/***************************************************************************
 *     Copyright (c) 1999-2016, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed Sep 28 07:26:26 2016
 *                 MD5 Checksum         c5b3804d8ec023400e054b5ca8c7e873
 *
 * Compiled with:  RDB Utility          3.0
 *                 RDB Parser           3.0
 *                 rdb2macro.pm         4.0
 *                 Perl Interpreter     5.010001
 *                 Operating System     linux
 *
 * Spec Versions:  ACD                  1
 *                 AFE                  1
 *                 BR_EOC               1
 *                 BR_MII               1
 *                 CFG                  1.0
 *                 CL45DEV1             1
 *                 CL45DEV3             1
 *                 CL45DEV7             1
 *                 CL45VEN              1
 *                 CORE                 1
 *                 CRG                  1.0
 *                 DMA1                 1.0
 *                 DMU                  1.0
 *                 DSP                  1
 *                 ETH                  1.0
 *                 GIO0                 1.0
 *                 I2C                  1.0
 *                 IND_ACC              1
 *                 IO                   1
 *                 MEM                  1.0
 *                 MISC                 1
 *                 MMI                  1.0
 *                 PKA                  1.0
 *                 PLL                  1
 *                 PWM                  1.0
 *                 QSPI                 1.0
 *                 RNG                  1.0
 *                 RemotePhy            1
 *                 SBM                  1.0
 *                 SPI0                 1.0
 *                 SPI1                 1.0
 *                 TB_TOP_1588          1
 *                 TIM0                 1.0
 *                 TOP_MISC             1
 *                 URT0                 1.0
 *                 VIC0                 1.0
 *                 WDT                  1.0
 *                 WOL                  1
 *                 aer                  1
 *                 comboDigital         1
 *                 dummy                1
 *                 fx100                1
 *                 ieee_cl22            1
 *                 over1G               1
 *                 pll2                 1
 *                 pll_afe              1
 *                 rx2                  1
 *                 rx3                  1
 *                 rx_afe               1
 *                 switch               1.0
 *                 tx_afe               1
 *                 xgxsBlk0             1
 *                 xgxsBlk1             1
 *                 xgxsBlk2             1
 *                 xgxsBlk4             1
 *                 xgxsBlk7             1
 *
 * RDB Files:  /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/bcm89530/bcm89530.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/arm_atcm.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/arm_b0tcm.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/arm_b1tcm.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/boot_rom.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/sys_cfg.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/vic0.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/sbm.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/dma1.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/eth.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/qspi.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/mem.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/tim0.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/spi1.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/wdt.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/dmu.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/i2c.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/cfg.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/urt0.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/spi0.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/pwm.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/gio0.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/mmi.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/pka.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/rng.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/scratch_0_1.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/cpusys/qspi_flash.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/bcm89530/top_bridge.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/brphys.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/brphy0.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/cl45dev1.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/cl45dev3.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/cl45dev7.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/cl45ven.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/core.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/dsp_taps.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/pll.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/acd.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/br_eoc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/top_misc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/wol.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/top_1588.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/br_mii.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/brphy1.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/ind_acc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/brphy2.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/brphy3.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/brphy4.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/sgmii_x3.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/SGMII_LANE0.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/ieee_cl22Regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock0_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock1_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/pll_afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/tx_afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/rx_afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock2_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock4_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/gpStatus_types.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/pll2.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock7_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/comboDigital_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/IDregs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/over1G_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/RemotePhy_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/fx100_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/rx2.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/rx3.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/aerBlock.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/SGMII_LANE1.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/ieee_cl22Regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock0_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock1_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/pll_afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/tx_afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/rx_afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock2_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock4_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/gpStatus_types.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/pll2.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock7_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/comboDigital_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/IDregs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/over1G_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/RemotePhy_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/fx100_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/rx2.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/rx3.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/aerBlock.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/SGMII_LANE2.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/ieee_cl22Regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock0_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock1_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/pll_afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/tx_afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/rx_afe.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock2_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock4_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/gpStatus_types.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/pll2.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/xgxsBlock7_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/comboDigital_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/IDregs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/over1G_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/RemotePhy_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/fx100_regs.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/rx2.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/rx3.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/aerBlock.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/sgmii/common_inc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/bcm89530/misc.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/bcm89530/crg.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/bcm89530/io.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/brphys/top_1588.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/swsys/swsys.rdb
 *             /projects/leo_ip/database_tag/LEO_B0_160219_R001/rdb/swsys/switch.rdb
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCM89530_H__
#define BCM89530_H__

/**
 * m = memory, c = core, r = register, f = field, d = data.
 */
#if !defined(GET_FIELD) && !defined(SET_FIELD)
#define BRCM_ALIGN(c,r,f)   c##_##r##_##f##_ALIGN
#define BRCM_BITS(c,r,f)    c##_##r##_##f##_BITS
#define BRCM_MASK(c,r,f)    c##_##r##_##f##_MASK
#define BRCM_SHIFT(c,r,f)   c##_##r##_##f##_SHIFT

#define GET_FIELD(m,c,r,f) \
	((((m) & BRCM_MASK(c,r,f)) >> BRCM_SHIFT(c,r,f)) << BRCM_ALIGN(c,r,f))

#define SET_FIELD(m,c,r,f,d) \
	((m) = (((m) & ~BRCM_MASK(c,r,f)) | ((((d) >> BRCM_ALIGN(c,r,f)) << \
	 BRCM_SHIFT(c,r,f)) & BRCM_MASK(c,r,f))) \
	)

#define SET_TYPE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##d)
#define SET_NAME_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,c##_##r##_##f##_##d)
#define SET_VALUE_FIELD(m,c,r,f,d) SET_FIELD(m,c,r,f,d)

#endif /* GET & SET */

/****************************************************************************
 * Core Enums.
 ***************************************************************************/
/****************************************************************************
 * Enums: aer_operationModes
 ***************************************************************************/
#define aer_operationModes_XGXS                            0
#define aer_operationModes_XGXG_nCC                        1
#define aer_operationModes_Indlane_OS8                     4
#define aer_operationModes_IndLane_OS5                     5
#define aer_operationModes_IndLane_OS4                     6
#define aer_operationModes_PCI                             7
#define aer_operationModes_XGXS_nLQ                        8
#define aer_operationModes_XGXS_nLQnCC                     9
#define aer_operationModes_PBypass                         10
#define aer_operationModes_PBypass_nDSK                    11
#define aer_operationModes_ComboCoreMode                   12
#define aer_operationModes_Clocks_off                      15

/****************************************************************************
 * Enums: aer_actualSpeeds4
 ***************************************************************************/
#define aer_actualSpeeds4_dr_10M                           0
#define aer_actualSpeeds4_dr_100M                          1
#define aer_actualSpeeds4_dr_1G                            2
#define aer_actualSpeeds4_dr_2p5G                          3
#define aer_actualSpeeds4_dr_5G_X4                         4
#define aer_actualSpeeds4_dr_6G_X4                         5
#define aer_actualSpeeds4_dr_10G_HiG                       6
#define aer_actualSpeeds4_dr_10G_CX4                       7
#define aer_actualSpeeds4_dr_12G_HiG                       8
#define aer_actualSpeeds4_dr_12p5G_X4                      9
#define aer_actualSpeeds4_dr_13G_X4                        10
#define aer_actualSpeeds4_dr_15G_X4                        11
#define aer_actualSpeeds4_dr_16G_X4                        12

/****************************************************************************
 * Enums: aer_actualSpeeds5
 ***************************************************************************/
#define aer_actualSpeeds5_dr_10M                           0
#define aer_actualSpeeds5_dr_100M                          1
#define aer_actualSpeeds5_dr_1G                            2
#define aer_actualSpeeds5_dr_2p5G                          3
#define aer_actualSpeeds5_dr_5G_X4                         4
#define aer_actualSpeeds5_dr_6G_X4                         5
#define aer_actualSpeeds5_dr_10G_HiG                       6
#define aer_actualSpeeds5_dr_10G_CX4                       7
#define aer_actualSpeeds5_dr_12G_HiG                       8
#define aer_actualSpeeds5_dr_12p5G_X4                      9
#define aer_actualSpeeds5_dr_13G_X4                        10
#define aer_actualSpeeds5_dr_15G_X4                        11
#define aer_actualSpeeds5_dr_16G_X4                        12
#define aer_actualSpeeds5_dr_1G_KX                         13
#define aer_actualSpeeds5_dr_10G_KX4                       14
#define aer_actualSpeeds5_dr_10G_KR                        15
#define aer_actualSpeeds5_dr_5G                            16
#define aer_actualSpeeds5_dr_6p4G                          17
#define aer_actualSpeeds5_dr_20G_X4                        18
#define aer_actualSpeeds5_dr_21G_X4                        19
#define aer_actualSpeeds5_dr_25G_X4                        20
#define aer_actualSpeeds5_dr_10G_HiG_DXGXS                 21
#define aer_actualSpeeds5_dr_10G_DXGXS                     22
#define aer_actualSpeeds5_dr_10p5G_HiG_DXGXS               23
#define aer_actualSpeeds5_dr_10p5G_DXGXS                   24
#define aer_actualSpeeds5_dr_12p773G_HiG_DXGXS             25
#define aer_actualSpeeds5_dr_12p773G_DXGXS                 26
#define aer_actualSpeeds5_dr_10G_XFI                       27
#define aer_actualSpeeds5_dr_40G                           28
#define aer_actualSpeeds5_dr_20G_HiG_DXGXS                 29
#define aer_actualSpeeds5_dr_20G_DXGXS                     30
#define aer_actualSpeeds5_dr_10G_SFI                       31
#define aer_actualSpeeds5_dr_31p5G                         32
#define aer_actualSpeeds5_dr_32p7G                         33
#define aer_actualSpeeds5_dr_20G_SCR                       34
#define aer_actualSpeeds5_dr_10G_HiG_DXGXS_SCR             35
#define aer_actualSpeeds5_dr_10G_DXGXS_SCR                 36
#define aer_actualSpeeds5_dr_12G_R2                        37
#define aer_actualSpeeds5_dr_10G_X2                        38
#define aer_actualSpeeds5_dr_40G_KR4                       39
#define aer_actualSpeeds5_dr_40G_CR4                       40
#define aer_actualSpeeds5_dr_100G_CR10                     41
#define aer_actualSpeeds5_dr_15p75G_DXGXS                  44
#define aer_actualSpeeds5_dr_20G_KR2                       57
#define aer_actualSpeeds5_dr_20G_CR2                       58

/****************************************************************************
 * Enums: aer_actualSpeedsMisc1
 ***************************************************************************/
#define aer_actualSpeedsMisc1_dr_2500BRCM_X1               16
#define aer_actualSpeedsMisc1_dr_5000BRCM_X4               17
#define aer_actualSpeedsMisc1_dr_6000BRCM_X4               18
#define aer_actualSpeedsMisc1_dr_10GHiGig_X4               19
#define aer_actualSpeedsMisc1_dr_10GBASE_CX4               20
#define aer_actualSpeedsMisc1_dr_12GHiGig_X4               21
#define aer_actualSpeedsMisc1_dr_12p5GHiGig_X4             22
#define aer_actualSpeedsMisc1_dr_13GHiGig_X4               23
#define aer_actualSpeedsMisc1_dr_15GHiGig_X4               24
#define aer_actualSpeedsMisc1_dr_16GHiGig_X4               25
#define aer_actualSpeedsMisc1_dr_5000BRCM_X1               26
#define aer_actualSpeedsMisc1_dr_6363BRCM_X1               27
#define aer_actualSpeedsMisc1_dr_20GHiGig_X4               28
#define aer_actualSpeedsMisc1_dr_21GHiGig_X4               29
#define aer_actualSpeedsMisc1_dr_25p45GHiGig_X4            30
#define aer_actualSpeedsMisc1_dr_10G_HiG_DXGXS             31

/****************************************************************************
 * Enums: aer_IndLaneModes
 ***************************************************************************/
#define aer_IndLaneModes_SWSDR_div2                        0
#define aer_IndLaneModes_SWSDR_div1                        1
#define aer_IndLaneModes_DWSDR_div2                        2
#define aer_IndLaneModes_DWSDR_div1                        3

/****************************************************************************
 * Enums: aer_prbsSelect
 ***************************************************************************/
#define aer_prbsSelect_prbs7                               0
#define aer_prbsSelect_prbs15                              1
#define aer_prbsSelect_prbs23                              2
#define aer_prbsSelect_prbs31                              3

/****************************************************************************
 * Enums: aer_vcoDivider
 ***************************************************************************/
#define aer_vcoDivider_div32                               0
#define aer_vcoDivider_div36                               1
#define aer_vcoDivider_div40                               2
#define aer_vcoDivider_div42                               3
#define aer_vcoDivider_div48                               4
#define aer_vcoDivider_div50                               5
#define aer_vcoDivider_div52                               6
#define aer_vcoDivider_div54                               7
#define aer_vcoDivider_div60                               8
#define aer_vcoDivider_div64                               9
#define aer_vcoDivider_div66                               10
#define aer_vcoDivider_div68                               11
#define aer_vcoDivider_div70                               12
#define aer_vcoDivider_div80                               13
#define aer_vcoDivider_div92                               14
#define aer_vcoDivider_div100                              15

/****************************************************************************
 * Enums: aer_refClkSelect
 ***************************************************************************/
#define aer_refClkSelect_clk_25MHz                         0
#define aer_refClkSelect_clk_100MHz                        1
#define aer_refClkSelect_clk_125MHz                        2
#define aer_refClkSelect_clk_156p25MHz                     3
#define aer_refClkSelect_clk_187p5MHz                      4
#define aer_refClkSelect_clk_161p25Mhz                     5
#define aer_refClkSelect_clk_50Mhz                         6
#define aer_refClkSelect_clk_106p25Mhz                     7

/****************************************************************************
 * Enums: aer_aerMMDdevTypeSelect
 ***************************************************************************/
#define aer_aerMMDdevTypeSelect_combo_core                 0
#define aer_aerMMDdevTypeSelect_PMA_PMD                    1
#define aer_aerMMDdevTypeSelect_PCS                        3
#define aer_aerMMDdevTypeSelect_PHY                        4
#define aer_aerMMDdevTypeSelect_DTE                        5
#define aer_aerMMDdevTypeSelect_CL73_AN                    7

/****************************************************************************
 * Enums: aer_aerMMDportSelect
 ***************************************************************************/
#define aer_aerMMDportSelect_ln0                           0
#define aer_aerMMDportSelect_ln1                           1
#define aer_aerMMDportSelect_ln2                           2
#define aer_aerMMDportSelect_ln3                           3
#define aer_aerMMDportSelect_BCST                          511

/****************************************************************************
 * Enums: aer_firmwareModeSelect
 ***************************************************************************/
#define aer_firmwareModeSelect_DEFAULT                     0
#define aer_firmwareModeSelect_SFP_OPT_LR                  1
#define aer_firmwareModeSelect_SFP_DAC                     2
#define aer_firmwareModeSelect_XLAUI                       3
#define aer_firmwareModeSelect_LONG_CH_6G                  4

/****************************************************************************
 * Enums: aer_tempIdxSelect
 ***************************************************************************/
#define aer_tempIdxSelect_LTE__22p9C                       15
#define aer_tempIdxSelect_LTE__12p6C                       14
#define aer_tempIdxSelect_LTE__3p0C                        13
#define aer_tempIdxSelect_LTE_6p7C                         12
#define aer_tempIdxSelect_LTE_16p4C                        11
#define aer_tempIdxSelect_LTE_26p6C                        10
#define aer_tempIdxSelect_LTE_36p3C                        9
#define aer_tempIdxSelect_LTE_46p0C                        8
#define aer_tempIdxSelect_LTE_56p2C                        7
#define aer_tempIdxSelect_LTE_65p9C                        6
#define aer_tempIdxSelect_LTE_75p6C                        5
#define aer_tempIdxSelect_LTE_85p3C                        4
#define aer_tempIdxSelect_LTE_95p5C                        3
#define aer_tempIdxSelect_LTE_105p2C                       2
#define aer_tempIdxSelect_LTE_114p9C                       1
#define aer_tempIdxSelect_LTE_125p1C                       0

/****************************************************************************
 * Enums: comboDigital_operationModes
 ***************************************************************************/
#define comboDigital_operationModes_XGXS                   0
#define comboDigital_operationModes_XGXG_nCC               1
#define comboDigital_operationModes_Indlane_OS8            4
#define comboDigital_operationModes_IndLane_OS5            5
#define comboDigital_operationModes_IndLane_OS4            6
#define comboDigital_operationModes_PCI                    7
#define comboDigital_operationModes_XGXS_nLQ               8
#define comboDigital_operationModes_XGXS_nLQnCC            9
#define comboDigital_operationModes_PBypass                10
#define comboDigital_operationModes_PBypass_nDSK           11
#define comboDigital_operationModes_ComboCoreMode          12
#define comboDigital_operationModes_Clocks_off             15

/****************************************************************************
 * Enums: comboDigital_actualSpeeds4
 ***************************************************************************/
#define comboDigital_actualSpeeds4_dr_10M                  0
#define comboDigital_actualSpeeds4_dr_100M                 1
#define comboDigital_actualSpeeds4_dr_1G                   2
#define comboDigital_actualSpeeds4_dr_2p5G                 3
#define comboDigital_actualSpeeds4_dr_5G_X4                4
#define comboDigital_actualSpeeds4_dr_6G_X4                5
#define comboDigital_actualSpeeds4_dr_10G_HiG              6
#define comboDigital_actualSpeeds4_dr_10G_CX4              7
#define comboDigital_actualSpeeds4_dr_12G_HiG              8
#define comboDigital_actualSpeeds4_dr_12p5G_X4             9
#define comboDigital_actualSpeeds4_dr_13G_X4               10
#define comboDigital_actualSpeeds4_dr_15G_X4               11
#define comboDigital_actualSpeeds4_dr_16G_X4               12

/****************************************************************************
 * Enums: comboDigital_actualSpeeds5
 ***************************************************************************/
#define comboDigital_actualSpeeds5_dr_10M                  0
#define comboDigital_actualSpeeds5_dr_100M                 1
#define comboDigital_actualSpeeds5_dr_1G                   2
#define comboDigital_actualSpeeds5_dr_2p5G                 3
#define comboDigital_actualSpeeds5_dr_5G_X4                4
#define comboDigital_actualSpeeds5_dr_6G_X4                5
#define comboDigital_actualSpeeds5_dr_10G_HiG              6
#define comboDigital_actualSpeeds5_dr_10G_CX4              7
#define comboDigital_actualSpeeds5_dr_12G_HiG              8
#define comboDigital_actualSpeeds5_dr_12p5G_X4             9
#define comboDigital_actualSpeeds5_dr_13G_X4               10
#define comboDigital_actualSpeeds5_dr_15G_X4               11
#define comboDigital_actualSpeeds5_dr_16G_X4               12
#define comboDigital_actualSpeeds5_dr_1G_KX                13
#define comboDigital_actualSpeeds5_dr_10G_KX4              14
#define comboDigital_actualSpeeds5_dr_10G_KR               15
#define comboDigital_actualSpeeds5_dr_5G                   16
#define comboDigital_actualSpeeds5_dr_6p4G                 17
#define comboDigital_actualSpeeds5_dr_20G_X4               18
#define comboDigital_actualSpeeds5_dr_21G_X4               19
#define comboDigital_actualSpeeds5_dr_25G_X4               20
#define comboDigital_actualSpeeds5_dr_10G_HiG_DXGXS        21
#define comboDigital_actualSpeeds5_dr_10G_DXGXS            22
#define comboDigital_actualSpeeds5_dr_10p5G_HiG_DXGXS      23
#define comboDigital_actualSpeeds5_dr_10p5G_DXGXS          24
#define comboDigital_actualSpeeds5_dr_12p773G_HiG_DXGXS    25
#define comboDigital_actualSpeeds5_dr_12p773G_DXGXS        26
#define comboDigital_actualSpeeds5_dr_10G_XFI              27
#define comboDigital_actualSpeeds5_dr_40G                  28
#define comboDigital_actualSpeeds5_dr_20G_HiG_DXGXS        29
#define comboDigital_actualSpeeds5_dr_20G_DXGXS            30
#define comboDigital_actualSpeeds5_dr_10G_SFI              31
#define comboDigital_actualSpeeds5_dr_31p5G                32
#define comboDigital_actualSpeeds5_dr_32p7G                33
#define comboDigital_actualSpeeds5_dr_20G_SCR              34
#define comboDigital_actualSpeeds5_dr_10G_HiG_DXGXS_SCR    35
#define comboDigital_actualSpeeds5_dr_10G_DXGXS_SCR        36
#define comboDigital_actualSpeeds5_dr_12G_R2               37
#define comboDigital_actualSpeeds5_dr_10G_X2               38
#define comboDigital_actualSpeeds5_dr_40G_KR4              39
#define comboDigital_actualSpeeds5_dr_40G_CR4              40
#define comboDigital_actualSpeeds5_dr_100G_CR10            41
#define comboDigital_actualSpeeds5_dr_15p75G_DXGXS         44
#define comboDigital_actualSpeeds5_dr_20G_KR2              57
#define comboDigital_actualSpeeds5_dr_20G_CR2              58

/****************************************************************************
 * Enums: comboDigital_actualSpeedsMisc1
 ***************************************************************************/
#define comboDigital_actualSpeedsMisc1_dr_2500BRCM_X1      16
#define comboDigital_actualSpeedsMisc1_dr_5000BRCM_X4      17
#define comboDigital_actualSpeedsMisc1_dr_6000BRCM_X4      18
#define comboDigital_actualSpeedsMisc1_dr_10GHiGig_X4      19
#define comboDigital_actualSpeedsMisc1_dr_10GBASE_CX4      20
#define comboDigital_actualSpeedsMisc1_dr_12GHiGig_X4      21
#define comboDigital_actualSpeedsMisc1_dr_12p5GHiGig_X4    22
#define comboDigital_actualSpeedsMisc1_dr_13GHiGig_X4      23
#define comboDigital_actualSpeedsMisc1_dr_15GHiGig_X4      24
#define comboDigital_actualSpeedsMisc1_dr_16GHiGig_X4      25
#define comboDigital_actualSpeedsMisc1_dr_5000BRCM_X1      26
#define comboDigital_actualSpeedsMisc1_dr_6363BRCM_X1      27
#define comboDigital_actualSpeedsMisc1_dr_20GHiGig_X4      28
#define comboDigital_actualSpeedsMisc1_dr_21GHiGig_X4      29
#define comboDigital_actualSpeedsMisc1_dr_25p45GHiGig_X4   30
#define comboDigital_actualSpeedsMisc1_dr_10G_HiG_DXGXS    31

/****************************************************************************
 * Enums: comboDigital_IndLaneModes
 ***************************************************************************/
#define comboDigital_IndLaneModes_SWSDR_div2               0
#define comboDigital_IndLaneModes_SWSDR_div1               1
#define comboDigital_IndLaneModes_DWSDR_div2               2
#define comboDigital_IndLaneModes_DWSDR_div1               3

/****************************************************************************
 * Enums: comboDigital_prbsSelect
 ***************************************************************************/
#define comboDigital_prbsSelect_prbs7                      0
#define comboDigital_prbsSelect_prbs15                     1
#define comboDigital_prbsSelect_prbs23                     2
#define comboDigital_prbsSelect_prbs31                     3

/****************************************************************************
 * Enums: comboDigital_vcoDivider
 ***************************************************************************/
#define comboDigital_vcoDivider_div32                      0
#define comboDigital_vcoDivider_div36                      1
#define comboDigital_vcoDivider_div40                      2
#define comboDigital_vcoDivider_div42                      3
#define comboDigital_vcoDivider_div48                      4
#define comboDigital_vcoDivider_div50                      5
#define comboDigital_vcoDivider_div52                      6
#define comboDigital_vcoDivider_div54                      7
#define comboDigital_vcoDivider_div60                      8
#define comboDigital_vcoDivider_div64                      9
#define comboDigital_vcoDivider_div66                      10
#define comboDigital_vcoDivider_div68                      11
#define comboDigital_vcoDivider_div70                      12
#define comboDigital_vcoDivider_div80                      13
#define comboDigital_vcoDivider_div92                      14
#define comboDigital_vcoDivider_div100                     15

/****************************************************************************
 * Enums: comboDigital_refClkSelect
 ***************************************************************************/
#define comboDigital_refClkSelect_clk_25MHz                0
#define comboDigital_refClkSelect_clk_100MHz               1
#define comboDigital_refClkSelect_clk_125MHz               2
#define comboDigital_refClkSelect_clk_156p25MHz            3
#define comboDigital_refClkSelect_clk_187p5MHz             4
#define comboDigital_refClkSelect_clk_161p25Mhz            5
#define comboDigital_refClkSelect_clk_50Mhz                6
#define comboDigital_refClkSelect_clk_106p25Mhz            7

/****************************************************************************
 * Enums: comboDigital_aerMMDdevTypeSelect
 ***************************************************************************/
#define comboDigital_aerMMDdevTypeSelect_combo_core        0
#define comboDigital_aerMMDdevTypeSelect_PMA_PMD           1
#define comboDigital_aerMMDdevTypeSelect_PCS               3
#define comboDigital_aerMMDdevTypeSelect_PHY               4
#define comboDigital_aerMMDdevTypeSelect_DTE               5
#define comboDigital_aerMMDdevTypeSelect_CL73_AN           7

/****************************************************************************
 * Enums: comboDigital_aerMMDportSelect
 ***************************************************************************/
#define comboDigital_aerMMDportSelect_ln0                  0
#define comboDigital_aerMMDportSelect_ln1                  1
#define comboDigital_aerMMDportSelect_ln2                  2
#define comboDigital_aerMMDportSelect_ln3                  3
#define comboDigital_aerMMDportSelect_BCST                 511

/****************************************************************************
 * Enums: comboDigital_firmwareModeSelect
 ***************************************************************************/
#define comboDigital_firmwareModeSelect_DEFAULT            0
#define comboDigital_firmwareModeSelect_SFP_OPT_LR         1
#define comboDigital_firmwareModeSelect_SFP_DAC            2
#define comboDigital_firmwareModeSelect_XLAUI              3
#define comboDigital_firmwareModeSelect_LONG_CH_6G         4

/****************************************************************************
 * Enums: comboDigital_tempIdxSelect
 ***************************************************************************/
#define comboDigital_tempIdxSelect_LTE__22p9C              15
#define comboDigital_tempIdxSelect_LTE__12p6C              14
#define comboDigital_tempIdxSelect_LTE__3p0C               13
#define comboDigital_tempIdxSelect_LTE_6p7C                12
#define comboDigital_tempIdxSelect_LTE_16p4C               11
#define comboDigital_tempIdxSelect_LTE_26p6C               10
#define comboDigital_tempIdxSelect_LTE_36p3C               9
#define comboDigital_tempIdxSelect_LTE_46p0C               8
#define comboDigital_tempIdxSelect_LTE_56p2C               7
#define comboDigital_tempIdxSelect_LTE_65p9C               6
#define comboDigital_tempIdxSelect_LTE_75p6C               5
#define comboDigital_tempIdxSelect_LTE_85p3C               4
#define comboDigital_tempIdxSelect_LTE_95p5C               3
#define comboDigital_tempIdxSelect_LTE_105p2C              2
#define comboDigital_tempIdxSelect_LTE_114p9C              1
#define comboDigital_tempIdxSelect_LTE_125p1C              0

/****************************************************************************
 * Enums: xgxsBlk0_operationModes
 ***************************************************************************/
#define xgxsBlk0_operationModes_XGXS                       0
#define xgxsBlk0_operationModes_XGXG_nCC                   1
#define xgxsBlk0_operationModes_Indlane_OS8                4
#define xgxsBlk0_operationModes_IndLane_OS5                5
#define xgxsBlk0_operationModes_IndLane_OS4                6
#define xgxsBlk0_operationModes_PCI                        7
#define xgxsBlk0_operationModes_XGXS_nLQ                   8
#define xgxsBlk0_operationModes_XGXS_nLQnCC                9
#define xgxsBlk0_operationModes_PBypass                    10
#define xgxsBlk0_operationModes_PBypass_nDSK               11
#define xgxsBlk0_operationModes_ComboCoreMode              12
#define xgxsBlk0_operationModes_Clocks_off                 15

/****************************************************************************
 * Enums: xgxsBlk0_actualSpeeds4
 ***************************************************************************/
#define xgxsBlk0_actualSpeeds4_dr_10M                      0
#define xgxsBlk0_actualSpeeds4_dr_100M                     1
#define xgxsBlk0_actualSpeeds4_dr_1G                       2
#define xgxsBlk0_actualSpeeds4_dr_2p5G                     3
#define xgxsBlk0_actualSpeeds4_dr_5G_X4                    4
#define xgxsBlk0_actualSpeeds4_dr_6G_X4                    5
#define xgxsBlk0_actualSpeeds4_dr_10G_HiG                  6
#define xgxsBlk0_actualSpeeds4_dr_10G_CX4                  7
#define xgxsBlk0_actualSpeeds4_dr_12G_HiG                  8
#define xgxsBlk0_actualSpeeds4_dr_12p5G_X4                 9
#define xgxsBlk0_actualSpeeds4_dr_13G_X4                   10
#define xgxsBlk0_actualSpeeds4_dr_15G_X4                   11
#define xgxsBlk0_actualSpeeds4_dr_16G_X4                   12

/****************************************************************************
 * Enums: xgxsBlk0_actualSpeeds5
 ***************************************************************************/
#define xgxsBlk0_actualSpeeds5_dr_10M                      0
#define xgxsBlk0_actualSpeeds5_dr_100M                     1
#define xgxsBlk0_actualSpeeds5_dr_1G                       2
#define xgxsBlk0_actualSpeeds5_dr_2p5G                     3
#define xgxsBlk0_actualSpeeds5_dr_5G_X4                    4
#define xgxsBlk0_actualSpeeds5_dr_6G_X4                    5
#define xgxsBlk0_actualSpeeds5_dr_10G_HiG                  6
#define xgxsBlk0_actualSpeeds5_dr_10G_CX4                  7
#define xgxsBlk0_actualSpeeds5_dr_12G_HiG                  8
#define xgxsBlk0_actualSpeeds5_dr_12p5G_X4                 9
#define xgxsBlk0_actualSpeeds5_dr_13G_X4                   10
#define xgxsBlk0_actualSpeeds5_dr_15G_X4                   11
#define xgxsBlk0_actualSpeeds5_dr_16G_X4                   12
#define xgxsBlk0_actualSpeeds5_dr_1G_KX                    13
#define xgxsBlk0_actualSpeeds5_dr_10G_KX4                  14
#define xgxsBlk0_actualSpeeds5_dr_10G_KR                   15
#define xgxsBlk0_actualSpeeds5_dr_5G                       16
#define xgxsBlk0_actualSpeeds5_dr_6p4G                     17
#define xgxsBlk0_actualSpeeds5_dr_20G_X4                   18
#define xgxsBlk0_actualSpeeds5_dr_21G_X4                   19
#define xgxsBlk0_actualSpeeds5_dr_25G_X4                   20
#define xgxsBlk0_actualSpeeds5_dr_10G_HiG_DXGXS            21
#define xgxsBlk0_actualSpeeds5_dr_10G_DXGXS                22
#define xgxsBlk0_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
#define xgxsBlk0_actualSpeeds5_dr_10p5G_DXGXS              24
#define xgxsBlk0_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
#define xgxsBlk0_actualSpeeds5_dr_12p773G_DXGXS            26
#define xgxsBlk0_actualSpeeds5_dr_10G_XFI                  27
#define xgxsBlk0_actualSpeeds5_dr_40G                      28
#define xgxsBlk0_actualSpeeds5_dr_20G_HiG_DXGXS            29
#define xgxsBlk0_actualSpeeds5_dr_20G_DXGXS                30
#define xgxsBlk0_actualSpeeds5_dr_10G_SFI                  31
#define xgxsBlk0_actualSpeeds5_dr_31p5G                    32
#define xgxsBlk0_actualSpeeds5_dr_32p7G                    33
#define xgxsBlk0_actualSpeeds5_dr_20G_SCR                  34
#define xgxsBlk0_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
#define xgxsBlk0_actualSpeeds5_dr_10G_DXGXS_SCR            36
#define xgxsBlk0_actualSpeeds5_dr_12G_R2                   37
#define xgxsBlk0_actualSpeeds5_dr_10G_X2                   38
#define xgxsBlk0_actualSpeeds5_dr_40G_KR4                  39
#define xgxsBlk0_actualSpeeds5_dr_40G_CR4                  40
#define xgxsBlk0_actualSpeeds5_dr_100G_CR10                41
#define xgxsBlk0_actualSpeeds5_dr_15p75G_DXGXS             44
#define xgxsBlk0_actualSpeeds5_dr_20G_KR2                  57
#define xgxsBlk0_actualSpeeds5_dr_20G_CR2                  58

/****************************************************************************
 * Enums: xgxsBlk0_actualSpeedsMisc1
 ***************************************************************************/
#define xgxsBlk0_actualSpeedsMisc1_dr_2500BRCM_X1          16
#define xgxsBlk0_actualSpeedsMisc1_dr_5000BRCM_X4          17
#define xgxsBlk0_actualSpeedsMisc1_dr_6000BRCM_X4          18
#define xgxsBlk0_actualSpeedsMisc1_dr_10GHiGig_X4          19
#define xgxsBlk0_actualSpeedsMisc1_dr_10GBASE_CX4          20
#define xgxsBlk0_actualSpeedsMisc1_dr_12GHiGig_X4          21
#define xgxsBlk0_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
#define xgxsBlk0_actualSpeedsMisc1_dr_13GHiGig_X4          23
#define xgxsBlk0_actualSpeedsMisc1_dr_15GHiGig_X4          24
#define xgxsBlk0_actualSpeedsMisc1_dr_16GHiGig_X4          25
#define xgxsBlk0_actualSpeedsMisc1_dr_5000BRCM_X1          26
#define xgxsBlk0_actualSpeedsMisc1_dr_6363BRCM_X1          27
#define xgxsBlk0_actualSpeedsMisc1_dr_20GHiGig_X4          28
#define xgxsBlk0_actualSpeedsMisc1_dr_21GHiGig_X4          29
#define xgxsBlk0_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
#define xgxsBlk0_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31

/****************************************************************************
 * Enums: xgxsBlk0_IndLaneModes
 ***************************************************************************/
#define xgxsBlk0_IndLaneModes_SWSDR_div2                   0
#define xgxsBlk0_IndLaneModes_SWSDR_div1                   1
#define xgxsBlk0_IndLaneModes_DWSDR_div2                   2
#define xgxsBlk0_IndLaneModes_DWSDR_div1                   3

/****************************************************************************
 * Enums: xgxsBlk0_prbsSelect
 ***************************************************************************/
#define xgxsBlk0_prbsSelect_prbs7                          0
#define xgxsBlk0_prbsSelect_prbs15                         1
#define xgxsBlk0_prbsSelect_prbs23                         2
#define xgxsBlk0_prbsSelect_prbs31                         3

/****************************************************************************
 * Enums: xgxsBlk0_vcoDivider
 ***************************************************************************/
#define xgxsBlk0_vcoDivider_div32                          0
#define xgxsBlk0_vcoDivider_div36                          1
#define xgxsBlk0_vcoDivider_div40                          2
#define xgxsBlk0_vcoDivider_div42                          3
#define xgxsBlk0_vcoDivider_div48                          4
#define xgxsBlk0_vcoDivider_div50                          5
#define xgxsBlk0_vcoDivider_div52                          6
#define xgxsBlk0_vcoDivider_div54                          7
#define xgxsBlk0_vcoDivider_div60                          8
#define xgxsBlk0_vcoDivider_div64                          9
#define xgxsBlk0_vcoDivider_div66                          10
#define xgxsBlk0_vcoDivider_div68                          11
#define xgxsBlk0_vcoDivider_div70                          12
#define xgxsBlk0_vcoDivider_div80                          13
#define xgxsBlk0_vcoDivider_div92                          14
#define xgxsBlk0_vcoDivider_div100                         15

/****************************************************************************
 * Enums: xgxsBlk0_refClkSelect
 ***************************************************************************/
#define xgxsBlk0_refClkSelect_clk_25MHz                    0
#define xgxsBlk0_refClkSelect_clk_100MHz                   1
#define xgxsBlk0_refClkSelect_clk_125MHz                   2
#define xgxsBlk0_refClkSelect_clk_156p25MHz                3
#define xgxsBlk0_refClkSelect_clk_187p5MHz                 4
#define xgxsBlk0_refClkSelect_clk_161p25Mhz                5
#define xgxsBlk0_refClkSelect_clk_50Mhz                    6
#define xgxsBlk0_refClkSelect_clk_106p25Mhz                7

/****************************************************************************
 * Enums: xgxsBlk0_aerMMDdevTypeSelect
 ***************************************************************************/
#define xgxsBlk0_aerMMDdevTypeSelect_combo_core            0
#define xgxsBlk0_aerMMDdevTypeSelect_PMA_PMD               1
#define xgxsBlk0_aerMMDdevTypeSelect_PCS                   3
#define xgxsBlk0_aerMMDdevTypeSelect_PHY                   4
#define xgxsBlk0_aerMMDdevTypeSelect_DTE                   5
#define xgxsBlk0_aerMMDdevTypeSelect_CL73_AN               7

/****************************************************************************
 * Enums: xgxsBlk0_aerMMDportSelect
 ***************************************************************************/
#define xgxsBlk0_aerMMDportSelect_ln0                      0
#define xgxsBlk0_aerMMDportSelect_ln1                      1
#define xgxsBlk0_aerMMDportSelect_ln2                      2
#define xgxsBlk0_aerMMDportSelect_ln3                      3
#define xgxsBlk0_aerMMDportSelect_BCST                     511

/****************************************************************************
 * Enums: xgxsBlk0_firmwareModeSelect
 ***************************************************************************/
#define xgxsBlk0_firmwareModeSelect_DEFAULT                0
#define xgxsBlk0_firmwareModeSelect_SFP_OPT_LR             1
#define xgxsBlk0_firmwareModeSelect_SFP_DAC                2
#define xgxsBlk0_firmwareModeSelect_XLAUI                  3
#define xgxsBlk0_firmwareModeSelect_LONG_CH_6G             4

/****************************************************************************
 * Enums: xgxsBlk0_tempIdxSelect
 ***************************************************************************/
#define xgxsBlk0_tempIdxSelect_LTE__22p9C                  15
#define xgxsBlk0_tempIdxSelect_LTE__12p6C                  14
#define xgxsBlk0_tempIdxSelect_LTE__3p0C                   13
#define xgxsBlk0_tempIdxSelect_LTE_6p7C                    12
#define xgxsBlk0_tempIdxSelect_LTE_16p4C                   11
#define xgxsBlk0_tempIdxSelect_LTE_26p6C                   10
#define xgxsBlk0_tempIdxSelect_LTE_36p3C                   9
#define xgxsBlk0_tempIdxSelect_LTE_46p0C                   8
#define xgxsBlk0_tempIdxSelect_LTE_56p2C                   7
#define xgxsBlk0_tempIdxSelect_LTE_65p9C                   6
#define xgxsBlk0_tempIdxSelect_LTE_75p6C                   5
#define xgxsBlk0_tempIdxSelect_LTE_85p3C                   4
#define xgxsBlk0_tempIdxSelect_LTE_95p5C                   3
#define xgxsBlk0_tempIdxSelect_LTE_105p2C                  2
#define xgxsBlk0_tempIdxSelect_LTE_114p9C                  1
#define xgxsBlk0_tempIdxSelect_LTE_125p1C                  0

/****************************************************************************
 * Enums: xgxsBlk1_operationModes
 ***************************************************************************/
#define xgxsBlk1_operationModes_XGXS                       0
#define xgxsBlk1_operationModes_XGXG_nCC                   1
#define xgxsBlk1_operationModes_Indlane_OS8                4
#define xgxsBlk1_operationModes_IndLane_OS5                5
#define xgxsBlk1_operationModes_IndLane_OS4                6
#define xgxsBlk1_operationModes_PCI                        7
#define xgxsBlk1_operationModes_XGXS_nLQ                   8
#define xgxsBlk1_operationModes_XGXS_nLQnCC                9
#define xgxsBlk1_operationModes_PBypass                    10
#define xgxsBlk1_operationModes_PBypass_nDSK               11
#define xgxsBlk1_operationModes_ComboCoreMode              12
#define xgxsBlk1_operationModes_Clocks_off                 15

/****************************************************************************
 * Enums: xgxsBlk1_actualSpeeds4
 ***************************************************************************/
#define xgxsBlk1_actualSpeeds4_dr_10M                      0
#define xgxsBlk1_actualSpeeds4_dr_100M                     1
#define xgxsBlk1_actualSpeeds4_dr_1G                       2
#define xgxsBlk1_actualSpeeds4_dr_2p5G                     3
#define xgxsBlk1_actualSpeeds4_dr_5G_X4                    4
#define xgxsBlk1_actualSpeeds4_dr_6G_X4                    5
#define xgxsBlk1_actualSpeeds4_dr_10G_HiG                  6
#define xgxsBlk1_actualSpeeds4_dr_10G_CX4                  7
#define xgxsBlk1_actualSpeeds4_dr_12G_HiG                  8
#define xgxsBlk1_actualSpeeds4_dr_12p5G_X4                 9
#define xgxsBlk1_actualSpeeds4_dr_13G_X4                   10
#define xgxsBlk1_actualSpeeds4_dr_15G_X4                   11
#define xgxsBlk1_actualSpeeds4_dr_16G_X4                   12

/****************************************************************************
 * Enums: xgxsBlk1_actualSpeeds5
 ***************************************************************************/
#define xgxsBlk1_actualSpeeds5_dr_10M                      0
#define xgxsBlk1_actualSpeeds5_dr_100M                     1
#define xgxsBlk1_actualSpeeds5_dr_1G                       2
#define xgxsBlk1_actualSpeeds5_dr_2p5G                     3
#define xgxsBlk1_actualSpeeds5_dr_5G_X4                    4
#define xgxsBlk1_actualSpeeds5_dr_6G_X4                    5
#define xgxsBlk1_actualSpeeds5_dr_10G_HiG                  6
#define xgxsBlk1_actualSpeeds5_dr_10G_CX4                  7
#define xgxsBlk1_actualSpeeds5_dr_12G_HiG                  8
#define xgxsBlk1_actualSpeeds5_dr_12p5G_X4                 9
#define xgxsBlk1_actualSpeeds5_dr_13G_X4                   10
#define xgxsBlk1_actualSpeeds5_dr_15G_X4                   11
#define xgxsBlk1_actualSpeeds5_dr_16G_X4                   12
#define xgxsBlk1_actualSpeeds5_dr_1G_KX                    13
#define xgxsBlk1_actualSpeeds5_dr_10G_KX4                  14
#define xgxsBlk1_actualSpeeds5_dr_10G_KR                   15
#define xgxsBlk1_actualSpeeds5_dr_5G                       16
#define xgxsBlk1_actualSpeeds5_dr_6p4G                     17
#define xgxsBlk1_actualSpeeds5_dr_20G_X4                   18
#define xgxsBlk1_actualSpeeds5_dr_21G_X4                   19
#define xgxsBlk1_actualSpeeds5_dr_25G_X4                   20
#define xgxsBlk1_actualSpeeds5_dr_10G_HiG_DXGXS            21
#define xgxsBlk1_actualSpeeds5_dr_10G_DXGXS                22
#define xgxsBlk1_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
#define xgxsBlk1_actualSpeeds5_dr_10p5G_DXGXS              24
#define xgxsBlk1_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
#define xgxsBlk1_actualSpeeds5_dr_12p773G_DXGXS            26
#define xgxsBlk1_actualSpeeds5_dr_10G_XFI                  27
#define xgxsBlk1_actualSpeeds5_dr_40G                      28
#define xgxsBlk1_actualSpeeds5_dr_20G_HiG_DXGXS            29
#define xgxsBlk1_actualSpeeds5_dr_20G_DXGXS                30
#define xgxsBlk1_actualSpeeds5_dr_10G_SFI                  31
#define xgxsBlk1_actualSpeeds5_dr_31p5G                    32
#define xgxsBlk1_actualSpeeds5_dr_32p7G                    33
#define xgxsBlk1_actualSpeeds5_dr_20G_SCR                  34
#define xgxsBlk1_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
#define xgxsBlk1_actualSpeeds5_dr_10G_DXGXS_SCR            36
#define xgxsBlk1_actualSpeeds5_dr_12G_R2                   37
#define xgxsBlk1_actualSpeeds5_dr_10G_X2                   38
#define xgxsBlk1_actualSpeeds5_dr_40G_KR4                  39
#define xgxsBlk1_actualSpeeds5_dr_40G_CR4                  40
#define xgxsBlk1_actualSpeeds5_dr_100G_CR10                41
#define xgxsBlk1_actualSpeeds5_dr_15p75G_DXGXS             44
#define xgxsBlk1_actualSpeeds5_dr_20G_KR2                  57
#define xgxsBlk1_actualSpeeds5_dr_20G_CR2                  58

/****************************************************************************
 * Enums: xgxsBlk1_actualSpeedsMisc1
 ***************************************************************************/
#define xgxsBlk1_actualSpeedsMisc1_dr_2500BRCM_X1          16
#define xgxsBlk1_actualSpeedsMisc1_dr_5000BRCM_X4          17
#define xgxsBlk1_actualSpeedsMisc1_dr_6000BRCM_X4          18
#define xgxsBlk1_actualSpeedsMisc1_dr_10GHiGig_X4          19
#define xgxsBlk1_actualSpeedsMisc1_dr_10GBASE_CX4          20
#define xgxsBlk1_actualSpeedsMisc1_dr_12GHiGig_X4          21
#define xgxsBlk1_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
#define xgxsBlk1_actualSpeedsMisc1_dr_13GHiGig_X4          23
#define xgxsBlk1_actualSpeedsMisc1_dr_15GHiGig_X4          24
#define xgxsBlk1_actualSpeedsMisc1_dr_16GHiGig_X4          25
#define xgxsBlk1_actualSpeedsMisc1_dr_5000BRCM_X1          26
#define xgxsBlk1_actualSpeedsMisc1_dr_6363BRCM_X1          27
#define xgxsBlk1_actualSpeedsMisc1_dr_20GHiGig_X4          28
#define xgxsBlk1_actualSpeedsMisc1_dr_21GHiGig_X4          29
#define xgxsBlk1_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
#define xgxsBlk1_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31

/****************************************************************************
 * Enums: xgxsBlk1_IndLaneModes
 ***************************************************************************/
#define xgxsBlk1_IndLaneModes_SWSDR_div2                   0
#define xgxsBlk1_IndLaneModes_SWSDR_div1                   1
#define xgxsBlk1_IndLaneModes_DWSDR_div2                   2
#define xgxsBlk1_IndLaneModes_DWSDR_div1                   3

/****************************************************************************
 * Enums: xgxsBlk1_prbsSelect
 ***************************************************************************/
#define xgxsBlk1_prbsSelect_prbs7                          0
#define xgxsBlk1_prbsSelect_prbs15                         1
#define xgxsBlk1_prbsSelect_prbs23                         2
#define xgxsBlk1_prbsSelect_prbs31                         3

/****************************************************************************
 * Enums: xgxsBlk1_vcoDivider
 ***************************************************************************/
#define xgxsBlk1_vcoDivider_div32                          0
#define xgxsBlk1_vcoDivider_div36                          1
#define xgxsBlk1_vcoDivider_div40                          2
#define xgxsBlk1_vcoDivider_div42                          3
#define xgxsBlk1_vcoDivider_div48                          4
#define xgxsBlk1_vcoDivider_div50                          5
#define xgxsBlk1_vcoDivider_div52                          6
#define xgxsBlk1_vcoDivider_div54                          7
#define xgxsBlk1_vcoDivider_div60                          8
#define xgxsBlk1_vcoDivider_div64                          9
#define xgxsBlk1_vcoDivider_div66                          10
#define xgxsBlk1_vcoDivider_div68                          11
#define xgxsBlk1_vcoDivider_div70                          12
#define xgxsBlk1_vcoDivider_div80                          13
#define xgxsBlk1_vcoDivider_div92                          14
#define xgxsBlk1_vcoDivider_div100                         15

/****************************************************************************
 * Enums: xgxsBlk1_refClkSelect
 ***************************************************************************/
#define xgxsBlk1_refClkSelect_clk_25MHz                    0
#define xgxsBlk1_refClkSelect_clk_100MHz                   1
#define xgxsBlk1_refClkSelect_clk_125MHz                   2
#define xgxsBlk1_refClkSelect_clk_156p25MHz                3
#define xgxsBlk1_refClkSelect_clk_187p5MHz                 4
#define xgxsBlk1_refClkSelect_clk_161p25Mhz                5
#define xgxsBlk1_refClkSelect_clk_50Mhz                    6
#define xgxsBlk1_refClkSelect_clk_106p25Mhz                7

/****************************************************************************
 * Enums: xgxsBlk1_aerMMDdevTypeSelect
 ***************************************************************************/
#define xgxsBlk1_aerMMDdevTypeSelect_combo_core            0
#define xgxsBlk1_aerMMDdevTypeSelect_PMA_PMD               1
#define xgxsBlk1_aerMMDdevTypeSelect_PCS                   3
#define xgxsBlk1_aerMMDdevTypeSelect_PHY                   4
#define xgxsBlk1_aerMMDdevTypeSelect_DTE                   5
#define xgxsBlk1_aerMMDdevTypeSelect_CL73_AN               7

/****************************************************************************
 * Enums: xgxsBlk1_aerMMDportSelect
 ***************************************************************************/
#define xgxsBlk1_aerMMDportSelect_ln0                      0
#define xgxsBlk1_aerMMDportSelect_ln1                      1
#define xgxsBlk1_aerMMDportSelect_ln2                      2
#define xgxsBlk1_aerMMDportSelect_ln3                      3
#define xgxsBlk1_aerMMDportSelect_BCST                     511

/****************************************************************************
 * Enums: xgxsBlk1_firmwareModeSelect
 ***************************************************************************/
#define xgxsBlk1_firmwareModeSelect_DEFAULT                0
#define xgxsBlk1_firmwareModeSelect_SFP_OPT_LR             1
#define xgxsBlk1_firmwareModeSelect_SFP_DAC                2
#define xgxsBlk1_firmwareModeSelect_XLAUI                  3
#define xgxsBlk1_firmwareModeSelect_LONG_CH_6G             4

/****************************************************************************
 * Enums: xgxsBlk1_tempIdxSelect
 ***************************************************************************/
#define xgxsBlk1_tempIdxSelect_LTE__22p9C                  15
#define xgxsBlk1_tempIdxSelect_LTE__12p6C                  14
#define xgxsBlk1_tempIdxSelect_LTE__3p0C                   13
#define xgxsBlk1_tempIdxSelect_LTE_6p7C                    12
#define xgxsBlk1_tempIdxSelect_LTE_16p4C                   11
#define xgxsBlk1_tempIdxSelect_LTE_26p6C                   10
#define xgxsBlk1_tempIdxSelect_LTE_36p3C                   9
#define xgxsBlk1_tempIdxSelect_LTE_46p0C                   8
#define xgxsBlk1_tempIdxSelect_LTE_56p2C                   7
#define xgxsBlk1_tempIdxSelect_LTE_65p9C                   6
#define xgxsBlk1_tempIdxSelect_LTE_75p6C                   5
#define xgxsBlk1_tempIdxSelect_LTE_85p3C                   4
#define xgxsBlk1_tempIdxSelect_LTE_95p5C                   3
#define xgxsBlk1_tempIdxSelect_LTE_105p2C                  2
#define xgxsBlk1_tempIdxSelect_LTE_114p9C                  1
#define xgxsBlk1_tempIdxSelect_LTE_125p1C                  0

/****************************************************************************
 * Enums: xgxsBlk2_operationModes
 ***************************************************************************/
#define xgxsBlk2_operationModes_XGXS                       0
#define xgxsBlk2_operationModes_XGXG_nCC                   1
#define xgxsBlk2_operationModes_Indlane_OS8                4
#define xgxsBlk2_operationModes_IndLane_OS5                5
#define xgxsBlk2_operationModes_IndLane_OS4                6
#define xgxsBlk2_operationModes_PCI                        7
#define xgxsBlk2_operationModes_XGXS_nLQ                   8
#define xgxsBlk2_operationModes_XGXS_nLQnCC                9
#define xgxsBlk2_operationModes_PBypass                    10
#define xgxsBlk2_operationModes_PBypass_nDSK               11
#define xgxsBlk2_operationModes_ComboCoreMode              12
#define xgxsBlk2_operationModes_Clocks_off                 15

/****************************************************************************
 * Enums: xgxsBlk2_actualSpeeds4
 ***************************************************************************/
#define xgxsBlk2_actualSpeeds4_dr_10M                      0
#define xgxsBlk2_actualSpeeds4_dr_100M                     1
#define xgxsBlk2_actualSpeeds4_dr_1G                       2
#define xgxsBlk2_actualSpeeds4_dr_2p5G                     3
#define xgxsBlk2_actualSpeeds4_dr_5G_X4                    4
#define xgxsBlk2_actualSpeeds4_dr_6G_X4                    5
#define xgxsBlk2_actualSpeeds4_dr_10G_HiG                  6
#define xgxsBlk2_actualSpeeds4_dr_10G_CX4                  7
#define xgxsBlk2_actualSpeeds4_dr_12G_HiG                  8
#define xgxsBlk2_actualSpeeds4_dr_12p5G_X4                 9
#define xgxsBlk2_actualSpeeds4_dr_13G_X4                   10
#define xgxsBlk2_actualSpeeds4_dr_15G_X4                   11
#define xgxsBlk2_actualSpeeds4_dr_16G_X4                   12

/****************************************************************************
 * Enums: xgxsBlk2_actualSpeeds5
 ***************************************************************************/
#define xgxsBlk2_actualSpeeds5_dr_10M                      0
#define xgxsBlk2_actualSpeeds5_dr_100M                     1
#define xgxsBlk2_actualSpeeds5_dr_1G                       2
#define xgxsBlk2_actualSpeeds5_dr_2p5G                     3
#define xgxsBlk2_actualSpeeds5_dr_5G_X4                    4
#define xgxsBlk2_actualSpeeds5_dr_6G_X4                    5
#define xgxsBlk2_actualSpeeds5_dr_10G_HiG                  6
#define xgxsBlk2_actualSpeeds5_dr_10G_CX4                  7
#define xgxsBlk2_actualSpeeds5_dr_12G_HiG                  8
#define xgxsBlk2_actualSpeeds5_dr_12p5G_X4                 9
#define xgxsBlk2_actualSpeeds5_dr_13G_X4                   10
#define xgxsBlk2_actualSpeeds5_dr_15G_X4                   11
#define xgxsBlk2_actualSpeeds5_dr_16G_X4                   12
#define xgxsBlk2_actualSpeeds5_dr_1G_KX                    13
#define xgxsBlk2_actualSpeeds5_dr_10G_KX4                  14
#define xgxsBlk2_actualSpeeds5_dr_10G_KR                   15
#define xgxsBlk2_actualSpeeds5_dr_5G                       16
#define xgxsBlk2_actualSpeeds5_dr_6p4G                     17
#define xgxsBlk2_actualSpeeds5_dr_20G_X4                   18
#define xgxsBlk2_actualSpeeds5_dr_21G_X4                   19
#define xgxsBlk2_actualSpeeds5_dr_25G_X4                   20
#define xgxsBlk2_actualSpeeds5_dr_10G_HiG_DXGXS            21
#define xgxsBlk2_actualSpeeds5_dr_10G_DXGXS                22
#define xgxsBlk2_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
#define xgxsBlk2_actualSpeeds5_dr_10p5G_DXGXS              24
#define xgxsBlk2_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
#define xgxsBlk2_actualSpeeds5_dr_12p773G_DXGXS            26
#define xgxsBlk2_actualSpeeds5_dr_10G_XFI                  27
#define xgxsBlk2_actualSpeeds5_dr_40G                      28
#define xgxsBlk2_actualSpeeds5_dr_20G_HiG_DXGXS            29
#define xgxsBlk2_actualSpeeds5_dr_20G_DXGXS                30
#define xgxsBlk2_actualSpeeds5_dr_10G_SFI                  31
#define xgxsBlk2_actualSpeeds5_dr_31p5G                    32
#define xgxsBlk2_actualSpeeds5_dr_32p7G                    33
#define xgxsBlk2_actualSpeeds5_dr_20G_SCR                  34
#define xgxsBlk2_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
#define xgxsBlk2_actualSpeeds5_dr_10G_DXGXS_SCR            36
#define xgxsBlk2_actualSpeeds5_dr_12G_R2                   37
#define xgxsBlk2_actualSpeeds5_dr_10G_X2                   38
#define xgxsBlk2_actualSpeeds5_dr_40G_KR4                  39
#define xgxsBlk2_actualSpeeds5_dr_40G_CR4                  40
#define xgxsBlk2_actualSpeeds5_dr_100G_CR10                41
#define xgxsBlk2_actualSpeeds5_dr_15p75G_DXGXS             44
#define xgxsBlk2_actualSpeeds5_dr_20G_KR2                  57
#define xgxsBlk2_actualSpeeds5_dr_20G_CR2                  58

/****************************************************************************
 * Enums: xgxsBlk2_actualSpeedsMisc1
 ***************************************************************************/
#define xgxsBlk2_actualSpeedsMisc1_dr_2500BRCM_X1          16
#define xgxsBlk2_actualSpeedsMisc1_dr_5000BRCM_X4          17
#define xgxsBlk2_actualSpeedsMisc1_dr_6000BRCM_X4          18
#define xgxsBlk2_actualSpeedsMisc1_dr_10GHiGig_X4          19
#define xgxsBlk2_actualSpeedsMisc1_dr_10GBASE_CX4          20
#define xgxsBlk2_actualSpeedsMisc1_dr_12GHiGig_X4          21
#define xgxsBlk2_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
#define xgxsBlk2_actualSpeedsMisc1_dr_13GHiGig_X4          23
#define xgxsBlk2_actualSpeedsMisc1_dr_15GHiGig_X4          24
#define xgxsBlk2_actualSpeedsMisc1_dr_16GHiGig_X4          25
#define xgxsBlk2_actualSpeedsMisc1_dr_5000BRCM_X1          26
#define xgxsBlk2_actualSpeedsMisc1_dr_6363BRCM_X1          27
#define xgxsBlk2_actualSpeedsMisc1_dr_20GHiGig_X4          28
#define xgxsBlk2_actualSpeedsMisc1_dr_21GHiGig_X4          29
#define xgxsBlk2_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
#define xgxsBlk2_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31

/****************************************************************************
 * Enums: xgxsBlk2_IndLaneModes
 ***************************************************************************/
#define xgxsBlk2_IndLaneModes_SWSDR_div2                   0
#define xgxsBlk2_IndLaneModes_SWSDR_div1                   1
#define xgxsBlk2_IndLaneModes_DWSDR_div2                   2
#define xgxsBlk2_IndLaneModes_DWSDR_div1                   3

/****************************************************************************
 * Enums: xgxsBlk2_prbsSelect
 ***************************************************************************/
#define xgxsBlk2_prbsSelect_prbs7                          0
#define xgxsBlk2_prbsSelect_prbs15                         1
#define xgxsBlk2_prbsSelect_prbs23                         2
#define xgxsBlk2_prbsSelect_prbs31                         3

/****************************************************************************
 * Enums: xgxsBlk2_vcoDivider
 ***************************************************************************/
#define xgxsBlk2_vcoDivider_div32                          0
#define xgxsBlk2_vcoDivider_div36                          1
#define xgxsBlk2_vcoDivider_div40                          2
#define xgxsBlk2_vcoDivider_div42                          3
#define xgxsBlk2_vcoDivider_div48                          4
#define xgxsBlk2_vcoDivider_div50                          5
#define xgxsBlk2_vcoDivider_div52                          6
#define xgxsBlk2_vcoDivider_div54                          7
#define xgxsBlk2_vcoDivider_div60                          8
#define xgxsBlk2_vcoDivider_div64                          9
#define xgxsBlk2_vcoDivider_div66                          10
#define xgxsBlk2_vcoDivider_div68                          11
#define xgxsBlk2_vcoDivider_div70                          12
#define xgxsBlk2_vcoDivider_div80                          13
#define xgxsBlk2_vcoDivider_div92                          14
#define xgxsBlk2_vcoDivider_div100                         15

/****************************************************************************
 * Enums: xgxsBlk2_refClkSelect
 ***************************************************************************/
#define xgxsBlk2_refClkSelect_clk_25MHz                    0
#define xgxsBlk2_refClkSelect_clk_100MHz                   1
#define xgxsBlk2_refClkSelect_clk_125MHz                   2
#define xgxsBlk2_refClkSelect_clk_156p25MHz                3
#define xgxsBlk2_refClkSelect_clk_187p5MHz                 4
#define xgxsBlk2_refClkSelect_clk_161p25Mhz                5
#define xgxsBlk2_refClkSelect_clk_50Mhz                    6
#define xgxsBlk2_refClkSelect_clk_106p25Mhz                7

/****************************************************************************
 * Enums: xgxsBlk2_aerMMDdevTypeSelect
 ***************************************************************************/
#define xgxsBlk2_aerMMDdevTypeSelect_combo_core            0
#define xgxsBlk2_aerMMDdevTypeSelect_PMA_PMD               1
#define xgxsBlk2_aerMMDdevTypeSelect_PCS                   3
#define xgxsBlk2_aerMMDdevTypeSelect_PHY                   4
#define xgxsBlk2_aerMMDdevTypeSelect_DTE                   5
#define xgxsBlk2_aerMMDdevTypeSelect_CL73_AN               7

/****************************************************************************
 * Enums: xgxsBlk2_aerMMDportSelect
 ***************************************************************************/
#define xgxsBlk2_aerMMDportSelect_ln0                      0
#define xgxsBlk2_aerMMDportSelect_ln1                      1
#define xgxsBlk2_aerMMDportSelect_ln2                      2
#define xgxsBlk2_aerMMDportSelect_ln3                      3
#define xgxsBlk2_aerMMDportSelect_BCST                     511

/****************************************************************************
 * Enums: xgxsBlk2_firmwareModeSelect
 ***************************************************************************/
#define xgxsBlk2_firmwareModeSelect_DEFAULT                0
#define xgxsBlk2_firmwareModeSelect_SFP_OPT_LR             1
#define xgxsBlk2_firmwareModeSelect_SFP_DAC                2
#define xgxsBlk2_firmwareModeSelect_XLAUI                  3
#define xgxsBlk2_firmwareModeSelect_LONG_CH_6G             4

/****************************************************************************
 * Enums: xgxsBlk2_tempIdxSelect
 ***************************************************************************/
#define xgxsBlk2_tempIdxSelect_LTE__22p9C                  15
#define xgxsBlk2_tempIdxSelect_LTE__12p6C                  14
#define xgxsBlk2_tempIdxSelect_LTE__3p0C                   13
#define xgxsBlk2_tempIdxSelect_LTE_6p7C                    12
#define xgxsBlk2_tempIdxSelect_LTE_16p4C                   11
#define xgxsBlk2_tempIdxSelect_LTE_26p6C                   10
#define xgxsBlk2_tempIdxSelect_LTE_36p3C                   9
#define xgxsBlk2_tempIdxSelect_LTE_46p0C                   8
#define xgxsBlk2_tempIdxSelect_LTE_56p2C                   7
#define xgxsBlk2_tempIdxSelect_LTE_65p9C                   6
#define xgxsBlk2_tempIdxSelect_LTE_75p6C                   5
#define xgxsBlk2_tempIdxSelect_LTE_85p3C                   4
#define xgxsBlk2_tempIdxSelect_LTE_95p5C                   3
#define xgxsBlk2_tempIdxSelect_LTE_105p2C                  2
#define xgxsBlk2_tempIdxSelect_LTE_114p9C                  1
#define xgxsBlk2_tempIdxSelect_LTE_125p1C                  0

/****************************************************************************
 * Enums: xgxsBlk4_operationModes
 ***************************************************************************/
#define xgxsBlk4_operationModes_XGXS                       0
#define xgxsBlk4_operationModes_XGXG_nCC                   1
#define xgxsBlk4_operationModes_Indlane_OS8                4
#define xgxsBlk4_operationModes_IndLane_OS5                5
#define xgxsBlk4_operationModes_IndLane_OS4                6
#define xgxsBlk4_operationModes_PCI                        7
#define xgxsBlk4_operationModes_XGXS_nLQ                   8
#define xgxsBlk4_operationModes_XGXS_nLQnCC                9
#define xgxsBlk4_operationModes_PBypass                    10
#define xgxsBlk4_operationModes_PBypass_nDSK               11
#define xgxsBlk4_operationModes_ComboCoreMode              12
#define xgxsBlk4_operationModes_Clocks_off                 15

/****************************************************************************
 * Enums: xgxsBlk4_actualSpeeds4
 ***************************************************************************/
#define xgxsBlk4_actualSpeeds4_dr_10M                      0
#define xgxsBlk4_actualSpeeds4_dr_100M                     1
#define xgxsBlk4_actualSpeeds4_dr_1G                       2
#define xgxsBlk4_actualSpeeds4_dr_2p5G                     3
#define xgxsBlk4_actualSpeeds4_dr_5G_X4                    4
#define xgxsBlk4_actualSpeeds4_dr_6G_X4                    5
#define xgxsBlk4_actualSpeeds4_dr_10G_HiG                  6
#define xgxsBlk4_actualSpeeds4_dr_10G_CX4                  7
#define xgxsBlk4_actualSpeeds4_dr_12G_HiG                  8
#define xgxsBlk4_actualSpeeds4_dr_12p5G_X4                 9
#define xgxsBlk4_actualSpeeds4_dr_13G_X4                   10
#define xgxsBlk4_actualSpeeds4_dr_15G_X4                   11
#define xgxsBlk4_actualSpeeds4_dr_16G_X4                   12

/****************************************************************************
 * Enums: xgxsBlk4_actualSpeeds5
 ***************************************************************************/
#define xgxsBlk4_actualSpeeds5_dr_10M                      0
#define xgxsBlk4_actualSpeeds5_dr_100M                     1
#define xgxsBlk4_actualSpeeds5_dr_1G                       2
#define xgxsBlk4_actualSpeeds5_dr_2p5G                     3
#define xgxsBlk4_actualSpeeds5_dr_5G_X4                    4
#define xgxsBlk4_actualSpeeds5_dr_6G_X4                    5
#define xgxsBlk4_actualSpeeds5_dr_10G_HiG                  6
#define xgxsBlk4_actualSpeeds5_dr_10G_CX4                  7
#define xgxsBlk4_actualSpeeds5_dr_12G_HiG                  8
#define xgxsBlk4_actualSpeeds5_dr_12p5G_X4                 9
#define xgxsBlk4_actualSpeeds5_dr_13G_X4                   10
#define xgxsBlk4_actualSpeeds5_dr_15G_X4                   11
#define xgxsBlk4_actualSpeeds5_dr_16G_X4                   12
#define xgxsBlk4_actualSpeeds5_dr_1G_KX                    13
#define xgxsBlk4_actualSpeeds5_dr_10G_KX4                  14
#define xgxsBlk4_actualSpeeds5_dr_10G_KR                   15
#define xgxsBlk4_actualSpeeds5_dr_5G                       16
#define xgxsBlk4_actualSpeeds5_dr_6p4G                     17
#define xgxsBlk4_actualSpeeds5_dr_20G_X4                   18
#define xgxsBlk4_actualSpeeds5_dr_21G_X4                   19
#define xgxsBlk4_actualSpeeds5_dr_25G_X4                   20
#define xgxsBlk4_actualSpeeds5_dr_10G_HiG_DXGXS            21
#define xgxsBlk4_actualSpeeds5_dr_10G_DXGXS                22
#define xgxsBlk4_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
#define xgxsBlk4_actualSpeeds5_dr_10p5G_DXGXS              24
#define xgxsBlk4_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
#define xgxsBlk4_actualSpeeds5_dr_12p773G_DXGXS            26
#define xgxsBlk4_actualSpeeds5_dr_10G_XFI                  27
#define xgxsBlk4_actualSpeeds5_dr_40G                      28
#define xgxsBlk4_actualSpeeds5_dr_20G_HiG_DXGXS            29
#define xgxsBlk4_actualSpeeds5_dr_20G_DXGXS                30
#define xgxsBlk4_actualSpeeds5_dr_10G_SFI                  31
#define xgxsBlk4_actualSpeeds5_dr_31p5G                    32
#define xgxsBlk4_actualSpeeds5_dr_32p7G                    33
#define xgxsBlk4_actualSpeeds5_dr_20G_SCR                  34
#define xgxsBlk4_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
#define xgxsBlk4_actualSpeeds5_dr_10G_DXGXS_SCR            36
#define xgxsBlk4_actualSpeeds5_dr_12G_R2                   37
#define xgxsBlk4_actualSpeeds5_dr_10G_X2                   38
#define xgxsBlk4_actualSpeeds5_dr_40G_KR4                  39
#define xgxsBlk4_actualSpeeds5_dr_40G_CR4                  40
#define xgxsBlk4_actualSpeeds5_dr_100G_CR10                41
#define xgxsBlk4_actualSpeeds5_dr_15p75G_DXGXS             44
#define xgxsBlk4_actualSpeeds5_dr_20G_KR2                  57
#define xgxsBlk4_actualSpeeds5_dr_20G_CR2                  58

/****************************************************************************
 * Enums: xgxsBlk4_actualSpeedsMisc1
 ***************************************************************************/
#define xgxsBlk4_actualSpeedsMisc1_dr_2500BRCM_X1          16
#define xgxsBlk4_actualSpeedsMisc1_dr_5000BRCM_X4          17
#define xgxsBlk4_actualSpeedsMisc1_dr_6000BRCM_X4          18
#define xgxsBlk4_actualSpeedsMisc1_dr_10GHiGig_X4          19
#define xgxsBlk4_actualSpeedsMisc1_dr_10GBASE_CX4          20
#define xgxsBlk4_actualSpeedsMisc1_dr_12GHiGig_X4          21
#define xgxsBlk4_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
#define xgxsBlk4_actualSpeedsMisc1_dr_13GHiGig_X4          23
#define xgxsBlk4_actualSpeedsMisc1_dr_15GHiGig_X4          24
#define xgxsBlk4_actualSpeedsMisc1_dr_16GHiGig_X4          25
#define xgxsBlk4_actualSpeedsMisc1_dr_5000BRCM_X1          26
#define xgxsBlk4_actualSpeedsMisc1_dr_6363BRCM_X1          27
#define xgxsBlk4_actualSpeedsMisc1_dr_20GHiGig_X4          28
#define xgxsBlk4_actualSpeedsMisc1_dr_21GHiGig_X4          29
#define xgxsBlk4_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
#define xgxsBlk4_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31

/****************************************************************************
 * Enums: xgxsBlk4_IndLaneModes
 ***************************************************************************/
#define xgxsBlk4_IndLaneModes_SWSDR_div2                   0
#define xgxsBlk4_IndLaneModes_SWSDR_div1                   1
#define xgxsBlk4_IndLaneModes_DWSDR_div2                   2
#define xgxsBlk4_IndLaneModes_DWSDR_div1                   3

/****************************************************************************
 * Enums: xgxsBlk4_prbsSelect
 ***************************************************************************/
#define xgxsBlk4_prbsSelect_prbs7                          0
#define xgxsBlk4_prbsSelect_prbs15                         1
#define xgxsBlk4_prbsSelect_prbs23                         2
#define xgxsBlk4_prbsSelect_prbs31                         3

/****************************************************************************
 * Enums: xgxsBlk4_vcoDivider
 ***************************************************************************/
#define xgxsBlk4_vcoDivider_div32                          0
#define xgxsBlk4_vcoDivider_div36                          1
#define xgxsBlk4_vcoDivider_div40                          2
#define xgxsBlk4_vcoDivider_div42                          3
#define xgxsBlk4_vcoDivider_div48                          4
#define xgxsBlk4_vcoDivider_div50                          5
#define xgxsBlk4_vcoDivider_div52                          6
#define xgxsBlk4_vcoDivider_div54                          7
#define xgxsBlk4_vcoDivider_div60                          8
#define xgxsBlk4_vcoDivider_div64                          9
#define xgxsBlk4_vcoDivider_div66                          10
#define xgxsBlk4_vcoDivider_div68                          11
#define xgxsBlk4_vcoDivider_div70                          12
#define xgxsBlk4_vcoDivider_div80                          13
#define xgxsBlk4_vcoDivider_div92                          14
#define xgxsBlk4_vcoDivider_div100                         15

/****************************************************************************
 * Enums: xgxsBlk4_refClkSelect
 ***************************************************************************/
#define xgxsBlk4_refClkSelect_clk_25MHz                    0
#define xgxsBlk4_refClkSelect_clk_100MHz                   1
#define xgxsBlk4_refClkSelect_clk_125MHz                   2
#define xgxsBlk4_refClkSelect_clk_156p25MHz                3
#define xgxsBlk4_refClkSelect_clk_187p5MHz                 4
#define xgxsBlk4_refClkSelect_clk_161p25Mhz                5
#define xgxsBlk4_refClkSelect_clk_50Mhz                    6
#define xgxsBlk4_refClkSelect_clk_106p25Mhz                7

/****************************************************************************
 * Enums: xgxsBlk4_aerMMDdevTypeSelect
 ***************************************************************************/
#define xgxsBlk4_aerMMDdevTypeSelect_combo_core            0
#define xgxsBlk4_aerMMDdevTypeSelect_PMA_PMD               1
#define xgxsBlk4_aerMMDdevTypeSelect_PCS                   3
#define xgxsBlk4_aerMMDdevTypeSelect_PHY                   4
#define xgxsBlk4_aerMMDdevTypeSelect_DTE                   5
#define xgxsBlk4_aerMMDdevTypeSelect_CL73_AN               7

/****************************************************************************
 * Enums: xgxsBlk4_aerMMDportSelect
 ***************************************************************************/
#define xgxsBlk4_aerMMDportSelect_ln0                      0
#define xgxsBlk4_aerMMDportSelect_ln1                      1
#define xgxsBlk4_aerMMDportSelect_ln2                      2
#define xgxsBlk4_aerMMDportSelect_ln3                      3
#define xgxsBlk4_aerMMDportSelect_BCST                     511

/****************************************************************************
 * Enums: xgxsBlk4_firmwareModeSelect
 ***************************************************************************/
#define xgxsBlk4_firmwareModeSelect_DEFAULT                0
#define xgxsBlk4_firmwareModeSelect_SFP_OPT_LR             1
#define xgxsBlk4_firmwareModeSelect_SFP_DAC                2
#define xgxsBlk4_firmwareModeSelect_XLAUI                  3
#define xgxsBlk4_firmwareModeSelect_LONG_CH_6G             4

/****************************************************************************
 * Enums: xgxsBlk4_tempIdxSelect
 ***************************************************************************/
#define xgxsBlk4_tempIdxSelect_LTE__22p9C                  15
#define xgxsBlk4_tempIdxSelect_LTE__12p6C                  14
#define xgxsBlk4_tempIdxSelect_LTE__3p0C                   13
#define xgxsBlk4_tempIdxSelect_LTE_6p7C                    12
#define xgxsBlk4_tempIdxSelect_LTE_16p4C                   11
#define xgxsBlk4_tempIdxSelect_LTE_26p6C                   10
#define xgxsBlk4_tempIdxSelect_LTE_36p3C                   9
#define xgxsBlk4_tempIdxSelect_LTE_46p0C                   8
#define xgxsBlk4_tempIdxSelect_LTE_56p2C                   7
#define xgxsBlk4_tempIdxSelect_LTE_65p9C                   6
#define xgxsBlk4_tempIdxSelect_LTE_75p6C                   5
#define xgxsBlk4_tempIdxSelect_LTE_85p3C                   4
#define xgxsBlk4_tempIdxSelect_LTE_95p5C                   3
#define xgxsBlk4_tempIdxSelect_LTE_105p2C                  2
#define xgxsBlk4_tempIdxSelect_LTE_114p9C                  1
#define xgxsBlk4_tempIdxSelect_LTE_125p1C                  0

/****************************************************************************
 * Enums: xgxsBlk7_operationModes
 ***************************************************************************/
#define xgxsBlk7_operationModes_XGXS                       0
#define xgxsBlk7_operationModes_XGXG_nCC                   1
#define xgxsBlk7_operationModes_Indlane_OS8                4
#define xgxsBlk7_operationModes_IndLane_OS5                5
#define xgxsBlk7_operationModes_IndLane_OS4                6
#define xgxsBlk7_operationModes_PCI                        7
#define xgxsBlk7_operationModes_XGXS_nLQ                   8
#define xgxsBlk7_operationModes_XGXS_nLQnCC                9
#define xgxsBlk7_operationModes_PBypass                    10
#define xgxsBlk7_operationModes_PBypass_nDSK               11
#define xgxsBlk7_operationModes_ComboCoreMode              12
#define xgxsBlk7_operationModes_Clocks_off                 15

/****************************************************************************
 * Enums: xgxsBlk7_actualSpeeds4
 ***************************************************************************/
#define xgxsBlk7_actualSpeeds4_dr_10M                      0
#define xgxsBlk7_actualSpeeds4_dr_100M                     1
#define xgxsBlk7_actualSpeeds4_dr_1G                       2
#define xgxsBlk7_actualSpeeds4_dr_2p5G                     3
#define xgxsBlk7_actualSpeeds4_dr_5G_X4                    4
#define xgxsBlk7_actualSpeeds4_dr_6G_X4                    5
#define xgxsBlk7_actualSpeeds4_dr_10G_HiG                  6
#define xgxsBlk7_actualSpeeds4_dr_10G_CX4                  7
#define xgxsBlk7_actualSpeeds4_dr_12G_HiG                  8
#define xgxsBlk7_actualSpeeds4_dr_12p5G_X4                 9
#define xgxsBlk7_actualSpeeds4_dr_13G_X4                   10
#define xgxsBlk7_actualSpeeds4_dr_15G_X4                   11
#define xgxsBlk7_actualSpeeds4_dr_16G_X4                   12

/****************************************************************************
 * Enums: xgxsBlk7_actualSpeeds5
 ***************************************************************************/
#define xgxsBlk7_actualSpeeds5_dr_10M                      0
#define xgxsBlk7_actualSpeeds5_dr_100M                     1
#define xgxsBlk7_actualSpeeds5_dr_1G                       2
#define xgxsBlk7_actualSpeeds5_dr_2p5G                     3
#define xgxsBlk7_actualSpeeds5_dr_5G_X4                    4
#define xgxsBlk7_actualSpeeds5_dr_6G_X4                    5
#define xgxsBlk7_actualSpeeds5_dr_10G_HiG                  6
#define xgxsBlk7_actualSpeeds5_dr_10G_CX4                  7
#define xgxsBlk7_actualSpeeds5_dr_12G_HiG                  8
#define xgxsBlk7_actualSpeeds5_dr_12p5G_X4                 9
#define xgxsBlk7_actualSpeeds5_dr_13G_X4                   10
#define xgxsBlk7_actualSpeeds5_dr_15G_X4                   11
#define xgxsBlk7_actualSpeeds5_dr_16G_X4                   12
#define xgxsBlk7_actualSpeeds5_dr_1G_KX                    13
#define xgxsBlk7_actualSpeeds5_dr_10G_KX4                  14
#define xgxsBlk7_actualSpeeds5_dr_10G_KR                   15
#define xgxsBlk7_actualSpeeds5_dr_5G                       16
#define xgxsBlk7_actualSpeeds5_dr_6p4G                     17
#define xgxsBlk7_actualSpeeds5_dr_20G_X4                   18
#define xgxsBlk7_actualSpeeds5_dr_21G_X4                   19
#define xgxsBlk7_actualSpeeds5_dr_25G_X4                   20
#define xgxsBlk7_actualSpeeds5_dr_10G_HiG_DXGXS            21
#define xgxsBlk7_actualSpeeds5_dr_10G_DXGXS                22
#define xgxsBlk7_actualSpeeds5_dr_10p5G_HiG_DXGXS          23
#define xgxsBlk7_actualSpeeds5_dr_10p5G_DXGXS              24
#define xgxsBlk7_actualSpeeds5_dr_12p773G_HiG_DXGXS        25
#define xgxsBlk7_actualSpeeds5_dr_12p773G_DXGXS            26
#define xgxsBlk7_actualSpeeds5_dr_10G_XFI                  27
#define xgxsBlk7_actualSpeeds5_dr_40G                      28
#define xgxsBlk7_actualSpeeds5_dr_20G_HiG_DXGXS            29
#define xgxsBlk7_actualSpeeds5_dr_20G_DXGXS                30
#define xgxsBlk7_actualSpeeds5_dr_10G_SFI                  31
#define xgxsBlk7_actualSpeeds5_dr_31p5G                    32
#define xgxsBlk7_actualSpeeds5_dr_32p7G                    33
#define xgxsBlk7_actualSpeeds5_dr_20G_SCR                  34
#define xgxsBlk7_actualSpeeds5_dr_10G_HiG_DXGXS_SCR        35
#define xgxsBlk7_actualSpeeds5_dr_10G_DXGXS_SCR            36
#define xgxsBlk7_actualSpeeds5_dr_12G_R2                   37
#define xgxsBlk7_actualSpeeds5_dr_10G_X2                   38
#define xgxsBlk7_actualSpeeds5_dr_40G_KR4                  39
#define xgxsBlk7_actualSpeeds5_dr_40G_CR4                  40
#define xgxsBlk7_actualSpeeds5_dr_100G_CR10                41
#define xgxsBlk7_actualSpeeds5_dr_15p75G_DXGXS             44
#define xgxsBlk7_actualSpeeds5_dr_20G_KR2                  57
#define xgxsBlk7_actualSpeeds5_dr_20G_CR2                  58

/****************************************************************************
 * Enums: xgxsBlk7_actualSpeedsMisc1
 ***************************************************************************/
#define xgxsBlk7_actualSpeedsMisc1_dr_2500BRCM_X1          16
#define xgxsBlk7_actualSpeedsMisc1_dr_5000BRCM_X4          17
#define xgxsBlk7_actualSpeedsMisc1_dr_6000BRCM_X4          18
#define xgxsBlk7_actualSpeedsMisc1_dr_10GHiGig_X4          19
#define xgxsBlk7_actualSpeedsMisc1_dr_10GBASE_CX4          20
#define xgxsBlk7_actualSpeedsMisc1_dr_12GHiGig_X4          21
#define xgxsBlk7_actualSpeedsMisc1_dr_12p5GHiGig_X4        22
#define xgxsBlk7_actualSpeedsMisc1_dr_13GHiGig_X4          23
#define xgxsBlk7_actualSpeedsMisc1_dr_15GHiGig_X4          24
#define xgxsBlk7_actualSpeedsMisc1_dr_16GHiGig_X4          25
#define xgxsBlk7_actualSpeedsMisc1_dr_5000BRCM_X1          26
#define xgxsBlk7_actualSpeedsMisc1_dr_6363BRCM_X1          27
#define xgxsBlk7_actualSpeedsMisc1_dr_20GHiGig_X4          28
#define xgxsBlk7_actualSpeedsMisc1_dr_21GHiGig_X4          29
#define xgxsBlk7_actualSpeedsMisc1_dr_25p45GHiGig_X4       30
#define xgxsBlk7_actualSpeedsMisc1_dr_10G_HiG_DXGXS        31

/****************************************************************************
 * Enums: xgxsBlk7_IndLaneModes
 ***************************************************************************/
#define xgxsBlk7_IndLaneModes_SWSDR_div2                   0
#define xgxsBlk7_IndLaneModes_SWSDR_div1                   1
#define xgxsBlk7_IndLaneModes_DWSDR_div2                   2
#define xgxsBlk7_IndLaneModes_DWSDR_div1                   3

/****************************************************************************
 * Enums: xgxsBlk7_prbsSelect
 ***************************************************************************/
#define xgxsBlk7_prbsSelect_prbs7                          0
#define xgxsBlk7_prbsSelect_prbs15                         1
#define xgxsBlk7_prbsSelect_prbs23                         2
#define xgxsBlk7_prbsSelect_prbs31                         3

/****************************************************************************
 * Enums: xgxsBlk7_vcoDivider
 ***************************************************************************/
#define xgxsBlk7_vcoDivider_div32                          0
#define xgxsBlk7_vcoDivider_div36                          1
#define xgxsBlk7_vcoDivider_div40                          2
#define xgxsBlk7_vcoDivider_div42                          3
#define xgxsBlk7_vcoDivider_div48                          4
#define xgxsBlk7_vcoDivider_div50                          5
#define xgxsBlk7_vcoDivider_div52                          6
#define xgxsBlk7_vcoDivider_div54                          7
#define xgxsBlk7_vcoDivider_div60                          8
#define xgxsBlk7_vcoDivider_div64                          9
#define xgxsBlk7_vcoDivider_div66                          10
#define xgxsBlk7_vcoDivider_div68                          11
#define xgxsBlk7_vcoDivider_div70                          12
#define xgxsBlk7_vcoDivider_div80                          13
#define xgxsBlk7_vcoDivider_div92                          14
#define xgxsBlk7_vcoDivider_div100                         15

/****************************************************************************
 * Enums: xgxsBlk7_refClkSelect
 ***************************************************************************/
#define xgxsBlk7_refClkSelect_clk_25MHz                    0
#define xgxsBlk7_refClkSelect_clk_100MHz                   1
#define xgxsBlk7_refClkSelect_clk_125MHz                   2
#define xgxsBlk7_refClkSelect_clk_156p25MHz                3
#define xgxsBlk7_refClkSelect_clk_187p5MHz                 4
#define xgxsBlk7_refClkSelect_clk_161p25Mhz                5
#define xgxsBlk7_refClkSelect_clk_50Mhz                    6
#define xgxsBlk7_refClkSelect_clk_106p25Mhz                7

/****************************************************************************
 * Enums: xgxsBlk7_aerMMDdevTypeSelect
 ***************************************************************************/
#define xgxsBlk7_aerMMDdevTypeSelect_combo_core            0
#define xgxsBlk7_aerMMDdevTypeSelect_PMA_PMD               1
#define xgxsBlk7_aerMMDdevTypeSelect_PCS                   3
#define xgxsBlk7_aerMMDdevTypeSelect_PHY                   4
#define xgxsBlk7_aerMMDdevTypeSelect_DTE                   5
#define xgxsBlk7_aerMMDdevTypeSelect_CL73_AN               7

/****************************************************************************
 * Enums: xgxsBlk7_aerMMDportSelect
 ***************************************************************************/
#define xgxsBlk7_aerMMDportSelect_ln0                      0
#define xgxsBlk7_aerMMDportSelect_ln1                      1
#define xgxsBlk7_aerMMDportSelect_ln2                      2
#define xgxsBlk7_aerMMDportSelect_ln3                      3
#define xgxsBlk7_aerMMDportSelect_BCST                     511

/****************************************************************************
 * Enums: xgxsBlk7_firmwareModeSelect
 ***************************************************************************/
#define xgxsBlk7_firmwareModeSelect_DEFAULT                0
#define xgxsBlk7_firmwareModeSelect_SFP_OPT_LR             1
#define xgxsBlk7_firmwareModeSelect_SFP_DAC                2
#define xgxsBlk7_firmwareModeSelect_XLAUI                  3
#define xgxsBlk7_firmwareModeSelect_LONG_CH_6G             4

/****************************************************************************
 * Enums: xgxsBlk7_tempIdxSelect
 ***************************************************************************/
#define xgxsBlk7_tempIdxSelect_LTE__22p9C                  15
#define xgxsBlk7_tempIdxSelect_LTE__12p6C                  14
#define xgxsBlk7_tempIdxSelect_LTE__3p0C                   13
#define xgxsBlk7_tempIdxSelect_LTE_6p7C                    12
#define xgxsBlk7_tempIdxSelect_LTE_16p4C                   11
#define xgxsBlk7_tempIdxSelect_LTE_26p6C                   10
#define xgxsBlk7_tempIdxSelect_LTE_36p3C                   9
#define xgxsBlk7_tempIdxSelect_LTE_46p0C                   8
#define xgxsBlk7_tempIdxSelect_LTE_56p2C                   7
#define xgxsBlk7_tempIdxSelect_LTE_65p9C                   6
#define xgxsBlk7_tempIdxSelect_LTE_75p6C                   5
#define xgxsBlk7_tempIdxSelect_LTE_85p3C                   4
#define xgxsBlk7_tempIdxSelect_LTE_95p5C                   3
#define xgxsBlk7_tempIdxSelect_LTE_105p2C                  2
#define xgxsBlk7_tempIdxSelect_LTE_114p9C                  1
#define xgxsBlk7_tempIdxSelect_LTE_125p1C                  0

/****************************************************************************
 * Enums: xgxsBlk7_cl48TxEEEStates_l
 ***************************************************************************/
#define xgxsBlk7_cl48TxEEEStates_l_TX_REFRESH              8
#define xgxsBlk7_cl48TxEEEStates_l_TX_QUIET                4
#define xgxsBlk7_cl48TxEEEStates_l_TX_SLEEP                2
#define xgxsBlk7_cl48TxEEEStates_l_TX_ACTIVE               1

/****************************************************************************
 * Enums: xgxsBlk7_cl48TxEEEStates_c
 ***************************************************************************/
#define xgxsBlk7_cl48TxEEEStates_c_TX_REFRESH              3
#define xgxsBlk7_cl48TxEEEStates_c_TX_QUIET                2
#define xgxsBlk7_cl48TxEEEStates_c_TX_SLEEP                1
#define xgxsBlk7_cl48TxEEEStates_c_TX_ACTIVE               0

/****************************************************************************
 * Enums: xgxsBlk7_cl48RxEEEStates_l
 ***************************************************************************/
#define xgxsBlk7_cl48RxEEEStates_l_RX_LINK_FAIL            32
#define xgxsBlk7_cl48RxEEEStates_l_RX_WAKE                 16
#define xgxsBlk7_cl48RxEEEStates_l_RX_QUIET                8
#define xgxsBlk7_cl48RxEEEStates_l_RX_DEACT                4
#define xgxsBlk7_cl48RxEEEStates_l_RX_SLEEP                2
#define xgxsBlk7_cl48RxEEEStates_l_RX_ACTIVE               1

/****************************************************************************
 * Enums: xgxsBlk7_cl48RxEEEStates_c
 ***************************************************************************/
#define xgxsBlk7_cl48RxEEEStates_c_RX_LINK_FAIL            5
#define xgxsBlk7_cl48RxEEEStates_c_RX_WAKE                 4
#define xgxsBlk7_cl48RxEEEStates_c_RX_QUIET                3
#define xgxsBlk7_cl48RxEEEStates_c_RX_DEACT                2
#define xgxsBlk7_cl48RxEEEStates_c_RX_SLEEP                1
#define xgxsBlk7_cl48RxEEEStates_c_RX_ACTIVE               0

/****************************************************************************
 * bcm89530_sys_cfg_VIC0
 ***************************************************************************/
#define VIC0_VICIRQSTATUS              0x00100000 /* IRQ Status Register */
#define VIC0_VICFIQSTATUS              0x00100004 /* FIQ Status Register */
#define VIC0_VICRAWINTR                0x00100008 /* Raw Interrupt Status Register */
#define VIC0_VICINTSELECT              0x0010000c /* Interrupt Select Register */
#define VIC0_VICINTENABLE              0x00100010 /* Interrupt Enable Register */
#define VIC0_VICINTENCLEAR             0x00100014 /* Interrupt Enable Clear Register */
#define VIC0_VICSOFTINT                0x00100018 /* Software Interrupt Register */
#define VIC0_VICSOFTINTCLEAR           0x0010001c /* Software Interrupt Clear Register */
#define VIC0_VICPROTECTION             0x00100020 /* Protection Enable Register */
#define VIC0_VICSWPRIORITYMASK         0x00100024 /* Software Priority Mask Register */
#define VIC0_VICSWPRIORITYDAISY        0x00100028 /* Vector Priority Register For Daisy Chain */
#define VIC0_VICVECTADDR0              0x00100100 /* Vector Address Registers */
#define VIC0_VICVECTADDR1              0x00100104 /* Vector Address Registers */
#define VIC0_VICVECTADDR2              0x00100108 /* Vector Address Registers */
#define VIC0_VICVECTADDR3              0x0010010c /* Vector Address Registers */
#define VIC0_VICVECTADDR4              0x00100110 /* Vector Address Registers */
#define VIC0_VICVECTADDR5              0x00100114 /* Vector Address Registers */
#define VIC0_VICVECTADDR6              0x00100118 /* Vector Address Registers */
#define VIC0_VICVECTADDR7              0x0010011c /* Vector Address Registers */
#define VIC0_VICVECTADDR8              0x00100120 /* Vector Address Registers */
#define VIC0_VICVECTADDR9              0x00100124 /* Vector Address Registers */
#define VIC0_VICVECTADDR10             0x00100128 /* Vector Address Registers */
#define VIC0_VICVECTADDR11             0x0010012c /* Vector Address Registers */
#define VIC0_VICVECTADDR12             0x00100130 /* Vector Address Registers */
#define VIC0_VICVECTADDR13             0x00100134 /* Vector Address Registers */
#define VIC0_VICVECTADDR14             0x00100138 /* Vector Address Registers */
#define VIC0_VICVECTADDR15             0x0010013c /* Vector Address Registers */
#define VIC0_VICVECTADDR16             0x00100140 /* Vector Address Registers */
#define VIC0_VICVECTADDR17             0x00100144 /* Vector Address Registers */
#define VIC0_VICVECTADDR18             0x00100148 /* Vector Address Registers */
#define VIC0_VICVECTADDR19             0x0010014c /* Vector Address Registers */
#define VIC0_VICVECTADDR20             0x00100150 /* Vector Address Registers */
#define VIC0_VICVECTADDR21             0x00100154 /* Vector Address Registers */
#define VIC0_VICVECTADDR22             0x00100158 /* Vector Address Registers */
#define VIC0_VICVECTADDR23             0x0010015c /* Vector Address Registers */
#define VIC0_VICVECTADDR24             0x00100160 /* Vector Address Registers */
#define VIC0_VICVECTADDR25             0x00100164 /* Vector Address Registers */
#define VIC0_VICVECTADDR26             0x00100168 /* Vector Address Registers */
#define VIC0_VICVECTADDR27             0x0010016c /* Vector Address Registers */
#define VIC0_VICVECTADDR28             0x00100170 /* Vector Address Registers */
#define VIC0_VICVECTADDR29             0x00100174 /* Vector Address Registers */
#define VIC0_VICVECTADDR30             0x00100178 /* Vector Address Registers */
#define VIC0_VICVECTADDR31             0x0010017c /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY0          0x00100200 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY1          0x00100204 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY2          0x00100208 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY3          0x0010020c /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY4          0x00100210 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY5          0x00100214 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY6          0x00100218 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY7          0x0010021c /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY8          0x00100220 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY9          0x00100224 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY10         0x00100228 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY11         0x0010022c /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY12         0x00100230 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY13         0x00100234 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY14         0x00100238 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY15         0x0010023c /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY16         0x00100240 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY17         0x00100244 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY18         0x00100248 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY19         0x0010024c /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY20         0x00100250 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY21         0x00100254 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY22         0x00100258 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY23         0x0010025c /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY24         0x00100260 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY25         0x00100264 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY26         0x00100268 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY27         0x0010026c /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY28         0x00100270 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY29         0x00100274 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY30         0x00100278 /* Vector Address Registers */
#define VIC0_VICVECTPRIORITY31         0x0010027c /* Vector Address Registers */
#define VIC0_VICADDRESS                0x00100f00 /* Vector Address Register */
#define VIC0_VICPERIPHID0              0x00100fe0 /* Peripheral Identification Register */
#define VIC0_VICPERIPHID1              0x00100fe4 /* Peripheral Identification Register */
#define VIC0_VICPERIPHID2              0x00100fe8 /* Peripheral Identification Register */
#define VIC0_VICPERIPHID3              0x00100fec /* Peripheral Identification Register */
#define VIC0_VICPCELLID0               0x00100ff0 /* Primecell Identification Register */
#define VIC0_VICPCELLID1               0x00100ff4 /* Primecell Identification Register */
#define VIC0_VICPCELLID2               0x00100ff8 /* Primecell Identification Register */
#define VIC0_VICPCELLID3               0x00100ffc /* Primecell Identification Register */


/****************************************************************************
 * bcm89530_sys_cfg_SBM
 ***************************************************************************/
#define SBM_CNT_CTRL                   0x00102000 /* Counts down 32Khz counter */
#define SBM_CMUX_CTRL                  0x00102004 /* Performance Monitoring Control Mux */
#define SBM_CNT_32K                    0x00102008 /* Current Value of 32KHZ Counter */
#define SBM_TO_CNT0                    0x0010200c /* Timeout Counter 0 */
#define SBM_TO_CNT1                    0x00102010 /* Timeout Counter 1 */
#define SBM_MISC_CTL                   0x00102014 /* Miscellaneous Control Register */
#define SBM_SLV0_PRI                   0x00102020 /* Slave Port 0 Master Priority Register */
#define SBM_TMR_S0_M1                  0x00102024 /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S0_M3                  0x00102028 /* Slave Port 8 Master Priority Register */
#define SBM_SLV1_PRI                   0x00102044 /* Slave Port 1 Master Priority Register */
#define SBM_TMR_S1_M1                  0x00102048 /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S1_M3                  0x0010204c /* Slave Port 8 Master Priority Register */
#define SBM_SLV2_PRI                   0x00102068 /* Slave Port 2 Master Priority Register */
#define SBM_TMR_S2_M1                  0x0010206c /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S2_M3                  0x00102070 /* Slave Port 8 Master Priority Register */
#define SBM_SLV3_PRI                   0x0010208c /* Slave Port 3 Master Priority Register */
#define SBM_TMR_S3_M1                  0x00102090 /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S3_M3                  0x00102094 /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S3_M5                  0x00102098 /* Slave Port 8 Master Priority Register */
#define SBM_SLV4_PRI                   0x001020b0 /* Slave Port 4 Master Priority Register */
#define SBM_TMR_S4_M1                  0x001020b4 /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S4_M3                  0x001020b8 /* Slave Port 8 Master Priority Register */
#define SBM_SLV5_PRI                   0x001020d4 /* Slave Port 5 Master Priority Register */
#define SBM_TMR_S5_M1                  0x001020d8 /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S5_M3                  0x001020dc /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S5_M5                  0x001020e0 /* Slave Port 8 Master Priority Register */
#define SBM_SLV6_PRI                   0x001020f8 /* Slave Port 6 Master Priority Register */
#define SBM_TMR_S6_M1                  0x001020fc /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S6_M3                  0x00102100 /* Slave Port 8 Master Priority Register */
#define SBM_TMR_S6_M5                  0x00102104 /* Slave Port 8 Master Priority Register */


/****************************************************************************
 * bcm89530_sys_cfg_DMA1
 ***************************************************************************/
#define DMA1_DMACINTSTATUS             0x00104000 /* Interrupt Status Register */
#define DMA1_DMACINTTCSTATUS           0x00104004 /* Interrupt Terminal Count Status Register */
#define DMA1_DMACINTTCCLEAR            0x00104008 /* Interrupt Terminal Count Clear Register */
#define DMA1_DMACINTERRORSTATUS        0x0010400c /* Interrupt Error Status Register */
#define DMA1_DMACINTERRCLR             0x00104010 /* Interrupt Error Clear Register */
#define DMA1_DMACRAWINTTCSTATUS        0x00104014 /* Raw Interrupt Terminal Count Status Register */
#define DMA1_DMACRAWINTERRORSTATUS     0x00104018 /* Raw Error Interrupt Status Register */
#define DMA1_DMACENBLDCHNS             0x0010401c /* Enabled Channel Register */
#define DMA1_DMACSOFTBREQ              0x00104020 /* Software Burst Request Register */
#define DMA1_DMACSOFTSREQ              0x00104024 /* Software Single Request Register */
#define DMA1_DMACSOFTLBREQ             0x00104028 /* Software Last Burst Request Register */
#define DMA1_DMACSOFTLSREQ             0x0010402c /* Software Last Single Request Register */
#define DMA1_DMACCONFIGURATION         0x00104030 /* Configuration Register */
#define DMA1_DMACSYNC                  0x00104034 /* Synchronization Register */
#define DMA1_DMACC0SRCADDR             0x00104100 /* Channel 0 Source Address Register */
#define DMA1_DMACC0DESTADDR            0x00104104 /* Channel 0 Destination Address Register */
#define DMA1_DMACC0LLI                 0x00104108 /* Channel 0 Linked List Item Register */
#define DMA1_DMACC0CONTROL             0x0010410c /* Channel 0 Control Registers */
#define DMA1_DMACC0CONFIGURATION       0x00104110 /* Channel 0 Configuration Register */
#define DMA1_DMACC1SRCADDR             0x00104120 /* Channel 1 Source Address Register */
#define DMA1_DMACC1DESTADDR            0x00104124 /* Channel 1 Destination Address Register */
#define DMA1_DMACC1LLI                 0x00104128 /* Channel 1 Linked List Item Register */
#define DMA1_DMACC1CONTROL             0x0010412c /* Channel 1 Control Registers */
#define DMA1_DMACC1CONFIGURATION       0x00104130 /* Channel 1 Configuration Register */
#define DMA1_DMACITCR                  0x00104500 /* Test Control Register */
#define DMA1_DMACITOP1                 0x00104504 /* Integration Test Output Register 1 */
#define DMA1_DMACITOP2                 0x00104508 /* Integration Test Output Register 2 */
#define DMA1_DMACITOP3                 0x0010450c /* Integration Test Output Register 3 */
#define DMA1_DMACPERIPHID0             0x00104fe0 /* Peripheral Identification Register */
#define DMA1_DMACPERIPHID1             0x00104fe4 /* Peripheral Identification Register */
#define DMA1_DMACPERIPHID2             0x00104fe8 /* Peripheral Identification Register */
#define DMA1_DMACPERIPHID3             0x00104fec /* Peripheral Identification Register */
#define DMA1_DMACPCELLID0              0x00104ff0 /* Primecell Identification Register */
#define DMA1_DMACPCELLID1              0x00104ff4 /* Primecell Identification Register */
#define DMA1_DMACPCELLID2              0x00104ff8 /* Primecell Identification Register */
#define DMA1_DMACPCELLID3              0x00104ffc /* Primecell Identification Register */


/****************************************************************************
 * bcm89530_sys_cfg_ETH
 ***************************************************************************/
#define ETH_ETH_CTRL                   0x00106000 /* Eth General Control */
#define ETH_INTR_MASK                  0x00106004 /* Interrupt Mask */
#define ETH_INTR                       0x00106008 /* Masked Interrupts */
#define ETH_INTR_RAW                   0x0010600c /* Raw Interrupts */
#define ETH_INTR_CLR                   0x00106010 /* Clear Interrupts (both RAW and INTR) */
#define ETH_MCADDRF0                   0x00106020 /* Multicast Address Filter 0 */
#define ETH_MCADDRF1                   0x00106024 /* Multicast Address Filter 1 */
#define ETH_LSADDR0                    0x00106028 /* Local Station Address Low */
#define ETH_LSCADDR1                   0x0010602c /* Local Station Address High */
#define ETH_OUIADDR0                   0x00106030 /* OUI Address Low */
#define ETH_OUIADDR1                   0x00106034 /* Local Station Address High */
#define ETH_PHYCTRL                    0x00106040 /* Onboard PHY control */
#define ETH_RBUFFCTRL                  0x00106104 /* Receiver Buffer Control */
#define ETH_RBASE                      0x00106110 /* Rx Descriptor Ring Base */
#define ETH_RBCFG                      0x00106114 /* Rx Descriptor Ring Configuration */
#define ETH_RBDPTR                     0x00106118 /* Pointer to Current HW Rx Descriptor */
#define ETH_RSWPTR                     0x0010611c /* Pointer to Current SW Rx Descriptor */
#define ETH_RBCFG_EXT                  0x00106120 /* Rx Descriptor Ring Configuration Extension */
#define ETH_TBASE                      0x00106210 /* Tx Descriptor Ring Base */
#define ETH_TBCFG                      0x00106214 /* Tx Descriptor Ring Configuration */
#define ETH_TBDPTR                     0x00106218 /* Pointer to Current HW Tx Descriptor */
#define ETH_TSWPTR                     0x0010621c /* Pointer to Current SW Tx Descriptor */
#define ETH_MACBP                      0x00106404 /* MAC HD Control */
#define ETH_MACCFG                     0x00106408 /* UniMAC Configuration */
#define ETH_MACADDR0                   0x0010640c /* Ethernet MAC Address Low */
#define ETH_MACADDR1                   0x00106410 /* Ethernet MAC Address Low */
#define ETH_MAXFRM                     0x00106414 /* Maximum allowed frame size */
#define ETH_MACPQ                      0x00106418 /* Ethernet Pause Quanta */
#define ETH_RXFIFO_EMPTY               0x0010641c /* MAC RX FIFO empty watermark */
#define ETH_RXFIFO_FULL                0x00106420 /* MAC RX FIFO full watermark */
#define ETH_TXFIFO_EMPTY               0x00106424 /* MAC TX FIFO empty watermark */
#define ETH_TXFIFO_FULL                0x00106428 /* MAC TX FIFO full watermark */
#define ETH_RXFIFO_AEMPTY              0x0010642c /* MAC RX FIFO almost empty watermark */
#define ETH_RXFIFO_AFULL               0x00106430 /* MAC RX FIFO almost full watermark */
#define ETH_TXFIFO_AEMPTY              0x00106434 /* MAC TX FIFO almost empty watermark */
#define ETH_TXFIFO_AFULL               0x00106438 /* MAC TX FIFO almost full watermark */
#define ETH_MACMODE                    0x00106444 /* Ethernet Mac Status */
#define ETH_VLANTAG0                   0x00106448 /* Outer VLAN Tag */
#define ETH_TXIPG                      0x0010645c /* Transmit Inter Packet Gap */
#define ETH_TXPCTRL                    0x00106730 /* Transmit Pause Control */
#define ETH_TXFIFOF                    0x00106734 /* Transmit Pause Control */
#define ETH_RXFIFOSTAT                 0x00106738 /* Rx FIFO Status */
#define ETH_TXFIFOSTAT                 0x0010673c /* Tx FIFO Status */
#define ETH_TXOCTGOOD                  0x00106800 /* Total Good Octets Transmitted */
#define ETH_TXFRMGOOD                  0x00106804 /* Total Good Frames Transmitted */
#define ETH_TXOCTTOTAL                 0x00106808 /* Total Octets Transmitted */
#define ETH_TXFRMTOTAL                 0x0010680c /* Total Frames Transmitted */
#define ETH_TXBCASTGOOD                0x00106810 /* Total Good Broadcast Frames Transmitted */
#define ETH_TXMCASTGOOD                0x00106814 /* Total Good Multicast Frames Transmitted */
#define ETH_TX64                       0x00106818 /* Total 64B Frames Transmitted */
#define ETH_TX65_127                   0x0010681c /* Total 65-127B Frames Transmitted */
#define ETH_TX128_255                  0x00106820 /* Total 128-255B Frames Transmitted */
#define ETH_TX256_511                  0x00106824 /* Total 256-511B Frames Transmitted */
#define ETH_TX512_1023                 0x00106828 /* Total 512-1023B Frames Transmitted */
#define ETH_TX1024_MAX                 0x0010682c /* Total 1024B-MAXFRM Frames Transmitted */
#define ETH_TXJABBER                   0x00106830 /* Total Frames > MAXFRM with bad CRC */
#define ETH_TXJUMBO                    0x00106834 /* Total Frames > MAXFRM with good CRC */
#define ETH_TXFRAG                     0x00106838 /* Total Frames < 64B with bad CRC */
#define ETH_TXUNDERRUN                 0x0010683c /* Total Frames that experienced an underrun */
#define ETH_TXCOLTOTAL                 0x00106840 /* Total number of collisions seen */
#define ETH_TX1COL                     0x00106844 /* Total Frames that saw exactly one collision */
#define ETH_TXMCOL                     0x00106848 /* Total Frames that saw more than one collision */
#define ETH_TXEXCOL                    0x0010684c /* Total frames that saw excessive collisions */
#define ETH_TXLATE                     0x00106850 /* Total frames that saw late collisions */
#define ETH_TXDEFER                    0x00106854 /* Total frames that were defered */
#define ETH_TXNOCRS                    0x00106858 /* Total frames that saw loss of carrier */
#define ETH_TXPAUSE                    0x0010685c /* Total pause frames sent */
#define ETH_TXCNTOF                    0x0010687c /* Tx Counter Overflow Reporting */
#define ETH_RXOCTGOOD                  0x00106880 /* Total Good Octets Received */
#define ETH_RXFRMGOOD                  0x00106884 /* Total Good Frames Received */
#define ETH_RXOCTTOTAL                 0x00106888 /* Total Octets Received */
#define ETH_RXFRMTOTAL                 0x0010688c /* Total Frames Received */
#define ETH_RXBCASTGOOD                0x00106890 /* Total Good Broadcast Frames Received */
#define ETH_RXMCASTGOOD                0x00106894 /* Total Good Multicast Frames Received */
#define ETH_RX64                       0x00106898 /* Total 64B Frames Received */
#define ETH_RX65_127                   0x0010689c /* Total 65-127B Frames Received */
#define ETH_RX128_255                  0x001068a0 /* Total 128-255B Frames Received */
#define ETH_RX256_511                  0x001068a4 /* Total 256-511B Frames Received */
#define ETH_RX512_1023                 0x001068a8 /* Total 512-1023B Frames Received */
#define ETH_RX1024_MAX                 0x001068ac /* Total 1024B-MAXFRM Frames Received */
#define ETH_RXJABBER                   0x001068b0 /* Total Frames > MAXFRM with bad CRC */
#define ETH_RXJUMBO                    0x001068b4 /* Total Frames > MAXFRM with good CRC */
#define ETH_RXFRAG                     0x001068b8 /* Total Frames < 64B with bad CRC */
#define ETH_RXOVERRUN                  0x001068bc /* Total Frames that experienced an overrun */
#define ETH_RXCRCALIGN                 0x001068c0 /* Rx Frames with bad CRC or alignment */
#define ETH_RXUSIZE                    0x001068c4 /* Total Frames < 64B with good CRC */
#define ETH_RXCRC                      0x001068c8 /* Rx Frames with bad CRC but even alignment */
#define ETH_RXALIGN                    0x001068cc /* Rx Frames with bad CRC and odd alignment */
#define ETH_RXCDERR                    0x001068d0 /* Rx Frames with Code Error (Rx_ER) */
#define ETH_RXPAUSE                    0x001068d4 /* Rx Pause Frames received */
#define ETH_RXCTRLFM                   0x001068d8 /* Rx Control Frames received */
#define ETH_RXCNTOF                    0x001068fc /* Rx Counter Overflow Reporting */


/****************************************************************************
 * bcm89530_sys_cfg_QSPI
 ***************************************************************************/
#define QSPI_BSPI_REGISTERS_REVISION_ID 0x0010a000 /* Revision ID */
#define QSPI_BSPI_REGISTERS_SCRATCH    0x0010a004 /* Revision ID */
#define QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL 0x0010a008 /* Master/Boot SPI Control Register */
#define QSPI_BSPI_REGISTERS_BUSY_STATUS 0x0010a00c /* BSPI Busy Status Register */
#define QSPI_BSPI_REGISTERS_INTR_STATUS 0x0010a010 /* Interrupt Status Register */
#define QSPI_BSPI_REGISTERS_B0_STATUS  0x0010a014 /* Prefetch Buffer 0 Status Register */
#define QSPI_BSPI_REGISTERS_B0_CTRL    0x0010a018 /* Prefetch Buffer 0 Control Register */
#define QSPI_BSPI_REGISTERS_B1_STATUS  0x0010a01c /* Prefetch Buffer 1 Status Register */
#define QSPI_BSPI_REGISTERS_B1_CTRL    0x0010a020 /* Prefetch Buffer 1 Control Register */
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL 0x0010a024 /* Dual/Single Receive Mode Control Register */
#define QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE 0x0010a028 /* Flexible Control Mode Enable Register */
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE 0x0010a02c /* "Bits per cycle b-p-c"" Control Register""" */
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE 0x0010a030 /* "Bits per Phase b-p-p"" Control Register""" */
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE 0x0010a034 /* Command and Mode Data Register */
#define QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE 0x0010a038 /* Bspi FLash upper address byte register */
#define QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE 0x0010a03c /* BSPI FLASH XOR Value Register */
#define QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE 0x0010a040 /* BSPI FLASH XOR Enable Register */
#define QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE 0x0010a044 /* BSPI Pin  Programmed IO Mode Enable Register */
#define QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR 0x0010a048 /* BSPI Pin  Programmed IO Mode Direction Register */
#define QSPI_BSPI_REGISTERS_BSPI_PIO_DATA 0x0010a04c /* BSPI Pin  Programmed IO Mode Data Register */
#define QSPI_RAF_START_ADDR            0x0010a100 /* Physical Starting Address Location in Flash device */
#define QSPI_RAF_NUM_WORDS             0x0010a104 /* Number of Words to be fetched */
#define QSPI_RAF_CTRL                  0x0010a108 /* RAF Session Control Register */
#define QSPI_RAF_FULLNESS              0x0010a10c /* Fullness indicator for the read ahead buffer */
#define QSPI_RAF_WATERMARK             0x0010a110 /* Watermark level in the read ahead buffer that triggers an interrupt */
#define QSPI_RAF_STATUS                0x0010a114 /* Linear Read Status Register */
#define QSPI_RAF_READ_DATA             0x0010a118 /* Read data from Raf-buffer */
#define QSPI_RAF_WORD_CNT              0x0010a11c /* Current number of words fetched from Flash */
#define QSPI_RAF_CURR_ADDR             0x0010a120 /* Current read address for the linear read session */
#define QSPI_MSPI_SPCR0_LSB            0x0010a200 /* SPCR0_LSB REGISTER */
#define QSPI_MSPI_SPCR0_MSB            0x0010a204 /* SPCR0_MSB Register */
#define QSPI_MSPI_SPCR1_LSB            0x0010a208 /* SPCR1_LSB REGISTER */
#define QSPI_MSPI_SPCR1_MSB            0x0010a20c /* SPCR1_MSB REGISTER */
#define QSPI_MSPI_NEWQP                0x0010a210 /* NEWQP REGISTER */
#define QSPI_MSPI_ENDQP                0x0010a214 /* ENDQP REGISTER */
#define QSPI_MSPI_SPCR2                0x0010a218 /* SPCR2 REGISTER */
#define QSPI_MSPI_MSPI_STATUS          0x0010a220 /* MSPI STATUS REGISTER */
#define QSPI_MSPI_CPTQP                0x0010a224 /* CPTQP REGISTER */
#define QSPI_MSPI_TXRAM00              0x0010a240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
#define QSPI_MSPI_TXRAM01              0x0010a244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
#define QSPI_MSPI_TXRAM02              0x0010a248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
#define QSPI_MSPI_TXRAM03              0x0010a24c /* LSbyte for bit 16 operation only (queue pointer = 1) */
#define QSPI_MSPI_TXRAM04              0x0010a250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
#define QSPI_MSPI_TXRAM05              0x0010a254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
#define QSPI_MSPI_TXRAM06              0x0010a258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
#define QSPI_MSPI_TXRAM07              0x0010a25c /* LSbyte for bit 16 operation only (queue pointer = 3) */
#define QSPI_MSPI_TXRAM08              0x0010a260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
#define QSPI_MSPI_TXRAM09              0x0010a264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
#define QSPI_MSPI_TXRAM10              0x0010a268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
#define QSPI_MSPI_TXRAM11              0x0010a26c /* LSbyte for bit 16 operation only (queue pointer = 5) */
#define QSPI_MSPI_TXRAM12              0x0010a270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
#define QSPI_MSPI_TXRAM13              0x0010a274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
#define QSPI_MSPI_TXRAM14              0x0010a278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
#define QSPI_MSPI_TXRAM15              0x0010a27c /* LSbyte for bit 16 operation only (queue pointer = 7) */
#define QSPI_MSPI_TXRAM16              0x0010a280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
#define QSPI_MSPI_TXRAM17              0x0010a284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
#define QSPI_MSPI_TXRAM18              0x0010a288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
#define QSPI_MSPI_TXRAM19              0x0010a28c /* LSbyte for bit 16 operation only (queue pointer = 9) */
#define QSPI_MSPI_TXRAM20              0x0010a290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
#define QSPI_MSPI_TXRAM21              0x0010a294 /* LSbyte for bit 16 operation only (queue pointer = a) */
#define QSPI_MSPI_TXRAM22              0x0010a298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
#define QSPI_MSPI_TXRAM23              0x0010a29c /* LSbyte for bit 16 operation only (queue pointer = b) */
#define QSPI_MSPI_TXRAM24              0x0010a2a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
#define QSPI_MSPI_TXRAM25              0x0010a2a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
#define QSPI_MSPI_TXRAM26              0x0010a2a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
#define QSPI_MSPI_TXRAM27              0x0010a2ac /* LSbyte for bit 16 operation only (queue pointer = d) */
#define QSPI_MSPI_TXRAM28              0x0010a2b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
#define QSPI_MSPI_TXRAM29              0x0010a2b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
#define QSPI_MSPI_TXRAM30              0x0010a2b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
#define QSPI_MSPI_TXRAM31              0x0010a2bc /* LSbyte for bit 16 operation only (queue pointer = f) */
#define QSPI_MSPI_RXRAM00              0x0010a2c0 /* MSbyte for bit 16 operation only (queue pointer = 0) */
#define QSPI_MSPI_RXRAM01              0x0010a2c4 /* LSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
#define QSPI_MSPI_RXRAM02              0x0010a2c8 /* MSbyte for bit 16 operation only (queue pointer = 1) */
#define QSPI_MSPI_RXRAM03              0x0010a2cc /* LSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
#define QSPI_MSPI_RXRAM04              0x0010a2d0 /* MSbyte for bit 16 operation only (queue pointer = 2) */
#define QSPI_MSPI_RXRAM05              0x0010a2d4 /* LSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
#define QSPI_MSPI_RXRAM06              0x0010a2d8 /* MSbyte for bit 16 operation only (queue pointer = 3) */
#define QSPI_MSPI_RXRAM07              0x0010a2dc /* LSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
#define QSPI_MSPI_RXRAM08              0x0010a2e0 /* MSbyte for bit 16 operation only (queue pointer = 4) */
#define QSPI_MSPI_RXRAM09              0x0010a2e4 /* LSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
#define QSPI_MSPI_RXRAM10              0x0010a2e8 /* MSbyte for bit 16 operation only (queue pointer = 5) */
#define QSPI_MSPI_RXRAM11              0x0010a2ec /* LSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
#define QSPI_MSPI_RXRAM12              0x0010a2f0 /* MSbyte for bit 16 operation only (queue pointer = 6) */
#define QSPI_MSPI_RXRAM13              0x0010a2f4 /* LSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
#define QSPI_MSPI_RXRAM14              0x0010a2f8 /* MSbyte for bit 16 operation only (queue pointer = 7) */
#define QSPI_MSPI_RXRAM15              0x0010a2fc /* LSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
#define QSPI_MSPI_RXRAM16              0x0010a300 /* MSbyte for bit 16 operation only (queue pointer = 8) */
#define QSPI_MSPI_RXRAM17              0x0010a304 /* LSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
#define QSPI_MSPI_RXRAM18              0x0010a308 /* MSbyte for bit 16 operation only (queue pointer = 9) */
#define QSPI_MSPI_RXRAM19              0x0010a30c /* LSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
#define QSPI_MSPI_RXRAM20              0x0010a310 /* MSbyte for bit 16 operation only (queue pointer = a) */
#define QSPI_MSPI_RXRAM21              0x0010a314 /* LSbyte for bit 16 or bit 8 operation (queue pointer = a) */
#define QSPI_MSPI_RXRAM22              0x0010a318 /* MSbyte for bit 16 operation only (queue pointer = b) */
#define QSPI_MSPI_RXRAM23              0x0010a31c /* LSbyte for bit 16 or bit 8 operation (queue pointer = b) */
#define QSPI_MSPI_RXRAM24              0x0010a320 /* MSbyte for bit 16 operation only (queue pointer = c) */
#define QSPI_MSPI_RXRAM25              0x0010a324 /* LSbyte for bit 16 or bit 8 operation (queue pointer = c) */
#define QSPI_MSPI_RXRAM26              0x0010a328 /* MSbyte for bit 16 operation only (queue pointer = d) */
#define QSPI_MSPI_RXRAM27              0x0010a32c /* LSbyte for bit 16 or bit 8 operation (queue pointer = d) */
#define QSPI_MSPI_RXRAM28              0x0010a330 /* MSbyte for bit 16 operation only (queue pointer = e) */
#define QSPI_MSPI_RXRAM29              0x0010a334 /* LSbyte for bit 16 or bit 8 operation (queue pointer = e) */
#define QSPI_MSPI_RXRAM30              0x0010a338 /* MSbyte for bit 16 operation only (queue pointer = f) */
#define QSPI_MSPI_RXRAM31              0x0010a33c /* LSbyte for bit 16 or bit 8 operation (queue pointer = f) */
#define QSPI_MSPI_CDRAM00              0x0010a340 /* 8-bit command (queue pointer = 0) */
#define QSPI_MSPI_CDRAM01              0x0010a344 /* 8-bit command (queue pointer = 1) */
#define QSPI_MSPI_CDRAM02              0x0010a348 /* 8-bit command (queue pointer = 2) */
#define QSPI_MSPI_CDRAM03              0x0010a34c /* 8-bit command (queue pointer = 3) */
#define QSPI_MSPI_CDRAM04              0x0010a350 /* 8-bit command (queue pointer = 4) */
#define QSPI_MSPI_CDRAM05              0x0010a354 /* 8-bit command (queue pointer = 5) */
#define QSPI_MSPI_CDRAM06              0x0010a358 /* 8-bit command (queue pointer = 6) */
#define QSPI_MSPI_CDRAM07              0x0010a35c /* 8-bit command (queue pointer = 7) */
#define QSPI_MSPI_CDRAM08              0x0010a360 /* 8-bit command (queue pointer = 8) */
#define QSPI_MSPI_CDRAM09              0x0010a364 /* 8-bit command (queue pointer = 9) */
#define QSPI_MSPI_CDRAM10              0x0010a368 /* 8-bit command (queue pointer = a) */
#define QSPI_MSPI_CDRAM11              0x0010a36c /* 8-bit command (queue pointer = b) */
#define QSPI_MSPI_CDRAM12              0x0010a370 /* 8-bit command (queue pointer = c) */
#define QSPI_MSPI_CDRAM13              0x0010a374 /* 8-bit command (queue pointer = d) */
#define QSPI_MSPI_CDRAM14              0x0010a378 /* 8-bit command (queue pointer = e) */
#define QSPI_MSPI_CDRAM15              0x0010a37c /* 8-bit command (queue pointer = f) */
#define QSPI_MSPI_WRITE_LOCK           0x0010a380 /* Control bit to lock group of write commands */
#define QSPI_MSPI_DISABLE_FLUSH_GEN    0x0010a384 /* Debug bit to mask the generation of flush signals from Mspi */
#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED 0x0010a3a0 /* Interrupt from RAF sub-block */
#define QSPI_RAF_INTERRUPT_LR_TRUNCATED 0x0010a3a4 /* Interrupt from RAF sub-block */
#define QSPI_RAF_INTERRUPT_LR_IMPATIENT 0x0010a3a8 /* Interrupt from RAF sub-block */
#define QSPI_RAF_INTERRUPT_LR_SESSION_DONE 0x0010a3ac /* Interrupt from RAF sub-block */
#define QSPI_RAF_INTERRUPT_LR_OVERREAD 0x0010a3b0 /* Interrupt from RAF sub-block */
#define QSPI_MSPI_INTERRUPT_MSPI_DONE  0x0010a3b4 /* Interrupt from MSPI sub-block */
#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE 0x0010a3b8 /* Interrupt from MSPI sub-block */


/****************************************************************************
 * bcm89530_sys_cfg_MEM
 ***************************************************************************/
#define MEM_STATUS                     0x0010d000 /* Mem Status register */
#define MEM_CNT                        0x0010d004 /* Single bit error counter and threshold */
#define MEM_CTRL                       0x0010d008 /* Mem main control register */
#define MEM_BAD_ADDR                   0x0010d00c /* Error snapshot:address */
#define MEM_BAD_CMD                    0x0010d010 /* Error snapshot:side band and error type */
#define MEM_BAD_DATA                   0x0010d014 /* Error snapshot: lower 32 bits of data */
#define MEM_BAD_DATA1                  0x0010d018 /* Error snapshot: upper 32 bits of data */
#define MEM_BAD_ECC                    0x0010d01c /* Error snapshot: parity and ECC */


/****************************************************************************
 * bcm89530_sys_cfg_TIM0
 ***************************************************************************/
#define TIM0_TIMER1LOAD                0x00140000 /* Load Timer Value for Timer 1 */
#define TIM0_TIMER1VALUE               0x00140004 /* Current Value for Timer 1 */
#define TIM0_TIMER1CONTROL             0x00140008 /* Timer 1 control register */
#define TIM0_TIMER1INTCLR              0x0014000c /* Timer 1 interrupt clear */
#define TIM0_TIMER1RIS                 0x00140010 /* Timer 1 raw interrupt status */
#define TIM0_TIMER1MIS                 0x00140014 /* Timer 1 masked interrupt status */
#define TIM0_TIMER1BGLOAD              0x00140018 /* Background load value for Timer 1 */
#define TIM0_TIMER2LOAD                0x00140020 /* Load Timer Value for Timer 2 */
#define TIM0_TIMER2VALUE               0x00140024 /* Current Value for Timer 2 */
#define TIM0_TIMER2CONTROL             0x00140028 /* Timer 2 control register */
#define TIM0_TIMER2INTCLR              0x0014002c /* Timer 2 interrupt clear */
#define TIM0_TIMER2RIS                 0x00140030 /* Timer 2 raw interrupt status */
#define TIM0_TIMER2MIS                 0x00140034 /* Timer 2 masked interrupt status */
#define TIM0_TIMER2BGLOAD              0x00140038 /* Background load value for Timer 2 */
#define TIM0_TIMERITCR                 0x00140f00 /* Integration test control register */
#define TIM0_TIMERITOP                 0x00140f04 /* Integration test output register */
#define TIM0_TIMERPERIPHID0            0x00140fe0 /* Peripheral ID register bits 7:0 */
#define TIM0_TIMERPERIPHID1            0x00140fe4 /* Peripheral ID register bits 15:8 */
#define TIM0_TIMERPERIPHID2            0x00140fe8 /* Peripheral ID register bits 23:16 */
#define TIM0_TIMERPERIPHID3            0x00140fec /* Peripheral ID register bits 31:24 */
#define TIM0_TIMERPCELLID0             0x00140ff0 /* PrimeCell ID register bits 7:0 */
#define TIM0_TIMERPCELLID1             0x00140ff4 /* PrimeCell ID register bits 15:8 */
#define TIM0_TIMERPCELLID2             0x00140ff8 /* PrimeCell ID register bits 23:16 */
#define TIM0_TIMERPCELLID3             0x00140ffc /* PrimeCell ID register bits 31:24 */


/****************************************************************************
 * bcm89530_sys_cfg_SPI1
 ***************************************************************************/
#define SPI1_SSPCR0                    0x00141000 /* Control Register 0. (See PL022 TRM for details) */
#define SPI1_SSPCR1                    0x00141004 /* Control Register 1. (See PL022 TRM for details) */
#define SPI1_SSPDR                     0x00141008 /* Receive FIFO (read) and transmit FIFO (write) data register. (See PL022 TRM for details) */
#define SPI1_SSPSR                     0x0014100c /* Status register. (See PL022 TRM for details) */
#define SPI1_SSPCPSR                   0x00141010 /* Clock prescale register. (See PL022 TRM for details) */
#define SPI1_SSPIMSC                   0x00141014 /* Interrupt mask set and clear register. (See PL022 TRM for details) */
#define SPI1_SSPRIS                    0x00141018 /* Raw interrupt status register. (See PL022 TRM for details) */
#define SPI1_SSPMIS                    0x0014101c /* Masked interrupt status register. (See PL022 TRM for details) */
#define SPI1_SSPICR                    0x00141020 /* Interrupt clear register. (See PL022 TRM for details) */
#define SPI1_SSPDMACR                  0x00141024 /* DMA control register. (See PL022 TRM for details) */
#define SPI1_SSPPERIPHID0              0x00141fe0 /* "Peripheral identification register bits [7:0]. (See PL022 TRM for details)" */
#define SPI1_SSPPERIPHID1              0x00141fe4 /* "Peripheral identification register bits [15:8]. (See PL022 TRM for details)" */
#define SPI1_SSPPERIPHID2              0x00141fe8 /* "Peripheral identification register bits [23:16]. (See PL022 TRM for details)" */
#define SPI1_SSPPERIPHID3              0x00141fec /* "Peripheral identification register bits [31:24]. (See PL022 TRM for details)" */
#define SPI1_SSPPCELLID0               0x00141ff0 /* "PrimeCell identification register bits [7:0]. (See PL022 TRM for details)" */
#define SPI1_SSPPCELLID1               0x00141ff4 /* "PrimeCell identification register bits [15:8]. (See PL022 TRM for details)" */
#define SPI1_SSPPCELLID2               0x00141ff8 /* "PrimeCell identification register bits [23:16]. (See PL022 TRM for details)" */
#define SPI1_SSPPCELLID3               0x00141ffc /* "PrimeCell identification register bits [31:24]. (See PL022 TRM for details)" */


/****************************************************************************
 * bcm89530_sys_cfg_WDT
 ***************************************************************************/
#define WDT_WDOGLOAD                   0x00145000 /* Watchdog load register. Minimum valid value is 1 */
#define WDT_WDOGVALUE                  0x00145004 /* Watchdog read value */
#define WDT_WDOGCONTROL                0x00145008 /*  */
#define WDT_WDOGINTCLR                 0x0014500c /* "A write of any value to this location clears the Watchdog module interrupt, and reloads the counter from the value in the WdogLoad Register." */
#define WDT_WDOGRIS                    0x00145010 /* Raw interrupt status from the counter */
#define WDT_WDOGMIS                    0x00145014 /* Enabled interrupt status from the counter */
#define WDT_WDOGLOCK                   0x00145c00 /*  */
#define WDT_WDOGITCR                   0x00145f00 /*  */
#define WDT_WDOGITOP                   0x00145f04 /*  */
#define WDT_WDOGPERIPHID0              0x00145fe0 /*  */
#define WDT_WDOGPERIPHID1              0x00145fe4 /*  */
#define WDT_WDOGPERIPHID2              0x00145fe8 /*  */
#define WDT_WDOGPERIPHID3              0x00145fec /*  */
#define WDT_WDOGPCELLID0               0x00145ff0 /*  */
#define WDT_WDOGPCELLID1               0x00145ff4 /*  */
#define WDT_WDOGPCELLID2               0x00145ff8 /*  */
#define WDT_WDOGPCELLID3               0x00145ffc /*  */


/****************************************************************************
 * bcm89530_sys_cfg_DMU
 ***************************************************************************/
#define DMU_DMU_STATUS                 0x00146040 /* DMU status register */
#define DMU_DMU_CLK_SEL                0x00146044 /* DMU Clock Control register */
#define DMU_DMU_CLKOUT_SEL             0x00146048 /* DMU CLKOUT Control register */
#define DMU_DMU_TIMER_ENABLE_SEL       0x0014604c /* Timer enable select register */
#define DMU_DMU_PM                     0x00146050 /* DMU PM control register */
#define DMU_DMU_SW_RST                 0x00146080 /* Software Reset */
#define DMU_DMU_RST_LAST               0x00146084 /* "Captured masked reset cause of last reset, this register is only cleared by L0 resets." */
#define DMU_DMU_RST_RAW                0x00146088 /* Sticky flags for unfiltered error and reset events. */
#define DMU_DMU_RST_ENABLE             0x0014608c /* Reset enables-All bits are active high. */
#define DMU_DMU_INT_ENABLE             0x00146090 /* DMU interrupt enable-All bits are active high. */
#define DMU_DMU_RST_TEST               0x00146094 /* Test resets: All bits active high with self clear (no need for SW to reset) */
#define DMU_DMU_RST_BLK1               0x00146098 /* "Block Reset Register\nThis register provides static control over all reset signals:\n0=Normal mode, 1=RESET" */
#define DMU_DMU_RST_BLK2               0x0014609c /* "Block Reset Register\nThis register provides static control over all reset signals:\n0=Normal mode, 1=RESET" */
#define DMU_DMU_PWD_BLK1               0x001460c0 /* "Block Power Down Register\nThis register provides static control over all reset signals:\n0=Normal mode, 1=POWER DOWN" */
#define DMU_DMU_PWD_BLK2               0x001460c4 /* "Block Power Down Register\nThis register provides static control over all reset signals:\n0=Normal mode, 1=POWER DOWN" */
#define DMU_DMU_PWD_ERR_BLK1           0x001460c8 /* "Block Power Down Error Register \nThis register provides static control over all reset signals:\n0=Normal mode, 1=Power Down Error" */
#define DMU_DMU_PWD_ERR_BLK2           0x001460cc /* "Block Power Down Error Register(Reserved/Unused)\nThis register provides static control over all reset signals:\n0=Normal mode, 1=Power Down Error" */
#define DMU_DMU_PM2                    0x001460f4 /* DMU PM control register 2 */


/****************************************************************************
 * bcm89530_sys_cfg_I2C
 ***************************************************************************/
#define I2C_BSCCS                      0x00147020 /* I2C Control and Status Register */
#define I2C_BSCTIM                     0x00147024 /* I2C Time Register */
#define I2C_BSCDAT                     0x00147028 /* I2C Data Register */
#define I2C_BSCTOUT                    0x0014702c /* I2C Timeout Register */
#define I2C_BSCFCR                     0x0014703c /* I2C FIFO Control Register */
#define I2C_BSCFIFORDOUT               0x00147040 /* I2C FIFO Read Out Register */
#define I2C_BSCIER                     0x00147044 /* I2C FIFO Interrupt Enable Register */
#define I2C_BSCISR                     0x00147048 /* I2C FIFO Interrupt Status Register */
#define I2C_BSCCLKEN                   0x0014704c /* I2C clock enable */


/****************************************************************************
 * bcm89530_sys_cfg_CFG
 ***************************************************************************/
#define CFG_SR                         0x00148000 /* Status register */
#define CFG_CFG_CPUSYS_MISC            0x00148004 /* CPUSYS misc config registers */
#define CFG_TM_0                       0x00148008 /* TM Bits [31:0] */
#define CFG_TM_1                       0x0014800c /* TM Bits [63:32] */
#define CFG_DEBUG_EN                   0x00148010 /* Debug enable register */
#define CFG_PARITY_DISABLE             0x00148020 /* Disables ECC and parity */
#define CFG_SRAB_CMDSTAT               0x0014802c /* Switch Register Access Bridge command status */
#define CFG_SRAB_WDH                   0x00148030 /* "Switch register access ,write data, high order word" */
#define CFG_SRAB_WDL                   0x00148034 /* "Switch register access ,write data, low order word" */
#define CFG_SRAB_RDH                   0x00148038 /* "Switch register access read data, high order word" */
#define CFG_SRAB_RDL                   0x0014803c /* "Switch register access read data, low order word" */
#define CFG_SW_IF                      0x00148040 /* Switch interface and control */
#define CFG_SW_INTR_CLR                0x00148044 /* Switch interrupt clear register */
#define CFG_QSPI_IO_STATUS             0x00148048 /* QSPI IO status register */
#define CFG_QSPI_IO_CONTROL            0x0014804c /* QSPI IO control direct access register */
#define CFG_QSPI_IP_REVID              0x00148050 /* QSPI Revision identifier access register */
#define CFG_SPI_CRC_CONTROL            0x00148054 /* SPI CRC control register */
#define CFG_SPI_CRC_STATUS             0x00148058 /* SPI CRC result status register */
#define CFG_CPU_INTR_RAW               0x0014805c /* VIC raw interrupt register */
#define CFG_CPU_INTR_STAT              0x00148060 /* VIC Status interrupt register */
#define CFG_CPU_INTR_MASK              0x00148064 /* VIC MASK interrupt register */
#define CFG_CPU_INTR_FORCE             0x00148068 /* VIC FORCE interrupt register */
#define CFG_CPU_INTR_CFG               0x0014806c /* PAD Output interrupt configuration register */
#define CFG_SPI_CRC_IDLE_CYCLE_COUNT   0x00148070 /* SPI CRC idle cycle count */
#define CFG_AHB2RDB_TIMEOUT            0x00148074 /* AHB2RDB timeout counter and status */


/****************************************************************************
 * bcm89530_sys_cfg_URT0
 ***************************************************************************/
#define URT0_UARTDR                    0x00149000 /* "Data read or written from the interface. It is 12 bits wide on a read, and 8 on a write. (See PL011 TRM for details)" */
#define URT0_UARTRSR_UARTECR           0x00149004 /* Receive status register (read)/error clear register (write). (See PL011 TRM for details) */
#define URT0_UARTFR                    0x00149018 /* Flag register. (See PL011 TRM for details) */
#define URT0_UARTILPR                  0x00149020 /* "IrDA low-power counter register. (See PL011 TRM for details)" */
#define URT0_UARTIBRD                  0x00149024 /* Integer baud rate divisor register. (See PL011 TRM for details) */
#define URT0_UARTFBRD                  0x00149028 /* "Fractional baud rate divisor register. (See PL011 TRM for details)" */
#define URT0_UARTLCR                   0x0014902c /* "Line control register, HIGH byte. (See PL011 TRM for details)" */
#define URT0_UARTCR                    0x00149030 /* Control register. (See PL011 TRM for details) */
#define URT0_UARTIFLS                  0x00149034 /* "Interrupt FIFO level select register. (See PL011 TRM for details)" */
#define URT0_UARTIMSC                  0x00149038 /* Interrupt mask set/clear. (See PL011 TRM for details) */
#define URT0_UARTRIS                   0x0014903c /* Raw interrupt status. (See PL011 TRM for details) */
#define URT0_UARTMIS                   0x00149040 /* Masked interrupt status. (See PL011 TRM for details) */
#define URT0_UARTICR                   0x00149044 /* Interrupt clear register. (See PL011 TRM for details) */
#define URT0_UARTDMACR                 0x00149048 /* DMA control register. (See PL011 TRM for details) */
#define URT0_UARTPERIPHID0             0x00149fe0 /* "Peripheral identification register bits [7:0]. (See PL011 TRM for details)" */
#define URT0_UARTPERIPHID1             0x00149fe4 /* "Peripheral identification register bits [15:8]. (See PL011 TRM for details)" */
#define URT0_UARTPERIPHID2             0x00149fe8 /* "Peripheral identification register bits [23:16]. (See PL011 TRM for details)" */
#define URT0_UARTPERIPHID3             0x00149fec /* "Peripheral identification register bits [31:24]. (See PL011 TRM for details)" */
#define URT0_UARTPCELLID0              0x00149ff0 /* "PrimeCell identification register bits [7:0]. (See PL011 TRM for details)" */
#define URT0_UARTPCELLID1              0x00149ff4 /* "PrimeCell identification register bits [15:8]. (See PL011 TRM for details)" */
#define URT0_UARTPCELLID2              0x00149ff8 /* "PrimeCell identification register bits [23:16]. (See PL011 TRM for details)" */
#define URT0_UARTPCELLID3              0x00149ffc /* "PrimeCell identification register bits [31:24]. (See PL011 TRM for details)" */


/****************************************************************************
 * bcm89530_sys_cfg_SPI0
 ***************************************************************************/
#define SPI0_SSPCR0                    0x0014a000 /* Control Register 0. (See PL022 TRM for details) */
#define SPI0_SSPCR1                    0x0014a004 /* Control Register 1. (See PL022 TRM for details) */
#define SPI0_SSPDR                     0x0014a008 /* Receive FIFO (read) and transmit FIFO (write) data register. (See PL022 TRM for details) */
#define SPI0_SSPSR                     0x0014a00c /* Status register. (See PL022 TRM for details) */
#define SPI0_SSPCPSR                   0x0014a010 /* Clock prescale register. (See PL022 TRM for details) */
#define SPI0_SSPIMSC                   0x0014a014 /* Interrupt mask set and clear register. (See PL022 TRM for details) */
#define SPI0_SSPRIS                    0x0014a018 /* Raw interrupt status register. (See PL022 TRM for details) */
#define SPI0_SSPMIS                    0x0014a01c /* Masked interrupt status register. (See PL022 TRM for details) */
#define SPI0_SSPICR                    0x0014a020 /* Interrupt clear register. (See PL022 TRM for details) */
#define SPI0_SSPDMACR                  0x0014a024 /* DMA control register. (See PL022 TRM for details) */
#define SPI0_SSPPERIPHID0              0x0014afe0 /* "Peripheral identification register bits [7:0]. (See PL022 TRM for details)" */
#define SPI0_SSPPERIPHID1              0x0014afe4 /* "Peripheral identification register bits [15:8]. (See PL022 TRM for details)" */
#define SPI0_SSPPERIPHID2              0x0014afe8 /* "Peripheral identification register bits [23:16]. (See PL022 TRM for details)" */
#define SPI0_SSPPERIPHID3              0x0014afec /* "Peripheral identification register bits [31:24]. (See PL022 TRM for details)" */
#define SPI0_SSPPCELLID0               0x0014aff0 /* "PrimeCell identification register bits [7:0]. (See PL022 TRM for details)" */
#define SPI0_SSPPCELLID1               0x0014aff4 /* "PrimeCell identification register bits [15:8]. (See PL022 TRM for details)" */
#define SPI0_SSPPCELLID2               0x0014aff8 /* "PrimeCell identification register bits [23:16]. (See PL022 TRM for details)" */
#define SPI0_SSPPCELLID3               0x0014affc /* "PrimeCell identification register bits [31:24]. (See PL022 TRM for details)" */


/****************************************************************************
 * bcm89530_sys_cfg_PWM
 ***************************************************************************/
#define PWM_PWMCTL                     0x0014b000 /* PWM Control Register */
#define PWM_PERIOD_CNT_0               0x0014b004 /* PWM Period Count for Channel0 */
#define PWM_DUTY_CNT_0                 0x0014b008 /* PWM Period Duty for Channel0 */
#define PWM_PERIOD_CNT_1               0x0014b00c /* PWM Period Count for Channel1 */
#define PWM_DUTY_CNT_1                 0x0014b010 /* PWM Period Duty for Channel2 */
#define PWM_PERIOD_CNT_2               0x0014b014 /* PWM Period Count for Channel2 */
#define PWM_DUTY_CNT_2                 0x0014b018 /* PWM Period Duty for Channel2 */
#define PWM_PERIOD_CNT_3               0x0014b01c /* PWM Period Count for Channel3 */
#define PWM_DUTY_CNT_3                 0x0014b020 /* PWM Period Duty for Channel3 */
#define PWM_PRESCALE                   0x0014b024 /* PWM Channel Prescale */


/****************************************************************************
 * bcm89530_sys_cfg_GIO0
 ***************************************************************************/
#define GIO0_GPIO_G0_DIN               0x0014c000 /* GPIO Data in regsiter */
#define GIO0_GPIO_G0_DOUT              0x0014c004 /* GPIO Data out regsiter */
#define GIO0_GPIO_G0_DRV_EN            0x0014c008 /* GPIO driver enable register. */
#define GIO0_GPIO_G0_INT_TYP           0x0014c00c /* GPIO interrupt type register */
#define GIO0_GPIO_G0_INT_DU_EDG        0x0014c010 /* GPIO interrupt dual edge register */
#define GIO0_GPIO_G0_INT_EDG_LVL_SEL   0x0014c014 /* GPIO interrupt edge/level selection register */
#define GIO0_GPIO_G0_INT_MSK           0x0014c018 /* GPIO interrupt mask register */
#define GIO0_GPIO_G0_INT_STS           0x0014c01c /* GPIO interrupt status register */
#define GIO0_GPIO_G0_INT_MSK_STS       0x0014c020 /* GPIO interrupt masked status register */
#define GIO0_GPIO_G0_INT_CLR           0x0014c024 /* GPIO interrupt clear register */
#define GIO0_GPIO_G0_I2C_SEL           0x0014c028 /* GPIO MUX Selection to I2C Register */
#define GIO0_GPIO_G0_INT_POL           0x0014c070 /* GPIO Interrupt Polarity register */
#define GIO0_GPIO_G1_DIN               0x0014c100 /* GPIO Data in regsiter */
#define GIO0_GPIO_G1_DOUT              0x0014c104 /* GPIO Data out regsiter */
#define GIO0_GPIO_G1_DRV_EN            0x0014c108 /* GPIO driver enable register. */
#define GIO0_GPIO_G1_INT_TYP           0x0014c10c /* GPIO interrupt type register */
#define GIO0_GPIO_G1_INT_DU_EDG        0x0014c110 /* GPIO interrupt dual edge register */
#define GIO0_GPIO_G1_INT_EDG_LVL_SEL   0x0014c114 /* GPIO interrupt edge/level selection register */
#define GIO0_GPIO_G1_INT_MSK           0x0014c118 /* GPIO interrupt mask register */
#define GIO0_GPIO_G1_INT_STS           0x0014c11c /* GPIO interrupt status register */
#define GIO0_GPIO_G1_INT_MSK_STS       0x0014c120 /* GPIO interrupt masked status register */
#define GIO0_GPIO_G1_INT_CLR           0x0014c124 /* GPIO interrupt clear register */
#define GIO0_GPIO_G1_PWM_SEL           0x0014c128 /* GPIO MUX Selection to PWM register */
#define GIO0_GPIO_G1_SEC_CFG           0x0014c12c /* GPIO Secure configuration register (Not2Release) */
#define GIO0_GPIO_G1_INIT              0x0014c130 /* GPIO Initial value register (Not2Release) */
#define GIO0_GPIO_G1_PAD_RES           0x0014c134 /* GPIO Pad resister selection register */
#define GIO0_GPIO_G1_PAD_RESIS_EN      0x0014c138 /* GPIO Pad resister enable register */
#define GIO0_GPIO_G1_TST_IN            0x0014c13c /* GPIO Test Input register (Not2Release) */
#define GIO0_GPIO_G1_TST_OUT           0x0014c140 /* GPIO Test Output register (Not2Release) */
#define GIO0_GPIO_G1_TST_IN_EN         0x0014c144 /* GPIO Test Input Enable register (Not2Release) */
#define GIO0_GPIO_G1_PWR_FAIL_TRI_STS  0x0014c150 /* GPIO Powerfail tristated status register (Not2Release) */
#define GIO0_GPIO_G1_PWR_FAIL_TRI_EN   0x0014c154 /* GPIO Powerfail Tristate Enable register (Not2Release) */
#define GIO0_GPIO_G1_HYSTER_EN         0x0014c158 /* GPIO Hysteresis Enable register */
#define GIO0_GPIO_G1_SLEW_CTRL         0x0014c15c /* GPIO Slew Control Register */
#define GIO0_GPIO_G1_DRV_SEL_0         0x0014c160 /* GPIO IO Drive Select 0 Register */
#define GIO0_GPIO_G1_DRV_SEL_1         0x0014c164 /* GPIO IO Drive Select 1 Register */
#define GIO0_GPIO_G1_DRV_SEL_2         0x0014c168 /* GPIO IO Drive Select 2 Register */
#define GIO0_GPIO_G1_AUX_SEL           0x0014c16c /* GPIO Aux01 Select Registers (Not2Release) */
#define GIO0_GPIO_G1_INT_POL           0x0014c170 /* GPIO Interrupt Polarity register */
#define GIO0_FLASH_CS_DIN              0x0014c200 /* Flash Chip Select Data In Register */
#define GIO0_FLASH_CS_DOUT             0x0014c204 /* Flash Chip Select Data Out Register */
#define GIO0_FLASH_CS_OE               0x0014c208 /* Flash Chip Select Data Output Enable Register */
#define GIO0_GPIO_G2_INT_TYP           0x0014c20c /* GPIO interrupt type register */
#define GIO0_GPIO_G2_INT_DU_EDG        0x0014c210 /* GPIO interrupt dual edge register */
#define GIO0_GPIO_G2_INT_EDG_LVL_SEL   0x0014c214 /* GPIO interrupt edge/level selection register */
#define GIO0_GPIO_G2_INT_MSK           0x0014c218 /* GPIO interrupt mask register */
#define GIO0_GPIO_G2_INT_STS           0x0014c21c /* GPIO interrupt status register */
#define GIO0_GPIO_G2_INT_MSK_STS       0x0014c220 /* GPIO interrupt masked status register */
#define GIO0_GPIO_G2_INT_CLR           0x0014c224 /* GPIO interrupt clear register */
#define GIO0_GPIO_G2_FLASH_SEL         0x0014c228 /* GPIO MUX Selection to FLASH register */
#define GIO0_GPIO_G2_INT_POL           0x0014c270 /* GPIO Interrupt Polarity register */


/****************************************************************************
 * bcm89530_sys_cfg_MMI
 ***************************************************************************/
#define MMI_MMI_CTRL                   0x0014d000 /* Eth General Control */
#define MMI_MMI_CMD                    0x0014d004 /* Interrupt Mask */


/****************************************************************************
 * bcm89530_sys_cfg_PKA
 ***************************************************************************/
#define PKA_CONTROL_STATUS             0x0014e000 /* PKA control/status register */
#define PKA_DATA_INPUT                 0x0014e004 /* PKA data input register */
#define PKA_DATA_OUTPUT                0x0014e008 /* PKA data output register */
#define PKA_ACCESS_CONTROL             0x0014e00c /* PKA access control register */
#define PKA_SCA_LFSR_SEED              0x0014e010 /* PKA side-channel-attack prevention LFSR seed register */


/****************************************************************************
 * bcm89530_sys_cfg_RNG
 ***************************************************************************/
#define RNG_CTRL                       0x0014f000 /* RNG Control Register */
#define RNG_STATUS                     0x0014f004 /* RNG Status Register */
#define RNG_DATA0                      0x0014f008 /* Random Number Register */
#define RNG_THRESHOLD                  0x0014f00c /* Random Number Register */
#define RNG_INT_MASK                   0x0014f010 /* Interrupt Disable Register */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_CL45DEV1
 ***************************************************************************/
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1  0x09020000 /* IEEE PMA/PMD CONTROL 1 REGISTER (REG 1.0) */
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1   0x09020002 /* IEEE PMA/PMD STATUS 1 REGISTER  (REG 1.1) */
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID0 0x09020004 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 0 (REG 1.2) */
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1 0x09020006 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 1 (REG 1.3) */
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0  0x0902000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 1.5) */
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1  0x0902000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 1.6) */
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID0 0x0902001c /* PMA/PMD PACKAGE IDENTIFIER (REG 1.14) */
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID1 0x0902001e /* PMA/PMD PACKAGE IDENTIFIER (REG 1.15) */
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP 0x09020e10 /* TimeSync PMA/PMD capability (REG 1.1800) */
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x09020e12 /* Maximum PMA/PMD transmit path data delay, lower (REG 1.1801) */
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x09020e14 /* Maximum PMA/PMD transmit path data delay, upper (REG 1.1802) */
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x09020e16 /* Minimum PMA/PMD transmit path data delay, lower (REG 1.1803) */
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x09020e18 /* Minimum PMA/PMD transmit path data delay, upper (REG 1.1804) */
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x09020e1a /* Maximum PMA/PMD receive path data delay, lower (REG 1.1805) */
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x09020e1c /* Maximum PMA/PMD receive path data delay, upper (REG 1.1806) */
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x09020e1e /* Minimum PMA/PMD receive path data delay, lower (REG 1.1807) */
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x09020e20 /* Minimum PMA/PMD receive path data delay, upper (REG 1.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_CL45DEV3
 ***************************************************************************/
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1  0x09060000 /* IEEE PCS CONTROL 1 REGISTER (REG 3.0) */
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1   0x09060002 /* IEEE PCS STATUS 1 REGISTER  (REG 3.1) */
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID0 0x09060004 /* IEEE PCS DEVICE IDENTIFIER PART 0 (REG 3.2) */
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1 0x09060006 /* IEEE PCS DEVICE IDENTIFIER PART 1 (REG 3.3) */
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0  0x0906000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 3.5) */
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1  0x0906000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 3.6) */
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID0 0x0906001c /* PCS PACKAGE IDENTIFIER (REG 3.14) */
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID1 0x0906001e /* PCS PACKAGE IDENTIFIER (REG 3.15) */
#define BRPHY0_CL45DEV3_PCS_EEE_CAP    0x09060028 /* PCS_EEE_CAP(REG 3.20) */
#define BRPHY0_CL45DEV3_PCS_EEE_WAKE_ERR_CNT 0x0906002c /* PCS_EEE_Wake_Err_Cnt(REG 3.22) */
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP 0x09060e10 /* TimeSync PCS capability (REG 3.1800) */
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x09060e12 /* Maximum PCS transmit path data delay, lower (REG 3.1801) */
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x09060e14 /* Maximum PCS transmit path data delay, upper (REG 3.1802) */
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x09060e16 /* Minimum PCS transmit path data delay, lower (REG 3.1803) */
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x09060e18 /* Minimum PCS transmit path data delay, upper (REG 3.1804) */
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x09060e1a /* Maximum PCS receive path data delay, lower (REG 3.1805) */
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x09060e1c /* Maximum PCS receive path data delay, upper (REG 3.1806) */
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x09060e1e /* Minimum PCS receive path data delay, lower (REG 3.1807) */
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x09060e20 /* Minimum PCS receive path data delay, upper (REG 3.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_CL45DEV7
 ***************************************************************************/
#define BRPHY0_CL45DEV7_AN_CTRL        0x090e0000 /* Auto Neg Extended Next Page Control     (0x0000) (REG 7.0) */
#define BRPHY0_CL45DEV7_AN_STAT        0x090e0002 /* AN Status (0x0001) (REG 7.1) */
#define BRPHY0_CL45DEV7_AN_DEV_ID_LSB  0x090e0004 /* Auto Neg Device Identifier Lower 16 bit (0x0002) (REG 7.2) */
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB  0x090e0006 /* Auto Neg Device Identifier Upper 16 bit (0x0003) (REG 7.3) */
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB 0x090e000a /* Auto Neg Device In Package Lower 16 bit (0x0005) (REG 7.5) */
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB 0x090e000c /* Auto Neg Device In Package Upper 16 bit (0x0006) (REG 7.6) */
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_LSB 0x090e001c /* Auto Neg Package ID Lower 16 bit(0x000e) (REG 7.14) */
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_MSB 0x090e001e /* Auto Neg Package ID Upper 16 bit(0x000f) (REG 7.15) */
#define BRPHY0_CL45DEV7_AN_AD          0x090e0020 /* Auto Neg AD(0x0010) (REG 7.16) */
#define BRPHY0_CL45DEV7_AN_LPA         0x090e0026 /* AN LP base page ability (0x0013) (REG 7.19) */
#define BRPHY0_CL45DEV7_AN_XNPA        0x090e002c /* AN XNP transmit A (0x0016) (REG 7.22) */
#define BRPHY0_CL45DEV7_AN_XNPB        0x090e002e /* AN XNP transmit B (0x0017) (REG 7.23) */
#define BRPHY0_CL45DEV7_AN_XNPC        0x090e0030 /* AN XNP transmit C (0x0018) (REG 7.24) */
#define BRPHY0_CL45DEV7_LP_XNPA        0x090e0032 /* AN LP XNP ability A (0x0019) (REG 7.25) */
#define BRPHY0_CL45DEV7_LP_XNPB        0x090e0034 /* AN LP XNP ability B (0x001a) (REG 7.26) */
#define BRPHY0_CL45DEV7_LP_XNPC        0x090e0036 /* AN LP XNP ability C (0x001b) (REG 7.27) */
#define BRPHY0_CL45DEV7_TENG_AN_CTRL   0x090e0040 /* 10G Base-T AN Control Register (0x0020) (REG 7.32) */
#define BRPHY0_CL45DEV7_TENG_AN_STAT   0x090e0042 /* 10G Base-T AN Status Register  (0x0021) (REG 7.33) */
#define BRPHY0_CL45DEV7_EEE_ADV        0x090e0078 /* EEE Advertisement (0x003C) (REG 7.60 ???) */
#define BRPHY0_CL45DEV7_EEE_LP_ADV     0x090e007a /* EEE Link Partner Advertisement (0x003D) (REG 7.61 ???) */
#define BRPHY0_CL45DEV7_EEE_MODE_CTL   0x090e007c /* EEE Mode Control (0x003E) (REG 7.62 ???) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_CL45VEN
 ***************************************************************************/
#define BRPHY0_CL45VEN_FORCE_LINK      0x090f0000 /* Force Link Register */
#define BRPHY0_CL45VEN_SELECTIVE_RESET 0x090f0002 /* Selective Reset Register */
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS 0x090f0004 /* Test State Machine For Extended Next Pages Register --mvadkert */
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS 0x090f0006 /* Test State Machine For Next Pages Register --mvadkert */
#define BRPHY0_CL45VEN_AN_MAN_TEST     0x090f0032 /* Auto Negotiation Manual Test Register */
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A 0x090f0034 /* Auto Negotiation Manual Link Partners Abilities Register A */
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B 0x090f0036 /* Auto Negotiation Manual Link Partners Abilities Register B */
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_A 0x090f0038 /* Link Partner Next Page */
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_B 0x090f003a /* Link Partner Next Page (cont.) */
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_C 0x090f003c /* Link Partner Next Page (cont.) */
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_D 0x090f003e /* Link Partner Next Page (cont.) */
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_E 0x090f0040 /* Link Partner Next Page (cont.) */
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_F 0x090f0042 /* Link Partner Next Page (cont.) */
#define BRPHY0_CL45VEN_EPON_CTRL_REG   0x090f0046 /* EPON mode control register */
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A 0x090f0060 /* EEE Test Control Register A eee_test_control_bus[15:0] */
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B 0x090f0062 /* EEE Test Control Register B eee_test_control_bus[31:16] */
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C 0x090f0064 /* EEE Test Control Register C eee_test_control_bus[47:32] */
#define BRPHY0_CL45VEN_EEE_SPARE_1     0x090f0076 /* EEE Spare Register 1 */
#define BRPHY0_CL45VEN_EEE_SPARE_2     0x090f0078 /* EEE Spare Register 2 */
#define BRPHY0_CL45VEN_EEE_CONTROL     0x090f007a /* EEE Control Register */
#define BRPHY0_CL45VEN_EEE_RES_STAT    0x090f007c /* EEE Resolution Status Register */
#define BRPHY0_CL45VEN_LPI_MODE_CNTR   0x090f007e /* LPI Mode Counter Register */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_A 0x090f0080 /* Local Device Message 5 */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_B 0x090f0082 /* Local Device Message 5 cont. */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_C 0x090f0084 /* Local Device Message 5 cont. */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_D 0x090f0086 /* Local Device Message 5 cont. */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A 0x090f0088 /* Link Partner Message 5 */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B 0x090f008a /* Link Partner Message 5 cont. */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C 0x090f008c /* Link Partner Message 5 cont. */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D 0x090f008e /* Link Partner Message 5 cont. */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_A 0x090f0090 /* Local Device Message 6 */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B 0x090f0092 /* Local Device Message 6 cont. */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C 0x090f0094 /* Local Device Message 6 cont. */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_D 0x090f0096 /* Local Device Message 6 cont. */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A 0x090f0098 /* Link Partner Message 6 */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B 0x090f009a /* Link Partner Message 6 cont. */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C 0x090f009c /* Link Partner Message 6 cont. */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D 0x090f009e /* Link Partner Message 6 cont. */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_GPHY_CORE
 ***************************************************************************/
#define BRPHY0_GPHY_CORE_BASE10        0x090f2000 /* PHY_Extended_ctl_Register */
#define BRPHY0_GPHY_CORE_BASE11        0x090f2002 /* PHY_Extended_Status_Register (copper side only) */
#define BRPHY0_GPHY_CORE_BASE12        0x090f2004 /* Receive_Error_Cntr_Register */
#define BRPHY0_GPHY_CORE_BASE13        0x090f2006 /* False_Carrier_Sense_Cntr_Register */
#define BRPHY0_GPHY_CORE_BASE14        0x090f2008 /* Local_Remote_Receiver_NOT_OK_Cntrs_Register */
#define BRPHY0_GPHY_CORE_EXP45         0x090f200a /* Pattern Generator Control Register */
#define BRPHY0_GPHY_CORE_EXP46         0x090f200b /* Pattern Generator Status Register */
#define BRPHY0_GPHY_CORE_BASE19        0x090f2012 /* Auxiliary Status Summary (copper side only) */
#define BRPHY0_GPHY_CORE_BASE1A        0x090f2014 /* Interrupt Status Register (copper side only) */
#define BRPHY0_GPHY_CORE_BASE1B        0x090f2016 /* Interrupt Mask Register */
#define BRPHY0_GPHY_CORE_BASE1D_SHD    0x090f2018 /* HCD Status Register */
#define BRPHY0_GPHY_CORE_BASE1D        0x090f201a /* Master/Slave Seed Register */
#define BRPHY0_GPHY_CORE_BASE1E        0x090f201c /* Test1_Register */
#define BRPHY0_GPHY_CORE_BASE1F        0x090f201e /* Test2_Register */
#define BRPHY0_GPHY_CORE_SHD1C_00      0x090f2020 /* Cabletron LED Register (Shadow Register Selector = "00h") */
#define BRPHY0_GPHY_CORE_SHD1C_01      0x090f2022 /* TVCO Selection Register (Shadow Register Selector = "01h") */
#define BRPHY0_GPHY_CORE_SHD1C_02      0x090f2024 /* reserved Control 1 Register (Shadow Register Selector = "02h") */
#define BRPHY0_GPHY_CORE_SHD1C_03      0x090f2026 /* Clock Alignment Control Regsiter (Shadow Register Selector = "03h") */
#define BRPHY0_GPHY_CORE_SHD1C_04      0x090f2028 /* reserved Control 2 Register (Shadow Register Selector = "04h") */
#define BRPHY0_GPHY_CORE_SHD1C_05      0x090f202a /* reserved Control 3 Register (Shadow Register Selector = "05h") */
#define BRPHY0_GPHY_CORE_SHD1C_06      0x090f202c /* Tdr Control 1 Register (Shadow Register Selector = "06h") */
#define BRPHY0_GPHY_CORE_SHD1C_07      0x090f202e /* Tdr Control 2 Register (Shadow Register Selector = "07h") */
#define BRPHY0_GPHY_CORE_SHD1C_08      0x090f2030 /* Led Status Register (Shadow Register Selector = "08h") */
#define BRPHY0_GPHY_CORE_SHD1C_09      0x090f2032 /* Led Control Register (Shadow Register Selector = "09h") */
#define BRPHY0_GPHY_CORE_SHD1C_0A      0x090f2034 /* Auto-Power Down Register (Shadow Register Selector = "0ah") */
#define BRPHY0_GPHY_CORE_SHD1C_0B      0x090f2036 /* reserved Control 4 Register (Shadow Register Selector = "0bh") */
#define BRPHY0_GPHY_CORE_SHD1C_0D      0x090f203a /* LED Selector 1 Register (Shadow Register Selector = "0dh") */
#define BRPHY0_GPHY_CORE_SHD1C_0E      0x090f203c /* LED Selector 2 Register (Shadow Register Selector = "0eh") */
#define BRPHY0_GPHY_CORE_SHD1C_0F      0x090f203e /* LED GPIO Control/Status Register (Shadow Register Selector = "0fh") */
#define BRPHY0_GPHY_CORE_SHD1C_10      0x090f2040 /* Cisco Enhanced Linkstatus Mode Control Register (Shadow Register Selector = "10h") */
#define BRPHY0_GPHY_CORE_SHD1C_1F      0x090f2042 /* Mode Control Register (Shadow Register Selector = "1fh") */
#define BRPHY0_GPHY_CORE_SHD18_000     0x090f2050 /* Auxiliary Control Register (Shadow Register Selector = "000") */
#define BRPHY0_GPHY_CORE_SHD18_001     0x090f2052 /* 10 Base-T Register (Shadow Register Selector = "001") */
#define BRPHY0_GPHY_CORE_SHD18_010     0x090f2054 /* Power/MII Control Register (Shadow Register Selector = "010") */
#define BRPHY0_GPHY_CORE_SHD18_011     0x090f2056 /* IP Phone Register  (Shadow Register Selector = "011") */
#define BRPHY0_GPHY_CORE_SHD18_100     0x090f2058 /* Misc Test Register  1 (Shadow Register Selector = "100") */
#define BRPHY0_GPHY_CORE_SHD18_101     0x090f205a /* Misc Test Register  2 (Shadow Register Selector = "101") */
#define BRPHY0_GPHY_CORE_SHD18_110     0x090f205c /* Manual IP Phone Seed Register (Shadow Register Selector = "110") */
#define BRPHY0_GPHY_CORE_SHD18_111     0x090f205e /* Miscellanous Control Register (Shadow Register Selector = "111") */
#define BRPHY0_GPHY_CORE_EXP00         0x090f2060 /* Transmit Packet Counter */
#define BRPHY0_GPHY_CORE_EXP01         0x090f2062 /* Expansion Interrupt Status */
#define BRPHY0_GPHY_CORE_EXP02         0x090f2064 /* Expansion Interrupt Mask */
#define BRPHY0_GPHY_CORE_EXP03         0x090f2066 /* Spare Registers */
#define BRPHY0_GPHY_CORE_EXP04         0x090f2068 /* Bicolor LED Selectors */
#define BRPHY0_GPHY_CORE_EXP05         0x090f206a /* Bicolor LED Flash Rate Controls */
#define BRPHY0_GPHY_CORE_EXP06         0x090f206c /* Bicolor LED Programmable Blink Controls */
#define BRPHY0_GPHY_CORE_EXP07         0x090f206e /* Far End Fault */
#define BRPHY0_GPHY_CORE_EXP08         0x090f2070 /* 10BT Controls */
#define BRPHY0_GPHY_CORE_EXP09         0x090f2072 /* AMRR Controls */
#define BRPHY0_GPHY_CORE_EXP0A         0x090f2074 /* DAC TEMPLATE Controls */
#define BRPHY0_GPHY_CORE_EXP0B         0x090f2076 /* External Status */
#define BRPHY0_GPHY_CORE_EXP0C         0x090f2078 /* Spare Registers */
#define BRPHY0_GPHY_CORE_EXP30         0x090f2080 /* Late Collision Counters Status Register */
#define BRPHY0_GPHY_CORE_EXP31         0x090f2082 /* Late Collision Counter [64:95] */
#define BRPHY0_GPHY_CORE_EXP32         0x090f2084 /* Late Collision Counter [96:127] */
#define BRPHY0_GPHY_CORE_EXP33         0x090f2086 /* Late Collision Counter [128:191] */
#define BRPHY0_GPHY_CORE_EXP34         0x090f2088 /* Late Collision Counter [192:319] */
#define BRPHY0_GPHY_CORE_EXP35         0x090f208a /* Late Collision Counter Threshold Register */
#define BRPHY0_GPHY_CORE_EXP36         0x090f208c /* Clock PPM Detection between Recovery and Transmit Clocks */
#define BRPHY0_GPHY_CORE_EXP37         0x090f208e /* Clock PPM Detection between GTX_CLK and Transmit Clocks */
#define BRPHY0_GPHY_CORE_EXP38         0x090f2090 /* IP PHONE Cable Length Status Register */
#define BRPHY0_GPHY_CORE_EXP42         0x090f20a2 /* Operating Mode Status */
#define BRPHY0_GPHY_CORE_EXP5F         0x090f20be /* PLL Frequency Offset Testmode Control */
#define BRPHY0_GPHY_CORE_EXP70         0x090f20e0 /* SOFT-RESET */
#define BRPHY0_GPHY_CORE_EXP71         0x090f20e2 /* Serial LED Control 1 */
#define BRPHY0_GPHY_CORE_EXP72         0x090f20e4 /* Serial LED Control 2 */
#define BRPHY0_GPHY_CORE_EXP73         0x090f20e6 /* LED Gating 2 (Used for dual-media applications) */
#define BRPHY0_GPHY_CORE_EXP74         0x090f20e8 /* LED Programmable Current Mode Control */
#define BRPHY0_GPHY_CORE_EXP75         0x090f20ea /* CED LED Error Mask */
#define BRPHY0_GPHY_CORE_EXP78         0x090f20f0 /* Misc Extended Control */
#define BRPHY0_GPHY_CORE_EXP7B         0x090f20f6 /* I2C Control */
#define BRPHY0_GPHY_CORE_EXP7C         0x090f20f8 /* I2C Status */
#define BRPHY0_GPHY_CORE_EXP7F         0x090f20fe /* External MACSec Interface Control */
#define BRPHY0_GPHY_CORE_ALIAS_18      0x090f2100 /* Alias to MII Reg 18 */
#define BRPHY0_GPHY_CORE_ALIAS_19      0x090f2102 /* Alias to MII Reg 19 */
#define BRPHY0_GPHY_CORE_ALIAS_1A      0x090f2104 /* Alias to MII Reg 1a */
#define BRPHY0_GPHY_CORE_ALIAS_1B      0x090f2106 /* Alias to MII Reg 1b */
#define BRPHY0_GPHY_CORE_ALIAS_1C      0x090f2108 /* Alias to MII Reg 1c */
#define BRPHY0_GPHY_CORE_ALIAS_1D      0x090f210a /* Alias to MII Reg 1d */
#define BRPHY0_GPHY_CORE_REG_MAP_CTL   0x090f210e /* MII Registers 10-1D mapping control */
#define BRPHY0_GPHY_CORE_EXP98         0x090f2130 /* First Slice of Quad-GPHY only): CAL-BIAS Status */
#define BRPHY0_GPHY_CORE_EXP9C         0x090f2138 /* SMII Control */
#define BRPHY0_GPHY_CORE_BT_LINK_FIX   0x090f214a /* 10BT LINK FIX Register */
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG 0x090f214c /* SyncE+ Debug */
#define BRPHY0_GPHY_CORE_SYNCE_PLUS    0x090f214e /* SyncE+ Status and Control */
#define BRPHY0_GPHY_CORE_EXPA8         0x090f2150 /* ADAPTIVE BIAS CONTROL */
#define BRPHY0_GPHY_CORE_EXPA9         0x090f2152 /* spare register */
#define BRPHY0_GPHY_CORE_EXPAA         0x090f2154 /* EEE Statistic timer 12hours lpi */
#define BRPHY0_GPHY_CORE_EXPAB         0x090f2156 /* EEE Statistic timer 12hours local */
#define BRPHY0_GPHY_CORE_EXPAC         0x090f2158 /* EEE Statistic loc lpi req 0_to_1 counter */
#define BRPHY0_GPHY_CORE_EXPAD         0x090f215a /* EEE Statistic rem lpi_req 0_to_1 counter */
#define BRPHY0_GPHY_CORE_EXPAE         0x090f215c /* spare register */
#define BRPHY0_GPHY_CORE_EXPAF         0x090f215e /* EEE Statistic counters ctrl/status */
#define BRPHY0_GPHY_CORE_EXPB0         0x090f2160 /* Bias Control 0 */
#define BRPHY0_GPHY_CORE_EXPB1         0x090f2162 /* Bias Control 1 */
#define BRPHY0_GPHY_CORE_EXPB2         0x090f2164 /* Bias Control 2 */
#define BRPHY0_GPHY_CORE_EXPE3         0x090f2166 /* TX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY0_GPHY_CORE_EXPE4         0x090f2168 /* TX PCS Delay 10BT (copper side) */
#define BRPHY0_GPHY_CORE_EXPE5         0x090f216a /* TX PCS Delay (fiber side) */
#define BRPHY0_GPHY_CORE_EXPE6         0x090f216c /* RX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY0_GPHY_CORE_EXPE7         0x090f216e /* RX PCS Delay 10BT (copper side) */
#define BRPHY0_GPHY_CORE_EXPE8         0x090f2170 /* RX PCS Delay (fiber side) */
#define BRPHY0_GPHY_CORE_EXPE9         0x090f2172 /* P1588 TX/RX Cycle Delay */
#define BRPHY0_GPHY_CORE_EXPE0         0x090f2174 /* TX PMA/PMD Delay (copper side) */
#define BRPHY0_GPHY_CORE_EXPE1         0x090f2176 /* TX PMA/PMD Delay (fiber side) */
#define BRPHY0_GPHY_CORE_EXPE2         0x090f2178 /* RX PMA/PMD Delay (copper side) */
#define BRPHY0_GPHY_CORE_EXPEA         0x090f217a /* TX/RX Adjustable Cycle Delay */
#define BRPHY0_GPHY_CORE_LED_PRA_MODE  0x090f2180 /* LED Proportional Rate Activity Control */
#define BRPHY0_GPHY_CORE_FIFO_CTL      0x090f2182 /* FIFO Control Register */
#define BRPHY0_GPHY_CORE_EXPD8         0x090f21b0 /* Halting agc/enc ctrl reg */
#define BRPHY0_GPHY_CORE_EXPF0         0x090f21e0 /* RGMII IBS Control */
#define BRPHY0_GPHY_CORE_EXPF5         0x090f21ea /* Time Sync */
#define BRPHY0_GPHY_CORE_EXPF6         0x090f21ec /* Analog Power Control Status */
#define BRPHY0_GPHY_CORE_EXPF7         0x090f21ee /* Auto-power Down Control Status */
#define BRPHY0_GPHY_CORE_EXPF8         0x090f21f0 /* Trim Settings from Fuse & to Bias Block */
#define BRPHY0_GPHY_CORE_EXPF9         0x090f21f2 /* reserved Register Bits */
#define BRPHY0_GPHY_CORE_EXPFA         0x090f21f4 /* Hidden Identifier */
#define BRPHY0_GPHY_CORE_EXPFB         0x090f21f6 /* TDR Override Values */
#define BRPHY0_GPHY_CORE_EXPFC         0x090f21f8 /*  */
#define BRPHY0_GPHY_CORE_EXPFD         0x090f21fa /* Clock gating control override value */
#define BRPHY0_GPHY_CORE_EXPFE         0x090f21fc /* Clock gating control override enable */
#define BRPHY0_GPHY_CORE_EXPFF         0x090f21fe /* Analog power control override */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_DSP_TAP
 ***************************************************************************/
#define BRPHY0_DSP_TAP_TAP0_C0         0x090f2200 /* AGC Control/Status Register A (x4) */
#define BRPHY0_DSP_TAP_TAP0_C1         0x090f2202 /* AGC Control/Status Register A (x4) */
#define BRPHY0_DSP_TAP_TAP0_C2         0x090f2204 /* AGC Control/Status Register A (x4) */
#define BRPHY0_DSP_TAP_TAP0_C3         0x090f2206 /* AGC Control/Status Register A (x4) */
#define BRPHY0_DSP_TAP_TAP1            0x090f2208 /* IPRF Control register (x1) */
#define BRPHY0_DSP_TAP_TAP2_C0         0x090f2210 /* MSE Status Register (x4) */
#define BRPHY0_DSP_TAP_TAP2_C1         0x090f2212 /* MSE Status Register (x4) */
#define BRPHY0_DSP_TAP_TAP2_C2         0x090f2214 /* MSE Status Register (x4) */
#define BRPHY0_DSP_TAP_TAP2_C3         0x090f2216 /* MSE Status Register (x4) */
#define BRPHY0_DSP_TAP_TAP3_C0         0x090f2218 /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY0_DSP_TAP_TAP3_C1         0x090f221a /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY0_DSP_TAP_TAP3_C2         0x090f221c /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY0_DSP_TAP_TAP3_C3         0x090f221e /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY0_DSP_TAP_TAP4_C0         0x090f2220 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY0_DSP_TAP_TAP4_C1         0x090f2222 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY0_DSP_TAP_TAP4_C2         0x090f2224 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY0_DSP_TAP_TAP4_C3         0x090f2226 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY0_DSP_TAP_TAP5_C0         0x090f2228 /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY0_DSP_TAP_TAP5_C1         0x090f222a /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY0_DSP_TAP_TAP5_C2         0x090f222c /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY0_DSP_TAP_TAP5_C3         0x090f222e /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY0_DSP_TAP_TAP6            0x090f2230 /* CFC Deadman Disable */
#define BRPHY0_DSP_TAP_TAP7_C0         0x090f2238 /* BIST TEST 0 */
#define BRPHY0_DSP_TAP_TAP7_C1         0x090f223a /* BIST TEST 1 */
#define BRPHY0_DSP_TAP_TAP7_C2         0x090f223c /* BIST TEST 2 */
#define BRPHY0_DSP_TAP_TAP8_C0         0x090f2240 /* ABIST TEST 0 */
#define BRPHY0_DSP_TAP_TAP8_C1         0x090f2242 /* ABIST TEST 1 */
#define BRPHY0_DSP_TAP_TAP8_C2         0x090f2244 /* ABIST TEST 2 */
#define BRPHY0_DSP_TAP_TAP8_C3         0x090f2246 /* BR HPF Control */
#define BRPHY0_DSP_TAP_TAP9            0x090f2248 /* Frequency Control/Status Register LSBs (x1) */
#define BRPHY0_DSP_TAP_TAP10           0x090f224a /* PLL Bandwidth Control/Status and Path Metric Reset Register (x1) */
#define BRPHY0_DSP_TAP_TAP11           0x090f224c /* PLL RCLK and TCLK Offset Freeze Register (x1) */
#define BRPHY0_DSP_TAP_TAP12_C0        0x090f2250 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY0_DSP_TAP_TAP12_C1        0x090f2252 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY0_DSP_TAP_TAP12_C2        0x090f2254 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY0_DSP_TAP_TAP12_C3        0x090f2256 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY0_DSP_TAP_TAP13           0x090f2258 /* HPF Bandwidth Control and Disable ADC LSBs (x1) */
#define BRPHY0_DSP_TAP_TAP14           0x090f225a /* MSE Threshold Register  #1 (x1) */
#define BRPHY0_DSP_TAP_TAP15           0x090f225c /* MSE Threshold Register #2 (x1) */
#define BRPHY0_DSP_TAP_TAP16_C0        0x090f2260 /* Logic Analyzer trigger delay (x1) */
#define BRPHY0_DSP_TAP_TAP16_C1        0x090f2262 /* BIST CRC Monitor (x4) */
#define BRPHY0_DSP_TAP_TAP16_C2        0x090f2264 /* BIST CRC Monitor (x4) */
#define BRPHY0_DSP_TAP_TAP16_C3        0x090f2266 /* BIST CRC Monitor (x4) */
#define BRPHY0_DSP_TAP_TAP17_C0        0x090f2268 /* Testmode testvalue (aliased with logic analyzer state selects) */
#define BRPHY0_DSP_TAP_TAP17_C1        0x090f226a /* Testmode and logic analyzer controls #1 */
#define BRPHY0_DSP_TAP_TAP17_C2        0x090f226c /* Logic analyzer controls #2 */
#define BRPHY0_DSP_TAP_TAP17_C3        0x090f226e /* Testmode and logic analyzer controls #3 */
#define BRPHY0_DSP_TAP_TAP18_C0        0x090f2270 /* Peak Noise detector (x4) */
#define BRPHY0_DSP_TAP_TAP18_C1        0x090f2272 /* Peak Noise detector (x4) */
#define BRPHY0_DSP_TAP_TAP18_C2        0x090f2274 /* Peak Noise detector (x4) */
#define BRPHY0_DSP_TAP_TAP18_C3        0x090f2276 /* Peak Noise detector (x4) */
#define BRPHY0_DSP_TAP_TAP20           0x090f2278 /* Echo Minimum Length and LMS/FIR delay adjustments (x1) */
#define BRPHY0_DSP_TAP_TAP21           0x090f227a /* Phy Control Monitors #1 (x1) */
#define BRPHY0_DSP_TAP_TAP22           0x090f227c /* Phy Control Monitors #2 (x1) */
#define BRPHY0_DSP_TAP_TAP23           0x090f227e /* Phy Control Monitors #3 (x1) */
#define BRPHY0_DSP_TAP_TAP24           0x090f2280 /* Phy Control Output Overrides #1 (x1) */
#define BRPHY0_DSP_TAP_TAP25           0x090f2282 /* Phy Control Output Overrides #2 (x1) */
#define BRPHY0_DSP_TAP_TAP26           0x090f2284 /* Phy Control Input Overrides #1 (x1) */
#define BRPHY0_DSP_TAP_TAP27           0x090f2286 /* Phy Control Input Overrides #2 (x1) */
#define BRPHY0_DSP_TAP_TAP28           0x090f2288 /* Phy Control Output Overrides #3 (x1) */
#define BRPHY0_DSP_TAP_TAP29           0x090f228a /* Phy Control Force State/Timers/Alternate Behaviour Register #1 (x1) */
#define BRPHY0_DSP_TAP_TAP30           0x090f228c /* Phy Control Force State/Timers/Alternate Behaviour Register #2 (x1) */
#define BRPHY0_DSP_TAP_TAP31_C0        0x090f2290 /* Channel Swap Override */
#define BRPHY0_DSP_TAP_TAP32_C0        0x090f2298 /* Transmit Testmode Sync Generation (x1) */
#define BRPHY0_DSP_TAP_FDFE_OV_RD      0x090f229a /* FDFE Override/Read Control Register */
#define BRPHY0_DSP_TAP_FDFE_COEFF      0x090f229c /* FDFE Coefficient Read Back Register */
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD 0x090f229e /* FDFE Beta Threshold Control */
#define BRPHY0_DSP_TAP_TAP33_C0        0x090f22a0 /* eee dsp test */
#define BRPHY0_DSP_TAP_TAP33_C1        0x090f22a2 /* eee sigdet */
#define BRPHY0_DSP_TAP_TAP33_C2        0x090f22a4 /* eee_lpi_timers */
#define BRPHY0_DSP_TAP_TAP33_C3        0x090f22a6 /* spare register */
#define BRPHY0_DSP_TAP_TAP34_C0        0x090f22a8 /* eee frequency control */
#define BRPHY0_DSP_TAP_TAP34_C1        0x090f22aa /* eee Gigabit Mode BW control */
#define BRPHY0_DSP_TAP_TAP34_C2        0x090f22ac /* eee 100TX Mode BW control */
#define BRPHY0_DSP_TAP_TAP34_C3        0x090f22ae /* phasectl TPO monitor */
#define BRPHY0_DSP_TAP_TAP35_C0        0x090f22b0 /* eee 100Base-tx timer control 1 */
#define BRPHY0_DSP_TAP_TAP35_C1        0x090f22b2 /* eee 100Base-tx timer control 2 */
#define BRPHY0_DSP_TAP_TAP35_C2        0x090f22b4 /* eee 100Base-tx timer misc control */
#define BRPHY0_DSP_TAP_TAP35_C3        0x090f22b6 /* pcs_lpi_test */
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0  0x090f22b8 /* Filter Freeze/Disable per channel Control */
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1  0x090f22ba /* Filter Freeze/Disable per channel Control */
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2  0x090f22bc /* Filter Freeze/Disable per channel Control */
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3  0x090f22be /* Filter Freeze/Disable per channel Control */
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0 0x090f22c0 /* FFEX Freeze/Disable per channel Control */
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1 0x090f22c2 /* FFEX Freeze/Disable per channel Control */
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2 0x090f22c4 /* FFEX Freeze/Disable per channel Control */
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3 0x090f22c6 /* FFEX Freeze/Disable per channel Control */
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL 0x090f22c8 /* EMI Datapath Control */
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2 0x090f22ca /* EMI Datapath Control2 */
#define BRPHY0_DSP_TAP_FFEX_CTL        0x090f22cc /* FFE X-tap Control */
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0 0x090f22ce /* Phycontrol Breakpoint Control 0 */
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1 0x090f22d0 /* Phycontrol Breakpoint Control 1 */
#define BRPHY0_DSP_TAP_FILTER_ADDR     0x090f2360 /* DSP Coefficient Address Register */
#define BRPHY0_DSP_TAP_FILTER_CTL      0x090f2362 /* DSP Control Register */
#define BRPHY0_DSP_TAP_FILTER_DATA     0x090f2364 /* DSP Coefficient Read/Write Port */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_PLL_CTRL
 ***************************************************************************/
#define BRPHY0_PLL_CTRL_PLLCTRL_0      0x090f2390 /* Analog pll control 0 */
#define BRPHY0_PLL_CTRL_PLLCTRL_1      0x090f2392 /* Analog pll control 1 */
#define BRPHY0_PLL_CTRL_PLLCTRL_2      0x090f2394 /* Analog pll control 2 */
#define BRPHY0_PLL_CTRL_PLLCTRL_3      0x090f2396 /* Analog pll control 3 */
#define BRPHY0_PLL_CTRL_PLLCTRL_4      0x090f2398 /* Analog pll control 4 */
#define BRPHY0_PLL_CTRL_PLLCTRL_5      0x090f239a /* Analog pll control 5 */
#define BRPHY0_PLL_CTRL_PLLCTRL_6      0x090f239c /* Analog pll control 6 */
#define BRPHY0_PLL_CTRL_PLL_STATUS_0   0x090f23a0 /* Analog PLL Status 0 */
#define BRPHY0_PLL_CTRL_PLL_STATUS_1   0x090f23a2 /* Analog PLL Status 1 */
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS 0x090f23a4 /* AFE Signal detect */
#define BRPHY0_PLL_CTRL_PLLCTRL_7      0x090f23a6 /* Analog pll control 7 */
#define BRPHY0_PLL_CTRL_PLLCTRL_8      0x090f23a8 /* Analog pll control 8 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_AFE_CTRL
 ***************************************************************************/
#define BRPHY0_AFE_CTRL_RXCONFIG_0     0x090f23c0 /* RXCONFIG 15:0 */
#define BRPHY0_AFE_CTRL_RXCONFIG_1     0x090f23c2 /* RXCONFIG 31:16 */
#define BRPHY0_AFE_CTRL_RXCONFIG_2     0x090f23c4 /* RXCONFIG 47:32 */
#define BRPHY0_AFE_CTRL_RXCONFIG_3     0x090f23c6 /* RXCONFIG 63:48 */
#define BRPHY0_AFE_CTRL_RXCONFIG_4     0x090f23c8 /* RXCONFIG 79:64 */
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP   0x090f23ca /* RXCONFIG 86:80 and LP tuning */
#define BRPHY0_AFE_CTRL_TX_CONFIG_0    0x090f23cc /* TXCONFIG 15:0 */
#define BRPHY0_AFE_CTRL_TX_CONFIG_1    0x090f23ce /* TXCONFIG 31:16 */
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_0   0x090f23d0 /* VDAC CURRENT Control 15:0 */
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_1   0x090f23d2 /* VDAC CURRENT Control 31:16 */
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_2   0x090f23d4 /* VDAC CURRENT Control 51:36 */
#define BRPHY0_AFE_CTRL_VDAC_OTHERS_0  0x090f23d6 /* VDAC CURRENT 35:32 and others */
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS 0x090f23d8 /* HPF trim and reserved bits */
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_0 0x090f23da /* TXCONFIG 15:0 */
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_1 0x090f23dc /* TXCONFIG 15:0 */
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_2 0x090f23de /* TXCONFIG 15:0 */
#define BRPHY0_AFE_CTRL_TEMPSEN_OTHERS 0x090f23e0 /* TEMPSEN_OTHERS 15:0 */
#define BRPHY0_AFE_CTRL_FUTURE_RSV     0x090f23e2 /* FUTURE_RSV 15:0 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_ECD_CTRL
 ***************************************************************************/
#define BRPHY0_ECD_CTRL_EXPC0          0x090f2540 /* ECD Control and Status */
#define BRPHY0_ECD_CTRL_EXPC1          0x090f2542 /* ECD Fault Type */
#define BRPHY0_ECD_CTRL_EXPC2          0x090f2544 /* ECD Pair A Length Results */
#define BRPHY0_ECD_CTRL_EXPC3          0x090f2546 /* ECD Pair B Length Results */
#define BRPHY0_ECD_CTRL_EXPC4          0x090f2548 /* ECD Pair C Length Results */
#define BRPHY0_ECD_CTRL_EXPC5          0x090f254a /* ECD Pair D Length Results */
#define BRPHY0_ECD_CTRL_EXPC6          0x090f254c /* ECD XTALK Map */
#define BRPHY0_ECD_CTRL_EXPC7          0x090f254e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPC8          0x090f2550 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPC9          0x090f2552 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPCA          0x090f2554 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPCB          0x090f2556 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPCC          0x090f2558 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPCD          0x090f255a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPCE          0x090f255c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPCF          0x090f255e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE0          0x090f2560 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE1          0x090f2562 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE2          0x090f2564 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE3          0x090f2566 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE4          0x090f2568 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE5          0x090f256a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE6          0x090f256c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE7          0x090f256e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE8          0x090f2570 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPE9          0x090f2572 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPEA          0x090f2574 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPEB          0x090f2576 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPEC          0x090f2578 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPED          0x090f257a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPEE          0x090f257c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY0_ECD_CTRL_EXPEF          0x090f257e /* ECD EXTRA RESERVED REGISTER */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_BR_CTRL
 ***************************************************************************/
#define BRPHY0_BR_CTRL_EXP90           0x090f2600 /* BroadReach LRE Misc Control */
#define BRPHY0_BR_CTRL_EXP91           0x090f2602 /* BroadReach LRE Misc Control */
#define BRPHY0_BR_CTRL_EXP92           0x090f2604 /* BroadReach LRE Misc Control */
#define BRPHY0_BR_CTRL_EXP93           0x090f2606 /* BroadReach LDS  Control */
#define BRPHY0_BR_CTRL_EXP94           0x090f2608 /* BroadReach LDS RX Control */
#define BRPHY0_BR_CTRL_EXP95           0x090f260a /* BroadReach LDS RX Control */
#define BRPHY0_BR_CTRL_EXP96           0x090f260c /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY0_BR_CTRL_EXP97           0x090f260e /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY0_BR_CTRL_EXP99           0x090f2612 /* BroadReach LDS Timer Control */
#define BRPHY0_BR_CTRL_EXP9A           0x090f2614 /* LDS Status */
#define BRPHY0_BR_CTRL_EXP9B           0x090f2616 /* BroadR-Reach PLL Control */
#define BRPHY0_BR_CTRL_EXP9D           0x090f261a /* EoC Internal Control 1 */
#define BRPHY0_BR_CTRL_EXP9E           0x090f261c /* LDS Length Threshold 0 */
#define BRPHY0_BR_CTRL_EXP9F           0x090f261e /* LDS Length Threshold 1 */
#define BRPHY0_BR_CTRL_EXPA0           0x090f2620 /* HLDS register, LDS extend advertisement register */
#define BRPHY0_BR_CTRL_EXPA1           0x090f2622 /* HLDS register, LDS link partner extend ability register */
#define BRPHY0_BR_CTRL_EXPA2           0x090f2624 /* HLDS Register */
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS 0x090f2626 /* Broadreach Misc Status */
#define BRPHY0_BR_CTRL_BR250_CTL       0x090f263c /* BR250 Control */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY_TOP_MISC_0
 ***************************************************************************/
#define BRPHY_TOP_MISC_0_SPARE_REG_0   0x090f3000 /* spare registers 16 bits */
#define BRPHY_TOP_MISC_0_SPARE_REG_1   0x090f3002 /* spare registers 16 bits */
#define BRPHY_TOP_MISC_0_AFE_OVR       0x090f3004 /* AFE Override Control Register */
#define BRPHY_TOP_MISC_0_TEST_REG0     0x090f3006 /* Test control register 0 for iddq etc. mode */
#define BRPHY_TOP_MISC_0_TEST_REG1     0x090f3008 /* Test control register 1 for test bus selection */
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG 0x090f300a /* Global Top level soft reset register */
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG 0x090f300c /* Top interrupt status register */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY_WOL
 ***************************************************************************/
#define BRPHY_WOL_TB_P0_CTRL           0x090f3200 /* Wake On LAN Main Control Register */
#define BRPHY_WOL_TB_P0_ITPID          0x090f3202 /* Inner Tag Protocol ID Register */
#define BRPHY_WOL_TB_P0_OTPID          0x090f3204 /* Outer Tag Protocol ID Register */
#define BRPHY_WOL_TB_P0_OTPID2         0x090f3206 /* Outer Tag Protocol ID 2 Register */
#define BRPHY_WOL_TB_P0_PKT1_15_00     0x090f3208 /* Magic Packet1 Data bit [15:0] Register */
#define BRPHY_WOL_TB_P0_PKT1_31_16     0x090f320a /* Magic Packet1 Data bit [31:16] Register */
#define BRPHY_WOL_TB_P0_PKT1_47_32     0x090f320c /* Magic Packet1 Data bit [47:32] Register */
#define BRPHY_WOL_TB_P0_PKT2_15_00     0x090f320e /* Magic Packet2/SecureKey Data bit [15:0] Register */
#define BRPHY_WOL_TB_P0_PKT2_31_16     0x090f3210 /* Magic Packet2/SecureKey Data bit [31:16] Register */
#define BRPHY_WOL_TB_P0_PKT2_47_32     0x090f3212 /* Magic Packet2/SecureKey Data bit [47:32] Register */
#define BRPHY_WOL_TB_P0_PKT2_63_48     0x090f3214 /* SecureKey Data bit [63:48] Register(SecureKey 8 byte mode) */
#define BRPHY_WOL_TB_P0_MSKCTR_15_00   0x090f3216 /* Wake On LAN Packet Mask Control Register [15:0] */
#define BRPHY_WOL_TB_P0_MSKCTR_31_16   0x090f3218 /* Wake On LAN Packet Mask Control Register [31:16] */
#define BRPHY_WOL_TB_P0_MSKCTR_47_32   0x090f321a /* Wake On LAN Packet Mask Control Register [47:32] */
#define BRPHY_WOL_TB_P0_SECKEY_15_00   0x090f321c /* Wake On LAN Secure Key Data Storage Register [15:0] */
#define BRPHY_WOL_TB_P0_SECKEY_31_16   0x090f321e /* Wake On LAN Secure Key Data Storage Register [31:16] */
#define BRPHY_WOL_TB_P0_SECKEY_47_32   0x090f3220 /* Wake On LAN Secure Key Data Storage Register [47:32] */
#define BRPHY_WOL_TB_P0_SECKEY_63_48   0x090f3222 /* Wake On LAN Secure Key Data Storage Register [63:48] */
#define BRPHY_WOL_TB_P0_PKT_CNT        0x090f3224 /* Magic Packet 1/2 Shared Counter Register */
#define BRPHY_WOL_TB_P1_CTRL           0x090f3226 /* Wake On LAN Main Control Register */
#define BRPHY_WOL_TB_P1_ITPID          0x090f3228 /* Inner Tag Protocol ID Register */
#define BRPHY_WOL_TB_P1_OTPID          0x090f322a /* Outer Tag Protocol ID Register */
#define BRPHY_WOL_TB_P1_OTPID2         0x090f322c /* Outer Tag Protocol ID 2 Register */
#define BRPHY_WOL_TB_P1_PKT1_15_00     0x090f322e /* Magic Packet1 Data bit [15:0] Register */
#define BRPHY_WOL_TB_P1_PKT1_31_16     0x090f3230 /* Magic Packet1 Data bit [31:16] Register */
#define BRPHY_WOL_TB_P1_PKT1_47_32     0x090f3232 /* Magic Packet1 Data bit [47:32] Register */
#define BRPHY_WOL_TB_P1_PKT2_15_00     0x090f3234 /* Magic Packet2/SecureKey Data bit [15:0] Register */
#define BRPHY_WOL_TB_P1_PKT2_31_16     0x090f3236 /* Magic Packet2/SecureKey Data bit [31:16] Register */
#define BRPHY_WOL_TB_P1_PKT2_47_32     0x090f3238 /* Magic Packet2/SecureKey Data bit [47:32] Register */
#define BRPHY_WOL_TB_P1_PKT2_63_48     0x090f323a /* SecureKey Data bit [63:48] Register(SecureKey 8 byte mode) */
#define BRPHY_WOL_TB_P1_MSKCTR_15_00   0x090f323c /* Wake On LAN Packet Mask Control Register [15:0] */
#define BRPHY_WOL_TB_P1_MSKCTR_31_16   0x090f323e /* Wake On LAN Packet Mask Control Register [31:16] */
#define BRPHY_WOL_TB_P1_MSKCTR_47_32   0x090f3240 /* Wake On LAN Packet Mask Control Register [47:32] */
#define BRPHY_WOL_TB_P1_SECKEY_15_00   0x090f3242 /* Wake On LAN Secure Key Data Storage Register [15:0] */
#define BRPHY_WOL_TB_P1_SECKEY_31_16   0x090f3244 /* Wake On LAN Secure Key Data Storage Register [31:16] */
#define BRPHY_WOL_TB_P1_SECKEY_47_32   0x090f3246 /* Wake On LAN Secure Key Data Storage Register [47:32] */
#define BRPHY_WOL_TB_P1_SECKEY_63_48   0x090f3248 /* Wake On LAN Secure Key Data Storage Register [63:48] */
#define BRPHY_WOL_TB_P1_PKT_CNT        0x090f324a /* Magic Packet 1/2 Shared Counter Register */
#define BRPHY_WOL_TB_P2_CTRL           0x090f324c /* Wake On LAN Main Control Register */
#define BRPHY_WOL_TB_P2_ITPID          0x090f324e /* Inner Tag Protocol ID Register */
#define BRPHY_WOL_TB_P2_OTPID          0x090f3250 /* Outer Tag Protocol ID Register */
#define BRPHY_WOL_TB_P2_OTPID2         0x090f3252 /* Outer Tag Protocol ID 2 Register */
#define BRPHY_WOL_TB_P2_PKT1_15_00     0x090f3254 /* Magic Packet1 Data bit [15:0] Register */
#define BRPHY_WOL_TB_P2_PKT1_31_16     0x090f3256 /* Magic Packet1 Data bit [31:16] Register */
#define BRPHY_WOL_TB_P2_PKT1_47_32     0x090f3258 /* Magic Packet1 Data bit [47:32] Register */
#define BRPHY_WOL_TB_P2_PKT2_15_00     0x090f325a /* Magic Packet2/SecureKey Data bit [15:0] Register */
#define BRPHY_WOL_TB_P2_PKT2_31_16     0x090f325c /* Magic Packet2/SecureKey Data bit [31:16] Register */
#define BRPHY_WOL_TB_P2_PKT2_47_32     0x090f325e /* Magic Packet2/SecureKey Data bit [47:32] Register */
#define BRPHY_WOL_TB_P2_PKT2_63_48     0x090f3260 /* SecureKey Data bit [63:48] Register(SecureKey 8 byte mode) */
#define BRPHY_WOL_TB_P2_MSKCTR_15_00   0x090f3262 /* Wake On LAN Packet Mask Control Register [15:0] */
#define BRPHY_WOL_TB_P2_MSKCTR_31_16   0x090f3264 /* Wake On LAN Packet Mask Control Register [31:16] */
#define BRPHY_WOL_TB_P2_MSKCTR_47_32   0x090f3266 /* Wake On LAN Packet Mask Control Register [47:32] */
#define BRPHY_WOL_TB_P2_SECKEY_15_00   0x090f3268 /* Wake On LAN Secure Key Data Storage Register [15:0] */
#define BRPHY_WOL_TB_P2_SECKEY_31_16   0x090f326a /* Wake On LAN Secure Key Data Storage Register [31:16] */
#define BRPHY_WOL_TB_P2_SECKEY_47_32   0x090f326c /* Wake On LAN Secure Key Data Storage Register [47:32] */
#define BRPHY_WOL_TB_P2_SECKEY_63_48   0x090f326e /* Wake On LAN Secure Key Data Storage Register [63:48] */
#define BRPHY_WOL_TB_P2_PKT_CNT        0x090f3270 /* Magic Packet 1/2 Shared Counter Register */
#define BRPHY_WOL_TB_P3_CTRL           0x090f3272 /* Wake On LAN Main Control Register */
#define BRPHY_WOL_TB_P3_ITPID          0x090f3274 /* Inner Tag Protocol ID Register */
#define BRPHY_WOL_TB_P3_OTPID          0x090f3276 /* Outer Tag Protocol ID Register */
#define BRPHY_WOL_TB_P3_OTPID2         0x090f3278 /* Outer Tag Protocol ID 2 Register */
#define BRPHY_WOL_TB_P3_PKT1_15_00     0x090f327a /* Magic Packet1 Data bit [15:0] Register */
#define BRPHY_WOL_TB_P3_PKT1_31_16     0x090f327c /* Magic Packet1 Data bit [31:16] Register */
#define BRPHY_WOL_TB_P3_PKT1_47_32     0x090f327e /* Magic Packet1 Data bit [47:32] Register */
#define BRPHY_WOL_TB_P3_PKT2_15_00     0x090f3280 /* Magic Packet2/SecureKey Data bit [15:0] Register */
#define BRPHY_WOL_TB_P3_PKT2_31_16     0x090f3282 /* Magic Packet2/SecureKey Data bit [31:16] Register */
#define BRPHY_WOL_TB_P3_PKT2_47_32     0x090f3284 /* Magic Packet2/SecureKey Data bit [47:32] Register */
#define BRPHY_WOL_TB_P3_PKT2_63_48     0x090f3286 /* SecureKey Data bit [63:48] Register(SecureKey 8 byte mode) */
#define BRPHY_WOL_TB_P3_MSKCTR_15_00   0x090f3288 /* Wake On LAN Packet Mask Control Register [15:0] */
#define BRPHY_WOL_TB_P3_MSKCTR_31_16   0x090f328a /* Wake On LAN Packet Mask Control Register [31:16] */
#define BRPHY_WOL_TB_P3_MSKCTR_47_32   0x090f328c /* Wake On LAN Packet Mask Control Register [47:32] */
#define BRPHY_WOL_TB_P3_SECKEY_15_00   0x090f328e /* Wake On LAN Secure Key Data Storage Register [15:0] */
#define BRPHY_WOL_TB_P3_SECKEY_31_16   0x090f3290 /* Wake On LAN Secure Key Data Storage Register [31:16] */
#define BRPHY_WOL_TB_P3_SECKEY_47_32   0x090f3292 /* Wake On LAN Secure Key Data Storage Register [47:32] */
#define BRPHY_WOL_TB_P3_SECKEY_63_48   0x090f3294 /* Wake On LAN Secure Key Data Storage Register [63:48] */
#define BRPHY_WOL_TB_P3_PKT_CNT        0x090f3296 /* Magic Packet 1/2 Shared Counter Register */
#define BRPHY_WOL_TB_P4_CTRL           0x090f3298 /* Wake On LAN Main Control Register */
#define BRPHY_WOL_TB_P4_ITPID          0x090f329a /* Inner Tag Protocol ID Register */
#define BRPHY_WOL_TB_P4_OTPID          0x090f329c /* Outer Tag Protocol ID Register */
#define BRPHY_WOL_TB_P4_OTPID2         0x090f329e /* Outer Tag Protocol ID 2 Register */
#define BRPHY_WOL_TB_P4_PKT1_15_00     0x090f32a0 /* Magic Packet1 Data bit [15:0] Register */
#define BRPHY_WOL_TB_P4_PKT1_31_16     0x090f32a2 /* Magic Packet1 Data bit [31:16] Register */
#define BRPHY_WOL_TB_P4_PKT1_47_32     0x090f32a4 /* Magic Packet1 Data bit [47:32] Register */
#define BRPHY_WOL_TB_P4_PKT2_15_00     0x090f32a6 /* Magic Packet2/SecureKey Data bit [15:0] Register */
#define BRPHY_WOL_TB_P4_PKT2_31_16     0x090f32a8 /* Magic Packet2/SecureKey Data bit [31:16] Register */
#define BRPHY_WOL_TB_P4_PKT2_47_32     0x090f32aa /* Magic Packet2/SecureKey Data bit [47:32] Register */
#define BRPHY_WOL_TB_P4_PKT2_63_48     0x090f32ac /* SecureKey Data bit [63:48] Register(SecureKey 8 byte mode) */
#define BRPHY_WOL_TB_P4_MSKCTR_15_00   0x090f32ae /* Wake On LAN Packet Mask Control Register [15:0] */
#define BRPHY_WOL_TB_P4_MSKCTR_31_16   0x090f32b0 /* Wake On LAN Packet Mask Control Register [31:16] */
#define BRPHY_WOL_TB_P4_MSKCTR_47_32   0x090f32b2 /* Wake On LAN Packet Mask Control Register [47:32] */
#define BRPHY_WOL_TB_P4_SECKEY_15_00   0x090f32b4 /* Wake On LAN Secure Key Data Storage Register [15:0] */
#define BRPHY_WOL_TB_P4_SECKEY_31_16   0x090f32b6 /* Wake On LAN Secure Key Data Storage Register [31:16] */
#define BRPHY_WOL_TB_P4_SECKEY_47_32   0x090f32b8 /* Wake On LAN Secure Key Data Storage Register [47:32] */
#define BRPHY_WOL_TB_P4_SECKEY_63_48   0x090f32ba /* Wake On LAN Secure Key Data Storage Register [63:48] */
#define BRPHY_WOL_TB_P4_PKT_CNT        0x090f32bc /* Magic Packet 1/2 Shared Counter Register */
#define BRPHY_WOL_TB_INTR_MSK0         0x090f32be /* Magic Packet Interrupt Mask Register 0 */
#define BRPHY_WOL_TB_INTR_STS0         0x090f32c0 /* Magic Packet Status Interrupt Register 0 */
#define BRPHY_WOL_TB_WOL_TPO_SEL       0x090f32c2 /* wol tpo port sel */
#define BRPHY_WOL_TB_WOL_SPARE         0x090f33fc /* Spare Register */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY_TOP_1588
 ***************************************************************************/
#define BRPHY_TOP_1588_SLICE_ENABLE    0x090f3420 /* P1588 Slice Enable Control Register */
#define BRPHY_TOP_1588_TX_MODE_PORT_0  0x090f3422 /* P1588 Port 0 TX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_TX_MODE_PORT_1  0x090f3424 /* P1588 Port 1 TX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_TX_MODE_PORT_2  0x090f3426 /* P1588 Port 2 TX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_TX_MODE_PORT_3  0x090f3428 /* P1588 Port 3 TX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_TX_MODE_PORT_4  0x090f342a /* P1588 Port 4 TX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_TX_MODE_PORT_5  0x090f342c /* P1588 Port 5 TX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_TX_MODE_PORT_6  0x090f342e /* P1588 Port 6 TX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_TX_MODE_PORT_7  0x090f3430 /* P1588 Port 7 TX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_RX_MODE_PORT_0  0x090f3432 /* P1588 Port 0 RX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_RX_MODE_PORT_1  0x090f3434 /* P1588 Port 1 RX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_RX_MODE_PORT_2  0x090f3436 /* P1588 Port 2 RX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_RX_MODE_PORT_3  0x090f3438 /* P1588 Port 3 RX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_RX_MODE_PORT_4  0x090f343a /* P1588 Port 4 RX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_RX_MODE_PORT_5  0x090f343c /* P1588 Port 5 RX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_RX_MODE_PORT_6  0x090f343e /* P1588 Port 6 RX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_RX_MODE_PORT_7  0x090f3440 /* P1588 Port 7 RX Event Message Mode1 and Mode2 Selection Register */
#define BRPHY_TOP_1588_TX_TS_CAP       0x090f3442 /* P1588 TX SOP Timestamp Capture Enable */
#define BRPHY_TOP_1588_RX_TS_CAP       0x090f3444 /* P1588 RX SOP Timestamp Capture Enable Register */
#define BRPHY_TOP_1588_RX_TX_OPTION    0x090f3446 /* P1588 RX and TX Option Register */
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_LSB 0x090f3448 /* P1588 Port 0 RX PORT Link delay LSB Register */
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_MSB 0x090f344a /* P1588 Port 0 RX PORT Link delay MSB Register */
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_LSB 0x090f344c /* P1588 Port 1 RX PORT Link delay LSB Register */
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_MSB 0x090f344e /* P1588 Port 1 RX PORT Link delay MSB Register */
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_LSB 0x090f3450 /* P1588 Port 2 RX PORT Link delay LSB Register */
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_MSB 0x090f3452 /* P1588 Port 2 RX PORT Link delay MSB Register */
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_LSB 0x090f3454 /* P1588 Port 3 RX PORT Link delay LSB Register */
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_MSB 0x090f3456 /* P1588 Port 3 RX PORT Link delay MSB Register */
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_LSB 0x090f3458 /* P1588 Port 4 RX PORT Link delay LSB Register */
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_MSB 0x090f345a /* P1588 Port 4 RX PORT Link delay MSB Register */
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_LSB 0x090f345c /* P1588 Port 5 RX PORT Link delay LSB Register */
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_MSB 0x090f345e /* P1588 Port 5 RX PORT Link delay MSB Register */
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_LSB 0x090f3460 /* P1588 Port 6 RX PORT Link delay LSB Register */
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_MSB 0x090f3462 /* P1588 Port 6 RX PORT Link delay MSB Register */
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_LSB 0x090f3464 /* P1588 Port 7 RX PORT Link delay LSB Register */
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_MSB 0x090f3466 /* P1588 Port 7 RX PORT Link delay MSB Register */
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_LSB 0x090f3468 /* P1588 Port 0 TX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB 0x090f346a /* P1588 Port 0 TX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_LSB 0x090f346c /* P1588 Port 1 TX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB 0x090f346e /* P1588 Port 1 TX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_LSB 0x090f3470 /* P1588 Port 2 TX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB 0x090f3472 /* P1588 Port 2 TX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_LSB 0x090f3474 /* P1588 Port 3 TX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB 0x090f3476 /* P1588 Port 3 TX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_LSB 0x090f3478 /* P1588 Port 4 TX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB 0x090f347a /* P1588 Port 4 TX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_LSB 0x090f347c /* P1588 Port 5 TX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB 0x090f347e /* P1588 Port 5 TX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_LSB 0x090f3480 /* P1588 Port 6 TX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB 0x090f3482 /* P1588 Port 6 TX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_LSB 0x090f3484 /* P1588 Port 7 TX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB 0x090f3486 /* P1588 Port 7 TX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_LSB 0x090f3488 /* P1588 Port 0 RX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB 0x090f348a /* P1588 Port 0 RX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_LSB 0x090f348c /* P1588 Port 1 RX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB 0x090f348e /* P1588 Port 1 RX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_LSB 0x090f3490 /* P1588 Port 2 RX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB 0x090f3492 /* P1588 Port 2 RX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_LSB 0x090f3494 /* P1588 Port 3 RX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB 0x090f3496 /* P1588 Port 3 RX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_LSB 0x090f3498 /* P1588 Port 4 RX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB 0x090f349a /* P1588 Port 4 RX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_LSB 0x090f349c /* P1588 Port 5 RX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB 0x090f349e /* P1588 Port 5 RX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_LSB 0x090f34a0 /* P1588 Port 6 RX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB 0x090f34a2 /* P1588 Port 6 RX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_LSB 0x090f34a4 /* P1588 Port 7 RX Timestamp Offset LSB Register */
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB 0x090f34a6 /* P1588 Port 7 RX Timestamp Offset MSB Register */
#define BRPHY_TOP_1588_TIME_CODE_0     0x090f34a8 /* P1588 Original Time Code 0 Register */
#define BRPHY_TOP_1588_TIME_CODE_1     0x090f34aa /* P1588 Original Time Code 1 Register */
#define BRPHY_TOP_1588_TIME_CODE_2     0x090f34ac /* P1588 Original Time Code 2 Register */
#define BRPHY_TOP_1588_TIME_CODE_3     0x090f34ae /* P1588 Original Time Code 3 Register */
#define BRPHY_TOP_1588_TIME_CODE_4     0x090f34b0 /* P1588 Original Time Code 4 Register */
#define BRPHY_TOP_1588_DPLL_DB_LSB     0x090f34b2 /* P1588 DPLL Debug LSB Register */
#define BRPHY_TOP_1588_DPLL_DB_MSB     0x090f34b4 /* P1588 DPLL Debug MSB Register */
#define BRPHY_TOP_1588_DPLL_DB_SEL     0x090f34b6 /* P1588 DPLL Debug Select Register */
#define BRPHY_TOP_1588_SHD_CTL         0x090f34b8 /* P1588 Shadow Register Control */
#define BRPHY_TOP_1588_SHD_LD          0x090f34ba /* P1588 Shadow Register Load */
#define BRPHY_TOP_1588_INT_MASK        0x090f34bc /* P1588 Interrupt Mask Register */
#define BRPHY_TOP_1588_INT_STAT        0x090f34be /* P1588 Interrupt Status Register */
#define BRPHY_TOP_1588_TX_CTL          0x090f34c0 /* P1588 Transmit Control Register */
#define BRPHY_TOP_1588_RX_CTL          0x090f34c2 /* P1588 Receive Control Register */
#define BRPHY_TOP_1588_RX_TX_CTL       0x090f34c4 /* P1588 Receive/Transmit Control Register */
#define BRPHY_TOP_1588_VLAN_ITPID      0x090f34c6 /* P1588 VLAN 1tags ITPID Register */
#define BRPHY_TOP_1588_VLAN_OTPID      0x090f34c8 /* P1588 VLAN 2tags OTPID Register */
#define BRPHY_TOP_1588_OTHER_OTPID     0x090f34ca /* P1588 VLAN 2Tags Other OTPID Register */
#define BRPHY_TOP_1588_NSE_DPLL_1      0x090f34cc /* P1588 NSE DPLL Register 1 */
#define BRPHY_TOP_1588_NSE_DPLL_2_0    0x090f34ce /* P1588 NSE DPLL Register 2(0) */
#define BRPHY_TOP_1588_NSE_DPLL_2_1    0x090f34d0 /* P1588 NSE DPLL Register 2(1) */
#define BRPHY_TOP_1588_NSE_DPLL_2_2    0x090f34d2 /* P1588 NSE DPLL Register 2(2) */
#define BRPHY_TOP_1588_NSE_DPLL_3_LSB  0x090f34d4 /* P1588 NSE DPLL Register 3 LSB */
#define BRPHY_TOP_1588_NSE_DPLL_3_MSB  0x090f34d6 /* P1588 NSE DPLL Register 3 MSB */
#define BRPHY_TOP_1588_NSE_DPLL_4      0x090f34d8 /* P1588 NSE DPLL Register 4 */
#define BRPHY_TOP_1588_NSE_DPLL_5      0x090f34da /* P1588 NSE DPLL Register 5 */
#define BRPHY_TOP_1588_NSE_DPLL_6      0x090f34dc /* P1588 NSE DPLL Register 6 */
#define BRPHY_TOP_1588_NSE_DPLL_7_0    0x090f34de /* P1588 NSE DPLL Register 7(0) */
#define BRPHY_TOP_1588_NSE_DPLL_7_1    0x090f34e0 /* P1588 NSE DPLL Register 7(1) */
#define BRPHY_TOP_1588_NSE_DPLL_7_2    0x090f34e2 /* P1588 NSE DPLL Register 7(2) */
#define BRPHY_TOP_1588_NSE_DPLL_7_3    0x090f34e4 /* P1588 NSE DPLL Register 7(3) */
#define BRPHY_TOP_1588_NSE_NCO_1_LSB   0x090f34e6 /* P1588 NSE DPLL NCO Register 1 LSB */
#define BRPHY_TOP_1588_NSE_NCO_1_MSB   0x090f34e8 /* P1588 NSE DPLL NCO Register 1 MSB */
#define BRPHY_TOP_1588_NSE_NCO_2_0     0x090f34ea /* P1588 NSE DPLL NCO Register 2(0) */
#define BRPHY_TOP_1588_NSE_NCO_2_1     0x090f34ec /* P1588 NSE DPLL NCO Register 2(1) */
#define BRPHY_TOP_1588_NSE_NCO_2_2     0x090f34ee /* P1588 NSE DPLL NCO Register 2(2) */
#define BRPHY_TOP_1588_NSE_NCO_3_0     0x090f34f0 /* P1588 NSE DPLL NCO Register 3(0) */
#define BRPHY_TOP_1588_NSE_NCO_3_1     0x090f34f2 /* P1588 NSE DPLL NCO Register 3(1) */
#define BRPHY_TOP_1588_NSE_NCO_3_2     0x090f34f4 /* P1588 NSE DPLL NCO Register 3(2) */
#define BRPHY_TOP_1588_NSE_NCO_4       0x090f34f6 /* P1588 NSE DPLL NCO Register 4 */
#define BRPHY_TOP_1588_NSE_NCO_5_0     0x090f34f8 /* P1588 NSE DPLL NCO Register 5(0) */
#define BRPHY_TOP_1588_NSE_NCO_5_1     0x090f34fa /* P1588 NSE DPLL NCO Register 5(1) */
#define BRPHY_TOP_1588_NSE_NCO_5_2     0x090f34fc /* P1588 NSE DPLL NCO Register 5(2) */
#define BRPHY_TOP_1588_NSE_NCO_6       0x090f34fe /* P1588 NSE DPLL NCO Register 6 */
#define BRPHY_TOP_1588_NSE_NCO_7_0     0x090f3500 /* P1588 NSE DPLL NCO Register 7(0) */
#define BRPHY_TOP_1588_NSE_NCO_7_1     0x090f3502 /* P1588 NSE DPLL NCO Register 7(1) */
#define BRPHY_TOP_1588_TX_COUNTER      0x090f3504 /* P1588 TX Counter */
#define BRPHY_TOP_1588_RX_COUNTER      0x090f3506 /* P1588 RX Counter */
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER 0x090f3508 /* P1588 RX TX 1588 Counter */
#define BRPHY_TOP_1588_TS_READ_START_END 0x090f350a /* P1588 Timestamp READ START/END Register */
#define BRPHY_TOP_1588_HEARTBEAT_0     0x090f350c /* P1588 Heartbeat Register(0) */
#define BRPHY_TOP_1588_HEARTBEAT_1     0x090f350e /* P1588 Heartbeat Register(1) */
#define BRPHY_TOP_1588_HEARTBEAT_2     0x090f3510 /* P1588 Heartbeat Register(2) */
#define BRPHY_TOP_1588_TIME_STAMP_0    0x090f3512 /* P1588 Time Stamp Register(0) */
#define BRPHY_TOP_1588_TIME_STAMP_1    0x090f3514 /* P1588 Time Stamp Register(1) */
#define BRPHY_TOP_1588_TIME_STAMP_2    0x090f3516 /* P1588 Time Stamp Register(2) */
#define BRPHY_TOP_1588_TIME_STAMP_INFO_1 0x090f3518 /* P1588 Time Stamp Register Info (1) */
#define BRPHY_TOP_1588_TIME_STAMP_INFO_2 0x090f351a /* P1588 Time Stamp Register Info (2) */
#define BRPHY_TOP_1588_CNTR_DBG        0x090f351c /* P1588 Control/Debug Register */
#define BRPHY_TOP_1588_MPLS_SPARE1     0x090f351e /* P1588 CPU TX and RX Port Enable Registers */
#define BRPHY_TOP_1588_MPLS_SPARE2     0x090f3520 /* P1588 DA1 Registers */
#define BRPHY_TOP_1588_MPLS_SPARE3     0x090f3522 /* P1588 DA2 Registers */
#define BRPHY_TOP_1588_MPLS_SPARE4     0x090f3524 /* P1588 DA3 Registers */
#define BRPHY_TOP_1588_MPLS_SPARE5     0x090f3526 /* P1588 MPLS Special Label LSB Registers */
#define BRPHY_TOP_1588_MPLS_SPARE6     0x090f3528 /* P1588 MPLS SPECIAL lABEL 4 MSB Registers */
#define BRPHY_TOP_1588_MPLS_TX_CNTL    0x090f352a /* P1588 MPLS TX Enable */
#define BRPHY_TOP_1588_MPLS_RX_CNTL    0x090f352c /* P1588 MPLS RX Enable */
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_MASK 0x090f352e /* P1588 MPLS label1 mask lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK 0x090f3530 /* P1588 MPLS label1 mask msb bit (*Inband P0 Control) */
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_VALUE 0x090f3532 /* P1588 MPLS label1 value lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE 0x090f3534 /* P1588 MPLS label1 value msb bit (*HSR P0 Offset) */
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_MASK 0x090f3536 /* P1588 MPLS label2 mask lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK 0x090f3538 /* P1588 MPLS label2 mask msb bit (*Inband P1 Control) */
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_VALUE 0x090f353a /* P1588 MPLS label2 value lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE 0x090f353c /* P1588 MPLS label2 value msb bit (*HSR P1 Offset) */
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_MASK 0x090f353e /* P1588 MPLS label3 mask lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK 0x090f3540 /* P1588 MPLS label3 mask msb bit (*Inband P2 Control) */
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_VALUE 0x090f3542 /* P1588 MPLS label3 value lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE 0x090f3544 /* P1588 MPLS label3 value msb bit (*HSR P2 Offset) */
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_MASK 0x090f3546 /* P1588 MPLS label4 mask lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK 0x090f3548 /* P1588 MPLS label4 mask msb bit (*Inband P3 Control) */
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_VALUE 0x090f354a /* P1588 MPLS label4 value lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE 0x090f354c /* P1588 MPLS label4 value msb bit (*HSR P3 Offset) */
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_MASK 0x090f354e /* P1588 MPLS label5 mask lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK 0x090f3550 /* P1588 MPLS label5 mask msb bit (*Inband P4 Control) */
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_VALUE 0x090f3552 /* P1588 MPLS label5 value lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE 0x090f3554 /* P1588 MPLS label5 value msb bit (*HSR P4 Offset) */
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_MASK 0x090f3556 /* P1588 MPLS label6 mask lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK 0x090f3558 /* P1588 MPLS label6 mask msb bit (*Inband P5 Control) */
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_VALUE 0x090f355a /* P1588 MPLS label6 value lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE 0x090f355c /* P1588 MPLS label6 value msb bit (*HSR P5 Offset) */
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_MASK 0x090f355e /* P1588 MPLS label7 mask lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK 0x090f3560 /* P1588 MPLS label7 mask msb bit (*Inband P6 Control) */
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_VALUE 0x090f3562 /* P1588 MPLS label7 value lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE 0x090f3564 /* P1588 MPLS label7 value msb bit (*HSR P6 Offset) */
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_MASK 0x090f3566 /* P1588 MPLS label8 mask lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK 0x090f3568 /* P1588 MPLS label8 mask msb bit (*Inband P7 Control) */
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_VALUE 0x090f356a /* P1588 MPLS label8 value lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE 0x090f356c /* P1588 MPLS label8 value msb bit (*HSR P7 Offset) */
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_MASK 0x090f356e /* P1588 MPLS label9 mask lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK 0x090f3570 /* P1588 MPLS label9 mask msb bit */
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_VALUE 0x090f3572 /* P1588 MPLS label9 value lsb bit */
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE 0x090f3574 /* P1588 MPLS label9 value msb bit */
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_MASK 0x090f3576 /* P1588 MPLS label10 mask lsb bit (*HSR Enable) */
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK 0x090f3578 /* P1588 MPLS label10 mask msb bit (*HSR Ethertype) */
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_VALUE 0x090f357a /* P1588 MPLS label10 value lsb bit (*HSR SNAP/LLC Control) */
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE 0x090f357c /* P1588 MPLS label10 value msb bit */
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER1 0x090f357e /* P1588 RX TX CPU 1588 Counter */
#define BRPHY_TOP_1588_RX_CF_SPEC      0x090f3580 /* P1588 RX CF + Insertion */
#define BRPHY_TOP_1588_TX_CF_SPEC      0x090f3582 /* P1588 TX CS Update */
#define BRPHY_TOP_1588_MPLS_PACKET_ENABLE 0x090f3584 /* P1588 MPLS_PACKET ENABLE */
#define BRPHY_TOP_1588_TIMECODE_SEL    0x090f3586 /* P1588 TIMECODE SEL */
#define BRPHY_TOP_1588_TIME_STAMP_3    0x090f3588 /* P1588 Time Stamp Register(3) */
#define BRPHY_TOP_1588_TIME_STAMP      0x090f358a /* P1588 Control/Debug Register */
#define BRPHY_TOP_1588_DM_TX_CNTL      0x090f358c /* P1588 Delay Measurment Control Register */
#define BRPHY_TOP_1588_DM_RX_CNTL      0x090f358e /* P1588 Delay Measurment Control Register */
#define BRPHY_TOP_1588_DM_ETHTYPE1     0x090f3590 /* P1588 Delay Measurment Ethtype1 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE2     0x090f3592 /* P1588 Delay Measurment Ethtype2 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE3     0x090f3594 /* P1588 Delay Measurment Ethtype3 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE4     0x090f3596 /* P1588 Delay Measurment Ethtype4 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE5     0x090f3598 /* P1588 Delay Measurment Ethtype5 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE6     0x090f359a /* P1588 Delay Measurment Ethtype6 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE7     0x090f359c /* P1588 Delay Measurment Ethtype7 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE8     0x090f359e /* P1588 Delay Measurment Ethtype8 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE9     0x090f35a0 /* P1588 Delay Measurment Ethtype9 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE10    0x090f35a2 /* P1588 Delay Measurment Ethtype10 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE11    0x090f35a4 /* P1588 Delay Measurment Ethtype11 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE12    0x090f35a6 /* P1588 Delay Measurment Ethtype12 Register */
#define BRPHY_TOP_1588_DM_ETHTYPE13    0x090f35a8 /* P1588 Delay Measurment Ethtype13 Register */
#define BRPHY_TOP_1588_DM_IETF_OFFSET  0x090f35aa /* P1588 Delay Measurment IETF Offfset Register */
#define BRPHY_TOP_1588_NTP_TIME_STAMP_0 0x090f35ac /* P1588 NTP Counter Time Stamp0  Register */
#define BRPHY_TOP_1588_NTP_TIME_STAMP_1 0x090f35ae /* P1588 NTP Counter Time Stamp1  Register */
#define BRPHY_TOP_1588_NTP_TIME_STAMP_2 0x090f35b0 /* P1588 NTP Counter Time Stamp2  Register */
#define BRPHY_TOP_1588_NTP_TIME_STAMP_3 0x090f35b2 /* P1588 NTP Counter Time Stamp3  Register */
#define BRPHY_TOP_1588_NTP_NCO_FREQ_0  0x090f35b4 /* P1588 NTP NCO Frequency0  Register */
#define BRPHY_TOP_1588_NTP_NCO_FREQ_1  0x090f35b6 /* P1588 NTP NCO Frequency1  Register */
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_0 0x090f35b8 /* P1588 NTP Down Counter 0  Register */
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_1 0x090f35ba /* P1588 NTP Down Counter 1  Register */
#define BRPHY_TOP_1588_NTP_ERR_LSB     0x090f35bc /* P1588 NTP ERR LSB  Register */
#define BRPHY_TOP_1588_NTP_ERR_MSB     0x090f35be /* P1588 NTP ERR MSB  Register */
#define BRPHY_TOP_1588_DM_MAC_L1_0     0x090f35c0 /* P1588 DM MAC Address Local1 0 Register */
#define BRPHY_TOP_1588_DM_MAC_L1_1     0x090f35c2 /* P1588 DM MAC Address Local1 0 Register */
#define BRPHY_TOP_1588_DM_MAC_L1_2     0x090f35c4 /* P1588 DM MAC Address Local1 0 Register */
#define BRPHY_TOP_1588_DM_MAC_L2_0     0x090f35c6 /* P1588 DM MAC Address Local2 0 Register */
#define BRPHY_TOP_1588_DM_MAC_L2_1     0x090f35c8 /* P1588 DM MAC Address Local2 0 Register */
#define BRPHY_TOP_1588_DM_MAC_L2_2     0x090f35ca /* P1588 DM MAC Address Local2 0 Register */
#define BRPHY_TOP_1588_DM_MAC_L3_0     0x090f35cc /* P1588 DM MAC Address Local3 0 Register */
#define BRPHY_TOP_1588_DM_MAC_L3_1     0x090f35ce /* P1588 DM MAC Address Local3 0 Register */
#define BRPHY_TOP_1588_DM_MAC_L3_2     0x090f35d0 /* P1588 DM MAC Address Local3 0 Register */
#define BRPHY_TOP_1588_DM_MAC_CTL_0    0x090f35d2 /* P1588 DM MAC cONTROL 0 Register */
#define BRPHY_TOP_1588_DM_MAC_CTL_1    0x090f35d4 /* P1588 DM MAC CONTROL 1 Register */
#define BRPHY_TOP_1588_DM_MAC_CTL_2    0x090f35d6 /* P1588 DM MAC CONTROL 2 Register */
#define BRPHY_TOP_1588_HEARTBEAT_3     0x090f35d8 /* P1588 Heartbeat Register(3) */
#define BRPHY_TOP_1588_HEARTBEAT_4     0x090f35da /* P1588 Heartbeat Register(4) */
#define BRPHY_TOP_1588_INBAND_CNTL_0   0x090f35dc /* P1588 Inband Control Port0 Register */
#define BRPHY_TOP_1588_INBAND_CNTL_1   0x090f35de /* P1588 Inband Control Port1 Register */
#define BRPHY_TOP_1588_INBAND_CNTL_2   0x090f35e0 /* P1588 Inband Control Port2 Register */
#define BRPHY_TOP_1588_INBAND_CNTL_3   0x090f35e2 /* P1588 Inband Control Port3 Register */
#define BRPHY_TOP_1588_INBAND_CNTL_4   0x090f35e4 /* P1588 Inband Control Port4 Register */
#define BRPHY_TOP_1588_INBAND_CNTL_5   0x090f35e6 /* P1588 Inband Control Port5 Register */
#define BRPHY_TOP_1588_INBAND_CNTL_6   0x090f35e8 /* P1588 Inband Control Port6 Register */
#define BRPHY_TOP_1588_INBAND_CNTL_7   0x090f35ea /* P1588 Inband Control Port7 Register */
#define BRPHY_TOP_1588_MEM_COUNTER     0x090f35ec /* P1588 Memory Counter Register */
#define BRPHY_TOP_1588_TIMESTAMP_DELTA 0x090f35ee /* P1588 Timestamp Delta Register */
#define BRPHY_TOP_1588_SOP_SEL         0x090f35f0 /* P1588 SOP Selection Register */
#define BRPHY_TOP_1588_TIME_STAMP_INFO_3 0x090f35f2 /* P1588 Time Stamp Register Info (3) */
#define BRPHY_TOP_1588_TIME_STAMP_INFO_4 0x090f35f4 /* P1588 Time Stamp Register Info (4) */
#define BRPHY_TOP_1588_TIME_STAMP_INFO_5 0x090f35f6 /* P1588 Time Stamp Register Info (5) */
#define BRPHY_TOP_1588_TIME_STAMP_INFO_6 0x090f35f8 /* P1588 Time Stamp Register Info (6) */
#define BRPHY_TOP_1588_TIME_STAMP_INFO_7 0x090f35fa /* P1588 Time Stamp Register Info (7) */
#define BRPHY_TOP_1588_TIME_STAMP_INFO_8 0x090f35fc /* P1588 Time Stamp Register Info (8) */
#define BRPHY_TOP_1588_INBAND_SPARE1   0x090f35fe /* P1588 Inband Spare1 Register */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_BR_CL22_IEEE
 ***************************************************************************/
#define BRPHY0_BR_CL22_IEEE_MII_CTRL   0x090fffc0 /* BR_LRE_Control_Register */
#define BRPHY0_BR_CL22_IEEE_MII_STAT   0x090fffc2 /* BR_LRE_Status_Register */
#define BRPHY0_BR_CL22_IEEE_PHY_ID_MSB 0x090fffc4 /* PHY_Identifier_MSB_Register */
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB 0x090fffc6 /* PHY_Identifier_LSB_Register */
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP 0x090fffc8 /* LDS_Advertised_Ability_Register (Base Page) */
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL 0x090fffca /* LDS_Advertised_Control_Register */
#define BRPHY0_BR_CL22_IEEE_LDS_ABILITY 0x090fffcc /* LDS_Ability_Register (Next Page) */
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP 0x090fffce /* LDS_Link_Partner_Ability_Base_Page_Register (Base Page) */
#define BRPHY0_BR_CL22_IEEE_LDS_LP_MSG_NXTP 0x090fffd0 /* LDS_Link_Partners_Nxt_Pg_Msg_Register (Next Page) */
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP 0x090fffd2 /* LDS_Link_Partner_Ability_Nxt_Pg_Register (Next Page) */
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP 0x090fffd4 /* LDS_Expansion_Register */
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT 0x090fffd6 /* IEEE_Extended_Status_Register */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_CL45DEV1
 ***************************************************************************/
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1  0x09420000 /* IEEE PMA/PMD CONTROL 1 REGISTER (REG 1.0) */
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1   0x09420002 /* IEEE PMA/PMD STATUS 1 REGISTER  (REG 1.1) */
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID0 0x09420004 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 0 (REG 1.2) */
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1 0x09420006 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 1 (REG 1.3) */
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0  0x0942000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 1.5) */
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1  0x0942000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 1.6) */
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID0 0x0942001c /* PMA/PMD PACKAGE IDENTIFIER (REG 1.14) */
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID1 0x0942001e /* PMA/PMD PACKAGE IDENTIFIER (REG 1.15) */
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP 0x09420e10 /* TimeSync PMA/PMD capability (REG 1.1800) */
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x09420e12 /* Maximum PMA/PMD transmit path data delay, lower (REG 1.1801) */
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x09420e14 /* Maximum PMA/PMD transmit path data delay, upper (REG 1.1802) */
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x09420e16 /* Minimum PMA/PMD transmit path data delay, lower (REG 1.1803) */
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x09420e18 /* Minimum PMA/PMD transmit path data delay, upper (REG 1.1804) */
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x09420e1a /* Maximum PMA/PMD receive path data delay, lower (REG 1.1805) */
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x09420e1c /* Maximum PMA/PMD receive path data delay, upper (REG 1.1806) */
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x09420e1e /* Minimum PMA/PMD receive path data delay, lower (REG 1.1807) */
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x09420e20 /* Minimum PMA/PMD receive path data delay, upper (REG 1.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_CL45DEV3
 ***************************************************************************/
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1  0x09460000 /* IEEE PCS CONTROL 1 REGISTER (REG 3.0) */
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1   0x09460002 /* IEEE PCS STATUS 1 REGISTER  (REG 3.1) */
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID0 0x09460004 /* IEEE PCS DEVICE IDENTIFIER PART 0 (REG 3.2) */
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1 0x09460006 /* IEEE PCS DEVICE IDENTIFIER PART 1 (REG 3.3) */
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0  0x0946000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 3.5) */
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1  0x0946000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 3.6) */
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID0 0x0946001c /* PCS PACKAGE IDENTIFIER (REG 3.14) */
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID1 0x0946001e /* PCS PACKAGE IDENTIFIER (REG 3.15) */
#define BRPHY1_CL45DEV3_PCS_EEE_CAP    0x09460028 /* PCS_EEE_CAP(REG 3.20) */
#define BRPHY1_CL45DEV3_PCS_EEE_WAKE_ERR_CNT 0x0946002c /* PCS_EEE_Wake_Err_Cnt(REG 3.22) */
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP 0x09460e10 /* TimeSync PCS capability (REG 3.1800) */
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x09460e12 /* Maximum PCS transmit path data delay, lower (REG 3.1801) */
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x09460e14 /* Maximum PCS transmit path data delay, upper (REG 3.1802) */
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x09460e16 /* Minimum PCS transmit path data delay, lower (REG 3.1803) */
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x09460e18 /* Minimum PCS transmit path data delay, upper (REG 3.1804) */
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x09460e1a /* Maximum PCS receive path data delay, lower (REG 3.1805) */
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x09460e1c /* Maximum PCS receive path data delay, upper (REG 3.1806) */
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x09460e1e /* Minimum PCS receive path data delay, lower (REG 3.1807) */
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x09460e20 /* Minimum PCS receive path data delay, upper (REG 3.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_CL45DEV7
 ***************************************************************************/
#define BRPHY1_CL45DEV7_AN_CTRL        0x094e0000 /* Auto Neg Extended Next Page Control     (0x0000) (REG 7.0) */
#define BRPHY1_CL45DEV7_AN_STAT        0x094e0002 /* AN Status (0x0001) (REG 7.1) */
#define BRPHY1_CL45DEV7_AN_DEV_ID_LSB  0x094e0004 /* Auto Neg Device Identifier Lower 16 bit (0x0002) (REG 7.2) */
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB  0x094e0006 /* Auto Neg Device Identifier Upper 16 bit (0x0003) (REG 7.3) */
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB 0x094e000a /* Auto Neg Device In Package Lower 16 bit (0x0005) (REG 7.5) */
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB 0x094e000c /* Auto Neg Device In Package Upper 16 bit (0x0006) (REG 7.6) */
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_LSB 0x094e001c /* Auto Neg Package ID Lower 16 bit(0x000e) (REG 7.14) */
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_MSB 0x094e001e /* Auto Neg Package ID Upper 16 bit(0x000f) (REG 7.15) */
#define BRPHY1_CL45DEV7_AN_AD          0x094e0020 /* Auto Neg AD(0x0010) (REG 7.16) */
#define BRPHY1_CL45DEV7_AN_LPA         0x094e0026 /* AN LP base page ability (0x0013) (REG 7.19) */
#define BRPHY1_CL45DEV7_AN_XNPA        0x094e002c /* AN XNP transmit A (0x0016) (REG 7.22) */
#define BRPHY1_CL45DEV7_AN_XNPB        0x094e002e /* AN XNP transmit B (0x0017) (REG 7.23) */
#define BRPHY1_CL45DEV7_AN_XNPC        0x094e0030 /* AN XNP transmit C (0x0018) (REG 7.24) */
#define BRPHY1_CL45DEV7_LP_XNPA        0x094e0032 /* AN LP XNP ability A (0x0019) (REG 7.25) */
#define BRPHY1_CL45DEV7_LP_XNPB        0x094e0034 /* AN LP XNP ability B (0x001a) (REG 7.26) */
#define BRPHY1_CL45DEV7_LP_XNPC        0x094e0036 /* AN LP XNP ability C (0x001b) (REG 7.27) */
#define BRPHY1_CL45DEV7_TENG_AN_CTRL   0x094e0040 /* 10G Base-T AN Control Register (0x0020) (REG 7.32) */
#define BRPHY1_CL45DEV7_TENG_AN_STAT   0x094e0042 /* 10G Base-T AN Status Register  (0x0021) (REG 7.33) */
#define BRPHY1_CL45DEV7_EEE_ADV        0x094e0078 /* EEE Advertisement (0x003C) (REG 7.60 ???) */
#define BRPHY1_CL45DEV7_EEE_LP_ADV     0x094e007a /* EEE Link Partner Advertisement (0x003D) (REG 7.61 ???) */
#define BRPHY1_CL45DEV7_EEE_MODE_CTL   0x094e007c /* EEE Mode Control (0x003E) (REG 7.62 ???) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_CL45VEN
 ***************************************************************************/
#define BRPHY1_CL45VEN_FORCE_LINK      0x094f0000 /* Force Link Register */
#define BRPHY1_CL45VEN_SELECTIVE_RESET 0x094f0002 /* Selective Reset Register */
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS 0x094f0004 /* Test State Machine For Extended Next Pages Register --mvadkert */
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS 0x094f0006 /* Test State Machine For Next Pages Register --mvadkert */
#define BRPHY1_CL45VEN_AN_MAN_TEST     0x094f0032 /* Auto Negotiation Manual Test Register */
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A 0x094f0034 /* Auto Negotiation Manual Link Partners Abilities Register A */
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B 0x094f0036 /* Auto Negotiation Manual Link Partners Abilities Register B */
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_A 0x094f0038 /* Link Partner Next Page */
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_B 0x094f003a /* Link Partner Next Page (cont.) */
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_C 0x094f003c /* Link Partner Next Page (cont.) */
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_D 0x094f003e /* Link Partner Next Page (cont.) */
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_E 0x094f0040 /* Link Partner Next Page (cont.) */
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_F 0x094f0042 /* Link Partner Next Page (cont.) */
#define BRPHY1_CL45VEN_EPON_CTRL_REG   0x094f0046 /* EPON mode control register */
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A 0x094f0060 /* EEE Test Control Register A eee_test_control_bus[15:0] */
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B 0x094f0062 /* EEE Test Control Register B eee_test_control_bus[31:16] */
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C 0x094f0064 /* EEE Test Control Register C eee_test_control_bus[47:32] */
#define BRPHY1_CL45VEN_EEE_SPARE_1     0x094f0076 /* EEE Spare Register 1 */
#define BRPHY1_CL45VEN_EEE_SPARE_2     0x094f0078 /* EEE Spare Register 2 */
#define BRPHY1_CL45VEN_EEE_CONTROL     0x094f007a /* EEE Control Register */
#define BRPHY1_CL45VEN_EEE_RES_STAT    0x094f007c /* EEE Resolution Status Register */
#define BRPHY1_CL45VEN_LPI_MODE_CNTR   0x094f007e /* LPI Mode Counter Register */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_A 0x094f0080 /* Local Device Message 5 */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_B 0x094f0082 /* Local Device Message 5 cont. */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_C 0x094f0084 /* Local Device Message 5 cont. */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_D 0x094f0086 /* Local Device Message 5 cont. */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A 0x094f0088 /* Link Partner Message 5 */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B 0x094f008a /* Link Partner Message 5 cont. */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C 0x094f008c /* Link Partner Message 5 cont. */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D 0x094f008e /* Link Partner Message 5 cont. */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_A 0x094f0090 /* Local Device Message 6 */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B 0x094f0092 /* Local Device Message 6 cont. */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C 0x094f0094 /* Local Device Message 6 cont. */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_D 0x094f0096 /* Local Device Message 6 cont. */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A 0x094f0098 /* Link Partner Message 6 */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B 0x094f009a /* Link Partner Message 6 cont. */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C 0x094f009c /* Link Partner Message 6 cont. */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D 0x094f009e /* Link Partner Message 6 cont. */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_GPHY_CORE
 ***************************************************************************/
#define BRPHY1_GPHY_CORE_BASE10        0x094f2000 /* PHY_Extended_ctl_Register */
#define BRPHY1_GPHY_CORE_BASE11        0x094f2002 /* PHY_Extended_Status_Register (copper side only) */
#define BRPHY1_GPHY_CORE_BASE12        0x094f2004 /* Receive_Error_Cntr_Register */
#define BRPHY1_GPHY_CORE_BASE13        0x094f2006 /* False_Carrier_Sense_Cntr_Register */
#define BRPHY1_GPHY_CORE_BASE14        0x094f2008 /* Local_Remote_Receiver_NOT_OK_Cntrs_Register */
#define BRPHY1_GPHY_CORE_EXP45         0x094f200a /* Pattern Generator Control Register */
#define BRPHY1_GPHY_CORE_EXP46         0x094f200b /* Pattern Generator Status Register */
#define BRPHY1_GPHY_CORE_BASE19        0x094f2012 /* Auxiliary Status Summary (copper side only) */
#define BRPHY1_GPHY_CORE_BASE1A        0x094f2014 /* Interrupt Status Register (copper side only) */
#define BRPHY1_GPHY_CORE_BASE1B        0x094f2016 /* Interrupt Mask Register */
#define BRPHY1_GPHY_CORE_BASE1D_SHD    0x094f2018 /* HCD Status Register */
#define BRPHY1_GPHY_CORE_BASE1D        0x094f201a /* Master/Slave Seed Register */
#define BRPHY1_GPHY_CORE_BASE1E        0x094f201c /* Test1_Register */
#define BRPHY1_GPHY_CORE_BASE1F        0x094f201e /* Test2_Register */
#define BRPHY1_GPHY_CORE_SHD1C_00      0x094f2020 /* Cabletron LED Register (Shadow Register Selector = "00h") */
#define BRPHY1_GPHY_CORE_SHD1C_01      0x094f2022 /* TVCO Selection Register (Shadow Register Selector = "01h") */
#define BRPHY1_GPHY_CORE_SHD1C_02      0x094f2024 /* reserved Control 1 Register (Shadow Register Selector = "02h") */
#define BRPHY1_GPHY_CORE_SHD1C_03      0x094f2026 /* Clock Alignment Control Regsiter (Shadow Register Selector = "03h") */
#define BRPHY1_GPHY_CORE_SHD1C_04      0x094f2028 /* reserved Control 2 Register (Shadow Register Selector = "04h") */
#define BRPHY1_GPHY_CORE_SHD1C_05      0x094f202a /* reserved Control 3 Register (Shadow Register Selector = "05h") */
#define BRPHY1_GPHY_CORE_SHD1C_06      0x094f202c /* Tdr Control 1 Register (Shadow Register Selector = "06h") */
#define BRPHY1_GPHY_CORE_SHD1C_07      0x094f202e /* Tdr Control 2 Register (Shadow Register Selector = "07h") */
#define BRPHY1_GPHY_CORE_SHD1C_08      0x094f2030 /* Led Status Register (Shadow Register Selector = "08h") */
#define BRPHY1_GPHY_CORE_SHD1C_09      0x094f2032 /* Led Control Register (Shadow Register Selector = "09h") */
#define BRPHY1_GPHY_CORE_SHD1C_0A      0x094f2034 /* Auto-Power Down Register (Shadow Register Selector = "0ah") */
#define BRPHY1_GPHY_CORE_SHD1C_0B      0x094f2036 /* reserved Control 4 Register (Shadow Register Selector = "0bh") */
#define BRPHY1_GPHY_CORE_SHD1C_0D      0x094f203a /* LED Selector 1 Register (Shadow Register Selector = "0dh") */
#define BRPHY1_GPHY_CORE_SHD1C_0E      0x094f203c /* LED Selector 2 Register (Shadow Register Selector = "0eh") */
#define BRPHY1_GPHY_CORE_SHD1C_0F      0x094f203e /* LED GPIO Control/Status Register (Shadow Register Selector = "0fh") */
#define BRPHY1_GPHY_CORE_SHD1C_10      0x094f2040 /* Cisco Enhanced Linkstatus Mode Control Register (Shadow Register Selector = "10h") */
#define BRPHY1_GPHY_CORE_SHD1C_1F      0x094f2042 /* Mode Control Register (Shadow Register Selector = "1fh") */
#define BRPHY1_GPHY_CORE_SHD18_000     0x094f2050 /* Auxiliary Control Register (Shadow Register Selector = "000") */
#define BRPHY1_GPHY_CORE_SHD18_001     0x094f2052 /* 10 Base-T Register (Shadow Register Selector = "001") */
#define BRPHY1_GPHY_CORE_SHD18_010     0x094f2054 /* Power/MII Control Register (Shadow Register Selector = "010") */
#define BRPHY1_GPHY_CORE_SHD18_011     0x094f2056 /* IP Phone Register  (Shadow Register Selector = "011") */
#define BRPHY1_GPHY_CORE_SHD18_100     0x094f2058 /* Misc Test Register  1 (Shadow Register Selector = "100") */
#define BRPHY1_GPHY_CORE_SHD18_101     0x094f205a /* Misc Test Register  2 (Shadow Register Selector = "101") */
#define BRPHY1_GPHY_CORE_SHD18_110     0x094f205c /* Manual IP Phone Seed Register (Shadow Register Selector = "110") */
#define BRPHY1_GPHY_CORE_SHD18_111     0x094f205e /* Miscellanous Control Register (Shadow Register Selector = "111") */
#define BRPHY1_GPHY_CORE_EXP00         0x094f2060 /* Transmit Packet Counter */
#define BRPHY1_GPHY_CORE_EXP01         0x094f2062 /* Expansion Interrupt Status */
#define BRPHY1_GPHY_CORE_EXP02         0x094f2064 /* Expansion Interrupt Mask */
#define BRPHY1_GPHY_CORE_EXP03         0x094f2066 /* Spare Registers */
#define BRPHY1_GPHY_CORE_EXP04         0x094f2068 /* Bicolor LED Selectors */
#define BRPHY1_GPHY_CORE_EXP05         0x094f206a /* Bicolor LED Flash Rate Controls */
#define BRPHY1_GPHY_CORE_EXP06         0x094f206c /* Bicolor LED Programmable Blink Controls */
#define BRPHY1_GPHY_CORE_EXP07         0x094f206e /* Far End Fault */
#define BRPHY1_GPHY_CORE_EXP08         0x094f2070 /* 10BT Controls */
#define BRPHY1_GPHY_CORE_EXP09         0x094f2072 /* AMRR Controls */
#define BRPHY1_GPHY_CORE_EXP0A         0x094f2074 /* DAC TEMPLATE Controls */
#define BRPHY1_GPHY_CORE_EXP0B         0x094f2076 /* External Status */
#define BRPHY1_GPHY_CORE_EXP0C         0x094f2078 /* Spare Registers */
#define BRPHY1_GPHY_CORE_EXP30         0x094f2080 /* Late Collision Counters Status Register */
#define BRPHY1_GPHY_CORE_EXP31         0x094f2082 /* Late Collision Counter [64:95] */
#define BRPHY1_GPHY_CORE_EXP32         0x094f2084 /* Late Collision Counter [96:127] */
#define BRPHY1_GPHY_CORE_EXP33         0x094f2086 /* Late Collision Counter [128:191] */
#define BRPHY1_GPHY_CORE_EXP34         0x094f2088 /* Late Collision Counter [192:319] */
#define BRPHY1_GPHY_CORE_EXP35         0x094f208a /* Late Collision Counter Threshold Register */
#define BRPHY1_GPHY_CORE_EXP36         0x094f208c /* Clock PPM Detection between Recovery and Transmit Clocks */
#define BRPHY1_GPHY_CORE_EXP37         0x094f208e /* Clock PPM Detection between GTX_CLK and Transmit Clocks */
#define BRPHY1_GPHY_CORE_EXP38         0x094f2090 /* IP PHONE Cable Length Status Register */
#define BRPHY1_GPHY_CORE_EXP42         0x094f20a2 /* Operating Mode Status */
#define BRPHY1_GPHY_CORE_EXP5F         0x094f20be /* PLL Frequency Offset Testmode Control */
#define BRPHY1_GPHY_CORE_EXP70         0x094f20e0 /* SOFT-RESET */
#define BRPHY1_GPHY_CORE_EXP71         0x094f20e2 /* Serial LED Control 1 */
#define BRPHY1_GPHY_CORE_EXP72         0x094f20e4 /* Serial LED Control 2 */
#define BRPHY1_GPHY_CORE_EXP73         0x094f20e6 /* LED Gating 2 (Used for dual-media applications) */
#define BRPHY1_GPHY_CORE_EXP74         0x094f20e8 /* LED Programmable Current Mode Control */
#define BRPHY1_GPHY_CORE_EXP75         0x094f20ea /* CED LED Error Mask */
#define BRPHY1_GPHY_CORE_EXP78         0x094f20f0 /* Misc Extended Control */
#define BRPHY1_GPHY_CORE_EXP7B         0x094f20f6 /* I2C Control */
#define BRPHY1_GPHY_CORE_EXP7C         0x094f20f8 /* I2C Status */
#define BRPHY1_GPHY_CORE_EXP7F         0x094f20fe /* External MACSec Interface Control */
#define BRPHY1_GPHY_CORE_ALIAS_18      0x094f2100 /* Alias to MII Reg 18 */
#define BRPHY1_GPHY_CORE_ALIAS_19      0x094f2102 /* Alias to MII Reg 19 */
#define BRPHY1_GPHY_CORE_ALIAS_1A      0x094f2104 /* Alias to MII Reg 1a */
#define BRPHY1_GPHY_CORE_ALIAS_1B      0x094f2106 /* Alias to MII Reg 1b */
#define BRPHY1_GPHY_CORE_ALIAS_1C      0x094f2108 /* Alias to MII Reg 1c */
#define BRPHY1_GPHY_CORE_ALIAS_1D      0x094f210a /* Alias to MII Reg 1d */
#define BRPHY1_GPHY_CORE_REG_MAP_CTL   0x094f210e /* MII Registers 10-1D mapping control */
#define BRPHY1_GPHY_CORE_EXP98         0x094f2130 /* First Slice of Quad-GPHY only): CAL-BIAS Status */
#define BRPHY1_GPHY_CORE_EXP9C         0x094f2138 /* SMII Control */
#define BRPHY1_GPHY_CORE_BT_LINK_FIX   0x094f214a /* 10BT LINK FIX Register */
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG 0x094f214c /* SyncE+ Debug */
#define BRPHY1_GPHY_CORE_SYNCE_PLUS    0x094f214e /* SyncE+ Status and Control */
#define BRPHY1_GPHY_CORE_EXPA8         0x094f2150 /* ADAPTIVE BIAS CONTROL */
#define BRPHY1_GPHY_CORE_EXPA9         0x094f2152 /* spare register */
#define BRPHY1_GPHY_CORE_EXPAA         0x094f2154 /* EEE Statistic timer 12hours lpi */
#define BRPHY1_GPHY_CORE_EXPAB         0x094f2156 /* EEE Statistic timer 12hours local */
#define BRPHY1_GPHY_CORE_EXPAC         0x094f2158 /* EEE Statistic loc lpi req 0_to_1 counter */
#define BRPHY1_GPHY_CORE_EXPAD         0x094f215a /* EEE Statistic rem lpi_req 0_to_1 counter */
#define BRPHY1_GPHY_CORE_EXPAE         0x094f215c /* spare register */
#define BRPHY1_GPHY_CORE_EXPAF         0x094f215e /* EEE Statistic counters ctrl/status */
#define BRPHY1_GPHY_CORE_EXPB0         0x094f2160 /* Bias Control 0 */
#define BRPHY1_GPHY_CORE_EXPB1         0x094f2162 /* Bias Control 1 */
#define BRPHY1_GPHY_CORE_EXPB2         0x094f2164 /* Bias Control 2 */
#define BRPHY1_GPHY_CORE_EXPE3         0x094f2166 /* TX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY1_GPHY_CORE_EXPE4         0x094f2168 /* TX PCS Delay 10BT (copper side) */
#define BRPHY1_GPHY_CORE_EXPE5         0x094f216a /* TX PCS Delay (fiber side) */
#define BRPHY1_GPHY_CORE_EXPE6         0x094f216c /* RX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY1_GPHY_CORE_EXPE7         0x094f216e /* RX PCS Delay 10BT (copper side) */
#define BRPHY1_GPHY_CORE_EXPE8         0x094f2170 /* RX PCS Delay (fiber side) */
#define BRPHY1_GPHY_CORE_EXPE9         0x094f2172 /* P1588 TX/RX Cycle Delay */
#define BRPHY1_GPHY_CORE_EXPE0         0x094f2174 /* TX PMA/PMD Delay (copper side) */
#define BRPHY1_GPHY_CORE_EXPE1         0x094f2176 /* TX PMA/PMD Delay (fiber side) */
#define BRPHY1_GPHY_CORE_EXPE2         0x094f2178 /* RX PMA/PMD Delay (copper side) */
#define BRPHY1_GPHY_CORE_EXPEA         0x094f217a /* TX/RX Adjustable Cycle Delay */
#define BRPHY1_GPHY_CORE_LED_PRA_MODE  0x094f2180 /* LED Proportional Rate Activity Control */
#define BRPHY1_GPHY_CORE_FIFO_CTL      0x094f2182 /* FIFO Control Register */
#define BRPHY1_GPHY_CORE_EXPD8         0x094f21b0 /* Halting agc/enc ctrl reg */
#define BRPHY1_GPHY_CORE_EXPF0         0x094f21e0 /* RGMII IBS Control */
#define BRPHY1_GPHY_CORE_EXPF5         0x094f21ea /* Time Sync */
#define BRPHY1_GPHY_CORE_EXPF6         0x094f21ec /* Analog Power Control Status */
#define BRPHY1_GPHY_CORE_EXPF7         0x094f21ee /* Auto-power Down Control Status */
#define BRPHY1_GPHY_CORE_EXPF8         0x094f21f0 /* Trim Settings from Fuse & to Bias Block */
#define BRPHY1_GPHY_CORE_EXPF9         0x094f21f2 /* reserved Register Bits */
#define BRPHY1_GPHY_CORE_EXPFA         0x094f21f4 /* Hidden Identifier */
#define BRPHY1_GPHY_CORE_EXPFB         0x094f21f6 /* TDR Override Values */
#define BRPHY1_GPHY_CORE_EXPFC         0x094f21f8 /*  */
#define BRPHY1_GPHY_CORE_EXPFD         0x094f21fa /* Clock gating control override value */
#define BRPHY1_GPHY_CORE_EXPFE         0x094f21fc /* Clock gating control override enable */
#define BRPHY1_GPHY_CORE_EXPFF         0x094f21fe /* Analog power control override */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_DSP_TAP
 ***************************************************************************/
#define BRPHY1_DSP_TAP_TAP0_C0         0x094f2200 /* AGC Control/Status Register A (x4) */
#define BRPHY1_DSP_TAP_TAP0_C1         0x094f2202 /* AGC Control/Status Register A (x4) */
#define BRPHY1_DSP_TAP_TAP0_C2         0x094f2204 /* AGC Control/Status Register A (x4) */
#define BRPHY1_DSP_TAP_TAP0_C3         0x094f2206 /* AGC Control/Status Register A (x4) */
#define BRPHY1_DSP_TAP_TAP1            0x094f2208 /* IPRF Control register (x1) */
#define BRPHY1_DSP_TAP_TAP2_C0         0x094f2210 /* MSE Status Register (x4) */
#define BRPHY1_DSP_TAP_TAP2_C1         0x094f2212 /* MSE Status Register (x4) */
#define BRPHY1_DSP_TAP_TAP2_C2         0x094f2214 /* MSE Status Register (x4) */
#define BRPHY1_DSP_TAP_TAP2_C3         0x094f2216 /* MSE Status Register (x4) */
#define BRPHY1_DSP_TAP_TAP3_C0         0x094f2218 /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY1_DSP_TAP_TAP3_C1         0x094f221a /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY1_DSP_TAP_TAP3_C2         0x094f221c /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY1_DSP_TAP_TAP3_C3         0x094f221e /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY1_DSP_TAP_TAP4_C0         0x094f2220 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY1_DSP_TAP_TAP4_C1         0x094f2222 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY1_DSP_TAP_TAP4_C2         0x094f2224 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY1_DSP_TAP_TAP4_C3         0x094f2226 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY1_DSP_TAP_TAP5_C0         0x094f2228 /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY1_DSP_TAP_TAP5_C1         0x094f222a /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY1_DSP_TAP_TAP5_C2         0x094f222c /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY1_DSP_TAP_TAP5_C3         0x094f222e /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY1_DSP_TAP_TAP6            0x094f2230 /* CFC Deadman Disable */
#define BRPHY1_DSP_TAP_TAP7_C0         0x094f2238 /* BIST TEST 0 */
#define BRPHY1_DSP_TAP_TAP7_C1         0x094f223a /* BIST TEST 1 */
#define BRPHY1_DSP_TAP_TAP7_C2         0x094f223c /* BIST TEST 2 */
#define BRPHY1_DSP_TAP_TAP8_C0         0x094f2240 /* ABIST TEST 0 */
#define BRPHY1_DSP_TAP_TAP8_C1         0x094f2242 /* ABIST TEST 1 */
#define BRPHY1_DSP_TAP_TAP8_C2         0x094f2244 /* ABIST TEST 2 */
#define BRPHY1_DSP_TAP_TAP8_C3         0x094f2246 /* BR HPF Control */
#define BRPHY1_DSP_TAP_TAP9            0x094f2248 /* Frequency Control/Status Register LSBs (x1) */
#define BRPHY1_DSP_TAP_TAP10           0x094f224a /* PLL Bandwidth Control/Status and Path Metric Reset Register (x1) */
#define BRPHY1_DSP_TAP_TAP11           0x094f224c /* PLL RCLK and TCLK Offset Freeze Register (x1) */
#define BRPHY1_DSP_TAP_TAP12_C0        0x094f2250 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY1_DSP_TAP_TAP12_C1        0x094f2252 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY1_DSP_TAP_TAP12_C2        0x094f2254 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY1_DSP_TAP_TAP12_C3        0x094f2256 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY1_DSP_TAP_TAP13           0x094f2258 /* HPF Bandwidth Control and Disable ADC LSBs (x1) */
#define BRPHY1_DSP_TAP_TAP14           0x094f225a /* MSE Threshold Register  #1 (x1) */
#define BRPHY1_DSP_TAP_TAP15           0x094f225c /* MSE Threshold Register #2 (x1) */
#define BRPHY1_DSP_TAP_TAP16_C0        0x094f2260 /* Logic Analyzer trigger delay (x1) */
#define BRPHY1_DSP_TAP_TAP16_C1        0x094f2262 /* BIST CRC Monitor (x4) */
#define BRPHY1_DSP_TAP_TAP16_C2        0x094f2264 /* BIST CRC Monitor (x4) */
#define BRPHY1_DSP_TAP_TAP16_C3        0x094f2266 /* BIST CRC Monitor (x4) */
#define BRPHY1_DSP_TAP_TAP17_C0        0x094f2268 /* Testmode testvalue (aliased with logic analyzer state selects) */
#define BRPHY1_DSP_TAP_TAP17_C1        0x094f226a /* Testmode and logic analyzer controls #1 */
#define BRPHY1_DSP_TAP_TAP17_C2        0x094f226c /* Logic analyzer controls #2 */
#define BRPHY1_DSP_TAP_TAP17_C3        0x094f226e /* Testmode and logic analyzer controls #3 */
#define BRPHY1_DSP_TAP_TAP18_C0        0x094f2270 /* Peak Noise detector (x4) */
#define BRPHY1_DSP_TAP_TAP18_C1        0x094f2272 /* Peak Noise detector (x4) */
#define BRPHY1_DSP_TAP_TAP18_C2        0x094f2274 /* Peak Noise detector (x4) */
#define BRPHY1_DSP_TAP_TAP18_C3        0x094f2276 /* Peak Noise detector (x4) */
#define BRPHY1_DSP_TAP_TAP20           0x094f2278 /* Echo Minimum Length and LMS/FIR delay adjustments (x1) */
#define BRPHY1_DSP_TAP_TAP21           0x094f227a /* Phy Control Monitors #1 (x1) */
#define BRPHY1_DSP_TAP_TAP22           0x094f227c /* Phy Control Monitors #2 (x1) */
#define BRPHY1_DSP_TAP_TAP23           0x094f227e /* Phy Control Monitors #3 (x1) */
#define BRPHY1_DSP_TAP_TAP24           0x094f2280 /* Phy Control Output Overrides #1 (x1) */
#define BRPHY1_DSP_TAP_TAP25           0x094f2282 /* Phy Control Output Overrides #2 (x1) */
#define BRPHY1_DSP_TAP_TAP26           0x094f2284 /* Phy Control Input Overrides #1 (x1) */
#define BRPHY1_DSP_TAP_TAP27           0x094f2286 /* Phy Control Input Overrides #2 (x1) */
#define BRPHY1_DSP_TAP_TAP28           0x094f2288 /* Phy Control Output Overrides #3 (x1) */
#define BRPHY1_DSP_TAP_TAP29           0x094f228a /* Phy Control Force State/Timers/Alternate Behaviour Register #1 (x1) */
#define BRPHY1_DSP_TAP_TAP30           0x094f228c /* Phy Control Force State/Timers/Alternate Behaviour Register #2 (x1) */
#define BRPHY1_DSP_TAP_TAP31_C0        0x094f2290 /* Channel Swap Override */
#define BRPHY1_DSP_TAP_TAP32_C0        0x094f2298 /* Transmit Testmode Sync Generation (x1) */
#define BRPHY1_DSP_TAP_FDFE_OV_RD      0x094f229a /* FDFE Override/Read Control Register */
#define BRPHY1_DSP_TAP_FDFE_COEFF      0x094f229c /* FDFE Coefficient Read Back Register */
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD 0x094f229e /* FDFE Beta Threshold Control */
#define BRPHY1_DSP_TAP_TAP33_C0        0x094f22a0 /* eee dsp test */
#define BRPHY1_DSP_TAP_TAP33_C1        0x094f22a2 /* eee sigdet */
#define BRPHY1_DSP_TAP_TAP33_C2        0x094f22a4 /* eee_lpi_timers */
#define BRPHY1_DSP_TAP_TAP33_C3        0x094f22a6 /* spare register */
#define BRPHY1_DSP_TAP_TAP34_C0        0x094f22a8 /* eee frequency control */
#define BRPHY1_DSP_TAP_TAP34_C1        0x094f22aa /* eee Gigabit Mode BW control */
#define BRPHY1_DSP_TAP_TAP34_C2        0x094f22ac /* eee 100TX Mode BW control */
#define BRPHY1_DSP_TAP_TAP34_C3        0x094f22ae /* phasectl TPO monitor */
#define BRPHY1_DSP_TAP_TAP35_C0        0x094f22b0 /* eee 100Base-tx timer control 1 */
#define BRPHY1_DSP_TAP_TAP35_C1        0x094f22b2 /* eee 100Base-tx timer control 2 */
#define BRPHY1_DSP_TAP_TAP35_C2        0x094f22b4 /* eee 100Base-tx timer misc control */
#define BRPHY1_DSP_TAP_TAP35_C3        0x094f22b6 /* pcs_lpi_test */
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0  0x094f22b8 /* Filter Freeze/Disable per channel Control */
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1  0x094f22ba /* Filter Freeze/Disable per channel Control */
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2  0x094f22bc /* Filter Freeze/Disable per channel Control */
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3  0x094f22be /* Filter Freeze/Disable per channel Control */
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0 0x094f22c0 /* FFEX Freeze/Disable per channel Control */
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1 0x094f22c2 /* FFEX Freeze/Disable per channel Control */
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2 0x094f22c4 /* FFEX Freeze/Disable per channel Control */
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3 0x094f22c6 /* FFEX Freeze/Disable per channel Control */
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL 0x094f22c8 /* EMI Datapath Control */
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2 0x094f22ca /* EMI Datapath Control2 */
#define BRPHY1_DSP_TAP_FFEX_CTL        0x094f22cc /* FFE X-tap Control */
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0 0x094f22ce /* Phycontrol Breakpoint Control 0 */
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1 0x094f22d0 /* Phycontrol Breakpoint Control 1 */
#define BRPHY1_DSP_TAP_FILTER_ADDR     0x094f2360 /* DSP Coefficient Address Register */
#define BRPHY1_DSP_TAP_FILTER_CTL      0x094f2362 /* DSP Control Register */
#define BRPHY1_DSP_TAP_FILTER_DATA     0x094f2364 /* DSP Coefficient Read/Write Port */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_PLL_CTRL
 ***************************************************************************/
#define BRPHY1_PLL_CTRL_PLLCTRL_0      0x094f2390 /* Analog pll control 0 */
#define BRPHY1_PLL_CTRL_PLLCTRL_1      0x094f2392 /* Analog pll control 1 */
#define BRPHY1_PLL_CTRL_PLLCTRL_2      0x094f2394 /* Analog pll control 2 */
#define BRPHY1_PLL_CTRL_PLLCTRL_3      0x094f2396 /* Analog pll control 3 */
#define BRPHY1_PLL_CTRL_PLLCTRL_4      0x094f2398 /* Analog pll control 4 */
#define BRPHY1_PLL_CTRL_PLLCTRL_5      0x094f239a /* Analog pll control 5 */
#define BRPHY1_PLL_CTRL_PLLCTRL_6      0x094f239c /* Analog pll control 6 */
#define BRPHY1_PLL_CTRL_PLL_STATUS_0   0x094f23a0 /* Analog PLL Status 0 */
#define BRPHY1_PLL_CTRL_PLL_STATUS_1   0x094f23a2 /* Analog PLL Status 1 */
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS 0x094f23a4 /* AFE Signal detect */
#define BRPHY1_PLL_CTRL_PLLCTRL_7      0x094f23a6 /* Analog pll control 7 */
#define BRPHY1_PLL_CTRL_PLLCTRL_8      0x094f23a8 /* Analog pll control 8 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_AFE_CTRL
 ***************************************************************************/
#define BRPHY1_AFE_CTRL_RXCONFIG_0     0x094f23c0 /* RXCONFIG 15:0 */
#define BRPHY1_AFE_CTRL_RXCONFIG_1     0x094f23c2 /* RXCONFIG 31:16 */
#define BRPHY1_AFE_CTRL_RXCONFIG_2     0x094f23c4 /* RXCONFIG 47:32 */
#define BRPHY1_AFE_CTRL_RXCONFIG_3     0x094f23c6 /* RXCONFIG 63:48 */
#define BRPHY1_AFE_CTRL_RXCONFIG_4     0x094f23c8 /* RXCONFIG 79:64 */
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP   0x094f23ca /* RXCONFIG 86:80 and LP tuning */
#define BRPHY1_AFE_CTRL_TX_CONFIG_0    0x094f23cc /* TXCONFIG 15:0 */
#define BRPHY1_AFE_CTRL_TX_CONFIG_1    0x094f23ce /* TXCONFIG 31:16 */
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_0   0x094f23d0 /* VDAC CURRENT Control 15:0 */
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_1   0x094f23d2 /* VDAC CURRENT Control 31:16 */
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_2   0x094f23d4 /* VDAC CURRENT Control 51:36 */
#define BRPHY1_AFE_CTRL_VDAC_OTHERS_0  0x094f23d6 /* VDAC CURRENT 35:32 and others */
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS 0x094f23d8 /* HPF trim and reserved bits */
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_0 0x094f23da /* TXCONFIG 15:0 */
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_1 0x094f23dc /* TXCONFIG 15:0 */
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_2 0x094f23de /* TXCONFIG 15:0 */
#define BRPHY1_AFE_CTRL_TEMPSEN_OTHERS 0x094f23e0 /* TEMPSEN_OTHERS 15:0 */
#define BRPHY1_AFE_CTRL_FUTURE_RSV     0x094f23e2 /* FUTURE_RSV 15:0 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_ECD_CTRL
 ***************************************************************************/
#define BRPHY1_ECD_CTRL_EXPC0          0x094f2540 /* ECD Control and Status */
#define BRPHY1_ECD_CTRL_EXPC1          0x094f2542 /* ECD Fault Type */
#define BRPHY1_ECD_CTRL_EXPC2          0x094f2544 /* ECD Pair A Length Results */
#define BRPHY1_ECD_CTRL_EXPC3          0x094f2546 /* ECD Pair B Length Results */
#define BRPHY1_ECD_CTRL_EXPC4          0x094f2548 /* ECD Pair C Length Results */
#define BRPHY1_ECD_CTRL_EXPC5          0x094f254a /* ECD Pair D Length Results */
#define BRPHY1_ECD_CTRL_EXPC6          0x094f254c /* ECD XTALK Map */
#define BRPHY1_ECD_CTRL_EXPC7          0x094f254e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPC8          0x094f2550 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPC9          0x094f2552 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPCA          0x094f2554 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPCB          0x094f2556 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPCC          0x094f2558 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPCD          0x094f255a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPCE          0x094f255c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPCF          0x094f255e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE0          0x094f2560 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE1          0x094f2562 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE2          0x094f2564 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE3          0x094f2566 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE4          0x094f2568 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE5          0x094f256a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE6          0x094f256c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE7          0x094f256e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE8          0x094f2570 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPE9          0x094f2572 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPEA          0x094f2574 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPEB          0x094f2576 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPEC          0x094f2578 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPED          0x094f257a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPEE          0x094f257c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY1_ECD_CTRL_EXPEF          0x094f257e /* ECD EXTRA RESERVED REGISTER */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_BR_CTRL
 ***************************************************************************/
#define BRPHY1_BR_CTRL_EXP90           0x094f2600 /* BroadReach LRE Misc Control */
#define BRPHY1_BR_CTRL_EXP91           0x094f2602 /* BroadReach LRE Misc Control */
#define BRPHY1_BR_CTRL_EXP92           0x094f2604 /* BroadReach LRE Misc Control */
#define BRPHY1_BR_CTRL_EXP93           0x094f2606 /* BroadReach LDS  Control */
#define BRPHY1_BR_CTRL_EXP94           0x094f2608 /* BroadReach LDS RX Control */
#define BRPHY1_BR_CTRL_EXP95           0x094f260a /* BroadReach LDS RX Control */
#define BRPHY1_BR_CTRL_EXP96           0x094f260c /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY1_BR_CTRL_EXP97           0x094f260e /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY1_BR_CTRL_EXP99           0x094f2612 /* BroadReach LDS Timer Control */
#define BRPHY1_BR_CTRL_EXP9A           0x094f2614 /* LDS Status */
#define BRPHY1_BR_CTRL_EXP9B           0x094f2616 /* BroadR-Reach PLL Control */
#define BRPHY1_BR_CTRL_EXP9D           0x094f261a /* EoC Internal Control 1 */
#define BRPHY1_BR_CTRL_EXP9E           0x094f261c /* LDS Length Threshold 0 */
#define BRPHY1_BR_CTRL_EXP9F           0x094f261e /* LDS Length Threshold 1 */
#define BRPHY1_BR_CTRL_EXPA0           0x094f2620 /* HLDS register, LDS extend advertisement register */
#define BRPHY1_BR_CTRL_EXPA1           0x094f2622 /* HLDS register, LDS link partner extend ability register */
#define BRPHY1_BR_CTRL_EXPA2           0x094f2624 /* HLDS Register */
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS 0x094f2626 /* Broadreach Misc Status */
#define BRPHY1_BR_CTRL_BR250_CTL       0x094f263c /* BR250 Control */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_IND_ACC
 ***************************************************************************/
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16 0x094f3000 /* Indirect Access SPI/MDIO CTRL/STATUS reg low  16 bits */
#define IND_ACC_RDB_IND_REGS_ADDR_SER_L16 0x094f3004 /* Indirect Access SPI/MDIO Address reg low  16 bits */
#define IND_ACC_RDB_IND_REGS_ADDR_SER_H16 0x094f3006 /* Indirect Access SPI/MDIO Address reg high 16 bits */
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_L16 0x094f3008 /* Indirect Access SPI/MDIO Data reg 15-0 bits */
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_H16 0x094f300a /* Indirect Access SPI/MDIO Data reg 31-16 bits */
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_L16 0x094f300c /* Indirect Access SPI/MDIO Data reg 47-32 bits */
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_H16 0x094f300e /* Indirect Access SPI/MDIO Data reg 63-48 bits */
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16 0x094f3010 /* Indirect Access CPU CTRL/STATUS reg low  16 bits */
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_L16 0x094f3014 /* Indirect Access CPU Address reg low  16 bits */
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_H16 0x094f3016 /* Indirect Access CPU Address reg high 16 bits */
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_L16 0x094f3018 /* Indirect Access CPU Data reg 15-0 bits */
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_H16 0x094f301a /* Indirect Access CPU Data reg 31-16 bits */
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_L16 0x094f301c /* Indirect Access CPU Data reg 47-32 bits */
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_H16 0x094f301e /* Indirect Access CPU Data reg 63-48 bits */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_BR_CL22_IEEE
 ***************************************************************************/
#define BRPHY1_BR_CL22_IEEE_MII_CTRL   0x094fffc0 /* BR_LRE_Control_Register */
#define BRPHY1_BR_CL22_IEEE_MII_STAT   0x094fffc2 /* BR_LRE_Status_Register */
#define BRPHY1_BR_CL22_IEEE_PHY_ID_MSB 0x094fffc4 /* PHY_Identifier_MSB_Register */
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB 0x094fffc6 /* PHY_Identifier_LSB_Register */
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP 0x094fffc8 /* LDS_Advertised_Ability_Register (Base Page) */
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL 0x094fffca /* LDS_Advertised_Control_Register */
#define BRPHY1_BR_CL22_IEEE_LDS_ABILITY 0x094fffcc /* LDS_Ability_Register (Next Page) */
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP 0x094fffce /* LDS_Link_Partner_Ability_Base_Page_Register (Base Page) */
#define BRPHY1_BR_CL22_IEEE_LDS_LP_MSG_NXTP 0x094fffd0 /* LDS_Link_Partners_Nxt_Pg_Msg_Register (Next Page) */
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP 0x094fffd2 /* LDS_Link_Partner_Ability_Nxt_Pg_Register (Next Page) */
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP 0x094fffd4 /* LDS_Expansion_Register */
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT 0x094fffd6 /* IEEE_Extended_Status_Register */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_CL45DEV1
 ***************************************************************************/
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1  0x09820000 /* IEEE PMA/PMD CONTROL 1 REGISTER (REG 1.0) */
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1   0x09820002 /* IEEE PMA/PMD STATUS 1 REGISTER  (REG 1.1) */
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID0 0x09820004 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 0 (REG 1.2) */
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1 0x09820006 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 1 (REG 1.3) */
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0  0x0982000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 1.5) */
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1  0x0982000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 1.6) */
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID0 0x0982001c /* PMA/PMD PACKAGE IDENTIFIER (REG 1.14) */
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID1 0x0982001e /* PMA/PMD PACKAGE IDENTIFIER (REG 1.15) */
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP 0x09820e10 /* TimeSync PMA/PMD capability (REG 1.1800) */
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x09820e12 /* Maximum PMA/PMD transmit path data delay, lower (REG 1.1801) */
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x09820e14 /* Maximum PMA/PMD transmit path data delay, upper (REG 1.1802) */
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x09820e16 /* Minimum PMA/PMD transmit path data delay, lower (REG 1.1803) */
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x09820e18 /* Minimum PMA/PMD transmit path data delay, upper (REG 1.1804) */
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x09820e1a /* Maximum PMA/PMD receive path data delay, lower (REG 1.1805) */
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x09820e1c /* Maximum PMA/PMD receive path data delay, upper (REG 1.1806) */
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x09820e1e /* Minimum PMA/PMD receive path data delay, lower (REG 1.1807) */
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x09820e20 /* Minimum PMA/PMD receive path data delay, upper (REG 1.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_CL45DEV3
 ***************************************************************************/
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1  0x09860000 /* IEEE PCS CONTROL 1 REGISTER (REG 3.0) */
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1   0x09860002 /* IEEE PCS STATUS 1 REGISTER  (REG 3.1) */
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID0 0x09860004 /* IEEE PCS DEVICE IDENTIFIER PART 0 (REG 3.2) */
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1 0x09860006 /* IEEE PCS DEVICE IDENTIFIER PART 1 (REG 3.3) */
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0  0x0986000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 3.5) */
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1  0x0986000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 3.6) */
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID0 0x0986001c /* PCS PACKAGE IDENTIFIER (REG 3.14) */
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID1 0x0986001e /* PCS PACKAGE IDENTIFIER (REG 3.15) */
#define BRPHY2_CL45DEV3_PCS_EEE_CAP    0x09860028 /* PCS_EEE_CAP(REG 3.20) */
#define BRPHY2_CL45DEV3_PCS_EEE_WAKE_ERR_CNT 0x0986002c /* PCS_EEE_Wake_Err_Cnt(REG 3.22) */
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP 0x09860e10 /* TimeSync PCS capability (REG 3.1800) */
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x09860e12 /* Maximum PCS transmit path data delay, lower (REG 3.1801) */
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x09860e14 /* Maximum PCS transmit path data delay, upper (REG 3.1802) */
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x09860e16 /* Minimum PCS transmit path data delay, lower (REG 3.1803) */
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x09860e18 /* Minimum PCS transmit path data delay, upper (REG 3.1804) */
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x09860e1a /* Maximum PCS receive path data delay, lower (REG 3.1805) */
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x09860e1c /* Maximum PCS receive path data delay, upper (REG 3.1806) */
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x09860e1e /* Minimum PCS receive path data delay, lower (REG 3.1807) */
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x09860e20 /* Minimum PCS receive path data delay, upper (REG 3.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_CL45DEV7
 ***************************************************************************/
#define BRPHY2_CL45DEV7_AN_CTRL        0x098e0000 /* Auto Neg Extended Next Page Control     (0x0000) (REG 7.0) */
#define BRPHY2_CL45DEV7_AN_STAT        0x098e0002 /* AN Status (0x0001) (REG 7.1) */
#define BRPHY2_CL45DEV7_AN_DEV_ID_LSB  0x098e0004 /* Auto Neg Device Identifier Lower 16 bit (0x0002) (REG 7.2) */
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB  0x098e0006 /* Auto Neg Device Identifier Upper 16 bit (0x0003) (REG 7.3) */
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB 0x098e000a /* Auto Neg Device In Package Lower 16 bit (0x0005) (REG 7.5) */
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB 0x098e000c /* Auto Neg Device In Package Upper 16 bit (0x0006) (REG 7.6) */
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_LSB 0x098e001c /* Auto Neg Package ID Lower 16 bit(0x000e) (REG 7.14) */
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_MSB 0x098e001e /* Auto Neg Package ID Upper 16 bit(0x000f) (REG 7.15) */
#define BRPHY2_CL45DEV7_AN_AD          0x098e0020 /* Auto Neg AD(0x0010) (REG 7.16) */
#define BRPHY2_CL45DEV7_AN_LPA         0x098e0026 /* AN LP base page ability (0x0013) (REG 7.19) */
#define BRPHY2_CL45DEV7_AN_XNPA        0x098e002c /* AN XNP transmit A (0x0016) (REG 7.22) */
#define BRPHY2_CL45DEV7_AN_XNPB        0x098e002e /* AN XNP transmit B (0x0017) (REG 7.23) */
#define BRPHY2_CL45DEV7_AN_XNPC        0x098e0030 /* AN XNP transmit C (0x0018) (REG 7.24) */
#define BRPHY2_CL45DEV7_LP_XNPA        0x098e0032 /* AN LP XNP ability A (0x0019) (REG 7.25) */
#define BRPHY2_CL45DEV7_LP_XNPB        0x098e0034 /* AN LP XNP ability B (0x001a) (REG 7.26) */
#define BRPHY2_CL45DEV7_LP_XNPC        0x098e0036 /* AN LP XNP ability C (0x001b) (REG 7.27) */
#define BRPHY2_CL45DEV7_TENG_AN_CTRL   0x098e0040 /* 10G Base-T AN Control Register (0x0020) (REG 7.32) */
#define BRPHY2_CL45DEV7_TENG_AN_STAT   0x098e0042 /* 10G Base-T AN Status Register  (0x0021) (REG 7.33) */
#define BRPHY2_CL45DEV7_EEE_ADV        0x098e0078 /* EEE Advertisement (0x003C) (REG 7.60 ???) */
#define BRPHY2_CL45DEV7_EEE_LP_ADV     0x098e007a /* EEE Link Partner Advertisement (0x003D) (REG 7.61 ???) */
#define BRPHY2_CL45DEV7_EEE_MODE_CTL   0x098e007c /* EEE Mode Control (0x003E) (REG 7.62 ???) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_CL45VEN
 ***************************************************************************/
#define BRPHY2_CL45VEN_FORCE_LINK      0x098f0000 /* Force Link Register */
#define BRPHY2_CL45VEN_SELECTIVE_RESET 0x098f0002 /* Selective Reset Register */
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS 0x098f0004 /* Test State Machine For Extended Next Pages Register --mvadkert */
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS 0x098f0006 /* Test State Machine For Next Pages Register --mvadkert */
#define BRPHY2_CL45VEN_AN_MAN_TEST     0x098f0032 /* Auto Negotiation Manual Test Register */
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A 0x098f0034 /* Auto Negotiation Manual Link Partners Abilities Register A */
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B 0x098f0036 /* Auto Negotiation Manual Link Partners Abilities Register B */
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_A 0x098f0038 /* Link Partner Next Page */
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_B 0x098f003a /* Link Partner Next Page (cont.) */
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_C 0x098f003c /* Link Partner Next Page (cont.) */
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_D 0x098f003e /* Link Partner Next Page (cont.) */
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_E 0x098f0040 /* Link Partner Next Page (cont.) */
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_F 0x098f0042 /* Link Partner Next Page (cont.) */
#define BRPHY2_CL45VEN_EPON_CTRL_REG   0x098f0046 /* EPON mode control register */
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A 0x098f0060 /* EEE Test Control Register A eee_test_control_bus[15:0] */
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B 0x098f0062 /* EEE Test Control Register B eee_test_control_bus[31:16] */
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C 0x098f0064 /* EEE Test Control Register C eee_test_control_bus[47:32] */
#define BRPHY2_CL45VEN_EEE_SPARE_1     0x098f0076 /* EEE Spare Register 1 */
#define BRPHY2_CL45VEN_EEE_SPARE_2     0x098f0078 /* EEE Spare Register 2 */
#define BRPHY2_CL45VEN_EEE_CONTROL     0x098f007a /* EEE Control Register */
#define BRPHY2_CL45VEN_EEE_RES_STAT    0x098f007c /* EEE Resolution Status Register */
#define BRPHY2_CL45VEN_LPI_MODE_CNTR   0x098f007e /* LPI Mode Counter Register */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_A 0x098f0080 /* Local Device Message 5 */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_B 0x098f0082 /* Local Device Message 5 cont. */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_C 0x098f0084 /* Local Device Message 5 cont. */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_D 0x098f0086 /* Local Device Message 5 cont. */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A 0x098f0088 /* Link Partner Message 5 */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B 0x098f008a /* Link Partner Message 5 cont. */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C 0x098f008c /* Link Partner Message 5 cont. */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D 0x098f008e /* Link Partner Message 5 cont. */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_A 0x098f0090 /* Local Device Message 6 */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B 0x098f0092 /* Local Device Message 6 cont. */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C 0x098f0094 /* Local Device Message 6 cont. */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_D 0x098f0096 /* Local Device Message 6 cont. */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A 0x098f0098 /* Link Partner Message 6 */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B 0x098f009a /* Link Partner Message 6 cont. */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C 0x098f009c /* Link Partner Message 6 cont. */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D 0x098f009e /* Link Partner Message 6 cont. */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_GPHY_CORE
 ***************************************************************************/
#define BRPHY2_GPHY_CORE_BASE10        0x098f2000 /* PHY_Extended_ctl_Register */
#define BRPHY2_GPHY_CORE_BASE11        0x098f2002 /* PHY_Extended_Status_Register (copper side only) */
#define BRPHY2_GPHY_CORE_BASE12        0x098f2004 /* Receive_Error_Cntr_Register */
#define BRPHY2_GPHY_CORE_BASE13        0x098f2006 /* False_Carrier_Sense_Cntr_Register */
#define BRPHY2_GPHY_CORE_BASE14        0x098f2008 /* Local_Remote_Receiver_NOT_OK_Cntrs_Register */
#define BRPHY2_GPHY_CORE_EXP45         0x098f200a /* Pattern Generator Control Register */
#define BRPHY2_GPHY_CORE_EXP46         0x098f200b /* Pattern Generator Status Register */
#define BRPHY2_GPHY_CORE_BASE19        0x098f2012 /* Auxiliary Status Summary (copper side only) */
#define BRPHY2_GPHY_CORE_BASE1A        0x098f2014 /* Interrupt Status Register (copper side only) */
#define BRPHY2_GPHY_CORE_BASE1B        0x098f2016 /* Interrupt Mask Register */
#define BRPHY2_GPHY_CORE_BASE1D_SHD    0x098f2018 /* HCD Status Register */
#define BRPHY2_GPHY_CORE_BASE1D        0x098f201a /* Master/Slave Seed Register */
#define BRPHY2_GPHY_CORE_BASE1E        0x098f201c /* Test1_Register */
#define BRPHY2_GPHY_CORE_BASE1F        0x098f201e /* Test2_Register */
#define BRPHY2_GPHY_CORE_SHD1C_00      0x098f2020 /* Cabletron LED Register (Shadow Register Selector = "00h") */
#define BRPHY2_GPHY_CORE_SHD1C_01      0x098f2022 /* TVCO Selection Register (Shadow Register Selector = "01h") */
#define BRPHY2_GPHY_CORE_SHD1C_02      0x098f2024 /* reserved Control 1 Register (Shadow Register Selector = "02h") */
#define BRPHY2_GPHY_CORE_SHD1C_03      0x098f2026 /* Clock Alignment Control Regsiter (Shadow Register Selector = "03h") */
#define BRPHY2_GPHY_CORE_SHD1C_04      0x098f2028 /* reserved Control 2 Register (Shadow Register Selector = "04h") */
#define BRPHY2_GPHY_CORE_SHD1C_05      0x098f202a /* reserved Control 3 Register (Shadow Register Selector = "05h") */
#define BRPHY2_GPHY_CORE_SHD1C_06      0x098f202c /* Tdr Control 1 Register (Shadow Register Selector = "06h") */
#define BRPHY2_GPHY_CORE_SHD1C_07      0x098f202e /* Tdr Control 2 Register (Shadow Register Selector = "07h") */
#define BRPHY2_GPHY_CORE_SHD1C_08      0x098f2030 /* Led Status Register (Shadow Register Selector = "08h") */
#define BRPHY2_GPHY_CORE_SHD1C_09      0x098f2032 /* Led Control Register (Shadow Register Selector = "09h") */
#define BRPHY2_GPHY_CORE_SHD1C_0A      0x098f2034 /* Auto-Power Down Register (Shadow Register Selector = "0ah") */
#define BRPHY2_GPHY_CORE_SHD1C_0B      0x098f2036 /* reserved Control 4 Register (Shadow Register Selector = "0bh") */
#define BRPHY2_GPHY_CORE_SHD1C_0D      0x098f203a /* LED Selector 1 Register (Shadow Register Selector = "0dh") */
#define BRPHY2_GPHY_CORE_SHD1C_0E      0x098f203c /* LED Selector 2 Register (Shadow Register Selector = "0eh") */
#define BRPHY2_GPHY_CORE_SHD1C_0F      0x098f203e /* LED GPIO Control/Status Register (Shadow Register Selector = "0fh") */
#define BRPHY2_GPHY_CORE_SHD1C_10      0x098f2040 /* Cisco Enhanced Linkstatus Mode Control Register (Shadow Register Selector = "10h") */
#define BRPHY2_GPHY_CORE_SHD1C_1F      0x098f2042 /* Mode Control Register (Shadow Register Selector = "1fh") */
#define BRPHY2_GPHY_CORE_SHD18_000     0x098f2050 /* Auxiliary Control Register (Shadow Register Selector = "000") */
#define BRPHY2_GPHY_CORE_SHD18_001     0x098f2052 /* 10 Base-T Register (Shadow Register Selector = "001") */
#define BRPHY2_GPHY_CORE_SHD18_010     0x098f2054 /* Power/MII Control Register (Shadow Register Selector = "010") */
#define BRPHY2_GPHY_CORE_SHD18_011     0x098f2056 /* IP Phone Register  (Shadow Register Selector = "011") */
#define BRPHY2_GPHY_CORE_SHD18_100     0x098f2058 /* Misc Test Register  1 (Shadow Register Selector = "100") */
#define BRPHY2_GPHY_CORE_SHD18_101     0x098f205a /* Misc Test Register  2 (Shadow Register Selector = "101") */
#define BRPHY2_GPHY_CORE_SHD18_110     0x098f205c /* Manual IP Phone Seed Register (Shadow Register Selector = "110") */
#define BRPHY2_GPHY_CORE_SHD18_111     0x098f205e /* Miscellanous Control Register (Shadow Register Selector = "111") */
#define BRPHY2_GPHY_CORE_EXP00         0x098f2060 /* Transmit Packet Counter */
#define BRPHY2_GPHY_CORE_EXP01         0x098f2062 /* Expansion Interrupt Status */
#define BRPHY2_GPHY_CORE_EXP02         0x098f2064 /* Expansion Interrupt Mask */
#define BRPHY2_GPHY_CORE_EXP03         0x098f2066 /* Spare Registers */
#define BRPHY2_GPHY_CORE_EXP04         0x098f2068 /* Bicolor LED Selectors */
#define BRPHY2_GPHY_CORE_EXP05         0x098f206a /* Bicolor LED Flash Rate Controls */
#define BRPHY2_GPHY_CORE_EXP06         0x098f206c /* Bicolor LED Programmable Blink Controls */
#define BRPHY2_GPHY_CORE_EXP07         0x098f206e /* Far End Fault */
#define BRPHY2_GPHY_CORE_EXP08         0x098f2070 /* 10BT Controls */
#define BRPHY2_GPHY_CORE_EXP09         0x098f2072 /* AMRR Controls */
#define BRPHY2_GPHY_CORE_EXP0A         0x098f2074 /* DAC TEMPLATE Controls */
#define BRPHY2_GPHY_CORE_EXP0B         0x098f2076 /* External Status */
#define BRPHY2_GPHY_CORE_EXP0C         0x098f2078 /* Spare Registers */
#define BRPHY2_GPHY_CORE_EXP30         0x098f2080 /* Late Collision Counters Status Register */
#define BRPHY2_GPHY_CORE_EXP31         0x098f2082 /* Late Collision Counter [64:95] */
#define BRPHY2_GPHY_CORE_EXP32         0x098f2084 /* Late Collision Counter [96:127] */
#define BRPHY2_GPHY_CORE_EXP33         0x098f2086 /* Late Collision Counter [128:191] */
#define BRPHY2_GPHY_CORE_EXP34         0x098f2088 /* Late Collision Counter [192:319] */
#define BRPHY2_GPHY_CORE_EXP35         0x098f208a /* Late Collision Counter Threshold Register */
#define BRPHY2_GPHY_CORE_EXP36         0x098f208c /* Clock PPM Detection between Recovery and Transmit Clocks */
#define BRPHY2_GPHY_CORE_EXP37         0x098f208e /* Clock PPM Detection between GTX_CLK and Transmit Clocks */
#define BRPHY2_GPHY_CORE_EXP38         0x098f2090 /* IP PHONE Cable Length Status Register */
#define BRPHY2_GPHY_CORE_EXP42         0x098f20a2 /* Operating Mode Status */
#define BRPHY2_GPHY_CORE_EXP5F         0x098f20be /* PLL Frequency Offset Testmode Control */
#define BRPHY2_GPHY_CORE_EXP70         0x098f20e0 /* SOFT-RESET */
#define BRPHY2_GPHY_CORE_EXP71         0x098f20e2 /* Serial LED Control 1 */
#define BRPHY2_GPHY_CORE_EXP72         0x098f20e4 /* Serial LED Control 2 */
#define BRPHY2_GPHY_CORE_EXP73         0x098f20e6 /* LED Gating 2 (Used for dual-media applications) */
#define BRPHY2_GPHY_CORE_EXP74         0x098f20e8 /* LED Programmable Current Mode Control */
#define BRPHY2_GPHY_CORE_EXP75         0x098f20ea /* CED LED Error Mask */
#define BRPHY2_GPHY_CORE_EXP78         0x098f20f0 /* Misc Extended Control */
#define BRPHY2_GPHY_CORE_EXP7B         0x098f20f6 /* I2C Control */
#define BRPHY2_GPHY_CORE_EXP7C         0x098f20f8 /* I2C Status */
#define BRPHY2_GPHY_CORE_EXP7F         0x098f20fe /* External MACSec Interface Control */
#define BRPHY2_GPHY_CORE_ALIAS_18      0x098f2100 /* Alias to MII Reg 18 */
#define BRPHY2_GPHY_CORE_ALIAS_19      0x098f2102 /* Alias to MII Reg 19 */
#define BRPHY2_GPHY_CORE_ALIAS_1A      0x098f2104 /* Alias to MII Reg 1a */
#define BRPHY2_GPHY_CORE_ALIAS_1B      0x098f2106 /* Alias to MII Reg 1b */
#define BRPHY2_GPHY_CORE_ALIAS_1C      0x098f2108 /* Alias to MII Reg 1c */
#define BRPHY2_GPHY_CORE_ALIAS_1D      0x098f210a /* Alias to MII Reg 1d */
#define BRPHY2_GPHY_CORE_REG_MAP_CTL   0x098f210e /* MII Registers 10-1D mapping control */
#define BRPHY2_GPHY_CORE_EXP98         0x098f2130 /* First Slice of Quad-GPHY only): CAL-BIAS Status */
#define BRPHY2_GPHY_CORE_EXP9C         0x098f2138 /* SMII Control */
#define BRPHY2_GPHY_CORE_BT_LINK_FIX   0x098f214a /* 10BT LINK FIX Register */
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG 0x098f214c /* SyncE+ Debug */
#define BRPHY2_GPHY_CORE_SYNCE_PLUS    0x098f214e /* SyncE+ Status and Control */
#define BRPHY2_GPHY_CORE_EXPA8         0x098f2150 /* ADAPTIVE BIAS CONTROL */
#define BRPHY2_GPHY_CORE_EXPA9         0x098f2152 /* spare register */
#define BRPHY2_GPHY_CORE_EXPAA         0x098f2154 /* EEE Statistic timer 12hours lpi */
#define BRPHY2_GPHY_CORE_EXPAB         0x098f2156 /* EEE Statistic timer 12hours local */
#define BRPHY2_GPHY_CORE_EXPAC         0x098f2158 /* EEE Statistic loc lpi req 0_to_1 counter */
#define BRPHY2_GPHY_CORE_EXPAD         0x098f215a /* EEE Statistic rem lpi_req 0_to_1 counter */
#define BRPHY2_GPHY_CORE_EXPAE         0x098f215c /* spare register */
#define BRPHY2_GPHY_CORE_EXPAF         0x098f215e /* EEE Statistic counters ctrl/status */
#define BRPHY2_GPHY_CORE_EXPB0         0x098f2160 /* Bias Control 0 */
#define BRPHY2_GPHY_CORE_EXPB1         0x098f2162 /* Bias Control 1 */
#define BRPHY2_GPHY_CORE_EXPB2         0x098f2164 /* Bias Control 2 */
#define BRPHY2_GPHY_CORE_EXPE3         0x098f2166 /* TX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY2_GPHY_CORE_EXPE4         0x098f2168 /* TX PCS Delay 10BT (copper side) */
#define BRPHY2_GPHY_CORE_EXPE5         0x098f216a /* TX PCS Delay (fiber side) */
#define BRPHY2_GPHY_CORE_EXPE6         0x098f216c /* RX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY2_GPHY_CORE_EXPE7         0x098f216e /* RX PCS Delay 10BT (copper side) */
#define BRPHY2_GPHY_CORE_EXPE8         0x098f2170 /* RX PCS Delay (fiber side) */
#define BRPHY2_GPHY_CORE_EXPE9         0x098f2172 /* P1588 TX/RX Cycle Delay */
#define BRPHY2_GPHY_CORE_EXPE0         0x098f2174 /* TX PMA/PMD Delay (copper side) */
#define BRPHY2_GPHY_CORE_EXPE1         0x098f2176 /* TX PMA/PMD Delay (fiber side) */
#define BRPHY2_GPHY_CORE_EXPE2         0x098f2178 /* RX PMA/PMD Delay (copper side) */
#define BRPHY2_GPHY_CORE_EXPEA         0x098f217a /* TX/RX Adjustable Cycle Delay */
#define BRPHY2_GPHY_CORE_LED_PRA_MODE  0x098f2180 /* LED Proportional Rate Activity Control */
#define BRPHY2_GPHY_CORE_FIFO_CTL      0x098f2182 /* FIFO Control Register */
#define BRPHY2_GPHY_CORE_EXPD8         0x098f21b0 /* Halting agc/enc ctrl reg */
#define BRPHY2_GPHY_CORE_EXPF0         0x098f21e0 /* RGMII IBS Control */
#define BRPHY2_GPHY_CORE_EXPF5         0x098f21ea /* Time Sync */
#define BRPHY2_GPHY_CORE_EXPF6         0x098f21ec /* Analog Power Control Status */
#define BRPHY2_GPHY_CORE_EXPF7         0x098f21ee /* Auto-power Down Control Status */
#define BRPHY2_GPHY_CORE_EXPF8         0x098f21f0 /* Trim Settings from Fuse & to Bias Block */
#define BRPHY2_GPHY_CORE_EXPF9         0x098f21f2 /* reserved Register Bits */
#define BRPHY2_GPHY_CORE_EXPFA         0x098f21f4 /* Hidden Identifier */
#define BRPHY2_GPHY_CORE_EXPFB         0x098f21f6 /* TDR Override Values */
#define BRPHY2_GPHY_CORE_EXPFC         0x098f21f8 /*  */
#define BRPHY2_GPHY_CORE_EXPFD         0x098f21fa /* Clock gating control override value */
#define BRPHY2_GPHY_CORE_EXPFE         0x098f21fc /* Clock gating control override enable */
#define BRPHY2_GPHY_CORE_EXPFF         0x098f21fe /* Analog power control override */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_DSP_TAP
 ***************************************************************************/
#define BRPHY2_DSP_TAP_TAP0_C0         0x098f2200 /* AGC Control/Status Register A (x4) */
#define BRPHY2_DSP_TAP_TAP0_C1         0x098f2202 /* AGC Control/Status Register A (x4) */
#define BRPHY2_DSP_TAP_TAP0_C2         0x098f2204 /* AGC Control/Status Register A (x4) */
#define BRPHY2_DSP_TAP_TAP0_C3         0x098f2206 /* AGC Control/Status Register A (x4) */
#define BRPHY2_DSP_TAP_TAP1            0x098f2208 /* IPRF Control register (x1) */
#define BRPHY2_DSP_TAP_TAP2_C0         0x098f2210 /* MSE Status Register (x4) */
#define BRPHY2_DSP_TAP_TAP2_C1         0x098f2212 /* MSE Status Register (x4) */
#define BRPHY2_DSP_TAP_TAP2_C2         0x098f2214 /* MSE Status Register (x4) */
#define BRPHY2_DSP_TAP_TAP2_C3         0x098f2216 /* MSE Status Register (x4) */
#define BRPHY2_DSP_TAP_TAP3_C0         0x098f2218 /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY2_DSP_TAP_TAP3_C1         0x098f221a /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY2_DSP_TAP_TAP3_C2         0x098f221c /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY2_DSP_TAP_TAP3_C3         0x098f221e /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY2_DSP_TAP_TAP4_C0         0x098f2220 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY2_DSP_TAP_TAP4_C1         0x098f2222 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY2_DSP_TAP_TAP4_C2         0x098f2224 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY2_DSP_TAP_TAP4_C3         0x098f2226 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY2_DSP_TAP_TAP5_C0         0x098f2228 /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY2_DSP_TAP_TAP5_C1         0x098f222a /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY2_DSP_TAP_TAP5_C2         0x098f222c /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY2_DSP_TAP_TAP5_C3         0x098f222e /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY2_DSP_TAP_TAP6            0x098f2230 /* CFC Deadman Disable */
#define BRPHY2_DSP_TAP_TAP7_C0         0x098f2238 /* BIST TEST 0 */
#define BRPHY2_DSP_TAP_TAP7_C1         0x098f223a /* BIST TEST 1 */
#define BRPHY2_DSP_TAP_TAP7_C2         0x098f223c /* BIST TEST 2 */
#define BRPHY2_DSP_TAP_TAP8_C0         0x098f2240 /* ABIST TEST 0 */
#define BRPHY2_DSP_TAP_TAP8_C1         0x098f2242 /* ABIST TEST 1 */
#define BRPHY2_DSP_TAP_TAP8_C2         0x098f2244 /* ABIST TEST 2 */
#define BRPHY2_DSP_TAP_TAP8_C3         0x098f2246 /* BR HPF Control */
#define BRPHY2_DSP_TAP_TAP9            0x098f2248 /* Frequency Control/Status Register LSBs (x1) */
#define BRPHY2_DSP_TAP_TAP10           0x098f224a /* PLL Bandwidth Control/Status and Path Metric Reset Register (x1) */
#define BRPHY2_DSP_TAP_TAP11           0x098f224c /* PLL RCLK and TCLK Offset Freeze Register (x1) */
#define BRPHY2_DSP_TAP_TAP12_C0        0x098f2250 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY2_DSP_TAP_TAP12_C1        0x098f2252 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY2_DSP_TAP_TAP12_C2        0x098f2254 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY2_DSP_TAP_TAP12_C3        0x098f2256 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY2_DSP_TAP_TAP13           0x098f2258 /* HPF Bandwidth Control and Disable ADC LSBs (x1) */
#define BRPHY2_DSP_TAP_TAP14           0x098f225a /* MSE Threshold Register  #1 (x1) */
#define BRPHY2_DSP_TAP_TAP15           0x098f225c /* MSE Threshold Register #2 (x1) */
#define BRPHY2_DSP_TAP_TAP16_C0        0x098f2260 /* Logic Analyzer trigger delay (x1) */
#define BRPHY2_DSP_TAP_TAP16_C1        0x098f2262 /* BIST CRC Monitor (x4) */
#define BRPHY2_DSP_TAP_TAP16_C2        0x098f2264 /* BIST CRC Monitor (x4) */
#define BRPHY2_DSP_TAP_TAP16_C3        0x098f2266 /* BIST CRC Monitor (x4) */
#define BRPHY2_DSP_TAP_TAP17_C0        0x098f2268 /* Testmode testvalue (aliased with logic analyzer state selects) */
#define BRPHY2_DSP_TAP_TAP17_C1        0x098f226a /* Testmode and logic analyzer controls #1 */
#define BRPHY2_DSP_TAP_TAP17_C2        0x098f226c /* Logic analyzer controls #2 */
#define BRPHY2_DSP_TAP_TAP17_C3        0x098f226e /* Testmode and logic analyzer controls #3 */
#define BRPHY2_DSP_TAP_TAP18_C0        0x098f2270 /* Peak Noise detector (x4) */
#define BRPHY2_DSP_TAP_TAP18_C1        0x098f2272 /* Peak Noise detector (x4) */
#define BRPHY2_DSP_TAP_TAP18_C2        0x098f2274 /* Peak Noise detector (x4) */
#define BRPHY2_DSP_TAP_TAP18_C3        0x098f2276 /* Peak Noise detector (x4) */
#define BRPHY2_DSP_TAP_TAP20           0x098f2278 /* Echo Minimum Length and LMS/FIR delay adjustments (x1) */
#define BRPHY2_DSP_TAP_TAP21           0x098f227a /* Phy Control Monitors #1 (x1) */
#define BRPHY2_DSP_TAP_TAP22           0x098f227c /* Phy Control Monitors #2 (x1) */
#define BRPHY2_DSP_TAP_TAP23           0x098f227e /* Phy Control Monitors #3 (x1) */
#define BRPHY2_DSP_TAP_TAP24           0x098f2280 /* Phy Control Output Overrides #1 (x1) */
#define BRPHY2_DSP_TAP_TAP25           0x098f2282 /* Phy Control Output Overrides #2 (x1) */
#define BRPHY2_DSP_TAP_TAP26           0x098f2284 /* Phy Control Input Overrides #1 (x1) */
#define BRPHY2_DSP_TAP_TAP27           0x098f2286 /* Phy Control Input Overrides #2 (x1) */
#define BRPHY2_DSP_TAP_TAP28           0x098f2288 /* Phy Control Output Overrides #3 (x1) */
#define BRPHY2_DSP_TAP_TAP29           0x098f228a /* Phy Control Force State/Timers/Alternate Behaviour Register #1 (x1) */
#define BRPHY2_DSP_TAP_TAP30           0x098f228c /* Phy Control Force State/Timers/Alternate Behaviour Register #2 (x1) */
#define BRPHY2_DSP_TAP_TAP31_C0        0x098f2290 /* Channel Swap Override */
#define BRPHY2_DSP_TAP_TAP32_C0        0x098f2298 /* Transmit Testmode Sync Generation (x1) */
#define BRPHY2_DSP_TAP_FDFE_OV_RD      0x098f229a /* FDFE Override/Read Control Register */
#define BRPHY2_DSP_TAP_FDFE_COEFF      0x098f229c /* FDFE Coefficient Read Back Register */
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD 0x098f229e /* FDFE Beta Threshold Control */
#define BRPHY2_DSP_TAP_TAP33_C0        0x098f22a0 /* eee dsp test */
#define BRPHY2_DSP_TAP_TAP33_C1        0x098f22a2 /* eee sigdet */
#define BRPHY2_DSP_TAP_TAP33_C2        0x098f22a4 /* eee_lpi_timers */
#define BRPHY2_DSP_TAP_TAP33_C3        0x098f22a6 /* spare register */
#define BRPHY2_DSP_TAP_TAP34_C0        0x098f22a8 /* eee frequency control */
#define BRPHY2_DSP_TAP_TAP34_C1        0x098f22aa /* eee Gigabit Mode BW control */
#define BRPHY2_DSP_TAP_TAP34_C2        0x098f22ac /* eee 100TX Mode BW control */
#define BRPHY2_DSP_TAP_TAP34_C3        0x098f22ae /* phasectl TPO monitor */
#define BRPHY2_DSP_TAP_TAP35_C0        0x098f22b0 /* eee 100Base-tx timer control 1 */
#define BRPHY2_DSP_TAP_TAP35_C1        0x098f22b2 /* eee 100Base-tx timer control 2 */
#define BRPHY2_DSP_TAP_TAP35_C2        0x098f22b4 /* eee 100Base-tx timer misc control */
#define BRPHY2_DSP_TAP_TAP35_C3        0x098f22b6 /* pcs_lpi_test */
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0  0x098f22b8 /* Filter Freeze/Disable per channel Control */
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1  0x098f22ba /* Filter Freeze/Disable per channel Control */
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2  0x098f22bc /* Filter Freeze/Disable per channel Control */
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3  0x098f22be /* Filter Freeze/Disable per channel Control */
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0 0x098f22c0 /* FFEX Freeze/Disable per channel Control */
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1 0x098f22c2 /* FFEX Freeze/Disable per channel Control */
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2 0x098f22c4 /* FFEX Freeze/Disable per channel Control */
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3 0x098f22c6 /* FFEX Freeze/Disable per channel Control */
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL 0x098f22c8 /* EMI Datapath Control */
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2 0x098f22ca /* EMI Datapath Control2 */
#define BRPHY2_DSP_TAP_FFEX_CTL        0x098f22cc /* FFE X-tap Control */
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0 0x098f22ce /* Phycontrol Breakpoint Control 0 */
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1 0x098f22d0 /* Phycontrol Breakpoint Control 1 */
#define BRPHY2_DSP_TAP_FILTER_ADDR     0x098f2360 /* DSP Coefficient Address Register */
#define BRPHY2_DSP_TAP_FILTER_CTL      0x098f2362 /* DSP Control Register */
#define BRPHY2_DSP_TAP_FILTER_DATA     0x098f2364 /* DSP Coefficient Read/Write Port */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_PLL_CTRL
 ***************************************************************************/
#define BRPHY2_PLL_CTRL_PLLCTRL_0      0x098f2390 /* Analog pll control 0 */
#define BRPHY2_PLL_CTRL_PLLCTRL_1      0x098f2392 /* Analog pll control 1 */
#define BRPHY2_PLL_CTRL_PLLCTRL_2      0x098f2394 /* Analog pll control 2 */
#define BRPHY2_PLL_CTRL_PLLCTRL_3      0x098f2396 /* Analog pll control 3 */
#define BRPHY2_PLL_CTRL_PLLCTRL_4      0x098f2398 /* Analog pll control 4 */
#define BRPHY2_PLL_CTRL_PLLCTRL_5      0x098f239a /* Analog pll control 5 */
#define BRPHY2_PLL_CTRL_PLLCTRL_6      0x098f239c /* Analog pll control 6 */
#define BRPHY2_PLL_CTRL_PLL_STATUS_0   0x098f23a0 /* Analog PLL Status 0 */
#define BRPHY2_PLL_CTRL_PLL_STATUS_1   0x098f23a2 /* Analog PLL Status 1 */
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS 0x098f23a4 /* AFE Signal detect */
#define BRPHY2_PLL_CTRL_PLLCTRL_7      0x098f23a6 /* Analog pll control 7 */
#define BRPHY2_PLL_CTRL_PLLCTRL_8      0x098f23a8 /* Analog pll control 8 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_AFE_CTRL
 ***************************************************************************/
#define BRPHY2_AFE_CTRL_RXCONFIG_0     0x098f23c0 /* RXCONFIG 15:0 */
#define BRPHY2_AFE_CTRL_RXCONFIG_1     0x098f23c2 /* RXCONFIG 31:16 */
#define BRPHY2_AFE_CTRL_RXCONFIG_2     0x098f23c4 /* RXCONFIG 47:32 */
#define BRPHY2_AFE_CTRL_RXCONFIG_3     0x098f23c6 /* RXCONFIG 63:48 */
#define BRPHY2_AFE_CTRL_RXCONFIG_4     0x098f23c8 /* RXCONFIG 79:64 */
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP   0x098f23ca /* RXCONFIG 86:80 and LP tuning */
#define BRPHY2_AFE_CTRL_TX_CONFIG_0    0x098f23cc /* TXCONFIG 15:0 */
#define BRPHY2_AFE_CTRL_TX_CONFIG_1    0x098f23ce /* TXCONFIG 31:16 */
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_0   0x098f23d0 /* VDAC CURRENT Control 15:0 */
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_1   0x098f23d2 /* VDAC CURRENT Control 31:16 */
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_2   0x098f23d4 /* VDAC CURRENT Control 51:36 */
#define BRPHY2_AFE_CTRL_VDAC_OTHERS_0  0x098f23d6 /* VDAC CURRENT 35:32 and others */
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS 0x098f23d8 /* HPF trim and reserved bits */
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_0 0x098f23da /* TXCONFIG 15:0 */
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_1 0x098f23dc /* TXCONFIG 15:0 */
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_2 0x098f23de /* TXCONFIG 15:0 */
#define BRPHY2_AFE_CTRL_TEMPSEN_OTHERS 0x098f23e0 /* TEMPSEN_OTHERS 15:0 */
#define BRPHY2_AFE_CTRL_FUTURE_RSV     0x098f23e2 /* FUTURE_RSV 15:0 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_ECD_CTRL
 ***************************************************************************/
#define BRPHY2_ECD_CTRL_EXPC0          0x098f2540 /* ECD Control and Status */
#define BRPHY2_ECD_CTRL_EXPC1          0x098f2542 /* ECD Fault Type */
#define BRPHY2_ECD_CTRL_EXPC2          0x098f2544 /* ECD Pair A Length Results */
#define BRPHY2_ECD_CTRL_EXPC3          0x098f2546 /* ECD Pair B Length Results */
#define BRPHY2_ECD_CTRL_EXPC4          0x098f2548 /* ECD Pair C Length Results */
#define BRPHY2_ECD_CTRL_EXPC5          0x098f254a /* ECD Pair D Length Results */
#define BRPHY2_ECD_CTRL_EXPC6          0x098f254c /* ECD XTALK Map */
#define BRPHY2_ECD_CTRL_EXPC7          0x098f254e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPC8          0x098f2550 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPC9          0x098f2552 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPCA          0x098f2554 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPCB          0x098f2556 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPCC          0x098f2558 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPCD          0x098f255a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPCE          0x098f255c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPCF          0x098f255e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE0          0x098f2560 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE1          0x098f2562 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE2          0x098f2564 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE3          0x098f2566 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE4          0x098f2568 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE5          0x098f256a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE6          0x098f256c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE7          0x098f256e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE8          0x098f2570 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPE9          0x098f2572 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPEA          0x098f2574 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPEB          0x098f2576 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPEC          0x098f2578 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPED          0x098f257a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPEE          0x098f257c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY2_ECD_CTRL_EXPEF          0x098f257e /* ECD EXTRA RESERVED REGISTER */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_BR_CTRL
 ***************************************************************************/
#define BRPHY2_BR_CTRL_EXP90           0x098f2600 /* BroadReach LRE Misc Control */
#define BRPHY2_BR_CTRL_EXP91           0x098f2602 /* BroadReach LRE Misc Control */
#define BRPHY2_BR_CTRL_EXP92           0x098f2604 /* BroadReach LRE Misc Control */
#define BRPHY2_BR_CTRL_EXP93           0x098f2606 /* BroadReach LDS  Control */
#define BRPHY2_BR_CTRL_EXP94           0x098f2608 /* BroadReach LDS RX Control */
#define BRPHY2_BR_CTRL_EXP95           0x098f260a /* BroadReach LDS RX Control */
#define BRPHY2_BR_CTRL_EXP96           0x098f260c /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY2_BR_CTRL_EXP97           0x098f260e /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY2_BR_CTRL_EXP99           0x098f2612 /* BroadReach LDS Timer Control */
#define BRPHY2_BR_CTRL_EXP9A           0x098f2614 /* LDS Status */
#define BRPHY2_BR_CTRL_EXP9B           0x098f2616 /* BroadR-Reach PLL Control */
#define BRPHY2_BR_CTRL_EXP9D           0x098f261a /* EoC Internal Control 1 */
#define BRPHY2_BR_CTRL_EXP9E           0x098f261c /* LDS Length Threshold 0 */
#define BRPHY2_BR_CTRL_EXP9F           0x098f261e /* LDS Length Threshold 1 */
#define BRPHY2_BR_CTRL_EXPA0           0x098f2620 /* HLDS register, LDS extend advertisement register */
#define BRPHY2_BR_CTRL_EXPA1           0x098f2622 /* HLDS register, LDS link partner extend ability register */
#define BRPHY2_BR_CTRL_EXPA2           0x098f2624 /* HLDS Register */
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS 0x098f2626 /* Broadreach Misc Status */
#define BRPHY2_BR_CTRL_BR250_CTL       0x098f263c /* BR250 Control */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_BR_CL22_IEEE
 ***************************************************************************/
#define BRPHY2_BR_CL22_IEEE_MII_CTRL   0x098fffc0 /* BR_LRE_Control_Register */
#define BRPHY2_BR_CL22_IEEE_MII_STAT   0x098fffc2 /* BR_LRE_Status_Register */
#define BRPHY2_BR_CL22_IEEE_PHY_ID_MSB 0x098fffc4 /* PHY_Identifier_MSB_Register */
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB 0x098fffc6 /* PHY_Identifier_LSB_Register */
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP 0x098fffc8 /* LDS_Advertised_Ability_Register (Base Page) */
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL 0x098fffca /* LDS_Advertised_Control_Register */
#define BRPHY2_BR_CL22_IEEE_LDS_ABILITY 0x098fffcc /* LDS_Ability_Register (Next Page) */
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP 0x098fffce /* LDS_Link_Partner_Ability_Base_Page_Register (Base Page) */
#define BRPHY2_BR_CL22_IEEE_LDS_LP_MSG_NXTP 0x098fffd0 /* LDS_Link_Partners_Nxt_Pg_Msg_Register (Next Page) */
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP 0x098fffd2 /* LDS_Link_Partner_Ability_Nxt_Pg_Register (Next Page) */
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP 0x098fffd4 /* LDS_Expansion_Register */
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT 0x098fffd6 /* IEEE_Extended_Status_Register */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_CL45DEV1
 ***************************************************************************/
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1  0x09c20000 /* IEEE PMA/PMD CONTROL 1 REGISTER (REG 1.0) */
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1   0x09c20002 /* IEEE PMA/PMD STATUS 1 REGISTER  (REG 1.1) */
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID0 0x09c20004 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 0 (REG 1.2) */
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1 0x09c20006 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 1 (REG 1.3) */
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0  0x09c2000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 1.5) */
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1  0x09c2000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 1.6) */
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID0 0x09c2001c /* PMA/PMD PACKAGE IDENTIFIER (REG 1.14) */
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID1 0x09c2001e /* PMA/PMD PACKAGE IDENTIFIER (REG 1.15) */
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP 0x09c20e10 /* TimeSync PMA/PMD capability (REG 1.1800) */
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x09c20e12 /* Maximum PMA/PMD transmit path data delay, lower (REG 1.1801) */
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x09c20e14 /* Maximum PMA/PMD transmit path data delay, upper (REG 1.1802) */
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x09c20e16 /* Minimum PMA/PMD transmit path data delay, lower (REG 1.1803) */
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x09c20e18 /* Minimum PMA/PMD transmit path data delay, upper (REG 1.1804) */
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x09c20e1a /* Maximum PMA/PMD receive path data delay, lower (REG 1.1805) */
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x09c20e1c /* Maximum PMA/PMD receive path data delay, upper (REG 1.1806) */
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x09c20e1e /* Minimum PMA/PMD receive path data delay, lower (REG 1.1807) */
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x09c20e20 /* Minimum PMA/PMD receive path data delay, upper (REG 1.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_CL45DEV3
 ***************************************************************************/
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1  0x09c60000 /* IEEE PCS CONTROL 1 REGISTER (REG 3.0) */
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1   0x09c60002 /* IEEE PCS STATUS 1 REGISTER  (REG 3.1) */
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID0 0x09c60004 /* IEEE PCS DEVICE IDENTIFIER PART 0 (REG 3.2) */
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1 0x09c60006 /* IEEE PCS DEVICE IDENTIFIER PART 1 (REG 3.3) */
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0  0x09c6000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 3.5) */
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1  0x09c6000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 3.6) */
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID0 0x09c6001c /* PCS PACKAGE IDENTIFIER (REG 3.14) */
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID1 0x09c6001e /* PCS PACKAGE IDENTIFIER (REG 3.15) */
#define BRPHY3_CL45DEV3_PCS_EEE_CAP    0x09c60028 /* PCS_EEE_CAP(REG 3.20) */
#define BRPHY3_CL45DEV3_PCS_EEE_WAKE_ERR_CNT 0x09c6002c /* PCS_EEE_Wake_Err_Cnt(REG 3.22) */
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP 0x09c60e10 /* TimeSync PCS capability (REG 3.1800) */
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x09c60e12 /* Maximum PCS transmit path data delay, lower (REG 3.1801) */
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x09c60e14 /* Maximum PCS transmit path data delay, upper (REG 3.1802) */
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x09c60e16 /* Minimum PCS transmit path data delay, lower (REG 3.1803) */
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x09c60e18 /* Minimum PCS transmit path data delay, upper (REG 3.1804) */
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x09c60e1a /* Maximum PCS receive path data delay, lower (REG 3.1805) */
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x09c60e1c /* Maximum PCS receive path data delay, upper (REG 3.1806) */
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x09c60e1e /* Minimum PCS receive path data delay, lower (REG 3.1807) */
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x09c60e20 /* Minimum PCS receive path data delay, upper (REG 3.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_CL45DEV7
 ***************************************************************************/
#define BRPHY3_CL45DEV7_AN_CTRL        0x09ce0000 /* Auto Neg Extended Next Page Control     (0x0000) (REG 7.0) */
#define BRPHY3_CL45DEV7_AN_STAT        0x09ce0002 /* AN Status (0x0001) (REG 7.1) */
#define BRPHY3_CL45DEV7_AN_DEV_ID_LSB  0x09ce0004 /* Auto Neg Device Identifier Lower 16 bit (0x0002) (REG 7.2) */
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB  0x09ce0006 /* Auto Neg Device Identifier Upper 16 bit (0x0003) (REG 7.3) */
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB 0x09ce000a /* Auto Neg Device In Package Lower 16 bit (0x0005) (REG 7.5) */
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB 0x09ce000c /* Auto Neg Device In Package Upper 16 bit (0x0006) (REG 7.6) */
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_LSB 0x09ce001c /* Auto Neg Package ID Lower 16 bit(0x000e) (REG 7.14) */
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_MSB 0x09ce001e /* Auto Neg Package ID Upper 16 bit(0x000f) (REG 7.15) */
#define BRPHY3_CL45DEV7_AN_AD          0x09ce0020 /* Auto Neg AD(0x0010) (REG 7.16) */
#define BRPHY3_CL45DEV7_AN_LPA         0x09ce0026 /* AN LP base page ability (0x0013) (REG 7.19) */
#define BRPHY3_CL45DEV7_AN_XNPA        0x09ce002c /* AN XNP transmit A (0x0016) (REG 7.22) */
#define BRPHY3_CL45DEV7_AN_XNPB        0x09ce002e /* AN XNP transmit B (0x0017) (REG 7.23) */
#define BRPHY3_CL45DEV7_AN_XNPC        0x09ce0030 /* AN XNP transmit C (0x0018) (REG 7.24) */
#define BRPHY3_CL45DEV7_LP_XNPA        0x09ce0032 /* AN LP XNP ability A (0x0019) (REG 7.25) */
#define BRPHY3_CL45DEV7_LP_XNPB        0x09ce0034 /* AN LP XNP ability B (0x001a) (REG 7.26) */
#define BRPHY3_CL45DEV7_LP_XNPC        0x09ce0036 /* AN LP XNP ability C (0x001b) (REG 7.27) */
#define BRPHY3_CL45DEV7_TENG_AN_CTRL   0x09ce0040 /* 10G Base-T AN Control Register (0x0020) (REG 7.32) */
#define BRPHY3_CL45DEV7_TENG_AN_STAT   0x09ce0042 /* 10G Base-T AN Status Register  (0x0021) (REG 7.33) */
#define BRPHY3_CL45DEV7_EEE_ADV        0x09ce0078 /* EEE Advertisement (0x003C) (REG 7.60 ???) */
#define BRPHY3_CL45DEV7_EEE_LP_ADV     0x09ce007a /* EEE Link Partner Advertisement (0x003D) (REG 7.61 ???) */
#define BRPHY3_CL45DEV7_EEE_MODE_CTL   0x09ce007c /* EEE Mode Control (0x003E) (REG 7.62 ???) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_CL45VEN
 ***************************************************************************/
#define BRPHY3_CL45VEN_FORCE_LINK      0x09cf0000 /* Force Link Register */
#define BRPHY3_CL45VEN_SELECTIVE_RESET 0x09cf0002 /* Selective Reset Register */
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS 0x09cf0004 /* Test State Machine For Extended Next Pages Register --mvadkert */
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS 0x09cf0006 /* Test State Machine For Next Pages Register --mvadkert */
#define BRPHY3_CL45VEN_AN_MAN_TEST     0x09cf0032 /* Auto Negotiation Manual Test Register */
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A 0x09cf0034 /* Auto Negotiation Manual Link Partners Abilities Register A */
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B 0x09cf0036 /* Auto Negotiation Manual Link Partners Abilities Register B */
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_A 0x09cf0038 /* Link Partner Next Page */
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_B 0x09cf003a /* Link Partner Next Page (cont.) */
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_C 0x09cf003c /* Link Partner Next Page (cont.) */
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_D 0x09cf003e /* Link Partner Next Page (cont.) */
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_E 0x09cf0040 /* Link Partner Next Page (cont.) */
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_F 0x09cf0042 /* Link Partner Next Page (cont.) */
#define BRPHY3_CL45VEN_EPON_CTRL_REG   0x09cf0046 /* EPON mode control register */
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A 0x09cf0060 /* EEE Test Control Register A eee_test_control_bus[15:0] */
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B 0x09cf0062 /* EEE Test Control Register B eee_test_control_bus[31:16] */
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C 0x09cf0064 /* EEE Test Control Register C eee_test_control_bus[47:32] */
#define BRPHY3_CL45VEN_EEE_SPARE_1     0x09cf0076 /* EEE Spare Register 1 */
#define BRPHY3_CL45VEN_EEE_SPARE_2     0x09cf0078 /* EEE Spare Register 2 */
#define BRPHY3_CL45VEN_EEE_CONTROL     0x09cf007a /* EEE Control Register */
#define BRPHY3_CL45VEN_EEE_RES_STAT    0x09cf007c /* EEE Resolution Status Register */
#define BRPHY3_CL45VEN_LPI_MODE_CNTR   0x09cf007e /* LPI Mode Counter Register */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_A 0x09cf0080 /* Local Device Message 5 */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_B 0x09cf0082 /* Local Device Message 5 cont. */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_C 0x09cf0084 /* Local Device Message 5 cont. */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_D 0x09cf0086 /* Local Device Message 5 cont. */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A 0x09cf0088 /* Link Partner Message 5 */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B 0x09cf008a /* Link Partner Message 5 cont. */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C 0x09cf008c /* Link Partner Message 5 cont. */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D 0x09cf008e /* Link Partner Message 5 cont. */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_A 0x09cf0090 /* Local Device Message 6 */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B 0x09cf0092 /* Local Device Message 6 cont. */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C 0x09cf0094 /* Local Device Message 6 cont. */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_D 0x09cf0096 /* Local Device Message 6 cont. */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A 0x09cf0098 /* Link Partner Message 6 */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B 0x09cf009a /* Link Partner Message 6 cont. */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C 0x09cf009c /* Link Partner Message 6 cont. */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D 0x09cf009e /* Link Partner Message 6 cont. */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_GPHY_CORE
 ***************************************************************************/
#define BRPHY3_GPHY_CORE_BASE10        0x09cf2000 /* PHY_Extended_ctl_Register */
#define BRPHY3_GPHY_CORE_BASE11        0x09cf2002 /* PHY_Extended_Status_Register (copper side only) */
#define BRPHY3_GPHY_CORE_BASE12        0x09cf2004 /* Receive_Error_Cntr_Register */
#define BRPHY3_GPHY_CORE_BASE13        0x09cf2006 /* False_Carrier_Sense_Cntr_Register */
#define BRPHY3_GPHY_CORE_BASE14        0x09cf2008 /* Local_Remote_Receiver_NOT_OK_Cntrs_Register */
#define BRPHY3_GPHY_CORE_EXP45         0x09cf200a /* Pattern Generator Control Register */
#define BRPHY3_GPHY_CORE_EXP46         0x09cf200b /* Pattern Generator Status Register */
#define BRPHY3_GPHY_CORE_BASE19        0x09cf2012 /* Auxiliary Status Summary (copper side only) */
#define BRPHY3_GPHY_CORE_BASE1A        0x09cf2014 /* Interrupt Status Register (copper side only) */
#define BRPHY3_GPHY_CORE_BASE1B        0x09cf2016 /* Interrupt Mask Register */
#define BRPHY3_GPHY_CORE_BASE1D_SHD    0x09cf2018 /* HCD Status Register */
#define BRPHY3_GPHY_CORE_BASE1D        0x09cf201a /* Master/Slave Seed Register */
#define BRPHY3_GPHY_CORE_BASE1E        0x09cf201c /* Test1_Register */
#define BRPHY3_GPHY_CORE_BASE1F        0x09cf201e /* Test2_Register */
#define BRPHY3_GPHY_CORE_SHD1C_00      0x09cf2020 /* Cabletron LED Register (Shadow Register Selector = "00h") */
#define BRPHY3_GPHY_CORE_SHD1C_01      0x09cf2022 /* TVCO Selection Register (Shadow Register Selector = "01h") */
#define BRPHY3_GPHY_CORE_SHD1C_02      0x09cf2024 /* reserved Control 1 Register (Shadow Register Selector = "02h") */
#define BRPHY3_GPHY_CORE_SHD1C_03      0x09cf2026 /* Clock Alignment Control Regsiter (Shadow Register Selector = "03h") */
#define BRPHY3_GPHY_CORE_SHD1C_04      0x09cf2028 /* reserved Control 2 Register (Shadow Register Selector = "04h") */
#define BRPHY3_GPHY_CORE_SHD1C_05      0x09cf202a /* reserved Control 3 Register (Shadow Register Selector = "05h") */
#define BRPHY3_GPHY_CORE_SHD1C_06      0x09cf202c /* Tdr Control 1 Register (Shadow Register Selector = "06h") */
#define BRPHY3_GPHY_CORE_SHD1C_07      0x09cf202e /* Tdr Control 2 Register (Shadow Register Selector = "07h") */
#define BRPHY3_GPHY_CORE_SHD1C_08      0x09cf2030 /* Led Status Register (Shadow Register Selector = "08h") */
#define BRPHY3_GPHY_CORE_SHD1C_09      0x09cf2032 /* Led Control Register (Shadow Register Selector = "09h") */
#define BRPHY3_GPHY_CORE_SHD1C_0A      0x09cf2034 /* Auto-Power Down Register (Shadow Register Selector = "0ah") */
#define BRPHY3_GPHY_CORE_SHD1C_0B      0x09cf2036 /* reserved Control 4 Register (Shadow Register Selector = "0bh") */
#define BRPHY3_GPHY_CORE_SHD1C_0D      0x09cf203a /* LED Selector 1 Register (Shadow Register Selector = "0dh") */
#define BRPHY3_GPHY_CORE_SHD1C_0E      0x09cf203c /* LED Selector 2 Register (Shadow Register Selector = "0eh") */
#define BRPHY3_GPHY_CORE_SHD1C_0F      0x09cf203e /* LED GPIO Control/Status Register (Shadow Register Selector = "0fh") */
#define BRPHY3_GPHY_CORE_SHD1C_10      0x09cf2040 /* Cisco Enhanced Linkstatus Mode Control Register (Shadow Register Selector = "10h") */
#define BRPHY3_GPHY_CORE_SHD1C_1F      0x09cf2042 /* Mode Control Register (Shadow Register Selector = "1fh") */
#define BRPHY3_GPHY_CORE_SHD18_000     0x09cf2050 /* Auxiliary Control Register (Shadow Register Selector = "000") */
#define BRPHY3_GPHY_CORE_SHD18_001     0x09cf2052 /* 10 Base-T Register (Shadow Register Selector = "001") */
#define BRPHY3_GPHY_CORE_SHD18_010     0x09cf2054 /* Power/MII Control Register (Shadow Register Selector = "010") */
#define BRPHY3_GPHY_CORE_SHD18_011     0x09cf2056 /* IP Phone Register  (Shadow Register Selector = "011") */
#define BRPHY3_GPHY_CORE_SHD18_100     0x09cf2058 /* Misc Test Register  1 (Shadow Register Selector = "100") */
#define BRPHY3_GPHY_CORE_SHD18_101     0x09cf205a /* Misc Test Register  2 (Shadow Register Selector = "101") */
#define BRPHY3_GPHY_CORE_SHD18_110     0x09cf205c /* Manual IP Phone Seed Register (Shadow Register Selector = "110") */
#define BRPHY3_GPHY_CORE_SHD18_111     0x09cf205e /* Miscellanous Control Register (Shadow Register Selector = "111") */
#define BRPHY3_GPHY_CORE_EXP00         0x09cf2060 /* Transmit Packet Counter */
#define BRPHY3_GPHY_CORE_EXP01         0x09cf2062 /* Expansion Interrupt Status */
#define BRPHY3_GPHY_CORE_EXP02         0x09cf2064 /* Expansion Interrupt Mask */
#define BRPHY3_GPHY_CORE_EXP03         0x09cf2066 /* Spare Registers */
#define BRPHY3_GPHY_CORE_EXP04         0x09cf2068 /* Bicolor LED Selectors */
#define BRPHY3_GPHY_CORE_EXP05         0x09cf206a /* Bicolor LED Flash Rate Controls */
#define BRPHY3_GPHY_CORE_EXP06         0x09cf206c /* Bicolor LED Programmable Blink Controls */
#define BRPHY3_GPHY_CORE_EXP07         0x09cf206e /* Far End Fault */
#define BRPHY3_GPHY_CORE_EXP08         0x09cf2070 /* 10BT Controls */
#define BRPHY3_GPHY_CORE_EXP09         0x09cf2072 /* AMRR Controls */
#define BRPHY3_GPHY_CORE_EXP0A         0x09cf2074 /* DAC TEMPLATE Controls */
#define BRPHY3_GPHY_CORE_EXP0B         0x09cf2076 /* External Status */
#define BRPHY3_GPHY_CORE_EXP0C         0x09cf2078 /* Spare Registers */
#define BRPHY3_GPHY_CORE_EXP30         0x09cf2080 /* Late Collision Counters Status Register */
#define BRPHY3_GPHY_CORE_EXP31         0x09cf2082 /* Late Collision Counter [64:95] */
#define BRPHY3_GPHY_CORE_EXP32         0x09cf2084 /* Late Collision Counter [96:127] */
#define BRPHY3_GPHY_CORE_EXP33         0x09cf2086 /* Late Collision Counter [128:191] */
#define BRPHY3_GPHY_CORE_EXP34         0x09cf2088 /* Late Collision Counter [192:319] */
#define BRPHY3_GPHY_CORE_EXP35         0x09cf208a /* Late Collision Counter Threshold Register */
#define BRPHY3_GPHY_CORE_EXP36         0x09cf208c /* Clock PPM Detection between Recovery and Transmit Clocks */
#define BRPHY3_GPHY_CORE_EXP37         0x09cf208e /* Clock PPM Detection between GTX_CLK and Transmit Clocks */
#define BRPHY3_GPHY_CORE_EXP38         0x09cf2090 /* IP PHONE Cable Length Status Register */
#define BRPHY3_GPHY_CORE_EXP42         0x09cf20a2 /* Operating Mode Status */
#define BRPHY3_GPHY_CORE_EXP5F         0x09cf20be /* PLL Frequency Offset Testmode Control */
#define BRPHY3_GPHY_CORE_EXP70         0x09cf20e0 /* SOFT-RESET */
#define BRPHY3_GPHY_CORE_EXP71         0x09cf20e2 /* Serial LED Control 1 */
#define BRPHY3_GPHY_CORE_EXP72         0x09cf20e4 /* Serial LED Control 2 */
#define BRPHY3_GPHY_CORE_EXP73         0x09cf20e6 /* LED Gating 2 (Used for dual-media applications) */
#define BRPHY3_GPHY_CORE_EXP74         0x09cf20e8 /* LED Programmable Current Mode Control */
#define BRPHY3_GPHY_CORE_EXP75         0x09cf20ea /* CED LED Error Mask */
#define BRPHY3_GPHY_CORE_EXP78         0x09cf20f0 /* Misc Extended Control */
#define BRPHY3_GPHY_CORE_EXP7B         0x09cf20f6 /* I2C Control */
#define BRPHY3_GPHY_CORE_EXP7C         0x09cf20f8 /* I2C Status */
#define BRPHY3_GPHY_CORE_EXP7F         0x09cf20fe /* External MACSec Interface Control */
#define BRPHY3_GPHY_CORE_ALIAS_18      0x09cf2100 /* Alias to MII Reg 18 */
#define BRPHY3_GPHY_CORE_ALIAS_19      0x09cf2102 /* Alias to MII Reg 19 */
#define BRPHY3_GPHY_CORE_ALIAS_1A      0x09cf2104 /* Alias to MII Reg 1a */
#define BRPHY3_GPHY_CORE_ALIAS_1B      0x09cf2106 /* Alias to MII Reg 1b */
#define BRPHY3_GPHY_CORE_ALIAS_1C      0x09cf2108 /* Alias to MII Reg 1c */
#define BRPHY3_GPHY_CORE_ALIAS_1D      0x09cf210a /* Alias to MII Reg 1d */
#define BRPHY3_GPHY_CORE_REG_MAP_CTL   0x09cf210e /* MII Registers 10-1D mapping control */
#define BRPHY3_GPHY_CORE_EXP98         0x09cf2130 /* First Slice of Quad-GPHY only): CAL-BIAS Status */
#define BRPHY3_GPHY_CORE_EXP9C         0x09cf2138 /* SMII Control */
#define BRPHY3_GPHY_CORE_BT_LINK_FIX   0x09cf214a /* 10BT LINK FIX Register */
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG 0x09cf214c /* SyncE+ Debug */
#define BRPHY3_GPHY_CORE_SYNCE_PLUS    0x09cf214e /* SyncE+ Status and Control */
#define BRPHY3_GPHY_CORE_EXPA8         0x09cf2150 /* ADAPTIVE BIAS CONTROL */
#define BRPHY3_GPHY_CORE_EXPA9         0x09cf2152 /* spare register */
#define BRPHY3_GPHY_CORE_EXPAA         0x09cf2154 /* EEE Statistic timer 12hours lpi */
#define BRPHY3_GPHY_CORE_EXPAB         0x09cf2156 /* EEE Statistic timer 12hours local */
#define BRPHY3_GPHY_CORE_EXPAC         0x09cf2158 /* EEE Statistic loc lpi req 0_to_1 counter */
#define BRPHY3_GPHY_CORE_EXPAD         0x09cf215a /* EEE Statistic rem lpi_req 0_to_1 counter */
#define BRPHY3_GPHY_CORE_EXPAE         0x09cf215c /* spare register */
#define BRPHY3_GPHY_CORE_EXPAF         0x09cf215e /* EEE Statistic counters ctrl/status */
#define BRPHY3_GPHY_CORE_EXPB0         0x09cf2160 /* Bias Control 0 */
#define BRPHY3_GPHY_CORE_EXPB1         0x09cf2162 /* Bias Control 1 */
#define BRPHY3_GPHY_CORE_EXPB2         0x09cf2164 /* Bias Control 2 */
#define BRPHY3_GPHY_CORE_EXPE3         0x09cf2166 /* TX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY3_GPHY_CORE_EXPE4         0x09cf2168 /* TX PCS Delay 10BT (copper side) */
#define BRPHY3_GPHY_CORE_EXPE5         0x09cf216a /* TX PCS Delay (fiber side) */
#define BRPHY3_GPHY_CORE_EXPE6         0x09cf216c /* RX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY3_GPHY_CORE_EXPE7         0x09cf216e /* RX PCS Delay 10BT (copper side) */
#define BRPHY3_GPHY_CORE_EXPE8         0x09cf2170 /* RX PCS Delay (fiber side) */
#define BRPHY3_GPHY_CORE_EXPE9         0x09cf2172 /* P1588 TX/RX Cycle Delay */
#define BRPHY3_GPHY_CORE_EXPE0         0x09cf2174 /* TX PMA/PMD Delay (copper side) */
#define BRPHY3_GPHY_CORE_EXPE1         0x09cf2176 /* TX PMA/PMD Delay (fiber side) */
#define BRPHY3_GPHY_CORE_EXPE2         0x09cf2178 /* RX PMA/PMD Delay (copper side) */
#define BRPHY3_GPHY_CORE_EXPEA         0x09cf217a /* TX/RX Adjustable Cycle Delay */
#define BRPHY3_GPHY_CORE_LED_PRA_MODE  0x09cf2180 /* LED Proportional Rate Activity Control */
#define BRPHY3_GPHY_CORE_FIFO_CTL      0x09cf2182 /* FIFO Control Register */
#define BRPHY3_GPHY_CORE_EXPD8         0x09cf21b0 /* Halting agc/enc ctrl reg */
#define BRPHY3_GPHY_CORE_EXPF0         0x09cf21e0 /* RGMII IBS Control */
#define BRPHY3_GPHY_CORE_EXPF5         0x09cf21ea /* Time Sync */
#define BRPHY3_GPHY_CORE_EXPF6         0x09cf21ec /* Analog Power Control Status */
#define BRPHY3_GPHY_CORE_EXPF7         0x09cf21ee /* Auto-power Down Control Status */
#define BRPHY3_GPHY_CORE_EXPF8         0x09cf21f0 /* Trim Settings from Fuse & to Bias Block */
#define BRPHY3_GPHY_CORE_EXPF9         0x09cf21f2 /* reserved Register Bits */
#define BRPHY3_GPHY_CORE_EXPFA         0x09cf21f4 /* Hidden Identifier */
#define BRPHY3_GPHY_CORE_EXPFB         0x09cf21f6 /* TDR Override Values */
#define BRPHY3_GPHY_CORE_EXPFC         0x09cf21f8 /*  */
#define BRPHY3_GPHY_CORE_EXPFD         0x09cf21fa /* Clock gating control override value */
#define BRPHY3_GPHY_CORE_EXPFE         0x09cf21fc /* Clock gating control override enable */
#define BRPHY3_GPHY_CORE_EXPFF         0x09cf21fe /* Analog power control override */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_DSP_TAP
 ***************************************************************************/
#define BRPHY3_DSP_TAP_TAP0_C0         0x09cf2200 /* AGC Control/Status Register A (x4) */
#define BRPHY3_DSP_TAP_TAP0_C1         0x09cf2202 /* AGC Control/Status Register A (x4) */
#define BRPHY3_DSP_TAP_TAP0_C2         0x09cf2204 /* AGC Control/Status Register A (x4) */
#define BRPHY3_DSP_TAP_TAP0_C3         0x09cf2206 /* AGC Control/Status Register A (x4) */
#define BRPHY3_DSP_TAP_TAP1            0x09cf2208 /* IPRF Control register (x1) */
#define BRPHY3_DSP_TAP_TAP2_C0         0x09cf2210 /* MSE Status Register (x4) */
#define BRPHY3_DSP_TAP_TAP2_C1         0x09cf2212 /* MSE Status Register (x4) */
#define BRPHY3_DSP_TAP_TAP2_C2         0x09cf2214 /* MSE Status Register (x4) */
#define BRPHY3_DSP_TAP_TAP2_C3         0x09cf2216 /* MSE Status Register (x4) */
#define BRPHY3_DSP_TAP_TAP3_C0         0x09cf2218 /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY3_DSP_TAP_TAP3_C1         0x09cf221a /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY3_DSP_TAP_TAP3_C2         0x09cf221c /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY3_DSP_TAP_TAP3_C3         0x09cf221e /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY3_DSP_TAP_TAP4_C0         0x09cf2220 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY3_DSP_TAP_TAP4_C1         0x09cf2222 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY3_DSP_TAP_TAP4_C2         0x09cf2224 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY3_DSP_TAP_TAP4_C3         0x09cf2226 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY3_DSP_TAP_TAP5_C0         0x09cf2228 /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY3_DSP_TAP_TAP5_C1         0x09cf222a /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY3_DSP_TAP_TAP5_C2         0x09cf222c /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY3_DSP_TAP_TAP5_C3         0x09cf222e /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY3_DSP_TAP_TAP6            0x09cf2230 /* CFC Deadman Disable */
#define BRPHY3_DSP_TAP_TAP7_C0         0x09cf2238 /* BIST TEST 0 */
#define BRPHY3_DSP_TAP_TAP7_C1         0x09cf223a /* BIST TEST 1 */
#define BRPHY3_DSP_TAP_TAP7_C2         0x09cf223c /* BIST TEST 2 */
#define BRPHY3_DSP_TAP_TAP8_C0         0x09cf2240 /* ABIST TEST 0 */
#define BRPHY3_DSP_TAP_TAP8_C1         0x09cf2242 /* ABIST TEST 1 */
#define BRPHY3_DSP_TAP_TAP8_C2         0x09cf2244 /* ABIST TEST 2 */
#define BRPHY3_DSP_TAP_TAP8_C3         0x09cf2246 /* BR HPF Control */
#define BRPHY3_DSP_TAP_TAP9            0x09cf2248 /* Frequency Control/Status Register LSBs (x1) */
#define BRPHY3_DSP_TAP_TAP10           0x09cf224a /* PLL Bandwidth Control/Status and Path Metric Reset Register (x1) */
#define BRPHY3_DSP_TAP_TAP11           0x09cf224c /* PLL RCLK and TCLK Offset Freeze Register (x1) */
#define BRPHY3_DSP_TAP_TAP12_C0        0x09cf2250 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY3_DSP_TAP_TAP12_C1        0x09cf2252 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY3_DSP_TAP_TAP12_C2        0x09cf2254 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY3_DSP_TAP_TAP12_C3        0x09cf2256 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY3_DSP_TAP_TAP13           0x09cf2258 /* HPF Bandwidth Control and Disable ADC LSBs (x1) */
#define BRPHY3_DSP_TAP_TAP14           0x09cf225a /* MSE Threshold Register  #1 (x1) */
#define BRPHY3_DSP_TAP_TAP15           0x09cf225c /* MSE Threshold Register #2 (x1) */
#define BRPHY3_DSP_TAP_TAP16_C0        0x09cf2260 /* Logic Analyzer trigger delay (x1) */
#define BRPHY3_DSP_TAP_TAP16_C1        0x09cf2262 /* BIST CRC Monitor (x4) */
#define BRPHY3_DSP_TAP_TAP16_C2        0x09cf2264 /* BIST CRC Monitor (x4) */
#define BRPHY3_DSP_TAP_TAP16_C3        0x09cf2266 /* BIST CRC Monitor (x4) */
#define BRPHY3_DSP_TAP_TAP17_C0        0x09cf2268 /* Testmode testvalue (aliased with logic analyzer state selects) */
#define BRPHY3_DSP_TAP_TAP17_C1        0x09cf226a /* Testmode and logic analyzer controls #1 */
#define BRPHY3_DSP_TAP_TAP17_C2        0x09cf226c /* Logic analyzer controls #2 */
#define BRPHY3_DSP_TAP_TAP17_C3        0x09cf226e /* Testmode and logic analyzer controls #3 */
#define BRPHY3_DSP_TAP_TAP18_C0        0x09cf2270 /* Peak Noise detector (x4) */
#define BRPHY3_DSP_TAP_TAP18_C1        0x09cf2272 /* Peak Noise detector (x4) */
#define BRPHY3_DSP_TAP_TAP18_C2        0x09cf2274 /* Peak Noise detector (x4) */
#define BRPHY3_DSP_TAP_TAP18_C3        0x09cf2276 /* Peak Noise detector (x4) */
#define BRPHY3_DSP_TAP_TAP20           0x09cf2278 /* Echo Minimum Length and LMS/FIR delay adjustments (x1) */
#define BRPHY3_DSP_TAP_TAP21           0x09cf227a /* Phy Control Monitors #1 (x1) */
#define BRPHY3_DSP_TAP_TAP22           0x09cf227c /* Phy Control Monitors #2 (x1) */
#define BRPHY3_DSP_TAP_TAP23           0x09cf227e /* Phy Control Monitors #3 (x1) */
#define BRPHY3_DSP_TAP_TAP24           0x09cf2280 /* Phy Control Output Overrides #1 (x1) */
#define BRPHY3_DSP_TAP_TAP25           0x09cf2282 /* Phy Control Output Overrides #2 (x1) */
#define BRPHY3_DSP_TAP_TAP26           0x09cf2284 /* Phy Control Input Overrides #1 (x1) */
#define BRPHY3_DSP_TAP_TAP27           0x09cf2286 /* Phy Control Input Overrides #2 (x1) */
#define BRPHY3_DSP_TAP_TAP28           0x09cf2288 /* Phy Control Output Overrides #3 (x1) */
#define BRPHY3_DSP_TAP_TAP29           0x09cf228a /* Phy Control Force State/Timers/Alternate Behaviour Register #1 (x1) */
#define BRPHY3_DSP_TAP_TAP30           0x09cf228c /* Phy Control Force State/Timers/Alternate Behaviour Register #2 (x1) */
#define BRPHY3_DSP_TAP_TAP31_C0        0x09cf2290 /* Channel Swap Override */
#define BRPHY3_DSP_TAP_TAP32_C0        0x09cf2298 /* Transmit Testmode Sync Generation (x1) */
#define BRPHY3_DSP_TAP_FDFE_OV_RD      0x09cf229a /* FDFE Override/Read Control Register */
#define BRPHY3_DSP_TAP_FDFE_COEFF      0x09cf229c /* FDFE Coefficient Read Back Register */
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD 0x09cf229e /* FDFE Beta Threshold Control */
#define BRPHY3_DSP_TAP_TAP33_C0        0x09cf22a0 /* eee dsp test */
#define BRPHY3_DSP_TAP_TAP33_C1        0x09cf22a2 /* eee sigdet */
#define BRPHY3_DSP_TAP_TAP33_C2        0x09cf22a4 /* eee_lpi_timers */
#define BRPHY3_DSP_TAP_TAP33_C3        0x09cf22a6 /* spare register */
#define BRPHY3_DSP_TAP_TAP34_C0        0x09cf22a8 /* eee frequency control */
#define BRPHY3_DSP_TAP_TAP34_C1        0x09cf22aa /* eee Gigabit Mode BW control */
#define BRPHY3_DSP_TAP_TAP34_C2        0x09cf22ac /* eee 100TX Mode BW control */
#define BRPHY3_DSP_TAP_TAP34_C3        0x09cf22ae /* phasectl TPO monitor */
#define BRPHY3_DSP_TAP_TAP35_C0        0x09cf22b0 /* eee 100Base-tx timer control 1 */
#define BRPHY3_DSP_TAP_TAP35_C1        0x09cf22b2 /* eee 100Base-tx timer control 2 */
#define BRPHY3_DSP_TAP_TAP35_C2        0x09cf22b4 /* eee 100Base-tx timer misc control */
#define BRPHY3_DSP_TAP_TAP35_C3        0x09cf22b6 /* pcs_lpi_test */
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0  0x09cf22b8 /* Filter Freeze/Disable per channel Control */
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1  0x09cf22ba /* Filter Freeze/Disable per channel Control */
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2  0x09cf22bc /* Filter Freeze/Disable per channel Control */
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3  0x09cf22be /* Filter Freeze/Disable per channel Control */
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0 0x09cf22c0 /* FFEX Freeze/Disable per channel Control */
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1 0x09cf22c2 /* FFEX Freeze/Disable per channel Control */
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2 0x09cf22c4 /* FFEX Freeze/Disable per channel Control */
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3 0x09cf22c6 /* FFEX Freeze/Disable per channel Control */
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL 0x09cf22c8 /* EMI Datapath Control */
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2 0x09cf22ca /* EMI Datapath Control2 */
#define BRPHY3_DSP_TAP_FFEX_CTL        0x09cf22cc /* FFE X-tap Control */
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0 0x09cf22ce /* Phycontrol Breakpoint Control 0 */
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1 0x09cf22d0 /* Phycontrol Breakpoint Control 1 */
#define BRPHY3_DSP_TAP_FILTER_ADDR     0x09cf2360 /* DSP Coefficient Address Register */
#define BRPHY3_DSP_TAP_FILTER_CTL      0x09cf2362 /* DSP Control Register */
#define BRPHY3_DSP_TAP_FILTER_DATA     0x09cf2364 /* DSP Coefficient Read/Write Port */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_PLL_CTRL
 ***************************************************************************/
#define BRPHY3_PLL_CTRL_PLLCTRL_0      0x09cf2390 /* Analog pll control 0 */
#define BRPHY3_PLL_CTRL_PLLCTRL_1      0x09cf2392 /* Analog pll control 1 */
#define BRPHY3_PLL_CTRL_PLLCTRL_2      0x09cf2394 /* Analog pll control 2 */
#define BRPHY3_PLL_CTRL_PLLCTRL_3      0x09cf2396 /* Analog pll control 3 */
#define BRPHY3_PLL_CTRL_PLLCTRL_4      0x09cf2398 /* Analog pll control 4 */
#define BRPHY3_PLL_CTRL_PLLCTRL_5      0x09cf239a /* Analog pll control 5 */
#define BRPHY3_PLL_CTRL_PLLCTRL_6      0x09cf239c /* Analog pll control 6 */
#define BRPHY3_PLL_CTRL_PLL_STATUS_0   0x09cf23a0 /* Analog PLL Status 0 */
#define BRPHY3_PLL_CTRL_PLL_STATUS_1   0x09cf23a2 /* Analog PLL Status 1 */
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS 0x09cf23a4 /* AFE Signal detect */
#define BRPHY3_PLL_CTRL_PLLCTRL_7      0x09cf23a6 /* Analog pll control 7 */
#define BRPHY3_PLL_CTRL_PLLCTRL_8      0x09cf23a8 /* Analog pll control 8 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_AFE_CTRL
 ***************************************************************************/
#define BRPHY3_AFE_CTRL_RXCONFIG_0     0x09cf23c0 /* RXCONFIG 15:0 */
#define BRPHY3_AFE_CTRL_RXCONFIG_1     0x09cf23c2 /* RXCONFIG 31:16 */
#define BRPHY3_AFE_CTRL_RXCONFIG_2     0x09cf23c4 /* RXCONFIG 47:32 */
#define BRPHY3_AFE_CTRL_RXCONFIG_3     0x09cf23c6 /* RXCONFIG 63:48 */
#define BRPHY3_AFE_CTRL_RXCONFIG_4     0x09cf23c8 /* RXCONFIG 79:64 */
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP   0x09cf23ca /* RXCONFIG 86:80 and LP tuning */
#define BRPHY3_AFE_CTRL_TX_CONFIG_0    0x09cf23cc /* TXCONFIG 15:0 */
#define BRPHY3_AFE_CTRL_TX_CONFIG_1    0x09cf23ce /* TXCONFIG 31:16 */
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_0   0x09cf23d0 /* VDAC CURRENT Control 15:0 */
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_1   0x09cf23d2 /* VDAC CURRENT Control 31:16 */
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_2   0x09cf23d4 /* VDAC CURRENT Control 51:36 */
#define BRPHY3_AFE_CTRL_VDAC_OTHERS_0  0x09cf23d6 /* VDAC CURRENT 35:32 and others */
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS 0x09cf23d8 /* HPF trim and reserved bits */
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_0 0x09cf23da /* TXCONFIG 15:0 */
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_1 0x09cf23dc /* TXCONFIG 15:0 */
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_2 0x09cf23de /* TXCONFIG 15:0 */
#define BRPHY3_AFE_CTRL_TEMPSEN_OTHERS 0x09cf23e0 /* TEMPSEN_OTHERS 15:0 */
#define BRPHY3_AFE_CTRL_FUTURE_RSV     0x09cf23e2 /* FUTURE_RSV 15:0 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_ECD_CTRL
 ***************************************************************************/
#define BRPHY3_ECD_CTRL_EXPC0          0x09cf2540 /* ECD Control and Status */
#define BRPHY3_ECD_CTRL_EXPC1          0x09cf2542 /* ECD Fault Type */
#define BRPHY3_ECD_CTRL_EXPC2          0x09cf2544 /* ECD Pair A Length Results */
#define BRPHY3_ECD_CTRL_EXPC3          0x09cf2546 /* ECD Pair B Length Results */
#define BRPHY3_ECD_CTRL_EXPC4          0x09cf2548 /* ECD Pair C Length Results */
#define BRPHY3_ECD_CTRL_EXPC5          0x09cf254a /* ECD Pair D Length Results */
#define BRPHY3_ECD_CTRL_EXPC6          0x09cf254c /* ECD XTALK Map */
#define BRPHY3_ECD_CTRL_EXPC7          0x09cf254e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPC8          0x09cf2550 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPC9          0x09cf2552 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPCA          0x09cf2554 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPCB          0x09cf2556 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPCC          0x09cf2558 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPCD          0x09cf255a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPCE          0x09cf255c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPCF          0x09cf255e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE0          0x09cf2560 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE1          0x09cf2562 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE2          0x09cf2564 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE3          0x09cf2566 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE4          0x09cf2568 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE5          0x09cf256a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE6          0x09cf256c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE7          0x09cf256e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE8          0x09cf2570 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPE9          0x09cf2572 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPEA          0x09cf2574 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPEB          0x09cf2576 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPEC          0x09cf2578 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPED          0x09cf257a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPEE          0x09cf257c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY3_ECD_CTRL_EXPEF          0x09cf257e /* ECD EXTRA RESERVED REGISTER */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_BR_CTRL
 ***************************************************************************/
#define BRPHY3_BR_CTRL_EXP90           0x09cf2600 /* BroadReach LRE Misc Control */
#define BRPHY3_BR_CTRL_EXP91           0x09cf2602 /* BroadReach LRE Misc Control */
#define BRPHY3_BR_CTRL_EXP92           0x09cf2604 /* BroadReach LRE Misc Control */
#define BRPHY3_BR_CTRL_EXP93           0x09cf2606 /* BroadReach LDS  Control */
#define BRPHY3_BR_CTRL_EXP94           0x09cf2608 /* BroadReach LDS RX Control */
#define BRPHY3_BR_CTRL_EXP95           0x09cf260a /* BroadReach LDS RX Control */
#define BRPHY3_BR_CTRL_EXP96           0x09cf260c /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY3_BR_CTRL_EXP97           0x09cf260e /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY3_BR_CTRL_EXP99           0x09cf2612 /* BroadReach LDS Timer Control */
#define BRPHY3_BR_CTRL_EXP9A           0x09cf2614 /* LDS Status */
#define BRPHY3_BR_CTRL_EXP9B           0x09cf2616 /* BroadR-Reach PLL Control */
#define BRPHY3_BR_CTRL_EXP9D           0x09cf261a /* EoC Internal Control 1 */
#define BRPHY3_BR_CTRL_EXP9E           0x09cf261c /* LDS Length Threshold 0 */
#define BRPHY3_BR_CTRL_EXP9F           0x09cf261e /* LDS Length Threshold 1 */
#define BRPHY3_BR_CTRL_EXPA0           0x09cf2620 /* HLDS register, LDS extend advertisement register */
#define BRPHY3_BR_CTRL_EXPA1           0x09cf2622 /* HLDS register, LDS link partner extend ability register */
#define BRPHY3_BR_CTRL_EXPA2           0x09cf2624 /* HLDS Register */
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS 0x09cf2626 /* Broadreach Misc Status */
#define BRPHY3_BR_CTRL_BR250_CTL       0x09cf263c /* BR250 Control */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_BR_CL22_IEEE
 ***************************************************************************/
#define BRPHY3_BR_CL22_IEEE_MII_CTRL   0x09cfffc0 /* BR_LRE_Control_Register */
#define BRPHY3_BR_CL22_IEEE_MII_STAT   0x09cfffc2 /* BR_LRE_Status_Register */
#define BRPHY3_BR_CL22_IEEE_PHY_ID_MSB 0x09cfffc4 /* PHY_Identifier_MSB_Register */
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB 0x09cfffc6 /* PHY_Identifier_LSB_Register */
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP 0x09cfffc8 /* LDS_Advertised_Ability_Register (Base Page) */
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL 0x09cfffca /* LDS_Advertised_Control_Register */
#define BRPHY3_BR_CL22_IEEE_LDS_ABILITY 0x09cfffcc /* LDS_Ability_Register (Next Page) */
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP 0x09cfffce /* LDS_Link_Partner_Ability_Base_Page_Register (Base Page) */
#define BRPHY3_BR_CL22_IEEE_LDS_LP_MSG_NXTP 0x09cfffd0 /* LDS_Link_Partners_Nxt_Pg_Msg_Register (Next Page) */
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP 0x09cfffd2 /* LDS_Link_Partner_Ability_Nxt_Pg_Register (Next Page) */
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP 0x09cfffd4 /* LDS_Expansion_Register */
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT 0x09cfffd6 /* IEEE_Extended_Status_Register */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_CL45DEV1
 ***************************************************************************/
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1  0x0a020000 /* IEEE PMA/PMD CONTROL 1 REGISTER (REG 1.0) */
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1   0x0a020002 /* IEEE PMA/PMD STATUS 1 REGISTER  (REG 1.1) */
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID0 0x0a020004 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 0 (REG 1.2) */
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1 0x0a020006 /* IEEE PMA/PMD DEVICE IDENTIFIER PART 1 (REG 1.3) */
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0  0x0a02000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 1.5) */
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1  0x0a02000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 1.6) */
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID0 0x0a02001c /* PMA/PMD PACKAGE IDENTIFIER (REG 1.14) */
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID1 0x0a02001e /* PMA/PMD PACKAGE IDENTIFIER (REG 1.15) */
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP 0x0a020e10 /* TimeSync PMA/PMD capability (REG 1.1800) */
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x0a020e12 /* Maximum PMA/PMD transmit path data delay, lower (REG 1.1801) */
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x0a020e14 /* Maximum PMA/PMD transmit path data delay, upper (REG 1.1802) */
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x0a020e16 /* Minimum PMA/PMD transmit path data delay, lower (REG 1.1803) */
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x0a020e18 /* Minimum PMA/PMD transmit path data delay, upper (REG 1.1804) */
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x0a020e1a /* Maximum PMA/PMD receive path data delay, lower (REG 1.1805) */
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x0a020e1c /* Maximum PMA/PMD receive path data delay, upper (REG 1.1806) */
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x0a020e1e /* Minimum PMA/PMD receive path data delay, lower (REG 1.1807) */
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x0a020e20 /* Minimum PMA/PMD receive path data delay, upper (REG 1.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_CL45DEV3
 ***************************************************************************/
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1  0x0a060000 /* IEEE PCS CONTROL 1 REGISTER (REG 3.0) */
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1   0x0a060002 /* IEEE PCS STATUS 1 REGISTER  (REG 3.1) */
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID0 0x0a060004 /* IEEE PCS DEVICE IDENTIFIER PART 0 (REG 3.2) */
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1 0x0a060006 /* IEEE PCS DEVICE IDENTIFIER PART 1 (REG 3.3) */
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0  0x0a06000a /* DEVICES IN PACKAGE REGISTER PART 0 (REG 3.5) */
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1  0x0a06000c /* DEVICES IN PACKAGE REGISTER PART 1 (REG 3.6) */
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID0 0x0a06001c /* PCS PACKAGE IDENTIFIER (REG 3.14) */
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID1 0x0a06001e /* PCS PACKAGE IDENTIFIER (REG 3.15) */
#define BRPHY4_CL45DEV3_PCS_EEE_CAP    0x0a060028 /* PCS_EEE_CAP(REG 3.20) */
#define BRPHY4_CL45DEV3_PCS_EEE_WAKE_ERR_CNT 0x0a06002c /* PCS_EEE_Wake_Err_Cnt(REG 3.22) */
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP 0x0a060e10 /* TimeSync PCS capability (REG 3.1800) */
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER 0x0a060e12 /* Maximum PCS transmit path data delay, lower (REG 3.1801) */
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER 0x0a060e14 /* Maximum PCS transmit path data delay, upper (REG 3.1802) */
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER 0x0a060e16 /* Minimum PCS transmit path data delay, lower (REG 3.1803) */
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER 0x0a060e18 /* Minimum PCS transmit path data delay, upper (REG 3.1804) */
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER 0x0a060e1a /* Maximum PCS receive path data delay, lower (REG 3.1805) */
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER 0x0a060e1c /* Maximum PCS receive path data delay, upper (REG 3.1806) */
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER 0x0a060e1e /* Minimum PCS receive path data delay, lower (REG 3.1807) */
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER 0x0a060e20 /* Minimum PCS receive path data delay, upper (REG 3.1808) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_CL45DEV7
 ***************************************************************************/
#define BRPHY4_CL45DEV7_AN_CTRL        0x0a0e0000 /* Auto Neg Extended Next Page Control     (0x0000) (REG 7.0) */
#define BRPHY4_CL45DEV7_AN_STAT        0x0a0e0002 /* AN Status (0x0001) (REG 7.1) */
#define BRPHY4_CL45DEV7_AN_DEV_ID_LSB  0x0a0e0004 /* Auto Neg Device Identifier Lower 16 bit (0x0002) (REG 7.2) */
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB  0x0a0e0006 /* Auto Neg Device Identifier Upper 16 bit (0x0003) (REG 7.3) */
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB 0x0a0e000a /* Auto Neg Device In Package Lower 16 bit (0x0005) (REG 7.5) */
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB 0x0a0e000c /* Auto Neg Device In Package Upper 16 bit (0x0006) (REG 7.6) */
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_LSB 0x0a0e001c /* Auto Neg Package ID Lower 16 bit(0x000e) (REG 7.14) */
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_MSB 0x0a0e001e /* Auto Neg Package ID Upper 16 bit(0x000f) (REG 7.15) */
#define BRPHY4_CL45DEV7_AN_AD          0x0a0e0020 /* Auto Neg AD(0x0010) (REG 7.16) */
#define BRPHY4_CL45DEV7_AN_LPA         0x0a0e0026 /* AN LP base page ability (0x0013) (REG 7.19) */
#define BRPHY4_CL45DEV7_AN_XNPA        0x0a0e002c /* AN XNP transmit A (0x0016) (REG 7.22) */
#define BRPHY4_CL45DEV7_AN_XNPB        0x0a0e002e /* AN XNP transmit B (0x0017) (REG 7.23) */
#define BRPHY4_CL45DEV7_AN_XNPC        0x0a0e0030 /* AN XNP transmit C (0x0018) (REG 7.24) */
#define BRPHY4_CL45DEV7_LP_XNPA        0x0a0e0032 /* AN LP XNP ability A (0x0019) (REG 7.25) */
#define BRPHY4_CL45DEV7_LP_XNPB        0x0a0e0034 /* AN LP XNP ability B (0x001a) (REG 7.26) */
#define BRPHY4_CL45DEV7_LP_XNPC        0x0a0e0036 /* AN LP XNP ability C (0x001b) (REG 7.27) */
#define BRPHY4_CL45DEV7_TENG_AN_CTRL   0x0a0e0040 /* 10G Base-T AN Control Register (0x0020) (REG 7.32) */
#define BRPHY4_CL45DEV7_TENG_AN_STAT   0x0a0e0042 /* 10G Base-T AN Status Register  (0x0021) (REG 7.33) */
#define BRPHY4_CL45DEV7_EEE_ADV        0x0a0e0078 /* EEE Advertisement (0x003C) (REG 7.60 ???) */
#define BRPHY4_CL45DEV7_EEE_LP_ADV     0x0a0e007a /* EEE Link Partner Advertisement (0x003D) (REG 7.61 ???) */
#define BRPHY4_CL45DEV7_EEE_MODE_CTL   0x0a0e007c /* EEE Mode Control (0x003E) (REG 7.62 ???) */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_CL45VEN
 ***************************************************************************/
#define BRPHY4_CL45VEN_FORCE_LINK      0x0a0f0000 /* Force Link Register */
#define BRPHY4_CL45VEN_SELECTIVE_RESET 0x0a0f0002 /* Selective Reset Register */
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS 0x0a0f0004 /* Test State Machine For Extended Next Pages Register --mvadkert */
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS 0x0a0f0006 /* Test State Machine For Next Pages Register --mvadkert */
#define BRPHY4_CL45VEN_AN_MAN_TEST     0x0a0f0032 /* Auto Negotiation Manual Test Register */
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A 0x0a0f0034 /* Auto Negotiation Manual Link Partners Abilities Register A */
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B 0x0a0f0036 /* Auto Negotiation Manual Link Partners Abilities Register B */
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_A 0x0a0f0038 /* Link Partner Next Page */
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_B 0x0a0f003a /* Link Partner Next Page (cont.) */
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_C 0x0a0f003c /* Link Partner Next Page (cont.) */
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_D 0x0a0f003e /* Link Partner Next Page (cont.) */
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_E 0x0a0f0040 /* Link Partner Next Page (cont.) */
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_F 0x0a0f0042 /* Link Partner Next Page (cont.) */
#define BRPHY4_CL45VEN_EPON_CTRL_REG   0x0a0f0046 /* EPON mode control register */
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A 0x0a0f0060 /* EEE Test Control Register A eee_test_control_bus[15:0] */
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B 0x0a0f0062 /* EEE Test Control Register B eee_test_control_bus[31:16] */
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C 0x0a0f0064 /* EEE Test Control Register C eee_test_control_bus[47:32] */
#define BRPHY4_CL45VEN_EEE_SPARE_1     0x0a0f0076 /* EEE Spare Register 1 */
#define BRPHY4_CL45VEN_EEE_SPARE_2     0x0a0f0078 /* EEE Spare Register 2 */
#define BRPHY4_CL45VEN_EEE_CONTROL     0x0a0f007a /* EEE Control Register */
#define BRPHY4_CL45VEN_EEE_RES_STAT    0x0a0f007c /* EEE Resolution Status Register */
#define BRPHY4_CL45VEN_LPI_MODE_CNTR   0x0a0f007e /* LPI Mode Counter Register */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_A 0x0a0f0080 /* Local Device Message 5 */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_B 0x0a0f0082 /* Local Device Message 5 cont. */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_C 0x0a0f0084 /* Local Device Message 5 cont. */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_D 0x0a0f0086 /* Local Device Message 5 cont. */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A 0x0a0f0088 /* Link Partner Message 5 */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B 0x0a0f008a /* Link Partner Message 5 cont. */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C 0x0a0f008c /* Link Partner Message 5 cont. */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D 0x0a0f008e /* Link Partner Message 5 cont. */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_A 0x0a0f0090 /* Local Device Message 6 */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B 0x0a0f0092 /* Local Device Message 6 cont. */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C 0x0a0f0094 /* Local Device Message 6 cont. */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_D 0x0a0f0096 /* Local Device Message 6 cont. */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A 0x0a0f0098 /* Link Partner Message 6 */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B 0x0a0f009a /* Link Partner Message 6 cont. */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C 0x0a0f009c /* Link Partner Message 6 cont. */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D 0x0a0f009e /* Link Partner Message 6 cont. */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_GPHY_CORE
 ***************************************************************************/
#define BRPHY4_GPHY_CORE_BASE10        0x0a0f2000 /* PHY_Extended_ctl_Register */
#define BRPHY4_GPHY_CORE_BASE11        0x0a0f2002 /* PHY_Extended_Status_Register (copper side only) */
#define BRPHY4_GPHY_CORE_BASE12        0x0a0f2004 /* Receive_Error_Cntr_Register */
#define BRPHY4_GPHY_CORE_BASE13        0x0a0f2006 /* False_Carrier_Sense_Cntr_Register */
#define BRPHY4_GPHY_CORE_BASE14        0x0a0f2008 /* Local_Remote_Receiver_NOT_OK_Cntrs_Register */
#define BRPHY4_GPHY_CORE_EXP45         0x0a0f200a /* Pattern Generator Control Register */
#define BRPHY4_GPHY_CORE_EXP46         0x0a0f200b /* Pattern Generator Status Register */
#define BRPHY4_GPHY_CORE_BASE19        0x0a0f2012 /* Auxiliary Status Summary (copper side only) */
#define BRPHY4_GPHY_CORE_BASE1A        0x0a0f2014 /* Interrupt Status Register (copper side only) */
#define BRPHY4_GPHY_CORE_BASE1B        0x0a0f2016 /* Interrupt Mask Register */
#define BRPHY4_GPHY_CORE_BASE1D_SHD    0x0a0f2018 /* HCD Status Register */
#define BRPHY4_GPHY_CORE_BASE1D        0x0a0f201a /* Master/Slave Seed Register */
#define BRPHY4_GPHY_CORE_BASE1E        0x0a0f201c /* Test1_Register */
#define BRPHY4_GPHY_CORE_BASE1F        0x0a0f201e /* Test2_Register */
#define BRPHY4_GPHY_CORE_SHD1C_00      0x0a0f2020 /* Cabletron LED Register (Shadow Register Selector = "00h") */
#define BRPHY4_GPHY_CORE_SHD1C_01      0x0a0f2022 /* TVCO Selection Register (Shadow Register Selector = "01h") */
#define BRPHY4_GPHY_CORE_SHD1C_02      0x0a0f2024 /* reserved Control 1 Register (Shadow Register Selector = "02h") */
#define BRPHY4_GPHY_CORE_SHD1C_03      0x0a0f2026 /* Clock Alignment Control Regsiter (Shadow Register Selector = "03h") */
#define BRPHY4_GPHY_CORE_SHD1C_04      0x0a0f2028 /* reserved Control 2 Register (Shadow Register Selector = "04h") */
#define BRPHY4_GPHY_CORE_SHD1C_05      0x0a0f202a /* reserved Control 3 Register (Shadow Register Selector = "05h") */
#define BRPHY4_GPHY_CORE_SHD1C_06      0x0a0f202c /* Tdr Control 1 Register (Shadow Register Selector = "06h") */
#define BRPHY4_GPHY_CORE_SHD1C_07      0x0a0f202e /* Tdr Control 2 Register (Shadow Register Selector = "07h") */
#define BRPHY4_GPHY_CORE_SHD1C_08      0x0a0f2030 /* Led Status Register (Shadow Register Selector = "08h") */
#define BRPHY4_GPHY_CORE_SHD1C_09      0x0a0f2032 /* Led Control Register (Shadow Register Selector = "09h") */
#define BRPHY4_GPHY_CORE_SHD1C_0A      0x0a0f2034 /* Auto-Power Down Register (Shadow Register Selector = "0ah") */
#define BRPHY4_GPHY_CORE_SHD1C_0B      0x0a0f2036 /* reserved Control 4 Register (Shadow Register Selector = "0bh") */
#define BRPHY4_GPHY_CORE_SHD1C_0D      0x0a0f203a /* LED Selector 1 Register (Shadow Register Selector = "0dh") */
#define BRPHY4_GPHY_CORE_SHD1C_0E      0x0a0f203c /* LED Selector 2 Register (Shadow Register Selector = "0eh") */
#define BRPHY4_GPHY_CORE_SHD1C_0F      0x0a0f203e /* LED GPIO Control/Status Register (Shadow Register Selector = "0fh") */
#define BRPHY4_GPHY_CORE_SHD1C_10      0x0a0f2040 /* Cisco Enhanced Linkstatus Mode Control Register (Shadow Register Selector = "10h") */
#define BRPHY4_GPHY_CORE_SHD1C_1F      0x0a0f2042 /* Mode Control Register (Shadow Register Selector = "1fh") */
#define BRPHY4_GPHY_CORE_SHD18_000     0x0a0f2050 /* Auxiliary Control Register (Shadow Register Selector = "000") */
#define BRPHY4_GPHY_CORE_SHD18_001     0x0a0f2052 /* 10 Base-T Register (Shadow Register Selector = "001") */
#define BRPHY4_GPHY_CORE_SHD18_010     0x0a0f2054 /* Power/MII Control Register (Shadow Register Selector = "010") */
#define BRPHY4_GPHY_CORE_SHD18_011     0x0a0f2056 /* IP Phone Register  (Shadow Register Selector = "011") */
#define BRPHY4_GPHY_CORE_SHD18_100     0x0a0f2058 /* Misc Test Register  1 (Shadow Register Selector = "100") */
#define BRPHY4_GPHY_CORE_SHD18_101     0x0a0f205a /* Misc Test Register  2 (Shadow Register Selector = "101") */
#define BRPHY4_GPHY_CORE_SHD18_110     0x0a0f205c /* Manual IP Phone Seed Register (Shadow Register Selector = "110") */
#define BRPHY4_GPHY_CORE_SHD18_111     0x0a0f205e /* Miscellanous Control Register (Shadow Register Selector = "111") */
#define BRPHY4_GPHY_CORE_EXP00         0x0a0f2060 /* Transmit Packet Counter */
#define BRPHY4_GPHY_CORE_EXP01         0x0a0f2062 /* Expansion Interrupt Status */
#define BRPHY4_GPHY_CORE_EXP02         0x0a0f2064 /* Expansion Interrupt Mask */
#define BRPHY4_GPHY_CORE_EXP03         0x0a0f2066 /* Spare Registers */
#define BRPHY4_GPHY_CORE_EXP04         0x0a0f2068 /* Bicolor LED Selectors */
#define BRPHY4_GPHY_CORE_EXP05         0x0a0f206a /* Bicolor LED Flash Rate Controls */
#define BRPHY4_GPHY_CORE_EXP06         0x0a0f206c /* Bicolor LED Programmable Blink Controls */
#define BRPHY4_GPHY_CORE_EXP07         0x0a0f206e /* Far End Fault */
#define BRPHY4_GPHY_CORE_EXP08         0x0a0f2070 /* 10BT Controls */
#define BRPHY4_GPHY_CORE_EXP09         0x0a0f2072 /* AMRR Controls */
#define BRPHY4_GPHY_CORE_EXP0A         0x0a0f2074 /* DAC TEMPLATE Controls */
#define BRPHY4_GPHY_CORE_EXP0B         0x0a0f2076 /* External Status */
#define BRPHY4_GPHY_CORE_EXP0C         0x0a0f2078 /* Spare Registers */
#define BRPHY4_GPHY_CORE_EXP30         0x0a0f2080 /* Late Collision Counters Status Register */
#define BRPHY4_GPHY_CORE_EXP31         0x0a0f2082 /* Late Collision Counter [64:95] */
#define BRPHY4_GPHY_CORE_EXP32         0x0a0f2084 /* Late Collision Counter [96:127] */
#define BRPHY4_GPHY_CORE_EXP33         0x0a0f2086 /* Late Collision Counter [128:191] */
#define BRPHY4_GPHY_CORE_EXP34         0x0a0f2088 /* Late Collision Counter [192:319] */
#define BRPHY4_GPHY_CORE_EXP35         0x0a0f208a /* Late Collision Counter Threshold Register */
#define BRPHY4_GPHY_CORE_EXP36         0x0a0f208c /* Clock PPM Detection between Recovery and Transmit Clocks */
#define BRPHY4_GPHY_CORE_EXP37         0x0a0f208e /* Clock PPM Detection between GTX_CLK and Transmit Clocks */
#define BRPHY4_GPHY_CORE_EXP38         0x0a0f2090 /* IP PHONE Cable Length Status Register */
#define BRPHY4_GPHY_CORE_EXP42         0x0a0f20a2 /* Operating Mode Status */
#define BRPHY4_GPHY_CORE_EXP5F         0x0a0f20be /* PLL Frequency Offset Testmode Control */
#define BRPHY4_GPHY_CORE_EXP70         0x0a0f20e0 /* SOFT-RESET */
#define BRPHY4_GPHY_CORE_EXP71         0x0a0f20e2 /* Serial LED Control 1 */
#define BRPHY4_GPHY_CORE_EXP72         0x0a0f20e4 /* Serial LED Control 2 */
#define BRPHY4_GPHY_CORE_EXP73         0x0a0f20e6 /* LED Gating 2 (Used for dual-media applications) */
#define BRPHY4_GPHY_CORE_EXP74         0x0a0f20e8 /* LED Programmable Current Mode Control */
#define BRPHY4_GPHY_CORE_EXP75         0x0a0f20ea /* CED LED Error Mask */
#define BRPHY4_GPHY_CORE_EXP78         0x0a0f20f0 /* Misc Extended Control */
#define BRPHY4_GPHY_CORE_EXP7B         0x0a0f20f6 /* I2C Control */
#define BRPHY4_GPHY_CORE_EXP7C         0x0a0f20f8 /* I2C Status */
#define BRPHY4_GPHY_CORE_EXP7F         0x0a0f20fe /* External MACSec Interface Control */
#define BRPHY4_GPHY_CORE_ALIAS_18      0x0a0f2100 /* Alias to MII Reg 18 */
#define BRPHY4_GPHY_CORE_ALIAS_19      0x0a0f2102 /* Alias to MII Reg 19 */
#define BRPHY4_GPHY_CORE_ALIAS_1A      0x0a0f2104 /* Alias to MII Reg 1a */
#define BRPHY4_GPHY_CORE_ALIAS_1B      0x0a0f2106 /* Alias to MII Reg 1b */
#define BRPHY4_GPHY_CORE_ALIAS_1C      0x0a0f2108 /* Alias to MII Reg 1c */
#define BRPHY4_GPHY_CORE_ALIAS_1D      0x0a0f210a /* Alias to MII Reg 1d */
#define BRPHY4_GPHY_CORE_REG_MAP_CTL   0x0a0f210e /* MII Registers 10-1D mapping control */
#define BRPHY4_GPHY_CORE_EXP98         0x0a0f2130 /* First Slice of Quad-GPHY only): CAL-BIAS Status */
#define BRPHY4_GPHY_CORE_EXP9C         0x0a0f2138 /* SMII Control */
#define BRPHY4_GPHY_CORE_BT_LINK_FIX   0x0a0f214a /* 10BT LINK FIX Register */
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG 0x0a0f214c /* SyncE+ Debug */
#define BRPHY4_GPHY_CORE_SYNCE_PLUS    0x0a0f214e /* SyncE+ Status and Control */
#define BRPHY4_GPHY_CORE_EXPA8         0x0a0f2150 /* ADAPTIVE BIAS CONTROL */
#define BRPHY4_GPHY_CORE_EXPA9         0x0a0f2152 /* spare register */
#define BRPHY4_GPHY_CORE_EXPAA         0x0a0f2154 /* EEE Statistic timer 12hours lpi */
#define BRPHY4_GPHY_CORE_EXPAB         0x0a0f2156 /* EEE Statistic timer 12hours local */
#define BRPHY4_GPHY_CORE_EXPAC         0x0a0f2158 /* EEE Statistic loc lpi req 0_to_1 counter */
#define BRPHY4_GPHY_CORE_EXPAD         0x0a0f215a /* EEE Statistic rem lpi_req 0_to_1 counter */
#define BRPHY4_GPHY_CORE_EXPAE         0x0a0f215c /* spare register */
#define BRPHY4_GPHY_CORE_EXPAF         0x0a0f215e /* EEE Statistic counters ctrl/status */
#define BRPHY4_GPHY_CORE_EXPB0         0x0a0f2160 /* Bias Control 0 */
#define BRPHY4_GPHY_CORE_EXPB1         0x0a0f2162 /* Bias Control 1 */
#define BRPHY4_GPHY_CORE_EXPB2         0x0a0f2164 /* Bias Control 2 */
#define BRPHY4_GPHY_CORE_EXPE3         0x0a0f2166 /* TX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY4_GPHY_CORE_EXPE4         0x0a0f2168 /* TX PCS Delay 10BT (copper side) */
#define BRPHY4_GPHY_CORE_EXPE5         0x0a0f216a /* TX PCS Delay (fiber side) */
#define BRPHY4_GPHY_CORE_EXPE6         0x0a0f216c /* RX PCS Delay 1000BT and 100TX (copper side) */
#define BRPHY4_GPHY_CORE_EXPE7         0x0a0f216e /* RX PCS Delay 10BT (copper side) */
#define BRPHY4_GPHY_CORE_EXPE8         0x0a0f2170 /* RX PCS Delay (fiber side) */
#define BRPHY4_GPHY_CORE_EXPE9         0x0a0f2172 /* P1588 TX/RX Cycle Delay */
#define BRPHY4_GPHY_CORE_EXPE0         0x0a0f2174 /* TX PMA/PMD Delay (copper side) */
#define BRPHY4_GPHY_CORE_EXPE1         0x0a0f2176 /* TX PMA/PMD Delay (fiber side) */
#define BRPHY4_GPHY_CORE_EXPE2         0x0a0f2178 /* RX PMA/PMD Delay (copper side) */
#define BRPHY4_GPHY_CORE_EXPEA         0x0a0f217a /* TX/RX Adjustable Cycle Delay */
#define BRPHY4_GPHY_CORE_LED_PRA_MODE  0x0a0f2180 /* LED Proportional Rate Activity Control */
#define BRPHY4_GPHY_CORE_FIFO_CTL      0x0a0f2182 /* FIFO Control Register */
#define BRPHY4_GPHY_CORE_EXPD8         0x0a0f21b0 /* Halting agc/enc ctrl reg */
#define BRPHY4_GPHY_CORE_EXPF0         0x0a0f21e0 /* RGMII IBS Control */
#define BRPHY4_GPHY_CORE_EXPF5         0x0a0f21ea /* Time Sync */
#define BRPHY4_GPHY_CORE_EXPF6         0x0a0f21ec /* Analog Power Control Status */
#define BRPHY4_GPHY_CORE_EXPF7         0x0a0f21ee /* Auto-power Down Control Status */
#define BRPHY4_GPHY_CORE_EXPF8         0x0a0f21f0 /* Trim Settings from Fuse & to Bias Block */
#define BRPHY4_GPHY_CORE_EXPF9         0x0a0f21f2 /* reserved Register Bits */
#define BRPHY4_GPHY_CORE_EXPFA         0x0a0f21f4 /* Hidden Identifier */
#define BRPHY4_GPHY_CORE_EXPFB         0x0a0f21f6 /* TDR Override Values */
#define BRPHY4_GPHY_CORE_EXPFC         0x0a0f21f8 /*  */
#define BRPHY4_GPHY_CORE_EXPFD         0x0a0f21fa /* Clock gating control override value */
#define BRPHY4_GPHY_CORE_EXPFE         0x0a0f21fc /* Clock gating control override enable */
#define BRPHY4_GPHY_CORE_EXPFF         0x0a0f21fe /* Analog power control override */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_DSP_TAP
 ***************************************************************************/
#define BRPHY4_DSP_TAP_TAP0_C0         0x0a0f2200 /* AGC Control/Status Register A (x4) */
#define BRPHY4_DSP_TAP_TAP0_C1         0x0a0f2202 /* AGC Control/Status Register A (x4) */
#define BRPHY4_DSP_TAP_TAP0_C2         0x0a0f2204 /* AGC Control/Status Register A (x4) */
#define BRPHY4_DSP_TAP_TAP0_C3         0x0a0f2206 /* AGC Control/Status Register A (x4) */
#define BRPHY4_DSP_TAP_TAP1            0x0a0f2208 /* IPRF Control register (x1) */
#define BRPHY4_DSP_TAP_TAP2_C0         0x0a0f2210 /* MSE Status Register (x4) */
#define BRPHY4_DSP_TAP_TAP2_C1         0x0a0f2212 /* MSE Status Register (x4) */
#define BRPHY4_DSP_TAP_TAP2_C2         0x0a0f2214 /* MSE Status Register (x4) */
#define BRPHY4_DSP_TAP_TAP2_C3         0x0a0f2216 /* MSE Status Register (x4) */
#define BRPHY4_DSP_TAP_TAP3_C0         0x0a0f2218 /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY4_DSP_TAP_TAP3_C1         0x0a0f221a /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY4_DSP_TAP_TAP3_C2         0x0a0f221c /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY4_DSP_TAP_TAP3_C3         0x0a0f221e /* Soft Decision (From DFE) Status Register (x4) */
#define BRPHY4_DSP_TAP_TAP4_C0         0x0a0f2220 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY4_DSP_TAP_TAP4_C1         0x0a0f2222 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY4_DSP_TAP_TAP4_C2         0x0a0f2224 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY4_DSP_TAP_TAP4_C3         0x0a0f2226 /* Phase Status Register and Coarse AGC High Gear (x4) */
#define BRPHY4_DSP_TAP_TAP5_C0         0x0a0f2228 /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY4_DSP_TAP_TAP5_C1         0x0a0f222a /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY4_DSP_TAP_TAP5_C2         0x0a0f222c /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY4_DSP_TAP_TAP5_C3         0x0a0f222e /* Wire Map/Skew Control/Status and Echo/NEXT Control and Transmitter Control and ADC Control Register and Slicer Zero (x4) */
#define BRPHY4_DSP_TAP_TAP6            0x0a0f2230 /* CFC Deadman Disable */
#define BRPHY4_DSP_TAP_TAP7_C0         0x0a0f2238 /* BIST TEST 0 */
#define BRPHY4_DSP_TAP_TAP7_C1         0x0a0f223a /* BIST TEST 1 */
#define BRPHY4_DSP_TAP_TAP7_C2         0x0a0f223c /* BIST TEST 2 */
#define BRPHY4_DSP_TAP_TAP8_C0         0x0a0f2240 /* ABIST TEST 0 */
#define BRPHY4_DSP_TAP_TAP8_C1         0x0a0f2242 /* ABIST TEST 1 */
#define BRPHY4_DSP_TAP_TAP8_C2         0x0a0f2244 /* ABIST TEST 2 */
#define BRPHY4_DSP_TAP_TAP8_C3         0x0a0f2246 /* BR HPF Control */
#define BRPHY4_DSP_TAP_TAP9            0x0a0f2248 /* Frequency Control/Status Register LSBs (x1) */
#define BRPHY4_DSP_TAP_TAP10           0x0a0f224a /* PLL Bandwidth Control/Status and Path Metric Reset Register (x1) */
#define BRPHY4_DSP_TAP_TAP11           0x0a0f224c /* PLL RCLK and TCLK Offset Freeze Register (x1) */
#define BRPHY4_DSP_TAP_TAP12_C0        0x0a0f2250 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY4_DSP_TAP_TAP12_C1        0x0a0f2252 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY4_DSP_TAP_TAP12_C2        0x0a0f2254 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY4_DSP_TAP_TAP12_C3        0x0a0f2256 /* PLL ACLK Offset/Freeze Register (x4) */
#define BRPHY4_DSP_TAP_TAP13           0x0a0f2258 /* HPF Bandwidth Control and Disable ADC LSBs (x1) */
#define BRPHY4_DSP_TAP_TAP14           0x0a0f225a /* MSE Threshold Register  #1 (x1) */
#define BRPHY4_DSP_TAP_TAP15           0x0a0f225c /* MSE Threshold Register #2 (x1) */
#define BRPHY4_DSP_TAP_TAP16_C0        0x0a0f2260 /* Logic Analyzer trigger delay (x1) */
#define BRPHY4_DSP_TAP_TAP16_C1        0x0a0f2262 /* BIST CRC Monitor (x4) */
#define BRPHY4_DSP_TAP_TAP16_C2        0x0a0f2264 /* BIST CRC Monitor (x4) */
#define BRPHY4_DSP_TAP_TAP16_C3        0x0a0f2266 /* BIST CRC Monitor (x4) */
#define BRPHY4_DSP_TAP_TAP17_C0        0x0a0f2268 /* Testmode testvalue (aliased with logic analyzer state selects) */
#define BRPHY4_DSP_TAP_TAP17_C1        0x0a0f226a /* Testmode and logic analyzer controls #1 */
#define BRPHY4_DSP_TAP_TAP17_C2        0x0a0f226c /* Logic analyzer controls #2 */
#define BRPHY4_DSP_TAP_TAP17_C3        0x0a0f226e /* Testmode and logic analyzer controls #3 */
#define BRPHY4_DSP_TAP_TAP18_C0        0x0a0f2270 /* Peak Noise detector (x4) */
#define BRPHY4_DSP_TAP_TAP18_C1        0x0a0f2272 /* Peak Noise detector (x4) */
#define BRPHY4_DSP_TAP_TAP18_C2        0x0a0f2274 /* Peak Noise detector (x4) */
#define BRPHY4_DSP_TAP_TAP18_C3        0x0a0f2276 /* Peak Noise detector (x4) */
#define BRPHY4_DSP_TAP_TAP20           0x0a0f2278 /* Echo Minimum Length and LMS/FIR delay adjustments (x1) */
#define BRPHY4_DSP_TAP_TAP21           0x0a0f227a /* Phy Control Monitors #1 (x1) */
#define BRPHY4_DSP_TAP_TAP22           0x0a0f227c /* Phy Control Monitors #2 (x1) */
#define BRPHY4_DSP_TAP_TAP23           0x0a0f227e /* Phy Control Monitors #3 (x1) */
#define BRPHY4_DSP_TAP_TAP24           0x0a0f2280 /* Phy Control Output Overrides #1 (x1) */
#define BRPHY4_DSP_TAP_TAP25           0x0a0f2282 /* Phy Control Output Overrides #2 (x1) */
#define BRPHY4_DSP_TAP_TAP26           0x0a0f2284 /* Phy Control Input Overrides #1 (x1) */
#define BRPHY4_DSP_TAP_TAP27           0x0a0f2286 /* Phy Control Input Overrides #2 (x1) */
#define BRPHY4_DSP_TAP_TAP28           0x0a0f2288 /* Phy Control Output Overrides #3 (x1) */
#define BRPHY4_DSP_TAP_TAP29           0x0a0f228a /* Phy Control Force State/Timers/Alternate Behaviour Register #1 (x1) */
#define BRPHY4_DSP_TAP_TAP30           0x0a0f228c /* Phy Control Force State/Timers/Alternate Behaviour Register #2 (x1) */
#define BRPHY4_DSP_TAP_TAP31_C0        0x0a0f2290 /* Channel Swap Override */
#define BRPHY4_DSP_TAP_TAP32_C0        0x0a0f2298 /* Transmit Testmode Sync Generation (x1) */
#define BRPHY4_DSP_TAP_FDFE_OV_RD      0x0a0f229a /* FDFE Override/Read Control Register */
#define BRPHY4_DSP_TAP_FDFE_COEFF      0x0a0f229c /* FDFE Coefficient Read Back Register */
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD 0x0a0f229e /* FDFE Beta Threshold Control */
#define BRPHY4_DSP_TAP_TAP33_C0        0x0a0f22a0 /* eee dsp test */
#define BRPHY4_DSP_TAP_TAP33_C1        0x0a0f22a2 /* eee sigdet */
#define BRPHY4_DSP_TAP_TAP33_C2        0x0a0f22a4 /* eee_lpi_timers */
#define BRPHY4_DSP_TAP_TAP33_C3        0x0a0f22a6 /* spare register */
#define BRPHY4_DSP_TAP_TAP34_C0        0x0a0f22a8 /* eee frequency control */
#define BRPHY4_DSP_TAP_TAP34_C1        0x0a0f22aa /* eee Gigabit Mode BW control */
#define BRPHY4_DSP_TAP_TAP34_C2        0x0a0f22ac /* eee 100TX Mode BW control */
#define BRPHY4_DSP_TAP_TAP34_C3        0x0a0f22ae /* phasectl TPO monitor */
#define BRPHY4_DSP_TAP_TAP35_C0        0x0a0f22b0 /* eee 100Base-tx timer control 1 */
#define BRPHY4_DSP_TAP_TAP35_C1        0x0a0f22b2 /* eee 100Base-tx timer control 2 */
#define BRPHY4_DSP_TAP_TAP35_C2        0x0a0f22b4 /* eee 100Base-tx timer misc control */
#define BRPHY4_DSP_TAP_TAP35_C3        0x0a0f22b6 /* pcs_lpi_test */
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0  0x0a0f22b8 /* Filter Freeze/Disable per channel Control */
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1  0x0a0f22ba /* Filter Freeze/Disable per channel Control */
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2  0x0a0f22bc /* Filter Freeze/Disable per channel Control */
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3  0x0a0f22be /* Filter Freeze/Disable per channel Control */
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0 0x0a0f22c0 /* FFEX Freeze/Disable per channel Control */
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1 0x0a0f22c2 /* FFEX Freeze/Disable per channel Control */
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2 0x0a0f22c4 /* FFEX Freeze/Disable per channel Control */
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3 0x0a0f22c6 /* FFEX Freeze/Disable per channel Control */
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL 0x0a0f22c8 /* EMI Datapath Control */
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2 0x0a0f22ca /* EMI Datapath Control2 */
#define BRPHY4_DSP_TAP_FFEX_CTL        0x0a0f22cc /* FFE X-tap Control */
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0 0x0a0f22ce /* Phycontrol Breakpoint Control 0 */
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1 0x0a0f22d0 /* Phycontrol Breakpoint Control 1 */
#define BRPHY4_DSP_TAP_FILTER_ADDR     0x0a0f2360 /* DSP Coefficient Address Register */
#define BRPHY4_DSP_TAP_FILTER_CTL      0x0a0f2362 /* DSP Control Register */
#define BRPHY4_DSP_TAP_FILTER_DATA     0x0a0f2364 /* DSP Coefficient Read/Write Port */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_PLL_CTRL
 ***************************************************************************/
#define BRPHY4_PLL_CTRL_PLLCTRL_0      0x0a0f2390 /* Analog pll control 0 */
#define BRPHY4_PLL_CTRL_PLLCTRL_1      0x0a0f2392 /* Analog pll control 1 */
#define BRPHY4_PLL_CTRL_PLLCTRL_2      0x0a0f2394 /* Analog pll control 2 */
#define BRPHY4_PLL_CTRL_PLLCTRL_3      0x0a0f2396 /* Analog pll control 3 */
#define BRPHY4_PLL_CTRL_PLLCTRL_4      0x0a0f2398 /* Analog pll control 4 */
#define BRPHY4_PLL_CTRL_PLLCTRL_5      0x0a0f239a /* Analog pll control 5 */
#define BRPHY4_PLL_CTRL_PLLCTRL_6      0x0a0f239c /* Analog pll control 6 */
#define BRPHY4_PLL_CTRL_PLL_STATUS_0   0x0a0f23a0 /* Analog PLL Status 0 */
#define BRPHY4_PLL_CTRL_PLL_STATUS_1   0x0a0f23a2 /* Analog PLL Status 1 */
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS 0x0a0f23a4 /* AFE Signal detect */
#define BRPHY4_PLL_CTRL_PLLCTRL_7      0x0a0f23a6 /* Analog pll control 7 */
#define BRPHY4_PLL_CTRL_PLLCTRL_8      0x0a0f23a8 /* Analog pll control 8 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_AFE_CTRL
 ***************************************************************************/
#define BRPHY4_AFE_CTRL_RXCONFIG_0     0x0a0f23c0 /* RXCONFIG 15:0 */
#define BRPHY4_AFE_CTRL_RXCONFIG_1     0x0a0f23c2 /* RXCONFIG 31:16 */
#define BRPHY4_AFE_CTRL_RXCONFIG_2     0x0a0f23c4 /* RXCONFIG 47:32 */
#define BRPHY4_AFE_CTRL_RXCONFIG_3     0x0a0f23c6 /* RXCONFIG 63:48 */
#define BRPHY4_AFE_CTRL_RXCONFIG_4     0x0a0f23c8 /* RXCONFIG 79:64 */
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP   0x0a0f23ca /* RXCONFIG 86:80 and LP tuning */
#define BRPHY4_AFE_CTRL_TX_CONFIG_0    0x0a0f23cc /* TXCONFIG 15:0 */
#define BRPHY4_AFE_CTRL_TX_CONFIG_1    0x0a0f23ce /* TXCONFIG 31:16 */
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_0   0x0a0f23d0 /* VDAC CURRENT Control 15:0 */
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_1   0x0a0f23d2 /* VDAC CURRENT Control 31:16 */
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_2   0x0a0f23d4 /* VDAC CURRENT Control 51:36 */
#define BRPHY4_AFE_CTRL_VDAC_OTHERS_0  0x0a0f23d6 /* VDAC CURRENT 35:32 and others */
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS 0x0a0f23d8 /* HPF trim and reserved bits */
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_0 0x0a0f23da /* TXCONFIG 15:0 */
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_1 0x0a0f23dc /* TXCONFIG 15:0 */
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_2 0x0a0f23de /* TXCONFIG 15:0 */
#define BRPHY4_AFE_CTRL_TEMPSEN_OTHERS 0x0a0f23e0 /* TEMPSEN_OTHERS 15:0 */
#define BRPHY4_AFE_CTRL_FUTURE_RSV     0x0a0f23e2 /* FUTURE_RSV 15:0 */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_ECD_CTRL
 ***************************************************************************/
#define BRPHY4_ECD_CTRL_EXPC0          0x0a0f2540 /* ECD Control and Status */
#define BRPHY4_ECD_CTRL_EXPC1          0x0a0f2542 /* ECD Fault Type */
#define BRPHY4_ECD_CTRL_EXPC2          0x0a0f2544 /* ECD Pair A Length Results */
#define BRPHY4_ECD_CTRL_EXPC3          0x0a0f2546 /* ECD Pair B Length Results */
#define BRPHY4_ECD_CTRL_EXPC4          0x0a0f2548 /* ECD Pair C Length Results */
#define BRPHY4_ECD_CTRL_EXPC5          0x0a0f254a /* ECD Pair D Length Results */
#define BRPHY4_ECD_CTRL_EXPC6          0x0a0f254c /* ECD XTALK Map */
#define BRPHY4_ECD_CTRL_EXPC7          0x0a0f254e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPC8          0x0a0f2550 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPC9          0x0a0f2552 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPCA          0x0a0f2554 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPCB          0x0a0f2556 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPCC          0x0a0f2558 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPCD          0x0a0f255a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPCE          0x0a0f255c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPCF          0x0a0f255e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE0          0x0a0f2560 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE1          0x0a0f2562 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE2          0x0a0f2564 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE3          0x0a0f2566 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE4          0x0a0f2568 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE5          0x0a0f256a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE6          0x0a0f256c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE7          0x0a0f256e /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE8          0x0a0f2570 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPE9          0x0a0f2572 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPEA          0x0a0f2574 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPEB          0x0a0f2576 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPEC          0x0a0f2578 /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPED          0x0a0f257a /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPEE          0x0a0f257c /* ECD EXTRA RESERVED REGISTER */
#define BRPHY4_ECD_CTRL_EXPEF          0x0a0f257e /* ECD EXTRA RESERVED REGISTER */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_BR_CTRL
 ***************************************************************************/
#define BRPHY4_BR_CTRL_EXP90           0x0a0f2600 /* BroadReach LRE Misc Control */
#define BRPHY4_BR_CTRL_EXP91           0x0a0f2602 /* BroadReach LRE Misc Control */
#define BRPHY4_BR_CTRL_EXP92           0x0a0f2604 /* BroadReach LRE Misc Control */
#define BRPHY4_BR_CTRL_EXP93           0x0a0f2606 /* BroadReach LDS  Control */
#define BRPHY4_BR_CTRL_EXP94           0x0a0f2608 /* BroadReach LDS RX Control */
#define BRPHY4_BR_CTRL_EXP95           0x0a0f260a /* BroadReach LDS RX Control */
#define BRPHY4_BR_CTRL_EXP96           0x0a0f260c /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY4_BR_CTRL_EXP97           0x0a0f260e /* BroadReach LDS Scan, ARB and TX Status */
#define BRPHY4_BR_CTRL_EXP99           0x0a0f2612 /* BroadReach LDS Timer Control */
#define BRPHY4_BR_CTRL_EXP9A           0x0a0f2614 /* LDS Status */
#define BRPHY4_BR_CTRL_EXP9B           0x0a0f2616 /* BroadR-Reach PLL Control */
#define BRPHY4_BR_CTRL_EXP9D           0x0a0f261a /* EoC Internal Control 1 */
#define BRPHY4_BR_CTRL_EXP9E           0x0a0f261c /* LDS Length Threshold 0 */
#define BRPHY4_BR_CTRL_EXP9F           0x0a0f261e /* LDS Length Threshold 1 */
#define BRPHY4_BR_CTRL_EXPA0           0x0a0f2620 /* HLDS register, LDS extend advertisement register */
#define BRPHY4_BR_CTRL_EXPA1           0x0a0f2622 /* HLDS register, LDS link partner extend ability register */
#define BRPHY4_BR_CTRL_EXPA2           0x0a0f2624 /* HLDS Register */
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS 0x0a0f2626 /* Broadreach Misc Status */
#define BRPHY4_BR_CTRL_BR250_CTL       0x0a0f263c /* BR250 Control */


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_BR_CL22_IEEE
 ***************************************************************************/
#define BRPHY4_BR_CL22_IEEE_MII_CTRL   0x0a0fffc0 /* BR_LRE_Control_Register */
#define BRPHY4_BR_CL22_IEEE_MII_STAT   0x0a0fffc2 /* BR_LRE_Status_Register */
#define BRPHY4_BR_CL22_IEEE_PHY_ID_MSB 0x0a0fffc4 /* PHY_Identifier_MSB_Register */
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB 0x0a0fffc6 /* PHY_Identifier_LSB_Register */
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP 0x0a0fffc8 /* LDS_Advertised_Ability_Register (Base Page) */
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL 0x0a0fffca /* LDS_Advertised_Control_Register */
#define BRPHY4_BR_CL22_IEEE_LDS_ABILITY 0x0a0fffcc /* LDS_Ability_Register (Next Page) */
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP 0x0a0fffce /* LDS_Link_Partner_Ability_Base_Page_Register (Base Page) */
#define BRPHY4_BR_CL22_IEEE_LDS_LP_MSG_NXTP 0x0a0fffd0 /* LDS_Link_Partners_Nxt_Pg_Msg_Register (Next Page) */
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP 0x0a0fffd2 /* LDS_Link_Partner_Ability_Nxt_Pg_Register (Next Page) */
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP 0x0a0fffd4 /* LDS_Expansion_Register */
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT 0x0a0fffd6 /* IEEE_Extended_Status_Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_CL22_B0
 ***************************************************************************/
#define SGMII0_CL22_B0_MIICNTL         0x0a400000 /* IEEE MII control register */
#define SGMII0_CL22_B0_MIISTAT         0x0a400002 /* IEEE MII status register */
#define SGMII0_CL22_B0_ID1             0x0a400004 /* IEEE phy ID LSByte register */
#define SGMII0_CL22_B0_ID2             0x0a400006 /* IEEE phy ID MSByte register */
#define SGMII0_CL22_B0_AUTONEGADV      0x0a400008 /* IEEE auto-negotiation advertised abilities register */
#define SGMII0_CL22_B0_AUTONEGLPABIL   0x0a40000a /* IEEE auto-negotiation link partner abilities register */
#define SGMII0_CL22_B0_AUTONEGEXP      0x0a40000c /* IEEE auto-negotiation expansion register */
#define SGMII0_CL22_B0_AUTONEGNP       0x0a40000e /* IEEE auto-negotiation next page register */
#define SGMII0_CL22_B0_AUTONEGLPABIL2  0x0a400010 /* IEEE auto-negotiation link partner next page register */
#define SGMII0_CL22_B0_MIIEXTSTAT      0x0a40001e /* IEEE MII extended status register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk0
 ***************************************************************************/
#define SGMII_BLK0_XGXSCONTROL         0x0a410000 /* XGXS control register */
#define SGMII_BLK0_MMDSELECT           0x0a41001a /* MMD select register */
#define SGMII_BLK0_MISCCONTROL1        0x0a41001c /* Miscellaneous control 1 register */
#define SGMII_BLK0_BLOCKADDRESS        0x0a41001e /* Block Address register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk1
 ***************************************************************************/
#define SGMII_BLK1_LANECTRL0           0x0a41002a /* Lane control 0 register */
#define SGMII_BLK1_LANECTRL1           0x0a41002c /* Lane control 1 register */
#define SGMII_BLK1_LANECTRL2           0x0a41002e /* Lane control 2 register */
#define SGMII_BLK1_LANECTRL3           0x0a410030 /* Lane control 3 register */
#define SGMII_BLK1_LANEPRBS            0x0a410032 /* Lane PRBS control register */
#define SGMII_BLK1_LANETEST            0x0a410034 /* Lane test control register */
#define SGMII_BLK1_BLOCKADDRESS        0x0a41003e /* Block Address register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_PLL_afe
 ***************************************************************************/
#define SGMII_PLL_AFE_CTRL0            0x0a4100a0 /* Analog PLL Control0 Register */
#define SGMII_PLL_AFE_CTRL1            0x0a4100a2 /* Analog PLL Control1 Register */
#define SGMII_PLL_AFE_CTRL2            0x0a4100a4 /* Analog PLL Control2 Register */
#define SGMII_PLL_AFE_CTRL3            0x0a4100a6 /* Analog PLL Control3 Register */
#define SGMII_PLL_AFE_CTRL4            0x0a4100a8 /* Analog PLL Control4 Register */
#define SGMII_PLL_AFE_CTRL5            0x0a4100aa /* Analog PLL Control5 Register */
#define SGMII_PLL_AFE_CTRL6            0x0a4100ac /* Analog PLL Control6 Register */
#define SGMII_PLL_AFE_CTRL7            0x0a4100ae /* Analog PLL Control7 Register */
#define SGMII_PLL_AFE_CTRL8            0x0a4100b0 /* Analog PLL Control8 Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_TX_afe
 ***************************************************************************/
#define SGMII0_TX_AFE_ANATXASTATUS0    0x0a4100c0 /* Tx analog status 0 register */
#define SGMII0_TX_AFE_ANATXACONTROL0   0x0a4100c2 /* Tx analog control 0 register */
#define SGMII0_TX_AFE_ANATXMDATA0      0x0a4100c4 /* Tx test mux data 0 register */
#define SGMII0_TX_AFE_ANATXMDATA1      0x0a4100c6 /* Tx test mux data 1 register */
#define SGMII0_TX_AFE_CONTROL0         0x0a4100ca /* Analog TX Control 0 Register */
#define SGMII0_TX_AFE_CONTROL1         0x0a4100cc /* Analog TX Control 1 Register */
#define SGMII0_TX_AFE_CONTROL2         0x0a4100ce /* Analog TX Control 2 Register */
#define SGMII0_TX_AFE_CONTROL3         0x0a4100d0 /* Analog TX Control 3 Register */
#define SGMII0_TX_AFE_INTERP           0x0a4100d2 /* txinterp Control Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_RX_afe
 ***************************************************************************/
#define SGMII0_RX_AFE_ANARXSTATUS      0x0a410160 /* Rx lane status register */
#define SGMII0_RX_AFE_ANARXCONTROL     0x0a410162 /* Rx lane control register */
#define SGMII0_RX_AFE_CTRL0            0x0a410164 /* AFE Control Register 15:0 */
#define SGMII0_RX_AFE_CTRL1            0x0a410166 /* AFE Control Register 31:16 */
#define SGMII0_RX_AFE_ANARXSIGDET      0x0a410168 /* Rx Sigdet Control */
#define SGMII0_RX_AFE_CTRL2            0x0a41016a /* AFE Control Register 47:32 */
#define SGMII0_RX_AFE_CTRL3            0x0a41016c /* AFE Control Register 63:48 */
#define SGMII0_RX_AFE_CTRL4            0x0a41016e /* AFE Control Register 79:64 */
#define SGMII0_RX_AFE_ANARXTEST        0x0a410170 /* Rx lane control register */
#define SGMII0_RX_AFE_ANARXCONTROL1G   0x0a410172 /* Rx 1G Control register */
#define SGMII0_RX_AFE_ANARXCONTROLPCI  0x0a410174 /* Rx PCI Control register */
#define SGMII0_RX_AFE_ANARXASTATUS     0x0a410176 /* Rx analog status register */
#define SGMII0_RX_AFE_CTRL5            0x0a410178 /* AFE Control Register 95:80 */
#define SGMII0_RX_AFE_CTRL6            0x0a41017a /* AFE Control Register 111:96 */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk2
 ***************************************************************************/
#define SGMII_BLK2_TESTMODELANE        0x0a41020c /* Test mode lane select register */
#define SGMII_BLK2_TESTMODECOMBO       0x0a41020e /* Test mode monitor control register */
#define SGMII_BLK2_TESTMODEMUX         0x0a410210 /* Test mode mux control register */
#define SGMII_BLK2_CX4SIGDETCNT        0x0a410212 /* 10GBASE-CX4 signal detect timeout value */
#define SGMII_BLK2_LANERESET           0x0a410214 /* Lane reset register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk4
 ***************************************************************************/
#define SGMII_BLK4_XGXSSTATUS1         0x0a410244 /* status 1 register */
#define SGMII_BLK4_XGXSSTATUS2         0x0a410246 /* status 2 register */
#define SGMII_BLK4_STATUS1000X1        0x0a410248 /* 1000X status 1 register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk7
 ***************************************************************************/
#define SGMII_BLK7_PRBS_DECOUPLE       0x0a4102b4 /* prbs monitor decouple control */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_PLL2
 ***************************************************************************/
#define SGMII_PLL2_STAT0               0x0a410300 /* Analog PLL Status0 Register */
#define SGMII_PLL2_CTRL1               0x0a410302 /* Analog PLL Control1 Register */
#define SGMII_PLL2_CTRL2               0x0a410304 /* Analog PLL Control2 Register */
#define SGMII_PLL2_CTRL3               0x0a410306 /* Analog PLL Control3 Register */
#define SGMII_PLL2_CTRL4               0x0a410308 /* Analog PLL Control4 Register */
#define SGMII_PLL2_CTRL5               0x0a41030a /* Analog PLL Control5 Register */
#define SGMII_PLL2_CTRL6               0x0a41030c /* Analog PLL Control6 Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_Digital
 ***************************************************************************/
#define SGMII0_DIGITAL_CONTROL1000X1   0x0a410600 /* 1000X control 1 register */
#define SGMII0_DIGITAL_CONTROL1000X2   0x0a410602 /* 1000X control 2 register */
#define SGMII0_DIGITAL_CONTROL1000X3   0x0a410604 /* 1000X control 3 register */
#define SGMII0_DIGITAL_CONTROL1000X4   0x0a410606 /* 1000X control 4 register */
#define SGMII0_DIGITAL_STATUS1000X1    0x0a410608 /* 1000X status 1 register */
#define SGMII0_DIGITAL_STATUS1000X2    0x0a41060a /* 1000X status 2 register */
#define SGMII0_DIGITAL_STATUS1000X3    0x0a41060c /* 1000X status 3 register */
#define SGMII0_DIGITAL_BADCODEGROUP    0x0a41060e /* Invalid code group count register */
#define SGMII0_DIGITAL_MISC1           0x0a410610 /* Miscellaneous 1 control register */
#define SGMII0_DIGITAL_MISC2           0x0a410612 /* Miscellaneous 2 control register */
#define SGMII0_DIGITAL_PATGENCTRL      0x0a410614 /* Pattern generator control register */
#define SGMII0_DIGITAL_PATGENSTAT      0x0a410616 /* Pattern generator status register */
#define SGMII0_DIGITAL_TESTMODE        0x0a410618 /* Test mode register */
#define SGMII0_DIGITAL_TXPKTCNT        0x0a41061a /* Tx packet count register */
#define SGMII0_DIGITAL_RXPKTCNT        0x0a41061c /* Rx packet count register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_serdesID
 ***************************************************************************/
#define SGMII0_SERDESID_SERDESID0      0x0a410620 /* Serdes ID 0 register */
#define SGMII0_SERDESID_SERDESID1      0x0a410622 /* Serdes ID 1 register */
#define SGMII0_SERDESID_SERDESID2      0x0a410624 /* Serdes ID 2 register */
#define SGMII0_SERDESID_SERDESID3      0x0a410626 /* Serdes ID 3 register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_Digital3
 ***************************************************************************/
#define SGMII0_DIGITAL3_TPOUT_1        0x0a41064e /* Test port out bits 15:0, tpout[15:0] */
#define SGMII0_DIGITAL3_TPOUT_2        0x0a410650 /* Test port out bits 23:8, tpout[23:8] */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_Digital4
 ***************************************************************************/
#define SGMII0_DIGITAL4_MISC3          0x0a410678 /* Miscellaneous 3 control register */
#define SGMII0_DIGITAL4_MISC5          0x0a41067c /* Miscelaneous 5 control register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_FX100
 ***************************************************************************/
#define SGMII0_FX100_CONTROL1          0x0a410800 /* 100FX control register 1 */
#define SGMII0_FX100_CONTROL2          0x0a410802 /* 100FX control register 2 */
#define SGMII0_FX100_CONTROL3          0x0a410804 /* 100FX control register 3 */
#define SGMII0_FX100_STATUS1           0x0a410806 /* 100FX status register 1 */
#define SGMII0_FX100_STATUS3           0x0a41080a /* 100FX status register 3 */
#define SGMII0_FX100_STATUS4           0x0a41080c /* 100FX status register 4 */
#define SGMII0_FX100_FX100IDLE1        0x0a41080e /* 100FX idle pattern register 1 */
#define SGMII0_FX100_FX100IDLE2        0x0a410810 /* 100FX idle pattern register 2 */
#define SGMII0_FX100_FX100IDLESTATUS   0x0a410812 /* 100FX idle status register */
#define SGMII0_FX100_FX100IDLETHRES    0x0a410814 /* 100FX idle threshold register */
#define SGMII0_FX100_FX100LOCKTMR      0x0a410816 /* 100FX lock timer register */
#define SGMII0_FX100_FX100LINKTMR      0x0a410818 /* 100FX link timer register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_RX2
 ***************************************************************************/
#define SGMII0_RX2_RXSEQ0              0x0a4108e0 /* rxseq0 Register */
#define SGMII0_RX2_RXSEQ1              0x0a4108e2 /* rxseq1 Register */
#define SGMII0_RX2_RXCDR0              0x0a4108e4 /* rxcdr0 Register */
#define SGMII0_RX2_RXCDR1              0x0a4108e6 /* rxcdr1 Register */
#define SGMII0_RX2_RXCDR2              0x0a4108e8 /* rxcdr2 Register */
#define SGMII0_RX2_RXCDR3              0x0a4108ea /* rxcdr3 Register */
#define SGMII0_RX2_RXCDR4              0x0a4108ec /* rxcdr4 Register */
#define SGMII0_RX2_STATUS0             0x0a4108ee /* rxstatus 0 Register */
#define SGMII0_RX2_STATUS1             0x0a4108f0 /* rxstatus 1 Register */
#define SGMII0_RX2_STATUS2             0x0a4108f2 /* rxstatus 2 Register */
#define SGMII0_RX2_STATUS3             0x0a4108f4 /* rxstatus 3 Register */
#define SGMII0_RX2_STATUS4             0x0a4108f6 /* rxstatus 4 Register */
#define SGMII0_RX2_STATUS5             0x0a4108f8 /* rxstatus 5 Register */
#define SGMII0_RX2_STATUS6             0x0a4108fa /* rxstatus 6 Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_RX3
 ***************************************************************************/
#define SGMII0_RX3_CONTROL0            0x0a410900 /* rx slice 0 Register */
#define SGMII0_RX3_CONTROL1            0x0a410902 /* rx slice 1 Register */
#define SGMII0_RX3_CONTROL2            0x0a410904 /* rx slice 2 Register */
#define SGMII0_RX3_CONTROL3            0x0a410906 /* rx slice 3 Register */
#define SGMII0_RX3_CONTROL4            0x0a410908 /* rx slice 4 Register */
#define SGMII0_RX3_CONTROL5            0x0a41090a /* rx slice 5 Register */
#define SGMII0_RX3_CONTROL6            0x0a41090c /* rx slice 6 Register */
#define SGMII0_RX3_CONTROL7            0x0a41090e /* rx slice 7 Register */
#define SGMII0_RX3_CONTROL8            0x0a410910 /* rx slice 8 Register */
#define SGMII0_RX3_CONTROL9            0x0a410912 /* rx slice 9 Register */
#define SGMII0_RX3_CONTROL10           0x0a410914 /* rx slice 10 Register */
#define SGMII0_RX3_CONTROL11           0x0a410916 /* rx slice 11 Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_aerBlk
 ***************************************************************************/
#define SGMII_AERBLK_AER               0x0a41ffbc /* Address Expansion Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_Combo_IEEE0
 ***************************************************************************/
#define SGMII0_COMBO_IEEE0_MIICNTL     0x0a41ffc0 /* IEEE MII control register */
#define SGMII0_COMBO_IEEE0_MIISTAT     0x0a41ffc2 /* IEEE MII status register */
#define SGMII0_COMBO_IEEE0_ID1         0x0a41ffc4 /* IEEE phy ID LSByte register */
#define SGMII0_COMBO_IEEE0_ID2         0x0a41ffc6 /* IEEE phy ID MSByte register */
#define SGMII0_COMBO_IEEE0_AUTONEGADV  0x0a41ffc8 /* IEEE auto-negotiation advertised abilities register */
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL 0x0a41ffca /* IEEE auto-negotiation link partner abilities register */
#define SGMII0_COMBO_IEEE0_AUTONEGEXP  0x0a41ffcc /* IEEE auto-negotiation expansion register */
#define SGMII0_COMBO_IEEE0_AUTONEGNP   0x0a41ffce /* IEEE auto-negotiation next page register */
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2 0x0a41ffd0 /* IEEE auto-negotiation link partner next page register */
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT  0x0a41ffde /* IEEE MII extended status register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_CL22_B0
 ***************************************************************************/
#define SGMII1_CL22_B0_MIICNTL         0x0a420000 /* IEEE MII control register */
#define SGMII1_CL22_B0_MIISTAT         0x0a420002 /* IEEE MII status register */
#define SGMII1_CL22_B0_ID1             0x0a420004 /* IEEE phy ID LSByte register */
#define SGMII1_CL22_B0_ID2             0x0a420006 /* IEEE phy ID MSByte register */
#define SGMII1_CL22_B0_AUTONEGADV      0x0a420008 /* IEEE auto-negotiation advertised abilities register */
#define SGMII1_CL22_B0_AUTONEGLPABIL   0x0a42000a /* IEEE auto-negotiation link partner abilities register */
#define SGMII1_CL22_B0_AUTONEGEXP      0x0a42000c /* IEEE auto-negotiation expansion register */
#define SGMII1_CL22_B0_AUTONEGNP       0x0a42000e /* IEEE auto-negotiation next page register */
#define SGMII1_CL22_B0_AUTONEGLPABIL2  0x0a420010 /* IEEE auto-negotiation link partner next page register */
#define SGMII1_CL22_B0_MIIEXTSTAT      0x0a42001e /* IEEE MII extended status register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_TX_afe
 ***************************************************************************/
#define SGMII1_TX_AFE_ANATXASTATUS0    0x0a4300c0 /* Tx analog status 0 register */
#define SGMII1_TX_AFE_ANATXACONTROL0   0x0a4300c2 /* Tx analog control 0 register */
#define SGMII1_TX_AFE_ANATXMDATA0      0x0a4300c4 /* Tx test mux data 0 register */
#define SGMII1_TX_AFE_ANATXMDATA1      0x0a4300c6 /* Tx test mux data 1 register */
#define SGMII1_TX_AFE_CONTROL0         0x0a4300ca /* Analog TX Control 0 Register */
#define SGMII1_TX_AFE_CONTROL1         0x0a4300cc /* Analog TX Control 1 Register */
#define SGMII1_TX_AFE_CONTROL2         0x0a4300ce /* Analog TX Control 2 Register */
#define SGMII1_TX_AFE_CONTROL3         0x0a4300d0 /* Analog TX Control 3 Register */
#define SGMII1_TX_AFE_INTERP           0x0a4300d2 /* txinterp Control Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_RX_afe
 ***************************************************************************/
#define SGMII1_RX_AFE_ANARXSTATUS      0x0a430160 /* Rx lane status register */
#define SGMII1_RX_AFE_ANARXCONTROL     0x0a430162 /* Rx lane control register */
#define SGMII1_RX_AFE_CTRL0            0x0a430164 /* AFE Control Register 15:0 */
#define SGMII1_RX_AFE_CTRL1            0x0a430166 /* AFE Control Register 31:16 */
#define SGMII1_RX_AFE_ANARXSIGDET      0x0a430168 /* Rx Sigdet Control */
#define SGMII1_RX_AFE_CTRL2            0x0a43016a /* AFE Control Register 47:32 */
#define SGMII1_RX_AFE_CTRL3            0x0a43016c /* AFE Control Register 63:48 */
#define SGMII1_RX_AFE_CTRL4            0x0a43016e /* AFE Control Register 79:64 */
#define SGMII1_RX_AFE_ANARXTEST        0x0a430170 /* Rx lane control register */
#define SGMII1_RX_AFE_ANARXCONTROL1G   0x0a430172 /* Rx 1G Control register */
#define SGMII1_RX_AFE_ANARXCONTROLPCI  0x0a430174 /* Rx PCI Control register */
#define SGMII1_RX_AFE_ANARXASTATUS     0x0a430176 /* Rx analog status register */
#define SGMII1_RX_AFE_CTRL5            0x0a430178 /* AFE Control Register 95:80 */
#define SGMII1_RX_AFE_CTRL6            0x0a43017a /* AFE Control Register 111:96 */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_Digital
 ***************************************************************************/
#define SGMII1_DIGITAL_CONTROL1000X1   0x0a430600 /* 1000X control 1 register */
#define SGMII1_DIGITAL_CONTROL1000X2   0x0a430602 /* 1000X control 2 register */
#define SGMII1_DIGITAL_CONTROL1000X3   0x0a430604 /* 1000X control 3 register */
#define SGMII1_DIGITAL_CONTROL1000X4   0x0a430606 /* 1000X control 4 register */
#define SGMII1_DIGITAL_STATUS1000X1    0x0a430608 /* 1000X status 1 register */
#define SGMII1_DIGITAL_STATUS1000X2    0x0a43060a /* 1000X status 2 register */
#define SGMII1_DIGITAL_STATUS1000X3    0x0a43060c /* 1000X status 3 register */
#define SGMII1_DIGITAL_BADCODEGROUP    0x0a43060e /* Invalid code group count register */
#define SGMII1_DIGITAL_MISC1           0x0a430610 /* Miscellaneous 1 control register */
#define SGMII1_DIGITAL_MISC2           0x0a430612 /* Miscellaneous 2 control register */
#define SGMII1_DIGITAL_PATGENCTRL      0x0a430614 /* Pattern generator control register */
#define SGMII1_DIGITAL_PATGENSTAT      0x0a430616 /* Pattern generator status register */
#define SGMII1_DIGITAL_TESTMODE        0x0a430618 /* Test mode register */
#define SGMII1_DIGITAL_TXPKTCNT        0x0a43061a /* Tx packet count register */
#define SGMII1_DIGITAL_RXPKTCNT        0x0a43061c /* Rx packet count register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_serdesID
 ***************************************************************************/
#define SGMII1_SERDESID_SERDESID0      0x0a430620 /* Serdes ID 0 register */
#define SGMII1_SERDESID_SERDESID1      0x0a430622 /* Serdes ID 1 register */
#define SGMII1_SERDESID_SERDESID2      0x0a430624 /* Serdes ID 2 register */
#define SGMII1_SERDESID_SERDESID3      0x0a430626 /* Serdes ID 3 register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_Digital3
 ***************************************************************************/
#define SGMII1_DIGITAL3_TPOUT_1        0x0a43064e /* Test port out bits 15:0, tpout[15:0] */
#define SGMII1_DIGITAL3_TPOUT_2        0x0a430650 /* Test port out bits 23:8, tpout[23:8] */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_Digital4
 ***************************************************************************/
#define SGMII1_DIGITAL4_MISC3          0x0a430678 /* Miscellaneous 3 control register */
#define SGMII1_DIGITAL4_MISC5          0x0a43067c /* Miscelaneous 5 control register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_FX100
 ***************************************************************************/
#define SGMII1_FX100_CONTROL1          0x0a430800 /* 100FX control register 1 */
#define SGMII1_FX100_CONTROL2          0x0a430802 /* 100FX control register 2 */
#define SGMII1_FX100_CONTROL3          0x0a430804 /* 100FX control register 3 */
#define SGMII1_FX100_STATUS1           0x0a430806 /* 100FX status register 1 */
#define SGMII1_FX100_STATUS3           0x0a43080a /* 100FX status register 3 */
#define SGMII1_FX100_STATUS4           0x0a43080c /* 100FX status register 4 */
#define SGMII1_FX100_FX100IDLE1        0x0a43080e /* 100FX idle pattern register 1 */
#define SGMII1_FX100_FX100IDLE2        0x0a430810 /* 100FX idle pattern register 2 */
#define SGMII1_FX100_FX100IDLESTATUS   0x0a430812 /* 100FX idle status register */
#define SGMII1_FX100_FX100IDLETHRES    0x0a430814 /* 100FX idle threshold register */
#define SGMII1_FX100_FX100LOCKTMR      0x0a430816 /* 100FX lock timer register */
#define SGMII1_FX100_FX100LINKTMR      0x0a430818 /* 100FX link timer register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_RX2
 ***************************************************************************/
#define SGMII1_RX2_RXSEQ0              0x0a4308e0 /* rxseq0 Register */
#define SGMII1_RX2_RXSEQ1              0x0a4308e2 /* rxseq1 Register */
#define SGMII1_RX2_RXCDR0              0x0a4308e4 /* rxcdr0 Register */
#define SGMII1_RX2_RXCDR1              0x0a4308e6 /* rxcdr1 Register */
#define SGMII1_RX2_RXCDR2              0x0a4308e8 /* rxcdr2 Register */
#define SGMII1_RX2_RXCDR3              0x0a4308ea /* rxcdr3 Register */
#define SGMII1_RX2_RXCDR4              0x0a4308ec /* rxcdr4 Register */
#define SGMII1_RX2_STATUS0             0x0a4308ee /* rxstatus 0 Register */
#define SGMII1_RX2_STATUS1             0x0a4308f0 /* rxstatus 1 Register */
#define SGMII1_RX2_STATUS2             0x0a4308f2 /* rxstatus 2 Register */
#define SGMII1_RX2_STATUS3             0x0a4308f4 /* rxstatus 3 Register */
#define SGMII1_RX2_STATUS4             0x0a4308f6 /* rxstatus 4 Register */
#define SGMII1_RX2_STATUS5             0x0a4308f8 /* rxstatus 5 Register */
#define SGMII1_RX2_STATUS6             0x0a4308fa /* rxstatus 6 Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_RX3
 ***************************************************************************/
#define SGMII1_RX3_CONTROL0            0x0a430900 /* rx slice 0 Register */
#define SGMII1_RX3_CONTROL1            0x0a430902 /* rx slice 1 Register */
#define SGMII1_RX3_CONTROL2            0x0a430904 /* rx slice 2 Register */
#define SGMII1_RX3_CONTROL3            0x0a430906 /* rx slice 3 Register */
#define SGMII1_RX3_CONTROL4            0x0a430908 /* rx slice 4 Register */
#define SGMII1_RX3_CONTROL5            0x0a43090a /* rx slice 5 Register */
#define SGMII1_RX3_CONTROL6            0x0a43090c /* rx slice 6 Register */
#define SGMII1_RX3_CONTROL7            0x0a43090e /* rx slice 7 Register */
#define SGMII1_RX3_CONTROL8            0x0a430910 /* rx slice 8 Register */
#define SGMII1_RX3_CONTROL9            0x0a430912 /* rx slice 9 Register */
#define SGMII1_RX3_CONTROL10           0x0a430914 /* rx slice 10 Register */
#define SGMII1_RX3_CONTROL11           0x0a430916 /* rx slice 11 Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_Combo_IEEE0
 ***************************************************************************/
#define SGMII1_COMBO_IEEE0_MIICNTL     0x0a43ffc0 /* IEEE MII control register */
#define SGMII1_COMBO_IEEE0_MIISTAT     0x0a43ffc2 /* IEEE MII status register */
#define SGMII1_COMBO_IEEE0_ID1         0x0a43ffc4 /* IEEE phy ID LSByte register */
#define SGMII1_COMBO_IEEE0_ID2         0x0a43ffc6 /* IEEE phy ID MSByte register */
#define SGMII1_COMBO_IEEE0_AUTONEGADV  0x0a43ffc8 /* IEEE auto-negotiation advertised abilities register */
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL 0x0a43ffca /* IEEE auto-negotiation link partner abilities register */
#define SGMII1_COMBO_IEEE0_AUTONEGEXP  0x0a43ffcc /* IEEE auto-negotiation expansion register */
#define SGMII1_COMBO_IEEE0_AUTONEGNP   0x0a43ffce /* IEEE auto-negotiation next page register */
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2 0x0a43ffd0 /* IEEE auto-negotiation link partner next page register */
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT  0x0a43ffde /* IEEE MII extended status register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_CL22_B0
 ***************************************************************************/
#define SGMII2_CL22_B0_MIICNTL         0x0a440000 /* IEEE MII control register */
#define SGMII2_CL22_B0_MIISTAT         0x0a440002 /* IEEE MII status register */
#define SGMII2_CL22_B0_ID1             0x0a440004 /* IEEE phy ID LSByte register */
#define SGMII2_CL22_B0_ID2             0x0a440006 /* IEEE phy ID MSByte register */
#define SGMII2_CL22_B0_AUTONEGADV      0x0a440008 /* IEEE auto-negotiation advertised abilities register */
#define SGMII2_CL22_B0_AUTONEGLPABIL   0x0a44000a /* IEEE auto-negotiation link partner abilities register */
#define SGMII2_CL22_B0_AUTONEGEXP      0x0a44000c /* IEEE auto-negotiation expansion register */
#define SGMII2_CL22_B0_AUTONEGNP       0x0a44000e /* IEEE auto-negotiation next page register */
#define SGMII2_CL22_B0_AUTONEGLPABIL2  0x0a440010 /* IEEE auto-negotiation link partner next page register */
#define SGMII2_CL22_B0_MIIEXTSTAT      0x0a44001e /* IEEE MII extended status register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_TX_afe
 ***************************************************************************/
#define SGMII2_TX_AFE_ANATXASTATUS0    0x0a4500c0 /* Tx analog status 0 register */
#define SGMII2_TX_AFE_ANATXACONTROL0   0x0a4500c2 /* Tx analog control 0 register */
#define SGMII2_TX_AFE_ANATXMDATA0      0x0a4500c4 /* Tx test mux data 0 register */
#define SGMII2_TX_AFE_ANATXMDATA1      0x0a4500c6 /* Tx test mux data 1 register */
#define SGMII2_TX_AFE_CONTROL0         0x0a4500ca /* Analog TX Control 0 Register */
#define SGMII2_TX_AFE_CONTROL1         0x0a4500cc /* Analog TX Control 1 Register */
#define SGMII2_TX_AFE_CONTROL2         0x0a4500ce /* Analog TX Control 2 Register */
#define SGMII2_TX_AFE_CONTROL3         0x0a4500d0 /* Analog TX Control 3 Register */
#define SGMII2_TX_AFE_INTERP           0x0a4500d2 /* txinterp Control Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_RX_afe
 ***************************************************************************/
#define SGMII2_RX_AFE_ANARXSTATUS      0x0a450160 /* Rx lane status register */
#define SGMII2_RX_AFE_ANARXCONTROL     0x0a450162 /* Rx lane control register */
#define SGMII2_RX_AFE_CTRL0            0x0a450164 /* AFE Control Register 15:0 */
#define SGMII2_RX_AFE_CTRL1            0x0a450166 /* AFE Control Register 31:16 */
#define SGMII2_RX_AFE_ANARXSIGDET      0x0a450168 /* Rx Sigdet Control */
#define SGMII2_RX_AFE_CTRL2            0x0a45016a /* AFE Control Register 47:32 */
#define SGMII2_RX_AFE_CTRL3            0x0a45016c /* AFE Control Register 63:48 */
#define SGMII2_RX_AFE_CTRL4            0x0a45016e /* AFE Control Register 79:64 */
#define SGMII2_RX_AFE_ANARXTEST        0x0a450170 /* Rx lane control register */
#define SGMII2_RX_AFE_ANARXCONTROL1G   0x0a450172 /* Rx 1G Control register */
#define SGMII2_RX_AFE_ANARXCONTROLPCI  0x0a450174 /* Rx PCI Control register */
#define SGMII2_RX_AFE_ANARXASTATUS     0x0a450176 /* Rx analog status register */
#define SGMII2_RX_AFE_CTRL5            0x0a450178 /* AFE Control Register 95:80 */
#define SGMII2_RX_AFE_CTRL6            0x0a45017a /* AFE Control Register 111:96 */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_Digital
 ***************************************************************************/
#define SGMII2_DIGITAL_CONTROL1000X1   0x0a450600 /* 1000X control 1 register */
#define SGMII2_DIGITAL_CONTROL1000X2   0x0a450602 /* 1000X control 2 register */
#define SGMII2_DIGITAL_CONTROL1000X3   0x0a450604 /* 1000X control 3 register */
#define SGMII2_DIGITAL_CONTROL1000X4   0x0a450606 /* 1000X control 4 register */
#define SGMII2_DIGITAL_STATUS1000X1    0x0a450608 /* 1000X status 1 register */
#define SGMII2_DIGITAL_STATUS1000X2    0x0a45060a /* 1000X status 2 register */
#define SGMII2_DIGITAL_STATUS1000X3    0x0a45060c /* 1000X status 3 register */
#define SGMII2_DIGITAL_BADCODEGROUP    0x0a45060e /* Invalid code group count register */
#define SGMII2_DIGITAL_MISC1           0x0a450610 /* Miscellaneous 1 control register */
#define SGMII2_DIGITAL_MISC2           0x0a450612 /* Miscellaneous 2 control register */
#define SGMII2_DIGITAL_PATGENCTRL      0x0a450614 /* Pattern generator control register */
#define SGMII2_DIGITAL_PATGENSTAT      0x0a450616 /* Pattern generator status register */
#define SGMII2_DIGITAL_TESTMODE        0x0a450618 /* Test mode register */
#define SGMII2_DIGITAL_TXPKTCNT        0x0a45061a /* Tx packet count register */
#define SGMII2_DIGITAL_RXPKTCNT        0x0a45061c /* Rx packet count register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_serdesID
 ***************************************************************************/
#define SGMII2_SERDESID_SERDESID0      0x0a450620 /* Serdes ID 0 register */
#define SGMII2_SERDESID_SERDESID1      0x0a450622 /* Serdes ID 1 register */
#define SGMII2_SERDESID_SERDESID2      0x0a450624 /* Serdes ID 2 register */
#define SGMII2_SERDESID_SERDESID3      0x0a450626 /* Serdes ID 3 register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_Digital3
 ***************************************************************************/
#define SGMII2_DIGITAL3_TPOUT_1        0x0a45064e /* Test port out bits 15:0, tpout[15:0] */
#define SGMII2_DIGITAL3_TPOUT_2        0x0a450650 /* Test port out bits 23:8, tpout[23:8] */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_Digital4
 ***************************************************************************/
#define SGMII2_DIGITAL4_MISC3          0x0a450678 /* Miscellaneous 3 control register */
#define SGMII2_DIGITAL4_MISC5          0x0a45067c /* Miscelaneous 5 control register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_FX100
 ***************************************************************************/
#define SGMII2_FX100_CONTROL1          0x0a450800 /* 100FX control register 1 */
#define SGMII2_FX100_CONTROL2          0x0a450802 /* 100FX control register 2 */
#define SGMII2_FX100_CONTROL3          0x0a450804 /* 100FX control register 3 */
#define SGMII2_FX100_STATUS1           0x0a450806 /* 100FX status register 1 */
#define SGMII2_FX100_STATUS3           0x0a45080a /* 100FX status register 3 */
#define SGMII2_FX100_STATUS4           0x0a45080c /* 100FX status register 4 */
#define SGMII2_FX100_FX100IDLE1        0x0a45080e /* 100FX idle pattern register 1 */
#define SGMII2_FX100_FX100IDLE2        0x0a450810 /* 100FX idle pattern register 2 */
#define SGMII2_FX100_FX100IDLESTATUS   0x0a450812 /* 100FX idle status register */
#define SGMII2_FX100_FX100IDLETHRES    0x0a450814 /* 100FX idle threshold register */
#define SGMII2_FX100_FX100LOCKTMR      0x0a450816 /* 100FX lock timer register */
#define SGMII2_FX100_FX100LINKTMR      0x0a450818 /* 100FX link timer register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_RX2
 ***************************************************************************/
#define SGMII2_RX2_RXSEQ0              0x0a4508e0 /* rxseq0 Register */
#define SGMII2_RX2_RXSEQ1              0x0a4508e2 /* rxseq1 Register */
#define SGMII2_RX2_RXCDR0              0x0a4508e4 /* rxcdr0 Register */
#define SGMII2_RX2_RXCDR1              0x0a4508e6 /* rxcdr1 Register */
#define SGMII2_RX2_RXCDR2              0x0a4508e8 /* rxcdr2 Register */
#define SGMII2_RX2_RXCDR3              0x0a4508ea /* rxcdr3 Register */
#define SGMII2_RX2_RXCDR4              0x0a4508ec /* rxcdr4 Register */
#define SGMII2_RX2_STATUS0             0x0a4508ee /* rxstatus 0 Register */
#define SGMII2_RX2_STATUS1             0x0a4508f0 /* rxstatus 1 Register */
#define SGMII2_RX2_STATUS2             0x0a4508f2 /* rxstatus 2 Register */
#define SGMII2_RX2_STATUS3             0x0a4508f4 /* rxstatus 3 Register */
#define SGMII2_RX2_STATUS4             0x0a4508f6 /* rxstatus 4 Register */
#define SGMII2_RX2_STATUS5             0x0a4508f8 /* rxstatus 5 Register */
#define SGMII2_RX2_STATUS6             0x0a4508fa /* rxstatus 6 Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_RX3
 ***************************************************************************/
#define SGMII2_RX3_CONTROL0            0x0a450900 /* rx slice 0 Register */
#define SGMII2_RX3_CONTROL1            0x0a450902 /* rx slice 1 Register */
#define SGMII2_RX3_CONTROL2            0x0a450904 /* rx slice 2 Register */
#define SGMII2_RX3_CONTROL3            0x0a450906 /* rx slice 3 Register */
#define SGMII2_RX3_CONTROL4            0x0a450908 /* rx slice 4 Register */
#define SGMII2_RX3_CONTROL5            0x0a45090a /* rx slice 5 Register */
#define SGMII2_RX3_CONTROL6            0x0a45090c /* rx slice 6 Register */
#define SGMII2_RX3_CONTROL7            0x0a45090e /* rx slice 7 Register */
#define SGMII2_RX3_CONTROL8            0x0a450910 /* rx slice 8 Register */
#define SGMII2_RX3_CONTROL9            0x0a450912 /* rx slice 9 Register */
#define SGMII2_RX3_CONTROL10           0x0a450914 /* rx slice 10 Register */
#define SGMII2_RX3_CONTROL11           0x0a450916 /* rx slice 11 Register */


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_Combo_IEEE0
 ***************************************************************************/
#define SGMII2_COMBO_IEEE0_MIICNTL     0x0a45ffc0 /* IEEE MII control register */
#define SGMII2_COMBO_IEEE0_MIISTAT     0x0a45ffc2 /* IEEE MII status register */
#define SGMII2_COMBO_IEEE0_ID1         0x0a45ffc4 /* IEEE phy ID LSByte register */
#define SGMII2_COMBO_IEEE0_ID2         0x0a45ffc6 /* IEEE phy ID MSByte register */
#define SGMII2_COMBO_IEEE0_AUTONEGADV  0x0a45ffc8 /* IEEE auto-negotiation advertised abilities register */
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL 0x0a45ffca /* IEEE auto-negotiation link partner abilities register */
#define SGMII2_COMBO_IEEE0_AUTONEGEXP  0x0a45ffcc /* IEEE auto-negotiation expansion register */
#define SGMII2_COMBO_IEEE0_AUTONEGNP   0x0a45ffce /* IEEE auto-negotiation next page register */
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2 0x0a45ffd0 /* IEEE auto-negotiation link partner next page register */
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT  0x0a45ffde /* IEEE MII extended status register */


/****************************************************************************
 * bcm89530_top_bridge_MISC
 ***************************************************************************/
#define MISC_MODEL_REV_NUM             0x0a800000 /* track the model and revision numbers */
#define MISC_DEVICEID_LO               0x0a800002 /* track device ID [11:0] */
#define MISC_DEVICEID_HI               0x0a800004 /* track device ID [19:12] */
#define MISC_SWITCH_MISC_CTRL          0x0a800006 /* miscallenaous switch config form chip level */
#define MISC_LDO_PWRDN                 0x0a800100 /* LDO Power Down register */
#define MISC_LDO_VREGCNTL_1            0x0a800102 /* LDO Voltage Regulator Control register 1 */
#define MISC_LDO_VREGCNTL_2            0x0a800104 /* LDO Voltage Regulator Control register 2 */
#define MISC_LDO_VREGCNTLEN            0x0a800106 /* LDO Voltage Regulator Control Enable register */
#define MISC_SWREG_CTRL_REG0           0x0a800110 /* Switching regulator control register0 */
#define MISC_SWREG_CTRL_REG1           0x0a800112 /* Switching regulator control register1 */
#define MISC_SWREG_CTRL_REG2           0x0a800114 /* Switching regulator control register2 */
#define MISC_SWREG_CTRL_REG3           0x0a800116 /* Switching regulator control register3 */
#define MISC_SWREG_CTRL_REG4           0x0a800118 /* Switching regulator control register4 */
#define MISC_SWREG_CTRL_REG5           0x0a80011a /* Switching regulator control register5 */
#define MISC_SWREG_CTRL_REG6           0x0a80011c /* Switching regulator control register6 */
#define MISC_SWREG_CTRL_REG7           0x0a80011e /* Switching regulator control register7 */
#define MISC_SWREG_CTRL_REG8           0x0a800120 /* Switching regulator control register8 */
#define MISC_SWREG_CTRL_REG9           0x0a800122 /* Switching regulator control register9 */
#define MISC_SWREG_STAT_REG12          0x0a800124 /* Switching regulator status register0 */
#define MISC_SWREG_STAT_REG13          0x0a800126 /* Switching regulator status register1 */
#define MISC_SWREG_STAT_REG14          0x0a800128 /* Switching regulator status register2 */
#define MISC_SWREG_STAT_REG15          0x0a80012a /* Switching regulator status register3 */
#define MISC_SWREG_ACCESS_CTRL_1       0x0a80012c /* Switching regulator access control register1 */
#define MISC_SWREG_ACCESS_CTRL_2       0x0a80012e /* Switching regulator access control register2 */
#define MISC_SWREG_CONTROL_STATUS      0x0a800130 /* Switching regulator miscellaneous control and status */
#define MISC_SGMII_PWRDWN              0x0a800140 /* SGMII PowerDown */
#define MISC_SGMII_HW_RST_DLY_VAL      0x0a800142 /* SGMII Hardware Reset Delay Value */
#define MISC_SGMII_MDIO_RST_DLY_VAL    0x0a800144 /* SGMII MDIO Reset Delay Value */
#define MISC_SGMII_PLL_RST_DLY_VAL     0x0a800146 /* SGMII PLL Reset Delay Value */
#define MISC_SGMII_EXT_CTL             0x0a800148 /* SGMII External Control */
#define MISC_SGMII_AN0                 0x0a80014a /* SGMII AutoNeg 0 */
#define MISC_SGMII_BASE_PAGE0          0x0a80014c /* SGMII Base Page 0 */
#define MISC_SGMII_AN1                 0x0a80014e /* SGMII AutoNeg 1 */
#define MISC_SGMII_BASE_PAGE1          0x0a800150 /* SGMII Base Page 1 */
#define MISC_SGMII_AN2                 0x0a800152 /* SGMII AutoNeg 2 */
#define MISC_SGMII_BASE_PAGE2          0x0a800154 /* SGMII Base Page 2 */
#define MISC_SGMII_MDIO_CTL            0x0a800156 /* SGMII MDIO Control */
#define MISC_OTP_CPU_COMMAND           0x0a800170 /* OTP CPU Command Register */
#define MISC_OTP_CPU_WRDATA_H          0x0a800172 /* CPU Write Data Register High */
#define MISC_OTP_CPU_WRDATA_L          0x0a800174 /* OTP CPU Write Data Register Low */
#define MISC_OTP_CONFIG                0x0a800176 /* OTP Configuration Register */
#define MISC_OTP_ADDRESS               0x0a800178 /* OTP Address Register */
#define MISC_OTP_STATUS_1              0x0a80017a /* OTP Status Register 1 */
#define MISC_OTP_STATUS_0              0x0a80017c /* OTP Status Register 0 */
#define MISC_OTP_RDATA_H               0x0a800180 /* OTP Read Data Register High */
#define MISC_OTP_RDATA_L               0x0a800182 /* OTP Read Data Register Low */
#define MISC_BISR_STATUS               0x0a800184 /* BISR Status Register */
#define MISC_PVTMON_CTRL               0x0a800200 /* PVTMON general controls */
#define MISC_PVTMON_SAMPLE_NUM         0x0a800202 /* number of temp & voltage samples to be collected in each measurement cycle in auto mode */
#define MISC_PVTMON_TMON_PERIOD        0x0a800204 /* period of occurence of tmon cycle w.r.t vmon cycles */
#define MISC_PVTMON_I_CTRL_31_16       0x0a800206 /* PVTMON i_ctrl[31:16] - to be used in EXPERT mode only */
#define MISC_PVTMON_I_CTRL_15_0        0x0a800208 /* PVTMON i_ctrl[15:0] - to be used in EXPERT mode only */
#define MISC_PVTMON_ADC_DATA           0x0a80020a /* 10-bit output from the SAR ADC - to be used when auto_mode=0 (OR) to be used in EXPERT mode */
#define MISC_PVTMON_DAC_DATA           0x0a80020c /* DAC input data from user - to be used in EXPERT mode only */
#define MISC_PVTMON_TMON_THRESH1_CTRL  0x0a80020e /* thresh1 controls for tmon */
#define MISC_PVTMON_TMON_THRESH2_CTRL  0x0a800210 /* thresh2 controls for tmon */
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL 0x0a800212 /* thresh1 controls for vmon_1v_h */
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL 0x0a800214 /* thresh2 controls for vmon_1v_h */
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL 0x0a800216 /* thresh1 controls for vmon_1v_l */
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL 0x0a800218 /* thresh2 controls for vmon_1v_l */
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL 0x0a80021a /* thresh1 controls for vmon_1p8v_h */
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL 0x0a80021c /* thresh2 controls for vmon_1p8v_h */
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL 0x0a80021e /* thresh1 controls for vmon_1p8v_l */
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL 0x0a800220 /* thresh2 controls for vmon_1p8v_l */
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL 0x0a800222 /* thresh1 controls for vmon_3p3v_h */
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL 0x0a800224 /* thresh2 controls for vmon_3p3v_h */
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL 0x0a800226 /* thresh1 controls for vmon_3p3v_l */
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL 0x0a800228 /* thresh2 controls for vmon_3p3v_l */
#define MISC_PVTMON_THRESHOLD_FILTER   0x0a80022a /* number of continous threshold breaches that will lead to "violation" */
#define MISC_PVTMON_VIOL_RAWSTS        0x0a80022c /* raw status showing whether we have a brownout violation */
#define MISC_PVTMON_INTR_STATUS        0x0a80022e /* latched status register for all interrupts from pvtmon */
#define MISC_PVTMON_INTSTS_CLEAR       0x0a800230 /* clear the interrupt status */
#define MISC_PVTMON_INTERRUPT_COUNT    0x0a800232 /* number of brownout interrupts until now */
#define MISC_PVTMON_TMON_SAMPLE        0x0a800234 /* last temp sample */
#define MISC_PVTMON_VMON_1V_SAMPLE     0x0a800236 /* last 1V sample */
#define MISC_PVTMON_VMON_1P8V_SAMPLE   0x0a800238 /* last 1.8V sample */
#define MISC_PVTMON_VMON_3P3V_SAMPLE   0x0a80023a /* last 3.3V sample */
#define MISC_F1_IMAGE_STATUS           0x0a800300 /* F1 Image Status */
#define MISC_F1_IMAGE_VERSION          0x0a800302 /* F1 Image Version */
#define MISC_F2_IMAGE_STATUS           0x0a800304 /* F2 Image Status */
#define MISC_F2_IMAGE_VERSION          0x0a800306 /* F2 Image Version */
#define MISC_SPARE_HW_REG4             0x0a800308 /* Spare H/W Register 4 */
#define MISC_SPARE_HW_REG5             0x0a80030a /* Spare H/W Register 5 */
#define MISC_SPARE_HW_REG6             0x0a80030c /* Spare H/W Register 6 */
#define MISC_SPARE_HW_REG7             0x0a80030e /* Spare H/W Register 7 */
#define MISC_SPARE_HW_REG8             0x0a800310 /* Spare H/W Register 8 */
#define MISC_SPARE_HW_REG9             0x0a800312 /* Spare H/W Register 9 */
#define MISC_SPARE_HW_REG10            0x0a800314 /* Spare H/W Register 10 */
#define MISC_SPARE_HW_REG11            0x0a800316 /* Spare H/W Register 11 */
#define MISC_SPARE_HW_REG12            0x0a800318 /* Spare H/W Register 12 */
#define MISC_SPARE_HW_REG13            0x0a80031a /* Spare H/W Register 13 */
#define MISC_SPARE_HW_REG14            0x0a80031c /* Spare H/W Register 14 */
#define MISC_SPARE_HW_REG15            0x0a80031e /* Spare H/W Register 15 */
#define MISC_SPARE_SW_REG0             0x0a800320 /* Spare S/W Register 0 */
#define MISC_SPARE_SW_REG1             0x0a800322 /* Spare S/W Register 1 */
#define MISC_SPARE_SW_REG2             0x0a800324 /* Spare S/W Register 2 */
#define MISC_SPARE_SW_REG3             0x0a800326 /* Spare S/W Register 3 */
#define MISC_SPARE_SW_REG4             0x0a800328 /* Spare S/W Register 4 */
#define MISC_SPARE_SW_REG5             0x0a80032a /* Spare S/W Register 5 */
#define MISC_SPARE_SW_REG6             0x0a80032c /* Spare S/W Register 6 */
#define MISC_SPARE_SW_REG7             0x0a80032e /* Spare S/W Register 7 */
#define MISC_SPARE_SW_REG8             0x0a800330 /* Spare S/W Register 8 */
#define MISC_SPARE_SW_REG9             0x0a800332 /* Spare S/W Register 9 */
#define MISC_SPARE_SW_REG10            0x0a800334 /* Spare S/W Register 10 */
#define MISC_SPARE_SW_REG11            0x0a800336 /* Spare S/W Register 11 */
#define MISC_SPARE_SW_REG12            0x0a800338 /* Spare S/W Register 12 */
#define MISC_SPARE_SW_REG13            0x0a80033a /* Spare S/W Register 13 */
#define MISC_SPARE_SW_REG14            0x0a80033c /* Spare S/W Register 14 */
#define MISC_SPARE_SW_REG15            0x0a80033e /* Spare S/W Register 15 */
#define MISC_CPUSYS_MISC               0x0a800340 /* Misc CPUSYS ctrl Register */
#define MISC_BRPHYS_CLEAR_ON_READ_REG  0x0a800342 /* Misc BRPHYS_CLEAR_ON_READ_REG ctrl Register */
#define MISC_SCRATCH_REG               0x0a800ffe /* Scratch reg */


/****************************************************************************
 * bcm89530_top_bridge_CRG
 ***************************************************************************/
#define CRG_XTAL_CONFIG                0x0a820000 /* XTAL Configuration register */
#define CRG_PLL_CONFIG1                0x0a820002 /* PLL configuration1 regsiter */
#define CRG_PLL_CONFIG2                0x0a820004 /* PLL configuration2 regsiter */
#define CRG_PLL_NDIV                   0x0a820006 /* PLL NDIV integer value */
#define CRG_PLL_CTRL0                  0x0a820008 /* PLL control regsiter0 */
#define CRG_PLL_CTRL1                  0x0a82000a /* PLL control regsiter1 */
#define CRG_PLL_CTRL2                  0x0a82000c /* PLL control regsiter2 */
#define CRG_PLL_CTRL3                  0x0a82000e /* PLL control regsiter3 */
#define CRG_PLL_MDIV_CH01              0x0a820010 /* MDIV for channel 0 and 1 */
#define CRG_PLL_MDIV_CH23              0x0a820012 /* MDIV for channel 2 and 3 */
#define CRG_PLL_SSC_CONFIG1            0x0a820014 /* PLL SSC config1 */
#define CRG_PLL_SSC_CONFIG2            0x0a820016 /* PLL SSC config2 */
#define CRG_PLL_SSC_STEP               0x0a820018 /* PLL SSC Step size */
#define CRG_PLL_STATUS                 0x0a82001a /* PLL Status register */
#define CRG_CLOCK_CONFIG1              0x0a82001c /* Clock config regsiter */
#define CRG_IDDQ_CHIP                  0x0a82001e /* Chip IDDQ register */
#define CRG_IDDQ_CONFIG                0x0a820020 /* Individual Block IDDQ configuration. */
#define CRG_RESET_CONFIG               0x0a820022 /* Reset Configuration */
#define CRG_SCRATCH_REG                0x0a820ffe /* Scratch reg */


/****************************************************************************
 * bcm89530_top_bridge_IO
 ***************************************************************************/
#define IO_MII1_CONFIG                 0x0a840000 /* MII1_CONFIG */
#define IO_MII2_CONFIG                 0x0a840002 /* MII2_CONFIG */
#define IO_IO_HYSTERESIS               0x0a840004 /* IO_HYSTERESIS */
#define IO_IO_SOURCE                   0x0a840006 /* IO_SOURCE */
#define IO_IO_SEL                      0x0a840008 /* IO_SEL */
#define IO_IO_MII1_MODEHV              0x0a84000a /* MII1_MODEHV */
#define IO_IO_MII2_MODEHV              0x0a84000c /* MII2_MODEHV */
#define IO_RGMII1_CTL                  0x0a840020 /* RGMII1_CTL */
#define IO_RGMII2_CTL                  0x0a840022 /* RGMII2_CTL */
#define IO_SGMII_RGMII_CTL             0x0a840024 /* SGMII_RGMII_CTL */
#define IO_RGMII1_GMII_CTL             0x0a840026 /* RGMII1_GMII_CTL */
#define IO_RGMII2_GMII_CTL             0x0a840028 /* RGMII2_GMII_CTL */
#define IO_CPU_GMII_CTL                0x0a84002a /* CPU_GMII_CTL */
#define IO_STRAPS_RAW                  0x0a840040 /* STRAPS_RAW */
#define IO_STRAPS_OV                   0x0a840042 /* STRAPS_OV */
#define IO_SW_OVRD0                    0x0a840050 /* SW_OVRD */
#define IO_SW_OVRD1                    0x0a840052 /* SW_OVRD */
#define IO_SW_OVRD2                    0x0a840054 /* SW_OVRD */
#define IO_SW_OVRD3                    0x0a840056 /* SW_OVRD */
#define IO_SW_OVRD4                    0x0a840058 /* SW_OVRD */
#define IO_SW_OVRD5                    0x0a84005a /* SW_OVRD */
#define IO_SW_OVRD6                    0x0a84005c /* SW_OVRD */
#define IO_SW_OVRD7                    0x0a84005e /* SW_OVRD */
#define IO_SW_OVRD8                    0x0a840060 /* SW_OVRD */
#define IO_TEST_BUS_SELECT             0x0a840070 /* TEST_BUS_SELECT */
#define IO_P1588_CONFIG                0x0a840072 /* Top level P1588 Config */
#define IO_P1588_SYNC_GEN              0x0a840074 /* P1588 Sync In pulse generator */
#define IO_IOFF                        0x0a840ffe /* IOFF */


/****************************************************************************
 * bcm89530_top_bridge_TOP_1588
 ***************************************************************************/
#define TOP_1588_SLICE_ENABLE          0x0a860020 /* P1588 Slice Enable Control Register */
#define TOP_1588_TX_MODE_PORT_0        0x0a860022 /* P1588 Port 0 TX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_TX_MODE_PORT_1        0x0a860024 /* P1588 Port 1 TX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_TX_MODE_PORT_2        0x0a860026 /* P1588 Port 2 TX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_TX_MODE_PORT_3        0x0a860028 /* P1588 Port 3 TX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_TX_MODE_PORT_4        0x0a86002a /* P1588 Port 4 TX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_TX_MODE_PORT_5        0x0a86002c /* P1588 Port 5 TX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_TX_MODE_PORT_6        0x0a86002e /* P1588 Port 6 TX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_TX_MODE_PORT_7        0x0a860030 /* P1588 Port 7 TX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_RX_MODE_PORT_0        0x0a860032 /* P1588 Port 0 RX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_RX_MODE_PORT_1        0x0a860034 /* P1588 Port 1 RX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_RX_MODE_PORT_2        0x0a860036 /* P1588 Port 2 RX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_RX_MODE_PORT_3        0x0a860038 /* P1588 Port 3 RX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_RX_MODE_PORT_4        0x0a86003a /* P1588 Port 4 RX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_RX_MODE_PORT_5        0x0a86003c /* P1588 Port 5 RX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_RX_MODE_PORT_6        0x0a86003e /* P1588 Port 6 RX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_RX_MODE_PORT_7        0x0a860040 /* P1588 Port 7 RX Event Message Mode1 and Mode2 Selection Register */
#define TOP_1588_TX_TS_CAP             0x0a860042 /* P1588 TX SOP Timestamp Capture Enable */
#define TOP_1588_RX_TS_CAP             0x0a860044 /* P1588 RX SOP Timestamp Capture Enable Register */
#define TOP_1588_RX_TX_OPTION          0x0a860046 /* P1588 RX and TX Option Register */
#define TOP_1588_RX_PORT_0_LINK_DELAY_LSB 0x0a860048 /* P1588 Port 0 RX PORT Link delay LSB Register */
#define TOP_1588_RX_PORT_0_LINK_DELAY_MSB 0x0a86004a /* P1588 Port 0 RX PORT Link delay MSB Register */
#define TOP_1588_RX_PORT_1_LINK_DELAY_LSB 0x0a86004c /* P1588 Port 1 RX PORT Link delay LSB Register */
#define TOP_1588_RX_PORT_1_LINK_DELAY_MSB 0x0a86004e /* P1588 Port 1 RX PORT Link delay MSB Register */
#define TOP_1588_RX_PORT_2_LINK_DELAY_LSB 0x0a860050 /* P1588 Port 2 RX PORT Link delay LSB Register */
#define TOP_1588_RX_PORT_2_LINK_DELAY_MSB 0x0a860052 /* P1588 Port 2 RX PORT Link delay MSB Register */
#define TOP_1588_RX_PORT_3_LINK_DELAY_LSB 0x0a860054 /* P1588 Port 3 RX PORT Link delay LSB Register */
#define TOP_1588_RX_PORT_3_LINK_DELAY_MSB 0x0a860056 /* P1588 Port 3 RX PORT Link delay MSB Register */
#define TOP_1588_RX_PORT_4_LINK_DELAY_LSB 0x0a860058 /* P1588 Port 4 RX PORT Link delay LSB Register */
#define TOP_1588_RX_PORT_4_LINK_DELAY_MSB 0x0a86005a /* P1588 Port 4 RX PORT Link delay MSB Register */
#define TOP_1588_RX_PORT_5_LINK_DELAY_LSB 0x0a86005c /* P1588 Port 5 RX PORT Link delay LSB Register */
#define TOP_1588_RX_PORT_5_LINK_DELAY_MSB 0x0a86005e /* P1588 Port 5 RX PORT Link delay MSB Register */
#define TOP_1588_RX_PORT_6_LINK_DELAY_LSB 0x0a860060 /* P1588 Port 6 RX PORT Link delay LSB Register */
#define TOP_1588_RX_PORT_6_LINK_DELAY_MSB 0x0a860062 /* P1588 Port 6 RX PORT Link delay MSB Register */
#define TOP_1588_RX_PORT_7_LINK_DELAY_LSB 0x0a860064 /* P1588 Port 7 RX PORT Link delay LSB Register */
#define TOP_1588_RX_PORT_7_LINK_DELAY_MSB 0x0a860066 /* P1588 Port 7 RX PORT Link delay MSB Register */
#define TOP_1588_TX_PORT_0_TS_OFFSET_LSB 0x0a860068 /* P1588 Port 0 TX Timestamp Offset LSB Register */
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB 0x0a86006a /* P1588 Port 0 TX Timestamp Offset MSB Register */
#define TOP_1588_TX_PORT_1_TS_OFFSET_LSB 0x0a86006c /* P1588 Port 1 TX Timestamp Offset LSB Register */
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB 0x0a86006e /* P1588 Port 1 TX Timestamp Offset MSB Register */
#define TOP_1588_TX_PORT_2_TS_OFFSET_LSB 0x0a860070 /* P1588 Port 2 TX Timestamp Offset LSB Register */
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB 0x0a860072 /* P1588 Port 2 TX Timestamp Offset MSB Register */
#define TOP_1588_TX_PORT_3_TS_OFFSET_LSB 0x0a860074 /* P1588 Port 3 TX Timestamp Offset LSB Register */
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB 0x0a860076 /* P1588 Port 3 TX Timestamp Offset MSB Register */
#define TOP_1588_TX_PORT_4_TS_OFFSET_LSB 0x0a860078 /* P1588 Port 4 TX Timestamp Offset LSB Register */
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB 0x0a86007a /* P1588 Port 4 TX Timestamp Offset MSB Register */
#define TOP_1588_TX_PORT_5_TS_OFFSET_LSB 0x0a86007c /* P1588 Port 5 TX Timestamp Offset LSB Register */
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB 0x0a86007e /* P1588 Port 5 TX Timestamp Offset MSB Register */
#define TOP_1588_TX_PORT_6_TS_OFFSET_LSB 0x0a860080 /* P1588 Port 6 TX Timestamp Offset LSB Register */
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB 0x0a860082 /* P1588 Port 6 TX Timestamp Offset MSB Register */
#define TOP_1588_TX_PORT_7_TS_OFFSET_LSB 0x0a860084 /* P1588 Port 7 TX Timestamp Offset LSB Register */
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB 0x0a860086 /* P1588 Port 7 TX Timestamp Offset MSB Register */
#define TOP_1588_RX_PORT_0_TS_OFFSET_LSB 0x0a860088 /* P1588 Port 0 RX Timestamp Offset LSB Register */
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB 0x0a86008a /* P1588 Port 0 RX Timestamp Offset MSB Register */
#define TOP_1588_RX_PORT_1_TS_OFFSET_LSB 0x0a86008c /* P1588 Port 1 RX Timestamp Offset LSB Register */
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB 0x0a86008e /* P1588 Port 1 RX Timestamp Offset MSB Register */
#define TOP_1588_RX_PORT_2_TS_OFFSET_LSB 0x0a860090 /* P1588 Port 2 RX Timestamp Offset LSB Register */
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB 0x0a860092 /* P1588 Port 2 RX Timestamp Offset MSB Register */
#define TOP_1588_RX_PORT_3_TS_OFFSET_LSB 0x0a860094 /* P1588 Port 3 RX Timestamp Offset LSB Register */
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB 0x0a860096 /* P1588 Port 3 RX Timestamp Offset MSB Register */
#define TOP_1588_RX_PORT_4_TS_OFFSET_LSB 0x0a860098 /* P1588 Port 4 RX Timestamp Offset LSB Register */
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB 0x0a86009a /* P1588 Port 4 RX Timestamp Offset MSB Register */
#define TOP_1588_RX_PORT_5_TS_OFFSET_LSB 0x0a86009c /* P1588 Port 5 RX Timestamp Offset LSB Register */
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB 0x0a86009e /* P1588 Port 5 RX Timestamp Offset MSB Register */
#define TOP_1588_RX_PORT_6_TS_OFFSET_LSB 0x0a8600a0 /* P1588 Port 6 RX Timestamp Offset LSB Register */
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB 0x0a8600a2 /* P1588 Port 6 RX Timestamp Offset MSB Register */
#define TOP_1588_RX_PORT_7_TS_OFFSET_LSB 0x0a8600a4 /* P1588 Port 7 RX Timestamp Offset LSB Register */
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB 0x0a8600a6 /* P1588 Port 7 RX Timestamp Offset MSB Register */
#define TOP_1588_TIME_CODE_0           0x0a8600a8 /* P1588 Original Time Code 0 Register */
#define TOP_1588_TIME_CODE_1           0x0a8600aa /* P1588 Original Time Code 1 Register */
#define TOP_1588_TIME_CODE_2           0x0a8600ac /* P1588 Original Time Code 2 Register */
#define TOP_1588_TIME_CODE_3           0x0a8600ae /* P1588 Original Time Code 3 Register */
#define TOP_1588_TIME_CODE_4           0x0a8600b0 /* P1588 Original Time Code 4 Register */
#define TOP_1588_DPLL_DB_LSB           0x0a8600b2 /* P1588 DPLL Debug LSB Register */
#define TOP_1588_DPLL_DB_MSB           0x0a8600b4 /* P1588 DPLL Debug MSB Register */
#define TOP_1588_DPLL_DB_SEL           0x0a8600b6 /* P1588 DPLL Debug Select Register */
#define TOP_1588_SHD_CTL               0x0a8600b8 /* P1588 Shadow Register Control */
#define TOP_1588_SHD_LD                0x0a8600ba /* P1588 Shadow Register Load */
#define TOP_1588_INT_MASK              0x0a8600bc /* P1588 Interrupt Mask Register */
#define TOP_1588_INT_STAT              0x0a8600be /* P1588 Interrupt Status Register */
#define TOP_1588_TX_CTL                0x0a8600c0 /* P1588 Transmit Control Register */
#define TOP_1588_RX_CTL                0x0a8600c2 /* P1588 Receive Control Register */
#define TOP_1588_RX_TX_CTL             0x0a8600c4 /* P1588 Receive/Transmit Control Register */
#define TOP_1588_VLAN_ITPID            0x0a8600c6 /* P1588 VLAN 1tags ITPID Register */
#define TOP_1588_VLAN_OTPID            0x0a8600c8 /* P1588 VLAN 2tags OTPID Register */
#define TOP_1588_OTHER_OTPID           0x0a8600ca /* P1588 VLAN 2Tags Other OTPID Register */
#define TOP_1588_NSE_DPLL_1            0x0a8600cc /* P1588 NSE DPLL Register 1 */
#define TOP_1588_NSE_DPLL_2_0          0x0a8600ce /* P1588 NSE DPLL Register 2(0) */
#define TOP_1588_NSE_DPLL_2_1          0x0a8600d0 /* P1588 NSE DPLL Register 2(1) */
#define TOP_1588_NSE_DPLL_2_2          0x0a8600d2 /* P1588 NSE DPLL Register 2(2) */
#define TOP_1588_NSE_DPLL_3_LSB        0x0a8600d4 /* P1588 NSE DPLL Register 3 LSB */
#define TOP_1588_NSE_DPLL_3_MSB        0x0a8600d6 /* P1588 NSE DPLL Register 3 MSB */
#define TOP_1588_NSE_DPLL_4            0x0a8600d8 /* P1588 NSE DPLL Register 4 */
#define TOP_1588_NSE_DPLL_5            0x0a8600da /* P1588 NSE DPLL Register 5 */
#define TOP_1588_NSE_DPLL_6            0x0a8600dc /* P1588 NSE DPLL Register 6 */
#define TOP_1588_NSE_DPLL_7_0          0x0a8600de /* P1588 NSE DPLL Register 7(0) */
#define TOP_1588_NSE_DPLL_7_1          0x0a8600e0 /* P1588 NSE DPLL Register 7(1) */
#define TOP_1588_NSE_DPLL_7_2          0x0a8600e2 /* P1588 NSE DPLL Register 7(2) */
#define TOP_1588_NSE_DPLL_7_3          0x0a8600e4 /* P1588 NSE DPLL Register 7(3) */
#define TOP_1588_NSE_NCO_1_LSB         0x0a8600e6 /* P1588 NSE DPLL NCO Register 1 LSB */
#define TOP_1588_NSE_NCO_1_MSB         0x0a8600e8 /* P1588 NSE DPLL NCO Register 1 MSB */
#define TOP_1588_NSE_NCO_2_0           0x0a8600ea /* P1588 NSE DPLL NCO Register 2(0) */
#define TOP_1588_NSE_NCO_2_1           0x0a8600ec /* P1588 NSE DPLL NCO Register 2(1) */
#define TOP_1588_NSE_NCO_2_2           0x0a8600ee /* P1588 NSE DPLL NCO Register 2(2) */
#define TOP_1588_NSE_NCO_3_0           0x0a8600f0 /* P1588 NSE DPLL NCO Register 3(0) */
#define TOP_1588_NSE_NCO_3_1           0x0a8600f2 /* P1588 NSE DPLL NCO Register 3(1) */
#define TOP_1588_NSE_NCO_3_2           0x0a8600f4 /* P1588 NSE DPLL NCO Register 3(2) */
#define TOP_1588_NSE_NCO_4             0x0a8600f6 /* P1588 NSE DPLL NCO Register 4 */
#define TOP_1588_NSE_NCO_5_0           0x0a8600f8 /* P1588 NSE DPLL NCO Register 5(0) */
#define TOP_1588_NSE_NCO_5_1           0x0a8600fa /* P1588 NSE DPLL NCO Register 5(1) */
#define TOP_1588_NSE_NCO_5_2           0x0a8600fc /* P1588 NSE DPLL NCO Register 5(2) */
#define TOP_1588_NSE_NCO_6             0x0a8600fe /* P1588 NSE DPLL NCO Register 6 */
#define TOP_1588_NSE_NCO_7_0           0x0a860100 /* P1588 NSE DPLL NCO Register 7(0) */
#define TOP_1588_NSE_NCO_7_1           0x0a860102 /* P1588 NSE DPLL NCO Register 7(1) */
#define TOP_1588_TX_COUNTER            0x0a860104 /* P1588 TX Counter */
#define TOP_1588_RX_COUNTER            0x0a860106 /* P1588 RX Counter */
#define TOP_1588_RX_TX_1588_COUNTER    0x0a860108 /* P1588 RX TX 1588 Counter */
#define TOP_1588_TS_READ_START_END     0x0a86010a /* P1588 Timestamp READ START/END Register */
#define TOP_1588_HEARTBEAT_0           0x0a86010c /* P1588 Heartbeat Register(0) */
#define TOP_1588_HEARTBEAT_1           0x0a86010e /* P1588 Heartbeat Register(1) */
#define TOP_1588_HEARTBEAT_2           0x0a860110 /* P1588 Heartbeat Register(2) */
#define TOP_1588_TIME_STAMP_0          0x0a860112 /* P1588 Time Stamp Register(0) */
#define TOP_1588_TIME_STAMP_1          0x0a860114 /* P1588 Time Stamp Register(1) */
#define TOP_1588_TIME_STAMP_2          0x0a860116 /* P1588 Time Stamp Register(2) */
#define TOP_1588_TIME_STAMP_INFO_1     0x0a860118 /* P1588 Time Stamp Register Info (1) */
#define TOP_1588_TIME_STAMP_INFO_2     0x0a86011a /* P1588 Time Stamp Register Info (2) */
#define TOP_1588_CNTR_DBG              0x0a86011c /* P1588 Control/Debug Register */
#define TOP_1588_MPLS_SPARE1           0x0a86011e /* P1588 CPU TX and RX Port Enable Registers */
#define TOP_1588_MPLS_SPARE2           0x0a860120 /* P1588 DA1 Registers */
#define TOP_1588_MPLS_SPARE3           0x0a860122 /* P1588 DA2 Registers */
#define TOP_1588_MPLS_SPARE4           0x0a860124 /* P1588 DA3 Registers */
#define TOP_1588_MPLS_SPARE5           0x0a860126 /* P1588 MPLS Special Label LSB Registers */
#define TOP_1588_MPLS_SPARE6           0x0a860128 /* P1588 MPLS SPECIAL lABEL 4 MSB Registers */
#define TOP_1588_MPLS_TX_CNTL          0x0a86012a /* P1588 MPLS TX Enable */
#define TOP_1588_MPLS_RX_CNTL          0x0a86012c /* P1588 MPLS RX Enable */
#define TOP_1588_MPLS_LABEL1_LSB_MASK  0x0a86012e /* P1588 MPLS label1 mask lsb bit */
#define TOP_1588_MPLS_LABEL1_MSB_MASK  0x0a860130 /* P1588 MPLS label1 mask msb bit (*Inband P0 Control) */
#define TOP_1588_MPLS_LABEL1_LSB_VALUE 0x0a860132 /* P1588 MPLS label1 value lsb bit */
#define TOP_1588_MPLS_LABEL1_MSB_VALUE 0x0a860134 /* P1588 MPLS label1 value msb bit (*HSR P0 Offset) */
#define TOP_1588_MPLS_LABEL2_LSB_MASK  0x0a860136 /* P1588 MPLS label2 mask lsb bit */
#define TOP_1588_MPLS_LABEL2_MSB_MASK  0x0a860138 /* P1588 MPLS label2 mask msb bit (*Inband P1 Control) */
#define TOP_1588_MPLS_LABEL2_LSB_VALUE 0x0a86013a /* P1588 MPLS label2 value lsb bit */
#define TOP_1588_MPLS_LABEL2_MSB_VALUE 0x0a86013c /* P1588 MPLS label2 value msb bit (*HSR P1 Offset) */
#define TOP_1588_MPLS_LABEL3_LSB_MASK  0x0a86013e /* P1588 MPLS label3 mask lsb bit */
#define TOP_1588_MPLS_LABEL3_MSB_MASK  0x0a860140 /* P1588 MPLS label3 mask msb bit (*Inband P2 Control) */
#define TOP_1588_MPLS_LABEL3_LSB_VALUE 0x0a860142 /* P1588 MPLS label3 value lsb bit */
#define TOP_1588_MPLS_LABEL3_MSB_VALUE 0x0a860144 /* P1588 MPLS label3 value msb bit (*HSR P2 Offset) */
#define TOP_1588_MPLS_LABEL4_LSB_MASK  0x0a860146 /* P1588 MPLS label4 mask lsb bit */
#define TOP_1588_MPLS_LABEL4_MSB_MASK  0x0a860148 /* P1588 MPLS label4 mask msb bit (*Inband P3 Control) */
#define TOP_1588_MPLS_LABEL4_LSB_VALUE 0x0a86014a /* P1588 MPLS label4 value lsb bit */
#define TOP_1588_MPLS_LABEL4_MSB_VALUE 0x0a86014c /* P1588 MPLS label4 value msb bit (*HSR P3 Offset) */
#define TOP_1588_MPLS_LABEL5_LSB_MASK  0x0a86014e /* P1588 MPLS label5 mask lsb bit */
#define TOP_1588_MPLS_LABEL5_MSB_MASK  0x0a860150 /* P1588 MPLS label5 mask msb bit (*Inband P4 Control) */
#define TOP_1588_MPLS_LABEL5_LSB_VALUE 0x0a860152 /* P1588 MPLS label5 value lsb bit */
#define TOP_1588_MPLS_LABEL5_MSB_VALUE 0x0a860154 /* P1588 MPLS label5 value msb bit (*HSR P4 Offset) */
#define TOP_1588_MPLS_LABEL6_LSB_MASK  0x0a860156 /* P1588 MPLS label6 mask lsb bit */
#define TOP_1588_MPLS_LABEL6_MSB_MASK  0x0a860158 /* P1588 MPLS label6 mask msb bit (*Inband P5 Control) */
#define TOP_1588_MPLS_LABEL6_LSB_VALUE 0x0a86015a /* P1588 MPLS label6 value lsb bit */
#define TOP_1588_MPLS_LABEL6_MSB_VALUE 0x0a86015c /* P1588 MPLS label6 value msb bit (*HSR P5 Offset) */
#define TOP_1588_MPLS_LABEL7_LSB_MASK  0x0a86015e /* P1588 MPLS label7 mask lsb bit */
#define TOP_1588_MPLS_LABEL7_MSB_MASK  0x0a860160 /* P1588 MPLS label7 mask msb bit (*Inband P6 Control) */
#define TOP_1588_MPLS_LABEL7_LSB_VALUE 0x0a860162 /* P1588 MPLS label7 value lsb bit */
#define TOP_1588_MPLS_LABEL7_MSB_VALUE 0x0a860164 /* P1588 MPLS label7 value msb bit (*HSR P6 Offset) */
#define TOP_1588_MPLS_LABEL8_LSB_MASK  0x0a860166 /* P1588 MPLS label8 mask lsb bit */
#define TOP_1588_MPLS_LABEL8_MSB_MASK  0x0a860168 /* P1588 MPLS label8 mask msb bit (*Inband P7 Control) */
#define TOP_1588_MPLS_LABEL8_LSB_VALUE 0x0a86016a /* P1588 MPLS label8 value lsb bit */
#define TOP_1588_MPLS_LABEL8_MSB_VALUE 0x0a86016c /* P1588 MPLS label8 value msb bit (*HSR P7 Offset) */
#define TOP_1588_MPLS_LABEL9_LSB_MASK  0x0a86016e /* P1588 MPLS label9 mask lsb bit */
#define TOP_1588_MPLS_LABEL9_MSB_MASK  0x0a860170 /* P1588 MPLS label9 mask msb bit */
#define TOP_1588_MPLS_LABEL9_LSB_VALUE 0x0a860172 /* P1588 MPLS label9 value lsb bit */
#define TOP_1588_MPLS_LABEL9_MSB_VALUE 0x0a860174 /* P1588 MPLS label9 value msb bit */
#define TOP_1588_MPLS_LABEL10_LSB_MASK 0x0a860176 /* P1588 MPLS label10 mask lsb bit (*HSR Enable) */
#define TOP_1588_MPLS_LABEL10_MSB_MASK 0x0a860178 /* P1588 MPLS label10 mask msb bit (*HSR Ethertype) */
#define TOP_1588_MPLS_LABEL10_LSB_VALUE 0x0a86017a /* P1588 MPLS label10 value lsb bit (*HSR SNAP/LLC Control) */
#define TOP_1588_MPLS_LABEL10_MSB_VALUE 0x0a86017c /* P1588 MPLS label10 value msb bit */
#define TOP_1588_RX_TX_1588_COUNTER1   0x0a86017e /* P1588 RX TX CPU 1588 Counter */
#define TOP_1588_RX_CF_SPEC            0x0a860180 /* P1588 RX CF + Insertion */
#define TOP_1588_TX_CF_SPEC            0x0a860182 /* P1588 TX CS Update */
#define TOP_1588_MPLS_PACKET_ENABLE    0x0a860184 /* P1588 MPLS_PACKET ENABLE */
#define TOP_1588_TIMECODE_SEL          0x0a860186 /* P1588 TIMECODE SEL */
#define TOP_1588_TIME_STAMP_3          0x0a860188 /* P1588 Time Stamp Register(3) */
#define TOP_1588_TIME_STAMP            0x0a86018a /* P1588 Control/Debug Register */
#define TOP_1588_DM_TX_CNTL            0x0a86018c /* P1588 Delay Measurment Control Register */
#define TOP_1588_DM_RX_CNTL            0x0a86018e /* P1588 Delay Measurment Control Register */
#define TOP_1588_DM_ETHTYPE1           0x0a860190 /* P1588 Delay Measurment Ethtype1 Register */
#define TOP_1588_DM_ETHTYPE2           0x0a860192 /* P1588 Delay Measurment Ethtype2 Register */
#define TOP_1588_DM_ETHTYPE3           0x0a860194 /* P1588 Delay Measurment Ethtype3 Register */
#define TOP_1588_DM_ETHTYPE4           0x0a860196 /* P1588 Delay Measurment Ethtype4 Register */
#define TOP_1588_DM_ETHTYPE5           0x0a860198 /* P1588 Delay Measurment Ethtype5 Register */
#define TOP_1588_DM_ETHTYPE6           0x0a86019a /* P1588 Delay Measurment Ethtype6 Register */
#define TOP_1588_DM_ETHTYPE7           0x0a86019c /* P1588 Delay Measurment Ethtype7 Register */
#define TOP_1588_DM_ETHTYPE8           0x0a86019e /* P1588 Delay Measurment Ethtype8 Register */
#define TOP_1588_DM_ETHTYPE9           0x0a8601a0 /* P1588 Delay Measurment Ethtype9 Register */
#define TOP_1588_DM_ETHTYPE10          0x0a8601a2 /* P1588 Delay Measurment Ethtype10 Register */
#define TOP_1588_DM_ETHTYPE11          0x0a8601a4 /* P1588 Delay Measurment Ethtype11 Register */
#define TOP_1588_DM_ETHTYPE12          0x0a8601a6 /* P1588 Delay Measurment Ethtype12 Register */
#define TOP_1588_DM_ETHTYPE13          0x0a8601a8 /* P1588 Delay Measurment Ethtype13 Register */
#define TOP_1588_DM_IETF_OFFSET        0x0a8601aa /* P1588 Delay Measurment IETF Offfset Register */
#define TOP_1588_NTP_TIME_STAMP_0      0x0a8601ac /* P1588 NTP Counter Time Stamp0  Register */
#define TOP_1588_NTP_TIME_STAMP_1      0x0a8601ae /* P1588 NTP Counter Time Stamp1  Register */
#define TOP_1588_NTP_TIME_STAMP_2      0x0a8601b0 /* P1588 NTP Counter Time Stamp2  Register */
#define TOP_1588_NTP_TIME_STAMP_3      0x0a8601b2 /* P1588 NTP Counter Time Stamp3  Register */
#define TOP_1588_NTP_NCO_FREQ_0        0x0a8601b4 /* P1588 NTP NCO Frequency0  Register */
#define TOP_1588_NTP_NCO_FREQ_1        0x0a8601b6 /* P1588 NTP NCO Frequency1  Register */
#define TOP_1588_NTP_DOWN_CNTER_0      0x0a8601b8 /* P1588 NTP Down Counter 0  Register */
#define TOP_1588_NTP_DOWN_CNTER_1      0x0a8601ba /* P1588 NTP Down Counter 1  Register */
#define TOP_1588_NTP_ERR_LSB           0x0a8601bc /* P1588 NTP ERR LSB  Register */
#define TOP_1588_NTP_ERR_MSB           0x0a8601be /* P1588 NTP ERR MSB  Register */
#define TOP_1588_DM_MAC_L1_0           0x0a8601c0 /* P1588 DM MAC Address Local1 0 Register */
#define TOP_1588_DM_MAC_L1_1           0x0a8601c2 /* P1588 DM MAC Address Local1 0 Register */
#define TOP_1588_DM_MAC_L1_2           0x0a8601c4 /* P1588 DM MAC Address Local1 0 Register */
#define TOP_1588_DM_MAC_L2_0           0x0a8601c6 /* P1588 DM MAC Address Local2 0 Register */
#define TOP_1588_DM_MAC_L2_1           0x0a8601c8 /* P1588 DM MAC Address Local2 0 Register */
#define TOP_1588_DM_MAC_L2_2           0x0a8601ca /* P1588 DM MAC Address Local2 0 Register */
#define TOP_1588_DM_MAC_L3_0           0x0a8601cc /* P1588 DM MAC Address Local3 0 Register */
#define TOP_1588_DM_MAC_L3_1           0x0a8601ce /* P1588 DM MAC Address Local3 0 Register */
#define TOP_1588_DM_MAC_L3_2           0x0a8601d0 /* P1588 DM MAC Address Local3 0 Register */
#define TOP_1588_DM_MAC_CTL_0          0x0a8601d2 /* P1588 DM MAC cONTROL 0 Register */
#define TOP_1588_DM_MAC_CTL_1          0x0a8601d4 /* P1588 DM MAC CONTROL 1 Register */
#define TOP_1588_DM_MAC_CTL_2          0x0a8601d6 /* P1588 DM MAC CONTROL 2 Register */
#define TOP_1588_HEARTBEAT_3           0x0a8601d8 /* P1588 Heartbeat Register(3) */
#define TOP_1588_HEARTBEAT_4           0x0a8601da /* P1588 Heartbeat Register(4) */
#define TOP_1588_INBAND_CNTL_0         0x0a8601dc /* P1588 Inband Control Port0 Register */
#define TOP_1588_INBAND_CNTL_1         0x0a8601de /* P1588 Inband Control Port1 Register */
#define TOP_1588_INBAND_CNTL_2         0x0a8601e0 /* P1588 Inband Control Port2 Register */
#define TOP_1588_INBAND_CNTL_3         0x0a8601e2 /* P1588 Inband Control Port3 Register */
#define TOP_1588_INBAND_CNTL_4         0x0a8601e4 /* P1588 Inband Control Port4 Register */
#define TOP_1588_INBAND_CNTL_5         0x0a8601e6 /* P1588 Inband Control Port5 Register */
#define TOP_1588_INBAND_CNTL_6         0x0a8601e8 /* P1588 Inband Control Port6 Register */
#define TOP_1588_INBAND_CNTL_7         0x0a8601ea /* P1588 Inband Control Port7 Register */
#define TOP_1588_MEM_COUNTER           0x0a8601ec /* P1588 Memory Counter Register */
#define TOP_1588_TIMESTAMP_DELTA       0x0a8601ee /* P1588 Timestamp Delta Register */
#define TOP_1588_SOP_SEL               0x0a8601f0 /* P1588 SOP Selection Register */
#define TOP_1588_TIME_STAMP_INFO_3     0x0a8601f2 /* P1588 Time Stamp Register Info (3) */
#define TOP_1588_TIME_STAMP_INFO_4     0x0a8601f4 /* P1588 Time Stamp Register Info (4) */
#define TOP_1588_TIME_STAMP_INFO_5     0x0a8601f6 /* P1588 Time Stamp Register Info (5) */
#define TOP_1588_TIME_STAMP_INFO_6     0x0a8601f8 /* P1588 Time Stamp Register Info (6) */
#define TOP_1588_TIME_STAMP_INFO_7     0x0a8601fa /* P1588 Time Stamp Register Info (7) */
#define TOP_1588_TIME_STAMP_INFO_8     0x0a8601fc /* P1588 Time Stamp Register Info (8) */
#define TOP_1588_INBAND_SPARE1         0x0a8601fe /* P1588 Inband Spare1 Register */


/****************************************************************************
 * bcm89530_swsys_switch
 ***************************************************************************/
#define SWITCH_PAGE_00_G_PCTL0         0x0b000000 /* Port 0 10/100/1000 Control Register */
#define SWITCH_PAGE_00_G_PCTL1         0x0b000001 /* Port 1 10/100/1000 Control Register */
#define SWITCH_PAGE_00_G_PCTL2         0x0b000002 /* Port 2 10/100/1000 Control Register */
#define SWITCH_PAGE_00_G_PCTL3         0x0b000003 /* Port 3 10/100/1000 Control Register */
#define SWITCH_PAGE_00_G_PCTL4         0x0b000004 /* Port 4 10/100/1000 Control Register */
#define SWITCH_PAGE_00_G_PCTL5         0x0b000005 /* Port 5 10/100/1000 Control Register */
#define SWITCH_PAGE_00_G_PCTL6         0x0b000006 /* Port 6 10/100/1000 Control Register */
#define SWITCH_PAGE_00_P7_CTL          0x0b000007 /* Port 7 Control Register */
#define SWITCH_PAGE_00_IMP_CTL         0x0b000008 /* IMP Port (Port 8) Control Register */
#define SWITCH_PAGE_00_RX_GLOBAL_CTL   0x0b00000a /* RX Global Control register(Not2Release) */
#define SWITCH_PAGE_00_SWMODE          0x0b00000b /* Switch Mode Register */
#define SWITCH_PAGE_00_LED_REFLSH_CTL  0x0b00000f /* LED Configuration Register */
#define SWITCH_PAGE_00_LED_FUNC0_CTL   0x0b000010 /* LED Function 0 control register */
#define SWITCH_PAGE_00_LED_FUNC1_CTL   0x0b000012 /* LED Function 1 control register */
#define SWITCH_PAGE_00_LED_FUNC_MAP    0x0b000014 /* LED Function Map register */
#define SWITCH_PAGE_00_LED_EN_MAP      0x0b000016 /* LED Enable Map register */
#define SWITCH_PAGE_00_LED_MODE_MAP_0  0x0b000018 /* LED Mode map 0 register */
#define SWITCH_PAGE_00_LED_MODE_MAP_1  0x0b00001a /* LED Mode map 1 register */
#define SWITCH_PAGE_00_POST_LED_CTRL   0x0b00001d /* Post LED Control Register */
#define SWITCH_PAGE_00_DEBUG_REG       0x0b00001e /* Debug Control Register(Not2Release) */
#define SWITCH_PAGE_00_NEW_CTRL        0x0b000021 /* New Control Register */
#define SWITCH_PAGE_00_SWITCH_CTRL     0x0b000022 /* Switch Control Register (Not2Release) */
#define SWITCH_PAGE_00_PROTECTED_SEL   0x0b000024 /* Protected Port Select Register */
#define SWITCH_PAGE_00_WAN_PORT_SEL    0x0b000026 /* WAN Port select Register */
#define SWITCH_PAGE_00_RSV_MCAST_CTRL  0x0b00002f /* Reserved Multicast Register */
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE  0x0b000031 /* TxQ Flush Mode Control Register(Not2Release) */
#define SWITCH_PAGE_00_ULF_DROP_MAP    0x0b000032 /* Unicast Lookup Failed Forward Map Register */
#define SWITCH_PAGE_00_MLF_DROP_MAP    0x0b000034 /* Multicast Lookup Failed Forward Map Register */
#define SWITCH_PAGE_00_MLF_IPMC_FWD_MAP 0x0b000036 /* IPMC Forward Map Register */
#define SWITCH_PAGE_00_RX_PAUSE_PASS   0x0b000038 /* Pause pass Through for RX Register */
#define SWITCH_PAGE_00_TX_PAUSE_PASS   0x0b00003a /* Pause pass Through for TX Register */
#define SWITCH_PAGE_00_DIS_LEARN       0x0b00003c /* Disable Learning Register */
#define SWITCH_PAGE_00_SFT_LRN_CTL     0x0b00003e /* Software Learning Control */
#define SWITCH_PAGE_00_LOW_POWER_EXP1  0x0b000040 /* Low Power Expansion I Register */
#define SWITCH_PAGE_00_PHY_INT_STS     0x0b000044 /* PHY Interrupt Status Register (Not2Release) */
#define SWITCH_PAGE_00_CTLREG_REG_SPARE 0x0b000054 /* Spare Register (Not2Release) */
#define SWITCH_PAGE_00_WATCH_DOG_RPT1  0x0b00007a /* Watch Dog Report 1 Register(Not2Release) */
#define SWITCH_PAGE_00_WATCH_DOG_RPT2  0x0b00007c /* Watch Dog Report 2 Register(Not2Release) */
#define SWITCH_PAGE_00_WATCH_DOG_RPT3  0x0b00007e /* Watch Dog Report 3 Register(Not2Release) */
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL  0x0b000080 /* Pause Frame Detection Control Register */
#define SWITCH_PAGE_00_PAUSE_ST_ADDR   0x0b000081 /* PAUSE Frame DA Address */
#define SWITCH_PAGE_00_FAST_AGE_CTRL   0x0b000088 /* Fast Ageing Control Register */
#define SWITCH_PAGE_00_FAST_AGE_PORT   0x0b000089 /* Fast Ageing Port Control Register */
#define SWITCH_PAGE_00_FAST_AGE_VID    0x0b00008a /* Fast Ageing VID Control Register */
#define SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL 0x0b000090 /* LED Function 0 Extended Control Register */
#define SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL 0x0b000092 /* LED Function 1 Extended Control Register */
#define SWITCH_PAGE_00_LOW_POWER_CTRL  0x0b0000de /* Core-Level LOW Power Control Register */
#define SWITCH_PAGE_00_TCAM_CTRL       0x0b0000e8 /* TCAM Control Register */
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS 0x0b0000ea /* TCAM Checksum Status Register */
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL 0x0b0000ec /* Light Stacking Control Register */
#define SWITCH_PAGE_01_LNKSTS          0x0b000100 /* Link Status Summary Register */
#define SWITCH_PAGE_01_LNKSTSCHG       0x0b000102 /* Link Status Change Register */
#define SWITCH_PAGE_01_SPDSTS          0x0b000104 /* Port Speed Summary Register */
#define SWITCH_PAGE_01_DUPSTS          0x0b000108 /* Duplex status Summary Register */
#define SWITCH_PAGE_01_PAUSESTS        0x0b00010a /* Pause Status Summary Register */
#define SWITCH_PAGE_01_SRCADRCHG       0x0b00010e /* Source Address Change Register */
#define SWITCH_PAGE_01_LSA_PORT0       0x0b000110 /* Port 0 Last Source Address */
#define SWITCH_PAGE_01_LSA_PORT1       0x0b000116 /* Port 1 Last Source Address */
#define SWITCH_PAGE_01_LSA_PORT2       0x0b00011c /* Port 2 Last Source Address */
#define SWITCH_PAGE_01_LSA_PORT3       0x0b000122 /* Port 3 Last Source Address */
#define SWITCH_PAGE_01_LSA_PORT4       0x0b000128 /* Port 4 Last Source Address */
#define SWITCH_PAGE_01_LSA_PORT5       0x0b00012e /* Port 5 Last Source Address */
#define SWITCH_PAGE_01_LSA_PORT6       0x0b000134 /* Port 6 Last Source Address */
#define SWITCH_PAGE_01_LSA_PORT7       0x0b00013a /* Port 7 Last Source Address */
#define SWITCH_PAGE_01_LSA_MII_PORT    0x0b000140 /* Port 8 Last Source Address */
#define SWITCH_PAGE_01_BIST_STS0       0x0b000146 /* BIST Status Register 0 */
#define SWITCH_PAGE_01_BIST_STS1       0x0b00014c /* BIST Status Register 1 */
#define SWITCH_PAGE_01_PBPTRFIFO_0     0x0b000150 /* PBPTRFIFO Status Register 0(Not2Release) */
#define SWITCH_PAGE_01_PBPTRFIFO_1     0x0b000156 /* PBPTRFIFO Status Register 1(Not2Release) */
#define SWITCH_PAGE_01_RESET_STATUS    0x0b000190 /* Reset Status Register */
#define SWITCH_PAGE_01_STREG_REG_SPARE0 0x0b0001a0 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_01_STREG_REG_SPARE1 0x0b0001a4 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_02_GMNGCFG         0x0b000200 /* Global Management Configuration Register */
#define SWITCH_PAGE_02_IMP0_PRT_ID     0x0b000201 /* IMP/IMP0 Port ID Register */
#define SWITCH_PAGE_02_IMP1_PRT_ID     0x0b000202 /* IMP1 Port ID Register */
#define SWITCH_PAGE_02_BRCM_HDR_CTRL   0x0b000203 /* BRCM Header Control Register */
#define SWITCH_PAGE_02_SPTAGT          0x0b000206 /* Aging Time Control Register */
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2  0x0b00020a /* BRCM Header Control 2 Register */
#define SWITCH_PAGE_02_IPG_SHRNK_CTRL  0x0b00020c /* IPG Shrink Control Register */
#define SWITCH_PAGE_02_MIRCAPCTL       0x0b000210 /* Mirror Capture Control Register */
#define SWITCH_PAGE_02_IGMIRCTL        0x0b000212 /* Ingress Mirror Control Register */
#define SWITCH_PAGE_02_IGMIRDIV        0x0b000214 /* Ingress Mirror Divider Register */
#define SWITCH_PAGE_02_IGMIRMAC        0x0b000216 /* Ingress Mirror Mac Address Register */
#define SWITCH_PAGE_02_EGMIRCTL        0x0b00021c /* Egress Mirror Control Register */
#define SWITCH_PAGE_02_EGMIRDIV        0x0b00021e /* Egress Mirror Divider Register */
#define SWITCH_PAGE_02_EGMIRMAC        0x0b000220 /* Egress Mirror MAC Address Register */
#define SWITCH_PAGE_02_SPANCTL         0x0b000226 /* SPAN RSPAN Control Register */
#define SWITCH_PAGE_02_RSPANVLAN       0x0b00022a /* RSPAN VLAN ID Register */
#define SWITCH_PAGE_02_MODEL_ID        0x0b000230 /* Model ID Register (Not2Release) */
#define SWITCH_PAGE_02_CHIP_REVID      0x0b000240 /* Chip Version ID Register */
#define SWITCH_PAGE_02_HL_PRTC_CTRL    0x0b000250 /* High Level Protocol Control Register */
#define SWITCH_PAGE_02_RST_MIB_CNT_EN  0x0b000254 /* Reset MIB Counter Enable Register */
#define SWITCH_PAGE_02_IPG_SHRINK_2G_WA 0x0b000258 /* IPG Shrink 2G Workaround Register (Not2Release) */
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE0 0x0b000270 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE1 0x0b000274 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_03_INT_STS         0x0b000300 /* External Host Raw Interrupt Status Register */
#define SWITCH_PAGE_03_INT_EN          0x0b000308 /* External Host Interrupt Enable Register */
#define SWITCH_PAGE_03_IMP_SLEEP_TIMER 0x0b000310 /* IMP Port(port 8) Sleep Timer Register */
#define SWITCH_PAGE_03_PORT7_SLEEP_TIMER 0x0b000312 /* Port 7 Sleep Timer Register */
#define SWITCH_PAGE_03_WAN_SLEEP_TIMER 0x0b000314 /* WAN Port Sleep Timer Register */
#define SWITCH_PAGE_03_PORT_SLEEP_STS  0x0b000318 /* Port Sleep Status Register */
#define SWITCH_PAGE_03_INT_TRIGGER     0x0b000320 /* Interrupt Trigger Register */
#define SWITCH_PAGE_03_LINK_STS_INT_EN 0x0b000324 /* Link Status Interrupt Enable Register */
#define SWITCH_PAGE_03_ENG_DET_INT_EN  0x0b000328 /* Energy Detection Interrupt Enable Register */
#define SWITCH_PAGE_03_LPI_STS_CHG_INT_EN 0x0b00032a /* LPI Status Change Interrupt Enable Register */
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER 0x0b000340 /* CPU Resource Arbitor Register */
#define SWITCH_PAGE_03_CPU_DATA_SHARE  0x0b000350 /* CPU Data Share Register */
#define SWITCH_PAGE_03_CPU_DATA_SHARE_1 0x0b000358 /* CPU Data Share 1 Register */
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS 0x0b000360 /* Memory ECC Double-Error-Detection Interrupt Status (Not2Release) */
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN 0x0b000362 /* Memory ECC Double-Error-Detection Interrupt Enable (Not2Release) */
#define SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS 0x0b000364 /* Per Port EVT Table ECC Double-Error-Detection Error Status (Not2Release) */
#define SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS 0x0b000366 /* Per Port MIB Counter ECC Double-Error-Detection Error Status (Not2Release) */
#define SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS 0x0b000368 /* Per Port TXQ ECC Double-Error-Detection Error Status (Not2Release) */
#define SWITCH_PAGE_03_PROBE_BUS_CTL   0x0b000370 /* Probe Bus Control Registers(Not2Release) */
#define SWITCH_PAGE_03_MDC_EXTEND_CTRL 0x0b000374 /* MDC Extend Clock Control Register (Not2Release) */
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN 0x0b000380 /* PPPoE Session Packet Parsing Enable Register */
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE0 0x0b000390 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE1 0x0b000394 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_04_GARLCFG         0x0b000400 /* Global ARL Configuration Register */
#define SWITCH_PAGE_04_BPDU_MCADDR     0x0b000404 /* BPDU Multicast Address Register */
#define SWITCH_PAGE_04_MULTI_PORT_CTL  0x0b00040e /* Multiport Control Register */
#define SWITCH_PAGE_04_MULTIPORT_ADDR0 0x0b000410 /* Multiport Address 0 Register (Default for TS) */
#define SWITCH_PAGE_04_MPORTVEC0       0x0b000418 /* Multiport Vector 0 Register */
#define SWITCH_PAGE_04_MULTIPORT_ADDR1 0x0b000420 /* Multiport Address 1 Register */
#define SWITCH_PAGE_04_MPORTVEC1       0x0b000428 /* Multiport Vector 1 Register */
#define SWITCH_PAGE_04_MULTIPORT_ADDR2 0x0b000430 /* Multiport Address 2 Register */
#define SWITCH_PAGE_04_MPORTVEC2       0x0b000438 /* Multiport Vector 2 Register */
#define SWITCH_PAGE_04_MULTIPORT_ADDR3 0x0b000440 /* Multiport Address 3 Register */
#define SWITCH_PAGE_04_MPORTVEC3       0x0b000448 /* Multiport Vector 3 Register */
#define SWITCH_PAGE_04_MULTIPORT_ADDR4 0x0b000450 /* Multiport Address 4 Register */
#define SWITCH_PAGE_04_MPORTVEC4       0x0b000458 /* Multiport Vector 4 Register */
#define SWITCH_PAGE_04_MULTIPORT_ADDR5 0x0b000460 /* Multiport Address 5 Register */
#define SWITCH_PAGE_04_MPORTVEC5       0x0b000468 /* Multiport Vector 5 Register */
#define SWITCH_PAGE_04_ARL_BIN_FULL_CNTR 0x0b000470 /* ARL Bin Full Counter Register */
#define SWITCH_PAGE_04_ARL_BIN_FULL_FWD 0x0b000474 /* ARL Biin Full Forward Enable Register */
#define SWITCH_PAGE_04_ARL_SEED        0x0b000476 /* ARL Programmable seed */
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE0 0x0b000480 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE1 0x0b000484 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_04_ARL_TCAM_CTRL   0x0b000490 /* ARL TCAM Control Register */
#define SWITCH_PAGE_04_ARL_TCAM_STS    0x0b000494 /* ARL TCAM Status Register */
#define SWITCH_PAGE_04_ARL_TCAM_FULL_CNTR 0x0b000498 /* ARL TCAM Full Counter Register */
#define SWITCH_PAGE_05_ARLA_RWCTL      0x0b000500 /* ARL Read/Write Control Register */
#define SWITCH_PAGE_05_ARLA_MAC        0x0b000502 /* MAC Address Index Register */
#define SWITCH_PAGE_05_ARLA_VID        0x0b000508 /* VID Index Register */
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0 0x0b000510 /* ARL MAC/VID Entry 0 Register */
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0 0x0b000518 /* ARL FWD Entry 0 Register */
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1 0x0b000520 /* ARL MAC/VID Entry 1 Register */
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1 0x0b000528 /* ARL FWD Entry 1 Register */
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2 0x0b000530 /* ARL MAC/VID Entry 2 Register */
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2 0x0b000538 /* ARL FWD Entry 2 Register */
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3 0x0b000540 /* ARL MAC/VID Entry 3 Register */
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3 0x0b000548 /* ARL FWD Entry 3 Register */
#define SWITCH_PAGE_05_ARLA_SRCH_CTL   0x0b000550 /* ARL Search Control Register */
#define SWITCH_PAGE_05_ARLA_SRCH_ADR   0x0b000551 /* ARL Search Address Register */
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID 0x0b000560 /* ARL Search MAC/VID Result 0 Register */
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0 0x0b000568 /* ARL Search Result 0 Register */
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID 0x0b000570 /* ARL Search MAC/VID Result 1 Register */
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1 0x0b000578 /* ARL Search Result 1 Register */
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL 0x0b000580 /* VTBL Read/Write/Clear Control Register */
#define SWITCH_PAGE_05_ARLA_VTBL_ADDR  0x0b000581 /* VTBL Address Index Register */
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY 0x0b000583 /* VTBL Entry Register */
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE0 0x0b000590 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE1 0x0b000594 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_08_MEM_CTRL        0x0b000800 /* Memory Debug Control Register */
#define SWITCH_PAGE_08_MEM_ADDR        0x0b000801 /* Memory Debug Address Register */
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_0 0x0b000808 /* Memory Debug Data 0_0 Register */
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_1 0x0b000810 /* Memory Debug Data 0_1 Register */
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_0 0x0b000812 /* Memory Debug Data 1_0 Register */
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_1 0x0b00081a /* Memory Debug Data 1_1 Register */
#define SWITCH_PAGE_08_MEM_FRM_ADDR    0x0b000820 /* Frame Memory Address Register */
#define SWITCH_PAGE_08_MEM_FRM_DATA0   0x0b000830 /* Frame Memory Data 1st Register */
#define SWITCH_PAGE_08_MEM_FRM_DATA1   0x0b000838 /* Frame Memory Data 2st Register */
#define SWITCH_PAGE_08_MEM_FRM_DATA2   0x0b000840 /* Frame Memory Data 3st Register */
#define SWITCH_PAGE_08_MEM_FRM_DATA3   0x0b000848 /* Frame Memory Data 4th Register */
#define SWITCH_PAGE_08_MEM_BTM_DATA0   0x0b000850 /* Buffer Tag Memory Register 0 */
#define SWITCH_PAGE_08_MEM_BTM_DATA1   0x0b000858 /* Buffer Tag Memory Register 1 */
#define SWITCH_PAGE_08_MEM_BFC_ADDR    0x0b000860 /* Buffer Control Memory Address Register */
#define SWITCH_PAGE_08_MEM_BFC_DATA    0x0b000862 /* Buffer Control Memory Data Register */
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL 0x0b000870 /* PRS_FIFO Debug Control Register(Not2Release) */
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_DATA 0x0b000871 /* PRS_FIFO Debug Data Register(Not2Release) */
#define SWITCH_PAGE_08_MEM_REG_SPARE0  0x0b0008a8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_08_MEM_REG_SPARE1  0x0b0008ac /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_08_MEM_MISC_CTRL   0x0b0008b0 /* Memory Misc Control Register */
#define SWITCH_PAGE_08_MEM_TEST_CTRL0  0x0b0008b4 /* Memory Test Control 0 Register */
#define SWITCH_PAGE_08_MEM_TEST_CTRL1  0x0b0008b8 /* Memory Test Control 1 Register */
#define SWITCH_PAGE_08_MEM_TEST_CTRL2  0x0b0008bc /* Memory Test Control 2 Register */
#define SWITCH_PAGE_08_MEM_TEST_CTRL3  0x0b0008c0 /* Memory Test Control 3 Register */
#define SWITCH_PAGE_08_MEM_TEST_CTRL4  0x0b0008c4 /* Memory Test Control 4 Register */
#define SWITCH_PAGE_08_MEM_TEST_CTRL5  0x0b0008c8 /* Memory Test Control 5 Register */
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL 0x0b0008e0 /* Memory PSM_VDD Pin Control register */
#define SWITCH_PAGE_09_PORT0_DEBUG     0x0b000900 /* PORT0 DEBUG */
#define SWITCH_PAGE_09_PORT1_DEBUG     0x0b000910 /* PORT1 DEBUG */
#define SWITCH_PAGE_09_PORT2_DEBUG     0x0b000920 /* PORT2 DEBUG */
#define SWITCH_PAGE_09_PORT3_DEBUG     0x0b000930 /* PORT3 DEBUG */
#define SWITCH_PAGE_09_PORT4_DEBUG     0x0b000940 /* PORT4 DEBUG */
#define SWITCH_PAGE_09_PORT5_DEBUG     0x0b000950 /* PORT5 DEBUG */
#define SWITCH_PAGE_09_PORT6_DEBUG     0x0b000960 /* PORT6 DEBUG */
#define SWITCH_PAGE_09_PORT7_DEBUG     0x0b000970 /* PORT7 DEBUG */
#define SWITCH_PAGE_09_PORT8_DEBUG     0x0b000980 /* PORT8 DEBUG */
#define SWITCH_PAGE_0A_FC_DIAG_CTRL    0x0b000a00 /* Flowcon Diagnosis Control Register */
#define SWITCH_PAGE_0A_FC_CTRL_MODE    0x0b000a02 /* Flow Control Mode Selection Register */
#define SWITCH_PAGE_0A_FC_CTRL_PORT    0x0b000a03 /* Flow Control Port Selection Register */
#define SWITCH_PAGE_0A_FC_OOB_PAUSE_EN 0x0b000a04 /* OOB Pause Signal Enable Register (Release2Customer) */
#define SWITCH_PAGE_0A_PAUSE_TIME_MAX  0x0b000a10 /* MAX Quantum Pause Time Register */
#define SWITCH_PAGE_0A_PAUSE_TIME_MIN  0x0b000a12 /* MIN Quantum Pause Time Register */
#define SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD 0x0b000a14 /* Quantum Pause Threshold Register */
#define SWITCH_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD 0x0b000a16 /* Quantum Pause Update Period Register */
#define SWITCH_PAGE_0A_PAUSE_TIME_DEFAULT 0x0b000a18 /* Default Quantum Pause Time Register */
#define SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL 0x0b000a1a /* Multicast Drop Control Register */
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL 0x0b000a1c /* Pause/Drop Control Register */
#define SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF 0x0b000a1e /* TXQ Pause Off Threshold Register */
#define SWITCH_PAGE_0A_FC_RX_RUNOFF    0x0b000a20 /* RX-Based Run-Off Register */
#define SWITCH_PAGE_0A_FC_RX_RSV_THD   0x0b000a22 /* RX-Based Reserved Register */
#define SWITCH_PAGE_0A_FC_RX_HYST_THD  0x0b000a24 /* RX-Based Hysteresis Register */
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR   0x0b000a26 /* RX-Based Maximum Buffer Remap Register */
#define SWITCH_PAGE_0A_FC_SPARE_ZERO_REG 0x0b000a28 /* Flow Control Spare Zero Register */
#define SWITCH_PAGE_0A_FC_SPARE_ONE_REG 0x0b000a2a /* Flow Control Spare One Register */
#define SWITCH_PAGE_0A_FC_MON_TXQ0     0x0b000a30 /* Monitored TXQ 0 Register */
#define SWITCH_PAGE_0A_FC_MON_TXQ1     0x0b000a32 /* Monitored TXQ 1 Register */
#define SWITCH_PAGE_0A_FC_MON_TXQ2     0x0b000a34 /* Monitored TXQ 2 Register */
#define SWITCH_PAGE_0A_FC_MON_TXQ3     0x0b000a36 /* Monitored TXQ 3 Register */
#define SWITCH_PAGE_0A_FC_MON_TXQ4     0x0b000a38 /* Monitored TXQ 4 Register */
#define SWITCH_PAGE_0A_FC_MON_TXQ5     0x0b000a3a /* Monitored TXQ 5 Register */
#define SWITCH_PAGE_0A_FC_MON_TXQ6     0x0b000a3c /* Monitored TXQ 6 Register */
#define SWITCH_PAGE_0A_FC_MON_TXQ7     0x0b000a3e /* Monitored TXQ 7 Register */
#define SWITCH_PAGE_0A_FC_PEAK_TXQ0    0x0b000a40 /* Peak TXQ 0 Counter Register */
#define SWITCH_PAGE_0A_FC_PEAK_TXQ1    0x0b000a42 /* Peak TXQ 1 Counter Register */
#define SWITCH_PAGE_0A_FC_PEAK_TXQ2    0x0b000a44 /* Peak TXQ 2 Counter Register */
#define SWITCH_PAGE_0A_FC_PEAK_TXQ3    0x0b000a46 /* Peak TXQ 3 Counter Register */
#define SWITCH_PAGE_0A_FC_PEAK_TXQ4    0x0b000a48 /* Peak TXQ 4 Counter Register */
#define SWITCH_PAGE_0A_FC_PEAK_TXQ5    0x0b000a4a /* Peak TXQ 5 Counter Register */
#define SWITCH_PAGE_0A_FC_PEAK_TXQ6    0x0b000a4c /* Peak TXQ 6 Counter Register */
#define SWITCH_PAGE_0A_FC_PEAK_TXQ7    0x0b000a4e /* Peak TXQ 7 Counter Register */
#define SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED 0x0b000a50 /* Peak Total Used Count Register */
#define SWITCH_PAGE_0A_FC_TOTAL_USED   0x0b000a52 /* Total Used Count Register */
#define SWITCH_PAGE_0A_FC_PEAK_RX_CNT  0x0b000a54 /* Peak RX Counter Register */
#define SWITCH_PAGE_0A_FC_LINK_PORTMAP 0x0b000a56 /* PHY Link Information Register */
#define SWITCH_PAGE_0A_FC_GIGA_PORTMAP 0x0b000a58 /* Giga Speed Information Register */
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT0 0x0b000a60 /* Port N (0 to 6) Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT1 0x0b000a62 /* Port N (0 to 6) Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT2 0x0b000a64 /* Port N (0 to 6) Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT3 0x0b000a66 /* Port N (0 to 6) Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT4 0x0b000a68 /* Port N (0 to 6) Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT5 0x0b000a6a /* Port N (0 to 6) Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT6 0x0b000a6c /* Port N (0 to 6) Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P7 0x0b000a6e /* Port 7 Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P8 0x0b000a70 /* Port 8 Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_PAUSE_HIS    0x0b000a78 /* Pause History Register */
#define SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS 0x0b000a7a /* TX Quantum Pause History Register */
#define SWITCH_PAGE_0A_FC_RX_PAUSE_HIS 0x0b000a7c /* RX Based Pause History Register */
#define SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS 0x0b000a7e /* RX Buffer Error History Register */
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT0 0x0b000a80 /* Port N (0 to 6) TXQ Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT1 0x0b000a82 /* Port N (0 to 6) TXQ Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT2 0x0b000a84 /* Port N (0 to 6) TXQ Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT3 0x0b000a86 /* Port N (0 to 6) TXQ Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT4 0x0b000a88 /* Port N (0 to 6) TXQ Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT5 0x0b000a8a /* Port N (0 to 6) TXQ Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT6 0x0b000a8c /* Port N (0 to 6) TXQ Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7 0x0b000a8e /* Port 7 TXQ Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8 0x0b000a90 /* Port 8 TXQ Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT0 0x0b000a9a /* Port N (0 to 6) Total Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT1 0x0b000a9c /* Port N (0 to 6) Total Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT2 0x0b000a9e /* Port N (0 to 6) Total Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT3 0x0b000aa0 /* Port N (0 to 6) Total Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT4 0x0b000aa2 /* Port N (0 to 6) Total Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT5 0x0b000aa4 /* Port N (0 to 6) Total Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT6 0x0b000aa6 /* Port N (0 to 6) Total Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7 0x0b000aa8 /* Port 7 Total Congested PortMap Register */
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8 0x0b000aaa /* Port 8 Total Congested PortMap Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0 0x0b000b00 /* LAN Port Queue 0 Reserved Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1 0x0b000b02 /* LAN Port Queue 1 Reserved Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2 0x0b000b04 /* LAN Port Queue 2 Reserved Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3 0x0b000b06 /* LAN Port Queue 3 Reserved Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4 0x0b000b08 /* LAN Port Queue 4 Reserved Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5 0x0b000b0a /* LAN Port Queue 5 Reserved Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6 0x0b000b0c /* LAN Port Queue 6 Reserved Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7 0x0b000b0e /* LAN Port Queue 7 Reserved Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0 0x0b000b10 /* LAN Port Queue 0 Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1 0x0b000b12 /* LAN Port Queue 1 Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2 0x0b000b14 /* LAN Port Queue 2 Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3 0x0b000b16 /* LAN Port Queue 3 Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4 0x0b000b18 /* LAN Port Queue 4 Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5 0x0b000b1a /* LAN Port Queue 5 Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6 0x0b000b1c /* LAN Port Queue 6 Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7 0x0b000b1e /* LAN Port Queue 7 Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0 0x0b000b20 /* LAN Port Queue 0 Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1 0x0b000b22 /* LAN Port Queue 1 Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2 0x0b000b24 /* LAN Port Queue 2 Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3 0x0b000b26 /* LAN Port Queue 3 Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4 0x0b000b28 /* LAN Port Queue 4 Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5 0x0b000b2a /* LAN Port Queue 5 Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6 0x0b000b2c /* LAN Port Queue 6 Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7 0x0b000b2e /* LAN Port Queue 0 Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0 0x0b000b30 /* LAN Port Queue 0 DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1 0x0b000b32 /* LAN Port Queue 1 DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2 0x0b000b34 /* LAN Port Queue 2 DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3 0x0b000b36 /* LAN Port Queue 3 DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4 0x0b000b38 /* LAN Port Queue 4 DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5 0x0b000b3a /* LAN Port Queue 5 DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6 0x0b000b3c /* LAN Port Queue 6 DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7 0x0b000b3e /* LAN Port Queue 7 DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0 0x0b000b40 /* LAN Port Queue 0 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1 0x0b000b42 /* LAN Port Queue 2 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2 0x0b000b44 /* LAN Port Queue 2 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3 0x0b000b46 /* LAN Port Queue 3 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4 0x0b000b48 /* LAN Port Queue 4 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5 0x0b000b4a /* LAN Port Queue 5 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6 0x0b000b4c /* LAN Port Queue 6 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7 0x0b000b4e /* LAN Port Queue 7 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0 0x0b000b50 /* LAN Port Queue 0 Total Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1 0x0b000b52 /* LAN Port Queue 1 Total Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2 0x0b000b54 /* LAN Port Queue 2 Total Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3 0x0b000b56 /* LAN Port Queue 3 Total Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4 0x0b000b58 /* LAN Port Queue 4 Total Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5 0x0b000b5a /* LAN Port Queue 5 Total Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6 0x0b000b5c /* LAN Port Queue 6 Total Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7 0x0b000b5e /* LAN Port Queue 7 Total Pause Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0 0x0b000b60 /* LAN Port Queue 0 Total DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1 0x0b000b62 /* LAN Port Queue 1 Total DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2 0x0b000b64 /* LAN Port Queue 2 Total DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3 0x0b000b66 /* LAN Port Queue 3 Total DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4 0x0b000b68 /* LAN Port Queue 4 Total DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5 0x0b000b6a /* LAN Port Queue 5 Total DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6 0x0b000b6c /* LAN Port Queue 6 Total DROP Threshold Register */
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7 0x0b000b6e /* LAN Port Queue 0 Total DROP Threshold Register */
#define SWITCH_PAGE_0C_P0_DEBUG_MUX    0x0b000c00 /* P0 DEBUG MUX */
#define SWITCH_PAGE_0C_P1_DEBUG_MUX    0x0b000c04 /* P1 DEBUG MUX */
#define SWITCH_PAGE_0C_P2_DEBUG_MUX    0x0b000c08 /* P2 DEBUG MUX */
#define SWITCH_PAGE_0C_P3_DEBUG_MUX    0x0b000c0c /* P3 DEBUG MUX */
#define SWITCH_PAGE_0C_P4_DEBUG_MUX    0x0b000c10 /* P4 DEBUG MUX */
#define SWITCH_PAGE_0C_P5_DEBUG_MUX    0x0b000c14 /* P5 DEBUG MUX */
#define SWITCH_PAGE_0C_P6_DEBUG_MUX    0x0b000c18 /* P6 DEBUG MUX */
#define SWITCH_PAGE_0C_P7_DEBUG_MUX    0x0b000c1c /* P7 DEBUG MUX */
#define SWITCH_PAGE_0C_IMP_DEBUG_MUX   0x0b000c20 /* IMP DEBUG MUX */
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_0 0x0b000c24 /* CFP DEBUG BUS 0 */
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_1 0x0b000c28 /* CFP DEBUG BUS 1 */
#define SWITCH_PAGE_0C_WRED_DEBUG_0    0x0b000c2c /* WRED DEBUG 0 */
#define SWITCH_PAGE_0C_WRED_DEBUG_1    0x0b000c30 /* WRED DEBUG 1 */
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_0 0x0b000c34 /* TOP MISC DEBUG 0 */
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_1 0x0b000c38 /* TOP MISC DEBUG 1 */
#define SWITCH_PAGE_0C_DIAGREG_BUFCON  0x0b000c3c /* DIAGREG BUFCON */
#define SWITCH_PAGE_0C_TESTBUS_P1588   0x0b000c40 /* TESTBUS P1588 */
#define SWITCH_PAGE_0C_FLOWCON_DEBUG_BUS 0x0b000c44 /* FLOWCON DEBUG BUS */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0 0x0b000d00 /* IMP0 Port Queue 0 Reserved Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1 0x0b000d02 /* IMP0 Port Queue 1 Reserved Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2 0x0b000d04 /* IMP0 Port Queue 2 Reserved Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3 0x0b000d06 /* IMP0 Port Queue 3 Reserved Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4 0x0b000d08 /* IMP0 Port Queue 4 Reserved Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5 0x0b000d0a /* IMP0 Port Queue 5 Reserved Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6 0x0b000d0c /* IMP0 Port Queue 6 Reserved Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7 0x0b000d0e /* IMP0 Port Queue 7 Reserved Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0 0x0b000d10 /* IMP0 Port Queue 0 Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1 0x0b000d12 /* IMP0 Port Queue 1 Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2 0x0b000d14 /* IMP0 Port Queue 2 Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3 0x0b000d16 /* IMP0 Port Queue 3 Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4 0x0b000d18 /* IMP0 Port Queue 4 Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5 0x0b000d1a /* IMP0 Port Queue 5 Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6 0x0b000d1c /* IMP0 Port Queue 6 Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7 0x0b000d1e /* IMP0 Port Queue 7 Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0 0x0b000d20 /* IMP0 Port Queue 0 Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1 0x0b000d22 /* IMP0 Port Queue 1 Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2 0x0b000d24 /* IMP0 Port Queue 2 Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3 0x0b000d26 /* IMP0 Port Queue 3 Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4 0x0b000d28 /* IMP0 Port Queue 4 Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5 0x0b000d2a /* IMP0 Port Queue 5 Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6 0x0b000d2c /* IMP0 Port Queue 6 Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7 0x0b000d2e /* IMP0 Port Queue 0 Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0 0x0b000d30 /* IMP0 Port Queue 0 DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1 0x0b000d32 /* IMP0 Port Queue 1 DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2 0x0b000d34 /* IMP0 Port Queue 2 DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3 0x0b000d36 /* IMP0 Port Queue 3 DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4 0x0b000d38 /* IMP0 Port Queue 4 DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5 0x0b000d3a /* IMP0 Port Queue 5 DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6 0x0b000d3c /* IMP0 Port Queue 6 DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7 0x0b000d3e /* IMP0 Port Queue 7 DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0 0x0b000d40 /* IMP0 Port Queue 0 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1 0x0b000d42 /* IMP0 Port Queue 2 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2 0x0b000d44 /* IMP0 Port Queue 2 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3 0x0b000d46 /* IMP0 Port Queue 3 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4 0x0b000d48 /* IMP0 Port Queue 4 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5 0x0b000d4a /* IMP0 Port Queue 5 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6 0x0b000d4c /* IMP0 Port Queue 6 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7 0x0b000d4e /* IMP0 Port Queue 7 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0 0x0b000d50 /* IMP0 Port Queue 0 Total Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1 0x0b000d52 /* IMP0 Port Queue 1 Total Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2 0x0b000d54 /* IMP0 Port Queue 2 Total Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3 0x0b000d56 /* IMP0 Port Queue 3 Total Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4 0x0b000d58 /* IMP0 Port Queue 4 Total Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5 0x0b000d5a /* IMP0 Port Queue 5 Total Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6 0x0b000d5c /* IMP0 Port Queue 6 Total Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7 0x0b000d5e /* IMP0 Port Queue 7 Total Pause Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0 0x0b000d60 /* IMP0 Port Queue 0 Total DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1 0x0b000d62 /* IMP0 Port Queue 1 Total DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2 0x0b000d64 /* IMP0 Port Queue 2 Total DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3 0x0b000d66 /* IMP0 Port Queue 3 Total DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4 0x0b000d68 /* IMP0 Port Queue 4 Total DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5 0x0b000d6a /* IMP0 Port Queue 5 Total DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6 0x0b000d6c /* IMP0 Port Queue 6 Total DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7 0x0b000d6e /* IMP0 Port Queue 0 Total DROP Threshold Register */
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE0 0x0b000d70 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE1 0x0b000d72 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0 0x0b000e00 /* WAN/IMP1 Port Queue 0 Reserved Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1 0x0b000e02 /* WAN/IMP1 Port Queue 1 Reserved Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2 0x0b000e04 /* WAN/IMP1 Port Queue 2 Reserved Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3 0x0b000e06 /* WAN/IMP1 Port Queue 3 Reserved Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4 0x0b000e08 /* WAN/IMP1 Port Queue 4 Reserved Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5 0x0b000e0a /* WAN/IMP1 Port Queue 5 Reserved Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6 0x0b000e0c /* WAN/IMP1 Port Queue 6 Reserved Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7 0x0b000e0e /* WAN/IMP1 Port Queue 7 Reserved Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0 0x0b000e10 /* WAN/IMP1 Port Queue 0 Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1 0x0b000e12 /* WAN/IMP1 Port Queue 1 Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2 0x0b000e14 /* WAN/IMP1 Port Queue 2 Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3 0x0b000e16 /* WAN/IMP1 Port Queue 3 Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4 0x0b000e18 /* WAN/IMP1 Port Queue 4 Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5 0x0b000e1a /* WAN/IMP1 Port Queue 5 Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6 0x0b000e1c /* WAN/IMP1 Port Queue 6 Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7 0x0b000e1e /* WAN/IMP1 Port Queue 7 Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 0x0b000e20 /* WAN/IMP1 Port Queue 0 Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 0x0b000e22 /* WAN/IMP1 Port Queue 1 Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 0x0b000e24 /* WAN/IMP1 Port Queue 2 Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 0x0b000e26 /* WAN/IMP1 Port Queue 3 Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 0x0b000e28 /* WAN/IMP1 Port Queue 4 Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 0x0b000e2a /* WAN/IMP1 Port Queue 5 Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 0x0b000e2c /* WAN/IMP1 Port Queue 6 Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 0x0b000e2e /* WAN/IMP1 Port Queue 0 Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0 0x0b000e30 /* WAN/IMP1 Port Queue 0 DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1 0x0b000e32 /* WAN/IMP1 Port Queue 1 DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2 0x0b000e34 /* WAN/IMP1 Port Queue 2 DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3 0x0b000e36 /* WAN/IMP1 Port Queue 3 DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4 0x0b000e38 /* WAN/IMP1 Port Queue 4 DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5 0x0b000e3a /* WAN/IMP1 Port Queue 5 DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6 0x0b000e3c /* WAN/IMP1 Port Queue 6 DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7 0x0b000e3e /* WAN/IMP1 Port Queue 7 DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0 0x0b000e40 /* WAN/IMP1 Port Queue 0 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1 0x0b000e42 /* WAN/IMP1 Port Queue 2 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2 0x0b000e44 /* WAN/IMP1 Port Queue 2 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3 0x0b000e46 /* WAN/IMP1 Port Queue 3 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4 0x0b000e48 /* WAN/IMP1 Port Queue 4 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5 0x0b000e4a /* WAN/IMP1 Port Queue 5 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6 0x0b000e4c /* WAN/IMP1 Port Queue 6 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7 0x0b000e4e /* WAN/IMP1 Port Queue 7 Total Hysteresis Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 0x0b000e50 /* WAN/IMP1 Port Queue 0 Total Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 0x0b000e52 /* WAN/IMP1 Port Queue 1 Total Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 0x0b000e54 /* WAN/IMP1 Port Queue 2 Total Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 0x0b000e56 /* WAN/IMP1 Port Queue 3 Total Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 0x0b000e58 /* WAN/IMP1 Port Queue 4 Total Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 0x0b000e5a /* WAN/IMP1 Port Queue 5 Total Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 0x0b000e5c /* WAN/IMP1 Port Queue 6 Total Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 0x0b000e5e /* WAN/IMP1 Port Queue 7 Total Pause Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0 0x0b000e60 /* WAN/IMP1 Port Queue 0 Total DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1 0x0b000e62 /* WAN/IMP1 Port Queue 1 Total DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2 0x0b000e64 /* WAN/IMP1 Port Queue 2 Total DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3 0x0b000e66 /* WAN/IMP1 Port Queue 3 Total DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4 0x0b000e68 /* WAN/IMP1 Port Queue 4 Total DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5 0x0b000e6a /* WAN/IMP1 Port Queue 5 Total DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6 0x0b000e6c /* WAN/IMP1 Port Queue 6 Total DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7 0x0b000e6e /* WAN/IMP1 Port Queue 0 Total DROP Threshold Register */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE0 0x0b000e70 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE1 0x0b000e72 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_20_TXOCTETS        0x0b002000 /* Tx Octets */
#define SWITCH_PAGE_20_TXDROPPKTS      0x0b002008 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_20_TXQPKTQ0        0x0b00200c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_20_TXBROADCASTPKTS 0x0b002010 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_20_TXMULTICASTPKTS 0x0b002014 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_20_TXUNICASTPKTS   0x0b002018 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_20_TXCOLLISIONS    0x0b00201c /* Tx Collision Counter */
#define SWITCH_PAGE_20_TXSINGLECOLLISION 0x0b002020 /* Tx Single Collision Counter */
#define SWITCH_PAGE_20_TXMULTIPLECOLLISION 0x0b002024 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_20_TXDEFERREDTRANSMIT 0x0b002028 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_20_TXLATECOLLISION 0x0b00202c /* Tx Late Collision Counter */
#define SWITCH_PAGE_20_TXEXCESSIVECOLLISION 0x0b002030 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_20_TXFRAMEINDISC   0x0b002034 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_20_TXPAUSEPKTS     0x0b002038 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_20_TXQPKTQ1        0x0b00203c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_20_TXQPKTQ2        0x0b002040 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_20_TXQPKTQ3        0x0b002044 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_20_TXQPKTQ4        0x0b002048 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_20_TXQPKTQ5        0x0b00204c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_20_RXOCTETS        0x0b002050 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_20_RXUNDERSIZEPKTS 0x0b002058 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_20_RXPAUSEPKTS     0x0b00205c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_20_RXPKTS64OCTETS  0x0b002060 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_20_RXPKTS65TO127OCTETS 0x0b002064 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_20_RXPKTS128TO255OCTETS 0x0b002068 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_20_RXPKTS256TO511OCTETS 0x0b00206c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_20_RXPKTS512TO1023OCTETS 0x0b002070 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_20_RXPKTS1024TOMAXPKTOCTETS 0x0b002074 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_20_RXOVERSIZEPKTS  0x0b002078 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_20_RXJABBERS       0x0b00207c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_20_RXALIGNMENTERRORS 0x0b002080 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_20_RXFCSERRORS     0x0b002084 /* Rx FCS Error Counter */
#define SWITCH_PAGE_20_RXGOODOCTETS    0x0b002088 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_20_RXDROPPKTS      0x0b002090 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_20_RXUNICASTPKTS   0x0b002094 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_20_RXMULTICASTPKTS 0x0b002098 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_20_RXBROADCASTPKTS 0x0b00209c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_20_RXSACHANGES     0x0b0020a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_20_RXFRAGMENTS     0x0b0020a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_20_RXJUMBOPKT      0x0b0020a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_20_RXSYMBLERR      0x0b0020ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_20_INRANGEERRCOUNT 0x0b0020b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_20_OUTRANGEERRCOUNT 0x0b0020b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_20_EEE_LPI_EVENT   0x0b0020b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_20_EEE_LPI_DURATION 0x0b0020bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_20_RXDISCARD       0x0b0020c0 /* Rx Discard Counter */
#define SWITCH_PAGE_20_TXQPKTQ6        0x0b0020c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_20_TXQPKTQ7        0x0b0020cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_20_TXPKTS64OCTETS  0x0b0020d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_20_TXPKTS65TO127OCTETS 0x0b0020d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_20_TXPKTS128TO255OCTETS 0x0b0020d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_20_TXPKTS256TO511OCTETS 0x0b0020dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_20_TXPKTS512TO1023OCTETS 0x0b0020e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_20_TXPKTS1024TOMAXPKTOCTETS 0x0b0020e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_21_TXOCTETS        0x0b002100 /* Tx Octets */
#define SWITCH_PAGE_21_TXDROPPKTS      0x0b002108 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_21_TXQPKTQ0        0x0b00210c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_21_TXBROADCASTPKTS 0x0b002110 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_21_TXMULTICASTPKTS 0x0b002114 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_21_TXUNICASTPKTS   0x0b002118 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_21_TXCOLLISIONS    0x0b00211c /* Tx Collision Counter */
#define SWITCH_PAGE_21_TXSINGLECOLLISION 0x0b002120 /* Tx Single Collision Counter */
#define SWITCH_PAGE_21_TXMULTIPLECOLLISION 0x0b002124 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_21_TXDEFERREDTRANSMIT 0x0b002128 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_21_TXLATECOLLISION 0x0b00212c /* Tx Late Collision Counter */
#define SWITCH_PAGE_21_TXEXCESSIVECOLLISION 0x0b002130 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_21_TXFRAMEINDISC   0x0b002134 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_21_TXPAUSEPKTS     0x0b002138 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_21_TXQPKTQ1        0x0b00213c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_21_TXQPKTQ2        0x0b002140 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_21_TXQPKTQ3        0x0b002144 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_21_TXQPKTQ4        0x0b002148 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_21_TXQPKTQ5        0x0b00214c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_21_RXOCTETS        0x0b002150 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_21_RXUNDERSIZEPKTS 0x0b002158 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_21_RXPAUSEPKTS     0x0b00215c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_21_RXPKTS64OCTETS  0x0b002160 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_21_RXPKTS65TO127OCTETS 0x0b002164 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_21_RXPKTS128TO255OCTETS 0x0b002168 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_21_RXPKTS256TO511OCTETS 0x0b00216c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_21_RXPKTS512TO1023OCTETS 0x0b002170 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_21_RXPKTS1024TOMAXPKTOCTETS 0x0b002174 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_21_RXOVERSIZEPKTS  0x0b002178 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_21_RXJABBERS       0x0b00217c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_21_RXALIGNMENTERRORS 0x0b002180 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_21_RXFCSERRORS     0x0b002184 /* Rx FCS Error Counter */
#define SWITCH_PAGE_21_RXGOODOCTETS    0x0b002188 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_21_RXDROPPKTS      0x0b002190 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_21_RXUNICASTPKTS   0x0b002194 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_21_RXMULTICASTPKTS 0x0b002198 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_21_RXBROADCASTPKTS 0x0b00219c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_21_RXSACHANGES     0x0b0021a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_21_RXFRAGMENTS     0x0b0021a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_21_RXJUMBOPKT      0x0b0021a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_21_RXSYMBLERR      0x0b0021ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_21_INRANGEERRCOUNT 0x0b0021b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_21_OUTRANGEERRCOUNT 0x0b0021b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_21_EEE_LPI_EVENT   0x0b0021b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_21_EEE_LPI_DURATION 0x0b0021bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_21_RXDISCARD       0x0b0021c0 /* Rx Discard Counter */
#define SWITCH_PAGE_21_TXQPKTQ6        0x0b0021c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_21_TXQPKTQ7        0x0b0021cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_21_TXPKTS64OCTETS  0x0b0021d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_21_TXPKTS65TO127OCTETS 0x0b0021d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_21_TXPKTS128TO255OCTETS 0x0b0021d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_21_TXPKTS256TO511OCTETS 0x0b0021dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_21_TXPKTS512TO1023OCTETS 0x0b0021e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_21_TXPKTS1024TOMAXPKTOCTETS 0x0b0021e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_22_TXOCTETS        0x0b002200 /* Tx Octets */
#define SWITCH_PAGE_22_TXDROPPKTS      0x0b002208 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_22_TXQPKTQ0        0x0b00220c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_22_TXBROADCASTPKTS 0x0b002210 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_22_TXMULTICASTPKTS 0x0b002214 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_22_TXUNICASTPKTS   0x0b002218 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_22_TXCOLLISIONS    0x0b00221c /* Tx Collision Counter */
#define SWITCH_PAGE_22_TXSINGLECOLLISION 0x0b002220 /* Tx Single Collision Counter */
#define SWITCH_PAGE_22_TXMULTIPLECOLLISION 0x0b002224 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_22_TXDEFERREDTRANSMIT 0x0b002228 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_22_TXLATECOLLISION 0x0b00222c /* Tx Late Collision Counter */
#define SWITCH_PAGE_22_TXEXCESSIVECOLLISION 0x0b002230 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_22_TXFRAMEINDISC   0x0b002234 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_22_TXPAUSEPKTS     0x0b002238 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_22_TXQPKTQ1        0x0b00223c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_22_TXQPKTQ2        0x0b002240 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_22_TXQPKTQ3        0x0b002244 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_22_TXQPKTQ4        0x0b002248 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_22_TXQPKTQ5        0x0b00224c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_22_RXOCTETS        0x0b002250 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_22_RXUNDERSIZEPKTS 0x0b002258 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_22_RXPAUSEPKTS     0x0b00225c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_22_RXPKTS64OCTETS  0x0b002260 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_22_RXPKTS65TO127OCTETS 0x0b002264 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_22_RXPKTS128TO255OCTETS 0x0b002268 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_22_RXPKTS256TO511OCTETS 0x0b00226c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_22_RXPKTS512TO1023OCTETS 0x0b002270 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_22_RXPKTS1024TOMAXPKTOCTETS 0x0b002274 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_22_RXOVERSIZEPKTS  0x0b002278 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_22_RXJABBERS       0x0b00227c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_22_RXALIGNMENTERRORS 0x0b002280 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_22_RXFCSERRORS     0x0b002284 /* Rx FCS Error Counter */
#define SWITCH_PAGE_22_RXGOODOCTETS    0x0b002288 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_22_RXDROPPKTS      0x0b002290 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_22_RXUNICASTPKTS   0x0b002294 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_22_RXMULTICASTPKTS 0x0b002298 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_22_RXBROADCASTPKTS 0x0b00229c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_22_RXSACHANGES     0x0b0022a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_22_RXFRAGMENTS     0x0b0022a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_22_RXJUMBOPKT      0x0b0022a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_22_RXSYMBLERR      0x0b0022ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_22_INRANGEERRCOUNT 0x0b0022b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_22_OUTRANGEERRCOUNT 0x0b0022b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_22_EEE_LPI_EVENT   0x0b0022b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_22_EEE_LPI_DURATION 0x0b0022bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_22_RXDISCARD       0x0b0022c0 /* Rx Discard Counter */
#define SWITCH_PAGE_22_TXQPKTQ6        0x0b0022c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_22_TXQPKTQ7        0x0b0022cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_22_TXPKTS64OCTETS  0x0b0022d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_22_TXPKTS65TO127OCTETS 0x0b0022d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_22_TXPKTS128TO255OCTETS 0x0b0022d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_22_TXPKTS256TO511OCTETS 0x0b0022dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_22_TXPKTS512TO1023OCTETS 0x0b0022e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_22_TXPKTS1024TOMAXPKTOCTETS 0x0b0022e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_23_TXOCTETS        0x0b002300 /* Tx Octets */
#define SWITCH_PAGE_23_TXDROPPKTS      0x0b002308 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_23_TXQPKTQ0        0x0b00230c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_23_TXBROADCASTPKTS 0x0b002310 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_23_TXMULTICASTPKTS 0x0b002314 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_23_TXUNICASTPKTS   0x0b002318 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_23_TXCOLLISIONS    0x0b00231c /* Tx Collision Counter */
#define SWITCH_PAGE_23_TXSINGLECOLLISION 0x0b002320 /* Tx Single Collision Counter */
#define SWITCH_PAGE_23_TXMULTIPLECOLLISION 0x0b002324 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_23_TXDEFERREDTRANSMIT 0x0b002328 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_23_TXLATECOLLISION 0x0b00232c /* Tx Late Collision Counter */
#define SWITCH_PAGE_23_TXEXCESSIVECOLLISION 0x0b002330 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_23_TXFRAMEINDISC   0x0b002334 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_23_TXPAUSEPKTS     0x0b002338 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_23_TXQPKTQ1        0x0b00233c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_23_TXQPKTQ2        0x0b002340 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_23_TXQPKTQ3        0x0b002344 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_23_TXQPKTQ4        0x0b002348 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_23_TXQPKTQ5        0x0b00234c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_23_RXOCTETS        0x0b002350 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_23_RXUNDERSIZEPKTS 0x0b002358 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_23_RXPAUSEPKTS     0x0b00235c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_23_RXPKTS64OCTETS  0x0b002360 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_23_RXPKTS65TO127OCTETS 0x0b002364 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_23_RXPKTS128TO255OCTETS 0x0b002368 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_23_RXPKTS256TO511OCTETS 0x0b00236c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_23_RXPKTS512TO1023OCTETS 0x0b002370 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_23_RXPKTS1024TOMAXPKTOCTETS 0x0b002374 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_23_RXOVERSIZEPKTS  0x0b002378 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_23_RXJABBERS       0x0b00237c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_23_RXALIGNMENTERRORS 0x0b002380 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_23_RXFCSERRORS     0x0b002384 /* Rx FCS Error Counter */
#define SWITCH_PAGE_23_RXGOODOCTETS    0x0b002388 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_23_RXDROPPKTS      0x0b002390 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_23_RXUNICASTPKTS   0x0b002394 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_23_RXMULTICASTPKTS 0x0b002398 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_23_RXBROADCASTPKTS 0x0b00239c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_23_RXSACHANGES     0x0b0023a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_23_RXFRAGMENTS     0x0b0023a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_23_RXJUMBOPKT      0x0b0023a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_23_RXSYMBLERR      0x0b0023ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_23_INRANGEERRCOUNT 0x0b0023b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_23_OUTRANGEERRCOUNT 0x0b0023b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_23_EEE_LPI_EVENT   0x0b0023b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_23_EEE_LPI_DURATION 0x0b0023bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_23_RXDISCARD       0x0b0023c0 /* Rx Discard Counter */
#define SWITCH_PAGE_23_TXQPKTQ6        0x0b0023c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_23_TXQPKTQ7        0x0b0023cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_23_TXPKTS64OCTETS  0x0b0023d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_23_TXPKTS65TO127OCTETS 0x0b0023d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_23_TXPKTS128TO255OCTETS 0x0b0023d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_23_TXPKTS256TO511OCTETS 0x0b0023dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_23_TXPKTS512TO1023OCTETS 0x0b0023e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_23_TXPKTS1024TOMAXPKTOCTETS 0x0b0023e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_24_TXOCTETS        0x0b002400 /* Tx Octets */
#define SWITCH_PAGE_24_TXDROPPKTS      0x0b002408 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_24_TXQPKTQ0        0x0b00240c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_24_TXBROADCASTPKTS 0x0b002410 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_24_TXMULTICASTPKTS 0x0b002414 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_24_TXUNICASTPKTS   0x0b002418 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_24_TXCOLLISIONS    0x0b00241c /* Tx Collision Counter */
#define SWITCH_PAGE_24_TXSINGLECOLLISION 0x0b002420 /* Tx Single Collision Counter */
#define SWITCH_PAGE_24_TXMULTIPLECOLLISION 0x0b002424 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_24_TXDEFERREDTRANSMIT 0x0b002428 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_24_TXLATECOLLISION 0x0b00242c /* Tx Late Collision Counter */
#define SWITCH_PAGE_24_TXEXCESSIVECOLLISION 0x0b002430 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_24_TXFRAMEINDISC   0x0b002434 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_24_TXPAUSEPKTS     0x0b002438 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_24_TXQPKTQ1        0x0b00243c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_24_TXQPKTQ2        0x0b002440 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_24_TXQPKTQ3        0x0b002444 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_24_TXQPKTQ4        0x0b002448 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_24_TXQPKTQ5        0x0b00244c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_24_RXOCTETS        0x0b002450 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_24_RXUNDERSIZEPKTS 0x0b002458 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_24_RXPAUSEPKTS     0x0b00245c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_24_RXPKTS64OCTETS  0x0b002460 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_24_RXPKTS65TO127OCTETS 0x0b002464 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_24_RXPKTS128TO255OCTETS 0x0b002468 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_24_RXPKTS256TO511OCTETS 0x0b00246c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_24_RXPKTS512TO1023OCTETS 0x0b002470 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_24_RXPKTS1024TOMAXPKTOCTETS 0x0b002474 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_24_RXOVERSIZEPKTS  0x0b002478 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_24_RXJABBERS       0x0b00247c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_24_RXALIGNMENTERRORS 0x0b002480 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_24_RXFCSERRORS     0x0b002484 /* Rx FCS Error Counter */
#define SWITCH_PAGE_24_RXGOODOCTETS    0x0b002488 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_24_RXDROPPKTS      0x0b002490 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_24_RXUNICASTPKTS   0x0b002494 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_24_RXMULTICASTPKTS 0x0b002498 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_24_RXBROADCASTPKTS 0x0b00249c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_24_RXSACHANGES     0x0b0024a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_24_RXFRAGMENTS     0x0b0024a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_24_RXJUMBOPKT      0x0b0024a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_24_RXSYMBLERR      0x0b0024ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_24_INRANGEERRCOUNT 0x0b0024b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_24_OUTRANGEERRCOUNT 0x0b0024b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_24_EEE_LPI_EVENT   0x0b0024b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_24_EEE_LPI_DURATION 0x0b0024bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_24_RXDISCARD       0x0b0024c0 /* Rx Discard Counter */
#define SWITCH_PAGE_24_TXQPKTQ6        0x0b0024c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_24_TXQPKTQ7        0x0b0024cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_24_TXPKTS64OCTETS  0x0b0024d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_24_TXPKTS65TO127OCTETS 0x0b0024d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_24_TXPKTS128TO255OCTETS 0x0b0024d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_24_TXPKTS256TO511OCTETS 0x0b0024dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_24_TXPKTS512TO1023OCTETS 0x0b0024e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_24_TXPKTS1024TOMAXPKTOCTETS 0x0b0024e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_25_TXOCTETS        0x0b002500 /* Tx Octets */
#define SWITCH_PAGE_25_TXDROPPKTS      0x0b002508 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_25_TXQPKTQ0        0x0b00250c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_25_TXBROADCASTPKTS 0x0b002510 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_25_TXMULTICASTPKTS 0x0b002514 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_25_TXUNICASTPKTS   0x0b002518 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_25_TXCOLLISIONS    0x0b00251c /* Tx Collision Counter */
#define SWITCH_PAGE_25_TXSINGLECOLLISION 0x0b002520 /* Tx Single Collision Counter */
#define SWITCH_PAGE_25_TXMULTIPLECOLLISION 0x0b002524 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_25_TXDEFERREDTRANSMIT 0x0b002528 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_25_TXLATECOLLISION 0x0b00252c /* Tx Late Collision Counter */
#define SWITCH_PAGE_25_TXEXCESSIVECOLLISION 0x0b002530 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_25_TXFRAMEINDISC   0x0b002534 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_25_TXPAUSEPKTS     0x0b002538 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_25_TXQPKTQ1        0x0b00253c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_25_TXQPKTQ2        0x0b002540 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_25_TXQPKTQ3        0x0b002544 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_25_TXQPKTQ4        0x0b002548 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_25_TXQPKTQ5        0x0b00254c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_25_RXOCTETS        0x0b002550 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_25_RXUNDERSIZEPKTS 0x0b002558 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_25_RXPAUSEPKTS     0x0b00255c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_25_RXPKTS64OCTETS  0x0b002560 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_25_RXPKTS65TO127OCTETS 0x0b002564 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_25_RXPKTS128TO255OCTETS 0x0b002568 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_25_RXPKTS256TO511OCTETS 0x0b00256c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_25_RXPKTS512TO1023OCTETS 0x0b002570 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_25_RXPKTS1024TOMAXPKTOCTETS 0x0b002574 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_25_RXOVERSIZEPKTS  0x0b002578 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_25_RXJABBERS       0x0b00257c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_25_RXALIGNMENTERRORS 0x0b002580 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_25_RXFCSERRORS     0x0b002584 /* Rx FCS Error Counter */
#define SWITCH_PAGE_25_RXGOODOCTETS    0x0b002588 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_25_RXDROPPKTS      0x0b002590 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_25_RXUNICASTPKTS   0x0b002594 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_25_RXMULTICASTPKTS 0x0b002598 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_25_RXBROADCASTPKTS 0x0b00259c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_25_RXSACHANGES     0x0b0025a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_25_RXFRAGMENTS     0x0b0025a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_25_RXJUMBOPKT      0x0b0025a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_25_RXSYMBLERR      0x0b0025ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_25_INRANGEERRCOUNT 0x0b0025b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_25_OUTRANGEERRCOUNT 0x0b0025b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_25_EEE_LPI_EVENT   0x0b0025b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_25_EEE_LPI_DURATION 0x0b0025bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_25_RXDISCARD       0x0b0025c0 /* Rx Discard Counter */
#define SWITCH_PAGE_25_TXQPKTQ6        0x0b0025c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_25_TXQPKTQ7        0x0b0025cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_25_TXPKTS64OCTETS  0x0b0025d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_25_TXPKTS65TO127OCTETS 0x0b0025d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_25_TXPKTS128TO255OCTETS 0x0b0025d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_25_TXPKTS256TO511OCTETS 0x0b0025dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_25_TXPKTS512TO1023OCTETS 0x0b0025e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_25_TXPKTS1024TOMAXPKTOCTETS 0x0b0025e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_26_TXOCTETS        0x0b002600 /* Tx Octets */
#define SWITCH_PAGE_26_TXDROPPKTS      0x0b002608 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_26_TXQPKTQ0        0x0b00260c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_26_TXBROADCASTPKTS 0x0b002610 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_26_TXMULTICASTPKTS 0x0b002614 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_26_TXUNICASTPKTS   0x0b002618 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_26_TXCOLLISIONS    0x0b00261c /* Tx Collision Counter */
#define SWITCH_PAGE_26_TXSINGLECOLLISION 0x0b002620 /* Tx Single Collision Counter */
#define SWITCH_PAGE_26_TXMULTIPLECOLLISION 0x0b002624 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_26_TXDEFERREDTRANSMIT 0x0b002628 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_26_TXLATECOLLISION 0x0b00262c /* Tx Late Collision Counter */
#define SWITCH_PAGE_26_TXEXCESSIVECOLLISION 0x0b002630 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_26_TXFRAMEINDISC   0x0b002634 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_26_TXPAUSEPKTS     0x0b002638 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_26_TXQPKTQ1        0x0b00263c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_26_TXQPKTQ2        0x0b002640 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_26_TXQPKTQ3        0x0b002644 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_26_TXQPKTQ4        0x0b002648 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_26_TXQPKTQ5        0x0b00264c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_26_RXOCTETS        0x0b002650 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_26_RXUNDERSIZEPKTS 0x0b002658 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_26_RXPAUSEPKTS     0x0b00265c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_26_RXPKTS64OCTETS  0x0b002660 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_26_RXPKTS65TO127OCTETS 0x0b002664 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_26_RXPKTS128TO255OCTETS 0x0b002668 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_26_RXPKTS256TO511OCTETS 0x0b00266c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_26_RXPKTS512TO1023OCTETS 0x0b002670 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_26_RXPKTS1024TOMAXPKTOCTETS 0x0b002674 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_26_RXOVERSIZEPKTS  0x0b002678 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_26_RXJABBERS       0x0b00267c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_26_RXALIGNMENTERRORS 0x0b002680 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_26_RXFCSERRORS     0x0b002684 /* Rx FCS Error Counter */
#define SWITCH_PAGE_26_RXGOODOCTETS    0x0b002688 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_26_RXDROPPKTS      0x0b002690 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_26_RXUNICASTPKTS   0x0b002694 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_26_RXMULTICASTPKTS 0x0b002698 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_26_RXBROADCASTPKTS 0x0b00269c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_26_RXSACHANGES     0x0b0026a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_26_RXFRAGMENTS     0x0b0026a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_26_RXJUMBOPKT      0x0b0026a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_26_RXSYMBLERR      0x0b0026ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_26_INRANGEERRCOUNT 0x0b0026b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_26_OUTRANGEERRCOUNT 0x0b0026b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_26_EEE_LPI_EVENT   0x0b0026b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_26_EEE_LPI_DURATION 0x0b0026bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_26_RXDISCARD       0x0b0026c0 /* Rx Discard Counter */
#define SWITCH_PAGE_26_TXQPKTQ6        0x0b0026c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_26_TXQPKTQ7        0x0b0026cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_26_TXPKTS64OCTETS  0x0b0026d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_26_TXPKTS65TO127OCTETS 0x0b0026d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_26_TXPKTS128TO255OCTETS 0x0b0026d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_26_TXPKTS256TO511OCTETS 0x0b0026dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_26_TXPKTS512TO1023OCTETS 0x0b0026e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_26_TXPKTS1024TOMAXPKTOCTETS 0x0b0026e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_27_TXOCTETS_P7     0x0b002700 /* Tx Octets */
#define SWITCH_PAGE_27_TXDROPPKTS_P7   0x0b002708 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_27_TXQPKTQ0_P7     0x0b00270c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_27_TXBROADCASTPKTS_P7 0x0b002710 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_27_TXMULTICASTPKTS_P7 0x0b002714 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_27_TXUNICASTPKTS_P7 0x0b002718 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_27_TXCOLLISIONS_P7 0x0b00271c /* Tx Collision Counter */
#define SWITCH_PAGE_27_TXSINGLECOLLISION_P7 0x0b002720 /* Tx Single Collision Counter */
#define SWITCH_PAGE_27_TXMULTIPLECOLLISION_P7 0x0b002724 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_27_TXDEFERREDTRANSMIT_P7 0x0b002728 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_27_TXLATECOLLISION_P7 0x0b00272c /* Tx Late Collision Counter */
#define SWITCH_PAGE_27_TXEXCESSIVECOLLISION_P7 0x0b002730 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_27_TXFRAMEINDISC_P7 0x0b002734 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_27_TXPAUSEPKTS_P7  0x0b002738 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_27_TXQPKTQ1_P7     0x0b00273c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_27_TXQPKTQ2_P7     0x0b002740 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_27_TXQPKTQ3_P7     0x0b002744 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_27_TXQPKTQ4_P7     0x0b002748 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_27_TXQPKTQ5_P7     0x0b00274c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_27_RXOCTETS_P7     0x0b002750 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_27_RXUNDERSIZEPKTS_P7 0x0b002758 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_27_RXPAUSEPKTS_P7  0x0b00275c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_27_RXPKTS64OCTETS_P7 0x0b002760 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_27_RXPKTS65TO127OCTETS_P7 0x0b002764 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_27_RXPKTS128TO255OCTETS_P7 0x0b002768 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_27_RXPKTS256TO511OCTETS_P7 0x0b00276c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_27_RXPKTS512TO1023OCTETS_P7 0x0b002770 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7 0x0b002774 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_27_RXOVERSIZEPKTS_P7 0x0b002778 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_27_RXJABBERS_P7    0x0b00277c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_27_RXALIGNMENTERRORS_P7 0x0b002780 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_27_RXFCSERRORS_P7  0x0b002784 /* Rx FCS Error Counter */
#define SWITCH_PAGE_27_RXGOODOCTETS_P7 0x0b002788 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_27_RXDROPPKTS_P7   0x0b002790 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_27_RXUNICASTPKTS_P7 0x0b002794 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_27_RXMULTICASTPKTS_P7 0x0b002798 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_27_RXBROADCASTPKTS_P7 0x0b00279c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_27_RXSACHANGES_P7  0x0b0027a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_27_RXFRAGMENTS_P7  0x0b0027a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_27_RXJUMBOPKT_P7   0x0b0027a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_27_RXSYMBLERR_P7   0x0b0027ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_27_INRANGEERRCOUNT_P7 0x0b0027b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_27_OUTRANGEERRCOUNT_P7 0x0b0027b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_27_EEE_LPI_EVENT_P7 0x0b0027b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_27_EEE_LPI_DURATION_P7 0x0b0027bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_27_RXDISCARD_P7    0x0b0027c0 /* Rx Discard Counter */
#define SWITCH_PAGE_27_TXQPKTQ6_P7     0x0b0027c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_27_TXQPKTQ7_P7     0x0b0027cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_27_TXPKTS64OCTETS_P7 0x0b0027d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_27_TXPKTS65TO127OCTETS_P7 0x0b0027d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_27_TXPKTS128TO255OCTETS_P7 0x0b0027d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_27_TXPKTS256TO511OCTETS_P7 0x0b0027dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_27_TXPKTS512TO1023OCTETS_P7 0x0b0027e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7 0x0b0027e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_28_TXOCTETS_IMP    0x0b002800 /* Tx Octets */
#define SWITCH_PAGE_28_TXDROPPKTS_IMP  0x0b002808 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_28_TXQPKTQ0_IMP    0x0b00280c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_28_TXBROADCASTPKTS_IMP 0x0b002810 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_28_TXMULTICASTPKTS_IMP 0x0b002814 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_28_TXUNICASTPKTS_IMP 0x0b002818 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_28_TXCOLLISIONS_IMP 0x0b00281c /* Tx Collision Counter */
#define SWITCH_PAGE_28_TXSINGLECOLLISION_IMP 0x0b002820 /* Tx Single Collision Counter */
#define SWITCH_PAGE_28_TXMULTIPLECOLLISION_IMP 0x0b002824 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_28_TXDEFERREDTRANSMIT_IMP 0x0b002828 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_28_TXLATECOLLISION_IMP 0x0b00282c /* Tx Late Collision Counter */
#define SWITCH_PAGE_28_TXEXCESSIVECOLLISION_IMP 0x0b002830 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_28_TXFRAMEINDISC_IMP 0x0b002834 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_28_TXPAUSEPKTS_IMP 0x0b002838 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_28_TXQPKTQ1_IMP    0x0b00283c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_28_TXQPKTQ2_IMP    0x0b002840 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_28_TXQPKTQ3_IMP    0x0b002844 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_28_TXQPKTQ4_IMP    0x0b002848 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_28_TXQPKTQ5_IMP    0x0b00284c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_28_RXOCTETS_IMP    0x0b002850 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_28_RXUNDERSIZEPKTS_IMP 0x0b002858 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_28_RXPAUSEPKTS_IMP 0x0b00285c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_28_RXPKTS64OCTETS_IMP 0x0b002860 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_28_RXPKTS65TO127OCTETS_IMP 0x0b002864 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_28_RXPKTS128TO255OCTETS_IMP 0x0b002868 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_28_RXPKTS256TO511OCTETS_IMP 0x0b00286c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_28_RXPKTS512TO1023OCTETS_IMP 0x0b002870 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP 0x0b002874 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_28_RXOVERSIZEPKTS_IMP 0x0b002878 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_28_RXJABBERS_IMP   0x0b00287c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_28_RXALIGNMENTERRORS_IMP 0x0b002880 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_28_RXFCSERRORS_IMP 0x0b002884 /* Rx FCS Error Counter */
#define SWITCH_PAGE_28_RXGOODOCTETS_IMP 0x0b002888 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_28_RXDROPPKTS_IMP  0x0b002890 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_28_RXUNICASTPKTS_IMP 0x0b002894 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_28_RXMULTICASTPKTS_IMP 0x0b002898 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_28_RXBROADCASTPKTS_IMP 0x0b00289c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_28_RXSACHANGES_IMP 0x0b0028a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_28_RXFRAGMENTS_IMP 0x0b0028a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_28_RXJUMBOPKT_IMP  0x0b0028a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_28_RXSYMBLERR_IMP  0x0b0028ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_28_INRANGEERRCOUNT_IMP 0x0b0028b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_28_OUTRANGEERRCOUNT_IMP 0x0b0028b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_28_EEE_LPI_EVENT_IMP 0x0b0028b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_28_EEE_LPI_DURATION_IMP 0x0b0028bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_28_RXDISCARD_IMP   0x0b0028c0 /* Rx Discard Counter */
#define SWITCH_PAGE_28_TXQPKTQ6_IMP    0x0b0028c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_28_TXQPKTQ7_IMP    0x0b0028cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_28_TXPKTS64OCTETS_IMP 0x0b0028d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_28_TXPKTS65TO127OCTETS_IMP 0x0b0028d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_28_TXPKTS128TO255OCTETS_IMP 0x0b0028d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_28_TXPKTS256TO511OCTETS_IMP 0x0b0028dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_28_TXPKTS512TO1023OCTETS_IMP 0x0b0028e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP 0x0b0028e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL 0x0b003000 /* QOS Global Control Register */
#define SWITCH_PAGE_30_QOS_1P_EN       0x0b003004 /* QoS 802.1P Enable Register */
#define SWITCH_PAGE_30_QOS_EN_DIFFSERV 0x0b003006 /* QOS DiffServ Enable Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0 0x0b003010 /* Port N (0 to 6) PCP to TC Map for DEI 0 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1 0x0b003014 /* Port N (0 to 6) PCP to TC Map for DEI 0 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2 0x0b003018 /* Port N (0 to 6) PCP to TC Map for DEI 0 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3 0x0b00301c /* Port N (0 to 6) PCP to TC Map for DEI 0 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4 0x0b003020 /* Port N (0 to 6) PCP to TC Map for DEI 0 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5 0x0b003024 /* Port N (0 to 6) PCP to TC Map for DEI 0 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6 0x0b003028 /* Port N (0 to 6) PCP to TC Map for DEI 0 Register */
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0  0x0b00302c /* Port 7 PCP to TC Map for DEI 0 Register */
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0 0x0b003030 /* Port 8 (IMP) PCP to TC Map for DEI 0 Register */
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0  0x0b003034 /* DiffServ Priority Map 0 Register */
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1  0x0b00303a /* DiffServ Priority Map 1 Register */
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2  0x0b003040 /* DiffServ Priority Map 2 Register */
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3  0x0b003046 /* DiffServ Priority Map 3 Register */
#define SWITCH_PAGE_30_PID2TC          0x0b00304c /* Port ID to TC Map Register */
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0 0x0b003054 /* Port N (0 to 6) TC Select Table Register */
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1 0x0b003056 /* Port N (0 to 6) TC Select Table Register */
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2 0x0b003058 /* Port N (0 to 6) TC Select Table Register */
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3 0x0b00305a /* Port N (0 to 6) TC Select Table Register */
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4 0x0b00305c /* Port N (0 to 6) TC Select Table Register */
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5 0x0b00305e /* Port N (0 to 6) TC Select Table Register */
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6 0x0b003060 /* Port N (0 to 6) TC Select Table Register */
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE 0x0b003062 /* Port 7 TC Select Table Register */
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE 0x0b003064 /* Port 8 TC Select Table Register */
#define SWITCH_PAGE_30_CPU2COS_MAP     0x0b003068 /* CPU to COS Mapping Register */
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0 0x0b003070 /* Port N (0 to 6) TC to COS Mapping Register */
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1 0x0b003074 /* Port N (0 to 6) TC to COS Mapping Register */
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2 0x0b003078 /* Port N (0 to 6) TC to COS Mapping Register */
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3 0x0b00307c /* Port N (0 to 6) TC to COS Mapping Register */
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4 0x0b003080 /* Port N (0 to 6) TC to COS Mapping Register */
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5 0x0b003084 /* Port N (0 to 6) TC to COS Mapping Register */
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6 0x0b003088 /* Port N (0 to 6) TC to COS Mapping Register */
#define SWITCH_PAGE_30_P7_TC2COS_MAP   0x0b00308c /* Port 7 TC to COS Mapping Register */
#define SWITCH_PAGE_30_IMP_TC2COS_MAP  0x0b003090 /* Port 8 TC to COS Mapping Register */
#define SWITCH_PAGE_30_QOS_REG_SPARE0  0x0b0030a8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_30_QOS_REG_SPARE1  0x0b0030ac /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0 0x0b0030b0 /* Port N (0 to 6) PCP to TC Map for DEI 1 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1 0x0b0030b4 /* Port N (0 to 6) PCP to TC Map for DEI 1 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2 0x0b0030b8 /* Port N (0 to 6) PCP to TC Map for DEI 1 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3 0x0b0030bc /* Port N (0 to 6) PCP to TC Map for DEI 1 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4 0x0b0030c0 /* Port N (0 to 6) PCP to TC Map for DEI 1 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5 0x0b0030c4 /* Port N (0 to 6) PCP to TC Map for DEI 1 Register */
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6 0x0b0030c8 /* Port N (0 to 6) PCP to TC Map for DEI 1 Register */
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1  0x0b0030cc /* Port 7 PCP to TC Map for DEI 1 Register */
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1 0x0b0030d0 /* Port 8 (IMP) PCP to TC Map for DEI 1 Register */
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0 0x0b003100 /* PORT N (0 to 6) VLAN Control Register */
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1 0x0b003102 /* PORT N (0 to 6) VLAN Control Register */
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2 0x0b003104 /* PORT N (0 to 6) VLAN Control Register */
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3 0x0b003106 /* PORT N (0 to 6) VLAN Control Register */
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4 0x0b003108 /* PORT N (0 to 6) VLAN Control Register */
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5 0x0b00310a /* PORT N (0 to 6) VLAN Control Register */
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6 0x0b00310c /* PORT N (0 to 6) VLAN Control Register */
#define SWITCH_PAGE_31_PORT_VLAN_CTL_P7 0x0b00310e /* PORT 7 VLAN Control Register */
#define SWITCH_PAGE_31_PORT_VLAN_CTL_IMP 0x0b003110 /* PORT 8 VLAN Control Register */
#define SWITCH_PAGE_31_VLAN_REG_SPARE0 0x0b003120 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_31_VLAN_REG_SPARE1 0x0b003124 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_32_MAC_TRUNK_CTL   0x0b003200 /* MAC Trunk Control Register */
#define SWITCH_PAGE_32_TRUNK_GRP_CTL0  0x0b003210 /* Trunk 0 Group Control Register */
#define SWITCH_PAGE_32_TRUNK_GRP_CTL1  0x0b003212 /* Trunk 1 Group Control Register */
#define SWITCH_PAGE_32_TRUNK_GRP_CTL2  0x0b003214 /* Trunk 2 Group Control Register */
#define SWITCH_PAGE_32_TRUNK_GRP_CTL3  0x0b003216 /* Trunk 3 Group Control Register */
#define SWITCH_PAGE_32_TRUNK_REG_SPARE0 0x0b003220 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_32_TRUNK_REG_SPARE1 0x0b003224 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_34_VLAN_CTRL0      0x0b003400 /* 802.1Q VLAN Control 0 Registers */
#define SWITCH_PAGE_34_VLAN_CTRL1      0x0b003401 /* 802.1Q VLAN Control 1 Registers */
#define SWITCH_PAGE_34_VLAN_CTRL2      0x0b003402 /* 802.1Q VLAN Control 2 Registers */
#define SWITCH_PAGE_34_VLAN_CTRL3      0x0b003403 /* 802.1Q VLAN Control 3 Registers */
#define SWITCH_PAGE_34_VLAN_CTRL4      0x0b003405 /* 802.1Q VLAN Control 4 Registers */
#define SWITCH_PAGE_34_VLAN_CTRL5      0x0b003406 /* 802.1Q VLAN Control 5 Registers */
#define SWITCH_PAGE_34_VLAN_CTRL6      0x0b003407 /* 802.1Q VLAN Control 6 Registers */
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL 0x0b00340a /* VLAN Multiport Address Control Register */
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0 0x0b003410 /* Port N (0 to 6) 802.1Q Default Tag Registers */
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1 0x0b003412 /* Port N (0 to 6) 802.1Q Default Tag Registers */
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2 0x0b003414 /* Port N (0 to 6) 802.1Q Default Tag Registers */
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3 0x0b003416 /* Port N (0 to 6) 802.1Q Default Tag Registers */
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4 0x0b003418 /* Port N (0 to 6) 802.1Q Default Tag Registers */
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5 0x0b00341a /* Port N (0 to 6) 802.1Q Default Tag Registers */
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6 0x0b00341c /* Port N (0 to 6) 802.1Q Default Tag Registers */
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7 0x0b00341e /* Port 7 802.1Q Default Tag Registers */
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP 0x0b003420 /* Port 8 802.1Q Default Tag Registers */
#define SWITCH_PAGE_34_DTAG_TPID       0x0b003430 /* Double Tagging TPID Registers */
#define SWITCH_PAGE_34_ISP_SEL_PORTMAP 0x0b003432 /* ISP Port Selection Portmap Registers */
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS 0x0b003440 /* Egress VID Remarking Table Access Register */
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA 0x0b003444 /* Egress VID Remarking Table Data Register */
#define SWITCH_PAGE_34_JOIN_ALL_VLAN_EN 0x0b003450 /* Join All VLAN Enable Register */
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL 0x0b003452 /* Port IVL or SVL Control Register */
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE0 0x0b003460 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE1 0x0b003464 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_36_DOS_CTRL        0x0b003600 /* DoS Control RegisterRegister */
#define SWITCH_PAGE_36_MINIMUM_TCP_HDR_SZ 0x0b003604 /* Minimum TCP Header Size Register */
#define SWITCH_PAGE_36_MAX_ICMPV4_SIZE_REG 0x0b003608 /* Maximum ICMPv4 Size Register */
#define SWITCH_PAGE_36_MAX_ICMPV6_SIZE_REG 0x0b00360c /* Maximum ICMPv6 Size Register */
#define SWITCH_PAGE_36_DOS_DIS_LRN_REG 0x0b003610 /* DoS Disable Learn Register */
#define SWITCH_PAGE_36_DOS_REG_SPARE0  0x0b003620 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_36_DOS_REG_SPARE1  0x0b003624 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_40_JUMBO_PORT_MASK 0x0b004001 /* Jumbo Frame Port Mask Registers */
#define SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE 0x0b004005 /* Jumbo MIB Good Frame Max Size Registers */
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE0 0x0b004010 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE1 0x0b004014 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_41_COMM_IRC_CON    0x0b004100 /* Common Ingress rate Control Configuration Registers */
#define SWITCH_PAGE_41_IRC_VIRTUAL_ZERO_THD 0x0b004104 /* Ingress Rate Control Virtual Zero Threshold Register (Not2Release) */
#define SWITCH_PAGE_41_IRC_ALARM_THD   0x0b004106 /* Ingress Rate Control Alarm Threshold Register (Not2Release) */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0 0x0b004110 /* Port N (0 to 6) Receive Rate Control Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1 0x0b004114 /* Port N (0 to 6) Receive Rate Control Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2 0x0b004118 /* Port N (0 to 6) Receive Rate Control Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3 0x0b00411c /* Port N (0 to 6) Receive Rate Control Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4 0x0b004120 /* Port N (0 to 6) Receive Rate Control Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5 0x0b004124 /* Port N (0 to 6) Receive Rate Control Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6 0x0b004128 /* Port N (0 to 6) Receive Rate Control Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7 0x0b00412c /* Port 7 Receive Rate Control Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP 0x0b004130 /* Port 8 Receive Rate Control Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0 0x0b004134 /* Port N (0 to 6) Receive Rate Control 1 Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1 0x0b004136 /* Port N (0 to 6) Receive Rate Control 1 Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2 0x0b004138 /* Port N (0 to 6) Receive Rate Control 1 Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3 0x0b00413a /* Port N (0 to 6) Receive Rate Control 1 Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4 0x0b00413c /* Port N (0 to 6) Receive Rate Control 1 Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5 0x0b00413e /* Port N (0 to 6) Receive Rate Control 1 Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6 0x0b004140 /* Port N (0 to 6) Receive Rate Control 1 Registers */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7 0x0b004142 /* Port 7 Receive Rate Control 1 Register */
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP 0x0b004144 /* Port 8 Receive Rate Control 1 Register */
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT0 0x0b004150 /* Port N (0 to 6) Suppressed Packet Drop Counter Register */
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT1 0x0b004154 /* Port N (0 to 6) Suppressed Packet Drop Counter Register */
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT2 0x0b004158 /* Port N (0 to 6) Suppressed Packet Drop Counter Register */
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT3 0x0b00415c /* Port N (0 to 6) Suppressed Packet Drop Counter Register */
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT4 0x0b004160 /* Port N (0 to 6) Suppressed Packet Drop Counter Register */
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT5 0x0b004164 /* Port N (0 to 6) Suppressed Packet Drop Counter Register */
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT6 0x0b004168 /* Port N (0 to 6) Suppressed Packet Drop Counter Register */
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P7 0x0b00416c /* Port 7 Suppressed Packet Drop Counter Register */
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_IMP 0x0b004170 /* Port 8 Suppressed Packet Drop Counter Register */
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE0 0x0b0041d0 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE1 0x0b0041d4 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_42_EAP_GLO_CON     0x0b004200 /* EAP Global Configuration Registers */
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL 0x0b004201 /* EAP Multiport Address Control Register */
#define SWITCH_PAGE_42_EAP_DIP0        0x0b004202 /* EAP Destination IP Registers */
#define SWITCH_PAGE_42_EAP_DIP1        0x0b00420a /* EAP Destination IP Registers */
#define SWITCH_PAGE_42_PORT_EAP_CON_P0 0x0b004220 /* Port 0 EAP Configuration Registers */
#define SWITCH_PAGE_42_PORT_EAP_CON_P1 0x0b004228 /* Port 1 EAP Configuration Registers */
#define SWITCH_PAGE_42_PORT_EAP_CON_P2 0x0b004230 /* Port 2 EAP Configuration Registers */
#define SWITCH_PAGE_42_PORT_EAP_CON_P3 0x0b004238 /* Port 3 EAP Configuration Registers */
#define SWITCH_PAGE_42_PORT_EAP_CON_P4 0x0b004240 /* Port 4 EAP Configuration Registers */
#define SWITCH_PAGE_42_PORT_EAP_CON_P5 0x0b004248 /* Port 5 EAP Configuration Registers */
#define SWITCH_PAGE_42_PORT_EAP_CON_P6 0x0b004250 /* Port 6 EAP Configuration Registers */
#define SWITCH_PAGE_42_PORT_EAP_CON_P7 0x0b004258 /* Port 7 EAP Configuration Registers */
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP 0x0b004260 /* IMP EAP Configuration Registers */
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE0 0x0b004270 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE1 0x0b004274 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_43_MST_CON         0x0b004300 /* MST Control Registers */
#define SWITCH_PAGE_43_MST_AGE         0x0b004302 /* MST Ageing Control Register */
#define SWITCH_PAGE_43_MST_TAB_0       0x0b004310 /* Multiple Spanning Tree Table 0 Enable Registers */
#define SWITCH_PAGE_43_MST_TAB_1       0x0b004314 /* Multiple Spanning Tree Table 1 Enable Registers */
#define SWITCH_PAGE_43_MST_TAB_2       0x0b004318 /* Multiple Spanning Tree Table 2 Enable Registers */
#define SWITCH_PAGE_43_MST_TAB_3       0x0b00431c /* Multiple Spanning Tree Table 3 Enable Registers */
#define SWITCH_PAGE_43_MST_TAB_4       0x0b004320 /* Multiple Spanning Tree Table 0 Enable Registers */
#define SWITCH_PAGE_43_MST_TAB_5       0x0b004324 /* Multiple Spanning Tree Table 5 Enable Registers */
#define SWITCH_PAGE_43_MST_TAB_6       0x0b004328 /* Multiple Spanning Tree Table 6 Enable Registers */
#define SWITCH_PAGE_43_MST_TAB_7       0x0b00432c /* Multiple Spanning Tree Table 0 Enable Registers */
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL 0x0b004350 /* STP Multiport Address Bypass Control Register */
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE0 0x0b004360 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE1 0x0b004364 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_45_SA_LIMIT_ENABLE 0x0b004500 /* SA Limit Enable Register */
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST 0x0b004502 /* SA Learned Counters Reset Register */
#define SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST 0x0b004504 /* SA Over Limit Counters Reset Register */
#define SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL 0x0b004510 /* Total SA Limit Control Register */
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0 0x0b004512 /* Port N (0 to 6) SA Limit Control Register */
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1 0x0b004514 /* Port N (0 to 6) SA Limit Control Register */
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2 0x0b004516 /* Port N (0 to 6) SA Limit Control Register */
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3 0x0b004518 /* Port N (0 to 6) SA Limit Control Register */
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4 0x0b00451a /* Port N (0 to 6) SA Limit Control Register */
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5 0x0b00451c /* Port N (0 to 6) SA Limit Control Register */
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6 0x0b00451e /* Port N (0 to 6) SA Limit Control Register */
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL 0x0b004520 /* Port 7 SA Limit Control Register */
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL 0x0b004522 /* Port 8 SA Limit Control Register */
#define SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR 0x0b004530 /* Total SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0 0x0b004532 /* Port N (0 to 6) SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1 0x0b004534 /* Port N (0 to 6) SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2 0x0b004536 /* Port N (0 to 6) SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3 0x0b004538 /* Port N (0 to 6) SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4 0x0b00453a /* Port N (0 to 6) SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5 0x0b00453c /* Port N (0 to 6) SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6 0x0b00453e /* Port N (0 to 6) SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR 0x0b004540 /* Port 7 SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR 0x0b004542 /* Port 8 SA Learned Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT0 0x0b004550 /* Port N (0 to 6) SA Over Limit Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT1 0x0b004554 /* Port N (0 to 6) SA Over Limit Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT2 0x0b004558 /* Port N (0 to 6) SA Over Limit Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT3 0x0b00455c /* Port N (0 to 6) SA Over Limit Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT4 0x0b004560 /* Port N (0 to 6) SA Over Limit Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT5 0x0b004564 /* Port N (0 to 6) SA Over Limit Counter Register */
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT6 0x0b004568 /* Port N (0 to 6) SA Over Limit Counter Register */
#define SWITCH_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR 0x0b00456c /* Port 7 SA Over Limit Counter Register */
#define SWITCH_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR 0x0b004570 /* Port 8 SA Over Limit Counter Register */
#define SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT 0x0b004574 /* SA Over Limit Actions Config Register */
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE0 0x0b004580 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE1 0x0b004584 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0 0x0b004600 /* "Port N (0 to 6), QOS Priority Control Register" */
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1 0x0b004601 /* "Port N (0 to 6), QOS Priority Control Register" */
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2 0x0b004602 /* "Port N (0 to 6), QOS Priority Control Register" */
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3 0x0b004603 /* "Port N (0 to 6), QOS Priority Control Register" */
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4 0x0b004604 /* "Port N (0 to 6), QOS Priority Control Register" */
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5 0x0b004605 /* "Port N (0 to 6), QOS Priority Control Register" */
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6 0x0b004606 /* "Port N (0 to 6), QOS Priority Control Register" */
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL  0x0b004607 /* "Port 7, QOS Priority Control Register" */
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL 0x0b004608 /* "Port 8, QOS Priority Control Register" */
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0 0x0b004610 /* "Port N (0 to 6), QOS Weight Register" */
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1 0x0b004618 /* "Port N (0 to 6), QOS Weight Register" */
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2 0x0b004620 /* "Port N (0 to 6), QOS Weight Register" */
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3 0x0b004628 /* "Port N (0 to 6), QOS Weight Register" */
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4 0x0b004630 /* "Port N (0 to 6), QOS Weight Register" */
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5 0x0b004638 /* "Port N (0 to 6), QOS Weight Register" */
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6 0x0b004640 /* "Port N (0 to 6), QOS Weight Register" */
#define SWITCH_PAGE_46_P7_QOS_WEIGHT   0x0b004648 /* "Port 7, QOS Weight Register" */
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT  0x0b004650 /* "Port 8, QOS Weight Register" */
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0 0x0b004660 /* "Port N (0 to 6), WDRR Weight-Scaling Penalty Register (Not2Release)" */
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1 0x0b004662 /* "Port N (0 to 6), WDRR Weight-Scaling Penalty Register (Not2Release)" */
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2 0x0b004664 /* "Port N (0 to 6), WDRR Weight-Scaling Penalty Register (Not2Release)" */
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3 0x0b004666 /* "Port N (0 to 6), WDRR Weight-Scaling Penalty Register (Not2Release)" */
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4 0x0b004668 /* "Port N (0 to 6), WDRR Weight-Scaling Penalty Register (Not2Release)" */
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5 0x0b00466a /* "Port N (0 to 6), WDRR Weight-Scaling Penalty Register (Not2Release)" */
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6 0x0b00466c /* "Port N (0 to 6), WDRR Weight-Scaling Penalty Register (Not2Release)" */
#define SWITCH_PAGE_46_P7_WDRR_PENALTY 0x0b004670 /* "Port 7, WDRR Weight-Scaling Penalty Register (Not2Release)" */
#define SWITCH_PAGE_46_P8_WDRR_PENALTY 0x0b004672 /* "Port 8, WDRR Weight-Scaling Penalty Register (Not2Release)" */
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE0 0x0b004680 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE1 0x0b004684 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0 0x0b004700 /* "Port N (0 to 6), Byte-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1 0x0b004704 /* "Port N (0 to 6), Byte-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2 0x0b004708 /* "Port N (0 to 6), Byte-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3 0x0b00470c /* "Port N (0 to 6), Byte-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4 0x0b004710 /* "Port N (0 to 6), Byte-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5 0x0b004714 /* "Port N (0 to 6), Byte-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6 0x0b004718 /* "Port N (0 to 6), Byte-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH 0x0b00471c /* "Port 7, Byte-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH 0x0b004720 /* "Port 8, Byte-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0 0x0b004730 /* "Port N (0 to 6), Byte-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1 0x0b004734 /* "Port N (0 to 6), Byte-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2 0x0b004738 /* "Port N (0 to 6), Byte-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3 0x0b00473c /* "Port N (0 to 6), Byte-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4 0x0b004740 /* "Port N (0 to 6), Byte-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5 0x0b004744 /* "Port N (0 to 6), Byte-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6 0x0b004748 /* "Port N (0 to 6), Byte-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL 0x0b00474c /* "Port 7, Byte-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL 0x0b004750 /* "Port 8, Byte-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0 0x0b004760 /* "Port N (0 to 6), PORT Shaper Status Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1 0x0b004764 /* "Port N (0 to 6), PORT Shaper Status Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2 0x0b004768 /* "Port N (0 to 6), PORT Shaper Status Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3 0x0b00476c /* "Port N (0 to 6), PORT Shaper Status Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4 0x0b004770 /* "Port N (0 to 6), PORT Shaper Status Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5 0x0b004774 /* "Port N (0 to 6), PORT Shaper Status Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6 0x0b004778 /* "Port N (0 to 6), PORT Shaper Status Register" */
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS 0x0b00477c /* "Port 7, PORT Shaper Status Register" */
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS 0x0b004780 /* "Port 8, PORT Shaper Status Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0 0x0b004790 /* "Port N (0 to 6), Packet-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1 0x0b004794 /* "Port N (0 to 6), Packet-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2 0x0b004798 /* "Port N (0 to 6), Packet-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3 0x0b00479c /* "Port N (0 to 6), Packet-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4 0x0b0047a0 /* "Port N (0 to 6), Packet-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5 0x0b0047a4 /* "Port N (0 to 6), Packet-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6 0x0b0047a8 /* "Port N (0 to 6), Packet-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH 0x0b0047ac /* "Port 7, Packet-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH 0x0b0047b0 /* "Port 8, Packet-Based, Port Shaper Shaping Rate Configure Register" */
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0 0x0b0047b8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1 0x0b0047bc /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0 0x0b0047c0 /* "Port N (0 to 6), Packet-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1 0x0b0047c4 /* "Port N (0 to 6), Packet-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2 0x0b0047c8 /* "Port N (0 to 6), Packet-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3 0x0b0047cc /* "Port N (0 to 6), Packet-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4 0x0b0047d0 /* "Port N (0 to 6), Packet-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5 0x0b0047d4 /* "Port N (0 to 6), Packet-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6 0x0b0047d8 /* "Port N (0 to 6), Packet-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL 0x0b0047dc /* "Port 7, Packet-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL 0x0b0047e0 /* "Port 8, Packet-Based, Port Shaper Burst Size Configure Register" */
#define SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE 0x0b0047e4 /* Port Shaper AVB Shaping Mode Control Register */
#define SWITCH_PAGE_47_PORT_SHAPER_ENABLE 0x0b0047e6 /* Port Shaper Enable Register */
#define SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT 0x0b0047e8 /* Port Shaper Bucket Count Select Register */
#define SWITCH_PAGE_47_PORT_SHAPER_BLOCKING 0x0b0047ea /* Port Shaper Blocking Control Register */
#define SWITCH_PAGE_47_IFG_BYTES       0x0b0047ee /* IFG Correction Control Register */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0 0x0b004800 /* "Port N (0 to 6), Byte-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1 0x0b004804 /* "Port N (0 to 6), Byte-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2 0x0b004808 /* "Port N (0 to 6), Byte-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3 0x0b00480c /* "Port N (0 to 6), Byte-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4 0x0b004810 /* "Port N (0 to 6), Byte-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5 0x0b004814 /* "Port N (0 to 6), Byte-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6 0x0b004818 /* "Port N (0 to 6), Byte-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH 0x0b00481c /* "Port 7, Byte-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH 0x0b004820 /* "Port 8, Byte-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0 0x0b004830 /* "Port N (0 to 6), Byte-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1 0x0b004834 /* "Port N (0 to 6), Byte-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2 0x0b004838 /* "Port N (0 to 6), Byte-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3 0x0b00483c /* "Port N (0 to 6), Byte-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4 0x0b004840 /* "Port N (0 to 6), Byte-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5 0x0b004844 /* "Port N (0 to 6), Byte-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6 0x0b004848 /* "Port N (0 to 6), Byte-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL 0x0b00484c /* "Port 7, Byte-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL 0x0b004850 /* "Port 8, Byte-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0 0x0b004860 /* "Port N (0 to 6), Queue 0 Shaper Status Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1 0x0b004864 /* "Port N (0 to 6), Queue 0 Shaper Status Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2 0x0b004868 /* "Port N (0 to 6), Queue 0 Shaper Status Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3 0x0b00486c /* "Port N (0 to 6), Queue 0 Shaper Status Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4 0x0b004870 /* "Port N (0 to 6), Queue 0 Shaper Status Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5 0x0b004874 /* "Port N (0 to 6), Queue 0 Shaper Status Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6 0x0b004878 /* "Port N (0 to 6), Queue 0 Shaper Status Register" */
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS 0x0b00487c /* "Port 7, Queue 0 Shaper Status Register" */
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS 0x0b004880 /* "Port 8, Queue 0 Shaper Status Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0 0x0b004890 /* "Port N (0 to 6), Packet-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1 0x0b004894 /* "Port N (0 to 6), Packet-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2 0x0b004898 /* "Port N (0 to 6), Packet-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3 0x0b00489c /* "Port N (0 to 6), Packet-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4 0x0b0048a0 /* "Port N (0 to 6), Packet-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5 0x0b0048a4 /* "Port N (0 to 6), Packet-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6 0x0b0048a8 /* "Port N (0 to 6), Packet-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH 0x0b0048ac /* "Port 7, Packet-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH 0x0b0048b0 /* "Port 8, Packet-based Queue 0 Shaping Rate Configure Register" */
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 0x0b0048b8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 0x0b0048bc /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0 0x0b0048c0 /* "Port N (0 to 6), Packet-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1 0x0b0048c4 /* "Port N (0 to 6), Packet-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2 0x0b0048c8 /* "Port N (0 to 6), Packet-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3 0x0b0048cc /* "Port N (0 to 6), Packet-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4 0x0b0048d0 /* "Port N (0 to 6), Packet-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5 0x0b0048d4 /* "Port N (0 to 6), Packet-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6 0x0b0048d8 /* "Port N (0 to 6), Packet-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL 0x0b0048dc /* "Port 7, Packet-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL 0x0b0048e0 /* "Port 8, Packet-based Queue 0 Burst Size Configure Register" */
#define SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE 0x0b0048e4 /* Queue 0 AVB Shaping Mode Control Register */
#define SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE 0x0b0048e6 /* Queue 0 Shaper Enable Register */
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT 0x0b0048e8 /* Queue 0 Bucket Count Select Register */
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING 0x0b0048ea /* Queue 0 Shaper Blocking Control Register */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0 0x0b004900 /* "Port N (0 to 6), Byte-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1 0x0b004904 /* "Port N (0 to 6), Byte-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2 0x0b004908 /* "Port N (0 to 6), Byte-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3 0x0b00490c /* "Port N (0 to 6), Byte-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4 0x0b004910 /* "Port N (0 to 6), Byte-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5 0x0b004914 /* "Port N (0 to 6), Byte-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6 0x0b004918 /* "Port N (0 to 6), Byte-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH 0x0b00491c /* "Port 7, Byte-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH 0x0b004920 /* "Port 8, Byte-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0 0x0b004930 /* "Port N (0 to 6), Byte-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1 0x0b004934 /* "Port N (0 to 6), Byte-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2 0x0b004938 /* "Port N (0 to 6), Byte-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3 0x0b00493c /* "Port N (0 to 6), Byte-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4 0x0b004940 /* "Port N (0 to 6), Byte-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5 0x0b004944 /* "Port N (0 to 6), Byte-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6 0x0b004948 /* "Port N (0 to 6), Byte-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL 0x0b00494c /* "Port 7, Byte-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL 0x0b004950 /* "Port 8, Byte-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0 0x0b004960 /* "Port N (0 to 6), Queue 1 Shaper Status Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1 0x0b004964 /* "Port N (0 to 6), Queue 1 Shaper Status Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2 0x0b004968 /* "Port N (0 to 6), Queue 1 Shaper Status Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3 0x0b00496c /* "Port N (0 to 6), Queue 1 Shaper Status Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4 0x0b004970 /* "Port N (0 to 6), Queue 1 Shaper Status Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5 0x0b004974 /* "Port N (0 to 6), Queue 1 Shaper Status Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6 0x0b004978 /* "Port N (0 to 6), Queue 1 Shaper Status Register" */
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS 0x0b00497c /* "Port 7, Queue 1 Shaper Status Register" */
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS 0x0b004980 /* "Port 8, Queue 1 Shaper Status Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0 0x0b004990 /* "Port N (0 to 6), Packet-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1 0x0b004994 /* "Port N (0 to 6), Packet-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2 0x0b004998 /* "Port N (0 to 6), Packet-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3 0x0b00499c /* "Port N (0 to 6), Packet-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4 0x0b0049a0 /* "Port N (0 to 6), Packet-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5 0x0b0049a4 /* "Port N (0 to 6), Packet-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6 0x0b0049a8 /* "Port N (0 to 6), Packet-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH 0x0b0049ac /* "Port 7, Packet-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH 0x0b0049b0 /* "Port 8, Packet-based Queue 1 Shaping Rate Configure Register" */
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 0x0b0049b8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 0x0b0049bc /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0 0x0b0049c0 /* "Port N (0 to 6), Packet-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1 0x0b0049c4 /* "Port N (0 to 6), Packet-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2 0x0b0049c8 /* "Port N (0 to 6), Packet-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3 0x0b0049cc /* "Port N (0 to 6), Packet-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4 0x0b0049d0 /* "Port N (0 to 6), Packet-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5 0x0b0049d4 /* "Port N (0 to 6), Packet-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6 0x0b0049d8 /* "Port N (0 to 6), Packet-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL 0x0b0049dc /* "Port 7, Packet-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL 0x0b0049e0 /* "Port 8, Packet-based Queue 1 Burst Size Configure Register" */
#define SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE 0x0b0049e4 /* Queue 1 AVB Shaping Mode Control Register */
#define SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE 0x0b0049e6 /* Queue 1 Shaper Enable Register */
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT 0x0b0049e8 /* Queue 1 Bucket Count Select Register */
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING 0x0b0049ea /* Queue 1 Shaper Blocking Control Register */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0 0x0b004a00 /* "Port N (0 to 6), Byte-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1 0x0b004a04 /* "Port N (0 to 6), Byte-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2 0x0b004a08 /* "Port N (0 to 6), Byte-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3 0x0b004a0c /* "Port N (0 to 6), Byte-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4 0x0b004a10 /* "Port N (0 to 6), Byte-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5 0x0b004a14 /* "Port N (0 to 6), Byte-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6 0x0b004a18 /* "Port N (0 to 6), Byte-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH 0x0b004a1c /* "Port 7, Byte-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH 0x0b004a20 /* "Port 8, Byte-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0 0x0b004a30 /* "Port N (0 to 6), Byte-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1 0x0b004a34 /* "Port N (0 to 6), Byte-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2 0x0b004a38 /* "Port N (0 to 6), Byte-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3 0x0b004a3c /* "Port N (0 to 6), Byte-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4 0x0b004a40 /* "Port N (0 to 6), Byte-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5 0x0b004a44 /* "Port N (0 to 6), Byte-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6 0x0b004a48 /* "Port N (0 to 6), Byte-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL 0x0b004a4c /* "Port 7, Byte-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL 0x0b004a50 /* "Port 8, Byte-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0 0x0b004a60 /* "Port N (0 to 6), Queue 2 Shaper Status Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1 0x0b004a64 /* "Port N (0 to 6), Queue 2 Shaper Status Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2 0x0b004a68 /* "Port N (0 to 6), Queue 2 Shaper Status Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3 0x0b004a6c /* "Port N (0 to 6), Queue 2 Shaper Status Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4 0x0b004a70 /* "Port N (0 to 6), Queue 2 Shaper Status Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5 0x0b004a74 /* "Port N (0 to 6), Queue 2 Shaper Status Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6 0x0b004a78 /* "Port N (0 to 6), Queue 2 Shaper Status Register" */
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS 0x0b004a7c /* "Port 7, Queue 2 Shaper Status Register" */
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS 0x0b004a80 /* "Port 8, Queue 2 Shaper Status Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0 0x0b004a90 /* "Port N (0 to 6), Packet-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1 0x0b004a94 /* "Port N (0 to 6), Packet-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2 0x0b004a98 /* "Port N (0 to 6), Packet-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3 0x0b004a9c /* "Port N (0 to 6), Packet-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4 0x0b004aa0 /* "Port N (0 to 6), Packet-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5 0x0b004aa4 /* "Port N (0 to 6), Packet-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6 0x0b004aa8 /* "Port N (0 to 6), Packet-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH 0x0b004aac /* "Port 7, Packet-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH 0x0b004ab0 /* "Port 8, Packet-based Queue 2 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 0x0b004ab8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 0x0b004abc /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0 0x0b004ac0 /* "Port N (0 to 6), Packet-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1 0x0b004ac4 /* "Port N (0 to 6), Packet-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2 0x0b004ac8 /* "Port N (0 to 6), Packet-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3 0x0b004acc /* "Port N (0 to 6), Packet-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4 0x0b004ad0 /* "Port N (0 to 6), Packet-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5 0x0b004ad4 /* "Port N (0 to 6), Packet-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6 0x0b004ad8 /* "Port N (0 to 6), Packet-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL 0x0b004adc /* "Port 7, Packet-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL 0x0b004ae0 /* "Port 8, Packet-based Queue 2 Burst Size Configure Register" */
#define SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE 0x0b004ae4 /* Queue 2 AVB Shaping Mode Control Register */
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE 0x0b004ae6 /* Queue 2 Shaper Enable Register */
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT 0x0b004ae8 /* Queue 2 Bucket Count Select Register */
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING 0x0b004aea /* Queue 2 Shaper Blocking Control Register */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0 0x0b004b00 /* "Port N (0 to 6), Byte-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1 0x0b004b04 /* "Port N (0 to 6), Byte-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2 0x0b004b08 /* "Port N (0 to 6), Byte-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3 0x0b004b0c /* "Port N (0 to 6), Byte-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4 0x0b004b10 /* "Port N (0 to 6), Byte-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5 0x0b004b14 /* "Port N (0 to 6), Byte-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6 0x0b004b18 /* "Port N (0 to 6), Byte-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH 0x0b004b1c /* "Port 7, Byte-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH 0x0b004b20 /* "Port 8, Byte-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0 0x0b004b30 /* "Port N (0 to 6), Byte-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1 0x0b004b34 /* "Port N (0 to 6), Byte-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2 0x0b004b38 /* "Port N (0 to 6), Byte-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3 0x0b004b3c /* "Port N (0 to 6), Byte-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4 0x0b004b40 /* "Port N (0 to 6), Byte-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5 0x0b004b44 /* "Port N (0 to 6), Byte-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6 0x0b004b48 /* "Port N (0 to 6), Byte-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL 0x0b004b4c /* "Port 7, Byte-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL 0x0b004b50 /* "Port 8, Byte-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0 0x0b004b60 /* "Port N (0 to 6), Queue 3 Shaper Status Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1 0x0b004b64 /* "Port N (0 to 6), Queue 3 Shaper Status Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2 0x0b004b68 /* "Port N (0 to 6), Queue 3 Shaper Status Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3 0x0b004b6c /* "Port N (0 to 6), Queue 3 Shaper Status Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4 0x0b004b70 /* "Port N (0 to 6), Queue 3 Shaper Status Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5 0x0b004b74 /* "Port N (0 to 6), Queue 3 Shaper Status Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6 0x0b004b78 /* "Port N (0 to 6), Queue 3 Shaper Status Register" */
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS 0x0b004b7c /* "Port 7, Queue 3 Shaper Status Register" */
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS 0x0b004b80 /* "Port 8, Queue 3 Shaper Status Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0 0x0b004b90 /* "Port N (0 to 6), Packet-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1 0x0b004b94 /* "Port N (0 to 6), Packet-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2 0x0b004b98 /* "Port N (0 to 6), Packet-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3 0x0b004b9c /* "Port N (0 to 6), Packet-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4 0x0b004ba0 /* "Port N (0 to 6), Packet-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5 0x0b004ba4 /* "Port N (0 to 6), Packet-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6 0x0b004ba8 /* "Port N (0 to 6), Packet-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH 0x0b004bac /* "Port 7, Packet-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH 0x0b004bb0 /* "Port 8, Packet-based Queue 3 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 0x0b004bb8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 0x0b004bbc /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0 0x0b004bc0 /* "Port N (0 to 6), Packet-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1 0x0b004bc4 /* "Port N (0 to 6), Packet-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2 0x0b004bc8 /* "Port N (0 to 6), Packet-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3 0x0b004bcc /* "Port N (0 to 6), Packet-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4 0x0b004bd0 /* "Port N (0 to 6), Packet-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5 0x0b004bd4 /* "Port N (0 to 6), Packet-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6 0x0b004bd8 /* "Port N (0 to 6), Packet-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL 0x0b004bdc /* "Port 7, Packet-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL 0x0b004be0 /* "Port 8, Packet-based Queue 3 Burst Size Configure Register" */
#define SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE 0x0b004be4 /* Queue 3 AVB Shaping Mode Control Register */
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE 0x0b004be6 /* Queue 3 Shaper Enable Register */
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT 0x0b004be8 /* Queue 3 Bucket Count Select Register */
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING 0x0b004bea /* Queue 3 Shaper Blocking Control Register */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0 0x0b004c00 /* "Port N (0 to 6), Byte-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1 0x0b004c04 /* "Port N (0 to 6), Byte-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2 0x0b004c08 /* "Port N (0 to 6), Byte-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3 0x0b004c0c /* "Port N (0 to 6), Byte-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4 0x0b004c10 /* "Port N (0 to 6), Byte-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5 0x0b004c14 /* "Port N (0 to 6), Byte-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6 0x0b004c18 /* "Port N (0 to 6), Byte-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH 0x0b004c1c /* "Port 7, Byte-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH 0x0b004c20 /* "Port 8, Byte-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0 0x0b004c30 /* "Port N (0 to 6), Byte-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1 0x0b004c34 /* "Port N (0 to 6), Byte-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2 0x0b004c38 /* "Port N (0 to 6), Byte-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3 0x0b004c3c /* "Port N (0 to 6), Byte-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4 0x0b004c40 /* "Port N (0 to 6), Byte-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5 0x0b004c44 /* "Port N (0 to 6), Byte-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6 0x0b004c48 /* "Port N (0 to 6), Byte-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL 0x0b004c4c /* "Port 7, Byte-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL 0x0b004c50 /* "Port 8, Byte-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0 0x0b004c60 /* "Port N (0 to 6), Queue 4 Shaper Status Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1 0x0b004c64 /* "Port N (0 to 6), Queue 4 Shaper Status Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2 0x0b004c68 /* "Port N (0 to 6), Queue 4 Shaper Status Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3 0x0b004c6c /* "Port N (0 to 6), Queue 4 Shaper Status Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4 0x0b004c70 /* "Port N (0 to 6), Queue 4 Shaper Status Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5 0x0b004c74 /* "Port N (0 to 6), Queue 4 Shaper Status Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6 0x0b004c78 /* "Port N (0 to 6), Queue 4 Shaper Status Register" */
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS 0x0b004c7c /* "Port 7, Queue 4 Shaper Status Register" */
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS 0x0b004c80 /* "Port 8, Queue 4 Shaper Status Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0 0x0b004c90 /* "Port N (0 to 6), Packet-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1 0x0b004c94 /* "Port N (0 to 6), Packet-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2 0x0b004c98 /* "Port N (0 to 6), Packet-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3 0x0b004c9c /* "Port N (0 to 6), Packet-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4 0x0b004ca0 /* "Port N (0 to 6), Packet-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5 0x0b004ca4 /* "Port N (0 to 6), Packet-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6 0x0b004ca8 /* "Port N (0 to 6), Packet-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH 0x0b004cac /* "Port 7, Packet-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH 0x0b004cb0 /* "Port 8, Packet-based Queue 4 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 0x0b004cb8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 0x0b004cbc /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0 0x0b004cc0 /* "Port N (0 to 6), Packet-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1 0x0b004cc4 /* "Port N (0 to 6), Packet-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2 0x0b004cc8 /* "Port N (0 to 6), Packet-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3 0x0b004ccc /* "Port N (0 to 6), Packet-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4 0x0b004cd0 /* "Port N (0 to 6), Packet-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5 0x0b004cd4 /* "Port N (0 to 6), Packet-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6 0x0b004cd8 /* "Port N (0 to 6), Packet-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL 0x0b004cdc /* "Port 7, Packet-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL 0x0b004ce0 /* "Port 8, Packet-based Queue 4 Burst Size Configure Register" */
#define SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE 0x0b004ce4 /* Queue 4 AVB Shaping Mode Control Register */
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE 0x0b004ce6 /* Queue 4 Shaper Enable Register */
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT 0x0b004ce8 /* Queue 4 Bucket Count Select Register */
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING 0x0b004cea /* Queue 4 Shaper Blocking Control Register */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0 0x0b004d00 /* "Port N (0 to 6), Byte-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1 0x0b004d04 /* "Port N (0 to 6), Byte-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2 0x0b004d08 /* "Port N (0 to 6), Byte-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3 0x0b004d0c /* "Port N (0 to 6), Byte-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4 0x0b004d10 /* "Port N (0 to 6), Byte-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5 0x0b004d14 /* "Port N (0 to 6), Byte-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6 0x0b004d18 /* "Port N (0 to 6), Byte-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH 0x0b004d1c /* "Port 7, Byte-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH 0x0b004d20 /* "Port 8, Byte-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0 0x0b004d30 /* "Port N (0 to 6), Byte-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1 0x0b004d34 /* "Port N (0 to 6), Byte-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2 0x0b004d38 /* "Port N (0 to 6), Byte-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3 0x0b004d3c /* "Port N (0 to 6), Byte-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4 0x0b004d40 /* "Port N (0 to 6), Byte-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5 0x0b004d44 /* "Port N (0 to 6), Byte-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6 0x0b004d48 /* "Port N (0 to 6), Byte-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL 0x0b004d4c /* "Port 7, Byte-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL 0x0b004d50 /* "Port 8, Byte-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0 0x0b004d60 /* "Port N (0 to 6), Queue 5 Shaper Status Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1 0x0b004d64 /* "Port N (0 to 6), Queue 5 Shaper Status Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2 0x0b004d68 /* "Port N (0 to 6), Queue 5 Shaper Status Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3 0x0b004d6c /* "Port N (0 to 6), Queue 5 Shaper Status Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4 0x0b004d70 /* "Port N (0 to 6), Queue 5 Shaper Status Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5 0x0b004d74 /* "Port N (0 to 6), Queue 5 Shaper Status Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6 0x0b004d78 /* "Port N (0 to 6), Queue 5 Shaper Status Register" */
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS 0x0b004d7c /* "Port 7, Queue 5 Shaper Status Register" */
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS 0x0b004d80 /* "Port 8, Queue 5 Shaper Status Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0 0x0b004d90 /* "Port N (0 to 6), Packet-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1 0x0b004d94 /* "Port N (0 to 6), Packet-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2 0x0b004d98 /* "Port N (0 to 6), Packet-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3 0x0b004d9c /* "Port N (0 to 6), Packet-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4 0x0b004da0 /* "Port N (0 to 6), Packet-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5 0x0b004da4 /* "Port N (0 to 6), Packet-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6 0x0b004da8 /* "Port N (0 to 6), Packet-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH 0x0b004dac /* "Port 7, Packet-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH 0x0b004db0 /* "Port 8, Packet-based Queue 5 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 0x0b004db8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 0x0b004dbc /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0 0x0b004dc0 /* "Port N (0 to 6), Packet-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1 0x0b004dc4 /* "Port N (0 to 6), Packet-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2 0x0b004dc8 /* "Port N (0 to 6), Packet-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3 0x0b004dcc /* "Port N (0 to 6), Packet-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4 0x0b004dd0 /* "Port N (0 to 6), Packet-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5 0x0b004dd4 /* "Port N (0 to 6), Packet-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6 0x0b004dd8 /* "Port N (0 to 6), Packet-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL 0x0b004ddc /* "Port 7, Packet-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL 0x0b004de0 /* "Port 8, Packet-based Queue 5 Burst Size Configure Register" */
#define SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE 0x0b004de4 /* Queue 5 AVB Shaping Mode Control Register */
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE 0x0b004de6 /* Queue 5 Shaper Enable Register */
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT 0x0b004de8 /* Queue 5 Bucket Count Select Register */
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING 0x0b004dea /* Queue 5 Shaper Blocking Control Register */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0 0x0b004e00 /* "Port N (0 to 6), Byte-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1 0x0b004e04 /* "Port N (0 to 6), Byte-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2 0x0b004e08 /* "Port N (0 to 6), Byte-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3 0x0b004e0c /* "Port N (0 to 6), Byte-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4 0x0b004e10 /* "Port N (0 to 6), Byte-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5 0x0b004e14 /* "Port N (0 to 6), Byte-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6 0x0b004e18 /* "Port N (0 to 6), Byte-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH 0x0b004e1c /* "Port 7, Byte-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH 0x0b004e20 /* "Port 8, Byte-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0 0x0b004e30 /* "Port N (0 to 6), Byte-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1 0x0b004e34 /* "Port N (0 to 6), Byte-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2 0x0b004e38 /* "Port N (0 to 6), Byte-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3 0x0b004e3c /* "Port N (0 to 6), Byte-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4 0x0b004e40 /* "Port N (0 to 6), Byte-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5 0x0b004e44 /* "Port N (0 to 6), Byte-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6 0x0b004e48 /* "Port N (0 to 6), Byte-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL 0x0b004e4c /* "Port 7, Byte-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL 0x0b004e50 /* "Port 8, Byte-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0 0x0b004e60 /* "Port N (0 to 6), Queue 6 Shaper Status Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1 0x0b004e64 /* "Port N (0 to 6), Queue 6 Shaper Status Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2 0x0b004e68 /* "Port N (0 to 6), Queue 6 Shaper Status Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3 0x0b004e6c /* "Port N (0 to 6), Queue 6 Shaper Status Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4 0x0b004e70 /* "Port N (0 to 6), Queue 6 Shaper Status Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5 0x0b004e74 /* "Port N (0 to 6), Queue 6 Shaper Status Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6 0x0b004e78 /* "Port N (0 to 6), Queue 6 Shaper Status Register" */
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS 0x0b004e7c /* "Port 7, Queue 6 Shaper Status Register" */
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS 0x0b004e80 /* "Port 8, Queue 6 Shaper Status Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0 0x0b004e90 /* "Port N (0 to 6), Packet-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1 0x0b004e94 /* "Port N (0 to 6), Packet-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2 0x0b004e98 /* "Port N (0 to 6), Packet-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3 0x0b004e9c /* "Port N (0 to 6), Packet-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4 0x0b004ea0 /* "Port N (0 to 6), Packet-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5 0x0b004ea4 /* "Port N (0 to 6), Packet-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6 0x0b004ea8 /* "Port N (0 to 6), Packet-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH 0x0b004eac /* "Port 7, Packet-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH 0x0b004eb0 /* "Port 8, Packet-based Queue 6 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 0x0b004eb8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 0x0b004ebc /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0 0x0b004ec0 /* "Port N (0 to 6), Packet-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1 0x0b004ec4 /* "Port N (0 to 6), Packet-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2 0x0b004ec8 /* "Port N (0 to 6), Packet-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3 0x0b004ecc /* "Port N (0 to 6), Packet-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4 0x0b004ed0 /* "Port N (0 to 6), Packet-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5 0x0b004ed4 /* "Port N (0 to 6), Packet-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6 0x0b004ed8 /* "Port N (0 to 6), Packet-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL 0x0b004edc /* "Port 7, Packet-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL 0x0b004ee0 /* "Port 8, Packet-based Queue 6 Burst Size Configure Register" */
#define SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE 0x0b004ee4 /* Queue 6 AVB Shaping Mode Control Register */
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE 0x0b004ee6 /* Queue 6 Shaper Enable Register */
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT 0x0b004ee8 /* Queue 6 Bucket Count Select Register */
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING 0x0b004eea /* Queue 6 Shaper Blocking Control Register */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0 0x0b004f00 /* "Port N (0 to 6), Byte-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1 0x0b004f04 /* "Port N (0 to 6), Byte-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2 0x0b004f08 /* "Port N (0 to 6), Byte-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3 0x0b004f0c /* "Port N (0 to 6), Byte-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4 0x0b004f10 /* "Port N (0 to 6), Byte-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5 0x0b004f14 /* "Port N (0 to 6), Byte-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6 0x0b004f18 /* "Port N (0 to 6), Byte-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH 0x0b004f1c /* "Port 7, Byte-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH 0x0b004f20 /* "Port 8, Byte-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0 0x0b004f30 /* "Port N (0 to 6), Byte-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1 0x0b004f34 /* "Port N (0 to 6), Byte-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2 0x0b004f38 /* "Port N (0 to 6), Byte-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3 0x0b004f3c /* "Port N (0 to 6), Byte-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4 0x0b004f40 /* "Port N (0 to 6), Byte-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5 0x0b004f44 /* "Port N (0 to 6), Byte-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6 0x0b004f48 /* "Port N (0 to 6), Byte-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL 0x0b004f4c /* "Port 7, Byte-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL 0x0b004f50 /* "Port 8, Byte-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0 0x0b004f60 /* "Port N (0 to 6), Queue 7 Shaper Status Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1 0x0b004f64 /* "Port N (0 to 6), Queue 7 Shaper Status Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2 0x0b004f68 /* "Port N (0 to 6), Queue 7 Shaper Status Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3 0x0b004f6c /* "Port N (0 to 6), Queue 7 Shaper Status Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4 0x0b004f70 /* "Port N (0 to 6), Queue 7 Shaper Status Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5 0x0b004f74 /* "Port N (0 to 6), Queue 7 Shaper Status Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6 0x0b004f78 /* "Port N (0 to 6), Queue 7 Shaper Status Register" */
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS 0x0b004f7c /* "Port 7, Queue 7 Shaper Status Register" */
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS 0x0b004f80 /* "Port 8, Queue 7 Shaper Status Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0 0x0b004f90 /* "Port N (0 to 6), Packet-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1 0x0b004f94 /* "Port N (0 to 6), Packet-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2 0x0b004f98 /* "Port N (0 to 6), Packet-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3 0x0b004f9c /* "Port N (0 to 6), Packet-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4 0x0b004fa0 /* "Port N (0 to 6), Packet-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5 0x0b004fa4 /* "Port N (0 to 6), Packet-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6 0x0b004fa8 /* "Port N (0 to 6), Packet-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH 0x0b004fac /* "Port 7, Packet-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH 0x0b004fb0 /* "Port 8, Packet-based Queue 7 Shaping Rate Configure Register" */
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 0x0b004fb8 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 0x0b004fbc /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0 0x0b004fc0 /* "Port N (0 to 6), Packet-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1 0x0b004fc4 /* "Port N (0 to 6), Packet-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2 0x0b004fc8 /* "Port N (0 to 6), Packet-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3 0x0b004fcc /* "Port N (0 to 6), Packet-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4 0x0b004fd0 /* "Port N (0 to 6), Packet-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5 0x0b004fd4 /* "Port N (0 to 6), Packet-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6 0x0b004fd8 /* "Port N (0 to 6), Packet-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL 0x0b004fdc /* "Port 7, Packet-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL 0x0b004fe0 /* "Port 8, Packet-based Queue 7 Burst Size Configure Register" */
#define SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE 0x0b004fe4 /* Queue 7 AVB Shaping Mode Control Register */
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE 0x0b004fe6 /* Queue 7 Shaper Enable Register */
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT 0x0b004fe8 /* Queue 7 Bucket Count Select Register */
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING 0x0b004fea /* Queue 7 Shaper Blocking Control Register */
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL 0x0b007000 /* MIB Snapshot Control Register */
#define SWITCH_PAGE_71_S_TXOCTETS      0x0b007100 /* Tx Octets */
#define SWITCH_PAGE_71_S_TXDROPPKTS    0x0b007108 /* Tx Drop Packet Counter */
#define SWITCH_PAGE_71_S_TXQPKTQ0      0x0b00710c /* Tx Q0 Packet Counter */
#define SWITCH_PAGE_71_S_TXBROADCASTPKTS 0x0b007110 /* Tx Broadcast Packet Counter */
#define SWITCH_PAGE_71_S_TXMULTICASTPKTS 0x0b007114 /* Tx Multicast Packet Counter */
#define SWITCH_PAGE_71_S_TXUNICASTPKTS 0x0b007118 /* Tx Unicast Packet Counter */
#define SWITCH_PAGE_71_S_TXCOLLISIONS  0x0b00711c /* Tx Collision Counter */
#define SWITCH_PAGE_71_S_TXSINGLECOLLISION 0x0b007120 /* Tx Single Collision Counter */
#define SWITCH_PAGE_71_S_TXMULTIPLECOLLISION 0x0b007124 /* Tx Multiple collsion Counter */
#define SWITCH_PAGE_71_S_TXDEFERREDTRANSMIT 0x0b007128 /* Tx Deferred Transmit Counter */
#define SWITCH_PAGE_71_S_TXLATECOLLISION 0x0b00712c /* Tx Late Collision Counter */
#define SWITCH_PAGE_71_S_TXEXCESSIVECOLLISION 0x0b007130 /* Tx Excessive Collision Counter */
#define SWITCH_PAGE_71_S_TXFRAMEINDISC 0x0b007134 /* Tx Fram IN Disc Counter */
#define SWITCH_PAGE_71_S_TXPAUSEPKTS   0x0b007138 /* Tx Pause Packet Counter */
#define SWITCH_PAGE_71_S_TXQPKTQ1      0x0b00713c /* Tx Q1 Packet Counter */
#define SWITCH_PAGE_71_S_TXQPKTQ2      0x0b007140 /* Tx Q2 Packet Counter */
#define SWITCH_PAGE_71_S_TXQPKTQ3      0x0b007144 /* Tx Q3 Packet Counter */
#define SWITCH_PAGE_71_S_TXQPKTQ4      0x0b007148 /* Tx Q4 Packet Counter */
#define SWITCH_PAGE_71_S_TXQPKTQ5      0x0b00714c /* Tx Q5 Packet Counter */
#define SWITCH_PAGE_71_S_RXOCTETS      0x0b007150 /* Rx Packet Octets Counter */
#define SWITCH_PAGE_71_S_RXUNDERSIZEPKTS 0x0b007158 /* Rx Under Size Packet Octets Counter */
#define SWITCH_PAGE_71_S_RXPAUSEPKTS   0x0b00715c /* Rx Pause Packet Counter */
#define SWITCH_PAGE_71_S_RXPKTS64OCTETS 0x0b007160 /* Rx 64 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_RXPKTS65TO127OCTETS 0x0b007164 /* Rx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_RXPKTS128TO255OCTETS 0x0b007168 /* Rx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_RXPKTS256TO511OCTETS 0x0b00716c /* Rx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_RXPKTS512TO1023OCTETS 0x0b007170 /* Rx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS 0x0b007174 /* Rx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_71_S_RXOVERSIZEPKTS 0x0b007178 /* Rx Over Size Packet Counter */
#define SWITCH_PAGE_71_S_RXJABBERS     0x0b00717c /* Rx Jabber Packet Counter */
#define SWITCH_PAGE_71_S_RXALIGNMENTERRORS 0x0b007180 /* Rx Alignment Error Counter */
#define SWITCH_PAGE_71_S_RXFCSERRORS   0x0b007184 /* Rx FCS Error Counter */
#define SWITCH_PAGE_71_S_RXGOODOCTETS  0x0b007188 /* Rx Good Packet Octet Counter */
#define SWITCH_PAGE_71_S_RXDROPPKTS    0x0b007190 /* Rx Drop Packet Counter */
#define SWITCH_PAGE_71_S_RXUNICASTPKTS 0x0b007194 /* Rx Unicast Packet Counter */
#define SWITCH_PAGE_71_S_RXMULTICASTPKTS 0x0b007198 /* Rx Multicast Packet Counter */
#define SWITCH_PAGE_71_S_RXBROADCASTPKTS 0x0b00719c /* Rx Broadcast Packet Counter */
#define SWITCH_PAGE_71_S_RXSACHANGES   0x0b0071a0 /* Rx SA Change Counter */
#define SWITCH_PAGE_71_S_RXFRAGMENTS   0x0b0071a4 /* Rx Fragment Counter */
#define SWITCH_PAGE_71_S_RXJUMBOPKT    0x0b0071a8 /* Jumbo Packet Counter */
#define SWITCH_PAGE_71_S_RXSYMBLERR    0x0b0071ac /* Rx Symbol Error Counter */
#define SWITCH_PAGE_71_S_INRANGEERRCOUNT 0x0b0071b0 /* InRangeErrCount Counter */
#define SWITCH_PAGE_71_S_OUTRANGEERRCOUNT 0x0b0071b4 /* OutRangeErrCount Counter */
#define SWITCH_PAGE_71_S_EEE_LPI_EVENT 0x0b0071b8 /* EEE Low-Power Idle Event Registers */
#define SWITCH_PAGE_71_S_EEE_LPI_DURATION 0x0b0071bc /* EEE Low-Power Idle Duration Registers */
#define SWITCH_PAGE_71_S_RXDISCARD     0x0b0071c0 /* Rx Discard Counter */
#define SWITCH_PAGE_71_S_TXQPKTQ6      0x0b0071c8 /* Tx Q6 Packet Counter */
#define SWITCH_PAGE_71_S_TXQPKTQ7      0x0b0071cc /* Tx Q7 Packet Counter */
#define SWITCH_PAGE_71_S_TXPKTS64OCTETS 0x0b0071d0 /* Tx 64 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_TXPKTS65TO127OCTETS 0x0b0071d4 /* Tx 65 to 127 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_TXPKTS128TO255OCTETS 0x0b0071d8 /* Tx 128 to 255 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_TXPKTS256TO511OCTETS 0x0b0071dc /* Tx 256 to 511 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_TXPKTS512TO1023OCTETS 0x0b0071e0 /* Tx 512 to 1023 Bytes Octets Counter */
#define SWITCH_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS 0x0b0071e4 /* Tx 1024 to MaxPkt Bytes Octets Counter */
#define SWITCH_PAGE_72_LPDET_CFG       0x0b007200 /* Loop Detection Configuration Registers */
#define SWITCH_PAGE_72_DF_TIMER        0x0b007202 /* Discovery Frame Timer Registers */
#define SWITCH_PAGE_72_LED_PORTMAP     0x0b007203 /* LED Waming Portmap Registers */
#define SWITCH_PAGE_72_MODULE_ID0      0x0b007205 /* Module ID 0 Registers */
#define SWITCH_PAGE_72_MODULE_ID1      0x0b00720b /* Module ID 1 Registers */
#define SWITCH_PAGE_72_LPDET_SA        0x0b007211 /* Loop Detect Frame SA Registers */
#define SWITCH_PAGE_72_LPDET_REG_SPARE0 0x0b007220 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_72_LPDET_REG_SPARE1 0x0b007224 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_73_BPM_CTRL        0x0b007300 /* BPM Power Switching Control Register */
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL 0x0b007301 /* BPM Power Switching SW Override Register */
#define SWITCH_PAGE_73_BPM_PSM_TIME_CFG 0x0b007302 /* PSM_VDD Timing Parameter Configuration Register */
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG 0x0b007304 /* PSM_VDD Switching Threshold Configuration Register */
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL 0x0b007308 /* BUFCON Row Status Valid Mask SW Override Control Register */
#define SWITCH_PAGE_73_BPM_STS         0x0b00730c /* BPM Status Register */
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL 0x0b007310 /* BPM PDA Switching SW Override Control Register */
#define SWITCH_PAGE_73_PDA_TIMEOUT_CFG 0x0b007312 /* BPM PDA Switching Timeout Counter Register */
#define SWITCH_PAGE_73_PDA_SETUP_TIME_CFG 0x0b007314 /* BPM PDA Switching Setup Time Register */
#define SWITCH_PAGE_73_PDA_HOLD_TIME_CFG 0x0b007316 /* BPM PDA Switching Hold Time Register */
#define SWITCH_PAGE_73_PBB_VBUFCNT_0   0x0b007318 /* Packet Buffer Block 0 Valid Buffer Count Register */
#define SWITCH_PAGE_73_PBB_VBUFCNT_1   0x0b00731a /* Packet Buffer Block 1 Valid Buffer Count Register */
#define SWITCH_PAGE_73_PBB_VBUFCNT_2   0x0b00731c /* Packet Buffer Block 2 Valid Buffer Count Register */
#define SWITCH_PAGE_73_RCY_TIME_CFG    0x0b00731e /* Recycling Check Pulse Period Counter Register */
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL 0x0b007320 /* PBB Powerdown Monitor Control Register */
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_0 0x0b007328 /* PBB Powerdown Time Monitor 0 Register */
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_1 0x0b007330 /* PBB Powerdown Time Monitor 1 Register */
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_2 0x0b007338 /* PBB Powerdown Time Monitor 2 Register */
#define SWITCH_PAGE_73_BPM_REG_SPARE0  0x0b007360 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_73_BPM_REG_SPARE1  0x0b007364 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_TIME_STAMP_EN 0x0b009000 /* AVB Time Stamp Enable Register (Not2Release) */
#define SWITCH_PAGE_90_TM_STAMP_RPT_CTRL 0x0b009002 /* AVB Time Stamp Report Control Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_TM_BASE     0x0b009010 /* AVB Time Base Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_TM_ADJ      0x0b009014 /* AVB Time Base Adjustment Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_SLOT_TICK   0x0b009018 /* AVB Slot Number and Tick Counter Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_SLOT_ADJ    0x0b00901c /* AVB Slot Adjustment Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT0 0x0b009090 /* Port N AVB Egress Time Stamp Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT1 0x0b009094 /* Port N AVB Egress Time Stamp Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT2 0x0b009098 /* Port N AVB Egress Time Stamp Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT3 0x0b00909c /* Port N AVB Egress Time Stamp Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT4 0x0b0090a0 /* Port N AVB Egress Time Stamp Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT5 0x0b0090a4 /* Port N AVB Egress Time Stamp Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT6 0x0b0090a8 /* Port N AVB Egress Time Stamp Register (Not2Release) */
#define SWITCH_PAGE_90_TM_STAMP_STATUS 0x0b0090af /* AVB Egress Time Stamp Status Register (Not2Release) */
#define SWITCH_PAGE_90_EAV_LNK_STATUS  0x0b0090b0 /* AVB Port AVB Link Status Register */
#define SWITCH_PAGE_90_P1588_CTRL      0x0b0090c0 /* P1588 Control Register */
#define SWITCH_PAGE_90_AVB_TICK_CTRL   0x0b0090c2 /* AVB tick control */
#define SWITCH_PAGE_90_AVB_REG_SPARE0  0x0b0090d0 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_90_AVB_REG_SPARE1  0x0b0090d4 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_91_TRREG_CTRL0     0x0b009100 /* Traffic Remarking Control 0 Register */
#define SWITCH_PAGE_91_TRREG_CTRL1     0x0b009104 /* Traffic Remarking Control 1 Register */
#define SWITCH_PAGE_91_TRREG_CTRL2     0x0b009108 /* Traffic Remarking Control 2 Register */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0 0x0b009110 /* "Port N (0 to 6), Egress TC to PCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1 0x0b009118 /* "Port N (0 to 6), Egress TC to PCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2 0x0b009120 /* "Port N (0 to 6), Egress TC to PCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3 0x0b009128 /* "Port N (0 to 6), Egress TC to PCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4 0x0b009130 /* "Port N (0 to 6), Egress TC to PCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5 0x0b009138 /* "Port N (0 to 6), Egress TC to PCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6 0x0b009140 /* "Port N (0 to 6), Egress TC to PCP mapping Register" */
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP 0x0b009148 /* "Port 7, Egress TC to PCP mapping Register" */
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP 0x0b009150 /* "Port 8, Egress TC to PCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0 0x0b009160 /* "Port N (0 to 6), Egress TC to CPCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1 0x0b009168 /* "Port N (0 to 6), Egress TC to CPCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2 0x0b009170 /* "Port N (0 to 6), Egress TC to CPCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3 0x0b009178 /* "Port N (0 to 6), Egress TC to CPCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4 0x0b009180 /* "Port N (0 to 6), Egress TC to CPCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5 0x0b009188 /* "Port N (0 to 6), Egress TC to CPCP mapping Register" */
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6 0x0b009190 /* "Port N (0 to 6), Egress TC to CPCP mapping Register" */
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP 0x0b009198 /* "Port 7, Egress TC to CPCP mapping Register" */
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP 0x0b0091a0 /* "Port 8, Egress TC to CPCP mapping Register" */
#define SWITCH_PAGE_91_TRREG_REG_SPARE0 0x0b0091b0 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_91_TRREG_REG_SPARE1 0x0b0091b4 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_92_EEE_EN_CTRL     0x0b009200 /* EEE Enable Control Registers */
#define SWITCH_PAGE_92_EEE_LPI_ASSERT  0x0b009202 /* EEE Low Power Assert Status Registers */
#define SWITCH_PAGE_92_EEE_LPI_INDICATE 0x0b009204 /* EEE Low Power Indicate Status Registers */
#define SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL 0x0b009206 /* EEE Receiving Idle Symbols Status Registers */
#define SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE 0x0b009208 /* EEE LPI Symbol Transmit Disable Registers(Not2Release) */
#define SWITCH_PAGE_92_EEE_PIPELINE_TIMER 0x0b00920c /* EEE Pipeline Delay Timer Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT0 0x0b009210 /* EEE Port N (0 to 6) Sleep Delay Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT1 0x0b009214 /* EEE Port N (0 to 6) Sleep Delay Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT2 0x0b009218 /* EEE Port N (0 to 6) Sleep Delay Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT3 0x0b00921c /* EEE Port N (0 to 6) Sleep Delay Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT4 0x0b009220 /* EEE Port N (0 to 6) Sleep Delay Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT5 0x0b009224 /* EEE Port N (0 to 6) Sleep Delay Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT6 0x0b009228 /* EEE Port N (0 to 6) Sleep Delay Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_P7 0x0b00922c /* EEE Port 7 Sleep Delay Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_IMP 0x0b009230 /* EEE Port 8(IMP) Sleep Delay Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT0 0x0b009234 /* EEE Port N (0 to 6) Sleep Delay Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT1 0x0b009238 /* EEE Port N (0 to 6) Sleep Delay Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT2 0x0b00923c /* EEE Port N (0 to 6) Sleep Delay Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT3 0x0b009240 /* EEE Port N (0 to 6) Sleep Delay Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT4 0x0b009244 /* EEE Port N (0 to 6) Sleep Delay Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT5 0x0b009248 /* EEE Port N (0 to 6) Sleep Delay Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT6 0x0b00924c /* EEE Port N (0 to 6) Sleep Delay Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_P7 0x0b009250 /* EEE Port 7 Sleep Delay Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_IMP 0x0b009254 /* EEE Port 8(IMP) Sleep Delay Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT0 0x0b009258 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT1 0x0b00925c /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT2 0x0b009260 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT3 0x0b009264 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT4 0x0b009268 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT5 0x0b00926c /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT6 0x0b009270 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_P7 0x0b009274 /* EEE Port 7 Minimum Low-Power Duration Timer Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_IMP 0x0b009278 /* EEE Port 8(IMP) Minimum Low-Power Duration Timer Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT0 0x0b00927c /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT1 0x0b009280 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT2 0x0b009284 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT3 0x0b009288 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT4 0x0b00928c /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT5 0x0b009290 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT6 0x0b009294 /* EEE Port (0 to 6) Minimum Low-Power Duration Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_P7 0x0b009298 /* EEE Port 7 Minimum Low-Power Duration Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_IMP 0x0b00929c /* EEE Port 8(IMP) Minimum Low-Power Duration Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT0 0x0b0092a0 /* EEE Port N (0 to 6) Wake Transition Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT1 0x0b0092a2 /* EEE Port N (0 to 6) Wake Transition Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT2 0x0b0092a4 /* EEE Port N (0 to 6) Wake Transition Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT3 0x0b0092a6 /* EEE Port N (0 to 6) Wake Transition Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT4 0x0b0092a8 /* EEE Port N (0 to 6) Wake Transition Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT5 0x0b0092aa /* EEE Port N (0 to 6) Wake Transition Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT6 0x0b0092ac /* EEE Port N (0 to 6) Wake Transition Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_P7 0x0b0092ae /* EEE Port 7 Wake Transition Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_IMP 0x0b0092b0 /* EEE Port 8(IMP) Wake Transition Timer - 1G Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT0 0x0b0092b2 /* EEE Port N (0 to 6) Wake Transition Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT1 0x0b0092b4 /* EEE Port N (0 to 6) Wake Transition Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT2 0x0b0092b6 /* EEE Port N (0 to 6) Wake Transition Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT3 0x0b0092b8 /* EEE Port N (0 to 6) Wake Transition Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT4 0x0b0092ba /* EEE Port N (0 to 6) Wake Transition Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT5 0x0b0092bc /* EEE Port N (0 to 6) Wake Transition Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT6 0x0b0092be /* EEE Port N (0 to 6) Wake Transition Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_P7 0x0b0092c0 /* EEE Port 7 Wake Transition Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_IMP 0x0b0092c2 /* EEE Port 8(IMP) Wake Transition Timer - 100M Registers */
#define SWITCH_PAGE_92_EEE_GLB_CONG_TH 0x0b0092c4 /* EEE Global Congestion Threshold Registers */
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH0 0x0b0092c6 /* EEE TXQ 0 Congestion Threshold Registers */
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH1 0x0b0092c8 /* EEE TXQ 1 Congestion Threshold Registers */
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH2 0x0b0092ca /* EEE TXQ 2 Congestion Threshold Registers */
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH3 0x0b0092cc /* EEE TXQ 3 Congestion Threshold Registers */
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH4 0x0b0092ce /* EEE TXQ 4 Congestion Threshold Registers */
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH5 0x0b0092d0 /* EEE TXQ 5 Congestion Threshold Registers */
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH6 0x0b0092d3 /* EEE TXQ 6 Congestion Threshold Registers */
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH7 0x0b0092d5 /* EEE TXQ 7 Congestion Threshold Registers */
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE0 0x0b0092db /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE1 0x0b0092e0 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_92_EEE_DEBUG       0x0b0092e7 /* EEE Debug Registers(Not2Release) */
#define SWITCH_PAGE_92_EEE_LINK_DLY_TIMER 0x0b0092e8 /* EEE Link Delay Timer Registers(Not2Release) */
#define SWITCH_PAGE_92_EEE_STATE       0x0b0092ec /* EEE Control Policy State Registers(Not2Release) */
#define SWITCH_PAGE_95_RED_CONTROL     0x0b009500 /* RED Control Register */
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE 0x0b009502 /* RED Table Configuration Register */
#define SWITCH_PAGE_95_RED_EGRESS_BYPASS 0x0b009504 /* RED Egress Bypass Register */
#define SWITCH_PAGE_95_RED_AQD_CONTROL 0x0b009506 /* RED AQD Control Register */
#define SWITCH_PAGE_95_RED_EXPONENT    0x0b009508 /* RED AQD Weighted Factor Register */
#define SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB 0x0b00950a /* RED Drop Add to MIB Register */
#define SWITCH_PAGE_95_RED_PROFILE_DEFAULT 0x0b009510 /* Default RED profile Register */
#define SWITCH_PAGE_95_WRED_REG_SPARE0 0x0b009514 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_95_WRED_REG_SPARE1 0x0b009518 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_95_RED_PROFILE_0   0x0b009520 /* RED profile 0 Register */
#define SWITCH_PAGE_95_RED_PROFILE_1   0x0b009524 /* RED profile 1 Register */
#define SWITCH_PAGE_95_RED_PROFILE_2   0x0b009528 /* RED profile 2 Register */
#define SWITCH_PAGE_95_RED_PROFILE_3   0x0b00952c /* RED profile 3 Register */
#define SWITCH_PAGE_95_RED_PROFILE_4   0x0b009530 /* RED profile 4 Register */
#define SWITCH_PAGE_95_RED_PROFILE_5   0x0b009534 /* RED profile 5 Register */
#define SWITCH_PAGE_95_RED_PROFILE_6   0x0b009538 /* RED profile 6 Register */
#define SWITCH_PAGE_95_RED_PROFILE_7   0x0b00953c /* RED profile 7 Register */
#define SWITCH_PAGE_95_RED_PROFILE_8   0x0b009540 /* RED profile 8 Register */
#define SWITCH_PAGE_95_RED_PROFILE_9   0x0b009544 /* RED profile 9 Register */
#define SWITCH_PAGE_95_RED_PROFILE_10  0x0b009548 /* RED profile 10 Register */
#define SWITCH_PAGE_95_RED_PROFILE_11  0x0b00954c /* RED profile 11 Register */
#define SWITCH_PAGE_95_RED_PROFILE_12  0x0b009550 /* RED profile 12 Register */
#define SWITCH_PAGE_95_RED_PROFILE_13  0x0b009554 /* RED profile 13 Register */
#define SWITCH_PAGE_95_RED_PROFILE_14  0x0b009558 /* RED profile 14 Register */
#define SWITCH_PAGE_95_RED_PROFILE_15  0x0b00955c /* RED profile 15 Register */
#define SWITCH_PAGE_95_RED_DROP_CNTR_RST 0x0b00956c /* RED Drop Counter Reset Register */
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT0 0x0b009570 /* PORT N (0 to 6) RED Packet Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT1 0x0b009574 /* PORT N (0 to 6) RED Packet Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT2 0x0b009578 /* PORT N (0 to 6) RED Packet Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT3 0x0b00957c /* PORT N (0 to 6) RED Packet Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT4 0x0b009580 /* PORT N (0 to 6) RED Packet Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT5 0x0b009584 /* PORT N (0 to 6) RED Packet Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT6 0x0b009588 /* PORT N (0 to 6) RED Packet Drop Counter Register */
#define SWITCH_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR 0x0b00958c /* PORT 7 RED Packet Drop Counter Register */
#define SWITCH_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR 0x0b009590 /* PORT 8 RED Packet Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT0 0x0b0095a0 /* PORT N (0 to 6) RED Byte Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT1 0x0b0095a8 /* PORT N (0 to 6) RED Byte Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT2 0x0b0095b0 /* PORT N (0 to 6) RED Byte Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT3 0x0b0095b8 /* PORT N (0 to 6) RED Byte Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT4 0x0b0095c0 /* PORT N (0 to 6) RED Byte Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT5 0x0b0095c8 /* PORT N (0 to 6) RED Byte Drop Counter Register */
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT6 0x0b0095d0 /* PORT N (0 to 6) RED Byte Drop Counter Register */
#define SWITCH_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR 0x0b0095d8 /* PORT 7 RED Byte Drop Counter Register */
#define SWITCH_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR 0x0b0095e0 /* PORT 8 RED Byte Drop Counter Register */
#define SWITCH_PAGE_A0_CFP_ACC         0x0b00a000 /* CFP Access Registers */
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL 0x0b00a004 /* CFP RATE METER Global Control Registers */
#define SWITCH_PAGE_A0_CFP_DATA0       0x0b00a010 /* CFP TCAM Data 0 Registers */
#define SWITCH_PAGE_A0_CFP_DATA1       0x0b00a014 /* CFP TCAM Data 1 Registers */
#define SWITCH_PAGE_A0_CFP_DATA2       0x0b00a018 /* CFP TCAM Data 2 Registers */
#define SWITCH_PAGE_A0_CFP_DATA3       0x0b00a01c /* CFP TCAM Data 3 Registers */
#define SWITCH_PAGE_A0_CFP_DATA4       0x0b00a020 /* CFP TCAM Data 4 Registers */
#define SWITCH_PAGE_A0_CFP_DATA5       0x0b00a024 /* CFP TCAM Data 5 Registers */
#define SWITCH_PAGE_A0_CFP_DATA6       0x0b00a028 /* CFP TCAM Data 6 Registers */
#define SWITCH_PAGE_A0_CFP_DATA7       0x0b00a02c /* CFP TCAM Data 7 Registers */
#define SWITCH_PAGE_A0_CFP_MASK0       0x0b00a030 /* CFP TCAM Mask 0 Registers */
#define SWITCH_PAGE_A0_CFP_MASK1       0x0b00a034 /* CFP TCAM Mask 1 Registers */
#define SWITCH_PAGE_A0_CFP_MASK2       0x0b00a038 /* CFP TCAM Mask 2 Registers */
#define SWITCH_PAGE_A0_CFP_MASK3       0x0b00a03c /* CFP TCAM Mask 3 Registers */
#define SWITCH_PAGE_A0_CFP_MASK4       0x0b00a040 /* CFP TCAM Mask 4 Registers */
#define SWITCH_PAGE_A0_CFP_MASK5       0x0b00a044 /* CFP TCAM Mask 5 Registers */
#define SWITCH_PAGE_A0_CFP_MASK6       0x0b00a048 /* CFP TCAM Mask 6 Registers */
#define SWITCH_PAGE_A0_CFP_MASK7       0x0b00a04c /* CFP TCAM Mask 7 Registers */
#define SWITCH_PAGE_A0_ACT_POL_DATA0   0x0b00a050 /* CFP Action/Policy Data 0 Registers */
#define SWITCH_PAGE_A0_ACT_POL_DATA1   0x0b00a054 /* CFP Action/Policy Data 1 Registers */
#define SWITCH_PAGE_A0_ACT_POL_DATA2   0x0b00a058 /* CFP Action/Policy Data 2 Registers */
#define SWITCH_PAGE_A0_RATE_METER0     0x0b00a060 /* CFP RATE METER DATA 0 Registers */
#define SWITCH_PAGE_A0_RATE_METER1     0x0b00a064 /* CFP RATE METER DATA 1 Registers */
#define SWITCH_PAGE_A0_RATE_METER2     0x0b00a068 /* CFP RATE METER DATA 2 Registers */
#define SWITCH_PAGE_A0_RATE_METER3     0x0b00a06c /* CFP RATE METER DATA 3 Registers */
#define SWITCH_PAGE_A0_RATE_METER4     0x0b00a070 /* CFP RATE METER DATA 4 Registers */
#define SWITCH_PAGE_A0_RATE_METER5     0x0b00a074 /* CFP RATE METER DATA 5 Registers */
#define SWITCH_PAGE_A0_RATE_METER6     0x0b00a078 /* CFP RATE METER DATA 6 Registers */
#define SWITCH_PAGE_A0_TC2COLOR        0x0b00a07c /* TC to COLOR Mapping Registers */
#define SWITCH_PAGE_A0_STAT_GREEN_CNTR 0x0b00a080 /* Policer Green color statistic counter */
#define SWITCH_PAGE_A0_STAT_YELLOW_CNTR 0x0b00a084 /* Policer Yellow color statistic counter */
#define SWITCH_PAGE_A0_STAT_RED_CNTR   0x0b00a088 /* Policer RED color statistic counter */
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL 0x0b00a0a0 /* TCAM BIST Control Registers (Not2Release) */
#define SWITCH_PAGE_A0_TCAM_BIST_STATUS 0x0b00a0a4 /* TCAM BIST Status Registers (Not2Release) */
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS 0x0b00a0a8 /* TCAM Test Compare Status Registers (Not2Release) */
#define SWITCH_PAGE_A0_CFP_REG_SPARE0  0x0b00a0b0 /* Spare 0 Register (Not2Release) */
#define SWITCH_PAGE_A0_CFP_REG_SPARE1  0x0b00a0b4 /* Spare 1 Register (Not2Release) */
#define SWITCH_PAGE_A1_CFP_CTL_REG     0x0b00a100 /* CFP Control Registers */
#define SWITCH_PAGE_A1_UDF_0_A_0       0x0b00a110 /* UDFs of slice 0 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_A_1       0x0b00a111 /* UDFs of slice 0 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_A_2       0x0b00a112 /* UDFs of slice 0 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_A_3       0x0b00a113 /* UDFs of slice 0 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_A_4       0x0b00a114 /* UDFs of slice 0 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_A_5       0x0b00a115 /* UDFs of slice 0 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_A_6       0x0b00a116 /* UDFs of slice 0 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_A_7       0x0b00a117 /* UDFs of slice 0 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_A_8       0x0b00a118 /* UDFs of slice 0 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_A_0       0x0b00a120 /* UDFs of slice 1 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_A_1       0x0b00a121 /* UDFs of slice 1 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_A_2       0x0b00a122 /* UDFs of slice 1 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_A_3       0x0b00a123 /* UDFs of slice 1 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_A_4       0x0b00a124 /* UDFs of slice 1 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_A_5       0x0b00a125 /* UDFs of slice 1 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_A_6       0x0b00a126 /* UDFs of slice 1 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_A_7       0x0b00a127 /* UDFs of slice 1 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_A_8       0x0b00a128 /* UDFs of slice 1 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_A_0       0x0b00a130 /* UDFs of slice 2 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_A_1       0x0b00a131 /* UDFs of slice 2 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_A_2       0x0b00a132 /* UDFs of slice 2 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_A_3       0x0b00a133 /* UDFs of slice 2 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_A_4       0x0b00a134 /* UDFs of slice 2 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_A_5       0x0b00a135 /* UDFs of slice 2 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_A_6       0x0b00a136 /* UDFs of slice 2 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_A_7       0x0b00a137 /* UDFs of slice 2 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_A_8       0x0b00a138 /* UDFs of slice 2 for IPv4 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_B_0       0x0b00a140 /* UDFs of slice 0 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_B_1       0x0b00a141 /* UDFs of slice 0 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_B_2       0x0b00a142 /* UDFs of slice 0 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_B_3       0x0b00a143 /* UDFs of slice 0 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_B_4       0x0b00a144 /* UDFs of slice 0 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_B_5       0x0b00a145 /* UDFs of slice 0 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_B_6       0x0b00a146 /* UDFs of slice 0 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_B_7       0x0b00a147 /* UDFs of slice 0 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_B_8       0x0b00a148 /* UDFs of slice 0 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_B_0       0x0b00a150 /* UDFs of slice 1 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_B_1       0x0b00a151 /* UDFs of slice 1 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_B_2       0x0b00a152 /* UDFs of slice 1 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_B_3       0x0b00a153 /* UDFs of slice 1 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_B_4       0x0b00a154 /* UDFs of slice 1 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_B_5       0x0b00a155 /* UDFs of slice 1 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_B_6       0x0b00a156 /* UDFs of slice 1 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_B_7       0x0b00a157 /* UDFs of slice 1 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_1_B_8       0x0b00a158 /* UDFs of slice 1 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_B_0       0x0b00a160 /* UDFs of slice 2 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_B_1       0x0b00a161 /* UDFs of slice 2 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_B_2       0x0b00a162 /* UDFs of slice 2 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_B_3       0x0b00a163 /* UDFs of slice 2 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_B_4       0x0b00a164 /* UDFs of slice 2 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_B_5       0x0b00a165 /* UDFs of slice 2 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_B_6       0x0b00a166 /* UDFs of slice 2 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_B_7       0x0b00a167 /* UDFs of slice 2 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_2_B_8       0x0b00a168 /* UDFs of slice 2 for IPv6 packet Registers */
#define SWITCH_PAGE_A1_UDF_0_C_0       0x0b00a170 /* UDFs of slice 0 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_0_C_1       0x0b00a171 /* UDFs of slice 0 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_0_C_2       0x0b00a172 /* UDFs of slice 0 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_0_C_3       0x0b00a173 /* UDFs of slice 0 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_0_C_4       0x0b00a174 /* UDFs of slice 0 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_0_C_5       0x0b00a175 /* UDFs of slice 0 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_0_C_6       0x0b00a176 /* UDFs of slice 0 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_0_C_7       0x0b00a177 /* UDFs of slice 0 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_0_C_8       0x0b00a178 /* UDFs of slice 0 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_1_C_0       0x0b00a180 /* UDFs of slice 1 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_1_C_1       0x0b00a181 /* UDFs of slice 1 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_1_C_2       0x0b00a182 /* UDFs of slice 1 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_1_C_3       0x0b00a183 /* UDFs of slice 1 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_1_C_4       0x0b00a184 /* UDFs of slice 1 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_1_C_5       0x0b00a185 /* UDFs of slice 1 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_1_C_6       0x0b00a186 /* UDFs of slice 1 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_1_C_7       0x0b00a187 /* UDFs of slice 1 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_1_C_8       0x0b00a188 /* UDFs of slice 1 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_2_C_0       0x0b00a190 /* UDFs of slice 2 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_2_C_1       0x0b00a191 /* UDFs of slice 2 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_2_C_2       0x0b00a192 /* UDFs of slice 2 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_2_C_3       0x0b00a193 /* UDFs of slice 2 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_2_C_4       0x0b00a194 /* UDFs of slice 2 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_2_C_5       0x0b00a195 /* UDFs of slice 2 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_2_C_6       0x0b00a196 /* UDFs of slice 2 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_2_C_7       0x0b00a197 /* UDFs of slice 2 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_2_C_8       0x0b00a198 /* UDFs of slice 2 for non-IP packet Registers */
#define SWITCH_PAGE_A1_UDF_0_D_0       0x0b00a1a0 /* UDF 0 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_1       0x0b00a1a1 /* UDF 1 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_2       0x0b00a1a2 /* UDF 2 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_3       0x0b00a1a3 /* UDF 3 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_4       0x0b00a1a4 /* UDF 4 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_5       0x0b00a1a5 /* UDF 5 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_6       0x0b00a1a6 /* UDF 6 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_7       0x0b00a1a7 /* UDF 7 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_8       0x0b00a1a8 /* UDF 8 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_9       0x0b00a1a9 /* UDF 9 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_A       0x0b00a1aa /* UDF 10 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_A1_UDF_0_D_B       0x0b00a1ab /* UDF 12 for IPv6 Chain Rule Registers */
#define SWITCH_PAGE_B0_ARL_TCAM_ACC    0x0b00b000 /* ARL TCAM and Secondary SRAM Access Register */
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_0 0x0b00b004 /* ARL TCAM Data Register */
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_1 0x0b00b008 /* ARL TCAM Data Register */
#define SWITCH_PAGE_B0_ARL_SMEM_DATA   0x0b00b014 /* ARL SMEM Data Register */
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL 0x0b00b020 /* TCAM BIST Control Registers (Not2Release) */
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_STS 0x0b00b024 /* TCAM BIST Status Registers (Not2Release) */


/****************************************************************************
 * bcm89530_sys_cfg_VIC0
 ***************************************************************************/
/****************************************************************************
 * VIC0 :: VICIRQSTATUS
 ***************************************************************************/
/* VIC0 :: VICIRQSTATUS :: IRQStatus [31:00] */
#define Wr_VIC0_VICIRQSTATUS_IRQStatus(x) WriteReg(VIC0_VICIRQSTATUS,x)
#define Rd_VIC0_VICIRQSTATUS_IRQStatus(x) ReadReg(VIC0_VICIRQSTATUS)
#define VIC0_VICIRQSTATUS_IRQSTATUS_MASK                           0xffffffff
#define VIC0_VICIRQSTATUS_IRQSTATUS_ALIGN                          0
#define VIC0_VICIRQSTATUS_IRQSTATUS_BITS                           32
#define VIC0_VICIRQSTATUS_IRQSTATUS_SHIFT                          0


/****************************************************************************
 * VIC0 :: VICFIQSTATUS
 ***************************************************************************/
/* VIC0 :: VICFIQSTATUS :: FIQStatus [31:00] */
#define Wr_VIC0_VICFIQSTATUS_FIQStatus(x) WriteReg(VIC0_VICFIQSTATUS,x)
#define Rd_VIC0_VICFIQSTATUS_FIQStatus(x) ReadReg(VIC0_VICFIQSTATUS)
#define VIC0_VICFIQSTATUS_FIQSTATUS_MASK                           0xffffffff
#define VIC0_VICFIQSTATUS_FIQSTATUS_ALIGN                          0
#define VIC0_VICFIQSTATUS_FIQSTATUS_BITS                           32
#define VIC0_VICFIQSTATUS_FIQSTATUS_SHIFT                          0


/****************************************************************************
 * VIC0 :: VICRAWINTR
 ***************************************************************************/
/* VIC0 :: VICRAWINTR :: RawInterrupt [31:00] */
#define Wr_VIC0_VICRAWINTR_RawInterrupt(x) WriteReg(VIC0_VICRAWINTR,x)
#define Rd_VIC0_VICRAWINTR_RawInterrupt(x) ReadReg(VIC0_VICRAWINTR)
#define VIC0_VICRAWINTR_RAWINTERRUPT_MASK                          0xffffffff
#define VIC0_VICRAWINTR_RAWINTERRUPT_ALIGN                         0
#define VIC0_VICRAWINTR_RAWINTERRUPT_BITS                          32
#define VIC0_VICRAWINTR_RAWINTERRUPT_SHIFT                         0


/****************************************************************************
 * VIC0 :: VICINTSELECT
 ***************************************************************************/
/* VIC0 :: VICINTSELECT :: IntSelect [31:00] */
#define Wr_VIC0_VICINTSELECT_IntSelect(x) WriteReg(VIC0_VICINTSELECT,x)
#define Rd_VIC0_VICINTSELECT_IntSelect(x) ReadReg(VIC0_VICINTSELECT)
#define VIC0_VICINTSELECT_INTSELECT_MASK                           0xffffffff
#define VIC0_VICINTSELECT_INTSELECT_ALIGN                          0
#define VIC0_VICINTSELECT_INTSELECT_BITS                           32
#define VIC0_VICINTSELECT_INTSELECT_SHIFT                          0


/****************************************************************************
 * VIC0 :: VICINTENABLE
 ***************************************************************************/
/* VIC0 :: VICINTENABLE :: IntEnable [31:00] */
#define Wr_VIC0_VICINTENABLE_IntEnable(x) WriteReg(VIC0_VICINTENABLE,x)
#define Rd_VIC0_VICINTENABLE_IntEnable(x) ReadReg(VIC0_VICINTENABLE)
#define VIC0_VICINTENABLE_INTENABLE_MASK                           0xffffffff
#define VIC0_VICINTENABLE_INTENABLE_ALIGN                          0
#define VIC0_VICINTENABLE_INTENABLE_BITS                           32
#define VIC0_VICINTENABLE_INTENABLE_SHIFT                          0


/****************************************************************************
 * VIC0 :: VICINTENCLEAR
 ***************************************************************************/
/* VIC0 :: VICINTENCLEAR :: IntEnableClear [31:00] */
#define Wr_VIC0_VICINTENCLEAR_IntEnableClear(x) WriteReg(VIC0_VICINTENCLEAR,x)
#define Rd_VIC0_VICINTENCLEAR_IntEnableClear(x) ReadReg(VIC0_VICINTENCLEAR)
#define VIC0_VICINTENCLEAR_INTENABLECLEAR_MASK                     0xffffffff
#define VIC0_VICINTENCLEAR_INTENABLECLEAR_ALIGN                    0
#define VIC0_VICINTENCLEAR_INTENABLECLEAR_BITS                     32
#define VIC0_VICINTENCLEAR_INTENABLECLEAR_SHIFT                    0


/****************************************************************************
 * VIC0 :: VICSOFTINT
 ***************************************************************************/
/* VIC0 :: VICSOFTINT :: SoftInt [31:00] */
#define Wr_VIC0_VICSOFTINT_SoftInt(x) WriteReg(VIC0_VICSOFTINT,x)
#define Rd_VIC0_VICSOFTINT_SoftInt(x) ReadReg(VIC0_VICSOFTINT)
#define VIC0_VICSOFTINT_SOFTINT_MASK                               0xffffffff
#define VIC0_VICSOFTINT_SOFTINT_ALIGN                              0
#define VIC0_VICSOFTINT_SOFTINT_BITS                               32
#define VIC0_VICSOFTINT_SOFTINT_SHIFT                              0


/****************************************************************************
 * VIC0 :: VICSOFTINTCLEAR
 ***************************************************************************/
/* VIC0 :: VICSOFTINTCLEAR :: SoftIntClear [31:00] */
#define Wr_VIC0_VICSOFTINTCLEAR_SoftIntClear(x) WriteReg(VIC0_VICSOFTINTCLEAR,x)
#define Rd_VIC0_VICSOFTINTCLEAR_SoftIntClear(x) ReadReg(VIC0_VICSOFTINTCLEAR)
#define VIC0_VICSOFTINTCLEAR_SOFTINTCLEAR_MASK                     0xffffffff
#define VIC0_VICSOFTINTCLEAR_SOFTINTCLEAR_ALIGN                    0
#define VIC0_VICSOFTINTCLEAR_SOFTINTCLEAR_BITS                     32
#define VIC0_VICSOFTINTCLEAR_SOFTINTCLEAR_SHIFT                    0


/****************************************************************************
 * VIC0 :: VICPROTECTION
 ***************************************************************************/
/* VIC0 :: VICPROTECTION :: reserved0 [31:01] */
#define VIC0_VICPROTECTION_RESERVED0_MASK                          0xfffffffe
#define VIC0_VICPROTECTION_RESERVED0_ALIGN                         0
#define VIC0_VICPROTECTION_RESERVED0_BITS                          31
#define VIC0_VICPROTECTION_RESERVED0_SHIFT                         1

/* VIC0 :: VICPROTECTION :: Protection [00:00] */
#define Wr_VIC0_VICPROTECTION_Protection(x) WriteRegBits(VIC0_VICPROTECTION,0x1,0,x)
#define Rd_VIC0_VICPROTECTION_Protection(x) ReadRegBits(VIC0_VICPROTECTION,0x1,0)
#define VIC0_VICPROTECTION_PROTECTION_MASK                         0x00000001
#define VIC0_VICPROTECTION_PROTECTION_ALIGN                        0
#define VIC0_VICPROTECTION_PROTECTION_BITS                         1
#define VIC0_VICPROTECTION_PROTECTION_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICSWPRIORITYMASK
 ***************************************************************************/
/* VIC0 :: VICSWPRIORITYMASK :: reserved0 [31:16] */
#define VIC0_VICSWPRIORITYMASK_RESERVED0_MASK                      0xffff0000
#define VIC0_VICSWPRIORITYMASK_RESERVED0_ALIGN                     0
#define VIC0_VICSWPRIORITYMASK_RESERVED0_BITS                      16
#define VIC0_VICSWPRIORITYMASK_RESERVED0_SHIFT                     16

/* VIC0 :: VICSWPRIORITYMASK :: SWPriorityMask [15:00] */
#define Wr_VIC0_VICSWPRIORITYMASK_SWPriorityMask(x) WriteRegBits(VIC0_VICSWPRIORITYMASK,0xffff,0,x)
#define Rd_VIC0_VICSWPRIORITYMASK_SWPriorityMask(x) ReadRegBits(VIC0_VICSWPRIORITYMASK,0xffff,0)
#define VIC0_VICSWPRIORITYMASK_SWPRIORITYMASK_MASK                 0x0000ffff
#define VIC0_VICSWPRIORITYMASK_SWPRIORITYMASK_ALIGN                0
#define VIC0_VICSWPRIORITYMASK_SWPRIORITYMASK_BITS                 16
#define VIC0_VICSWPRIORITYMASK_SWPRIORITYMASK_SHIFT                0


/****************************************************************************
 * VIC0 :: VICSWPRIORITYDAISY
 ***************************************************************************/
/* VIC0 :: VICSWPRIORITYDAISY :: reserved0 [31:04] */
#define VIC0_VICSWPRIORITYDAISY_RESERVED0_MASK                     0xfffffff0
#define VIC0_VICSWPRIORITYDAISY_RESERVED0_ALIGN                    0
#define VIC0_VICSWPRIORITYDAISY_RESERVED0_BITS                     28
#define VIC0_VICSWPRIORITYDAISY_RESERVED0_SHIFT                    4

/* VIC0 :: VICSWPRIORITYDAISY :: VectPriority [03:00] */
#define Wr_VIC0_VICSWPRIORITYDAISY_VectPriority(x) WriteRegBits(VIC0_VICSWPRIORITYDAISY,0xf,0,x)
#define Rd_VIC0_VICSWPRIORITYDAISY_VectPriority(x) ReadRegBits(VIC0_VICSWPRIORITYDAISY,0xf,0)
#define VIC0_VICSWPRIORITYDAISY_VECTPRIORITY_MASK                  0x0000000f
#define VIC0_VICSWPRIORITYDAISY_VECTPRIORITY_ALIGN                 0
#define VIC0_VICSWPRIORITYDAISY_VECTPRIORITY_BITS                  4
#define VIC0_VICSWPRIORITYDAISY_VECTPRIORITY_SHIFT                 0


/****************************************************************************
 * VIC0 :: VICVECTADDR0
 ***************************************************************************/
/* VIC0 :: VICVECTADDR0 :: VectorAddr0 [31:00] */
#define Wr_VIC0_VICVECTADDR0_VectorAddr0(x) WriteReg(VIC0_VICVECTADDR0,x)
#define Rd_VIC0_VICVECTADDR0_VectorAddr0(x) ReadReg(VIC0_VICVECTADDR0)
#define VIC0_VICVECTADDR0_VECTORADDR0_MASK                         0xffffffff
#define VIC0_VICVECTADDR0_VECTORADDR0_ALIGN                        0
#define VIC0_VICVECTADDR0_VECTORADDR0_BITS                         32
#define VIC0_VICVECTADDR0_VECTORADDR0_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR1
 ***************************************************************************/
/* VIC0 :: VICVECTADDR1 :: VectorAddr1 [31:00] */
#define Wr_VIC0_VICVECTADDR1_VectorAddr1(x) WriteReg(VIC0_VICVECTADDR1,x)
#define Rd_VIC0_VICVECTADDR1_VectorAddr1(x) ReadReg(VIC0_VICVECTADDR1)
#define VIC0_VICVECTADDR1_VECTORADDR1_MASK                         0xffffffff
#define VIC0_VICVECTADDR1_VECTORADDR1_ALIGN                        0
#define VIC0_VICVECTADDR1_VECTORADDR1_BITS                         32
#define VIC0_VICVECTADDR1_VECTORADDR1_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR2
 ***************************************************************************/
/* VIC0 :: VICVECTADDR2 :: VectorAddr2 [31:00] */
#define Wr_VIC0_VICVECTADDR2_VectorAddr2(x) WriteReg(VIC0_VICVECTADDR2,x)
#define Rd_VIC0_VICVECTADDR2_VectorAddr2(x) ReadReg(VIC0_VICVECTADDR2)
#define VIC0_VICVECTADDR2_VECTORADDR2_MASK                         0xffffffff
#define VIC0_VICVECTADDR2_VECTORADDR2_ALIGN                        0
#define VIC0_VICVECTADDR2_VECTORADDR2_BITS                         32
#define VIC0_VICVECTADDR2_VECTORADDR2_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR3
 ***************************************************************************/
/* VIC0 :: VICVECTADDR3 :: VectorAddr3 [31:00] */
#define Wr_VIC0_VICVECTADDR3_VectorAddr3(x) WriteReg(VIC0_VICVECTADDR3,x)
#define Rd_VIC0_VICVECTADDR3_VectorAddr3(x) ReadReg(VIC0_VICVECTADDR3)
#define VIC0_VICVECTADDR3_VECTORADDR3_MASK                         0xffffffff
#define VIC0_VICVECTADDR3_VECTORADDR3_ALIGN                        0
#define VIC0_VICVECTADDR3_VECTORADDR3_BITS                         32
#define VIC0_VICVECTADDR3_VECTORADDR3_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR4
 ***************************************************************************/
/* VIC0 :: VICVECTADDR4 :: VectorAddr4 [31:00] */
#define Wr_VIC0_VICVECTADDR4_VectorAddr4(x) WriteReg(VIC0_VICVECTADDR4,x)
#define Rd_VIC0_VICVECTADDR4_VectorAddr4(x) ReadReg(VIC0_VICVECTADDR4)
#define VIC0_VICVECTADDR4_VECTORADDR4_MASK                         0xffffffff
#define VIC0_VICVECTADDR4_VECTORADDR4_ALIGN                        0
#define VIC0_VICVECTADDR4_VECTORADDR4_BITS                         32
#define VIC0_VICVECTADDR4_VECTORADDR4_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR5
 ***************************************************************************/
/* VIC0 :: VICVECTADDR5 :: VectorAddr5 [31:00] */
#define Wr_VIC0_VICVECTADDR5_VectorAddr5(x) WriteReg(VIC0_VICVECTADDR5,x)
#define Rd_VIC0_VICVECTADDR5_VectorAddr5(x) ReadReg(VIC0_VICVECTADDR5)
#define VIC0_VICVECTADDR5_VECTORADDR5_MASK                         0xffffffff
#define VIC0_VICVECTADDR5_VECTORADDR5_ALIGN                        0
#define VIC0_VICVECTADDR5_VECTORADDR5_BITS                         32
#define VIC0_VICVECTADDR5_VECTORADDR5_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR6
 ***************************************************************************/
/* VIC0 :: VICVECTADDR6 :: VectorAddr6 [31:00] */
#define Wr_VIC0_VICVECTADDR6_VectorAddr6(x) WriteReg(VIC0_VICVECTADDR6,x)
#define Rd_VIC0_VICVECTADDR6_VectorAddr6(x) ReadReg(VIC0_VICVECTADDR6)
#define VIC0_VICVECTADDR6_VECTORADDR6_MASK                         0xffffffff
#define VIC0_VICVECTADDR6_VECTORADDR6_ALIGN                        0
#define VIC0_VICVECTADDR6_VECTORADDR6_BITS                         32
#define VIC0_VICVECTADDR6_VECTORADDR6_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR7
 ***************************************************************************/
/* VIC0 :: VICVECTADDR7 :: VectorAddr7 [31:00] */
#define Wr_VIC0_VICVECTADDR7_VectorAddr7(x) WriteReg(VIC0_VICVECTADDR7,x)
#define Rd_VIC0_VICVECTADDR7_VectorAddr7(x) ReadReg(VIC0_VICVECTADDR7)
#define VIC0_VICVECTADDR7_VECTORADDR7_MASK                         0xffffffff
#define VIC0_VICVECTADDR7_VECTORADDR7_ALIGN                        0
#define VIC0_VICVECTADDR7_VECTORADDR7_BITS                         32
#define VIC0_VICVECTADDR7_VECTORADDR7_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR8
 ***************************************************************************/
/* VIC0 :: VICVECTADDR8 :: VectorAddr8 [31:00] */
#define Wr_VIC0_VICVECTADDR8_VectorAddr8(x) WriteReg(VIC0_VICVECTADDR8,x)
#define Rd_VIC0_VICVECTADDR8_VectorAddr8(x) ReadReg(VIC0_VICVECTADDR8)
#define VIC0_VICVECTADDR8_VECTORADDR8_MASK                         0xffffffff
#define VIC0_VICVECTADDR8_VECTORADDR8_ALIGN                        0
#define VIC0_VICVECTADDR8_VECTORADDR8_BITS                         32
#define VIC0_VICVECTADDR8_VECTORADDR8_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR9
 ***************************************************************************/
/* VIC0 :: VICVECTADDR9 :: VectorAddr9 [31:00] */
#define Wr_VIC0_VICVECTADDR9_VectorAddr9(x) WriteReg(VIC0_VICVECTADDR9,x)
#define Rd_VIC0_VICVECTADDR9_VectorAddr9(x) ReadReg(VIC0_VICVECTADDR9)
#define VIC0_VICVECTADDR9_VECTORADDR9_MASK                         0xffffffff
#define VIC0_VICVECTADDR9_VECTORADDR9_ALIGN                        0
#define VIC0_VICVECTADDR9_VECTORADDR9_BITS                         32
#define VIC0_VICVECTADDR9_VECTORADDR9_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICVECTADDR10
 ***************************************************************************/
/* VIC0 :: VICVECTADDR10 :: VectorAddr10 [31:00] */
#define Wr_VIC0_VICVECTADDR10_VectorAddr10(x) WriteReg(VIC0_VICVECTADDR10,x)
#define Rd_VIC0_VICVECTADDR10_VectorAddr10(x) ReadReg(VIC0_VICVECTADDR10)
#define VIC0_VICVECTADDR10_VECTORADDR10_MASK                       0xffffffff
#define VIC0_VICVECTADDR10_VECTORADDR10_ALIGN                      0
#define VIC0_VICVECTADDR10_VECTORADDR10_BITS                       32
#define VIC0_VICVECTADDR10_VECTORADDR10_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR11
 ***************************************************************************/
/* VIC0 :: VICVECTADDR11 :: VectorAddr11 [31:00] */
#define Wr_VIC0_VICVECTADDR11_VectorAddr11(x) WriteReg(VIC0_VICVECTADDR11,x)
#define Rd_VIC0_VICVECTADDR11_VectorAddr11(x) ReadReg(VIC0_VICVECTADDR11)
#define VIC0_VICVECTADDR11_VECTORADDR11_MASK                       0xffffffff
#define VIC0_VICVECTADDR11_VECTORADDR11_ALIGN                      0
#define VIC0_VICVECTADDR11_VECTORADDR11_BITS                       32
#define VIC0_VICVECTADDR11_VECTORADDR11_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR12
 ***************************************************************************/
/* VIC0 :: VICVECTADDR12 :: VectorAddr12 [31:00] */
#define Wr_VIC0_VICVECTADDR12_VectorAddr12(x) WriteReg(VIC0_VICVECTADDR12,x)
#define Rd_VIC0_VICVECTADDR12_VectorAddr12(x) ReadReg(VIC0_VICVECTADDR12)
#define VIC0_VICVECTADDR12_VECTORADDR12_MASK                       0xffffffff
#define VIC0_VICVECTADDR12_VECTORADDR12_ALIGN                      0
#define VIC0_VICVECTADDR12_VECTORADDR12_BITS                       32
#define VIC0_VICVECTADDR12_VECTORADDR12_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR13
 ***************************************************************************/
/* VIC0 :: VICVECTADDR13 :: VectorAddr13 [31:00] */
#define Wr_VIC0_VICVECTADDR13_VectorAddr13(x) WriteReg(VIC0_VICVECTADDR13,x)
#define Rd_VIC0_VICVECTADDR13_VectorAddr13(x) ReadReg(VIC0_VICVECTADDR13)
#define VIC0_VICVECTADDR13_VECTORADDR13_MASK                       0xffffffff
#define VIC0_VICVECTADDR13_VECTORADDR13_ALIGN                      0
#define VIC0_VICVECTADDR13_VECTORADDR13_BITS                       32
#define VIC0_VICVECTADDR13_VECTORADDR13_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR14
 ***************************************************************************/
/* VIC0 :: VICVECTADDR14 :: VectorAddr14 [31:00] */
#define Wr_VIC0_VICVECTADDR14_VectorAddr14(x) WriteReg(VIC0_VICVECTADDR14,x)
#define Rd_VIC0_VICVECTADDR14_VectorAddr14(x) ReadReg(VIC0_VICVECTADDR14)
#define VIC0_VICVECTADDR14_VECTORADDR14_MASK                       0xffffffff
#define VIC0_VICVECTADDR14_VECTORADDR14_ALIGN                      0
#define VIC0_VICVECTADDR14_VECTORADDR14_BITS                       32
#define VIC0_VICVECTADDR14_VECTORADDR14_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR15
 ***************************************************************************/
/* VIC0 :: VICVECTADDR15 :: VectorAddr15 [31:00] */
#define Wr_VIC0_VICVECTADDR15_VectorAddr15(x) WriteReg(VIC0_VICVECTADDR15,x)
#define Rd_VIC0_VICVECTADDR15_VectorAddr15(x) ReadReg(VIC0_VICVECTADDR15)
#define VIC0_VICVECTADDR15_VECTORADDR15_MASK                       0xffffffff
#define VIC0_VICVECTADDR15_VECTORADDR15_ALIGN                      0
#define VIC0_VICVECTADDR15_VECTORADDR15_BITS                       32
#define VIC0_VICVECTADDR15_VECTORADDR15_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR16
 ***************************************************************************/
/* VIC0 :: VICVECTADDR16 :: VectorAddr16 [31:00] */
#define Wr_VIC0_VICVECTADDR16_VectorAddr16(x) WriteReg(VIC0_VICVECTADDR16,x)
#define Rd_VIC0_VICVECTADDR16_VectorAddr16(x) ReadReg(VIC0_VICVECTADDR16)
#define VIC0_VICVECTADDR16_VECTORADDR16_MASK                       0xffffffff
#define VIC0_VICVECTADDR16_VECTORADDR16_ALIGN                      0
#define VIC0_VICVECTADDR16_VECTORADDR16_BITS                       32
#define VIC0_VICVECTADDR16_VECTORADDR16_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR17
 ***************************************************************************/
/* VIC0 :: VICVECTADDR17 :: VectorAddr17 [31:00] */
#define Wr_VIC0_VICVECTADDR17_VectorAddr17(x) WriteReg(VIC0_VICVECTADDR17,x)
#define Rd_VIC0_VICVECTADDR17_VectorAddr17(x) ReadReg(VIC0_VICVECTADDR17)
#define VIC0_VICVECTADDR17_VECTORADDR17_MASK                       0xffffffff
#define VIC0_VICVECTADDR17_VECTORADDR17_ALIGN                      0
#define VIC0_VICVECTADDR17_VECTORADDR17_BITS                       32
#define VIC0_VICVECTADDR17_VECTORADDR17_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR18
 ***************************************************************************/
/* VIC0 :: VICVECTADDR18 :: VectorAddr18 [31:00] */
#define Wr_VIC0_VICVECTADDR18_VectorAddr18(x) WriteReg(VIC0_VICVECTADDR18,x)
#define Rd_VIC0_VICVECTADDR18_VectorAddr18(x) ReadReg(VIC0_VICVECTADDR18)
#define VIC0_VICVECTADDR18_VECTORADDR18_MASK                       0xffffffff
#define VIC0_VICVECTADDR18_VECTORADDR18_ALIGN                      0
#define VIC0_VICVECTADDR18_VECTORADDR18_BITS                       32
#define VIC0_VICVECTADDR18_VECTORADDR18_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR19
 ***************************************************************************/
/* VIC0 :: VICVECTADDR19 :: VectorAddr19 [31:00] */
#define Wr_VIC0_VICVECTADDR19_VectorAddr19(x) WriteReg(VIC0_VICVECTADDR19,x)
#define Rd_VIC0_VICVECTADDR19_VectorAddr19(x) ReadReg(VIC0_VICVECTADDR19)
#define VIC0_VICVECTADDR19_VECTORADDR19_MASK                       0xffffffff
#define VIC0_VICVECTADDR19_VECTORADDR19_ALIGN                      0
#define VIC0_VICVECTADDR19_VECTORADDR19_BITS                       32
#define VIC0_VICVECTADDR19_VECTORADDR19_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR20
 ***************************************************************************/
/* VIC0 :: VICVECTADDR20 :: VectorAddr20 [31:00] */
#define Wr_VIC0_VICVECTADDR20_VectorAddr20(x) WriteReg(VIC0_VICVECTADDR20,x)
#define Rd_VIC0_VICVECTADDR20_VectorAddr20(x) ReadReg(VIC0_VICVECTADDR20)
#define VIC0_VICVECTADDR20_VECTORADDR20_MASK                       0xffffffff
#define VIC0_VICVECTADDR20_VECTORADDR20_ALIGN                      0
#define VIC0_VICVECTADDR20_VECTORADDR20_BITS                       32
#define VIC0_VICVECTADDR20_VECTORADDR20_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR21
 ***************************************************************************/
/* VIC0 :: VICVECTADDR21 :: VectorAddr21 [31:00] */
#define Wr_VIC0_VICVECTADDR21_VectorAddr21(x) WriteReg(VIC0_VICVECTADDR21,x)
#define Rd_VIC0_VICVECTADDR21_VectorAddr21(x) ReadReg(VIC0_VICVECTADDR21)
#define VIC0_VICVECTADDR21_VECTORADDR21_MASK                       0xffffffff
#define VIC0_VICVECTADDR21_VECTORADDR21_ALIGN                      0
#define VIC0_VICVECTADDR21_VECTORADDR21_BITS                       32
#define VIC0_VICVECTADDR21_VECTORADDR21_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR22
 ***************************************************************************/
/* VIC0 :: VICVECTADDR22 :: VectorAddr22 [31:00] */
#define Wr_VIC0_VICVECTADDR22_VectorAddr22(x) WriteReg(VIC0_VICVECTADDR22,x)
#define Rd_VIC0_VICVECTADDR22_VectorAddr22(x) ReadReg(VIC0_VICVECTADDR22)
#define VIC0_VICVECTADDR22_VECTORADDR22_MASK                       0xffffffff
#define VIC0_VICVECTADDR22_VECTORADDR22_ALIGN                      0
#define VIC0_VICVECTADDR22_VECTORADDR22_BITS                       32
#define VIC0_VICVECTADDR22_VECTORADDR22_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR23
 ***************************************************************************/
/* VIC0 :: VICVECTADDR23 :: VectorAddr23 [31:00] */
#define Wr_VIC0_VICVECTADDR23_VectorAddr23(x) WriteReg(VIC0_VICVECTADDR23,x)
#define Rd_VIC0_VICVECTADDR23_VectorAddr23(x) ReadReg(VIC0_VICVECTADDR23)
#define VIC0_VICVECTADDR23_VECTORADDR23_MASK                       0xffffffff
#define VIC0_VICVECTADDR23_VECTORADDR23_ALIGN                      0
#define VIC0_VICVECTADDR23_VECTORADDR23_BITS                       32
#define VIC0_VICVECTADDR23_VECTORADDR23_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR24
 ***************************************************************************/
/* VIC0 :: VICVECTADDR24 :: VectorAddr24 [31:00] */
#define Wr_VIC0_VICVECTADDR24_VectorAddr24(x) WriteReg(VIC0_VICVECTADDR24,x)
#define Rd_VIC0_VICVECTADDR24_VectorAddr24(x) ReadReg(VIC0_VICVECTADDR24)
#define VIC0_VICVECTADDR24_VECTORADDR24_MASK                       0xffffffff
#define VIC0_VICVECTADDR24_VECTORADDR24_ALIGN                      0
#define VIC0_VICVECTADDR24_VECTORADDR24_BITS                       32
#define VIC0_VICVECTADDR24_VECTORADDR24_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR25
 ***************************************************************************/
/* VIC0 :: VICVECTADDR25 :: VectorAddr25 [31:00] */
#define Wr_VIC0_VICVECTADDR25_VectorAddr25(x) WriteReg(VIC0_VICVECTADDR25,x)
#define Rd_VIC0_VICVECTADDR25_VectorAddr25(x) ReadReg(VIC0_VICVECTADDR25)
#define VIC0_VICVECTADDR25_VECTORADDR25_MASK                       0xffffffff
#define VIC0_VICVECTADDR25_VECTORADDR25_ALIGN                      0
#define VIC0_VICVECTADDR25_VECTORADDR25_BITS                       32
#define VIC0_VICVECTADDR25_VECTORADDR25_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR26
 ***************************************************************************/
/* VIC0 :: VICVECTADDR26 :: VectorAddr26 [31:00] */
#define Wr_VIC0_VICVECTADDR26_VectorAddr26(x) WriteReg(VIC0_VICVECTADDR26,x)
#define Rd_VIC0_VICVECTADDR26_VectorAddr26(x) ReadReg(VIC0_VICVECTADDR26)
#define VIC0_VICVECTADDR26_VECTORADDR26_MASK                       0xffffffff
#define VIC0_VICVECTADDR26_VECTORADDR26_ALIGN                      0
#define VIC0_VICVECTADDR26_VECTORADDR26_BITS                       32
#define VIC0_VICVECTADDR26_VECTORADDR26_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR27
 ***************************************************************************/
/* VIC0 :: VICVECTADDR27 :: VectorAddr27 [31:00] */
#define Wr_VIC0_VICVECTADDR27_VectorAddr27(x) WriteReg(VIC0_VICVECTADDR27,x)
#define Rd_VIC0_VICVECTADDR27_VectorAddr27(x) ReadReg(VIC0_VICVECTADDR27)
#define VIC0_VICVECTADDR27_VECTORADDR27_MASK                       0xffffffff
#define VIC0_VICVECTADDR27_VECTORADDR27_ALIGN                      0
#define VIC0_VICVECTADDR27_VECTORADDR27_BITS                       32
#define VIC0_VICVECTADDR27_VECTORADDR27_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR28
 ***************************************************************************/
/* VIC0 :: VICVECTADDR28 :: VectorAddr28 [31:00] */
#define Wr_VIC0_VICVECTADDR28_VectorAddr28(x) WriteReg(VIC0_VICVECTADDR28,x)
#define Rd_VIC0_VICVECTADDR28_VectorAddr28(x) ReadReg(VIC0_VICVECTADDR28)
#define VIC0_VICVECTADDR28_VECTORADDR28_MASK                       0xffffffff
#define VIC0_VICVECTADDR28_VECTORADDR28_ALIGN                      0
#define VIC0_VICVECTADDR28_VECTORADDR28_BITS                       32
#define VIC0_VICVECTADDR28_VECTORADDR28_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR29
 ***************************************************************************/
/* VIC0 :: VICVECTADDR29 :: VectorAddr29 [31:00] */
#define Wr_VIC0_VICVECTADDR29_VectorAddr29(x) WriteReg(VIC0_VICVECTADDR29,x)
#define Rd_VIC0_VICVECTADDR29_VectorAddr29(x) ReadReg(VIC0_VICVECTADDR29)
#define VIC0_VICVECTADDR29_VECTORADDR29_MASK                       0xffffffff
#define VIC0_VICVECTADDR29_VECTORADDR29_ALIGN                      0
#define VIC0_VICVECTADDR29_VECTORADDR29_BITS                       32
#define VIC0_VICVECTADDR29_VECTORADDR29_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR30
 ***************************************************************************/
/* VIC0 :: VICVECTADDR30 :: VectorAddr30 [31:00] */
#define Wr_VIC0_VICVECTADDR30_VectorAddr30(x) WriteReg(VIC0_VICVECTADDR30,x)
#define Rd_VIC0_VICVECTADDR30_VectorAddr30(x) ReadReg(VIC0_VICVECTADDR30)
#define VIC0_VICVECTADDR30_VECTORADDR30_MASK                       0xffffffff
#define VIC0_VICVECTADDR30_VECTORADDR30_ALIGN                      0
#define VIC0_VICVECTADDR30_VECTORADDR30_BITS                       32
#define VIC0_VICVECTADDR30_VECTORADDR30_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTADDR31
 ***************************************************************************/
/* VIC0 :: VICVECTADDR31 :: VectorAddr31 [31:00] */
#define Wr_VIC0_VICVECTADDR31_VectorAddr31(x) WriteReg(VIC0_VICVECTADDR31,x)
#define Rd_VIC0_VICVECTADDR31_VectorAddr31(x) ReadReg(VIC0_VICVECTADDR31)
#define VIC0_VICVECTADDR31_VECTORADDR31_MASK                       0xffffffff
#define VIC0_VICVECTADDR31_VECTORADDR31_ALIGN                      0
#define VIC0_VICVECTADDR31_VECTORADDR31_BITS                       32
#define VIC0_VICVECTADDR31_VECTORADDR31_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY0
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY0 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY0_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY0_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY0_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY0_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY0 :: VectPriority0 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY0_VectPriority0(x) WriteRegBits(VIC0_VICVECTPRIORITY0,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY0_VectPriority0(x) ReadRegBits(VIC0_VICVECTPRIORITY0,0xf,0)
#define VIC0_VICVECTPRIORITY0_VECTPRIORITY0_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY0_VECTPRIORITY0_ALIGN                  0
#define VIC0_VICVECTPRIORITY0_VECTPRIORITY0_BITS                   4
#define VIC0_VICVECTPRIORITY0_VECTPRIORITY0_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY1
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY1 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY1_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY1_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY1_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY1_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY1 :: VectPriority1 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY1_VectPriority1(x) WriteRegBits(VIC0_VICVECTPRIORITY1,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY1_VectPriority1(x) ReadRegBits(VIC0_VICVECTPRIORITY1,0xf,0)
#define VIC0_VICVECTPRIORITY1_VECTPRIORITY1_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY1_VECTPRIORITY1_ALIGN                  0
#define VIC0_VICVECTPRIORITY1_VECTPRIORITY1_BITS                   4
#define VIC0_VICVECTPRIORITY1_VECTPRIORITY1_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY2
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY2 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY2_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY2_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY2_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY2_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY2 :: VectPriority2 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY2_VectPriority2(x) WriteRegBits(VIC0_VICVECTPRIORITY2,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY2_VectPriority2(x) ReadRegBits(VIC0_VICVECTPRIORITY2,0xf,0)
#define VIC0_VICVECTPRIORITY2_VECTPRIORITY2_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY2_VECTPRIORITY2_ALIGN                  0
#define VIC0_VICVECTPRIORITY2_VECTPRIORITY2_BITS                   4
#define VIC0_VICVECTPRIORITY2_VECTPRIORITY2_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY3
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY3 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY3_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY3_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY3_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY3_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY3 :: VectPriority3 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY3_VectPriority3(x) WriteRegBits(VIC0_VICVECTPRIORITY3,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY3_VectPriority3(x) ReadRegBits(VIC0_VICVECTPRIORITY3,0xf,0)
#define VIC0_VICVECTPRIORITY3_VECTPRIORITY3_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY3_VECTPRIORITY3_ALIGN                  0
#define VIC0_VICVECTPRIORITY3_VECTPRIORITY3_BITS                   4
#define VIC0_VICVECTPRIORITY3_VECTPRIORITY3_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY4
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY4 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY4_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY4_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY4_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY4_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY4 :: VectPriority4 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY4_VectPriority4(x) WriteRegBits(VIC0_VICVECTPRIORITY4,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY4_VectPriority4(x) ReadRegBits(VIC0_VICVECTPRIORITY4,0xf,0)
#define VIC0_VICVECTPRIORITY4_VECTPRIORITY4_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY4_VECTPRIORITY4_ALIGN                  0
#define VIC0_VICVECTPRIORITY4_VECTPRIORITY4_BITS                   4
#define VIC0_VICVECTPRIORITY4_VECTPRIORITY4_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY5
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY5 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY5_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY5_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY5_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY5_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY5 :: VectPriority5 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY5_VectPriority5(x) WriteRegBits(VIC0_VICVECTPRIORITY5,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY5_VectPriority5(x) ReadRegBits(VIC0_VICVECTPRIORITY5,0xf,0)
#define VIC0_VICVECTPRIORITY5_VECTPRIORITY5_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY5_VECTPRIORITY5_ALIGN                  0
#define VIC0_VICVECTPRIORITY5_VECTPRIORITY5_BITS                   4
#define VIC0_VICVECTPRIORITY5_VECTPRIORITY5_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY6
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY6 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY6_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY6_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY6_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY6_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY6 :: VectPriority6 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY6_VectPriority6(x) WriteRegBits(VIC0_VICVECTPRIORITY6,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY6_VectPriority6(x) ReadRegBits(VIC0_VICVECTPRIORITY6,0xf,0)
#define VIC0_VICVECTPRIORITY6_VECTPRIORITY6_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY6_VECTPRIORITY6_ALIGN                  0
#define VIC0_VICVECTPRIORITY6_VECTPRIORITY6_BITS                   4
#define VIC0_VICVECTPRIORITY6_VECTPRIORITY6_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY7
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY7 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY7_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY7_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY7_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY7_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY7 :: VectPriority7 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY7_VectPriority7(x) WriteRegBits(VIC0_VICVECTPRIORITY7,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY7_VectPriority7(x) ReadRegBits(VIC0_VICVECTPRIORITY7,0xf,0)
#define VIC0_VICVECTPRIORITY7_VECTPRIORITY7_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY7_VECTPRIORITY7_ALIGN                  0
#define VIC0_VICVECTPRIORITY7_VECTPRIORITY7_BITS                   4
#define VIC0_VICVECTPRIORITY7_VECTPRIORITY7_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY8
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY8 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY8_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY8_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY8_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY8_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY8 :: VectPriority8 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY8_VectPriority8(x) WriteRegBits(VIC0_VICVECTPRIORITY8,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY8_VectPriority8(x) ReadRegBits(VIC0_VICVECTPRIORITY8,0xf,0)
#define VIC0_VICVECTPRIORITY8_VECTPRIORITY8_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY8_VECTPRIORITY8_ALIGN                  0
#define VIC0_VICVECTPRIORITY8_VECTPRIORITY8_BITS                   4
#define VIC0_VICVECTPRIORITY8_VECTPRIORITY8_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY9
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY9 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY9_RESERVED0_MASK                       0xfffffff0
#define VIC0_VICVECTPRIORITY9_RESERVED0_ALIGN                      0
#define VIC0_VICVECTPRIORITY9_RESERVED0_BITS                       28
#define VIC0_VICVECTPRIORITY9_RESERVED0_SHIFT                      4

/* VIC0 :: VICVECTPRIORITY9 :: VectPriority9 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY9_VectPriority9(x) WriteRegBits(VIC0_VICVECTPRIORITY9,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY9_VectPriority9(x) ReadRegBits(VIC0_VICVECTPRIORITY9,0xf,0)
#define VIC0_VICVECTPRIORITY9_VECTPRIORITY9_MASK                   0x0000000f
#define VIC0_VICVECTPRIORITY9_VECTPRIORITY9_ALIGN                  0
#define VIC0_VICVECTPRIORITY9_VECTPRIORITY9_BITS                   4
#define VIC0_VICVECTPRIORITY9_VECTPRIORITY9_SHIFT                  0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY10
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY10 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY10_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY10_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY10_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY10_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY10 :: VectPriority10 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY10_VectPriority10(x) WriteRegBits(VIC0_VICVECTPRIORITY10,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY10_VectPriority10(x) ReadRegBits(VIC0_VICVECTPRIORITY10,0xf,0)
#define VIC0_VICVECTPRIORITY10_VECTPRIORITY10_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY10_VECTPRIORITY10_ALIGN                0
#define VIC0_VICVECTPRIORITY10_VECTPRIORITY10_BITS                 4
#define VIC0_VICVECTPRIORITY10_VECTPRIORITY10_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY11
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY11 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY11_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY11_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY11_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY11_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY11 :: VectPriority11 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY11_VectPriority11(x) WriteRegBits(VIC0_VICVECTPRIORITY11,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY11_VectPriority11(x) ReadRegBits(VIC0_VICVECTPRIORITY11,0xf,0)
#define VIC0_VICVECTPRIORITY11_VECTPRIORITY11_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY11_VECTPRIORITY11_ALIGN                0
#define VIC0_VICVECTPRIORITY11_VECTPRIORITY11_BITS                 4
#define VIC0_VICVECTPRIORITY11_VECTPRIORITY11_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY12
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY12 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY12_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY12_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY12_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY12_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY12 :: VectPriority12 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY12_VectPriority12(x) WriteRegBits(VIC0_VICVECTPRIORITY12,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY12_VectPriority12(x) ReadRegBits(VIC0_VICVECTPRIORITY12,0xf,0)
#define VIC0_VICVECTPRIORITY12_VECTPRIORITY12_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY12_VECTPRIORITY12_ALIGN                0
#define VIC0_VICVECTPRIORITY12_VECTPRIORITY12_BITS                 4
#define VIC0_VICVECTPRIORITY12_VECTPRIORITY12_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY13
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY13 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY13_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY13_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY13_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY13_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY13 :: VectPriority13 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY13_VectPriority13(x) WriteRegBits(VIC0_VICVECTPRIORITY13,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY13_VectPriority13(x) ReadRegBits(VIC0_VICVECTPRIORITY13,0xf,0)
#define VIC0_VICVECTPRIORITY13_VECTPRIORITY13_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY13_VECTPRIORITY13_ALIGN                0
#define VIC0_VICVECTPRIORITY13_VECTPRIORITY13_BITS                 4
#define VIC0_VICVECTPRIORITY13_VECTPRIORITY13_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY14
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY14 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY14_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY14_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY14_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY14_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY14 :: VectPriority14 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY14_VectPriority14(x) WriteRegBits(VIC0_VICVECTPRIORITY14,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY14_VectPriority14(x) ReadRegBits(VIC0_VICVECTPRIORITY14,0xf,0)
#define VIC0_VICVECTPRIORITY14_VECTPRIORITY14_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY14_VECTPRIORITY14_ALIGN                0
#define VIC0_VICVECTPRIORITY14_VECTPRIORITY14_BITS                 4
#define VIC0_VICVECTPRIORITY14_VECTPRIORITY14_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY15
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY15 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY15_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY15_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY15_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY15_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY15 :: VectPriority15 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY15_VectPriority15(x) WriteRegBits(VIC0_VICVECTPRIORITY15,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY15_VectPriority15(x) ReadRegBits(VIC0_VICVECTPRIORITY15,0xf,0)
#define VIC0_VICVECTPRIORITY15_VECTPRIORITY15_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY15_VECTPRIORITY15_ALIGN                0
#define VIC0_VICVECTPRIORITY15_VECTPRIORITY15_BITS                 4
#define VIC0_VICVECTPRIORITY15_VECTPRIORITY15_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY16
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY16 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY16_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY16_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY16_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY16_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY16 :: VectPriority16 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY16_VectPriority16(x) WriteRegBits(VIC0_VICVECTPRIORITY16,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY16_VectPriority16(x) ReadRegBits(VIC0_VICVECTPRIORITY16,0xf,0)
#define VIC0_VICVECTPRIORITY16_VECTPRIORITY16_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY16_VECTPRIORITY16_ALIGN                0
#define VIC0_VICVECTPRIORITY16_VECTPRIORITY16_BITS                 4
#define VIC0_VICVECTPRIORITY16_VECTPRIORITY16_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY17
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY17 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY17_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY17_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY17_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY17_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY17 :: VectPriority17 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY17_VectPriority17(x) WriteRegBits(VIC0_VICVECTPRIORITY17,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY17_VectPriority17(x) ReadRegBits(VIC0_VICVECTPRIORITY17,0xf,0)
#define VIC0_VICVECTPRIORITY17_VECTPRIORITY17_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY17_VECTPRIORITY17_ALIGN                0
#define VIC0_VICVECTPRIORITY17_VECTPRIORITY17_BITS                 4
#define VIC0_VICVECTPRIORITY17_VECTPRIORITY17_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY18
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY18 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY18_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY18_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY18_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY18_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY18 :: VectPriority18 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY18_VectPriority18(x) WriteRegBits(VIC0_VICVECTPRIORITY18,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY18_VectPriority18(x) ReadRegBits(VIC0_VICVECTPRIORITY18,0xf,0)
#define VIC0_VICVECTPRIORITY18_VECTPRIORITY18_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY18_VECTPRIORITY18_ALIGN                0
#define VIC0_VICVECTPRIORITY18_VECTPRIORITY18_BITS                 4
#define VIC0_VICVECTPRIORITY18_VECTPRIORITY18_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY19
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY19 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY19_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY19_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY19_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY19_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY19 :: VectPriority19 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY19_VectPriority19(x) WriteRegBits(VIC0_VICVECTPRIORITY19,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY19_VectPriority19(x) ReadRegBits(VIC0_VICVECTPRIORITY19,0xf,0)
#define VIC0_VICVECTPRIORITY19_VECTPRIORITY19_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY19_VECTPRIORITY19_ALIGN                0
#define VIC0_VICVECTPRIORITY19_VECTPRIORITY19_BITS                 4
#define VIC0_VICVECTPRIORITY19_VECTPRIORITY19_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY20
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY20 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY20_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY20_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY20_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY20_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY20 :: VectPriority20 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY20_VectPriority20(x) WriteRegBits(VIC0_VICVECTPRIORITY20,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY20_VectPriority20(x) ReadRegBits(VIC0_VICVECTPRIORITY20,0xf,0)
#define VIC0_VICVECTPRIORITY20_VECTPRIORITY20_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY20_VECTPRIORITY20_ALIGN                0
#define VIC0_VICVECTPRIORITY20_VECTPRIORITY20_BITS                 4
#define VIC0_VICVECTPRIORITY20_VECTPRIORITY20_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY21
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY21 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY21_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY21_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY21_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY21_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY21 :: VectPriority21 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY21_VectPriority21(x) WriteRegBits(VIC0_VICVECTPRIORITY21,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY21_VectPriority21(x) ReadRegBits(VIC0_VICVECTPRIORITY21,0xf,0)
#define VIC0_VICVECTPRIORITY21_VECTPRIORITY21_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY21_VECTPRIORITY21_ALIGN                0
#define VIC0_VICVECTPRIORITY21_VECTPRIORITY21_BITS                 4
#define VIC0_VICVECTPRIORITY21_VECTPRIORITY21_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY22
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY22 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY22_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY22_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY22_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY22_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY22 :: VectPriority22 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY22_VectPriority22(x) WriteRegBits(VIC0_VICVECTPRIORITY22,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY22_VectPriority22(x) ReadRegBits(VIC0_VICVECTPRIORITY22,0xf,0)
#define VIC0_VICVECTPRIORITY22_VECTPRIORITY22_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY22_VECTPRIORITY22_ALIGN                0
#define VIC0_VICVECTPRIORITY22_VECTPRIORITY22_BITS                 4
#define VIC0_VICVECTPRIORITY22_VECTPRIORITY22_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY23
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY23 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY23_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY23_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY23_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY23_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY23 :: VectPriority23 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY23_VectPriority23(x) WriteRegBits(VIC0_VICVECTPRIORITY23,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY23_VectPriority23(x) ReadRegBits(VIC0_VICVECTPRIORITY23,0xf,0)
#define VIC0_VICVECTPRIORITY23_VECTPRIORITY23_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY23_VECTPRIORITY23_ALIGN                0
#define VIC0_VICVECTPRIORITY23_VECTPRIORITY23_BITS                 4
#define VIC0_VICVECTPRIORITY23_VECTPRIORITY23_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY24
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY24 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY24_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY24_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY24_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY24_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY24 :: VectPriority24 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY24_VectPriority24(x) WriteRegBits(VIC0_VICVECTPRIORITY24,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY24_VectPriority24(x) ReadRegBits(VIC0_VICVECTPRIORITY24,0xf,0)
#define VIC0_VICVECTPRIORITY24_VECTPRIORITY24_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY24_VECTPRIORITY24_ALIGN                0
#define VIC0_VICVECTPRIORITY24_VECTPRIORITY24_BITS                 4
#define VIC0_VICVECTPRIORITY24_VECTPRIORITY24_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY25
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY25 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY25_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY25_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY25_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY25_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY25 :: VectPriority25 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY25_VectPriority25(x) WriteRegBits(VIC0_VICVECTPRIORITY25,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY25_VectPriority25(x) ReadRegBits(VIC0_VICVECTPRIORITY25,0xf,0)
#define VIC0_VICVECTPRIORITY25_VECTPRIORITY25_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY25_VECTPRIORITY25_ALIGN                0
#define VIC0_VICVECTPRIORITY25_VECTPRIORITY25_BITS                 4
#define VIC0_VICVECTPRIORITY25_VECTPRIORITY25_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY26
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY26 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY26_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY26_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY26_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY26_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY26 :: VectPriority26 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY26_VectPriority26(x) WriteRegBits(VIC0_VICVECTPRIORITY26,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY26_VectPriority26(x) ReadRegBits(VIC0_VICVECTPRIORITY26,0xf,0)
#define VIC0_VICVECTPRIORITY26_VECTPRIORITY26_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY26_VECTPRIORITY26_ALIGN                0
#define VIC0_VICVECTPRIORITY26_VECTPRIORITY26_BITS                 4
#define VIC0_VICVECTPRIORITY26_VECTPRIORITY26_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY27
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY27 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY27_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY27_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY27_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY27_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY27 :: VectPriority27 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY27_VectPriority27(x) WriteRegBits(VIC0_VICVECTPRIORITY27,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY27_VectPriority27(x) ReadRegBits(VIC0_VICVECTPRIORITY27,0xf,0)
#define VIC0_VICVECTPRIORITY27_VECTPRIORITY27_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY27_VECTPRIORITY27_ALIGN                0
#define VIC0_VICVECTPRIORITY27_VECTPRIORITY27_BITS                 4
#define VIC0_VICVECTPRIORITY27_VECTPRIORITY27_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY28
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY28 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY28_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY28_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY28_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY28_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY28 :: VectPriority28 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY28_VectPriority28(x) WriteRegBits(VIC0_VICVECTPRIORITY28,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY28_VectPriority28(x) ReadRegBits(VIC0_VICVECTPRIORITY28,0xf,0)
#define VIC0_VICVECTPRIORITY28_VECTPRIORITY28_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY28_VECTPRIORITY28_ALIGN                0
#define VIC0_VICVECTPRIORITY28_VECTPRIORITY28_BITS                 4
#define VIC0_VICVECTPRIORITY28_VECTPRIORITY28_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY29
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY29 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY29_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY29_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY29_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY29_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY29 :: VectPriority29 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY29_VectPriority29(x) WriteRegBits(VIC0_VICVECTPRIORITY29,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY29_VectPriority29(x) ReadRegBits(VIC0_VICVECTPRIORITY29,0xf,0)
#define VIC0_VICVECTPRIORITY29_VECTPRIORITY29_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY29_VECTPRIORITY29_ALIGN                0
#define VIC0_VICVECTPRIORITY29_VECTPRIORITY29_BITS                 4
#define VIC0_VICVECTPRIORITY29_VECTPRIORITY29_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY30
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY30 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY30_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY30_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY30_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY30_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY30 :: VectPriority30 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY30_VectPriority30(x) WriteRegBits(VIC0_VICVECTPRIORITY30,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY30_VectPriority30(x) ReadRegBits(VIC0_VICVECTPRIORITY30,0xf,0)
#define VIC0_VICVECTPRIORITY30_VECTPRIORITY30_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY30_VECTPRIORITY30_ALIGN                0
#define VIC0_VICVECTPRIORITY30_VECTPRIORITY30_BITS                 4
#define VIC0_VICVECTPRIORITY30_VECTPRIORITY30_SHIFT                0


/****************************************************************************
 * VIC0 :: VICVECTPRIORITY31
 ***************************************************************************/
/* VIC0 :: VICVECTPRIORITY31 :: reserved0 [31:04] */
#define VIC0_VICVECTPRIORITY31_RESERVED0_MASK                      0xfffffff0
#define VIC0_VICVECTPRIORITY31_RESERVED0_ALIGN                     0
#define VIC0_VICVECTPRIORITY31_RESERVED0_BITS                      28
#define VIC0_VICVECTPRIORITY31_RESERVED0_SHIFT                     4

/* VIC0 :: VICVECTPRIORITY31 :: VectPriority31 [03:00] */
#define Wr_VIC0_VICVECTPRIORITY31_VectPriority31(x) WriteRegBits(VIC0_VICVECTPRIORITY31,0xf,0,x)
#define Rd_VIC0_VICVECTPRIORITY31_VectPriority31(x) ReadRegBits(VIC0_VICVECTPRIORITY31,0xf,0)
#define VIC0_VICVECTPRIORITY31_VECTPRIORITY31_MASK                 0x0000000f
#define VIC0_VICVECTPRIORITY31_VECTPRIORITY31_ALIGN                0
#define VIC0_VICVECTPRIORITY31_VECTPRIORITY31_BITS                 4
#define VIC0_VICVECTPRIORITY31_VECTPRIORITY31_SHIFT                0


/****************************************************************************
 * VIC0 :: VICADDRESS
 ***************************************************************************/
/* VIC0 :: VICADDRESS :: VectorAddr [31:00] */
#define Wr_VIC0_VICADDRESS_VectorAddr(x) WriteReg(VIC0_VICADDRESS,x)
#define Rd_VIC0_VICADDRESS_VectorAddr(x) ReadReg(VIC0_VICADDRESS)
#define VIC0_VICADDRESS_VECTORADDR_MASK                            0xffffffff
#define VIC0_VICADDRESS_VECTORADDR_ALIGN                           0
#define VIC0_VICADDRESS_VECTORADDR_BITS                            32
#define VIC0_VICADDRESS_VECTORADDR_SHIFT                           0


/****************************************************************************
 * VIC0 :: VICPERIPHID0
 ***************************************************************************/
/* VIC0 :: VICPERIPHID0 :: reserved0 [31:08] */
#define VIC0_VICPERIPHID0_RESERVED0_MASK                           0xffffff00
#define VIC0_VICPERIPHID0_RESERVED0_ALIGN                          0
#define VIC0_VICPERIPHID0_RESERVED0_BITS                           24
#define VIC0_VICPERIPHID0_RESERVED0_SHIFT                          8

/* VIC0 :: VICPERIPHID0 :: Partnumber0 [07:00] */
#define Wr_VIC0_VICPERIPHID0_Partnumber0(x) WriteRegBits(VIC0_VICPERIPHID0,0xff,0,x)
#define Rd_VIC0_VICPERIPHID0_Partnumber0(x) ReadRegBits(VIC0_VICPERIPHID0,0xff,0)
#define VIC0_VICPERIPHID0_PARTNUMBER0_MASK                         0x000000ff
#define VIC0_VICPERIPHID0_PARTNUMBER0_ALIGN                        0
#define VIC0_VICPERIPHID0_PARTNUMBER0_BITS                         8
#define VIC0_VICPERIPHID0_PARTNUMBER0_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICPERIPHID1
 ***************************************************************************/
/* VIC0 :: VICPERIPHID1 :: reserved0 [31:08] */
#define VIC0_VICPERIPHID1_RESERVED0_MASK                           0xffffff00
#define VIC0_VICPERIPHID1_RESERVED0_ALIGN                          0
#define VIC0_VICPERIPHID1_RESERVED0_BITS                           24
#define VIC0_VICPERIPHID1_RESERVED0_SHIFT                          8

/* VIC0 :: VICPERIPHID1 :: Designer0 [07:04] */
#define Wr_VIC0_VICPERIPHID1_Designer0(x) WriteRegBits(VIC0_VICPERIPHID1,0xf0,4,x)
#define Rd_VIC0_VICPERIPHID1_Designer0(x) ReadRegBits(VIC0_VICPERIPHID1,0xf0,4)
#define VIC0_VICPERIPHID1_DESIGNER0_MASK                           0x000000f0
#define VIC0_VICPERIPHID1_DESIGNER0_ALIGN                          0
#define VIC0_VICPERIPHID1_DESIGNER0_BITS                           4
#define VIC0_VICPERIPHID1_DESIGNER0_SHIFT                          4

/* VIC0 :: VICPERIPHID1 :: Partnumber1 [03:00] */
#define Wr_VIC0_VICPERIPHID1_Partnumber1(x) WriteRegBits(VIC0_VICPERIPHID1,0xf,0,x)
#define Rd_VIC0_VICPERIPHID1_Partnumber1(x) ReadRegBits(VIC0_VICPERIPHID1,0xf,0)
#define VIC0_VICPERIPHID1_PARTNUMBER1_MASK                         0x0000000f
#define VIC0_VICPERIPHID1_PARTNUMBER1_ALIGN                        0
#define VIC0_VICPERIPHID1_PARTNUMBER1_BITS                         4
#define VIC0_VICPERIPHID1_PARTNUMBER1_SHIFT                        0


/****************************************************************************
 * VIC0 :: VICPERIPHID2
 ***************************************************************************/
/* VIC0 :: VICPERIPHID2 :: reserved0 [31:08] */
#define VIC0_VICPERIPHID2_RESERVED0_MASK                           0xffffff00
#define VIC0_VICPERIPHID2_RESERVED0_ALIGN                          0
#define VIC0_VICPERIPHID2_RESERVED0_BITS                           24
#define VIC0_VICPERIPHID2_RESERVED0_SHIFT                          8

/* VIC0 :: VICPERIPHID2 :: Revision [07:04] */
#define Wr_VIC0_VICPERIPHID2_Revision(x) WriteRegBits(VIC0_VICPERIPHID2,0xf0,4,x)
#define Rd_VIC0_VICPERIPHID2_Revision(x) ReadRegBits(VIC0_VICPERIPHID2,0xf0,4)
#define VIC0_VICPERIPHID2_REVISION_MASK                            0x000000f0
#define VIC0_VICPERIPHID2_REVISION_ALIGN                           0
#define VIC0_VICPERIPHID2_REVISION_BITS                            4
#define VIC0_VICPERIPHID2_REVISION_SHIFT                           4

/* VIC0 :: VICPERIPHID2 :: Designer1 [03:00] */
#define Wr_VIC0_VICPERIPHID2_Designer1(x) WriteRegBits(VIC0_VICPERIPHID2,0xf,0,x)
#define Rd_VIC0_VICPERIPHID2_Designer1(x) ReadRegBits(VIC0_VICPERIPHID2,0xf,0)
#define VIC0_VICPERIPHID2_DESIGNER1_MASK                           0x0000000f
#define VIC0_VICPERIPHID2_DESIGNER1_ALIGN                          0
#define VIC0_VICPERIPHID2_DESIGNER1_BITS                           4
#define VIC0_VICPERIPHID2_DESIGNER1_SHIFT                          0


/****************************************************************************
 * VIC0 :: VICPERIPHID3
 ***************************************************************************/
/* VIC0 :: VICPERIPHID3 :: reserved0 [31:08] */
#define VIC0_VICPERIPHID3_RESERVED0_MASK                           0xffffff00
#define VIC0_VICPERIPHID3_RESERVED0_ALIGN                          0
#define VIC0_VICPERIPHID3_RESERVED0_BITS                           24
#define VIC0_VICPERIPHID3_RESERVED0_SHIFT                          8

/* VIC0 :: VICPERIPHID3 :: Configuration [07:00] */
#define Wr_VIC0_VICPERIPHID3_Configuration(x) WriteRegBits(VIC0_VICPERIPHID3,0xff,0,x)
#define Rd_VIC0_VICPERIPHID3_Configuration(x) ReadRegBits(VIC0_VICPERIPHID3,0xff,0)
#define VIC0_VICPERIPHID3_CONFIGURATION_MASK                       0x000000ff
#define VIC0_VICPERIPHID3_CONFIGURATION_ALIGN                      0
#define VIC0_VICPERIPHID3_CONFIGURATION_BITS                       8
#define VIC0_VICPERIPHID3_CONFIGURATION_SHIFT                      0


/****************************************************************************
 * VIC0 :: VICPCELLID0
 ***************************************************************************/
/* VIC0 :: VICPCELLID0 :: reserved0 [31:08] */
#define VIC0_VICPCELLID0_RESERVED0_MASK                            0xffffff00
#define VIC0_VICPCELLID0_RESERVED0_ALIGN                           0
#define VIC0_VICPCELLID0_RESERVED0_BITS                            24
#define VIC0_VICPCELLID0_RESERVED0_SHIFT                           8

/* VIC0 :: VICPCELLID0 :: VICPCellID0 [07:00] */
#define Wr_VIC0_VICPCELLID0_VICPCellID0(x) WriteRegBits(VIC0_VICPCELLID0,0xff,0,x)
#define Rd_VIC0_VICPCELLID0_VICPCellID0(x) ReadRegBits(VIC0_VICPCELLID0,0xff,0)
#define VIC0_VICPCELLID0_VICPCELLID0_MASK                          0x000000ff
#define VIC0_VICPCELLID0_VICPCELLID0_ALIGN                         0
#define VIC0_VICPCELLID0_VICPCELLID0_BITS                          8
#define VIC0_VICPCELLID0_VICPCELLID0_SHIFT                         0


/****************************************************************************
 * VIC0 :: VICPCELLID1
 ***************************************************************************/
/* VIC0 :: VICPCELLID1 :: reserved0 [31:08] */
#define VIC0_VICPCELLID1_RESERVED0_MASK                            0xffffff00
#define VIC0_VICPCELLID1_RESERVED0_ALIGN                           0
#define VIC0_VICPCELLID1_RESERVED0_BITS                            24
#define VIC0_VICPCELLID1_RESERVED0_SHIFT                           8

/* VIC0 :: VICPCELLID1 :: VICPCellID1 [07:00] */
#define Wr_VIC0_VICPCELLID1_VICPCellID1(x) WriteRegBits(VIC0_VICPCELLID1,0xff,0,x)
#define Rd_VIC0_VICPCELLID1_VICPCellID1(x) ReadRegBits(VIC0_VICPCELLID1,0xff,0)
#define VIC0_VICPCELLID1_VICPCELLID1_MASK                          0x000000ff
#define VIC0_VICPCELLID1_VICPCELLID1_ALIGN                         0
#define VIC0_VICPCELLID1_VICPCELLID1_BITS                          8
#define VIC0_VICPCELLID1_VICPCELLID1_SHIFT                         0


/****************************************************************************
 * VIC0 :: VICPCELLID2
 ***************************************************************************/
/* VIC0 :: VICPCELLID2 :: reserved0 [31:08] */
#define VIC0_VICPCELLID2_RESERVED0_MASK                            0xffffff00
#define VIC0_VICPCELLID2_RESERVED0_ALIGN                           0
#define VIC0_VICPCELLID2_RESERVED0_BITS                            24
#define VIC0_VICPCELLID2_RESERVED0_SHIFT                           8

/* VIC0 :: VICPCELLID2 :: VICPCellID2 [07:00] */
#define Wr_VIC0_VICPCELLID2_VICPCellID2(x) WriteRegBits(VIC0_VICPCELLID2,0xff,0,x)
#define Rd_VIC0_VICPCELLID2_VICPCellID2(x) ReadRegBits(VIC0_VICPCELLID2,0xff,0)
#define VIC0_VICPCELLID2_VICPCELLID2_MASK                          0x000000ff
#define VIC0_VICPCELLID2_VICPCELLID2_ALIGN                         0
#define VIC0_VICPCELLID2_VICPCELLID2_BITS                          8
#define VIC0_VICPCELLID2_VICPCELLID2_SHIFT                         0


/****************************************************************************
 * VIC0 :: VICPCELLID3
 ***************************************************************************/
/* VIC0 :: VICPCELLID3 :: reserved0 [31:08] */
#define VIC0_VICPCELLID3_RESERVED0_MASK                            0xffffff00
#define VIC0_VICPCELLID3_RESERVED0_ALIGN                           0
#define VIC0_VICPCELLID3_RESERVED0_BITS                            24
#define VIC0_VICPCELLID3_RESERVED0_SHIFT                           8

/* VIC0 :: VICPCELLID3 :: VICPCellID3 [07:00] */
#define Wr_VIC0_VICPCELLID3_VICPCellID3(x) WriteRegBits(VIC0_VICPCELLID3,0xff,0,x)
#define Rd_VIC0_VICPCELLID3_VICPCellID3(x) ReadRegBits(VIC0_VICPCELLID3,0xff,0)
#define VIC0_VICPCELLID3_VICPCELLID3_MASK                          0x000000ff
#define VIC0_VICPCELLID3_VICPCELLID3_ALIGN                         0
#define VIC0_VICPCELLID3_VICPCELLID3_BITS                          8
#define VIC0_VICPCELLID3_VICPCELLID3_SHIFT                         0


/****************************************************************************
 * bcm89530_sys_cfg_SBM
 ***************************************************************************/
/****************************************************************************
 * SBM :: CNT_CTRL
 ***************************************************************************/
/* SBM :: CNT_CTRL :: reserved0 [31:02] */
#define SBM_CNT_CTRL_RESERVED0_MASK                                0xfffffffc
#define SBM_CNT_CTRL_RESERVED0_ALIGN                               0
#define SBM_CNT_CTRL_RESERVED0_BITS                                30
#define SBM_CNT_CTRL_RESERVED0_SHIFT                               2

/* SBM :: CNT_CTRL :: CntDn32KhzEn [01:01] */
#define Wr_SBM_CNT_CTRL_CntDn32KhzEn(x) WriteRegBits(SBM_CNT_CTRL,0x2,1,x)
#define Rd_SBM_CNT_CTRL_CntDn32KhzEn(x) ReadRegBits(SBM_CNT_CTRL,0x2,1)
#define SBM_CNT_CTRL_CNTDN32KHZEN_MASK                             0x00000002
#define SBM_CNT_CTRL_CNTDN32KHZEN_ALIGN                            0
#define SBM_CNT_CTRL_CNTDN32KHZEN_BITS                             1
#define SBM_CNT_CTRL_CNTDN32KHZEN_SHIFT                            1

/* SBM :: CNT_CTRL :: reserved1 [00:00] */
#define SBM_CNT_CTRL_RESERVED1_MASK                                0x00000001
#define SBM_CNT_CTRL_RESERVED1_ALIGN                               0
#define SBM_CNT_CTRL_RESERVED1_BITS                                1
#define SBM_CNT_CTRL_RESERVED1_SHIFT                               0


/****************************************************************************
 * SBM :: CMUX_CTRL
 ***************************************************************************/
/* SBM :: CMUX_CTRL :: reserved0 [31:16] */
#define SBM_CMUX_CTRL_RESERVED0_MASK                               0xffff0000
#define SBM_CMUX_CTRL_RESERVED0_ALIGN                              0
#define SBM_CMUX_CTRL_RESERVED0_BITS                               16
#define SBM_CMUX_CTRL_RESERVED0_SHIFT                              16

/* SBM :: CMUX_CTRL :: MasterSelCnt1 [15:12] */
#define Wr_SBM_CMUX_CTRL_MasterSelCnt1(x) WriteRegBits(SBM_CMUX_CTRL,0xf000,12,x)
#define Rd_SBM_CMUX_CTRL_MasterSelCnt1(x) ReadRegBits(SBM_CMUX_CTRL,0xf000,12)
#define SBM_CMUX_CTRL_MASTERSELCNT1_MASK                           0x0000f000
#define SBM_CMUX_CTRL_MASTERSELCNT1_ALIGN                          0
#define SBM_CMUX_CTRL_MASTERSELCNT1_BITS                           4
#define SBM_CMUX_CTRL_MASTERSELCNT1_SHIFT                          12

/* SBM :: CMUX_CTRL :: SlaveSelCnt1 [11:08] */
#define Wr_SBM_CMUX_CTRL_SlaveSelCnt1(x) WriteRegBits(SBM_CMUX_CTRL,0xf00,8,x)
#define Rd_SBM_CMUX_CTRL_SlaveSelCnt1(x) ReadRegBits(SBM_CMUX_CTRL,0xf00,8)
#define SBM_CMUX_CTRL_SLAVESELCNT1_MASK                            0x00000f00
#define SBM_CMUX_CTRL_SLAVESELCNT1_ALIGN                           0
#define SBM_CMUX_CTRL_SLAVESELCNT1_BITS                            4
#define SBM_CMUX_CTRL_SLAVESELCNT1_SHIFT                           8

/* SBM :: CMUX_CTRL :: MasterSelCnt0 [07:04] */
#define Wr_SBM_CMUX_CTRL_MasterSelCnt0(x) WriteRegBits(SBM_CMUX_CTRL,0xf0,4,x)
#define Rd_SBM_CMUX_CTRL_MasterSelCnt0(x) ReadRegBits(SBM_CMUX_CTRL,0xf0,4)
#define SBM_CMUX_CTRL_MASTERSELCNT0_MASK                           0x000000f0
#define SBM_CMUX_CTRL_MASTERSELCNT0_ALIGN                          0
#define SBM_CMUX_CTRL_MASTERSELCNT0_BITS                           4
#define SBM_CMUX_CTRL_MASTERSELCNT0_SHIFT                          4

/* SBM :: CMUX_CTRL :: SlaveSelCnt0 [03:00] */
#define Wr_SBM_CMUX_CTRL_SlaveSelCnt0(x) WriteRegBits(SBM_CMUX_CTRL,0xf,0,x)
#define Rd_SBM_CMUX_CTRL_SlaveSelCnt0(x) ReadRegBits(SBM_CMUX_CTRL,0xf,0)
#define SBM_CMUX_CTRL_SLAVESELCNT0_MASK                            0x0000000f
#define SBM_CMUX_CTRL_SLAVESELCNT0_ALIGN                           0
#define SBM_CMUX_CTRL_SLAVESELCNT0_BITS                            4
#define SBM_CMUX_CTRL_SLAVESELCNT0_SHIFT                           0


/****************************************************************************
 * SBM :: CNT_32K
 ***************************************************************************/
/* SBM :: CNT_32K :: ClockCnt32Khz [31:00] */
#define Wr_SBM_CNT_32K_ClockCnt32Khz(x) WriteReg(SBM_CNT_32K,x)
#define Rd_SBM_CNT_32K_ClockCnt32Khz(x) ReadReg(SBM_CNT_32K)
#define SBM_CNT_32K_CLOCKCNT32KHZ_MASK                             0xffffffff
#define SBM_CNT_32K_CLOCKCNT32KHZ_ALIGN                            0
#define SBM_CNT_32K_CLOCKCNT32KHZ_BITS                             32
#define SBM_CNT_32K_CLOCKCNT32KHZ_SHIFT                            0


/****************************************************************************
 * SBM :: TO_CNT0
 ***************************************************************************/
/* SBM :: TO_CNT0 :: TimeOutCnt0 [31:00] */
#define Wr_SBM_TO_CNT0_TimeOutCnt0(x) WriteReg(SBM_TO_CNT0,x)
#define Rd_SBM_TO_CNT0_TimeOutCnt0(x) ReadReg(SBM_TO_CNT0)
#define SBM_TO_CNT0_TIMEOUTCNT0_MASK                               0xffffffff
#define SBM_TO_CNT0_TIMEOUTCNT0_ALIGN                              0
#define SBM_TO_CNT0_TIMEOUTCNT0_BITS                               32
#define SBM_TO_CNT0_TIMEOUTCNT0_SHIFT                              0


/****************************************************************************
 * SBM :: TO_CNT1
 ***************************************************************************/
/* SBM :: TO_CNT1 :: TimeOutCnt1 [31:00] */
#define Wr_SBM_TO_CNT1_TimeOutCnt1(x) WriteReg(SBM_TO_CNT1,x)
#define Rd_SBM_TO_CNT1_TimeOutCnt1(x) ReadReg(SBM_TO_CNT1)
#define SBM_TO_CNT1_TIMEOUTCNT1_MASK                               0xffffffff
#define SBM_TO_CNT1_TIMEOUTCNT1_ALIGN                              0
#define SBM_TO_CNT1_TIMEOUTCNT1_BITS                               32
#define SBM_TO_CNT1_TIMEOUTCNT1_SHIFT                              0


/****************************************************************************
 * SBM :: MISC_CTL
 ***************************************************************************/
/* SBM :: MISC_CTL :: Reserved1 [31:10] */
#define Wr_SBM_MISC_CTL_Reserved1(x) WriteRegBits(SBM_MISC_CTL,0xfffffc00,10,x)
#define Rd_SBM_MISC_CTL_Reserved1(x) ReadRegBits(SBM_MISC_CTL,0xfffffc00,10)
#define SBM_MISC_CTL_RESERVED1_MASK                                0xfffffc00
#define SBM_MISC_CTL_RESERVED1_ALIGN                               0
#define SBM_MISC_CTL_RESERVED1_BITS                                22
#define SBM_MISC_CTL_RESERVED1_SHIFT                               10

/* SBM :: MISC_CTL :: Reserved2 [09:04] */
#define Wr_SBM_MISC_CTL_Reserved2(x) WriteRegBits(SBM_MISC_CTL,0x3f0,4,x)
#define Rd_SBM_MISC_CTL_Reserved2(x) ReadRegBits(SBM_MISC_CTL,0x3f0,4)
#define SBM_MISC_CTL_RESERVED2_MASK                                0x000003f0
#define SBM_MISC_CTL_RESERVED2_ALIGN                               0
#define SBM_MISC_CTL_RESERVED2_BITS                                6
#define SBM_MISC_CTL_RESERVED2_SHIFT                               4

/* SBM :: MISC_CTL :: Reserved3 [03:03] */
#define Wr_SBM_MISC_CTL_Reserved3(x) WriteRegBits(SBM_MISC_CTL,0x8,3,x)
#define Rd_SBM_MISC_CTL_Reserved3(x) ReadRegBits(SBM_MISC_CTL,0x8,3)
#define SBM_MISC_CTL_RESERVED3_MASK                                0x00000008
#define SBM_MISC_CTL_RESERVED3_ALIGN                               0
#define SBM_MISC_CTL_RESERVED3_BITS                                1
#define SBM_MISC_CTL_RESERVED3_SHIFT                               3

/* SBM :: MISC_CTL :: Reserved4 [02:00] */
#define Wr_SBM_MISC_CTL_Reserved4(x) WriteRegBits(SBM_MISC_CTL,0x7,0,x)
#define Rd_SBM_MISC_CTL_Reserved4(x) ReadRegBits(SBM_MISC_CTL,0x7,0)
#define SBM_MISC_CTL_RESERVED4_MASK                                0x00000007
#define SBM_MISC_CTL_RESERVED4_ALIGN                               0
#define SBM_MISC_CTL_RESERVED4_BITS                                3
#define SBM_MISC_CTL_RESERVED4_SHIFT                               0


/****************************************************************************
 * SBM :: SLV0_PRI
 ***************************************************************************/
/* SBM :: SLV0_PRI :: reserved0 [31:08] */
#define SBM_SLV0_PRI_RESERVED0_MASK                                0xffffff00
#define SBM_SLV0_PRI_RESERVED0_ALIGN                               0
#define SBM_SLV0_PRI_RESERVED0_BITS                                24
#define SBM_SLV0_PRI_RESERVED0_SHIFT                               8

/* SBM :: SLV0_PRI :: mstr_pri0_4 [07:06] */
#define Wr_SBM_SLV0_PRI_mstr_pri0_4(x) WriteRegBits(SBM_SLV0_PRI,0xc0,6,x)
#define Rd_SBM_SLV0_PRI_mstr_pri0_4(x) ReadRegBits(SBM_SLV0_PRI,0xc0,6)
#define SBM_SLV0_PRI_MSTR_PRI0_4_MASK                              0x000000c0
#define SBM_SLV0_PRI_MSTR_PRI0_4_ALIGN                             0
#define SBM_SLV0_PRI_MSTR_PRI0_4_BITS                              2
#define SBM_SLV0_PRI_MSTR_PRI0_4_SHIFT                             6

/* SBM :: SLV0_PRI :: mstr_pri0_3 [05:04] */
#define Wr_SBM_SLV0_PRI_mstr_pri0_3(x) WriteRegBits(SBM_SLV0_PRI,0x30,4,x)
#define Rd_SBM_SLV0_PRI_mstr_pri0_3(x) ReadRegBits(SBM_SLV0_PRI,0x30,4)
#define SBM_SLV0_PRI_MSTR_PRI0_3_MASK                              0x00000030
#define SBM_SLV0_PRI_MSTR_PRI0_3_ALIGN                             0
#define SBM_SLV0_PRI_MSTR_PRI0_3_BITS                              2
#define SBM_SLV0_PRI_MSTR_PRI0_3_SHIFT                             4

/* SBM :: SLV0_PRI :: mstr_pri0_2 [03:02] */
#define Wr_SBM_SLV0_PRI_mstr_pri0_2(x) WriteRegBits(SBM_SLV0_PRI,0xc,2,x)
#define Rd_SBM_SLV0_PRI_mstr_pri0_2(x) ReadRegBits(SBM_SLV0_PRI,0xc,2)
#define SBM_SLV0_PRI_MSTR_PRI0_2_MASK                              0x0000000c
#define SBM_SLV0_PRI_MSTR_PRI0_2_ALIGN                             0
#define SBM_SLV0_PRI_MSTR_PRI0_2_BITS                              2
#define SBM_SLV0_PRI_MSTR_PRI0_2_SHIFT                             2

/* SBM :: SLV0_PRI :: mstr_pri0_0 [01:00] */
#define Wr_SBM_SLV0_PRI_mstr_pri0_0(x) WriteRegBits(SBM_SLV0_PRI,0x3,0,x)
#define Rd_SBM_SLV0_PRI_mstr_pri0_0(x) ReadRegBits(SBM_SLV0_PRI,0x3,0)
#define SBM_SLV0_PRI_MSTR_PRI0_0_MASK                              0x00000003
#define SBM_SLV0_PRI_MSTR_PRI0_0_ALIGN                             0
#define SBM_SLV0_PRI_MSTR_PRI0_0_BITS                              2
#define SBM_SLV0_PRI_MSTR_PRI0_0_SHIFT                             0


/****************************************************************************
 * SBM :: TMR_S0_M1
 ***************************************************************************/
/* SBM :: TMR_S0_M1 :: reserved0 [31:28] */
#define SBM_TMR_S0_M1_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S0_M1_RESERVED0_ALIGN                              0
#define SBM_TMR_S0_M1_RESERVED0_BITS                               4
#define SBM_TMR_S0_M1_RESERVED0_SHIFT                              28

/* SBM :: TMR_S0_M1 :: mstr_arb_tmr0_2 [27:16] */
#define Wr_SBM_TMR_S0_M1_mstr_arb_tmr0_2(x) WriteRegBits(SBM_TMR_S0_M1,0xfff0000,16,x)
#define Rd_SBM_TMR_S0_M1_mstr_arb_tmr0_2(x) ReadRegBits(SBM_TMR_S0_M1,0xfff0000,16)
#define SBM_TMR_S0_M1_MSTR_ARB_TMR0_2_MASK                         0x0fff0000
#define SBM_TMR_S0_M1_MSTR_ARB_TMR0_2_ALIGN                        0
#define SBM_TMR_S0_M1_MSTR_ARB_TMR0_2_BITS                         12
#define SBM_TMR_S0_M1_MSTR_ARB_TMR0_2_SHIFT                        16

/* SBM :: TMR_S0_M1 :: reserved1 [15:12] */
#define SBM_TMR_S0_M1_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S0_M1_RESERVED1_ALIGN                              0
#define SBM_TMR_S0_M1_RESERVED1_BITS                               4
#define SBM_TMR_S0_M1_RESERVED1_SHIFT                              12

/* SBM :: TMR_S0_M1 :: mstr_arb_tmr0_0 [11:00] */
#define Wr_SBM_TMR_S0_M1_mstr_arb_tmr0_0(x) WriteRegBits(SBM_TMR_S0_M1,0xfff,0,x)
#define Rd_SBM_TMR_S0_M1_mstr_arb_tmr0_0(x) ReadRegBits(SBM_TMR_S0_M1,0xfff,0)
#define SBM_TMR_S0_M1_MSTR_ARB_TMR0_0_MASK                         0x00000fff
#define SBM_TMR_S0_M1_MSTR_ARB_TMR0_0_ALIGN                        0
#define SBM_TMR_S0_M1_MSTR_ARB_TMR0_0_BITS                         12
#define SBM_TMR_S0_M1_MSTR_ARB_TMR0_0_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S0_M3
 ***************************************************************************/
/* SBM :: TMR_S0_M3 :: reserved0 [31:28] */
#define SBM_TMR_S0_M3_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S0_M3_RESERVED0_ALIGN                              0
#define SBM_TMR_S0_M3_RESERVED0_BITS                               4
#define SBM_TMR_S0_M3_RESERVED0_SHIFT                              28

/* SBM :: TMR_S0_M3 :: mstr_arb_tmr0_4 [27:16] */
#define Wr_SBM_TMR_S0_M3_mstr_arb_tmr0_4(x) WriteRegBits(SBM_TMR_S0_M3,0xfff0000,16,x)
#define Rd_SBM_TMR_S0_M3_mstr_arb_tmr0_4(x) ReadRegBits(SBM_TMR_S0_M3,0xfff0000,16)
#define SBM_TMR_S0_M3_MSTR_ARB_TMR0_4_MASK                         0x0fff0000
#define SBM_TMR_S0_M3_MSTR_ARB_TMR0_4_ALIGN                        0
#define SBM_TMR_S0_M3_MSTR_ARB_TMR0_4_BITS                         12
#define SBM_TMR_S0_M3_MSTR_ARB_TMR0_4_SHIFT                        16

/* SBM :: TMR_S0_M3 :: reserved1 [15:12] */
#define SBM_TMR_S0_M3_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S0_M3_RESERVED1_ALIGN                              0
#define SBM_TMR_S0_M3_RESERVED1_BITS                               4
#define SBM_TMR_S0_M3_RESERVED1_SHIFT                              12

/* SBM :: TMR_S0_M3 :: mstr_arb_tmr0_3 [11:00] */
#define Wr_SBM_TMR_S0_M3_mstr_arb_tmr0_3(x) WriteRegBits(SBM_TMR_S0_M3,0xfff,0,x)
#define Rd_SBM_TMR_S0_M3_mstr_arb_tmr0_3(x) ReadRegBits(SBM_TMR_S0_M3,0xfff,0)
#define SBM_TMR_S0_M3_MSTR_ARB_TMR0_3_MASK                         0x00000fff
#define SBM_TMR_S0_M3_MSTR_ARB_TMR0_3_ALIGN                        0
#define SBM_TMR_S0_M3_MSTR_ARB_TMR0_3_BITS                         12
#define SBM_TMR_S0_M3_MSTR_ARB_TMR0_3_SHIFT                        0


/****************************************************************************
 * SBM :: SLV1_PRI
 ***************************************************************************/
/* SBM :: SLV1_PRI :: reserved0 [31:08] */
#define SBM_SLV1_PRI_RESERVED0_MASK                                0xffffff00
#define SBM_SLV1_PRI_RESERVED0_ALIGN                               0
#define SBM_SLV1_PRI_RESERVED0_BITS                                24
#define SBM_SLV1_PRI_RESERVED0_SHIFT                               8

/* SBM :: SLV1_PRI :: mstr_pri1_4 [07:06] */
#define Wr_SBM_SLV1_PRI_mstr_pri1_4(x) WriteRegBits(SBM_SLV1_PRI,0xc0,6,x)
#define Rd_SBM_SLV1_PRI_mstr_pri1_4(x) ReadRegBits(SBM_SLV1_PRI,0xc0,6)
#define SBM_SLV1_PRI_MSTR_PRI1_4_MASK                              0x000000c0
#define SBM_SLV1_PRI_MSTR_PRI1_4_ALIGN                             0
#define SBM_SLV1_PRI_MSTR_PRI1_4_BITS                              2
#define SBM_SLV1_PRI_MSTR_PRI1_4_SHIFT                             6

/* SBM :: SLV1_PRI :: mstr_pri1_3 [05:04] */
#define Wr_SBM_SLV1_PRI_mstr_pri1_3(x) WriteRegBits(SBM_SLV1_PRI,0x30,4,x)
#define Rd_SBM_SLV1_PRI_mstr_pri1_3(x) ReadRegBits(SBM_SLV1_PRI,0x30,4)
#define SBM_SLV1_PRI_MSTR_PRI1_3_MASK                              0x00000030
#define SBM_SLV1_PRI_MSTR_PRI1_3_ALIGN                             0
#define SBM_SLV1_PRI_MSTR_PRI1_3_BITS                              2
#define SBM_SLV1_PRI_MSTR_PRI1_3_SHIFT                             4

/* SBM :: SLV1_PRI :: mstr_pri1_2 [03:02] */
#define Wr_SBM_SLV1_PRI_mstr_pri1_2(x) WriteRegBits(SBM_SLV1_PRI,0xc,2,x)
#define Rd_SBM_SLV1_PRI_mstr_pri1_2(x) ReadRegBits(SBM_SLV1_PRI,0xc,2)
#define SBM_SLV1_PRI_MSTR_PRI1_2_MASK                              0x0000000c
#define SBM_SLV1_PRI_MSTR_PRI1_2_ALIGN                             0
#define SBM_SLV1_PRI_MSTR_PRI1_2_BITS                              2
#define SBM_SLV1_PRI_MSTR_PRI1_2_SHIFT                             2

/* SBM :: SLV1_PRI :: mstr_pri1_0 [01:00] */
#define Wr_SBM_SLV1_PRI_mstr_pri1_0(x) WriteRegBits(SBM_SLV1_PRI,0x3,0,x)
#define Rd_SBM_SLV1_PRI_mstr_pri1_0(x) ReadRegBits(SBM_SLV1_PRI,0x3,0)
#define SBM_SLV1_PRI_MSTR_PRI1_0_MASK                              0x00000003
#define SBM_SLV1_PRI_MSTR_PRI1_0_ALIGN                             0
#define SBM_SLV1_PRI_MSTR_PRI1_0_BITS                              2
#define SBM_SLV1_PRI_MSTR_PRI1_0_SHIFT                             0


/****************************************************************************
 * SBM :: TMR_S1_M1
 ***************************************************************************/
/* SBM :: TMR_S1_M1 :: reserved0 [31:28] */
#define SBM_TMR_S1_M1_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S1_M1_RESERVED0_ALIGN                              0
#define SBM_TMR_S1_M1_RESERVED0_BITS                               4
#define SBM_TMR_S1_M1_RESERVED0_SHIFT                              28

/* SBM :: TMR_S1_M1 :: mstr_arb_tmr1_2 [27:16] */
#define Wr_SBM_TMR_S1_M1_mstr_arb_tmr1_2(x) WriteRegBits(SBM_TMR_S1_M1,0xfff0000,16,x)
#define Rd_SBM_TMR_S1_M1_mstr_arb_tmr1_2(x) ReadRegBits(SBM_TMR_S1_M1,0xfff0000,16)
#define SBM_TMR_S1_M1_MSTR_ARB_TMR1_2_MASK                         0x0fff0000
#define SBM_TMR_S1_M1_MSTR_ARB_TMR1_2_ALIGN                        0
#define SBM_TMR_S1_M1_MSTR_ARB_TMR1_2_BITS                         12
#define SBM_TMR_S1_M1_MSTR_ARB_TMR1_2_SHIFT                        16

/* SBM :: TMR_S1_M1 :: reserved1 [15:12] */
#define SBM_TMR_S1_M1_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S1_M1_RESERVED1_ALIGN                              0
#define SBM_TMR_S1_M1_RESERVED1_BITS                               4
#define SBM_TMR_S1_M1_RESERVED1_SHIFT                              12

/* SBM :: TMR_S1_M1 :: mstr_arb_tmr1_0 [11:00] */
#define Wr_SBM_TMR_S1_M1_mstr_arb_tmr1_0(x) WriteRegBits(SBM_TMR_S1_M1,0xfff,0,x)
#define Rd_SBM_TMR_S1_M1_mstr_arb_tmr1_0(x) ReadRegBits(SBM_TMR_S1_M1,0xfff,0)
#define SBM_TMR_S1_M1_MSTR_ARB_TMR1_0_MASK                         0x00000fff
#define SBM_TMR_S1_M1_MSTR_ARB_TMR1_0_ALIGN                        0
#define SBM_TMR_S1_M1_MSTR_ARB_TMR1_0_BITS                         12
#define SBM_TMR_S1_M1_MSTR_ARB_TMR1_0_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S1_M3
 ***************************************************************************/
/* SBM :: TMR_S1_M3 :: reserved0 [31:28] */
#define SBM_TMR_S1_M3_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S1_M3_RESERVED0_ALIGN                              0
#define SBM_TMR_S1_M3_RESERVED0_BITS                               4
#define SBM_TMR_S1_M3_RESERVED0_SHIFT                              28

/* SBM :: TMR_S1_M3 :: mstr_arb_tmr1_4 [27:16] */
#define Wr_SBM_TMR_S1_M3_mstr_arb_tmr1_4(x) WriteRegBits(SBM_TMR_S1_M3,0xfff0000,16,x)
#define Rd_SBM_TMR_S1_M3_mstr_arb_tmr1_4(x) ReadRegBits(SBM_TMR_S1_M3,0xfff0000,16)
#define SBM_TMR_S1_M3_MSTR_ARB_TMR1_4_MASK                         0x0fff0000
#define SBM_TMR_S1_M3_MSTR_ARB_TMR1_4_ALIGN                        0
#define SBM_TMR_S1_M3_MSTR_ARB_TMR1_4_BITS                         12
#define SBM_TMR_S1_M3_MSTR_ARB_TMR1_4_SHIFT                        16

/* SBM :: TMR_S1_M3 :: reserved1 [15:12] */
#define SBM_TMR_S1_M3_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S1_M3_RESERVED1_ALIGN                              0
#define SBM_TMR_S1_M3_RESERVED1_BITS                               4
#define SBM_TMR_S1_M3_RESERVED1_SHIFT                              12

/* SBM :: TMR_S1_M3 :: mstr_arb_tmr1_3 [11:00] */
#define Wr_SBM_TMR_S1_M3_mstr_arb_tmr1_3(x) WriteRegBits(SBM_TMR_S1_M3,0xfff,0,x)
#define Rd_SBM_TMR_S1_M3_mstr_arb_tmr1_3(x) ReadRegBits(SBM_TMR_S1_M3,0xfff,0)
#define SBM_TMR_S1_M3_MSTR_ARB_TMR1_3_MASK                         0x00000fff
#define SBM_TMR_S1_M3_MSTR_ARB_TMR1_3_ALIGN                        0
#define SBM_TMR_S1_M3_MSTR_ARB_TMR1_3_BITS                         12
#define SBM_TMR_S1_M3_MSTR_ARB_TMR1_3_SHIFT                        0


/****************************************************************************
 * SBM :: SLV2_PRI
 ***************************************************************************/
/* SBM :: SLV2_PRI :: reserved0 [31:06] */
#define SBM_SLV2_PRI_RESERVED0_MASK                                0xffffffc0
#define SBM_SLV2_PRI_RESERVED0_ALIGN                               0
#define SBM_SLV2_PRI_RESERVED0_BITS                                26
#define SBM_SLV2_PRI_RESERVED0_SHIFT                               6

/* SBM :: SLV2_PRI :: mstr_pri2_4 [05:04] */
#define Wr_SBM_SLV2_PRI_mstr_pri2_4(x) WriteRegBits(SBM_SLV2_PRI,0x30,4,x)
#define Rd_SBM_SLV2_PRI_mstr_pri2_4(x) ReadRegBits(SBM_SLV2_PRI,0x30,4)
#define SBM_SLV2_PRI_MSTR_PRI2_4_MASK                              0x00000030
#define SBM_SLV2_PRI_MSTR_PRI2_4_ALIGN                             0
#define SBM_SLV2_PRI_MSTR_PRI2_4_BITS                              2
#define SBM_SLV2_PRI_MSTR_PRI2_4_SHIFT                             4

/* SBM :: SLV2_PRI :: mstr_pri2_2 [03:02] */
#define Wr_SBM_SLV2_PRI_mstr_pri2_2(x) WriteRegBits(SBM_SLV2_PRI,0xc,2,x)
#define Rd_SBM_SLV2_PRI_mstr_pri2_2(x) ReadRegBits(SBM_SLV2_PRI,0xc,2)
#define SBM_SLV2_PRI_MSTR_PRI2_2_MASK                              0x0000000c
#define SBM_SLV2_PRI_MSTR_PRI2_2_ALIGN                             0
#define SBM_SLV2_PRI_MSTR_PRI2_2_BITS                              2
#define SBM_SLV2_PRI_MSTR_PRI2_2_SHIFT                             2

/* SBM :: SLV2_PRI :: mstr_pri2_0 [01:00] */
#define Wr_SBM_SLV2_PRI_mstr_pri2_0(x) WriteRegBits(SBM_SLV2_PRI,0x3,0,x)
#define Rd_SBM_SLV2_PRI_mstr_pri2_0(x) ReadRegBits(SBM_SLV2_PRI,0x3,0)
#define SBM_SLV2_PRI_MSTR_PRI2_0_MASK                              0x00000003
#define SBM_SLV2_PRI_MSTR_PRI2_0_ALIGN                             0
#define SBM_SLV2_PRI_MSTR_PRI2_0_BITS                              2
#define SBM_SLV2_PRI_MSTR_PRI2_0_SHIFT                             0


/****************************************************************************
 * SBM :: TMR_S2_M1
 ***************************************************************************/
/* SBM :: TMR_S2_M1 :: reserved0 [31:28] */
#define SBM_TMR_S2_M1_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S2_M1_RESERVED0_ALIGN                              0
#define SBM_TMR_S2_M1_RESERVED0_BITS                               4
#define SBM_TMR_S2_M1_RESERVED0_SHIFT                              28

/* SBM :: TMR_S2_M1 :: mstr_arb_tmr2_2 [27:16] */
#define Wr_SBM_TMR_S2_M1_mstr_arb_tmr2_2(x) WriteRegBits(SBM_TMR_S2_M1,0xfff0000,16,x)
#define Rd_SBM_TMR_S2_M1_mstr_arb_tmr2_2(x) ReadRegBits(SBM_TMR_S2_M1,0xfff0000,16)
#define SBM_TMR_S2_M1_MSTR_ARB_TMR2_2_MASK                         0x0fff0000
#define SBM_TMR_S2_M1_MSTR_ARB_TMR2_2_ALIGN                        0
#define SBM_TMR_S2_M1_MSTR_ARB_TMR2_2_BITS                         12
#define SBM_TMR_S2_M1_MSTR_ARB_TMR2_2_SHIFT                        16

/* SBM :: TMR_S2_M1 :: reserved1 [15:12] */
#define SBM_TMR_S2_M1_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S2_M1_RESERVED1_ALIGN                              0
#define SBM_TMR_S2_M1_RESERVED1_BITS                               4
#define SBM_TMR_S2_M1_RESERVED1_SHIFT                              12

/* SBM :: TMR_S2_M1 :: mstr_arb_tmr2_0 [11:00] */
#define Wr_SBM_TMR_S2_M1_mstr_arb_tmr2_0(x) WriteRegBits(SBM_TMR_S2_M1,0xfff,0,x)
#define Rd_SBM_TMR_S2_M1_mstr_arb_tmr2_0(x) ReadRegBits(SBM_TMR_S2_M1,0xfff,0)
#define SBM_TMR_S2_M1_MSTR_ARB_TMR2_0_MASK                         0x00000fff
#define SBM_TMR_S2_M1_MSTR_ARB_TMR2_0_ALIGN                        0
#define SBM_TMR_S2_M1_MSTR_ARB_TMR2_0_BITS                         12
#define SBM_TMR_S2_M1_MSTR_ARB_TMR2_0_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S2_M3
 ***************************************************************************/
/* SBM :: TMR_S2_M3 :: reserved0 [31:12] */
#define SBM_TMR_S2_M3_RESERVED0_MASK                               0xfffff000
#define SBM_TMR_S2_M3_RESERVED0_ALIGN                              0
#define SBM_TMR_S2_M3_RESERVED0_BITS                               20
#define SBM_TMR_S2_M3_RESERVED0_SHIFT                              12

/* SBM :: TMR_S2_M3 :: mstr_arb_tmr2_4 [11:00] */
#define Wr_SBM_TMR_S2_M3_mstr_arb_tmr2_4(x) WriteRegBits(SBM_TMR_S2_M3,0xfff,0,x)
#define Rd_SBM_TMR_S2_M3_mstr_arb_tmr2_4(x) ReadRegBits(SBM_TMR_S2_M3,0xfff,0)
#define SBM_TMR_S2_M3_MSTR_ARB_TMR2_4_MASK                         0x00000fff
#define SBM_TMR_S2_M3_MSTR_ARB_TMR2_4_ALIGN                        0
#define SBM_TMR_S2_M3_MSTR_ARB_TMR2_4_BITS                         12
#define SBM_TMR_S2_M3_MSTR_ARB_TMR2_4_SHIFT                        0


/****************************************************************************
 * SBM :: SLV3_PRI
 ***************************************************************************/
/* SBM :: SLV3_PRI :: reserved0 [31:10] */
#define SBM_SLV3_PRI_RESERVED0_MASK                                0xfffffc00
#define SBM_SLV3_PRI_RESERVED0_ALIGN                               0
#define SBM_SLV3_PRI_RESERVED0_BITS                                22
#define SBM_SLV3_PRI_RESERVED0_SHIFT                               10

/* SBM :: SLV3_PRI :: mstr_pri3_4 [09:08] */
#define Wr_SBM_SLV3_PRI_mstr_pri3_4(x) WriteRegBits(SBM_SLV3_PRI,0x300,8,x)
#define Rd_SBM_SLV3_PRI_mstr_pri3_4(x) ReadRegBits(SBM_SLV3_PRI,0x300,8)
#define SBM_SLV3_PRI_MSTR_PRI3_4_MASK                              0x00000300
#define SBM_SLV3_PRI_MSTR_PRI3_4_ALIGN                             0
#define SBM_SLV3_PRI_MSTR_PRI3_4_BITS                              2
#define SBM_SLV3_PRI_MSTR_PRI3_4_SHIFT                             8

/* SBM :: SLV3_PRI :: mstr_pri3_3 [07:06] */
#define Wr_SBM_SLV3_PRI_mstr_pri3_3(x) WriteRegBits(SBM_SLV3_PRI,0xc0,6,x)
#define Rd_SBM_SLV3_PRI_mstr_pri3_3(x) ReadRegBits(SBM_SLV3_PRI,0xc0,6)
#define SBM_SLV3_PRI_MSTR_PRI3_3_MASK                              0x000000c0
#define SBM_SLV3_PRI_MSTR_PRI3_3_ALIGN                             0
#define SBM_SLV3_PRI_MSTR_PRI3_3_BITS                              2
#define SBM_SLV3_PRI_MSTR_PRI3_3_SHIFT                             6

/* SBM :: SLV3_PRI :: mstr_pri3_2 [05:04] */
#define Wr_SBM_SLV3_PRI_mstr_pri3_2(x) WriteRegBits(SBM_SLV3_PRI,0x30,4,x)
#define Rd_SBM_SLV3_PRI_mstr_pri3_2(x) ReadRegBits(SBM_SLV3_PRI,0x30,4)
#define SBM_SLV3_PRI_MSTR_PRI3_2_MASK                              0x00000030
#define SBM_SLV3_PRI_MSTR_PRI3_2_ALIGN                             0
#define SBM_SLV3_PRI_MSTR_PRI3_2_BITS                              2
#define SBM_SLV3_PRI_MSTR_PRI3_2_SHIFT                             4

/* SBM :: SLV3_PRI :: mstr_pri3_1 [03:02] */
#define Wr_SBM_SLV3_PRI_mstr_pri3_1(x) WriteRegBits(SBM_SLV3_PRI,0xc,2,x)
#define Rd_SBM_SLV3_PRI_mstr_pri3_1(x) ReadRegBits(SBM_SLV3_PRI,0xc,2)
#define SBM_SLV3_PRI_MSTR_PRI3_1_MASK                              0x0000000c
#define SBM_SLV3_PRI_MSTR_PRI3_1_ALIGN                             0
#define SBM_SLV3_PRI_MSTR_PRI3_1_BITS                              2
#define SBM_SLV3_PRI_MSTR_PRI3_1_SHIFT                             2

/* SBM :: SLV3_PRI :: mstr_pri3_0 [01:00] */
#define Wr_SBM_SLV3_PRI_mstr_pri3_0(x) WriteRegBits(SBM_SLV3_PRI,0x3,0,x)
#define Rd_SBM_SLV3_PRI_mstr_pri3_0(x) ReadRegBits(SBM_SLV3_PRI,0x3,0)
#define SBM_SLV3_PRI_MSTR_PRI3_0_MASK                              0x00000003
#define SBM_SLV3_PRI_MSTR_PRI3_0_ALIGN                             0
#define SBM_SLV3_PRI_MSTR_PRI3_0_BITS                              2
#define SBM_SLV3_PRI_MSTR_PRI3_0_SHIFT                             0


/****************************************************************************
 * SBM :: TMR_S3_M1
 ***************************************************************************/
/* SBM :: TMR_S3_M1 :: reserved0 [31:28] */
#define SBM_TMR_S3_M1_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S3_M1_RESERVED0_ALIGN                              0
#define SBM_TMR_S3_M1_RESERVED0_BITS                               4
#define SBM_TMR_S3_M1_RESERVED0_SHIFT                              28

/* SBM :: TMR_S3_M1 :: mstr_arb_tmr3_1 [27:16] */
#define Wr_SBM_TMR_S3_M1_mstr_arb_tmr3_1(x) WriteRegBits(SBM_TMR_S3_M1,0xfff0000,16,x)
#define Rd_SBM_TMR_S3_M1_mstr_arb_tmr3_1(x) ReadRegBits(SBM_TMR_S3_M1,0xfff0000,16)
#define SBM_TMR_S3_M1_MSTR_ARB_TMR3_1_MASK                         0x0fff0000
#define SBM_TMR_S3_M1_MSTR_ARB_TMR3_1_ALIGN                        0
#define SBM_TMR_S3_M1_MSTR_ARB_TMR3_1_BITS                         12
#define SBM_TMR_S3_M1_MSTR_ARB_TMR3_1_SHIFT                        16

/* SBM :: TMR_S3_M1 :: reserved1 [15:12] */
#define SBM_TMR_S3_M1_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S3_M1_RESERVED1_ALIGN                              0
#define SBM_TMR_S3_M1_RESERVED1_BITS                               4
#define SBM_TMR_S3_M1_RESERVED1_SHIFT                              12

/* SBM :: TMR_S3_M1 :: mstr_arb_tmr3_0 [11:00] */
#define Wr_SBM_TMR_S3_M1_mstr_arb_tmr3_0(x) WriteRegBits(SBM_TMR_S3_M1,0xfff,0,x)
#define Rd_SBM_TMR_S3_M1_mstr_arb_tmr3_0(x) ReadRegBits(SBM_TMR_S3_M1,0xfff,0)
#define SBM_TMR_S3_M1_MSTR_ARB_TMR3_0_MASK                         0x00000fff
#define SBM_TMR_S3_M1_MSTR_ARB_TMR3_0_ALIGN                        0
#define SBM_TMR_S3_M1_MSTR_ARB_TMR3_0_BITS                         12
#define SBM_TMR_S3_M1_MSTR_ARB_TMR3_0_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S3_M3
 ***************************************************************************/
/* SBM :: TMR_S3_M3 :: reserved0 [31:28] */
#define SBM_TMR_S3_M3_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S3_M3_RESERVED0_ALIGN                              0
#define SBM_TMR_S3_M3_RESERVED0_BITS                               4
#define SBM_TMR_S3_M3_RESERVED0_SHIFT                              28

/* SBM :: TMR_S3_M3 :: mstr_arb_tmr3_3 [27:16] */
#define Wr_SBM_TMR_S3_M3_mstr_arb_tmr3_3(x) WriteRegBits(SBM_TMR_S3_M3,0xfff0000,16,x)
#define Rd_SBM_TMR_S3_M3_mstr_arb_tmr3_3(x) ReadRegBits(SBM_TMR_S3_M3,0xfff0000,16)
#define SBM_TMR_S3_M3_MSTR_ARB_TMR3_3_MASK                         0x0fff0000
#define SBM_TMR_S3_M3_MSTR_ARB_TMR3_3_ALIGN                        0
#define SBM_TMR_S3_M3_MSTR_ARB_TMR3_3_BITS                         12
#define SBM_TMR_S3_M3_MSTR_ARB_TMR3_3_SHIFT                        16

/* SBM :: TMR_S3_M3 :: reserved1 [15:12] */
#define SBM_TMR_S3_M3_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S3_M3_RESERVED1_ALIGN                              0
#define SBM_TMR_S3_M3_RESERVED1_BITS                               4
#define SBM_TMR_S3_M3_RESERVED1_SHIFT                              12

/* SBM :: TMR_S3_M3 :: mstr_arb_tmr3_2 [11:00] */
#define Wr_SBM_TMR_S3_M3_mstr_arb_tmr3_2(x) WriteRegBits(SBM_TMR_S3_M3,0xfff,0,x)
#define Rd_SBM_TMR_S3_M3_mstr_arb_tmr3_2(x) ReadRegBits(SBM_TMR_S3_M3,0xfff,0)
#define SBM_TMR_S3_M3_MSTR_ARB_TMR3_2_MASK                         0x00000fff
#define SBM_TMR_S3_M3_MSTR_ARB_TMR3_2_ALIGN                        0
#define SBM_TMR_S3_M3_MSTR_ARB_TMR3_2_BITS                         12
#define SBM_TMR_S3_M3_MSTR_ARB_TMR3_2_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S3_M5
 ***************************************************************************/
/* SBM :: TMR_S3_M5 :: reserved0 [31:12] */
#define SBM_TMR_S3_M5_RESERVED0_MASK                               0xfffff000
#define SBM_TMR_S3_M5_RESERVED0_ALIGN                              0
#define SBM_TMR_S3_M5_RESERVED0_BITS                               20
#define SBM_TMR_S3_M5_RESERVED0_SHIFT                              12

/* SBM :: TMR_S3_M5 :: mstr_arb_tmr3_4 [11:00] */
#define Wr_SBM_TMR_S3_M5_mstr_arb_tmr3_4(x) WriteRegBits(SBM_TMR_S3_M5,0xfff,0,x)
#define Rd_SBM_TMR_S3_M5_mstr_arb_tmr3_4(x) ReadRegBits(SBM_TMR_S3_M5,0xfff,0)
#define SBM_TMR_S3_M5_MSTR_ARB_TMR3_4_MASK                         0x00000fff
#define SBM_TMR_S3_M5_MSTR_ARB_TMR3_4_ALIGN                        0
#define SBM_TMR_S3_M5_MSTR_ARB_TMR3_4_BITS                         12
#define SBM_TMR_S3_M5_MSTR_ARB_TMR3_4_SHIFT                        0


/****************************************************************************
 * SBM :: SLV4_PRI
 ***************************************************************************/
/* SBM :: SLV4_PRI :: reserved0 [31:06] */
#define SBM_SLV4_PRI_RESERVED0_MASK                                0xffffffc0
#define SBM_SLV4_PRI_RESERVED0_ALIGN                               0
#define SBM_SLV4_PRI_RESERVED0_BITS                                26
#define SBM_SLV4_PRI_RESERVED0_SHIFT                               6

/* SBM :: SLV4_PRI :: mstr_pri4_4 [05:04] */
#define Wr_SBM_SLV4_PRI_mstr_pri4_4(x) WriteRegBits(SBM_SLV4_PRI,0x30,4,x)
#define Rd_SBM_SLV4_PRI_mstr_pri4_4(x) ReadRegBits(SBM_SLV4_PRI,0x30,4)
#define SBM_SLV4_PRI_MSTR_PRI4_4_MASK                              0x00000030
#define SBM_SLV4_PRI_MSTR_PRI4_4_ALIGN                             0
#define SBM_SLV4_PRI_MSTR_PRI4_4_BITS                              2
#define SBM_SLV4_PRI_MSTR_PRI4_4_SHIFT                             4

/* SBM :: SLV4_PRI :: mstr_pri4_2 [03:02] */
#define Wr_SBM_SLV4_PRI_mstr_pri4_2(x) WriteRegBits(SBM_SLV4_PRI,0xc,2,x)
#define Rd_SBM_SLV4_PRI_mstr_pri4_2(x) ReadRegBits(SBM_SLV4_PRI,0xc,2)
#define SBM_SLV4_PRI_MSTR_PRI4_2_MASK                              0x0000000c
#define SBM_SLV4_PRI_MSTR_PRI4_2_ALIGN                             0
#define SBM_SLV4_PRI_MSTR_PRI4_2_BITS                              2
#define SBM_SLV4_PRI_MSTR_PRI4_2_SHIFT                             2

/* SBM :: SLV4_PRI :: mstr_pri4_1 [01:00] */
#define Wr_SBM_SLV4_PRI_mstr_pri4_1(x) WriteRegBits(SBM_SLV4_PRI,0x3,0,x)
#define Rd_SBM_SLV4_PRI_mstr_pri4_1(x) ReadRegBits(SBM_SLV4_PRI,0x3,0)
#define SBM_SLV4_PRI_MSTR_PRI4_1_MASK                              0x00000003
#define SBM_SLV4_PRI_MSTR_PRI4_1_ALIGN                             0
#define SBM_SLV4_PRI_MSTR_PRI4_1_BITS                              2
#define SBM_SLV4_PRI_MSTR_PRI4_1_SHIFT                             0


/****************************************************************************
 * SBM :: TMR_S4_M1
 ***************************************************************************/
/* SBM :: TMR_S4_M1 :: reserved0 [31:28] */
#define SBM_TMR_S4_M1_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S4_M1_RESERVED0_ALIGN                              0
#define SBM_TMR_S4_M1_RESERVED0_BITS                               4
#define SBM_TMR_S4_M1_RESERVED0_SHIFT                              28

/* SBM :: TMR_S4_M1 :: mstr_arb_tmr4_2 [27:16] */
#define Wr_SBM_TMR_S4_M1_mstr_arb_tmr4_2(x) WriteRegBits(SBM_TMR_S4_M1,0xfff0000,16,x)
#define Rd_SBM_TMR_S4_M1_mstr_arb_tmr4_2(x) ReadRegBits(SBM_TMR_S4_M1,0xfff0000,16)
#define SBM_TMR_S4_M1_MSTR_ARB_TMR4_2_MASK                         0x0fff0000
#define SBM_TMR_S4_M1_MSTR_ARB_TMR4_2_ALIGN                        0
#define SBM_TMR_S4_M1_MSTR_ARB_TMR4_2_BITS                         12
#define SBM_TMR_S4_M1_MSTR_ARB_TMR4_2_SHIFT                        16

/* SBM :: TMR_S4_M1 :: reserved1 [15:12] */
#define SBM_TMR_S4_M1_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S4_M1_RESERVED1_ALIGN                              0
#define SBM_TMR_S4_M1_RESERVED1_BITS                               4
#define SBM_TMR_S4_M1_RESERVED1_SHIFT                              12

/* SBM :: TMR_S4_M1 :: mstr_arb_tmr4_1 [11:00] */
#define Wr_SBM_TMR_S4_M1_mstr_arb_tmr4_1(x) WriteRegBits(SBM_TMR_S4_M1,0xfff,0,x)
#define Rd_SBM_TMR_S4_M1_mstr_arb_tmr4_1(x) ReadRegBits(SBM_TMR_S4_M1,0xfff,0)
#define SBM_TMR_S4_M1_MSTR_ARB_TMR4_1_MASK                         0x00000fff
#define SBM_TMR_S4_M1_MSTR_ARB_TMR4_1_ALIGN                        0
#define SBM_TMR_S4_M1_MSTR_ARB_TMR4_1_BITS                         12
#define SBM_TMR_S4_M1_MSTR_ARB_TMR4_1_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S4_M3
 ***************************************************************************/
/* SBM :: TMR_S4_M3 :: reserved0 [31:12] */
#define SBM_TMR_S4_M3_RESERVED0_MASK                               0xfffff000
#define SBM_TMR_S4_M3_RESERVED0_ALIGN                              0
#define SBM_TMR_S4_M3_RESERVED0_BITS                               20
#define SBM_TMR_S4_M3_RESERVED0_SHIFT                              12

/* SBM :: TMR_S4_M3 :: mstr_arb_tmr4_4 [11:00] */
#define Wr_SBM_TMR_S4_M3_mstr_arb_tmr4_4(x) WriteRegBits(SBM_TMR_S4_M3,0xfff,0,x)
#define Rd_SBM_TMR_S4_M3_mstr_arb_tmr4_4(x) ReadRegBits(SBM_TMR_S4_M3,0xfff,0)
#define SBM_TMR_S4_M3_MSTR_ARB_TMR4_4_MASK                         0x00000fff
#define SBM_TMR_S4_M3_MSTR_ARB_TMR4_4_ALIGN                        0
#define SBM_TMR_S4_M3_MSTR_ARB_TMR4_4_BITS                         12
#define SBM_TMR_S4_M3_MSTR_ARB_TMR4_4_SHIFT                        0


/****************************************************************************
 * SBM :: SLV5_PRI
 ***************************************************************************/
/* SBM :: SLV5_PRI :: reserved0 [31:10] */
#define SBM_SLV5_PRI_RESERVED0_MASK                                0xfffffc00
#define SBM_SLV5_PRI_RESERVED0_ALIGN                               0
#define SBM_SLV5_PRI_RESERVED0_BITS                                22
#define SBM_SLV5_PRI_RESERVED0_SHIFT                               10

/* SBM :: SLV5_PRI :: mstr_pri5_4 [09:08] */
#define Wr_SBM_SLV5_PRI_mstr_pri5_4(x) WriteRegBits(SBM_SLV5_PRI,0x300,8,x)
#define Rd_SBM_SLV5_PRI_mstr_pri5_4(x) ReadRegBits(SBM_SLV5_PRI,0x300,8)
#define SBM_SLV5_PRI_MSTR_PRI5_4_MASK                              0x00000300
#define SBM_SLV5_PRI_MSTR_PRI5_4_ALIGN                             0
#define SBM_SLV5_PRI_MSTR_PRI5_4_BITS                              2
#define SBM_SLV5_PRI_MSTR_PRI5_4_SHIFT                             8

/* SBM :: SLV5_PRI :: mstr_pri5_3 [07:06] */
#define Wr_SBM_SLV5_PRI_mstr_pri5_3(x) WriteRegBits(SBM_SLV5_PRI,0xc0,6,x)
#define Rd_SBM_SLV5_PRI_mstr_pri5_3(x) ReadRegBits(SBM_SLV5_PRI,0xc0,6)
#define SBM_SLV5_PRI_MSTR_PRI5_3_MASK                              0x000000c0
#define SBM_SLV5_PRI_MSTR_PRI5_3_ALIGN                             0
#define SBM_SLV5_PRI_MSTR_PRI5_3_BITS                              2
#define SBM_SLV5_PRI_MSTR_PRI5_3_SHIFT                             6

/* SBM :: SLV5_PRI :: mstr_pri5_2 [05:04] */
#define Wr_SBM_SLV5_PRI_mstr_pri5_2(x) WriteRegBits(SBM_SLV5_PRI,0x30,4,x)
#define Rd_SBM_SLV5_PRI_mstr_pri5_2(x) ReadRegBits(SBM_SLV5_PRI,0x30,4)
#define SBM_SLV5_PRI_MSTR_PRI5_2_MASK                              0x00000030
#define SBM_SLV5_PRI_MSTR_PRI5_2_ALIGN                             0
#define SBM_SLV5_PRI_MSTR_PRI5_2_BITS                              2
#define SBM_SLV5_PRI_MSTR_PRI5_2_SHIFT                             4

/* SBM :: SLV5_PRI :: mstr_pri5_1 [03:02] */
#define Wr_SBM_SLV5_PRI_mstr_pri5_1(x) WriteRegBits(SBM_SLV5_PRI,0xc,2,x)
#define Rd_SBM_SLV5_PRI_mstr_pri5_1(x) ReadRegBits(SBM_SLV5_PRI,0xc,2)
#define SBM_SLV5_PRI_MSTR_PRI5_1_MASK                              0x0000000c
#define SBM_SLV5_PRI_MSTR_PRI5_1_ALIGN                             0
#define SBM_SLV5_PRI_MSTR_PRI5_1_BITS                              2
#define SBM_SLV5_PRI_MSTR_PRI5_1_SHIFT                             2

/* SBM :: SLV5_PRI :: mstr_pri5_0 [01:00] */
#define Wr_SBM_SLV5_PRI_mstr_pri5_0(x) WriteRegBits(SBM_SLV5_PRI,0x3,0,x)
#define Rd_SBM_SLV5_PRI_mstr_pri5_0(x) ReadRegBits(SBM_SLV5_PRI,0x3,0)
#define SBM_SLV5_PRI_MSTR_PRI5_0_MASK                              0x00000003
#define SBM_SLV5_PRI_MSTR_PRI5_0_ALIGN                             0
#define SBM_SLV5_PRI_MSTR_PRI5_0_BITS                              2
#define SBM_SLV5_PRI_MSTR_PRI5_0_SHIFT                             0


/****************************************************************************
 * SBM :: TMR_S5_M1
 ***************************************************************************/
/* SBM :: TMR_S5_M1 :: reserved0 [31:28] */
#define SBM_TMR_S5_M1_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S5_M1_RESERVED0_ALIGN                              0
#define SBM_TMR_S5_M1_RESERVED0_BITS                               4
#define SBM_TMR_S5_M1_RESERVED0_SHIFT                              28

/* SBM :: TMR_S5_M1 :: mstr_arb_tmr5_1 [27:16] */
#define Wr_SBM_TMR_S5_M1_mstr_arb_tmr5_1(x) WriteRegBits(SBM_TMR_S5_M1,0xfff0000,16,x)
#define Rd_SBM_TMR_S5_M1_mstr_arb_tmr5_1(x) ReadRegBits(SBM_TMR_S5_M1,0xfff0000,16)
#define SBM_TMR_S5_M1_MSTR_ARB_TMR5_1_MASK                         0x0fff0000
#define SBM_TMR_S5_M1_MSTR_ARB_TMR5_1_ALIGN                        0
#define SBM_TMR_S5_M1_MSTR_ARB_TMR5_1_BITS                         12
#define SBM_TMR_S5_M1_MSTR_ARB_TMR5_1_SHIFT                        16

/* SBM :: TMR_S5_M1 :: reserved1 [15:12] */
#define SBM_TMR_S5_M1_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S5_M1_RESERVED1_ALIGN                              0
#define SBM_TMR_S5_M1_RESERVED1_BITS                               4
#define SBM_TMR_S5_M1_RESERVED1_SHIFT                              12

/* SBM :: TMR_S5_M1 :: mstr_arb_tmr5_0 [11:00] */
#define Wr_SBM_TMR_S5_M1_mstr_arb_tmr5_0(x) WriteRegBits(SBM_TMR_S5_M1,0xfff,0,x)
#define Rd_SBM_TMR_S5_M1_mstr_arb_tmr5_0(x) ReadRegBits(SBM_TMR_S5_M1,0xfff,0)
#define SBM_TMR_S5_M1_MSTR_ARB_TMR5_0_MASK                         0x00000fff
#define SBM_TMR_S5_M1_MSTR_ARB_TMR5_0_ALIGN                        0
#define SBM_TMR_S5_M1_MSTR_ARB_TMR5_0_BITS                         12
#define SBM_TMR_S5_M1_MSTR_ARB_TMR5_0_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S5_M3
 ***************************************************************************/
/* SBM :: TMR_S5_M3 :: reserved0 [31:28] */
#define SBM_TMR_S5_M3_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S5_M3_RESERVED0_ALIGN                              0
#define SBM_TMR_S5_M3_RESERVED0_BITS                               4
#define SBM_TMR_S5_M3_RESERVED0_SHIFT                              28

/* SBM :: TMR_S5_M3 :: mstr_arb_tmr5_3 [27:16] */
#define Wr_SBM_TMR_S5_M3_mstr_arb_tmr5_3(x) WriteRegBits(SBM_TMR_S5_M3,0xfff0000,16,x)
#define Rd_SBM_TMR_S5_M3_mstr_arb_tmr5_3(x) ReadRegBits(SBM_TMR_S5_M3,0xfff0000,16)
#define SBM_TMR_S5_M3_MSTR_ARB_TMR5_3_MASK                         0x0fff0000
#define SBM_TMR_S5_M3_MSTR_ARB_TMR5_3_ALIGN                        0
#define SBM_TMR_S5_M3_MSTR_ARB_TMR5_3_BITS                         12
#define SBM_TMR_S5_M3_MSTR_ARB_TMR5_3_SHIFT                        16

/* SBM :: TMR_S5_M3 :: reserved1 [15:12] */
#define SBM_TMR_S5_M3_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S5_M3_RESERVED1_ALIGN                              0
#define SBM_TMR_S5_M3_RESERVED1_BITS                               4
#define SBM_TMR_S5_M3_RESERVED1_SHIFT                              12

/* SBM :: TMR_S5_M3 :: mstr_arb_tmr5_2 [11:00] */
#define Wr_SBM_TMR_S5_M3_mstr_arb_tmr5_2(x) WriteRegBits(SBM_TMR_S5_M3,0xfff,0,x)
#define Rd_SBM_TMR_S5_M3_mstr_arb_tmr5_2(x) ReadRegBits(SBM_TMR_S5_M3,0xfff,0)
#define SBM_TMR_S5_M3_MSTR_ARB_TMR5_2_MASK                         0x00000fff
#define SBM_TMR_S5_M3_MSTR_ARB_TMR5_2_ALIGN                        0
#define SBM_TMR_S5_M3_MSTR_ARB_TMR5_2_BITS                         12
#define SBM_TMR_S5_M3_MSTR_ARB_TMR5_2_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S5_M5
 ***************************************************************************/
/* SBM :: TMR_S5_M5 :: reserved0 [31:12] */
#define SBM_TMR_S5_M5_RESERVED0_MASK                               0xfffff000
#define SBM_TMR_S5_M5_RESERVED0_ALIGN                              0
#define SBM_TMR_S5_M5_RESERVED0_BITS                               20
#define SBM_TMR_S5_M5_RESERVED0_SHIFT                              12

/* SBM :: TMR_S5_M5 :: mstr_arb_tmr5_4 [11:00] */
#define Wr_SBM_TMR_S5_M5_mstr_arb_tmr5_4(x) WriteRegBits(SBM_TMR_S5_M5,0xfff,0,x)
#define Rd_SBM_TMR_S5_M5_mstr_arb_tmr5_4(x) ReadRegBits(SBM_TMR_S5_M5,0xfff,0)
#define SBM_TMR_S5_M5_MSTR_ARB_TMR5_4_MASK                         0x00000fff
#define SBM_TMR_S5_M5_MSTR_ARB_TMR5_4_ALIGN                        0
#define SBM_TMR_S5_M5_MSTR_ARB_TMR5_4_BITS                         12
#define SBM_TMR_S5_M5_MSTR_ARB_TMR5_4_SHIFT                        0


/****************************************************************************
 * SBM :: SLV6_PRI
 ***************************************************************************/
/* SBM :: SLV6_PRI :: reserved0 [31:10] */
#define SBM_SLV6_PRI_RESERVED0_MASK                                0xfffffc00
#define SBM_SLV6_PRI_RESERVED0_ALIGN                               0
#define SBM_SLV6_PRI_RESERVED0_BITS                                22
#define SBM_SLV6_PRI_RESERVED0_SHIFT                               10

/* SBM :: SLV6_PRI :: mstr_pri6_4 [09:08] */
#define Wr_SBM_SLV6_PRI_mstr_pri6_4(x) WriteRegBits(SBM_SLV6_PRI,0x300,8,x)
#define Rd_SBM_SLV6_PRI_mstr_pri6_4(x) ReadRegBits(SBM_SLV6_PRI,0x300,8)
#define SBM_SLV6_PRI_MSTR_PRI6_4_MASK                              0x00000300
#define SBM_SLV6_PRI_MSTR_PRI6_4_ALIGN                             0
#define SBM_SLV6_PRI_MSTR_PRI6_4_BITS                              2
#define SBM_SLV6_PRI_MSTR_PRI6_4_SHIFT                             8

/* SBM :: SLV6_PRI :: mstr_pri6_3 [07:06] */
#define Wr_SBM_SLV6_PRI_mstr_pri6_3(x) WriteRegBits(SBM_SLV6_PRI,0xc0,6,x)
#define Rd_SBM_SLV6_PRI_mstr_pri6_3(x) ReadRegBits(SBM_SLV6_PRI,0xc0,6)
#define SBM_SLV6_PRI_MSTR_PRI6_3_MASK                              0x000000c0
#define SBM_SLV6_PRI_MSTR_PRI6_3_ALIGN                             0
#define SBM_SLV6_PRI_MSTR_PRI6_3_BITS                              2
#define SBM_SLV6_PRI_MSTR_PRI6_3_SHIFT                             6

/* SBM :: SLV6_PRI :: mstr_pri6_2 [05:04] */
#define Wr_SBM_SLV6_PRI_mstr_pri6_2(x) WriteRegBits(SBM_SLV6_PRI,0x30,4,x)
#define Rd_SBM_SLV6_PRI_mstr_pri6_2(x) ReadRegBits(SBM_SLV6_PRI,0x30,4)
#define SBM_SLV6_PRI_MSTR_PRI6_2_MASK                              0x00000030
#define SBM_SLV6_PRI_MSTR_PRI6_2_ALIGN                             0
#define SBM_SLV6_PRI_MSTR_PRI6_2_BITS                              2
#define SBM_SLV6_PRI_MSTR_PRI6_2_SHIFT                             4

/* SBM :: SLV6_PRI :: mstr_pri6_1 [03:02] */
#define Wr_SBM_SLV6_PRI_mstr_pri6_1(x) WriteRegBits(SBM_SLV6_PRI,0xc,2,x)
#define Rd_SBM_SLV6_PRI_mstr_pri6_1(x) ReadRegBits(SBM_SLV6_PRI,0xc,2)
#define SBM_SLV6_PRI_MSTR_PRI6_1_MASK                              0x0000000c
#define SBM_SLV6_PRI_MSTR_PRI6_1_ALIGN                             0
#define SBM_SLV6_PRI_MSTR_PRI6_1_BITS                              2
#define SBM_SLV6_PRI_MSTR_PRI6_1_SHIFT                             2

/* SBM :: SLV6_PRI :: mstr_pri6_0 [01:00] */
#define Wr_SBM_SLV6_PRI_mstr_pri6_0(x) WriteRegBits(SBM_SLV6_PRI,0x3,0,x)
#define Rd_SBM_SLV6_PRI_mstr_pri6_0(x) ReadRegBits(SBM_SLV6_PRI,0x3,0)
#define SBM_SLV6_PRI_MSTR_PRI6_0_MASK                              0x00000003
#define SBM_SLV6_PRI_MSTR_PRI6_0_ALIGN                             0
#define SBM_SLV6_PRI_MSTR_PRI6_0_BITS                              2
#define SBM_SLV6_PRI_MSTR_PRI6_0_SHIFT                             0


/****************************************************************************
 * SBM :: TMR_S6_M1
 ***************************************************************************/
/* SBM :: TMR_S6_M1 :: reserved0 [31:28] */
#define SBM_TMR_S6_M1_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S6_M1_RESERVED0_ALIGN                              0
#define SBM_TMR_S6_M1_RESERVED0_BITS                               4
#define SBM_TMR_S6_M1_RESERVED0_SHIFT                              28

/* SBM :: TMR_S6_M1 :: mstr_arb_tmr6_1 [27:16] */
#define Wr_SBM_TMR_S6_M1_mstr_arb_tmr6_1(x) WriteRegBits(SBM_TMR_S6_M1,0xfff0000,16,x)
#define Rd_SBM_TMR_S6_M1_mstr_arb_tmr6_1(x) ReadRegBits(SBM_TMR_S6_M1,0xfff0000,16)
#define SBM_TMR_S6_M1_MSTR_ARB_TMR6_1_MASK                         0x0fff0000
#define SBM_TMR_S6_M1_MSTR_ARB_TMR6_1_ALIGN                        0
#define SBM_TMR_S6_M1_MSTR_ARB_TMR6_1_BITS                         12
#define SBM_TMR_S6_M1_MSTR_ARB_TMR6_1_SHIFT                        16

/* SBM :: TMR_S6_M1 :: reserved1 [15:12] */
#define SBM_TMR_S6_M1_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S6_M1_RESERVED1_ALIGN                              0
#define SBM_TMR_S6_M1_RESERVED1_BITS                               4
#define SBM_TMR_S6_M1_RESERVED1_SHIFT                              12

/* SBM :: TMR_S6_M1 :: mstr_arb_tmr6_0 [11:00] */
#define Wr_SBM_TMR_S6_M1_mstr_arb_tmr6_0(x) WriteRegBits(SBM_TMR_S6_M1,0xfff,0,x)
#define Rd_SBM_TMR_S6_M1_mstr_arb_tmr6_0(x) ReadRegBits(SBM_TMR_S6_M1,0xfff,0)
#define SBM_TMR_S6_M1_MSTR_ARB_TMR6_0_MASK                         0x00000fff
#define SBM_TMR_S6_M1_MSTR_ARB_TMR6_0_ALIGN                        0
#define SBM_TMR_S6_M1_MSTR_ARB_TMR6_0_BITS                         12
#define SBM_TMR_S6_M1_MSTR_ARB_TMR6_0_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S6_M3
 ***************************************************************************/
/* SBM :: TMR_S6_M3 :: reserved0 [31:28] */
#define SBM_TMR_S6_M3_RESERVED0_MASK                               0xf0000000
#define SBM_TMR_S6_M3_RESERVED0_ALIGN                              0
#define SBM_TMR_S6_M3_RESERVED0_BITS                               4
#define SBM_TMR_S6_M3_RESERVED0_SHIFT                              28

/* SBM :: TMR_S6_M3 :: mstr_arb_tmr6_3 [27:16] */
#define Wr_SBM_TMR_S6_M3_mstr_arb_tmr6_3(x) WriteRegBits(SBM_TMR_S6_M3,0xfff0000,16,x)
#define Rd_SBM_TMR_S6_M3_mstr_arb_tmr6_3(x) ReadRegBits(SBM_TMR_S6_M3,0xfff0000,16)
#define SBM_TMR_S6_M3_MSTR_ARB_TMR6_3_MASK                         0x0fff0000
#define SBM_TMR_S6_M3_MSTR_ARB_TMR6_3_ALIGN                        0
#define SBM_TMR_S6_M3_MSTR_ARB_TMR6_3_BITS                         12
#define SBM_TMR_S6_M3_MSTR_ARB_TMR6_3_SHIFT                        16

/* SBM :: TMR_S6_M3 :: reserved1 [15:12] */
#define SBM_TMR_S6_M3_RESERVED1_MASK                               0x0000f000
#define SBM_TMR_S6_M3_RESERVED1_ALIGN                              0
#define SBM_TMR_S6_M3_RESERVED1_BITS                               4
#define SBM_TMR_S6_M3_RESERVED1_SHIFT                              12

/* SBM :: TMR_S6_M3 :: mstr_arb_tmr6_2 [11:00] */
#define Wr_SBM_TMR_S6_M3_mstr_arb_tmr6_2(x) WriteRegBits(SBM_TMR_S6_M3,0xfff,0,x)
#define Rd_SBM_TMR_S6_M3_mstr_arb_tmr6_2(x) ReadRegBits(SBM_TMR_S6_M3,0xfff,0)
#define SBM_TMR_S6_M3_MSTR_ARB_TMR6_2_MASK                         0x00000fff
#define SBM_TMR_S6_M3_MSTR_ARB_TMR6_2_ALIGN                        0
#define SBM_TMR_S6_M3_MSTR_ARB_TMR6_2_BITS                         12
#define SBM_TMR_S6_M3_MSTR_ARB_TMR6_2_SHIFT                        0


/****************************************************************************
 * SBM :: TMR_S6_M5
 ***************************************************************************/
/* SBM :: TMR_S6_M5 :: reserved0 [31:12] */
#define SBM_TMR_S6_M5_RESERVED0_MASK                               0xfffff000
#define SBM_TMR_S6_M5_RESERVED0_ALIGN                              0
#define SBM_TMR_S6_M5_RESERVED0_BITS                               20
#define SBM_TMR_S6_M5_RESERVED0_SHIFT                              12

/* SBM :: TMR_S6_M5 :: mstr_arb_tmr6_4 [11:00] */
#define Wr_SBM_TMR_S6_M5_mstr_arb_tmr6_4(x) WriteRegBits(SBM_TMR_S6_M5,0xfff,0,x)
#define Rd_SBM_TMR_S6_M5_mstr_arb_tmr6_4(x) ReadRegBits(SBM_TMR_S6_M5,0xfff,0)
#define SBM_TMR_S6_M5_MSTR_ARB_TMR6_4_MASK                         0x00000fff
#define SBM_TMR_S6_M5_MSTR_ARB_TMR6_4_ALIGN                        0
#define SBM_TMR_S6_M5_MSTR_ARB_TMR6_4_BITS                         12
#define SBM_TMR_S6_M5_MSTR_ARB_TMR6_4_SHIFT                        0


/****************************************************************************
 * bcm89530_sys_cfg_DMA1
 ***************************************************************************/
/****************************************************************************
 * DMA1 :: DMACIntStatus
 ***************************************************************************/
/* DMA1 :: DMACIntStatus :: reserved0 [31:02] */
#define DMA1_DMACINTSTATUS_RESERVED0_MASK                          0xfffffffc
#define DMA1_DMACINTSTATUS_RESERVED0_ALIGN                         0
#define DMA1_DMACINTSTATUS_RESERVED0_BITS                          30
#define DMA1_DMACINTSTATUS_RESERVED0_SHIFT                         2

/* DMA1 :: DMACIntStatus :: IntStatus [01:00] */
#define Wr_DMA1_DMACIntStatus_IntStatus(x) WriteRegBits(DMA1_DMACINTSTATUS,0x3,0,x)
#define Rd_DMA1_DMACIntStatus_IntStatus(x) ReadRegBits(DMA1_DMACINTSTATUS,0x3,0)
#define DMA1_DMACINTSTATUS_INTSTATUS_MASK                          0x00000003
#define DMA1_DMACINTSTATUS_INTSTATUS_ALIGN                         0
#define DMA1_DMACINTSTATUS_INTSTATUS_BITS                          2
#define DMA1_DMACINTSTATUS_INTSTATUS_SHIFT                         0


/****************************************************************************
 * DMA1 :: DMACIntTCStatus
 ***************************************************************************/
/* DMA1 :: DMACIntTCStatus :: reserved0 [31:02] */
#define DMA1_DMACINTTCSTATUS_RESERVED0_MASK                        0xfffffffc
#define DMA1_DMACINTTCSTATUS_RESERVED0_ALIGN                       0
#define DMA1_DMACINTTCSTATUS_RESERVED0_BITS                        30
#define DMA1_DMACINTTCSTATUS_RESERVED0_SHIFT                       2

/* DMA1 :: DMACIntTCStatus :: IntTCStatus [01:00] */
#define Wr_DMA1_DMACIntTCStatus_IntTCStatus(x) WriteRegBits(DMA1_DMACINTTCSTATUS,0x3,0,x)
#define Rd_DMA1_DMACIntTCStatus_IntTCStatus(x) ReadRegBits(DMA1_DMACINTTCSTATUS,0x3,0)
#define DMA1_DMACINTTCSTATUS_INTTCSTATUS_MASK                      0x00000003
#define DMA1_DMACINTTCSTATUS_INTTCSTATUS_ALIGN                     0
#define DMA1_DMACINTTCSTATUS_INTTCSTATUS_BITS                      2
#define DMA1_DMACINTTCSTATUS_INTTCSTATUS_SHIFT                     0


/****************************************************************************
 * DMA1 :: DMACIntTCClear
 ***************************************************************************/
/* DMA1 :: DMACIntTCClear :: reserved0 [31:02] */
#define DMA1_DMACINTTCCLEAR_RESERVED0_MASK                         0xfffffffc
#define DMA1_DMACINTTCCLEAR_RESERVED0_ALIGN                        0
#define DMA1_DMACINTTCCLEAR_RESERVED0_BITS                         30
#define DMA1_DMACINTTCCLEAR_RESERVED0_SHIFT                        2

/* DMA1 :: DMACIntTCClear :: IntTCClear [01:00] */
#define Wr_DMA1_DMACIntTCClear_IntTCClear(x) WriteRegBits(DMA1_DMACINTTCCLEAR,0x3,0,x)
#define Rd_DMA1_DMACIntTCClear_IntTCClear(x) ReadRegBits(DMA1_DMACINTTCCLEAR,0x3,0)
#define DMA1_DMACINTTCCLEAR_INTTCCLEAR_MASK                        0x00000003
#define DMA1_DMACINTTCCLEAR_INTTCCLEAR_ALIGN                       0
#define DMA1_DMACINTTCCLEAR_INTTCCLEAR_BITS                        2
#define DMA1_DMACINTTCCLEAR_INTTCCLEAR_SHIFT                       0


/****************************************************************************
 * DMA1 :: DMACIntErrorStatus
 ***************************************************************************/
/* DMA1 :: DMACIntErrorStatus :: reserved0 [31:02] */
#define DMA1_DMACINTERRORSTATUS_RESERVED0_MASK                     0xfffffffc
#define DMA1_DMACINTERRORSTATUS_RESERVED0_ALIGN                    0
#define DMA1_DMACINTERRORSTATUS_RESERVED0_BITS                     30
#define DMA1_DMACINTERRORSTATUS_RESERVED0_SHIFT                    2

/* DMA1 :: DMACIntErrorStatus :: IntErrorStatus [01:00] */
#define Wr_DMA1_DMACIntErrorStatus_IntErrorStatus(x) WriteRegBits(DMA1_DMACINTERRORSTATUS,0x3,0,x)
#define Rd_DMA1_DMACIntErrorStatus_IntErrorStatus(x) ReadRegBits(DMA1_DMACINTERRORSTATUS,0x3,0)
#define DMA1_DMACINTERRORSTATUS_INTERRORSTATUS_MASK                0x00000003
#define DMA1_DMACINTERRORSTATUS_INTERRORSTATUS_ALIGN               0
#define DMA1_DMACINTERRORSTATUS_INTERRORSTATUS_BITS                2
#define DMA1_DMACINTERRORSTATUS_INTERRORSTATUS_SHIFT               0


/****************************************************************************
 * DMA1 :: DMACIntErrClr
 ***************************************************************************/
/* DMA1 :: DMACIntErrClr :: reserved0 [31:02] */
#define DMA1_DMACINTERRCLR_RESERVED0_MASK                          0xfffffffc
#define DMA1_DMACINTERRCLR_RESERVED0_ALIGN                         0
#define DMA1_DMACINTERRCLR_RESERVED0_BITS                          30
#define DMA1_DMACINTERRCLR_RESERVED0_SHIFT                         2

/* DMA1 :: DMACIntErrClr :: IntErrClr [01:00] */
#define Wr_DMA1_DMACIntErrClr_IntErrClr(x) WriteRegBits(DMA1_DMACINTERRCLR,0x3,0,x)
#define Rd_DMA1_DMACIntErrClr_IntErrClr(x) ReadRegBits(DMA1_DMACINTERRCLR,0x3,0)
#define DMA1_DMACINTERRCLR_INTERRCLR_MASK                          0x00000003
#define DMA1_DMACINTERRCLR_INTERRCLR_ALIGN                         0
#define DMA1_DMACINTERRCLR_INTERRCLR_BITS                          2
#define DMA1_DMACINTERRCLR_INTERRCLR_SHIFT                         0


/****************************************************************************
 * DMA1 :: DMACRawIntTCStatus
 ***************************************************************************/
/* DMA1 :: DMACRawIntTCStatus :: reserved0 [31:02] */
#define DMA1_DMACRAWINTTCSTATUS_RESERVED0_MASK                     0xfffffffc
#define DMA1_DMACRAWINTTCSTATUS_RESERVED0_ALIGN                    0
#define DMA1_DMACRAWINTTCSTATUS_RESERVED0_BITS                     30
#define DMA1_DMACRAWINTTCSTATUS_RESERVED0_SHIFT                    2

/* DMA1 :: DMACRawIntTCStatus :: RawIntTCStatus [01:00] */
#define Wr_DMA1_DMACRawIntTCStatus_RawIntTCStatus(x) WriteRegBits(DMA1_DMACRAWINTTCSTATUS,0x3,0,x)
#define Rd_DMA1_DMACRawIntTCStatus_RawIntTCStatus(x) ReadRegBits(DMA1_DMACRAWINTTCSTATUS,0x3,0)
#define DMA1_DMACRAWINTTCSTATUS_RAWINTTCSTATUS_MASK                0x00000003
#define DMA1_DMACRAWINTTCSTATUS_RAWINTTCSTATUS_ALIGN               0
#define DMA1_DMACRAWINTTCSTATUS_RAWINTTCSTATUS_BITS                2
#define DMA1_DMACRAWINTTCSTATUS_RAWINTTCSTATUS_SHIFT               0


/****************************************************************************
 * DMA1 :: DMACRawIntErrorStatus
 ***************************************************************************/
/* DMA1 :: DMACRawIntErrorStatus :: reserved0 [31:02] */
#define DMA1_DMACRAWINTERRORSTATUS_RESERVED0_MASK                  0xfffffffc
#define DMA1_DMACRAWINTERRORSTATUS_RESERVED0_ALIGN                 0
#define DMA1_DMACRAWINTERRORSTATUS_RESERVED0_BITS                  30
#define DMA1_DMACRAWINTERRORSTATUS_RESERVED0_SHIFT                 2

/* DMA1 :: DMACRawIntErrorStatus :: RawIntErrorStatus [01:00] */
#define Wr_DMA1_DMACRawIntErrorStatus_RawIntErrorStatus(x) WriteRegBits(DMA1_DMACRAWINTERRORSTATUS,0x3,0,x)
#define Rd_DMA1_DMACRawIntErrorStatus_RawIntErrorStatus(x) ReadRegBits(DMA1_DMACRAWINTERRORSTATUS,0x3,0)
#define DMA1_DMACRAWINTERRORSTATUS_RAWINTERRORSTATUS_MASK          0x00000003
#define DMA1_DMACRAWINTERRORSTATUS_RAWINTERRORSTATUS_ALIGN         0
#define DMA1_DMACRAWINTERRORSTATUS_RAWINTERRORSTATUS_BITS          2
#define DMA1_DMACRAWINTERRORSTATUS_RAWINTERRORSTATUS_SHIFT         0


/****************************************************************************
 * DMA1 :: DMACEnbldChns
 ***************************************************************************/
/* DMA1 :: DMACEnbldChns :: reserved0 [31:02] */
#define DMA1_DMACENBLDCHNS_RESERVED0_MASK                          0xfffffffc
#define DMA1_DMACENBLDCHNS_RESERVED0_ALIGN                         0
#define DMA1_DMACENBLDCHNS_RESERVED0_BITS                          30
#define DMA1_DMACENBLDCHNS_RESERVED0_SHIFT                         2

/* DMA1 :: DMACEnbldChns :: EnabledChannels [01:00] */
#define Wr_DMA1_DMACEnbldChns_EnabledChannels(x) WriteRegBits(DMA1_DMACENBLDCHNS,0x3,0,x)
#define Rd_DMA1_DMACEnbldChns_EnabledChannels(x) ReadRegBits(DMA1_DMACENBLDCHNS,0x3,0)
#define DMA1_DMACENBLDCHNS_ENABLEDCHANNELS_MASK                    0x00000003
#define DMA1_DMACENBLDCHNS_ENABLEDCHANNELS_ALIGN                   0
#define DMA1_DMACENBLDCHNS_ENABLEDCHANNELS_BITS                    2
#define DMA1_DMACENBLDCHNS_ENABLEDCHANNELS_SHIFT                   0


/****************************************************************************
 * DMA1 :: DMACSoftBReq
 ***************************************************************************/
/* DMA1 :: DMACSoftBReq :: reserved0 [31:16] */
#define DMA1_DMACSOFTBREQ_RESERVED0_MASK                           0xffff0000
#define DMA1_DMACSOFTBREQ_RESERVED0_ALIGN                          0
#define DMA1_DMACSOFTBREQ_RESERVED0_BITS                           16
#define DMA1_DMACSOFTBREQ_RESERVED0_SHIFT                          16

/* DMA1 :: DMACSoftBReq :: SoftBReq [15:00] */
#define Wr_DMA1_DMACSoftBReq_SoftBReq(x) WriteRegBits(DMA1_DMACSOFTBREQ,0xffff,0,x)
#define Rd_DMA1_DMACSoftBReq_SoftBReq(x) ReadRegBits(DMA1_DMACSOFTBREQ,0xffff,0)
#define DMA1_DMACSOFTBREQ_SOFTBREQ_MASK                            0x0000ffff
#define DMA1_DMACSOFTBREQ_SOFTBREQ_ALIGN                           0
#define DMA1_DMACSOFTBREQ_SOFTBREQ_BITS                            16
#define DMA1_DMACSOFTBREQ_SOFTBREQ_SHIFT                           0


/****************************************************************************
 * DMA1 :: DMACSoftSReq
 ***************************************************************************/
/* DMA1 :: DMACSoftSReq :: reserved0 [31:16] */
#define DMA1_DMACSOFTSREQ_RESERVED0_MASK                           0xffff0000
#define DMA1_DMACSOFTSREQ_RESERVED0_ALIGN                          0
#define DMA1_DMACSOFTSREQ_RESERVED0_BITS                           16
#define DMA1_DMACSOFTSREQ_RESERVED0_SHIFT                          16

/* DMA1 :: DMACSoftSReq :: SoftSReq [15:00] */
#define Wr_DMA1_DMACSoftSReq_SoftSReq(x) WriteRegBits(DMA1_DMACSOFTSREQ,0xffff,0,x)
#define Rd_DMA1_DMACSoftSReq_SoftSReq(x) ReadRegBits(DMA1_DMACSOFTSREQ,0xffff,0)
#define DMA1_DMACSOFTSREQ_SOFTSREQ_MASK                            0x0000ffff
#define DMA1_DMACSOFTSREQ_SOFTSREQ_ALIGN                           0
#define DMA1_DMACSOFTSREQ_SOFTSREQ_BITS                            16
#define DMA1_DMACSOFTSREQ_SOFTSREQ_SHIFT                           0


/****************************************************************************
 * DMA1 :: DMACSoftLBReq
 ***************************************************************************/
/* DMA1 :: DMACSoftLBReq :: reserved0 [31:16] */
#define DMA1_DMACSOFTLBREQ_RESERVED0_MASK                          0xffff0000
#define DMA1_DMACSOFTLBREQ_RESERVED0_ALIGN                         0
#define DMA1_DMACSOFTLBREQ_RESERVED0_BITS                          16
#define DMA1_DMACSOFTLBREQ_RESERVED0_SHIFT                         16

/* DMA1 :: DMACSoftLBReq :: SoftLBReq [15:00] */
#define Wr_DMA1_DMACSoftLBReq_SoftLBReq(x) WriteRegBits(DMA1_DMACSOFTLBREQ,0xffff,0,x)
#define Rd_DMA1_DMACSoftLBReq_SoftLBReq(x) ReadRegBits(DMA1_DMACSOFTLBREQ,0xffff,0)
#define DMA1_DMACSOFTLBREQ_SOFTLBREQ_MASK                          0x0000ffff
#define DMA1_DMACSOFTLBREQ_SOFTLBREQ_ALIGN                         0
#define DMA1_DMACSOFTLBREQ_SOFTLBREQ_BITS                          16
#define DMA1_DMACSOFTLBREQ_SOFTLBREQ_SHIFT                         0


/****************************************************************************
 * DMA1 :: DMACSoftLSReq
 ***************************************************************************/
/* DMA1 :: DMACSoftLSReq :: reserved0 [31:16] */
#define DMA1_DMACSOFTLSREQ_RESERVED0_MASK                          0xffff0000
#define DMA1_DMACSOFTLSREQ_RESERVED0_ALIGN                         0
#define DMA1_DMACSOFTLSREQ_RESERVED0_BITS                          16
#define DMA1_DMACSOFTLSREQ_RESERVED0_SHIFT                         16

/* DMA1 :: DMACSoftLSReq :: SoftLSReq [15:00] */
#define Wr_DMA1_DMACSoftLSReq_SoftLSReq(x) WriteRegBits(DMA1_DMACSOFTLSREQ,0xffff,0,x)
#define Rd_DMA1_DMACSoftLSReq_SoftLSReq(x) ReadRegBits(DMA1_DMACSOFTLSREQ,0xffff,0)
#define DMA1_DMACSOFTLSREQ_SOFTLSREQ_MASK                          0x0000ffff
#define DMA1_DMACSOFTLSREQ_SOFTLSREQ_ALIGN                         0
#define DMA1_DMACSOFTLSREQ_SOFTLSREQ_BITS                          16
#define DMA1_DMACSOFTLSREQ_SOFTLSREQ_SHIFT                         0


/****************************************************************************
 * DMA1 :: DMACConfiguration
 ***************************************************************************/
/* DMA1 :: DMACConfiguration :: reserved0 [31:02] */
#define DMA1_DMACCONFIGURATION_RESERVED0_MASK                      0xfffffffc
#define DMA1_DMACCONFIGURATION_RESERVED0_ALIGN                     0
#define DMA1_DMACCONFIGURATION_RESERVED0_BITS                      30
#define DMA1_DMACCONFIGURATION_RESERVED0_SHIFT                     2

/* DMA1 :: DMACConfiguration :: MasterEndian [01:01] */
#define Wr_DMA1_DMACConfiguration_MasterEndian(x) WriteRegBits(DMA1_DMACCONFIGURATION,0x2,1,x)
#define Rd_DMA1_DMACConfiguration_MasterEndian(x) ReadRegBits(DMA1_DMACCONFIGURATION,0x2,1)
#define DMA1_DMACCONFIGURATION_MASTERENDIAN_MASK                   0x00000002
#define DMA1_DMACCONFIGURATION_MASTERENDIAN_ALIGN                  0
#define DMA1_DMACCONFIGURATION_MASTERENDIAN_BITS                   1
#define DMA1_DMACCONFIGURATION_MASTERENDIAN_SHIFT                  1

/* DMA1 :: DMACConfiguration :: Enable [00:00] */
#define Wr_DMA1_DMACConfiguration_Enable(x) WriteRegBits(DMA1_DMACCONFIGURATION,0x1,0,x)
#define Rd_DMA1_DMACConfiguration_Enable(x) ReadRegBits(DMA1_DMACCONFIGURATION,0x1,0)
#define DMA1_DMACCONFIGURATION_ENABLE_MASK                         0x00000001
#define DMA1_DMACCONFIGURATION_ENABLE_ALIGN                        0
#define DMA1_DMACCONFIGURATION_ENABLE_BITS                         1
#define DMA1_DMACCONFIGURATION_ENABLE_SHIFT                        0


/****************************************************************************
 * DMA1 :: DMACSync
 ***************************************************************************/
/* DMA1 :: DMACSync :: reserved0 [31:16] */
#define DMA1_DMACSYNC_RESERVED0_MASK                               0xffff0000
#define DMA1_DMACSYNC_RESERVED0_ALIGN                              0
#define DMA1_DMACSYNC_RESERVED0_BITS                               16
#define DMA1_DMACSYNC_RESERVED0_SHIFT                              16

/* DMA1 :: DMACSync :: DMACSync [15:00] */
#define Wr_DMA1_DMACSync_DMACSync(x) WriteRegBits(DMA1_DMACSYNC,0xffff,0,x)
#define Rd_DMA1_DMACSync_DMACSync(x) ReadRegBits(DMA1_DMACSYNC,0xffff,0)
#define DMA1_DMACSYNC_DMACSYNC_MASK                                0x0000ffff
#define DMA1_DMACSYNC_DMACSYNC_ALIGN                               0
#define DMA1_DMACSYNC_DMACSYNC_BITS                                16
#define DMA1_DMACSYNC_DMACSYNC_SHIFT                               0


/****************************************************************************
 * DMA1 :: DMACC0SrcAddr
 ***************************************************************************/
/* DMA1 :: DMACC0SrcAddr :: C0SrcAddr [31:00] */
#define Wr_DMA1_DMACC0SrcAddr_C0SrcAddr(x) WriteReg(DMA1_DMACC0SRCADDR,x)
#define Rd_DMA1_DMACC0SrcAddr_C0SrcAddr(x) ReadReg(DMA1_DMACC0SRCADDR)
#define DMA1_DMACC0SRCADDR_C0SRCADDR_MASK                          0xffffffff
#define DMA1_DMACC0SRCADDR_C0SRCADDR_ALIGN                         0
#define DMA1_DMACC0SRCADDR_C0SRCADDR_BITS                          32
#define DMA1_DMACC0SRCADDR_C0SRCADDR_SHIFT                         0


/****************************************************************************
 * DMA1 :: DMACC0DestAddr
 ***************************************************************************/
/* DMA1 :: DMACC0DestAddr :: C0DestAddr [31:00] */
#define Wr_DMA1_DMACC0DestAddr_C0DestAddr(x) WriteReg(DMA1_DMACC0DESTADDR,x)
#define Rd_DMA1_DMACC0DestAddr_C0DestAddr(x) ReadReg(DMA1_DMACC0DESTADDR)
#define DMA1_DMACC0DESTADDR_C0DESTADDR_MASK                        0xffffffff
#define DMA1_DMACC0DESTADDR_C0DESTADDR_ALIGN                       0
#define DMA1_DMACC0DESTADDR_C0DESTADDR_BITS                        32
#define DMA1_DMACC0DESTADDR_C0DESTADDR_SHIFT                       0


/****************************************************************************
 * DMA1 :: DMACC0LLI
 ***************************************************************************/
/* DMA1 :: DMACC0LLI :: C0LLI [31:02] */
#define Wr_DMA1_DMACC0LLI_C0LLI(x) WriteRegBits(DMA1_DMACC0LLI,0xfffffffc,2,x)
#define Rd_DMA1_DMACC0LLI_C0LLI(x) ReadRegBits(DMA1_DMACC0LLI,0xfffffffc,2)
#define DMA1_DMACC0LLI_C0LLI_MASK                                  0xfffffffc
#define DMA1_DMACC0LLI_C0LLI_ALIGN                                 0
#define DMA1_DMACC0LLI_C0LLI_BITS                                  30
#define DMA1_DMACC0LLI_C0LLI_SHIFT                                 2

/* DMA1 :: DMACC0LLI :: reserved0 [01:00] */
#define DMA1_DMACC0LLI_RESERVED0_MASK                              0x00000003
#define DMA1_DMACC0LLI_RESERVED0_ALIGN                             0
#define DMA1_DMACC0LLI_RESERVED0_BITS                              2
#define DMA1_DMACC0LLI_RESERVED0_SHIFT                             0


/****************************************************************************
 * DMA1 :: DMACC0Control
 ***************************************************************************/
/* DMA1 :: DMACC0Control :: C0I [31:31] */
#define Wr_DMA1_DMACC0Control_C0I(x) WriteRegBits(DMA1_DMACC0CONTROL,0x80000000,31,x)
#define Rd_DMA1_DMACC0Control_C0I(x) ReadRegBits(DMA1_DMACC0CONTROL,0x80000000,31)
#define DMA1_DMACC0CONTROL_C0I_MASK                                0x80000000
#define DMA1_DMACC0CONTROL_C0I_ALIGN                               0
#define DMA1_DMACC0CONTROL_C0I_BITS                                1
#define DMA1_DMACC0CONTROL_C0I_SHIFT                               31

/* DMA1 :: DMACC0Control :: C0Prot [30:28] */
#define Wr_DMA1_DMACC0Control_C0Prot(x) WriteRegBits(DMA1_DMACC0CONTROL,0x70000000,28,x)
#define Rd_DMA1_DMACC0Control_C0Prot(x) ReadRegBits(DMA1_DMACC0CONTROL,0x70000000,28)
#define DMA1_DMACC0CONTROL_C0PROT_MASK                             0x70000000
#define DMA1_DMACC0CONTROL_C0PROT_ALIGN                            0
#define DMA1_DMACC0CONTROL_C0PROT_BITS                             3
#define DMA1_DMACC0CONTROL_C0PROT_SHIFT                            28

/* DMA1 :: DMACC0Control :: C0DestInc [27:27] */
#define Wr_DMA1_DMACC0Control_C0DestInc(x) WriteRegBits(DMA1_DMACC0CONTROL,0x8000000,27,x)
#define Rd_DMA1_DMACC0Control_C0DestInc(x) ReadRegBits(DMA1_DMACC0CONTROL,0x8000000,27)
#define DMA1_DMACC0CONTROL_C0DESTINC_MASK                          0x08000000
#define DMA1_DMACC0CONTROL_C0DESTINC_ALIGN                         0
#define DMA1_DMACC0CONTROL_C0DESTINC_BITS                          1
#define DMA1_DMACC0CONTROL_C0DESTINC_SHIFT                         27

/* DMA1 :: DMACC0Control :: C0SrcInc [26:26] */
#define Wr_DMA1_DMACC0Control_C0SrcInc(x) WriteRegBits(DMA1_DMACC0CONTROL,0x4000000,26,x)
#define Rd_DMA1_DMACC0Control_C0SrcInc(x) ReadRegBits(DMA1_DMACC0CONTROL,0x4000000,26)
#define DMA1_DMACC0CONTROL_C0SRCINC_MASK                           0x04000000
#define DMA1_DMACC0CONTROL_C0SRCINC_ALIGN                          0
#define DMA1_DMACC0CONTROL_C0SRCINC_BITS                           1
#define DMA1_DMACC0CONTROL_C0SRCINC_SHIFT                          26

/* DMA1 :: DMACC0Control :: reserved0 [25:24] */
#define DMA1_DMACC0CONTROL_RESERVED0_MASK                          0x03000000
#define DMA1_DMACC0CONTROL_RESERVED0_ALIGN                         0
#define DMA1_DMACC0CONTROL_RESERVED0_BITS                          2
#define DMA1_DMACC0CONTROL_RESERVED0_SHIFT                         24

/* DMA1 :: DMACC0Control :: C0DestWidth [23:21] */
#define Wr_DMA1_DMACC0Control_C0DestWidth(x) WriteRegBits(DMA1_DMACC0CONTROL,0xe00000,21,x)
#define Rd_DMA1_DMACC0Control_C0DestWidth(x) ReadRegBits(DMA1_DMACC0CONTROL,0xe00000,21)
#define DMA1_DMACC0CONTROL_C0DESTWIDTH_MASK                        0x00e00000
#define DMA1_DMACC0CONTROL_C0DESTWIDTH_ALIGN                       0
#define DMA1_DMACC0CONTROL_C0DESTWIDTH_BITS                        3
#define DMA1_DMACC0CONTROL_C0DESTWIDTH_SHIFT                       21

/* DMA1 :: DMACC0Control :: C0SrcWidth [20:18] */
#define Wr_DMA1_DMACC0Control_C0SrcWidth(x) WriteRegBits(DMA1_DMACC0CONTROL,0x1c0000,18,x)
#define Rd_DMA1_DMACC0Control_C0SrcWidth(x) ReadRegBits(DMA1_DMACC0CONTROL,0x1c0000,18)
#define DMA1_DMACC0CONTROL_C0SRCWIDTH_MASK                         0x001c0000
#define DMA1_DMACC0CONTROL_C0SRCWIDTH_ALIGN                        0
#define DMA1_DMACC0CONTROL_C0SRCWIDTH_BITS                         3
#define DMA1_DMACC0CONTROL_C0SRCWIDTH_SHIFT                        18

/* DMA1 :: DMACC0Control :: C0DestBurstSize [17:15] */
#define Wr_DMA1_DMACC0Control_C0DestBurstSize(x) WriteRegBits(DMA1_DMACC0CONTROL,0x38000,15,x)
#define Rd_DMA1_DMACC0Control_C0DestBurstSize(x) ReadRegBits(DMA1_DMACC0CONTROL,0x38000,15)
#define DMA1_DMACC0CONTROL_C0DESTBURSTSIZE_MASK                    0x00038000
#define DMA1_DMACC0CONTROL_C0DESTBURSTSIZE_ALIGN                   0
#define DMA1_DMACC0CONTROL_C0DESTBURSTSIZE_BITS                    3
#define DMA1_DMACC0CONTROL_C0DESTBURSTSIZE_SHIFT                   15

/* DMA1 :: DMACC0Control :: C0SrcBurstSize [14:12] */
#define Wr_DMA1_DMACC0Control_C0SrcBurstSize(x) WriteRegBits(DMA1_DMACC0CONTROL,0x7000,12,x)
#define Rd_DMA1_DMACC0Control_C0SrcBurstSize(x) ReadRegBits(DMA1_DMACC0CONTROL,0x7000,12)
#define DMA1_DMACC0CONTROL_C0SRCBURSTSIZE_MASK                     0x00007000
#define DMA1_DMACC0CONTROL_C0SRCBURSTSIZE_ALIGN                    0
#define DMA1_DMACC0CONTROL_C0SRCBURSTSIZE_BITS                     3
#define DMA1_DMACC0CONTROL_C0SRCBURSTSIZE_SHIFT                    12

/* DMA1 :: DMACC0Control :: C0TransferSize [11:00] */
#define Wr_DMA1_DMACC0Control_C0TransferSize(x) WriteRegBits(DMA1_DMACC0CONTROL,0xfff,0,x)
#define Rd_DMA1_DMACC0Control_C0TransferSize(x) ReadRegBits(DMA1_DMACC0CONTROL,0xfff,0)
#define DMA1_DMACC0CONTROL_C0TRANSFERSIZE_MASK                     0x00000fff
#define DMA1_DMACC0CONTROL_C0TRANSFERSIZE_ALIGN                    0
#define DMA1_DMACC0CONTROL_C0TRANSFERSIZE_BITS                     12
#define DMA1_DMACC0CONTROL_C0TRANSFERSIZE_SHIFT                    0


/****************************************************************************
 * DMA1 :: DMACC0Configuration
 ***************************************************************************/
/* DMA1 :: DMACC0Configuration :: reserved0 [31:19] */
#define DMA1_DMACC0CONFIGURATION_RESERVED0_MASK                    0xfff80000
#define DMA1_DMACC0CONFIGURATION_RESERVED0_ALIGN                   0
#define DMA1_DMACC0CONFIGURATION_RESERVED0_BITS                    13
#define DMA1_DMACC0CONFIGURATION_RESERVED0_SHIFT                   19

/* DMA1 :: DMACC0Configuration :: C0Halt [18:18] */
#define Wr_DMA1_DMACC0Configuration_C0Halt(x) WriteRegBits(DMA1_DMACC0CONFIGURATION,0x40000,18,x)
#define Rd_DMA1_DMACC0Configuration_C0Halt(x) ReadRegBits(DMA1_DMACC0CONFIGURATION,0x40000,18)
#define DMA1_DMACC0CONFIGURATION_C0HALT_MASK                       0x00040000
#define DMA1_DMACC0CONFIGURATION_C0HALT_ALIGN                      0
#define DMA1_DMACC0CONFIGURATION_C0HALT_BITS                       1
#define DMA1_DMACC0CONFIGURATION_C0HALT_SHIFT                      18

/* DMA1 :: DMACC0Configuration :: C0Active [17:17] */
#define Wr_DMA1_DMACC0Configuration_C0Active(x) WriteRegBits(DMA1_DMACC0CONFIGURATION,0x20000,17,x)
#define Rd_DMA1_DMACC0Configuration_C0Active(x) ReadRegBits(DMA1_DMACC0CONFIGURATION,0x20000,17)
#define DMA1_DMACC0CONFIGURATION_C0ACTIVE_MASK                     0x00020000
#define DMA1_DMACC0CONFIGURATION_C0ACTIVE_ALIGN                    0
#define DMA1_DMACC0CONFIGURATION_C0ACTIVE_BITS                     1
#define DMA1_DMACC0CONFIGURATION_C0ACTIVE_SHIFT                    17

/* DMA1 :: DMACC0Configuration :: C0Lock [16:16] */
#define Wr_DMA1_DMACC0Configuration_C0Lock(x) WriteRegBits(DMA1_DMACC0CONFIGURATION,0x10000,16,x)
#define Rd_DMA1_DMACC0Configuration_C0Lock(x) ReadRegBits(DMA1_DMACC0CONFIGURATION,0x10000,16)
#define DMA1_DMACC0CONFIGURATION_C0LOCK_MASK                       0x00010000
#define DMA1_DMACC0CONFIGURATION_C0LOCK_ALIGN                      0
#define DMA1_DMACC0CONFIGURATION_C0LOCK_BITS                       1
#define DMA1_DMACC0CONFIGURATION_C0LOCK_SHIFT                      16

/* DMA1 :: DMACC0Configuration :: C0IntTCMask [15:15] */
#define Wr_DMA1_DMACC0Configuration_C0IntTCMask(x) WriteRegBits(DMA1_DMACC0CONFIGURATION,0x8000,15,x)
#define Rd_DMA1_DMACC0Configuration_C0IntTCMask(x) ReadRegBits(DMA1_DMACC0CONFIGURATION,0x8000,15)
#define DMA1_DMACC0CONFIGURATION_C0INTTCMASK_MASK                  0x00008000
#define DMA1_DMACC0CONFIGURATION_C0INTTCMASK_ALIGN                 0
#define DMA1_DMACC0CONFIGURATION_C0INTTCMASK_BITS                  1
#define DMA1_DMACC0CONFIGURATION_C0INTTCMASK_SHIFT                 15

/* DMA1 :: DMACC0Configuration :: C0IntErrorMask [14:14] */
#define Wr_DMA1_DMACC0Configuration_C0IntErrorMask(x) WriteRegBits(DMA1_DMACC0CONFIGURATION,0x4000,14,x)
#define Rd_DMA1_DMACC0Configuration_C0IntErrorMask(x) ReadRegBits(DMA1_DMACC0CONFIGURATION,0x4000,14)
#define DMA1_DMACC0CONFIGURATION_C0INTERRORMASK_MASK               0x00004000
#define DMA1_DMACC0CONFIGURATION_C0INTERRORMASK_ALIGN              0
#define DMA1_DMACC0CONFIGURATION_C0INTERRORMASK_BITS               1
#define DMA1_DMACC0CONFIGURATION_C0INTERRORMASK_SHIFT              14

/* DMA1 :: DMACC0Configuration :: C0FlowCntrl [13:11] */
#define Wr_DMA1_DMACC0Configuration_C0FlowCntrl(x) WriteRegBits(DMA1_DMACC0CONFIGURATION,0x3800,11,x)
#define Rd_DMA1_DMACC0Configuration_C0FlowCntrl(x) ReadRegBits(DMA1_DMACC0CONFIGURATION,0x3800,11)
#define DMA1_DMACC0CONFIGURATION_C0FLOWCNTRL_MASK                  0x00003800
#define DMA1_DMACC0CONFIGURATION_C0FLOWCNTRL_ALIGN                 0
#define DMA1_DMACC0CONFIGURATION_C0FLOWCNTRL_BITS                  3
#define DMA1_DMACC0CONFIGURATION_C0FLOWCNTRL_SHIFT                 11

/* DMA1 :: DMACC0Configuration :: reserved1 [10:10] */
#define DMA1_DMACC0CONFIGURATION_RESERVED1_MASK                    0x00000400
#define DMA1_DMACC0CONFIGURATION_RESERVED1_ALIGN                   0
#define DMA1_DMACC0CONFIGURATION_RESERVED1_BITS                    1
#define DMA1_DMACC0CONFIGURATION_RESERVED1_SHIFT                   10

/* DMA1 :: DMACC0Configuration :: C0DestPeripheral [09:06] */
#define Wr_DMA1_DMACC0Configuration_C0DestPeripheral(x) WriteRegBits(DMA1_DMACC0CONFIGURATION,0x3c0,6,x)
#define Rd_DMA1_DMACC0Configuration_C0DestPeripheral(x) ReadRegBits(DMA1_DMACC0CONFIGURATION,0x3c0,6)
#define DMA1_DMACC0CONFIGURATION_C0DESTPERIPHERAL_MASK             0x000003c0
#define DMA1_DMACC0CONFIGURATION_C0DESTPERIPHERAL_ALIGN            0
#define DMA1_DMACC0CONFIGURATION_C0DESTPERIPHERAL_BITS             4
#define DMA1_DMACC0CONFIGURATION_C0DESTPERIPHERAL_SHIFT            6

/* DMA1 :: DMACC0Configuration :: reserved2 [05:05] */
#define DMA1_DMACC0CONFIGURATION_RESERVED2_MASK                    0x00000020
#define DMA1_DMACC0CONFIGURATION_RESERVED2_ALIGN                   0
#define DMA1_DMACC0CONFIGURATION_RESERVED2_BITS                    1
#define DMA1_DMACC0CONFIGURATION_RESERVED2_SHIFT                   5

/* DMA1 :: DMACC0Configuration :: C0SrcPeripheral [04:01] */
#define Wr_DMA1_DMACC0Configuration_C0SrcPeripheral(x) WriteRegBits(DMA1_DMACC0CONFIGURATION,0x1e,1,x)
#define Rd_DMA1_DMACC0Configuration_C0SrcPeripheral(x) ReadRegBits(DMA1_DMACC0CONFIGURATION,0x1e,1)
#define DMA1_DMACC0CONFIGURATION_C0SRCPERIPHERAL_MASK              0x0000001e
#define DMA1_DMACC0CONFIGURATION_C0SRCPERIPHERAL_ALIGN             0
#define DMA1_DMACC0CONFIGURATION_C0SRCPERIPHERAL_BITS              4
#define DMA1_DMACC0CONFIGURATION_C0SRCPERIPHERAL_SHIFT             1

/* DMA1 :: DMACC0Configuration :: C0Enable [00:00] */
#define Wr_DMA1_DMACC0Configuration_C0Enable(x) WriteRegBits(DMA1_DMACC0CONFIGURATION,0x1,0,x)
#define Rd_DMA1_DMACC0Configuration_C0Enable(x) ReadRegBits(DMA1_DMACC0CONFIGURATION,0x1,0)
#define DMA1_DMACC0CONFIGURATION_C0ENABLE_MASK                     0x00000001
#define DMA1_DMACC0CONFIGURATION_C0ENABLE_ALIGN                    0
#define DMA1_DMACC0CONFIGURATION_C0ENABLE_BITS                     1
#define DMA1_DMACC0CONFIGURATION_C0ENABLE_SHIFT                    0


/****************************************************************************
 * DMA1 :: DMACC1SrcAddr
 ***************************************************************************/
/* DMA1 :: DMACC1SrcAddr :: C1SrcAddr [31:00] */
#define Wr_DMA1_DMACC1SrcAddr_C1SrcAddr(x) WriteReg(DMA1_DMACC1SRCADDR,x)
#define Rd_DMA1_DMACC1SrcAddr_C1SrcAddr(x) ReadReg(DMA1_DMACC1SRCADDR)
#define DMA1_DMACC1SRCADDR_C1SRCADDR_MASK                          0xffffffff
#define DMA1_DMACC1SRCADDR_C1SRCADDR_ALIGN                         0
#define DMA1_DMACC1SRCADDR_C1SRCADDR_BITS                          32
#define DMA1_DMACC1SRCADDR_C1SRCADDR_SHIFT                         0


/****************************************************************************
 * DMA1 :: DMACC1DestAddr
 ***************************************************************************/
/* DMA1 :: DMACC1DestAddr :: C1DestAddr [31:00] */
#define Wr_DMA1_DMACC1DestAddr_C1DestAddr(x) WriteReg(DMA1_DMACC1DESTADDR,x)
#define Rd_DMA1_DMACC1DestAddr_C1DestAddr(x) ReadReg(DMA1_DMACC1DESTADDR)
#define DMA1_DMACC1DESTADDR_C1DESTADDR_MASK                        0xffffffff
#define DMA1_DMACC1DESTADDR_C1DESTADDR_ALIGN                       0
#define DMA1_DMACC1DESTADDR_C1DESTADDR_BITS                        32
#define DMA1_DMACC1DESTADDR_C1DESTADDR_SHIFT                       0


/****************************************************************************
 * DMA1 :: DMACC1LLI
 ***************************************************************************/
/* DMA1 :: DMACC1LLI :: C1LLI [31:02] */
#define Wr_DMA1_DMACC1LLI_C1LLI(x) WriteRegBits(DMA1_DMACC1LLI,0xfffffffc,2,x)
#define Rd_DMA1_DMACC1LLI_C1LLI(x) ReadRegBits(DMA1_DMACC1LLI,0xfffffffc,2)
#define DMA1_DMACC1LLI_C1LLI_MASK                                  0xfffffffc
#define DMA1_DMACC1LLI_C1LLI_ALIGN                                 0
#define DMA1_DMACC1LLI_C1LLI_BITS                                  30
#define DMA1_DMACC1LLI_C1LLI_SHIFT                                 2

/* DMA1 :: DMACC1LLI :: reserved0 [01:00] */
#define DMA1_DMACC1LLI_RESERVED0_MASK                              0x00000003
#define DMA1_DMACC1LLI_RESERVED0_ALIGN                             0
#define DMA1_DMACC1LLI_RESERVED0_BITS                              2
#define DMA1_DMACC1LLI_RESERVED0_SHIFT                             0


/****************************************************************************
 * DMA1 :: DMACC1Control
 ***************************************************************************/
/* DMA1 :: DMACC1Control :: C1I [31:31] */
#define Wr_DMA1_DMACC1Control_C1I(x) WriteRegBits(DMA1_DMACC1CONTROL,0x80000000,31,x)
#define Rd_DMA1_DMACC1Control_C1I(x) ReadRegBits(DMA1_DMACC1CONTROL,0x80000000,31)
#define DMA1_DMACC1CONTROL_C1I_MASK                                0x80000000
#define DMA1_DMACC1CONTROL_C1I_ALIGN                               0
#define DMA1_DMACC1CONTROL_C1I_BITS                                1
#define DMA1_DMACC1CONTROL_C1I_SHIFT                               31

/* DMA1 :: DMACC1Control :: C1Prot [30:28] */
#define Wr_DMA1_DMACC1Control_C1Prot(x) WriteRegBits(DMA1_DMACC1CONTROL,0x70000000,28,x)
#define Rd_DMA1_DMACC1Control_C1Prot(x) ReadRegBits(DMA1_DMACC1CONTROL,0x70000000,28)
#define DMA1_DMACC1CONTROL_C1PROT_MASK                             0x70000000
#define DMA1_DMACC1CONTROL_C1PROT_ALIGN                            0
#define DMA1_DMACC1CONTROL_C1PROT_BITS                             3
#define DMA1_DMACC1CONTROL_C1PROT_SHIFT                            28

/* DMA1 :: DMACC1Control :: C1DestInc [27:27] */
#define Wr_DMA1_DMACC1Control_C1DestInc(x) WriteRegBits(DMA1_DMACC1CONTROL,0x8000000,27,x)
#define Rd_DMA1_DMACC1Control_C1DestInc(x) ReadRegBits(DMA1_DMACC1CONTROL,0x8000000,27)
#define DMA1_DMACC1CONTROL_C1DESTINC_MASK                          0x08000000
#define DMA1_DMACC1CONTROL_C1DESTINC_ALIGN                         0
#define DMA1_DMACC1CONTROL_C1DESTINC_BITS                          1
#define DMA1_DMACC1CONTROL_C1DESTINC_SHIFT                         27

/* DMA1 :: DMACC1Control :: C1SrcInc [26:26] */
#define Wr_DMA1_DMACC1Control_C1SrcInc(x) WriteRegBits(DMA1_DMACC1CONTROL,0x4000000,26,x)
#define Rd_DMA1_DMACC1Control_C1SrcInc(x) ReadRegBits(DMA1_DMACC1CONTROL,0x4000000,26)
#define DMA1_DMACC1CONTROL_C1SRCINC_MASK                           0x04000000
#define DMA1_DMACC1CONTROL_C1SRCINC_ALIGN                          0
#define DMA1_DMACC1CONTROL_C1SRCINC_BITS                           1
#define DMA1_DMACC1CONTROL_C1SRCINC_SHIFT                          26

/* DMA1 :: DMACC1Control :: reserved0 [25:24] */
#define DMA1_DMACC1CONTROL_RESERVED0_MASK                          0x03000000
#define DMA1_DMACC1CONTROL_RESERVED0_ALIGN                         0
#define DMA1_DMACC1CONTROL_RESERVED0_BITS                          2
#define DMA1_DMACC1CONTROL_RESERVED0_SHIFT                         24

/* DMA1 :: DMACC1Control :: C1DestWidth [23:21] */
#define Wr_DMA1_DMACC1Control_C1DestWidth(x) WriteRegBits(DMA1_DMACC1CONTROL,0xe00000,21,x)
#define Rd_DMA1_DMACC1Control_C1DestWidth(x) ReadRegBits(DMA1_DMACC1CONTROL,0xe00000,21)
#define DMA1_DMACC1CONTROL_C1DESTWIDTH_MASK                        0x00e00000
#define DMA1_DMACC1CONTROL_C1DESTWIDTH_ALIGN                       0
#define DMA1_DMACC1CONTROL_C1DESTWIDTH_BITS                        3
#define DMA1_DMACC1CONTROL_C1DESTWIDTH_SHIFT                       21

/* DMA1 :: DMACC1Control :: C1SrcWidth [20:18] */
#define Wr_DMA1_DMACC1Control_C1SrcWidth(x) WriteRegBits(DMA1_DMACC1CONTROL,0x1c0000,18,x)
#define Rd_DMA1_DMACC1Control_C1SrcWidth(x) ReadRegBits(DMA1_DMACC1CONTROL,0x1c0000,18)
#define DMA1_DMACC1CONTROL_C1SRCWIDTH_MASK                         0x001c0000
#define DMA1_DMACC1CONTROL_C1SRCWIDTH_ALIGN                        0
#define DMA1_DMACC1CONTROL_C1SRCWIDTH_BITS                         3
#define DMA1_DMACC1CONTROL_C1SRCWIDTH_SHIFT                        18

/* DMA1 :: DMACC1Control :: C1DestBurstSize [17:15] */
#define Wr_DMA1_DMACC1Control_C1DestBurstSize(x) WriteRegBits(DMA1_DMACC1CONTROL,0x38000,15,x)
#define Rd_DMA1_DMACC1Control_C1DestBurstSize(x) ReadRegBits(DMA1_DMACC1CONTROL,0x38000,15)
#define DMA1_DMACC1CONTROL_C1DESTBURSTSIZE_MASK                    0x00038000
#define DMA1_DMACC1CONTROL_C1DESTBURSTSIZE_ALIGN                   0
#define DMA1_DMACC1CONTROL_C1DESTBURSTSIZE_BITS                    3
#define DMA1_DMACC1CONTROL_C1DESTBURSTSIZE_SHIFT                   15

/* DMA1 :: DMACC1Control :: C1SrcBurstSize [14:12] */
#define Wr_DMA1_DMACC1Control_C1SrcBurstSize(x) WriteRegBits(DMA1_DMACC1CONTROL,0x7000,12,x)
#define Rd_DMA1_DMACC1Control_C1SrcBurstSize(x) ReadRegBits(DMA1_DMACC1CONTROL,0x7000,12)
#define DMA1_DMACC1CONTROL_C1SRCBURSTSIZE_MASK                     0x00007000
#define DMA1_DMACC1CONTROL_C1SRCBURSTSIZE_ALIGN                    0
#define DMA1_DMACC1CONTROL_C1SRCBURSTSIZE_BITS                     3
#define DMA1_DMACC1CONTROL_C1SRCBURSTSIZE_SHIFT                    12

/* DMA1 :: DMACC1Control :: C1TransferSize [11:00] */
#define Wr_DMA1_DMACC1Control_C1TransferSize(x) WriteRegBits(DMA1_DMACC1CONTROL,0xfff,0,x)
#define Rd_DMA1_DMACC1Control_C1TransferSize(x) ReadRegBits(DMA1_DMACC1CONTROL,0xfff,0)
#define DMA1_DMACC1CONTROL_C1TRANSFERSIZE_MASK                     0x00000fff
#define DMA1_DMACC1CONTROL_C1TRANSFERSIZE_ALIGN                    0
#define DMA1_DMACC1CONTROL_C1TRANSFERSIZE_BITS                     12
#define DMA1_DMACC1CONTROL_C1TRANSFERSIZE_SHIFT                    0


/****************************************************************************
 * DMA1 :: DMACC1Configuration
 ***************************************************************************/
/* DMA1 :: DMACC1Configuration :: reserved0 [31:19] */
#define DMA1_DMACC1CONFIGURATION_RESERVED0_MASK                    0xfff80000
#define DMA1_DMACC1CONFIGURATION_RESERVED0_ALIGN                   0
#define DMA1_DMACC1CONFIGURATION_RESERVED0_BITS                    13
#define DMA1_DMACC1CONFIGURATION_RESERVED0_SHIFT                   19

/* DMA1 :: DMACC1Configuration :: C1Halt [18:18] */
#define Wr_DMA1_DMACC1Configuration_C1Halt(x) WriteRegBits(DMA1_DMACC1CONFIGURATION,0x40000,18,x)
#define Rd_DMA1_DMACC1Configuration_C1Halt(x) ReadRegBits(DMA1_DMACC1CONFIGURATION,0x40000,18)
#define DMA1_DMACC1CONFIGURATION_C1HALT_MASK                       0x00040000
#define DMA1_DMACC1CONFIGURATION_C1HALT_ALIGN                      0
#define DMA1_DMACC1CONFIGURATION_C1HALT_BITS                       1
#define DMA1_DMACC1CONFIGURATION_C1HALT_SHIFT                      18

/* DMA1 :: DMACC1Configuration :: C1Active [17:17] */
#define Wr_DMA1_DMACC1Configuration_C1Active(x) WriteRegBits(DMA1_DMACC1CONFIGURATION,0x20000,17,x)
#define Rd_DMA1_DMACC1Configuration_C1Active(x) ReadRegBits(DMA1_DMACC1CONFIGURATION,0x20000,17)
#define DMA1_DMACC1CONFIGURATION_C1ACTIVE_MASK                     0x00020000
#define DMA1_DMACC1CONFIGURATION_C1ACTIVE_ALIGN                    0
#define DMA1_DMACC1CONFIGURATION_C1ACTIVE_BITS                     1
#define DMA1_DMACC1CONFIGURATION_C1ACTIVE_SHIFT                    17

/* DMA1 :: DMACC1Configuration :: C1Lock [16:16] */
#define Wr_DMA1_DMACC1Configuration_C1Lock(x) WriteRegBits(DMA1_DMACC1CONFIGURATION,0x10000,16,x)
#define Rd_DMA1_DMACC1Configuration_C1Lock(x) ReadRegBits(DMA1_DMACC1CONFIGURATION,0x10000,16)
#define DMA1_DMACC1CONFIGURATION_C1LOCK_MASK                       0x00010000
#define DMA1_DMACC1CONFIGURATION_C1LOCK_ALIGN                      0
#define DMA1_DMACC1CONFIGURATION_C1LOCK_BITS                       1
#define DMA1_DMACC1CONFIGURATION_C1LOCK_SHIFT                      16

/* DMA1 :: DMACC1Configuration :: C1IntTCMask [15:15] */
#define Wr_DMA1_DMACC1Configuration_C1IntTCMask(x) WriteRegBits(DMA1_DMACC1CONFIGURATION,0x8000,15,x)
#define Rd_DMA1_DMACC1Configuration_C1IntTCMask(x) ReadRegBits(DMA1_DMACC1CONFIGURATION,0x8000,15)
#define DMA1_DMACC1CONFIGURATION_C1INTTCMASK_MASK                  0x00008000
#define DMA1_DMACC1CONFIGURATION_C1INTTCMASK_ALIGN                 0
#define DMA1_DMACC1CONFIGURATION_C1INTTCMASK_BITS                  1
#define DMA1_DMACC1CONFIGURATION_C1INTTCMASK_SHIFT                 15

/* DMA1 :: DMACC1Configuration :: C1IntErrorMask [14:14] */
#define Wr_DMA1_DMACC1Configuration_C1IntErrorMask(x) WriteRegBits(DMA1_DMACC1CONFIGURATION,0x4000,14,x)
#define Rd_DMA1_DMACC1Configuration_C1IntErrorMask(x) ReadRegBits(DMA1_DMACC1CONFIGURATION,0x4000,14)
#define DMA1_DMACC1CONFIGURATION_C1INTERRORMASK_MASK               0x00004000
#define DMA1_DMACC1CONFIGURATION_C1INTERRORMASK_ALIGN              0
#define DMA1_DMACC1CONFIGURATION_C1INTERRORMASK_BITS               1
#define DMA1_DMACC1CONFIGURATION_C1INTERRORMASK_SHIFT              14

/* DMA1 :: DMACC1Configuration :: C1FlowCntrl [13:11] */
#define Wr_DMA1_DMACC1Configuration_C1FlowCntrl(x) WriteRegBits(DMA1_DMACC1CONFIGURATION,0x3800,11,x)
#define Rd_DMA1_DMACC1Configuration_C1FlowCntrl(x) ReadRegBits(DMA1_DMACC1CONFIGURATION,0x3800,11)
#define DMA1_DMACC1CONFIGURATION_C1FLOWCNTRL_MASK                  0x00003800
#define DMA1_DMACC1CONFIGURATION_C1FLOWCNTRL_ALIGN                 0
#define DMA1_DMACC1CONFIGURATION_C1FLOWCNTRL_BITS                  3
#define DMA1_DMACC1CONFIGURATION_C1FLOWCNTRL_SHIFT                 11

/* DMA1 :: DMACC1Configuration :: reserved1 [10:10] */
#define DMA1_DMACC1CONFIGURATION_RESERVED1_MASK                    0x00000400
#define DMA1_DMACC1CONFIGURATION_RESERVED1_ALIGN                   0
#define DMA1_DMACC1CONFIGURATION_RESERVED1_BITS                    1
#define DMA1_DMACC1CONFIGURATION_RESERVED1_SHIFT                   10

/* DMA1 :: DMACC1Configuration :: C1DestPeripheral [09:06] */
#define Wr_DMA1_DMACC1Configuration_C1DestPeripheral(x) WriteRegBits(DMA1_DMACC1CONFIGURATION,0x3c0,6,x)
#define Rd_DMA1_DMACC1Configuration_C1DestPeripheral(x) ReadRegBits(DMA1_DMACC1CONFIGURATION,0x3c0,6)
#define DMA1_DMACC1CONFIGURATION_C1DESTPERIPHERAL_MASK             0x000003c0
#define DMA1_DMACC1CONFIGURATION_C1DESTPERIPHERAL_ALIGN            0
#define DMA1_DMACC1CONFIGURATION_C1DESTPERIPHERAL_BITS             4
#define DMA1_DMACC1CONFIGURATION_C1DESTPERIPHERAL_SHIFT            6

/* DMA1 :: DMACC1Configuration :: reserved2 [05:05] */
#define DMA1_DMACC1CONFIGURATION_RESERVED2_MASK                    0x00000020
#define DMA1_DMACC1CONFIGURATION_RESERVED2_ALIGN                   0
#define DMA1_DMACC1CONFIGURATION_RESERVED2_BITS                    1
#define DMA1_DMACC1CONFIGURATION_RESERVED2_SHIFT                   5

/* DMA1 :: DMACC1Configuration :: C1SrcPeripheral [04:01] */
#define Wr_DMA1_DMACC1Configuration_C1SrcPeripheral(x) WriteRegBits(DMA1_DMACC1CONFIGURATION,0x1e,1,x)
#define Rd_DMA1_DMACC1Configuration_C1SrcPeripheral(x) ReadRegBits(DMA1_DMACC1CONFIGURATION,0x1e,1)
#define DMA1_DMACC1CONFIGURATION_C1SRCPERIPHERAL_MASK              0x0000001e
#define DMA1_DMACC1CONFIGURATION_C1SRCPERIPHERAL_ALIGN             0
#define DMA1_DMACC1CONFIGURATION_C1SRCPERIPHERAL_BITS              4
#define DMA1_DMACC1CONFIGURATION_C1SRCPERIPHERAL_SHIFT             1

/* DMA1 :: DMACC1Configuration :: C1Enable [00:00] */
#define Wr_DMA1_DMACC1Configuration_C1Enable(x) WriteRegBits(DMA1_DMACC1CONFIGURATION,0x1,0,x)
#define Rd_DMA1_DMACC1Configuration_C1Enable(x) ReadRegBits(DMA1_DMACC1CONFIGURATION,0x1,0)
#define DMA1_DMACC1CONFIGURATION_C1ENABLE_MASK                     0x00000001
#define DMA1_DMACC1CONFIGURATION_C1ENABLE_ALIGN                    0
#define DMA1_DMACC1CONFIGURATION_C1ENABLE_BITS                     1
#define DMA1_DMACC1CONFIGURATION_C1ENABLE_SHIFT                    0


/****************************************************************************
 * DMA1 :: DMACITCR
 ***************************************************************************/
/* DMA1 :: DMACITCR :: reserved0 [31:01] */
#define DMA1_DMACITCR_RESERVED0_MASK                               0xfffffffe
#define DMA1_DMACITCR_RESERVED0_ALIGN                              0
#define DMA1_DMACITCR_RESERVED0_BITS                               31
#define DMA1_DMACITCR_RESERVED0_SHIFT                              1

/* DMA1 :: DMACITCR :: TestEnable [00:00] */
#define Wr_DMA1_DMACITCR_TestEnable(x) WriteRegBits(DMA1_DMACITCR,0x1,0,x)
#define Rd_DMA1_DMACITCR_TestEnable(x) ReadRegBits(DMA1_DMACITCR,0x1,0)
#define DMA1_DMACITCR_TESTENABLE_MASK                              0x00000001
#define DMA1_DMACITCR_TESTENABLE_ALIGN                             0
#define DMA1_DMACITCR_TESTENABLE_BITS                              1
#define DMA1_DMACITCR_TESTENABLE_SHIFT                             0


/****************************************************************************
 * DMA1 :: DMACITOP1
 ***************************************************************************/
/* DMA1 :: DMACITOP1 :: reserved0 [31:16] */
#define DMA1_DMACITOP1_RESERVED0_MASK                              0xffff0000
#define DMA1_DMACITOP1_RESERVED0_ALIGN                             0
#define DMA1_DMACITOP1_RESERVED0_BITS                              16
#define DMA1_DMACITOP1_RESERVED0_SHIFT                             16

/* DMA1 :: DMACITOP1 :: DMACCLR [15:00] */
#define Wr_DMA1_DMACITOP1_DMACCLR(x) WriteRegBits(DMA1_DMACITOP1,0xffff,0,x)
#define Rd_DMA1_DMACITOP1_DMACCLR(x) ReadRegBits(DMA1_DMACITOP1,0xffff,0)
#define DMA1_DMACITOP1_DMACCLR_MASK                                0x0000ffff
#define DMA1_DMACITOP1_DMACCLR_ALIGN                               0
#define DMA1_DMACITOP1_DMACCLR_BITS                                16
#define DMA1_DMACITOP1_DMACCLR_SHIFT                               0


/****************************************************************************
 * DMA1 :: DMACITOP2
 ***************************************************************************/
/* DMA1 :: DMACITOP2 :: reserved0 [31:16] */
#define DMA1_DMACITOP2_RESERVED0_MASK                              0xffff0000
#define DMA1_DMACITOP2_RESERVED0_ALIGN                             0
#define DMA1_DMACITOP2_RESERVED0_BITS                              16
#define DMA1_DMACITOP2_RESERVED0_SHIFT                             16

/* DMA1 :: DMACITOP2 :: DMACTC [15:00] */
#define Wr_DMA1_DMACITOP2_DMACTC(x) WriteRegBits(DMA1_DMACITOP2,0xffff,0,x)
#define Rd_DMA1_DMACITOP2_DMACTC(x) ReadRegBits(DMA1_DMACITOP2,0xffff,0)
#define DMA1_DMACITOP2_DMACTC_MASK                                 0x0000ffff
#define DMA1_DMACITOP2_DMACTC_ALIGN                                0
#define DMA1_DMACITOP2_DMACTC_BITS                                 16
#define DMA1_DMACITOP2_DMACTC_SHIFT                                0


/****************************************************************************
 * DMA1 :: DMACITOP3
 ***************************************************************************/
/* DMA1 :: DMACITOP3 :: reserved0 [31:02] */
#define DMA1_DMACITOP3_RESERVED0_MASK                              0xfffffffc
#define DMA1_DMACITOP3_RESERVED0_ALIGN                             0
#define DMA1_DMACITOP3_RESERVED0_BITS                              30
#define DMA1_DMACITOP3_RESERVED0_SHIFT                             2

/* DMA1 :: DMACITOP3 :: INTTC [01:01] */
#define Wr_DMA1_DMACITOP3_INTTC(x) WriteRegBits(DMA1_DMACITOP3,0x2,1,x)
#define Rd_DMA1_DMACITOP3_INTTC(x) ReadRegBits(DMA1_DMACITOP3,0x2,1)
#define DMA1_DMACITOP3_INTTC_MASK                                  0x00000002
#define DMA1_DMACITOP3_INTTC_ALIGN                                 0
#define DMA1_DMACITOP3_INTTC_BITS                                  1
#define DMA1_DMACITOP3_INTTC_SHIFT                                 1

/* DMA1 :: DMACITOP3 :: INTERR [00:00] */
#define Wr_DMA1_DMACITOP3_INTERR(x) WriteRegBits(DMA1_DMACITOP3,0x1,0,x)
#define Rd_DMA1_DMACITOP3_INTERR(x) ReadRegBits(DMA1_DMACITOP3,0x1,0)
#define DMA1_DMACITOP3_INTERR_MASK                                 0x00000001
#define DMA1_DMACITOP3_INTERR_ALIGN                                0
#define DMA1_DMACITOP3_INTERR_BITS                                 1
#define DMA1_DMACITOP3_INTERR_SHIFT                                0


/****************************************************************************
 * DMA1 :: DMACPeriphID0
 ***************************************************************************/
/* DMA1 :: DMACPeriphID0 :: reserved0 [31:08] */
#define DMA1_DMACPERIPHID0_RESERVED0_MASK                          0xffffff00
#define DMA1_DMACPERIPHID0_RESERVED0_ALIGN                         0
#define DMA1_DMACPERIPHID0_RESERVED0_BITS                          24
#define DMA1_DMACPERIPHID0_RESERVED0_SHIFT                         8

/* DMA1 :: DMACPeriphID0 :: Partnumber0 [07:00] */
#define Wr_DMA1_DMACPeriphID0_Partnumber0(x) WriteRegBits(DMA1_DMACPERIPHID0,0xff,0,x)
#define Rd_DMA1_DMACPeriphID0_Partnumber0(x) ReadRegBits(DMA1_DMACPERIPHID0,0xff,0)
#define DMA1_DMACPERIPHID0_PARTNUMBER0_MASK                        0x000000ff
#define DMA1_DMACPERIPHID0_PARTNUMBER0_ALIGN                       0
#define DMA1_DMACPERIPHID0_PARTNUMBER0_BITS                        8
#define DMA1_DMACPERIPHID0_PARTNUMBER0_SHIFT                       0


/****************************************************************************
 * DMA1 :: DMACPeriphID1
 ***************************************************************************/
/* DMA1 :: DMACPeriphID1 :: reserved0 [31:08] */
#define DMA1_DMACPERIPHID1_RESERVED0_MASK                          0xffffff00
#define DMA1_DMACPERIPHID1_RESERVED0_ALIGN                         0
#define DMA1_DMACPERIPHID1_RESERVED0_BITS                          24
#define DMA1_DMACPERIPHID1_RESERVED0_SHIFT                         8

/* DMA1 :: DMACPeriphID1 :: Designer0 [07:04] */
#define Wr_DMA1_DMACPeriphID1_Designer0(x) WriteRegBits(DMA1_DMACPERIPHID1,0xf0,4,x)
#define Rd_DMA1_DMACPeriphID1_Designer0(x) ReadRegBits(DMA1_DMACPERIPHID1,0xf0,4)
#define DMA1_DMACPERIPHID1_DESIGNER0_MASK                          0x000000f0
#define DMA1_DMACPERIPHID1_DESIGNER0_ALIGN                         0
#define DMA1_DMACPERIPHID1_DESIGNER0_BITS                          4
#define DMA1_DMACPERIPHID1_DESIGNER0_SHIFT                         4

/* DMA1 :: DMACPeriphID1 :: Partnumber1 [03:00] */
#define Wr_DMA1_DMACPeriphID1_Partnumber1(x) WriteRegBits(DMA1_DMACPERIPHID1,0xf,0,x)
#define Rd_DMA1_DMACPeriphID1_Partnumber1(x) ReadRegBits(DMA1_DMACPERIPHID1,0xf,0)
#define DMA1_DMACPERIPHID1_PARTNUMBER1_MASK                        0x0000000f
#define DMA1_DMACPERIPHID1_PARTNUMBER1_ALIGN                       0
#define DMA1_DMACPERIPHID1_PARTNUMBER1_BITS                        4
#define DMA1_DMACPERIPHID1_PARTNUMBER1_SHIFT                       0


/****************************************************************************
 * DMA1 :: DMACPeriphID2
 ***************************************************************************/
/* DMA1 :: DMACPeriphID2 :: reserved0 [31:08] */
#define DMA1_DMACPERIPHID2_RESERVED0_MASK                          0xffffff00
#define DMA1_DMACPERIPHID2_RESERVED0_ALIGN                         0
#define DMA1_DMACPERIPHID2_RESERVED0_BITS                          24
#define DMA1_DMACPERIPHID2_RESERVED0_SHIFT                         8

/* DMA1 :: DMACPeriphID2 :: Revision [07:04] */
#define Wr_DMA1_DMACPeriphID2_Revision(x) WriteRegBits(DMA1_DMACPERIPHID2,0xf0,4,x)
#define Rd_DMA1_DMACPeriphID2_Revision(x) ReadRegBits(DMA1_DMACPERIPHID2,0xf0,4)
#define DMA1_DMACPERIPHID2_REVISION_MASK                           0x000000f0
#define DMA1_DMACPERIPHID2_REVISION_ALIGN                          0
#define DMA1_DMACPERIPHID2_REVISION_BITS                           4
#define DMA1_DMACPERIPHID2_REVISION_SHIFT                          4

/* DMA1 :: DMACPeriphID2 :: Designer1 [03:00] */
#define Wr_DMA1_DMACPeriphID2_Designer1(x) WriteRegBits(DMA1_DMACPERIPHID2,0xf,0,x)
#define Rd_DMA1_DMACPeriphID2_Designer1(x) ReadRegBits(DMA1_DMACPERIPHID2,0xf,0)
#define DMA1_DMACPERIPHID2_DESIGNER1_MASK                          0x0000000f
#define DMA1_DMACPERIPHID2_DESIGNER1_ALIGN                         0
#define DMA1_DMACPERIPHID2_DESIGNER1_BITS                          4
#define DMA1_DMACPERIPHID2_DESIGNER1_SHIFT                         0


/****************************************************************************
 * DMA1 :: DMACPeriphID3
 ***************************************************************************/
/* DMA1 :: DMACPeriphID3 :: reserved0 [31:08] */
#define DMA1_DMACPERIPHID3_RESERVED0_MASK                          0xffffff00
#define DMA1_DMACPERIPHID3_RESERVED0_ALIGN                         0
#define DMA1_DMACPERIPHID3_RESERVED0_BITS                          24
#define DMA1_DMACPERIPHID3_RESERVED0_SHIFT                         8

/* DMA1 :: DMACPeriphID3 :: Configuration [07:00] */
#define Wr_DMA1_DMACPeriphID3_Configuration(x) WriteRegBits(DMA1_DMACPERIPHID3,0xff,0,x)
#define Rd_DMA1_DMACPeriphID3_Configuration(x) ReadRegBits(DMA1_DMACPERIPHID3,0xff,0)
#define DMA1_DMACPERIPHID3_CONFIGURATION_MASK                      0x000000ff
#define DMA1_DMACPERIPHID3_CONFIGURATION_ALIGN                     0
#define DMA1_DMACPERIPHID3_CONFIGURATION_BITS                      8
#define DMA1_DMACPERIPHID3_CONFIGURATION_SHIFT                     0


/****************************************************************************
 * DMA1 :: DMACPCellID0
 ***************************************************************************/
/* DMA1 :: DMACPCellID0 :: reserved0 [31:08] */
#define DMA1_DMACPCELLID0_RESERVED0_MASK                           0xffffff00
#define DMA1_DMACPCELLID0_RESERVED0_ALIGN                          0
#define DMA1_DMACPCELLID0_RESERVED0_BITS                           24
#define DMA1_DMACPCELLID0_RESERVED0_SHIFT                          8

/* DMA1 :: DMACPCellID0 :: DMACPCellID0 [07:00] */
#define Wr_DMA1_DMACPCellID0_DMACPCellID0(x) WriteRegBits(DMA1_DMACPCELLID0,0xff,0,x)
#define Rd_DMA1_DMACPCellID0_DMACPCellID0(x) ReadRegBits(DMA1_DMACPCELLID0,0xff,0)
#define DMA1_DMACPCELLID0_DMACPCELLID0_MASK                        0x000000ff
#define DMA1_DMACPCELLID0_DMACPCELLID0_ALIGN                       0
#define DMA1_DMACPCELLID0_DMACPCELLID0_BITS                        8
#define DMA1_DMACPCELLID0_DMACPCELLID0_SHIFT                       0


/****************************************************************************
 * DMA1 :: DMACPCellID1
 ***************************************************************************/
/* DMA1 :: DMACPCellID1 :: reserved0 [31:08] */
#define DMA1_DMACPCELLID1_RESERVED0_MASK                           0xffffff00
#define DMA1_DMACPCELLID1_RESERVED0_ALIGN                          0
#define DMA1_DMACPCELLID1_RESERVED0_BITS                           24
#define DMA1_DMACPCELLID1_RESERVED0_SHIFT                          8

/* DMA1 :: DMACPCellID1 :: DMACPCellID1 [07:00] */
#define Wr_DMA1_DMACPCellID1_DMACPCellID1(x) WriteRegBits(DMA1_DMACPCELLID1,0xff,0,x)
#define Rd_DMA1_DMACPCellID1_DMACPCellID1(x) ReadRegBits(DMA1_DMACPCELLID1,0xff,0)
#define DMA1_DMACPCELLID1_DMACPCELLID1_MASK                        0x000000ff
#define DMA1_DMACPCELLID1_DMACPCELLID1_ALIGN                       0
#define DMA1_DMACPCELLID1_DMACPCELLID1_BITS                        8
#define DMA1_DMACPCELLID1_DMACPCELLID1_SHIFT                       0


/****************************************************************************
 * DMA1 :: DMACPCellID2
 ***************************************************************************/
/* DMA1 :: DMACPCellID2 :: reserved0 [31:08] */
#define DMA1_DMACPCELLID2_RESERVED0_MASK                           0xffffff00
#define DMA1_DMACPCELLID2_RESERVED0_ALIGN                          0
#define DMA1_DMACPCELLID2_RESERVED0_BITS                           24
#define DMA1_DMACPCELLID2_RESERVED0_SHIFT                          8

/* DMA1 :: DMACPCellID2 :: DMACPCellID2 [07:00] */
#define Wr_DMA1_DMACPCellID2_DMACPCellID2(x) WriteRegBits(DMA1_DMACPCELLID2,0xff,0,x)
#define Rd_DMA1_DMACPCellID2_DMACPCellID2(x) ReadRegBits(DMA1_DMACPCELLID2,0xff,0)
#define DMA1_DMACPCELLID2_DMACPCELLID2_MASK                        0x000000ff
#define DMA1_DMACPCELLID2_DMACPCELLID2_ALIGN                       0
#define DMA1_DMACPCELLID2_DMACPCELLID2_BITS                        8
#define DMA1_DMACPCELLID2_DMACPCELLID2_SHIFT                       0


/****************************************************************************
 * DMA1 :: DMACPCellID3
 ***************************************************************************/
/* DMA1 :: DMACPCellID3 :: reserved0 [31:08] */
#define DMA1_DMACPCELLID3_RESERVED0_MASK                           0xffffff00
#define DMA1_DMACPCELLID3_RESERVED0_ALIGN                          0
#define DMA1_DMACPCELLID3_RESERVED0_BITS                           24
#define DMA1_DMACPCELLID3_RESERVED0_SHIFT                          8

/* DMA1 :: DMACPCellID3 :: DMACPCellID3 [07:00] */
#define Wr_DMA1_DMACPCellID3_DMACPCellID3(x) WriteRegBits(DMA1_DMACPCELLID3,0xff,0,x)
#define Rd_DMA1_DMACPCellID3_DMACPCellID3(x) ReadRegBits(DMA1_DMACPCELLID3,0xff,0)
#define DMA1_DMACPCELLID3_DMACPCELLID3_MASK                        0x000000ff
#define DMA1_DMACPCELLID3_DMACPCELLID3_ALIGN                       0
#define DMA1_DMACPCELLID3_DMACPCELLID3_BITS                        8
#define DMA1_DMACPCELLID3_DMACPCELLID3_SHIFT                       0


/****************************************************************************
 * bcm89530_sys_cfg_ETH
 ***************************************************************************/
/****************************************************************************
 * ETH :: eth_ctrl
 ***************************************************************************/
/* ETH :: eth_ctrl :: reserved0 [31:16] */
#define ETH_ETH_CTRL_RESERVED0_MASK                                0xffff0000
#define ETH_ETH_CTRL_RESERVED0_ALIGN                               0
#define ETH_ETH_CTRL_RESERVED0_BITS                                16
#define ETH_ETH_CTRL_RESERVED0_SHIFT                               16

/* ETH :: eth_ctrl :: oobbpe [15:15] */
#define Wr_ETH_eth_ctrl_oobbpe(x) WriteRegBits(ETH_ETH_CTRL,0x8000,15,x)
#define Rd_ETH_eth_ctrl_oobbpe(x) ReadRegBits(ETH_ETH_CTRL,0x8000,15)
#define ETH_ETH_CTRL_OOBBPE_MASK                                   0x00008000
#define ETH_ETH_CTRL_OOBBPE_ALIGN                                  0
#define ETH_ETH_CTRL_OOBBPE_BITS                                   1
#define ETH_ETH_CTRL_OOBBPE_SHIFT                                  15

/* ETH :: eth_ctrl :: be [14:14] */
#define Wr_ETH_eth_ctrl_be(x) WriteRegBits(ETH_ETH_CTRL,0x4000,14,x)
#define Rd_ETH_eth_ctrl_be(x) ReadRegBits(ETH_ETH_CTRL,0x4000,14)
#define ETH_ETH_CTRL_BE_MASK                                       0x00004000
#define ETH_ETH_CTRL_BE_ALIGN                                      0
#define ETH_ETH_CTRL_BE_BITS                                       1
#define ETH_ETH_CTRL_BE_SHIFT                                      14

/* ETH :: eth_ctrl :: fbp [13:13] */
#define Wr_ETH_eth_ctrl_fbp(x) WriteRegBits(ETH_ETH_CTRL,0x2000,13,x)
#define Rd_ETH_eth_ctrl_fbp(x) ReadRegBits(ETH_ETH_CTRL,0x2000,13)
#define ETH_ETH_CTRL_FBP_MASK                                      0x00002000
#define ETH_ETH_CTRL_FBP_ALIGN                                     0
#define ETH_ETH_CTRL_FBP_BITS                                      1
#define ETH_ETH_CTRL_FBP_SHIFT                                     13

/* ETH :: eth_ctrl :: bcr [12:12] */
#define Wr_ETH_eth_ctrl_bcr(x) WriteRegBits(ETH_ETH_CTRL,0x1000,12,x)
#define Rd_ETH_eth_ctrl_bcr(x) ReadRegBits(ETH_ETH_CTRL,0x1000,12)
#define ETH_ETH_CTRL_BCR_MASK                                      0x00001000
#define ETH_ETH_CTRL_BCR_ALIGN                                     0
#define ETH_ETH_CTRL_BCR_BITS                                      1
#define ETH_ETH_CTRL_BCR_SHIFT                                     12

/* ETH :: eth_ctrl :: reserved1 [11:11] */
#define ETH_ETH_CTRL_RESERVED1_MASK                                0x00000800
#define ETH_ETH_CTRL_RESERVED1_ALIGN                               0
#define ETH_ETH_CTRL_RESERVED1_BITS                                1
#define ETH_ETH_CTRL_RESERVED1_SHIFT                               11

/* ETH :: eth_ctrl :: led1 [10:08] */
#define Wr_ETH_eth_ctrl_led1(x) WriteRegBits(ETH_ETH_CTRL,0x700,8,x)
#define Rd_ETH_eth_ctrl_led1(x) ReadRegBits(ETH_ETH_CTRL,0x700,8)
#define ETH_ETH_CTRL_LED1_MASK                                     0x00000700
#define ETH_ETH_CTRL_LED1_ALIGN                                    0
#define ETH_ETH_CTRL_LED1_BITS                                     3
#define ETH_ETH_CTRL_LED1_SHIFT                                    8

/* ETH :: eth_ctrl :: reserved2 [07:07] */
#define ETH_ETH_CTRL_RESERVED2_MASK                                0x00000080
#define ETH_ETH_CTRL_RESERVED2_ALIGN                               0
#define ETH_ETH_CTRL_RESERVED2_BITS                                1
#define ETH_ETH_CTRL_RESERVED2_SHIFT                               7

/* ETH :: eth_ctrl :: led0 [06:04] */
#define Wr_ETH_eth_ctrl_led0(x) WriteRegBits(ETH_ETH_CTRL,0x70,4,x)
#define Rd_ETH_eth_ctrl_led0(x) ReadRegBits(ETH_ETH_CTRL,0x70,4)
#define ETH_ETH_CTRL_LED0_MASK                                     0x00000070
#define ETH_ETH_CTRL_LED0_ALIGN                                    0
#define ETH_ETH_CTRL_LED0_BITS                                     3
#define ETH_ETH_CTRL_LED0_SHIFT                                    4

/* ETH :: eth_ctrl :: men [03:03] */
#define Wr_ETH_eth_ctrl_men(x) WriteRegBits(ETH_ETH_CTRL,0x8,3,x)
#define Rd_ETH_eth_ctrl_men(x) ReadRegBits(ETH_ETH_CTRL,0x8,3)
#define ETH_ETH_CTRL_MEN_MASK                                      0x00000008
#define ETH_ETH_CTRL_MEN_ALIGN                                     0
#define ETH_ETH_CTRL_MEN_BITS                                      1
#define ETH_ETH_CTRL_MEN_SHIFT                                     3

/* ETH :: eth_ctrl :: clronrd [02:02] */
#define Wr_ETH_eth_ctrl_clronrd(x) WriteRegBits(ETH_ETH_CTRL,0x4,2,x)
#define Rd_ETH_eth_ctrl_clronrd(x) ReadRegBits(ETH_ETH_CTRL,0x4,2)
#define ETH_ETH_CTRL_CLRONRD_MASK                                  0x00000004
#define ETH_ETH_CTRL_CLRONRD_ALIGN                                 0
#define ETH_ETH_CTRL_CLRONRD_BITS                                  1
#define ETH_ETH_CTRL_CLRONRD_SHIFT                                 2

/* ETH :: eth_ctrl :: grs [01:01] */
#define Wr_ETH_eth_ctrl_grs(x) WriteRegBits(ETH_ETH_CTRL,0x2,1,x)
#define Rd_ETH_eth_ctrl_grs(x) ReadRegBits(ETH_ETH_CTRL,0x2,1)
#define ETH_ETH_CTRL_GRS_MASK                                      0x00000002
#define ETH_ETH_CTRL_GRS_ALIGN                                     0
#define ETH_ETH_CTRL_GRS_BITS                                      1
#define ETH_ETH_CTRL_GRS_SHIFT                                     1

/* ETH :: eth_ctrl :: gts [00:00] */
#define Wr_ETH_eth_ctrl_gts(x) WriteRegBits(ETH_ETH_CTRL,0x1,0,x)
#define Rd_ETH_eth_ctrl_gts(x) ReadRegBits(ETH_ETH_CTRL,0x1,0)
#define ETH_ETH_CTRL_GTS_MASK                                      0x00000001
#define ETH_ETH_CTRL_GTS_ALIGN                                     0
#define ETH_ETH_CTRL_GTS_BITS                                      1
#define ETH_ETH_CTRL_GTS_SHIFT                                     0


/****************************************************************************
 * ETH :: intr_mask
 ***************************************************************************/
/* ETH :: intr_mask :: reserved0 [31:17] */
#define ETH_INTR_MASK_RESERVED0_MASK                               0xfffe0000
#define ETH_INTR_MASK_RESERVED0_ALIGN                              0
#define ETH_INTR_MASK_RESERVED0_BITS                               15
#define ETH_INTR_MASK_RESERVED0_SHIFT                              17

/* ETH :: intr_mask :: phy_mask [16:16] */
#define Wr_ETH_intr_mask_phy_mask(x) WriteRegBits(ETH_INTR_MASK,0x10000,16,x)
#define Rd_ETH_intr_mask_phy_mask(x) ReadRegBits(ETH_INTR_MASK,0x10000,16)
#define ETH_INTR_MASK_PHY_MASK_MASK                                0x00010000
#define ETH_INTR_MASK_PHY_MASK_ALIGN                               0
#define ETH_INTR_MASK_PHY_MASK_BITS                                1
#define ETH_INTR_MASK_PHY_MASK_SHIFT                               16

/* ETH :: intr_mask :: rthr_mask [15:15] */
#define Wr_ETH_intr_mask_rthr_mask(x) WriteRegBits(ETH_INTR_MASK,0x8000,15,x)
#define Rd_ETH_intr_mask_rthr_mask(x) ReadRegBits(ETH_INTR_MASK,0x8000,15)
#define ETH_INTR_MASK_RTHR_MASK_MASK                               0x00008000
#define ETH_INTR_MASK_RTHR_MASK_ALIGN                              0
#define ETH_INTR_MASK_RTHR_MASK_BITS                               1
#define ETH_INTR_MASK_RTHR_MASK_SHIFT                              15

/* ETH :: intr_mask :: tthr_mask [14:14] */
#define Wr_ETH_intr_mask_tthr_mask(x) WriteRegBits(ETH_INTR_MASK,0x4000,14,x)
#define Rd_ETH_intr_mask_tthr_mask(x) ReadRegBits(ETH_INTR_MASK,0x4000,14)
#define ETH_INTR_MASK_TTHR_MASK_MASK                               0x00004000
#define ETH_INTR_MASK_TTHR_MASK_ALIGN                              0
#define ETH_INTR_MASK_TTHR_MASK_BITS                               1
#define ETH_INTR_MASK_TTHR_MASK_SHIFT                              14

/* ETH :: intr_mask :: rhlt_mask [13:13] */
#define Wr_ETH_intr_mask_rhlt_mask(x) WriteRegBits(ETH_INTR_MASK,0x2000,13,x)
#define Rd_ETH_intr_mask_rhlt_mask(x) ReadRegBits(ETH_INTR_MASK,0x2000,13)
#define ETH_INTR_MASK_RHLT_MASK_MASK                               0x00002000
#define ETH_INTR_MASK_RHLT_MASK_ALIGN                              0
#define ETH_INTR_MASK_RHLT_MASK_BITS                               1
#define ETH_INTR_MASK_RHLT_MASK_SHIFT                              13

/* ETH :: intr_mask :: thlt_mask [12:12] */
#define Wr_ETH_intr_mask_thlt_mask(x) WriteRegBits(ETH_INTR_MASK,0x1000,12,x)
#define Rd_ETH_intr_mask_thlt_mask(x) ReadRegBits(ETH_INTR_MASK,0x1000,12)
#define ETH_INTR_MASK_THLT_MASK_MASK                               0x00001000
#define ETH_INTR_MASK_THLT_MASK_ALIGN                              0
#define ETH_INTR_MASK_THLT_MASK_BITS                               1
#define ETH_INTR_MASK_THLT_MASK_SHIFT                              12

/* ETH :: intr_mask :: rov_mask [11:11] */
#define Wr_ETH_intr_mask_rov_mask(x) WriteRegBits(ETH_INTR_MASK,0x800,11,x)
#define Rd_ETH_intr_mask_rov_mask(x) ReadRegBits(ETH_INTR_MASK,0x800,11)
#define ETH_INTR_MASK_ROV_MASK_MASK                                0x00000800
#define ETH_INTR_MASK_ROV_MASK_ALIGN                               0
#define ETH_INTR_MASK_ROV_MASK_BITS                                1
#define ETH_INTR_MASK_ROV_MASK_SHIFT                               11

/* ETH :: intr_mask :: tun_mask [10:10] */
#define Wr_ETH_intr_mask_tun_mask(x) WriteRegBits(ETH_INTR_MASK,0x400,10,x)
#define Rd_ETH_intr_mask_tun_mask(x) ReadRegBits(ETH_INTR_MASK,0x400,10)
#define ETH_INTR_MASK_TUN_MASK_MASK                                0x00000400
#define ETH_INTR_MASK_TUN_MASK_ALIGN                               0
#define ETH_INTR_MASK_TUN_MASK_BITS                                1
#define ETH_INTR_MASK_TUN_MASK_SHIFT                               10

/* ETH :: intr_mask :: tec_mask [09:09] */
#define Wr_ETH_intr_mask_tec_mask(x) WriteRegBits(ETH_INTR_MASK,0x200,9,x)
#define Rd_ETH_intr_mask_tec_mask(x) ReadRegBits(ETH_INTR_MASK,0x200,9)
#define ETH_INTR_MASK_TEC_MASK_MASK                                0x00000200
#define ETH_INTR_MASK_TEC_MASK_ALIGN                               0
#define ETH_INTR_MASK_TEC_MASK_BITS                                1
#define ETH_INTR_MASK_TEC_MASK_SHIFT                               9

/* ETH :: intr_mask :: tlc_mask [08:08] */
#define Wr_ETH_intr_mask_tlc_mask(x) WriteRegBits(ETH_INTR_MASK,0x100,8,x)
#define Rd_ETH_intr_mask_tlc_mask(x) ReadRegBits(ETH_INTR_MASK,0x100,8)
#define ETH_INTR_MASK_TLC_MASK_MASK                                0x00000100
#define ETH_INTR_MASK_TLC_MASK_ALIGN                               0
#define ETH_INTR_MASK_TLC_MASK_BITS                                1
#define ETH_INTR_MASK_TLC_MASK_SHIFT                               8

/* ETH :: intr_mask :: rxb_mask [07:07] */
#define Wr_ETH_intr_mask_rxb_mask(x) WriteRegBits(ETH_INTR_MASK,0x80,7,x)
#define Rd_ETH_intr_mask_rxb_mask(x) ReadRegBits(ETH_INTR_MASK,0x80,7)
#define ETH_INTR_MASK_RXB_MASK_MASK                                0x00000080
#define ETH_INTR_MASK_RXB_MASK_ALIGN                               0
#define ETH_INTR_MASK_RXB_MASK_BITS                                1
#define ETH_INTR_MASK_RXB_MASK_SHIFT                               7

/* ETH :: intr_mask :: txb_mask [06:06] */
#define Wr_ETH_intr_mask_txb_mask(x) WriteRegBits(ETH_INTR_MASK,0x40,6,x)
#define Rd_ETH_intr_mask_txb_mask(x) ReadRegBits(ETH_INTR_MASK,0x40,6)
#define ETH_INTR_MASK_TXB_MASK_MASK                                0x00000040
#define ETH_INTR_MASK_TXB_MASK_ALIGN                               0
#define ETH_INTR_MASK_TXB_MASK_BITS                                1
#define ETH_INTR_MASK_TXB_MASK_SHIFT                               6

/* ETH :: intr_mask :: rxf_mask [05:05] */
#define Wr_ETH_intr_mask_rxf_mask(x) WriteRegBits(ETH_INTR_MASK,0x20,5,x)
#define Rd_ETH_intr_mask_rxf_mask(x) ReadRegBits(ETH_INTR_MASK,0x20,5)
#define ETH_INTR_MASK_RXF_MASK_MASK                                0x00000020
#define ETH_INTR_MASK_RXF_MASK_ALIGN                               0
#define ETH_INTR_MASK_RXF_MASK_BITS                                1
#define ETH_INTR_MASK_RXF_MASK_SHIFT                               5

/* ETH :: intr_mask :: txf_mask [04:04] */
#define Wr_ETH_intr_mask_txf_mask(x) WriteRegBits(ETH_INTR_MASK,0x10,4,x)
#define Rd_ETH_intr_mask_txf_mask(x) ReadRegBits(ETH_INTR_MASK,0x10,4)
#define ETH_INTR_MASK_TXF_MASK_MASK                                0x00000010
#define ETH_INTR_MASK_TXF_MASK_ALIGN                               0
#define ETH_INTR_MASK_TXF_MASK_BITS                                1
#define ETH_INTR_MASK_TXF_MASK_SHIFT                               4

/* ETH :: intr_mask :: berr_mask [03:03] */
#define Wr_ETH_intr_mask_berr_mask(x) WriteRegBits(ETH_INTR_MASK,0x8,3,x)
#define Rd_ETH_intr_mask_berr_mask(x) ReadRegBits(ETH_INTR_MASK,0x8,3)
#define ETH_INTR_MASK_BERR_MASK_MASK                               0x00000008
#define ETH_INTR_MASK_BERR_MASK_ALIGN                              0
#define ETH_INTR_MASK_BERR_MASK_BITS                               1
#define ETH_INTR_MASK_BERR_MASK_SHIFT                              3

/* ETH :: intr_mask :: reserved1 [02:02] */
#define ETH_INTR_MASK_RESERVED1_MASK                               0x00000004
#define ETH_INTR_MASK_RESERVED1_ALIGN                              0
#define ETH_INTR_MASK_RESERVED1_BITS                               1
#define ETH_INTR_MASK_RESERVED1_SHIFT                              2

/* ETH :: intr_mask :: grsc_mask [01:01] */
#define Wr_ETH_intr_mask_grsc_mask(x) WriteRegBits(ETH_INTR_MASK,0x2,1,x)
#define Rd_ETH_intr_mask_grsc_mask(x) ReadRegBits(ETH_INTR_MASK,0x2,1)
#define ETH_INTR_MASK_GRSC_MASK_MASK                               0x00000002
#define ETH_INTR_MASK_GRSC_MASK_ALIGN                              0
#define ETH_INTR_MASK_GRSC_MASK_BITS                               1
#define ETH_INTR_MASK_GRSC_MASK_SHIFT                              1

/* ETH :: intr_mask :: gtsc_mask [00:00] */
#define Wr_ETH_intr_mask_gtsc_mask(x) WriteRegBits(ETH_INTR_MASK,0x1,0,x)
#define Rd_ETH_intr_mask_gtsc_mask(x) ReadRegBits(ETH_INTR_MASK,0x1,0)
#define ETH_INTR_MASK_GTSC_MASK_MASK                               0x00000001
#define ETH_INTR_MASK_GTSC_MASK_ALIGN                              0
#define ETH_INTR_MASK_GTSC_MASK_BITS                               1
#define ETH_INTR_MASK_GTSC_MASK_SHIFT                              0


/****************************************************************************
 * ETH :: intr
 ***************************************************************************/
/* ETH :: intr :: reserved0 [31:17] */
#define ETH_INTR_RESERVED0_MASK                                    0xfffe0000
#define ETH_INTR_RESERVED0_ALIGN                                   0
#define ETH_INTR_RESERVED0_BITS                                    15
#define ETH_INTR_RESERVED0_SHIFT                                   17

/* ETH :: intr :: phy [16:16] */
#define Wr_ETH_intr_phy(x) WriteRegBits(ETH_INTR,0x10000,16,x)
#define Rd_ETH_intr_phy(x) ReadRegBits(ETH_INTR,0x10000,16)
#define ETH_INTR_PHY_MASK                                          0x00010000
#define ETH_INTR_PHY_ALIGN                                         0
#define ETH_INTR_PHY_BITS                                          1
#define ETH_INTR_PHY_SHIFT                                         16

/* ETH :: intr :: rthr [15:15] */
#define Wr_ETH_intr_rthr(x) WriteRegBits(ETH_INTR,0x8000,15,x)
#define Rd_ETH_intr_rthr(x) ReadRegBits(ETH_INTR,0x8000,15)
#define ETH_INTR_RTHR_MASK                                         0x00008000
#define ETH_INTR_RTHR_ALIGN                                        0
#define ETH_INTR_RTHR_BITS                                         1
#define ETH_INTR_RTHR_SHIFT                                        15

/* ETH :: intr :: tthr [14:14] */
#define Wr_ETH_intr_tthr(x) WriteRegBits(ETH_INTR,0x4000,14,x)
#define Rd_ETH_intr_tthr(x) ReadRegBits(ETH_INTR,0x4000,14)
#define ETH_INTR_TTHR_MASK                                         0x00004000
#define ETH_INTR_TTHR_ALIGN                                        0
#define ETH_INTR_TTHR_BITS                                         1
#define ETH_INTR_TTHR_SHIFT                                        14

/* ETH :: intr :: rhlt [13:13] */
#define Wr_ETH_intr_rhlt(x) WriteRegBits(ETH_INTR,0x2000,13,x)
#define Rd_ETH_intr_rhlt(x) ReadRegBits(ETH_INTR,0x2000,13)
#define ETH_INTR_RHLT_MASK                                         0x00002000
#define ETH_INTR_RHLT_ALIGN                                        0
#define ETH_INTR_RHLT_BITS                                         1
#define ETH_INTR_RHLT_SHIFT                                        13

/* ETH :: intr :: thlt [12:12] */
#define Wr_ETH_intr_thlt(x) WriteRegBits(ETH_INTR,0x1000,12,x)
#define Rd_ETH_intr_thlt(x) ReadRegBits(ETH_INTR,0x1000,12)
#define ETH_INTR_THLT_MASK                                         0x00001000
#define ETH_INTR_THLT_ALIGN                                        0
#define ETH_INTR_THLT_BITS                                         1
#define ETH_INTR_THLT_SHIFT                                        12

/* ETH :: intr :: rov [11:11] */
#define Wr_ETH_intr_rov(x) WriteRegBits(ETH_INTR,0x800,11,x)
#define Rd_ETH_intr_rov(x) ReadRegBits(ETH_INTR,0x800,11)
#define ETH_INTR_ROV_MASK                                          0x00000800
#define ETH_INTR_ROV_ALIGN                                         0
#define ETH_INTR_ROV_BITS                                          1
#define ETH_INTR_ROV_SHIFT                                         11

/* ETH :: intr :: tun [10:10] */
#define Wr_ETH_intr_tun(x) WriteRegBits(ETH_INTR,0x400,10,x)
#define Rd_ETH_intr_tun(x) ReadRegBits(ETH_INTR,0x400,10)
#define ETH_INTR_TUN_MASK                                          0x00000400
#define ETH_INTR_TUN_ALIGN                                         0
#define ETH_INTR_TUN_BITS                                          1
#define ETH_INTR_TUN_SHIFT                                         10

/* ETH :: intr :: tec [09:09] */
#define Wr_ETH_intr_tec(x) WriteRegBits(ETH_INTR,0x200,9,x)
#define Rd_ETH_intr_tec(x) ReadRegBits(ETH_INTR,0x200,9)
#define ETH_INTR_TEC_MASK                                          0x00000200
#define ETH_INTR_TEC_ALIGN                                         0
#define ETH_INTR_TEC_BITS                                          1
#define ETH_INTR_TEC_SHIFT                                         9

/* ETH :: intr :: tlc [08:08] */
#define Wr_ETH_intr_tlc(x) WriteRegBits(ETH_INTR,0x100,8,x)
#define Rd_ETH_intr_tlc(x) ReadRegBits(ETH_INTR,0x100,8)
#define ETH_INTR_TLC_MASK                                          0x00000100
#define ETH_INTR_TLC_ALIGN                                         0
#define ETH_INTR_TLC_BITS                                          1
#define ETH_INTR_TLC_SHIFT                                         8

/* ETH :: intr :: rxb [07:07] */
#define Wr_ETH_intr_rxb(x) WriteRegBits(ETH_INTR,0x80,7,x)
#define Rd_ETH_intr_rxb(x) ReadRegBits(ETH_INTR,0x80,7)
#define ETH_INTR_RXB_MASK                                          0x00000080
#define ETH_INTR_RXB_ALIGN                                         0
#define ETH_INTR_RXB_BITS                                          1
#define ETH_INTR_RXB_SHIFT                                         7

/* ETH :: intr :: txb [06:06] */
#define Wr_ETH_intr_txb(x) WriteRegBits(ETH_INTR,0x40,6,x)
#define Rd_ETH_intr_txb(x) ReadRegBits(ETH_INTR,0x40,6)
#define ETH_INTR_TXB_MASK                                          0x00000040
#define ETH_INTR_TXB_ALIGN                                         0
#define ETH_INTR_TXB_BITS                                          1
#define ETH_INTR_TXB_SHIFT                                         6

/* ETH :: intr :: rxf [05:05] */
#define Wr_ETH_intr_rxf(x) WriteRegBits(ETH_INTR,0x20,5,x)
#define Rd_ETH_intr_rxf(x) ReadRegBits(ETH_INTR,0x20,5)
#define ETH_INTR_RXF_MASK                                          0x00000020
#define ETH_INTR_RXF_ALIGN                                         0
#define ETH_INTR_RXF_BITS                                          1
#define ETH_INTR_RXF_SHIFT                                         5

/* ETH :: intr :: txf [04:04] */
#define Wr_ETH_intr_txf(x) WriteRegBits(ETH_INTR,0x10,4,x)
#define Rd_ETH_intr_txf(x) ReadRegBits(ETH_INTR,0x10,4)
#define ETH_INTR_TXF_MASK                                          0x00000010
#define ETH_INTR_TXF_ALIGN                                         0
#define ETH_INTR_TXF_BITS                                          1
#define ETH_INTR_TXF_SHIFT                                         4

/* ETH :: intr :: berr [03:03] */
#define Wr_ETH_intr_berr(x) WriteRegBits(ETH_INTR,0x8,3,x)
#define Rd_ETH_intr_berr(x) ReadRegBits(ETH_INTR,0x8,3)
#define ETH_INTR_BERR_MASK                                         0x00000008
#define ETH_INTR_BERR_ALIGN                                        0
#define ETH_INTR_BERR_BITS                                         1
#define ETH_INTR_BERR_SHIFT                                        3

/* ETH :: intr :: reserved1 [02:02] */
#define ETH_INTR_RESERVED1_MASK                                    0x00000004
#define ETH_INTR_RESERVED1_ALIGN                                   0
#define ETH_INTR_RESERVED1_BITS                                    1
#define ETH_INTR_RESERVED1_SHIFT                                   2

/* ETH :: intr :: grsc [01:01] */
#define Wr_ETH_intr_grsc(x) WriteRegBits(ETH_INTR,0x2,1,x)
#define Rd_ETH_intr_grsc(x) ReadRegBits(ETH_INTR,0x2,1)
#define ETH_INTR_GRSC_MASK                                         0x00000002
#define ETH_INTR_GRSC_ALIGN                                        0
#define ETH_INTR_GRSC_BITS                                         1
#define ETH_INTR_GRSC_SHIFT                                        1

/* ETH :: intr :: gtsc [00:00] */
#define Wr_ETH_intr_gtsc(x) WriteRegBits(ETH_INTR,0x1,0,x)
#define Rd_ETH_intr_gtsc(x) ReadRegBits(ETH_INTR,0x1,0)
#define ETH_INTR_GTSC_MASK                                         0x00000001
#define ETH_INTR_GTSC_ALIGN                                        0
#define ETH_INTR_GTSC_BITS                                         1
#define ETH_INTR_GTSC_SHIFT                                        0


/****************************************************************************
 * ETH :: intr_raw
 ***************************************************************************/
/* ETH :: intr_raw :: reserved0 [31:17] */
#define ETH_INTR_RAW_RESERVED0_MASK                                0xfffe0000
#define ETH_INTR_RAW_RESERVED0_ALIGN                               0
#define ETH_INTR_RAW_RESERVED0_BITS                                15
#define ETH_INTR_RAW_RESERVED0_SHIFT                               17

/* ETH :: intr_raw :: phy_raw [16:16] */
#define Wr_ETH_intr_raw_phy_raw(x) WriteRegBits(ETH_INTR_RAW,0x10000,16,x)
#define Rd_ETH_intr_raw_phy_raw(x) ReadRegBits(ETH_INTR_RAW,0x10000,16)
#define ETH_INTR_RAW_PHY_RAW_MASK                                  0x00010000
#define ETH_INTR_RAW_PHY_RAW_ALIGN                                 0
#define ETH_INTR_RAW_PHY_RAW_BITS                                  1
#define ETH_INTR_RAW_PHY_RAW_SHIFT                                 16

/* ETH :: intr_raw :: rthr_raw [15:15] */
#define Wr_ETH_intr_raw_rthr_raw(x) WriteRegBits(ETH_INTR_RAW,0x8000,15,x)
#define Rd_ETH_intr_raw_rthr_raw(x) ReadRegBits(ETH_INTR_RAW,0x8000,15)
#define ETH_INTR_RAW_RTHR_RAW_MASK                                 0x00008000
#define ETH_INTR_RAW_RTHR_RAW_ALIGN                                0
#define ETH_INTR_RAW_RTHR_RAW_BITS                                 1
#define ETH_INTR_RAW_RTHR_RAW_SHIFT                                15

/* ETH :: intr_raw :: tthr_raw [14:14] */
#define Wr_ETH_intr_raw_tthr_raw(x) WriteRegBits(ETH_INTR_RAW,0x4000,14,x)
#define Rd_ETH_intr_raw_tthr_raw(x) ReadRegBits(ETH_INTR_RAW,0x4000,14)
#define ETH_INTR_RAW_TTHR_RAW_MASK                                 0x00004000
#define ETH_INTR_RAW_TTHR_RAW_ALIGN                                0
#define ETH_INTR_RAW_TTHR_RAW_BITS                                 1
#define ETH_INTR_RAW_TTHR_RAW_SHIFT                                14

/* ETH :: intr_raw :: rhlt_raw [13:13] */
#define Wr_ETH_intr_raw_rhlt_raw(x) WriteRegBits(ETH_INTR_RAW,0x2000,13,x)
#define Rd_ETH_intr_raw_rhlt_raw(x) ReadRegBits(ETH_INTR_RAW,0x2000,13)
#define ETH_INTR_RAW_RHLT_RAW_MASK                                 0x00002000
#define ETH_INTR_RAW_RHLT_RAW_ALIGN                                0
#define ETH_INTR_RAW_RHLT_RAW_BITS                                 1
#define ETH_INTR_RAW_RHLT_RAW_SHIFT                                13

/* ETH :: intr_raw :: thlt_raw [12:12] */
#define Wr_ETH_intr_raw_thlt_raw(x) WriteRegBits(ETH_INTR_RAW,0x1000,12,x)
#define Rd_ETH_intr_raw_thlt_raw(x) ReadRegBits(ETH_INTR_RAW,0x1000,12)
#define ETH_INTR_RAW_THLT_RAW_MASK                                 0x00001000
#define ETH_INTR_RAW_THLT_RAW_ALIGN                                0
#define ETH_INTR_RAW_THLT_RAW_BITS                                 1
#define ETH_INTR_RAW_THLT_RAW_SHIFT                                12

/* ETH :: intr_raw :: rov_raw [11:11] */
#define Wr_ETH_intr_raw_rov_raw(x) WriteRegBits(ETH_INTR_RAW,0x800,11,x)
#define Rd_ETH_intr_raw_rov_raw(x) ReadRegBits(ETH_INTR_RAW,0x800,11)
#define ETH_INTR_RAW_ROV_RAW_MASK                                  0x00000800
#define ETH_INTR_RAW_ROV_RAW_ALIGN                                 0
#define ETH_INTR_RAW_ROV_RAW_BITS                                  1
#define ETH_INTR_RAW_ROV_RAW_SHIFT                                 11

/* ETH :: intr_raw :: tun_raw [10:10] */
#define Wr_ETH_intr_raw_tun_raw(x) WriteRegBits(ETH_INTR_RAW,0x400,10,x)
#define Rd_ETH_intr_raw_tun_raw(x) ReadRegBits(ETH_INTR_RAW,0x400,10)
#define ETH_INTR_RAW_TUN_RAW_MASK                                  0x00000400
#define ETH_INTR_RAW_TUN_RAW_ALIGN                                 0
#define ETH_INTR_RAW_TUN_RAW_BITS                                  1
#define ETH_INTR_RAW_TUN_RAW_SHIFT                                 10

/* ETH :: intr_raw :: tec_raw [09:09] */
#define Wr_ETH_intr_raw_tec_raw(x) WriteRegBits(ETH_INTR_RAW,0x200,9,x)
#define Rd_ETH_intr_raw_tec_raw(x) ReadRegBits(ETH_INTR_RAW,0x200,9)
#define ETH_INTR_RAW_TEC_RAW_MASK                                  0x00000200
#define ETH_INTR_RAW_TEC_RAW_ALIGN                                 0
#define ETH_INTR_RAW_TEC_RAW_BITS                                  1
#define ETH_INTR_RAW_TEC_RAW_SHIFT                                 9

/* ETH :: intr_raw :: tlc_raw [08:08] */
#define Wr_ETH_intr_raw_tlc_raw(x) WriteRegBits(ETH_INTR_RAW,0x100,8,x)
#define Rd_ETH_intr_raw_tlc_raw(x) ReadRegBits(ETH_INTR_RAW,0x100,8)
#define ETH_INTR_RAW_TLC_RAW_MASK                                  0x00000100
#define ETH_INTR_RAW_TLC_RAW_ALIGN                                 0
#define ETH_INTR_RAW_TLC_RAW_BITS                                  1
#define ETH_INTR_RAW_TLC_RAW_SHIFT                                 8

/* ETH :: intr_raw :: rxb_raw [07:07] */
#define Wr_ETH_intr_raw_rxb_raw(x) WriteRegBits(ETH_INTR_RAW,0x80,7,x)
#define Rd_ETH_intr_raw_rxb_raw(x) ReadRegBits(ETH_INTR_RAW,0x80,7)
#define ETH_INTR_RAW_RXB_RAW_MASK                                  0x00000080
#define ETH_INTR_RAW_RXB_RAW_ALIGN                                 0
#define ETH_INTR_RAW_RXB_RAW_BITS                                  1
#define ETH_INTR_RAW_RXB_RAW_SHIFT                                 7

/* ETH :: intr_raw :: txb_raw [06:06] */
#define Wr_ETH_intr_raw_txb_raw(x) WriteRegBits(ETH_INTR_RAW,0x40,6,x)
#define Rd_ETH_intr_raw_txb_raw(x) ReadRegBits(ETH_INTR_RAW,0x40,6)
#define ETH_INTR_RAW_TXB_RAW_MASK                                  0x00000040
#define ETH_INTR_RAW_TXB_RAW_ALIGN                                 0
#define ETH_INTR_RAW_TXB_RAW_BITS                                  1
#define ETH_INTR_RAW_TXB_RAW_SHIFT                                 6

/* ETH :: intr_raw :: rxf_raw [05:05] */
#define Wr_ETH_intr_raw_rxf_raw(x) WriteRegBits(ETH_INTR_RAW,0x20,5,x)
#define Rd_ETH_intr_raw_rxf_raw(x) ReadRegBits(ETH_INTR_RAW,0x20,5)
#define ETH_INTR_RAW_RXF_RAW_MASK                                  0x00000020
#define ETH_INTR_RAW_RXF_RAW_ALIGN                                 0
#define ETH_INTR_RAW_RXF_RAW_BITS                                  1
#define ETH_INTR_RAW_RXF_RAW_SHIFT                                 5

/* ETH :: intr_raw :: txf_raw [04:04] */
#define Wr_ETH_intr_raw_txf_raw(x) WriteRegBits(ETH_INTR_RAW,0x10,4,x)
#define Rd_ETH_intr_raw_txf_raw(x) ReadRegBits(ETH_INTR_RAW,0x10,4)
#define ETH_INTR_RAW_TXF_RAW_MASK                                  0x00000010
#define ETH_INTR_RAW_TXF_RAW_ALIGN                                 0
#define ETH_INTR_RAW_TXF_RAW_BITS                                  1
#define ETH_INTR_RAW_TXF_RAW_SHIFT                                 4

/* ETH :: intr_raw :: berr_raw [03:03] */
#define Wr_ETH_intr_raw_berr_raw(x) WriteRegBits(ETH_INTR_RAW,0x8,3,x)
#define Rd_ETH_intr_raw_berr_raw(x) ReadRegBits(ETH_INTR_RAW,0x8,3)
#define ETH_INTR_RAW_BERR_RAW_MASK                                 0x00000008
#define ETH_INTR_RAW_BERR_RAW_ALIGN                                0
#define ETH_INTR_RAW_BERR_RAW_BITS                                 1
#define ETH_INTR_RAW_BERR_RAW_SHIFT                                3

/* ETH :: intr_raw :: reserved1 [02:02] */
#define ETH_INTR_RAW_RESERVED1_MASK                                0x00000004
#define ETH_INTR_RAW_RESERVED1_ALIGN                               0
#define ETH_INTR_RAW_RESERVED1_BITS                                1
#define ETH_INTR_RAW_RESERVED1_SHIFT                               2

/* ETH :: intr_raw :: grsc_raw [01:01] */
#define Wr_ETH_intr_raw_grsc_raw(x) WriteRegBits(ETH_INTR_RAW,0x2,1,x)
#define Rd_ETH_intr_raw_grsc_raw(x) ReadRegBits(ETH_INTR_RAW,0x2,1)
#define ETH_INTR_RAW_GRSC_RAW_MASK                                 0x00000002
#define ETH_INTR_RAW_GRSC_RAW_ALIGN                                0
#define ETH_INTR_RAW_GRSC_RAW_BITS                                 1
#define ETH_INTR_RAW_GRSC_RAW_SHIFT                                1

/* ETH :: intr_raw :: gtsc_raw [00:00] */
#define Wr_ETH_intr_raw_gtsc_raw(x) WriteRegBits(ETH_INTR_RAW,0x1,0,x)
#define Rd_ETH_intr_raw_gtsc_raw(x) ReadRegBits(ETH_INTR_RAW,0x1,0)
#define ETH_INTR_RAW_GTSC_RAW_MASK                                 0x00000001
#define ETH_INTR_RAW_GTSC_RAW_ALIGN                                0
#define ETH_INTR_RAW_GTSC_RAW_BITS                                 1
#define ETH_INTR_RAW_GTSC_RAW_SHIFT                                0


/****************************************************************************
 * ETH :: intr_clr
 ***************************************************************************/
/* ETH :: intr_clr :: reserved0 [31:17] */
#define ETH_INTR_CLR_RESERVED0_MASK                                0xfffe0000
#define ETH_INTR_CLR_RESERVED0_ALIGN                               0
#define ETH_INTR_CLR_RESERVED0_BITS                                15
#define ETH_INTR_CLR_RESERVED0_SHIFT                               17

/* ETH :: intr_clr :: phy_clr [16:16] */
#define Wr_ETH_intr_clr_phy_clr(x) WriteRegBits(ETH_INTR_CLR,0x10000,16,x)
#define Rd_ETH_intr_clr_phy_clr(x) ReadRegBits(ETH_INTR_CLR,0x10000,16)
#define ETH_INTR_CLR_PHY_CLR_MASK                                  0x00010000
#define ETH_INTR_CLR_PHY_CLR_ALIGN                                 0
#define ETH_INTR_CLR_PHY_CLR_BITS                                  1
#define ETH_INTR_CLR_PHY_CLR_SHIFT                                 16

/* ETH :: intr_clr :: rthr_clr [15:15] */
#define Wr_ETH_intr_clr_rthr_clr(x) WriteRegBits(ETH_INTR_CLR,0x8000,15,x)
#define Rd_ETH_intr_clr_rthr_clr(x) ReadRegBits(ETH_INTR_CLR,0x8000,15)
#define ETH_INTR_CLR_RTHR_CLR_MASK                                 0x00008000
#define ETH_INTR_CLR_RTHR_CLR_ALIGN                                0
#define ETH_INTR_CLR_RTHR_CLR_BITS                                 1
#define ETH_INTR_CLR_RTHR_CLR_SHIFT                                15

/* ETH :: intr_clr :: tthr_clr [14:14] */
#define Wr_ETH_intr_clr_tthr_clr(x) WriteRegBits(ETH_INTR_CLR,0x4000,14,x)
#define Rd_ETH_intr_clr_tthr_clr(x) ReadRegBits(ETH_INTR_CLR,0x4000,14)
#define ETH_INTR_CLR_TTHR_CLR_MASK                                 0x00004000
#define ETH_INTR_CLR_TTHR_CLR_ALIGN                                0
#define ETH_INTR_CLR_TTHR_CLR_BITS                                 1
#define ETH_INTR_CLR_TTHR_CLR_SHIFT                                14

/* ETH :: intr_clr :: rhlt_clr [13:13] */
#define Wr_ETH_intr_clr_rhlt_clr(x) WriteRegBits(ETH_INTR_CLR,0x2000,13,x)
#define Rd_ETH_intr_clr_rhlt_clr(x) ReadRegBits(ETH_INTR_CLR,0x2000,13)
#define ETH_INTR_CLR_RHLT_CLR_MASK                                 0x00002000
#define ETH_INTR_CLR_RHLT_CLR_ALIGN                                0
#define ETH_INTR_CLR_RHLT_CLR_BITS                                 1
#define ETH_INTR_CLR_RHLT_CLR_SHIFT                                13

/* ETH :: intr_clr :: thlt_clr [12:12] */
#define Wr_ETH_intr_clr_thlt_clr(x) WriteRegBits(ETH_INTR_CLR,0x1000,12,x)
#define Rd_ETH_intr_clr_thlt_clr(x) ReadRegBits(ETH_INTR_CLR,0x1000,12)
#define ETH_INTR_CLR_THLT_CLR_MASK                                 0x00001000
#define ETH_INTR_CLR_THLT_CLR_ALIGN                                0
#define ETH_INTR_CLR_THLT_CLR_BITS                                 1
#define ETH_INTR_CLR_THLT_CLR_SHIFT                                12

/* ETH :: intr_clr :: rov_clr [11:11] */
#define Wr_ETH_intr_clr_rov_clr(x) WriteRegBits(ETH_INTR_CLR,0x800,11,x)
#define Rd_ETH_intr_clr_rov_clr(x) ReadRegBits(ETH_INTR_CLR,0x800,11)
#define ETH_INTR_CLR_ROV_CLR_MASK                                  0x00000800
#define ETH_INTR_CLR_ROV_CLR_ALIGN                                 0
#define ETH_INTR_CLR_ROV_CLR_BITS                                  1
#define ETH_INTR_CLR_ROV_CLR_SHIFT                                 11

/* ETH :: intr_clr :: tun_clr [10:10] */
#define Wr_ETH_intr_clr_tun_clr(x) WriteRegBits(ETH_INTR_CLR,0x400,10,x)
#define Rd_ETH_intr_clr_tun_clr(x) ReadRegBits(ETH_INTR_CLR,0x400,10)
#define ETH_INTR_CLR_TUN_CLR_MASK                                  0x00000400
#define ETH_INTR_CLR_TUN_CLR_ALIGN                                 0
#define ETH_INTR_CLR_TUN_CLR_BITS                                  1
#define ETH_INTR_CLR_TUN_CLR_SHIFT                                 10

/* ETH :: intr_clr :: tec_clr [09:09] */
#define Wr_ETH_intr_clr_tec_clr(x) WriteRegBits(ETH_INTR_CLR,0x200,9,x)
#define Rd_ETH_intr_clr_tec_clr(x) ReadRegBits(ETH_INTR_CLR,0x200,9)
#define ETH_INTR_CLR_TEC_CLR_MASK                                  0x00000200
#define ETH_INTR_CLR_TEC_CLR_ALIGN                                 0
#define ETH_INTR_CLR_TEC_CLR_BITS                                  1
#define ETH_INTR_CLR_TEC_CLR_SHIFT                                 9

/* ETH :: intr_clr :: tlc_clr [08:08] */
#define Wr_ETH_intr_clr_tlc_clr(x) WriteRegBits(ETH_INTR_CLR,0x100,8,x)
#define Rd_ETH_intr_clr_tlc_clr(x) ReadRegBits(ETH_INTR_CLR,0x100,8)
#define ETH_INTR_CLR_TLC_CLR_MASK                                  0x00000100
#define ETH_INTR_CLR_TLC_CLR_ALIGN                                 0
#define ETH_INTR_CLR_TLC_CLR_BITS                                  1
#define ETH_INTR_CLR_TLC_CLR_SHIFT                                 8

/* ETH :: intr_clr :: rxb_clr [07:07] */
#define Wr_ETH_intr_clr_rxb_clr(x) WriteRegBits(ETH_INTR_CLR,0x80,7,x)
#define Rd_ETH_intr_clr_rxb_clr(x) ReadRegBits(ETH_INTR_CLR,0x80,7)
#define ETH_INTR_CLR_RXB_CLR_MASK                                  0x00000080
#define ETH_INTR_CLR_RXB_CLR_ALIGN                                 0
#define ETH_INTR_CLR_RXB_CLR_BITS                                  1
#define ETH_INTR_CLR_RXB_CLR_SHIFT                                 7

/* ETH :: intr_clr :: txb_clr [06:06] */
#define Wr_ETH_intr_clr_txb_clr(x) WriteRegBits(ETH_INTR_CLR,0x40,6,x)
#define Rd_ETH_intr_clr_txb_clr(x) ReadRegBits(ETH_INTR_CLR,0x40,6)
#define ETH_INTR_CLR_TXB_CLR_MASK                                  0x00000040
#define ETH_INTR_CLR_TXB_CLR_ALIGN                                 0
#define ETH_INTR_CLR_TXB_CLR_BITS                                  1
#define ETH_INTR_CLR_TXB_CLR_SHIFT                                 6

/* ETH :: intr_clr :: rxf_clr [05:05] */
#define Wr_ETH_intr_clr_rxf_clr(x) WriteRegBits(ETH_INTR_CLR,0x20,5,x)
#define Rd_ETH_intr_clr_rxf_clr(x) ReadRegBits(ETH_INTR_CLR,0x20,5)
#define ETH_INTR_CLR_RXF_CLR_MASK                                  0x00000020
#define ETH_INTR_CLR_RXF_CLR_ALIGN                                 0
#define ETH_INTR_CLR_RXF_CLR_BITS                                  1
#define ETH_INTR_CLR_RXF_CLR_SHIFT                                 5

/* ETH :: intr_clr :: txf_clr [04:04] */
#define Wr_ETH_intr_clr_txf_clr(x) WriteRegBits(ETH_INTR_CLR,0x10,4,x)
#define Rd_ETH_intr_clr_txf_clr(x) ReadRegBits(ETH_INTR_CLR,0x10,4)
#define ETH_INTR_CLR_TXF_CLR_MASK                                  0x00000010
#define ETH_INTR_CLR_TXF_CLR_ALIGN                                 0
#define ETH_INTR_CLR_TXF_CLR_BITS                                  1
#define ETH_INTR_CLR_TXF_CLR_SHIFT                                 4

/* ETH :: intr_clr :: berr_clr [03:03] */
#define Wr_ETH_intr_clr_berr_clr(x) WriteRegBits(ETH_INTR_CLR,0x8,3,x)
#define Rd_ETH_intr_clr_berr_clr(x) ReadRegBits(ETH_INTR_CLR,0x8,3)
#define ETH_INTR_CLR_BERR_CLR_MASK                                 0x00000008
#define ETH_INTR_CLR_BERR_CLR_ALIGN                                0
#define ETH_INTR_CLR_BERR_CLR_BITS                                 1
#define ETH_INTR_CLR_BERR_CLR_SHIFT                                3

/* ETH :: intr_clr :: reserved1 [02:02] */
#define ETH_INTR_CLR_RESERVED1_MASK                                0x00000004
#define ETH_INTR_CLR_RESERVED1_ALIGN                               0
#define ETH_INTR_CLR_RESERVED1_BITS                                1
#define ETH_INTR_CLR_RESERVED1_SHIFT                               2

/* ETH :: intr_clr :: grsc_clr [01:01] */
#define Wr_ETH_intr_clr_grsc_clr(x) WriteRegBits(ETH_INTR_CLR,0x2,1,x)
#define Rd_ETH_intr_clr_grsc_clr(x) ReadRegBits(ETH_INTR_CLR,0x2,1)
#define ETH_INTR_CLR_GRSC_CLR_MASK                                 0x00000002
#define ETH_INTR_CLR_GRSC_CLR_ALIGN                                0
#define ETH_INTR_CLR_GRSC_CLR_BITS                                 1
#define ETH_INTR_CLR_GRSC_CLR_SHIFT                                1

/* ETH :: intr_clr :: gtsc_clr [00:00] */
#define Wr_ETH_intr_clr_gtsc_clr(x) WriteRegBits(ETH_INTR_CLR,0x1,0,x)
#define Rd_ETH_intr_clr_gtsc_clr(x) ReadRegBits(ETH_INTR_CLR,0x1,0)
#define ETH_INTR_CLR_GTSC_CLR_MASK                                 0x00000001
#define ETH_INTR_CLR_GTSC_CLR_ALIGN                                0
#define ETH_INTR_CLR_GTSC_CLR_BITS                                 1
#define ETH_INTR_CLR_GTSC_CLR_SHIFT                                0


/****************************************************************************
 * ETH :: mcaddrf0
 ***************************************************************************/
/* ETH :: mcaddrf0 :: mcaddrf0 [31:00] */
#define Wr_ETH_mcaddrf0_mcaddrf0(x) WriteReg(ETH_MCADDRF0,x)
#define Rd_ETH_mcaddrf0_mcaddrf0(x) ReadReg(ETH_MCADDRF0)
#define ETH_MCADDRF0_MCADDRF0_MASK                                 0xffffffff
#define ETH_MCADDRF0_MCADDRF0_ALIGN                                0
#define ETH_MCADDRF0_MCADDRF0_BITS                                 32
#define ETH_MCADDRF0_MCADDRF0_SHIFT                                0


/****************************************************************************
 * ETH :: mcaddrf1
 ***************************************************************************/
/* ETH :: mcaddrf1 :: mcaddrf1 [31:00] */
#define Wr_ETH_mcaddrf1_mcaddrf1(x) WriteReg(ETH_MCADDRF1,x)
#define Rd_ETH_mcaddrf1_mcaddrf1(x) ReadReg(ETH_MCADDRF1)
#define ETH_MCADDRF1_MCADDRF1_MASK                                 0xffffffff
#define ETH_MCADDRF1_MCADDRF1_ALIGN                                0
#define ETH_MCADDRF1_MCADDRF1_BITS                                 32
#define ETH_MCADDRF1_MCADDRF1_SHIFT                                0


/****************************************************************************
 * ETH :: lsaddr0
 ***************************************************************************/
/* ETH :: lsaddr0 :: lssabyte0 [31:24] */
#define Wr_ETH_lsaddr0_lssabyte0(x) WriteRegBits(ETH_LSADDR0,0xff000000,24,x)
#define Rd_ETH_lsaddr0_lssabyte0(x) ReadRegBits(ETH_LSADDR0,0xff000000,24)
#define ETH_LSADDR0_LSSABYTE0_MASK                                 0xff000000
#define ETH_LSADDR0_LSSABYTE0_ALIGN                                0
#define ETH_LSADDR0_LSSABYTE0_BITS                                 8
#define ETH_LSADDR0_LSSABYTE0_SHIFT                                24

/* ETH :: lsaddr0 :: lssabyte1 [23:16] */
#define Wr_ETH_lsaddr0_lssabyte1(x) WriteRegBits(ETH_LSADDR0,0xff0000,16,x)
#define Rd_ETH_lsaddr0_lssabyte1(x) ReadRegBits(ETH_LSADDR0,0xff0000,16)
#define ETH_LSADDR0_LSSABYTE1_MASK                                 0x00ff0000
#define ETH_LSADDR0_LSSABYTE1_ALIGN                                0
#define ETH_LSADDR0_LSSABYTE1_BITS                                 8
#define ETH_LSADDR0_LSSABYTE1_SHIFT                                16

/* ETH :: lsaddr0 :: lssabyte2 [15:08] */
#define Wr_ETH_lsaddr0_lssabyte2(x) WriteRegBits(ETH_LSADDR0,0xff00,8,x)
#define Rd_ETH_lsaddr0_lssabyte2(x) ReadRegBits(ETH_LSADDR0,0xff00,8)
#define ETH_LSADDR0_LSSABYTE2_MASK                                 0x0000ff00
#define ETH_LSADDR0_LSSABYTE2_ALIGN                                0
#define ETH_LSADDR0_LSSABYTE2_BITS                                 8
#define ETH_LSADDR0_LSSABYTE2_SHIFT                                8

/* ETH :: lsaddr0 :: lssabyte3 [07:00] */
#define Wr_ETH_lsaddr0_lssabyte3(x) WriteRegBits(ETH_LSADDR0,0xff,0,x)
#define Rd_ETH_lsaddr0_lssabyte3(x) ReadRegBits(ETH_LSADDR0,0xff,0)
#define ETH_LSADDR0_LSSABYTE3_MASK                                 0x000000ff
#define ETH_LSADDR0_LSSABYTE3_ALIGN                                0
#define ETH_LSADDR0_LSSABYTE3_BITS                                 8
#define ETH_LSADDR0_LSSABYTE3_SHIFT                                0


/****************************************************************************
 * ETH :: lscaddr1
 ***************************************************************************/
/* ETH :: lscaddr1 :: reserved0 [31:16] */
#define ETH_LSCADDR1_RESERVED0_MASK                                0xffff0000
#define ETH_LSCADDR1_RESERVED0_ALIGN                               0
#define ETH_LSCADDR1_RESERVED0_BITS                                16
#define ETH_LSCADDR1_RESERVED0_SHIFT                               16

/* ETH :: lscaddr1 :: lssabyte4 [15:08] */
#define Wr_ETH_lscaddr1_lssabyte4(x) WriteRegBits(ETH_LSCADDR1,0xff00,8,x)
#define Rd_ETH_lscaddr1_lssabyte4(x) ReadRegBits(ETH_LSCADDR1,0xff00,8)
#define ETH_LSCADDR1_LSSABYTE4_MASK                                0x0000ff00
#define ETH_LSCADDR1_LSSABYTE4_ALIGN                               0
#define ETH_LSCADDR1_LSSABYTE4_BITS                                8
#define ETH_LSCADDR1_LSSABYTE4_SHIFT                               8

/* ETH :: lscaddr1 :: lssabyte5 [07:00] */
#define Wr_ETH_lscaddr1_lssabyte5(x) WriteRegBits(ETH_LSCADDR1,0xff,0,x)
#define Rd_ETH_lscaddr1_lssabyte5(x) ReadRegBits(ETH_LSCADDR1,0xff,0)
#define ETH_LSCADDR1_LSSABYTE5_MASK                                0x000000ff
#define ETH_LSCADDR1_LSSABYTE5_ALIGN                               0
#define ETH_LSCADDR1_LSSABYTE5_BITS                                8
#define ETH_LSCADDR1_LSSABYTE5_SHIFT                               0


/****************************************************************************
 * ETH :: ouiaddr0
 ***************************************************************************/
/* ETH :: ouiaddr0 :: ouisabyte0 [31:24] */
#define Wr_ETH_ouiaddr0_ouisabyte0(x) WriteRegBits(ETH_OUIADDR0,0xff000000,24,x)
#define Rd_ETH_ouiaddr0_ouisabyte0(x) ReadRegBits(ETH_OUIADDR0,0xff000000,24)
#define ETH_OUIADDR0_OUISABYTE0_MASK                               0xff000000
#define ETH_OUIADDR0_OUISABYTE0_ALIGN                              0
#define ETH_OUIADDR0_OUISABYTE0_BITS                               8
#define ETH_OUIADDR0_OUISABYTE0_SHIFT                              24

/* ETH :: ouiaddr0 :: ouisabyte1 [23:16] */
#define Wr_ETH_ouiaddr0_ouisabyte1(x) WriteRegBits(ETH_OUIADDR0,0xff0000,16,x)
#define Rd_ETH_ouiaddr0_ouisabyte1(x) ReadRegBits(ETH_OUIADDR0,0xff0000,16)
#define ETH_OUIADDR0_OUISABYTE1_MASK                               0x00ff0000
#define ETH_OUIADDR0_OUISABYTE1_ALIGN                              0
#define ETH_OUIADDR0_OUISABYTE1_BITS                               8
#define ETH_OUIADDR0_OUISABYTE1_SHIFT                              16

/* ETH :: ouiaddr0 :: ouisabyte2 [15:08] */
#define Wr_ETH_ouiaddr0_ouisabyte2(x) WriteRegBits(ETH_OUIADDR0,0xff00,8,x)
#define Rd_ETH_ouiaddr0_ouisabyte2(x) ReadRegBits(ETH_OUIADDR0,0xff00,8)
#define ETH_OUIADDR0_OUISABYTE2_MASK                               0x0000ff00
#define ETH_OUIADDR0_OUISABYTE2_ALIGN                              0
#define ETH_OUIADDR0_OUISABYTE2_BITS                               8
#define ETH_OUIADDR0_OUISABYTE2_SHIFT                              8

/* ETH :: ouiaddr0 :: ouisabyte3 [07:00] */
#define Wr_ETH_ouiaddr0_ouisabyte3(x) WriteRegBits(ETH_OUIADDR0,0xff,0,x)
#define Rd_ETH_ouiaddr0_ouisabyte3(x) ReadRegBits(ETH_OUIADDR0,0xff,0)
#define ETH_OUIADDR0_OUISABYTE3_MASK                               0x000000ff
#define ETH_OUIADDR0_OUISABYTE3_ALIGN                              0
#define ETH_OUIADDR0_OUISABYTE3_BITS                               8
#define ETH_OUIADDR0_OUISABYTE3_SHIFT                              0


/****************************************************************************
 * ETH :: ouiaddr1
 ***************************************************************************/
/* ETH :: ouiaddr1 :: reserved0 [31:16] */
#define ETH_OUIADDR1_RESERVED0_MASK                                0xffff0000
#define ETH_OUIADDR1_RESERVED0_ALIGN                               0
#define ETH_OUIADDR1_RESERVED0_BITS                                16
#define ETH_OUIADDR1_RESERVED0_SHIFT                               16

/* ETH :: ouiaddr1 :: ouisabyte4 [15:08] */
#define Wr_ETH_ouiaddr1_ouisabyte4(x) WriteRegBits(ETH_OUIADDR1,0xff00,8,x)
#define Rd_ETH_ouiaddr1_ouisabyte4(x) ReadRegBits(ETH_OUIADDR1,0xff00,8)
#define ETH_OUIADDR1_OUISABYTE4_MASK                               0x0000ff00
#define ETH_OUIADDR1_OUISABYTE4_ALIGN                              0
#define ETH_OUIADDR1_OUISABYTE4_BITS                               8
#define ETH_OUIADDR1_OUISABYTE4_SHIFT                              8

/* ETH :: ouiaddr1 :: ouisabyte5 [07:00] */
#define Wr_ETH_ouiaddr1_ouisabyte5(x) WriteRegBits(ETH_OUIADDR1,0xff,0,x)
#define Rd_ETH_ouiaddr1_ouisabyte5(x) ReadRegBits(ETH_OUIADDR1,0xff,0)
#define ETH_OUIADDR1_OUISABYTE5_MASK                               0x000000ff
#define ETH_OUIADDR1_OUISABYTE5_ALIGN                              0
#define ETH_OUIADDR1_OUISABYTE5_BITS                               8
#define ETH_OUIADDR1_OUISABYTE5_SHIFT                              0


/****************************************************************************
 * ETH :: phyctrl
 ***************************************************************************/
/* ETH :: phyctrl :: ext [31:31] */
#define Wr_ETH_phyctrl_ext(x) WriteRegBits(ETH_PHYCTRL,0x80000000,31,x)
#define Rd_ETH_phyctrl_ext(x) ReadRegBits(ETH_PHYCTRL,0x80000000,31)
#define ETH_PHYCTRL_EXT_MASK                                       0x80000000
#define ETH_PHYCTRL_EXT_ALIGN                                      0
#define ETH_PHYCTRL_EXT_BITS                                       1
#define ETH_PHYCTRL_EXT_SHIFT                                      31

/* ETH :: phyctrl :: reserved0 [30:12] */
#define ETH_PHYCTRL_RESERVED0_MASK                                 0x7ffff000
#define ETH_PHYCTRL_RESERVED0_ALIGN                                0
#define ETH_PHYCTRL_RESERVED0_BITS                                 19
#define ETH_PHYCTRL_RESERVED0_SHIFT                                12

/* ETH :: phyctrl :: trim [11:08] */
#define Wr_ETH_phyctrl_trim(x) WriteRegBits(ETH_PHYCTRL,0xf00,8,x)
#define Rd_ETH_phyctrl_trim(x) ReadRegBits(ETH_PHYCTRL,0xf00,8)
#define ETH_PHYCTRL_TRIM_MASK                                      0x00000f00
#define ETH_PHYCTRL_TRIM_ALIGN                                     0
#define ETH_PHYCTRL_TRIM_BITS                                      4
#define ETH_PHYCTRL_TRIM_SHIFT                                     8

/* ETH :: phyctrl :: reserved1 [07:06] */
#define ETH_PHYCTRL_RESERVED1_MASK                                 0x000000c0
#define ETH_PHYCTRL_RESERVED1_ALIGN                                0
#define ETH_PHYCTRL_RESERVED1_BITS                                 2
#define ETH_PHYCTRL_RESERVED1_SHIFT                                6

/* ETH :: phyctrl :: ttst [05:05] */
#define Wr_ETH_phyctrl_ttst(x) WriteRegBits(ETH_PHYCTRL,0x20,5,x)
#define Rd_ETH_phyctrl_ttst(x) ReadRegBits(ETH_PHYCTRL,0x20,5)
#define ETH_PHYCTRL_TTST_MASK                                      0x00000020
#define ETH_PHYCTRL_TTST_ALIGN                                     0
#define ETH_PHYCTRL_TTST_BITS                                      1
#define ETH_PHYCTRL_TTST_SHIFT                                     5

/* ETH :: phyctrl :: idq [04:04] */
#define Wr_ETH_phyctrl_idq(x) WriteRegBits(ETH_PHYCTRL,0x10,4,x)
#define Rd_ETH_phyctrl_idq(x) ReadRegBits(ETH_PHYCTRL,0x10,4)
#define ETH_PHYCTRL_IDQ_MASK                                       0x00000010
#define ETH_PHYCTRL_IDQ_ALIGN                                      0
#define ETH_PHYCTRL_IDQ_BITS                                       1
#define ETH_PHYCTRL_IDQ_SHIFT                                      4

/* ETH :: phyctrl :: det [03:03] */
#define Wr_ETH_phyctrl_det(x) WriteRegBits(ETH_PHYCTRL,0x8,3,x)
#define Rd_ETH_phyctrl_det(x) ReadRegBits(ETH_PHYCTRL,0x8,3)
#define ETH_PHYCTRL_DET_MASK                                       0x00000008
#define ETH_PHYCTRL_DET_ALIGN                                      0
#define ETH_PHYCTRL_DET_BITS                                       1
#define ETH_PHYCTRL_DET_SHIFT                                      3

/* ETH :: phyctrl :: pdb [02:02] */
#define Wr_ETH_phyctrl_pdb(x) WriteRegBits(ETH_PHYCTRL,0x4,2,x)
#define Rd_ETH_phyctrl_pdb(x) ReadRegBits(ETH_PHYCTRL,0x4,2)
#define ETH_PHYCTRL_PDB_MASK                                       0x00000004
#define ETH_PHYCTRL_PDB_ALIGN                                      0
#define ETH_PHYCTRL_PDB_BITS                                       1
#define ETH_PHYCTRL_PDB_SHIFT                                      2

/* ETH :: phyctrl :: pdd [01:01] */
#define Wr_ETH_phyctrl_pdd(x) WriteRegBits(ETH_PHYCTRL,0x2,1,x)
#define Rd_ETH_phyctrl_pdd(x) ReadRegBits(ETH_PHYCTRL,0x2,1)
#define ETH_PHYCTRL_PDD_MASK                                       0x00000002
#define ETH_PHYCTRL_PDD_ALIGN                                      0
#define ETH_PHYCTRL_PDD_BITS                                       1
#define ETH_PHYCTRL_PDD_SHIFT                                      1

/* ETH :: phyctrl :: pdp [00:00] */
#define Wr_ETH_phyctrl_pdp(x) WriteRegBits(ETH_PHYCTRL,0x1,0,x)
#define Rd_ETH_phyctrl_pdp(x) ReadRegBits(ETH_PHYCTRL,0x1,0)
#define ETH_PHYCTRL_PDP_MASK                                       0x00000001
#define ETH_PHYCTRL_PDP_ALIGN                                      0
#define ETH_PHYCTRL_PDP_BITS                                       1
#define ETH_PHYCTRL_PDP_SHIFT                                      0


/****************************************************************************
 * ETH :: rbuffctrl
 ***************************************************************************/
/* ETH :: rbuffctrl :: rbuffpad [31:31] */
#define Wr_ETH_rbuffctrl_rbuffpad(x) WriteRegBits(ETH_RBUFFCTRL,0x80000000,31,x)
#define Rd_ETH_rbuffctrl_rbuffpad(x) ReadRegBits(ETH_RBUFFCTRL,0x80000000,31)
#define ETH_RBUFFCTRL_RBUFFPAD_MASK                                0x80000000
#define ETH_RBUFFCTRL_RBUFFPAD_ALIGN                               0
#define ETH_RBUFFCTRL_RBUFFPAD_BITS                                1
#define ETH_RBUFFCTRL_RBUFFPAD_SHIFT                               31

/* ETH :: rbuffctrl :: reserved0 [30:16] */
#define ETH_RBUFFCTRL_RESERVED0_MASK                               0x7fff0000
#define ETH_RBUFFCTRL_RESERVED0_ALIGN                              0
#define ETH_RBUFFCTRL_RESERVED0_BITS                               15
#define ETH_RBUFFCTRL_RESERVED0_SHIFT                              16

/* ETH :: rbuffctrl :: rbuffsz [15:05] */
#define Wr_ETH_rbuffctrl_rbuffsz(x) WriteRegBits(ETH_RBUFFCTRL,0xffe0,5,x)
#define Rd_ETH_rbuffctrl_rbuffsz(x) ReadRegBits(ETH_RBUFFCTRL,0xffe0,5)
#define ETH_RBUFFCTRL_RBUFFSZ_MASK                                 0x0000ffe0
#define ETH_RBUFFCTRL_RBUFFSZ_ALIGN                                0
#define ETH_RBUFFCTRL_RBUFFSZ_BITS                                 11
#define ETH_RBUFFCTRL_RBUFFSZ_SHIFT                                5

/* ETH :: rbuffctrl :: reserved1 [04:00] */
#define ETH_RBUFFCTRL_RESERVED1_MASK                               0x0000001f
#define ETH_RBUFFCTRL_RESERVED1_ALIGN                              0
#define ETH_RBUFFCTRL_RESERVED1_BITS                               5
#define ETH_RBUFFCTRL_RESERVED1_SHIFT                              0


/****************************************************************************
 * ETH :: rbase
 ***************************************************************************/
/* ETH :: rbase :: rbase [31:05] */
#define Wr_ETH_rbase_rbase(x) WriteRegBits(ETH_RBASE,0xffffffe0,5,x)
#define Rd_ETH_rbase_rbase(x) ReadRegBits(ETH_RBASE,0xffffffe0,5)
#define ETH_RBASE_RBASE_MASK                                       0xffffffe0
#define ETH_RBASE_RBASE_ALIGN                                      0
#define ETH_RBASE_RBASE_BITS                                       27
#define ETH_RBASE_RBASE_SHIFT                                      5

/* ETH :: rbase :: reserved0 [04:00] */
#define ETH_RBASE_RESERVED0_MASK                                   0x0000001f
#define ETH_RBASE_RESERVED0_ALIGN                                  0
#define ETH_RBASE_RESERVED0_BITS                                   5
#define ETH_RBASE_RESERVED0_SHIFT                                  0


/****************************************************************************
 * ETH :: rbcfg
 ***************************************************************************/
/* ETH :: rbcfg :: rfbwmrk [31:16] */
#define Wr_ETH_rbcfg_rfbwmrk(x) WriteRegBits(ETH_RBCFG,0xffff0000,16,x)
#define Rd_ETH_rbcfg_rfbwmrk(x) ReadRegBits(ETH_RBCFG,0xffff0000,16)
#define ETH_RBCFG_RFBWMRK_MASK                                     0xffff0000
#define ETH_RBCFG_RFBWMRK_ALIGN                                    0
#define ETH_RBCFG_RFBWMRK_BITS                                     16
#define ETH_RBCFG_RFBWMRK_SHIFT                                    16

/* ETH :: rbcfg :: rlen [15:00] */
#define Wr_ETH_rbcfg_rlen(x) WriteRegBits(ETH_RBCFG,0xffff,0,x)
#define Rd_ETH_rbcfg_rlen(x) ReadRegBits(ETH_RBCFG,0xffff,0)
#define ETH_RBCFG_RLEN_MASK                                        0x0000ffff
#define ETH_RBCFG_RLEN_ALIGN                                       0
#define ETH_RBCFG_RLEN_BITS                                        16
#define ETH_RBCFG_RLEN_SHIFT                                       0


/****************************************************************************
 * ETH :: rbdptr
 ***************************************************************************/
/* ETH :: rbdptr :: rbdptr [31:03] */
#define Wr_ETH_rbdptr_rbdptr(x) WriteRegBits(ETH_RBDPTR,0xfffffff8,3,x)
#define Rd_ETH_rbdptr_rbdptr(x) ReadRegBits(ETH_RBDPTR,0xfffffff8,3)
#define ETH_RBDPTR_RBDPTR_MASK                                     0xfffffff8
#define ETH_RBDPTR_RBDPTR_ALIGN                                    0
#define ETH_RBDPTR_RBDPTR_BITS                                     29
#define ETH_RBDPTR_RBDPTR_SHIFT                                    3

/* ETH :: rbdptr :: reserved0 [02:00] */
#define ETH_RBDPTR_RESERVED0_MASK                                  0x00000007
#define ETH_RBDPTR_RESERVED0_ALIGN                                 0
#define ETH_RBDPTR_RESERVED0_BITS                                  3
#define ETH_RBDPTR_RESERVED0_SHIFT                                 0


/****************************************************************************
 * ETH :: rswptr
 ***************************************************************************/
/* ETH :: rswptr :: rswptr [31:03] */
#define Wr_ETH_rswptr_rswptr(x) WriteRegBits(ETH_RSWPTR,0xfffffff8,3,x)
#define Rd_ETH_rswptr_rswptr(x) ReadRegBits(ETH_RSWPTR,0xfffffff8,3)
#define ETH_RSWPTR_RSWPTR_MASK                                     0xfffffff8
#define ETH_RSWPTR_RSWPTR_ALIGN                                    0
#define ETH_RSWPTR_RSWPTR_BITS                                     29
#define ETH_RSWPTR_RSWPTR_SHIFT                                    3

/* ETH :: rswptr :: reserved0 [02:00] */
#define ETH_RSWPTR_RESERVED0_MASK                                  0x00000007
#define ETH_RSWPTR_RESERVED0_ALIGN                                 0
#define ETH_RSWPTR_RESERVED0_BITS                                  3
#define ETH_RSWPTR_RESERVED0_SHIFT                                 0


/****************************************************************************
 * ETH :: rbcfg_ext
 ***************************************************************************/
/* ETH :: rbcfg_ext :: rfbwmrk_bp_disable [31:16] */
#define Wr_ETH_rbcfg_ext_rfbwmrk_bp_disable(x) WriteRegBits(ETH_RBCFG_EXT,0xffff0000,16,x)
#define Rd_ETH_rbcfg_ext_rfbwmrk_bp_disable(x) ReadRegBits(ETH_RBCFG_EXT,0xffff0000,16)
#define ETH_RBCFG_EXT_RFBWMRK_BP_DISABLE_MASK                      0xffff0000
#define ETH_RBCFG_EXT_RFBWMRK_BP_DISABLE_ALIGN                     0
#define ETH_RBCFG_EXT_RFBWMRK_BP_DISABLE_BITS                      16
#define ETH_RBCFG_EXT_RFBWMRK_BP_DISABLE_SHIFT                     16

/* ETH :: rbcfg_ext :: reserved0 [15:01] */
#define ETH_RBCFG_EXT_RESERVED0_MASK                               0x0000fffe
#define ETH_RBCFG_EXT_RESERVED0_ALIGN                              0
#define ETH_RBCFG_EXT_RESERVED0_BITS                               15
#define ETH_RBCFG_EXT_RESERVED0_SHIFT                              1

/* ETH :: rbcfg_ext :: rfbwmrk_bp_disable_vld [00:00] */
#define Wr_ETH_rbcfg_ext_rfbwmrk_bp_disable_vld(x) WriteRegBits(ETH_RBCFG_EXT,0x1,0,x)
#define Rd_ETH_rbcfg_ext_rfbwmrk_bp_disable_vld(x) ReadRegBits(ETH_RBCFG_EXT,0x1,0)
#define ETH_RBCFG_EXT_RFBWMRK_BP_DISABLE_VLD_MASK                  0x00000001
#define ETH_RBCFG_EXT_RFBWMRK_BP_DISABLE_VLD_ALIGN                 0
#define ETH_RBCFG_EXT_RFBWMRK_BP_DISABLE_VLD_BITS                  1
#define ETH_RBCFG_EXT_RFBWMRK_BP_DISABLE_VLD_SHIFT                 0


/****************************************************************************
 * ETH :: tbase
 ***************************************************************************/
/* ETH :: tbase :: tbase [31:05] */
#define Wr_ETH_tbase_tbase(x) WriteRegBits(ETH_TBASE,0xffffffe0,5,x)
#define Rd_ETH_tbase_tbase(x) ReadRegBits(ETH_TBASE,0xffffffe0,5)
#define ETH_TBASE_TBASE_MASK                                       0xffffffe0
#define ETH_TBASE_TBASE_ALIGN                                      0
#define ETH_TBASE_TBASE_BITS                                       27
#define ETH_TBASE_TBASE_SHIFT                                      5

/* ETH :: tbase :: reserved0 [04:00] */
#define ETH_TBASE_RESERVED0_MASK                                   0x0000001f
#define ETH_TBASE_RESERVED0_ALIGN                                  0
#define ETH_TBASE_RESERVED0_BITS                                   5
#define ETH_TBASE_RESERVED0_SHIFT                                  0


/****************************************************************************
 * ETH :: tbcfg
 ***************************************************************************/
/* ETH :: tbcfg :: trbwmrk [31:16] */
#define Wr_ETH_tbcfg_trbwmrk(x) WriteRegBits(ETH_TBCFG,0xffff0000,16,x)
#define Rd_ETH_tbcfg_trbwmrk(x) ReadRegBits(ETH_TBCFG,0xffff0000,16)
#define ETH_TBCFG_TRBWMRK_MASK                                     0xffff0000
#define ETH_TBCFG_TRBWMRK_ALIGN                                    0
#define ETH_TBCFG_TRBWMRK_BITS                                     16
#define ETH_TBCFG_TRBWMRK_SHIFT                                    16

/* ETH :: tbcfg :: tlen [15:00] */
#define Wr_ETH_tbcfg_tlen(x) WriteRegBits(ETH_TBCFG,0xffff,0,x)
#define Rd_ETH_tbcfg_tlen(x) ReadRegBits(ETH_TBCFG,0xffff,0)
#define ETH_TBCFG_TLEN_MASK                                        0x0000ffff
#define ETH_TBCFG_TLEN_ALIGN                                       0
#define ETH_TBCFG_TLEN_BITS                                        16
#define ETH_TBCFG_TLEN_SHIFT                                       0


/****************************************************************************
 * ETH :: tbdptr
 ***************************************************************************/
/* ETH :: tbdptr :: tbdptr [31:03] */
#define Wr_ETH_tbdptr_tbdptr(x) WriteRegBits(ETH_TBDPTR,0xfffffff8,3,x)
#define Rd_ETH_tbdptr_tbdptr(x) ReadRegBits(ETH_TBDPTR,0xfffffff8,3)
#define ETH_TBDPTR_TBDPTR_MASK                                     0xfffffff8
#define ETH_TBDPTR_TBDPTR_ALIGN                                    0
#define ETH_TBDPTR_TBDPTR_BITS                                     29
#define ETH_TBDPTR_TBDPTR_SHIFT                                    3

/* ETH :: tbdptr :: reserved0 [02:00] */
#define ETH_TBDPTR_RESERVED0_MASK                                  0x00000007
#define ETH_TBDPTR_RESERVED0_ALIGN                                 0
#define ETH_TBDPTR_RESERVED0_BITS                                  3
#define ETH_TBDPTR_RESERVED0_SHIFT                                 0


/****************************************************************************
 * ETH :: tswptr
 ***************************************************************************/
/* ETH :: tswptr :: tswptr [31:03] */
#define Wr_ETH_tswptr_tswptr(x) WriteRegBits(ETH_TSWPTR,0xfffffff8,3,x)
#define Rd_ETH_tswptr_tswptr(x) ReadRegBits(ETH_TSWPTR,0xfffffff8,3)
#define ETH_TSWPTR_TSWPTR_MASK                                     0xfffffff8
#define ETH_TSWPTR_TSWPTR_ALIGN                                    0
#define ETH_TSWPTR_TSWPTR_BITS                                     29
#define ETH_TSWPTR_TSWPTR_SHIFT                                    3

/* ETH :: tswptr :: reserved0 [02:00] */
#define ETH_TSWPTR_RESERVED0_MASK                                  0x00000007
#define ETH_TSWPTR_RESERVED0_ALIGN                                 0
#define ETH_TSWPTR_RESERVED0_BITS                                  3
#define ETH_TSWPTR_RESERVED0_SHIFT                                 0


/****************************************************************************
 * ETH :: macbp
 ***************************************************************************/
/* ETH :: macbp :: reserved0 [31:07] */
#define ETH_MACBP_RESERVED0_MASK                                   0xffffff80
#define ETH_MACBP_RESERVED0_ALIGN                                  0
#define ETH_MACBP_RESERVED0_BITS                                   25
#define ETH_MACBP_RESERVED0_SHIFT                                  7

/* ETH :: macbp :: ipg_cfg [06:02] */
#define Wr_ETH_macbp_ipg_cfg(x) WriteRegBits(ETH_MACBP,0x7c,2,x)
#define Rd_ETH_macbp_ipg_cfg(x) ReadRegBits(ETH_MACBP,0x7c,2)
#define ETH_MACBP_IPG_CFG_MASK                                     0x0000007c
#define ETH_MACBP_IPG_CFG_ALIGN                                    0
#define ETH_MACBP_IPG_CFG_BITS                                     5
#define ETH_MACBP_IPG_CFG_SHIFT                                    2

/* ETH :: macbp :: bken [01:01] */
#define Wr_ETH_macbp_bken(x) WriteRegBits(ETH_MACBP,0x2,1,x)
#define Rd_ETH_macbp_bken(x) ReadRegBits(ETH_MACBP,0x2,1)
#define ETH_MACBP_BKEN_MASK                                        0x00000002
#define ETH_MACBP_BKEN_ALIGN                                       0
#define ETH_MACBP_BKEN_BITS                                        1
#define ETH_MACBP_BKEN_SHIFT                                       1

/* ETH :: macbp :: fcen [00:00] */
#define Wr_ETH_macbp_fcen(x) WriteRegBits(ETH_MACBP,0x1,0,x)
#define Rd_ETH_macbp_fcen(x) ReadRegBits(ETH_MACBP,0x1,0)
#define ETH_MACBP_FCEN_MASK                                        0x00000001
#define ETH_MACBP_FCEN_ALIGN                                       0
#define ETH_MACBP_FCEN_BITS                                        1
#define ETH_MACBP_FCEN_SHIFT                                       0


/****************************************************************************
 * ETH :: maccfg
 ***************************************************************************/
/* ETH :: maccfg :: reserved0 [31:31] */
#define ETH_MACCFG_RESERVED0_MASK                                  0x80000000
#define ETH_MACCFG_RESERVED0_ALIGN                                 0
#define ETH_MACCFG_RESERVED0_BITS                                  1
#define ETH_MACCFG_RESERVED0_SHIFT                                 31

/* ETH :: maccfg :: ipg_cfgrsf [30:30] */
#define Wr_ETH_maccfg_ipg_cfgrsf(x) WriteRegBits(ETH_MACCFG,0x40000000,30,x)
#define Rd_ETH_maccfg_ipg_cfgrsf(x) ReadRegBits(ETH_MACCFG,0x40000000,30)
#define ETH_MACCFG_IPG_CFGRSF_MASK                                 0x40000000
#define ETH_MACCFG_IPG_CFGRSF_ALIGN                                0
#define ETH_MACCFG_IPG_CFGRSF_BITS                                 1
#define ETH_MACCFG_IPG_CFGRSF_SHIFT                                30

/* ETH :: maccfg :: txrx [29:29] */
#define Wr_ETH_maccfg_txrx(x) WriteRegBits(ETH_MACCFG,0x20000000,29,x)
#define Rd_ETH_maccfg_txrx(x) ReadRegBits(ETH_MACCFG,0x20000000,29)
#define ETH_MACCFG_TXRX_MASK                                       0x20000000
#define ETH_MACCFG_TXRX_ALIGN                                      0
#define ETH_MACCFG_TXRX_BITS                                       1
#define ETH_MACCFG_TXRX_SHIFT                                      29

/* ETH :: maccfg :: tpd [28:28] */
#define Wr_ETH_maccfg_tpd(x) WriteRegBits(ETH_MACCFG,0x10000000,28,x)
#define Rd_ETH_maccfg_tpd(x) ReadRegBits(ETH_MACCFG,0x10000000,28)
#define ETH_MACCFG_TPD_MASK                                        0x10000000
#define ETH_MACCFG_TPD_ALIGN                                       0
#define ETH_MACCFG_TPD_BITS                                        1
#define ETH_MACCFG_TPD_SHIFT                                       28

/* ETH :: maccfg :: reserved1 [27:26] */
#define ETH_MACCFG_RESERVED1_MASK                                  0x0c000000
#define ETH_MACCFG_RESERVED1_ALIGN                                 0
#define ETH_MACCFG_RESERVED1_BITS                                  2
#define ETH_MACCFG_RESERVED1_SHIFT                                 26

/* ETH :: maccfg :: rlb [25:25] */
#define Wr_ETH_maccfg_rlb(x) WriteRegBits(ETH_MACCFG,0x2000000,25,x)
#define Rd_ETH_maccfg_rlb(x) ReadRegBits(ETH_MACCFG,0x2000000,25)
#define ETH_MACCFG_RLB_MASK                                        0x02000000
#define ETH_MACCFG_RLB_ALIGN                                       0
#define ETH_MACCFG_RLB_BITS                                        1
#define ETH_MACCFG_RLB_SHIFT                                       25

/* ETH :: maccfg :: nolc [24:24] */
#define Wr_ETH_maccfg_nolc(x) WriteRegBits(ETH_MACCFG,0x1000000,24,x)
#define Rd_ETH_maccfg_nolc(x) ReadRegBits(ETH_MACCFG,0x1000000,24)
#define ETH_MACCFG_NOLC_MASK                                       0x01000000
#define ETH_MACCFG_NOLC_ALIGN                                      0
#define ETH_MACCFG_NOLC_BITS                                       1
#define ETH_MACCFG_NOLC_SHIFT                                      24

/* ETH :: maccfg :: cfa [23:23] */
#define Wr_ETH_maccfg_cfa(x) WriteRegBits(ETH_MACCFG,0x800000,23,x)
#define Rd_ETH_maccfg_cfa(x) ReadRegBits(ETH_MACCFG,0x800000,23)
#define ETH_MACCFG_CFA_MASK                                        0x00800000
#define ETH_MACCFG_CFA_ALIGN                                       0
#define ETH_MACCFG_CFA_BITS                                        1
#define ETH_MACCFG_CFA_SHIFT                                       23

/* ETH :: maccfg :: acfg [22:22] */
#define Wr_ETH_maccfg_acfg(x) WriteRegBits(ETH_MACCFG,0x400000,22,x)
#define Rd_ETH_maccfg_acfg(x) ReadRegBits(ETH_MACCFG,0x400000,22)
#define ETH_MACCFG_ACFG_MASK                                       0x00400000
#define ETH_MACCFG_ACFG_ALIGN                                      0
#define ETH_MACCFG_ACFG_BITS                                       1
#define ETH_MACCFG_ACFG_SHIFT                                      22

/* ETH :: maccfg :: reserved2 [21:16] */
#define ETH_MACCFG_RESERVED2_MASK                                  0x003f0000
#define ETH_MACCFG_RESERVED2_ALIGN                                 0
#define ETH_MACCFG_RESERVED2_BITS                                  6
#define ETH_MACCFG_RESERVED2_SHIFT                                 16

/* ETH :: maccfg :: llb [15:15] */
#define Wr_ETH_maccfg_llb(x) WriteRegBits(ETH_MACCFG,0x8000,15,x)
#define Rd_ETH_maccfg_llb(x) ReadRegBits(ETH_MACCFG,0x8000,15)
#define ETH_MACCFG_LLB_MASK                                        0x00008000
#define ETH_MACCFG_LLB_ALIGN                                       0
#define ETH_MACCFG_LLB_BITS                                        1
#define ETH_MACCFG_LLB_SHIFT                                       15

/* ETH :: maccfg :: crpt [14:14] */
#define Wr_ETH_maccfg_crpt(x) WriteRegBits(ETH_MACCFG,0x4000,14,x)
#define Rd_ETH_maccfg_crpt(x) ReadRegBits(ETH_MACCFG,0x4000,14)
#define ETH_MACCFG_CRPT_MASK                                       0x00004000
#define ETH_MACCFG_CRPT_ALIGN                                      0
#define ETH_MACCFG_CRPT_BITS                                       1
#define ETH_MACCFG_CRPT_SHIFT                                      14

/* ETH :: maccfg :: srst [13:13] */
#define Wr_ETH_maccfg_srst(x) WriteRegBits(ETH_MACCFG,0x2000,13,x)
#define Rd_ETH_maccfg_srst(x) ReadRegBits(ETH_MACCFG,0x2000,13)
#define ETH_MACCFG_SRST_MASK                                       0x00002000
#define ETH_MACCFG_SRST_ALIGN                                      0
#define ETH_MACCFG_SRST_BITS                                       1
#define ETH_MACCFG_SRST_SHIFT                                      13

/* ETH :: maccfg :: ofen [12:12] */
#define Wr_ETH_maccfg_ofen(x) WriteRegBits(ETH_MACCFG,0x1000,12,x)
#define Rd_ETH_maccfg_ofen(x) ReadRegBits(ETH_MACCFG,0x1000,12)
#define ETH_MACCFG_OFEN_MASK                                       0x00001000
#define ETH_MACCFG_OFEN_ALIGN                                      0
#define ETH_MACCFG_OFEN_BITS                                       1
#define ETH_MACCFG_OFEN_SHIFT                                      12

/* ETH :: maccfg :: reserved3 [11:11] */
#define ETH_MACCFG_RESERVED3_MASK                                  0x00000800
#define ETH_MACCFG_RESERVED3_ALIGN                                 0
#define ETH_MACCFG_RESERVED3_BITS                                  1
#define ETH_MACCFG_RESERVED3_SHIFT                                 11

/* ETH :: maccfg :: hden [10:10] */
#define Wr_ETH_maccfg_hden(x) WriteRegBits(ETH_MACCFG,0x400,10,x)
#define Rd_ETH_maccfg_hden(x) ReadRegBits(ETH_MACCFG,0x400,10)
#define ETH_MACCFG_HDEN_MASK                                       0x00000400
#define ETH_MACCFG_HDEN_ALIGN                                      0
#define ETH_MACCFG_HDEN_BITS                                       1
#define ETH_MACCFG_HDEN_SHIFT                                      10

/* ETH :: maccfg :: txad [09:09] */
#define Wr_ETH_maccfg_txad(x) WriteRegBits(ETH_MACCFG,0x200,9,x)
#define Rd_ETH_maccfg_txad(x) ReadRegBits(ETH_MACCFG,0x200,9)
#define ETH_MACCFG_TXAD_MASK                                       0x00000200
#define ETH_MACCFG_TXAD_ALIGN                                      0
#define ETH_MACCFG_TXAD_BITS                                       1
#define ETH_MACCFG_TXAD_SHIFT                                      9

/* ETH :: maccfg :: pdis [08:08] */
#define Wr_ETH_maccfg_pdis(x) WriteRegBits(ETH_MACCFG,0x100,8,x)
#define Rd_ETH_maccfg_pdis(x) ReadRegBits(ETH_MACCFG,0x100,8)
#define ETH_MACCFG_PDIS_MASK                                       0x00000100
#define ETH_MACCFG_PDIS_ALIGN                                      0
#define ETH_MACCFG_PDIS_BITS                                       1
#define ETH_MACCFG_PDIS_SHIFT                                      8

/* ETH :: maccfg :: pfwd [07:07] */
#define Wr_ETH_maccfg_pfwd(x) WriteRegBits(ETH_MACCFG,0x80,7,x)
#define Rd_ETH_maccfg_pfwd(x) ReadRegBits(ETH_MACCFG,0x80,7)
#define ETH_MACCFG_PFWD_MASK                                       0x00000080
#define ETH_MACCFG_PFWD_ALIGN                                      0
#define ETH_MACCFG_PFWD_BITS                                       1
#define ETH_MACCFG_PFWD_SHIFT                                      7

/* ETH :: maccfg :: cfwd [06:06] */
#define Wr_ETH_maccfg_cfwd(x) WriteRegBits(ETH_MACCFG,0x40,6,x)
#define Rd_ETH_maccfg_cfwd(x) ReadRegBits(ETH_MACCFG,0x40,6)
#define ETH_MACCFG_CFWD_MASK                                       0x00000040
#define ETH_MACCFG_CFWD_ALIGN                                      0
#define ETH_MACCFG_CFWD_BITS                                       1
#define ETH_MACCFG_CFWD_SHIFT                                      6

/* ETH :: maccfg :: rxpad [05:05] */
#define Wr_ETH_maccfg_rxpad(x) WriteRegBits(ETH_MACCFG,0x20,5,x)
#define Rd_ETH_maccfg_rxpad(x) ReadRegBits(ETH_MACCFG,0x20,5)
#define ETH_MACCFG_RXPAD_MASK                                      0x00000020
#define ETH_MACCFG_RXPAD_ALIGN                                     0
#define ETH_MACCFG_RXPAD_BITS                                      1
#define ETH_MACCFG_RXPAD_SHIFT                                     5

/* ETH :: maccfg :: prom [04:04] */
#define Wr_ETH_maccfg_prom(x) WriteRegBits(ETH_MACCFG,0x10,4,x)
#define Rd_ETH_maccfg_prom(x) ReadRegBits(ETH_MACCFG,0x10,4)
#define ETH_MACCFG_PROM_MASK                                       0x00000010
#define ETH_MACCFG_PROM_ALIGN                                      0
#define ETH_MACCFG_PROM_BITS                                       1
#define ETH_MACCFG_PROM_SHIFT                                      4

/* ETH :: maccfg :: espd [03:02] */
#define Wr_ETH_maccfg_espd(x) WriteRegBits(ETH_MACCFG,0xc,2,x)
#define Rd_ETH_maccfg_espd(x) ReadRegBits(ETH_MACCFG,0xc,2)
#define ETH_MACCFG_ESPD_MASK                                       0x0000000c
#define ETH_MACCFG_ESPD_ALIGN                                      0
#define ETH_MACCFG_ESPD_BITS                                       2
#define ETH_MACCFG_ESPD_SHIFT                                      2

/* ETH :: maccfg :: rxen [01:01] */
#define Wr_ETH_maccfg_rxen(x) WriteRegBits(ETH_MACCFG,0x2,1,x)
#define Rd_ETH_maccfg_rxen(x) ReadRegBits(ETH_MACCFG,0x2,1)
#define ETH_MACCFG_RXEN_MASK                                       0x00000002
#define ETH_MACCFG_RXEN_ALIGN                                      0
#define ETH_MACCFG_RXEN_BITS                                       1
#define ETH_MACCFG_RXEN_SHIFT                                      1

/* ETH :: maccfg :: txen [00:00] */
#define Wr_ETH_maccfg_txen(x) WriteRegBits(ETH_MACCFG,0x1,0,x)
#define Rd_ETH_maccfg_txen(x) ReadRegBits(ETH_MACCFG,0x1,0)
#define ETH_MACCFG_TXEN_MASK                                       0x00000001
#define ETH_MACCFG_TXEN_ALIGN                                      0
#define ETH_MACCFG_TXEN_BITS                                       1
#define ETH_MACCFG_TXEN_SHIFT                                      0


/****************************************************************************
 * ETH :: macaddr0
 ***************************************************************************/
/* ETH :: macaddr0 :: sabyte0 [31:24] */
#define Wr_ETH_macaddr0_sabyte0(x) WriteRegBits(ETH_MACADDR0,0xff000000,24,x)
#define Rd_ETH_macaddr0_sabyte0(x) ReadRegBits(ETH_MACADDR0,0xff000000,24)
#define ETH_MACADDR0_SABYTE0_MASK                                  0xff000000
#define ETH_MACADDR0_SABYTE0_ALIGN                                 0
#define ETH_MACADDR0_SABYTE0_BITS                                  8
#define ETH_MACADDR0_SABYTE0_SHIFT                                 24

/* ETH :: macaddr0 :: sabyte1 [23:16] */
#define Wr_ETH_macaddr0_sabyte1(x) WriteRegBits(ETH_MACADDR0,0xff0000,16,x)
#define Rd_ETH_macaddr0_sabyte1(x) ReadRegBits(ETH_MACADDR0,0xff0000,16)
#define ETH_MACADDR0_SABYTE1_MASK                                  0x00ff0000
#define ETH_MACADDR0_SABYTE1_ALIGN                                 0
#define ETH_MACADDR0_SABYTE1_BITS                                  8
#define ETH_MACADDR0_SABYTE1_SHIFT                                 16

/* ETH :: macaddr0 :: sabyte2 [15:08] */
#define Wr_ETH_macaddr0_sabyte2(x) WriteRegBits(ETH_MACADDR0,0xff00,8,x)
#define Rd_ETH_macaddr0_sabyte2(x) ReadRegBits(ETH_MACADDR0,0xff00,8)
#define ETH_MACADDR0_SABYTE2_MASK                                  0x0000ff00
#define ETH_MACADDR0_SABYTE2_ALIGN                                 0
#define ETH_MACADDR0_SABYTE2_BITS                                  8
#define ETH_MACADDR0_SABYTE2_SHIFT                                 8

/* ETH :: macaddr0 :: sabyte3 [07:00] */
#define Wr_ETH_macaddr0_sabyte3(x) WriteRegBits(ETH_MACADDR0,0xff,0,x)
#define Rd_ETH_macaddr0_sabyte3(x) ReadRegBits(ETH_MACADDR0,0xff,0)
#define ETH_MACADDR0_SABYTE3_MASK                                  0x000000ff
#define ETH_MACADDR0_SABYTE3_ALIGN                                 0
#define ETH_MACADDR0_SABYTE3_BITS                                  8
#define ETH_MACADDR0_SABYTE3_SHIFT                                 0


/****************************************************************************
 * ETH :: macaddr1
 ***************************************************************************/
/* ETH :: macaddr1 :: reserved0 [31:16] */
#define ETH_MACADDR1_RESERVED0_MASK                                0xffff0000
#define ETH_MACADDR1_RESERVED0_ALIGN                               0
#define ETH_MACADDR1_RESERVED0_BITS                                16
#define ETH_MACADDR1_RESERVED0_SHIFT                               16

/* ETH :: macaddr1 :: sabyte4 [15:08] */
#define Wr_ETH_macaddr1_sabyte4(x) WriteRegBits(ETH_MACADDR1,0xff00,8,x)
#define Rd_ETH_macaddr1_sabyte4(x) ReadRegBits(ETH_MACADDR1,0xff00,8)
#define ETH_MACADDR1_SABYTE4_MASK                                  0x0000ff00
#define ETH_MACADDR1_SABYTE4_ALIGN                                 0
#define ETH_MACADDR1_SABYTE4_BITS                                  8
#define ETH_MACADDR1_SABYTE4_SHIFT                                 8

/* ETH :: macaddr1 :: sabyte5 [07:00] */
#define Wr_ETH_macaddr1_sabyte5(x) WriteRegBits(ETH_MACADDR1,0xff,0,x)
#define Rd_ETH_macaddr1_sabyte5(x) ReadRegBits(ETH_MACADDR1,0xff,0)
#define ETH_MACADDR1_SABYTE5_MASK                                  0x000000ff
#define ETH_MACADDR1_SABYTE5_ALIGN                                 0
#define ETH_MACADDR1_SABYTE5_BITS                                  8
#define ETH_MACADDR1_SABYTE5_SHIFT                                 0


/****************************************************************************
 * ETH :: maxfrm
 ***************************************************************************/
/* ETH :: maxfrm :: reserved0 [31:14] */
#define ETH_MAXFRM_RESERVED0_MASK                                  0xffffc000
#define ETH_MAXFRM_RESERVED0_ALIGN                                 0
#define ETH_MAXFRM_RESERVED0_BITS                                  18
#define ETH_MAXFRM_RESERVED0_SHIFT                                 14

/* ETH :: maxfrm :: maxfrm [13:00] */
#define Wr_ETH_maxfrm_maxfrm(x) WriteRegBits(ETH_MAXFRM,0x3fff,0,x)
#define Rd_ETH_maxfrm_maxfrm(x) ReadRegBits(ETH_MAXFRM,0x3fff,0)
#define ETH_MAXFRM_MAXFRM_MASK                                     0x00003fff
#define ETH_MAXFRM_MAXFRM_ALIGN                                    0
#define ETH_MAXFRM_MAXFRM_BITS                                     14
#define ETH_MAXFRM_MAXFRM_SHIFT                                    0


/****************************************************************************
 * ETH :: macpq
 ***************************************************************************/
/* ETH :: macpq :: reserved0 [31:16] */
#define ETH_MACPQ_RESERVED0_MASK                                   0xffff0000
#define ETH_MACPQ_RESERVED0_ALIGN                                  0
#define ETH_MACPQ_RESERVED0_BITS                                   16
#define ETH_MACPQ_RESERVED0_SHIFT                                  16

/* ETH :: macpq :: macpq [15:00] */
#define Wr_ETH_macpq_macpq(x) WriteRegBits(ETH_MACPQ,0xffff,0,x)
#define Rd_ETH_macpq_macpq(x) ReadRegBits(ETH_MACPQ,0xffff,0)
#define ETH_MACPQ_MACPQ_MASK                                       0x0000ffff
#define ETH_MACPQ_MACPQ_ALIGN                                      0
#define ETH_MACPQ_MACPQ_BITS                                       16
#define ETH_MACPQ_MACPQ_SHIFT                                      0


/****************************************************************************
 * ETH :: rxfifo_empty
 ***************************************************************************/
/* ETH :: rxfifo_empty :: reserved0 [31:04] */
#define ETH_RXFIFO_EMPTY_RESERVED0_MASK                            0xfffffff0
#define ETH_RXFIFO_EMPTY_RESERVED0_ALIGN                           0
#define ETH_RXFIFO_EMPTY_RESERVED0_BITS                            28
#define ETH_RXFIFO_EMPTY_RESERVED0_SHIFT                           4

/* ETH :: rxfifo_empty :: rxfe [03:00] */
#define Wr_ETH_rxfifo_empty_rxfe(x) WriteRegBits(ETH_RXFIFO_EMPTY,0xf,0,x)
#define Rd_ETH_rxfifo_empty_rxfe(x) ReadRegBits(ETH_RXFIFO_EMPTY,0xf,0)
#define ETH_RXFIFO_EMPTY_RXFE_MASK                                 0x0000000f
#define ETH_RXFIFO_EMPTY_RXFE_ALIGN                                0
#define ETH_RXFIFO_EMPTY_RXFE_BITS                                 4
#define ETH_RXFIFO_EMPTY_RXFE_SHIFT                                0


/****************************************************************************
 * ETH :: rxfifo_full
 ***************************************************************************/
/* ETH :: rxfifo_full :: reserved0 [31:04] */
#define ETH_RXFIFO_FULL_RESERVED0_MASK                             0xfffffff0
#define ETH_RXFIFO_FULL_RESERVED0_ALIGN                            0
#define ETH_RXFIFO_FULL_RESERVED0_BITS                             28
#define ETH_RXFIFO_FULL_RESERVED0_SHIFT                            4

/* ETH :: rxfifo_full :: rxff [03:00] */
#define Wr_ETH_rxfifo_full_rxff(x) WriteRegBits(ETH_RXFIFO_FULL,0xf,0,x)
#define Rd_ETH_rxfifo_full_rxff(x) ReadRegBits(ETH_RXFIFO_FULL,0xf,0)
#define ETH_RXFIFO_FULL_RXFF_MASK                                  0x0000000f
#define ETH_RXFIFO_FULL_RXFF_ALIGN                                 0
#define ETH_RXFIFO_FULL_RXFF_BITS                                  4
#define ETH_RXFIFO_FULL_RXFF_SHIFT                                 0


/****************************************************************************
 * ETH :: txfifo_empty
 ***************************************************************************/
/* ETH :: txfifo_empty :: reserved0 [31:04] */
#define ETH_TXFIFO_EMPTY_RESERVED0_MASK                            0xfffffff0
#define ETH_TXFIFO_EMPTY_RESERVED0_ALIGN                           0
#define ETH_TXFIFO_EMPTY_RESERVED0_BITS                            28
#define ETH_TXFIFO_EMPTY_RESERVED0_SHIFT                           4

/* ETH :: txfifo_empty :: txfe [03:00] */
#define Wr_ETH_txfifo_empty_txfe(x) WriteRegBits(ETH_TXFIFO_EMPTY,0xf,0,x)
#define Rd_ETH_txfifo_empty_txfe(x) ReadRegBits(ETH_TXFIFO_EMPTY,0xf,0)
#define ETH_TXFIFO_EMPTY_TXFE_MASK                                 0x0000000f
#define ETH_TXFIFO_EMPTY_TXFE_ALIGN                                0
#define ETH_TXFIFO_EMPTY_TXFE_BITS                                 4
#define ETH_TXFIFO_EMPTY_TXFE_SHIFT                                0


/****************************************************************************
 * ETH :: txfifo_full
 ***************************************************************************/
/* ETH :: txfifo_full :: reserved0 [31:04] */
#define ETH_TXFIFO_FULL_RESERVED0_MASK                             0xfffffff0
#define ETH_TXFIFO_FULL_RESERVED0_ALIGN                            0
#define ETH_TXFIFO_FULL_RESERVED0_BITS                             28
#define ETH_TXFIFO_FULL_RESERVED0_SHIFT                            4

/* ETH :: txfifo_full :: txff [03:00] */
#define Wr_ETH_txfifo_full_txff(x) WriteRegBits(ETH_TXFIFO_FULL,0xf,0,x)
#define Rd_ETH_txfifo_full_txff(x) ReadRegBits(ETH_TXFIFO_FULL,0xf,0)
#define ETH_TXFIFO_FULL_TXFF_MASK                                  0x0000000f
#define ETH_TXFIFO_FULL_TXFF_ALIGN                                 0
#define ETH_TXFIFO_FULL_TXFF_BITS                                  4
#define ETH_TXFIFO_FULL_TXFF_SHIFT                                 0


/****************************************************************************
 * ETH :: rxfifo_aempty
 ***************************************************************************/
/* ETH :: rxfifo_aempty :: reserved0 [31:04] */
#define ETH_RXFIFO_AEMPTY_RESERVED0_MASK                           0xfffffff0
#define ETH_RXFIFO_AEMPTY_RESERVED0_ALIGN                          0
#define ETH_RXFIFO_AEMPTY_RESERVED0_BITS                           28
#define ETH_RXFIFO_AEMPTY_RESERVED0_SHIFT                          4

/* ETH :: rxfifo_aempty :: rxfae [03:00] */
#define Wr_ETH_rxfifo_aempty_rxfae(x) WriteRegBits(ETH_RXFIFO_AEMPTY,0xf,0,x)
#define Rd_ETH_rxfifo_aempty_rxfae(x) ReadRegBits(ETH_RXFIFO_AEMPTY,0xf,0)
#define ETH_RXFIFO_AEMPTY_RXFAE_MASK                               0x0000000f
#define ETH_RXFIFO_AEMPTY_RXFAE_ALIGN                              0
#define ETH_RXFIFO_AEMPTY_RXFAE_BITS                               4
#define ETH_RXFIFO_AEMPTY_RXFAE_SHIFT                              0


/****************************************************************************
 * ETH :: rxfifo_afull
 ***************************************************************************/
/* ETH :: rxfifo_afull :: reserved0 [31:04] */
#define ETH_RXFIFO_AFULL_RESERVED0_MASK                            0xfffffff0
#define ETH_RXFIFO_AFULL_RESERVED0_ALIGN                           0
#define ETH_RXFIFO_AFULL_RESERVED0_BITS                            28
#define ETH_RXFIFO_AFULL_RESERVED0_SHIFT                           4

/* ETH :: rxfifo_afull :: rxfaf [03:00] */
#define Wr_ETH_rxfifo_afull_rxfaf(x) WriteRegBits(ETH_RXFIFO_AFULL,0xf,0,x)
#define Rd_ETH_rxfifo_afull_rxfaf(x) ReadRegBits(ETH_RXFIFO_AFULL,0xf,0)
#define ETH_RXFIFO_AFULL_RXFAF_MASK                                0x0000000f
#define ETH_RXFIFO_AFULL_RXFAF_ALIGN                               0
#define ETH_RXFIFO_AFULL_RXFAF_BITS                                4
#define ETH_RXFIFO_AFULL_RXFAF_SHIFT                               0


/****************************************************************************
 * ETH :: txfifo_aempty
 ***************************************************************************/
/* ETH :: txfifo_aempty :: reserved0 [31:04] */
#define ETH_TXFIFO_AEMPTY_RESERVED0_MASK                           0xfffffff0
#define ETH_TXFIFO_AEMPTY_RESERVED0_ALIGN                          0
#define ETH_TXFIFO_AEMPTY_RESERVED0_BITS                           28
#define ETH_TXFIFO_AEMPTY_RESERVED0_SHIFT                          4

/* ETH :: txfifo_aempty :: txfae [03:00] */
#define Wr_ETH_txfifo_aempty_txfae(x) WriteRegBits(ETH_TXFIFO_AEMPTY,0xf,0,x)
#define Rd_ETH_txfifo_aempty_txfae(x) ReadRegBits(ETH_TXFIFO_AEMPTY,0xf,0)
#define ETH_TXFIFO_AEMPTY_TXFAE_MASK                               0x0000000f
#define ETH_TXFIFO_AEMPTY_TXFAE_ALIGN                              0
#define ETH_TXFIFO_AEMPTY_TXFAE_BITS                               4
#define ETH_TXFIFO_AEMPTY_TXFAE_SHIFT                              0


/****************************************************************************
 * ETH :: txfifo_afull
 ***************************************************************************/
/* ETH :: txfifo_afull :: reserved0 [31:04] */
#define ETH_TXFIFO_AFULL_RESERVED0_MASK                            0xfffffff0
#define ETH_TXFIFO_AFULL_RESERVED0_ALIGN                           0
#define ETH_TXFIFO_AFULL_RESERVED0_BITS                            28
#define ETH_TXFIFO_AFULL_RESERVED0_SHIFT                           4

/* ETH :: txfifo_afull :: txfaf [03:00] */
#define Wr_ETH_txfifo_afull_txfaf(x) WriteRegBits(ETH_TXFIFO_AFULL,0xf,0,x)
#define Rd_ETH_txfifo_afull_txfaf(x) ReadRegBits(ETH_TXFIFO_AFULL,0xf,0)
#define ETH_TXFIFO_AFULL_TXFAF_MASK                                0x0000000f
#define ETH_TXFIFO_AFULL_TXFAF_ALIGN                               0
#define ETH_TXFIFO_AFULL_TXFAF_BITS                                4
#define ETH_TXFIFO_AFULL_TXFAF_SHIFT                               0


/****************************************************************************
 * ETH :: macmode
 ***************************************************************************/
/* ETH :: macmode :: reserved0 [31:06] */
#define ETH_MACMODE_RESERVED0_MASK                                 0xffffffc0
#define ETH_MACMODE_RESERVED0_ALIGN                                0
#define ETH_MACMODE_RESERVED0_BITS                                 26
#define ETH_MACMODE_RESERVED0_SHIFT                                6

/* ETH :: macmode :: lnk [05:05] */
#define Wr_ETH_macmode_lnk(x) WriteRegBits(ETH_MACMODE,0x20,5,x)
#define Rd_ETH_macmode_lnk(x) ReadRegBits(ETH_MACMODE,0x20,5)
#define ETH_MACMODE_LNK_MASK                                       0x00000020
#define ETH_MACMODE_LNK_ALIGN                                      0
#define ETH_MACMODE_LNK_BITS                                       1
#define ETH_MACMODE_LNK_SHIFT                                      5

/* ETH :: macmode :: txp [04:04] */
#define Wr_ETH_macmode_txp(x) WriteRegBits(ETH_MACMODE,0x10,4,x)
#define Rd_ETH_macmode_txp(x) ReadRegBits(ETH_MACMODE,0x10,4)
#define ETH_MACMODE_TXP_MASK                                       0x00000010
#define ETH_MACMODE_TXP_ALIGN                                      0
#define ETH_MACMODE_TXP_BITS                                       1
#define ETH_MACMODE_TXP_SHIFT                                      4

/* ETH :: macmode :: rsp [03:03] */
#define Wr_ETH_macmode_rsp(x) WriteRegBits(ETH_MACMODE,0x8,3,x)
#define Rd_ETH_macmode_rsp(x) ReadRegBits(ETH_MACMODE,0x8,3)
#define ETH_MACMODE_RSP_MASK                                       0x00000008
#define ETH_MACMODE_RSP_ALIGN                                      0
#define ETH_MACMODE_RSP_BITS                                       1
#define ETH_MACMODE_RSP_SHIFT                                      3

/* ETH :: macmode :: dp [02:02] */
#define Wr_ETH_macmode_dp(x) WriteRegBits(ETH_MACMODE,0x4,2,x)
#define Rd_ETH_macmode_dp(x) ReadRegBits(ETH_MACMODE,0x4,2)
#define ETH_MACMODE_DP_MASK                                        0x00000004
#define ETH_MACMODE_DP_ALIGN                                       0
#define ETH_MACMODE_DP_BITS                                        1
#define ETH_MACMODE_DP_SHIFT                                       2

/* ETH :: macmode :: mspd [01:00] */
#define Wr_ETH_macmode_mspd(x) WriteRegBits(ETH_MACMODE,0x3,0,x)
#define Rd_ETH_macmode_mspd(x) ReadRegBits(ETH_MACMODE,0x3,0)
#define ETH_MACMODE_MSPD_MASK                                      0x00000003
#define ETH_MACMODE_MSPD_ALIGN                                     0
#define ETH_MACMODE_MSPD_BITS                                      2
#define ETH_MACMODE_MSPD_SHIFT                                     0


/****************************************************************************
 * ETH :: vlantag0
 ***************************************************************************/
/* ETH :: vlantag0 :: reserved0 [31:16] */
#define ETH_VLANTAG0_RESERVED0_MASK                                0xffff0000
#define ETH_VLANTAG0_RESERVED0_ALIGN                               0
#define ETH_VLANTAG0_RESERVED0_BITS                                16
#define ETH_VLANTAG0_RESERVED0_SHIFT                               16

/* ETH :: vlantag0 :: vlantag0 [15:00] */
#define Wr_ETH_vlantag0_vlantag0(x) WriteRegBits(ETH_VLANTAG0,0xffff,0,x)
#define Rd_ETH_vlantag0_vlantag0(x) ReadRegBits(ETH_VLANTAG0,0xffff,0)
#define ETH_VLANTAG0_VLANTAG0_MASK                                 0x0000ffff
#define ETH_VLANTAG0_VLANTAG0_ALIGN                                0
#define ETH_VLANTAG0_VLANTAG0_BITS                                 16
#define ETH_VLANTAG0_VLANTAG0_SHIFT                                0


/****************************************************************************
 * ETH :: txipg
 ***************************************************************************/
/* ETH :: txipg :: reserved0 [31:05] */
#define ETH_TXIPG_RESERVED0_MASK                                   0xffffffe0
#define ETH_TXIPG_RESERVED0_ALIGN                                  0
#define ETH_TXIPG_RESERVED0_BITS                                   27
#define ETH_TXIPG_RESERVED0_SHIFT                                  5

/* ETH :: txipg :: txipg [04:00] */
#define Wr_ETH_txipg_txipg(x) WriteRegBits(ETH_TXIPG,0x1f,0,x)
#define Rd_ETH_txipg_txipg(x) ReadRegBits(ETH_TXIPG,0x1f,0)
#define ETH_TXIPG_TXIPG_MASK                                       0x0000001f
#define ETH_TXIPG_TXIPG_ALIGN                                      0
#define ETH_TXIPG_TXIPG_BITS                                       5
#define ETH_TXIPG_TXIPG_SHIFT                                      0


/****************************************************************************
 * ETH :: txpctrl
 ***************************************************************************/
/* ETH :: txpctrl :: reserved0 [31:18] */
#define ETH_TXPCTRL_RESERVED0_MASK                                 0xfffc0000
#define ETH_TXPCTRL_RESERVED0_ALIGN                                0
#define ETH_TXPCTRL_RESERVED0_BITS                                 14
#define ETH_TXPCTRL_RESERVED0_SHIFT                                18

/* ETH :: txpctrl :: en [17:17] */
#define Wr_ETH_txpctrl_en(x) WriteRegBits(ETH_TXPCTRL,0x20000,17,x)
#define Rd_ETH_txpctrl_en(x) ReadRegBits(ETH_TXPCTRL,0x20000,17)
#define ETH_TXPCTRL_EN_MASK                                        0x00020000
#define ETH_TXPCTRL_EN_ALIGN                                       0
#define ETH_TXPCTRL_EN_BITS                                        1
#define ETH_TXPCTRL_EN_SHIFT                                       17

/* ETH :: txpctrl :: ptimer [16:00] */
#define Wr_ETH_txpctrl_ptimer(x) WriteRegBits(ETH_TXPCTRL,0x1ffff,0,x)
#define Rd_ETH_txpctrl_ptimer(x) ReadRegBits(ETH_TXPCTRL,0x1ffff,0)
#define ETH_TXPCTRL_PTIMER_MASK                                    0x0001ffff
#define ETH_TXPCTRL_PTIMER_ALIGN                                   0
#define ETH_TXPCTRL_PTIMER_BITS                                    17
#define ETH_TXPCTRL_PTIMER_SHIFT                                   0


/****************************************************************************
 * ETH :: txfifof
 ***************************************************************************/
/* ETH :: txfifof :: reserved0 [31:01] */
#define ETH_TXFIFOF_RESERVED0_MASK                                 0xfffffffe
#define ETH_TXFIFOF_RESERVED0_ALIGN                                0
#define ETH_TXFIFOF_RESERVED0_BITS                                 31
#define ETH_TXFIFOF_RESERVED0_SHIFT                                1

/* ETH :: txfifof :: flush [00:00] */
#define Wr_ETH_txfifof_flush(x) WriteRegBits(ETH_TXFIFOF,0x1,0,x)
#define Rd_ETH_txfifof_flush(x) ReadRegBits(ETH_TXFIFOF,0x1,0)
#define ETH_TXFIFOF_FLUSH_MASK                                     0x00000001
#define ETH_TXFIFOF_FLUSH_ALIGN                                    0
#define ETH_TXFIFOF_FLUSH_BITS                                     1
#define ETH_TXFIFOF_FLUSH_SHIFT                                    0


/****************************************************************************
 * ETH :: rxfifostat
 ***************************************************************************/
/* ETH :: rxfifostat :: reserved0 [31:02] */
#define ETH_RXFIFOSTAT_RESERVED0_MASK                              0xfffffffc
#define ETH_RXFIFOSTAT_RESERVED0_ALIGN                             0
#define ETH_RXFIFOSTAT_RESERVED0_BITS                              30
#define ETH_RXFIFOSTAT_RESERVED0_SHIFT                             2

/* ETH :: rxfifostat :: rxor [01:01] */
#define Wr_ETH_rxfifostat_rxor(x) WriteRegBits(ETH_RXFIFOSTAT,0x2,1,x)
#define Rd_ETH_rxfifostat_rxor(x) ReadRegBits(ETH_RXFIFOSTAT,0x2,1)
#define ETH_RXFIFOSTAT_RXOR_MASK                                   0x00000002
#define ETH_RXFIFOSTAT_RXOR_ALIGN                                  0
#define ETH_RXFIFOSTAT_RXOR_BITS                                   1
#define ETH_RXFIFOSTAT_RXOR_SHIFT                                  1

/* ETH :: rxfifostat :: rxur [00:00] */
#define Wr_ETH_rxfifostat_rxur(x) WriteRegBits(ETH_RXFIFOSTAT,0x1,0,x)
#define Rd_ETH_rxfifostat_rxur(x) ReadRegBits(ETH_RXFIFOSTAT,0x1,0)
#define ETH_RXFIFOSTAT_RXUR_MASK                                   0x00000001
#define ETH_RXFIFOSTAT_RXUR_ALIGN                                  0
#define ETH_RXFIFOSTAT_RXUR_BITS                                   1
#define ETH_RXFIFOSTAT_RXUR_SHIFT                                  0


/****************************************************************************
 * ETH :: txfifostat
 ***************************************************************************/
/* ETH :: txfifostat :: reserved0 [31:02] */
#define ETH_TXFIFOSTAT_RESERVED0_MASK                              0xfffffffc
#define ETH_TXFIFOSTAT_RESERVED0_ALIGN                             0
#define ETH_TXFIFOSTAT_RESERVED0_BITS                              30
#define ETH_TXFIFOSTAT_RESERVED0_SHIFT                             2

/* ETH :: txfifostat :: txor [01:01] */
#define Wr_ETH_txfifostat_txor(x) WriteRegBits(ETH_TXFIFOSTAT,0x2,1,x)
#define Rd_ETH_txfifostat_txor(x) ReadRegBits(ETH_TXFIFOSTAT,0x2,1)
#define ETH_TXFIFOSTAT_TXOR_MASK                                   0x00000002
#define ETH_TXFIFOSTAT_TXOR_ALIGN                                  0
#define ETH_TXFIFOSTAT_TXOR_BITS                                   1
#define ETH_TXFIFOSTAT_TXOR_SHIFT                                  1

/* ETH :: txfifostat :: txur [00:00] */
#define Wr_ETH_txfifostat_txur(x) WriteRegBits(ETH_TXFIFOSTAT,0x1,0,x)
#define Rd_ETH_txfifostat_txur(x) ReadRegBits(ETH_TXFIFOSTAT,0x1,0)
#define ETH_TXFIFOSTAT_TXUR_MASK                                   0x00000001
#define ETH_TXFIFOSTAT_TXUR_ALIGN                                  0
#define ETH_TXFIFOSTAT_TXUR_BITS                                   1
#define ETH_TXFIFOSTAT_TXUR_SHIFT                                  0


/****************************************************************************
 * ETH :: txoctgood
 ***************************************************************************/
/* ETH :: txoctgood :: txoctgood [31:00] */
#define Wr_ETH_txoctgood_txoctgood(x) WriteReg(ETH_TXOCTGOOD,x)
#define Rd_ETH_txoctgood_txoctgood(x) ReadReg(ETH_TXOCTGOOD)
#define ETH_TXOCTGOOD_TXOCTGOOD_MASK                               0xffffffff
#define ETH_TXOCTGOOD_TXOCTGOOD_ALIGN                              0
#define ETH_TXOCTGOOD_TXOCTGOOD_BITS                               32
#define ETH_TXOCTGOOD_TXOCTGOOD_SHIFT                              0


/****************************************************************************
 * ETH :: txfrmgood
 ***************************************************************************/
/* ETH :: txfrmgood :: reserved0 [31:16] */
#define ETH_TXFRMGOOD_RESERVED0_MASK                               0xffff0000
#define ETH_TXFRMGOOD_RESERVED0_ALIGN                              0
#define ETH_TXFRMGOOD_RESERVED0_BITS                               16
#define ETH_TXFRMGOOD_RESERVED0_SHIFT                              16

/* ETH :: txfrmgood :: txfrmgood [15:00] */
#define Wr_ETH_txfrmgood_txfrmgood(x) WriteRegBits(ETH_TXFRMGOOD,0xffff,0,x)
#define Rd_ETH_txfrmgood_txfrmgood(x) ReadRegBits(ETH_TXFRMGOOD,0xffff,0)
#define ETH_TXFRMGOOD_TXFRMGOOD_MASK                               0x0000ffff
#define ETH_TXFRMGOOD_TXFRMGOOD_ALIGN                              0
#define ETH_TXFRMGOOD_TXFRMGOOD_BITS                               16
#define ETH_TXFRMGOOD_TXFRMGOOD_SHIFT                              0


/****************************************************************************
 * ETH :: txocttotal
 ***************************************************************************/
/* ETH :: txocttotal :: txocttotal [31:00] */
#define Wr_ETH_txocttotal_txocttotal(x) WriteReg(ETH_TXOCTTOTAL,x)
#define Rd_ETH_txocttotal_txocttotal(x) ReadReg(ETH_TXOCTTOTAL)
#define ETH_TXOCTTOTAL_TXOCTTOTAL_MASK                             0xffffffff
#define ETH_TXOCTTOTAL_TXOCTTOTAL_ALIGN                            0
#define ETH_TXOCTTOTAL_TXOCTTOTAL_BITS                             32
#define ETH_TXOCTTOTAL_TXOCTTOTAL_SHIFT                            0


/****************************************************************************
 * ETH :: txfrmtotal
 ***************************************************************************/
/* ETH :: txfrmtotal :: reserved0 [31:16] */
#define ETH_TXFRMTOTAL_RESERVED0_MASK                              0xffff0000
#define ETH_TXFRMTOTAL_RESERVED0_ALIGN                             0
#define ETH_TXFRMTOTAL_RESERVED0_BITS                              16
#define ETH_TXFRMTOTAL_RESERVED0_SHIFT                             16

/* ETH :: txfrmtotal :: txfrmtotal [15:00] */
#define Wr_ETH_txfrmtotal_txfrmtotal(x) WriteRegBits(ETH_TXFRMTOTAL,0xffff,0,x)
#define Rd_ETH_txfrmtotal_txfrmtotal(x) ReadRegBits(ETH_TXFRMTOTAL,0xffff,0)
#define ETH_TXFRMTOTAL_TXFRMTOTAL_MASK                             0x0000ffff
#define ETH_TXFRMTOTAL_TXFRMTOTAL_ALIGN                            0
#define ETH_TXFRMTOTAL_TXFRMTOTAL_BITS                             16
#define ETH_TXFRMTOTAL_TXFRMTOTAL_SHIFT                            0


/****************************************************************************
 * ETH :: txbcastgood
 ***************************************************************************/
/* ETH :: txbcastgood :: reserved0 [31:16] */
#define ETH_TXBCASTGOOD_RESERVED0_MASK                             0xffff0000
#define ETH_TXBCASTGOOD_RESERVED0_ALIGN                            0
#define ETH_TXBCASTGOOD_RESERVED0_BITS                             16
#define ETH_TXBCASTGOOD_RESERVED0_SHIFT                            16

/* ETH :: txbcastgood :: txbcastgood [15:00] */
#define Wr_ETH_txbcastgood_txbcastgood(x) WriteRegBits(ETH_TXBCASTGOOD,0xffff,0,x)
#define Rd_ETH_txbcastgood_txbcastgood(x) ReadRegBits(ETH_TXBCASTGOOD,0xffff,0)
#define ETH_TXBCASTGOOD_TXBCASTGOOD_MASK                           0x0000ffff
#define ETH_TXBCASTGOOD_TXBCASTGOOD_ALIGN                          0
#define ETH_TXBCASTGOOD_TXBCASTGOOD_BITS                           16
#define ETH_TXBCASTGOOD_TXBCASTGOOD_SHIFT                          0


/****************************************************************************
 * ETH :: txmcastgood
 ***************************************************************************/
/* ETH :: txmcastgood :: reserved0 [31:16] */
#define ETH_TXMCASTGOOD_RESERVED0_MASK                             0xffff0000
#define ETH_TXMCASTGOOD_RESERVED0_ALIGN                            0
#define ETH_TXMCASTGOOD_RESERVED0_BITS                             16
#define ETH_TXMCASTGOOD_RESERVED0_SHIFT                            16

/* ETH :: txmcastgood :: txmcastgood [15:00] */
#define Wr_ETH_txmcastgood_txmcastgood(x) WriteRegBits(ETH_TXMCASTGOOD,0xffff,0,x)
#define Rd_ETH_txmcastgood_txmcastgood(x) ReadRegBits(ETH_TXMCASTGOOD,0xffff,0)
#define ETH_TXMCASTGOOD_TXMCASTGOOD_MASK                           0x0000ffff
#define ETH_TXMCASTGOOD_TXMCASTGOOD_ALIGN                          0
#define ETH_TXMCASTGOOD_TXMCASTGOOD_BITS                           16
#define ETH_TXMCASTGOOD_TXMCASTGOOD_SHIFT                          0


/****************************************************************************
 * ETH :: tx64
 ***************************************************************************/
/* ETH :: tx64 :: reserved0 [31:16] */
#define ETH_TX64_RESERVED0_MASK                                    0xffff0000
#define ETH_TX64_RESERVED0_ALIGN                                   0
#define ETH_TX64_RESERVED0_BITS                                    16
#define ETH_TX64_RESERVED0_SHIFT                                   16

/* ETH :: tx64 :: tx64 [15:00] */
#define Wr_ETH_tx64_tx64(x) WriteRegBits(ETH_TX64,0xffff,0,x)
#define Rd_ETH_tx64_tx64(x) ReadRegBits(ETH_TX64,0xffff,0)
#define ETH_TX64_TX64_MASK                                         0x0000ffff
#define ETH_TX64_TX64_ALIGN                                        0
#define ETH_TX64_TX64_BITS                                         16
#define ETH_TX64_TX64_SHIFT                                        0


/****************************************************************************
 * ETH :: tx65_127
 ***************************************************************************/
/* ETH :: tx65_127 :: reserved0 [31:16] */
#define ETH_TX65_127_RESERVED0_MASK                                0xffff0000
#define ETH_TX65_127_RESERVED0_ALIGN                               0
#define ETH_TX65_127_RESERVED0_BITS                                16
#define ETH_TX65_127_RESERVED0_SHIFT                               16

/* ETH :: tx65_127 :: tx65_127 [15:00] */
#define Wr_ETH_tx65_127_tx65_127(x) WriteRegBits(ETH_TX65_127,0xffff,0,x)
#define Rd_ETH_tx65_127_tx65_127(x) ReadRegBits(ETH_TX65_127,0xffff,0)
#define ETH_TX65_127_TX65_127_MASK                                 0x0000ffff
#define ETH_TX65_127_TX65_127_ALIGN                                0
#define ETH_TX65_127_TX65_127_BITS                                 16
#define ETH_TX65_127_TX65_127_SHIFT                                0


/****************************************************************************
 * ETH :: tx128_255
 ***************************************************************************/
/* ETH :: tx128_255 :: reserved0 [31:16] */
#define ETH_TX128_255_RESERVED0_MASK                               0xffff0000
#define ETH_TX128_255_RESERVED0_ALIGN                              0
#define ETH_TX128_255_RESERVED0_BITS                               16
#define ETH_TX128_255_RESERVED0_SHIFT                              16

/* ETH :: tx128_255 :: tx128_255 [15:00] */
#define Wr_ETH_tx128_255_tx128_255(x) WriteRegBits(ETH_TX128_255,0xffff,0,x)
#define Rd_ETH_tx128_255_tx128_255(x) ReadRegBits(ETH_TX128_255,0xffff,0)
#define ETH_TX128_255_TX128_255_MASK                               0x0000ffff
#define ETH_TX128_255_TX128_255_ALIGN                              0
#define ETH_TX128_255_TX128_255_BITS                               16
#define ETH_TX128_255_TX128_255_SHIFT                              0


/****************************************************************************
 * ETH :: tx256_511
 ***************************************************************************/
/* ETH :: tx256_511 :: reserved0 [31:16] */
#define ETH_TX256_511_RESERVED0_MASK                               0xffff0000
#define ETH_TX256_511_RESERVED0_ALIGN                              0
#define ETH_TX256_511_RESERVED0_BITS                               16
#define ETH_TX256_511_RESERVED0_SHIFT                              16

/* ETH :: tx256_511 :: tx256_511 [15:00] */
#define Wr_ETH_tx256_511_tx256_511(x) WriteRegBits(ETH_TX256_511,0xffff,0,x)
#define Rd_ETH_tx256_511_tx256_511(x) ReadRegBits(ETH_TX256_511,0xffff,0)
#define ETH_TX256_511_TX256_511_MASK                               0x0000ffff
#define ETH_TX256_511_TX256_511_ALIGN                              0
#define ETH_TX256_511_TX256_511_BITS                               16
#define ETH_TX256_511_TX256_511_SHIFT                              0


/****************************************************************************
 * ETH :: tx512_1023
 ***************************************************************************/
/* ETH :: tx512_1023 :: reserved0 [31:16] */
#define ETH_TX512_1023_RESERVED0_MASK                              0xffff0000
#define ETH_TX512_1023_RESERVED0_ALIGN                             0
#define ETH_TX512_1023_RESERVED0_BITS                              16
#define ETH_TX512_1023_RESERVED0_SHIFT                             16

/* ETH :: tx512_1023 :: tx512_1023 [15:00] */
#define Wr_ETH_tx512_1023_tx512_1023(x) WriteRegBits(ETH_TX512_1023,0xffff,0,x)
#define Rd_ETH_tx512_1023_tx512_1023(x) ReadRegBits(ETH_TX512_1023,0xffff,0)
#define ETH_TX512_1023_TX512_1023_MASK                             0x0000ffff
#define ETH_TX512_1023_TX512_1023_ALIGN                            0
#define ETH_TX512_1023_TX512_1023_BITS                             16
#define ETH_TX512_1023_TX512_1023_SHIFT                            0


/****************************************************************************
 * ETH :: tx1024_MAX
 ***************************************************************************/
/* ETH :: tx1024_MAX :: reserved0 [31:16] */
#define ETH_TX1024_MAX_RESERVED0_MASK                              0xffff0000
#define ETH_TX1024_MAX_RESERVED0_ALIGN                             0
#define ETH_TX1024_MAX_RESERVED0_BITS                              16
#define ETH_TX1024_MAX_RESERVED0_SHIFT                             16

/* ETH :: tx1024_MAX :: tx1024_MAX [15:00] */
#define Wr_ETH_tx1024_MAX_tx1024_MAX(x) WriteRegBits(ETH_TX1024_MAX,0xffff,0,x)
#define Rd_ETH_tx1024_MAX_tx1024_MAX(x) ReadRegBits(ETH_TX1024_MAX,0xffff,0)
#define ETH_TX1024_MAX_TX1024_MAX_MASK                             0x0000ffff
#define ETH_TX1024_MAX_TX1024_MAX_ALIGN                            0
#define ETH_TX1024_MAX_TX1024_MAX_BITS                             16
#define ETH_TX1024_MAX_TX1024_MAX_SHIFT                            0


/****************************************************************************
 * ETH :: txjabber
 ***************************************************************************/
/* ETH :: txjabber :: reserved0 [31:16] */
#define ETH_TXJABBER_RESERVED0_MASK                                0xffff0000
#define ETH_TXJABBER_RESERVED0_ALIGN                               0
#define ETH_TXJABBER_RESERVED0_BITS                                16
#define ETH_TXJABBER_RESERVED0_SHIFT                               16

/* ETH :: txjabber :: txjabber [15:00] */
#define Wr_ETH_txjabber_txjabber(x) WriteRegBits(ETH_TXJABBER,0xffff,0,x)
#define Rd_ETH_txjabber_txjabber(x) ReadRegBits(ETH_TXJABBER,0xffff,0)
#define ETH_TXJABBER_TXJABBER_MASK                                 0x0000ffff
#define ETH_TXJABBER_TXJABBER_ALIGN                                0
#define ETH_TXJABBER_TXJABBER_BITS                                 16
#define ETH_TXJABBER_TXJABBER_SHIFT                                0


/****************************************************************************
 * ETH :: txjumbo
 ***************************************************************************/
/* ETH :: txjumbo :: reserved0 [31:16] */
#define ETH_TXJUMBO_RESERVED0_MASK                                 0xffff0000
#define ETH_TXJUMBO_RESERVED0_ALIGN                                0
#define ETH_TXJUMBO_RESERVED0_BITS                                 16
#define ETH_TXJUMBO_RESERVED0_SHIFT                                16

/* ETH :: txjumbo :: txjumbo [15:00] */
#define Wr_ETH_txjumbo_txjumbo(x) WriteRegBits(ETH_TXJUMBO,0xffff,0,x)
#define Rd_ETH_txjumbo_txjumbo(x) ReadRegBits(ETH_TXJUMBO,0xffff,0)
#define ETH_TXJUMBO_TXJUMBO_MASK                                   0x0000ffff
#define ETH_TXJUMBO_TXJUMBO_ALIGN                                  0
#define ETH_TXJUMBO_TXJUMBO_BITS                                   16
#define ETH_TXJUMBO_TXJUMBO_SHIFT                                  0


/****************************************************************************
 * ETH :: txfrag
 ***************************************************************************/
/* ETH :: txfrag :: reserved0 [31:16] */
#define ETH_TXFRAG_RESERVED0_MASK                                  0xffff0000
#define ETH_TXFRAG_RESERVED0_ALIGN                                 0
#define ETH_TXFRAG_RESERVED0_BITS                                  16
#define ETH_TXFRAG_RESERVED0_SHIFT                                 16

/* ETH :: txfrag :: txfrag [15:00] */
#define Wr_ETH_txfrag_txfrag(x) WriteRegBits(ETH_TXFRAG,0xffff,0,x)
#define Rd_ETH_txfrag_txfrag(x) ReadRegBits(ETH_TXFRAG,0xffff,0)
#define ETH_TXFRAG_TXFRAG_MASK                                     0x0000ffff
#define ETH_TXFRAG_TXFRAG_ALIGN                                    0
#define ETH_TXFRAG_TXFRAG_BITS                                     16
#define ETH_TXFRAG_TXFRAG_SHIFT                                    0


/****************************************************************************
 * ETH :: txunderrun
 ***************************************************************************/
/* ETH :: txunderrun :: reserved0 [31:16] */
#define ETH_TXUNDERRUN_RESERVED0_MASK                              0xffff0000
#define ETH_TXUNDERRUN_RESERVED0_ALIGN                             0
#define ETH_TXUNDERRUN_RESERVED0_BITS                              16
#define ETH_TXUNDERRUN_RESERVED0_SHIFT                             16

/* ETH :: txunderrun :: txunderrun [15:00] */
#define Wr_ETH_txunderrun_txunderrun(x) WriteRegBits(ETH_TXUNDERRUN,0xffff,0,x)
#define Rd_ETH_txunderrun_txunderrun(x) ReadRegBits(ETH_TXUNDERRUN,0xffff,0)
#define ETH_TXUNDERRUN_TXUNDERRUN_MASK                             0x0000ffff
#define ETH_TXUNDERRUN_TXUNDERRUN_ALIGN                            0
#define ETH_TXUNDERRUN_TXUNDERRUN_BITS                             16
#define ETH_TXUNDERRUN_TXUNDERRUN_SHIFT                            0


/****************************************************************************
 * ETH :: txcoltotal
 ***************************************************************************/
/* ETH :: txcoltotal :: reserved0 [31:16] */
#define ETH_TXCOLTOTAL_RESERVED0_MASK                              0xffff0000
#define ETH_TXCOLTOTAL_RESERVED0_ALIGN                             0
#define ETH_TXCOLTOTAL_RESERVED0_BITS                              16
#define ETH_TXCOLTOTAL_RESERVED0_SHIFT                             16

/* ETH :: txcoltotal :: txcoltotal [15:00] */
#define Wr_ETH_txcoltotal_txcoltotal(x) WriteRegBits(ETH_TXCOLTOTAL,0xffff,0,x)
#define Rd_ETH_txcoltotal_txcoltotal(x) ReadRegBits(ETH_TXCOLTOTAL,0xffff,0)
#define ETH_TXCOLTOTAL_TXCOLTOTAL_MASK                             0x0000ffff
#define ETH_TXCOLTOTAL_TXCOLTOTAL_ALIGN                            0
#define ETH_TXCOLTOTAL_TXCOLTOTAL_BITS                             16
#define ETH_TXCOLTOTAL_TXCOLTOTAL_SHIFT                            0


/****************************************************************************
 * ETH :: tx1col
 ***************************************************************************/
/* ETH :: tx1col :: reserved0 [31:16] */
#define ETH_TX1COL_RESERVED0_MASK                                  0xffff0000
#define ETH_TX1COL_RESERVED0_ALIGN                                 0
#define ETH_TX1COL_RESERVED0_BITS                                  16
#define ETH_TX1COL_RESERVED0_SHIFT                                 16

/* ETH :: tx1col :: tx1col [15:00] */
#define Wr_ETH_tx1col_tx1col(x) WriteRegBits(ETH_TX1COL,0xffff,0,x)
#define Rd_ETH_tx1col_tx1col(x) ReadRegBits(ETH_TX1COL,0xffff,0)
#define ETH_TX1COL_TX1COL_MASK                                     0x0000ffff
#define ETH_TX1COL_TX1COL_ALIGN                                    0
#define ETH_TX1COL_TX1COL_BITS                                     16
#define ETH_TX1COL_TX1COL_SHIFT                                    0


/****************************************************************************
 * ETH :: txmcol
 ***************************************************************************/
/* ETH :: txmcol :: reserved0 [31:16] */
#define ETH_TXMCOL_RESERVED0_MASK                                  0xffff0000
#define ETH_TXMCOL_RESERVED0_ALIGN                                 0
#define ETH_TXMCOL_RESERVED0_BITS                                  16
#define ETH_TXMCOL_RESERVED0_SHIFT                                 16

/* ETH :: txmcol :: txmcol [15:00] */
#define Wr_ETH_txmcol_txmcol(x) WriteRegBits(ETH_TXMCOL,0xffff,0,x)
#define Rd_ETH_txmcol_txmcol(x) ReadRegBits(ETH_TXMCOL,0xffff,0)
#define ETH_TXMCOL_TXMCOL_MASK                                     0x0000ffff
#define ETH_TXMCOL_TXMCOL_ALIGN                                    0
#define ETH_TXMCOL_TXMCOL_BITS                                     16
#define ETH_TXMCOL_TXMCOL_SHIFT                                    0


/****************************************************************************
 * ETH :: txexcol
 ***************************************************************************/
/* ETH :: txexcol :: reserved0 [31:16] */
#define ETH_TXEXCOL_RESERVED0_MASK                                 0xffff0000
#define ETH_TXEXCOL_RESERVED0_ALIGN                                0
#define ETH_TXEXCOL_RESERVED0_BITS                                 16
#define ETH_TXEXCOL_RESERVED0_SHIFT                                16

/* ETH :: txexcol :: txexcol [15:00] */
#define Wr_ETH_txexcol_txexcol(x) WriteRegBits(ETH_TXEXCOL,0xffff,0,x)
#define Rd_ETH_txexcol_txexcol(x) ReadRegBits(ETH_TXEXCOL,0xffff,0)
#define ETH_TXEXCOL_TXEXCOL_MASK                                   0x0000ffff
#define ETH_TXEXCOL_TXEXCOL_ALIGN                                  0
#define ETH_TXEXCOL_TXEXCOL_BITS                                   16
#define ETH_TXEXCOL_TXEXCOL_SHIFT                                  0


/****************************************************************************
 * ETH :: txlate
 ***************************************************************************/
/* ETH :: txlate :: reserved0 [31:16] */
#define ETH_TXLATE_RESERVED0_MASK                                  0xffff0000
#define ETH_TXLATE_RESERVED0_ALIGN                                 0
#define ETH_TXLATE_RESERVED0_BITS                                  16
#define ETH_TXLATE_RESERVED0_SHIFT                                 16

/* ETH :: txlate :: txlate [15:00] */
#define Wr_ETH_txlate_txlate(x) WriteRegBits(ETH_TXLATE,0xffff,0,x)
#define Rd_ETH_txlate_txlate(x) ReadRegBits(ETH_TXLATE,0xffff,0)
#define ETH_TXLATE_TXLATE_MASK                                     0x0000ffff
#define ETH_TXLATE_TXLATE_ALIGN                                    0
#define ETH_TXLATE_TXLATE_BITS                                     16
#define ETH_TXLATE_TXLATE_SHIFT                                    0


/****************************************************************************
 * ETH :: txdefer
 ***************************************************************************/
/* ETH :: txdefer :: reserved0 [31:16] */
#define ETH_TXDEFER_RESERVED0_MASK                                 0xffff0000
#define ETH_TXDEFER_RESERVED0_ALIGN                                0
#define ETH_TXDEFER_RESERVED0_BITS                                 16
#define ETH_TXDEFER_RESERVED0_SHIFT                                16

/* ETH :: txdefer :: txdefer [15:00] */
#define Wr_ETH_txdefer_txdefer(x) WriteRegBits(ETH_TXDEFER,0xffff,0,x)
#define Rd_ETH_txdefer_txdefer(x) ReadRegBits(ETH_TXDEFER,0xffff,0)
#define ETH_TXDEFER_TXDEFER_MASK                                   0x0000ffff
#define ETH_TXDEFER_TXDEFER_ALIGN                                  0
#define ETH_TXDEFER_TXDEFER_BITS                                   16
#define ETH_TXDEFER_TXDEFER_SHIFT                                  0


/****************************************************************************
 * ETH :: txnocrs
 ***************************************************************************/
/* ETH :: txnocrs :: reserved0 [31:16] */
#define ETH_TXNOCRS_RESERVED0_MASK                                 0xffff0000
#define ETH_TXNOCRS_RESERVED0_ALIGN                                0
#define ETH_TXNOCRS_RESERVED0_BITS                                 16
#define ETH_TXNOCRS_RESERVED0_SHIFT                                16

/* ETH :: txnocrs :: txnocrs [15:00] */
#define Wr_ETH_txnocrs_txnocrs(x) WriteRegBits(ETH_TXNOCRS,0xffff,0,x)
#define Rd_ETH_txnocrs_txnocrs(x) ReadRegBits(ETH_TXNOCRS,0xffff,0)
#define ETH_TXNOCRS_TXNOCRS_MASK                                   0x0000ffff
#define ETH_TXNOCRS_TXNOCRS_ALIGN                                  0
#define ETH_TXNOCRS_TXNOCRS_BITS                                   16
#define ETH_TXNOCRS_TXNOCRS_SHIFT                                  0


/****************************************************************************
 * ETH :: txpause
 ***************************************************************************/
/* ETH :: txpause :: reserved0 [31:16] */
#define ETH_TXPAUSE_RESERVED0_MASK                                 0xffff0000
#define ETH_TXPAUSE_RESERVED0_ALIGN                                0
#define ETH_TXPAUSE_RESERVED0_BITS                                 16
#define ETH_TXPAUSE_RESERVED0_SHIFT                                16

/* ETH :: txpause :: txpause [15:00] */
#define Wr_ETH_txpause_txpause(x) WriteRegBits(ETH_TXPAUSE,0xffff,0,x)
#define Rd_ETH_txpause_txpause(x) ReadRegBits(ETH_TXPAUSE,0xffff,0)
#define ETH_TXPAUSE_TXPAUSE_MASK                                   0x0000ffff
#define ETH_TXPAUSE_TXPAUSE_ALIGN                                  0
#define ETH_TXPAUSE_TXPAUSE_BITS                                   16
#define ETH_TXPAUSE_TXPAUSE_SHIFT                                  0


/****************************************************************************
 * ETH :: txcntof
 ***************************************************************************/
/* ETH :: txcntof :: reserved0 [31:24] */
#define ETH_TXCNTOF_RESERVED0_MASK                                 0xff000000
#define ETH_TXCNTOF_RESERVED0_ALIGN                                0
#define ETH_TXCNTOF_RESERVED0_BITS                                 8
#define ETH_TXCNTOF_RESERVED0_SHIFT                                24

/* ETH :: txcntof :: txoctgood_of [23:23] */
#define Wr_ETH_txcntof_txoctgood_of(x) WriteRegBits(ETH_TXCNTOF,0x800000,23,x)
#define Rd_ETH_txcntof_txoctgood_of(x) ReadRegBits(ETH_TXCNTOF,0x800000,23)
#define ETH_TXCNTOF_TXOCTGOOD_OF_MASK                              0x00800000
#define ETH_TXCNTOF_TXOCTGOOD_OF_ALIGN                             0
#define ETH_TXCNTOF_TXOCTGOOD_OF_BITS                              1
#define ETH_TXCNTOF_TXOCTGOOD_OF_SHIFT                             23

/* ETH :: txcntof :: txfrmgood_of [22:22] */
#define Wr_ETH_txcntof_txfrmgood_of(x) WriteRegBits(ETH_TXCNTOF,0x400000,22,x)
#define Rd_ETH_txcntof_txfrmgood_of(x) ReadRegBits(ETH_TXCNTOF,0x400000,22)
#define ETH_TXCNTOF_TXFRMGOOD_OF_MASK                              0x00400000
#define ETH_TXCNTOF_TXFRMGOOD_OF_ALIGN                             0
#define ETH_TXCNTOF_TXFRMGOOD_OF_BITS                              1
#define ETH_TXCNTOF_TXFRMGOOD_OF_SHIFT                             22

/* ETH :: txcntof :: txocttotal_of [21:21] */
#define Wr_ETH_txcntof_txocttotal_of(x) WriteRegBits(ETH_TXCNTOF,0x200000,21,x)
#define Rd_ETH_txcntof_txocttotal_of(x) ReadRegBits(ETH_TXCNTOF,0x200000,21)
#define ETH_TXCNTOF_TXOCTTOTAL_OF_MASK                             0x00200000
#define ETH_TXCNTOF_TXOCTTOTAL_OF_ALIGN                            0
#define ETH_TXCNTOF_TXOCTTOTAL_OF_BITS                             1
#define ETH_TXCNTOF_TXOCTTOTAL_OF_SHIFT                            21

/* ETH :: txcntof :: txfrmtotal_of [20:20] */
#define Wr_ETH_txcntof_txfrmtotal_of(x) WriteRegBits(ETH_TXCNTOF,0x100000,20,x)
#define Rd_ETH_txcntof_txfrmtotal_of(x) ReadRegBits(ETH_TXCNTOF,0x100000,20)
#define ETH_TXCNTOF_TXFRMTOTAL_OF_MASK                             0x00100000
#define ETH_TXCNTOF_TXFRMTOTAL_OF_ALIGN                            0
#define ETH_TXCNTOF_TXFRMTOTAL_OF_BITS                             1
#define ETH_TXCNTOF_TXFRMTOTAL_OF_SHIFT                            20

/* ETH :: txcntof :: txbcastgood_of [19:19] */
#define Wr_ETH_txcntof_txbcastgood_of(x) WriteRegBits(ETH_TXCNTOF,0x80000,19,x)
#define Rd_ETH_txcntof_txbcastgood_of(x) ReadRegBits(ETH_TXCNTOF,0x80000,19)
#define ETH_TXCNTOF_TXBCASTGOOD_OF_MASK                            0x00080000
#define ETH_TXCNTOF_TXBCASTGOOD_OF_ALIGN                           0
#define ETH_TXCNTOF_TXBCASTGOOD_OF_BITS                            1
#define ETH_TXCNTOF_TXBCASTGOOD_OF_SHIFT                           19

/* ETH :: txcntof :: txmcastgood_of [18:18] */
#define Wr_ETH_txcntof_txmcastgood_of(x) WriteRegBits(ETH_TXCNTOF,0x40000,18,x)
#define Rd_ETH_txcntof_txmcastgood_of(x) ReadRegBits(ETH_TXCNTOF,0x40000,18)
#define ETH_TXCNTOF_TXMCASTGOOD_OF_MASK                            0x00040000
#define ETH_TXCNTOF_TXMCASTGOOD_OF_ALIGN                           0
#define ETH_TXCNTOF_TXMCASTGOOD_OF_BITS                            1
#define ETH_TXCNTOF_TXMCASTGOOD_OF_SHIFT                           18

/* ETH :: txcntof :: tx64_of [17:17] */
#define Wr_ETH_txcntof_tx64_of(x) WriteRegBits(ETH_TXCNTOF,0x20000,17,x)
#define Rd_ETH_txcntof_tx64_of(x) ReadRegBits(ETH_TXCNTOF,0x20000,17)
#define ETH_TXCNTOF_TX64_OF_MASK                                   0x00020000
#define ETH_TXCNTOF_TX64_OF_ALIGN                                  0
#define ETH_TXCNTOF_TX64_OF_BITS                                   1
#define ETH_TXCNTOF_TX64_OF_SHIFT                                  17

/* ETH :: txcntof :: tx65_127_of [16:16] */
#define Wr_ETH_txcntof_tx65_127_of(x) WriteRegBits(ETH_TXCNTOF,0x10000,16,x)
#define Rd_ETH_txcntof_tx65_127_of(x) ReadRegBits(ETH_TXCNTOF,0x10000,16)
#define ETH_TXCNTOF_TX65_127_OF_MASK                               0x00010000
#define ETH_TXCNTOF_TX65_127_OF_ALIGN                              0
#define ETH_TXCNTOF_TX65_127_OF_BITS                               1
#define ETH_TXCNTOF_TX65_127_OF_SHIFT                              16

/* ETH :: txcntof :: tx128_255_of [15:15] */
#define Wr_ETH_txcntof_tx128_255_of(x) WriteRegBits(ETH_TXCNTOF,0x8000,15,x)
#define Rd_ETH_txcntof_tx128_255_of(x) ReadRegBits(ETH_TXCNTOF,0x8000,15)
#define ETH_TXCNTOF_TX128_255_OF_MASK                              0x00008000
#define ETH_TXCNTOF_TX128_255_OF_ALIGN                             0
#define ETH_TXCNTOF_TX128_255_OF_BITS                              1
#define ETH_TXCNTOF_TX128_255_OF_SHIFT                             15

/* ETH :: txcntof :: tx256_511_of [14:14] */
#define Wr_ETH_txcntof_tx256_511_of(x) WriteRegBits(ETH_TXCNTOF,0x4000,14,x)
#define Rd_ETH_txcntof_tx256_511_of(x) ReadRegBits(ETH_TXCNTOF,0x4000,14)
#define ETH_TXCNTOF_TX256_511_OF_MASK                              0x00004000
#define ETH_TXCNTOF_TX256_511_OF_ALIGN                             0
#define ETH_TXCNTOF_TX256_511_OF_BITS                              1
#define ETH_TXCNTOF_TX256_511_OF_SHIFT                             14

/* ETH :: txcntof :: tx512_1023_of [13:13] */
#define Wr_ETH_txcntof_tx512_1023_of(x) WriteRegBits(ETH_TXCNTOF,0x2000,13,x)
#define Rd_ETH_txcntof_tx512_1023_of(x) ReadRegBits(ETH_TXCNTOF,0x2000,13)
#define ETH_TXCNTOF_TX512_1023_OF_MASK                             0x00002000
#define ETH_TXCNTOF_TX512_1023_OF_ALIGN                            0
#define ETH_TXCNTOF_TX512_1023_OF_BITS                             1
#define ETH_TXCNTOF_TX512_1023_OF_SHIFT                            13

/* ETH :: txcntof :: tx1024_max_of [12:12] */
#define Wr_ETH_txcntof_tx1024_max_of(x) WriteRegBits(ETH_TXCNTOF,0x1000,12,x)
#define Rd_ETH_txcntof_tx1024_max_of(x) ReadRegBits(ETH_TXCNTOF,0x1000,12)
#define ETH_TXCNTOF_TX1024_MAX_OF_MASK                             0x00001000
#define ETH_TXCNTOF_TX1024_MAX_OF_ALIGN                            0
#define ETH_TXCNTOF_TX1024_MAX_OF_BITS                             1
#define ETH_TXCNTOF_TX1024_MAX_OF_SHIFT                            12

/* ETH :: txcntof :: txjabber_of [11:11] */
#define Wr_ETH_txcntof_txjabber_of(x) WriteRegBits(ETH_TXCNTOF,0x800,11,x)
#define Rd_ETH_txcntof_txjabber_of(x) ReadRegBits(ETH_TXCNTOF,0x800,11)
#define ETH_TXCNTOF_TXJABBER_OF_MASK                               0x00000800
#define ETH_TXCNTOF_TXJABBER_OF_ALIGN                              0
#define ETH_TXCNTOF_TXJABBER_OF_BITS                               1
#define ETH_TXCNTOF_TXJABBER_OF_SHIFT                              11

/* ETH :: txcntof :: txjumbo_of [10:10] */
#define Wr_ETH_txcntof_txjumbo_of(x) WriteRegBits(ETH_TXCNTOF,0x400,10,x)
#define Rd_ETH_txcntof_txjumbo_of(x) ReadRegBits(ETH_TXCNTOF,0x400,10)
#define ETH_TXCNTOF_TXJUMBO_OF_MASK                                0x00000400
#define ETH_TXCNTOF_TXJUMBO_OF_ALIGN                               0
#define ETH_TXCNTOF_TXJUMBO_OF_BITS                                1
#define ETH_TXCNTOF_TXJUMBO_OF_SHIFT                               10

/* ETH :: txcntof :: txfrag_of [09:09] */
#define Wr_ETH_txcntof_txfrag_of(x) WriteRegBits(ETH_TXCNTOF,0x200,9,x)
#define Rd_ETH_txcntof_txfrag_of(x) ReadRegBits(ETH_TXCNTOF,0x200,9)
#define ETH_TXCNTOF_TXFRAG_OF_MASK                                 0x00000200
#define ETH_TXCNTOF_TXFRAG_OF_ALIGN                                0
#define ETH_TXCNTOF_TXFRAG_OF_BITS                                 1
#define ETH_TXCNTOF_TXFRAG_OF_SHIFT                                9

/* ETH :: txcntof :: txunderrun_of [08:08] */
#define Wr_ETH_txcntof_txunderrun_of(x) WriteRegBits(ETH_TXCNTOF,0x100,8,x)
#define Rd_ETH_txcntof_txunderrun_of(x) ReadRegBits(ETH_TXCNTOF,0x100,8)
#define ETH_TXCNTOF_TXUNDERRUN_OF_MASK                             0x00000100
#define ETH_TXCNTOF_TXUNDERRUN_OF_ALIGN                            0
#define ETH_TXCNTOF_TXUNDERRUN_OF_BITS                             1
#define ETH_TXCNTOF_TXUNDERRUN_OF_SHIFT                            8

/* ETH :: txcntof :: txcoltotal_of [07:07] */
#define Wr_ETH_txcntof_txcoltotal_of(x) WriteRegBits(ETH_TXCNTOF,0x80,7,x)
#define Rd_ETH_txcntof_txcoltotal_of(x) ReadRegBits(ETH_TXCNTOF,0x80,7)
#define ETH_TXCNTOF_TXCOLTOTAL_OF_MASK                             0x00000080
#define ETH_TXCNTOF_TXCOLTOTAL_OF_ALIGN                            0
#define ETH_TXCNTOF_TXCOLTOTAL_OF_BITS                             1
#define ETH_TXCNTOF_TXCOLTOTAL_OF_SHIFT                            7

/* ETH :: txcntof :: tx1col_of [06:06] */
#define Wr_ETH_txcntof_tx1col_of(x) WriteRegBits(ETH_TXCNTOF,0x40,6,x)
#define Rd_ETH_txcntof_tx1col_of(x) ReadRegBits(ETH_TXCNTOF,0x40,6)
#define ETH_TXCNTOF_TX1COL_OF_MASK                                 0x00000040
#define ETH_TXCNTOF_TX1COL_OF_ALIGN                                0
#define ETH_TXCNTOF_TX1COL_OF_BITS                                 1
#define ETH_TXCNTOF_TX1COL_OF_SHIFT                                6

/* ETH :: txcntof :: txmcol_of [05:05] */
#define Wr_ETH_txcntof_txmcol_of(x) WriteRegBits(ETH_TXCNTOF,0x20,5,x)
#define Rd_ETH_txcntof_txmcol_of(x) ReadRegBits(ETH_TXCNTOF,0x20,5)
#define ETH_TXCNTOF_TXMCOL_OF_MASK                                 0x00000020
#define ETH_TXCNTOF_TXMCOL_OF_ALIGN                                0
#define ETH_TXCNTOF_TXMCOL_OF_BITS                                 1
#define ETH_TXCNTOF_TXMCOL_OF_SHIFT                                5

/* ETH :: txcntof :: txexcol_of [04:04] */
#define Wr_ETH_txcntof_txexcol_of(x) WriteRegBits(ETH_TXCNTOF,0x10,4,x)
#define Rd_ETH_txcntof_txexcol_of(x) ReadRegBits(ETH_TXCNTOF,0x10,4)
#define ETH_TXCNTOF_TXEXCOL_OF_MASK                                0x00000010
#define ETH_TXCNTOF_TXEXCOL_OF_ALIGN                               0
#define ETH_TXCNTOF_TXEXCOL_OF_BITS                                1
#define ETH_TXCNTOF_TXEXCOL_OF_SHIFT                               4

/* ETH :: txcntof :: txlate_of [03:03] */
#define Wr_ETH_txcntof_txlate_of(x) WriteRegBits(ETH_TXCNTOF,0x8,3,x)
#define Rd_ETH_txcntof_txlate_of(x) ReadRegBits(ETH_TXCNTOF,0x8,3)
#define ETH_TXCNTOF_TXLATE_OF_MASK                                 0x00000008
#define ETH_TXCNTOF_TXLATE_OF_ALIGN                                0
#define ETH_TXCNTOF_TXLATE_OF_BITS                                 1
#define ETH_TXCNTOF_TXLATE_OF_SHIFT                                3

/* ETH :: txcntof :: txdefer_of [02:02] */
#define Wr_ETH_txcntof_txdefer_of(x) WriteRegBits(ETH_TXCNTOF,0x4,2,x)
#define Rd_ETH_txcntof_txdefer_of(x) ReadRegBits(ETH_TXCNTOF,0x4,2)
#define ETH_TXCNTOF_TXDEFER_OF_MASK                                0x00000004
#define ETH_TXCNTOF_TXDEFER_OF_ALIGN                               0
#define ETH_TXCNTOF_TXDEFER_OF_BITS                                1
#define ETH_TXCNTOF_TXDEFER_OF_SHIFT                               2

/* ETH :: txcntof :: txnocrs_of [01:01] */
#define Wr_ETH_txcntof_txnocrs_of(x) WriteRegBits(ETH_TXCNTOF,0x2,1,x)
#define Rd_ETH_txcntof_txnocrs_of(x) ReadRegBits(ETH_TXCNTOF,0x2,1)
#define ETH_TXCNTOF_TXNOCRS_OF_MASK                                0x00000002
#define ETH_TXCNTOF_TXNOCRS_OF_ALIGN                               0
#define ETH_TXCNTOF_TXNOCRS_OF_BITS                                1
#define ETH_TXCNTOF_TXNOCRS_OF_SHIFT                               1

/* ETH :: txcntof :: txpause_of [00:00] */
#define Wr_ETH_txcntof_txpause_of(x) WriteRegBits(ETH_TXCNTOF,0x1,0,x)
#define Rd_ETH_txcntof_txpause_of(x) ReadRegBits(ETH_TXCNTOF,0x1,0)
#define ETH_TXCNTOF_TXPAUSE_OF_MASK                                0x00000001
#define ETH_TXCNTOF_TXPAUSE_OF_ALIGN                               0
#define ETH_TXCNTOF_TXPAUSE_OF_BITS                                1
#define ETH_TXCNTOF_TXPAUSE_OF_SHIFT                               0


/****************************************************************************
 * ETH :: rxoctgood
 ***************************************************************************/
/* ETH :: rxoctgood :: rxoctgood [31:00] */
#define Wr_ETH_rxoctgood_rxoctgood(x) WriteReg(ETH_RXOCTGOOD,x)
#define Rd_ETH_rxoctgood_rxoctgood(x) ReadReg(ETH_RXOCTGOOD)
#define ETH_RXOCTGOOD_RXOCTGOOD_MASK                               0xffffffff
#define ETH_RXOCTGOOD_RXOCTGOOD_ALIGN                              0
#define ETH_RXOCTGOOD_RXOCTGOOD_BITS                               32
#define ETH_RXOCTGOOD_RXOCTGOOD_SHIFT                              0


/****************************************************************************
 * ETH :: rxfrmgood
 ***************************************************************************/
/* ETH :: rxfrmgood :: reserved0 [31:16] */
#define ETH_RXFRMGOOD_RESERVED0_MASK                               0xffff0000
#define ETH_RXFRMGOOD_RESERVED0_ALIGN                              0
#define ETH_RXFRMGOOD_RESERVED0_BITS                               16
#define ETH_RXFRMGOOD_RESERVED0_SHIFT                              16

/* ETH :: rxfrmgood :: rxfrmgood [15:00] */
#define Wr_ETH_rxfrmgood_rxfrmgood(x) WriteRegBits(ETH_RXFRMGOOD,0xffff,0,x)
#define Rd_ETH_rxfrmgood_rxfrmgood(x) ReadRegBits(ETH_RXFRMGOOD,0xffff,0)
#define ETH_RXFRMGOOD_RXFRMGOOD_MASK                               0x0000ffff
#define ETH_RXFRMGOOD_RXFRMGOOD_ALIGN                              0
#define ETH_RXFRMGOOD_RXFRMGOOD_BITS                               16
#define ETH_RXFRMGOOD_RXFRMGOOD_SHIFT                              0


/****************************************************************************
 * ETH :: rxocttotal
 ***************************************************************************/
/* ETH :: rxocttotal :: rxocttotal [31:00] */
#define Wr_ETH_rxocttotal_rxocttotal(x) WriteReg(ETH_RXOCTTOTAL,x)
#define Rd_ETH_rxocttotal_rxocttotal(x) ReadReg(ETH_RXOCTTOTAL)
#define ETH_RXOCTTOTAL_RXOCTTOTAL_MASK                             0xffffffff
#define ETH_RXOCTTOTAL_RXOCTTOTAL_ALIGN                            0
#define ETH_RXOCTTOTAL_RXOCTTOTAL_BITS                             32
#define ETH_RXOCTTOTAL_RXOCTTOTAL_SHIFT                            0


/****************************************************************************
 * ETH :: rxfrmtotal
 ***************************************************************************/
/* ETH :: rxfrmtotal :: reserved0 [31:16] */
#define ETH_RXFRMTOTAL_RESERVED0_MASK                              0xffff0000
#define ETH_RXFRMTOTAL_RESERVED0_ALIGN                             0
#define ETH_RXFRMTOTAL_RESERVED0_BITS                              16
#define ETH_RXFRMTOTAL_RESERVED0_SHIFT                             16

/* ETH :: rxfrmtotal :: rxfrmtotal [15:00] */
#define Wr_ETH_rxfrmtotal_rxfrmtotal(x) WriteRegBits(ETH_RXFRMTOTAL,0xffff,0,x)
#define Rd_ETH_rxfrmtotal_rxfrmtotal(x) ReadRegBits(ETH_RXFRMTOTAL,0xffff,0)
#define ETH_RXFRMTOTAL_RXFRMTOTAL_MASK                             0x0000ffff
#define ETH_RXFRMTOTAL_RXFRMTOTAL_ALIGN                            0
#define ETH_RXFRMTOTAL_RXFRMTOTAL_BITS                             16
#define ETH_RXFRMTOTAL_RXFRMTOTAL_SHIFT                            0


/****************************************************************************
 * ETH :: rxbcastgood
 ***************************************************************************/
/* ETH :: rxbcastgood :: reserved0 [31:16] */
#define ETH_RXBCASTGOOD_RESERVED0_MASK                             0xffff0000
#define ETH_RXBCASTGOOD_RESERVED0_ALIGN                            0
#define ETH_RXBCASTGOOD_RESERVED0_BITS                             16
#define ETH_RXBCASTGOOD_RESERVED0_SHIFT                            16

/* ETH :: rxbcastgood :: rxbcastgood [15:00] */
#define Wr_ETH_rxbcastgood_rxbcastgood(x) WriteRegBits(ETH_RXBCASTGOOD,0xffff,0,x)
#define Rd_ETH_rxbcastgood_rxbcastgood(x) ReadRegBits(ETH_RXBCASTGOOD,0xffff,0)
#define ETH_RXBCASTGOOD_RXBCASTGOOD_MASK                           0x0000ffff
#define ETH_RXBCASTGOOD_RXBCASTGOOD_ALIGN                          0
#define ETH_RXBCASTGOOD_RXBCASTGOOD_BITS                           16
#define ETH_RXBCASTGOOD_RXBCASTGOOD_SHIFT                          0


/****************************************************************************
 * ETH :: rxmcastgood
 ***************************************************************************/
/* ETH :: rxmcastgood :: reserved0 [31:16] */
#define ETH_RXMCASTGOOD_RESERVED0_MASK                             0xffff0000
#define ETH_RXMCASTGOOD_RESERVED0_ALIGN                            0
#define ETH_RXMCASTGOOD_RESERVED0_BITS                             16
#define ETH_RXMCASTGOOD_RESERVED0_SHIFT                            16

/* ETH :: rxmcastgood :: rxmcastgood [15:00] */
#define Wr_ETH_rxmcastgood_rxmcastgood(x) WriteRegBits(ETH_RXMCASTGOOD,0xffff,0,x)
#define Rd_ETH_rxmcastgood_rxmcastgood(x) ReadRegBits(ETH_RXMCASTGOOD,0xffff,0)
#define ETH_RXMCASTGOOD_RXMCASTGOOD_MASK                           0x0000ffff
#define ETH_RXMCASTGOOD_RXMCASTGOOD_ALIGN                          0
#define ETH_RXMCASTGOOD_RXMCASTGOOD_BITS                           16
#define ETH_RXMCASTGOOD_RXMCASTGOOD_SHIFT                          0


/****************************************************************************
 * ETH :: rx64
 ***************************************************************************/
/* ETH :: rx64 :: reserved0 [31:16] */
#define ETH_RX64_RESERVED0_MASK                                    0xffff0000
#define ETH_RX64_RESERVED0_ALIGN                                   0
#define ETH_RX64_RESERVED0_BITS                                    16
#define ETH_RX64_RESERVED0_SHIFT                                   16

/* ETH :: rx64 :: rx64 [15:00] */
#define Wr_ETH_rx64_rx64(x) WriteRegBits(ETH_RX64,0xffff,0,x)
#define Rd_ETH_rx64_rx64(x) ReadRegBits(ETH_RX64,0xffff,0)
#define ETH_RX64_RX64_MASK                                         0x0000ffff
#define ETH_RX64_RX64_ALIGN                                        0
#define ETH_RX64_RX64_BITS                                         16
#define ETH_RX64_RX64_SHIFT                                        0


/****************************************************************************
 * ETH :: rx65_127
 ***************************************************************************/
/* ETH :: rx65_127 :: reserved0 [31:16] */
#define ETH_RX65_127_RESERVED0_MASK                                0xffff0000
#define ETH_RX65_127_RESERVED0_ALIGN                               0
#define ETH_RX65_127_RESERVED0_BITS                                16
#define ETH_RX65_127_RESERVED0_SHIFT                               16

/* ETH :: rx65_127 :: rx65_127 [15:00] */
#define Wr_ETH_rx65_127_rx65_127(x) WriteRegBits(ETH_RX65_127,0xffff,0,x)
#define Rd_ETH_rx65_127_rx65_127(x) ReadRegBits(ETH_RX65_127,0xffff,0)
#define ETH_RX65_127_RX65_127_MASK                                 0x0000ffff
#define ETH_RX65_127_RX65_127_ALIGN                                0
#define ETH_RX65_127_RX65_127_BITS                                 16
#define ETH_RX65_127_RX65_127_SHIFT                                0


/****************************************************************************
 * ETH :: rx128_255
 ***************************************************************************/
/* ETH :: rx128_255 :: reserved0 [31:16] */
#define ETH_RX128_255_RESERVED0_MASK                               0xffff0000
#define ETH_RX128_255_RESERVED0_ALIGN                              0
#define ETH_RX128_255_RESERVED0_BITS                               16
#define ETH_RX128_255_RESERVED0_SHIFT                              16

/* ETH :: rx128_255 :: rx128_255 [15:00] */
#define Wr_ETH_rx128_255_rx128_255(x) WriteRegBits(ETH_RX128_255,0xffff,0,x)
#define Rd_ETH_rx128_255_rx128_255(x) ReadRegBits(ETH_RX128_255,0xffff,0)
#define ETH_RX128_255_RX128_255_MASK                               0x0000ffff
#define ETH_RX128_255_RX128_255_ALIGN                              0
#define ETH_RX128_255_RX128_255_BITS                               16
#define ETH_RX128_255_RX128_255_SHIFT                              0


/****************************************************************************
 * ETH :: rx256_511
 ***************************************************************************/
/* ETH :: rx256_511 :: reserved0 [31:16] */
#define ETH_RX256_511_RESERVED0_MASK                               0xffff0000
#define ETH_RX256_511_RESERVED0_ALIGN                              0
#define ETH_RX256_511_RESERVED0_BITS                               16
#define ETH_RX256_511_RESERVED0_SHIFT                              16

/* ETH :: rx256_511 :: rx256_511 [15:00] */
#define Wr_ETH_rx256_511_rx256_511(x) WriteRegBits(ETH_RX256_511,0xffff,0,x)
#define Rd_ETH_rx256_511_rx256_511(x) ReadRegBits(ETH_RX256_511,0xffff,0)
#define ETH_RX256_511_RX256_511_MASK                               0x0000ffff
#define ETH_RX256_511_RX256_511_ALIGN                              0
#define ETH_RX256_511_RX256_511_BITS                               16
#define ETH_RX256_511_RX256_511_SHIFT                              0


/****************************************************************************
 * ETH :: rx512_1023
 ***************************************************************************/
/* ETH :: rx512_1023 :: reserved0 [31:16] */
#define ETH_RX512_1023_RESERVED0_MASK                              0xffff0000
#define ETH_RX512_1023_RESERVED0_ALIGN                             0
#define ETH_RX512_1023_RESERVED0_BITS                              16
#define ETH_RX512_1023_RESERVED0_SHIFT                             16

/* ETH :: rx512_1023 :: rx512_1023 [15:00] */
#define Wr_ETH_rx512_1023_rx512_1023(x) WriteRegBits(ETH_RX512_1023,0xffff,0,x)
#define Rd_ETH_rx512_1023_rx512_1023(x) ReadRegBits(ETH_RX512_1023,0xffff,0)
#define ETH_RX512_1023_RX512_1023_MASK                             0x0000ffff
#define ETH_RX512_1023_RX512_1023_ALIGN                            0
#define ETH_RX512_1023_RX512_1023_BITS                             16
#define ETH_RX512_1023_RX512_1023_SHIFT                            0


/****************************************************************************
 * ETH :: rx1024_MAX
 ***************************************************************************/
/* ETH :: rx1024_MAX :: reserved0 [31:16] */
#define ETH_RX1024_MAX_RESERVED0_MASK                              0xffff0000
#define ETH_RX1024_MAX_RESERVED0_ALIGN                             0
#define ETH_RX1024_MAX_RESERVED0_BITS                              16
#define ETH_RX1024_MAX_RESERVED0_SHIFT                             16

/* ETH :: rx1024_MAX :: rx1024_MAX [15:00] */
#define Wr_ETH_rx1024_MAX_rx1024_MAX(x) WriteRegBits(ETH_RX1024_MAX,0xffff,0,x)
#define Rd_ETH_rx1024_MAX_rx1024_MAX(x) ReadRegBits(ETH_RX1024_MAX,0xffff,0)
#define ETH_RX1024_MAX_RX1024_MAX_MASK                             0x0000ffff
#define ETH_RX1024_MAX_RX1024_MAX_ALIGN                            0
#define ETH_RX1024_MAX_RX1024_MAX_BITS                             16
#define ETH_RX1024_MAX_RX1024_MAX_SHIFT                            0


/****************************************************************************
 * ETH :: rxjabber
 ***************************************************************************/
/* ETH :: rxjabber :: reserved0 [31:16] */
#define ETH_RXJABBER_RESERVED0_MASK                                0xffff0000
#define ETH_RXJABBER_RESERVED0_ALIGN                               0
#define ETH_RXJABBER_RESERVED0_BITS                                16
#define ETH_RXJABBER_RESERVED0_SHIFT                               16

/* ETH :: rxjabber :: rxjabber [15:00] */
#define Wr_ETH_rxjabber_rxjabber(x) WriteRegBits(ETH_RXJABBER,0xffff,0,x)
#define Rd_ETH_rxjabber_rxjabber(x) ReadRegBits(ETH_RXJABBER,0xffff,0)
#define ETH_RXJABBER_RXJABBER_MASK                                 0x0000ffff
#define ETH_RXJABBER_RXJABBER_ALIGN                                0
#define ETH_RXJABBER_RXJABBER_BITS                                 16
#define ETH_RXJABBER_RXJABBER_SHIFT                                0


/****************************************************************************
 * ETH :: rxjumbo
 ***************************************************************************/
/* ETH :: rxjumbo :: reserved0 [31:16] */
#define ETH_RXJUMBO_RESERVED0_MASK                                 0xffff0000
#define ETH_RXJUMBO_RESERVED0_ALIGN                                0
#define ETH_RXJUMBO_RESERVED0_BITS                                 16
#define ETH_RXJUMBO_RESERVED0_SHIFT                                16

/* ETH :: rxjumbo :: rxjumbo [15:00] */
#define Wr_ETH_rxjumbo_rxjumbo(x) WriteRegBits(ETH_RXJUMBO,0xffff,0,x)
#define Rd_ETH_rxjumbo_rxjumbo(x) ReadRegBits(ETH_RXJUMBO,0xffff,0)
#define ETH_RXJUMBO_RXJUMBO_MASK                                   0x0000ffff
#define ETH_RXJUMBO_RXJUMBO_ALIGN                                  0
#define ETH_RXJUMBO_RXJUMBO_BITS                                   16
#define ETH_RXJUMBO_RXJUMBO_SHIFT                                  0


/****************************************************************************
 * ETH :: rxfrag
 ***************************************************************************/
/* ETH :: rxfrag :: reserved0 [31:16] */
#define ETH_RXFRAG_RESERVED0_MASK                                  0xffff0000
#define ETH_RXFRAG_RESERVED0_ALIGN                                 0
#define ETH_RXFRAG_RESERVED0_BITS                                  16
#define ETH_RXFRAG_RESERVED0_SHIFT                                 16

/* ETH :: rxfrag :: rxfrag [15:00] */
#define Wr_ETH_rxfrag_rxfrag(x) WriteRegBits(ETH_RXFRAG,0xffff,0,x)
#define Rd_ETH_rxfrag_rxfrag(x) ReadRegBits(ETH_RXFRAG,0xffff,0)
#define ETH_RXFRAG_RXFRAG_MASK                                     0x0000ffff
#define ETH_RXFRAG_RXFRAG_ALIGN                                    0
#define ETH_RXFRAG_RXFRAG_BITS                                     16
#define ETH_RXFRAG_RXFRAG_SHIFT                                    0


/****************************************************************************
 * ETH :: rxoverrun
 ***************************************************************************/
/* ETH :: rxoverrun :: reserved0 [31:16] */
#define ETH_RXOVERRUN_RESERVED0_MASK                               0xffff0000
#define ETH_RXOVERRUN_RESERVED0_ALIGN                              0
#define ETH_RXOVERRUN_RESERVED0_BITS                               16
#define ETH_RXOVERRUN_RESERVED0_SHIFT                              16

/* ETH :: rxoverrun :: rxoverrun [15:00] */
#define Wr_ETH_rxoverrun_rxoverrun(x) WriteRegBits(ETH_RXOVERRUN,0xffff,0,x)
#define Rd_ETH_rxoverrun_rxoverrun(x) ReadRegBits(ETH_RXOVERRUN,0xffff,0)
#define ETH_RXOVERRUN_RXOVERRUN_MASK                               0x0000ffff
#define ETH_RXOVERRUN_RXOVERRUN_ALIGN                              0
#define ETH_RXOVERRUN_RXOVERRUN_BITS                               16
#define ETH_RXOVERRUN_RXOVERRUN_SHIFT                              0


/****************************************************************************
 * ETH :: rxcrcalign
 ***************************************************************************/
/* ETH :: rxcrcalign :: reserved0 [31:16] */
#define ETH_RXCRCALIGN_RESERVED0_MASK                              0xffff0000
#define ETH_RXCRCALIGN_RESERVED0_ALIGN                             0
#define ETH_RXCRCALIGN_RESERVED0_BITS                              16
#define ETH_RXCRCALIGN_RESERVED0_SHIFT                             16

/* ETH :: rxcrcalign :: rxcrcalign [15:00] */
#define Wr_ETH_rxcrcalign_rxcrcalign(x) WriteRegBits(ETH_RXCRCALIGN,0xffff,0,x)
#define Rd_ETH_rxcrcalign_rxcrcalign(x) ReadRegBits(ETH_RXCRCALIGN,0xffff,0)
#define ETH_RXCRCALIGN_RXCRCALIGN_MASK                             0x0000ffff
#define ETH_RXCRCALIGN_RXCRCALIGN_ALIGN                            0
#define ETH_RXCRCALIGN_RXCRCALIGN_BITS                             16
#define ETH_RXCRCALIGN_RXCRCALIGN_SHIFT                            0


/****************************************************************************
 * ETH :: rxusize
 ***************************************************************************/
/* ETH :: rxusize :: reserved0 [31:16] */
#define ETH_RXUSIZE_RESERVED0_MASK                                 0xffff0000
#define ETH_RXUSIZE_RESERVED0_ALIGN                                0
#define ETH_RXUSIZE_RESERVED0_BITS                                 16
#define ETH_RXUSIZE_RESERVED0_SHIFT                                16

/* ETH :: rxusize :: rxusize [15:00] */
#define Wr_ETH_rxusize_rxusize(x) WriteRegBits(ETH_RXUSIZE,0xffff,0,x)
#define Rd_ETH_rxusize_rxusize(x) ReadRegBits(ETH_RXUSIZE,0xffff,0)
#define ETH_RXUSIZE_RXUSIZE_MASK                                   0x0000ffff
#define ETH_RXUSIZE_RXUSIZE_ALIGN                                  0
#define ETH_RXUSIZE_RXUSIZE_BITS                                   16
#define ETH_RXUSIZE_RXUSIZE_SHIFT                                  0


/****************************************************************************
 * ETH :: rxcrc
 ***************************************************************************/
/* ETH :: rxcrc :: reserved0 [31:16] */
#define ETH_RXCRC_RESERVED0_MASK                                   0xffff0000
#define ETH_RXCRC_RESERVED0_ALIGN                                  0
#define ETH_RXCRC_RESERVED0_BITS                                   16
#define ETH_RXCRC_RESERVED0_SHIFT                                  16

/* ETH :: rxcrc :: rxcrc [15:00] */
#define Wr_ETH_rxcrc_rxcrc(x) WriteRegBits(ETH_RXCRC,0xffff,0,x)
#define Rd_ETH_rxcrc_rxcrc(x) ReadRegBits(ETH_RXCRC,0xffff,0)
#define ETH_RXCRC_RXCRC_MASK                                       0x0000ffff
#define ETH_RXCRC_RXCRC_ALIGN                                      0
#define ETH_RXCRC_RXCRC_BITS                                       16
#define ETH_RXCRC_RXCRC_SHIFT                                      0


/****************************************************************************
 * ETH :: rxalign
 ***************************************************************************/
/* ETH :: rxalign :: reserved0 [31:16] */
#define ETH_RXALIGN_RESERVED0_MASK                                 0xffff0000
#define ETH_RXALIGN_RESERVED0_ALIGN                                0
#define ETH_RXALIGN_RESERVED0_BITS                                 16
#define ETH_RXALIGN_RESERVED0_SHIFT                                16

/* ETH :: rxalign :: rxalign [15:00] */
#define Wr_ETH_rxalign_rxalign(x) WriteRegBits(ETH_RXALIGN,0xffff,0,x)
#define Rd_ETH_rxalign_rxalign(x) ReadRegBits(ETH_RXALIGN,0xffff,0)
#define ETH_RXALIGN_RXALIGN_MASK                                   0x0000ffff
#define ETH_RXALIGN_RXALIGN_ALIGN                                  0
#define ETH_RXALIGN_RXALIGN_BITS                                   16
#define ETH_RXALIGN_RXALIGN_SHIFT                                  0


/****************************************************************************
 * ETH :: rxcderr
 ***************************************************************************/
/* ETH :: rxcderr :: reserved0 [31:16] */
#define ETH_RXCDERR_RESERVED0_MASK                                 0xffff0000
#define ETH_RXCDERR_RESERVED0_ALIGN                                0
#define ETH_RXCDERR_RESERVED0_BITS                                 16
#define ETH_RXCDERR_RESERVED0_SHIFT                                16

/* ETH :: rxcderr :: rxcderr [15:00] */
#define Wr_ETH_rxcderr_rxcderr(x) WriteRegBits(ETH_RXCDERR,0xffff,0,x)
#define Rd_ETH_rxcderr_rxcderr(x) ReadRegBits(ETH_RXCDERR,0xffff,0)
#define ETH_RXCDERR_RXCDERR_MASK                                   0x0000ffff
#define ETH_RXCDERR_RXCDERR_ALIGN                                  0
#define ETH_RXCDERR_RXCDERR_BITS                                   16
#define ETH_RXCDERR_RXCDERR_SHIFT                                  0


/****************************************************************************
 * ETH :: rxpause
 ***************************************************************************/
/* ETH :: rxpause :: reserved0 [31:16] */
#define ETH_RXPAUSE_RESERVED0_MASK                                 0xffff0000
#define ETH_RXPAUSE_RESERVED0_ALIGN                                0
#define ETH_RXPAUSE_RESERVED0_BITS                                 16
#define ETH_RXPAUSE_RESERVED0_SHIFT                                16

/* ETH :: rxpause :: rxpause [15:00] */
#define Wr_ETH_rxpause_rxpause(x) WriteRegBits(ETH_RXPAUSE,0xffff,0,x)
#define Rd_ETH_rxpause_rxpause(x) ReadRegBits(ETH_RXPAUSE,0xffff,0)
#define ETH_RXPAUSE_RXPAUSE_MASK                                   0x0000ffff
#define ETH_RXPAUSE_RXPAUSE_ALIGN                                  0
#define ETH_RXPAUSE_RXPAUSE_BITS                                   16
#define ETH_RXPAUSE_RXPAUSE_SHIFT                                  0


/****************************************************************************
 * ETH :: rxctrlfm
 ***************************************************************************/
/* ETH :: rxctrlfm :: reserved0 [31:16] */
#define ETH_RXCTRLFM_RESERVED0_MASK                                0xffff0000
#define ETH_RXCTRLFM_RESERVED0_ALIGN                               0
#define ETH_RXCTRLFM_RESERVED0_BITS                                16
#define ETH_RXCTRLFM_RESERVED0_SHIFT                               16

/* ETH :: rxctrlfm :: rxctrlfm [15:00] */
#define Wr_ETH_rxctrlfm_rxctrlfm(x) WriteRegBits(ETH_RXCTRLFM,0xffff,0,x)
#define Rd_ETH_rxctrlfm_rxctrlfm(x) ReadRegBits(ETH_RXCTRLFM,0xffff,0)
#define ETH_RXCTRLFM_RXCTRLFM_MASK                                 0x0000ffff
#define ETH_RXCTRLFM_RXCTRLFM_ALIGN                                0
#define ETH_RXCTRLFM_RXCTRLFM_BITS                                 16
#define ETH_RXCTRLFM_RXCTRLFM_SHIFT                                0


/****************************************************************************
 * ETH :: rxcntof
 ***************************************************************************/
/* ETH :: rxcntof :: reserved0 [31:23] */
#define ETH_RXCNTOF_RESERVED0_MASK                                 0xff800000
#define ETH_RXCNTOF_RESERVED0_ALIGN                                0
#define ETH_RXCNTOF_RESERVED0_BITS                                 9
#define ETH_RXCNTOF_RESERVED0_SHIFT                                23

/* ETH :: rxcntof :: rxoctgood_of [22:22] */
#define Wr_ETH_rxcntof_rxoctgood_of(x) WriteRegBits(ETH_RXCNTOF,0x400000,22,x)
#define Rd_ETH_rxcntof_rxoctgood_of(x) ReadRegBits(ETH_RXCNTOF,0x400000,22)
#define ETH_RXCNTOF_RXOCTGOOD_OF_MASK                              0x00400000
#define ETH_RXCNTOF_RXOCTGOOD_OF_ALIGN                             0
#define ETH_RXCNTOF_RXOCTGOOD_OF_BITS                              1
#define ETH_RXCNTOF_RXOCTGOOD_OF_SHIFT                             22

/* ETH :: rxcntof :: rxfrmgood_of [21:21] */
#define Wr_ETH_rxcntof_rxfrmgood_of(x) WriteRegBits(ETH_RXCNTOF,0x200000,21,x)
#define Rd_ETH_rxcntof_rxfrmgood_of(x) ReadRegBits(ETH_RXCNTOF,0x200000,21)
#define ETH_RXCNTOF_RXFRMGOOD_OF_MASK                              0x00200000
#define ETH_RXCNTOF_RXFRMGOOD_OF_ALIGN                             0
#define ETH_RXCNTOF_RXFRMGOOD_OF_BITS                              1
#define ETH_RXCNTOF_RXFRMGOOD_OF_SHIFT                             21

/* ETH :: rxcntof :: rxocttotal_of [20:20] */
#define Wr_ETH_rxcntof_rxocttotal_of(x) WriteRegBits(ETH_RXCNTOF,0x100000,20,x)
#define Rd_ETH_rxcntof_rxocttotal_of(x) ReadRegBits(ETH_RXCNTOF,0x100000,20)
#define ETH_RXCNTOF_RXOCTTOTAL_OF_MASK                             0x00100000
#define ETH_RXCNTOF_RXOCTTOTAL_OF_ALIGN                            0
#define ETH_RXCNTOF_RXOCTTOTAL_OF_BITS                             1
#define ETH_RXCNTOF_RXOCTTOTAL_OF_SHIFT                            20

/* ETH :: rxcntof :: rxfrmtotal_of [19:19] */
#define Wr_ETH_rxcntof_rxfrmtotal_of(x) WriteRegBits(ETH_RXCNTOF,0x80000,19,x)
#define Rd_ETH_rxcntof_rxfrmtotal_of(x) ReadRegBits(ETH_RXCNTOF,0x80000,19)
#define ETH_RXCNTOF_RXFRMTOTAL_OF_MASK                             0x00080000
#define ETH_RXCNTOF_RXFRMTOTAL_OF_ALIGN                            0
#define ETH_RXCNTOF_RXFRMTOTAL_OF_BITS                             1
#define ETH_RXCNTOF_RXFRMTOTAL_OF_SHIFT                            19

/* ETH :: rxcntof :: rxbcastgood_of [18:18] */
#define Wr_ETH_rxcntof_rxbcastgood_of(x) WriteRegBits(ETH_RXCNTOF,0x40000,18,x)
#define Rd_ETH_rxcntof_rxbcastgood_of(x) ReadRegBits(ETH_RXCNTOF,0x40000,18)
#define ETH_RXCNTOF_RXBCASTGOOD_OF_MASK                            0x00040000
#define ETH_RXCNTOF_RXBCASTGOOD_OF_ALIGN                           0
#define ETH_RXCNTOF_RXBCASTGOOD_OF_BITS                            1
#define ETH_RXCNTOF_RXBCASTGOOD_OF_SHIFT                           18

/* ETH :: rxcntof :: rxmcastgood_of [17:17] */
#define Wr_ETH_rxcntof_rxmcastgood_of(x) WriteRegBits(ETH_RXCNTOF,0x20000,17,x)
#define Rd_ETH_rxcntof_rxmcastgood_of(x) ReadRegBits(ETH_RXCNTOF,0x20000,17)
#define ETH_RXCNTOF_RXMCASTGOOD_OF_MASK                            0x00020000
#define ETH_RXCNTOF_RXMCASTGOOD_OF_ALIGN                           0
#define ETH_RXCNTOF_RXMCASTGOOD_OF_BITS                            1
#define ETH_RXCNTOF_RXMCASTGOOD_OF_SHIFT                           17

/* ETH :: rxcntof :: rx64_of [16:16] */
#define Wr_ETH_rxcntof_rx64_of(x) WriteRegBits(ETH_RXCNTOF,0x10000,16,x)
#define Rd_ETH_rxcntof_rx64_of(x) ReadRegBits(ETH_RXCNTOF,0x10000,16)
#define ETH_RXCNTOF_RX64_OF_MASK                                   0x00010000
#define ETH_RXCNTOF_RX64_OF_ALIGN                                  0
#define ETH_RXCNTOF_RX64_OF_BITS                                   1
#define ETH_RXCNTOF_RX64_OF_SHIFT                                  16

/* ETH :: rxcntof :: rx65_127_of [15:15] */
#define Wr_ETH_rxcntof_rx65_127_of(x) WriteRegBits(ETH_RXCNTOF,0x8000,15,x)
#define Rd_ETH_rxcntof_rx65_127_of(x) ReadRegBits(ETH_RXCNTOF,0x8000,15)
#define ETH_RXCNTOF_RX65_127_OF_MASK                               0x00008000
#define ETH_RXCNTOF_RX65_127_OF_ALIGN                              0
#define ETH_RXCNTOF_RX65_127_OF_BITS                               1
#define ETH_RXCNTOF_RX65_127_OF_SHIFT                              15

/* ETH :: rxcntof :: rx128_255_of [14:14] */
#define Wr_ETH_rxcntof_rx128_255_of(x) WriteRegBits(ETH_RXCNTOF,0x4000,14,x)
#define Rd_ETH_rxcntof_rx128_255_of(x) ReadRegBits(ETH_RXCNTOF,0x4000,14)
#define ETH_RXCNTOF_RX128_255_OF_MASK                              0x00004000
#define ETH_RXCNTOF_RX128_255_OF_ALIGN                             0
#define ETH_RXCNTOF_RX128_255_OF_BITS                              1
#define ETH_RXCNTOF_RX128_255_OF_SHIFT                             14

/* ETH :: rxcntof :: rx256_511_of [13:13] */
#define Wr_ETH_rxcntof_rx256_511_of(x) WriteRegBits(ETH_RXCNTOF,0x2000,13,x)
#define Rd_ETH_rxcntof_rx256_511_of(x) ReadRegBits(ETH_RXCNTOF,0x2000,13)
#define ETH_RXCNTOF_RX256_511_OF_MASK                              0x00002000
#define ETH_RXCNTOF_RX256_511_OF_ALIGN                             0
#define ETH_RXCNTOF_RX256_511_OF_BITS                              1
#define ETH_RXCNTOF_RX256_511_OF_SHIFT                             13

/* ETH :: rxcntof :: rx512_1023_of [12:12] */
#define Wr_ETH_rxcntof_rx512_1023_of(x) WriteRegBits(ETH_RXCNTOF,0x1000,12,x)
#define Rd_ETH_rxcntof_rx512_1023_of(x) ReadRegBits(ETH_RXCNTOF,0x1000,12)
#define ETH_RXCNTOF_RX512_1023_OF_MASK                             0x00001000
#define ETH_RXCNTOF_RX512_1023_OF_ALIGN                            0
#define ETH_RXCNTOF_RX512_1023_OF_BITS                             1
#define ETH_RXCNTOF_RX512_1023_OF_SHIFT                            12

/* ETH :: rxcntof :: rx1024_max_of [11:11] */
#define Wr_ETH_rxcntof_rx1024_max_of(x) WriteRegBits(ETH_RXCNTOF,0x800,11,x)
#define Rd_ETH_rxcntof_rx1024_max_of(x) ReadRegBits(ETH_RXCNTOF,0x800,11)
#define ETH_RXCNTOF_RX1024_MAX_OF_MASK                             0x00000800
#define ETH_RXCNTOF_RX1024_MAX_OF_ALIGN                            0
#define ETH_RXCNTOF_RX1024_MAX_OF_BITS                             1
#define ETH_RXCNTOF_RX1024_MAX_OF_SHIFT                            11

/* ETH :: rxcntof :: rxjabber_of [10:10] */
#define Wr_ETH_rxcntof_rxjabber_of(x) WriteRegBits(ETH_RXCNTOF,0x400,10,x)
#define Rd_ETH_rxcntof_rxjabber_of(x) ReadRegBits(ETH_RXCNTOF,0x400,10)
#define ETH_RXCNTOF_RXJABBER_OF_MASK                               0x00000400
#define ETH_RXCNTOF_RXJABBER_OF_ALIGN                              0
#define ETH_RXCNTOF_RXJABBER_OF_BITS                               1
#define ETH_RXCNTOF_RXJABBER_OF_SHIFT                              10

/* ETH :: rxcntof :: rxjumbo_of [09:09] */
#define Wr_ETH_rxcntof_rxjumbo_of(x) WriteRegBits(ETH_RXCNTOF,0x200,9,x)
#define Rd_ETH_rxcntof_rxjumbo_of(x) ReadRegBits(ETH_RXCNTOF,0x200,9)
#define ETH_RXCNTOF_RXJUMBO_OF_MASK                                0x00000200
#define ETH_RXCNTOF_RXJUMBO_OF_ALIGN                               0
#define ETH_RXCNTOF_RXJUMBO_OF_BITS                                1
#define ETH_RXCNTOF_RXJUMBO_OF_SHIFT                               9

/* ETH :: rxcntof :: rxfrag_of [08:08] */
#define Wr_ETH_rxcntof_rxfrag_of(x) WriteRegBits(ETH_RXCNTOF,0x100,8,x)
#define Rd_ETH_rxcntof_rxfrag_of(x) ReadRegBits(ETH_RXCNTOF,0x100,8)
#define ETH_RXCNTOF_RXFRAG_OF_MASK                                 0x00000100
#define ETH_RXCNTOF_RXFRAG_OF_ALIGN                                0
#define ETH_RXCNTOF_RXFRAG_OF_BITS                                 1
#define ETH_RXCNTOF_RXFRAG_OF_SHIFT                                8

/* ETH :: rxcntof :: rxoverrun_of [07:07] */
#define Wr_ETH_rxcntof_rxoverrun_of(x) WriteRegBits(ETH_RXCNTOF,0x80,7,x)
#define Rd_ETH_rxcntof_rxoverrun_of(x) ReadRegBits(ETH_RXCNTOF,0x80,7)
#define ETH_RXCNTOF_RXOVERRUN_OF_MASK                              0x00000080
#define ETH_RXCNTOF_RXOVERRUN_OF_ALIGN                             0
#define ETH_RXCNTOF_RXOVERRUN_OF_BITS                              1
#define ETH_RXCNTOF_RXOVERRUN_OF_SHIFT                             7

/* ETH :: rxcntof :: rxcrcalign_of [06:06] */
#define Wr_ETH_rxcntof_rxcrcalign_of(x) WriteRegBits(ETH_RXCNTOF,0x40,6,x)
#define Rd_ETH_rxcntof_rxcrcalign_of(x) ReadRegBits(ETH_RXCNTOF,0x40,6)
#define ETH_RXCNTOF_RXCRCALIGN_OF_MASK                             0x00000040
#define ETH_RXCNTOF_RXCRCALIGN_OF_ALIGN                            0
#define ETH_RXCNTOF_RXCRCALIGN_OF_BITS                             1
#define ETH_RXCNTOF_RXCRCALIGN_OF_SHIFT                            6

/* ETH :: rxcntof :: rxusize_of [05:05] */
#define Wr_ETH_rxcntof_rxusize_of(x) WriteRegBits(ETH_RXCNTOF,0x20,5,x)
#define Rd_ETH_rxcntof_rxusize_of(x) ReadRegBits(ETH_RXCNTOF,0x20,5)
#define ETH_RXCNTOF_RXUSIZE_OF_MASK                                0x00000020
#define ETH_RXCNTOF_RXUSIZE_OF_ALIGN                               0
#define ETH_RXCNTOF_RXUSIZE_OF_BITS                                1
#define ETH_RXCNTOF_RXUSIZE_OF_SHIFT                               5

/* ETH :: rxcntof :: rxcrc_of [04:04] */
#define Wr_ETH_rxcntof_rxcrc_of(x) WriteRegBits(ETH_RXCNTOF,0x10,4,x)
#define Rd_ETH_rxcntof_rxcrc_of(x) ReadRegBits(ETH_RXCNTOF,0x10,4)
#define ETH_RXCNTOF_RXCRC_OF_MASK                                  0x00000010
#define ETH_RXCNTOF_RXCRC_OF_ALIGN                                 0
#define ETH_RXCNTOF_RXCRC_OF_BITS                                  1
#define ETH_RXCNTOF_RXCRC_OF_SHIFT                                 4

/* ETH :: rxcntof :: rxalign_of [03:03] */
#define Wr_ETH_rxcntof_rxalign_of(x) WriteRegBits(ETH_RXCNTOF,0x8,3,x)
#define Rd_ETH_rxcntof_rxalign_of(x) ReadRegBits(ETH_RXCNTOF,0x8,3)
#define ETH_RXCNTOF_RXALIGN_OF_MASK                                0x00000008
#define ETH_RXCNTOF_RXALIGN_OF_ALIGN                               0
#define ETH_RXCNTOF_RXALIGN_OF_BITS                                1
#define ETH_RXCNTOF_RXALIGN_OF_SHIFT                               3

/* ETH :: rxcntof :: rxcderr_of [02:02] */
#define Wr_ETH_rxcntof_rxcderr_of(x) WriteRegBits(ETH_RXCNTOF,0x4,2,x)
#define Rd_ETH_rxcntof_rxcderr_of(x) ReadRegBits(ETH_RXCNTOF,0x4,2)
#define ETH_RXCNTOF_RXCDERR_OF_MASK                                0x00000004
#define ETH_RXCNTOF_RXCDERR_OF_ALIGN                               0
#define ETH_RXCNTOF_RXCDERR_OF_BITS                                1
#define ETH_RXCNTOF_RXCDERR_OF_SHIFT                               2

/* ETH :: rxcntof :: rxpausefm_of [01:01] */
#define Wr_ETH_rxcntof_rxpausefm_of(x) WriteRegBits(ETH_RXCNTOF,0x2,1,x)
#define Rd_ETH_rxcntof_rxpausefm_of(x) ReadRegBits(ETH_RXCNTOF,0x2,1)
#define ETH_RXCNTOF_RXPAUSEFM_OF_MASK                              0x00000002
#define ETH_RXCNTOF_RXPAUSEFM_OF_ALIGN                             0
#define ETH_RXCNTOF_RXPAUSEFM_OF_BITS                              1
#define ETH_RXCNTOF_RXPAUSEFM_OF_SHIFT                             1

/* ETH :: rxcntof :: rxctrlfm_of [00:00] */
#define Wr_ETH_rxcntof_rxctrlfm_of(x) WriteRegBits(ETH_RXCNTOF,0x1,0,x)
#define Rd_ETH_rxcntof_rxctrlfm_of(x) ReadRegBits(ETH_RXCNTOF,0x1,0)
#define ETH_RXCNTOF_RXCTRLFM_OF_MASK                               0x00000001
#define ETH_RXCNTOF_RXCTRLFM_OF_ALIGN                              0
#define ETH_RXCNTOF_RXCTRLFM_OF_BITS                               1
#define ETH_RXCNTOF_RXCTRLFM_OF_SHIFT                              0


/****************************************************************************
 * bcm89530_sys_cfg_QSPI
 ***************************************************************************/
/****************************************************************************
 * QSPI :: bspi_registers_REVISION_ID
 ***************************************************************************/
/* QSPI :: bspi_registers_REVISION_ID :: bspi_registers_REVISION_ID_reserved [31:16] */
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_RESERVED_MASK 0xffff0000
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_RESERVED_BITS 16
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_RESERVED_SHIFT 16

/* QSPI :: bspi_registers_REVISION_ID :: bspi_registers_REVISION_ID_MAJOR [15:08] */
#define Wr_QSPI_bspi_registers_REVISION_ID_bspi_registers_REVISION_ID_MAJOR(x) WriteRegBits(QSPI_BSPI_REGISTERS_REVISION_ID,0xff00,8,x)
#define Rd_QSPI_bspi_registers_REVISION_ID_bspi_registers_REVISION_ID_MAJOR(x) ReadRegBits(QSPI_BSPI_REGISTERS_REVISION_ID,0xff00,8)
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_MAJOR_MASK 0x0000ff00
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_MAJOR_ALIGN 0
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_MAJOR_BITS 8
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_MAJOR_SHIFT 8

/* QSPI :: bspi_registers_REVISION_ID :: bspi_registers_REVISION_ID_MINOR [07:00] */
#define Wr_QSPI_bspi_registers_REVISION_ID_bspi_registers_REVISION_ID_MINOR(x) WriteRegBits(QSPI_BSPI_REGISTERS_REVISION_ID,0xff,0,x)
#define Rd_QSPI_bspi_registers_REVISION_ID_bspi_registers_REVISION_ID_MINOR(x) ReadRegBits(QSPI_BSPI_REGISTERS_REVISION_ID,0xff,0)
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_MINOR_MASK 0x000000ff
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_MINOR_ALIGN 0
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_MINOR_BITS 8
#define QSPI_BSPI_REGISTERS_REVISION_ID_BSPI_REGISTERS_REVISION_ID_MINOR_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_SCRATCH
 ***************************************************************************/
/* QSPI :: bspi_registers_SCRATCH :: bspi_registers_SCRATCH_SCRATCH [31:00] */
#define Wr_QSPI_bspi_registers_SCRATCH_bspi_registers_SCRATCH_SCRATCH(x) WriteReg(QSPI_BSPI_REGISTERS_SCRATCH,x)
#define Rd_QSPI_bspi_registers_SCRATCH_bspi_registers_SCRATCH_SCRATCH(x) ReadReg(QSPI_BSPI_REGISTERS_SCRATCH)
#define QSPI_BSPI_REGISTERS_SCRATCH_BSPI_REGISTERS_SCRATCH_SCRATCH_MASK 0xffffffff
#define QSPI_BSPI_REGISTERS_SCRATCH_BSPI_REGISTERS_SCRATCH_SCRATCH_ALIGN 0
#define QSPI_BSPI_REGISTERS_SCRATCH_BSPI_REGISTERS_SCRATCH_SCRATCH_BITS 32
#define QSPI_BSPI_REGISTERS_SCRATCH_BSPI_REGISTERS_SCRATCH_SCRATCH_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_MAST_N_BOOT_CTRL
 ***************************************************************************/
/* QSPI :: bspi_registers_MAST_N_BOOT_CTRL :: bspi_registers_MAST_N_BOOT_CTRL_reserved [31:01] */
#define QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BSPI_REGISTERS_MAST_N_BOOT_CTRL_RESERVED_MASK 0xfffffffe
#define QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BSPI_REGISTERS_MAST_N_BOOT_CTRL_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BSPI_REGISTERS_MAST_N_BOOT_CTRL_RESERVED_BITS 31
#define QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BSPI_REGISTERS_MAST_N_BOOT_CTRL_RESERVED_SHIFT 1

/* QSPI :: bspi_registers_MAST_N_BOOT_CTRL :: bspi_registers_MAST_N_BOOT_CTRL_mast_n_boot [00:00] */
#define Wr_QSPI_bspi_registers_MAST_N_BOOT_CTRL_bspi_registers_MAST_N_BOOT_CTRL_mast_n_boot(x) WriteRegBits(QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL,0x1,0,x)
#define Rd_QSPI_bspi_registers_MAST_N_BOOT_CTRL_bspi_registers_MAST_N_BOOT_CTRL_mast_n_boot(x) ReadRegBits(QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL,0x1,0)
#define QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BSPI_REGISTERS_MAST_N_BOOT_CTRL_MAST_N_BOOT_MASK 0x00000001
#define QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BSPI_REGISTERS_MAST_N_BOOT_CTRL_MAST_N_BOOT_ALIGN 0
#define QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BSPI_REGISTERS_MAST_N_BOOT_CTRL_MAST_N_BOOT_BITS 1
#define QSPI_BSPI_REGISTERS_MAST_N_BOOT_CTRL_BSPI_REGISTERS_MAST_N_BOOT_CTRL_MAST_N_BOOT_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_BUSY_STATUS
 ***************************************************************************/
/* QSPI :: bspi_registers_BUSY_STATUS :: bspi_registers_BUSY_STATUS_reserved [31:01] */
#define QSPI_BSPI_REGISTERS_BUSY_STATUS_BSPI_REGISTERS_BUSY_STATUS_RESERVED_MASK 0xfffffffe
#define QSPI_BSPI_REGISTERS_BUSY_STATUS_BSPI_REGISTERS_BUSY_STATUS_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_BUSY_STATUS_BSPI_REGISTERS_BUSY_STATUS_RESERVED_BITS 31
#define QSPI_BSPI_REGISTERS_BUSY_STATUS_BSPI_REGISTERS_BUSY_STATUS_RESERVED_SHIFT 1

/* QSPI :: bspi_registers_BUSY_STATUS :: bspi_registers_BUSY_STATUS_busy [00:00] */
#define Wr_QSPI_bspi_registers_BUSY_STATUS_bspi_registers_BUSY_STATUS_busy(x) WriteRegBits(QSPI_BSPI_REGISTERS_BUSY_STATUS,0x1,0,x)
#define Rd_QSPI_bspi_registers_BUSY_STATUS_bspi_registers_BUSY_STATUS_busy(x) ReadRegBits(QSPI_BSPI_REGISTERS_BUSY_STATUS,0x1,0)
#define QSPI_BSPI_REGISTERS_BUSY_STATUS_BSPI_REGISTERS_BUSY_STATUS_BUSY_MASK 0x00000001
#define QSPI_BSPI_REGISTERS_BUSY_STATUS_BSPI_REGISTERS_BUSY_STATUS_BUSY_ALIGN 0
#define QSPI_BSPI_REGISTERS_BUSY_STATUS_BSPI_REGISTERS_BUSY_STATUS_BUSY_BITS 1
#define QSPI_BSPI_REGISTERS_BUSY_STATUS_BSPI_REGISTERS_BUSY_STATUS_BUSY_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_INTR_STATUS
 ***************************************************************************/
/* QSPI :: bspi_registers_INTR_STATUS :: bspi_registers_INTR_STATUS_reserved [31:02] */
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_RESERVED_MASK 0xfffffffc
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_RESERVED_BITS 30
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_RESERVED_SHIFT 2

/* QSPI :: bspi_registers_INTR_STATUS :: bspi_registers_INTR_STATUS_intr_1 [01:01] */
#define Wr_QSPI_bspi_registers_INTR_STATUS_bspi_registers_INTR_STATUS_intr_1(x) WriteRegBits(QSPI_BSPI_REGISTERS_INTR_STATUS,0x2,1,x)
#define Rd_QSPI_bspi_registers_INTR_STATUS_bspi_registers_INTR_STATUS_intr_1(x) ReadRegBits(QSPI_BSPI_REGISTERS_INTR_STATUS,0x2,1)
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_INTR_1_MASK 0x00000002
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_INTR_1_ALIGN 0
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_INTR_1_BITS 1
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_INTR_1_SHIFT 1

/* QSPI :: bspi_registers_INTR_STATUS :: bspi_registers_INTR_STATUS_intr_0 [00:00] */
#define Wr_QSPI_bspi_registers_INTR_STATUS_bspi_registers_INTR_STATUS_intr_0(x) WriteRegBits(QSPI_BSPI_REGISTERS_INTR_STATUS,0x1,0,x)
#define Rd_QSPI_bspi_registers_INTR_STATUS_bspi_registers_INTR_STATUS_intr_0(x) ReadRegBits(QSPI_BSPI_REGISTERS_INTR_STATUS,0x1,0)
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_INTR_0_MASK 0x00000001
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_INTR_0_ALIGN 0
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_INTR_0_BITS 1
#define QSPI_BSPI_REGISTERS_INTR_STATUS_BSPI_REGISTERS_INTR_STATUS_INTR_0_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_B0_STATUS
 ***************************************************************************/
/* QSPI :: bspi_registers_B0_STATUS :: bspi_registers_B0_STATUS_reserved [31:31] */
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_RESERVED_MASK 0x80000000
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_RESERVED_BITS 1
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_RESERVED_SHIFT 31

/* QSPI :: bspi_registers_B0_STATUS :: bspi_registers_B0_STATUS_b0_prefetch_active [30:30] */
#define Wr_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_prefetch_active(x) WriteRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x40000000,30,x)
#define Rd_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_prefetch_active(x) ReadRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x40000000,30)
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_PREFETCH_ACTIVE_MASK 0x40000000
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_PREFETCH_ACTIVE_ALIGN 0
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_PREFETCH_ACTIVE_BITS 1
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_PREFETCH_ACTIVE_SHIFT 30

/* QSPI :: bspi_registers_B0_STATUS :: bspi_registers_B0_STATUS_b0_full [29:29] */
#define Wr_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_full(x) WriteRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x20000000,29,x)
#define Rd_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_full(x) ReadRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x20000000,29)
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_FULL_MASK 0x20000000
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_FULL_ALIGN 0
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_FULL_BITS 1
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_FULL_SHIFT 29

/* QSPI :: bspi_registers_B0_STATUS :: bspi_registers_B0_STATUS_b0_empty [28:28] */
#define Wr_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_empty(x) WriteRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x10000000,28,x)
#define Rd_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_empty(x) ReadRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x10000000,28)
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_EMPTY_MASK 0x10000000
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_EMPTY_ALIGN 0
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_EMPTY_BITS 1
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_EMPTY_SHIFT 28

/* QSPI :: bspi_registers_B0_STATUS :: bspi_registers_B0_STATUS_b0_miss [27:27] */
#define Wr_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_miss(x) WriteRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x8000000,27,x)
#define Rd_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_miss(x) ReadRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x8000000,27)
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_MISS_MASK 0x08000000
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_MISS_ALIGN 0
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_MISS_BITS 1
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_MISS_SHIFT 27

/* QSPI :: bspi_registers_B0_STATUS :: bspi_registers_B0_STATUS_b0_hit [26:26] */
#define Wr_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_hit(x) WriteRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x4000000,26,x)
#define Rd_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_hit(x) ReadRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x4000000,26)
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_HIT_MASK 0x04000000
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_HIT_ALIGN 0
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_HIT_BITS 1
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_HIT_SHIFT 26

/* QSPI :: bspi_registers_B0_STATUS :: bspi_registers_B0_STATUS_b0_address [25:00] */
#define Wr_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_address(x) WriteRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x3ffffff,0,x)
#define Rd_QSPI_bspi_registers_B0_STATUS_bspi_registers_B0_STATUS_b0_address(x) ReadRegBits(QSPI_BSPI_REGISTERS_B0_STATUS,0x3ffffff,0)
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_ADDRESS_MASK 0x03ffffff
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_ADDRESS_ALIGN 0
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_ADDRESS_BITS 26
#define QSPI_BSPI_REGISTERS_B0_STATUS_BSPI_REGISTERS_B0_STATUS_B0_ADDRESS_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_B0_CTRL
 ***************************************************************************/
/* QSPI :: bspi_registers_B0_CTRL :: bspi_registers_B0_CTRL_reserved [31:01] */
#define QSPI_BSPI_REGISTERS_B0_CTRL_BSPI_REGISTERS_B0_CTRL_RESERVED_MASK 0xfffffffe
#define QSPI_BSPI_REGISTERS_B0_CTRL_BSPI_REGISTERS_B0_CTRL_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_B0_CTRL_BSPI_REGISTERS_B0_CTRL_RESERVED_BITS 31
#define QSPI_BSPI_REGISTERS_B0_CTRL_BSPI_REGISTERS_B0_CTRL_RESERVED_SHIFT 1

/* QSPI :: bspi_registers_B0_CTRL :: bspi_registers_B0_CTRL_b0_flush [00:00] */
#define Wr_QSPI_bspi_registers_B0_CTRL_bspi_registers_B0_CTRL_b0_flush(x) WriteRegBits(QSPI_BSPI_REGISTERS_B0_CTRL,0x1,0,x)
#define Rd_QSPI_bspi_registers_B0_CTRL_bspi_registers_B0_CTRL_b0_flush(x) ReadRegBits(QSPI_BSPI_REGISTERS_B0_CTRL,0x1,0)
#define QSPI_BSPI_REGISTERS_B0_CTRL_BSPI_REGISTERS_B0_CTRL_B0_FLUSH_MASK 0x00000001
#define QSPI_BSPI_REGISTERS_B0_CTRL_BSPI_REGISTERS_B0_CTRL_B0_FLUSH_ALIGN 0
#define QSPI_BSPI_REGISTERS_B0_CTRL_BSPI_REGISTERS_B0_CTRL_B0_FLUSH_BITS 1
#define QSPI_BSPI_REGISTERS_B0_CTRL_BSPI_REGISTERS_B0_CTRL_B0_FLUSH_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_B1_STATUS
 ***************************************************************************/
/* QSPI :: bspi_registers_B1_STATUS :: bspi_registers_B1_STATUS_reserved [31:31] */
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_RESERVED_MASK 0x80000000
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_RESERVED_BITS 1
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_RESERVED_SHIFT 31

/* QSPI :: bspi_registers_B1_STATUS :: bspi_registers_B1_STATUS_b1_prefetch_active [30:30] */
#define Wr_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_prefetch_active(x) WriteRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x40000000,30,x)
#define Rd_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_prefetch_active(x) ReadRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x40000000,30)
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_PREFETCH_ACTIVE_MASK 0x40000000
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_PREFETCH_ACTIVE_ALIGN 0
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_PREFETCH_ACTIVE_BITS 1
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_PREFETCH_ACTIVE_SHIFT 30

/* QSPI :: bspi_registers_B1_STATUS :: bspi_registers_B1_STATUS_b1_full [29:29] */
#define Wr_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_full(x) WriteRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x20000000,29,x)
#define Rd_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_full(x) ReadRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x20000000,29)
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_FULL_MASK 0x20000000
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_FULL_ALIGN 0
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_FULL_BITS 1
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_FULL_SHIFT 29

/* QSPI :: bspi_registers_B1_STATUS :: bspi_registers_B1_STATUS_b1_empty [28:28] */
#define Wr_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_empty(x) WriteRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x10000000,28,x)
#define Rd_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_empty(x) ReadRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x10000000,28)
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_EMPTY_MASK 0x10000000
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_EMPTY_ALIGN 0
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_EMPTY_BITS 1
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_EMPTY_SHIFT 28

/* QSPI :: bspi_registers_B1_STATUS :: bspi_registers_B1_STATUS_b1_miss [27:27] */
#define Wr_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_miss(x) WriteRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x8000000,27,x)
#define Rd_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_miss(x) ReadRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x8000000,27)
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_MISS_MASK 0x08000000
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_MISS_ALIGN 0
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_MISS_BITS 1
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_MISS_SHIFT 27

/* QSPI :: bspi_registers_B1_STATUS :: bspi_registers_B1_STATUS_b1_hit [26:26] */
#define Wr_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_hit(x) WriteRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x4000000,26,x)
#define Rd_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_hit(x) ReadRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x4000000,26)
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_HIT_MASK 0x04000000
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_HIT_ALIGN 0
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_HIT_BITS 1
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_HIT_SHIFT 26

/* QSPI :: bspi_registers_B1_STATUS :: bspi_registers_B1_STATUS_b1_address [25:00] */
#define Wr_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_address(x) WriteRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x3ffffff,0,x)
#define Rd_QSPI_bspi_registers_B1_STATUS_bspi_registers_B1_STATUS_b1_address(x) ReadRegBits(QSPI_BSPI_REGISTERS_B1_STATUS,0x3ffffff,0)
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_ADDRESS_MASK 0x03ffffff
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_ADDRESS_ALIGN 0
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_ADDRESS_BITS 26
#define QSPI_BSPI_REGISTERS_B1_STATUS_BSPI_REGISTERS_B1_STATUS_B1_ADDRESS_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_B1_CTRL
 ***************************************************************************/
/* QSPI :: bspi_registers_B1_CTRL :: bspi_registers_B1_CTRL_reserved [31:01] */
#define QSPI_BSPI_REGISTERS_B1_CTRL_BSPI_REGISTERS_B1_CTRL_RESERVED_MASK 0xfffffffe
#define QSPI_BSPI_REGISTERS_B1_CTRL_BSPI_REGISTERS_B1_CTRL_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_B1_CTRL_BSPI_REGISTERS_B1_CTRL_RESERVED_BITS 31
#define QSPI_BSPI_REGISTERS_B1_CTRL_BSPI_REGISTERS_B1_CTRL_RESERVED_SHIFT 1

/* QSPI :: bspi_registers_B1_CTRL :: bspi_registers_B1_CTRL_b1_flush [00:00] */
#define Wr_QSPI_bspi_registers_B1_CTRL_bspi_registers_B1_CTRL_b1_flush(x) WriteRegBits(QSPI_BSPI_REGISTERS_B1_CTRL,0x1,0,x)
#define Rd_QSPI_bspi_registers_B1_CTRL_bspi_registers_B1_CTRL_b1_flush(x) ReadRegBits(QSPI_BSPI_REGISTERS_B1_CTRL,0x1,0)
#define QSPI_BSPI_REGISTERS_B1_CTRL_BSPI_REGISTERS_B1_CTRL_B1_FLUSH_MASK 0x00000001
#define QSPI_BSPI_REGISTERS_B1_CTRL_BSPI_REGISTERS_B1_CTRL_B1_FLUSH_ALIGN 0
#define QSPI_BSPI_REGISTERS_B1_CTRL_BSPI_REGISTERS_B1_CTRL_B1_FLUSH_BITS 1
#define QSPI_BSPI_REGISTERS_B1_CTRL_BSPI_REGISTERS_B1_CTRL_B1_FLUSH_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_STRAP_OVERRIDE_CTRL
 ***************************************************************************/
/* QSPI :: bspi_registers_STRAP_OVERRIDE_CTRL :: bspi_registers_STRAP_OVERRIDE_CTRL_reserved [31:05] */
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_RESERVED_MASK 0xffffffe0
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_RESERVED_BITS 27
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_RESERVED_SHIFT 5

/* QSPI :: bspi_registers_STRAP_OVERRIDE_CTRL :: bspi_registers_STRAP_OVERRIDE_CTRL_endian_mode [04:04] */
#define Wr_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_endian_mode(x) WriteRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x10,4,x)
#define Rd_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_endian_mode(x) ReadRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x10,4)
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_ENDIAN_MODE_MASK 0x00000010
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_ENDIAN_MODE_ALIGN 0
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_ENDIAN_MODE_BITS 1
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_ENDIAN_MODE_SHIFT 4

/* QSPI :: bspi_registers_STRAP_OVERRIDE_CTRL :: bspi_registers_STRAP_OVERRIDE_CTRL_data_quad [03:03] */
#define Wr_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_data_quad(x) WriteRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x8,3,x)
#define Rd_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_data_quad(x) ReadRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x8,3)
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_DATA_QUAD_MASK 0x00000008
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_DATA_QUAD_ALIGN 0
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_DATA_QUAD_BITS 1
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_DATA_QUAD_SHIFT 3

/* QSPI :: bspi_registers_STRAP_OVERRIDE_CTRL :: bspi_registers_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte [02:02] */
#define Wr_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte(x) WriteRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x4,2,x)
#define Rd_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_addr_4byte_n_3byte(x) ReadRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x4,2)
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_ADDR_4BYTE_N_3BYTE_MASK 0x00000004
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_ADDR_4BYTE_N_3BYTE_ALIGN 0
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_ADDR_4BYTE_N_3BYTE_BITS 1
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_ADDR_4BYTE_N_3BYTE_SHIFT 2

/* QSPI :: bspi_registers_STRAP_OVERRIDE_CTRL :: bspi_registers_STRAP_OVERRIDE_CTRL_data_dual_n_sgl [01:01] */
#define Wr_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_data_dual_n_sgl(x) WriteRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x2,1,x)
#define Rd_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_data_dual_n_sgl(x) ReadRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x2,1)
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_DATA_DUAL_N_SGL_MASK 0x00000002
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_DATA_DUAL_N_SGL_ALIGN 0
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_DATA_DUAL_N_SGL_BITS 1
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_DATA_DUAL_N_SGL_SHIFT 1

/* QSPI :: bspi_registers_STRAP_OVERRIDE_CTRL :: bspi_registers_STRAP_OVERRIDE_CTRL_override [00:00] */
#define Wr_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_override(x) WriteRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x1,0,x)
#define Rd_QSPI_bspi_registers_STRAP_OVERRIDE_CTRL_bspi_registers_STRAP_OVERRIDE_CTRL_override(x) ReadRegBits(QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL,0x1,0)
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_OVERRIDE_MASK 0x00000001
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_OVERRIDE_ALIGN 0
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_OVERRIDE_BITS 1
#define QSPI_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_BSPI_REGISTERS_STRAP_OVERRIDE_CTRL_OVERRIDE_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_FLEX_MODE_ENABLE
 ***************************************************************************/
/* QSPI :: bspi_registers_FLEX_MODE_ENABLE :: bspi_registers_FLEX_MODE_ENABLE_reserved [31:01] */
#define QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_REGISTERS_FLEX_MODE_ENABLE_RESERVED_MASK 0xfffffffe
#define QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_REGISTERS_FLEX_MODE_ENABLE_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_REGISTERS_FLEX_MODE_ENABLE_RESERVED_BITS 31
#define QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_REGISTERS_FLEX_MODE_ENABLE_RESERVED_SHIFT 1

/* QSPI :: bspi_registers_FLEX_MODE_ENABLE :: bspi_registers_FLEX_MODE_ENABLE_bspi_flex_mode_enable [00:00] */
#define Wr_QSPI_bspi_registers_FLEX_MODE_ENABLE_bspi_registers_FLEX_MODE_ENABLE_bspi_flex_mode_enable(x) WriteRegBits(QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE,0x1,0,x)
#define Rd_QSPI_bspi_registers_FLEX_MODE_ENABLE_bspi_registers_FLEX_MODE_ENABLE_bspi_flex_mode_enable(x) ReadRegBits(QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE,0x1,0)
#define QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_FLEX_MODE_ENABLE_MASK 0x00000001
#define QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_FLEX_MODE_ENABLE_ALIGN 0
#define QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_FLEX_MODE_ENABLE_BITS 1
#define QSPI_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_REGISTERS_FLEX_MODE_ENABLE_BSPI_FLEX_MODE_ENABLE_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_BITS_PER_CYCLE
 ***************************************************************************/
/* QSPI :: bspi_registers_BITS_PER_CYCLE :: bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_RSVD_5 [31:26] */
#define Wr_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_RSVD_5(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0xfc000000,26,x)
#define Rd_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_RSVD_5(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0xfc000000,26)
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_5_MASK 0xfc000000
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_5_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_5_BITS 6
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_5_SHIFT 26

/* QSPI :: bspi_registers_BITS_PER_CYCLE :: bspi_registers_BITS_PER_CYCLE_cmd_bpc_select [25:24] */
#define Wr_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_cmd_bpc_select(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0x3000000,24,x)
#define Rd_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_cmd_bpc_select(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0x3000000,24)
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_CMD_BPC_SELECT_MASK 0x03000000
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_CMD_BPC_SELECT_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_CMD_BPC_SELECT_BITS 2
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_CMD_BPC_SELECT_SHIFT 24

/* QSPI :: bspi_registers_BITS_PER_CYCLE :: bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_RSVD_4 [23:18] */
#define Wr_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_RSVD_4(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0xfc0000,18,x)
#define Rd_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_RSVD_4(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0xfc0000,18)
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_4_MASK 0x00fc0000
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_4_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_4_BITS 6
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_4_SHIFT 18

/* QSPI :: bspi_registers_BITS_PER_CYCLE :: bspi_registers_BITS_PER_CYCLE_addr_bpc_select [17:16] */
#define Wr_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_addr_bpc_select(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0x30000,16,x)
#define Rd_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_addr_bpc_select(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0x30000,16)
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_ADDR_BPC_SELECT_MASK 0x00030000
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_ADDR_BPC_SELECT_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_ADDR_BPC_SELECT_BITS 2
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_ADDR_BPC_SELECT_SHIFT 16

/* QSPI :: bspi_registers_BITS_PER_CYCLE :: bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_RSVD_3 [15:10] */
#define Wr_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_RSVD_3(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0xfc00,10,x)
#define Rd_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_RSVD_3(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0xfc00,10)
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_3_MASK 0x0000fc00
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_3_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_3_BITS 6
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RSVD_3_SHIFT 10

/* QSPI :: bspi_registers_BITS_PER_CYCLE :: bspi_registers_BITS_PER_CYCLE_mode_bpc_select [09:08] */
#define Wr_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_mode_bpc_select(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0x300,8,x)
#define Rd_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_mode_bpc_select(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0x300,8)
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_MODE_BPC_SELECT_MASK 0x00000300
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_MODE_BPC_SELECT_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_MODE_BPC_SELECT_BITS 2
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_MODE_BPC_SELECT_SHIFT 8

/* QSPI :: bspi_registers_BITS_PER_CYCLE :: bspi_registers_BITS_PER_CYCLE_reserved [07:02] */
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RESERVED_MASK 0x000000fc
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RESERVED_BITS 6
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_RESERVED_SHIFT 2

/* QSPI :: bspi_registers_BITS_PER_CYCLE :: bspi_registers_BITS_PER_CYCLE_data_bpc_select [01:00] */
#define Wr_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_data_bpc_select(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0x3,0,x)
#define Rd_QSPI_bspi_registers_BITS_PER_CYCLE_bspi_registers_BITS_PER_CYCLE_data_bpc_select(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_CYCLE,0x3,0)
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_DATA_BPC_SELECT_MASK 0x00000003
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_DATA_BPC_SELECT_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_DATA_BPC_SELECT_BITS 2
#define QSPI_BSPI_REGISTERS_BITS_PER_CYCLE_BSPI_REGISTERS_BITS_PER_CYCLE_DATA_BPC_SELECT_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_BITS_PER_PHASE
 ***************************************************************************/
/* QSPI :: bspi_registers_BITS_PER_PHASE :: bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_RSVD_5 [31:25] */
#define Wr_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_RSVD_5(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0xfe000000,25,x)
#define Rd_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_RSVD_5(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0xfe000000,25)
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RSVD_5_MASK 0xfe000000
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RSVD_5_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RSVD_5_BITS 7
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RSVD_5_SHIFT 25

/* QSPI :: bspi_registers_BITS_PER_PHASE :: bspi_registers_BITS_PER_PHASE_cmd_bpp_select [24:24] */
#define Wr_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_cmd_bpp_select(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0x1000000,24,x)
#define Rd_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_cmd_bpp_select(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0x1000000,24)
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_CMD_BPP_SELECT_MASK 0x01000000
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_CMD_BPP_SELECT_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_CMD_BPP_SELECT_BITS 1
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_CMD_BPP_SELECT_SHIFT 24

/* QSPI :: bspi_registers_BITS_PER_PHASE :: bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_RSVD_4 [23:17] */
#define Wr_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_RSVD_4(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0xfe0000,17,x)
#define Rd_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_RSVD_4(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0xfe0000,17)
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RSVD_4_MASK 0x00fe0000
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RSVD_4_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RSVD_4_BITS 7
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RSVD_4_SHIFT 17

/* QSPI :: bspi_registers_BITS_PER_PHASE :: bspi_registers_BITS_PER_PHASE_addr_bpp_select [16:16] */
#define Wr_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_addr_bpp_select(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0x10000,16,x)
#define Rd_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_addr_bpp_select(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0x10000,16)
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_ADDR_BPP_SELECT_MASK 0x00010000
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_ADDR_BPP_SELECT_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_ADDR_BPP_SELECT_BITS 1
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_ADDR_BPP_SELECT_SHIFT 16

/* QSPI :: bspi_registers_BITS_PER_PHASE :: bspi_registers_BITS_PER_PHASE_reserved [15:09] */
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RESERVED_MASK 0x0000fe00
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RESERVED_BITS 7
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_RESERVED_SHIFT 9

/* QSPI :: bspi_registers_BITS_PER_PHASE :: bspi_registers_BITS_PER_PHASE_mode_bpp [08:08] */
#define Wr_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_mode_bpp(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0x100,8,x)
#define Rd_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_mode_bpp(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0x100,8)
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_MODE_BPP_MASK 0x00000100
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_MODE_BPP_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_MODE_BPP_BITS 1
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_MODE_BPP_SHIFT 8

/* QSPI :: bspi_registers_BITS_PER_PHASE :: bspi_registers_BITS_PER_PHASE_dummy_cycles [07:00] */
#define Wr_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_dummy_cycles(x) WriteRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0xff,0,x)
#define Rd_QSPI_bspi_registers_BITS_PER_PHASE_bspi_registers_BITS_PER_PHASE_dummy_cycles(x) ReadRegBits(QSPI_BSPI_REGISTERS_BITS_PER_PHASE,0xff,0)
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_DUMMY_CYCLES_MASK 0x000000ff
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_DUMMY_CYCLES_ALIGN 0
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_DUMMY_CYCLES_BITS 8
#define QSPI_BSPI_REGISTERS_BITS_PER_PHASE_BSPI_REGISTERS_BITS_PER_PHASE_DUMMY_CYCLES_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_CMD_AND_MODE_BYTE
 ***************************************************************************/
/* QSPI :: bspi_registers_CMD_AND_MODE_BYTE :: bspi_registers_CMD_AND_MODE_BYTE_bspi_registers_CMD_AND_MODE_BYTE_RSVD_3 [31:24] */
#define Wr_QSPI_bspi_registers_CMD_AND_MODE_BYTE_bspi_registers_CMD_AND_MODE_BYTE_bspi_registers_CMD_AND_MODE_BYTE_RSVD_3(x) WriteRegBits(QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE,0xff000000,24,x)
#define Rd_QSPI_bspi_registers_CMD_AND_MODE_BYTE_bspi_registers_CMD_AND_MODE_BYTE_bspi_registers_CMD_AND_MODE_BYTE_RSVD_3(x) ReadRegBits(QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE,0xff000000,24)
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_RSVD_3_MASK 0xff000000
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_RSVD_3_ALIGN 0
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_RSVD_3_BITS 8
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_RSVD_3_SHIFT 24

/* QSPI :: bspi_registers_CMD_AND_MODE_BYTE :: bspi_registers_CMD_AND_MODE_BYTE_bspi_mode_byte [23:16] */
#define Wr_QSPI_bspi_registers_CMD_AND_MODE_BYTE_bspi_registers_CMD_AND_MODE_BYTE_bspi_mode_byte(x) WriteRegBits(QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE,0xff0000,16,x)
#define Rd_QSPI_bspi_registers_CMD_AND_MODE_BYTE_bspi_registers_CMD_AND_MODE_BYTE_bspi_mode_byte(x) ReadRegBits(QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE,0xff0000,16)
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_MODE_BYTE_MASK 0x00ff0000
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_MODE_BYTE_ALIGN 0
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_MODE_BYTE_BITS 8
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_MODE_BYTE_SHIFT 16

/* QSPI :: bspi_registers_CMD_AND_MODE_BYTE :: bspi_registers_CMD_AND_MODE_BYTE_reserved [15:08] */
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_RESERVED_MASK 0x0000ff00
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_RESERVED_BITS 8
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_RESERVED_SHIFT 8

/* QSPI :: bspi_registers_CMD_AND_MODE_BYTE :: bspi_registers_CMD_AND_MODE_BYTE_bspi_cmd_byte [07:00] */
#define Wr_QSPI_bspi_registers_CMD_AND_MODE_BYTE_bspi_registers_CMD_AND_MODE_BYTE_bspi_cmd_byte(x) WriteRegBits(QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE,0xff,0,x)
#define Rd_QSPI_bspi_registers_CMD_AND_MODE_BYTE_bspi_registers_CMD_AND_MODE_BYTE_bspi_cmd_byte(x) ReadRegBits(QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE,0xff,0)
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_CMD_BYTE_MASK 0x000000ff
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_CMD_BYTE_ALIGN 0
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_CMD_BYTE_BITS 8
#define QSPI_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_REGISTERS_CMD_AND_MODE_BYTE_BSPI_CMD_BYTE_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_BSPI_FLASH_UPPER_ADDR_BYTE
 ***************************************************************************/
/* QSPI :: bspi_registers_BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_registers_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr [31:24] */
#define Wr_QSPI_bspi_registers_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_registers_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr(x) WriteRegBits(QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE,0xff000000,24,x)
#define Rd_QSPI_bspi_registers_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_registers_BSPI_FLASH_UPPER_ADDR_BYTE_bspi_flash_upper_addr(x) ReadRegBits(QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE,0xff000000,24)
#define QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_FLASH_UPPER_ADDR_MASK 0xff000000
#define QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_FLASH_UPPER_ADDR_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_FLASH_UPPER_ADDR_BITS 8
#define QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_FLASH_UPPER_ADDR_SHIFT 24

/* QSPI :: bspi_registers_BSPI_FLASH_UPPER_ADDR_BYTE :: bspi_registers_BSPI_FLASH_UPPER_ADDR_BYTE_reserved [23:00] */
#define QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_RESERVED_MASK 0x00ffffff
#define QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_RESERVED_BITS 24
#define QSPI_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_BSPI_REGISTERS_BSPI_FLASH_UPPER_ADDR_BYTE_RESERVED_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_BSPI_XOR_VALUE
 ***************************************************************************/
/* QSPI :: bspi_registers_BSPI_XOR_VALUE :: bspi_registers_BSPI_XOR_VALUE_bspi_xor_value [31:20] */
#define Wr_QSPI_bspi_registers_BSPI_XOR_VALUE_bspi_registers_BSPI_XOR_VALUE_bspi_xor_value(x) WriteRegBits(QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE,0xfff00000,20,x)
#define Rd_QSPI_bspi_registers_BSPI_XOR_VALUE_bspi_registers_BSPI_XOR_VALUE_bspi_xor_value(x) ReadRegBits(QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE,0xfff00000,20)
#define QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_XOR_VALUE_MASK 0xfff00000
#define QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_XOR_VALUE_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_XOR_VALUE_BITS 12
#define QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_XOR_VALUE_SHIFT 20

/* QSPI :: bspi_registers_BSPI_XOR_VALUE :: bspi_registers_BSPI_XOR_VALUE_reserved [19:00] */
#define QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_REGISTERS_BSPI_XOR_VALUE_RESERVED_MASK 0x000fffff
#define QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_REGISTERS_BSPI_XOR_VALUE_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_REGISTERS_BSPI_XOR_VALUE_RESERVED_BITS 20
#define QSPI_BSPI_REGISTERS_BSPI_XOR_VALUE_BSPI_REGISTERS_BSPI_XOR_VALUE_RESERVED_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_BSPI_XOR_ENABLE
 ***************************************************************************/
/* QSPI :: bspi_registers_BSPI_XOR_ENABLE :: bspi_registers_BSPI_XOR_ENABLE_reserved [31:01] */
#define QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_REGISTERS_BSPI_XOR_ENABLE_RESERVED_MASK 0xfffffffe
#define QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_REGISTERS_BSPI_XOR_ENABLE_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_REGISTERS_BSPI_XOR_ENABLE_RESERVED_BITS 31
#define QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_REGISTERS_BSPI_XOR_ENABLE_RESERVED_SHIFT 1

/* QSPI :: bspi_registers_BSPI_XOR_ENABLE :: bspi_registers_BSPI_XOR_ENABLE_bspi_xor_enable [00:00] */
#define Wr_QSPI_bspi_registers_BSPI_XOR_ENABLE_bspi_registers_BSPI_XOR_ENABLE_bspi_xor_enable(x) WriteRegBits(QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE,0x1,0,x)
#define Rd_QSPI_bspi_registers_BSPI_XOR_ENABLE_bspi_registers_BSPI_XOR_ENABLE_bspi_xor_enable(x) ReadRegBits(QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE,0x1,0)
#define QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_XOR_ENABLE_MASK 0x00000001
#define QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_XOR_ENABLE_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_XOR_ENABLE_BITS 1
#define QSPI_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_REGISTERS_BSPI_XOR_ENABLE_BSPI_XOR_ENABLE_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_BSPI_PIO_MODE_ENABLE
 ***************************************************************************/
/* QSPI :: bspi_registers_BSPI_PIO_MODE_ENABLE :: bspi_registers_BSPI_PIO_MODE_ENABLE_reserved [31:01] */
#define QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_RESERVED_MASK 0xfffffffe
#define QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_RESERVED_BITS 31
#define QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_RESERVED_SHIFT 1

/* QSPI :: bspi_registers_BSPI_PIO_MODE_ENABLE :: bspi_registers_BSPI_PIO_MODE_ENABLE_bspi_pio_mode [00:00] */
#define Wr_QSPI_bspi_registers_BSPI_PIO_MODE_ENABLE_bspi_registers_BSPI_PIO_MODE_ENABLE_bspi_pio_mode(x) WriteRegBits(QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE,0x1,0,x)
#define Rd_QSPI_bspi_registers_BSPI_PIO_MODE_ENABLE_bspi_registers_BSPI_PIO_MODE_ENABLE_bspi_pio_mode(x) ReadRegBits(QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE,0x1,0)
#define QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_PIO_MODE_MASK 0x00000001
#define QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_PIO_MODE_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_PIO_MODE_BITS 1
#define QSPI_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_REGISTERS_BSPI_PIO_MODE_ENABLE_BSPI_PIO_MODE_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_BSPI_PIO_IODIR
 ***************************************************************************/
/* QSPI :: bspi_registers_BSPI_PIO_IODIR :: bspi_registers_BSPI_PIO_IODIR_reserved [31:03] */
#define QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_REGISTERS_BSPI_PIO_IODIR_RESERVED_MASK 0xfffffff8
#define QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_REGISTERS_BSPI_PIO_IODIR_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_REGISTERS_BSPI_PIO_IODIR_RESERVED_BITS 29
#define QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_REGISTERS_BSPI_PIO_IODIR_RESERVED_SHIFT 3

/* QSPI :: bspi_registers_BSPI_PIO_IODIR :: bspi_registers_BSPI_PIO_IODIR_bspi_pio_dir [02:00] */
#define Wr_QSPI_bspi_registers_BSPI_PIO_IODIR_bspi_registers_BSPI_PIO_IODIR_bspi_pio_dir(x) WriteRegBits(QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR,0x7,0,x)
#define Rd_QSPI_bspi_registers_BSPI_PIO_IODIR_bspi_registers_BSPI_PIO_IODIR_bspi_pio_dir(x) ReadRegBits(QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR,0x7,0)
#define QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_PIO_DIR_MASK 0x00000007
#define QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_PIO_DIR_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_PIO_DIR_BITS 3
#define QSPI_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_REGISTERS_BSPI_PIO_IODIR_BSPI_PIO_DIR_SHIFT 0


/****************************************************************************
 * QSPI :: bspi_registers_BSPI_PIO_DATA
 ***************************************************************************/
/* QSPI :: bspi_registers_BSPI_PIO_DATA :: bspi_registers_BSPI_PIO_DATA_reserved [31:03] */
#define QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_REGISTERS_BSPI_PIO_DATA_RESERVED_MASK 0xfffffff8
#define QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_REGISTERS_BSPI_PIO_DATA_RESERVED_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_REGISTERS_BSPI_PIO_DATA_RESERVED_BITS 29
#define QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_REGISTERS_BSPI_PIO_DATA_RESERVED_SHIFT 3

/* QSPI :: bspi_registers_BSPI_PIO_DATA :: bspi_registers_BSPI_PIO_DATA_bspi_pio_data [02:00] */
#define Wr_QSPI_bspi_registers_BSPI_PIO_DATA_bspi_registers_BSPI_PIO_DATA_bspi_pio_data(x) WriteRegBits(QSPI_BSPI_REGISTERS_BSPI_PIO_DATA,0x7,0,x)
#define Rd_QSPI_bspi_registers_BSPI_PIO_DATA_bspi_registers_BSPI_PIO_DATA_bspi_pio_data(x) ReadRegBits(QSPI_BSPI_REGISTERS_BSPI_PIO_DATA,0x7,0)
#define QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_PIO_DATA_MASK 0x00000007
#define QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_PIO_DATA_ALIGN 0
#define QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_PIO_DATA_BITS 3
#define QSPI_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_REGISTERS_BSPI_PIO_DATA_BSPI_PIO_DATA_SHIFT 0


/****************************************************************************
 * QSPI :: raf_START_ADDR
 ***************************************************************************/
/* QSPI :: raf_START_ADDR :: raf_START_ADDR_START_ADDR [31:00] */
#define Wr_QSPI_raf_START_ADDR_raf_START_ADDR_START_ADDR(x) WriteReg(QSPI_RAF_START_ADDR,x)
#define Rd_QSPI_raf_START_ADDR_raf_START_ADDR_START_ADDR(x) ReadReg(QSPI_RAF_START_ADDR)
#define QSPI_RAF_START_ADDR_RAF_START_ADDR_START_ADDR_MASK         0xffffffff
#define QSPI_RAF_START_ADDR_RAF_START_ADDR_START_ADDR_ALIGN        0
#define QSPI_RAF_START_ADDR_RAF_START_ADDR_START_ADDR_BITS         32
#define QSPI_RAF_START_ADDR_RAF_START_ADDR_START_ADDR_SHIFT        0


/****************************************************************************
 * QSPI :: raf_NUM_WORDS
 ***************************************************************************/
/* QSPI :: raf_NUM_WORDS :: raf_NUM_WORDS_NumWords [31:00] */
#define Wr_QSPI_raf_NUM_WORDS_raf_NUM_WORDS_NumWords(x) WriteReg(QSPI_RAF_NUM_WORDS,x)
#define Rd_QSPI_raf_NUM_WORDS_raf_NUM_WORDS_NumWords(x) ReadReg(QSPI_RAF_NUM_WORDS)
#define QSPI_RAF_NUM_WORDS_RAF_NUM_WORDS_NUMWORDS_MASK             0xffffffff
#define QSPI_RAF_NUM_WORDS_RAF_NUM_WORDS_NUMWORDS_ALIGN            0
#define QSPI_RAF_NUM_WORDS_RAF_NUM_WORDS_NUMWORDS_BITS             32
#define QSPI_RAF_NUM_WORDS_RAF_NUM_WORDS_NUMWORDS_SHIFT            0


/****************************************************************************
 * QSPI :: raf_CTRL
 ***************************************************************************/
/* QSPI :: raf_CTRL :: raf_CTRL_reserved [31:02] */
#define QSPI_RAF_CTRL_RAF_CTRL_RESERVED_MASK                       0xfffffffc
#define QSPI_RAF_CTRL_RAF_CTRL_RESERVED_ALIGN                      0
#define QSPI_RAF_CTRL_RAF_CTRL_RESERVED_BITS                       30
#define QSPI_RAF_CTRL_RAF_CTRL_RESERVED_SHIFT                      2

/* QSPI :: raf_CTRL :: raf_CTRL_CLEAR [01:01] */
#define Wr_QSPI_raf_CTRL_raf_CTRL_CLEAR(x) WriteRegBits(QSPI_RAF_CTRL,0x2,1,x)
#define Rd_QSPI_raf_CTRL_raf_CTRL_CLEAR(x) ReadRegBits(QSPI_RAF_CTRL,0x2,1)
#define QSPI_RAF_CTRL_RAF_CTRL_CLEAR_MASK                          0x00000002
#define QSPI_RAF_CTRL_RAF_CTRL_CLEAR_ALIGN                         0
#define QSPI_RAF_CTRL_RAF_CTRL_CLEAR_BITS                          1
#define QSPI_RAF_CTRL_RAF_CTRL_CLEAR_SHIFT                         1

/* QSPI :: raf_CTRL :: raf_CTRL_START [00:00] */
#define Wr_QSPI_raf_CTRL_raf_CTRL_START(x) WriteRegBits(QSPI_RAF_CTRL,0x1,0,x)
#define Rd_QSPI_raf_CTRL_raf_CTRL_START(x) ReadRegBits(QSPI_RAF_CTRL,0x1,0)
#define QSPI_RAF_CTRL_RAF_CTRL_START_MASK                          0x00000001
#define QSPI_RAF_CTRL_RAF_CTRL_START_ALIGN                         0
#define QSPI_RAF_CTRL_RAF_CTRL_START_BITS                          1
#define QSPI_RAF_CTRL_RAF_CTRL_START_SHIFT                         0


/****************************************************************************
 * QSPI :: raf_FULLNESS
 ***************************************************************************/
/* QSPI :: raf_FULLNESS :: raf_FULLNESS_reserved [31:07] */
#define QSPI_RAF_FULLNESS_RAF_FULLNESS_RESERVED_MASK               0xffffff80
#define QSPI_RAF_FULLNESS_RAF_FULLNESS_RESERVED_ALIGN              0
#define QSPI_RAF_FULLNESS_RAF_FULLNESS_RESERVED_BITS               25
#define QSPI_RAF_FULLNESS_RAF_FULLNESS_RESERVED_SHIFT              7

/* QSPI :: raf_FULLNESS :: raf_FULLNESS_FULLNESS [06:00] */
#define Wr_QSPI_raf_FULLNESS_raf_FULLNESS_FULLNESS(x) WriteRegBits(QSPI_RAF_FULLNESS,0x7f,0,x)
#define Rd_QSPI_raf_FULLNESS_raf_FULLNESS_FULLNESS(x) ReadRegBits(QSPI_RAF_FULLNESS,0x7f,0)
#define QSPI_RAF_FULLNESS_RAF_FULLNESS_FULLNESS_MASK               0x0000007f
#define QSPI_RAF_FULLNESS_RAF_FULLNESS_FULLNESS_ALIGN              0
#define QSPI_RAF_FULLNESS_RAF_FULLNESS_FULLNESS_BITS               7
#define QSPI_RAF_FULLNESS_RAF_FULLNESS_FULLNESS_SHIFT              0


/****************************************************************************
 * QSPI :: raf_WATERMARK
 ***************************************************************************/
/* QSPI :: raf_WATERMARK :: raf_WATERMARK_reserved [31:02] */
#define QSPI_RAF_WATERMARK_RAF_WATERMARK_RESERVED_MASK             0xfffffffc
#define QSPI_RAF_WATERMARK_RAF_WATERMARK_RESERVED_ALIGN            0
#define QSPI_RAF_WATERMARK_RAF_WATERMARK_RESERVED_BITS             30
#define QSPI_RAF_WATERMARK_RAF_WATERMARK_RESERVED_SHIFT            2

/* QSPI :: raf_WATERMARK :: raf_WATERMARK_FULLNESS_WATERMARK [01:00] */
#define Wr_QSPI_raf_WATERMARK_raf_WATERMARK_FULLNESS_WATERMARK(x) WriteRegBits(QSPI_RAF_WATERMARK,0x3,0,x)
#define Rd_QSPI_raf_WATERMARK_raf_WATERMARK_FULLNESS_WATERMARK(x) ReadRegBits(QSPI_RAF_WATERMARK,0x3,0)
#define QSPI_RAF_WATERMARK_RAF_WATERMARK_FULLNESS_WATERMARK_MASK   0x00000003
#define QSPI_RAF_WATERMARK_RAF_WATERMARK_FULLNESS_WATERMARK_ALIGN  0
#define QSPI_RAF_WATERMARK_RAF_WATERMARK_FULLNESS_WATERMARK_BITS   2
#define QSPI_RAF_WATERMARK_RAF_WATERMARK_FULLNESS_WATERMARK_SHIFT  0


/****************************************************************************
 * QSPI :: raf_STATUS
 ***************************************************************************/
/* QSPI :: raf_STATUS :: raf_STATUS_reserved [31:03] */
#define QSPI_RAF_STATUS_RAF_STATUS_RESERVED_MASK                   0xfffffff8
#define QSPI_RAF_STATUS_RAF_STATUS_RESERVED_ALIGN                  0
#define QSPI_RAF_STATUS_RAF_STATUS_RESERVED_BITS                   29
#define QSPI_RAF_STATUS_RAF_STATUS_RESERVED_SHIFT                  3

/* QSPI :: raf_STATUS :: raf_STATUS_FIFO_FULL [02:02] */
#define Wr_QSPI_raf_STATUS_raf_STATUS_FIFO_FULL(x) WriteRegBits(QSPI_RAF_STATUS,0x4,2,x)
#define Rd_QSPI_raf_STATUS_raf_STATUS_FIFO_FULL(x) ReadRegBits(QSPI_RAF_STATUS,0x4,2)
#define QSPI_RAF_STATUS_RAF_STATUS_FIFO_FULL_MASK                  0x00000004
#define QSPI_RAF_STATUS_RAF_STATUS_FIFO_FULL_ALIGN                 0
#define QSPI_RAF_STATUS_RAF_STATUS_FIFO_FULL_BITS                  1
#define QSPI_RAF_STATUS_RAF_STATUS_FIFO_FULL_SHIFT                 2

/* QSPI :: raf_STATUS :: raf_STATUS_FIFO_EMPTY [01:01] */
#define Wr_QSPI_raf_STATUS_raf_STATUS_FIFO_EMPTY(x) WriteRegBits(QSPI_RAF_STATUS,0x2,1,x)
#define Rd_QSPI_raf_STATUS_raf_STATUS_FIFO_EMPTY(x) ReadRegBits(QSPI_RAF_STATUS,0x2,1)
#define QSPI_RAF_STATUS_RAF_STATUS_FIFO_EMPTY_MASK                 0x00000002
#define QSPI_RAF_STATUS_RAF_STATUS_FIFO_EMPTY_ALIGN                0
#define QSPI_RAF_STATUS_RAF_STATUS_FIFO_EMPTY_BITS                 1
#define QSPI_RAF_STATUS_RAF_STATUS_FIFO_EMPTY_SHIFT                1

/* QSPI :: raf_STATUS :: raf_STATUS_SESSION_BUSY [00:00] */
#define Wr_QSPI_raf_STATUS_raf_STATUS_SESSION_BUSY(x) WriteRegBits(QSPI_RAF_STATUS,0x1,0,x)
#define Rd_QSPI_raf_STATUS_raf_STATUS_SESSION_BUSY(x) ReadRegBits(QSPI_RAF_STATUS,0x1,0)
#define QSPI_RAF_STATUS_RAF_STATUS_SESSION_BUSY_MASK               0x00000001
#define QSPI_RAF_STATUS_RAF_STATUS_SESSION_BUSY_ALIGN              0
#define QSPI_RAF_STATUS_RAF_STATUS_SESSION_BUSY_BITS               1
#define QSPI_RAF_STATUS_RAF_STATUS_SESSION_BUSY_SHIFT              0


/****************************************************************************
 * QSPI :: raf_READ_DATA
 ***************************************************************************/
/* QSPI :: raf_READ_DATA :: raf_READ_DATA_DATA [31:00] */
#define Wr_QSPI_raf_READ_DATA_raf_READ_DATA_DATA(x) WriteReg(QSPI_RAF_READ_DATA,x)
#define Rd_QSPI_raf_READ_DATA_raf_READ_DATA_DATA(x) ReadReg(QSPI_RAF_READ_DATA)
#define QSPI_RAF_READ_DATA_RAF_READ_DATA_DATA_MASK                 0xffffffff
#define QSPI_RAF_READ_DATA_RAF_READ_DATA_DATA_ALIGN                0
#define QSPI_RAF_READ_DATA_RAF_READ_DATA_DATA_BITS                 32
#define QSPI_RAF_READ_DATA_RAF_READ_DATA_DATA_SHIFT                0


/****************************************************************************
 * QSPI :: raf_WORD_CNT
 ***************************************************************************/
/* QSPI :: raf_WORD_CNT :: raf_WORD_CNT_CURRENT_WORD_COUNT [31:00] */
#define Wr_QSPI_raf_WORD_CNT_raf_WORD_CNT_CURRENT_WORD_COUNT(x) WriteReg(QSPI_RAF_WORD_CNT,x)
#define Rd_QSPI_raf_WORD_CNT_raf_WORD_CNT_CURRENT_WORD_COUNT(x) ReadReg(QSPI_RAF_WORD_CNT)
#define QSPI_RAF_WORD_CNT_RAF_WORD_CNT_CURRENT_WORD_COUNT_MASK     0xffffffff
#define QSPI_RAF_WORD_CNT_RAF_WORD_CNT_CURRENT_WORD_COUNT_ALIGN    0
#define QSPI_RAF_WORD_CNT_RAF_WORD_CNT_CURRENT_WORD_COUNT_BITS     32
#define QSPI_RAF_WORD_CNT_RAF_WORD_CNT_CURRENT_WORD_COUNT_SHIFT    0


/****************************************************************************
 * QSPI :: raf_CURR_ADDR
 ***************************************************************************/
/* QSPI :: raf_CURR_ADDR :: raf_CURR_ADDR_CURRENT_ADDRESS [31:00] */
#define Wr_QSPI_raf_CURR_ADDR_raf_CURR_ADDR_CURRENT_ADDRESS(x) WriteReg(QSPI_RAF_CURR_ADDR,x)
#define Rd_QSPI_raf_CURR_ADDR_raf_CURR_ADDR_CURRENT_ADDRESS(x) ReadReg(QSPI_RAF_CURR_ADDR)
#define QSPI_RAF_CURR_ADDR_RAF_CURR_ADDR_CURRENT_ADDRESS_MASK      0xffffffff
#define QSPI_RAF_CURR_ADDR_RAF_CURR_ADDR_CURRENT_ADDRESS_ALIGN     0
#define QSPI_RAF_CURR_ADDR_RAF_CURR_ADDR_CURRENT_ADDRESS_BITS      32
#define QSPI_RAF_CURR_ADDR_RAF_CURR_ADDR_CURRENT_ADDRESS_SHIFT     0


/****************************************************************************
 * QSPI :: mspi_SPCR0_LSB
 ***************************************************************************/
/* QSPI :: mspi_SPCR0_LSB :: mspi_SPCR0_LSB_reserved [31:08] */
#define QSPI_MSPI_SPCR0_LSB_MSPI_SPCR0_LSB_RESERVED_MASK           0xffffff00
#define QSPI_MSPI_SPCR0_LSB_MSPI_SPCR0_LSB_RESERVED_ALIGN          0
#define QSPI_MSPI_SPCR0_LSB_MSPI_SPCR0_LSB_RESERVED_BITS           24
#define QSPI_MSPI_SPCR0_LSB_MSPI_SPCR0_LSB_RESERVED_SHIFT          8

/* QSPI :: mspi_SPCR0_LSB :: mspi_SPCR0_LSB_SPBR [07:00] */
#define Wr_QSPI_mspi_SPCR0_LSB_mspi_SPCR0_LSB_SPBR(x) WriteRegBits(QSPI_MSPI_SPCR0_LSB,0xff,0,x)
#define Rd_QSPI_mspi_SPCR0_LSB_mspi_SPCR0_LSB_SPBR(x) ReadRegBits(QSPI_MSPI_SPCR0_LSB,0xff,0)
#define QSPI_MSPI_SPCR0_LSB_MSPI_SPCR0_LSB_SPBR_MASK               0x000000ff
#define QSPI_MSPI_SPCR0_LSB_MSPI_SPCR0_LSB_SPBR_ALIGN              0
#define QSPI_MSPI_SPCR0_LSB_MSPI_SPCR0_LSB_SPBR_BITS               8
#define QSPI_MSPI_SPCR0_LSB_MSPI_SPCR0_LSB_SPBR_SHIFT              0


/****************************************************************************
 * QSPI :: mspi_SPCR0_MSB
 ***************************************************************************/
/* QSPI :: mspi_SPCR0_MSB :: mspi_SPCR0_MSB_reserved [31:08] */
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_RESERVED_MASK           0xffffff00
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_RESERVED_ALIGN          0
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_RESERVED_BITS           24
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_RESERVED_SHIFT          8

/* QSPI :: mspi_SPCR0_MSB :: mspi_SPCR0_MSB_MSTR [07:07] */
#define Wr_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_MSTR(x) WriteRegBits(QSPI_MSPI_SPCR0_MSB,0x80,7,x)
#define Rd_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_MSTR(x) ReadRegBits(QSPI_MSPI_SPCR0_MSB,0x80,7)
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_MSTR_MASK               0x00000080
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_MSTR_ALIGN              0
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_MSTR_BITS               1
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_MSTR_SHIFT              7

/* QSPI :: mspi_SPCR0_MSB :: mspi_SPCR0_MSB_StartTransDelay [06:06] */
#define Wr_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_StartTransDelay(x) WriteRegBits(QSPI_MSPI_SPCR0_MSB,0x40,6,x)
#define Rd_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_StartTransDelay(x) ReadRegBits(QSPI_MSPI_SPCR0_MSB,0x40,6)
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_STARTTRANSDELAY_MASK    0x00000040
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_STARTTRANSDELAY_ALIGN   0
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_STARTTRANSDELAY_BITS    1
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_STARTTRANSDELAY_SHIFT   6

/* QSPI :: mspi_SPCR0_MSB :: mspi_SPCR0_MSB_BitS [05:02] */
#define Wr_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_BitS(x) WriteRegBits(QSPI_MSPI_SPCR0_MSB,0x3c,2,x)
#define Rd_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_BitS(x) ReadRegBits(QSPI_MSPI_SPCR0_MSB,0x3c,2)
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_BITS_MASK               0x0000003c
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_BITS_ALIGN              0
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_BITS_BITS               4
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_BITS_SHIFT              2

/* QSPI :: mspi_SPCR0_MSB :: mspi_SPCR0_MSB_CPOL [01:01] */
#define Wr_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_CPOL(x) WriteRegBits(QSPI_MSPI_SPCR0_MSB,0x2,1,x)
#define Rd_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_CPOL(x) ReadRegBits(QSPI_MSPI_SPCR0_MSB,0x2,1)
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_CPOL_MASK               0x00000002
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_CPOL_ALIGN              0
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_CPOL_BITS               1
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_CPOL_SHIFT              1

/* QSPI :: mspi_SPCR0_MSB :: mspi_SPCR0_MSB_CPHA [00:00] */
#define Wr_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_CPHA(x) WriteRegBits(QSPI_MSPI_SPCR0_MSB,0x1,0,x)
#define Rd_QSPI_mspi_SPCR0_MSB_mspi_SPCR0_MSB_CPHA(x) ReadRegBits(QSPI_MSPI_SPCR0_MSB,0x1,0)
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_CPHA_MASK               0x00000001
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_CPHA_ALIGN              0
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_CPHA_BITS               1
#define QSPI_MSPI_SPCR0_MSB_MSPI_SPCR0_MSB_CPHA_SHIFT              0


/****************************************************************************
 * QSPI :: mspi_SPCR1_LSB
 ***************************************************************************/
/* QSPI :: mspi_SPCR1_LSB :: mspi_SPCR1_LSB_reserved [31:08] */
#define QSPI_MSPI_SPCR1_LSB_MSPI_SPCR1_LSB_RESERVED_MASK           0xffffff00
#define QSPI_MSPI_SPCR1_LSB_MSPI_SPCR1_LSB_RESERVED_ALIGN          0
#define QSPI_MSPI_SPCR1_LSB_MSPI_SPCR1_LSB_RESERVED_BITS           24
#define QSPI_MSPI_SPCR1_LSB_MSPI_SPCR1_LSB_RESERVED_SHIFT          8

/* QSPI :: mspi_SPCR1_LSB :: mspi_SPCR1_LSB_DTL [07:00] */
#define Wr_QSPI_mspi_SPCR1_LSB_mspi_SPCR1_LSB_DTL(x) WriteRegBits(QSPI_MSPI_SPCR1_LSB,0xff,0,x)
#define Rd_QSPI_mspi_SPCR1_LSB_mspi_SPCR1_LSB_DTL(x) ReadRegBits(QSPI_MSPI_SPCR1_LSB,0xff,0)
#define QSPI_MSPI_SPCR1_LSB_MSPI_SPCR1_LSB_DTL_MASK                0x000000ff
#define QSPI_MSPI_SPCR1_LSB_MSPI_SPCR1_LSB_DTL_ALIGN               0
#define QSPI_MSPI_SPCR1_LSB_MSPI_SPCR1_LSB_DTL_BITS                8
#define QSPI_MSPI_SPCR1_LSB_MSPI_SPCR1_LSB_DTL_SHIFT               0


/****************************************************************************
 * QSPI :: mspi_SPCR1_MSB
 ***************************************************************************/
/* QSPI :: mspi_SPCR1_MSB :: mspi_SPCR1_MSB_reserved [31:08] */
#define QSPI_MSPI_SPCR1_MSB_MSPI_SPCR1_MSB_RESERVED_MASK           0xffffff00
#define QSPI_MSPI_SPCR1_MSB_MSPI_SPCR1_MSB_RESERVED_ALIGN          0
#define QSPI_MSPI_SPCR1_MSB_MSPI_SPCR1_MSB_RESERVED_BITS           24
#define QSPI_MSPI_SPCR1_MSB_MSPI_SPCR1_MSB_RESERVED_SHIFT          8

/* QSPI :: mspi_SPCR1_MSB :: mspi_SPCR1_MSB_RDSCLK [07:00] */
#define Wr_QSPI_mspi_SPCR1_MSB_mspi_SPCR1_MSB_RDSCLK(x) WriteRegBits(QSPI_MSPI_SPCR1_MSB,0xff,0,x)
#define Rd_QSPI_mspi_SPCR1_MSB_mspi_SPCR1_MSB_RDSCLK(x) ReadRegBits(QSPI_MSPI_SPCR1_MSB,0xff,0)
#define QSPI_MSPI_SPCR1_MSB_MSPI_SPCR1_MSB_RDSCLK_MASK             0x000000ff
#define QSPI_MSPI_SPCR1_MSB_MSPI_SPCR1_MSB_RDSCLK_ALIGN            0
#define QSPI_MSPI_SPCR1_MSB_MSPI_SPCR1_MSB_RDSCLK_BITS             8
#define QSPI_MSPI_SPCR1_MSB_MSPI_SPCR1_MSB_RDSCLK_SHIFT            0


/****************************************************************************
 * QSPI :: mspi_NEWQP
 ***************************************************************************/
/* QSPI :: mspi_NEWQP :: mspi_NEWQP_reserved [31:04] */
#define QSPI_MSPI_NEWQP_MSPI_NEWQP_RESERVED_MASK                   0xfffffff0
#define QSPI_MSPI_NEWQP_MSPI_NEWQP_RESERVED_ALIGN                  0
#define QSPI_MSPI_NEWQP_MSPI_NEWQP_RESERVED_BITS                   28
#define QSPI_MSPI_NEWQP_MSPI_NEWQP_RESERVED_SHIFT                  4

/* QSPI :: mspi_NEWQP :: mspi_NEWQP_newqp [03:00] */
#define Wr_QSPI_mspi_NEWQP_mspi_NEWQP_newqp(x) WriteRegBits(QSPI_MSPI_NEWQP,0xf,0,x)
#define Rd_QSPI_mspi_NEWQP_mspi_NEWQP_newqp(x) ReadRegBits(QSPI_MSPI_NEWQP,0xf,0)
#define QSPI_MSPI_NEWQP_MSPI_NEWQP_NEWQP_MASK                      0x0000000f
#define QSPI_MSPI_NEWQP_MSPI_NEWQP_NEWQP_ALIGN                     0
#define QSPI_MSPI_NEWQP_MSPI_NEWQP_NEWQP_BITS                      4
#define QSPI_MSPI_NEWQP_MSPI_NEWQP_NEWQP_SHIFT                     0


/****************************************************************************
 * QSPI :: mspi_ENDQP
 ***************************************************************************/
/* QSPI :: mspi_ENDQP :: mspi_ENDQP_reserved [31:04] */
#define QSPI_MSPI_ENDQP_MSPI_ENDQP_RESERVED_MASK                   0xfffffff0
#define QSPI_MSPI_ENDQP_MSPI_ENDQP_RESERVED_ALIGN                  0
#define QSPI_MSPI_ENDQP_MSPI_ENDQP_RESERVED_BITS                   28
#define QSPI_MSPI_ENDQP_MSPI_ENDQP_RESERVED_SHIFT                  4

/* QSPI :: mspi_ENDQP :: mspi_ENDQP_endqp [03:00] */
#define Wr_QSPI_mspi_ENDQP_mspi_ENDQP_endqp(x) WriteRegBits(QSPI_MSPI_ENDQP,0xf,0,x)
#define Rd_QSPI_mspi_ENDQP_mspi_ENDQP_endqp(x) ReadRegBits(QSPI_MSPI_ENDQP,0xf,0)
#define QSPI_MSPI_ENDQP_MSPI_ENDQP_ENDQP_MASK                      0x0000000f
#define QSPI_MSPI_ENDQP_MSPI_ENDQP_ENDQP_ALIGN                     0
#define QSPI_MSPI_ENDQP_MSPI_ENDQP_ENDQP_BITS                      4
#define QSPI_MSPI_ENDQP_MSPI_ENDQP_ENDQP_SHIFT                     0


/****************************************************************************
 * QSPI :: mspi_SPCR2
 ***************************************************************************/
/* QSPI :: mspi_SPCR2 :: mspi_SPCR2_reserved [31:08] */
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_RESERVED_MASK                   0xffffff00
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_RESERVED_ALIGN                  0
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_RESERVED_BITS                   24
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_RESERVED_SHIFT                  8

/* QSPI :: mspi_SPCR2 :: mspi_SPCR2_cont_after_cmd [07:07] */
#define Wr_QSPI_mspi_SPCR2_mspi_SPCR2_cont_after_cmd(x) WriteRegBits(QSPI_MSPI_SPCR2,0x80,7,x)
#define Rd_QSPI_mspi_SPCR2_mspi_SPCR2_cont_after_cmd(x) ReadRegBits(QSPI_MSPI_SPCR2,0x80,7)
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_CONT_AFTER_CMD_MASK             0x00000080
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_CONT_AFTER_CMD_ALIGN            0
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_CONT_AFTER_CMD_BITS             1
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_CONT_AFTER_CMD_SHIFT            7

/* QSPI :: mspi_SPCR2 :: mspi_SPCR2_spe [06:06] */
#define Wr_QSPI_mspi_SPCR2_mspi_SPCR2_spe(x) WriteRegBits(QSPI_MSPI_SPCR2,0x40,6,x)
#define Rd_QSPI_mspi_SPCR2_mspi_SPCR2_spe(x) ReadRegBits(QSPI_MSPI_SPCR2,0x40,6)
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_SPE_MASK                        0x00000040
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_SPE_ALIGN                       0
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_SPE_BITS                        1
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_SPE_SHIFT                       6

/* QSPI :: mspi_SPCR2 :: mspi_SPCR2_spifie [05:05] */
#define Wr_QSPI_mspi_SPCR2_mspi_SPCR2_spifie(x) WriteRegBits(QSPI_MSPI_SPCR2,0x20,5,x)
#define Rd_QSPI_mspi_SPCR2_mspi_SPCR2_spifie(x) ReadRegBits(QSPI_MSPI_SPCR2,0x20,5)
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_SPIFIE_MASK                     0x00000020
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_SPIFIE_ALIGN                    0
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_SPIFIE_BITS                     1
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_SPIFIE_SHIFT                    5

/* QSPI :: mspi_SPCR2 :: mspi_SPCR2_wren [04:04] */
#define Wr_QSPI_mspi_SPCR2_mspi_SPCR2_wren(x) WriteRegBits(QSPI_MSPI_SPCR2,0x10,4,x)
#define Rd_QSPI_mspi_SPCR2_mspi_SPCR2_wren(x) ReadRegBits(QSPI_MSPI_SPCR2,0x10,4)
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_WREN_MASK                       0x00000010
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_WREN_ALIGN                      0
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_WREN_BITS                       1
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_WREN_SHIFT                      4

/* QSPI :: mspi_SPCR2 :: mspi_SPCR2_wrt0 [03:03] */
#define Wr_QSPI_mspi_SPCR2_mspi_SPCR2_wrt0(x) WriteRegBits(QSPI_MSPI_SPCR2,0x8,3,x)
#define Rd_QSPI_mspi_SPCR2_mspi_SPCR2_wrt0(x) ReadRegBits(QSPI_MSPI_SPCR2,0x8,3)
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_WRT0_MASK                       0x00000008
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_WRT0_ALIGN                      0
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_WRT0_BITS                       1
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_WRT0_SHIFT                      3

/* QSPI :: mspi_SPCR2 :: mspi_SPCR2_loopq [02:02] */
#define Wr_QSPI_mspi_SPCR2_mspi_SPCR2_loopq(x) WriteRegBits(QSPI_MSPI_SPCR2,0x4,2,x)
#define Rd_QSPI_mspi_SPCR2_mspi_SPCR2_loopq(x) ReadRegBits(QSPI_MSPI_SPCR2,0x4,2)
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_LOOPQ_MASK                      0x00000004
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_LOOPQ_ALIGN                     0
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_LOOPQ_BITS                      1
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_LOOPQ_SHIFT                     2

/* QSPI :: mspi_SPCR2 :: mspi_SPCR2_hie [01:01] */
#define Wr_QSPI_mspi_SPCR2_mspi_SPCR2_hie(x) WriteRegBits(QSPI_MSPI_SPCR2,0x2,1,x)
#define Rd_QSPI_mspi_SPCR2_mspi_SPCR2_hie(x) ReadRegBits(QSPI_MSPI_SPCR2,0x2,1)
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_HIE_MASK                        0x00000002
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_HIE_ALIGN                       0
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_HIE_BITS                        1
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_HIE_SHIFT                       1

/* QSPI :: mspi_SPCR2 :: mspi_SPCR2_halt [00:00] */
#define Wr_QSPI_mspi_SPCR2_mspi_SPCR2_halt(x) WriteRegBits(QSPI_MSPI_SPCR2,0x1,0,x)
#define Rd_QSPI_mspi_SPCR2_mspi_SPCR2_halt(x) ReadRegBits(QSPI_MSPI_SPCR2,0x1,0)
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_HALT_MASK                       0x00000001
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_HALT_ALIGN                      0
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_HALT_BITS                       1
#define QSPI_MSPI_SPCR2_MSPI_SPCR2_HALT_SHIFT                      0


/****************************************************************************
 * QSPI :: mspi_MSPI_STATUS
 ***************************************************************************/
/* QSPI :: mspi_MSPI_STATUS :: mspi_MSPI_STATUS_reserved [31:02] */
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_RESERVED_MASK       0xfffffffc
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_RESERVED_ALIGN      0
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_RESERVED_BITS       30
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_RESERVED_SHIFT      2

/* QSPI :: mspi_MSPI_STATUS :: mspi_MSPI_STATUS_HALTA [01:01] */
#define Wr_QSPI_mspi_MSPI_STATUS_mspi_MSPI_STATUS_HALTA(x) WriteRegBits(QSPI_MSPI_MSPI_STATUS,0x2,1,x)
#define Rd_QSPI_mspi_MSPI_STATUS_mspi_MSPI_STATUS_HALTA(x) ReadRegBits(QSPI_MSPI_MSPI_STATUS,0x2,1)
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_HALTA_MASK          0x00000002
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_HALTA_ALIGN         0
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_HALTA_BITS          1
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_HALTA_SHIFT         1

/* QSPI :: mspi_MSPI_STATUS :: mspi_MSPI_STATUS_SPIF [00:00] */
#define Wr_QSPI_mspi_MSPI_STATUS_mspi_MSPI_STATUS_SPIF(x) WriteRegBits(QSPI_MSPI_MSPI_STATUS,0x1,0,x)
#define Rd_QSPI_mspi_MSPI_STATUS_mspi_MSPI_STATUS_SPIF(x) ReadRegBits(QSPI_MSPI_MSPI_STATUS,0x1,0)
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_SPIF_MASK           0x00000001
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_SPIF_ALIGN          0
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_SPIF_BITS           1
#define QSPI_MSPI_MSPI_STATUS_MSPI_MSPI_STATUS_SPIF_SHIFT          0


/****************************************************************************
 * QSPI :: mspi_CPTQP
 ***************************************************************************/
/* QSPI :: mspi_CPTQP :: mspi_CPTQP_reserved [31:04] */
#define QSPI_MSPI_CPTQP_MSPI_CPTQP_RESERVED_MASK                   0xfffffff0
#define QSPI_MSPI_CPTQP_MSPI_CPTQP_RESERVED_ALIGN                  0
#define QSPI_MSPI_CPTQP_MSPI_CPTQP_RESERVED_BITS                   28
#define QSPI_MSPI_CPTQP_MSPI_CPTQP_RESERVED_SHIFT                  4

/* QSPI :: mspi_CPTQP :: mspi_CPTQP_cptqp [03:00] */
#define Wr_QSPI_mspi_CPTQP_mspi_CPTQP_cptqp(x) WriteRegBits(QSPI_MSPI_CPTQP,0xf,0,x)
#define Rd_QSPI_mspi_CPTQP_mspi_CPTQP_cptqp(x) ReadRegBits(QSPI_MSPI_CPTQP,0xf,0)
#define QSPI_MSPI_CPTQP_MSPI_CPTQP_CPTQP_MASK                      0x0000000f
#define QSPI_MSPI_CPTQP_MSPI_CPTQP_CPTQP_ALIGN                     0
#define QSPI_MSPI_CPTQP_MSPI_CPTQP_CPTQP_BITS                      4
#define QSPI_MSPI_CPTQP_MSPI_CPTQP_CPTQP_SHIFT                     0


/****************************************************************************
 * QSPI :: mspi_TXRAM00
 ***************************************************************************/
/* QSPI :: mspi_TXRAM00 :: mspi_TXRAM00_reserved [31:08] */
#define QSPI_MSPI_TXRAM00_MSPI_TXRAM00_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM00_MSPI_TXRAM00_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM00_MSPI_TXRAM00_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM00_MSPI_TXRAM00_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM00 :: mspi_TXRAM00_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM00_mspi_TXRAM00_txram(x) WriteRegBits(QSPI_MSPI_TXRAM00,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM00_mspi_TXRAM00_txram(x) ReadRegBits(QSPI_MSPI_TXRAM00,0xff,0)
#define QSPI_MSPI_TXRAM00_MSPI_TXRAM00_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM00_MSPI_TXRAM00_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM00_MSPI_TXRAM00_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM00_MSPI_TXRAM00_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM01
 ***************************************************************************/
/* QSPI :: mspi_TXRAM01 :: mspi_TXRAM01_reserved [31:08] */
#define QSPI_MSPI_TXRAM01_MSPI_TXRAM01_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM01_MSPI_TXRAM01_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM01_MSPI_TXRAM01_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM01_MSPI_TXRAM01_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM01 :: mspi_TXRAM01_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM01_mspi_TXRAM01_txram(x) WriteRegBits(QSPI_MSPI_TXRAM01,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM01_mspi_TXRAM01_txram(x) ReadRegBits(QSPI_MSPI_TXRAM01,0xff,0)
#define QSPI_MSPI_TXRAM01_MSPI_TXRAM01_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM01_MSPI_TXRAM01_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM01_MSPI_TXRAM01_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM01_MSPI_TXRAM01_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM02
 ***************************************************************************/
/* QSPI :: mspi_TXRAM02 :: mspi_TXRAM02_reserved [31:08] */
#define QSPI_MSPI_TXRAM02_MSPI_TXRAM02_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM02_MSPI_TXRAM02_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM02_MSPI_TXRAM02_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM02_MSPI_TXRAM02_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM02 :: mspi_TXRAM02_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM02_mspi_TXRAM02_txram(x) WriteRegBits(QSPI_MSPI_TXRAM02,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM02_mspi_TXRAM02_txram(x) ReadRegBits(QSPI_MSPI_TXRAM02,0xff,0)
#define QSPI_MSPI_TXRAM02_MSPI_TXRAM02_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM02_MSPI_TXRAM02_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM02_MSPI_TXRAM02_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM02_MSPI_TXRAM02_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM03
 ***************************************************************************/
/* QSPI :: mspi_TXRAM03 :: mspi_TXRAM03_reserved [31:08] */
#define QSPI_MSPI_TXRAM03_MSPI_TXRAM03_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM03_MSPI_TXRAM03_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM03_MSPI_TXRAM03_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM03_MSPI_TXRAM03_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM03 :: mspi_TXRAM03_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM03_mspi_TXRAM03_txram(x) WriteRegBits(QSPI_MSPI_TXRAM03,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM03_mspi_TXRAM03_txram(x) ReadRegBits(QSPI_MSPI_TXRAM03,0xff,0)
#define QSPI_MSPI_TXRAM03_MSPI_TXRAM03_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM03_MSPI_TXRAM03_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM03_MSPI_TXRAM03_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM03_MSPI_TXRAM03_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM04
 ***************************************************************************/
/* QSPI :: mspi_TXRAM04 :: mspi_TXRAM04_reserved [31:08] */
#define QSPI_MSPI_TXRAM04_MSPI_TXRAM04_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM04_MSPI_TXRAM04_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM04_MSPI_TXRAM04_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM04_MSPI_TXRAM04_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM04 :: mspi_TXRAM04_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM04_mspi_TXRAM04_txram(x) WriteRegBits(QSPI_MSPI_TXRAM04,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM04_mspi_TXRAM04_txram(x) ReadRegBits(QSPI_MSPI_TXRAM04,0xff,0)
#define QSPI_MSPI_TXRAM04_MSPI_TXRAM04_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM04_MSPI_TXRAM04_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM04_MSPI_TXRAM04_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM04_MSPI_TXRAM04_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM05
 ***************************************************************************/
/* QSPI :: mspi_TXRAM05 :: mspi_TXRAM05_reserved [31:08] */
#define QSPI_MSPI_TXRAM05_MSPI_TXRAM05_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM05_MSPI_TXRAM05_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM05_MSPI_TXRAM05_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM05_MSPI_TXRAM05_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM05 :: mspi_TXRAM05_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM05_mspi_TXRAM05_txram(x) WriteRegBits(QSPI_MSPI_TXRAM05,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM05_mspi_TXRAM05_txram(x) ReadRegBits(QSPI_MSPI_TXRAM05,0xff,0)
#define QSPI_MSPI_TXRAM05_MSPI_TXRAM05_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM05_MSPI_TXRAM05_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM05_MSPI_TXRAM05_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM05_MSPI_TXRAM05_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM06
 ***************************************************************************/
/* QSPI :: mspi_TXRAM06 :: mspi_TXRAM06_reserved [31:08] */
#define QSPI_MSPI_TXRAM06_MSPI_TXRAM06_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM06_MSPI_TXRAM06_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM06_MSPI_TXRAM06_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM06_MSPI_TXRAM06_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM06 :: mspi_TXRAM06_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM06_mspi_TXRAM06_txram(x) WriteRegBits(QSPI_MSPI_TXRAM06,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM06_mspi_TXRAM06_txram(x) ReadRegBits(QSPI_MSPI_TXRAM06,0xff,0)
#define QSPI_MSPI_TXRAM06_MSPI_TXRAM06_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM06_MSPI_TXRAM06_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM06_MSPI_TXRAM06_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM06_MSPI_TXRAM06_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM07
 ***************************************************************************/
/* QSPI :: mspi_TXRAM07 :: mspi_TXRAM07_reserved [31:08] */
#define QSPI_MSPI_TXRAM07_MSPI_TXRAM07_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM07_MSPI_TXRAM07_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM07_MSPI_TXRAM07_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM07_MSPI_TXRAM07_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM07 :: mspi_TXRAM07_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM07_mspi_TXRAM07_txram(x) WriteRegBits(QSPI_MSPI_TXRAM07,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM07_mspi_TXRAM07_txram(x) ReadRegBits(QSPI_MSPI_TXRAM07,0xff,0)
#define QSPI_MSPI_TXRAM07_MSPI_TXRAM07_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM07_MSPI_TXRAM07_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM07_MSPI_TXRAM07_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM07_MSPI_TXRAM07_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM08
 ***************************************************************************/
/* QSPI :: mspi_TXRAM08 :: mspi_TXRAM08_reserved [31:08] */
#define QSPI_MSPI_TXRAM08_MSPI_TXRAM08_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM08_MSPI_TXRAM08_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM08_MSPI_TXRAM08_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM08_MSPI_TXRAM08_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM08 :: mspi_TXRAM08_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM08_mspi_TXRAM08_txram(x) WriteRegBits(QSPI_MSPI_TXRAM08,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM08_mspi_TXRAM08_txram(x) ReadRegBits(QSPI_MSPI_TXRAM08,0xff,0)
#define QSPI_MSPI_TXRAM08_MSPI_TXRAM08_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM08_MSPI_TXRAM08_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM08_MSPI_TXRAM08_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM08_MSPI_TXRAM08_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM09
 ***************************************************************************/
/* QSPI :: mspi_TXRAM09 :: mspi_TXRAM09_reserved [31:08] */
#define QSPI_MSPI_TXRAM09_MSPI_TXRAM09_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM09_MSPI_TXRAM09_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM09_MSPI_TXRAM09_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM09_MSPI_TXRAM09_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM09 :: mspi_TXRAM09_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM09_mspi_TXRAM09_txram(x) WriteRegBits(QSPI_MSPI_TXRAM09,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM09_mspi_TXRAM09_txram(x) ReadRegBits(QSPI_MSPI_TXRAM09,0xff,0)
#define QSPI_MSPI_TXRAM09_MSPI_TXRAM09_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM09_MSPI_TXRAM09_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM09_MSPI_TXRAM09_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM09_MSPI_TXRAM09_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM10
 ***************************************************************************/
/* QSPI :: mspi_TXRAM10 :: mspi_TXRAM10_reserved [31:08] */
#define QSPI_MSPI_TXRAM10_MSPI_TXRAM10_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM10_MSPI_TXRAM10_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM10_MSPI_TXRAM10_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM10_MSPI_TXRAM10_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM10 :: mspi_TXRAM10_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM10_mspi_TXRAM10_txram(x) WriteRegBits(QSPI_MSPI_TXRAM10,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM10_mspi_TXRAM10_txram(x) ReadRegBits(QSPI_MSPI_TXRAM10,0xff,0)
#define QSPI_MSPI_TXRAM10_MSPI_TXRAM10_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM10_MSPI_TXRAM10_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM10_MSPI_TXRAM10_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM10_MSPI_TXRAM10_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM11
 ***************************************************************************/
/* QSPI :: mspi_TXRAM11 :: mspi_TXRAM11_reserved [31:08] */
#define QSPI_MSPI_TXRAM11_MSPI_TXRAM11_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM11_MSPI_TXRAM11_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM11_MSPI_TXRAM11_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM11_MSPI_TXRAM11_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM11 :: mspi_TXRAM11_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM11_mspi_TXRAM11_txram(x) WriteRegBits(QSPI_MSPI_TXRAM11,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM11_mspi_TXRAM11_txram(x) ReadRegBits(QSPI_MSPI_TXRAM11,0xff,0)
#define QSPI_MSPI_TXRAM11_MSPI_TXRAM11_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM11_MSPI_TXRAM11_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM11_MSPI_TXRAM11_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM11_MSPI_TXRAM11_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM12
 ***************************************************************************/
/* QSPI :: mspi_TXRAM12 :: mspi_TXRAM12_reserved [31:08] */
#define QSPI_MSPI_TXRAM12_MSPI_TXRAM12_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM12_MSPI_TXRAM12_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM12_MSPI_TXRAM12_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM12_MSPI_TXRAM12_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM12 :: mspi_TXRAM12_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM12_mspi_TXRAM12_txram(x) WriteRegBits(QSPI_MSPI_TXRAM12,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM12_mspi_TXRAM12_txram(x) ReadRegBits(QSPI_MSPI_TXRAM12,0xff,0)
#define QSPI_MSPI_TXRAM12_MSPI_TXRAM12_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM12_MSPI_TXRAM12_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM12_MSPI_TXRAM12_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM12_MSPI_TXRAM12_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM13
 ***************************************************************************/
/* QSPI :: mspi_TXRAM13 :: mspi_TXRAM13_reserved [31:08] */
#define QSPI_MSPI_TXRAM13_MSPI_TXRAM13_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM13_MSPI_TXRAM13_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM13_MSPI_TXRAM13_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM13_MSPI_TXRAM13_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM13 :: mspi_TXRAM13_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM13_mspi_TXRAM13_txram(x) WriteRegBits(QSPI_MSPI_TXRAM13,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM13_mspi_TXRAM13_txram(x) ReadRegBits(QSPI_MSPI_TXRAM13,0xff,0)
#define QSPI_MSPI_TXRAM13_MSPI_TXRAM13_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM13_MSPI_TXRAM13_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM13_MSPI_TXRAM13_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM13_MSPI_TXRAM13_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM14
 ***************************************************************************/
/* QSPI :: mspi_TXRAM14 :: mspi_TXRAM14_reserved [31:08] */
#define QSPI_MSPI_TXRAM14_MSPI_TXRAM14_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM14_MSPI_TXRAM14_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM14_MSPI_TXRAM14_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM14_MSPI_TXRAM14_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM14 :: mspi_TXRAM14_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM14_mspi_TXRAM14_txram(x) WriteRegBits(QSPI_MSPI_TXRAM14,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM14_mspi_TXRAM14_txram(x) ReadRegBits(QSPI_MSPI_TXRAM14,0xff,0)
#define QSPI_MSPI_TXRAM14_MSPI_TXRAM14_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM14_MSPI_TXRAM14_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM14_MSPI_TXRAM14_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM14_MSPI_TXRAM14_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM15
 ***************************************************************************/
/* QSPI :: mspi_TXRAM15 :: mspi_TXRAM15_reserved [31:08] */
#define QSPI_MSPI_TXRAM15_MSPI_TXRAM15_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM15_MSPI_TXRAM15_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM15_MSPI_TXRAM15_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM15_MSPI_TXRAM15_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM15 :: mspi_TXRAM15_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM15_mspi_TXRAM15_txram(x) WriteRegBits(QSPI_MSPI_TXRAM15,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM15_mspi_TXRAM15_txram(x) ReadRegBits(QSPI_MSPI_TXRAM15,0xff,0)
#define QSPI_MSPI_TXRAM15_MSPI_TXRAM15_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM15_MSPI_TXRAM15_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM15_MSPI_TXRAM15_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM15_MSPI_TXRAM15_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM16
 ***************************************************************************/
/* QSPI :: mspi_TXRAM16 :: mspi_TXRAM16_reserved [31:08] */
#define QSPI_MSPI_TXRAM16_MSPI_TXRAM16_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM16_MSPI_TXRAM16_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM16_MSPI_TXRAM16_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM16_MSPI_TXRAM16_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM16 :: mspi_TXRAM16_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM16_mspi_TXRAM16_txram(x) WriteRegBits(QSPI_MSPI_TXRAM16,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM16_mspi_TXRAM16_txram(x) ReadRegBits(QSPI_MSPI_TXRAM16,0xff,0)
#define QSPI_MSPI_TXRAM16_MSPI_TXRAM16_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM16_MSPI_TXRAM16_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM16_MSPI_TXRAM16_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM16_MSPI_TXRAM16_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM17
 ***************************************************************************/
/* QSPI :: mspi_TXRAM17 :: mspi_TXRAM17_reserved [31:08] */
#define QSPI_MSPI_TXRAM17_MSPI_TXRAM17_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM17_MSPI_TXRAM17_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM17_MSPI_TXRAM17_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM17_MSPI_TXRAM17_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM17 :: mspi_TXRAM17_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM17_mspi_TXRAM17_txram(x) WriteRegBits(QSPI_MSPI_TXRAM17,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM17_mspi_TXRAM17_txram(x) ReadRegBits(QSPI_MSPI_TXRAM17,0xff,0)
#define QSPI_MSPI_TXRAM17_MSPI_TXRAM17_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM17_MSPI_TXRAM17_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM17_MSPI_TXRAM17_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM17_MSPI_TXRAM17_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM18
 ***************************************************************************/
/* QSPI :: mspi_TXRAM18 :: mspi_TXRAM18_reserved [31:08] */
#define QSPI_MSPI_TXRAM18_MSPI_TXRAM18_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM18_MSPI_TXRAM18_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM18_MSPI_TXRAM18_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM18_MSPI_TXRAM18_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM18 :: mspi_TXRAM18_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM18_mspi_TXRAM18_txram(x) WriteRegBits(QSPI_MSPI_TXRAM18,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM18_mspi_TXRAM18_txram(x) ReadRegBits(QSPI_MSPI_TXRAM18,0xff,0)
#define QSPI_MSPI_TXRAM18_MSPI_TXRAM18_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM18_MSPI_TXRAM18_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM18_MSPI_TXRAM18_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM18_MSPI_TXRAM18_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM19
 ***************************************************************************/
/* QSPI :: mspi_TXRAM19 :: mspi_TXRAM19_reserved [31:08] */
#define QSPI_MSPI_TXRAM19_MSPI_TXRAM19_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM19_MSPI_TXRAM19_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM19_MSPI_TXRAM19_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM19_MSPI_TXRAM19_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM19 :: mspi_TXRAM19_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM19_mspi_TXRAM19_txram(x) WriteRegBits(QSPI_MSPI_TXRAM19,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM19_mspi_TXRAM19_txram(x) ReadRegBits(QSPI_MSPI_TXRAM19,0xff,0)
#define QSPI_MSPI_TXRAM19_MSPI_TXRAM19_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM19_MSPI_TXRAM19_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM19_MSPI_TXRAM19_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM19_MSPI_TXRAM19_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM20
 ***************************************************************************/
/* QSPI :: mspi_TXRAM20 :: mspi_TXRAM20_reserved [31:08] */
#define QSPI_MSPI_TXRAM20_MSPI_TXRAM20_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM20_MSPI_TXRAM20_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM20_MSPI_TXRAM20_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM20_MSPI_TXRAM20_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM20 :: mspi_TXRAM20_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM20_mspi_TXRAM20_txram(x) WriteRegBits(QSPI_MSPI_TXRAM20,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM20_mspi_TXRAM20_txram(x) ReadRegBits(QSPI_MSPI_TXRAM20,0xff,0)
#define QSPI_MSPI_TXRAM20_MSPI_TXRAM20_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM20_MSPI_TXRAM20_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM20_MSPI_TXRAM20_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM20_MSPI_TXRAM20_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM21
 ***************************************************************************/
/* QSPI :: mspi_TXRAM21 :: mspi_TXRAM21_reserved [31:08] */
#define QSPI_MSPI_TXRAM21_MSPI_TXRAM21_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM21_MSPI_TXRAM21_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM21_MSPI_TXRAM21_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM21_MSPI_TXRAM21_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM21 :: mspi_TXRAM21_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM21_mspi_TXRAM21_txram(x) WriteRegBits(QSPI_MSPI_TXRAM21,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM21_mspi_TXRAM21_txram(x) ReadRegBits(QSPI_MSPI_TXRAM21,0xff,0)
#define QSPI_MSPI_TXRAM21_MSPI_TXRAM21_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM21_MSPI_TXRAM21_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM21_MSPI_TXRAM21_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM21_MSPI_TXRAM21_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM22
 ***************************************************************************/
/* QSPI :: mspi_TXRAM22 :: mspi_TXRAM22_reserved [31:08] */
#define QSPI_MSPI_TXRAM22_MSPI_TXRAM22_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM22_MSPI_TXRAM22_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM22_MSPI_TXRAM22_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM22_MSPI_TXRAM22_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM22 :: mspi_TXRAM22_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM22_mspi_TXRAM22_txram(x) WriteRegBits(QSPI_MSPI_TXRAM22,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM22_mspi_TXRAM22_txram(x) ReadRegBits(QSPI_MSPI_TXRAM22,0xff,0)
#define QSPI_MSPI_TXRAM22_MSPI_TXRAM22_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM22_MSPI_TXRAM22_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM22_MSPI_TXRAM22_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM22_MSPI_TXRAM22_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM23
 ***************************************************************************/
/* QSPI :: mspi_TXRAM23 :: mspi_TXRAM23_reserved [31:08] */
#define QSPI_MSPI_TXRAM23_MSPI_TXRAM23_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM23_MSPI_TXRAM23_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM23_MSPI_TXRAM23_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM23_MSPI_TXRAM23_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM23 :: mspi_TXRAM23_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM23_mspi_TXRAM23_txram(x) WriteRegBits(QSPI_MSPI_TXRAM23,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM23_mspi_TXRAM23_txram(x) ReadRegBits(QSPI_MSPI_TXRAM23,0xff,0)
#define QSPI_MSPI_TXRAM23_MSPI_TXRAM23_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM23_MSPI_TXRAM23_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM23_MSPI_TXRAM23_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM23_MSPI_TXRAM23_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM24
 ***************************************************************************/
/* QSPI :: mspi_TXRAM24 :: mspi_TXRAM24_reserved [31:08] */
#define QSPI_MSPI_TXRAM24_MSPI_TXRAM24_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM24_MSPI_TXRAM24_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM24_MSPI_TXRAM24_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM24_MSPI_TXRAM24_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM24 :: mspi_TXRAM24_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM24_mspi_TXRAM24_txram(x) WriteRegBits(QSPI_MSPI_TXRAM24,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM24_mspi_TXRAM24_txram(x) ReadRegBits(QSPI_MSPI_TXRAM24,0xff,0)
#define QSPI_MSPI_TXRAM24_MSPI_TXRAM24_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM24_MSPI_TXRAM24_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM24_MSPI_TXRAM24_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM24_MSPI_TXRAM24_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM25
 ***************************************************************************/
/* QSPI :: mspi_TXRAM25 :: mspi_TXRAM25_reserved [31:08] */
#define QSPI_MSPI_TXRAM25_MSPI_TXRAM25_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM25_MSPI_TXRAM25_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM25_MSPI_TXRAM25_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM25_MSPI_TXRAM25_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM25 :: mspi_TXRAM25_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM25_mspi_TXRAM25_txram(x) WriteRegBits(QSPI_MSPI_TXRAM25,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM25_mspi_TXRAM25_txram(x) ReadRegBits(QSPI_MSPI_TXRAM25,0xff,0)
#define QSPI_MSPI_TXRAM25_MSPI_TXRAM25_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM25_MSPI_TXRAM25_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM25_MSPI_TXRAM25_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM25_MSPI_TXRAM25_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM26
 ***************************************************************************/
/* QSPI :: mspi_TXRAM26 :: mspi_TXRAM26_reserved [31:08] */
#define QSPI_MSPI_TXRAM26_MSPI_TXRAM26_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM26_MSPI_TXRAM26_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM26_MSPI_TXRAM26_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM26_MSPI_TXRAM26_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM26 :: mspi_TXRAM26_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM26_mspi_TXRAM26_txram(x) WriteRegBits(QSPI_MSPI_TXRAM26,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM26_mspi_TXRAM26_txram(x) ReadRegBits(QSPI_MSPI_TXRAM26,0xff,0)
#define QSPI_MSPI_TXRAM26_MSPI_TXRAM26_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM26_MSPI_TXRAM26_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM26_MSPI_TXRAM26_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM26_MSPI_TXRAM26_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM27
 ***************************************************************************/
/* QSPI :: mspi_TXRAM27 :: mspi_TXRAM27_reserved [31:08] */
#define QSPI_MSPI_TXRAM27_MSPI_TXRAM27_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM27_MSPI_TXRAM27_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM27_MSPI_TXRAM27_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM27_MSPI_TXRAM27_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM27 :: mspi_TXRAM27_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM27_mspi_TXRAM27_txram(x) WriteRegBits(QSPI_MSPI_TXRAM27,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM27_mspi_TXRAM27_txram(x) ReadRegBits(QSPI_MSPI_TXRAM27,0xff,0)
#define QSPI_MSPI_TXRAM27_MSPI_TXRAM27_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM27_MSPI_TXRAM27_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM27_MSPI_TXRAM27_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM27_MSPI_TXRAM27_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM28
 ***************************************************************************/
/* QSPI :: mspi_TXRAM28 :: mspi_TXRAM28_reserved [31:08] */
#define QSPI_MSPI_TXRAM28_MSPI_TXRAM28_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM28_MSPI_TXRAM28_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM28_MSPI_TXRAM28_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM28_MSPI_TXRAM28_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM28 :: mspi_TXRAM28_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM28_mspi_TXRAM28_txram(x) WriteRegBits(QSPI_MSPI_TXRAM28,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM28_mspi_TXRAM28_txram(x) ReadRegBits(QSPI_MSPI_TXRAM28,0xff,0)
#define QSPI_MSPI_TXRAM28_MSPI_TXRAM28_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM28_MSPI_TXRAM28_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM28_MSPI_TXRAM28_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM28_MSPI_TXRAM28_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM29
 ***************************************************************************/
/* QSPI :: mspi_TXRAM29 :: mspi_TXRAM29_reserved [31:08] */
#define QSPI_MSPI_TXRAM29_MSPI_TXRAM29_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM29_MSPI_TXRAM29_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM29_MSPI_TXRAM29_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM29_MSPI_TXRAM29_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM29 :: mspi_TXRAM29_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM29_mspi_TXRAM29_txram(x) WriteRegBits(QSPI_MSPI_TXRAM29,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM29_mspi_TXRAM29_txram(x) ReadRegBits(QSPI_MSPI_TXRAM29,0xff,0)
#define QSPI_MSPI_TXRAM29_MSPI_TXRAM29_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM29_MSPI_TXRAM29_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM29_MSPI_TXRAM29_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM29_MSPI_TXRAM29_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM30
 ***************************************************************************/
/* QSPI :: mspi_TXRAM30 :: mspi_TXRAM30_reserved [31:08] */
#define QSPI_MSPI_TXRAM30_MSPI_TXRAM30_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM30_MSPI_TXRAM30_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM30_MSPI_TXRAM30_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM30_MSPI_TXRAM30_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM30 :: mspi_TXRAM30_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM30_mspi_TXRAM30_txram(x) WriteRegBits(QSPI_MSPI_TXRAM30,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM30_mspi_TXRAM30_txram(x) ReadRegBits(QSPI_MSPI_TXRAM30,0xff,0)
#define QSPI_MSPI_TXRAM30_MSPI_TXRAM30_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM30_MSPI_TXRAM30_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM30_MSPI_TXRAM30_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM30_MSPI_TXRAM30_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_TXRAM31
 ***************************************************************************/
/* QSPI :: mspi_TXRAM31 :: mspi_TXRAM31_reserved [31:08] */
#define QSPI_MSPI_TXRAM31_MSPI_TXRAM31_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_TXRAM31_MSPI_TXRAM31_RESERVED_ALIGN              0
#define QSPI_MSPI_TXRAM31_MSPI_TXRAM31_RESERVED_BITS               24
#define QSPI_MSPI_TXRAM31_MSPI_TXRAM31_RESERVED_SHIFT              8

/* QSPI :: mspi_TXRAM31 :: mspi_TXRAM31_txram [07:00] */
#define Wr_QSPI_mspi_TXRAM31_mspi_TXRAM31_txram(x) WriteRegBits(QSPI_MSPI_TXRAM31,0xff,0,x)
#define Rd_QSPI_mspi_TXRAM31_mspi_TXRAM31_txram(x) ReadRegBits(QSPI_MSPI_TXRAM31,0xff,0)
#define QSPI_MSPI_TXRAM31_MSPI_TXRAM31_TXRAM_MASK                  0x000000ff
#define QSPI_MSPI_TXRAM31_MSPI_TXRAM31_TXRAM_ALIGN                 0
#define QSPI_MSPI_TXRAM31_MSPI_TXRAM31_TXRAM_BITS                  8
#define QSPI_MSPI_TXRAM31_MSPI_TXRAM31_TXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM00
 ***************************************************************************/
/* QSPI :: mspi_RXRAM00 :: mspi_RXRAM00_reserved [31:08] */
#define QSPI_MSPI_RXRAM00_MSPI_RXRAM00_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM00_MSPI_RXRAM00_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM00_MSPI_RXRAM00_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM00_MSPI_RXRAM00_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM00 :: mspi_RXRAM00_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM00_mspi_RXRAM00_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM00,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM00_mspi_RXRAM00_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM00,0xff,0)
#define QSPI_MSPI_RXRAM00_MSPI_RXRAM00_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM00_MSPI_RXRAM00_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM00_MSPI_RXRAM00_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM00_MSPI_RXRAM00_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM01
 ***************************************************************************/
/* QSPI :: mspi_RXRAM01 :: mspi_RXRAM01_reserved [31:08] */
#define QSPI_MSPI_RXRAM01_MSPI_RXRAM01_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM01_MSPI_RXRAM01_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM01_MSPI_RXRAM01_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM01_MSPI_RXRAM01_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM01 :: mspi_RXRAM01_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM01_mspi_RXRAM01_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM01,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM01_mspi_RXRAM01_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM01,0xff,0)
#define QSPI_MSPI_RXRAM01_MSPI_RXRAM01_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM01_MSPI_RXRAM01_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM01_MSPI_RXRAM01_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM01_MSPI_RXRAM01_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM02
 ***************************************************************************/
/* QSPI :: mspi_RXRAM02 :: mspi_RXRAM02_reserved [31:08] */
#define QSPI_MSPI_RXRAM02_MSPI_RXRAM02_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM02_MSPI_RXRAM02_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM02_MSPI_RXRAM02_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM02_MSPI_RXRAM02_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM02 :: mspi_RXRAM02_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM02_mspi_RXRAM02_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM02,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM02_mspi_RXRAM02_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM02,0xff,0)
#define QSPI_MSPI_RXRAM02_MSPI_RXRAM02_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM02_MSPI_RXRAM02_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM02_MSPI_RXRAM02_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM02_MSPI_RXRAM02_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM03
 ***************************************************************************/
/* QSPI :: mspi_RXRAM03 :: mspi_RXRAM03_reserved [31:08] */
#define QSPI_MSPI_RXRAM03_MSPI_RXRAM03_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM03_MSPI_RXRAM03_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM03_MSPI_RXRAM03_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM03_MSPI_RXRAM03_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM03 :: mspi_RXRAM03_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM03_mspi_RXRAM03_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM03,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM03_mspi_RXRAM03_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM03,0xff,0)
#define QSPI_MSPI_RXRAM03_MSPI_RXRAM03_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM03_MSPI_RXRAM03_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM03_MSPI_RXRAM03_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM03_MSPI_RXRAM03_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM04
 ***************************************************************************/
/* QSPI :: mspi_RXRAM04 :: mspi_RXRAM04_reserved [31:08] */
#define QSPI_MSPI_RXRAM04_MSPI_RXRAM04_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM04_MSPI_RXRAM04_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM04_MSPI_RXRAM04_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM04_MSPI_RXRAM04_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM04 :: mspi_RXRAM04_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM04_mspi_RXRAM04_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM04,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM04_mspi_RXRAM04_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM04,0xff,0)
#define QSPI_MSPI_RXRAM04_MSPI_RXRAM04_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM04_MSPI_RXRAM04_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM04_MSPI_RXRAM04_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM04_MSPI_RXRAM04_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM05
 ***************************************************************************/
/* QSPI :: mspi_RXRAM05 :: mspi_RXRAM05_reserved [31:08] */
#define QSPI_MSPI_RXRAM05_MSPI_RXRAM05_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM05_MSPI_RXRAM05_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM05_MSPI_RXRAM05_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM05_MSPI_RXRAM05_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM05 :: mspi_RXRAM05_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM05_mspi_RXRAM05_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM05,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM05_mspi_RXRAM05_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM05,0xff,0)
#define QSPI_MSPI_RXRAM05_MSPI_RXRAM05_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM05_MSPI_RXRAM05_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM05_MSPI_RXRAM05_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM05_MSPI_RXRAM05_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM06
 ***************************************************************************/
/* QSPI :: mspi_RXRAM06 :: mspi_RXRAM06_reserved [31:08] */
#define QSPI_MSPI_RXRAM06_MSPI_RXRAM06_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM06_MSPI_RXRAM06_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM06_MSPI_RXRAM06_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM06_MSPI_RXRAM06_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM06 :: mspi_RXRAM06_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM06_mspi_RXRAM06_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM06,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM06_mspi_RXRAM06_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM06,0xff,0)
#define QSPI_MSPI_RXRAM06_MSPI_RXRAM06_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM06_MSPI_RXRAM06_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM06_MSPI_RXRAM06_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM06_MSPI_RXRAM06_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM07
 ***************************************************************************/
/* QSPI :: mspi_RXRAM07 :: mspi_RXRAM07_reserved [31:08] */
#define QSPI_MSPI_RXRAM07_MSPI_RXRAM07_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM07_MSPI_RXRAM07_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM07_MSPI_RXRAM07_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM07_MSPI_RXRAM07_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM07 :: mspi_RXRAM07_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM07_mspi_RXRAM07_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM07,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM07_mspi_RXRAM07_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM07,0xff,0)
#define QSPI_MSPI_RXRAM07_MSPI_RXRAM07_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM07_MSPI_RXRAM07_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM07_MSPI_RXRAM07_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM07_MSPI_RXRAM07_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM08
 ***************************************************************************/
/* QSPI :: mspi_RXRAM08 :: mspi_RXRAM08_reserved [31:08] */
#define QSPI_MSPI_RXRAM08_MSPI_RXRAM08_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM08_MSPI_RXRAM08_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM08_MSPI_RXRAM08_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM08_MSPI_RXRAM08_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM08 :: mspi_RXRAM08_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM08_mspi_RXRAM08_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM08,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM08_mspi_RXRAM08_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM08,0xff,0)
#define QSPI_MSPI_RXRAM08_MSPI_RXRAM08_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM08_MSPI_RXRAM08_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM08_MSPI_RXRAM08_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM08_MSPI_RXRAM08_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM09
 ***************************************************************************/
/* QSPI :: mspi_RXRAM09 :: mspi_RXRAM09_reserved [31:08] */
#define QSPI_MSPI_RXRAM09_MSPI_RXRAM09_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM09_MSPI_RXRAM09_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM09_MSPI_RXRAM09_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM09_MSPI_RXRAM09_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM09 :: mspi_RXRAM09_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM09_mspi_RXRAM09_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM09,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM09_mspi_RXRAM09_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM09,0xff,0)
#define QSPI_MSPI_RXRAM09_MSPI_RXRAM09_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM09_MSPI_RXRAM09_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM09_MSPI_RXRAM09_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM09_MSPI_RXRAM09_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM10
 ***************************************************************************/
/* QSPI :: mspi_RXRAM10 :: mspi_RXRAM10_reserved [31:08] */
#define QSPI_MSPI_RXRAM10_MSPI_RXRAM10_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM10_MSPI_RXRAM10_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM10_MSPI_RXRAM10_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM10_MSPI_RXRAM10_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM10 :: mspi_RXRAM10_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM10_mspi_RXRAM10_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM10,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM10_mspi_RXRAM10_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM10,0xff,0)
#define QSPI_MSPI_RXRAM10_MSPI_RXRAM10_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM10_MSPI_RXRAM10_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM10_MSPI_RXRAM10_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM10_MSPI_RXRAM10_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM11
 ***************************************************************************/
/* QSPI :: mspi_RXRAM11 :: mspi_RXRAM11_reserved [31:08] */
#define QSPI_MSPI_RXRAM11_MSPI_RXRAM11_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM11_MSPI_RXRAM11_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM11_MSPI_RXRAM11_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM11_MSPI_RXRAM11_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM11 :: mspi_RXRAM11_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM11_mspi_RXRAM11_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM11,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM11_mspi_RXRAM11_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM11,0xff,0)
#define QSPI_MSPI_RXRAM11_MSPI_RXRAM11_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM11_MSPI_RXRAM11_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM11_MSPI_RXRAM11_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM11_MSPI_RXRAM11_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM12
 ***************************************************************************/
/* QSPI :: mspi_RXRAM12 :: mspi_RXRAM12_reserved [31:08] */
#define QSPI_MSPI_RXRAM12_MSPI_RXRAM12_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM12_MSPI_RXRAM12_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM12_MSPI_RXRAM12_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM12_MSPI_RXRAM12_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM12 :: mspi_RXRAM12_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM12_mspi_RXRAM12_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM12,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM12_mspi_RXRAM12_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM12,0xff,0)
#define QSPI_MSPI_RXRAM12_MSPI_RXRAM12_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM12_MSPI_RXRAM12_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM12_MSPI_RXRAM12_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM12_MSPI_RXRAM12_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM13
 ***************************************************************************/
/* QSPI :: mspi_RXRAM13 :: mspi_RXRAM13_reserved [31:08] */
#define QSPI_MSPI_RXRAM13_MSPI_RXRAM13_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM13_MSPI_RXRAM13_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM13_MSPI_RXRAM13_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM13_MSPI_RXRAM13_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM13 :: mspi_RXRAM13_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM13_mspi_RXRAM13_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM13,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM13_mspi_RXRAM13_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM13,0xff,0)
#define QSPI_MSPI_RXRAM13_MSPI_RXRAM13_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM13_MSPI_RXRAM13_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM13_MSPI_RXRAM13_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM13_MSPI_RXRAM13_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM14
 ***************************************************************************/
/* QSPI :: mspi_RXRAM14 :: mspi_RXRAM14_reserved [31:08] */
#define QSPI_MSPI_RXRAM14_MSPI_RXRAM14_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM14_MSPI_RXRAM14_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM14_MSPI_RXRAM14_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM14_MSPI_RXRAM14_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM14 :: mspi_RXRAM14_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM14_mspi_RXRAM14_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM14,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM14_mspi_RXRAM14_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM14,0xff,0)
#define QSPI_MSPI_RXRAM14_MSPI_RXRAM14_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM14_MSPI_RXRAM14_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM14_MSPI_RXRAM14_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM14_MSPI_RXRAM14_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM15
 ***************************************************************************/
/* QSPI :: mspi_RXRAM15 :: mspi_RXRAM15_reserved [31:08] */
#define QSPI_MSPI_RXRAM15_MSPI_RXRAM15_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM15_MSPI_RXRAM15_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM15_MSPI_RXRAM15_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM15_MSPI_RXRAM15_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM15 :: mspi_RXRAM15_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM15_mspi_RXRAM15_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM15,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM15_mspi_RXRAM15_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM15,0xff,0)
#define QSPI_MSPI_RXRAM15_MSPI_RXRAM15_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM15_MSPI_RXRAM15_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM15_MSPI_RXRAM15_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM15_MSPI_RXRAM15_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM16
 ***************************************************************************/
/* QSPI :: mspi_RXRAM16 :: mspi_RXRAM16_reserved [31:08] */
#define QSPI_MSPI_RXRAM16_MSPI_RXRAM16_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM16_MSPI_RXRAM16_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM16_MSPI_RXRAM16_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM16_MSPI_RXRAM16_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM16 :: mspi_RXRAM16_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM16_mspi_RXRAM16_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM16,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM16_mspi_RXRAM16_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM16,0xff,0)
#define QSPI_MSPI_RXRAM16_MSPI_RXRAM16_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM16_MSPI_RXRAM16_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM16_MSPI_RXRAM16_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM16_MSPI_RXRAM16_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM17
 ***************************************************************************/
/* QSPI :: mspi_RXRAM17 :: mspi_RXRAM17_reserved [31:08] */
#define QSPI_MSPI_RXRAM17_MSPI_RXRAM17_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM17_MSPI_RXRAM17_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM17_MSPI_RXRAM17_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM17_MSPI_RXRAM17_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM17 :: mspi_RXRAM17_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM17_mspi_RXRAM17_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM17,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM17_mspi_RXRAM17_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM17,0xff,0)
#define QSPI_MSPI_RXRAM17_MSPI_RXRAM17_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM17_MSPI_RXRAM17_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM17_MSPI_RXRAM17_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM17_MSPI_RXRAM17_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM18
 ***************************************************************************/
/* QSPI :: mspi_RXRAM18 :: mspi_RXRAM18_reserved [31:08] */
#define QSPI_MSPI_RXRAM18_MSPI_RXRAM18_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM18_MSPI_RXRAM18_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM18_MSPI_RXRAM18_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM18_MSPI_RXRAM18_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM18 :: mspi_RXRAM18_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM18_mspi_RXRAM18_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM18,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM18_mspi_RXRAM18_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM18,0xff,0)
#define QSPI_MSPI_RXRAM18_MSPI_RXRAM18_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM18_MSPI_RXRAM18_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM18_MSPI_RXRAM18_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM18_MSPI_RXRAM18_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM19
 ***************************************************************************/
/* QSPI :: mspi_RXRAM19 :: mspi_RXRAM19_reserved [31:08] */
#define QSPI_MSPI_RXRAM19_MSPI_RXRAM19_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM19_MSPI_RXRAM19_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM19_MSPI_RXRAM19_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM19_MSPI_RXRAM19_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM19 :: mspi_RXRAM19_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM19_mspi_RXRAM19_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM19,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM19_mspi_RXRAM19_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM19,0xff,0)
#define QSPI_MSPI_RXRAM19_MSPI_RXRAM19_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM19_MSPI_RXRAM19_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM19_MSPI_RXRAM19_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM19_MSPI_RXRAM19_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM20
 ***************************************************************************/
/* QSPI :: mspi_RXRAM20 :: mspi_RXRAM20_reserved [31:08] */
#define QSPI_MSPI_RXRAM20_MSPI_RXRAM20_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM20_MSPI_RXRAM20_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM20_MSPI_RXRAM20_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM20_MSPI_RXRAM20_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM20 :: mspi_RXRAM20_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM20_mspi_RXRAM20_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM20,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM20_mspi_RXRAM20_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM20,0xff,0)
#define QSPI_MSPI_RXRAM20_MSPI_RXRAM20_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM20_MSPI_RXRAM20_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM20_MSPI_RXRAM20_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM20_MSPI_RXRAM20_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM21
 ***************************************************************************/
/* QSPI :: mspi_RXRAM21 :: mspi_RXRAM21_reserved [31:08] */
#define QSPI_MSPI_RXRAM21_MSPI_RXRAM21_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM21_MSPI_RXRAM21_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM21_MSPI_RXRAM21_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM21_MSPI_RXRAM21_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM21 :: mspi_RXRAM21_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM21_mspi_RXRAM21_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM21,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM21_mspi_RXRAM21_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM21,0xff,0)
#define QSPI_MSPI_RXRAM21_MSPI_RXRAM21_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM21_MSPI_RXRAM21_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM21_MSPI_RXRAM21_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM21_MSPI_RXRAM21_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM22
 ***************************************************************************/
/* QSPI :: mspi_RXRAM22 :: mspi_RXRAM22_reserved [31:08] */
#define QSPI_MSPI_RXRAM22_MSPI_RXRAM22_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM22_MSPI_RXRAM22_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM22_MSPI_RXRAM22_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM22_MSPI_RXRAM22_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM22 :: mspi_RXRAM22_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM22_mspi_RXRAM22_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM22,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM22_mspi_RXRAM22_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM22,0xff,0)
#define QSPI_MSPI_RXRAM22_MSPI_RXRAM22_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM22_MSPI_RXRAM22_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM22_MSPI_RXRAM22_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM22_MSPI_RXRAM22_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM23
 ***************************************************************************/
/* QSPI :: mspi_RXRAM23 :: mspi_RXRAM23_reserved [31:08] */
#define QSPI_MSPI_RXRAM23_MSPI_RXRAM23_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM23_MSPI_RXRAM23_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM23_MSPI_RXRAM23_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM23_MSPI_RXRAM23_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM23 :: mspi_RXRAM23_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM23_mspi_RXRAM23_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM23,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM23_mspi_RXRAM23_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM23,0xff,0)
#define QSPI_MSPI_RXRAM23_MSPI_RXRAM23_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM23_MSPI_RXRAM23_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM23_MSPI_RXRAM23_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM23_MSPI_RXRAM23_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM24
 ***************************************************************************/
/* QSPI :: mspi_RXRAM24 :: mspi_RXRAM24_reserved [31:08] */
#define QSPI_MSPI_RXRAM24_MSPI_RXRAM24_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM24_MSPI_RXRAM24_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM24_MSPI_RXRAM24_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM24_MSPI_RXRAM24_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM24 :: mspi_RXRAM24_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM24_mspi_RXRAM24_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM24,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM24_mspi_RXRAM24_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM24,0xff,0)
#define QSPI_MSPI_RXRAM24_MSPI_RXRAM24_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM24_MSPI_RXRAM24_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM24_MSPI_RXRAM24_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM24_MSPI_RXRAM24_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM25
 ***************************************************************************/
/* QSPI :: mspi_RXRAM25 :: mspi_RXRAM25_reserved [31:08] */
#define QSPI_MSPI_RXRAM25_MSPI_RXRAM25_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM25_MSPI_RXRAM25_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM25_MSPI_RXRAM25_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM25_MSPI_RXRAM25_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM25 :: mspi_RXRAM25_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM25_mspi_RXRAM25_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM25,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM25_mspi_RXRAM25_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM25,0xff,0)
#define QSPI_MSPI_RXRAM25_MSPI_RXRAM25_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM25_MSPI_RXRAM25_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM25_MSPI_RXRAM25_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM25_MSPI_RXRAM25_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM26
 ***************************************************************************/
/* QSPI :: mspi_RXRAM26 :: mspi_RXRAM26_reserved [31:08] */
#define QSPI_MSPI_RXRAM26_MSPI_RXRAM26_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM26_MSPI_RXRAM26_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM26_MSPI_RXRAM26_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM26_MSPI_RXRAM26_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM26 :: mspi_RXRAM26_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM26_mspi_RXRAM26_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM26,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM26_mspi_RXRAM26_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM26,0xff,0)
#define QSPI_MSPI_RXRAM26_MSPI_RXRAM26_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM26_MSPI_RXRAM26_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM26_MSPI_RXRAM26_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM26_MSPI_RXRAM26_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM27
 ***************************************************************************/
/* QSPI :: mspi_RXRAM27 :: mspi_RXRAM27_reserved [31:08] */
#define QSPI_MSPI_RXRAM27_MSPI_RXRAM27_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM27_MSPI_RXRAM27_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM27_MSPI_RXRAM27_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM27_MSPI_RXRAM27_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM27 :: mspi_RXRAM27_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM27_mspi_RXRAM27_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM27,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM27_mspi_RXRAM27_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM27,0xff,0)
#define QSPI_MSPI_RXRAM27_MSPI_RXRAM27_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM27_MSPI_RXRAM27_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM27_MSPI_RXRAM27_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM27_MSPI_RXRAM27_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM28
 ***************************************************************************/
/* QSPI :: mspi_RXRAM28 :: mspi_RXRAM28_reserved [31:08] */
#define QSPI_MSPI_RXRAM28_MSPI_RXRAM28_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM28_MSPI_RXRAM28_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM28_MSPI_RXRAM28_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM28_MSPI_RXRAM28_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM28 :: mspi_RXRAM28_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM28_mspi_RXRAM28_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM28,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM28_mspi_RXRAM28_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM28,0xff,0)
#define QSPI_MSPI_RXRAM28_MSPI_RXRAM28_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM28_MSPI_RXRAM28_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM28_MSPI_RXRAM28_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM28_MSPI_RXRAM28_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM29
 ***************************************************************************/
/* QSPI :: mspi_RXRAM29 :: mspi_RXRAM29_reserved [31:08] */
#define QSPI_MSPI_RXRAM29_MSPI_RXRAM29_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM29_MSPI_RXRAM29_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM29_MSPI_RXRAM29_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM29_MSPI_RXRAM29_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM29 :: mspi_RXRAM29_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM29_mspi_RXRAM29_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM29,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM29_mspi_RXRAM29_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM29,0xff,0)
#define QSPI_MSPI_RXRAM29_MSPI_RXRAM29_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM29_MSPI_RXRAM29_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM29_MSPI_RXRAM29_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM29_MSPI_RXRAM29_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM30
 ***************************************************************************/
/* QSPI :: mspi_RXRAM30 :: mspi_RXRAM30_reserved [31:08] */
#define QSPI_MSPI_RXRAM30_MSPI_RXRAM30_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM30_MSPI_RXRAM30_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM30_MSPI_RXRAM30_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM30_MSPI_RXRAM30_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM30 :: mspi_RXRAM30_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM30_mspi_RXRAM30_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM30,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM30_mspi_RXRAM30_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM30,0xff,0)
#define QSPI_MSPI_RXRAM30_MSPI_RXRAM30_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM30_MSPI_RXRAM30_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM30_MSPI_RXRAM30_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM30_MSPI_RXRAM30_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_RXRAM31
 ***************************************************************************/
/* QSPI :: mspi_RXRAM31 :: mspi_RXRAM31_reserved [31:08] */
#define QSPI_MSPI_RXRAM31_MSPI_RXRAM31_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_RXRAM31_MSPI_RXRAM31_RESERVED_ALIGN              0
#define QSPI_MSPI_RXRAM31_MSPI_RXRAM31_RESERVED_BITS               24
#define QSPI_MSPI_RXRAM31_MSPI_RXRAM31_RESERVED_SHIFT              8

/* QSPI :: mspi_RXRAM31 :: mspi_RXRAM31_rxram [07:00] */
#define Wr_QSPI_mspi_RXRAM31_mspi_RXRAM31_rxram(x) WriteRegBits(QSPI_MSPI_RXRAM31,0xff,0,x)
#define Rd_QSPI_mspi_RXRAM31_mspi_RXRAM31_rxram(x) ReadRegBits(QSPI_MSPI_RXRAM31,0xff,0)
#define QSPI_MSPI_RXRAM31_MSPI_RXRAM31_RXRAM_MASK                  0x000000ff
#define QSPI_MSPI_RXRAM31_MSPI_RXRAM31_RXRAM_ALIGN                 0
#define QSPI_MSPI_RXRAM31_MSPI_RXRAM31_RXRAM_BITS                  8
#define QSPI_MSPI_RXRAM31_MSPI_RXRAM31_RXRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM00
 ***************************************************************************/
/* QSPI :: mspi_CDRAM00 :: mspi_CDRAM00_reserved [31:08] */
#define QSPI_MSPI_CDRAM00_MSPI_CDRAM00_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM00_MSPI_CDRAM00_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM00_MSPI_CDRAM00_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM00_MSPI_CDRAM00_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM00 :: mspi_CDRAM00_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM00_mspi_CDRAM00_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM00,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM00_mspi_CDRAM00_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM00,0xff,0)
#define QSPI_MSPI_CDRAM00_MSPI_CDRAM00_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM00_MSPI_CDRAM00_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM00_MSPI_CDRAM00_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM00_MSPI_CDRAM00_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM01
 ***************************************************************************/
/* QSPI :: mspi_CDRAM01 :: mspi_CDRAM01_reserved [31:08] */
#define QSPI_MSPI_CDRAM01_MSPI_CDRAM01_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM01_MSPI_CDRAM01_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM01_MSPI_CDRAM01_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM01_MSPI_CDRAM01_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM01 :: mspi_CDRAM01_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM01_mspi_CDRAM01_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM01,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM01_mspi_CDRAM01_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM01,0xff,0)
#define QSPI_MSPI_CDRAM01_MSPI_CDRAM01_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM01_MSPI_CDRAM01_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM01_MSPI_CDRAM01_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM01_MSPI_CDRAM01_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM02
 ***************************************************************************/
/* QSPI :: mspi_CDRAM02 :: mspi_CDRAM02_reserved [31:08] */
#define QSPI_MSPI_CDRAM02_MSPI_CDRAM02_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM02_MSPI_CDRAM02_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM02_MSPI_CDRAM02_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM02_MSPI_CDRAM02_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM02 :: mspi_CDRAM02_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM02_mspi_CDRAM02_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM02,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM02_mspi_CDRAM02_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM02,0xff,0)
#define QSPI_MSPI_CDRAM02_MSPI_CDRAM02_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM02_MSPI_CDRAM02_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM02_MSPI_CDRAM02_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM02_MSPI_CDRAM02_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM03
 ***************************************************************************/
/* QSPI :: mspi_CDRAM03 :: mspi_CDRAM03_reserved [31:08] */
#define QSPI_MSPI_CDRAM03_MSPI_CDRAM03_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM03_MSPI_CDRAM03_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM03_MSPI_CDRAM03_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM03_MSPI_CDRAM03_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM03 :: mspi_CDRAM03_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM03_mspi_CDRAM03_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM03,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM03_mspi_CDRAM03_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM03,0xff,0)
#define QSPI_MSPI_CDRAM03_MSPI_CDRAM03_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM03_MSPI_CDRAM03_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM03_MSPI_CDRAM03_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM03_MSPI_CDRAM03_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM04
 ***************************************************************************/
/* QSPI :: mspi_CDRAM04 :: mspi_CDRAM04_reserved [31:08] */
#define QSPI_MSPI_CDRAM04_MSPI_CDRAM04_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM04_MSPI_CDRAM04_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM04_MSPI_CDRAM04_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM04_MSPI_CDRAM04_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM04 :: mspi_CDRAM04_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM04_mspi_CDRAM04_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM04,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM04_mspi_CDRAM04_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM04,0xff,0)
#define QSPI_MSPI_CDRAM04_MSPI_CDRAM04_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM04_MSPI_CDRAM04_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM04_MSPI_CDRAM04_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM04_MSPI_CDRAM04_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM05
 ***************************************************************************/
/* QSPI :: mspi_CDRAM05 :: mspi_CDRAM05_reserved [31:08] */
#define QSPI_MSPI_CDRAM05_MSPI_CDRAM05_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM05_MSPI_CDRAM05_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM05_MSPI_CDRAM05_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM05_MSPI_CDRAM05_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM05 :: mspi_CDRAM05_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM05_mspi_CDRAM05_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM05,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM05_mspi_CDRAM05_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM05,0xff,0)
#define QSPI_MSPI_CDRAM05_MSPI_CDRAM05_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM05_MSPI_CDRAM05_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM05_MSPI_CDRAM05_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM05_MSPI_CDRAM05_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM06
 ***************************************************************************/
/* QSPI :: mspi_CDRAM06 :: mspi_CDRAM06_reserved [31:08] */
#define QSPI_MSPI_CDRAM06_MSPI_CDRAM06_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM06_MSPI_CDRAM06_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM06_MSPI_CDRAM06_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM06_MSPI_CDRAM06_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM06 :: mspi_CDRAM06_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM06_mspi_CDRAM06_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM06,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM06_mspi_CDRAM06_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM06,0xff,0)
#define QSPI_MSPI_CDRAM06_MSPI_CDRAM06_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM06_MSPI_CDRAM06_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM06_MSPI_CDRAM06_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM06_MSPI_CDRAM06_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM07
 ***************************************************************************/
/* QSPI :: mspi_CDRAM07 :: mspi_CDRAM07_reserved [31:08] */
#define QSPI_MSPI_CDRAM07_MSPI_CDRAM07_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM07_MSPI_CDRAM07_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM07_MSPI_CDRAM07_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM07_MSPI_CDRAM07_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM07 :: mspi_CDRAM07_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM07_mspi_CDRAM07_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM07,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM07_mspi_CDRAM07_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM07,0xff,0)
#define QSPI_MSPI_CDRAM07_MSPI_CDRAM07_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM07_MSPI_CDRAM07_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM07_MSPI_CDRAM07_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM07_MSPI_CDRAM07_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM08
 ***************************************************************************/
/* QSPI :: mspi_CDRAM08 :: mspi_CDRAM08_reserved [31:08] */
#define QSPI_MSPI_CDRAM08_MSPI_CDRAM08_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM08_MSPI_CDRAM08_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM08_MSPI_CDRAM08_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM08_MSPI_CDRAM08_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM08 :: mspi_CDRAM08_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM08_mspi_CDRAM08_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM08,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM08_mspi_CDRAM08_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM08,0xff,0)
#define QSPI_MSPI_CDRAM08_MSPI_CDRAM08_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM08_MSPI_CDRAM08_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM08_MSPI_CDRAM08_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM08_MSPI_CDRAM08_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM09
 ***************************************************************************/
/* QSPI :: mspi_CDRAM09 :: mspi_CDRAM09_reserved [31:08] */
#define QSPI_MSPI_CDRAM09_MSPI_CDRAM09_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM09_MSPI_CDRAM09_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM09_MSPI_CDRAM09_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM09_MSPI_CDRAM09_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM09 :: mspi_CDRAM09_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM09_mspi_CDRAM09_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM09,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM09_mspi_CDRAM09_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM09,0xff,0)
#define QSPI_MSPI_CDRAM09_MSPI_CDRAM09_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM09_MSPI_CDRAM09_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM09_MSPI_CDRAM09_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM09_MSPI_CDRAM09_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM10
 ***************************************************************************/
/* QSPI :: mspi_CDRAM10 :: mspi_CDRAM10_reserved [31:08] */
#define QSPI_MSPI_CDRAM10_MSPI_CDRAM10_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM10_MSPI_CDRAM10_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM10_MSPI_CDRAM10_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM10_MSPI_CDRAM10_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM10 :: mspi_CDRAM10_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM10_mspi_CDRAM10_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM10,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM10_mspi_CDRAM10_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM10,0xff,0)
#define QSPI_MSPI_CDRAM10_MSPI_CDRAM10_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM10_MSPI_CDRAM10_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM10_MSPI_CDRAM10_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM10_MSPI_CDRAM10_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM11
 ***************************************************************************/
/* QSPI :: mspi_CDRAM11 :: mspi_CDRAM11_reserved [31:08] */
#define QSPI_MSPI_CDRAM11_MSPI_CDRAM11_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM11_MSPI_CDRAM11_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM11_MSPI_CDRAM11_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM11_MSPI_CDRAM11_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM11 :: mspi_CDRAM11_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM11_mspi_CDRAM11_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM11,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM11_mspi_CDRAM11_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM11,0xff,0)
#define QSPI_MSPI_CDRAM11_MSPI_CDRAM11_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM11_MSPI_CDRAM11_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM11_MSPI_CDRAM11_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM11_MSPI_CDRAM11_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM12
 ***************************************************************************/
/* QSPI :: mspi_CDRAM12 :: mspi_CDRAM12_reserved [31:08] */
#define QSPI_MSPI_CDRAM12_MSPI_CDRAM12_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM12_MSPI_CDRAM12_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM12_MSPI_CDRAM12_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM12_MSPI_CDRAM12_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM12 :: mspi_CDRAM12_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM12_mspi_CDRAM12_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM12,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM12_mspi_CDRAM12_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM12,0xff,0)
#define QSPI_MSPI_CDRAM12_MSPI_CDRAM12_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM12_MSPI_CDRAM12_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM12_MSPI_CDRAM12_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM12_MSPI_CDRAM12_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM13
 ***************************************************************************/
/* QSPI :: mspi_CDRAM13 :: mspi_CDRAM13_reserved [31:08] */
#define QSPI_MSPI_CDRAM13_MSPI_CDRAM13_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM13_MSPI_CDRAM13_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM13_MSPI_CDRAM13_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM13_MSPI_CDRAM13_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM13 :: mspi_CDRAM13_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM13_mspi_CDRAM13_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM13,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM13_mspi_CDRAM13_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM13,0xff,0)
#define QSPI_MSPI_CDRAM13_MSPI_CDRAM13_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM13_MSPI_CDRAM13_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM13_MSPI_CDRAM13_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM13_MSPI_CDRAM13_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM14
 ***************************************************************************/
/* QSPI :: mspi_CDRAM14 :: mspi_CDRAM14_reserved [31:08] */
#define QSPI_MSPI_CDRAM14_MSPI_CDRAM14_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM14_MSPI_CDRAM14_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM14_MSPI_CDRAM14_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM14_MSPI_CDRAM14_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM14 :: mspi_CDRAM14_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM14_mspi_CDRAM14_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM14,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM14_mspi_CDRAM14_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM14,0xff,0)
#define QSPI_MSPI_CDRAM14_MSPI_CDRAM14_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM14_MSPI_CDRAM14_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM14_MSPI_CDRAM14_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM14_MSPI_CDRAM14_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_CDRAM15
 ***************************************************************************/
/* QSPI :: mspi_CDRAM15 :: mspi_CDRAM15_reserved [31:08] */
#define QSPI_MSPI_CDRAM15_MSPI_CDRAM15_RESERVED_MASK               0xffffff00
#define QSPI_MSPI_CDRAM15_MSPI_CDRAM15_RESERVED_ALIGN              0
#define QSPI_MSPI_CDRAM15_MSPI_CDRAM15_RESERVED_BITS               24
#define QSPI_MSPI_CDRAM15_MSPI_CDRAM15_RESERVED_SHIFT              8

/* QSPI :: mspi_CDRAM15 :: mspi_CDRAM15_cdram [07:00] */
#define Wr_QSPI_mspi_CDRAM15_mspi_CDRAM15_cdram(x) WriteRegBits(QSPI_MSPI_CDRAM15,0xff,0,x)
#define Rd_QSPI_mspi_CDRAM15_mspi_CDRAM15_cdram(x) ReadRegBits(QSPI_MSPI_CDRAM15,0xff,0)
#define QSPI_MSPI_CDRAM15_MSPI_CDRAM15_CDRAM_MASK                  0x000000ff
#define QSPI_MSPI_CDRAM15_MSPI_CDRAM15_CDRAM_ALIGN                 0
#define QSPI_MSPI_CDRAM15_MSPI_CDRAM15_CDRAM_BITS                  8
#define QSPI_MSPI_CDRAM15_MSPI_CDRAM15_CDRAM_SHIFT                 0


/****************************************************************************
 * QSPI :: mspi_WRITE_LOCK
 ***************************************************************************/
/* QSPI :: mspi_WRITE_LOCK :: mspi_WRITE_LOCK_reserved [31:01] */
#define QSPI_MSPI_WRITE_LOCK_MSPI_WRITE_LOCK_RESERVED_MASK         0xfffffffe
#define QSPI_MSPI_WRITE_LOCK_MSPI_WRITE_LOCK_RESERVED_ALIGN        0
#define QSPI_MSPI_WRITE_LOCK_MSPI_WRITE_LOCK_RESERVED_BITS         31
#define QSPI_MSPI_WRITE_LOCK_MSPI_WRITE_LOCK_RESERVED_SHIFT        1

/* QSPI :: mspi_WRITE_LOCK :: mspi_WRITE_LOCK_WriteLock [00:00] */
#define Wr_QSPI_mspi_WRITE_LOCK_mspi_WRITE_LOCK_WriteLock(x) WriteRegBits(QSPI_MSPI_WRITE_LOCK,0x1,0,x)
#define Rd_QSPI_mspi_WRITE_LOCK_mspi_WRITE_LOCK_WriteLock(x) ReadRegBits(QSPI_MSPI_WRITE_LOCK,0x1,0)
#define QSPI_MSPI_WRITE_LOCK_MSPI_WRITE_LOCK_WRITELOCK_MASK        0x00000001
#define QSPI_MSPI_WRITE_LOCK_MSPI_WRITE_LOCK_WRITELOCK_ALIGN       0
#define QSPI_MSPI_WRITE_LOCK_MSPI_WRITE_LOCK_WRITELOCK_BITS        1
#define QSPI_MSPI_WRITE_LOCK_MSPI_WRITE_LOCK_WRITELOCK_SHIFT       0


/****************************************************************************
 * QSPI :: mspi_DISABLE_FLUSH_GEN
 ***************************************************************************/
/* QSPI :: mspi_DISABLE_FLUSH_GEN :: mspi_DISABLE_FLUSH_GEN_reserved [31:01] */
#define QSPI_MSPI_DISABLE_FLUSH_GEN_MSPI_DISABLE_FLUSH_GEN_RESERVED_MASK 0xfffffffe
#define QSPI_MSPI_DISABLE_FLUSH_GEN_MSPI_DISABLE_FLUSH_GEN_RESERVED_ALIGN 0
#define QSPI_MSPI_DISABLE_FLUSH_GEN_MSPI_DISABLE_FLUSH_GEN_RESERVED_BITS 31
#define QSPI_MSPI_DISABLE_FLUSH_GEN_MSPI_DISABLE_FLUSH_GEN_RESERVED_SHIFT 1

/* QSPI :: mspi_DISABLE_FLUSH_GEN :: mspi_DISABLE_FLUSH_GEN_DisableFlushGen [00:00] */
#define Wr_QSPI_mspi_DISABLE_FLUSH_GEN_mspi_DISABLE_FLUSH_GEN_DisableFlushGen(x) WriteRegBits(QSPI_MSPI_DISABLE_FLUSH_GEN,0x1,0,x)
#define Rd_QSPI_mspi_DISABLE_FLUSH_GEN_mspi_DISABLE_FLUSH_GEN_DisableFlushGen(x) ReadRegBits(QSPI_MSPI_DISABLE_FLUSH_GEN,0x1,0)
#define QSPI_MSPI_DISABLE_FLUSH_GEN_MSPI_DISABLE_FLUSH_GEN_DISABLEFLUSHGEN_MASK 0x00000001
#define QSPI_MSPI_DISABLE_FLUSH_GEN_MSPI_DISABLE_FLUSH_GEN_DISABLEFLUSHGEN_ALIGN 0
#define QSPI_MSPI_DISABLE_FLUSH_GEN_MSPI_DISABLE_FLUSH_GEN_DISABLEFLUSHGEN_BITS 1
#define QSPI_MSPI_DISABLE_FLUSH_GEN_MSPI_DISABLE_FLUSH_GEN_DISABLEFLUSHGEN_SHIFT 0


/****************************************************************************
 * QSPI :: raf_interrupt_LR_fullness_reached
 ***************************************************************************/
/* QSPI :: raf_interrupt_LR_fullness_reached :: raf_interrupt_LR_fullness_reached_raf_interrupt_LR_fullness_reached_RSVD_1 [31:01] */
#define Wr_QSPI_raf_interrupt_LR_fullness_reached_raf_interrupt_LR_fullness_reached_raf_interrupt_LR_fullness_reached_RSVD_1(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED,0xfffffffe,1,x)
#define Rd_QSPI_raf_interrupt_LR_fullness_reached_raf_interrupt_LR_fullness_reached_raf_interrupt_LR_fullness_reached_RSVD_1(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED,0xfffffffe,1)
#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_RSVD_1_MASK 0xfffffffe
#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_RSVD_1_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_RSVD_1_BITS 31
#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_RSVD_1_SHIFT 1

/* QSPI :: raf_interrupt_LR_fullness_reached :: raf_interrupt_LR_fullness_reached_spi_LR_fullness_reached [00:00] */
#define Wr_QSPI_raf_interrupt_LR_fullness_reached_raf_interrupt_LR_fullness_reached_spi_LR_fullness_reached(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED,0x1,0,x)
#define Rd_QSPI_raf_interrupt_LR_fullness_reached_raf_interrupt_LR_fullness_reached_spi_LR_fullness_reached(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED,0x1,0)
#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_SPI_LR_FULLNESS_REACHED_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_SPI_LR_FULLNESS_REACHED_BITS 1
#define QSPI_RAF_INTERRUPT_LR_FULLNESS_REACHED_RAF_INTERRUPT_LR_FULLNESS_REACHED_SPI_LR_FULLNESS_REACHED_SHIFT 0


/****************************************************************************
 * QSPI :: raf_interrupt_LR_truncated
 ***************************************************************************/
/* QSPI :: raf_interrupt_LR_truncated :: raf_interrupt_LR_truncated_raf_interrupt_LR_truncated_RSVD_1 [31:01] */
#define Wr_QSPI_raf_interrupt_LR_truncated_raf_interrupt_LR_truncated_raf_interrupt_LR_truncated_RSVD_1(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_TRUNCATED,0xfffffffe,1,x)
#define Rd_QSPI_raf_interrupt_LR_truncated_raf_interrupt_LR_truncated_raf_interrupt_LR_truncated_RSVD_1(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_TRUNCATED,0xfffffffe,1)
#define QSPI_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_RSVD_1_MASK 0xfffffffe
#define QSPI_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_RSVD_1_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_RSVD_1_BITS 31
#define QSPI_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_RSVD_1_SHIFT 1

/* QSPI :: raf_interrupt_LR_truncated :: raf_interrupt_LR_truncated_spi_LR_truncated [00:00] */
#define Wr_QSPI_raf_interrupt_LR_truncated_raf_interrupt_LR_truncated_spi_LR_truncated(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_TRUNCATED,0x1,0,x)
#define Rd_QSPI_raf_interrupt_LR_truncated_raf_interrupt_LR_truncated_spi_LR_truncated(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_TRUNCATED,0x1,0)
#define QSPI_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_SPI_LR_TRUNCATED_MASK 0x00000001
#define QSPI_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_SPI_LR_TRUNCATED_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_SPI_LR_TRUNCATED_BITS 1
#define QSPI_RAF_INTERRUPT_LR_TRUNCATED_RAF_INTERRUPT_LR_TRUNCATED_SPI_LR_TRUNCATED_SHIFT 0


/****************************************************************************
 * QSPI :: raf_interrupt_LR_impatient
 ***************************************************************************/
/* QSPI :: raf_interrupt_LR_impatient :: raf_interrupt_LR_impatient_raf_interrupt_LR_impatient_RSVD_1 [31:01] */
#define Wr_QSPI_raf_interrupt_LR_impatient_raf_interrupt_LR_impatient_raf_interrupt_LR_impatient_RSVD_1(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_IMPATIENT,0xfffffffe,1,x)
#define Rd_QSPI_raf_interrupt_LR_impatient_raf_interrupt_LR_impatient_raf_interrupt_LR_impatient_RSVD_1(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_IMPATIENT,0xfffffffe,1)
#define QSPI_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_RSVD_1_MASK 0xfffffffe
#define QSPI_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_RSVD_1_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_RSVD_1_BITS 31
#define QSPI_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_RSVD_1_SHIFT 1

/* QSPI :: raf_interrupt_LR_impatient :: raf_interrupt_LR_impatient_spi_LR_impatient [00:00] */
#define Wr_QSPI_raf_interrupt_LR_impatient_raf_interrupt_LR_impatient_spi_LR_impatient(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_IMPATIENT,0x1,0,x)
#define Rd_QSPI_raf_interrupt_LR_impatient_raf_interrupt_LR_impatient_spi_LR_impatient(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_IMPATIENT,0x1,0)
#define QSPI_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_SPI_LR_IMPATIENT_MASK 0x00000001
#define QSPI_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_SPI_LR_IMPATIENT_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_SPI_LR_IMPATIENT_BITS 1
#define QSPI_RAF_INTERRUPT_LR_IMPATIENT_RAF_INTERRUPT_LR_IMPATIENT_SPI_LR_IMPATIENT_SHIFT 0


/****************************************************************************
 * QSPI :: raf_interrupt_LR_session_done
 ***************************************************************************/
/* QSPI :: raf_interrupt_LR_session_done :: raf_interrupt_LR_session_done_raf_interrupt_LR_session_done_RSVD_1 [31:01] */
#define Wr_QSPI_raf_interrupt_LR_session_done_raf_interrupt_LR_session_done_raf_interrupt_LR_session_done_RSVD_1(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_SESSION_DONE,0xfffffffe,1,x)
#define Rd_QSPI_raf_interrupt_LR_session_done_raf_interrupt_LR_session_done_raf_interrupt_LR_session_done_RSVD_1(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_SESSION_DONE,0xfffffffe,1)
#define QSPI_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_RSVD_1_MASK 0xfffffffe
#define QSPI_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_RSVD_1_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_RSVD_1_BITS 31
#define QSPI_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_RSVD_1_SHIFT 1

/* QSPI :: raf_interrupt_LR_session_done :: raf_interrupt_LR_session_done_spi_LR_session_done [00:00] */
#define Wr_QSPI_raf_interrupt_LR_session_done_raf_interrupt_LR_session_done_spi_LR_session_done(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_SESSION_DONE,0x1,0,x)
#define Rd_QSPI_raf_interrupt_LR_session_done_raf_interrupt_LR_session_done_spi_LR_session_done(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_SESSION_DONE,0x1,0)
#define QSPI_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_SPI_LR_SESSION_DONE_MASK 0x00000001
#define QSPI_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_SPI_LR_SESSION_DONE_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_SPI_LR_SESSION_DONE_BITS 1
#define QSPI_RAF_INTERRUPT_LR_SESSION_DONE_RAF_INTERRUPT_LR_SESSION_DONE_SPI_LR_SESSION_DONE_SHIFT 0


/****************************************************************************
 * QSPI :: raf_interrupt_LR_overread
 ***************************************************************************/
/* QSPI :: raf_interrupt_LR_overread :: raf_interrupt_LR_overread_raf_interrupt_LR_overread_RSVD_1 [31:01] */
#define Wr_QSPI_raf_interrupt_LR_overread_raf_interrupt_LR_overread_raf_interrupt_LR_overread_RSVD_1(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_OVERREAD,0xfffffffe,1,x)
#define Rd_QSPI_raf_interrupt_LR_overread_raf_interrupt_LR_overread_raf_interrupt_LR_overread_RSVD_1(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_OVERREAD,0xfffffffe,1)
#define QSPI_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_RSVD_1_MASK 0xfffffffe
#define QSPI_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_RSVD_1_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_RSVD_1_BITS 31
#define QSPI_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_RSVD_1_SHIFT 1

/* QSPI :: raf_interrupt_LR_overread :: raf_interrupt_LR_overread_spi_LR_overread [00:00] */
#define Wr_QSPI_raf_interrupt_LR_overread_raf_interrupt_LR_overread_spi_LR_overread(x) WriteRegBits(QSPI_RAF_INTERRUPT_LR_OVERREAD,0x1,0,x)
#define Rd_QSPI_raf_interrupt_LR_overread_raf_interrupt_LR_overread_spi_LR_overread(x) ReadRegBits(QSPI_RAF_INTERRUPT_LR_OVERREAD,0x1,0)
#define QSPI_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_SPI_LR_OVERREAD_MASK 0x00000001
#define QSPI_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_SPI_LR_OVERREAD_ALIGN 0
#define QSPI_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_SPI_LR_OVERREAD_BITS 1
#define QSPI_RAF_INTERRUPT_LR_OVERREAD_RAF_INTERRUPT_LR_OVERREAD_SPI_LR_OVERREAD_SHIFT 0


/****************************************************************************
 * QSPI :: mspi_interrupt_MSPI_done
 ***************************************************************************/
/* QSPI :: mspi_interrupt_MSPI_done :: mspi_interrupt_MSPI_done_mspi_interrupt_MSPI_done_RSVD_1 [31:01] */
#define Wr_QSPI_mspi_interrupt_MSPI_done_mspi_interrupt_MSPI_done_mspi_interrupt_MSPI_done_RSVD_1(x) WriteRegBits(QSPI_MSPI_INTERRUPT_MSPI_DONE,0xfffffffe,1,x)
#define Rd_QSPI_mspi_interrupt_MSPI_done_mspi_interrupt_MSPI_done_mspi_interrupt_MSPI_done_RSVD_1(x) ReadRegBits(QSPI_MSPI_INTERRUPT_MSPI_DONE,0xfffffffe,1)
#define QSPI_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_RSVD_1_MASK 0xfffffffe
#define QSPI_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_RSVD_1_ALIGN 0
#define QSPI_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_RSVD_1_BITS 31
#define QSPI_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_RSVD_1_SHIFT 1

/* QSPI :: mspi_interrupt_MSPI_done :: mspi_interrupt_MSPI_done_MSPI_done [00:00] */
#define Wr_QSPI_mspi_interrupt_MSPI_done_mspi_interrupt_MSPI_done_MSPI_done(x) WriteRegBits(QSPI_MSPI_INTERRUPT_MSPI_DONE,0x1,0,x)
#define Rd_QSPI_mspi_interrupt_MSPI_done_mspi_interrupt_MSPI_done_MSPI_done(x) ReadRegBits(QSPI_MSPI_INTERRUPT_MSPI_DONE,0x1,0)
#define QSPI_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_MSPI_DONE_MASK 0x00000001
#define QSPI_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_MSPI_DONE_ALIGN 0
#define QSPI_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_MSPI_DONE_BITS 1
#define QSPI_MSPI_INTERRUPT_MSPI_DONE_MSPI_INTERRUPT_MSPI_DONE_MSPI_DONE_SHIFT 0


/****************************************************************************
 * QSPI :: mspi_interrupt_MSPI_halt_set_transaction_done
 ***************************************************************************/
/* QSPI :: mspi_interrupt_MSPI_halt_set_transaction_done :: mspi_interrupt_MSPI_halt_set_transaction_done_mspi_interrupt_MSPI_halt_set_transaction_done_RSVD_1 [31:01] */
#define Wr_QSPI_mspi_interrupt_MSPI_halt_set_transaction_done_mspi_interrupt_MSPI_halt_set_transaction_done_mspi_interrupt_MSPI_halt_set_transaction_done_RSVD_1(x) WriteRegBits(QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE,0xfffffffe,1,x)
#define Rd_QSPI_mspi_interrupt_MSPI_halt_set_transaction_done_mspi_interrupt_MSPI_halt_set_transaction_done_mspi_interrupt_MSPI_halt_set_transaction_done_RSVD_1(x) ReadRegBits(QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE,0xfffffffe,1)
#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_RSVD_1_MASK 0xfffffffe
#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_RSVD_1_ALIGN 0
#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_RSVD_1_BITS 31
#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_RSVD_1_SHIFT 1

/* QSPI :: mspi_interrupt_MSPI_halt_set_transaction_done :: mspi_interrupt_MSPI_halt_set_transaction_done_MSPI_halt_set_transaction_done [00:00] */
#define Wr_QSPI_mspi_interrupt_MSPI_halt_set_transaction_done_mspi_interrupt_MSPI_halt_set_transaction_done_MSPI_halt_set_transaction_done(x) WriteRegBits(QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE,0x1,0,x)
#define Rd_QSPI_mspi_interrupt_MSPI_halt_set_transaction_done_mspi_interrupt_MSPI_halt_set_transaction_done_MSPI_halt_set_transaction_done(x) ReadRegBits(QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE,0x1,0)
#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_HALT_SET_TRANSACTION_DONE_MASK 0x00000001
#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_HALT_SET_TRANSACTION_DONE_ALIGN 0
#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_HALT_SET_TRANSACTION_DONE_BITS 1
#define QSPI_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_INTERRUPT_MSPI_HALT_SET_TRANSACTION_DONE_MSPI_HALT_SET_TRANSACTION_DONE_SHIFT 0


/****************************************************************************
 * bcm89530_sys_cfg_MEM
 ***************************************************************************/
/****************************************************************************
 * MEM :: STATUS
 ***************************************************************************/
/* MEM :: STATUS :: MEM_SIZE [31:16] */
#define Wr_MEM_STATUS_MEM_SIZE(x) WriteRegBits(MEM_STATUS,0xffff0000,16,x)
#define Rd_MEM_STATUS_MEM_SIZE(x) ReadRegBits(MEM_STATUS,0xffff0000,16)
#define MEM_STATUS_MEM_SIZE_MASK                                   0xffff0000
#define MEM_STATUS_MEM_SIZE_ALIGN                                  0
#define MEM_STATUS_MEM_SIZE_BITS                                   16
#define MEM_STATUS_MEM_SIZE_SHIFT                                  16

/* MEM :: STATUS :: reserved0 [15:06] */
#define MEM_STATUS_RESERVED0_MASK                                  0x0000ffc0
#define MEM_STATUS_RESERVED0_ALIGN                                 0
#define MEM_STATUS_RESERVED0_BITS                                  10
#define MEM_STATUS_RESERVED0_SHIFT                                 6

/* MEM :: STATUS :: MEM_COR_R [05:05] */
#define Wr_MEM_STATUS_MEM_COR_R(x) WriteRegBits(MEM_STATUS,0x20,5,x)
#define Rd_MEM_STATUS_MEM_COR_R(x) ReadRegBits(MEM_STATUS,0x20,5)
#define MEM_STATUS_MEM_COR_R_MASK                                  0x00000020
#define MEM_STATUS_MEM_COR_R_ALIGN                                 0
#define MEM_STATUS_MEM_COR_R_BITS                                  1
#define MEM_STATUS_MEM_COR_R_SHIFT                                 5

/* MEM :: STATUS :: MEM_COR_W [04:04] */
#define Wr_MEM_STATUS_MEM_COR_W(x) WriteRegBits(MEM_STATUS,0x10,4,x)
#define Rd_MEM_STATUS_MEM_COR_W(x) ReadRegBits(MEM_STATUS,0x10,4)
#define MEM_STATUS_MEM_COR_W_MASK                                  0x00000010
#define MEM_STATUS_MEM_COR_W_ALIGN                                 0
#define MEM_STATUS_MEM_COR_W_BITS                                  1
#define MEM_STATUS_MEM_COR_W_SHIFT                                 4

/* MEM :: STATUS :: MEM_COR [03:03] */
#define Wr_MEM_STATUS_MEM_COR(x) WriteRegBits(MEM_STATUS,0x8,3,x)
#define Rd_MEM_STATUS_MEM_COR(x) ReadRegBits(MEM_STATUS,0x8,3)
#define MEM_STATUS_MEM_COR_MASK                                    0x00000008
#define MEM_STATUS_MEM_COR_ALIGN                                   0
#define MEM_STATUS_MEM_COR_BITS                                    1
#define MEM_STATUS_MEM_COR_SHIFT                                   3

/* MEM :: STATUS :: MEM_UNCOR [02:02] */
#define Wr_MEM_STATUS_MEM_UNCOR(x) WriteRegBits(MEM_STATUS,0x4,2,x)
#define Rd_MEM_STATUS_MEM_UNCOR(x) ReadRegBits(MEM_STATUS,0x4,2)
#define MEM_STATUS_MEM_UNCOR_MASK                                  0x00000004
#define MEM_STATUS_MEM_UNCOR_ALIGN                                 0
#define MEM_STATUS_MEM_UNCOR_BITS                                  1
#define MEM_STATUS_MEM_UNCOR_SHIFT                                 2

/* MEM :: STATUS :: MEM_SBMA_MISMATCH [01:01] */
#define Wr_MEM_STATUS_MEM_SBMA_MISMATCH(x) WriteRegBits(MEM_STATUS,0x2,1,x)
#define Rd_MEM_STATUS_MEM_SBMA_MISMATCH(x) ReadRegBits(MEM_STATUS,0x2,1)
#define MEM_STATUS_MEM_SBMA_MISMATCH_MASK                          0x00000002
#define MEM_STATUS_MEM_SBMA_MISMATCH_ALIGN                         0
#define MEM_STATUS_MEM_SBMA_MISMATCH_BITS                          1
#define MEM_STATUS_MEM_SBMA_MISMATCH_SHIFT                         1

/* MEM :: STATUS :: MEM_ACC_VIO [00:00] */
#define Wr_MEM_STATUS_MEM_ACC_VIO(x) WriteRegBits(MEM_STATUS,0x1,0,x)
#define Rd_MEM_STATUS_MEM_ACC_VIO(x) ReadRegBits(MEM_STATUS,0x1,0)
#define MEM_STATUS_MEM_ACC_VIO_MASK                                0x00000001
#define MEM_STATUS_MEM_ACC_VIO_ALIGN                               0
#define MEM_STATUS_MEM_ACC_VIO_BITS                                1
#define MEM_STATUS_MEM_ACC_VIO_SHIFT                               0


/****************************************************************************
 * MEM :: CNT
 ***************************************************************************/
/* MEM :: CNT :: MEM_CTHRESH [31:16] */
#define Wr_MEM_CNT_MEM_CTHRESH(x) WriteRegBits(MEM_CNT,0xffff0000,16,x)
#define Rd_MEM_CNT_MEM_CTHRESH(x) ReadRegBits(MEM_CNT,0xffff0000,16)
#define MEM_CNT_MEM_CTHRESH_MASK                                   0xffff0000
#define MEM_CNT_MEM_CTHRESH_ALIGN                                  0
#define MEM_CNT_MEM_CTHRESH_BITS                                   16
#define MEM_CNT_MEM_CTHRESH_SHIFT                                  16

/* MEM :: CNT :: MEM_CCNT [15:00] */
#define Wr_MEM_CNT_MEM_CCNT(x) WriteRegBits(MEM_CNT,0xffff,0,x)
#define Rd_MEM_CNT_MEM_CCNT(x) ReadRegBits(MEM_CNT,0xffff,0)
#define MEM_CNT_MEM_CCNT_MASK                                      0x0000ffff
#define MEM_CNT_MEM_CCNT_ALIGN                                     0
#define MEM_CNT_MEM_CCNT_BITS                                      16
#define MEM_CNT_MEM_CCNT_SHIFT                                     0


/****************************************************************************
 * MEM :: CTRL
 ***************************************************************************/
/* MEM :: CTRL :: reserved0 [31:02] */
#define MEM_CTRL_RESERVED0_MASK                                    0xfffffffc
#define MEM_CTRL_RESERVED0_ALIGN                                   0
#define MEM_CTRL_RESERVED0_BITS                                    30
#define MEM_CTRL_RESERVED0_SHIFT                                   2

/* MEM :: CTRL :: MEM_ERR_PROT [01:00] */
#define Wr_MEM_CTRL_MEM_ERR_PROT(x) WriteRegBits(MEM_CTRL,0x3,0,x)
#define Rd_MEM_CTRL_MEM_ERR_PROT(x) ReadRegBits(MEM_CTRL,0x3,0)
#define MEM_CTRL_MEM_ERR_PROT_MASK                                 0x00000003
#define MEM_CTRL_MEM_ERR_PROT_ALIGN                                0
#define MEM_CTRL_MEM_ERR_PROT_BITS                                 2
#define MEM_CTRL_MEM_ERR_PROT_SHIFT                                0


/****************************************************************************
 * MEM :: BAD_ADDR
 ***************************************************************************/
/* MEM :: BAD_ADDR :: reserved0 [31:24] */
#define MEM_BAD_ADDR_RESERVED0_MASK                                0xff000000
#define MEM_BAD_ADDR_RESERVED0_ALIGN                               0
#define MEM_BAD_ADDR_RESERVED0_BITS                                8
#define MEM_BAD_ADDR_RESERVED0_SHIFT                               24

/* MEM :: BAD_ADDR :: MEM_BAD_ADDR [23:00] */
#define Wr_MEM_BAD_ADDR_MEM_BAD_ADDR(x) WriteRegBits(MEM_BAD_ADDR,0xffffff,0,x)
#define Rd_MEM_BAD_ADDR_MEM_BAD_ADDR(x) ReadRegBits(MEM_BAD_ADDR,0xffffff,0)
#define MEM_BAD_ADDR_MEM_BAD_ADDR_MASK                             0x00ffffff
#define MEM_BAD_ADDR_MEM_BAD_ADDR_ALIGN                            0
#define MEM_BAD_ADDR_MEM_BAD_ADDR_BITS                             24
#define MEM_BAD_ADDR_MEM_BAD_ADDR_SHIFT                            0


/****************************************************************************
 * MEM :: BAD_CMD
 ***************************************************************************/
/* MEM :: BAD_CMD :: reserved0 [31:20] */
#define MEM_BAD_CMD_RESERVED0_MASK                                 0xfff00000
#define MEM_BAD_CMD_RESERVED0_ALIGN                                0
#define MEM_BAD_CMD_RESERVED0_BITS                                 12
#define MEM_BAD_CMD_RESERVED0_SHIFT                                20

/* MEM :: BAD_CMD :: MEM_BAD_COR_R [19:19] */
#define Wr_MEM_BAD_CMD_MEM_BAD_COR_R(x) WriteRegBits(MEM_BAD_CMD,0x80000,19,x)
#define Rd_MEM_BAD_CMD_MEM_BAD_COR_R(x) ReadRegBits(MEM_BAD_CMD,0x80000,19)
#define MEM_BAD_CMD_MEM_BAD_COR_R_MASK                             0x00080000
#define MEM_BAD_CMD_MEM_BAD_COR_R_ALIGN                            0
#define MEM_BAD_CMD_MEM_BAD_COR_R_BITS                             1
#define MEM_BAD_CMD_MEM_BAD_COR_R_SHIFT                            19

/* MEM :: BAD_CMD :: MEM_BAD_COR_W [18:18] */
#define Wr_MEM_BAD_CMD_MEM_BAD_COR_W(x) WriteRegBits(MEM_BAD_CMD,0x40000,18,x)
#define Rd_MEM_BAD_CMD_MEM_BAD_COR_W(x) ReadRegBits(MEM_BAD_CMD,0x40000,18)
#define MEM_BAD_CMD_MEM_BAD_COR_W_MASK                             0x00040000
#define MEM_BAD_CMD_MEM_BAD_COR_W_ALIGN                            0
#define MEM_BAD_CMD_MEM_BAD_COR_W_BITS                             1
#define MEM_BAD_CMD_MEM_BAD_COR_W_SHIFT                            18

/* MEM :: BAD_CMD :: MEM_BAD_UNCOR [17:17] */
#define Wr_MEM_BAD_CMD_MEM_BAD_UNCOR(x) WriteRegBits(MEM_BAD_CMD,0x20000,17,x)
#define Rd_MEM_BAD_CMD_MEM_BAD_UNCOR(x) ReadRegBits(MEM_BAD_CMD,0x20000,17)
#define MEM_BAD_CMD_MEM_BAD_UNCOR_MASK                             0x00020000
#define MEM_BAD_CMD_MEM_BAD_UNCOR_ALIGN                            0
#define MEM_BAD_CMD_MEM_BAD_UNCOR_BITS                             1
#define MEM_BAD_CMD_MEM_BAD_UNCOR_SHIFT                            17

/* MEM :: BAD_CMD :: MEM_BAD_ACC [16:16] */
#define Wr_MEM_BAD_CMD_MEM_BAD_ACC(x) WriteRegBits(MEM_BAD_CMD,0x10000,16,x)
#define Rd_MEM_BAD_CMD_MEM_BAD_ACC(x) ReadRegBits(MEM_BAD_CMD,0x10000,16)
#define MEM_BAD_CMD_MEM_BAD_ACC_MASK                               0x00010000
#define MEM_BAD_CMD_MEM_BAD_ACC_ALIGN                              0
#define MEM_BAD_CMD_MEM_BAD_ACC_BITS                               1
#define MEM_BAD_CMD_MEM_BAD_ACC_SHIFT                              16

/* MEM :: BAD_CMD :: reserved1 [15:14] */
#define MEM_BAD_CMD_RESERVED1_MASK                                 0x0000c000
#define MEM_BAD_CMD_RESERVED1_ALIGN                                0
#define MEM_BAD_CMD_RESERVED1_BITS                                 2
#define MEM_BAD_CMD_RESERVED1_SHIFT                                14

/* MEM :: BAD_CMD :: MEM_BAD_TRANS [13:12] */
#define Wr_MEM_BAD_CMD_MEM_BAD_TRANS(x) WriteRegBits(MEM_BAD_CMD,0x3000,12,x)
#define Rd_MEM_BAD_CMD_MEM_BAD_TRANS(x) ReadRegBits(MEM_BAD_CMD,0x3000,12)
#define MEM_BAD_CMD_MEM_BAD_TRANS_MASK                             0x00003000
#define MEM_BAD_CMD_MEM_BAD_TRANS_ALIGN                            0
#define MEM_BAD_CMD_MEM_BAD_TRANS_BITS                             2
#define MEM_BAD_CMD_MEM_BAD_TRANS_SHIFT                            12

/* MEM :: BAD_CMD :: MEM_BAD_SBMA [11:10] */
#define Wr_MEM_BAD_CMD_MEM_BAD_SBMA(x) WriteRegBits(MEM_BAD_CMD,0xc00,10,x)
#define Rd_MEM_BAD_CMD_MEM_BAD_SBMA(x) ReadRegBits(MEM_BAD_CMD,0xc00,10)
#define MEM_BAD_CMD_MEM_BAD_SBMA_MASK                              0x00000c00
#define MEM_BAD_CMD_MEM_BAD_SBMA_ALIGN                             0
#define MEM_BAD_CMD_MEM_BAD_SBMA_BITS                              2
#define MEM_BAD_CMD_MEM_BAD_SBMA_SHIFT                             10

/* MEM :: BAD_CMD :: MEM_BAD_PROT [09:04] */
#define Wr_MEM_BAD_CMD_MEM_BAD_PROT(x) WriteRegBits(MEM_BAD_CMD,0x3f0,4,x)
#define Rd_MEM_BAD_CMD_MEM_BAD_PROT(x) ReadRegBits(MEM_BAD_CMD,0x3f0,4)
#define MEM_BAD_CMD_MEM_BAD_PROT_MASK                              0x000003f0
#define MEM_BAD_CMD_MEM_BAD_PROT_ALIGN                             0
#define MEM_BAD_CMD_MEM_BAD_PROT_BITS                              6
#define MEM_BAD_CMD_MEM_BAD_PROT_SHIFT                             4

/* MEM :: BAD_CMD :: MEM_BAD_SIZE [03:01] */
#define Wr_MEM_BAD_CMD_MEM_BAD_SIZE(x) WriteRegBits(MEM_BAD_CMD,0xe,1,x)
#define Rd_MEM_BAD_CMD_MEM_BAD_SIZE(x) ReadRegBits(MEM_BAD_CMD,0xe,1)
#define MEM_BAD_CMD_MEM_BAD_SIZE_MASK                              0x0000000e
#define MEM_BAD_CMD_MEM_BAD_SIZE_ALIGN                             0
#define MEM_BAD_CMD_MEM_BAD_SIZE_BITS                              3
#define MEM_BAD_CMD_MEM_BAD_SIZE_SHIFT                             1

/* MEM :: BAD_CMD :: MEM_BAD_WRITE [00:00] */
#define Wr_MEM_BAD_CMD_MEM_BAD_WRITE(x) WriteRegBits(MEM_BAD_CMD,0x1,0,x)
#define Rd_MEM_BAD_CMD_MEM_BAD_WRITE(x) ReadRegBits(MEM_BAD_CMD,0x1,0)
#define MEM_BAD_CMD_MEM_BAD_WRITE_MASK                             0x00000001
#define MEM_BAD_CMD_MEM_BAD_WRITE_ALIGN                            0
#define MEM_BAD_CMD_MEM_BAD_WRITE_BITS                             1
#define MEM_BAD_CMD_MEM_BAD_WRITE_SHIFT                            0


/****************************************************************************
 * MEM :: BAD_DATA
 ***************************************************************************/
/* MEM :: BAD_DATA :: MEM_BAD_DATA [31:00] */
#define Wr_MEM_BAD_DATA_MEM_BAD_DATA(x) WriteReg(MEM_BAD_DATA,x)
#define Rd_MEM_BAD_DATA_MEM_BAD_DATA(x) ReadReg(MEM_BAD_DATA)
#define MEM_BAD_DATA_MEM_BAD_DATA_MASK                             0xffffffff
#define MEM_BAD_DATA_MEM_BAD_DATA_ALIGN                            0
#define MEM_BAD_DATA_MEM_BAD_DATA_BITS                             32
#define MEM_BAD_DATA_MEM_BAD_DATA_SHIFT                            0


/****************************************************************************
 * MEM :: BAD_DATA1
 ***************************************************************************/
/* MEM :: BAD_DATA1 :: MEM_BAD_DATA1 [31:00] */
#define Wr_MEM_BAD_DATA1_MEM_BAD_DATA1(x) WriteReg(MEM_BAD_DATA1,x)
#define Rd_MEM_BAD_DATA1_MEM_BAD_DATA1(x) ReadReg(MEM_BAD_DATA1)
#define MEM_BAD_DATA1_MEM_BAD_DATA1_MASK                           0xffffffff
#define MEM_BAD_DATA1_MEM_BAD_DATA1_ALIGN                          0
#define MEM_BAD_DATA1_MEM_BAD_DATA1_BITS                           32
#define MEM_BAD_DATA1_MEM_BAD_DATA1_SHIFT                          0


/****************************************************************************
 * MEM :: BAD_ECC
 ***************************************************************************/
/* MEM :: BAD_ECC :: reserved0 [31:14] */
#define MEM_BAD_ECC_RESERVED0_MASK                                 0xffffc000
#define MEM_BAD_ECC_RESERVED0_ALIGN                                0
#define MEM_BAD_ECC_RESERVED0_BITS                                 18
#define MEM_BAD_ECC_RESERVED0_SHIFT                                14

/* MEM :: BAD_ECC :: MEM_BAD_ECC [13:00] */
#define Wr_MEM_BAD_ECC_MEM_BAD_ECC(x) WriteRegBits(MEM_BAD_ECC,0x3fff,0,x)
#define Rd_MEM_BAD_ECC_MEM_BAD_ECC(x) ReadRegBits(MEM_BAD_ECC,0x3fff,0)
#define MEM_BAD_ECC_MEM_BAD_ECC_MASK                               0x00003fff
#define MEM_BAD_ECC_MEM_BAD_ECC_ALIGN                              0
#define MEM_BAD_ECC_MEM_BAD_ECC_BITS                               14
#define MEM_BAD_ECC_MEM_BAD_ECC_SHIFT                              0


/****************************************************************************
 * bcm89530_sys_cfg_TIM0
 ***************************************************************************/
/****************************************************************************
 * TIM0 :: Timer1Load
 ***************************************************************************/
/* TIM0 :: Timer1Load :: TIMER1LOAD [31:00] */
#define Wr_TIM0_Timer1Load_TIMER1LOAD(x) WriteReg(TIM0_TIMER1LOAD,x)
#define Rd_TIM0_Timer1Load_TIMER1LOAD(x) ReadReg(TIM0_TIMER1LOAD)
#define TIM0_TIMER1LOAD_TIMER1LOAD_MASK                            0xffffffff
#define TIM0_TIMER1LOAD_TIMER1LOAD_ALIGN                           0
#define TIM0_TIMER1LOAD_TIMER1LOAD_BITS                            32
#define TIM0_TIMER1LOAD_TIMER1LOAD_SHIFT                           0


/****************************************************************************
 * TIM0 :: Timer1Value
 ***************************************************************************/
/* TIM0 :: Timer1Value :: TIMER1VALUE [31:00] */
#define Wr_TIM0_Timer1Value_TIMER1VALUE(x) WriteReg(TIM0_TIMER1VALUE,x)
#define Rd_TIM0_Timer1Value_TIMER1VALUE(x) ReadReg(TIM0_TIMER1VALUE)
#define TIM0_TIMER1VALUE_TIMER1VALUE_MASK                          0xffffffff
#define TIM0_TIMER1VALUE_TIMER1VALUE_ALIGN                         0
#define TIM0_TIMER1VALUE_TIMER1VALUE_BITS                          32
#define TIM0_TIMER1VALUE_TIMER1VALUE_SHIFT                         0


/****************************************************************************
 * TIM0 :: Timer1Control
 ***************************************************************************/
/* TIM0 :: Timer1Control :: reserved0 [31:08] */
#define TIM0_TIMER1CONTROL_RESERVED0_MASK                          0xffffff00
#define TIM0_TIMER1CONTROL_RESERVED0_ALIGN                         0
#define TIM0_TIMER1CONTROL_RESERVED0_BITS                          24
#define TIM0_TIMER1CONTROL_RESERVED0_SHIFT                         8

/* TIM0 :: Timer1Control :: Timer1En [07:07] */
#define Wr_TIM0_Timer1Control_Timer1En(x) WriteRegBits(TIM0_TIMER1CONTROL,0x80,7,x)
#define Rd_TIM0_Timer1Control_Timer1En(x) ReadRegBits(TIM0_TIMER1CONTROL,0x80,7)
#define TIM0_TIMER1CONTROL_TIMER1EN_MASK                           0x00000080
#define TIM0_TIMER1CONTROL_TIMER1EN_ALIGN                          0
#define TIM0_TIMER1CONTROL_TIMER1EN_BITS                           1
#define TIM0_TIMER1CONTROL_TIMER1EN_SHIFT                          7

/* TIM0 :: Timer1Control :: Timer1Mode [06:06] */
#define Wr_TIM0_Timer1Control_Timer1Mode(x) WriteRegBits(TIM0_TIMER1CONTROL,0x40,6,x)
#define Rd_TIM0_Timer1Control_Timer1Mode(x) ReadRegBits(TIM0_TIMER1CONTROL,0x40,6)
#define TIM0_TIMER1CONTROL_TIMER1MODE_MASK                         0x00000040
#define TIM0_TIMER1CONTROL_TIMER1MODE_ALIGN                        0
#define TIM0_TIMER1CONTROL_TIMER1MODE_BITS                         1
#define TIM0_TIMER1CONTROL_TIMER1MODE_SHIFT                        6

/* TIM0 :: Timer1Control :: IntEnable1 [05:05] */
#define Wr_TIM0_Timer1Control_IntEnable1(x) WriteRegBits(TIM0_TIMER1CONTROL,0x20,5,x)
#define Rd_TIM0_Timer1Control_IntEnable1(x) ReadRegBits(TIM0_TIMER1CONTROL,0x20,5)
#define TIM0_TIMER1CONTROL_INTENABLE1_MASK                         0x00000020
#define TIM0_TIMER1CONTROL_INTENABLE1_ALIGN                        0
#define TIM0_TIMER1CONTROL_INTENABLE1_BITS                         1
#define TIM0_TIMER1CONTROL_INTENABLE1_SHIFT                        5

/* TIM0 :: Timer1Control :: reserved1 [04:04] */
#define TIM0_TIMER1CONTROL_RESERVED1_MASK                          0x00000010
#define TIM0_TIMER1CONTROL_RESERVED1_ALIGN                         0
#define TIM0_TIMER1CONTROL_RESERVED1_BITS                          1
#define TIM0_TIMER1CONTROL_RESERVED1_SHIFT                         4

/* TIM0 :: Timer1Control :: Timer1Pre [03:02] */
#define Wr_TIM0_Timer1Control_Timer1Pre(x) WriteRegBits(TIM0_TIMER1CONTROL,0xc,2,x)
#define Rd_TIM0_Timer1Control_Timer1Pre(x) ReadRegBits(TIM0_TIMER1CONTROL,0xc,2)
#define TIM0_TIMER1CONTROL_TIMER1PRE_MASK                          0x0000000c
#define TIM0_TIMER1CONTROL_TIMER1PRE_ALIGN                         0
#define TIM0_TIMER1CONTROL_TIMER1PRE_BITS                          2
#define TIM0_TIMER1CONTROL_TIMER1PRE_SHIFT                         2

/* TIM0 :: Timer1Control :: Timer1Size [01:01] */
#define Wr_TIM0_Timer1Control_Timer1Size(x) WriteRegBits(TIM0_TIMER1CONTROL,0x2,1,x)
#define Rd_TIM0_Timer1Control_Timer1Size(x) ReadRegBits(TIM0_TIMER1CONTROL,0x2,1)
#define TIM0_TIMER1CONTROL_TIMER1SIZE_MASK                         0x00000002
#define TIM0_TIMER1CONTROL_TIMER1SIZE_ALIGN                        0
#define TIM0_TIMER1CONTROL_TIMER1SIZE_BITS                         1
#define TIM0_TIMER1CONTROL_TIMER1SIZE_SHIFT                        1

/* TIM0 :: Timer1Control :: OneShot_Timer1 [00:00] */
#define Wr_TIM0_Timer1Control_OneShot_Timer1(x) WriteRegBits(TIM0_TIMER1CONTROL,0x1,0,x)
#define Rd_TIM0_Timer1Control_OneShot_Timer1(x) ReadRegBits(TIM0_TIMER1CONTROL,0x1,0)
#define TIM0_TIMER1CONTROL_ONESHOT_TIMER1_MASK                     0x00000001
#define TIM0_TIMER1CONTROL_ONESHOT_TIMER1_ALIGN                    0
#define TIM0_TIMER1CONTROL_ONESHOT_TIMER1_BITS                     1
#define TIM0_TIMER1CONTROL_ONESHOT_TIMER1_SHIFT                    0


/****************************************************************************
 * TIM0 :: Timer1IntClr
 ***************************************************************************/
/* TIM0 :: Timer1IntClr :: reserved0 [31:01] */
#define TIM0_TIMER1INTCLR_RESERVED0_MASK                           0xfffffffe
#define TIM0_TIMER1INTCLR_RESERVED0_ALIGN                          0
#define TIM0_TIMER1INTCLR_RESERVED0_BITS                           31
#define TIM0_TIMER1INTCLR_RESERVED0_SHIFT                          1

/* TIM0 :: Timer1IntClr :: TIMER1INTCLR [00:00] */
#define Wr_TIM0_Timer1IntClr_TIMER1INTCLR(x) WriteRegBits(TIM0_TIMER1INTCLR,0x1,0,x)
#define Rd_TIM0_Timer1IntClr_TIMER1INTCLR(x) ReadRegBits(TIM0_TIMER1INTCLR,0x1,0)
#define TIM0_TIMER1INTCLR_TIMER1INTCLR_MASK                        0x00000001
#define TIM0_TIMER1INTCLR_TIMER1INTCLR_ALIGN                       0
#define TIM0_TIMER1INTCLR_TIMER1INTCLR_BITS                        1
#define TIM0_TIMER1INTCLR_TIMER1INTCLR_SHIFT                       0


/****************************************************************************
 * TIM0 :: Timer1RIS
 ***************************************************************************/
/* TIM0 :: Timer1RIS :: reserved0 [31:01] */
#define TIM0_TIMER1RIS_RESERVED0_MASK                              0xfffffffe
#define TIM0_TIMER1RIS_RESERVED0_ALIGN                             0
#define TIM0_TIMER1RIS_RESERVED0_BITS                              31
#define TIM0_TIMER1RIS_RESERVED0_SHIFT                             1

/* TIM0 :: Timer1RIS :: Timer1RIS [00:00] */
#define Wr_TIM0_Timer1RIS_Timer1RIS(x) WriteRegBits(TIM0_TIMER1RIS,0x1,0,x)
#define Rd_TIM0_Timer1RIS_Timer1RIS(x) ReadRegBits(TIM0_TIMER1RIS,0x1,0)
#define TIM0_TIMER1RIS_TIMER1RIS_MASK                              0x00000001
#define TIM0_TIMER1RIS_TIMER1RIS_ALIGN                             0
#define TIM0_TIMER1RIS_TIMER1RIS_BITS                              1
#define TIM0_TIMER1RIS_TIMER1RIS_SHIFT                             0


/****************************************************************************
 * TIM0 :: Timer1MIS
 ***************************************************************************/
/* TIM0 :: Timer1MIS :: reserved0 [31:01] */
#define TIM0_TIMER1MIS_RESERVED0_MASK                              0xfffffffe
#define TIM0_TIMER1MIS_RESERVED0_ALIGN                             0
#define TIM0_TIMER1MIS_RESERVED0_BITS                              31
#define TIM0_TIMER1MIS_RESERVED0_SHIFT                             1

/* TIM0 :: Timer1MIS :: Timer1MIS [00:00] */
#define Wr_TIM0_Timer1MIS_Timer1MIS(x) WriteRegBits(TIM0_TIMER1MIS,0x1,0,x)
#define Rd_TIM0_Timer1MIS_Timer1MIS(x) ReadRegBits(TIM0_TIMER1MIS,0x1,0)
#define TIM0_TIMER1MIS_TIMER1MIS_MASK                              0x00000001
#define TIM0_TIMER1MIS_TIMER1MIS_ALIGN                             0
#define TIM0_TIMER1MIS_TIMER1MIS_BITS                              1
#define TIM0_TIMER1MIS_TIMER1MIS_SHIFT                             0


/****************************************************************************
 * TIM0 :: Timer1BGLoad
 ***************************************************************************/
/* TIM0 :: Timer1BGLoad :: TIMER1BGLoad [31:00] */
#define Wr_TIM0_Timer1BGLoad_TIMER1BGLoad(x) WriteReg(TIM0_TIMER1BGLOAD,x)
#define Rd_TIM0_Timer1BGLoad_TIMER1BGLoad(x) ReadReg(TIM0_TIMER1BGLOAD)
#define TIM0_TIMER1BGLOAD_TIMER1BGLOAD_MASK                        0xffffffff
#define TIM0_TIMER1BGLOAD_TIMER1BGLOAD_ALIGN                       0
#define TIM0_TIMER1BGLOAD_TIMER1BGLOAD_BITS                        32
#define TIM0_TIMER1BGLOAD_TIMER1BGLOAD_SHIFT                       0


/****************************************************************************
 * TIM0 :: Timer2Load
 ***************************************************************************/
/* TIM0 :: Timer2Load :: TIMER2LOAD [31:00] */
#define Wr_TIM0_Timer2Load_TIMER2LOAD(x) WriteReg(TIM0_TIMER2LOAD,x)
#define Rd_TIM0_Timer2Load_TIMER2LOAD(x) ReadReg(TIM0_TIMER2LOAD)
#define TIM0_TIMER2LOAD_TIMER2LOAD_MASK                            0xffffffff
#define TIM0_TIMER2LOAD_TIMER2LOAD_ALIGN                           0
#define TIM0_TIMER2LOAD_TIMER2LOAD_BITS                            32
#define TIM0_TIMER2LOAD_TIMER2LOAD_SHIFT                           0


/****************************************************************************
 * TIM0 :: Timer2Value
 ***************************************************************************/
/* TIM0 :: Timer2Value :: TIMER2VALUE [31:00] */
#define Wr_TIM0_Timer2Value_TIMER2VALUE(x) WriteReg(TIM0_TIMER2VALUE,x)
#define Rd_TIM0_Timer2Value_TIMER2VALUE(x) ReadReg(TIM0_TIMER2VALUE)
#define TIM0_TIMER2VALUE_TIMER2VALUE_MASK                          0xffffffff
#define TIM0_TIMER2VALUE_TIMER2VALUE_ALIGN                         0
#define TIM0_TIMER2VALUE_TIMER2VALUE_BITS                          32
#define TIM0_TIMER2VALUE_TIMER2VALUE_SHIFT                         0


/****************************************************************************
 * TIM0 :: Timer2Control
 ***************************************************************************/
/* TIM0 :: Timer2Control :: reserved0 [31:08] */
#define TIM0_TIMER2CONTROL_RESERVED0_MASK                          0xffffff00
#define TIM0_TIMER2CONTROL_RESERVED0_ALIGN                         0
#define TIM0_TIMER2CONTROL_RESERVED0_BITS                          24
#define TIM0_TIMER2CONTROL_RESERVED0_SHIFT                         8

/* TIM0 :: Timer2Control :: Timer2En [07:07] */
#define Wr_TIM0_Timer2Control_Timer2En(x) WriteRegBits(TIM0_TIMER2CONTROL,0x80,7,x)
#define Rd_TIM0_Timer2Control_Timer2En(x) ReadRegBits(TIM0_TIMER2CONTROL,0x80,7)
#define TIM0_TIMER2CONTROL_TIMER2EN_MASK                           0x00000080
#define TIM0_TIMER2CONTROL_TIMER2EN_ALIGN                          0
#define TIM0_TIMER2CONTROL_TIMER2EN_BITS                           1
#define TIM0_TIMER2CONTROL_TIMER2EN_SHIFT                          7

/* TIM0 :: Timer2Control :: Timer2Mode [06:06] */
#define Wr_TIM0_Timer2Control_Timer2Mode(x) WriteRegBits(TIM0_TIMER2CONTROL,0x40,6,x)
#define Rd_TIM0_Timer2Control_Timer2Mode(x) ReadRegBits(TIM0_TIMER2CONTROL,0x40,6)
#define TIM0_TIMER2CONTROL_TIMER2MODE_MASK                         0x00000040
#define TIM0_TIMER2CONTROL_TIMER2MODE_ALIGN                        0
#define TIM0_TIMER2CONTROL_TIMER2MODE_BITS                         1
#define TIM0_TIMER2CONTROL_TIMER2MODE_SHIFT                        6

/* TIM0 :: Timer2Control :: IntEnable2 [05:05] */
#define Wr_TIM0_Timer2Control_IntEnable2(x) WriteRegBits(TIM0_TIMER2CONTROL,0x20,5,x)
#define Rd_TIM0_Timer2Control_IntEnable2(x) ReadRegBits(TIM0_TIMER2CONTROL,0x20,5)
#define TIM0_TIMER2CONTROL_INTENABLE2_MASK                         0x00000020
#define TIM0_TIMER2CONTROL_INTENABLE2_ALIGN                        0
#define TIM0_TIMER2CONTROL_INTENABLE2_BITS                         1
#define TIM0_TIMER2CONTROL_INTENABLE2_SHIFT                        5

/* TIM0 :: Timer2Control :: reserved1 [04:04] */
#define TIM0_TIMER2CONTROL_RESERVED1_MASK                          0x00000010
#define TIM0_TIMER2CONTROL_RESERVED1_ALIGN                         0
#define TIM0_TIMER2CONTROL_RESERVED1_BITS                          1
#define TIM0_TIMER2CONTROL_RESERVED1_SHIFT                         4

/* TIM0 :: Timer2Control :: Timer2Pre [03:02] */
#define Wr_TIM0_Timer2Control_Timer2Pre(x) WriteRegBits(TIM0_TIMER2CONTROL,0xc,2,x)
#define Rd_TIM0_Timer2Control_Timer2Pre(x) ReadRegBits(TIM0_TIMER2CONTROL,0xc,2)
#define TIM0_TIMER2CONTROL_TIMER2PRE_MASK                          0x0000000c
#define TIM0_TIMER2CONTROL_TIMER2PRE_ALIGN                         0
#define TIM0_TIMER2CONTROL_TIMER2PRE_BITS                          2
#define TIM0_TIMER2CONTROL_TIMER2PRE_SHIFT                         2

/* TIM0 :: Timer2Control :: Timer2Size [01:01] */
#define Wr_TIM0_Timer2Control_Timer2Size(x) WriteRegBits(TIM0_TIMER2CONTROL,0x2,1,x)
#define Rd_TIM0_Timer2Control_Timer2Size(x) ReadRegBits(TIM0_TIMER2CONTROL,0x2,1)
#define TIM0_TIMER2CONTROL_TIMER2SIZE_MASK                         0x00000002
#define TIM0_TIMER2CONTROL_TIMER2SIZE_ALIGN                        0
#define TIM0_TIMER2CONTROL_TIMER2SIZE_BITS                         1
#define TIM0_TIMER2CONTROL_TIMER2SIZE_SHIFT                        1

/* TIM0 :: Timer2Control :: OneShot_Timer2 [00:00] */
#define Wr_TIM0_Timer2Control_OneShot_Timer2(x) WriteRegBits(TIM0_TIMER2CONTROL,0x1,0,x)
#define Rd_TIM0_Timer2Control_OneShot_Timer2(x) ReadRegBits(TIM0_TIMER2CONTROL,0x1,0)
#define TIM0_TIMER2CONTROL_ONESHOT_TIMER2_MASK                     0x00000001
#define TIM0_TIMER2CONTROL_ONESHOT_TIMER2_ALIGN                    0
#define TIM0_TIMER2CONTROL_ONESHOT_TIMER2_BITS                     1
#define TIM0_TIMER2CONTROL_ONESHOT_TIMER2_SHIFT                    0


/****************************************************************************
 * TIM0 :: Timer2IntClr
 ***************************************************************************/
/* TIM0 :: Timer2IntClr :: reserved0 [31:01] */
#define TIM0_TIMER2INTCLR_RESERVED0_MASK                           0xfffffffe
#define TIM0_TIMER2INTCLR_RESERVED0_ALIGN                          0
#define TIM0_TIMER2INTCLR_RESERVED0_BITS                           31
#define TIM0_TIMER2INTCLR_RESERVED0_SHIFT                          1

/* TIM0 :: Timer2IntClr :: TIMER2INTCLR [00:00] */
#define Wr_TIM0_Timer2IntClr_TIMER2INTCLR(x) WriteRegBits(TIM0_TIMER2INTCLR,0x1,0,x)
#define Rd_TIM0_Timer2IntClr_TIMER2INTCLR(x) ReadRegBits(TIM0_TIMER2INTCLR,0x1,0)
#define TIM0_TIMER2INTCLR_TIMER2INTCLR_MASK                        0x00000001
#define TIM0_TIMER2INTCLR_TIMER2INTCLR_ALIGN                       0
#define TIM0_TIMER2INTCLR_TIMER2INTCLR_BITS                        1
#define TIM0_TIMER2INTCLR_TIMER2INTCLR_SHIFT                       0


/****************************************************************************
 * TIM0 :: Timer2RIS
 ***************************************************************************/
/* TIM0 :: Timer2RIS :: reserved0 [31:01] */
#define TIM0_TIMER2RIS_RESERVED0_MASK                              0xfffffffe
#define TIM0_TIMER2RIS_RESERVED0_ALIGN                             0
#define TIM0_TIMER2RIS_RESERVED0_BITS                              31
#define TIM0_TIMER2RIS_RESERVED0_SHIFT                             1

/* TIM0 :: Timer2RIS :: Timer2RIS [00:00] */
#define Wr_TIM0_Timer2RIS_Timer2RIS(x) WriteRegBits(TIM0_TIMER2RIS,0x1,0,x)
#define Rd_TIM0_Timer2RIS_Timer2RIS(x) ReadRegBits(TIM0_TIMER2RIS,0x1,0)
#define TIM0_TIMER2RIS_TIMER2RIS_MASK                              0x00000001
#define TIM0_TIMER2RIS_TIMER2RIS_ALIGN                             0
#define TIM0_TIMER2RIS_TIMER2RIS_BITS                              1
#define TIM0_TIMER2RIS_TIMER2RIS_SHIFT                             0


/****************************************************************************
 * TIM0 :: Timer2MIS
 ***************************************************************************/
/* TIM0 :: Timer2MIS :: reserved0 [31:01] */
#define TIM0_TIMER2MIS_RESERVED0_MASK                              0xfffffffe
#define TIM0_TIMER2MIS_RESERVED0_ALIGN                             0
#define TIM0_TIMER2MIS_RESERVED0_BITS                              31
#define TIM0_TIMER2MIS_RESERVED0_SHIFT                             1

/* TIM0 :: Timer2MIS :: Timer2MIS [00:00] */
#define Wr_TIM0_Timer2MIS_Timer2MIS(x) WriteRegBits(TIM0_TIMER2MIS,0x1,0,x)
#define Rd_TIM0_Timer2MIS_Timer2MIS(x) ReadRegBits(TIM0_TIMER2MIS,0x1,0)
#define TIM0_TIMER2MIS_TIMER2MIS_MASK                              0x00000001
#define TIM0_TIMER2MIS_TIMER2MIS_ALIGN                             0
#define TIM0_TIMER2MIS_TIMER2MIS_BITS                              1
#define TIM0_TIMER2MIS_TIMER2MIS_SHIFT                             0


/****************************************************************************
 * TIM0 :: Timer2BGLoad
 ***************************************************************************/
/* TIM0 :: Timer2BGLoad :: TIMER2BGLoad [31:00] */
#define Wr_TIM0_Timer2BGLoad_TIMER2BGLoad(x) WriteReg(TIM0_TIMER2BGLOAD,x)
#define Rd_TIM0_Timer2BGLoad_TIMER2BGLoad(x) ReadReg(TIM0_TIMER2BGLOAD)
#define TIM0_TIMER2BGLOAD_TIMER2BGLOAD_MASK                        0xffffffff
#define TIM0_TIMER2BGLOAD_TIMER2BGLOAD_ALIGN                       0
#define TIM0_TIMER2BGLOAD_TIMER2BGLOAD_BITS                        32
#define TIM0_TIMER2BGLOAD_TIMER2BGLOAD_SHIFT                       0


/****************************************************************************
 * TIM0 :: TimerITCR
 ***************************************************************************/
/* TIM0 :: TimerITCR :: reserved0 [31:01] */
#define TIM0_TIMERITCR_RESERVED0_MASK                              0xfffffffe
#define TIM0_TIMERITCR_RESERVED0_ALIGN                             0
#define TIM0_TIMERITCR_RESERVED0_BITS                              31
#define TIM0_TIMERITCR_RESERVED0_SHIFT                             1

/* TIM0 :: TimerITCR :: ITEN [00:00] */
#define Wr_TIM0_TimerITCR_ITEN(x) WriteRegBits(TIM0_TIMERITCR,0x1,0,x)
#define Rd_TIM0_TimerITCR_ITEN(x) ReadRegBits(TIM0_TIMERITCR,0x1,0)
#define TIM0_TIMERITCR_ITEN_MASK                                   0x00000001
#define TIM0_TIMERITCR_ITEN_ALIGN                                  0
#define TIM0_TIMERITCR_ITEN_BITS                                   1
#define TIM0_TIMERITCR_ITEN_SHIFT                                  0


/****************************************************************************
 * TIM0 :: TimerITOP
 ***************************************************************************/
/* TIM0 :: TimerITOP :: reserved0 [31:02] */
#define TIM0_TIMERITOP_RESERVED0_MASK                              0xfffffffc
#define TIM0_TIMERITOP_RESERVED0_ALIGN                             0
#define TIM0_TIMERITOP_RESERVED0_BITS                              30
#define TIM0_TIMERITOP_RESERVED0_SHIFT                             2

/* TIM0 :: TimerITOP :: TIMINT2 [01:01] */
#define Wr_TIM0_TimerITOP_TIMINT2(x) WriteRegBits(TIM0_TIMERITOP,0x2,1,x)
#define Rd_TIM0_TimerITOP_TIMINT2(x) ReadRegBits(TIM0_TIMERITOP,0x2,1)
#define TIM0_TIMERITOP_TIMINT2_MASK                                0x00000002
#define TIM0_TIMERITOP_TIMINT2_ALIGN                               0
#define TIM0_TIMERITOP_TIMINT2_BITS                                1
#define TIM0_TIMERITOP_TIMINT2_SHIFT                               1

/* TIM0 :: TimerITOP :: TIMINT1 [00:00] */
#define Wr_TIM0_TimerITOP_TIMINT1(x) WriteRegBits(TIM0_TIMERITOP,0x1,0,x)
#define Rd_TIM0_TimerITOP_TIMINT1(x) ReadRegBits(TIM0_TIMERITOP,0x1,0)
#define TIM0_TIMERITOP_TIMINT1_MASK                                0x00000001
#define TIM0_TIMERITOP_TIMINT1_ALIGN                               0
#define TIM0_TIMERITOP_TIMINT1_BITS                                1
#define TIM0_TIMERITOP_TIMINT1_SHIFT                               0


/****************************************************************************
 * TIM0 :: TimerPeriphID0
 ***************************************************************************/
/* TIM0 :: TimerPeriphID0 :: reserved0 [31:08] */
#define TIM0_TIMERPERIPHID0_RESERVED0_MASK                         0xffffff00
#define TIM0_TIMERPERIPHID0_RESERVED0_ALIGN                        0
#define TIM0_TIMERPERIPHID0_RESERVED0_BITS                         24
#define TIM0_TIMERPERIPHID0_RESERVED0_SHIFT                        8

/* TIM0 :: TimerPeriphID0 :: PartNumber0 [07:00] */
#define Wr_TIM0_TimerPeriphID0_PartNumber0(x) WriteRegBits(TIM0_TIMERPERIPHID0,0xff,0,x)
#define Rd_TIM0_TimerPeriphID0_PartNumber0(x) ReadRegBits(TIM0_TIMERPERIPHID0,0xff,0)
#define TIM0_TIMERPERIPHID0_PARTNUMBER0_MASK                       0x000000ff
#define TIM0_TIMERPERIPHID0_PARTNUMBER0_ALIGN                      0
#define TIM0_TIMERPERIPHID0_PARTNUMBER0_BITS                       8
#define TIM0_TIMERPERIPHID0_PARTNUMBER0_SHIFT                      0


/****************************************************************************
 * TIM0 :: TimerPeriphID1
 ***************************************************************************/
/* TIM0 :: TimerPeriphID1 :: reserved0 [31:08] */
#define TIM0_TIMERPERIPHID1_RESERVED0_MASK                         0xffffff00
#define TIM0_TIMERPERIPHID1_RESERVED0_ALIGN                        0
#define TIM0_TIMERPERIPHID1_RESERVED0_BITS                         24
#define TIM0_TIMERPERIPHID1_RESERVED0_SHIFT                        8

/* TIM0 :: TimerPeriphID1 :: Designer0 [07:04] */
#define Wr_TIM0_TimerPeriphID1_Designer0(x) WriteRegBits(TIM0_TIMERPERIPHID1,0xf0,4,x)
#define Rd_TIM0_TimerPeriphID1_Designer0(x) ReadRegBits(TIM0_TIMERPERIPHID1,0xf0,4)
#define TIM0_TIMERPERIPHID1_DESIGNER0_MASK                         0x000000f0
#define TIM0_TIMERPERIPHID1_DESIGNER0_ALIGN                        0
#define TIM0_TIMERPERIPHID1_DESIGNER0_BITS                         4
#define TIM0_TIMERPERIPHID1_DESIGNER0_SHIFT                        4

/* TIM0 :: TimerPeriphID1 :: PartNumber1 [03:00] */
#define Wr_TIM0_TimerPeriphID1_PartNumber1(x) WriteRegBits(TIM0_TIMERPERIPHID1,0xf,0,x)
#define Rd_TIM0_TimerPeriphID1_PartNumber1(x) ReadRegBits(TIM0_TIMERPERIPHID1,0xf,0)
#define TIM0_TIMERPERIPHID1_PARTNUMBER1_MASK                       0x0000000f
#define TIM0_TIMERPERIPHID1_PARTNUMBER1_ALIGN                      0
#define TIM0_TIMERPERIPHID1_PARTNUMBER1_BITS                       4
#define TIM0_TIMERPERIPHID1_PARTNUMBER1_SHIFT                      0


/****************************************************************************
 * TIM0 :: TimerPeriphID2
 ***************************************************************************/
/* TIM0 :: TimerPeriphID2 :: reserved0 [31:08] */
#define TIM0_TIMERPERIPHID2_RESERVED0_MASK                         0xffffff00
#define TIM0_TIMERPERIPHID2_RESERVED0_ALIGN                        0
#define TIM0_TIMERPERIPHID2_RESERVED0_BITS                         24
#define TIM0_TIMERPERIPHID2_RESERVED0_SHIFT                        8

/* TIM0 :: TimerPeriphID2 :: Revision [07:04] */
#define Wr_TIM0_TimerPeriphID2_Revision(x) WriteRegBits(TIM0_TIMERPERIPHID2,0xf0,4,x)
#define Rd_TIM0_TimerPeriphID2_Revision(x) ReadRegBits(TIM0_TIMERPERIPHID2,0xf0,4)
#define TIM0_TIMERPERIPHID2_REVISION_MASK                          0x000000f0
#define TIM0_TIMERPERIPHID2_REVISION_ALIGN                         0
#define TIM0_TIMERPERIPHID2_REVISION_BITS                          4
#define TIM0_TIMERPERIPHID2_REVISION_SHIFT                         4

/* TIM0 :: TimerPeriphID2 :: Designer1 [03:00] */
#define Wr_TIM0_TimerPeriphID2_Designer1(x) WriteRegBits(TIM0_TIMERPERIPHID2,0xf,0,x)
#define Rd_TIM0_TimerPeriphID2_Designer1(x) ReadRegBits(TIM0_TIMERPERIPHID2,0xf,0)
#define TIM0_TIMERPERIPHID2_DESIGNER1_MASK                         0x0000000f
#define TIM0_TIMERPERIPHID2_DESIGNER1_ALIGN                        0
#define TIM0_TIMERPERIPHID2_DESIGNER1_BITS                         4
#define TIM0_TIMERPERIPHID2_DESIGNER1_SHIFT                        0


/****************************************************************************
 * TIM0 :: TimerPeriphID3
 ***************************************************************************/
/* TIM0 :: TimerPeriphID3 :: reserved0 [31:08] */
#define TIM0_TIMERPERIPHID3_RESERVED0_MASK                         0xffffff00
#define TIM0_TIMERPERIPHID3_RESERVED0_ALIGN                        0
#define TIM0_TIMERPERIPHID3_RESERVED0_BITS                         24
#define TIM0_TIMERPERIPHID3_RESERVED0_SHIFT                        8

/* TIM0 :: TimerPeriphID3 :: Configuration [07:00] */
#define Wr_TIM0_TimerPeriphID3_Configuration(x) WriteRegBits(TIM0_TIMERPERIPHID3,0xff,0,x)
#define Rd_TIM0_TimerPeriphID3_Configuration(x) ReadRegBits(TIM0_TIMERPERIPHID3,0xff,0)
#define TIM0_TIMERPERIPHID3_CONFIGURATION_MASK                     0x000000ff
#define TIM0_TIMERPERIPHID3_CONFIGURATION_ALIGN                    0
#define TIM0_TIMERPERIPHID3_CONFIGURATION_BITS                     8
#define TIM0_TIMERPERIPHID3_CONFIGURATION_SHIFT                    0


/****************************************************************************
 * TIM0 :: TimerPCellID0
 ***************************************************************************/
/* TIM0 :: TimerPCellID0 :: reserved0 [31:08] */
#define TIM0_TIMERPCELLID0_RESERVED0_MASK                          0xffffff00
#define TIM0_TIMERPCELLID0_RESERVED0_ALIGN                         0
#define TIM0_TIMERPCELLID0_RESERVED0_BITS                          24
#define TIM0_TIMERPCELLID0_RESERVED0_SHIFT                         8

/* TIM0 :: TimerPCellID0 :: TimerPCellID0 [07:00] */
#define Wr_TIM0_TimerPCellID0_TimerPCellID0(x) WriteRegBits(TIM0_TIMERPCELLID0,0xff,0,x)
#define Rd_TIM0_TimerPCellID0_TimerPCellID0(x) ReadRegBits(TIM0_TIMERPCELLID0,0xff,0)
#define TIM0_TIMERPCELLID0_TIMERPCELLID0_MASK                      0x000000ff
#define TIM0_TIMERPCELLID0_TIMERPCELLID0_ALIGN                     0
#define TIM0_TIMERPCELLID0_TIMERPCELLID0_BITS                      8
#define TIM0_TIMERPCELLID0_TIMERPCELLID0_SHIFT                     0


/****************************************************************************
 * TIM0 :: TimerPCellID1
 ***************************************************************************/
/* TIM0 :: TimerPCellID1 :: reserved0 [31:08] */
#define TIM0_TIMERPCELLID1_RESERVED0_MASK                          0xffffff00
#define TIM0_TIMERPCELLID1_RESERVED0_ALIGN                         0
#define TIM0_TIMERPCELLID1_RESERVED0_BITS                          24
#define TIM0_TIMERPCELLID1_RESERVED0_SHIFT                         8

/* TIM0 :: TimerPCellID1 :: TimerPCellID1 [07:00] */
#define Wr_TIM0_TimerPCellID1_TimerPCellID1(x) WriteRegBits(TIM0_TIMERPCELLID1,0xff,0,x)
#define Rd_TIM0_TimerPCellID1_TimerPCellID1(x) ReadRegBits(TIM0_TIMERPCELLID1,0xff,0)
#define TIM0_TIMERPCELLID1_TIMERPCELLID1_MASK                      0x000000ff
#define TIM0_TIMERPCELLID1_TIMERPCELLID1_ALIGN                     0
#define TIM0_TIMERPCELLID1_TIMERPCELLID1_BITS                      8
#define TIM0_TIMERPCELLID1_TIMERPCELLID1_SHIFT                     0


/****************************************************************************
 * TIM0 :: TimerPCellID2
 ***************************************************************************/
/* TIM0 :: TimerPCellID2 :: reserved0 [31:08] */
#define TIM0_TIMERPCELLID2_RESERVED0_MASK                          0xffffff00
#define TIM0_TIMERPCELLID2_RESERVED0_ALIGN                         0
#define TIM0_TIMERPCELLID2_RESERVED0_BITS                          24
#define TIM0_TIMERPCELLID2_RESERVED0_SHIFT                         8

/* TIM0 :: TimerPCellID2 :: TimerPCellID2 [07:00] */
#define Wr_TIM0_TimerPCellID2_TimerPCellID2(x) WriteRegBits(TIM0_TIMERPCELLID2,0xff,0,x)
#define Rd_TIM0_TimerPCellID2_TimerPCellID2(x) ReadRegBits(TIM0_TIMERPCELLID2,0xff,0)
#define TIM0_TIMERPCELLID2_TIMERPCELLID2_MASK                      0x000000ff
#define TIM0_TIMERPCELLID2_TIMERPCELLID2_ALIGN                     0
#define TIM0_TIMERPCELLID2_TIMERPCELLID2_BITS                      8
#define TIM0_TIMERPCELLID2_TIMERPCELLID2_SHIFT                     0


/****************************************************************************
 * TIM0 :: TimerPCellID3
 ***************************************************************************/
/* TIM0 :: TimerPCellID3 :: reserved0 [31:08] */
#define TIM0_TIMERPCELLID3_RESERVED0_MASK                          0xffffff00
#define TIM0_TIMERPCELLID3_RESERVED0_ALIGN                         0
#define TIM0_TIMERPCELLID3_RESERVED0_BITS                          24
#define TIM0_TIMERPCELLID3_RESERVED0_SHIFT                         8

/* TIM0 :: TimerPCellID3 :: TimerPCellID3 [07:00] */
#define Wr_TIM0_TimerPCellID3_TimerPCellID3(x) WriteRegBits(TIM0_TIMERPCELLID3,0xff,0,x)
#define Rd_TIM0_TimerPCellID3_TimerPCellID3(x) ReadRegBits(TIM0_TIMERPCELLID3,0xff,0)
#define TIM0_TIMERPCELLID3_TIMERPCELLID3_MASK                      0x000000ff
#define TIM0_TIMERPCELLID3_TIMERPCELLID3_ALIGN                     0
#define TIM0_TIMERPCELLID3_TIMERPCELLID3_BITS                      8
#define TIM0_TIMERPCELLID3_TIMERPCELLID3_SHIFT                     0


/****************************************************************************
 * bcm89530_sys_cfg_SPI1
 ***************************************************************************/
/****************************************************************************
 * SPI1 :: SSPCR0
 ***************************************************************************/
/* SPI1 :: SSPCR0 :: reserved0 [31:16] */
#define SPI1_SSPCR0_RESERVED0_MASK                                 0xffff0000
#define SPI1_SSPCR0_RESERVED0_ALIGN                                0
#define SPI1_SSPCR0_RESERVED0_BITS                                 16
#define SPI1_SSPCR0_RESERVED0_SHIFT                                16

/* SPI1 :: SSPCR0 :: SCR [15:08] */
#define Wr_SPI1_SSPCR0_SCR(x) WriteRegBits(SPI1_SSPCR0,0xff00,8,x)
#define Rd_SPI1_SSPCR0_SCR(x) ReadRegBits(SPI1_SSPCR0,0xff00,8)
#define SPI1_SSPCR0_SCR_MASK                                       0x0000ff00
#define SPI1_SSPCR0_SCR_ALIGN                                      0
#define SPI1_SSPCR0_SCR_BITS                                       8
#define SPI1_SSPCR0_SCR_SHIFT                                      8

/* SPI1 :: SSPCR0 :: SPH [07:07] */
#define Wr_SPI1_SSPCR0_SPH(x) WriteRegBits(SPI1_SSPCR0,0x80,7,x)
#define Rd_SPI1_SSPCR0_SPH(x) ReadRegBits(SPI1_SSPCR0,0x80,7)
#define SPI1_SSPCR0_SPH_MASK                                       0x00000080
#define SPI1_SSPCR0_SPH_ALIGN                                      0
#define SPI1_SSPCR0_SPH_BITS                                       1
#define SPI1_SSPCR0_SPH_SHIFT                                      7

/* SPI1 :: SSPCR0 :: SPO [06:06] */
#define Wr_SPI1_SSPCR0_SPO(x) WriteRegBits(SPI1_SSPCR0,0x40,6,x)
#define Rd_SPI1_SSPCR0_SPO(x) ReadRegBits(SPI1_SSPCR0,0x40,6)
#define SPI1_SSPCR0_SPO_MASK                                       0x00000040
#define SPI1_SSPCR0_SPO_ALIGN                                      0
#define SPI1_SSPCR0_SPO_BITS                                       1
#define SPI1_SSPCR0_SPO_SHIFT                                      6

/* SPI1 :: SSPCR0 :: FRF [05:04] */
#define Wr_SPI1_SSPCR0_FRF(x) WriteRegBits(SPI1_SSPCR0,0x30,4,x)
#define Rd_SPI1_SSPCR0_FRF(x) ReadRegBits(SPI1_SSPCR0,0x30,4)
#define SPI1_SSPCR0_FRF_MASK                                       0x00000030
#define SPI1_SSPCR0_FRF_ALIGN                                      0
#define SPI1_SSPCR0_FRF_BITS                                       2
#define SPI1_SSPCR0_FRF_SHIFT                                      4

/* SPI1 :: SSPCR0 :: DSS [03:00] */
#define Wr_SPI1_SSPCR0_DSS(x) WriteRegBits(SPI1_SSPCR0,0xf,0,x)
#define Rd_SPI1_SSPCR0_DSS(x) ReadRegBits(SPI1_SSPCR0,0xf,0)
#define SPI1_SSPCR0_DSS_MASK                                       0x0000000f
#define SPI1_SSPCR0_DSS_ALIGN                                      0
#define SPI1_SSPCR0_DSS_BITS                                       4
#define SPI1_SSPCR0_DSS_SHIFT                                      0


/****************************************************************************
 * SPI1 :: SSPCR1
 ***************************************************************************/
/* SPI1 :: SSPCR1 :: reserved0 [31:04] */
#define SPI1_SSPCR1_RESERVED0_MASK                                 0xfffffff0
#define SPI1_SSPCR1_RESERVED0_ALIGN                                0
#define SPI1_SSPCR1_RESERVED0_BITS                                 28
#define SPI1_SSPCR1_RESERVED0_SHIFT                                4

/* SPI1 :: SSPCR1 :: SOD [03:03] */
#define Wr_SPI1_SSPCR1_SOD(x) WriteRegBits(SPI1_SSPCR1,0x8,3,x)
#define Rd_SPI1_SSPCR1_SOD(x) ReadRegBits(SPI1_SSPCR1,0x8,3)
#define SPI1_SSPCR1_SOD_MASK                                       0x00000008
#define SPI1_SSPCR1_SOD_ALIGN                                      0
#define SPI1_SSPCR1_SOD_BITS                                       1
#define SPI1_SSPCR1_SOD_SHIFT                                      3

/* SPI1 :: SSPCR1 :: MS [02:02] */
#define Wr_SPI1_SSPCR1_MS(x) WriteRegBits(SPI1_SSPCR1,0x4,2,x)
#define Rd_SPI1_SSPCR1_MS(x) ReadRegBits(SPI1_SSPCR1,0x4,2)
#define SPI1_SSPCR1_MS_MASK                                        0x00000004
#define SPI1_SSPCR1_MS_ALIGN                                       0
#define SPI1_SSPCR1_MS_BITS                                        1
#define SPI1_SSPCR1_MS_SHIFT                                       2

/* SPI1 :: SSPCR1 :: SSE [01:01] */
#define Wr_SPI1_SSPCR1_SSE(x) WriteRegBits(SPI1_SSPCR1,0x2,1,x)
#define Rd_SPI1_SSPCR1_SSE(x) ReadRegBits(SPI1_SSPCR1,0x2,1)
#define SPI1_SSPCR1_SSE_MASK                                       0x00000002
#define SPI1_SSPCR1_SSE_ALIGN                                      0
#define SPI1_SSPCR1_SSE_BITS                                       1
#define SPI1_SSPCR1_SSE_SHIFT                                      1

/* SPI1 :: SSPCR1 :: reserved1 [00:00] */
#define SPI1_SSPCR1_RESERVED1_MASK                                 0x00000001
#define SPI1_SSPCR1_RESERVED1_ALIGN                                0
#define SPI1_SSPCR1_RESERVED1_BITS                                 1
#define SPI1_SSPCR1_RESERVED1_SHIFT                                0


/****************************************************************************
 * SPI1 :: SSPDR
 ***************************************************************************/
/* SPI1 :: SSPDR :: reserved0 [31:16] */
#define SPI1_SSPDR_RESERVED0_MASK                                  0xffff0000
#define SPI1_SSPDR_RESERVED0_ALIGN                                 0
#define SPI1_SSPDR_RESERVED0_BITS                                  16
#define SPI1_SSPDR_RESERVED0_SHIFT                                 16

/* SPI1 :: SSPDR :: DATA [15:00] */
#define Wr_SPI1_SSPDR_DATA(x) WriteRegBits(SPI1_SSPDR,0xffff,0,x)
#define Rd_SPI1_SSPDR_DATA(x) ReadRegBits(SPI1_SSPDR,0xffff,0)
#define SPI1_SSPDR_DATA_MASK                                       0x0000ffff
#define SPI1_SSPDR_DATA_ALIGN                                      0
#define SPI1_SSPDR_DATA_BITS                                       16
#define SPI1_SSPDR_DATA_SHIFT                                      0


/****************************************************************************
 * SPI1 :: SSPSR
 ***************************************************************************/
/* SPI1 :: SSPSR :: reserved0 [31:05] */
#define SPI1_SSPSR_RESERVED0_MASK                                  0xffffffe0
#define SPI1_SSPSR_RESERVED0_ALIGN                                 0
#define SPI1_SSPSR_RESERVED0_BITS                                  27
#define SPI1_SSPSR_RESERVED0_SHIFT                                 5

/* SPI1 :: SSPSR :: BSY [04:04] */
#define Wr_SPI1_SSPSR_BSY(x) WriteRegBits(SPI1_SSPSR,0x10,4,x)
#define Rd_SPI1_SSPSR_BSY(x) ReadRegBits(SPI1_SSPSR,0x10,4)
#define SPI1_SSPSR_BSY_MASK                                        0x00000010
#define SPI1_SSPSR_BSY_ALIGN                                       0
#define SPI1_SSPSR_BSY_BITS                                        1
#define SPI1_SSPSR_BSY_SHIFT                                       4

/* SPI1 :: SSPSR :: RFF [03:03] */
#define Wr_SPI1_SSPSR_RFF(x) WriteRegBits(SPI1_SSPSR,0x8,3,x)
#define Rd_SPI1_SSPSR_RFF(x) ReadRegBits(SPI1_SSPSR,0x8,3)
#define SPI1_SSPSR_RFF_MASK                                        0x00000008
#define SPI1_SSPSR_RFF_ALIGN                                       0
#define SPI1_SSPSR_RFF_BITS                                        1
#define SPI1_SSPSR_RFF_SHIFT                                       3

/* SPI1 :: SSPSR :: RNE [02:02] */
#define Wr_SPI1_SSPSR_RNE(x) WriteRegBits(SPI1_SSPSR,0x4,2,x)
#define Rd_SPI1_SSPSR_RNE(x) ReadRegBits(SPI1_SSPSR,0x4,2)
#define SPI1_SSPSR_RNE_MASK                                        0x00000004
#define SPI1_SSPSR_RNE_ALIGN                                       0
#define SPI1_SSPSR_RNE_BITS                                        1
#define SPI1_SSPSR_RNE_SHIFT                                       2

/* SPI1 :: SSPSR :: TNF [01:01] */
#define Wr_SPI1_SSPSR_TNF(x) WriteRegBits(SPI1_SSPSR,0x2,1,x)
#define Rd_SPI1_SSPSR_TNF(x) ReadRegBits(SPI1_SSPSR,0x2,1)
#define SPI1_SSPSR_TNF_MASK                                        0x00000002
#define SPI1_SSPSR_TNF_ALIGN                                       0
#define SPI1_SSPSR_TNF_BITS                                        1
#define SPI1_SSPSR_TNF_SHIFT                                       1

/* SPI1 :: SSPSR :: TFE [00:00] */
#define Wr_SPI1_SSPSR_TFE(x) WriteRegBits(SPI1_SSPSR,0x1,0,x)
#define Rd_SPI1_SSPSR_TFE(x) ReadRegBits(SPI1_SSPSR,0x1,0)
#define SPI1_SSPSR_TFE_MASK                                        0x00000001
#define SPI1_SSPSR_TFE_ALIGN                                       0
#define SPI1_SSPSR_TFE_BITS                                        1
#define SPI1_SSPSR_TFE_SHIFT                                       0


/****************************************************************************
 * SPI1 :: SSPCPSR
 ***************************************************************************/
/* SPI1 :: SSPCPSR :: reserved0 [31:08] */
#define SPI1_SSPCPSR_RESERVED0_MASK                                0xffffff00
#define SPI1_SSPCPSR_RESERVED0_ALIGN                               0
#define SPI1_SSPCPSR_RESERVED0_BITS                                24
#define SPI1_SSPCPSR_RESERVED0_SHIFT                               8

/* SPI1 :: SSPCPSR :: CPSDVSR [07:00] */
#define Wr_SPI1_SSPCPSR_CPSDVSR(x) WriteRegBits(SPI1_SSPCPSR,0xff,0,x)
#define Rd_SPI1_SSPCPSR_CPSDVSR(x) ReadRegBits(SPI1_SSPCPSR,0xff,0)
#define SPI1_SSPCPSR_CPSDVSR_MASK                                  0x000000ff
#define SPI1_SSPCPSR_CPSDVSR_ALIGN                                 0
#define SPI1_SSPCPSR_CPSDVSR_BITS                                  8
#define SPI1_SSPCPSR_CPSDVSR_SHIFT                                 0


/****************************************************************************
 * SPI1 :: SSPIMSC
 ***************************************************************************/
/* SPI1 :: SSPIMSC :: reserved0 [31:04] */
#define SPI1_SSPIMSC_RESERVED0_MASK                                0xfffffff0
#define SPI1_SSPIMSC_RESERVED0_ALIGN                               0
#define SPI1_SSPIMSC_RESERVED0_BITS                                28
#define SPI1_SSPIMSC_RESERVED0_SHIFT                               4

/* SPI1 :: SSPIMSC :: TXIM [03:03] */
#define Wr_SPI1_SSPIMSC_TXIM(x) WriteRegBits(SPI1_SSPIMSC,0x8,3,x)
#define Rd_SPI1_SSPIMSC_TXIM(x) ReadRegBits(SPI1_SSPIMSC,0x8,3)
#define SPI1_SSPIMSC_TXIM_MASK                                     0x00000008
#define SPI1_SSPIMSC_TXIM_ALIGN                                    0
#define SPI1_SSPIMSC_TXIM_BITS                                     1
#define SPI1_SSPIMSC_TXIM_SHIFT                                    3

/* SPI1 :: SSPIMSC :: RXIM [02:02] */
#define Wr_SPI1_SSPIMSC_RXIM(x) WriteRegBits(SPI1_SSPIMSC,0x4,2,x)
#define Rd_SPI1_SSPIMSC_RXIM(x) ReadRegBits(SPI1_SSPIMSC,0x4,2)
#define SPI1_SSPIMSC_RXIM_MASK                                     0x00000004
#define SPI1_SSPIMSC_RXIM_ALIGN                                    0
#define SPI1_SSPIMSC_RXIM_BITS                                     1
#define SPI1_SSPIMSC_RXIM_SHIFT                                    2

/* SPI1 :: SSPIMSC :: RTIM [01:01] */
#define Wr_SPI1_SSPIMSC_RTIM(x) WriteRegBits(SPI1_SSPIMSC,0x2,1,x)
#define Rd_SPI1_SSPIMSC_RTIM(x) ReadRegBits(SPI1_SSPIMSC,0x2,1)
#define SPI1_SSPIMSC_RTIM_MASK                                     0x00000002
#define SPI1_SSPIMSC_RTIM_ALIGN                                    0
#define SPI1_SSPIMSC_RTIM_BITS                                     1
#define SPI1_SSPIMSC_RTIM_SHIFT                                    1

/* SPI1 :: SSPIMSC :: RORIM [00:00] */
#define Wr_SPI1_SSPIMSC_RORIM(x) WriteRegBits(SPI1_SSPIMSC,0x1,0,x)
#define Rd_SPI1_SSPIMSC_RORIM(x) ReadRegBits(SPI1_SSPIMSC,0x1,0)
#define SPI1_SSPIMSC_RORIM_MASK                                    0x00000001
#define SPI1_SSPIMSC_RORIM_ALIGN                                   0
#define SPI1_SSPIMSC_RORIM_BITS                                    1
#define SPI1_SSPIMSC_RORIM_SHIFT                                   0


/****************************************************************************
 * SPI1 :: SSPRIS
 ***************************************************************************/
/* SPI1 :: SSPRIS :: reserved0 [31:04] */
#define SPI1_SSPRIS_RESERVED0_MASK                                 0xfffffff0
#define SPI1_SSPRIS_RESERVED0_ALIGN                                0
#define SPI1_SSPRIS_RESERVED0_BITS                                 28
#define SPI1_SSPRIS_RESERVED0_SHIFT                                4

/* SPI1 :: SSPRIS :: TXRIS [03:03] */
#define Wr_SPI1_SSPRIS_TXRIS(x) WriteRegBits(SPI1_SSPRIS,0x8,3,x)
#define Rd_SPI1_SSPRIS_TXRIS(x) ReadRegBits(SPI1_SSPRIS,0x8,3)
#define SPI1_SSPRIS_TXRIS_MASK                                     0x00000008
#define SPI1_SSPRIS_TXRIS_ALIGN                                    0
#define SPI1_SSPRIS_TXRIS_BITS                                     1
#define SPI1_SSPRIS_TXRIS_SHIFT                                    3

/* SPI1 :: SSPRIS :: RXRIS [02:02] */
#define Wr_SPI1_SSPRIS_RXRIS(x) WriteRegBits(SPI1_SSPRIS,0x4,2,x)
#define Rd_SPI1_SSPRIS_RXRIS(x) ReadRegBits(SPI1_SSPRIS,0x4,2)
#define SPI1_SSPRIS_RXRIS_MASK                                     0x00000004
#define SPI1_SSPRIS_RXRIS_ALIGN                                    0
#define SPI1_SSPRIS_RXRIS_BITS                                     1
#define SPI1_SSPRIS_RXRIS_SHIFT                                    2

/* SPI1 :: SSPRIS :: RTRIS [01:01] */
#define Wr_SPI1_SSPRIS_RTRIS(x) WriteRegBits(SPI1_SSPRIS,0x2,1,x)
#define Rd_SPI1_SSPRIS_RTRIS(x) ReadRegBits(SPI1_SSPRIS,0x2,1)
#define SPI1_SSPRIS_RTRIS_MASK                                     0x00000002
#define SPI1_SSPRIS_RTRIS_ALIGN                                    0
#define SPI1_SSPRIS_RTRIS_BITS                                     1
#define SPI1_SSPRIS_RTRIS_SHIFT                                    1

/* SPI1 :: SSPRIS :: RORRIS [00:00] */
#define Wr_SPI1_SSPRIS_RORRIS(x) WriteRegBits(SPI1_SSPRIS,0x1,0,x)
#define Rd_SPI1_SSPRIS_RORRIS(x) ReadRegBits(SPI1_SSPRIS,0x1,0)
#define SPI1_SSPRIS_RORRIS_MASK                                    0x00000001
#define SPI1_SSPRIS_RORRIS_ALIGN                                   0
#define SPI1_SSPRIS_RORRIS_BITS                                    1
#define SPI1_SSPRIS_RORRIS_SHIFT                                   0


/****************************************************************************
 * SPI1 :: SSPMIS
 ***************************************************************************/
/* SPI1 :: SSPMIS :: reserved0 [31:04] */
#define SPI1_SSPMIS_RESERVED0_MASK                                 0xfffffff0
#define SPI1_SSPMIS_RESERVED0_ALIGN                                0
#define SPI1_SSPMIS_RESERVED0_BITS                                 28
#define SPI1_SSPMIS_RESERVED0_SHIFT                                4

/* SPI1 :: SSPMIS :: TXMIS [03:03] */
#define Wr_SPI1_SSPMIS_TXMIS(x) WriteRegBits(SPI1_SSPMIS,0x8,3,x)
#define Rd_SPI1_SSPMIS_TXMIS(x) ReadRegBits(SPI1_SSPMIS,0x8,3)
#define SPI1_SSPMIS_TXMIS_MASK                                     0x00000008
#define SPI1_SSPMIS_TXMIS_ALIGN                                    0
#define SPI1_SSPMIS_TXMIS_BITS                                     1
#define SPI1_SSPMIS_TXMIS_SHIFT                                    3

/* SPI1 :: SSPMIS :: RXMIS [02:02] */
#define Wr_SPI1_SSPMIS_RXMIS(x) WriteRegBits(SPI1_SSPMIS,0x4,2,x)
#define Rd_SPI1_SSPMIS_RXMIS(x) ReadRegBits(SPI1_SSPMIS,0x4,2)
#define SPI1_SSPMIS_RXMIS_MASK                                     0x00000004
#define SPI1_SSPMIS_RXMIS_ALIGN                                    0
#define SPI1_SSPMIS_RXMIS_BITS                                     1
#define SPI1_SSPMIS_RXMIS_SHIFT                                    2

/* SPI1 :: SSPMIS :: RTMIS [01:01] */
#define Wr_SPI1_SSPMIS_RTMIS(x) WriteRegBits(SPI1_SSPMIS,0x2,1,x)
#define Rd_SPI1_SSPMIS_RTMIS(x) ReadRegBits(SPI1_SSPMIS,0x2,1)
#define SPI1_SSPMIS_RTMIS_MASK                                     0x00000002
#define SPI1_SSPMIS_RTMIS_ALIGN                                    0
#define SPI1_SSPMIS_RTMIS_BITS                                     1
#define SPI1_SSPMIS_RTMIS_SHIFT                                    1

/* SPI1 :: SSPMIS :: RORMIS [00:00] */
#define Wr_SPI1_SSPMIS_RORMIS(x) WriteRegBits(SPI1_SSPMIS,0x1,0,x)
#define Rd_SPI1_SSPMIS_RORMIS(x) ReadRegBits(SPI1_SSPMIS,0x1,0)
#define SPI1_SSPMIS_RORMIS_MASK                                    0x00000001
#define SPI1_SSPMIS_RORMIS_ALIGN                                   0
#define SPI1_SSPMIS_RORMIS_BITS                                    1
#define SPI1_SSPMIS_RORMIS_SHIFT                                   0


/****************************************************************************
 * SPI1 :: SSPICR
 ***************************************************************************/
/* SPI1 :: SSPICR :: reserved0 [31:02] */
#define SPI1_SSPICR_RESERVED0_MASK                                 0xfffffffc
#define SPI1_SSPICR_RESERVED0_ALIGN                                0
#define SPI1_SSPICR_RESERVED0_BITS                                 30
#define SPI1_SSPICR_RESERVED0_SHIFT                                2

/* SPI1 :: SSPICR :: RTIC [01:01] */
#define Wr_SPI1_SSPICR_RTIC(x) WriteRegBits(SPI1_SSPICR,0x2,1,x)
#define Rd_SPI1_SSPICR_RTIC(x) ReadRegBits(SPI1_SSPICR,0x2,1)
#define SPI1_SSPICR_RTIC_MASK                                      0x00000002
#define SPI1_SSPICR_RTIC_ALIGN                                     0
#define SPI1_SSPICR_RTIC_BITS                                      1
#define SPI1_SSPICR_RTIC_SHIFT                                     1

/* SPI1 :: SSPICR :: RORIC [00:00] */
#define Wr_SPI1_SSPICR_RORIC(x) WriteRegBits(SPI1_SSPICR,0x1,0,x)
#define Rd_SPI1_SSPICR_RORIC(x) ReadRegBits(SPI1_SSPICR,0x1,0)
#define SPI1_SSPICR_RORIC_MASK                                     0x00000001
#define SPI1_SSPICR_RORIC_ALIGN                                    0
#define SPI1_SSPICR_RORIC_BITS                                     1
#define SPI1_SSPICR_RORIC_SHIFT                                    0


/****************************************************************************
 * SPI1 :: SSPDMACR
 ***************************************************************************/
/* SPI1 :: SSPDMACR :: reserved0 [31:02] */
#define SPI1_SSPDMACR_RESERVED0_MASK                               0xfffffffc
#define SPI1_SSPDMACR_RESERVED0_ALIGN                              0
#define SPI1_SSPDMACR_RESERVED0_BITS                               30
#define SPI1_SSPDMACR_RESERVED0_SHIFT                              2

/* SPI1 :: SSPDMACR :: TXDMAE [01:01] */
#define Wr_SPI1_SSPDMACR_TXDMAE(x) WriteRegBits(SPI1_SSPDMACR,0x2,1,x)
#define Rd_SPI1_SSPDMACR_TXDMAE(x) ReadRegBits(SPI1_SSPDMACR,0x2,1)
#define SPI1_SSPDMACR_TXDMAE_MASK                                  0x00000002
#define SPI1_SSPDMACR_TXDMAE_ALIGN                                 0
#define SPI1_SSPDMACR_TXDMAE_BITS                                  1
#define SPI1_SSPDMACR_TXDMAE_SHIFT                                 1

/* SPI1 :: SSPDMACR :: RXDMAE [00:00] */
#define Wr_SPI1_SSPDMACR_RXDMAE(x) WriteRegBits(SPI1_SSPDMACR,0x1,0,x)
#define Rd_SPI1_SSPDMACR_RXDMAE(x) ReadRegBits(SPI1_SSPDMACR,0x1,0)
#define SPI1_SSPDMACR_RXDMAE_MASK                                  0x00000001
#define SPI1_SSPDMACR_RXDMAE_ALIGN                                 0
#define SPI1_SSPDMACR_RXDMAE_BITS                                  1
#define SPI1_SSPDMACR_RXDMAE_SHIFT                                 0


/****************************************************************************
 * SPI1 :: SSPPeriphID0
 ***************************************************************************/
/* SPI1 :: SSPPeriphID0 :: reserved0 [31:08] */
#define SPI1_SSPPERIPHID0_RESERVED0_MASK                           0xffffff00
#define SPI1_SSPPERIPHID0_RESERVED0_ALIGN                          0
#define SPI1_SSPPERIPHID0_RESERVED0_BITS                           24
#define SPI1_SSPPERIPHID0_RESERVED0_SHIFT                          8

/* SPI1 :: SSPPeriphID0 :: PartNumber0 [07:00] */
#define Wr_SPI1_SSPPeriphID0_PartNumber0(x) WriteRegBits(SPI1_SSPPERIPHID0,0xff,0,x)
#define Rd_SPI1_SSPPeriphID0_PartNumber0(x) ReadRegBits(SPI1_SSPPERIPHID0,0xff,0)
#define SPI1_SSPPERIPHID0_PARTNUMBER0_MASK                         0x000000ff
#define SPI1_SSPPERIPHID0_PARTNUMBER0_ALIGN                        0
#define SPI1_SSPPERIPHID0_PARTNUMBER0_BITS                         8
#define SPI1_SSPPERIPHID0_PARTNUMBER0_SHIFT                        0


/****************************************************************************
 * SPI1 :: SSPPeriphID1
 ***************************************************************************/
/* SPI1 :: SSPPeriphID1 :: reserved0 [31:08] */
#define SPI1_SSPPERIPHID1_RESERVED0_MASK                           0xffffff00
#define SPI1_SSPPERIPHID1_RESERVED0_ALIGN                          0
#define SPI1_SSPPERIPHID1_RESERVED0_BITS                           24
#define SPI1_SSPPERIPHID1_RESERVED0_SHIFT                          8

/* SPI1 :: SSPPeriphID1 :: Designer0 [07:04] */
#define Wr_SPI1_SSPPeriphID1_Designer0(x) WriteRegBits(SPI1_SSPPERIPHID1,0xf0,4,x)
#define Rd_SPI1_SSPPeriphID1_Designer0(x) ReadRegBits(SPI1_SSPPERIPHID1,0xf0,4)
#define SPI1_SSPPERIPHID1_DESIGNER0_MASK                           0x000000f0
#define SPI1_SSPPERIPHID1_DESIGNER0_ALIGN                          0
#define SPI1_SSPPERIPHID1_DESIGNER0_BITS                           4
#define SPI1_SSPPERIPHID1_DESIGNER0_SHIFT                          4

/* SPI1 :: SSPPeriphID1 :: PartNumber1 [03:00] */
#define Wr_SPI1_SSPPeriphID1_PartNumber1(x) WriteRegBits(SPI1_SSPPERIPHID1,0xf,0,x)
#define Rd_SPI1_SSPPeriphID1_PartNumber1(x) ReadRegBits(SPI1_SSPPERIPHID1,0xf,0)
#define SPI1_SSPPERIPHID1_PARTNUMBER1_MASK                         0x0000000f
#define SPI1_SSPPERIPHID1_PARTNUMBER1_ALIGN                        0
#define SPI1_SSPPERIPHID1_PARTNUMBER1_BITS                         4
#define SPI1_SSPPERIPHID1_PARTNUMBER1_SHIFT                        0


/****************************************************************************
 * SPI1 :: SSPPeriphID2
 ***************************************************************************/
/* SPI1 :: SSPPeriphID2 :: reserved0 [31:08] */
#define SPI1_SSPPERIPHID2_RESERVED0_MASK                           0xffffff00
#define SPI1_SSPPERIPHID2_RESERVED0_ALIGN                          0
#define SPI1_SSPPERIPHID2_RESERVED0_BITS                           24
#define SPI1_SSPPERIPHID2_RESERVED0_SHIFT                          8

/* SPI1 :: SSPPeriphID2 :: Revision [07:04] */
#define Wr_SPI1_SSPPeriphID2_Revision(x) WriteRegBits(SPI1_SSPPERIPHID2,0xf0,4,x)
#define Rd_SPI1_SSPPeriphID2_Revision(x) ReadRegBits(SPI1_SSPPERIPHID2,0xf0,4)
#define SPI1_SSPPERIPHID2_REVISION_MASK                            0x000000f0
#define SPI1_SSPPERIPHID2_REVISION_ALIGN                           0
#define SPI1_SSPPERIPHID2_REVISION_BITS                            4
#define SPI1_SSPPERIPHID2_REVISION_SHIFT                           4

/* SPI1 :: SSPPeriphID2 :: Designer1 [03:00] */
#define Wr_SPI1_SSPPeriphID2_Designer1(x) WriteRegBits(SPI1_SSPPERIPHID2,0xf,0,x)
#define Rd_SPI1_SSPPeriphID2_Designer1(x) ReadRegBits(SPI1_SSPPERIPHID2,0xf,0)
#define SPI1_SSPPERIPHID2_DESIGNER1_MASK                           0x0000000f
#define SPI1_SSPPERIPHID2_DESIGNER1_ALIGN                          0
#define SPI1_SSPPERIPHID2_DESIGNER1_BITS                           4
#define SPI1_SSPPERIPHID2_DESIGNER1_SHIFT                          0


/****************************************************************************
 * SPI1 :: SSPPeriphID3
 ***************************************************************************/
/* SPI1 :: SSPPeriphID3 :: reserved0 [31:08] */
#define SPI1_SSPPERIPHID3_RESERVED0_MASK                           0xffffff00
#define SPI1_SSPPERIPHID3_RESERVED0_ALIGN                          0
#define SPI1_SSPPERIPHID3_RESERVED0_BITS                           24
#define SPI1_SSPPERIPHID3_RESERVED0_SHIFT                          8

/* SPI1 :: SSPPeriphID3 :: Configuration [07:00] */
#define Wr_SPI1_SSPPeriphID3_Configuration(x) WriteRegBits(SPI1_SSPPERIPHID3,0xff,0,x)
#define Rd_SPI1_SSPPeriphID3_Configuration(x) ReadRegBits(SPI1_SSPPERIPHID3,0xff,0)
#define SPI1_SSPPERIPHID3_CONFIGURATION_MASK                       0x000000ff
#define SPI1_SSPPERIPHID3_CONFIGURATION_ALIGN                      0
#define SPI1_SSPPERIPHID3_CONFIGURATION_BITS                       8
#define SPI1_SSPPERIPHID3_CONFIGURATION_SHIFT                      0


/****************************************************************************
 * SPI1 :: SSPPCellID0
 ***************************************************************************/
/* SPI1 :: SSPPCellID0 :: reserved0 [31:08] */
#define SPI1_SSPPCELLID0_RESERVED0_MASK                            0xffffff00
#define SPI1_SSPPCELLID0_RESERVED0_ALIGN                           0
#define SPI1_SSPPCELLID0_RESERVED0_BITS                            24
#define SPI1_SSPPCELLID0_RESERVED0_SHIFT                           8

/* SPI1 :: SSPPCellID0 :: SSPPCellID0 [07:00] */
#define Wr_SPI1_SSPPCellID0_SSPPCellID0(x) WriteRegBits(SPI1_SSPPCELLID0,0xff,0,x)
#define Rd_SPI1_SSPPCellID0_SSPPCellID0(x) ReadRegBits(SPI1_SSPPCELLID0,0xff,0)
#define SPI1_SSPPCELLID0_SSPPCELLID0_MASK                          0x000000ff
#define SPI1_SSPPCELLID0_SSPPCELLID0_ALIGN                         0
#define SPI1_SSPPCELLID0_SSPPCELLID0_BITS                          8
#define SPI1_SSPPCELLID0_SSPPCELLID0_SHIFT                         0


/****************************************************************************
 * SPI1 :: SSPPCellID1
 ***************************************************************************/
/* SPI1 :: SSPPCellID1 :: reserved0 [31:08] */
#define SPI1_SSPPCELLID1_RESERVED0_MASK                            0xffffff00
#define SPI1_SSPPCELLID1_RESERVED0_ALIGN                           0
#define SPI1_SSPPCELLID1_RESERVED0_BITS                            24
#define SPI1_SSPPCELLID1_RESERVED0_SHIFT                           8

/* SPI1 :: SSPPCellID1 :: SSPPCellID1 [07:00] */
#define Wr_SPI1_SSPPCellID1_SSPPCellID1(x) WriteRegBits(SPI1_SSPPCELLID1,0xff,0,x)
#define Rd_SPI1_SSPPCellID1_SSPPCellID1(x) ReadRegBits(SPI1_SSPPCELLID1,0xff,0)
#define SPI1_SSPPCELLID1_SSPPCELLID1_MASK                          0x000000ff
#define SPI1_SSPPCELLID1_SSPPCELLID1_ALIGN                         0
#define SPI1_SSPPCELLID1_SSPPCELLID1_BITS                          8
#define SPI1_SSPPCELLID1_SSPPCELLID1_SHIFT                         0


/****************************************************************************
 * SPI1 :: SSPPCellID2
 ***************************************************************************/
/* SPI1 :: SSPPCellID2 :: reserved0 [31:08] */
#define SPI1_SSPPCELLID2_RESERVED0_MASK                            0xffffff00
#define SPI1_SSPPCELLID2_RESERVED0_ALIGN                           0
#define SPI1_SSPPCELLID2_RESERVED0_BITS                            24
#define SPI1_SSPPCELLID2_RESERVED0_SHIFT                           8

/* SPI1 :: SSPPCellID2 :: SSPPCellID2 [07:00] */
#define Wr_SPI1_SSPPCellID2_SSPPCellID2(x) WriteRegBits(SPI1_SSPPCELLID2,0xff,0,x)
#define Rd_SPI1_SSPPCellID2_SSPPCellID2(x) ReadRegBits(SPI1_SSPPCELLID2,0xff,0)
#define SPI1_SSPPCELLID2_SSPPCELLID2_MASK                          0x000000ff
#define SPI1_SSPPCELLID2_SSPPCELLID2_ALIGN                         0
#define SPI1_SSPPCELLID2_SSPPCELLID2_BITS                          8
#define SPI1_SSPPCELLID2_SSPPCELLID2_SHIFT                         0


/****************************************************************************
 * SPI1 :: SSPPCellID3
 ***************************************************************************/
/* SPI1 :: SSPPCellID3 :: reserved0 [31:08] */
#define SPI1_SSPPCELLID3_RESERVED0_MASK                            0xffffff00
#define SPI1_SSPPCELLID3_RESERVED0_ALIGN                           0
#define SPI1_SSPPCELLID3_RESERVED0_BITS                            24
#define SPI1_SSPPCELLID3_RESERVED0_SHIFT                           8

/* SPI1 :: SSPPCellID3 :: SSPPCellID3 [07:00] */
#define Wr_SPI1_SSPPCellID3_SSPPCellID3(x) WriteRegBits(SPI1_SSPPCELLID3,0xff,0,x)
#define Rd_SPI1_SSPPCellID3_SSPPCellID3(x) ReadRegBits(SPI1_SSPPCELLID3,0xff,0)
#define SPI1_SSPPCELLID3_SSPPCELLID3_MASK                          0x000000ff
#define SPI1_SSPPCELLID3_SSPPCELLID3_ALIGN                         0
#define SPI1_SSPPCELLID3_SSPPCELLID3_BITS                          8
#define SPI1_SSPPCELLID3_SSPPCELLID3_SHIFT                         0


/****************************************************************************
 * bcm89530_sys_cfg_WDT
 ***************************************************************************/
/****************************************************************************
 * WDT :: WdogLoad
 ***************************************************************************/
/* WDT :: WdogLoad :: WdogLoad [31:00] */
#define Wr_WDT_WdogLoad_WdogLoad(x) WriteReg(WDT_WDOGLOAD,x)
#define Rd_WDT_WdogLoad_WdogLoad(x) ReadReg(WDT_WDOGLOAD)
#define WDT_WDOGLOAD_WDOGLOAD_MASK                                 0xffffffff
#define WDT_WDOGLOAD_WDOGLOAD_ALIGN                                0
#define WDT_WDOGLOAD_WDOGLOAD_BITS                                 32
#define WDT_WDOGLOAD_WDOGLOAD_SHIFT                                0


/****************************************************************************
 * WDT :: WdogValue
 ***************************************************************************/
/* WDT :: WdogValue :: WdogValue [31:00] */
#define Wr_WDT_WdogValue_WdogValue(x) WriteReg(WDT_WDOGVALUE,x)
#define Rd_WDT_WdogValue_WdogValue(x) ReadReg(WDT_WDOGVALUE)
#define WDT_WDOGVALUE_WDOGVALUE_MASK                               0xffffffff
#define WDT_WDOGVALUE_WDOGVALUE_ALIGN                              0
#define WDT_WDOGVALUE_WDOGVALUE_BITS                               32
#define WDT_WDOGVALUE_WDOGVALUE_SHIFT                              0


/****************************************************************************
 * WDT :: WdogControl
 ***************************************************************************/
/* WDT :: WdogControl :: reserved0 [31:02] */
#define WDT_WDOGCONTROL_RESERVED0_MASK                             0xfffffffc
#define WDT_WDOGCONTROL_RESERVED0_ALIGN                            0
#define WDT_WDOGCONTROL_RESERVED0_BITS                             30
#define WDT_WDOGCONTROL_RESERVED0_SHIFT                            2

/* WDT :: WdogControl :: RESEN [01:01] */
#define Wr_WDT_WdogControl_RESEN(x) WriteRegBits(WDT_WDOGCONTROL,0x2,1,x)
#define Rd_WDT_WdogControl_RESEN(x) ReadRegBits(WDT_WDOGCONTROL,0x2,1)
#define WDT_WDOGCONTROL_RESEN_MASK                                 0x00000002
#define WDT_WDOGCONTROL_RESEN_ALIGN                                0
#define WDT_WDOGCONTROL_RESEN_BITS                                 1
#define WDT_WDOGCONTROL_RESEN_SHIFT                                1

/* WDT :: WdogControl :: INTEN [00:00] */
#define Wr_WDT_WdogControl_INTEN(x) WriteRegBits(WDT_WDOGCONTROL,0x1,0,x)
#define Rd_WDT_WdogControl_INTEN(x) ReadRegBits(WDT_WDOGCONTROL,0x1,0)
#define WDT_WDOGCONTROL_INTEN_MASK                                 0x00000001
#define WDT_WDOGCONTROL_INTEN_ALIGN                                0
#define WDT_WDOGCONTROL_INTEN_BITS                                 1
#define WDT_WDOGCONTROL_INTEN_SHIFT                                0


/****************************************************************************
 * WDT :: WdogIntClr
 ***************************************************************************/
/* WDT :: WdogIntClr :: reserved0 [31:01] */
#define WDT_WDOGINTCLR_RESERVED0_MASK                              0xfffffffe
#define WDT_WDOGINTCLR_RESERVED0_ALIGN                             0
#define WDT_WDOGINTCLR_RESERVED0_BITS                              31
#define WDT_WDOGINTCLR_RESERVED0_SHIFT                             1

/* WDT :: WdogIntClr :: WdogIntClr [00:00] */
#define Wr_WDT_WdogIntClr_WdogIntClr(x) WriteRegBits(WDT_WDOGINTCLR,0x1,0,x)
#define Rd_WDT_WdogIntClr_WdogIntClr(x) ReadRegBits(WDT_WDOGINTCLR,0x1,0)
#define WDT_WDOGINTCLR_WDOGINTCLR_MASK                             0x00000001
#define WDT_WDOGINTCLR_WDOGINTCLR_ALIGN                            0
#define WDT_WDOGINTCLR_WDOGINTCLR_BITS                             1
#define WDT_WDOGINTCLR_WDOGINTCLR_SHIFT                            0


/****************************************************************************
 * WDT :: WdogRIS
 ***************************************************************************/
/* WDT :: WdogRIS :: reserved0 [31:01] */
#define WDT_WDOGRIS_RESERVED0_MASK                                 0xfffffffe
#define WDT_WDOGRIS_RESERVED0_ALIGN                                0
#define WDT_WDOGRIS_RESERVED0_BITS                                 31
#define WDT_WDOGRIS_RESERVED0_SHIFT                                1

/* WDT :: WdogRIS :: WDOGRIS [00:00] */
#define Wr_WDT_WdogRIS_WDOGRIS(x) WriteRegBits(WDT_WDOGRIS,0x1,0,x)
#define Rd_WDT_WdogRIS_WDOGRIS(x) ReadRegBits(WDT_WDOGRIS,0x1,0)
#define WDT_WDOGRIS_WDOGRIS_MASK                                   0x00000001
#define WDT_WDOGRIS_WDOGRIS_ALIGN                                  0
#define WDT_WDOGRIS_WDOGRIS_BITS                                   1
#define WDT_WDOGRIS_WDOGRIS_SHIFT                                  0


/****************************************************************************
 * WDT :: WdogMIS
 ***************************************************************************/
/* WDT :: WdogMIS :: reserved0 [31:01] */
#define WDT_WDOGMIS_RESERVED0_MASK                                 0xfffffffe
#define WDT_WDOGMIS_RESERVED0_ALIGN                                0
#define WDT_WDOGMIS_RESERVED0_BITS                                 31
#define WDT_WDOGMIS_RESERVED0_SHIFT                                1

/* WDT :: WdogMIS :: WDOGMIS [00:00] */
#define Wr_WDT_WdogMIS_WDOGMIS(x) WriteRegBits(WDT_WDOGMIS,0x1,0,x)
#define Rd_WDT_WdogMIS_WDOGMIS(x) ReadRegBits(WDT_WDOGMIS,0x1,0)
#define WDT_WDOGMIS_WDOGMIS_MASK                                   0x00000001
#define WDT_WDOGMIS_WDOGMIS_ALIGN                                  0
#define WDT_WDOGMIS_WDOGMIS_BITS                                   1
#define WDT_WDOGMIS_WDOGMIS_SHIFT                                  0


/****************************************************************************
 * WDT :: WdogLock
 ***************************************************************************/
/* WDT :: WdogLock :: WDOGLOCK [31:00] */
#define Wr_WDT_WdogLock_WDOGLOCK(x) WriteReg(WDT_WDOGLOCK,x)
#define Rd_WDT_WdogLock_WDOGLOCK(x) ReadReg(WDT_WDOGLOCK)
#define WDT_WDOGLOCK_WDOGLOCK_MASK                                 0xffffffff
#define WDT_WDOGLOCK_WDOGLOCK_ALIGN                                0
#define WDT_WDOGLOCK_WDOGLOCK_BITS                                 32
#define WDT_WDOGLOCK_WDOGLOCK_SHIFT                                0


/****************************************************************************
 * WDT :: WdogITCR
 ***************************************************************************/
/* WDT :: WdogITCR :: reserved0 [31:01] */
#define WDT_WDOGITCR_RESERVED0_MASK                                0xfffffffe
#define WDT_WDOGITCR_RESERVED0_ALIGN                               0
#define WDT_WDOGITCR_RESERVED0_BITS                                31
#define WDT_WDOGITCR_RESERVED0_SHIFT                               1

/* WDT :: WdogITCR :: ITEN [00:00] */
#define Wr_WDT_WdogITCR_ITEN(x) WriteRegBits(WDT_WDOGITCR,0x1,0,x)
#define Rd_WDT_WdogITCR_ITEN(x) ReadRegBits(WDT_WDOGITCR,0x1,0)
#define WDT_WDOGITCR_ITEN_MASK                                     0x00000001
#define WDT_WDOGITCR_ITEN_ALIGN                                    0
#define WDT_WDOGITCR_ITEN_BITS                                     1
#define WDT_WDOGITCR_ITEN_SHIFT                                    0


/****************************************************************************
 * WDT :: WdogITOP
 ***************************************************************************/
/* WDT :: WdogITOP :: reserved0 [31:02] */
#define WDT_WDOGITOP_RESERVED0_MASK                                0xfffffffc
#define WDT_WDOGITOP_RESERVED0_ALIGN                               0
#define WDT_WDOGITOP_RESERVED0_BITS                                30
#define WDT_WDOGITOP_RESERVED0_SHIFT                               2

/* WDT :: WdogITOP :: WDOGINT [01:01] */
#define Wr_WDT_WdogITOP_WDOGINT(x) WriteRegBits(WDT_WDOGITOP,0x2,1,x)
#define Rd_WDT_WdogITOP_WDOGINT(x) ReadRegBits(WDT_WDOGITOP,0x2,1)
#define WDT_WDOGITOP_WDOGINT_MASK                                  0x00000002
#define WDT_WDOGITOP_WDOGINT_ALIGN                                 0
#define WDT_WDOGITOP_WDOGINT_BITS                                  1
#define WDT_WDOGITOP_WDOGINT_SHIFT                                 1

/* WDT :: WdogITOP :: WDOGRES [00:00] */
#define Wr_WDT_WdogITOP_WDOGRES(x) WriteRegBits(WDT_WDOGITOP,0x1,0,x)
#define Rd_WDT_WdogITOP_WDOGRES(x) ReadRegBits(WDT_WDOGITOP,0x1,0)
#define WDT_WDOGITOP_WDOGRES_MASK                                  0x00000001
#define WDT_WDOGITOP_WDOGRES_ALIGN                                 0
#define WDT_WDOGITOP_WDOGRES_BITS                                  1
#define WDT_WDOGITOP_WDOGRES_SHIFT                                 0


/****************************************************************************
 * WDT :: WdogPeriphID0
 ***************************************************************************/
/* WDT :: WdogPeriphID0 :: reserved0 [31:08] */
#define WDT_WDOGPERIPHID0_RESERVED0_MASK                           0xffffff00
#define WDT_WDOGPERIPHID0_RESERVED0_ALIGN                          0
#define WDT_WDOGPERIPHID0_RESERVED0_BITS                           24
#define WDT_WDOGPERIPHID0_RESERVED0_SHIFT                          8

/* WDT :: WdogPeriphID0 :: PartNumber0 [07:00] */
#define Wr_WDT_WdogPeriphID0_PartNumber0(x) WriteRegBits(WDT_WDOGPERIPHID0,0xff,0,x)
#define Rd_WDT_WdogPeriphID0_PartNumber0(x) ReadRegBits(WDT_WDOGPERIPHID0,0xff,0)
#define WDT_WDOGPERIPHID0_PARTNUMBER0_MASK                         0x000000ff
#define WDT_WDOGPERIPHID0_PARTNUMBER0_ALIGN                        0
#define WDT_WDOGPERIPHID0_PARTNUMBER0_BITS                         8
#define WDT_WDOGPERIPHID0_PARTNUMBER0_SHIFT                        0


/****************************************************************************
 * WDT :: WdogPeriphID1
 ***************************************************************************/
/* WDT :: WdogPeriphID1 :: reserved0 [31:08] */
#define WDT_WDOGPERIPHID1_RESERVED0_MASK                           0xffffff00
#define WDT_WDOGPERIPHID1_RESERVED0_ALIGN                          0
#define WDT_WDOGPERIPHID1_RESERVED0_BITS                           24
#define WDT_WDOGPERIPHID1_RESERVED0_SHIFT                          8

/* WDT :: WdogPeriphID1 :: Designer0 [07:04] */
#define Wr_WDT_WdogPeriphID1_Designer0(x) WriteRegBits(WDT_WDOGPERIPHID1,0xf0,4,x)
#define Rd_WDT_WdogPeriphID1_Designer0(x) ReadRegBits(WDT_WDOGPERIPHID1,0xf0,4)
#define WDT_WDOGPERIPHID1_DESIGNER0_MASK                           0x000000f0
#define WDT_WDOGPERIPHID1_DESIGNER0_ALIGN                          0
#define WDT_WDOGPERIPHID1_DESIGNER0_BITS                           4
#define WDT_WDOGPERIPHID1_DESIGNER0_SHIFT                          4

/* WDT :: WdogPeriphID1 :: PartNumber1 [03:00] */
#define Wr_WDT_WdogPeriphID1_PartNumber1(x) WriteRegBits(WDT_WDOGPERIPHID1,0xf,0,x)
#define Rd_WDT_WdogPeriphID1_PartNumber1(x) ReadRegBits(WDT_WDOGPERIPHID1,0xf,0)
#define WDT_WDOGPERIPHID1_PARTNUMBER1_MASK                         0x0000000f
#define WDT_WDOGPERIPHID1_PARTNUMBER1_ALIGN                        0
#define WDT_WDOGPERIPHID1_PARTNUMBER1_BITS                         4
#define WDT_WDOGPERIPHID1_PARTNUMBER1_SHIFT                        0


/****************************************************************************
 * WDT :: WdogPeriphID2
 ***************************************************************************/
/* WDT :: WdogPeriphID2 :: reserved0 [31:08] */
#define WDT_WDOGPERIPHID2_RESERVED0_MASK                           0xffffff00
#define WDT_WDOGPERIPHID2_RESERVED0_ALIGN                          0
#define WDT_WDOGPERIPHID2_RESERVED0_BITS                           24
#define WDT_WDOGPERIPHID2_RESERVED0_SHIFT                          8

/* WDT :: WdogPeriphID2 :: Revision [07:04] */
#define Wr_WDT_WdogPeriphID2_Revision(x) WriteRegBits(WDT_WDOGPERIPHID2,0xf0,4,x)
#define Rd_WDT_WdogPeriphID2_Revision(x) ReadRegBits(WDT_WDOGPERIPHID2,0xf0,4)
#define WDT_WDOGPERIPHID2_REVISION_MASK                            0x000000f0
#define WDT_WDOGPERIPHID2_REVISION_ALIGN                           0
#define WDT_WDOGPERIPHID2_REVISION_BITS                            4
#define WDT_WDOGPERIPHID2_REVISION_SHIFT                           4

/* WDT :: WdogPeriphID2 :: Designer1 [03:00] */
#define Wr_WDT_WdogPeriphID2_Designer1(x) WriteRegBits(WDT_WDOGPERIPHID2,0xf,0,x)
#define Rd_WDT_WdogPeriphID2_Designer1(x) ReadRegBits(WDT_WDOGPERIPHID2,0xf,0)
#define WDT_WDOGPERIPHID2_DESIGNER1_MASK                           0x0000000f
#define WDT_WDOGPERIPHID2_DESIGNER1_ALIGN                          0
#define WDT_WDOGPERIPHID2_DESIGNER1_BITS                           4
#define WDT_WDOGPERIPHID2_DESIGNER1_SHIFT                          0


/****************************************************************************
 * WDT :: WdogPeriphID3
 ***************************************************************************/
/* WDT :: WdogPeriphID3 :: reserved0 [31:08] */
#define WDT_WDOGPERIPHID3_RESERVED0_MASK                           0xffffff00
#define WDT_WDOGPERIPHID3_RESERVED0_ALIGN                          0
#define WDT_WDOGPERIPHID3_RESERVED0_BITS                           24
#define WDT_WDOGPERIPHID3_RESERVED0_SHIFT                          8

/* WDT :: WdogPeriphID3 :: Configuration [07:00] */
#define Wr_WDT_WdogPeriphID3_Configuration(x) WriteRegBits(WDT_WDOGPERIPHID3,0xff,0,x)
#define Rd_WDT_WdogPeriphID3_Configuration(x) ReadRegBits(WDT_WDOGPERIPHID3,0xff,0)
#define WDT_WDOGPERIPHID3_CONFIGURATION_MASK                       0x000000ff
#define WDT_WDOGPERIPHID3_CONFIGURATION_ALIGN                      0
#define WDT_WDOGPERIPHID3_CONFIGURATION_BITS                       8
#define WDT_WDOGPERIPHID3_CONFIGURATION_SHIFT                      0


/****************************************************************************
 * WDT :: WdogPCellID0
 ***************************************************************************/
/* WDT :: WdogPCellID0 :: reserved0 [31:08] */
#define WDT_WDOGPCELLID0_RESERVED0_MASK                            0xffffff00
#define WDT_WDOGPCELLID0_RESERVED0_ALIGN                           0
#define WDT_WDOGPCELLID0_RESERVED0_BITS                            24
#define WDT_WDOGPCELLID0_RESERVED0_SHIFT                           8

/* WDT :: WdogPCellID0 :: WdogPCellID0 [07:00] */
#define Wr_WDT_WdogPCellID0_WdogPCellID0(x) WriteRegBits(WDT_WDOGPCELLID0,0xff,0,x)
#define Rd_WDT_WdogPCellID0_WdogPCellID0(x) ReadRegBits(WDT_WDOGPCELLID0,0xff,0)
#define WDT_WDOGPCELLID0_WDOGPCELLID0_MASK                         0x000000ff
#define WDT_WDOGPCELLID0_WDOGPCELLID0_ALIGN                        0
#define WDT_WDOGPCELLID0_WDOGPCELLID0_BITS                         8
#define WDT_WDOGPCELLID0_WDOGPCELLID0_SHIFT                        0


/****************************************************************************
 * WDT :: WdogPCellID1
 ***************************************************************************/
/* WDT :: WdogPCellID1 :: reserved0 [31:08] */
#define WDT_WDOGPCELLID1_RESERVED0_MASK                            0xffffff00
#define WDT_WDOGPCELLID1_RESERVED0_ALIGN                           0
#define WDT_WDOGPCELLID1_RESERVED0_BITS                            24
#define WDT_WDOGPCELLID1_RESERVED0_SHIFT                           8

/* WDT :: WdogPCellID1 :: WdogPCellID1 [07:00] */
#define Wr_WDT_WdogPCellID1_WdogPCellID1(x) WriteRegBits(WDT_WDOGPCELLID1,0xff,0,x)
#define Rd_WDT_WdogPCellID1_WdogPCellID1(x) ReadRegBits(WDT_WDOGPCELLID1,0xff,0)
#define WDT_WDOGPCELLID1_WDOGPCELLID1_MASK                         0x000000ff
#define WDT_WDOGPCELLID1_WDOGPCELLID1_ALIGN                        0
#define WDT_WDOGPCELLID1_WDOGPCELLID1_BITS                         8
#define WDT_WDOGPCELLID1_WDOGPCELLID1_SHIFT                        0


/****************************************************************************
 * WDT :: WdogPCellID2
 ***************************************************************************/
/* WDT :: WdogPCellID2 :: reserved0 [31:08] */
#define WDT_WDOGPCELLID2_RESERVED0_MASK                            0xffffff00
#define WDT_WDOGPCELLID2_RESERVED0_ALIGN                           0
#define WDT_WDOGPCELLID2_RESERVED0_BITS                            24
#define WDT_WDOGPCELLID2_RESERVED0_SHIFT                           8

/* WDT :: WdogPCellID2 :: WdogPCellID2 [07:00] */
#define Wr_WDT_WdogPCellID2_WdogPCellID2(x) WriteRegBits(WDT_WDOGPCELLID2,0xff,0,x)
#define Rd_WDT_WdogPCellID2_WdogPCellID2(x) ReadRegBits(WDT_WDOGPCELLID2,0xff,0)
#define WDT_WDOGPCELLID2_WDOGPCELLID2_MASK                         0x000000ff
#define WDT_WDOGPCELLID2_WDOGPCELLID2_ALIGN                        0
#define WDT_WDOGPCELLID2_WDOGPCELLID2_BITS                         8
#define WDT_WDOGPCELLID2_WDOGPCELLID2_SHIFT                        0


/****************************************************************************
 * WDT :: WdogPCellID3
 ***************************************************************************/
/* WDT :: WdogPCellID3 :: reserved0 [31:08] */
#define WDT_WDOGPCELLID3_RESERVED0_MASK                            0xffffff00
#define WDT_WDOGPCELLID3_RESERVED0_ALIGN                           0
#define WDT_WDOGPCELLID3_RESERVED0_BITS                            24
#define WDT_WDOGPCELLID3_RESERVED0_SHIFT                           8

/* WDT :: WdogPCellID3 :: WdogPCellID3 [07:00] */
#define Wr_WDT_WdogPCellID3_WdogPCellID3(x) WriteRegBits(WDT_WDOGPCELLID3,0xff,0,x)
#define Rd_WDT_WdogPCellID3_WdogPCellID3(x) ReadRegBits(WDT_WDOGPCELLID3,0xff,0)
#define WDT_WDOGPCELLID3_WDOGPCELLID3_MASK                         0x000000ff
#define WDT_WDOGPCELLID3_WDOGPCELLID3_ALIGN                        0
#define WDT_WDOGPCELLID3_WDOGPCELLID3_BITS                         8
#define WDT_WDOGPCELLID3_WDOGPCELLID3_SHIFT                        0


/****************************************************************************
 * bcm89530_sys_cfg_DMU
 ***************************************************************************/
/****************************************************************************
 * DMU :: dmu_status
 ***************************************************************************/
/* DMU :: dmu_status :: reserved0 [31:18] */
#define DMU_DMU_STATUS_RESERVED0_MASK                              0xfffc0000
#define DMU_DMU_STATUS_RESERVED0_ALIGN                             0
#define DMU_DMU_STATUS_RESERVED0_BITS                              14
#define DMU_DMU_STATUS_RESERVED0_SHIFT                             18

/* DMU :: dmu_status :: dmu_clk_en_timeout_top [17:17] */
#define Wr_DMU_dmu_status_dmu_clk_en_timeout_top(x) WriteRegBits(DMU_DMU_STATUS,0x20000,17,x)
#define Rd_DMU_dmu_status_dmu_clk_en_timeout_top(x) ReadRegBits(DMU_DMU_STATUS,0x20000,17)
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_TOP_MASK                 0x00020000
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_TOP_ALIGN                0
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_TOP_BITS                 1
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_TOP_SHIFT                17

/* DMU :: dmu_status :: dmu_clk_en_timeout_cpuclk [16:16] */
#define Wr_DMU_dmu_status_dmu_clk_en_timeout_cpuclk(x) WriteRegBits(DMU_DMU_STATUS,0x10000,16,x)
#define Rd_DMU_dmu_status_dmu_clk_en_timeout_cpuclk(x) ReadRegBits(DMU_DMU_STATUS,0x10000,16)
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_CPUCLK_MASK              0x00010000
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_CPUCLK_ALIGN             0
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_CPUCLK_BITS              1
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_CPUCLK_SHIFT             16

/* DMU :: dmu_status :: reserved1 [15:15] */
#define DMU_DMU_STATUS_RESERVED1_MASK                              0x00008000
#define DMU_DMU_STATUS_RESERVED1_ALIGN                             0
#define DMU_DMU_STATUS_RESERVED1_BITS                              1
#define DMU_DMU_STATUS_RESERVED1_SHIFT                             15

/* DMU :: dmu_status :: dmu_clk_en_timeout_eth [14:14] */
#define Wr_DMU_dmu_status_dmu_clk_en_timeout_eth(x) WriteRegBits(DMU_DMU_STATUS,0x4000,14,x)
#define Rd_DMU_dmu_status_dmu_clk_en_timeout_eth(x) ReadRegBits(DMU_DMU_STATUS,0x4000,14)
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_ETH_MASK                 0x00004000
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_ETH_ALIGN                0
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_ETH_BITS                 1
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_ETH_SHIFT                14

/* DMU :: dmu_status :: reserved2 [13:13] */
#define DMU_DMU_STATUS_RESERVED2_MASK                              0x00002000
#define DMU_DMU_STATUS_RESERVED2_ALIGN                             0
#define DMU_DMU_STATUS_RESERVED2_BITS                              1
#define DMU_DMU_STATUS_RESERVED2_SHIFT                             13

/* DMU :: dmu_status :: dmu_clk_en_timeout_proc [12:12] */
#define Wr_DMU_dmu_status_dmu_clk_en_timeout_proc(x) WriteRegBits(DMU_DMU_STATUS,0x1000,12,x)
#define Rd_DMU_dmu_status_dmu_clk_en_timeout_proc(x) ReadRegBits(DMU_DMU_STATUS,0x1000,12)
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_PROC_MASK                0x00001000
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_PROC_ALIGN               0
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_PROC_BITS                1
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_PROC_SHIFT               12

/* DMU :: dmu_status :: reserved3 [11:11] */
#define DMU_DMU_STATUS_RESERVED3_MASK                              0x00000800
#define DMU_DMU_STATUS_RESERVED3_ALIGN                             0
#define DMU_DMU_STATUS_RESERVED3_BITS                              1
#define DMU_DMU_STATUS_RESERVED3_SHIFT                             11

/* DMU :: dmu_status :: dmu_clk_en_timeout_apbp [10:10] */
#define Wr_DMU_dmu_status_dmu_clk_en_timeout_apbp(x) WriteRegBits(DMU_DMU_STATUS,0x400,10,x)
#define Rd_DMU_dmu_status_dmu_clk_en_timeout_apbp(x) ReadRegBits(DMU_DMU_STATUS,0x400,10)
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_APBP_MASK                0x00000400
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_APBP_ALIGN               0
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_APBP_BITS                1
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_APBP_SHIFT               10

/* DMU :: dmu_status :: dmu_clk_en_timeout_ahbm [09:09] */
#define Wr_DMU_dmu_status_dmu_clk_en_timeout_ahbm(x) WriteRegBits(DMU_DMU_STATUS,0x200,9,x)
#define Rd_DMU_dmu_status_dmu_clk_en_timeout_ahbm(x) ReadRegBits(DMU_DMU_STATUS,0x200,9)
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_AHBM_MASK                0x00000200
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_AHBM_ALIGN               0
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_AHBM_BITS                1
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_AHBM_SHIFT               9

/* DMU :: dmu_status :: dmu_clk_en_timeout_clkout [08:08] */
#define Wr_DMU_dmu_status_dmu_clk_en_timeout_clkout(x) WriteRegBits(DMU_DMU_STATUS,0x100,8,x)
#define Rd_DMU_dmu_status_dmu_clk_en_timeout_clkout(x) ReadRegBits(DMU_DMU_STATUS,0x100,8)
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_CLKOUT_MASK              0x00000100
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_CLKOUT_ALIGN             0
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_CLKOUT_BITS              1
#define DMU_DMU_STATUS_DMU_CLK_EN_TIMEOUT_CLKOUT_SHIFT             8

/* DMU :: dmu_status :: reserved4 [07:06] */
#define DMU_DMU_STATUS_RESERVED4_MASK                              0x000000c0
#define DMU_DMU_STATUS_RESERVED4_ALIGN                             0
#define DMU_DMU_STATUS_RESERVED4_BITS                              2
#define DMU_DMU_STATUS_RESERVED4_SHIFT                             6

/* DMU :: dmu_status :: dmu_err_intrp [05:05] */
#define Wr_DMU_dmu_status_dmu_err_intrp(x) WriteRegBits(DMU_DMU_STATUS,0x20,5,x)
#define Rd_DMU_dmu_status_dmu_err_intrp(x) ReadRegBits(DMU_DMU_STATUS,0x20,5)
#define DMU_DMU_STATUS_DMU_ERR_INTRP_MASK                          0x00000020
#define DMU_DMU_STATUS_DMU_ERR_INTRP_ALIGN                         0
#define DMU_DMU_STATUS_DMU_ERR_INTRP_BITS                          1
#define DMU_DMU_STATUS_DMU_ERR_INTRP_SHIFT                         5

/* DMU :: dmu_status :: dmu_clk_sel_busy [04:04] */
#define Wr_DMU_dmu_status_dmu_clk_sel_busy(x) WriteRegBits(DMU_DMU_STATUS,0x10,4,x)
#define Rd_DMU_dmu_status_dmu_clk_sel_busy(x) ReadRegBits(DMU_DMU_STATUS,0x10,4)
#define DMU_DMU_STATUS_DMU_CLK_SEL_BUSY_MASK                       0x00000010
#define DMU_DMU_STATUS_DMU_CLK_SEL_BUSY_ALIGN                      0
#define DMU_DMU_STATUS_DMU_CLK_SEL_BUSY_BITS                       1
#define DMU_DMU_STATUS_DMU_CLK_SEL_BUSY_SHIFT                      4

/* DMU :: dmu_status :: reserved5 [03:00] */
#define DMU_DMU_STATUS_RESERVED5_MASK                              0x0000000f
#define DMU_DMU_STATUS_RESERVED5_ALIGN                             0
#define DMU_DMU_STATUS_RESERVED5_BITS                              4
#define DMU_DMU_STATUS_RESERVED5_SHIFT                             0


/****************************************************************************
 * DMU :: dmu_clk_sel
 ***************************************************************************/
/* DMU :: dmu_clk_sel :: reserved0 [31:21] */
#define DMU_DMU_CLK_SEL_RESERVED0_MASK                             0xffe00000
#define DMU_DMU_CLK_SEL_RESERVED0_ALIGN                            0
#define DMU_DMU_CLK_SEL_RESERVED0_BITS                             11
#define DMU_DMU_CLK_SEL_RESERVED0_SHIFT                            21

/* DMU :: dmu_clk_sel :: reserved_1 [20:12] */
#define DMU_DMU_CLK_SEL_RESERVED_1_MASK                            0x001ff000
#define DMU_DMU_CLK_SEL_RESERVED_1_ALIGN                           0
#define DMU_DMU_CLK_SEL_RESERVED_1_BITS                            9
#define DMU_DMU_CLK_SEL_RESERVED_1_SHIFT                           12

/* DMU :: dmu_clk_sel :: reserved1 [11:08] */
#define DMU_DMU_CLK_SEL_RESERVED1_MASK                             0x00000f00
#define DMU_DMU_CLK_SEL_RESERVED1_ALIGN                            0
#define DMU_DMU_CLK_SEL_RESERVED1_BITS                             4
#define DMU_DMU_CLK_SEL_RESERVED1_SHIFT                            8

/* DMU :: dmu_clk_sel :: dmu_pclk_sel [07:06] */
#define Wr_DMU_dmu_clk_sel_dmu_pclk_sel(x) WriteRegBits(DMU_DMU_CLK_SEL,0xc0,6,x)
#define Rd_DMU_dmu_clk_sel_dmu_pclk_sel(x) ReadRegBits(DMU_DMU_CLK_SEL,0xc0,6)
#define DMU_DMU_CLK_SEL_DMU_PCLK_SEL_MASK                          0x000000c0
#define DMU_DMU_CLK_SEL_DMU_PCLK_SEL_ALIGN                         0
#define DMU_DMU_CLK_SEL_DMU_PCLK_SEL_BITS                          2
#define DMU_DMU_CLK_SEL_DMU_PCLK_SEL_SHIFT                         6

/* DMU :: dmu_clk_sel :: dmu_hclk_sel [05:04] */
#define Wr_DMU_dmu_clk_sel_dmu_hclk_sel(x) WriteRegBits(DMU_DMU_CLK_SEL,0x30,4,x)
#define Rd_DMU_dmu_clk_sel_dmu_hclk_sel(x) ReadRegBits(DMU_DMU_CLK_SEL,0x30,4)
#define DMU_DMU_CLK_SEL_DMU_HCLK_SEL_MASK                          0x00000030
#define DMU_DMU_CLK_SEL_DMU_HCLK_SEL_ALIGN                         0
#define DMU_DMU_CLK_SEL_DMU_HCLK_SEL_BITS                          2
#define DMU_DMU_CLK_SEL_DMU_HCLK_SEL_SHIFT                         4

/* DMU :: dmu_clk_sel :: dmu_qclk_sel [03:02] */
#define Wr_DMU_dmu_clk_sel_dmu_qclk_sel(x) WriteRegBits(DMU_DMU_CLK_SEL,0xc,2,x)
#define Rd_DMU_dmu_clk_sel_dmu_qclk_sel(x) ReadRegBits(DMU_DMU_CLK_SEL,0xc,2)
#define DMU_DMU_CLK_SEL_DMU_QCLK_SEL_MASK                          0x0000000c
#define DMU_DMU_CLK_SEL_DMU_QCLK_SEL_ALIGN                         0
#define DMU_DMU_CLK_SEL_DMU_QCLK_SEL_BITS                          2
#define DMU_DMU_CLK_SEL_DMU_QCLK_SEL_SHIFT                         2

/* DMU :: dmu_clk_sel :: dmu_cpuclk_sel [01:00] */
#define Wr_DMU_dmu_clk_sel_dmu_cpuclk_sel(x) WriteRegBits(DMU_DMU_CLK_SEL,0x3,0,x)
#define Rd_DMU_dmu_clk_sel_dmu_cpuclk_sel(x) ReadRegBits(DMU_DMU_CLK_SEL,0x3,0)
#define DMU_DMU_CLK_SEL_DMU_CPUCLK_SEL_MASK                        0x00000003
#define DMU_DMU_CLK_SEL_DMU_CPUCLK_SEL_ALIGN                       0
#define DMU_DMU_CLK_SEL_DMU_CPUCLK_SEL_BITS                        2
#define DMU_DMU_CLK_SEL_DMU_CPUCLK_SEL_SHIFT                       0


/****************************************************************************
 * DMU :: dmu_clkout_sel
 ***************************************************************************/
/* DMU :: dmu_clkout_sel :: reserved_1 [31:16] */
#define DMU_DMU_CLKOUT_SEL_RESERVED_1_MASK                         0xffff0000
#define DMU_DMU_CLKOUT_SEL_RESERVED_1_ALIGN                        0
#define DMU_DMU_CLKOUT_SEL_RESERVED_1_BITS                         16
#define DMU_DMU_CLKOUT_SEL_RESERVED_1_SHIFT                        16

/* DMU :: dmu_clkout_sel :: dmu_clkout0_scalar [15:06] */
#define Wr_DMU_dmu_clkout_sel_dmu_clkout0_scalar(x) WriteRegBits(DMU_DMU_CLKOUT_SEL,0xffc0,6,x)
#define Rd_DMU_dmu_clkout_sel_dmu_clkout0_scalar(x) ReadRegBits(DMU_DMU_CLKOUT_SEL,0xffc0,6)
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_SCALAR_MASK                 0x0000ffc0
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_SCALAR_ALIGN                0
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_SCALAR_BITS                 10
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_SCALAR_SHIFT                6

/* DMU :: dmu_clkout_sel :: dmu_clkout0_sel [05:02] */
#define Wr_DMU_dmu_clkout_sel_dmu_clkout0_sel(x) WriteRegBits(DMU_DMU_CLKOUT_SEL,0x3c,2,x)
#define Rd_DMU_dmu_clkout_sel_dmu_clkout0_sel(x) ReadRegBits(DMU_DMU_CLKOUT_SEL,0x3c,2)
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_SEL_MASK                    0x0000003c
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_SEL_ALIGN                   0
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_SEL_BITS                    4
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_SEL_SHIFT                   2

/* DMU :: dmu_clkout_sel :: dmu_clkout0_data [01:01] */
#define Wr_DMU_dmu_clkout_sel_dmu_clkout0_data(x) WriteRegBits(DMU_DMU_CLKOUT_SEL,0x2,1,x)
#define Rd_DMU_dmu_clkout_sel_dmu_clkout0_data(x) ReadRegBits(DMU_DMU_CLKOUT_SEL,0x2,1)
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_DATA_MASK                   0x00000002
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_DATA_ALIGN                  0
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_DATA_BITS                   1
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_DATA_SHIFT                  1

/* DMU :: dmu_clkout_sel :: dmu_clkout0_pwd [00:00] */
#define Wr_DMU_dmu_clkout_sel_dmu_clkout0_pwd(x) WriteRegBits(DMU_DMU_CLKOUT_SEL,0x1,0,x)
#define Rd_DMU_dmu_clkout_sel_dmu_clkout0_pwd(x) ReadRegBits(DMU_DMU_CLKOUT_SEL,0x1,0)
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_PWD_MASK                    0x00000001
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_PWD_ALIGN                   0
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_PWD_BITS                    1
#define DMU_DMU_CLKOUT_SEL_DMU_CLKOUT0_PWD_SHIFT                   0


/****************************************************************************
 * DMU :: dmu_timer_enable_sel
 ***************************************************************************/
/* DMU :: dmu_timer_enable_sel :: reserved0 [31:06] */
#define DMU_DMU_TIMER_ENABLE_SEL_RESERVED0_MASK                    0xffffffc0
#define DMU_DMU_TIMER_ENABLE_SEL_RESERVED0_ALIGN                   0
#define DMU_DMU_TIMER_ENABLE_SEL_RESERVED0_BITS                    26
#define DMU_DMU_TIMER_ENABLE_SEL_RESERVED0_SHIFT                   6

/* DMU :: dmu_timer_enable_sel :: dmu_wdt_enable_pclk [05:05] */
#define Wr_DMU_dmu_timer_enable_sel_dmu_wdt_enable_pclk(x) WriteRegBits(DMU_DMU_TIMER_ENABLE_SEL,0x20,5,x)
#define Rd_DMU_dmu_timer_enable_sel_dmu_wdt_enable_pclk(x) ReadRegBits(DMU_DMU_TIMER_ENABLE_SEL,0x20,5)
#define DMU_DMU_TIMER_ENABLE_SEL_DMU_WDT_ENABLE_PCLK_MASK          0x00000020
#define DMU_DMU_TIMER_ENABLE_SEL_DMU_WDT_ENABLE_PCLK_ALIGN         0
#define DMU_DMU_TIMER_ENABLE_SEL_DMU_WDT_ENABLE_PCLK_BITS          1
#define DMU_DMU_TIMER_ENABLE_SEL_DMU_WDT_ENABLE_PCLK_SHIFT         5

/* DMU :: dmu_timer_enable_sel :: reserved1 [04:01] */
#define DMU_DMU_TIMER_ENABLE_SEL_RESERVED1_MASK                    0x0000001e
#define DMU_DMU_TIMER_ENABLE_SEL_RESERVED1_ALIGN                   0
#define DMU_DMU_TIMER_ENABLE_SEL_RESERVED1_BITS                    4
#define DMU_DMU_TIMER_ENABLE_SEL_RESERVED1_SHIFT                   1

/* DMU :: dmu_timer_enable_sel :: dmu_tim0_enable_pclk [00:00] */
#define Wr_DMU_dmu_timer_enable_sel_dmu_tim0_enable_pclk(x) WriteRegBits(DMU_DMU_TIMER_ENABLE_SEL,0x1,0,x)
#define Rd_DMU_dmu_timer_enable_sel_dmu_tim0_enable_pclk(x) ReadRegBits(DMU_DMU_TIMER_ENABLE_SEL,0x1,0)
#define DMU_DMU_TIMER_ENABLE_SEL_DMU_TIM0_ENABLE_PCLK_MASK         0x00000001
#define DMU_DMU_TIMER_ENABLE_SEL_DMU_TIM0_ENABLE_PCLK_ALIGN        0
#define DMU_DMU_TIMER_ENABLE_SEL_DMU_TIM0_ENABLE_PCLK_BITS         1
#define DMU_DMU_TIMER_ENABLE_SEL_DMU_TIM0_ENABLE_PCLK_SHIFT        0


/****************************************************************************
 * DMU :: dmu_pm
 ***************************************************************************/
/* DMU :: dmu_pm :: pm_deepsleep_timeout [31:00] */
#define Wr_DMU_dmu_pm_pm_deepsleep_timeout(x) WriteReg(DMU_DMU_PM,x)
#define Rd_DMU_dmu_pm_pm_deepsleep_timeout(x) ReadReg(DMU_DMU_PM)
#define DMU_DMU_PM_PM_DEEPSLEEP_TIMEOUT_MASK                       0xffffffff
#define DMU_DMU_PM_PM_DEEPSLEEP_TIMEOUT_ALIGN                      0
#define DMU_DMU_PM_PM_DEEPSLEEP_TIMEOUT_BITS                       32
#define DMU_DMU_PM_PM_DEEPSLEEP_TIMEOUT_SHIFT                      0


/****************************************************************************
 * DMU :: dmu_sw_rst
 ***************************************************************************/
/* DMU :: dmu_sw_rst :: reserved0 [31:02] */
#define DMU_DMU_SW_RST_RESERVED0_MASK                              0xfffffffc
#define DMU_DMU_SW_RST_RESERVED0_ALIGN                             0
#define DMU_DMU_SW_RST_RESERVED0_BITS                              30
#define DMU_DMU_SW_RST_RESERVED0_SHIFT                             2

/* DMU :: dmu_sw_rst :: dmu_mem_clr_snap [01:01] */
#define Wr_DMU_dmu_sw_rst_dmu_mem_clr_snap(x) WriteRegBits(DMU_DMU_SW_RST,0x2,1,x)
#define Rd_DMU_dmu_sw_rst_dmu_mem_clr_snap(x) ReadRegBits(DMU_DMU_SW_RST,0x2,1)
#define DMU_DMU_SW_RST_DMU_MEM_CLR_SNAP_MASK                       0x00000002
#define DMU_DMU_SW_RST_DMU_MEM_CLR_SNAP_ALIGN                      0
#define DMU_DMU_SW_RST_DMU_MEM_CLR_SNAP_BITS                       1
#define DMU_DMU_SW_RST_DMU_MEM_CLR_SNAP_SHIFT                      1

/* DMU :: dmu_sw_rst :: dmu_swrst [00:00] */
#define Wr_DMU_dmu_sw_rst_dmu_swrst(x) WriteRegBits(DMU_DMU_SW_RST,0x1,0,x)
#define Rd_DMU_dmu_sw_rst_dmu_swrst(x) ReadRegBits(DMU_DMU_SW_RST,0x1,0)
#define DMU_DMU_SW_RST_DMU_SWRST_MASK                              0x00000001
#define DMU_DMU_SW_RST_DMU_SWRST_ALIGN                             0
#define DMU_DMU_SW_RST_DMU_SWRST_BITS                              1
#define DMU_DMU_SW_RST_DMU_SWRST_SHIFT                             0


/****************************************************************************
 * DMU :: dmu_rst_last
 ***************************************************************************/
/* DMU :: dmu_rst_last :: last_ram_uncorrectable [31:31] */
#define Wr_DMU_dmu_rst_last_last_ram_uncorrectable(x) WriteRegBits(DMU_DMU_RST_LAST,0x80000000,31,x)
#define Rd_DMU_dmu_rst_last_last_ram_uncorrectable(x) ReadRegBits(DMU_DMU_RST_LAST,0x80000000,31)
#define DMU_DMU_RST_LAST_LAST_RAM_UNCORRECTABLE_MASK               0x80000000
#define DMU_DMU_RST_LAST_LAST_RAM_UNCORRECTABLE_ALIGN              0
#define DMU_DMU_RST_LAST_LAST_RAM_UNCORRECTABLE_BITS               1
#define DMU_DMU_RST_LAST_LAST_RAM_UNCORRECTABLE_SHIFT              31

/* DMU :: dmu_rst_last :: last_rng_interrupt [30:30] */
#define Wr_DMU_dmu_rst_last_last_rng_interrupt(x) WriteRegBits(DMU_DMU_RST_LAST,0x40000000,30,x)
#define Rd_DMU_dmu_rst_last_last_rng_interrupt(x) ReadRegBits(DMU_DMU_RST_LAST,0x40000000,30)
#define DMU_DMU_RST_LAST_LAST_RNG_INTERRUPT_MASK                   0x40000000
#define DMU_DMU_RST_LAST_LAST_RNG_INTERRUPT_ALIGN                  0
#define DMU_DMU_RST_LAST_LAST_RNG_INTERRUPT_BITS                   1
#define DMU_DMU_RST_LAST_LAST_RNG_INTERRUPT_SHIFT                  30

/* DMU :: dmu_rst_last :: last_tamper_l1 [29:29] */
#define Wr_DMU_dmu_rst_last_last_tamper_l1(x) WriteRegBits(DMU_DMU_RST_LAST,0x20000000,29,x)
#define Rd_DMU_dmu_rst_last_last_tamper_l1(x) ReadRegBits(DMU_DMU_RST_LAST,0x20000000,29)
#define DMU_DMU_RST_LAST_LAST_TAMPER_L1_MASK                       0x20000000
#define DMU_DMU_RST_LAST_LAST_TAMPER_L1_ALIGN                      0
#define DMU_DMU_RST_LAST_LAST_TAMPER_L1_BITS                       1
#define DMU_DMU_RST_LAST_LAST_TAMPER_L1_SHIFT                      29

/* DMU :: dmu_rst_last :: last_ram_correctable [28:28] */
#define Wr_DMU_dmu_rst_last_last_ram_correctable(x) WriteRegBits(DMU_DMU_RST_LAST,0x10000000,28,x)
#define Rd_DMU_dmu_rst_last_last_ram_correctable(x) ReadRegBits(DMU_DMU_RST_LAST,0x10000000,28)
#define DMU_DMU_RST_LAST_LAST_RAM_CORRECTABLE_MASK                 0x10000000
#define DMU_DMU_RST_LAST_LAST_RAM_CORRECTABLE_ALIGN                0
#define DMU_DMU_RST_LAST_LAST_RAM_CORRECTABLE_BITS                 1
#define DMU_DMU_RST_LAST_LAST_RAM_CORRECTABLE_SHIFT                28

/* DMU :: dmu_rst_last :: last_smu_par_err [27:27] */
#define Wr_DMU_dmu_rst_last_last_smu_par_err(x) WriteRegBits(DMU_DMU_RST_LAST,0x8000000,27,x)
#define Rd_DMU_dmu_rst_last_last_smu_par_err(x) ReadRegBits(DMU_DMU_RST_LAST,0x8000000,27)
#define DMU_DMU_RST_LAST_LAST_SMU_PAR_ERR_MASK                     0x08000000
#define DMU_DMU_RST_LAST_LAST_SMU_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_LAST_LAST_SMU_PAR_ERR_BITS                     1
#define DMU_DMU_RST_LAST_LAST_SMU_PAR_ERR_SHIFT                    27

/* DMU :: dmu_rst_last :: last_smu_auth_err [26:26] */
#define Wr_DMU_dmu_rst_last_last_smu_auth_err(x) WriteRegBits(DMU_DMU_RST_LAST,0x4000000,26,x)
#define Rd_DMU_dmu_rst_last_last_smu_auth_err(x) ReadRegBits(DMU_DMU_RST_LAST,0x4000000,26)
#define DMU_DMU_RST_LAST_LAST_SMU_AUTH_ERR_MASK                    0x04000000
#define DMU_DMU_RST_LAST_LAST_SMU_AUTH_ERR_ALIGN                   0
#define DMU_DMU_RST_LAST_LAST_SMU_AUTH_ERR_BITS                    1
#define DMU_DMU_RST_LAST_LAST_SMU_AUTH_ERR_SHIFT                   26

/* DMU :: dmu_rst_last :: last_mem_uncorrectable [25:25] */
#define Wr_DMU_dmu_rst_last_last_mem_uncorrectable(x) WriteRegBits(DMU_DMU_RST_LAST,0x2000000,25,x)
#define Rd_DMU_dmu_rst_last_last_mem_uncorrectable(x) ReadRegBits(DMU_DMU_RST_LAST,0x2000000,25)
#define DMU_DMU_RST_LAST_LAST_MEM_UNCORRECTABLE_MASK               0x02000000
#define DMU_DMU_RST_LAST_LAST_MEM_UNCORRECTABLE_ALIGN              0
#define DMU_DMU_RST_LAST_LAST_MEM_UNCORRECTABLE_BITS               1
#define DMU_DMU_RST_LAST_LAST_MEM_UNCORRECTABLE_SHIFT              25

/* DMU :: dmu_rst_last :: last_mem_correctable [24:24] */
#define Wr_DMU_dmu_rst_last_last_mem_correctable(x) WriteRegBits(DMU_DMU_RST_LAST,0x1000000,24,x)
#define Rd_DMU_dmu_rst_last_last_mem_correctable(x) ReadRegBits(DMU_DMU_RST_LAST,0x1000000,24)
#define DMU_DMU_RST_LAST_LAST_MEM_CORRECTABLE_MASK                 0x01000000
#define DMU_DMU_RST_LAST_LAST_MEM_CORRECTABLE_ALIGN                0
#define DMU_DMU_RST_LAST_LAST_MEM_CORRECTABLE_BITS                 1
#define DMU_DMU_RST_LAST_LAST_MEM_CORRECTABLE_SHIFT                24

/* DMU :: dmu_rst_last :: reserved0 [23:21] */
#define DMU_DMU_RST_LAST_RESERVED0_MASK                            0x00e00000
#define DMU_DMU_RST_LAST_RESERVED0_ALIGN                           0
#define DMU_DMU_RST_LAST_RESERVED0_BITS                            3
#define DMU_DMU_RST_LAST_RESERVED0_SHIFT                           21

/* DMU :: dmu_rst_last :: last_pmb_sbma_update_fail [20:20] */
#define Wr_DMU_dmu_rst_last_last_pmb_sbma_update_fail(x) WriteRegBits(DMU_DMU_RST_LAST,0x100000,20,x)
#define Rd_DMU_dmu_rst_last_last_pmb_sbma_update_fail(x) ReadRegBits(DMU_DMU_RST_LAST,0x100000,20)
#define DMU_DMU_RST_LAST_LAST_PMB_SBMA_UPDATE_FAIL_MASK            0x00100000
#define DMU_DMU_RST_LAST_LAST_PMB_SBMA_UPDATE_FAIL_ALIGN           0
#define DMU_DMU_RST_LAST_LAST_PMB_SBMA_UPDATE_FAIL_BITS            1
#define DMU_DMU_RST_LAST_LAST_PMB_SBMA_UPDATE_FAIL_SHIFT           20

/* DMU :: dmu_rst_last :: last_pmb_entry_mon_fail [19:19] */
#define Wr_DMU_dmu_rst_last_last_pmb_entry_mon_fail(x) WriteRegBits(DMU_DMU_RST_LAST,0x80000,19,x)
#define Rd_DMU_dmu_rst_last_last_pmb_entry_mon_fail(x) ReadRegBits(DMU_DMU_RST_LAST,0x80000,19)
#define DMU_DMU_RST_LAST_LAST_PMB_ENTRY_MON_FAIL_MASK              0x00080000
#define DMU_DMU_RST_LAST_LAST_PMB_ENTRY_MON_FAIL_ALIGN             0
#define DMU_DMU_RST_LAST_LAST_PMB_ENTRY_MON_FAIL_BITS              1
#define DMU_DMU_RST_LAST_LAST_PMB_ENTRY_MON_FAIL_SHIFT             19

/* DMU :: dmu_rst_last :: last_pmb_exit_mon_fail [18:18] */
#define Wr_DMU_dmu_rst_last_last_pmb_exit_mon_fail(x) WriteRegBits(DMU_DMU_RST_LAST,0x40000,18,x)
#define Rd_DMU_dmu_rst_last_last_pmb_exit_mon_fail(x) ReadRegBits(DMU_DMU_RST_LAST,0x40000,18)
#define DMU_DMU_RST_LAST_LAST_PMB_EXIT_MON_FAIL_MASK               0x00040000
#define DMU_DMU_RST_LAST_LAST_PMB_EXIT_MON_FAIL_ALIGN              0
#define DMU_DMU_RST_LAST_LAST_PMB_EXIT_MON_FAIL_BITS               1
#define DMU_DMU_RST_LAST_LAST_PMB_EXIT_MON_FAIL_SHIFT              18

/* DMU :: dmu_rst_last :: last_pmb_coproc_mon_fail [17:17] */
#define Wr_DMU_dmu_rst_last_last_pmb_coproc_mon_fail(x) WriteRegBits(DMU_DMU_RST_LAST,0x20000,17,x)
#define Rd_DMU_dmu_rst_last_last_pmb_coproc_mon_fail(x) ReadRegBits(DMU_DMU_RST_LAST,0x20000,17)
#define DMU_DMU_RST_LAST_LAST_PMB_COPROC_MON_FAIL_MASK             0x00020000
#define DMU_DMU_RST_LAST_LAST_PMB_COPROC_MON_FAIL_ALIGN            0
#define DMU_DMU_RST_LAST_LAST_PMB_COPROC_MON_FAIL_BITS             1
#define DMU_DMU_RST_LAST_LAST_PMB_COPROC_MON_FAIL_SHIFT            17

/* DMU :: dmu_rst_last :: last_pmb_par_err [16:16] */
#define Wr_DMU_dmu_rst_last_last_pmb_par_err(x) WriteRegBits(DMU_DMU_RST_LAST,0x10000,16,x)
#define Rd_DMU_dmu_rst_last_last_pmb_par_err(x) ReadRegBits(DMU_DMU_RST_LAST,0x10000,16)
#define DMU_DMU_RST_LAST_LAST_PMB_PAR_ERR_MASK                     0x00010000
#define DMU_DMU_RST_LAST_LAST_PMB_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_LAST_LAST_PMB_PAR_ERR_BITS                     1
#define DMU_DMU_RST_LAST_LAST_PMB_PAR_ERR_SHIFT                    16

/* DMU :: dmu_rst_last :: last_arm_par_err [15:15] */
#define Wr_DMU_dmu_rst_last_last_arm_par_err(x) WriteRegBits(DMU_DMU_RST_LAST,0x8000,15,x)
#define Rd_DMU_dmu_rst_last_last_arm_par_err(x) ReadRegBits(DMU_DMU_RST_LAST,0x8000,15)
#define DMU_DMU_RST_LAST_LAST_ARM_PAR_ERR_MASK                     0x00008000
#define DMU_DMU_RST_LAST_LAST_ARM_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_LAST_LAST_ARM_PAR_ERR_BITS                     1
#define DMU_DMU_RST_LAST_LAST_ARM_PAR_ERR_SHIFT                    15

/* DMU :: dmu_rst_last :: last_bbl_par_err [14:14] */
#define Wr_DMU_dmu_rst_last_last_bbl_par_err(x) WriteRegBits(DMU_DMU_RST_LAST,0x4000,14,x)
#define Rd_DMU_dmu_rst_last_last_bbl_par_err(x) ReadRegBits(DMU_DMU_RST_LAST,0x4000,14)
#define DMU_DMU_RST_LAST_LAST_BBL_PAR_ERR_MASK                     0x00004000
#define DMU_DMU_RST_LAST_LAST_BBL_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_LAST_LAST_BBL_PAR_ERR_BITS                     1
#define DMU_DMU_RST_LAST_LAST_BBL_PAR_ERR_SHIFT                    14

/* DMU :: dmu_rst_last :: last_usb_par_err [13:13] */
#define Wr_DMU_dmu_rst_last_last_usb_par_err(x) WriteRegBits(DMU_DMU_RST_LAST,0x2000,13,x)
#define Rd_DMU_dmu_rst_last_last_usb_par_err(x) ReadRegBits(DMU_DMU_RST_LAST,0x2000,13)
#define DMU_DMU_RST_LAST_LAST_USB_PAR_ERR_MASK                     0x00002000
#define DMU_DMU_RST_LAST_LAST_USB_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_LAST_LAST_USB_PAR_ERR_BITS                     1
#define DMU_DMU_RST_LAST_LAST_USB_PAR_ERR_SHIFT                    13

/* DMU :: dmu_rst_last :: last_sbma_mismatch [12:12] */
#define Wr_DMU_dmu_rst_last_last_sbma_mismatch(x) WriteRegBits(DMU_DMU_RST_LAST,0x1000,12,x)
#define Rd_DMU_dmu_rst_last_last_sbma_mismatch(x) ReadRegBits(DMU_DMU_RST_LAST,0x1000,12)
#define DMU_DMU_RST_LAST_LAST_SBMA_MISMATCH_MASK                   0x00001000
#define DMU_DMU_RST_LAST_LAST_SBMA_MISMATCH_ALIGN                  0
#define DMU_DMU_RST_LAST_LAST_SBMA_MISMATCH_BITS                   1
#define DMU_DMU_RST_LAST_LAST_SBMA_MISMATCH_SHIFT                  12

/* DMU :: dmu_rst_last :: last_open_wdog [11:11] */
#define Wr_DMU_dmu_rst_last_last_open_wdog(x) WriteRegBits(DMU_DMU_RST_LAST,0x800,11,x)
#define Rd_DMU_dmu_rst_last_last_open_wdog(x) ReadRegBits(DMU_DMU_RST_LAST,0x800,11)
#define DMU_DMU_RST_LAST_LAST_OPEN_WDOG_MASK                       0x00000800
#define DMU_DMU_RST_LAST_LAST_OPEN_WDOG_ALIGN                      0
#define DMU_DMU_RST_LAST_LAST_OPEN_WDOG_BITS                       1
#define DMU_DMU_RST_LAST_LAST_OPEN_WDOG_SHIFT                      11

/* DMU :: dmu_rst_last :: last_spl_pvt_event [10:10] */
#define Wr_DMU_dmu_rst_last_last_spl_pvt_event(x) WriteRegBits(DMU_DMU_RST_LAST,0x400,10,x)
#define Rd_DMU_dmu_rst_last_last_spl_pvt_event(x) ReadRegBits(DMU_DMU_RST_LAST,0x400,10)
#define DMU_DMU_RST_LAST_LAST_SPL_PVT_EVENT_MASK                   0x00000400
#define DMU_DMU_RST_LAST_LAST_SPL_PVT_EVENT_ALIGN                  0
#define DMU_DMU_RST_LAST_LAST_SPL_PVT_EVENT_BITS                   1
#define DMU_DMU_RST_LAST_LAST_SPL_PVT_EVENT_SHIFT                  10

/* DMU :: dmu_rst_last :: last_spl_rst_event [09:09] */
#define Wr_DMU_dmu_rst_last_last_spl_rst_event(x) WriteRegBits(DMU_DMU_RST_LAST,0x200,9,x)
#define Rd_DMU_dmu_rst_last_last_spl_rst_event(x) ReadRegBits(DMU_DMU_RST_LAST,0x200,9)
#define DMU_DMU_RST_LAST_LAST_SPL_RST_EVENT_MASK                   0x00000200
#define DMU_DMU_RST_LAST_LAST_SPL_RST_EVENT_ALIGN                  0
#define DMU_DMU_RST_LAST_LAST_SPL_RST_EVENT_BITS                   1
#define DMU_DMU_RST_LAST_LAST_SPL_RST_EVENT_SHIFT                  9

/* DMU :: dmu_rst_last :: last_spl_wdog_event [08:08] */
#define Wr_DMU_dmu_rst_last_last_spl_wdog_event(x) WriteRegBits(DMU_DMU_RST_LAST,0x100,8,x)
#define Rd_DMU_dmu_rst_last_last_spl_wdog_event(x) ReadRegBits(DMU_DMU_RST_LAST,0x100,8)
#define DMU_DMU_RST_LAST_LAST_SPL_WDOG_EVENT_MASK                  0x00000100
#define DMU_DMU_RST_LAST_LAST_SPL_WDOG_EVENT_ALIGN                 0
#define DMU_DMU_RST_LAST_LAST_SPL_WDOG_EVENT_BITS                  1
#define DMU_DMU_RST_LAST_LAST_SPL_WDOG_EVENT_SHIFT                 8

/* DMU :: dmu_rst_last :: last_spl_freq_event [07:07] */
#define Wr_DMU_dmu_rst_last_last_spl_freq_event(x) WriteRegBits(DMU_DMU_RST_LAST,0x80,7,x)
#define Rd_DMU_dmu_rst_last_last_spl_freq_event(x) ReadRegBits(DMU_DMU_RST_LAST,0x80,7)
#define DMU_DMU_RST_LAST_LAST_SPL_FREQ_EVENT_MASK                  0x00000080
#define DMU_DMU_RST_LAST_LAST_SPL_FREQ_EVENT_ALIGN                 0
#define DMU_DMU_RST_LAST_LAST_SPL_FREQ_EVENT_BITS                  1
#define DMU_DMU_RST_LAST_LAST_SPL_FREQ_EVENT_SHIFT                 7

/* DMU :: dmu_rst_last :: reserved1 [06:05] */
#define DMU_DMU_RST_LAST_RESERVED1_MASK                            0x00000060
#define DMU_DMU_RST_LAST_RESERVED1_ALIGN                           0
#define DMU_DMU_RST_LAST_RESERVED1_BITS                            2
#define DMU_DMU_RST_LAST_RESERVED1_SHIFT                           5

/* DMU :: dmu_rst_last :: last_tamper [04:04] */
#define Wr_DMU_dmu_rst_last_last_tamper(x) WriteRegBits(DMU_DMU_RST_LAST,0x10,4,x)
#define Rd_DMU_dmu_rst_last_last_tamper(x) ReadRegBits(DMU_DMU_RST_LAST,0x10,4)
#define DMU_DMU_RST_LAST_LAST_TAMPER_MASK                          0x00000010
#define DMU_DMU_RST_LAST_LAST_TAMPER_ALIGN                         0
#define DMU_DMU_RST_LAST_LAST_TAMPER_BITS                          1
#define DMU_DMU_RST_LAST_LAST_TAMPER_SHIFT                         4

/* DMU :: dmu_rst_last :: last_pwd_err [03:03] */
#define Wr_DMU_dmu_rst_last_last_pwd_err(x) WriteRegBits(DMU_DMU_RST_LAST,0x8,3,x)
#define Rd_DMU_dmu_rst_last_last_pwd_err(x) ReadRegBits(DMU_DMU_RST_LAST,0x8,3)
#define DMU_DMU_RST_LAST_LAST_PWD_ERR_MASK                         0x00000008
#define DMU_DMU_RST_LAST_LAST_PWD_ERR_ALIGN                        0
#define DMU_DMU_RST_LAST_LAST_PWD_ERR_BITS                         1
#define DMU_DMU_RST_LAST_LAST_PWD_ERR_SHIFT                        3

/* DMU :: dmu_rst_last :: last_acc_err [02:02] */
#define Wr_DMU_dmu_rst_last_last_acc_err(x) WriteRegBits(DMU_DMU_RST_LAST,0x4,2,x)
#define Rd_DMU_dmu_rst_last_last_acc_err(x) ReadRegBits(DMU_DMU_RST_LAST,0x4,2)
#define DMU_DMU_RST_LAST_LAST_ACC_ERR_MASK                         0x00000004
#define DMU_DMU_RST_LAST_LAST_ACC_ERR_ALIGN                        0
#define DMU_DMU_RST_LAST_LAST_ACC_ERR_BITS                         1
#define DMU_DMU_RST_LAST_LAST_ACC_ERR_SHIFT                        2

/* DMU :: dmu_rst_last :: last_deepsleep_exit [01:01] */
#define Wr_DMU_dmu_rst_last_last_deepsleep_exit(x) WriteRegBits(DMU_DMU_RST_LAST,0x2,1,x)
#define Rd_DMU_dmu_rst_last_last_deepsleep_exit(x) ReadRegBits(DMU_DMU_RST_LAST,0x2,1)
#define DMU_DMU_RST_LAST_LAST_DEEPSLEEP_EXIT_MASK                  0x00000002
#define DMU_DMU_RST_LAST_LAST_DEEPSLEEP_EXIT_ALIGN                 0
#define DMU_DMU_RST_LAST_LAST_DEEPSLEEP_EXIT_BITS                  1
#define DMU_DMU_RST_LAST_LAST_DEEPSLEEP_EXIT_SHIFT                 1

/* DMU :: dmu_rst_last :: last_dmu_swrst [00:00] */
#define Wr_DMU_dmu_rst_last_last_dmu_swrst(x) WriteRegBits(DMU_DMU_RST_LAST,0x1,0,x)
#define Rd_DMU_dmu_rst_last_last_dmu_swrst(x) ReadRegBits(DMU_DMU_RST_LAST,0x1,0)
#define DMU_DMU_RST_LAST_LAST_DMU_SWRST_MASK                       0x00000001
#define DMU_DMU_RST_LAST_LAST_DMU_SWRST_ALIGN                      0
#define DMU_DMU_RST_LAST_LAST_DMU_SWRST_BITS                       1
#define DMU_DMU_RST_LAST_LAST_DMU_SWRST_SHIFT                      0


/****************************************************************************
 * DMU :: dmu_rst_raw
 ***************************************************************************/
/* DMU :: dmu_rst_raw :: raw_ram_uncorrectable [31:31] */
#define Wr_DMU_dmu_rst_raw_raw_ram_uncorrectable(x) WriteRegBits(DMU_DMU_RST_RAW,0x80000000,31,x)
#define Rd_DMU_dmu_rst_raw_raw_ram_uncorrectable(x) ReadRegBits(DMU_DMU_RST_RAW,0x80000000,31)
#define DMU_DMU_RST_RAW_RAW_RAM_UNCORRECTABLE_MASK                 0x80000000
#define DMU_DMU_RST_RAW_RAW_RAM_UNCORRECTABLE_ALIGN                0
#define DMU_DMU_RST_RAW_RAW_RAM_UNCORRECTABLE_BITS                 1
#define DMU_DMU_RST_RAW_RAW_RAM_UNCORRECTABLE_SHIFT                31

/* DMU :: dmu_rst_raw :: raw_rng_interrupt [30:30] */
#define Wr_DMU_dmu_rst_raw_raw_rng_interrupt(x) WriteRegBits(DMU_DMU_RST_RAW,0x40000000,30,x)
#define Rd_DMU_dmu_rst_raw_raw_rng_interrupt(x) ReadRegBits(DMU_DMU_RST_RAW,0x40000000,30)
#define DMU_DMU_RST_RAW_RAW_RNG_INTERRUPT_MASK                     0x40000000
#define DMU_DMU_RST_RAW_RAW_RNG_INTERRUPT_ALIGN                    0
#define DMU_DMU_RST_RAW_RAW_RNG_INTERRUPT_BITS                     1
#define DMU_DMU_RST_RAW_RAW_RNG_INTERRUPT_SHIFT                    30

/* DMU :: dmu_rst_raw :: raw_tamper_l1 [29:29] */
#define Wr_DMU_dmu_rst_raw_raw_tamper_l1(x) WriteRegBits(DMU_DMU_RST_RAW,0x20000000,29,x)
#define Rd_DMU_dmu_rst_raw_raw_tamper_l1(x) ReadRegBits(DMU_DMU_RST_RAW,0x20000000,29)
#define DMU_DMU_RST_RAW_RAW_TAMPER_L1_MASK                         0x20000000
#define DMU_DMU_RST_RAW_RAW_TAMPER_L1_ALIGN                        0
#define DMU_DMU_RST_RAW_RAW_TAMPER_L1_BITS                         1
#define DMU_DMU_RST_RAW_RAW_TAMPER_L1_SHIFT                        29

/* DMU :: dmu_rst_raw :: raw_ram_correctable [28:28] */
#define Wr_DMU_dmu_rst_raw_raw_ram_correctable(x) WriteRegBits(DMU_DMU_RST_RAW,0x10000000,28,x)
#define Rd_DMU_dmu_rst_raw_raw_ram_correctable(x) ReadRegBits(DMU_DMU_RST_RAW,0x10000000,28)
#define DMU_DMU_RST_RAW_RAW_RAM_CORRECTABLE_MASK                   0x10000000
#define DMU_DMU_RST_RAW_RAW_RAM_CORRECTABLE_ALIGN                  0
#define DMU_DMU_RST_RAW_RAW_RAM_CORRECTABLE_BITS                   1
#define DMU_DMU_RST_RAW_RAW_RAM_CORRECTABLE_SHIFT                  28

/* DMU :: dmu_rst_raw :: raw_smu_par_err [27:27] */
#define Wr_DMU_dmu_rst_raw_raw_smu_par_err(x) WriteRegBits(DMU_DMU_RST_RAW,0x8000000,27,x)
#define Rd_DMU_dmu_rst_raw_raw_smu_par_err(x) ReadRegBits(DMU_DMU_RST_RAW,0x8000000,27)
#define DMU_DMU_RST_RAW_RAW_SMU_PAR_ERR_MASK                       0x08000000
#define DMU_DMU_RST_RAW_RAW_SMU_PAR_ERR_ALIGN                      0
#define DMU_DMU_RST_RAW_RAW_SMU_PAR_ERR_BITS                       1
#define DMU_DMU_RST_RAW_RAW_SMU_PAR_ERR_SHIFT                      27

/* DMU :: dmu_rst_raw :: raw_smu_auth_err [26:26] */
#define Wr_DMU_dmu_rst_raw_raw_smu_auth_err(x) WriteRegBits(DMU_DMU_RST_RAW,0x4000000,26,x)
#define Rd_DMU_dmu_rst_raw_raw_smu_auth_err(x) ReadRegBits(DMU_DMU_RST_RAW,0x4000000,26)
#define DMU_DMU_RST_RAW_RAW_SMU_AUTH_ERR_MASK                      0x04000000
#define DMU_DMU_RST_RAW_RAW_SMU_AUTH_ERR_ALIGN                     0
#define DMU_DMU_RST_RAW_RAW_SMU_AUTH_ERR_BITS                      1
#define DMU_DMU_RST_RAW_RAW_SMU_AUTH_ERR_SHIFT                     26

/* DMU :: dmu_rst_raw :: raw_mem_uncorrectable [25:25] */
#define Wr_DMU_dmu_rst_raw_raw_mem_uncorrectable(x) WriteRegBits(DMU_DMU_RST_RAW,0x2000000,25,x)
#define Rd_DMU_dmu_rst_raw_raw_mem_uncorrectable(x) ReadRegBits(DMU_DMU_RST_RAW,0x2000000,25)
#define DMU_DMU_RST_RAW_RAW_MEM_UNCORRECTABLE_MASK                 0x02000000
#define DMU_DMU_RST_RAW_RAW_MEM_UNCORRECTABLE_ALIGN                0
#define DMU_DMU_RST_RAW_RAW_MEM_UNCORRECTABLE_BITS                 1
#define DMU_DMU_RST_RAW_RAW_MEM_UNCORRECTABLE_SHIFT                25

/* DMU :: dmu_rst_raw :: raw_mem_correctable [24:24] */
#define Wr_DMU_dmu_rst_raw_raw_mem_correctable(x) WriteRegBits(DMU_DMU_RST_RAW,0x1000000,24,x)
#define Rd_DMU_dmu_rst_raw_raw_mem_correctable(x) ReadRegBits(DMU_DMU_RST_RAW,0x1000000,24)
#define DMU_DMU_RST_RAW_RAW_MEM_CORRECTABLE_MASK                   0x01000000
#define DMU_DMU_RST_RAW_RAW_MEM_CORRECTABLE_ALIGN                  0
#define DMU_DMU_RST_RAW_RAW_MEM_CORRECTABLE_BITS                   1
#define DMU_DMU_RST_RAW_RAW_MEM_CORRECTABLE_SHIFT                  24

/* DMU :: dmu_rst_raw :: reserved0 [23:21] */
#define DMU_DMU_RST_RAW_RESERVED0_MASK                             0x00e00000
#define DMU_DMU_RST_RAW_RESERVED0_ALIGN                            0
#define DMU_DMU_RST_RAW_RESERVED0_BITS                             3
#define DMU_DMU_RST_RAW_RESERVED0_SHIFT                            21

/* DMU :: dmu_rst_raw :: raw_pmb_sbma_update_fail [20:20] */
#define Wr_DMU_dmu_rst_raw_raw_pmb_sbma_update_fail(x) WriteRegBits(DMU_DMU_RST_RAW,0x100000,20,x)
#define Rd_DMU_dmu_rst_raw_raw_pmb_sbma_update_fail(x) ReadRegBits(DMU_DMU_RST_RAW,0x100000,20)
#define DMU_DMU_RST_RAW_RAW_PMB_SBMA_UPDATE_FAIL_MASK              0x00100000
#define DMU_DMU_RST_RAW_RAW_PMB_SBMA_UPDATE_FAIL_ALIGN             0
#define DMU_DMU_RST_RAW_RAW_PMB_SBMA_UPDATE_FAIL_BITS              1
#define DMU_DMU_RST_RAW_RAW_PMB_SBMA_UPDATE_FAIL_SHIFT             20

/* DMU :: dmu_rst_raw :: raw_pmb_entry_mon_fail [19:19] */
#define Wr_DMU_dmu_rst_raw_raw_pmb_entry_mon_fail(x) WriteRegBits(DMU_DMU_RST_RAW,0x80000,19,x)
#define Rd_DMU_dmu_rst_raw_raw_pmb_entry_mon_fail(x) ReadRegBits(DMU_DMU_RST_RAW,0x80000,19)
#define DMU_DMU_RST_RAW_RAW_PMB_ENTRY_MON_FAIL_MASK                0x00080000
#define DMU_DMU_RST_RAW_RAW_PMB_ENTRY_MON_FAIL_ALIGN               0
#define DMU_DMU_RST_RAW_RAW_PMB_ENTRY_MON_FAIL_BITS                1
#define DMU_DMU_RST_RAW_RAW_PMB_ENTRY_MON_FAIL_SHIFT               19

/* DMU :: dmu_rst_raw :: raw_pmb_exit_mon_fail [18:18] */
#define Wr_DMU_dmu_rst_raw_raw_pmb_exit_mon_fail(x) WriteRegBits(DMU_DMU_RST_RAW,0x40000,18,x)
#define Rd_DMU_dmu_rst_raw_raw_pmb_exit_mon_fail(x) ReadRegBits(DMU_DMU_RST_RAW,0x40000,18)
#define DMU_DMU_RST_RAW_RAW_PMB_EXIT_MON_FAIL_MASK                 0x00040000
#define DMU_DMU_RST_RAW_RAW_PMB_EXIT_MON_FAIL_ALIGN                0
#define DMU_DMU_RST_RAW_RAW_PMB_EXIT_MON_FAIL_BITS                 1
#define DMU_DMU_RST_RAW_RAW_PMB_EXIT_MON_FAIL_SHIFT                18

/* DMU :: dmu_rst_raw :: raw_pmb_coproc_mon_fail [17:17] */
#define Wr_DMU_dmu_rst_raw_raw_pmb_coproc_mon_fail(x) WriteRegBits(DMU_DMU_RST_RAW,0x20000,17,x)
#define Rd_DMU_dmu_rst_raw_raw_pmb_coproc_mon_fail(x) ReadRegBits(DMU_DMU_RST_RAW,0x20000,17)
#define DMU_DMU_RST_RAW_RAW_PMB_COPROC_MON_FAIL_MASK               0x00020000
#define DMU_DMU_RST_RAW_RAW_PMB_COPROC_MON_FAIL_ALIGN              0
#define DMU_DMU_RST_RAW_RAW_PMB_COPROC_MON_FAIL_BITS               1
#define DMU_DMU_RST_RAW_RAW_PMB_COPROC_MON_FAIL_SHIFT              17

/* DMU :: dmu_rst_raw :: raw_pmb_par_err [16:16] */
#define Wr_DMU_dmu_rst_raw_raw_pmb_par_err(x) WriteRegBits(DMU_DMU_RST_RAW,0x10000,16,x)
#define Rd_DMU_dmu_rst_raw_raw_pmb_par_err(x) ReadRegBits(DMU_DMU_RST_RAW,0x10000,16)
#define DMU_DMU_RST_RAW_RAW_PMB_PAR_ERR_MASK                       0x00010000
#define DMU_DMU_RST_RAW_RAW_PMB_PAR_ERR_ALIGN                      0
#define DMU_DMU_RST_RAW_RAW_PMB_PAR_ERR_BITS                       1
#define DMU_DMU_RST_RAW_RAW_PMB_PAR_ERR_SHIFT                      16

/* DMU :: dmu_rst_raw :: raw_arm_par_err [15:15] */
#define Wr_DMU_dmu_rst_raw_raw_arm_par_err(x) WriteRegBits(DMU_DMU_RST_RAW,0x8000,15,x)
#define Rd_DMU_dmu_rst_raw_raw_arm_par_err(x) ReadRegBits(DMU_DMU_RST_RAW,0x8000,15)
#define DMU_DMU_RST_RAW_RAW_ARM_PAR_ERR_MASK                       0x00008000
#define DMU_DMU_RST_RAW_RAW_ARM_PAR_ERR_ALIGN                      0
#define DMU_DMU_RST_RAW_RAW_ARM_PAR_ERR_BITS                       1
#define DMU_DMU_RST_RAW_RAW_ARM_PAR_ERR_SHIFT                      15

/* DMU :: dmu_rst_raw :: raw_bbl_par_err [14:14] */
#define Wr_DMU_dmu_rst_raw_raw_bbl_par_err(x) WriteRegBits(DMU_DMU_RST_RAW,0x4000,14,x)
#define Rd_DMU_dmu_rst_raw_raw_bbl_par_err(x) ReadRegBits(DMU_DMU_RST_RAW,0x4000,14)
#define DMU_DMU_RST_RAW_RAW_BBL_PAR_ERR_MASK                       0x00004000
#define DMU_DMU_RST_RAW_RAW_BBL_PAR_ERR_ALIGN                      0
#define DMU_DMU_RST_RAW_RAW_BBL_PAR_ERR_BITS                       1
#define DMU_DMU_RST_RAW_RAW_BBL_PAR_ERR_SHIFT                      14

/* DMU :: dmu_rst_raw :: raw_usb_par_err [13:13] */
#define Wr_DMU_dmu_rst_raw_raw_usb_par_err(x) WriteRegBits(DMU_DMU_RST_RAW,0x2000,13,x)
#define Rd_DMU_dmu_rst_raw_raw_usb_par_err(x) ReadRegBits(DMU_DMU_RST_RAW,0x2000,13)
#define DMU_DMU_RST_RAW_RAW_USB_PAR_ERR_MASK                       0x00002000
#define DMU_DMU_RST_RAW_RAW_USB_PAR_ERR_ALIGN                      0
#define DMU_DMU_RST_RAW_RAW_USB_PAR_ERR_BITS                       1
#define DMU_DMU_RST_RAW_RAW_USB_PAR_ERR_SHIFT                      13

/* DMU :: dmu_rst_raw :: raw_sbma_mismatch [12:12] */
#define Wr_DMU_dmu_rst_raw_raw_sbma_mismatch(x) WriteRegBits(DMU_DMU_RST_RAW,0x1000,12,x)
#define Rd_DMU_dmu_rst_raw_raw_sbma_mismatch(x) ReadRegBits(DMU_DMU_RST_RAW,0x1000,12)
#define DMU_DMU_RST_RAW_RAW_SBMA_MISMATCH_MASK                     0x00001000
#define DMU_DMU_RST_RAW_RAW_SBMA_MISMATCH_ALIGN                    0
#define DMU_DMU_RST_RAW_RAW_SBMA_MISMATCH_BITS                     1
#define DMU_DMU_RST_RAW_RAW_SBMA_MISMATCH_SHIFT                    12

/* DMU :: dmu_rst_raw :: raw_open_wdog [11:11] */
#define Wr_DMU_dmu_rst_raw_raw_open_wdog(x) WriteRegBits(DMU_DMU_RST_RAW,0x800,11,x)
#define Rd_DMU_dmu_rst_raw_raw_open_wdog(x) ReadRegBits(DMU_DMU_RST_RAW,0x800,11)
#define DMU_DMU_RST_RAW_RAW_OPEN_WDOG_MASK                         0x00000800
#define DMU_DMU_RST_RAW_RAW_OPEN_WDOG_ALIGN                        0
#define DMU_DMU_RST_RAW_RAW_OPEN_WDOG_BITS                         1
#define DMU_DMU_RST_RAW_RAW_OPEN_WDOG_SHIFT                        11

/* DMU :: dmu_rst_raw :: raw_spl_pvt_event [10:10] */
#define Wr_DMU_dmu_rst_raw_raw_spl_pvt_event(x) WriteRegBits(DMU_DMU_RST_RAW,0x400,10,x)
#define Rd_DMU_dmu_rst_raw_raw_spl_pvt_event(x) ReadRegBits(DMU_DMU_RST_RAW,0x400,10)
#define DMU_DMU_RST_RAW_RAW_SPL_PVT_EVENT_MASK                     0x00000400
#define DMU_DMU_RST_RAW_RAW_SPL_PVT_EVENT_ALIGN                    0
#define DMU_DMU_RST_RAW_RAW_SPL_PVT_EVENT_BITS                     1
#define DMU_DMU_RST_RAW_RAW_SPL_PVT_EVENT_SHIFT                    10

/* DMU :: dmu_rst_raw :: raw_spl_rst_event [09:09] */
#define Wr_DMU_dmu_rst_raw_raw_spl_rst_event(x) WriteRegBits(DMU_DMU_RST_RAW,0x200,9,x)
#define Rd_DMU_dmu_rst_raw_raw_spl_rst_event(x) ReadRegBits(DMU_DMU_RST_RAW,0x200,9)
#define DMU_DMU_RST_RAW_RAW_SPL_RST_EVENT_MASK                     0x00000200
#define DMU_DMU_RST_RAW_RAW_SPL_RST_EVENT_ALIGN                    0
#define DMU_DMU_RST_RAW_RAW_SPL_RST_EVENT_BITS                     1
#define DMU_DMU_RST_RAW_RAW_SPL_RST_EVENT_SHIFT                    9

/* DMU :: dmu_rst_raw :: raw_spl_wdog_event [08:08] */
#define Wr_DMU_dmu_rst_raw_raw_spl_wdog_event(x) WriteRegBits(DMU_DMU_RST_RAW,0x100,8,x)
#define Rd_DMU_dmu_rst_raw_raw_spl_wdog_event(x) ReadRegBits(DMU_DMU_RST_RAW,0x100,8)
#define DMU_DMU_RST_RAW_RAW_SPL_WDOG_EVENT_MASK                    0x00000100
#define DMU_DMU_RST_RAW_RAW_SPL_WDOG_EVENT_ALIGN                   0
#define DMU_DMU_RST_RAW_RAW_SPL_WDOG_EVENT_BITS                    1
#define DMU_DMU_RST_RAW_RAW_SPL_WDOG_EVENT_SHIFT                   8

/* DMU :: dmu_rst_raw :: raw_spl_freq_event [07:07] */
#define Wr_DMU_dmu_rst_raw_raw_spl_freq_event(x) WriteRegBits(DMU_DMU_RST_RAW,0x80,7,x)
#define Rd_DMU_dmu_rst_raw_raw_spl_freq_event(x) ReadRegBits(DMU_DMU_RST_RAW,0x80,7)
#define DMU_DMU_RST_RAW_RAW_SPL_FREQ_EVENT_MASK                    0x00000080
#define DMU_DMU_RST_RAW_RAW_SPL_FREQ_EVENT_ALIGN                   0
#define DMU_DMU_RST_RAW_RAW_SPL_FREQ_EVENT_BITS                    1
#define DMU_DMU_RST_RAW_RAW_SPL_FREQ_EVENT_SHIFT                   7

/* DMU :: dmu_rst_raw :: reserved1 [06:05] */
#define DMU_DMU_RST_RAW_RESERVED1_MASK                             0x00000060
#define DMU_DMU_RST_RAW_RESERVED1_ALIGN                            0
#define DMU_DMU_RST_RAW_RESERVED1_BITS                             2
#define DMU_DMU_RST_RAW_RESERVED1_SHIFT                            5

/* DMU :: dmu_rst_raw :: raw_tamper [04:04] */
#define Wr_DMU_dmu_rst_raw_raw_tamper(x) WriteRegBits(DMU_DMU_RST_RAW,0x10,4,x)
#define Rd_DMU_dmu_rst_raw_raw_tamper(x) ReadRegBits(DMU_DMU_RST_RAW,0x10,4)
#define DMU_DMU_RST_RAW_RAW_TAMPER_MASK                            0x00000010
#define DMU_DMU_RST_RAW_RAW_TAMPER_ALIGN                           0
#define DMU_DMU_RST_RAW_RAW_TAMPER_BITS                            1
#define DMU_DMU_RST_RAW_RAW_TAMPER_SHIFT                           4

/* DMU :: dmu_rst_raw :: raw_pwd_err [03:03] */
#define Wr_DMU_dmu_rst_raw_raw_pwd_err(x) WriteRegBits(DMU_DMU_RST_RAW,0x8,3,x)
#define Rd_DMU_dmu_rst_raw_raw_pwd_err(x) ReadRegBits(DMU_DMU_RST_RAW,0x8,3)
#define DMU_DMU_RST_RAW_RAW_PWD_ERR_MASK                           0x00000008
#define DMU_DMU_RST_RAW_RAW_PWD_ERR_ALIGN                          0
#define DMU_DMU_RST_RAW_RAW_PWD_ERR_BITS                           1
#define DMU_DMU_RST_RAW_RAW_PWD_ERR_SHIFT                          3

/* DMU :: dmu_rst_raw :: raw_acc_err [02:02] */
#define Wr_DMU_dmu_rst_raw_raw_acc_err(x) WriteRegBits(DMU_DMU_RST_RAW,0x4,2,x)
#define Rd_DMU_dmu_rst_raw_raw_acc_err(x) ReadRegBits(DMU_DMU_RST_RAW,0x4,2)
#define DMU_DMU_RST_RAW_RAW_ACC_ERR_MASK                           0x00000004
#define DMU_DMU_RST_RAW_RAW_ACC_ERR_ALIGN                          0
#define DMU_DMU_RST_RAW_RAW_ACC_ERR_BITS                           1
#define DMU_DMU_RST_RAW_RAW_ACC_ERR_SHIFT                          2

/* DMU :: dmu_rst_raw :: raw_deepsleep_exit [01:01] */
#define Wr_DMU_dmu_rst_raw_raw_deepsleep_exit(x) WriteRegBits(DMU_DMU_RST_RAW,0x2,1,x)
#define Rd_DMU_dmu_rst_raw_raw_deepsleep_exit(x) ReadRegBits(DMU_DMU_RST_RAW,0x2,1)
#define DMU_DMU_RST_RAW_RAW_DEEPSLEEP_EXIT_MASK                    0x00000002
#define DMU_DMU_RST_RAW_RAW_DEEPSLEEP_EXIT_ALIGN                   0
#define DMU_DMU_RST_RAW_RAW_DEEPSLEEP_EXIT_BITS                    1
#define DMU_DMU_RST_RAW_RAW_DEEPSLEEP_EXIT_SHIFT                   1

/* DMU :: dmu_rst_raw :: raw_dmu_swrst [00:00] */
#define Wr_DMU_dmu_rst_raw_raw_dmu_swrst(x) WriteRegBits(DMU_DMU_RST_RAW,0x1,0,x)
#define Rd_DMU_dmu_rst_raw_raw_dmu_swrst(x) ReadRegBits(DMU_DMU_RST_RAW,0x1,0)
#define DMU_DMU_RST_RAW_RAW_DMU_SWRST_MASK                         0x00000001
#define DMU_DMU_RST_RAW_RAW_DMU_SWRST_ALIGN                        0
#define DMU_DMU_RST_RAW_RAW_DMU_SWRST_BITS                         1
#define DMU_DMU_RST_RAW_RAW_DMU_SWRST_SHIFT                        0


/****************************************************************************
 * DMU :: dmu_rst_enable
 ***************************************************************************/
/* DMU :: dmu_rst_enable :: ena_ram_uncorrectable [31:31] */
#define Wr_DMU_dmu_rst_enable_ena_ram_uncorrectable(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x80000000,31,x)
#define Rd_DMU_dmu_rst_enable_ena_ram_uncorrectable(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x80000000,31)
#define DMU_DMU_RST_ENABLE_ENA_RAM_UNCORRECTABLE_MASK              0x80000000
#define DMU_DMU_RST_ENABLE_ENA_RAM_UNCORRECTABLE_ALIGN             0
#define DMU_DMU_RST_ENABLE_ENA_RAM_UNCORRECTABLE_BITS              1
#define DMU_DMU_RST_ENABLE_ENA_RAM_UNCORRECTABLE_SHIFT             31

/* DMU :: dmu_rst_enable :: ena_rng_interrupt [30:30] */
#define Wr_DMU_dmu_rst_enable_ena_rng_interrupt(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x40000000,30,x)
#define Rd_DMU_dmu_rst_enable_ena_rng_interrupt(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x40000000,30)
#define DMU_DMU_RST_ENABLE_ENA_RNG_INTERRUPT_MASK                  0x40000000
#define DMU_DMU_RST_ENABLE_ENA_RNG_INTERRUPT_ALIGN                 0
#define DMU_DMU_RST_ENABLE_ENA_RNG_INTERRUPT_BITS                  1
#define DMU_DMU_RST_ENABLE_ENA_RNG_INTERRUPT_SHIFT                 30

/* DMU :: dmu_rst_enable :: ena_tamper_l1 [29:29] */
#define Wr_DMU_dmu_rst_enable_ena_tamper_l1(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x20000000,29,x)
#define Rd_DMU_dmu_rst_enable_ena_tamper_l1(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x20000000,29)
#define DMU_DMU_RST_ENABLE_ENA_TAMPER_L1_MASK                      0x20000000
#define DMU_DMU_RST_ENABLE_ENA_TAMPER_L1_ALIGN                     0
#define DMU_DMU_RST_ENABLE_ENA_TAMPER_L1_BITS                      1
#define DMU_DMU_RST_ENABLE_ENA_TAMPER_L1_SHIFT                     29

/* DMU :: dmu_rst_enable :: ena_ram_correctable [28:28] */
#define Wr_DMU_dmu_rst_enable_ena_ram_correctable(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x10000000,28,x)
#define Rd_DMU_dmu_rst_enable_ena_ram_correctable(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x10000000,28)
#define DMU_DMU_RST_ENABLE_ENA_RAM_CORRECTABLE_MASK                0x10000000
#define DMU_DMU_RST_ENABLE_ENA_RAM_CORRECTABLE_ALIGN               0
#define DMU_DMU_RST_ENABLE_ENA_RAM_CORRECTABLE_BITS                1
#define DMU_DMU_RST_ENABLE_ENA_RAM_CORRECTABLE_SHIFT               28

/* DMU :: dmu_rst_enable :: ena_smu_par_err [27:27] */
#define Wr_DMU_dmu_rst_enable_ena_smu_par_err(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x8000000,27,x)
#define Rd_DMU_dmu_rst_enable_ena_smu_par_err(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x8000000,27)
#define DMU_DMU_RST_ENABLE_ENA_SMU_PAR_ERR_MASK                    0x08000000
#define DMU_DMU_RST_ENABLE_ENA_SMU_PAR_ERR_ALIGN                   0
#define DMU_DMU_RST_ENABLE_ENA_SMU_PAR_ERR_BITS                    1
#define DMU_DMU_RST_ENABLE_ENA_SMU_PAR_ERR_SHIFT                   27

/* DMU :: dmu_rst_enable :: ena_smu_auth_err [26:26] */
#define Wr_DMU_dmu_rst_enable_ena_smu_auth_err(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x4000000,26,x)
#define Rd_DMU_dmu_rst_enable_ena_smu_auth_err(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x4000000,26)
#define DMU_DMU_RST_ENABLE_ENA_SMU_AUTH_ERR_MASK                   0x04000000
#define DMU_DMU_RST_ENABLE_ENA_SMU_AUTH_ERR_ALIGN                  0
#define DMU_DMU_RST_ENABLE_ENA_SMU_AUTH_ERR_BITS                   1
#define DMU_DMU_RST_ENABLE_ENA_SMU_AUTH_ERR_SHIFT                  26

/* DMU :: dmu_rst_enable :: ena_mem_uncorrectable [25:25] */
#define Wr_DMU_dmu_rst_enable_ena_mem_uncorrectable(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x2000000,25,x)
#define Rd_DMU_dmu_rst_enable_ena_mem_uncorrectable(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x2000000,25)
#define DMU_DMU_RST_ENABLE_ENA_MEM_UNCORRECTABLE_MASK              0x02000000
#define DMU_DMU_RST_ENABLE_ENA_MEM_UNCORRECTABLE_ALIGN             0
#define DMU_DMU_RST_ENABLE_ENA_MEM_UNCORRECTABLE_BITS              1
#define DMU_DMU_RST_ENABLE_ENA_MEM_UNCORRECTABLE_SHIFT             25

/* DMU :: dmu_rst_enable :: ena_mem_correctable [24:24] */
#define Wr_DMU_dmu_rst_enable_ena_mem_correctable(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x1000000,24,x)
#define Rd_DMU_dmu_rst_enable_ena_mem_correctable(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x1000000,24)
#define DMU_DMU_RST_ENABLE_ENA_MEM_CORRECTABLE_MASK                0x01000000
#define DMU_DMU_RST_ENABLE_ENA_MEM_CORRECTABLE_ALIGN               0
#define DMU_DMU_RST_ENABLE_ENA_MEM_CORRECTABLE_BITS                1
#define DMU_DMU_RST_ENABLE_ENA_MEM_CORRECTABLE_SHIFT               24

/* DMU :: dmu_rst_enable :: reserved0 [23:21] */
#define DMU_DMU_RST_ENABLE_RESERVED0_MASK                          0x00e00000
#define DMU_DMU_RST_ENABLE_RESERVED0_ALIGN                         0
#define DMU_DMU_RST_ENABLE_RESERVED0_BITS                          3
#define DMU_DMU_RST_ENABLE_RESERVED0_SHIFT                         21

/* DMU :: dmu_rst_enable :: ena_pmb_sbma_update_fail [20:20] */
#define Wr_DMU_dmu_rst_enable_ena_pmb_sbma_update_fail(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x100000,20,x)
#define Rd_DMU_dmu_rst_enable_ena_pmb_sbma_update_fail(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x100000,20)
#define DMU_DMU_RST_ENABLE_ENA_PMB_SBMA_UPDATE_FAIL_MASK           0x00100000
#define DMU_DMU_RST_ENABLE_ENA_PMB_SBMA_UPDATE_FAIL_ALIGN          0
#define DMU_DMU_RST_ENABLE_ENA_PMB_SBMA_UPDATE_FAIL_BITS           1
#define DMU_DMU_RST_ENABLE_ENA_PMB_SBMA_UPDATE_FAIL_SHIFT          20

/* DMU :: dmu_rst_enable :: ena_pmb_entry_mon_fail [19:19] */
#define Wr_DMU_dmu_rst_enable_ena_pmb_entry_mon_fail(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x80000,19,x)
#define Rd_DMU_dmu_rst_enable_ena_pmb_entry_mon_fail(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x80000,19)
#define DMU_DMU_RST_ENABLE_ENA_PMB_ENTRY_MON_FAIL_MASK             0x00080000
#define DMU_DMU_RST_ENABLE_ENA_PMB_ENTRY_MON_FAIL_ALIGN            0
#define DMU_DMU_RST_ENABLE_ENA_PMB_ENTRY_MON_FAIL_BITS             1
#define DMU_DMU_RST_ENABLE_ENA_PMB_ENTRY_MON_FAIL_SHIFT            19

/* DMU :: dmu_rst_enable :: ena_pmb_exit_mon_fail [18:18] */
#define Wr_DMU_dmu_rst_enable_ena_pmb_exit_mon_fail(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x40000,18,x)
#define Rd_DMU_dmu_rst_enable_ena_pmb_exit_mon_fail(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x40000,18)
#define DMU_DMU_RST_ENABLE_ENA_PMB_EXIT_MON_FAIL_MASK              0x00040000
#define DMU_DMU_RST_ENABLE_ENA_PMB_EXIT_MON_FAIL_ALIGN             0
#define DMU_DMU_RST_ENABLE_ENA_PMB_EXIT_MON_FAIL_BITS              1
#define DMU_DMU_RST_ENABLE_ENA_PMB_EXIT_MON_FAIL_SHIFT             18

/* DMU :: dmu_rst_enable :: ena_pmb_coproc_mon_fail [17:17] */
#define Wr_DMU_dmu_rst_enable_ena_pmb_coproc_mon_fail(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x20000,17,x)
#define Rd_DMU_dmu_rst_enable_ena_pmb_coproc_mon_fail(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x20000,17)
#define DMU_DMU_RST_ENABLE_ENA_PMB_COPROC_MON_FAIL_MASK            0x00020000
#define DMU_DMU_RST_ENABLE_ENA_PMB_COPROC_MON_FAIL_ALIGN           0
#define DMU_DMU_RST_ENABLE_ENA_PMB_COPROC_MON_FAIL_BITS            1
#define DMU_DMU_RST_ENABLE_ENA_PMB_COPROC_MON_FAIL_SHIFT           17

/* DMU :: dmu_rst_enable :: ena_pmb_par_err [16:16] */
#define Wr_DMU_dmu_rst_enable_ena_pmb_par_err(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x10000,16,x)
#define Rd_DMU_dmu_rst_enable_ena_pmb_par_err(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x10000,16)
#define DMU_DMU_RST_ENABLE_ENA_PMB_PAR_ERR_MASK                    0x00010000
#define DMU_DMU_RST_ENABLE_ENA_PMB_PAR_ERR_ALIGN                   0
#define DMU_DMU_RST_ENABLE_ENA_PMB_PAR_ERR_BITS                    1
#define DMU_DMU_RST_ENABLE_ENA_PMB_PAR_ERR_SHIFT                   16

/* DMU :: dmu_rst_enable :: ena_arm_par_err [15:15] */
#define Wr_DMU_dmu_rst_enable_ena_arm_par_err(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x8000,15,x)
#define Rd_DMU_dmu_rst_enable_ena_arm_par_err(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x8000,15)
#define DMU_DMU_RST_ENABLE_ENA_ARM_PAR_ERR_MASK                    0x00008000
#define DMU_DMU_RST_ENABLE_ENA_ARM_PAR_ERR_ALIGN                   0
#define DMU_DMU_RST_ENABLE_ENA_ARM_PAR_ERR_BITS                    1
#define DMU_DMU_RST_ENABLE_ENA_ARM_PAR_ERR_SHIFT                   15

/* DMU :: dmu_rst_enable :: ena_bbl_par_err [14:14] */
#define Wr_DMU_dmu_rst_enable_ena_bbl_par_err(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x4000,14,x)
#define Rd_DMU_dmu_rst_enable_ena_bbl_par_err(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x4000,14)
#define DMU_DMU_RST_ENABLE_ENA_BBL_PAR_ERR_MASK                    0x00004000
#define DMU_DMU_RST_ENABLE_ENA_BBL_PAR_ERR_ALIGN                   0
#define DMU_DMU_RST_ENABLE_ENA_BBL_PAR_ERR_BITS                    1
#define DMU_DMU_RST_ENABLE_ENA_BBL_PAR_ERR_SHIFT                   14

/* DMU :: dmu_rst_enable :: ena_usb_par_err [13:13] */
#define Wr_DMU_dmu_rst_enable_ena_usb_par_err(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x2000,13,x)
#define Rd_DMU_dmu_rst_enable_ena_usb_par_err(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x2000,13)
#define DMU_DMU_RST_ENABLE_ENA_USB_PAR_ERR_MASK                    0x00002000
#define DMU_DMU_RST_ENABLE_ENA_USB_PAR_ERR_ALIGN                   0
#define DMU_DMU_RST_ENABLE_ENA_USB_PAR_ERR_BITS                    1
#define DMU_DMU_RST_ENABLE_ENA_USB_PAR_ERR_SHIFT                   13

/* DMU :: dmu_rst_enable :: ena_sbma_mismatch [12:12] */
#define Wr_DMU_dmu_rst_enable_ena_sbma_mismatch(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x1000,12,x)
#define Rd_DMU_dmu_rst_enable_ena_sbma_mismatch(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x1000,12)
#define DMU_DMU_RST_ENABLE_ENA_SBMA_MISMATCH_MASK                  0x00001000
#define DMU_DMU_RST_ENABLE_ENA_SBMA_MISMATCH_ALIGN                 0
#define DMU_DMU_RST_ENABLE_ENA_SBMA_MISMATCH_BITS                  1
#define DMU_DMU_RST_ENABLE_ENA_SBMA_MISMATCH_SHIFT                 12

/* DMU :: dmu_rst_enable :: ena_open_wdog [11:11] */
#define Wr_DMU_dmu_rst_enable_ena_open_wdog(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x800,11,x)
#define Rd_DMU_dmu_rst_enable_ena_open_wdog(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x800,11)
#define DMU_DMU_RST_ENABLE_ENA_OPEN_WDOG_MASK                      0x00000800
#define DMU_DMU_RST_ENABLE_ENA_OPEN_WDOG_ALIGN                     0
#define DMU_DMU_RST_ENABLE_ENA_OPEN_WDOG_BITS                      1
#define DMU_DMU_RST_ENABLE_ENA_OPEN_WDOG_SHIFT                     11

/* DMU :: dmu_rst_enable :: ena_spl_pvt_event [10:10] */
#define Wr_DMU_dmu_rst_enable_ena_spl_pvt_event(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x400,10,x)
#define Rd_DMU_dmu_rst_enable_ena_spl_pvt_event(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x400,10)
#define DMU_DMU_RST_ENABLE_ENA_SPL_PVT_EVENT_MASK                  0x00000400
#define DMU_DMU_RST_ENABLE_ENA_SPL_PVT_EVENT_ALIGN                 0
#define DMU_DMU_RST_ENABLE_ENA_SPL_PVT_EVENT_BITS                  1
#define DMU_DMU_RST_ENABLE_ENA_SPL_PVT_EVENT_SHIFT                 10

/* DMU :: dmu_rst_enable :: ena_spl_rst_event [09:09] */
#define Wr_DMU_dmu_rst_enable_ena_spl_rst_event(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x200,9,x)
#define Rd_DMU_dmu_rst_enable_ena_spl_rst_event(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x200,9)
#define DMU_DMU_RST_ENABLE_ENA_SPL_RST_EVENT_MASK                  0x00000200
#define DMU_DMU_RST_ENABLE_ENA_SPL_RST_EVENT_ALIGN                 0
#define DMU_DMU_RST_ENABLE_ENA_SPL_RST_EVENT_BITS                  1
#define DMU_DMU_RST_ENABLE_ENA_SPL_RST_EVENT_SHIFT                 9

/* DMU :: dmu_rst_enable :: ena_spl_wdog_event [08:08] */
#define Wr_DMU_dmu_rst_enable_ena_spl_wdog_event(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x100,8,x)
#define Rd_DMU_dmu_rst_enable_ena_spl_wdog_event(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x100,8)
#define DMU_DMU_RST_ENABLE_ENA_SPL_WDOG_EVENT_MASK                 0x00000100
#define DMU_DMU_RST_ENABLE_ENA_SPL_WDOG_EVENT_ALIGN                0
#define DMU_DMU_RST_ENABLE_ENA_SPL_WDOG_EVENT_BITS                 1
#define DMU_DMU_RST_ENABLE_ENA_SPL_WDOG_EVENT_SHIFT                8

/* DMU :: dmu_rst_enable :: ena_spl_freq_event [07:07] */
#define Wr_DMU_dmu_rst_enable_ena_spl_freq_event(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x80,7,x)
#define Rd_DMU_dmu_rst_enable_ena_spl_freq_event(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x80,7)
#define DMU_DMU_RST_ENABLE_ENA_SPL_FREQ_EVENT_MASK                 0x00000080
#define DMU_DMU_RST_ENABLE_ENA_SPL_FREQ_EVENT_ALIGN                0
#define DMU_DMU_RST_ENABLE_ENA_SPL_FREQ_EVENT_BITS                 1
#define DMU_DMU_RST_ENABLE_ENA_SPL_FREQ_EVENT_SHIFT                7

/* DMU :: dmu_rst_enable :: reserved1 [06:05] */
#define DMU_DMU_RST_ENABLE_RESERVED1_MASK                          0x00000060
#define DMU_DMU_RST_ENABLE_RESERVED1_ALIGN                         0
#define DMU_DMU_RST_ENABLE_RESERVED1_BITS                          2
#define DMU_DMU_RST_ENABLE_RESERVED1_SHIFT                         5

/* DMU :: dmu_rst_enable :: ena_tamper [04:04] */
#define Wr_DMU_dmu_rst_enable_ena_tamper(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x10,4,x)
#define Rd_DMU_dmu_rst_enable_ena_tamper(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x10,4)
#define DMU_DMU_RST_ENABLE_ENA_TAMPER_MASK                         0x00000010
#define DMU_DMU_RST_ENABLE_ENA_TAMPER_ALIGN                        0
#define DMU_DMU_RST_ENABLE_ENA_TAMPER_BITS                         1
#define DMU_DMU_RST_ENABLE_ENA_TAMPER_SHIFT                        4

/* DMU :: dmu_rst_enable :: ena_pwd_err [03:03] */
#define Wr_DMU_dmu_rst_enable_ena_pwd_err(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x8,3,x)
#define Rd_DMU_dmu_rst_enable_ena_pwd_err(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x8,3)
#define DMU_DMU_RST_ENABLE_ENA_PWD_ERR_MASK                        0x00000008
#define DMU_DMU_RST_ENABLE_ENA_PWD_ERR_ALIGN                       0
#define DMU_DMU_RST_ENABLE_ENA_PWD_ERR_BITS                        1
#define DMU_DMU_RST_ENABLE_ENA_PWD_ERR_SHIFT                       3

/* DMU :: dmu_rst_enable :: ena_acc_err [02:02] */
#define Wr_DMU_dmu_rst_enable_ena_acc_err(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x4,2,x)
#define Rd_DMU_dmu_rst_enable_ena_acc_err(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x4,2)
#define DMU_DMU_RST_ENABLE_ENA_ACC_ERR_MASK                        0x00000004
#define DMU_DMU_RST_ENABLE_ENA_ACC_ERR_ALIGN                       0
#define DMU_DMU_RST_ENABLE_ENA_ACC_ERR_BITS                        1
#define DMU_DMU_RST_ENABLE_ENA_ACC_ERR_SHIFT                       2

/* DMU :: dmu_rst_enable :: ena_deepsleep_exit [01:01] */
#define Wr_DMU_dmu_rst_enable_ena_deepsleep_exit(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x2,1,x)
#define Rd_DMU_dmu_rst_enable_ena_deepsleep_exit(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x2,1)
#define DMU_DMU_RST_ENABLE_ENA_DEEPSLEEP_EXIT_MASK                 0x00000002
#define DMU_DMU_RST_ENABLE_ENA_DEEPSLEEP_EXIT_ALIGN                0
#define DMU_DMU_RST_ENABLE_ENA_DEEPSLEEP_EXIT_BITS                 1
#define DMU_DMU_RST_ENABLE_ENA_DEEPSLEEP_EXIT_SHIFT                1

/* DMU :: dmu_rst_enable :: ena_dmu_swrst [00:00] */
#define Wr_DMU_dmu_rst_enable_ena_dmu_swrst(x) WriteRegBits(DMU_DMU_RST_ENABLE,0x1,0,x)
#define Rd_DMU_dmu_rst_enable_ena_dmu_swrst(x) ReadRegBits(DMU_DMU_RST_ENABLE,0x1,0)
#define DMU_DMU_RST_ENABLE_ENA_DMU_SWRST_MASK                      0x00000001
#define DMU_DMU_RST_ENABLE_ENA_DMU_SWRST_ALIGN                     0
#define DMU_DMU_RST_ENABLE_ENA_DMU_SWRST_BITS                      1
#define DMU_DMU_RST_ENABLE_ENA_DMU_SWRST_SHIFT                     0


/****************************************************************************
 * DMU :: dmu_int_enable
 ***************************************************************************/
/* DMU :: dmu_int_enable :: int_ram_uncorrectable [31:31] */
#define Wr_DMU_dmu_int_enable_int_ram_uncorrectable(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x80000000,31,x)
#define Rd_DMU_dmu_int_enable_int_ram_uncorrectable(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x80000000,31)
#define DMU_DMU_INT_ENABLE_INT_RAM_UNCORRECTABLE_MASK              0x80000000
#define DMU_DMU_INT_ENABLE_INT_RAM_UNCORRECTABLE_ALIGN             0
#define DMU_DMU_INT_ENABLE_INT_RAM_UNCORRECTABLE_BITS              1
#define DMU_DMU_INT_ENABLE_INT_RAM_UNCORRECTABLE_SHIFT             31

/* DMU :: dmu_int_enable :: int_rng_interrupt [30:30] */
#define Wr_DMU_dmu_int_enable_int_rng_interrupt(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x40000000,30,x)
#define Rd_DMU_dmu_int_enable_int_rng_interrupt(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x40000000,30)
#define DMU_DMU_INT_ENABLE_INT_RNG_INTERRUPT_MASK                  0x40000000
#define DMU_DMU_INT_ENABLE_INT_RNG_INTERRUPT_ALIGN                 0
#define DMU_DMU_INT_ENABLE_INT_RNG_INTERRUPT_BITS                  1
#define DMU_DMU_INT_ENABLE_INT_RNG_INTERRUPT_SHIFT                 30

/* DMU :: dmu_int_enable :: reserved0 [29:29] */
#define DMU_DMU_INT_ENABLE_RESERVED0_MASK                          0x20000000
#define DMU_DMU_INT_ENABLE_RESERVED0_ALIGN                         0
#define DMU_DMU_INT_ENABLE_RESERVED0_BITS                          1
#define DMU_DMU_INT_ENABLE_RESERVED0_SHIFT                         29

/* DMU :: dmu_int_enable :: int_ram_correctable [28:28] */
#define Wr_DMU_dmu_int_enable_int_ram_correctable(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x10000000,28,x)
#define Rd_DMU_dmu_int_enable_int_ram_correctable(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x10000000,28)
#define DMU_DMU_INT_ENABLE_INT_RAM_CORRECTABLE_MASK                0x10000000
#define DMU_DMU_INT_ENABLE_INT_RAM_CORRECTABLE_ALIGN               0
#define DMU_DMU_INT_ENABLE_INT_RAM_CORRECTABLE_BITS                1
#define DMU_DMU_INT_ENABLE_INT_RAM_CORRECTABLE_SHIFT               28

/* DMU :: dmu_int_enable :: int_smu_par_err [27:27] */
#define Wr_DMU_dmu_int_enable_int_smu_par_err(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x8000000,27,x)
#define Rd_DMU_dmu_int_enable_int_smu_par_err(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x8000000,27)
#define DMU_DMU_INT_ENABLE_INT_SMU_PAR_ERR_MASK                    0x08000000
#define DMU_DMU_INT_ENABLE_INT_SMU_PAR_ERR_ALIGN                   0
#define DMU_DMU_INT_ENABLE_INT_SMU_PAR_ERR_BITS                    1
#define DMU_DMU_INT_ENABLE_INT_SMU_PAR_ERR_SHIFT                   27

/* DMU :: dmu_int_enable :: int_smu_auth_err [26:26] */
#define Wr_DMU_dmu_int_enable_int_smu_auth_err(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x4000000,26,x)
#define Rd_DMU_dmu_int_enable_int_smu_auth_err(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x4000000,26)
#define DMU_DMU_INT_ENABLE_INT_SMU_AUTH_ERR_MASK                   0x04000000
#define DMU_DMU_INT_ENABLE_INT_SMU_AUTH_ERR_ALIGN                  0
#define DMU_DMU_INT_ENABLE_INT_SMU_AUTH_ERR_BITS                   1
#define DMU_DMU_INT_ENABLE_INT_SMU_AUTH_ERR_SHIFT                  26

/* DMU :: dmu_int_enable :: int_mem_uncorrectable [25:25] */
#define Wr_DMU_dmu_int_enable_int_mem_uncorrectable(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x2000000,25,x)
#define Rd_DMU_dmu_int_enable_int_mem_uncorrectable(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x2000000,25)
#define DMU_DMU_INT_ENABLE_INT_MEM_UNCORRECTABLE_MASK              0x02000000
#define DMU_DMU_INT_ENABLE_INT_MEM_UNCORRECTABLE_ALIGN             0
#define DMU_DMU_INT_ENABLE_INT_MEM_UNCORRECTABLE_BITS              1
#define DMU_DMU_INT_ENABLE_INT_MEM_UNCORRECTABLE_SHIFT             25

/* DMU :: dmu_int_enable :: int_mem_correctable [24:24] */
#define Wr_DMU_dmu_int_enable_int_mem_correctable(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x1000000,24,x)
#define Rd_DMU_dmu_int_enable_int_mem_correctable(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x1000000,24)
#define DMU_DMU_INT_ENABLE_INT_MEM_CORRECTABLE_MASK                0x01000000
#define DMU_DMU_INT_ENABLE_INT_MEM_CORRECTABLE_ALIGN               0
#define DMU_DMU_INT_ENABLE_INT_MEM_CORRECTABLE_BITS                1
#define DMU_DMU_INT_ENABLE_INT_MEM_CORRECTABLE_SHIFT               24

/* DMU :: dmu_int_enable :: reserved1 [23:21] */
#define DMU_DMU_INT_ENABLE_RESERVED1_MASK                          0x00e00000
#define DMU_DMU_INT_ENABLE_RESERVED1_ALIGN                         0
#define DMU_DMU_INT_ENABLE_RESERVED1_BITS                          3
#define DMU_DMU_INT_ENABLE_RESERVED1_SHIFT                         21

/* DMU :: dmu_int_enable :: int_pmb_sbma_update_fail [20:20] */
#define Wr_DMU_dmu_int_enable_int_pmb_sbma_update_fail(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x100000,20,x)
#define Rd_DMU_dmu_int_enable_int_pmb_sbma_update_fail(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x100000,20)
#define DMU_DMU_INT_ENABLE_INT_PMB_SBMA_UPDATE_FAIL_MASK           0x00100000
#define DMU_DMU_INT_ENABLE_INT_PMB_SBMA_UPDATE_FAIL_ALIGN          0
#define DMU_DMU_INT_ENABLE_INT_PMB_SBMA_UPDATE_FAIL_BITS           1
#define DMU_DMU_INT_ENABLE_INT_PMB_SBMA_UPDATE_FAIL_SHIFT          20

/* DMU :: dmu_int_enable :: int_pmb_entry_mon_fail [19:19] */
#define Wr_DMU_dmu_int_enable_int_pmb_entry_mon_fail(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x80000,19,x)
#define Rd_DMU_dmu_int_enable_int_pmb_entry_mon_fail(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x80000,19)
#define DMU_DMU_INT_ENABLE_INT_PMB_ENTRY_MON_FAIL_MASK             0x00080000
#define DMU_DMU_INT_ENABLE_INT_PMB_ENTRY_MON_FAIL_ALIGN            0
#define DMU_DMU_INT_ENABLE_INT_PMB_ENTRY_MON_FAIL_BITS             1
#define DMU_DMU_INT_ENABLE_INT_PMB_ENTRY_MON_FAIL_SHIFT            19

/* DMU :: dmu_int_enable :: int_pmb_exit_mon_fail [18:18] */
#define Wr_DMU_dmu_int_enable_int_pmb_exit_mon_fail(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x40000,18,x)
#define Rd_DMU_dmu_int_enable_int_pmb_exit_mon_fail(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x40000,18)
#define DMU_DMU_INT_ENABLE_INT_PMB_EXIT_MON_FAIL_MASK              0x00040000
#define DMU_DMU_INT_ENABLE_INT_PMB_EXIT_MON_FAIL_ALIGN             0
#define DMU_DMU_INT_ENABLE_INT_PMB_EXIT_MON_FAIL_BITS              1
#define DMU_DMU_INT_ENABLE_INT_PMB_EXIT_MON_FAIL_SHIFT             18

/* DMU :: dmu_int_enable :: int_pmb_coproc_mon_fail [17:17] */
#define Wr_DMU_dmu_int_enable_int_pmb_coproc_mon_fail(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x20000,17,x)
#define Rd_DMU_dmu_int_enable_int_pmb_coproc_mon_fail(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x20000,17)
#define DMU_DMU_INT_ENABLE_INT_PMB_COPROC_MON_FAIL_MASK            0x00020000
#define DMU_DMU_INT_ENABLE_INT_PMB_COPROC_MON_FAIL_ALIGN           0
#define DMU_DMU_INT_ENABLE_INT_PMB_COPROC_MON_FAIL_BITS            1
#define DMU_DMU_INT_ENABLE_INT_PMB_COPROC_MON_FAIL_SHIFT           17

/* DMU :: dmu_int_enable :: int_pmb_par_err [16:16] */
#define Wr_DMU_dmu_int_enable_int_pmb_par_err(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x10000,16,x)
#define Rd_DMU_dmu_int_enable_int_pmb_par_err(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x10000,16)
#define DMU_DMU_INT_ENABLE_INT_PMB_PAR_ERR_MASK                    0x00010000
#define DMU_DMU_INT_ENABLE_INT_PMB_PAR_ERR_ALIGN                   0
#define DMU_DMU_INT_ENABLE_INT_PMB_PAR_ERR_BITS                    1
#define DMU_DMU_INT_ENABLE_INT_PMB_PAR_ERR_SHIFT                   16

/* DMU :: dmu_int_enable :: int_arm_par_err [15:15] */
#define Wr_DMU_dmu_int_enable_int_arm_par_err(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x8000,15,x)
#define Rd_DMU_dmu_int_enable_int_arm_par_err(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x8000,15)
#define DMU_DMU_INT_ENABLE_INT_ARM_PAR_ERR_MASK                    0x00008000
#define DMU_DMU_INT_ENABLE_INT_ARM_PAR_ERR_ALIGN                   0
#define DMU_DMU_INT_ENABLE_INT_ARM_PAR_ERR_BITS                    1
#define DMU_DMU_INT_ENABLE_INT_ARM_PAR_ERR_SHIFT                   15

/* DMU :: dmu_int_enable :: int_bbl_par_err [14:14] */
#define Wr_DMU_dmu_int_enable_int_bbl_par_err(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x4000,14,x)
#define Rd_DMU_dmu_int_enable_int_bbl_par_err(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x4000,14)
#define DMU_DMU_INT_ENABLE_INT_BBL_PAR_ERR_MASK                    0x00004000
#define DMU_DMU_INT_ENABLE_INT_BBL_PAR_ERR_ALIGN                   0
#define DMU_DMU_INT_ENABLE_INT_BBL_PAR_ERR_BITS                    1
#define DMU_DMU_INT_ENABLE_INT_BBL_PAR_ERR_SHIFT                   14

/* DMU :: dmu_int_enable :: int_usb_par_err [13:13] */
#define Wr_DMU_dmu_int_enable_int_usb_par_err(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x2000,13,x)
#define Rd_DMU_dmu_int_enable_int_usb_par_err(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x2000,13)
#define DMU_DMU_INT_ENABLE_INT_USB_PAR_ERR_MASK                    0x00002000
#define DMU_DMU_INT_ENABLE_INT_USB_PAR_ERR_ALIGN                   0
#define DMU_DMU_INT_ENABLE_INT_USB_PAR_ERR_BITS                    1
#define DMU_DMU_INT_ENABLE_INT_USB_PAR_ERR_SHIFT                   13

/* DMU :: dmu_int_enable :: int_sbma_mismatch [12:12] */
#define Wr_DMU_dmu_int_enable_int_sbma_mismatch(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x1000,12,x)
#define Rd_DMU_dmu_int_enable_int_sbma_mismatch(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x1000,12)
#define DMU_DMU_INT_ENABLE_INT_SBMA_MISMATCH_MASK                  0x00001000
#define DMU_DMU_INT_ENABLE_INT_SBMA_MISMATCH_ALIGN                 0
#define DMU_DMU_INT_ENABLE_INT_SBMA_MISMATCH_BITS                  1
#define DMU_DMU_INT_ENABLE_INT_SBMA_MISMATCH_SHIFT                 12

/* DMU :: dmu_int_enable :: int_open_wdog [11:11] */
#define Wr_DMU_dmu_int_enable_int_open_wdog(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x800,11,x)
#define Rd_DMU_dmu_int_enable_int_open_wdog(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x800,11)
#define DMU_DMU_INT_ENABLE_INT_OPEN_WDOG_MASK                      0x00000800
#define DMU_DMU_INT_ENABLE_INT_OPEN_WDOG_ALIGN                     0
#define DMU_DMU_INT_ENABLE_INT_OPEN_WDOG_BITS                      1
#define DMU_DMU_INT_ENABLE_INT_OPEN_WDOG_SHIFT                     11

/* DMU :: dmu_int_enable :: int_spl_pvt_event [10:10] */
#define Wr_DMU_dmu_int_enable_int_spl_pvt_event(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x400,10,x)
#define Rd_DMU_dmu_int_enable_int_spl_pvt_event(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x400,10)
#define DMU_DMU_INT_ENABLE_INT_SPL_PVT_EVENT_MASK                  0x00000400
#define DMU_DMU_INT_ENABLE_INT_SPL_PVT_EVENT_ALIGN                 0
#define DMU_DMU_INT_ENABLE_INT_SPL_PVT_EVENT_BITS                  1
#define DMU_DMU_INT_ENABLE_INT_SPL_PVT_EVENT_SHIFT                 10

/* DMU :: dmu_int_enable :: int_spl_rst_event [09:09] */
#define Wr_DMU_dmu_int_enable_int_spl_rst_event(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x200,9,x)
#define Rd_DMU_dmu_int_enable_int_spl_rst_event(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x200,9)
#define DMU_DMU_INT_ENABLE_INT_SPL_RST_EVENT_MASK                  0x00000200
#define DMU_DMU_INT_ENABLE_INT_SPL_RST_EVENT_ALIGN                 0
#define DMU_DMU_INT_ENABLE_INT_SPL_RST_EVENT_BITS                  1
#define DMU_DMU_INT_ENABLE_INT_SPL_RST_EVENT_SHIFT                 9

/* DMU :: dmu_int_enable :: int_spl_wdog_event [08:08] */
#define Wr_DMU_dmu_int_enable_int_spl_wdog_event(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x100,8,x)
#define Rd_DMU_dmu_int_enable_int_spl_wdog_event(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x100,8)
#define DMU_DMU_INT_ENABLE_INT_SPL_WDOG_EVENT_MASK                 0x00000100
#define DMU_DMU_INT_ENABLE_INT_SPL_WDOG_EVENT_ALIGN                0
#define DMU_DMU_INT_ENABLE_INT_SPL_WDOG_EVENT_BITS                 1
#define DMU_DMU_INT_ENABLE_INT_SPL_WDOG_EVENT_SHIFT                8

/* DMU :: dmu_int_enable :: int_spl_freq_event [07:07] */
#define Wr_DMU_dmu_int_enable_int_spl_freq_event(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x80,7,x)
#define Rd_DMU_dmu_int_enable_int_spl_freq_event(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x80,7)
#define DMU_DMU_INT_ENABLE_INT_SPL_FREQ_EVENT_MASK                 0x00000080
#define DMU_DMU_INT_ENABLE_INT_SPL_FREQ_EVENT_ALIGN                0
#define DMU_DMU_INT_ENABLE_INT_SPL_FREQ_EVENT_BITS                 1
#define DMU_DMU_INT_ENABLE_INT_SPL_FREQ_EVENT_SHIFT                7

/* DMU :: dmu_int_enable :: reserved2 [06:05] */
#define DMU_DMU_INT_ENABLE_RESERVED2_MASK                          0x00000060
#define DMU_DMU_INT_ENABLE_RESERVED2_ALIGN                         0
#define DMU_DMU_INT_ENABLE_RESERVED2_BITS                          2
#define DMU_DMU_INT_ENABLE_RESERVED2_SHIFT                         5

/* DMU :: dmu_int_enable :: int_tamper [04:04] */
#define Wr_DMU_dmu_int_enable_int_tamper(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x10,4,x)
#define Rd_DMU_dmu_int_enable_int_tamper(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x10,4)
#define DMU_DMU_INT_ENABLE_INT_TAMPER_MASK                         0x00000010
#define DMU_DMU_INT_ENABLE_INT_TAMPER_ALIGN                        0
#define DMU_DMU_INT_ENABLE_INT_TAMPER_BITS                         1
#define DMU_DMU_INT_ENABLE_INT_TAMPER_SHIFT                        4

/* DMU :: dmu_int_enable :: int_pwd_err [03:03] */
#define Wr_DMU_dmu_int_enable_int_pwd_err(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x8,3,x)
#define Rd_DMU_dmu_int_enable_int_pwd_err(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x8,3)
#define DMU_DMU_INT_ENABLE_INT_PWD_ERR_MASK                        0x00000008
#define DMU_DMU_INT_ENABLE_INT_PWD_ERR_ALIGN                       0
#define DMU_DMU_INT_ENABLE_INT_PWD_ERR_BITS                        1
#define DMU_DMU_INT_ENABLE_INT_PWD_ERR_SHIFT                       3

/* DMU :: dmu_int_enable :: int_acc_err [02:02] */
#define Wr_DMU_dmu_int_enable_int_acc_err(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x4,2,x)
#define Rd_DMU_dmu_int_enable_int_acc_err(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x4,2)
#define DMU_DMU_INT_ENABLE_INT_ACC_ERR_MASK                        0x00000004
#define DMU_DMU_INT_ENABLE_INT_ACC_ERR_ALIGN                       0
#define DMU_DMU_INT_ENABLE_INT_ACC_ERR_BITS                        1
#define DMU_DMU_INT_ENABLE_INT_ACC_ERR_SHIFT                       2

/* DMU :: dmu_int_enable :: int_deepsleep_exit [01:01] */
#define Wr_DMU_dmu_int_enable_int_deepsleep_exit(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x2,1,x)
#define Rd_DMU_dmu_int_enable_int_deepsleep_exit(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x2,1)
#define DMU_DMU_INT_ENABLE_INT_DEEPSLEEP_EXIT_MASK                 0x00000002
#define DMU_DMU_INT_ENABLE_INT_DEEPSLEEP_EXIT_ALIGN                0
#define DMU_DMU_INT_ENABLE_INT_DEEPSLEEP_EXIT_BITS                 1
#define DMU_DMU_INT_ENABLE_INT_DEEPSLEEP_EXIT_SHIFT                1

/* DMU :: dmu_int_enable :: int_dmu_swrst [00:00] */
#define Wr_DMU_dmu_int_enable_int_dmu_swrst(x) WriteRegBits(DMU_DMU_INT_ENABLE,0x1,0,x)
#define Rd_DMU_dmu_int_enable_int_dmu_swrst(x) ReadRegBits(DMU_DMU_INT_ENABLE,0x1,0)
#define DMU_DMU_INT_ENABLE_INT_DMU_SWRST_MASK                      0x00000001
#define DMU_DMU_INT_ENABLE_INT_DMU_SWRST_ALIGN                     0
#define DMU_DMU_INT_ENABLE_INT_DMU_SWRST_BITS                      1
#define DMU_DMU_INT_ENABLE_INT_DMU_SWRST_SHIFT                     0


/****************************************************************************
 * DMU :: dmu_rst_test
 ***************************************************************************/
/* DMU :: dmu_rst_test :: test_ram_uncorrectable [31:31] */
#define Wr_DMU_dmu_rst_test_test_ram_uncorrectable(x) WriteRegBits(DMU_DMU_RST_TEST,0x80000000,31,x)
#define Rd_DMU_dmu_rst_test_test_ram_uncorrectable(x) ReadRegBits(DMU_DMU_RST_TEST,0x80000000,31)
#define DMU_DMU_RST_TEST_TEST_RAM_UNCORRECTABLE_MASK               0x80000000
#define DMU_DMU_RST_TEST_TEST_RAM_UNCORRECTABLE_ALIGN              0
#define DMU_DMU_RST_TEST_TEST_RAM_UNCORRECTABLE_BITS               1
#define DMU_DMU_RST_TEST_TEST_RAM_UNCORRECTABLE_SHIFT              31

/* DMU :: dmu_rst_test :: test_rng_interrupt [30:30] */
#define Wr_DMU_dmu_rst_test_test_rng_interrupt(x) WriteRegBits(DMU_DMU_RST_TEST,0x40000000,30,x)
#define Rd_DMU_dmu_rst_test_test_rng_interrupt(x) ReadRegBits(DMU_DMU_RST_TEST,0x40000000,30)
#define DMU_DMU_RST_TEST_TEST_RNG_INTERRUPT_MASK                   0x40000000
#define DMU_DMU_RST_TEST_TEST_RNG_INTERRUPT_ALIGN                  0
#define DMU_DMU_RST_TEST_TEST_RNG_INTERRUPT_BITS                   1
#define DMU_DMU_RST_TEST_TEST_RNG_INTERRUPT_SHIFT                  30

/* DMU :: dmu_rst_test :: test_tamper_l1 [29:29] */
#define Wr_DMU_dmu_rst_test_test_tamper_l1(x) WriteRegBits(DMU_DMU_RST_TEST,0x20000000,29,x)
#define Rd_DMU_dmu_rst_test_test_tamper_l1(x) ReadRegBits(DMU_DMU_RST_TEST,0x20000000,29)
#define DMU_DMU_RST_TEST_TEST_TAMPER_L1_MASK                       0x20000000
#define DMU_DMU_RST_TEST_TEST_TAMPER_L1_ALIGN                      0
#define DMU_DMU_RST_TEST_TEST_TAMPER_L1_BITS                       1
#define DMU_DMU_RST_TEST_TEST_TAMPER_L1_SHIFT                      29

/* DMU :: dmu_rst_test :: test_ram_correctable [28:28] */
#define Wr_DMU_dmu_rst_test_test_ram_correctable(x) WriteRegBits(DMU_DMU_RST_TEST,0x10000000,28,x)
#define Rd_DMU_dmu_rst_test_test_ram_correctable(x) ReadRegBits(DMU_DMU_RST_TEST,0x10000000,28)
#define DMU_DMU_RST_TEST_TEST_RAM_CORRECTABLE_MASK                 0x10000000
#define DMU_DMU_RST_TEST_TEST_RAM_CORRECTABLE_ALIGN                0
#define DMU_DMU_RST_TEST_TEST_RAM_CORRECTABLE_BITS                 1
#define DMU_DMU_RST_TEST_TEST_RAM_CORRECTABLE_SHIFT                28

/* DMU :: dmu_rst_test :: test_smu_par_err [27:27] */
#define Wr_DMU_dmu_rst_test_test_smu_par_err(x) WriteRegBits(DMU_DMU_RST_TEST,0x8000000,27,x)
#define Rd_DMU_dmu_rst_test_test_smu_par_err(x) ReadRegBits(DMU_DMU_RST_TEST,0x8000000,27)
#define DMU_DMU_RST_TEST_TEST_SMU_PAR_ERR_MASK                     0x08000000
#define DMU_DMU_RST_TEST_TEST_SMU_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_TEST_TEST_SMU_PAR_ERR_BITS                     1
#define DMU_DMU_RST_TEST_TEST_SMU_PAR_ERR_SHIFT                    27

/* DMU :: dmu_rst_test :: test_smu_auth_err [26:26] */
#define Wr_DMU_dmu_rst_test_test_smu_auth_err(x) WriteRegBits(DMU_DMU_RST_TEST,0x4000000,26,x)
#define Rd_DMU_dmu_rst_test_test_smu_auth_err(x) ReadRegBits(DMU_DMU_RST_TEST,0x4000000,26)
#define DMU_DMU_RST_TEST_TEST_SMU_AUTH_ERR_MASK                    0x04000000
#define DMU_DMU_RST_TEST_TEST_SMU_AUTH_ERR_ALIGN                   0
#define DMU_DMU_RST_TEST_TEST_SMU_AUTH_ERR_BITS                    1
#define DMU_DMU_RST_TEST_TEST_SMU_AUTH_ERR_SHIFT                   26

/* DMU :: dmu_rst_test :: test_mem_uncorrectable [25:25] */
#define Wr_DMU_dmu_rst_test_test_mem_uncorrectable(x) WriteRegBits(DMU_DMU_RST_TEST,0x2000000,25,x)
#define Rd_DMU_dmu_rst_test_test_mem_uncorrectable(x) ReadRegBits(DMU_DMU_RST_TEST,0x2000000,25)
#define DMU_DMU_RST_TEST_TEST_MEM_UNCORRECTABLE_MASK               0x02000000
#define DMU_DMU_RST_TEST_TEST_MEM_UNCORRECTABLE_ALIGN              0
#define DMU_DMU_RST_TEST_TEST_MEM_UNCORRECTABLE_BITS               1
#define DMU_DMU_RST_TEST_TEST_MEM_UNCORRECTABLE_SHIFT              25

/* DMU :: dmu_rst_test :: test_mem_correctable [24:24] */
#define Wr_DMU_dmu_rst_test_test_mem_correctable(x) WriteRegBits(DMU_DMU_RST_TEST,0x1000000,24,x)
#define Rd_DMU_dmu_rst_test_test_mem_correctable(x) ReadRegBits(DMU_DMU_RST_TEST,0x1000000,24)
#define DMU_DMU_RST_TEST_TEST_MEM_CORRECTABLE_MASK                 0x01000000
#define DMU_DMU_RST_TEST_TEST_MEM_CORRECTABLE_ALIGN                0
#define DMU_DMU_RST_TEST_TEST_MEM_CORRECTABLE_BITS                 1
#define DMU_DMU_RST_TEST_TEST_MEM_CORRECTABLE_SHIFT                24

/* DMU :: dmu_rst_test :: reserved0 [23:21] */
#define DMU_DMU_RST_TEST_RESERVED0_MASK                            0x00e00000
#define DMU_DMU_RST_TEST_RESERVED0_ALIGN                           0
#define DMU_DMU_RST_TEST_RESERVED0_BITS                            3
#define DMU_DMU_RST_TEST_RESERVED0_SHIFT                           21

/* DMU :: dmu_rst_test :: test_pmb_sbma_update_fail [20:20] */
#define Wr_DMU_dmu_rst_test_test_pmb_sbma_update_fail(x) WriteRegBits(DMU_DMU_RST_TEST,0x100000,20,x)
#define Rd_DMU_dmu_rst_test_test_pmb_sbma_update_fail(x) ReadRegBits(DMU_DMU_RST_TEST,0x100000,20)
#define DMU_DMU_RST_TEST_TEST_PMB_SBMA_UPDATE_FAIL_MASK            0x00100000
#define DMU_DMU_RST_TEST_TEST_PMB_SBMA_UPDATE_FAIL_ALIGN           0
#define DMU_DMU_RST_TEST_TEST_PMB_SBMA_UPDATE_FAIL_BITS            1
#define DMU_DMU_RST_TEST_TEST_PMB_SBMA_UPDATE_FAIL_SHIFT           20

/* DMU :: dmu_rst_test :: test_pmb_entry_mon_fail [19:19] */
#define Wr_DMU_dmu_rst_test_test_pmb_entry_mon_fail(x) WriteRegBits(DMU_DMU_RST_TEST,0x80000,19,x)
#define Rd_DMU_dmu_rst_test_test_pmb_entry_mon_fail(x) ReadRegBits(DMU_DMU_RST_TEST,0x80000,19)
#define DMU_DMU_RST_TEST_TEST_PMB_ENTRY_MON_FAIL_MASK              0x00080000
#define DMU_DMU_RST_TEST_TEST_PMB_ENTRY_MON_FAIL_ALIGN             0
#define DMU_DMU_RST_TEST_TEST_PMB_ENTRY_MON_FAIL_BITS              1
#define DMU_DMU_RST_TEST_TEST_PMB_ENTRY_MON_FAIL_SHIFT             19

/* DMU :: dmu_rst_test :: test_pmb_exit_mon_fail [18:18] */
#define Wr_DMU_dmu_rst_test_test_pmb_exit_mon_fail(x) WriteRegBits(DMU_DMU_RST_TEST,0x40000,18,x)
#define Rd_DMU_dmu_rst_test_test_pmb_exit_mon_fail(x) ReadRegBits(DMU_DMU_RST_TEST,0x40000,18)
#define DMU_DMU_RST_TEST_TEST_PMB_EXIT_MON_FAIL_MASK               0x00040000
#define DMU_DMU_RST_TEST_TEST_PMB_EXIT_MON_FAIL_ALIGN              0
#define DMU_DMU_RST_TEST_TEST_PMB_EXIT_MON_FAIL_BITS               1
#define DMU_DMU_RST_TEST_TEST_PMB_EXIT_MON_FAIL_SHIFT              18

/* DMU :: dmu_rst_test :: test_pmb_coproc_mon_fail [17:17] */
#define Wr_DMU_dmu_rst_test_test_pmb_coproc_mon_fail(x) WriteRegBits(DMU_DMU_RST_TEST,0x20000,17,x)
#define Rd_DMU_dmu_rst_test_test_pmb_coproc_mon_fail(x) ReadRegBits(DMU_DMU_RST_TEST,0x20000,17)
#define DMU_DMU_RST_TEST_TEST_PMB_COPROC_MON_FAIL_MASK             0x00020000
#define DMU_DMU_RST_TEST_TEST_PMB_COPROC_MON_FAIL_ALIGN            0
#define DMU_DMU_RST_TEST_TEST_PMB_COPROC_MON_FAIL_BITS             1
#define DMU_DMU_RST_TEST_TEST_PMB_COPROC_MON_FAIL_SHIFT            17

/* DMU :: dmu_rst_test :: test_pmb_par_err [16:16] */
#define Wr_DMU_dmu_rst_test_test_pmb_par_err(x) WriteRegBits(DMU_DMU_RST_TEST,0x10000,16,x)
#define Rd_DMU_dmu_rst_test_test_pmb_par_err(x) ReadRegBits(DMU_DMU_RST_TEST,0x10000,16)
#define DMU_DMU_RST_TEST_TEST_PMB_PAR_ERR_MASK                     0x00010000
#define DMU_DMU_RST_TEST_TEST_PMB_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_TEST_TEST_PMB_PAR_ERR_BITS                     1
#define DMU_DMU_RST_TEST_TEST_PMB_PAR_ERR_SHIFT                    16

/* DMU :: dmu_rst_test :: test_arm_par_err [15:15] */
#define Wr_DMU_dmu_rst_test_test_arm_par_err(x) WriteRegBits(DMU_DMU_RST_TEST,0x8000,15,x)
#define Rd_DMU_dmu_rst_test_test_arm_par_err(x) ReadRegBits(DMU_DMU_RST_TEST,0x8000,15)
#define DMU_DMU_RST_TEST_TEST_ARM_PAR_ERR_MASK                     0x00008000
#define DMU_DMU_RST_TEST_TEST_ARM_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_TEST_TEST_ARM_PAR_ERR_BITS                     1
#define DMU_DMU_RST_TEST_TEST_ARM_PAR_ERR_SHIFT                    15

/* DMU :: dmu_rst_test :: test_bbl_par_err [14:14] */
#define Wr_DMU_dmu_rst_test_test_bbl_par_err(x) WriteRegBits(DMU_DMU_RST_TEST,0x4000,14,x)
#define Rd_DMU_dmu_rst_test_test_bbl_par_err(x) ReadRegBits(DMU_DMU_RST_TEST,0x4000,14)
#define DMU_DMU_RST_TEST_TEST_BBL_PAR_ERR_MASK                     0x00004000
#define DMU_DMU_RST_TEST_TEST_BBL_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_TEST_TEST_BBL_PAR_ERR_BITS                     1
#define DMU_DMU_RST_TEST_TEST_BBL_PAR_ERR_SHIFT                    14

/* DMU :: dmu_rst_test :: test_usb_par_err [13:13] */
#define Wr_DMU_dmu_rst_test_test_usb_par_err(x) WriteRegBits(DMU_DMU_RST_TEST,0x2000,13,x)
#define Rd_DMU_dmu_rst_test_test_usb_par_err(x) ReadRegBits(DMU_DMU_RST_TEST,0x2000,13)
#define DMU_DMU_RST_TEST_TEST_USB_PAR_ERR_MASK                     0x00002000
#define DMU_DMU_RST_TEST_TEST_USB_PAR_ERR_ALIGN                    0
#define DMU_DMU_RST_TEST_TEST_USB_PAR_ERR_BITS                     1
#define DMU_DMU_RST_TEST_TEST_USB_PAR_ERR_SHIFT                    13

/* DMU :: dmu_rst_test :: test_sbma_mismatch [12:12] */
#define Wr_DMU_dmu_rst_test_test_sbma_mismatch(x) WriteRegBits(DMU_DMU_RST_TEST,0x1000,12,x)
#define Rd_DMU_dmu_rst_test_test_sbma_mismatch(x) ReadRegBits(DMU_DMU_RST_TEST,0x1000,12)
#define DMU_DMU_RST_TEST_TEST_SBMA_MISMATCH_MASK                   0x00001000
#define DMU_DMU_RST_TEST_TEST_SBMA_MISMATCH_ALIGN                  0
#define DMU_DMU_RST_TEST_TEST_SBMA_MISMATCH_BITS                   1
#define DMU_DMU_RST_TEST_TEST_SBMA_MISMATCH_SHIFT                  12

/* DMU :: dmu_rst_test :: test_open_wdog [11:11] */
#define Wr_DMU_dmu_rst_test_test_open_wdog(x) WriteRegBits(DMU_DMU_RST_TEST,0x800,11,x)
#define Rd_DMU_dmu_rst_test_test_open_wdog(x) ReadRegBits(DMU_DMU_RST_TEST,0x800,11)
#define DMU_DMU_RST_TEST_TEST_OPEN_WDOG_MASK                       0x00000800
#define DMU_DMU_RST_TEST_TEST_OPEN_WDOG_ALIGN                      0
#define DMU_DMU_RST_TEST_TEST_OPEN_WDOG_BITS                       1
#define DMU_DMU_RST_TEST_TEST_OPEN_WDOG_SHIFT                      11

/* DMU :: dmu_rst_test :: test_spl_pvt_event [10:10] */
#define Wr_DMU_dmu_rst_test_test_spl_pvt_event(x) WriteRegBits(DMU_DMU_RST_TEST,0x400,10,x)
#define Rd_DMU_dmu_rst_test_test_spl_pvt_event(x) ReadRegBits(DMU_DMU_RST_TEST,0x400,10)
#define DMU_DMU_RST_TEST_TEST_SPL_PVT_EVENT_MASK                   0x00000400
#define DMU_DMU_RST_TEST_TEST_SPL_PVT_EVENT_ALIGN                  0
#define DMU_DMU_RST_TEST_TEST_SPL_PVT_EVENT_BITS                   1
#define DMU_DMU_RST_TEST_TEST_SPL_PVT_EVENT_SHIFT                  10

/* DMU :: dmu_rst_test :: test_spl_rst_event [09:09] */
#define Wr_DMU_dmu_rst_test_test_spl_rst_event(x) WriteRegBits(DMU_DMU_RST_TEST,0x200,9,x)
#define Rd_DMU_dmu_rst_test_test_spl_rst_event(x) ReadRegBits(DMU_DMU_RST_TEST,0x200,9)
#define DMU_DMU_RST_TEST_TEST_SPL_RST_EVENT_MASK                   0x00000200
#define DMU_DMU_RST_TEST_TEST_SPL_RST_EVENT_ALIGN                  0
#define DMU_DMU_RST_TEST_TEST_SPL_RST_EVENT_BITS                   1
#define DMU_DMU_RST_TEST_TEST_SPL_RST_EVENT_SHIFT                  9

/* DMU :: dmu_rst_test :: test_spl_wdog_event [08:08] */
#define Wr_DMU_dmu_rst_test_test_spl_wdog_event(x) WriteRegBits(DMU_DMU_RST_TEST,0x100,8,x)
#define Rd_DMU_dmu_rst_test_test_spl_wdog_event(x) ReadRegBits(DMU_DMU_RST_TEST,0x100,8)
#define DMU_DMU_RST_TEST_TEST_SPL_WDOG_EVENT_MASK                  0x00000100
#define DMU_DMU_RST_TEST_TEST_SPL_WDOG_EVENT_ALIGN                 0
#define DMU_DMU_RST_TEST_TEST_SPL_WDOG_EVENT_BITS                  1
#define DMU_DMU_RST_TEST_TEST_SPL_WDOG_EVENT_SHIFT                 8

/* DMU :: dmu_rst_test :: test_spl_freq_event [07:07] */
#define Wr_DMU_dmu_rst_test_test_spl_freq_event(x) WriteRegBits(DMU_DMU_RST_TEST,0x80,7,x)
#define Rd_DMU_dmu_rst_test_test_spl_freq_event(x) ReadRegBits(DMU_DMU_RST_TEST,0x80,7)
#define DMU_DMU_RST_TEST_TEST_SPL_FREQ_EVENT_MASK                  0x00000080
#define DMU_DMU_RST_TEST_TEST_SPL_FREQ_EVENT_ALIGN                 0
#define DMU_DMU_RST_TEST_TEST_SPL_FREQ_EVENT_BITS                  1
#define DMU_DMU_RST_TEST_TEST_SPL_FREQ_EVENT_SHIFT                 7

/* DMU :: dmu_rst_test :: reserved1 [06:05] */
#define DMU_DMU_RST_TEST_RESERVED1_MASK                            0x00000060
#define DMU_DMU_RST_TEST_RESERVED1_ALIGN                           0
#define DMU_DMU_RST_TEST_RESERVED1_BITS                            2
#define DMU_DMU_RST_TEST_RESERVED1_SHIFT                           5

/* DMU :: dmu_rst_test :: test_tamper [04:04] */
#define Wr_DMU_dmu_rst_test_test_tamper(x) WriteRegBits(DMU_DMU_RST_TEST,0x10,4,x)
#define Rd_DMU_dmu_rst_test_test_tamper(x) ReadRegBits(DMU_DMU_RST_TEST,0x10,4)
#define DMU_DMU_RST_TEST_TEST_TAMPER_MASK                          0x00000010
#define DMU_DMU_RST_TEST_TEST_TAMPER_ALIGN                         0
#define DMU_DMU_RST_TEST_TEST_TAMPER_BITS                          1
#define DMU_DMU_RST_TEST_TEST_TAMPER_SHIFT                         4

/* DMU :: dmu_rst_test :: test_pwd_err [03:03] */
#define Wr_DMU_dmu_rst_test_test_pwd_err(x) WriteRegBits(DMU_DMU_RST_TEST,0x8,3,x)
#define Rd_DMU_dmu_rst_test_test_pwd_err(x) ReadRegBits(DMU_DMU_RST_TEST,0x8,3)
#define DMU_DMU_RST_TEST_TEST_PWD_ERR_MASK                         0x00000008
#define DMU_DMU_RST_TEST_TEST_PWD_ERR_ALIGN                        0
#define DMU_DMU_RST_TEST_TEST_PWD_ERR_BITS                         1
#define DMU_DMU_RST_TEST_TEST_PWD_ERR_SHIFT                        3

/* DMU :: dmu_rst_test :: test_acc_err [02:02] */
#define Wr_DMU_dmu_rst_test_test_acc_err(x) WriteRegBits(DMU_DMU_RST_TEST,0x4,2,x)
#define Rd_DMU_dmu_rst_test_test_acc_err(x) ReadRegBits(DMU_DMU_RST_TEST,0x4,2)
#define DMU_DMU_RST_TEST_TEST_ACC_ERR_MASK                         0x00000004
#define DMU_DMU_RST_TEST_TEST_ACC_ERR_ALIGN                        0
#define DMU_DMU_RST_TEST_TEST_ACC_ERR_BITS                         1
#define DMU_DMU_RST_TEST_TEST_ACC_ERR_SHIFT                        2

/* DMU :: dmu_rst_test :: test_deepsleep_exit [01:01] */
#define Wr_DMU_dmu_rst_test_test_deepsleep_exit(x) WriteRegBits(DMU_DMU_RST_TEST,0x2,1,x)
#define Rd_DMU_dmu_rst_test_test_deepsleep_exit(x) ReadRegBits(DMU_DMU_RST_TEST,0x2,1)
#define DMU_DMU_RST_TEST_TEST_DEEPSLEEP_EXIT_MASK                  0x00000002
#define DMU_DMU_RST_TEST_TEST_DEEPSLEEP_EXIT_ALIGN                 0
#define DMU_DMU_RST_TEST_TEST_DEEPSLEEP_EXIT_BITS                  1
#define DMU_DMU_RST_TEST_TEST_DEEPSLEEP_EXIT_SHIFT                 1

/* DMU :: dmu_rst_test :: test_dmu_swrst [00:00] */
#define Wr_DMU_dmu_rst_test_test_dmu_swrst(x) WriteRegBits(DMU_DMU_RST_TEST,0x1,0,x)
#define Rd_DMU_dmu_rst_test_test_dmu_swrst(x) ReadRegBits(DMU_DMU_RST_TEST,0x1,0)
#define DMU_DMU_RST_TEST_TEST_DMU_SWRST_MASK                       0x00000001
#define DMU_DMU_RST_TEST_TEST_DMU_SWRST_ALIGN                      0
#define DMU_DMU_RST_TEST_TEST_DMU_SWRST_BITS                       1
#define DMU_DMU_RST_TEST_TEST_DMU_SWRST_SHIFT                      0


/****************************************************************************
 * DMU :: dmu_rst_blk1
 ***************************************************************************/
/* DMU :: dmu_rst_blk1 :: dmu_rst_sci0 [31:31] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_sci0(x) WriteRegBits(DMU_DMU_RST_BLK1,0x80000000,31,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_sci0(x) ReadRegBits(DMU_DMU_RST_BLK1,0x80000000,31)
#define DMU_DMU_RST_BLK1_DMU_RST_SCI0_MASK                         0x80000000
#define DMU_DMU_RST_BLK1_DMU_RST_SCI0_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_SCI0_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_SCI0_SHIFT                        31

/* DMU :: dmu_rst_blk1 :: dmu_rst_rom [30:30] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_rom(x) WriteRegBits(DMU_DMU_RST_BLK1,0x40000000,30,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_rom(x) ReadRegBits(DMU_DMU_RST_BLK1,0x40000000,30)
#define DMU_DMU_RST_BLK1_DMU_RST_ROM_MASK                          0x40000000
#define DMU_DMU_RST_BLK1_DMU_RST_ROM_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_ROM_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_ROM_SHIFT                         30

/* DMU :: dmu_rst_blk1 :: dmu_rst_rng [29:29] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_rng(x) WriteRegBits(DMU_DMU_RST_BLK1,0x20000000,29,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_rng(x) ReadRegBits(DMU_DMU_RST_BLK1,0x20000000,29)
#define DMU_DMU_RST_BLK1_DMU_RST_RNG_MASK                          0x20000000
#define DMU_DMU_RST_BLK1_DMU_RST_RNG_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_RNG_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_RNG_SHIFT                         29

/* DMU :: dmu_rst_blk1 :: dmu_rst_pwm [28:28] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_pwm(x) WriteRegBits(DMU_DMU_RST_BLK1,0x10000000,28,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_pwm(x) ReadRegBits(DMU_DMU_RST_BLK1,0x10000000,28)
#define DMU_DMU_RST_BLK1_DMU_RST_PWM_MASK                          0x10000000
#define DMU_DMU_RST_BLK1_DMU_RST_PWM_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_PWM_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_PWM_SHIFT                         28

/* DMU :: dmu_rst_blk1 :: dmu_rst_pka [27:27] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_pka(x) WriteRegBits(DMU_DMU_RST_BLK1,0x8000000,27,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_pka(x) ReadRegBits(DMU_DMU_RST_BLK1,0x8000000,27)
#define DMU_DMU_RST_BLK1_DMU_RST_PKA_MASK                          0x08000000
#define DMU_DMU_RST_BLK1_DMU_RST_PKA_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_PKA_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_PKA_SHIFT                         27

/* DMU :: dmu_rst_blk1 :: dmu_rst_pbz [26:26] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_pbz(x) WriteRegBits(DMU_DMU_RST_BLK1,0x4000000,26,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_pbz(x) ReadRegBits(DMU_DMU_RST_BLK1,0x4000000,26)
#define DMU_DMU_RST_BLK1_DMU_RST_PBZ_MASK                          0x04000000
#define DMU_DMU_RST_BLK1_DMU_RST_PBZ_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_PBZ_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_PBZ_SHIFT                         26

/* DMU :: dmu_rst_blk1 :: dmu_rst_pby [25:25] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_pby(x) WriteRegBits(DMU_DMU_RST_BLK1,0x2000000,25,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_pby(x) ReadRegBits(DMU_DMU_RST_BLK1,0x2000000,25)
#define DMU_DMU_RST_BLK1_DMU_RST_PBY_MASK                          0x02000000
#define DMU_DMU_RST_BLK1_DMU_RST_PBY_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_PBY_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_PBY_SHIFT                         25

/* DMU :: dmu_rst_blk1 :: dmu_rst_pbx [24:24] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_pbx(x) WriteRegBits(DMU_DMU_RST_BLK1,0x1000000,24,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_pbx(x) ReadRegBits(DMU_DMU_RST_BLK1,0x1000000,24)
#define DMU_DMU_RST_BLK1_DMU_RST_PBX_MASK                          0x01000000
#define DMU_DMU_RST_BLK1_DMU_RST_PBX_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_PBX_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_PBX_SHIFT                         24

/* DMU :: dmu_rst_blk1 :: dmu_rst_odma [23:23] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_odma(x) WriteRegBits(DMU_DMU_RST_BLK1,0x800000,23,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_odma(x) ReadRegBits(DMU_DMU_RST_BLK1,0x800000,23)
#define DMU_DMU_RST_BLK1_DMU_RST_ODMA_MASK                         0x00800000
#define DMU_DMU_RST_BLK1_DMU_RST_ODMA_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_ODMA_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_ODMA_SHIFT                        23

/* DMU :: dmu_rst_blk1 :: dmu_rst_nvm [22:22] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_nvm(x) WriteRegBits(DMU_DMU_RST_BLK1,0x400000,22,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_nvm(x) ReadRegBits(DMU_DMU_RST_BLK1,0x400000,22)
#define DMU_DMU_RST_BLK1_DMU_RST_NVM_MASK                          0x00400000
#define DMU_DMU_RST_BLK1_DMU_RST_NVM_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_NVM_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_NVM_SHIFT                         22

/* DMU :: dmu_rst_blk1 :: dmu_rst_msr [21:21] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_msr(x) WriteRegBits(DMU_DMU_RST_BLK1,0x200000,21,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_msr(x) ReadRegBits(DMU_DMU_RST_BLK1,0x200000,21)
#define DMU_DMU_RST_BLK1_DMU_RST_MSR_MASK                          0x00200000
#define DMU_DMU_RST_BLK1_DMU_RST_MSR_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_MSR_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_MSR_SHIFT                         21

/* DMU :: dmu_rst_blk1 :: dmu_rst_mmi [20:20] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_mmi(x) WriteRegBits(DMU_DMU_RST_BLK1,0x100000,20,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_mmi(x) ReadRegBits(DMU_DMU_RST_BLK1,0x100000,20)
#define DMU_DMU_RST_BLK1_DMU_RST_MMI_MASK                          0x00100000
#define DMU_DMU_RST_BLK1_DMU_RST_MMI_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_MMI_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_MMI_SHIFT                         20

/* DMU :: dmu_rst_blk1 :: dmu_rst_mem [19:19] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_mem(x) WriteRegBits(DMU_DMU_RST_BLK1,0x80000,19,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_mem(x) ReadRegBits(DMU_DMU_RST_BLK1,0x80000,19)
#define DMU_DMU_RST_BLK1_DMU_RST_MEM_MASK                          0x00080000
#define DMU_DMU_RST_BLK1_DMU_RST_MEM_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_MEM_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_MEM_SHIFT                         19

/* DMU :: dmu_rst_blk1 :: dmu_rst_lcd [18:18] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_lcd(x) WriteRegBits(DMU_DMU_RST_BLK1,0x40000,18,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_lcd(x) ReadRegBits(DMU_DMU_RST_BLK1,0x40000,18)
#define DMU_DMU_RST_BLK1_DMU_RST_LCD_MASK                          0x00040000
#define DMU_DMU_RST_BLK1_DMU_RST_LCD_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_LCD_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_LCD_SHIFT                         18

/* DMU :: dmu_rst_blk1 :: dmu_rst_i2s [17:17] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_i2s(x) WriteRegBits(DMU_DMU_RST_BLK1,0x20000,17,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_i2s(x) ReadRegBits(DMU_DMU_RST_BLK1,0x20000,17)
#define DMU_DMU_RST_BLK1_DMU_RST_I2S_MASK                          0x00020000
#define DMU_DMU_RST_BLK1_DMU_RST_I2S_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_I2S_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_I2S_SHIFT                         17

/* DMU :: dmu_rst_blk1 :: dmu_rst_i2c1 [16:16] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_i2c1(x) WriteRegBits(DMU_DMU_RST_BLK1,0x10000,16,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_i2c1(x) ReadRegBits(DMU_DMU_RST_BLK1,0x10000,16)
#define DMU_DMU_RST_BLK1_DMU_RST_I2C1_MASK                         0x00010000
#define DMU_DMU_RST_BLK1_DMU_RST_I2C1_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_I2C1_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_I2C1_SHIFT                        16

/* DMU :: dmu_rst_blk1 :: dmu_rst_i2c0 [15:15] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_i2c0(x) WriteRegBits(DMU_DMU_RST_BLK1,0x8000,15,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_i2c0(x) ReadRegBits(DMU_DMU_RST_BLK1,0x8000,15)
#define DMU_DMU_RST_BLK1_DMU_RST_I2C0_MASK                         0x00008000
#define DMU_DMU_RST_BLK1_DMU_RST_I2C0_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_I2C0_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_I2C0_SHIFT                        15

/* DMU :: dmu_rst_blk1 :: dmu_rst_gio4 [14:14] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_gio4(x) WriteRegBits(DMU_DMU_RST_BLK1,0x4000,14,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_gio4(x) ReadRegBits(DMU_DMU_RST_BLK1,0x4000,14)
#define DMU_DMU_RST_BLK1_DMU_RST_GIO4_MASK                         0x00004000
#define DMU_DMU_RST_BLK1_DMU_RST_GIO4_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_GIO4_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_GIO4_SHIFT                        14

/* DMU :: dmu_rst_blk1 :: dmu_rst_gio3 [13:13] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_gio3(x) WriteRegBits(DMU_DMU_RST_BLK1,0x2000,13,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_gio3(x) ReadRegBits(DMU_DMU_RST_BLK1,0x2000,13)
#define DMU_DMU_RST_BLK1_DMU_RST_GIO3_MASK                         0x00002000
#define DMU_DMU_RST_BLK1_DMU_RST_GIO3_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_GIO3_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_GIO3_SHIFT                        13

/* DMU :: dmu_rst_blk1 :: dmu_rst_gio2 [12:12] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_gio2(x) WriteRegBits(DMU_DMU_RST_BLK1,0x1000,12,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_gio2(x) ReadRegBits(DMU_DMU_RST_BLK1,0x1000,12)
#define DMU_DMU_RST_BLK1_DMU_RST_GIO2_MASK                         0x00001000
#define DMU_DMU_RST_BLK1_DMU_RST_GIO2_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_GIO2_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_GIO2_SHIFT                        12

/* DMU :: dmu_rst_blk1 :: dmu_rst_gio1 [11:11] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_gio1(x) WriteRegBits(DMU_DMU_RST_BLK1,0x800,11,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_gio1(x) ReadRegBits(DMU_DMU_RST_BLK1,0x800,11)
#define DMU_DMU_RST_BLK1_DMU_RST_GIO1_MASK                         0x00000800
#define DMU_DMU_RST_BLK1_DMU_RST_GIO1_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_GIO1_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_GIO1_SHIFT                        11

/* DMU :: dmu_rst_blk1 :: dmu_rst_gio0 [10:10] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_gio0(x) WriteRegBits(DMU_DMU_RST_BLK1,0x400,10,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_gio0(x) ReadRegBits(DMU_DMU_RST_BLK1,0x400,10)
#define DMU_DMU_RST_BLK1_DMU_RST_GIO0_MASK                         0x00000400
#define DMU_DMU_RST_BLK1_DMU_RST_GIO0_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_GIO0_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_GIO0_SHIFT                        10

/* DMU :: dmu_rst_blk1 :: dmu_rst_etm [09:09] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_etm(x) WriteRegBits(DMU_DMU_RST_BLK1,0x200,9,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_etm(x) ReadRegBits(DMU_DMU_RST_BLK1,0x200,9)
#define DMU_DMU_RST_BLK1_DMU_RST_ETM_MASK                          0x00000200
#define DMU_DMU_RST_BLK1_DMU_RST_ETM_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_ETM_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_ETM_SHIFT                         9

/* DMU :: dmu_rst_blk1 :: dmu_rst_eth [08:08] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_eth(x) WriteRegBits(DMU_DMU_RST_BLK1,0x100,8,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_eth(x) ReadRegBits(DMU_DMU_RST_BLK1,0x100,8)
#define DMU_DMU_RST_BLK1_DMU_RST_ETH_MASK                          0x00000100
#define DMU_DMU_RST_BLK1_DMU_RST_ETH_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_ETH_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_ETH_SHIFT                         8

/* DMU :: dmu_rst_blk1 :: dmu_rst_dec [07:07] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_dec(x) WriteRegBits(DMU_DMU_RST_BLK1,0x80,7,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_dec(x) ReadRegBits(DMU_DMU_RST_BLK1,0x80,7)
#define DMU_DMU_RST_BLK1_DMU_RST_DEC_MASK                          0x00000080
#define DMU_DMU_RST_BLK1_DMU_RST_DEC_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_DEC_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_DEC_SHIFT                         7

/* DMU :: dmu_rst_blk1 :: dmu_rst_ddr [06:06] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_ddr(x) WriteRegBits(DMU_DMU_RST_BLK1,0x40,6,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_ddr(x) ReadRegBits(DMU_DMU_RST_BLK1,0x40,6)
#define DMU_DMU_RST_BLK1_DMU_RST_DDR_MASK                          0x00000040
#define DMU_DMU_RST_BLK1_DMU_RST_DDR_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_DDR_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_DDR_SHIFT                         6

/* DMU :: dmu_rst_blk1 :: dmu_rst_dac [05:05] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_dac(x) WriteRegBits(DMU_DMU_RST_BLK1,0x20,5,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_dac(x) ReadRegBits(DMU_DMU_RST_BLK1,0x20,5)
#define DMU_DMU_RST_BLK1_DMU_RST_DAC_MASK                          0x00000020
#define DMU_DMU_RST_BLK1_DMU_RST_DAC_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_DAC_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_DAC_SHIFT                         5

/* DMU :: dmu_rst_blk1 :: dmu_rst_d1w [04:04] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_d1w(x) WriteRegBits(DMU_DMU_RST_BLK1,0x10,4,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_d1w(x) ReadRegBits(DMU_DMU_RST_BLK1,0x10,4)
#define DMU_DMU_RST_BLK1_DMU_RST_D1W_MASK                          0x00000010
#define DMU_DMU_RST_BLK1_DMU_RST_D1W_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_D1W_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_D1W_SHIFT                         4

/* DMU :: dmu_rst_blk1 :: dmu_rst_cfg [03:03] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_cfg(x) WriteRegBits(DMU_DMU_RST_BLK1,0x8,3,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_cfg(x) ReadRegBits(DMU_DMU_RST_BLK1,0x8,3)
#define DMU_DMU_RST_BLK1_DMU_RST_CFG_MASK                          0x00000008
#define DMU_DMU_RST_BLK1_DMU_RST_CFG_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_CFG_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_CFG_SHIFT                         3

/* DMU :: dmu_rst_blk1 :: dmu_rst_bbl [02:02] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_bbl(x) WriteRegBits(DMU_DMU_RST_BLK1,0x4,2,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_bbl(x) ReadRegBits(DMU_DMU_RST_BLK1,0x4,2)
#define DMU_DMU_RST_BLK1_DMU_RST_BBL_MASK                          0x00000004
#define DMU_DMU_RST_BLK1_DMU_RST_BBL_ALIGN                         0
#define DMU_DMU_RST_BLK1_DMU_RST_BBL_BITS                          1
#define DMU_DMU_RST_BLK1_DMU_RST_BBL_SHIFT                         2

/* DMU :: dmu_rst_blk1 :: dmu_rst_adc1 [01:01] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_adc1(x) WriteRegBits(DMU_DMU_RST_BLK1,0x2,1,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_adc1(x) ReadRegBits(DMU_DMU_RST_BLK1,0x2,1)
#define DMU_DMU_RST_BLK1_DMU_RST_ADC1_MASK                         0x00000002
#define DMU_DMU_RST_BLK1_DMU_RST_ADC1_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_ADC1_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_ADC1_SHIFT                        1

/* DMU :: dmu_rst_blk1 :: dmu_rst_adc0 [00:00] */
#define Wr_DMU_dmu_rst_blk1_dmu_rst_adc0(x) WriteRegBits(DMU_DMU_RST_BLK1,0x1,0,x)
#define Rd_DMU_dmu_rst_blk1_dmu_rst_adc0(x) ReadRegBits(DMU_DMU_RST_BLK1,0x1,0)
#define DMU_DMU_RST_BLK1_DMU_RST_ADC0_MASK                         0x00000001
#define DMU_DMU_RST_BLK1_DMU_RST_ADC0_ALIGN                        0
#define DMU_DMU_RST_BLK1_DMU_RST_ADC0_BITS                         1
#define DMU_DMU_RST_BLK1_DMU_RST_ADC0_SHIFT                        0


/****************************************************************************
 * DMU :: dmu_rst_blk2
 ***************************************************************************/
/* DMU :: dmu_rst_blk2 :: reserved0 [31:27] */
#define DMU_DMU_RST_BLK2_RESERVED0_MASK                            0xf8000000
#define DMU_DMU_RST_BLK2_RESERVED0_ALIGN                           0
#define DMU_DMU_RST_BLK2_RESERVED0_BITS                            5
#define DMU_DMU_RST_BLK2_RESERVED0_SHIFT                           27

/* DMU :: dmu_rst_blk2 :: dmu_rst_ram [26:26] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_ram(x) WriteRegBits(DMU_DMU_RST_BLK2,0x4000000,26,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_ram(x) ReadRegBits(DMU_DMU_RST_BLK2,0x4000000,26)
#define DMU_DMU_RST_BLK2_DMU_RST_RAM_MASK                          0x04000000
#define DMU_DMU_RST_BLK2_DMU_RST_RAM_ALIGN                         0
#define DMU_DMU_RST_BLK2_DMU_RST_RAM_BITS                          1
#define DMU_DMU_RST_BLK2_DMU_RST_RAM_SHIFT                         26

/* DMU :: dmu_rst_blk2 :: dmu_rst_wdt [25:25] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_wdt(x) WriteRegBits(DMU_DMU_RST_BLK2,0x2000000,25,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_wdt(x) ReadRegBits(DMU_DMU_RST_BLK2,0x2000000,25)
#define DMU_DMU_RST_BLK2_DMU_RST_WDT_MASK                          0x02000000
#define DMU_DMU_RST_BLK2_DMU_RST_WDT_ALIGN                         0
#define DMU_DMU_RST_BLK2_DMU_RST_WDT_BITS                          1
#define DMU_DMU_RST_BLK2_DMU_RST_WDT_SHIFT                         25

/* DMU :: dmu_rst_blk2 :: dmu_rst_usb2 [24:24] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_usb2(x) WriteRegBits(DMU_DMU_RST_BLK2,0x1000000,24,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_usb2(x) ReadRegBits(DMU_DMU_RST_BLK2,0x1000000,24)
#define DMU_DMU_RST_BLK2_DMU_RST_USB2_MASK                         0x01000000
#define DMU_DMU_RST_BLK2_DMU_RST_USB2_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_USB2_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_USB2_SHIFT                        24

/* DMU :: dmu_rst_blk2 :: dmu_rst_usb1 [23:23] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_usb1(x) WriteRegBits(DMU_DMU_RST_BLK2,0x800000,23,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_usb1(x) ReadRegBits(DMU_DMU_RST_BLK2,0x800000,23)
#define DMU_DMU_RST_BLK2_DMU_RST_USB1_MASK                         0x00800000
#define DMU_DMU_RST_BLK2_DMU_RST_USB1_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_USB1_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_USB1_SHIFT                        23

/* DMU :: dmu_rst_blk2 :: dmu_rst_usb0 [22:22] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_usb0(x) WriteRegBits(DMU_DMU_RST_BLK2,0x400000,22,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_usb0(x) ReadRegBits(DMU_DMU_RST_BLK2,0x400000,22)
#define DMU_DMU_RST_BLK2_DMU_RST_USB0_MASK                         0x00400000
#define DMU_DMU_RST_BLK2_DMU_RST_USB0_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_USB0_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_USB0_SHIFT                        22

/* DMU :: dmu_rst_blk2 :: dmu_rst_urt3 [21:21] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_urt3(x) WriteRegBits(DMU_DMU_RST_BLK2,0x200000,21,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_urt3(x) ReadRegBits(DMU_DMU_RST_BLK2,0x200000,21)
#define DMU_DMU_RST_BLK2_DMU_RST_URT3_MASK                         0x00200000
#define DMU_DMU_RST_BLK2_DMU_RST_URT3_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_URT3_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_URT3_SHIFT                        21

/* DMU :: dmu_rst_blk2 :: dmu_rst_urt2 [20:20] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_urt2(x) WriteRegBits(DMU_DMU_RST_BLK2,0x100000,20,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_urt2(x) ReadRegBits(DMU_DMU_RST_BLK2,0x100000,20)
#define DMU_DMU_RST_BLK2_DMU_RST_URT2_MASK                         0x00100000
#define DMU_DMU_RST_BLK2_DMU_RST_URT2_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_URT2_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_URT2_SHIFT                        20

/* DMU :: dmu_rst_blk2 :: dmu_rst_urt1 [19:19] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_urt1(x) WriteRegBits(DMU_DMU_RST_BLK2,0x80000,19,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_urt1(x) ReadRegBits(DMU_DMU_RST_BLK2,0x80000,19)
#define DMU_DMU_RST_BLK2_DMU_RST_URT1_MASK                         0x00080000
#define DMU_DMU_RST_BLK2_DMU_RST_URT1_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_URT1_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_URT1_SHIFT                        19

/* DMU :: dmu_rst_blk2 :: dmu_rst_urt0 [18:18] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_urt0(x) WriteRegBits(DMU_DMU_RST_BLK2,0x40000,18,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_urt0(x) ReadRegBits(DMU_DMU_RST_BLK2,0x40000,18)
#define DMU_DMU_RST_BLK2_DMU_RST_URT0_MASK                         0x00040000
#define DMU_DMU_RST_BLK2_DMU_RST_URT0_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_URT0_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_URT0_SHIFT                        18

/* DMU :: dmu_rst_blk2 :: dmu_rst_umc [17:17] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_umc(x) WriteRegBits(DMU_DMU_RST_BLK2,0x20000,17,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_umc(x) ReadRegBits(DMU_DMU_RST_BLK2,0x20000,17)
#define DMU_DMU_RST_BLK2_DMU_RST_UMC_MASK                          0x00020000
#define DMU_DMU_RST_BLK2_DMU_RST_UMC_ALIGN                         0
#define DMU_DMU_RST_BLK2_DMU_RST_UMC_BITS                          1
#define DMU_DMU_RST_BLK2_DMU_RST_UMC_SHIFT                         17

/* DMU :: dmu_rst_blk2 :: dmu_rst_tpb [16:16] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_tpb(x) WriteRegBits(DMU_DMU_RST_BLK2,0x10000,16,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_tpb(x) ReadRegBits(DMU_DMU_RST_BLK2,0x10000,16)
#define DMU_DMU_RST_BLK2_DMU_RST_TPB_MASK                          0x00010000
#define DMU_DMU_RST_BLK2_DMU_RST_TPB_ALIGN                         0
#define DMU_DMU_RST_BLK2_DMU_RST_TPB_BITS                          1
#define DMU_DMU_RST_BLK2_DMU_RST_TPB_SHIFT                         16

/* DMU :: dmu_rst_blk2 :: dmu_rst_tim4 [15:15] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_tim4(x) WriteRegBits(DMU_DMU_RST_BLK2,0x8000,15,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_tim4(x) ReadRegBits(DMU_DMU_RST_BLK2,0x8000,15)
#define DMU_DMU_RST_BLK2_DMU_RST_TIM4_MASK                         0x00008000
#define DMU_DMU_RST_BLK2_DMU_RST_TIM4_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_TIM4_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_TIM4_SHIFT                        15

/* DMU :: dmu_rst_blk2 :: dmu_rst_tim3 [14:14] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_tim3(x) WriteRegBits(DMU_DMU_RST_BLK2,0x4000,14,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_tim3(x) ReadRegBits(DMU_DMU_RST_BLK2,0x4000,14)
#define DMU_DMU_RST_BLK2_DMU_RST_TIM3_MASK                         0x00004000
#define DMU_DMU_RST_BLK2_DMU_RST_TIM3_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_TIM3_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_TIM3_SHIFT                        14

/* DMU :: dmu_rst_blk2 :: dmu_rst_tim2 [13:13] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_tim2(x) WriteRegBits(DMU_DMU_RST_BLK2,0x2000,13,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_tim2(x) ReadRegBits(DMU_DMU_RST_BLK2,0x2000,13)
#define DMU_DMU_RST_BLK2_DMU_RST_TIM2_MASK                         0x00002000
#define DMU_DMU_RST_BLK2_DMU_RST_TIM2_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_TIM2_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_TIM2_SHIFT                        13

/* DMU :: dmu_rst_blk2 :: dmu_rst_tim1 [12:12] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_tim1(x) WriteRegBits(DMU_DMU_RST_BLK2,0x1000,12,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_tim1(x) ReadRegBits(DMU_DMU_RST_BLK2,0x1000,12)
#define DMU_DMU_RST_BLK2_DMU_RST_TIM1_MASK                         0x00001000
#define DMU_DMU_RST_BLK2_DMU_RST_TIM1_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_TIM1_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_TIM1_SHIFT                        12

/* DMU :: dmu_rst_blk2 :: dmu_rst_tim0 [11:11] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_tim0(x) WriteRegBits(DMU_DMU_RST_BLK2,0x800,11,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_tim0(x) ReadRegBits(DMU_DMU_RST_BLK2,0x800,11)
#define DMU_DMU_RST_BLK2_DMU_RST_TIM0_MASK                         0x00000800
#define DMU_DMU_RST_BLK2_DMU_RST_TIM0_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_TIM0_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_TIM0_SHIFT                        11

/* DMU :: dmu_rst_blk2 :: dmu_rst_spl [10:10] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_spl(x) WriteRegBits(DMU_DMU_RST_BLK2,0x400,10,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_spl(x) ReadRegBits(DMU_DMU_RST_BLK2,0x400,10)
#define DMU_DMU_RST_BLK2_DMU_RST_SPL_MASK                          0x00000400
#define DMU_DMU_RST_BLK2_DMU_RST_SPL_ALIGN                         0
#define DMU_DMU_RST_BLK2_DMU_RST_SPL_BITS                          1
#define DMU_DMU_RST_BLK2_DMU_RST_SPL_SHIFT                         10

/* DMU :: dmu_rst_blk2 :: dmu_rst_qspi [09:09] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_qspi(x) WriteRegBits(DMU_DMU_RST_BLK2,0x200,9,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_qspi(x) ReadRegBits(DMU_DMU_RST_BLK2,0x200,9)
#define DMU_DMU_RST_BLK2_DMU_RST_QSPI_MASK                         0x00000200
#define DMU_DMU_RST_BLK2_DMU_RST_QSPI_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_QSPI_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_QSPI_SHIFT                        9

/* DMU :: dmu_rst_blk2 :: dmu_rst_spi2 [08:08] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_spi2(x) WriteRegBits(DMU_DMU_RST_BLK2,0x100,8,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_spi2(x) ReadRegBits(DMU_DMU_RST_BLK2,0x100,8)
#define DMU_DMU_RST_BLK2_DMU_RST_SPI2_MASK                         0x00000100
#define DMU_DMU_RST_BLK2_DMU_RST_SPI2_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_SPI2_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_SPI2_SHIFT                        8

/* DMU :: dmu_rst_blk2 :: dmu_rst_spi1 [07:07] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_spi1(x) WriteRegBits(DMU_DMU_RST_BLK2,0x80,7,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_spi1(x) ReadRegBits(DMU_DMU_RST_BLK2,0x80,7)
#define DMU_DMU_RST_BLK2_DMU_RST_SPI1_MASK                         0x00000080
#define DMU_DMU_RST_BLK2_DMU_RST_SPI1_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_SPI1_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_SPI1_SHIFT                        7

/* DMU :: dmu_rst_blk2 :: dmu_rst_spi0 [06:06] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_spi0(x) WriteRegBits(DMU_DMU_RST_BLK2,0x40,6,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_spi0(x) ReadRegBits(DMU_DMU_RST_BLK2,0x40,6)
#define DMU_DMU_RST_BLK2_DMU_RST_SPI0_MASK                         0x00000040
#define DMU_DMU_RST_BLK2_DMU_RST_SPI0_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_SPI0_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_SPI0_SHIFT                        6

/* DMU :: dmu_rst_blk2 :: dmu_rst_smu [05:05] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_smu(x) WriteRegBits(DMU_DMU_RST_BLK2,0x20,5,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_smu(x) ReadRegBits(DMU_DMU_RST_BLK2,0x20,5)
#define DMU_DMU_RST_BLK2_DMU_RST_SMU_MASK                          0x00000020
#define DMU_DMU_RST_BLK2_DMU_RST_SMU_ALIGN                         0
#define DMU_DMU_RST_BLK2_DMU_RST_SMU_BITS                          1
#define DMU_DMU_RST_BLK2_DMU_RST_SMU_SHIFT                         5

/* DMU :: dmu_rst_blk2 :: dmu_rst_smc [04:04] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_smc(x) WriteRegBits(DMU_DMU_RST_BLK2,0x10,4,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_smc(x) ReadRegBits(DMU_DMU_RST_BLK2,0x10,4)
#define DMU_DMU_RST_BLK2_DMU_RST_SMC_MASK                          0x00000010
#define DMU_DMU_RST_BLK2_DMU_RST_SMC_ALIGN                         0
#define DMU_DMU_RST_BLK2_DMU_RST_SMC_BITS                          1
#define DMU_DMU_RST_BLK2_DMU_RST_SMC_SHIFT                         4

/* DMU :: dmu_rst_blk2 :: dmu_rst_sdma [03:03] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_sdma(x) WriteRegBits(DMU_DMU_RST_BLK2,0x8,3,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_sdma(x) ReadRegBits(DMU_DMU_RST_BLK2,0x8,3)
#define DMU_DMU_RST_BLK2_DMU_RST_SDMA_MASK                         0x00000008
#define DMU_DMU_RST_BLK2_DMU_RST_SDMA_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_SDMA_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_SDMA_SHIFT                        3

/* DMU :: dmu_rst_blk2 :: dmu_rst_sdm1 [02:02] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_sdm1(x) WriteRegBits(DMU_DMU_RST_BLK2,0x4,2,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_sdm1(x) ReadRegBits(DMU_DMU_RST_BLK2,0x4,2)
#define DMU_DMU_RST_BLK2_DMU_RST_SDM1_MASK                         0x00000004
#define DMU_DMU_RST_BLK2_DMU_RST_SDM1_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_SDM1_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_SDM1_SHIFT                        2

/* DMU :: dmu_rst_blk2 :: dmu_rst_sdm0 [01:01] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_sdm0(x) WriteRegBits(DMU_DMU_RST_BLK2,0x2,1,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_sdm0(x) ReadRegBits(DMU_DMU_RST_BLK2,0x2,1)
#define DMU_DMU_RST_BLK2_DMU_RST_SDM0_MASK                         0x00000002
#define DMU_DMU_RST_BLK2_DMU_RST_SDM0_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_SDM0_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_SDM0_SHIFT                        1

/* DMU :: dmu_rst_blk2 :: dmu_rst_sci1 [00:00] */
#define Wr_DMU_dmu_rst_blk2_dmu_rst_sci1(x) WriteRegBits(DMU_DMU_RST_BLK2,0x1,0,x)
#define Rd_DMU_dmu_rst_blk2_dmu_rst_sci1(x) ReadRegBits(DMU_DMU_RST_BLK2,0x1,0)
#define DMU_DMU_RST_BLK2_DMU_RST_SCI1_MASK                         0x00000001
#define DMU_DMU_RST_BLK2_DMU_RST_SCI1_ALIGN                        0
#define DMU_DMU_RST_BLK2_DMU_RST_SCI1_BITS                         1
#define DMU_DMU_RST_BLK2_DMU_RST_SCI1_SHIFT                        0


/****************************************************************************
 * DMU :: dmu_pwd_blk1
 ***************************************************************************/
/* DMU :: dmu_pwd_blk1 :: dmu_pwd_sci0 [31:31] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_sci0(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x80000000,31,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_sci0(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x80000000,31)
#define DMU_DMU_PWD_BLK1_DMU_PWD_SCI0_MASK                         0x80000000
#define DMU_DMU_PWD_BLK1_DMU_PWD_SCI0_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_SCI0_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_SCI0_SHIFT                        31

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_rom [30:30] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_rom(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x40000000,30,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_rom(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x40000000,30)
#define DMU_DMU_PWD_BLK1_DMU_PWD_ROM_MASK                          0x40000000
#define DMU_DMU_PWD_BLK1_DMU_PWD_ROM_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_ROM_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_ROM_SHIFT                         30

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_rng [29:29] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_rng(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x20000000,29,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_rng(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x20000000,29)
#define DMU_DMU_PWD_BLK1_DMU_PWD_RNG_MASK                          0x20000000
#define DMU_DMU_PWD_BLK1_DMU_PWD_RNG_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_RNG_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_RNG_SHIFT                         29

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_pwm [28:28] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_pwm(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x10000000,28,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_pwm(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x10000000,28)
#define DMU_DMU_PWD_BLK1_DMU_PWD_PWM_MASK                          0x10000000
#define DMU_DMU_PWD_BLK1_DMU_PWD_PWM_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_PWM_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_PWM_SHIFT                         28

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_pka [27:27] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_pka(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x8000000,27,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_pka(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x8000000,27)
#define DMU_DMU_PWD_BLK1_DMU_PWD_PKA_MASK                          0x08000000
#define DMU_DMU_PWD_BLK1_DMU_PWD_PKA_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_PKA_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_PKA_SHIFT                         27

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_pbz [26:26] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_pbz(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x4000000,26,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_pbz(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x4000000,26)
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBZ_MASK                          0x04000000
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBZ_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBZ_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBZ_SHIFT                         26

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_pby [25:25] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_pby(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x2000000,25,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_pby(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x2000000,25)
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBY_MASK                          0x02000000
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBY_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBY_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBY_SHIFT                         25

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_pbx [24:24] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_pbx(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x1000000,24,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_pbx(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x1000000,24)
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBX_MASK                          0x01000000
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBX_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBX_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_PBX_SHIFT                         24

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_odma [23:23] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_odma(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x800000,23,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_odma(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x800000,23)
#define DMU_DMU_PWD_BLK1_DMU_PWD_ODMA_MASK                         0x00800000
#define DMU_DMU_PWD_BLK1_DMU_PWD_ODMA_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_ODMA_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_ODMA_SHIFT                        23

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_nvm [22:22] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_nvm(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x400000,22,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_nvm(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x400000,22)
#define DMU_DMU_PWD_BLK1_DMU_PWD_NVM_MASK                          0x00400000
#define DMU_DMU_PWD_BLK1_DMU_PWD_NVM_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_NVM_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_NVM_SHIFT                         22

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_msr [21:21] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_msr(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x200000,21,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_msr(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x200000,21)
#define DMU_DMU_PWD_BLK1_DMU_PWD_MSR_MASK                          0x00200000
#define DMU_DMU_PWD_BLK1_DMU_PWD_MSR_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_MSR_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_MSR_SHIFT                         21

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_mmi [20:20] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_mmi(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x100000,20,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_mmi(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x100000,20)
#define DMU_DMU_PWD_BLK1_DMU_PWD_MMI_MASK                          0x00100000
#define DMU_DMU_PWD_BLK1_DMU_PWD_MMI_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_MMI_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_MMI_SHIFT                         20

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_mem [19:19] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_mem(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x80000,19,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_mem(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x80000,19)
#define DMU_DMU_PWD_BLK1_DMU_PWD_MEM_MASK                          0x00080000
#define DMU_DMU_PWD_BLK1_DMU_PWD_MEM_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_MEM_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_MEM_SHIFT                         19

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_lcd [18:18] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_lcd(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x40000,18,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_lcd(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x40000,18)
#define DMU_DMU_PWD_BLK1_DMU_PWD_LCD_MASK                          0x00040000
#define DMU_DMU_PWD_BLK1_DMU_PWD_LCD_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_LCD_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_LCD_SHIFT                         18

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_i2s [17:17] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_i2s(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x20000,17,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_i2s(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x20000,17)
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2S_MASK                          0x00020000
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2S_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2S_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2S_SHIFT                         17

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_i2c1 [16:16] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_i2c1(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x10000,16,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_i2c1(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x10000,16)
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2C1_MASK                         0x00010000
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2C1_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2C1_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2C1_SHIFT                        16

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_i2c0 [15:15] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_i2c0(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x8000,15,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_i2c0(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x8000,15)
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2C0_MASK                         0x00008000
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2C0_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2C0_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_I2C0_SHIFT                        15

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_gio4 [14:14] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_gio4(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x4000,14,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_gio4(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x4000,14)
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO4_MASK                         0x00004000
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO4_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO4_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO4_SHIFT                        14

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_gio3 [13:13] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_gio3(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x2000,13,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_gio3(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x2000,13)
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO3_MASK                         0x00002000
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO3_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO3_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO3_SHIFT                        13

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_gio2 [12:12] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_gio2(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x1000,12,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_gio2(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x1000,12)
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO2_MASK                         0x00001000
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO2_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO2_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO2_SHIFT                        12

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_gio1 [11:11] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_gio1(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x800,11,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_gio1(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x800,11)
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO1_MASK                         0x00000800
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO1_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO1_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO1_SHIFT                        11

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_gio0 [10:10] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_gio0(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x400,10,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_gio0(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x400,10)
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO0_MASK                         0x00000400
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO0_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO0_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_GIO0_SHIFT                        10

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_etm [09:09] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_etm(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x200,9,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_etm(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x200,9)
#define DMU_DMU_PWD_BLK1_DMU_PWD_ETM_MASK                          0x00000200
#define DMU_DMU_PWD_BLK1_DMU_PWD_ETM_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_ETM_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_ETM_SHIFT                         9

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_eth [08:08] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_eth(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x100,8,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_eth(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x100,8)
#define DMU_DMU_PWD_BLK1_DMU_PWD_ETH_MASK                          0x00000100
#define DMU_DMU_PWD_BLK1_DMU_PWD_ETH_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_ETH_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_ETH_SHIFT                         8

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_dec [07:07] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_dec(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x80,7,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_dec(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x80,7)
#define DMU_DMU_PWD_BLK1_DMU_PWD_DEC_MASK                          0x00000080
#define DMU_DMU_PWD_BLK1_DMU_PWD_DEC_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_DEC_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_DEC_SHIFT                         7

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_ddr [06:06] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_ddr(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x40,6,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_ddr(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x40,6)
#define DMU_DMU_PWD_BLK1_DMU_PWD_DDR_MASK                          0x00000040
#define DMU_DMU_PWD_BLK1_DMU_PWD_DDR_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_DDR_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_DDR_SHIFT                         6

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_dac [05:05] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_dac(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x20,5,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_dac(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x20,5)
#define DMU_DMU_PWD_BLK1_DMU_PWD_DAC_MASK                          0x00000020
#define DMU_DMU_PWD_BLK1_DMU_PWD_DAC_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_DAC_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_DAC_SHIFT                         5

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_d1w [04:04] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_d1w(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x10,4,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_d1w(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x10,4)
#define DMU_DMU_PWD_BLK1_DMU_PWD_D1W_MASK                          0x00000010
#define DMU_DMU_PWD_BLK1_DMU_PWD_D1W_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_D1W_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_D1W_SHIFT                         4

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_cfg [03:03] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_cfg(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x8,3,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_cfg(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x8,3)
#define DMU_DMU_PWD_BLK1_DMU_PWD_CFG_MASK                          0x00000008
#define DMU_DMU_PWD_BLK1_DMU_PWD_CFG_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_CFG_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_CFG_SHIFT                         3

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_bbl [02:02] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_bbl(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x4,2,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_bbl(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x4,2)
#define DMU_DMU_PWD_BLK1_DMU_PWD_BBL_MASK                          0x00000004
#define DMU_DMU_PWD_BLK1_DMU_PWD_BBL_ALIGN                         0
#define DMU_DMU_PWD_BLK1_DMU_PWD_BBL_BITS                          1
#define DMU_DMU_PWD_BLK1_DMU_PWD_BBL_SHIFT                         2

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_adc1 [01:01] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_adc1(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x2,1,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_adc1(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x2,1)
#define DMU_DMU_PWD_BLK1_DMU_PWD_ADC1_MASK                         0x00000002
#define DMU_DMU_PWD_BLK1_DMU_PWD_ADC1_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_ADC1_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_ADC1_SHIFT                        1

/* DMU :: dmu_pwd_blk1 :: dmu_pwd_adc0 [00:00] */
#define Wr_DMU_dmu_pwd_blk1_dmu_pwd_adc0(x) WriteRegBits(DMU_DMU_PWD_BLK1,0x1,0,x)
#define Rd_DMU_dmu_pwd_blk1_dmu_pwd_adc0(x) ReadRegBits(DMU_DMU_PWD_BLK1,0x1,0)
#define DMU_DMU_PWD_BLK1_DMU_PWD_ADC0_MASK                         0x00000001
#define DMU_DMU_PWD_BLK1_DMU_PWD_ADC0_ALIGN                        0
#define DMU_DMU_PWD_BLK1_DMU_PWD_ADC0_BITS                         1
#define DMU_DMU_PWD_BLK1_DMU_PWD_ADC0_SHIFT                        0


/****************************************************************************
 * DMU :: dmu_pwd_blk2
 ***************************************************************************/
/* DMU :: dmu_pwd_blk2 :: reserved0 [31:27] */
#define DMU_DMU_PWD_BLK2_RESERVED0_MASK                            0xf8000000
#define DMU_DMU_PWD_BLK2_RESERVED0_ALIGN                           0
#define DMU_DMU_PWD_BLK2_RESERVED0_BITS                            5
#define DMU_DMU_PWD_BLK2_RESERVED0_SHIFT                           27

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_ram [26:26] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_ram(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x4000000,26,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_ram(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x4000000,26)
#define DMU_DMU_PWD_BLK2_DMU_PWD_RAM_MASK                          0x04000000
#define DMU_DMU_PWD_BLK2_DMU_PWD_RAM_ALIGN                         0
#define DMU_DMU_PWD_BLK2_DMU_PWD_RAM_BITS                          1
#define DMU_DMU_PWD_BLK2_DMU_PWD_RAM_SHIFT                         26

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_wdt [25:25] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_wdt(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x2000000,25,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_wdt(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x2000000,25)
#define DMU_DMU_PWD_BLK2_DMU_PWD_WDT_MASK                          0x02000000
#define DMU_DMU_PWD_BLK2_DMU_PWD_WDT_ALIGN                         0
#define DMU_DMU_PWD_BLK2_DMU_PWD_WDT_BITS                          1
#define DMU_DMU_PWD_BLK2_DMU_PWD_WDT_SHIFT                         25

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_usb2 [24:24] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_usb2(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x1000000,24,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_usb2(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x1000000,24)
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB2_MASK                         0x01000000
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB2_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB2_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB2_SHIFT                        24

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_usb1 [23:23] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_usb1(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x800000,23,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_usb1(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x800000,23)
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB1_MASK                         0x00800000
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB1_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB1_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB1_SHIFT                        23

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_usb0 [22:22] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_usb0(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x400000,22,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_usb0(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x400000,22)
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB0_MASK                         0x00400000
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB0_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB0_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_USB0_SHIFT                        22

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_urt3 [21:21] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_urt3(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x200000,21,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_urt3(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x200000,21)
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT3_MASK                         0x00200000
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT3_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT3_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT3_SHIFT                        21

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_urt2 [20:20] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_urt2(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x100000,20,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_urt2(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x100000,20)
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT2_MASK                         0x00100000
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT2_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT2_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT2_SHIFT                        20

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_urt1 [19:19] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_urt1(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x80000,19,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_urt1(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x80000,19)
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT1_MASK                         0x00080000
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT1_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT1_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT1_SHIFT                        19

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_urt0 [18:18] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_urt0(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x40000,18,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_urt0(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x40000,18)
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT0_MASK                         0x00040000
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT0_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT0_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_URT0_SHIFT                        18

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_umc [17:17] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_umc(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x20000,17,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_umc(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x20000,17)
#define DMU_DMU_PWD_BLK2_DMU_PWD_UMC_MASK                          0x00020000
#define DMU_DMU_PWD_BLK2_DMU_PWD_UMC_ALIGN                         0
#define DMU_DMU_PWD_BLK2_DMU_PWD_UMC_BITS                          1
#define DMU_DMU_PWD_BLK2_DMU_PWD_UMC_SHIFT                         17

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_tpb [16:16] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_tpb(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x10000,16,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_tpb(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x10000,16)
#define DMU_DMU_PWD_BLK2_DMU_PWD_TPB_MASK                          0x00010000
#define DMU_DMU_PWD_BLK2_DMU_PWD_TPB_ALIGN                         0
#define DMU_DMU_PWD_BLK2_DMU_PWD_TPB_BITS                          1
#define DMU_DMU_PWD_BLK2_DMU_PWD_TPB_SHIFT                         16

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_tim4 [15:15] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_tim4(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x8000,15,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_tim4(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x8000,15)
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM4_MASK                         0x00008000
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM4_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM4_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM4_SHIFT                        15

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_tim3 [14:14] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_tim3(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x4000,14,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_tim3(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x4000,14)
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM3_MASK                         0x00004000
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM3_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM3_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM3_SHIFT                        14

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_tim2 [13:13] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_tim2(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x2000,13,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_tim2(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x2000,13)
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM2_MASK                         0x00002000
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM2_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM2_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM2_SHIFT                        13

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_tim1 [12:12] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_tim1(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x1000,12,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_tim1(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x1000,12)
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM1_MASK                         0x00001000
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM1_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM1_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM1_SHIFT                        12

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_tim0 [11:11] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_tim0(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x800,11,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_tim0(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x800,11)
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM0_MASK                         0x00000800
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM0_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM0_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_TIM0_SHIFT                        11

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_spl [10:10] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_spl(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x400,10,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_spl(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x400,10)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPL_MASK                          0x00000400
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPL_ALIGN                         0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPL_BITS                          1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPL_SHIFT                         10

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_qspi [09:09] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_qspi(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x200,9,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_qspi(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x200,9)
#define DMU_DMU_PWD_BLK2_DMU_PWD_QSPI_MASK                         0x00000200
#define DMU_DMU_PWD_BLK2_DMU_PWD_QSPI_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_QSPI_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_QSPI_SHIFT                        9

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_spi2 [08:08] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_spi2(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x100,8,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_spi2(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x100,8)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI2_MASK                         0x00000100
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI2_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI2_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI2_SHIFT                        8

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_spi1 [07:07] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_spi1(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x80,7,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_spi1(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x80,7)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI1_MASK                         0x00000080
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI1_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI1_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI1_SHIFT                        7

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_spi0 [06:06] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_spi0(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x40,6,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_spi0(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x40,6)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI0_MASK                         0x00000040
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI0_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI0_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SPI0_SHIFT                        6

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_smu [05:05] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_smu(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x20,5,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_smu(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x20,5)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SMU_MASK                          0x00000020
#define DMU_DMU_PWD_BLK2_DMU_PWD_SMU_ALIGN                         0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SMU_BITS                          1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SMU_SHIFT                         5

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_smc [04:04] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_smc(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x10,4,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_smc(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x10,4)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SMC_MASK                          0x00000010
#define DMU_DMU_PWD_BLK2_DMU_PWD_SMC_ALIGN                         0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SMC_BITS                          1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SMC_SHIFT                         4

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_sdma [03:03] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_sdma(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x8,3,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_sdma(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x8,3)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDMA_MASK                         0x00000008
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDMA_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDMA_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDMA_SHIFT                        3

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_sdm1 [02:02] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_sdm1(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x4,2,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_sdm1(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x4,2)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDM1_MASK                         0x00000004
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDM1_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDM1_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDM1_SHIFT                        2

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_sdm0 [01:01] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_sdm0(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x2,1,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_sdm0(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x2,1)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDM0_MASK                         0x00000002
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDM0_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDM0_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SDM0_SHIFT                        1

/* DMU :: dmu_pwd_blk2 :: dmu_pwd_sci1 [00:00] */
#define Wr_DMU_dmu_pwd_blk2_dmu_pwd_sci1(x) WriteRegBits(DMU_DMU_PWD_BLK2,0x1,0,x)
#define Rd_DMU_dmu_pwd_blk2_dmu_pwd_sci1(x) ReadRegBits(DMU_DMU_PWD_BLK2,0x1,0)
#define DMU_DMU_PWD_BLK2_DMU_PWD_SCI1_MASK                         0x00000001
#define DMU_DMU_PWD_BLK2_DMU_PWD_SCI1_ALIGN                        0
#define DMU_DMU_PWD_BLK2_DMU_PWD_SCI1_BITS                         1
#define DMU_DMU_PWD_BLK2_DMU_PWD_SCI1_SHIFT                        0


/****************************************************************************
 * DMU :: dmu_pwd_err_blk1
 ***************************************************************************/
/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_sci0 [31:31] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_sci0(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x80000000,31,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_sci0(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x80000000,31)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_SCI0_MASK                 0x80000000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_SCI0_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_SCI0_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_SCI0_SHIFT                31

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_rom [30:30] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_rom(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x40000000,30,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_rom(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x40000000,30)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ROM_MASK                  0x40000000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ROM_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ROM_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ROM_SHIFT                 30

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_rng [29:29] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_rng(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x20000000,29,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_rng(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x20000000,29)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_RNG_MASK                  0x20000000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_RNG_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_RNG_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_RNG_SHIFT                 29

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_pwm [28:28] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pwm(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x10000000,28,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pwm(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x10000000,28)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PWM_MASK                  0x10000000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PWM_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PWM_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PWM_SHIFT                 28

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_pka [27:27] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pka(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x8000000,27,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pka(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x8000000,27)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PKA_MASK                  0x08000000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PKA_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PKA_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PKA_SHIFT                 27

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_pbz [26:26] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pbz(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x4000000,26,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pbz(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x4000000,26)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBZ_MASK                  0x04000000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBZ_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBZ_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBZ_SHIFT                 26

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_pby [25:25] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pby(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x2000000,25,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pby(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x2000000,25)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBY_MASK                  0x02000000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBY_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBY_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBY_SHIFT                 25

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_pbx [24:24] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pbx(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x1000000,24,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_pbx(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x1000000,24)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBX_MASK                  0x01000000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBX_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBX_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_PBX_SHIFT                 24

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_odma [23:23] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_odma(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x800000,23,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_odma(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x800000,23)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ODMA_MASK                 0x00800000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ODMA_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ODMA_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ODMA_SHIFT                23

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_nvm [22:22] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_nvm(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x400000,22,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_nvm(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x400000,22)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_NVM_MASK                  0x00400000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_NVM_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_NVM_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_NVM_SHIFT                 22

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_msr [21:21] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_msr(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x200000,21,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_msr(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x200000,21)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MSR_MASK                  0x00200000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MSR_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MSR_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MSR_SHIFT                 21

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_mmi [20:20] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_mmi(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x100000,20,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_mmi(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x100000,20)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MMI_MASK                  0x00100000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MMI_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MMI_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MMI_SHIFT                 20

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_mem [19:19] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_mem(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x80000,19,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_mem(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x80000,19)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MEM_MASK                  0x00080000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MEM_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MEM_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_MEM_SHIFT                 19

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_lcd [18:18] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_lcd(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x40000,18,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_lcd(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x40000,18)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_LCD_MASK                  0x00040000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_LCD_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_LCD_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_LCD_SHIFT                 18

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_i2s [17:17] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_i2s(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x20000,17,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_i2s(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x20000,17)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2S_MASK                  0x00020000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2S_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2S_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2S_SHIFT                 17

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_i2c1 [16:16] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_i2c1(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x10000,16,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_i2c1(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x10000,16)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2C1_MASK                 0x00010000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2C1_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2C1_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2C1_SHIFT                16

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_i2c0 [15:15] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_i2c0(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x8000,15,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_i2c0(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x8000,15)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2C0_MASK                 0x00008000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2C0_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2C0_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_I2C0_SHIFT                15

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_gio4 [14:14] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio4(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x4000,14,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio4(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x4000,14)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO4_MASK                 0x00004000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO4_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO4_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO4_SHIFT                14

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_gio3 [13:13] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio3(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x2000,13,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio3(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x2000,13)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO3_MASK                 0x00002000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO3_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO3_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO3_SHIFT                13

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_gio2 [12:12] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio2(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x1000,12,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio2(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x1000,12)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO2_MASK                 0x00001000
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO2_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO2_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO2_SHIFT                12

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_gio1 [11:11] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio1(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x800,11,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio1(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x800,11)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO1_MASK                 0x00000800
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO1_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO1_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO1_SHIFT                11

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_gio0 [10:10] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio0(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x400,10,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_gio0(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x400,10)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO0_MASK                 0x00000400
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO0_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO0_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_GIO0_SHIFT                10

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_etm [09:09] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_etm(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x200,9,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_etm(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x200,9)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ETM_MASK                  0x00000200
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ETM_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ETM_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ETM_SHIFT                 9

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_eth [08:08] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_eth(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x100,8,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_eth(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x100,8)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ETH_MASK                  0x00000100
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ETH_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ETH_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ETH_SHIFT                 8

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_dec [07:07] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_dec(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x80,7,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_dec(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x80,7)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DEC_MASK                  0x00000080
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DEC_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DEC_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DEC_SHIFT                 7

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_ddr [06:06] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_ddr(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x40,6,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_ddr(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x40,6)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DDR_MASK                  0x00000040
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DDR_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DDR_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DDR_SHIFT                 6

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_dac [05:05] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_dac(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x20,5,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_dac(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x20,5)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DAC_MASK                  0x00000020
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DAC_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DAC_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_DAC_SHIFT                 5

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_d1w [04:04] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_d1w(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x10,4,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_d1w(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x10,4)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_D1W_MASK                  0x00000010
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_D1W_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_D1W_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_D1W_SHIFT                 4

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_cfg [03:03] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_cfg(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x8,3,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_cfg(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x8,3)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_CFG_MASK                  0x00000008
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_CFG_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_CFG_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_CFG_SHIFT                 3

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_bbl [02:02] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_bbl(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x4,2,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_bbl(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x4,2)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_BBL_MASK                  0x00000004
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_BBL_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_BBL_BITS                  1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_BBL_SHIFT                 2

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_adc1 [01:01] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_adc1(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x2,1,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_adc1(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x2,1)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ADC1_MASK                 0x00000002
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ADC1_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ADC1_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ADC1_SHIFT                1

/* DMU :: dmu_pwd_err_blk1 :: dmu_pwd_err_adc0 [00:00] */
#define Wr_DMU_dmu_pwd_err_blk1_dmu_pwd_err_adc0(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK1,0x1,0,x)
#define Rd_DMU_dmu_pwd_err_blk1_dmu_pwd_err_adc0(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK1,0x1,0)
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ADC0_MASK                 0x00000001
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ADC0_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ADC0_BITS                 1
#define DMU_DMU_PWD_ERR_BLK1_DMU_PWD_ERR_ADC0_SHIFT                0


/****************************************************************************
 * DMU :: dmu_pwd_err_blk2
 ***************************************************************************/
/* DMU :: dmu_pwd_err_blk2 :: reserved0 [31:27] */
#define DMU_DMU_PWD_ERR_BLK2_RESERVED0_MASK                        0xf8000000
#define DMU_DMU_PWD_ERR_BLK2_RESERVED0_ALIGN                       0
#define DMU_DMU_PWD_ERR_BLK2_RESERVED0_BITS                        5
#define DMU_DMU_PWD_ERR_BLK2_RESERVED0_SHIFT                       27

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_ram [26:26] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_ram(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x4000000,26,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_ram(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x4000000,26)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_RAM_MASK                  0x04000000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_RAM_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_RAM_BITS                  1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_RAM_SHIFT                 26

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_wdt [25:25] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_wdt(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x2000000,25,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_wdt(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x2000000,25)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_WDT_MASK                  0x02000000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_WDT_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_WDT_BITS                  1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_WDT_SHIFT                 25

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_usb2 [24:24] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_usb2(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x1000000,24,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_usb2(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x1000000,24)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB2_MASK                 0x01000000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB2_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB2_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB2_SHIFT                24

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_usb1 [23:23] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_usb1(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x800000,23,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_usb1(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x800000,23)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB1_MASK                 0x00800000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB1_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB1_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB1_SHIFT                23

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_usb0 [22:22] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_usb0(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x400000,22,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_usb0(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x400000,22)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB0_MASK                 0x00400000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB0_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB0_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_USB0_SHIFT                22

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_urt3 [21:21] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_urt3(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x200000,21,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_urt3(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x200000,21)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT3_MASK                 0x00200000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT3_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT3_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT3_SHIFT                21

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_urt2 [20:20] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_urt2(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x100000,20,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_urt2(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x100000,20)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT2_MASK                 0x00100000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT2_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT2_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT2_SHIFT                20

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_urt1 [19:19] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_urt1(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x80000,19,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_urt1(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x80000,19)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT1_MASK                 0x00080000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT1_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT1_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT1_SHIFT                19

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_urt0 [18:18] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_urt0(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x40000,18,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_urt0(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x40000,18)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT0_MASK                 0x00040000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT0_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT0_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_URT0_SHIFT                18

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_umc [17:17] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_umc(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x20000,17,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_umc(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x20000,17)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_UMC_MASK                  0x00020000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_UMC_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_UMC_BITS                  1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_UMC_SHIFT                 17

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_tpb [16:16] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tpb(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x10000,16,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tpb(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x10000,16)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TPB_MASK                  0x00010000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TPB_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TPB_BITS                  1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TPB_SHIFT                 16

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_tim4 [15:15] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim4(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x8000,15,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim4(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x8000,15)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM4_MASK                 0x00008000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM4_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM4_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM4_SHIFT                15

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_tim3 [14:14] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim3(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x4000,14,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim3(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x4000,14)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM3_MASK                 0x00004000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM3_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM3_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM3_SHIFT                14

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_tim2 [13:13] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim2(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x2000,13,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim2(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x2000,13)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM2_MASK                 0x00002000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM2_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM2_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM2_SHIFT                13

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_tim1 [12:12] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim1(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x1000,12,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim1(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x1000,12)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM1_MASK                 0x00001000
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM1_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM1_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM1_SHIFT                12

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_tim0 [11:11] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim0(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x800,11,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_tim0(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x800,11)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM0_MASK                 0x00000800
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM0_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM0_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_TIM0_SHIFT                11

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_spl [10:10] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_spl(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x400,10,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_spl(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x400,10)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPL_MASK                  0x00000400
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPL_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPL_BITS                  1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPL_SHIFT                 10

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_qspi [09:09] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_qspi(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x200,9,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_qspi(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x200,9)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_QSPI_MASK                 0x00000200
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_QSPI_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_QSPI_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_QSPI_SHIFT                9

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_spi2 [08:08] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_spi2(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x100,8,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_spi2(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x100,8)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI2_MASK                 0x00000100
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI2_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI2_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI2_SHIFT                8

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_spi1 [07:07] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_spi1(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x80,7,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_spi1(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x80,7)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI1_MASK                 0x00000080
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI1_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI1_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI1_SHIFT                7

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_spi0 [06:06] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_spi0(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x40,6,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_spi0(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x40,6)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI0_MASK                 0x00000040
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI0_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI0_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SPI0_SHIFT                6

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_smu [05:05] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_smu(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x20,5,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_smu(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x20,5)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SMU_MASK                  0x00000020
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SMU_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SMU_BITS                  1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SMU_SHIFT                 5

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_smc [04:04] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_smc(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x10,4,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_smc(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x10,4)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SMC_MASK                  0x00000010
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SMC_ALIGN                 0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SMC_BITS                  1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SMC_SHIFT                 4

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_sdma [03:03] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_sdma(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x8,3,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_sdma(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x8,3)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDMA_MASK                 0x00000008
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDMA_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDMA_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDMA_SHIFT                3

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_sdm1 [02:02] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_sdm1(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x4,2,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_sdm1(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x4,2)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDM1_MASK                 0x00000004
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDM1_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDM1_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDM1_SHIFT                2

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_sdm0 [01:01] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_sdm0(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x2,1,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_sdm0(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x2,1)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDM0_MASK                 0x00000002
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDM0_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDM0_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SDM0_SHIFT                1

/* DMU :: dmu_pwd_err_blk2 :: dmu_pwd_err_sci1 [00:00] */
#define Wr_DMU_dmu_pwd_err_blk2_dmu_pwd_err_sci1(x) WriteRegBits(DMU_DMU_PWD_ERR_BLK2,0x1,0,x)
#define Rd_DMU_dmu_pwd_err_blk2_dmu_pwd_err_sci1(x) ReadRegBits(DMU_DMU_PWD_ERR_BLK2,0x1,0)
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SCI1_MASK                 0x00000001
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SCI1_ALIGN                0
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SCI1_BITS                 1
#define DMU_DMU_PWD_ERR_BLK2_DMU_PWD_ERR_SCI1_SHIFT                0


/****************************************************************************
 * DMU :: dmu_pm2
 ***************************************************************************/
/* DMU :: dmu_pm2 :: pm_deepsleep_exit_timeout [31:00] */
#define Wr_DMU_dmu_pm2_pm_deepsleep_exit_timeout(x) WriteReg(DMU_DMU_PM2,x)
#define Rd_DMU_dmu_pm2_pm_deepsleep_exit_timeout(x) ReadReg(DMU_DMU_PM2)
#define DMU_DMU_PM2_PM_DEEPSLEEP_EXIT_TIMEOUT_MASK                 0xffffffff
#define DMU_DMU_PM2_PM_DEEPSLEEP_EXIT_TIMEOUT_ALIGN                0
#define DMU_DMU_PM2_PM_DEEPSLEEP_EXIT_TIMEOUT_BITS                 32
#define DMU_DMU_PM2_PM_DEEPSLEEP_EXIT_TIMEOUT_SHIFT                0


/****************************************************************************
 * bcm89530_sys_cfg_I2C
 ***************************************************************************/
/****************************************************************************
 * I2C :: BSCCS
 ***************************************************************************/
/* I2C :: BSCCS :: reserved0 [31:08] */
#define I2C_BSCCS_RESERVED0_MASK                                   0xffffff00
#define I2C_BSCCS_RESERVED0_ALIGN                                  0
#define I2C_BSCCS_RESERVED0_BITS                                   24
#define I2C_BSCCS_RESERVED0_SHIFT                                  8

/* I2C :: BSCCS :: SDA [07:07] */
#define Wr_I2C_BSCCS_SDA(x) WriteRegBits(I2C_BSCCS,0x80,7,x)
#define Rd_I2C_BSCCS_SDA(x) ReadRegBits(I2C_BSCCS,0x80,7)
#define I2C_BSCCS_SDA_MASK                                         0x00000080
#define I2C_BSCCS_SDA_ALIGN                                        0
#define I2C_BSCCS_SDA_BITS                                         1
#define I2C_BSCCS_SDA_SHIFT                                        7

/* I2C :: BSCCS :: SCL [06:06] */
#define Wr_I2C_BSCCS_SCL(x) WriteRegBits(I2C_BSCCS,0x40,6,x)
#define Rd_I2C_BSCCS_SCL(x) ReadRegBits(I2C_BSCCS,0x40,6)
#define I2C_BSCCS_SCL_MASK                                         0x00000040
#define I2C_BSCCS_SCL_ALIGN                                        0
#define I2C_BSCCS_SCL_BITS                                         1
#define I2C_BSCCS_SCL_SHIFT                                        6

/* I2C :: BSCCS :: BUSY [05:05] */
#define Wr_I2C_BSCCS_BUSY(x) WriteRegBits(I2C_BSCCS,0x20,5,x)
#define Rd_I2C_BSCCS_BUSY(x) ReadRegBits(I2C_BSCCS,0x20,5)
#define I2C_BSCCS_BUSY_MASK                                        0x00000020
#define I2C_BSCCS_BUSY_ALIGN                                       0
#define I2C_BSCCS_BUSY_BITS                                        1
#define I2C_BSCCS_BUSY_SHIFT                                       5

/* I2C :: BSCCS :: RDY [04:04] */
#define Wr_I2C_BSCCS_RDY(x) WriteRegBits(I2C_BSCCS,0x10,4,x)
#define Rd_I2C_BSCCS_RDY(x) ReadRegBits(I2C_BSCCS,0x10,4)
#define I2C_BSCCS_RDY_MASK                                         0x00000010
#define I2C_BSCCS_RDY_ALIGN                                        0
#define I2C_BSCCS_RDY_BITS                                         1
#define I2C_BSCCS_RDY_SHIFT                                        4

/* I2C :: BSCCS :: ACK [03:03] */
#define Wr_I2C_BSCCS_ACK(x) WriteRegBits(I2C_BSCCS,0x8,3,x)
#define Rd_I2C_BSCCS_ACK(x) ReadRegBits(I2C_BSCCS,0x8,3)
#define I2C_BSCCS_ACK_MASK                                         0x00000008
#define I2C_BSCCS_ACK_ALIGN                                        0
#define I2C_BSCCS_ACK_BITS                                         1
#define I2C_BSCCS_ACK_SHIFT                                        3

/* I2C :: BSCCS :: CMD [02:01] */
#define Wr_I2C_BSCCS_CMD(x) WriteRegBits(I2C_BSCCS,0x6,1,x)
#define Rd_I2C_BSCCS_CMD(x) ReadRegBits(I2C_BSCCS,0x6,1)
#define I2C_BSCCS_CMD_MASK                                         0x00000006
#define I2C_BSCCS_CMD_ALIGN                                        0
#define I2C_BSCCS_CMD_BITS                                         2
#define I2C_BSCCS_CMD_SHIFT                                        1

/* I2C :: BSCCS :: EN [00:00] */
#define Wr_I2C_BSCCS_EN(x) WriteRegBits(I2C_BSCCS,0x1,0,x)
#define Rd_I2C_BSCCS_EN(x) ReadRegBits(I2C_BSCCS,0x1,0)
#define I2C_BSCCS_EN_MASK                                          0x00000001
#define I2C_BSCCS_EN_ALIGN                                         0
#define I2C_BSCCS_EN_BITS                                          1
#define I2C_BSCCS_EN_SHIFT                                         0


/****************************************************************************
 * I2C :: BSCTIM
 ***************************************************************************/
/* I2C :: BSCTIM :: reserved0 [31:08] */
#define I2C_BSCTIM_RESERVED0_MASK                                  0xffffff00
#define I2C_BSCTIM_RESERVED0_ALIGN                                 0
#define I2C_BSCTIM_RESERVED0_BITS                                  24
#define I2C_BSCTIM_RESERVED0_SHIFT                                 8

/* I2C :: BSCTIM :: DEGLITCH_EN [07:07] */
#define Wr_I2C_BSCTIM_DEGLITCH_EN(x) WriteRegBits(I2C_BSCTIM,0x80,7,x)
#define Rd_I2C_BSCTIM_DEGLITCH_EN(x) ReadRegBits(I2C_BSCTIM,0x80,7)
#define I2C_BSCTIM_DEGLITCH_EN_MASK                                0x00000080
#define I2C_BSCTIM_DEGLITCH_EN_ALIGN                               0
#define I2C_BSCTIM_DEGLITCH_EN_BITS                                1
#define I2C_BSCTIM_DEGLITCH_EN_SHIFT                               7

/* I2C :: BSCTIM :: reserved1 [06:06] */
#define I2C_BSCTIM_RESERVED1_MASK                                  0x00000040
#define I2C_BSCTIM_RESERVED1_ALIGN                                 0
#define I2C_BSCTIM_RESERVED1_BITS                                  1
#define I2C_BSCTIM_RESERVED1_SHIFT                                 6

/* I2C :: BSCTIM :: P [05:03] */
#define Wr_I2C_BSCTIM_P(x) WriteRegBits(I2C_BSCTIM,0x38,3,x)
#define Rd_I2C_BSCTIM_P(x) ReadRegBits(I2C_BSCTIM,0x38,3)
#define I2C_BSCTIM_P_MASK                                          0x00000038
#define I2C_BSCTIM_P_ALIGN                                         0
#define I2C_BSCTIM_P_BITS                                          3
#define I2C_BSCTIM_P_SHIFT                                         3

/* I2C :: BSCTIM :: reserved2 [02:02] */
#define I2C_BSCTIM_RESERVED2_MASK                                  0x00000004
#define I2C_BSCTIM_RESERVED2_ALIGN                                 0
#define I2C_BSCTIM_RESERVED2_BITS                                  1
#define I2C_BSCTIM_RESERVED2_SHIFT                                 2

/* I2C :: BSCTIM :: DIV [01:00] */
#define Wr_I2C_BSCTIM_DIV(x) WriteRegBits(I2C_BSCTIM,0x3,0,x)
#define Rd_I2C_BSCTIM_DIV(x) ReadRegBits(I2C_BSCTIM,0x3,0)
#define I2C_BSCTIM_DIV_MASK                                        0x00000003
#define I2C_BSCTIM_DIV_ALIGN                                       0
#define I2C_BSCTIM_DIV_BITS                                        2
#define I2C_BSCTIM_DIV_SHIFT                                       0


/****************************************************************************
 * I2C :: BSCDAT
 ***************************************************************************/
/* I2C :: BSCDAT :: reserved0 [31:08] */
#define I2C_BSCDAT_RESERVED0_MASK                                  0xffffff00
#define I2C_BSCDAT_RESERVED0_ALIGN                                 0
#define I2C_BSCDAT_RESERVED0_BITS                                  24
#define I2C_BSCDAT_RESERVED0_SHIFT                                 8

/* I2C :: BSCDAT :: DAT [07:00] */
#define Wr_I2C_BSCDAT_DAT(x) WriteRegBits(I2C_BSCDAT,0xff,0,x)
#define Rd_I2C_BSCDAT_DAT(x) ReadRegBits(I2C_BSCDAT,0xff,0)
#define I2C_BSCDAT_DAT_MASK                                        0x000000ff
#define I2C_BSCDAT_DAT_ALIGN                                       0
#define I2C_BSCDAT_DAT_BITS                                        8
#define I2C_BSCDAT_DAT_SHIFT                                       0


/****************************************************************************
 * I2C :: BSCTOUT
 ***************************************************************************/
/* I2C :: BSCTOUT :: reserved0 [31:08] */
#define I2C_BSCTOUT_RESERVED0_MASK                                 0xffffff00
#define I2C_BSCTOUT_RESERVED0_ALIGN                                0
#define I2C_BSCTOUT_RESERVED0_BITS                                 24
#define I2C_BSCTOUT_RESERVED0_SHIFT                                8

/* I2C :: BSCTOUT :: TE [07:07] */
#define Wr_I2C_BSCTOUT_TE(x) WriteRegBits(I2C_BSCTOUT,0x80,7,x)
#define Rd_I2C_BSCTOUT_TE(x) ReadRegBits(I2C_BSCTOUT,0x80,7)
#define I2C_BSCTOUT_TE_MASK                                        0x00000080
#define I2C_BSCTOUT_TE_ALIGN                                       0
#define I2C_BSCTOUT_TE_BITS                                        1
#define I2C_BSCTOUT_TE_SHIFT                                       7

/* I2C :: BSCTOUT :: TOUT [06:00] */
#define Wr_I2C_BSCTOUT_TOUT(x) WriteRegBits(I2C_BSCTOUT,0x7f,0,x)
#define Rd_I2C_BSCTOUT_TOUT(x) ReadRegBits(I2C_BSCTOUT,0x7f,0)
#define I2C_BSCTOUT_TOUT_MASK                                      0x0000007f
#define I2C_BSCTOUT_TOUT_ALIGN                                     0
#define I2C_BSCTOUT_TOUT_BITS                                      7
#define I2C_BSCTOUT_TOUT_SHIFT                                     0


/****************************************************************************
 * I2C :: BSCFCR
 ***************************************************************************/
/* I2C :: BSCFCR :: reserved0 [31:08] */
#define I2C_BSCFCR_RESERVED0_MASK                                  0xffffff00
#define I2C_BSCFCR_RESERVED0_ALIGN                                 0
#define I2C_BSCFCR_RESERVED0_BITS                                  24
#define I2C_BSCFCR_RESERVED0_SHIFT                                 8

/* I2C :: BSCFCR :: Flush [07:07] */
#define Wr_I2C_BSCFCR_Flush(x) WriteRegBits(I2C_BSCFCR,0x80,7,x)
#define Rd_I2C_BSCFCR_Flush(x) ReadRegBits(I2C_BSCFCR,0x80,7)
#define I2C_BSCFCR_FLUSH_MASK                                      0x00000080
#define I2C_BSCFCR_FLUSH_ALIGN                                     0
#define I2C_BSCFCR_FLUSH_BITS                                      1
#define I2C_BSCFCR_FLUSH_SHIFT                                     7

/* I2C :: BSCFCR :: FIFOEN [06:06] */
#define Wr_I2C_BSCFCR_FIFOEN(x) WriteRegBits(I2C_BSCFCR,0x40,6,x)
#define Rd_I2C_BSCFCR_FIFOEN(x) ReadRegBits(I2C_BSCFCR,0x40,6)
#define I2C_BSCFCR_FIFOEN_MASK                                     0x00000040
#define I2C_BSCFCR_FIFOEN_ALIGN                                    0
#define I2C_BSCFCR_FIFOEN_BITS                                     1
#define I2C_BSCFCR_FIFOEN_SHIFT                                    6

/* I2C :: BSCFCR :: reserved1 [05:03] */
#define I2C_BSCFCR_RESERVED1_MASK                                  0x00000038
#define I2C_BSCFCR_RESERVED1_ALIGN                                 0
#define I2C_BSCFCR_RESERVED1_BITS                                  3
#define I2C_BSCFCR_RESERVED1_SHIFT                                 3

/* I2C :: BSCFCR :: FIFOCNT [02:00] */
#define Wr_I2C_BSCFCR_FIFOCNT(x) WriteRegBits(I2C_BSCFCR,0x7,0,x)
#define Rd_I2C_BSCFCR_FIFOCNT(x) ReadRegBits(I2C_BSCFCR,0x7,0)
#define I2C_BSCFCR_FIFOCNT_MASK                                    0x00000007
#define I2C_BSCFCR_FIFOCNT_ALIGN                                   0
#define I2C_BSCFCR_FIFOCNT_BITS                                    3
#define I2C_BSCFCR_FIFOCNT_SHIFT                                   0


/****************************************************************************
 * I2C :: BSCFIFORDOUT
 ***************************************************************************/
/* I2C :: BSCFIFORDOUT :: reserved0 [31:08] */
#define I2C_BSCFIFORDOUT_RESERVED0_MASK                            0xffffff00
#define I2C_BSCFIFORDOUT_RESERVED0_ALIGN                           0
#define I2C_BSCFIFORDOUT_RESERVED0_BITS                            24
#define I2C_BSCFIFORDOUT_RESERVED0_SHIFT                           8

/* I2C :: BSCFIFORDOUT :: FIFO_RDOUT [07:00] */
#define Wr_I2C_BSCFIFORDOUT_FIFO_RDOUT(x) WriteRegBits(I2C_BSCFIFORDOUT,0xff,0,x)
#define Rd_I2C_BSCFIFORDOUT_FIFO_RDOUT(x) ReadRegBits(I2C_BSCFIFORDOUT,0xff,0)
#define I2C_BSCFIFORDOUT_FIFO_RDOUT_MASK                           0x000000ff
#define I2C_BSCFIFORDOUT_FIFO_RDOUT_ALIGN                          0
#define I2C_BSCFIFORDOUT_FIFO_RDOUT_BITS                           8
#define I2C_BSCFIFORDOUT_FIFO_RDOUT_SHIFT                          0


/****************************************************************************
 * I2C :: BSCIER
 ***************************************************************************/
/* I2C :: BSCIER :: reserved0 [31:08] */
#define I2C_BSCIER_RESERVED0_MASK                                  0xffffff00
#define I2C_BSCIER_RESERVED0_ALIGN                                 0
#define I2C_BSCIER_RESERVED0_BITS                                  24
#define I2C_BSCIER_RESERVED0_SHIFT                                 8

/* I2C :: BSCIER :: CMD_RUN_INT_EN [07:07] */
#define Wr_I2C_BSCIER_CMD_RUN_INT_EN(x) WriteRegBits(I2C_BSCIER,0x80,7,x)
#define Rd_I2C_BSCIER_CMD_RUN_INT_EN(x) ReadRegBits(I2C_BSCIER,0x80,7)
#define I2C_BSCIER_CMD_RUN_INT_EN_MASK                             0x00000080
#define I2C_BSCIER_CMD_RUN_INT_EN_ALIGN                            0
#define I2C_BSCIER_CMD_RUN_INT_EN_BITS                             1
#define I2C_BSCIER_CMD_RUN_INT_EN_SHIFT                            7

/* I2C :: BSCIER :: reserved1 [06:04] */
#define I2C_BSCIER_RESERVED1_MASK                                  0x00000070
#define I2C_BSCIER_RESERVED1_ALIGN                                 0
#define I2C_BSCIER_RESERVED1_BITS                                  3
#define I2C_BSCIER_RESERVED1_SHIFT                                 4

/* I2C :: BSCIER :: BSC_INT_EN [03:03] */
#define Wr_I2C_BSCIER_BSC_INT_EN(x) WriteRegBits(I2C_BSCIER,0x8,3,x)
#define Rd_I2C_BSCIER_BSC_INT_EN(x) ReadRegBits(I2C_BSCIER,0x8,3)
#define I2C_BSCIER_BSC_INT_EN_MASK                                 0x00000008
#define I2C_BSCIER_BSC_INT_EN_ALIGN                                0
#define I2C_BSCIER_BSC_INT_EN_BITS                                 1
#define I2C_BSCIER_BSC_INT_EN_SHIFT                                3

/* I2C :: BSCIER :: ERRINT_EN [02:02] */
#define Wr_I2C_BSCIER_ERRINT_EN(x) WriteRegBits(I2C_BSCIER,0x4,2,x)
#define Rd_I2C_BSCIER_ERRINT_EN(x) ReadRegBits(I2C_BSCIER,0x4,2)
#define I2C_BSCIER_ERRINT_EN_MASK                                  0x00000004
#define I2C_BSCIER_ERRINT_EN_ALIGN                                 0
#define I2C_BSCIER_ERRINT_EN_BITS                                  1
#define I2C_BSCIER_ERRINT_EN_SHIFT                                 2

/* I2C :: BSCIER :: FIFOINT_EN [01:01] */
#define Wr_I2C_BSCIER_FIFOINT_EN(x) WriteRegBits(I2C_BSCIER,0x2,1,x)
#define Rd_I2C_BSCIER_FIFOINT_EN(x) ReadRegBits(I2C_BSCIER,0x2,1)
#define I2C_BSCIER_FIFOINT_EN_MASK                                 0x00000002
#define I2C_BSCIER_FIFOINT_EN_ALIGN                                0
#define I2C_BSCIER_FIFOINT_EN_BITS                                 1
#define I2C_BSCIER_FIFOINT_EN_SHIFT                                1

/* I2C :: BSCIER :: NOACK_EN [00:00] */
#define Wr_I2C_BSCIER_NOACK_EN(x) WriteRegBits(I2C_BSCIER,0x1,0,x)
#define Rd_I2C_BSCIER_NOACK_EN(x) ReadRegBits(I2C_BSCIER,0x1,0)
#define I2C_BSCIER_NOACK_EN_MASK                                   0x00000001
#define I2C_BSCIER_NOACK_EN_ALIGN                                  0
#define I2C_BSCIER_NOACK_EN_BITS                                   1
#define I2C_BSCIER_NOACK_EN_SHIFT                                  0


/****************************************************************************
 * I2C :: BSCISR
 ***************************************************************************/
/* I2C :: BSCISR :: reserved0 [31:08] */
#define I2C_BSCISR_RESERVED0_MASK                                  0xffffff00
#define I2C_BSCISR_RESERVED0_ALIGN                                 0
#define I2C_BSCISR_RESERVED0_BITS                                  24
#define I2C_BSCISR_RESERVED0_SHIFT                                 8

/* I2C :: BSCISR :: COMMAND_RUN [07:07] */
#define Wr_I2C_BSCISR_COMMAND_RUN(x) WriteRegBits(I2C_BSCISR,0x80,7,x)
#define Rd_I2C_BSCISR_COMMAND_RUN(x) ReadRegBits(I2C_BSCISR,0x80,7)
#define I2C_BSCISR_COMMAND_RUN_MASK                                0x00000080
#define I2C_BSCISR_COMMAND_RUN_ALIGN                               0
#define I2C_BSCISR_COMMAND_RUN_BITS                                1
#define I2C_BSCISR_COMMAND_RUN_SHIFT                               7

/* I2C :: BSCISR :: reserved1 [06:04] */
#define I2C_BSCISR_RESERVED1_MASK                                  0x00000070
#define I2C_BSCISR_RESERVED1_ALIGN                                 0
#define I2C_BSCISR_RESERVED1_BITS                                  3
#define I2C_BSCISR_RESERVED1_SHIFT                                 4

/* I2C :: BSCISR :: BSC_SES_DONE [03:03] */
#define Wr_I2C_BSCISR_BSC_SES_DONE(x) WriteRegBits(I2C_BSCISR,0x8,3,x)
#define Rd_I2C_BSCISR_BSC_SES_DONE(x) ReadRegBits(I2C_BSCISR,0x8,3)
#define I2C_BSCISR_BSC_SES_DONE_MASK                               0x00000008
#define I2C_BSCISR_BSC_SES_DONE_ALIGN                              0
#define I2C_BSCISR_BSC_SES_DONE_BITS                               1
#define I2C_BSCISR_BSC_SES_DONE_SHIFT                              3

/* I2C :: BSCISR :: BSCERR [02:02] */
#define Wr_I2C_BSCISR_BSCERR(x) WriteRegBits(I2C_BSCISR,0x4,2,x)
#define Rd_I2C_BSCISR_BSCERR(x) ReadRegBits(I2C_BSCISR,0x4,2)
#define I2C_BSCISR_BSCERR_MASK                                     0x00000004
#define I2C_BSCISR_BSCERR_ALIGN                                    0
#define I2C_BSCISR_BSCERR_BITS                                     1
#define I2C_BSCISR_BSCERR_SHIFT                                    2

/* I2C :: BSCISR :: TXFIFOEMPTY [01:01] */
#define Wr_I2C_BSCISR_TXFIFOEMPTY(x) WriteRegBits(I2C_BSCISR,0x2,1,x)
#define Rd_I2C_BSCISR_TXFIFOEMPTY(x) ReadRegBits(I2C_BSCISR,0x2,1)
#define I2C_BSCISR_TXFIFOEMPTY_MASK                                0x00000002
#define I2C_BSCISR_TXFIFOEMPTY_ALIGN                               0
#define I2C_BSCISR_TXFIFOEMPTY_BITS                                1
#define I2C_BSCISR_TXFIFOEMPTY_SHIFT                               1

/* I2C :: BSCISR :: NOACK [00:00] */
#define Wr_I2C_BSCISR_NOACK(x) WriteRegBits(I2C_BSCISR,0x1,0,x)
#define Rd_I2C_BSCISR_NOACK(x) ReadRegBits(I2C_BSCISR,0x1,0)
#define I2C_BSCISR_NOACK_MASK                                      0x00000001
#define I2C_BSCISR_NOACK_ALIGN                                     0
#define I2C_BSCISR_NOACK_BITS                                      1
#define I2C_BSCISR_NOACK_SHIFT                                     0


/****************************************************************************
 * I2C :: BSCCLKEN
 ***************************************************************************/
/* I2C :: BSCCLKEN :: reserved0 [31:08] */
#define I2C_BSCCLKEN_RESERVED0_MASK                                0xffffff00
#define I2C_BSCCLKEN_RESERVED0_ALIGN                               0
#define I2C_BSCCLKEN_RESERVED0_BITS                                24
#define I2C_BSCCLKEN_RESERVED0_SHIFT                               8

/* I2C :: BSCCLKEN :: AUTO_SENSE [07:07] */
#define Wr_I2C_BSCCLKEN_AUTO_SENSE(x) WriteRegBits(I2C_BSCCLKEN,0x80,7,x)
#define Rd_I2C_BSCCLKEN_AUTO_SENSE(x) ReadRegBits(I2C_BSCCLKEN,0x80,7)
#define I2C_BSCCLKEN_AUTO_SENSE_MASK                               0x00000080
#define I2C_BSCCLKEN_AUTO_SENSE_ALIGN                              0
#define I2C_BSCCLKEN_AUTO_SENSE_BITS                               1
#define I2C_BSCCLKEN_AUTO_SENSE_SHIFT                              7

/* I2C :: BSCCLKEN :: MPHASE [06:04] */
#define Wr_I2C_BSCCLKEN_MPHASE(x) WriteRegBits(I2C_BSCCLKEN,0x70,4,x)
#define Rd_I2C_BSCCLKEN_MPHASE(x) ReadRegBits(I2C_BSCCLKEN,0x70,4)
#define I2C_BSCCLKEN_MPHASE_MASK                                   0x00000070
#define I2C_BSCCLKEN_MPHASE_ALIGN                                  0
#define I2C_BSCCLKEN_MPHASE_BITS                                   3
#define I2C_BSCCLKEN_MPHASE_SHIFT                                  4

/* I2C :: BSCCLKEN :: NPHASE [03:01] */
#define Wr_I2C_BSCCLKEN_NPHASE(x) WriteRegBits(I2C_BSCCLKEN,0xe,1,x)
#define Rd_I2C_BSCCLKEN_NPHASE(x) ReadRegBits(I2C_BSCCLKEN,0xe,1)
#define I2C_BSCCLKEN_NPHASE_MASK                                   0x0000000e
#define I2C_BSCCLKEN_NPHASE_ALIGN                                  0
#define I2C_BSCCLKEN_NPHASE_BITS                                   3
#define I2C_BSCCLKEN_NPHASE_SHIFT                                  1

/* I2C :: BSCCLKEN :: CLKEN [00:00] */
#define Wr_I2C_BSCCLKEN_CLKEN(x) WriteRegBits(I2C_BSCCLKEN,0x1,0,x)
#define Rd_I2C_BSCCLKEN_CLKEN(x) ReadRegBits(I2C_BSCCLKEN,0x1,0)
#define I2C_BSCCLKEN_CLKEN_MASK                                    0x00000001
#define I2C_BSCCLKEN_CLKEN_ALIGN                                   0
#define I2C_BSCCLKEN_CLKEN_BITS                                    1
#define I2C_BSCCLKEN_CLKEN_SHIFT                                   0


/****************************************************************************
 * bcm89530_sys_cfg_CFG
 ***************************************************************************/
/****************************************************************************
 * CFG :: SR
 ***************************************************************************/
/* CFG :: SR :: reserved0 [31:12] */
#define CFG_SR_RESERVED0_MASK                                      0xfffff000
#define CFG_SR_RESERVED0_ALIGN                                     0
#define CFG_SR_RESERVED0_BITS                                      20
#define CFG_SR_RESERVED0_SHIFT                                     12

/* CFG :: SR :: MEM_INIT_DONE [11:11] */
#define Wr_CFG_SR_MEM_INIT_DONE(x) WriteRegBits(CFG_SR,0x800,11,x)
#define Rd_CFG_SR_MEM_INIT_DONE(x) ReadRegBits(CFG_SR,0x800,11)
#define CFG_SR_MEM_INIT_DONE_MASK                                  0x00000800
#define CFG_SR_MEM_INIT_DONE_ALIGN                                 0
#define CFG_SR_MEM_INIT_DONE_BITS                                  1
#define CFG_SR_MEM_INIT_DONE_SHIFT                                 11

/* CFG :: SR :: ENG_BOOT [10:10] */
#define Wr_CFG_SR_ENG_BOOT(x) WriteRegBits(CFG_SR,0x400,10,x)
#define Rd_CFG_SR_ENG_BOOT(x) ReadRegBits(CFG_SR,0x400,10)
#define CFG_SR_ENG_BOOT_MASK                                       0x00000400
#define CFG_SR_ENG_BOOT_ALIGN                                      0
#define CFG_SR_ENG_BOOT_BITS                                       1
#define CFG_SR_ENG_BOOT_SHIFT                                      10

/* CFG :: SR :: SEC_BOOT [09:09] */
#define Wr_CFG_SR_SEC_BOOT(x) WriteRegBits(CFG_SR,0x200,9,x)
#define Rd_CFG_SR_SEC_BOOT(x) ReadRegBits(CFG_SR,0x200,9)
#define CFG_SR_SEC_BOOT_MASK                                       0x00000200
#define CFG_SR_SEC_BOOT_ALIGN                                      0
#define CFG_SR_SEC_BOOT_BITS                                       1
#define CFG_SR_SEC_BOOT_SHIFT                                      9

/* CFG :: SR :: JTAG_OTP_READY [08:08] */
#define Wr_CFG_SR_JTAG_OTP_READY(x) WriteRegBits(CFG_SR,0x100,8,x)
#define Rd_CFG_SR_JTAG_OTP_READY(x) ReadRegBits(CFG_SR,0x100,8)
#define CFG_SR_JTAG_OTP_READY_MASK                                 0x00000100
#define CFG_SR_JTAG_OTP_READY_ALIGN                                0
#define CFG_SR_JTAG_OTP_READY_BITS                                 1
#define CFG_SR_JTAG_OTP_READY_SHIFT                                8

/* CFG :: SR :: reserved1 [07:03] */
#define CFG_SR_RESERVED1_MASK                                      0x000000f8
#define CFG_SR_RESERVED1_ALIGN                                     0
#define CFG_SR_RESERVED1_BITS                                      5
#define CFG_SR_RESERVED1_SHIFT                                     3

/* CFG :: SR :: UK_RCVED [02:02] */
#define Wr_CFG_SR_UK_RCVED(x) WriteRegBits(CFG_SR,0x4,2,x)
#define Rd_CFG_SR_UK_RCVED(x) ReadRegBits(CFG_SR,0x4,2)
#define CFG_SR_UK_RCVED_MASK                                       0x00000004
#define CFG_SR_UK_RCVED_ALIGN                                      0
#define CFG_SR_UK_RCVED_BITS                                       1
#define CFG_SR_UK_RCVED_SHIFT                                      2

/* CFG :: SR :: JTAG_UNLOCK [01:01] */
#define Wr_CFG_SR_JTAG_UNLOCK(x) WriteRegBits(CFG_SR,0x2,1,x)
#define Rd_CFG_SR_JTAG_UNLOCK(x) ReadRegBits(CFG_SR,0x2,1)
#define CFG_SR_JTAG_UNLOCK_MASK                                    0x00000002
#define CFG_SR_JTAG_UNLOCK_ALIGN                                   0
#define CFG_SR_JTAG_UNLOCK_BITS                                    1
#define CFG_SR_JTAG_UNLOCK_SHIFT                                   1

/* CFG :: SR :: OTP_BIT [00:00] */
#define Wr_CFG_SR_OTP_BIT(x) WriteRegBits(CFG_SR,0x1,0,x)
#define Rd_CFG_SR_OTP_BIT(x) ReadRegBits(CFG_SR,0x1,0)
#define CFG_SR_OTP_BIT_MASK                                        0x00000001
#define CFG_SR_OTP_BIT_ALIGN                                       0
#define CFG_SR_OTP_BIT_BITS                                        1
#define CFG_SR_OTP_BIT_SHIFT                                       0


/****************************************************************************
 * CFG :: CFG_CPUSYS_MISC
 ***************************************************************************/
/* CFG :: CFG_CPUSYS_MISC :: spare_reg [31:23] */
#define Wr_CFG_CFG_CPUSYS_MISC_spare_reg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0xff800000,23,x)
#define Rd_CFG_CFG_CPUSYS_MISC_spare_reg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0xff800000,23)
#define CFG_CFG_CPUSYS_MISC_SPARE_REG_MASK                         0xff800000
#define CFG_CFG_CPUSYS_MISC_SPARE_REG_ALIGN                        0
#define CFG_CFG_CPUSYS_MISC_SPARE_REG_BITS                         9
#define CFG_CFG_CPUSYS_MISC_SPARE_REG_SHIFT                        23

/* CFG :: CFG_CPUSYS_MISC :: SPEED_UP_MEM_INIT_cfg [22:22] */
#define Wr_CFG_CFG_CPUSYS_MISC_SPEED_UP_MEM_INIT_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x400000,22,x)
#define Rd_CFG_CFG_CPUSYS_MISC_SPEED_UP_MEM_INIT_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x400000,22)
#define CFG_CFG_CPUSYS_MISC_SPEED_UP_MEM_INIT_CFG_MASK             0x00400000
#define CFG_CFG_CPUSYS_MISC_SPEED_UP_MEM_INIT_CFG_ALIGN            0
#define CFG_CFG_CPUSYS_MISC_SPEED_UP_MEM_INIT_CFG_BITS             1
#define CFG_CFG_CPUSYS_MISC_SPEED_UP_MEM_INIT_CFG_SHIFT            22

/* CFG :: CFG_CPUSYS_MISC :: SER_ACCESS_CTRL_cfg [21:21] */
#define Wr_CFG_CFG_CPUSYS_MISC_SER_ACCESS_CTRL_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x200000,21,x)
#define Rd_CFG_CFG_CPUSYS_MISC_SER_ACCESS_CTRL_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x200000,21)
#define CFG_CFG_CPUSYS_MISC_SER_ACCESS_CTRL_CFG_MASK               0x00200000
#define CFG_CFG_CPUSYS_MISC_SER_ACCESS_CTRL_CFG_ALIGN              0
#define CFG_CFG_CPUSYS_MISC_SER_ACCESS_CTRL_CFG_BITS               1
#define CFG_CFG_CPUSYS_MISC_SER_ACCESS_CTRL_CFG_SHIFT              21

/* CFG :: CFG_CPUSYS_MISC :: WR_PROTECT_ROM_cfg [20:20] */
#define Wr_CFG_CFG_CPUSYS_MISC_WR_PROTECT_ROM_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x100000,20,x)
#define Rd_CFG_CFG_CPUSYS_MISC_WR_PROTECT_ROM_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x100000,20)
#define CFG_CFG_CPUSYS_MISC_WR_PROTECT_ROM_CFG_MASK                0x00100000
#define CFG_CFG_CPUSYS_MISC_WR_PROTECT_ROM_CFG_ALIGN               0
#define CFG_CFG_CPUSYS_MISC_WR_PROTECT_ROM_CFG_BITS                1
#define CFG_CFG_CPUSYS_MISC_WR_PROTECT_ROM_CFG_SHIFT               20

/* CFG :: CFG_CPUSYS_MISC :: SLBTCMSB_cfg [19:19] */
#define Wr_CFG_CFG_CPUSYS_MISC_SLBTCMSB_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x80000,19,x)
#define Rd_CFG_CFG_CPUSYS_MISC_SLBTCMSB_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x80000,19)
#define CFG_CFG_CPUSYS_MISC_SLBTCMSB_CFG_MASK                      0x00080000
#define CFG_CFG_CPUSYS_MISC_SLBTCMSB_CFG_ALIGN                     0
#define CFG_CFG_CPUSYS_MISC_SLBTCMSB_CFG_BITS                      1
#define CFG_CFG_CPUSYS_MISC_SLBTCMSB_CFG_SHIFT                     19

/* CFG :: CFG_CPUSYS_MISC :: PARECCENRAM_cfg [18:16] */
#define Wr_CFG_CFG_CPUSYS_MISC_PARECCENRAM_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x70000,16,x)
#define Rd_CFG_CFG_CPUSYS_MISC_PARECCENRAM_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x70000,16)
#define CFG_CFG_CPUSYS_MISC_PARECCENRAM_CFG_MASK                   0x00070000
#define CFG_CFG_CPUSYS_MISC_PARECCENRAM_CFG_ALIGN                  0
#define CFG_CFG_CPUSYS_MISC_PARECCENRAM_CFG_BITS                   3
#define CFG_CFG_CPUSYS_MISC_PARECCENRAM_CFG_SHIFT                  16

/* CFG :: CFG_CPUSYS_MISC :: CFGBTCMSZ_cfg [15:12] */
#define Wr_CFG_CFG_CPUSYS_MISC_CFGBTCMSZ_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0xf000,12,x)
#define Rd_CFG_CFG_CPUSYS_MISC_CFGBTCMSZ_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0xf000,12)
#define CFG_CFG_CPUSYS_MISC_CFGBTCMSZ_CFG_MASK                     0x0000f000
#define CFG_CFG_CPUSYS_MISC_CFGBTCMSZ_CFG_ALIGN                    0
#define CFG_CFG_CPUSYS_MISC_CFGBTCMSZ_CFG_BITS                     4
#define CFG_CFG_CPUSYS_MISC_CFGBTCMSZ_CFG_SHIFT                    12

/* CFG :: CFG_CPUSYS_MISC :: CFGATCMSZ_cfg [11:08] */
#define Wr_CFG_CFG_CPUSYS_MISC_CFGATCMSZ_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0xf00,8,x)
#define Rd_CFG_CFG_CPUSYS_MISC_CFGATCMSZ_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0xf00,8)
#define CFG_CFG_CPUSYS_MISC_CFGATCMSZ_CFG_MASK                     0x00000f00
#define CFG_CFG_CPUSYS_MISC_CFGATCMSZ_CFG_ALIGN                    0
#define CFG_CFG_CPUSYS_MISC_CFGATCMSZ_CFG_BITS                     4
#define CFG_CFG_CPUSYS_MISC_CFGATCMSZ_CFG_SHIFT                    8

/* CFG :: CFG_CPUSYS_MISC :: LOCZRAMA_cfg [07:07] */
#define Wr_CFG_CFG_CPUSYS_MISC_LOCZRAMA_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x80,7,x)
#define Rd_CFG_CFG_CPUSYS_MISC_LOCZRAMA_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x80,7)
#define CFG_CFG_CPUSYS_MISC_LOCZRAMA_CFG_MASK                      0x00000080
#define CFG_CFG_CPUSYS_MISC_LOCZRAMA_CFG_ALIGN                     0
#define CFG_CFG_CPUSYS_MISC_LOCZRAMA_CFG_BITS                      1
#define CFG_CFG_CPUSYS_MISC_LOCZRAMA_CFG_SHIFT                     7

/* CFG :: CFG_CPUSYS_MISC :: VINITHI_cfg [06:06] */
#define Wr_CFG_CFG_CPUSYS_MISC_VINITHI_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x40,6,x)
#define Rd_CFG_CFG_CPUSYS_MISC_VINITHI_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x40,6)
#define CFG_CFG_CPUSYS_MISC_VINITHI_CFG_MASK                       0x00000040
#define CFG_CFG_CPUSYS_MISC_VINITHI_CFG_ALIGN                      0
#define CFG_CFG_CPUSYS_MISC_VINITHI_CFG_BITS                       1
#define CFG_CFG_CPUSYS_MISC_VINITHI_CFG_SHIFT                      6

/* CFG :: CFG_CPUSYS_MISC :: nCPUHALT_ov [05:05] */
#define Wr_CFG_CFG_CPUSYS_MISC_nCPUHALT_ov(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x20,5,x)
#define Rd_CFG_CFG_CPUSYS_MISC_nCPUHALT_ov(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x20,5)
#define CFG_CFG_CPUSYS_MISC_NCPUHALT_OV_MASK                       0x00000020
#define CFG_CFG_CPUSYS_MISC_NCPUHALT_OV_ALIGN                      0
#define CFG_CFG_CPUSYS_MISC_NCPUHALT_OV_BITS                       1
#define CFG_CFG_CPUSYS_MISC_NCPUHALT_OV_SHIFT                      5

/* CFG :: CFG_CPUSYS_MISC :: nCPUHALT_cfg [04:04] */
#define Wr_CFG_CFG_CPUSYS_MISC_nCPUHALT_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x10,4,x)
#define Rd_CFG_CFG_CPUSYS_MISC_nCPUHALT_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x10,4)
#define CFG_CFG_CPUSYS_MISC_NCPUHALT_CFG_MASK                      0x00000010
#define CFG_CFG_CPUSYS_MISC_NCPUHALT_CFG_ALIGN                     0
#define CFG_CFG_CPUSYS_MISC_NCPUHALT_CFG_BITS                      1
#define CFG_CFG_CPUSYS_MISC_NCPUHALT_CFG_SHIFT                     4

/* CFG :: CFG_CPUSYS_MISC :: nRESET_ov [03:03] */
#define Wr_CFG_CFG_CPUSYS_MISC_nRESET_ov(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x8,3,x)
#define Rd_CFG_CFG_CPUSYS_MISC_nRESET_ov(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x8,3)
#define CFG_CFG_CPUSYS_MISC_NRESET_OV_MASK                         0x00000008
#define CFG_CFG_CPUSYS_MISC_NRESET_OV_ALIGN                        0
#define CFG_CFG_CPUSYS_MISC_NRESET_OV_BITS                         1
#define CFG_CFG_CPUSYS_MISC_NRESET_OV_SHIFT                        3

/* CFG :: CFG_CPUSYS_MISC :: nRESET_cfg [02:02] */
#define Wr_CFG_CFG_CPUSYS_MISC_nRESET_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x4,2,x)
#define Rd_CFG_CFG_CPUSYS_MISC_nRESET_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x4,2)
#define CFG_CFG_CPUSYS_MISC_NRESET_CFG_MASK                        0x00000004
#define CFG_CFG_CPUSYS_MISC_NRESET_CFG_ALIGN                       0
#define CFG_CFG_CPUSYS_MISC_NRESET_CFG_BITS                        1
#define CFG_CFG_CPUSYS_MISC_NRESET_CFG_SHIFT                       2

/* CFG :: CFG_CPUSYS_MISC :: nSYSPORESET_ov [01:01] */
#define Wr_CFG_CFG_CPUSYS_MISC_nSYSPORESET_ov(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x2,1,x)
#define Rd_CFG_CFG_CPUSYS_MISC_nSYSPORESET_ov(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x2,1)
#define CFG_CFG_CPUSYS_MISC_NSYSPORESET_OV_MASK                    0x00000002
#define CFG_CFG_CPUSYS_MISC_NSYSPORESET_OV_ALIGN                   0
#define CFG_CFG_CPUSYS_MISC_NSYSPORESET_OV_BITS                    1
#define CFG_CFG_CPUSYS_MISC_NSYSPORESET_OV_SHIFT                   1

/* CFG :: CFG_CPUSYS_MISC :: nSYSPORESET_cfg [00:00] */
#define Wr_CFG_CFG_CPUSYS_MISC_nSYSPORESET_cfg(x) WriteRegBits(CFG_CFG_CPUSYS_MISC,0x1,0,x)
#define Rd_CFG_CFG_CPUSYS_MISC_nSYSPORESET_cfg(x) ReadRegBits(CFG_CFG_CPUSYS_MISC,0x1,0)
#define CFG_CFG_CPUSYS_MISC_NSYSPORESET_CFG_MASK                   0x00000001
#define CFG_CFG_CPUSYS_MISC_NSYSPORESET_CFG_ALIGN                  0
#define CFG_CFG_CPUSYS_MISC_NSYSPORESET_CFG_BITS                   1
#define CFG_CFG_CPUSYS_MISC_NSYSPORESET_CFG_SHIFT                  0


/****************************************************************************
 * CFG :: TM_0
 ***************************************************************************/
/* CFG :: TM_0 :: reserved0 [31:16] */
#define CFG_TM_0_RESERVED0_MASK                                    0xffff0000
#define CFG_TM_0_RESERVED0_ALIGN                                   0
#define CFG_TM_0_RESERVED0_BITS                                    16
#define CFG_TM_0_RESERVED0_SHIFT                                   16

/* CFG :: TM_0 :: CFG_ALL_TM [15:00] */
#define Wr_CFG_TM_0_CFG_ALL_TM(x) WriteRegBits(CFG_TM_0,0xffff,0,x)
#define Rd_CFG_TM_0_CFG_ALL_TM(x) ReadRegBits(CFG_TM_0,0xffff,0)
#define CFG_TM_0_CFG_ALL_TM_MASK                                   0x0000ffff
#define CFG_TM_0_CFG_ALL_TM_ALIGN                                  0
#define CFG_TM_0_CFG_ALL_TM_BITS                                   16
#define CFG_TM_0_CFG_ALL_TM_SHIFT                                  0


/****************************************************************************
 * CFG :: TM_1
 ***************************************************************************/
/* CFG :: TM_1 :: CFG_TM1 [31:00] */
#define Wr_CFG_TM_1_CFG_TM1(x) WriteReg(CFG_TM_1,x)
#define Rd_CFG_TM_1_CFG_TM1(x) ReadReg(CFG_TM_1)
#define CFG_TM_1_CFG_TM1_MASK                                      0xffffffff
#define CFG_TM_1_CFG_TM1_ALIGN                                     0
#define CFG_TM_1_CFG_TM1_BITS                                      32
#define CFG_TM_1_CFG_TM1_SHIFT                                     0


/****************************************************************************
 * CFG :: DEBUG_EN
 ***************************************************************************/
/* CFG :: DEBUG_EN :: reserved0 [31:01] */
#define CFG_DEBUG_EN_RESERVED0_MASK                                0xfffffffe
#define CFG_DEBUG_EN_RESERVED0_ALIGN                               0
#define CFG_DEBUG_EN_RESERVED0_BITS                                31
#define CFG_DEBUG_EN_RESERVED0_SHIFT                               1

/* CFG :: DEBUG_EN :: jtagice_enable [00:00] */
#define Wr_CFG_DEBUG_EN_jtagice_enable(x) WriteRegBits(CFG_DEBUG_EN,0x1,0,x)
#define Rd_CFG_DEBUG_EN_jtagice_enable(x) ReadRegBits(CFG_DEBUG_EN,0x1,0)
#define CFG_DEBUG_EN_JTAGICE_ENABLE_MASK                           0x00000001
#define CFG_DEBUG_EN_JTAGICE_ENABLE_ALIGN                          0
#define CFG_DEBUG_EN_JTAGICE_ENABLE_BITS                           1
#define CFG_DEBUG_EN_JTAGICE_ENABLE_SHIFT                          0


/****************************************************************************
 * CFG :: PARITY_DISABLE
 ***************************************************************************/
/* CFG :: PARITY_DISABLE :: reserved0 [31:05] */
#define CFG_PARITY_DISABLE_RESERVED0_MASK                          0xffffffe0
#define CFG_PARITY_DISABLE_RESERVED0_ALIGN                         0
#define CFG_PARITY_DISABLE_RESERVED0_BITS                          27
#define CFG_PARITY_DISABLE_RESERVED0_SHIFT                         5

/* CFG :: PARITY_DISABLE :: axi2ahb_enh_dis [04:04] */
#define Wr_CFG_PARITY_DISABLE_axi2ahb_enh_dis(x) WriteRegBits(CFG_PARITY_DISABLE,0x10,4,x)
#define Rd_CFG_PARITY_DISABLE_axi2ahb_enh_dis(x) ReadRegBits(CFG_PARITY_DISABLE,0x10,4)
#define CFG_PARITY_DISABLE_AXI2AHB_ENH_DIS_MASK                    0x00000010
#define CFG_PARITY_DISABLE_AXI2AHB_ENH_DIS_ALIGN                   0
#define CFG_PARITY_DISABLE_AXI2AHB_ENH_DIS_BITS                    1
#define CFG_PARITY_DISABLE_AXI2AHB_ENH_DIS_SHIFT                   4

/* CFG :: PARITY_DISABLE :: reserved1 [03:03] */
#define CFG_PARITY_DISABLE_RESERVED1_MASK                          0x00000008
#define CFG_PARITY_DISABLE_RESERVED1_ALIGN                         0
#define CFG_PARITY_DISABLE_RESERVED1_BITS                          1
#define CFG_PARITY_DISABLE_RESERVED1_SHIFT                         3

/* CFG :: PARITY_DISABLE :: arm_ecc_disable [02:02] */
#define Wr_CFG_PARITY_DISABLE_arm_ecc_disable(x) WriteRegBits(CFG_PARITY_DISABLE,0x4,2,x)
#define Rd_CFG_PARITY_DISABLE_arm_ecc_disable(x) ReadRegBits(CFG_PARITY_DISABLE,0x4,2)
#define CFG_PARITY_DISABLE_ARM_ECC_DISABLE_MASK                    0x00000004
#define CFG_PARITY_DISABLE_ARM_ECC_DISABLE_ALIGN                   0
#define CFG_PARITY_DISABLE_ARM_ECC_DISABLE_BITS                    1
#define CFG_PARITY_DISABLE_ARM_ECC_DISABLE_SHIFT                   2

/* CFG :: PARITY_DISABLE :: mem_ecc_disable [01:01] */
#define Wr_CFG_PARITY_DISABLE_mem_ecc_disable(x) WriteRegBits(CFG_PARITY_DISABLE,0x2,1,x)
#define Rd_CFG_PARITY_DISABLE_mem_ecc_disable(x) ReadRegBits(CFG_PARITY_DISABLE,0x2,1)
#define CFG_PARITY_DISABLE_MEM_ECC_DISABLE_MASK                    0x00000002
#define CFG_PARITY_DISABLE_MEM_ECC_DISABLE_ALIGN                   0
#define CFG_PARITY_DISABLE_MEM_ECC_DISABLE_BITS                    1
#define CFG_PARITY_DISABLE_MEM_ECC_DISABLE_SHIFT                   1

/* CFG :: PARITY_DISABLE :: Usb_Parity_Disable [00:00] */
#define Wr_CFG_PARITY_DISABLE_Usb_Parity_Disable(x) WriteRegBits(CFG_PARITY_DISABLE,0x1,0,x)
#define Rd_CFG_PARITY_DISABLE_Usb_Parity_Disable(x) ReadRegBits(CFG_PARITY_DISABLE,0x1,0)
#define CFG_PARITY_DISABLE_USB_PARITY_DISABLE_MASK                 0x00000001
#define CFG_PARITY_DISABLE_USB_PARITY_DISABLE_ALIGN                0
#define CFG_PARITY_DISABLE_USB_PARITY_DISABLE_BITS                 1
#define CFG_PARITY_DISABLE_USB_PARITY_DISABLE_SHIFT                0


/****************************************************************************
 * CFG :: SRAB_CMDSTAT
 ***************************************************************************/
/* CFG :: SRAB_CMDSTAT :: sra_page [31:24] */
#define Wr_CFG_SRAB_CMDSTAT_sra_page(x) WriteRegBits(CFG_SRAB_CMDSTAT,0xff000000,24,x)
#define Rd_CFG_SRAB_CMDSTAT_sra_page(x) ReadRegBits(CFG_SRAB_CMDSTAT,0xff000000,24)
#define CFG_SRAB_CMDSTAT_SRA_PAGE_MASK                             0xff000000
#define CFG_SRAB_CMDSTAT_SRA_PAGE_ALIGN                            0
#define CFG_SRAB_CMDSTAT_SRA_PAGE_BITS                             8
#define CFG_SRAB_CMDSTAT_SRA_PAGE_SHIFT                            24

/* CFG :: SRAB_CMDSTAT :: sra_offset [23:16] */
#define Wr_CFG_SRAB_CMDSTAT_sra_offset(x) WriteRegBits(CFG_SRAB_CMDSTAT,0xff0000,16,x)
#define Rd_CFG_SRAB_CMDSTAT_sra_offset(x) ReadRegBits(CFG_SRAB_CMDSTAT,0xff0000,16)
#define CFG_SRAB_CMDSTAT_SRA_OFFSET_MASK                           0x00ff0000
#define CFG_SRAB_CMDSTAT_SRA_OFFSET_ALIGN                          0
#define CFG_SRAB_CMDSTAT_SRA_OFFSET_BITS                           8
#define CFG_SRAB_CMDSTAT_SRA_OFFSET_SHIFT                          16

/* CFG :: SRAB_CMDSTAT :: reserved0 [15:03] */
#define CFG_SRAB_CMDSTAT_RESERVED0_MASK                            0x0000fff8
#define CFG_SRAB_CMDSTAT_RESERVED0_ALIGN                           0
#define CFG_SRAB_CMDSTAT_RESERVED0_BITS                            13
#define CFG_SRAB_CMDSTAT_RESERVED0_SHIFT                           3

/* CFG :: SRAB_CMDSTAT :: sra_rst [02:02] */
#define Wr_CFG_SRAB_CMDSTAT_sra_rst(x) WriteRegBits(CFG_SRAB_CMDSTAT,0x4,2,x)
#define Rd_CFG_SRAB_CMDSTAT_sra_rst(x) ReadRegBits(CFG_SRAB_CMDSTAT,0x4,2)
#define CFG_SRAB_CMDSTAT_SRA_RST_MASK                              0x00000004
#define CFG_SRAB_CMDSTAT_SRA_RST_ALIGN                             0
#define CFG_SRAB_CMDSTAT_SRA_RST_BITS                              1
#define CFG_SRAB_CMDSTAT_SRA_RST_SHIFT                             2

/* CFG :: SRAB_CMDSTAT :: sra_write [01:01] */
#define Wr_CFG_SRAB_CMDSTAT_sra_write(x) WriteRegBits(CFG_SRAB_CMDSTAT,0x2,1,x)
#define Rd_CFG_SRAB_CMDSTAT_sra_write(x) ReadRegBits(CFG_SRAB_CMDSTAT,0x2,1)
#define CFG_SRAB_CMDSTAT_SRA_WRITE_MASK                            0x00000002
#define CFG_SRAB_CMDSTAT_SRA_WRITE_ALIGN                           0
#define CFG_SRAB_CMDSTAT_SRA_WRITE_BITS                            1
#define CFG_SRAB_CMDSTAT_SRA_WRITE_SHIFT                           1

/* CFG :: SRAB_CMDSTAT :: sra_gordyn [00:00] */
#define Wr_CFG_SRAB_CMDSTAT_sra_gordyn(x) WriteRegBits(CFG_SRAB_CMDSTAT,0x1,0,x)
#define Rd_CFG_SRAB_CMDSTAT_sra_gordyn(x) ReadRegBits(CFG_SRAB_CMDSTAT,0x1,0)
#define CFG_SRAB_CMDSTAT_SRA_GORDYN_MASK                           0x00000001
#define CFG_SRAB_CMDSTAT_SRA_GORDYN_ALIGN                          0
#define CFG_SRAB_CMDSTAT_SRA_GORDYN_BITS                           1
#define CFG_SRAB_CMDSTAT_SRA_GORDYN_SHIFT                          0


/****************************************************************************
 * CFG :: SRAB_WDH
 ***************************************************************************/
/* CFG :: SRAB_WDH :: sr_wdata_h [31:00] */
#define Wr_CFG_SRAB_WDH_sr_wdata_h(x) WriteReg(CFG_SRAB_WDH,x)
#define Rd_CFG_SRAB_WDH_sr_wdata_h(x) ReadReg(CFG_SRAB_WDH)
#define CFG_SRAB_WDH_SR_WDATA_H_MASK                               0xffffffff
#define CFG_SRAB_WDH_SR_WDATA_H_ALIGN                              0
#define CFG_SRAB_WDH_SR_WDATA_H_BITS                               32
#define CFG_SRAB_WDH_SR_WDATA_H_SHIFT                              0


/****************************************************************************
 * CFG :: SRAB_WDL
 ***************************************************************************/
/* CFG :: SRAB_WDL :: sr_wdata_l [31:00] */
#define Wr_CFG_SRAB_WDL_sr_wdata_l(x) WriteReg(CFG_SRAB_WDL,x)
#define Rd_CFG_SRAB_WDL_sr_wdata_l(x) ReadReg(CFG_SRAB_WDL)
#define CFG_SRAB_WDL_SR_WDATA_L_MASK                               0xffffffff
#define CFG_SRAB_WDL_SR_WDATA_L_ALIGN                              0
#define CFG_SRAB_WDL_SR_WDATA_L_BITS                               32
#define CFG_SRAB_WDL_SR_WDATA_L_SHIFT                              0


/****************************************************************************
 * CFG :: SRAB_RDH
 ***************************************************************************/
/* CFG :: SRAB_RDH :: sr_rdata_h [31:00] */
#define Wr_CFG_SRAB_RDH_sr_rdata_h(x) WriteReg(CFG_SRAB_RDH,x)
#define Rd_CFG_SRAB_RDH_sr_rdata_h(x) ReadReg(CFG_SRAB_RDH)
#define CFG_SRAB_RDH_SR_RDATA_H_MASK                               0xffffffff
#define CFG_SRAB_RDH_SR_RDATA_H_ALIGN                              0
#define CFG_SRAB_RDH_SR_RDATA_H_BITS                               32
#define CFG_SRAB_RDH_SR_RDATA_H_SHIFT                              0


/****************************************************************************
 * CFG :: SRAB_RDL
 ***************************************************************************/
/* CFG :: SRAB_RDL :: sr_rdata_l [31:00] */
#define Wr_CFG_SRAB_RDL_sr_rdata_l(x) WriteReg(CFG_SRAB_RDL,x)
#define Rd_CFG_SRAB_RDL_sr_rdata_l(x) ReadReg(CFG_SRAB_RDL)
#define CFG_SRAB_RDL_SR_RDATA_L_MASK                               0xffffffff
#define CFG_SRAB_RDL_SR_RDATA_L_ALIGN                              0
#define CFG_SRAB_RDL_SR_RDATA_L_BITS                               32
#define CFG_SRAB_RDL_SR_RDATA_L_SHIFT                              0


/****************************************************************************
 * CFG :: SW_IF
 ***************************************************************************/
/* CFG :: SW_IF :: reserved0 [31:16] */
#define CFG_SW_IF_RESERVED0_MASK                                   0xffff0000
#define CFG_SW_IF_RESERVED0_ALIGN                                  0
#define CFG_SW_IF_RESERVED0_BITS                                   16
#define CFG_SW_IF_RESERVED0_SHIFT                                  16

/* CFG :: SW_IF :: otp_ctrl [15:08] */
#define Wr_CFG_SW_IF_otp_ctrl(x) WriteRegBits(CFG_SW_IF,0xff00,8,x)
#define Rd_CFG_SW_IF_otp_ctrl(x) ReadRegBits(CFG_SW_IF,0xff00,8)
#define CFG_SW_IF_OTP_CTRL_MASK                                    0x0000ff00
#define CFG_SW_IF_OTP_CTRL_ALIGN                                   0
#define CFG_SW_IF_OTP_CTRL_BITS                                    8
#define CFG_SW_IF_OTP_CTRL_SHIFT                                   8

/* CFG :: SW_IF :: reserved1 [07:07] */
#define CFG_SW_IF_RESERVED1_MASK                                   0x00000080
#define CFG_SW_IF_RESERVED1_ALIGN                                  0
#define CFG_SW_IF_RESERVED1_BITS                                   1
#define CFG_SW_IF_RESERVED1_SHIFT                                  7

/* CFG :: SW_IF :: sw_init_done [06:06] */
#define Wr_CFG_SW_IF_sw_init_done(x) WriteRegBits(CFG_SW_IF,0x40,6,x)
#define Rd_CFG_SW_IF_sw_init_done(x) ReadRegBits(CFG_SW_IF,0x40,6)
#define CFG_SW_IF_SW_INIT_DONE_MASK                                0x00000040
#define CFG_SW_IF_SW_INIT_DONE_ALIGN                               0
#define CFG_SW_IF_SW_INIT_DONE_BITS                                1
#define CFG_SW_IF_SW_INIT_DONE_SHIFT                               6

/* CFG :: SW_IF :: reserved2 [05:05] */
#define CFG_SW_IF_RESERVED2_MASK                                   0x00000020
#define CFG_SW_IF_RESERVED2_ALIGN                                  0
#define CFG_SW_IF_RESERVED2_BITS                                   1
#define CFG_SW_IF_RESERVED2_SHIFT                                  5

/* CFG :: SW_IF :: rcagnt [04:04] */
#define Wr_CFG_SW_IF_rcagnt(x) WriteRegBits(CFG_SW_IF,0x10,4,x)
#define Rd_CFG_SW_IF_rcagnt(x) ReadRegBits(CFG_SW_IF,0x10,4)
#define CFG_SW_IF_RCAGNT_MASK                                      0x00000010
#define CFG_SW_IF_RCAGNT_ALIGN                                     0
#define CFG_SW_IF_RCAGNT_BITS                                      1
#define CFG_SW_IF_RCAGNT_SHIFT                                     4

/* CFG :: SW_IF :: reserved3 [03:02] */
#define CFG_SW_IF_RESERVED3_MASK                                   0x0000000c
#define CFG_SW_IF_RESERVED3_ALIGN                                  0
#define CFG_SW_IF_RESERVED3_BITS                                   2
#define CFG_SW_IF_RESERVED3_SHIFT                                  2

/* CFG :: SW_IF :: host_intr [01:01] */
#define Wr_CFG_SW_IF_host_intr(x) WriteRegBits(CFG_SW_IF,0x2,1,x)
#define Rd_CFG_SW_IF_host_intr(x) ReadRegBits(CFG_SW_IF,0x2,1)
#define CFG_SW_IF_HOST_INTR_MASK                                   0x00000002
#define CFG_SW_IF_HOST_INTR_ALIGN                                  0
#define CFG_SW_IF_HOST_INTR_BITS                                   1
#define CFG_SW_IF_HOST_INTR_SHIFT                                  1

/* CFG :: SW_IF :: spimux_arm_sel [00:00] */
#define Wr_CFG_SW_IF_spimux_arm_sel(x) WriteRegBits(CFG_SW_IF,0x1,0,x)
#define Rd_CFG_SW_IF_spimux_arm_sel(x) ReadRegBits(CFG_SW_IF,0x1,0)
#define CFG_SW_IF_SPIMUX_ARM_SEL_MASK                              0x00000001
#define CFG_SW_IF_SPIMUX_ARM_SEL_ALIGN                             0
#define CFG_SW_IF_SPIMUX_ARM_SEL_BITS                              1
#define CFG_SW_IF_SPIMUX_ARM_SEL_SHIFT                             0


/****************************************************************************
 * CFG :: SW_INTR_CLR
 ***************************************************************************/
/* CFG :: SW_INTR_CLR :: sw_intr_clr [31:00] */
#define Wr_CFG_SW_INTR_CLR_sw_intr_clr(x) WriteReg(CFG_SW_INTR_CLR,x)
#define Rd_CFG_SW_INTR_CLR_sw_intr_clr(x) ReadReg(CFG_SW_INTR_CLR)
#define CFG_SW_INTR_CLR_SW_INTR_CLR_MASK                           0xffffffff
#define CFG_SW_INTR_CLR_SW_INTR_CLR_ALIGN                          0
#define CFG_SW_INTR_CLR_SW_INTR_CLR_BITS                           32
#define CFG_SW_INTR_CLR_SW_INTR_CLR_SHIFT                          0


/****************************************************************************
 * CFG :: QSPI_IO_STATUS
 ***************************************************************************/
/* CFG :: QSPI_IO_STATUS :: IO_status_reserved [31:04] */
#define CFG_QSPI_IO_STATUS_IO_STATUS_RESERVED_MASK                 0xfffffff0
#define CFG_QSPI_IO_STATUS_IO_STATUS_RESERVED_ALIGN                0
#define CFG_QSPI_IO_STATUS_IO_STATUS_RESERVED_BITS                 28
#define CFG_QSPI_IO_STATUS_IO_STATUS_RESERVED_SHIFT                4

/* CFG :: QSPI_IO_STATUS :: strap_ip_disable_qspi [03:03] */
#define Wr_CFG_QSPI_IO_STATUS_strap_ip_disable_qspi(x) WriteRegBits(CFG_QSPI_IO_STATUS,0x8,3,x)
#define Rd_CFG_QSPI_IO_STATUS_strap_ip_disable_qspi(x) ReadRegBits(CFG_QSPI_IO_STATUS,0x8,3)
#define CFG_QSPI_IO_STATUS_STRAP_IP_DISABLE_QSPI_MASK              0x00000008
#define CFG_QSPI_IO_STATUS_STRAP_IP_DISABLE_QSPI_ALIGN             0
#define CFG_QSPI_IO_STATUS_STRAP_IP_DISABLE_QSPI_BITS              1
#define CFG_QSPI_IO_STATUS_STRAP_IP_DISABLE_QSPI_SHIFT             3

/* CFG :: QSPI_IO_STATUS :: STRAP_4BYTE_ADDR_MODE [02:02] */
#define Wr_CFG_QSPI_IO_STATUS_STRAP_4BYTE_ADDR_MODE(x) WriteRegBits(CFG_QSPI_IO_STATUS,0x4,2,x)
#define Rd_CFG_QSPI_IO_STATUS_STRAP_4BYTE_ADDR_MODE(x) ReadRegBits(CFG_QSPI_IO_STATUS,0x4,2)
#define CFG_QSPI_IO_STATUS_STRAP_4BYTE_ADDR_MODE_MASK              0x00000004
#define CFG_QSPI_IO_STATUS_STRAP_4BYTE_ADDR_MODE_ALIGN             0
#define CFG_QSPI_IO_STATUS_STRAP_4BYTE_ADDR_MODE_BITS              1
#define CFG_QSPI_IO_STATUS_STRAP_4BYTE_ADDR_MODE_SHIFT             2

/* CFG :: QSPI_IO_STATUS :: STRAP_QUAD_LANE [01:01] */
#define Wr_CFG_QSPI_IO_STATUS_STRAP_QUAD_LANE(x) WriteRegBits(CFG_QSPI_IO_STATUS,0x2,1,x)
#define Rd_CFG_QSPI_IO_STATUS_STRAP_QUAD_LANE(x) ReadRegBits(CFG_QSPI_IO_STATUS,0x2,1)
#define CFG_QSPI_IO_STATUS_STRAP_QUAD_LANE_MASK                    0x00000002
#define CFG_QSPI_IO_STATUS_STRAP_QUAD_LANE_ALIGN                   0
#define CFG_QSPI_IO_STATUS_STRAP_QUAD_LANE_BITS                    1
#define CFG_QSPI_IO_STATUS_STRAP_QUAD_LANE_SHIFT                   1

/* CFG :: QSPI_IO_STATUS :: STRAP_DUAL_LANE [00:00] */
#define Wr_CFG_QSPI_IO_STATUS_STRAP_DUAL_LANE(x) WriteRegBits(CFG_QSPI_IO_STATUS,0x1,0,x)
#define Rd_CFG_QSPI_IO_STATUS_STRAP_DUAL_LANE(x) ReadRegBits(CFG_QSPI_IO_STATUS,0x1,0)
#define CFG_QSPI_IO_STATUS_STRAP_DUAL_LANE_MASK                    0x00000001
#define CFG_QSPI_IO_STATUS_STRAP_DUAL_LANE_ALIGN                   0
#define CFG_QSPI_IO_STATUS_STRAP_DUAL_LANE_BITS                    1
#define CFG_QSPI_IO_STATUS_STRAP_DUAL_LANE_SHIFT                   0


/****************************************************************************
 * CFG :: QSPI_IO_CONTROL
 ***************************************************************************/
/* CFG :: QSPI_IO_CONTROL :: io_control_reserved_1 [31:24] */
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_1_MASK             0xff000000
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_1_ALIGN            0
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_1_BITS             8
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_1_SHIFT            24

/* CFG :: QSPI_IO_CONTROL :: io_control_reserved_3 [23:16] */
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_3_MASK             0x00ff0000
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_3_ALIGN            0
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_3_BITS             8
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_3_SHIFT            16

/* CFG :: QSPI_IO_CONTROL :: io_control_reserved_2 [15:11] */
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_2_MASK             0x0000f800
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_2_ALIGN            0
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_2_BITS             5
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_2_SHIFT            11

/* CFG :: QSPI_IO_CONTROL :: DISABLE_MSPI_FLUSH [10:10] */
#define Wr_CFG_QSPI_IO_CONTROL_DISABLE_MSPI_FLUSH(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x400,10,x)
#define Rd_CFG_QSPI_IO_CONTROL_DISABLE_MSPI_FLUSH(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x400,10)
#define CFG_QSPI_IO_CONTROL_DISABLE_MSPI_FLUSH_MASK                0x00000400
#define CFG_QSPI_IO_CONTROL_DISABLE_MSPI_FLUSH_ALIGN               0
#define CFG_QSPI_IO_CONTROL_DISABLE_MSPI_FLUSH_BITS                1
#define CFG_QSPI_IO_CONTROL_DISABLE_MSPI_FLUSH_SHIFT               10

/* CFG :: QSPI_IO_CONTROL :: ENABLE_RBUS_ARBITER_TIMER [09:09] */
#define Wr_CFG_QSPI_IO_CONTROL_ENABLE_RBUS_ARBITER_TIMER(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x200,9,x)
#define Rd_CFG_QSPI_IO_CONTROL_ENABLE_RBUS_ARBITER_TIMER(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x200,9)
#define CFG_QSPI_IO_CONTROL_ENABLE_RBUS_ARBITER_TIMER_MASK         0x00000200
#define CFG_QSPI_IO_CONTROL_ENABLE_RBUS_ARBITER_TIMER_ALIGN        0
#define CFG_QSPI_IO_CONTROL_ENABLE_RBUS_ARBITER_TIMER_BITS         1
#define CFG_QSPI_IO_CONTROL_ENABLE_RBUS_ARBITER_TIMER_SHIFT        9

/* CFG :: QSPI_IO_CONTROL :: ENABLE_MSPI_halt_set_transaction_done [08:08] */
#define Wr_CFG_QSPI_IO_CONTROL_ENABLE_MSPI_halt_set_transaction_done(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x100,8,x)
#define Rd_CFG_QSPI_IO_CONTROL_ENABLE_MSPI_halt_set_transaction_done(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x100,8)
#define CFG_QSPI_IO_CONTROL_ENABLE_MSPI_HALT_SET_TRANSACTION_DONE_MASK 0x00000100
#define CFG_QSPI_IO_CONTROL_ENABLE_MSPI_HALT_SET_TRANSACTION_DONE_ALIGN 0
#define CFG_QSPI_IO_CONTROL_ENABLE_MSPI_HALT_SET_TRANSACTION_DONE_BITS 1
#define CFG_QSPI_IO_CONTROL_ENABLE_MSPI_HALT_SET_TRANSACTION_DONE_SHIFT 8

/* CFG :: QSPI_IO_CONTROL :: ENABLE_MSPI_done [07:07] */
#define Wr_CFG_QSPI_IO_CONTROL_ENABLE_MSPI_done(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x80,7,x)
#define Rd_CFG_QSPI_IO_CONTROL_ENABLE_MSPI_done(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x80,7)
#define CFG_QSPI_IO_CONTROL_ENABLE_MSPI_DONE_MASK                  0x00000080
#define CFG_QSPI_IO_CONTROL_ENABLE_MSPI_DONE_ALIGN                 0
#define CFG_QSPI_IO_CONTROL_ENABLE_MSPI_DONE_BITS                  1
#define CFG_QSPI_IO_CONTROL_ENABLE_MSPI_DONE_SHIFT                 7

/* CFG :: QSPI_IO_CONTROL :: ENABLE_spi_overread [06:06] */
#define Wr_CFG_QSPI_IO_CONTROL_ENABLE_spi_overread(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x40,6,x)
#define Rd_CFG_QSPI_IO_CONTROL_ENABLE_spi_overread(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x40,6)
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_OVERREAD_MASK               0x00000040
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_OVERREAD_ALIGN              0
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_OVERREAD_BITS               1
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_OVERREAD_SHIFT              6

/* CFG :: QSPI_IO_CONTROL :: ENABLE_spi_LR_session_done [05:05] */
#define Wr_CFG_QSPI_IO_CONTROL_ENABLE_spi_LR_session_done(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x20,5,x)
#define Rd_CFG_QSPI_IO_CONTROL_ENABLE_spi_LR_session_done(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x20,5)
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_SESSION_DONE_MASK        0x00000020
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_SESSION_DONE_ALIGN       0
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_SESSION_DONE_BITS        1
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_SESSION_DONE_SHIFT       5

/* CFG :: QSPI_IO_CONTROL :: ENABLE_spi_LR_impatient [04:04] */
#define Wr_CFG_QSPI_IO_CONTROL_ENABLE_spi_LR_impatient(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x10,4,x)
#define Rd_CFG_QSPI_IO_CONTROL_ENABLE_spi_LR_impatient(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x10,4)
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_IMPATIENT_MASK           0x00000010
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_IMPATIENT_ALIGN          0
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_IMPATIENT_BITS           1
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_IMPATIENT_SHIFT          4

/* CFG :: QSPI_IO_CONTROL :: ENABLE_spi_LR_truncated [03:03] */
#define Wr_CFG_QSPI_IO_CONTROL_ENABLE_spi_LR_truncated(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x8,3,x)
#define Rd_CFG_QSPI_IO_CONTROL_ENABLE_spi_LR_truncated(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x8,3)
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_TRUNCATED_MASK           0x00000008
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_TRUNCATED_ALIGN          0
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_TRUNCATED_BITS           1
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_TRUNCATED_SHIFT          3

/* CFG :: QSPI_IO_CONTROL :: ENABLE_spi_LR_fullness_reached [02:02] */
#define Wr_CFG_QSPI_IO_CONTROL_ENABLE_spi_LR_fullness_reached(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x4,2,x)
#define Rd_CFG_QSPI_IO_CONTROL_ENABLE_spi_LR_fullness_reached(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x4,2)
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_FULLNESS_REACHED_MASK    0x00000004
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_FULLNESS_REACHED_ALIGN   0
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_FULLNESS_REACHED_BITS    1
#define CFG_QSPI_IO_CONTROL_ENABLE_SPI_LR_FULLNESS_REACHED_SHIFT   2

/* CFG :: QSPI_IO_CONTROL :: IO_control_reserved [01:01] */
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_MASK               0x00000002
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_ALIGN              0
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_BITS               1
#define CFG_QSPI_IO_CONTROL_IO_CONTROL_RESERVED_SHIFT              1

/* CFG :: QSPI_IO_CONTROL :: clk_enable [00:00] */
#define Wr_CFG_QSPI_IO_CONTROL_clk_enable(x) WriteRegBits(CFG_QSPI_IO_CONTROL,0x1,0,x)
#define Rd_CFG_QSPI_IO_CONTROL_clk_enable(x) ReadRegBits(CFG_QSPI_IO_CONTROL,0x1,0)
#define CFG_QSPI_IO_CONTROL_CLK_ENABLE_MASK                        0x00000001
#define CFG_QSPI_IO_CONTROL_CLK_ENABLE_ALIGN                       0
#define CFG_QSPI_IO_CONTROL_CLK_ENABLE_BITS                        1
#define CFG_QSPI_IO_CONTROL_CLK_ENABLE_SHIFT                       0


/****************************************************************************
 * CFG :: QSPI_IP_REVID
 ***************************************************************************/
/* CFG :: QSPI_IP_REVID :: ip_revid_reserved [31:08] */
#define CFG_QSPI_IP_REVID_IP_REVID_RESERVED_MASK                   0xffffff00
#define CFG_QSPI_IP_REVID_IP_REVID_RESERVED_ALIGN                  0
#define CFG_QSPI_IP_REVID_IP_REVID_RESERVED_BITS                   24
#define CFG_QSPI_IP_REVID_IP_REVID_RESERVED_SHIFT                  8

/* CFG :: QSPI_IP_REVID :: QSPI_REVID [07:00] */
#define Wr_CFG_QSPI_IP_REVID_QSPI_REVID(x) WriteRegBits(CFG_QSPI_IP_REVID,0xff,0,x)
#define Rd_CFG_QSPI_IP_REVID_QSPI_REVID(x) ReadRegBits(CFG_QSPI_IP_REVID,0xff,0)
#define CFG_QSPI_IP_REVID_QSPI_REVID_MASK                          0x000000ff
#define CFG_QSPI_IP_REVID_QSPI_REVID_ALIGN                         0
#define CFG_QSPI_IP_REVID_QSPI_REVID_BITS                          8
#define CFG_QSPI_IP_REVID_QSPI_REVID_SHIFT                         0


/****************************************************************************
 * CFG :: SPI_CRC_CONTROL
 ***************************************************************************/
/* CFG :: SPI_CRC_CONTROL :: crc_enable_reserved [31:02] */
#define CFG_SPI_CRC_CONTROL_CRC_ENABLE_RESERVED_MASK               0xfffffffc
#define CFG_SPI_CRC_CONTROL_CRC_ENABLE_RESERVED_ALIGN              0
#define CFG_SPI_CRC_CONTROL_CRC_ENABLE_RESERVED_BITS               30
#define CFG_SPI_CRC_CONTROL_CRC_ENABLE_RESERVED_SHIFT              2

/* CFG :: SPI_CRC_CONTROL :: crc_clear [01:01] */
#define Wr_CFG_SPI_CRC_CONTROL_crc_clear(x) WriteRegBits(CFG_SPI_CRC_CONTROL,0x2,1,x)
#define Rd_CFG_SPI_CRC_CONTROL_crc_clear(x) ReadRegBits(CFG_SPI_CRC_CONTROL,0x2,1)
#define CFG_SPI_CRC_CONTROL_CRC_CLEAR_MASK                         0x00000002
#define CFG_SPI_CRC_CONTROL_CRC_CLEAR_ALIGN                        0
#define CFG_SPI_CRC_CONTROL_CRC_CLEAR_BITS                         1
#define CFG_SPI_CRC_CONTROL_CRC_CLEAR_SHIFT                        1

/* CFG :: SPI_CRC_CONTROL :: crc_enable [00:00] */
#define Wr_CFG_SPI_CRC_CONTROL_crc_enable(x) WriteRegBits(CFG_SPI_CRC_CONTROL,0x1,0,x)
#define Rd_CFG_SPI_CRC_CONTROL_crc_enable(x) ReadRegBits(CFG_SPI_CRC_CONTROL,0x1,0)
#define CFG_SPI_CRC_CONTROL_CRC_ENABLE_MASK                        0x00000001
#define CFG_SPI_CRC_CONTROL_CRC_ENABLE_ALIGN                       0
#define CFG_SPI_CRC_CONTROL_CRC_ENABLE_BITS                        1
#define CFG_SPI_CRC_CONTROL_CRC_ENABLE_SHIFT                       0


/****************************************************************************
 * CFG :: SPI_CRC_STATUS
 ***************************************************************************/
/* CFG :: SPI_CRC_STATUS :: qspi_output [31:00] */
#define Wr_CFG_SPI_CRC_STATUS_qspi_output(x) WriteReg(CFG_SPI_CRC_STATUS,x)
#define Rd_CFG_SPI_CRC_STATUS_qspi_output(x) ReadReg(CFG_SPI_CRC_STATUS)
#define CFG_SPI_CRC_STATUS_QSPI_OUTPUT_MASK                        0xffffffff
#define CFG_SPI_CRC_STATUS_QSPI_OUTPUT_ALIGN                       0
#define CFG_SPI_CRC_STATUS_QSPI_OUTPUT_BITS                        32
#define CFG_SPI_CRC_STATUS_QSPI_OUTPUT_SHIFT                       0


/****************************************************************************
 * CFG :: CPU_INTR_RAW
 ***************************************************************************/
/* CFG :: CPU_INTR_RAW :: cpu_intr_raw [31:00] */
#define Wr_CFG_CPU_INTR_RAW_cpu_intr_raw(x) WriteReg(CFG_CPU_INTR_RAW,x)
#define Rd_CFG_CPU_INTR_RAW_cpu_intr_raw(x) ReadReg(CFG_CPU_INTR_RAW)
#define CFG_CPU_INTR_RAW_CPU_INTR_RAW_MASK                         0xffffffff
#define CFG_CPU_INTR_RAW_CPU_INTR_RAW_ALIGN                        0
#define CFG_CPU_INTR_RAW_CPU_INTR_RAW_BITS                         32
#define CFG_CPU_INTR_RAW_CPU_INTR_RAW_SHIFT                        0


/****************************************************************************
 * CFG :: CPU_INTR_STAT
 ***************************************************************************/
/* CFG :: CPU_INTR_STAT :: cpu_intr_stat [31:00] */
#define Wr_CFG_CPU_INTR_STAT_cpu_intr_stat(x) WriteReg(CFG_CPU_INTR_STAT,x)
#define Rd_CFG_CPU_INTR_STAT_cpu_intr_stat(x) ReadReg(CFG_CPU_INTR_STAT)
#define CFG_CPU_INTR_STAT_CPU_INTR_STAT_MASK                       0xffffffff
#define CFG_CPU_INTR_STAT_CPU_INTR_STAT_ALIGN                      0
#define CFG_CPU_INTR_STAT_CPU_INTR_STAT_BITS                       32
#define CFG_CPU_INTR_STAT_CPU_INTR_STAT_SHIFT                      0


/****************************************************************************
 * CFG :: CPU_INTR_MASK
 ***************************************************************************/
/* CFG :: CPU_INTR_MASK :: cpu_intr_mask [31:00] */
#define Wr_CFG_CPU_INTR_MASK_cpu_intr_mask(x) WriteReg(CFG_CPU_INTR_MASK,x)
#define Rd_CFG_CPU_INTR_MASK_cpu_intr_mask(x) ReadReg(CFG_CPU_INTR_MASK)
#define CFG_CPU_INTR_MASK_CPU_INTR_MASK_MASK                       0xffffffff
#define CFG_CPU_INTR_MASK_CPU_INTR_MASK_ALIGN                      0
#define CFG_CPU_INTR_MASK_CPU_INTR_MASK_BITS                       32
#define CFG_CPU_INTR_MASK_CPU_INTR_MASK_SHIFT                      0


/****************************************************************************
 * CFG :: CPU_INTR_FORCE
 ***************************************************************************/
/* CFG :: CPU_INTR_FORCE :: cpu_intr_force [31:00] */
#define Wr_CFG_CPU_INTR_FORCE_cpu_intr_force(x) WriteReg(CFG_CPU_INTR_FORCE,x)
#define Rd_CFG_CPU_INTR_FORCE_cpu_intr_force(x) ReadReg(CFG_CPU_INTR_FORCE)
#define CFG_CPU_INTR_FORCE_CPU_INTR_FORCE_MASK                     0xffffffff
#define CFG_CPU_INTR_FORCE_CPU_INTR_FORCE_ALIGN                    0
#define CFG_CPU_INTR_FORCE_CPU_INTR_FORCE_BITS                     32
#define CFG_CPU_INTR_FORCE_CPU_INTR_FORCE_SHIFT                    0


/****************************************************************************
 * CFG :: CPU_INTR_CFG
 ***************************************************************************/
/* CFG :: CPU_INTR_CFG :: reserved0 [31:03] */
#define CFG_CPU_INTR_CFG_RESERVED0_MASK                            0xfffffff8
#define CFG_CPU_INTR_CFG_RESERVED0_ALIGN                           0
#define CFG_CPU_INTR_CFG_RESERVED0_BITS                            29
#define CFG_CPU_INTR_CFG_RESERVED0_SHIFT                           3

/* CFG :: CPU_INTR_CFG :: soft2vic_intr_cfg [02:02] */
#define Wr_CFG_CPU_INTR_CFG_soft2vic_intr_cfg(x) WriteRegBits(CFG_CPU_INTR_CFG,0x4,2,x)
#define Rd_CFG_CPU_INTR_CFG_soft2vic_intr_cfg(x) ReadRegBits(CFG_CPU_INTR_CFG,0x4,2)
#define CFG_CPU_INTR_CFG_SOFT2VIC_INTR_CFG_MASK                    0x00000004
#define CFG_CPU_INTR_CFG_SOFT2VIC_INTR_CFG_ALIGN                   0
#define CFG_CPU_INTR_CFG_SOFT2VIC_INTR_CFG_BITS                    1
#define CFG_CPU_INTR_CFG_SOFT2VIC_INTR_CFG_SHIFT                   2

/* CFG :: CPU_INTR_CFG :: pad_intr_n_sel [01:01] */
#define Wr_CFG_CPU_INTR_CFG_pad_intr_n_sel(x) WriteRegBits(CFG_CPU_INTR_CFG,0x2,1,x)
#define Rd_CFG_CPU_INTR_CFG_pad_intr_n_sel(x) ReadRegBits(CFG_CPU_INTR_CFG,0x2,1)
#define CFG_CPU_INTR_CFG_PAD_INTR_N_SEL_MASK                       0x00000002
#define CFG_CPU_INTR_CFG_PAD_INTR_N_SEL_ALIGN                      0
#define CFG_CPU_INTR_CFG_PAD_INTR_N_SEL_BITS                       1
#define CFG_CPU_INTR_CFG_PAD_INTR_N_SEL_SHIFT                      1

/* CFG :: CPU_INTR_CFG :: pad_intr_n_mode [00:00] */
#define Wr_CFG_CPU_INTR_CFG_pad_intr_n_mode(x) WriteRegBits(CFG_CPU_INTR_CFG,0x1,0,x)
#define Rd_CFG_CPU_INTR_CFG_pad_intr_n_mode(x) ReadRegBits(CFG_CPU_INTR_CFG,0x1,0)
#define CFG_CPU_INTR_CFG_PAD_INTR_N_MODE_MASK                      0x00000001
#define CFG_CPU_INTR_CFG_PAD_INTR_N_MODE_ALIGN                     0
#define CFG_CPU_INTR_CFG_PAD_INTR_N_MODE_BITS                      1
#define CFG_CPU_INTR_CFG_PAD_INTR_N_MODE_SHIFT                     0


/****************************************************************************
 * CFG :: SPI_CRC_IDLE_CYCLE_COUNT
 ***************************************************************************/
/* CFG :: SPI_CRC_IDLE_CYCLE_COUNT :: crc_idle_cycle_count [31:00] */
#define Wr_CFG_SPI_CRC_IDLE_CYCLE_COUNT_crc_idle_cycle_count(x) WriteReg(CFG_SPI_CRC_IDLE_CYCLE_COUNT,x)
#define Rd_CFG_SPI_CRC_IDLE_CYCLE_COUNT_crc_idle_cycle_count(x) ReadReg(CFG_SPI_CRC_IDLE_CYCLE_COUNT)
#define CFG_SPI_CRC_IDLE_CYCLE_COUNT_CRC_IDLE_CYCLE_COUNT_MASK     0xffffffff
#define CFG_SPI_CRC_IDLE_CYCLE_COUNT_CRC_IDLE_CYCLE_COUNT_ALIGN    0
#define CFG_SPI_CRC_IDLE_CYCLE_COUNT_CRC_IDLE_CYCLE_COUNT_BITS     32
#define CFG_SPI_CRC_IDLE_CYCLE_COUNT_CRC_IDLE_CYCLE_COUNT_SHIFT    0


/****************************************************************************
 * CFG :: AHB2RDB_TIMEOUT
 ***************************************************************************/
/* CFG :: AHB2RDB_TIMEOUT :: reserved0 [31:19] */
#define CFG_AHB2RDB_TIMEOUT_RESERVED0_MASK                         0xfff80000
#define CFG_AHB2RDB_TIMEOUT_RESERVED0_ALIGN                        0
#define CFG_AHB2RDB_TIMEOUT_RESERVED0_BITS                         13
#define CFG_AHB2RDB_TIMEOUT_RESERVED0_SHIFT                        19

/* CFG :: AHB2RDB_TIMEOUT :: ahb2rdb_timeout_qspi [18:18] */
#define Wr_CFG_AHB2RDB_TIMEOUT_ahb2rdb_timeout_qspi(x) WriteRegBits(CFG_AHB2RDB_TIMEOUT,0x40000,18,x)
#define Rd_CFG_AHB2RDB_TIMEOUT_ahb2rdb_timeout_qspi(x) ReadRegBits(CFG_AHB2RDB_TIMEOUT,0x40000,18)
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_QSPI_MASK              0x00040000
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_QSPI_ALIGN             0
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_QSPI_BITS              1
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_QSPI_SHIFT             18

/* CFG :: AHB2RDB_TIMEOUT :: ahb2rdb_timeout_rdb16 [17:17] */
#define Wr_CFG_AHB2RDB_TIMEOUT_ahb2rdb_timeout_rdb16(x) WriteRegBits(CFG_AHB2RDB_TIMEOUT,0x20000,17,x)
#define Rd_CFG_AHB2RDB_TIMEOUT_ahb2rdb_timeout_rdb16(x) ReadRegBits(CFG_AHB2RDB_TIMEOUT,0x20000,17)
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_RDB16_MASK             0x00020000
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_RDB16_ALIGN            0
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_RDB16_BITS             1
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_RDB16_SHIFT            17

/* CFG :: AHB2RDB_TIMEOUT :: ahb2rdb_timeout_srab [16:16] */
#define Wr_CFG_AHB2RDB_TIMEOUT_ahb2rdb_timeout_srab(x) WriteRegBits(CFG_AHB2RDB_TIMEOUT,0x10000,16,x)
#define Rd_CFG_AHB2RDB_TIMEOUT_ahb2rdb_timeout_srab(x) ReadRegBits(CFG_AHB2RDB_TIMEOUT,0x10000,16)
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_SRAB_MASK              0x00010000
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_SRAB_ALIGN             0
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_SRAB_BITS              1
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_SRAB_SHIFT             16

/* CFG :: AHB2RDB_TIMEOUT :: ahb2rdb_timeout_time [15:00] */
#define Wr_CFG_AHB2RDB_TIMEOUT_ahb2rdb_timeout_time(x) WriteRegBits(CFG_AHB2RDB_TIMEOUT,0xffff,0,x)
#define Rd_CFG_AHB2RDB_TIMEOUT_ahb2rdb_timeout_time(x) ReadRegBits(CFG_AHB2RDB_TIMEOUT,0xffff,0)
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_TIME_MASK              0x0000ffff
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_TIME_ALIGN             0
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_TIME_BITS              16
#define CFG_AHB2RDB_TIMEOUT_AHB2RDB_TIMEOUT_TIME_SHIFT             0


/****************************************************************************
 * bcm89530_sys_cfg_URT0
 ***************************************************************************/
/****************************************************************************
 * URT0 :: UARTDR
 ***************************************************************************/
/* URT0 :: UARTDR :: reserved0 [31:12] */
#define URT0_UARTDR_RESERVED0_MASK                                 0xfffff000
#define URT0_UARTDR_RESERVED0_ALIGN                                0
#define URT0_UARTDR_RESERVED0_BITS                                 20
#define URT0_UARTDR_RESERVED0_SHIFT                                12

/* URT0 :: UARTDR :: OE [11:11] */
#define Wr_URT0_UARTDR_OE(x) WriteRegBits(URT0_UARTDR,0x800,11,x)
#define Rd_URT0_UARTDR_OE(x) ReadRegBits(URT0_UARTDR,0x800,11)
#define URT0_UARTDR_OE_MASK                                        0x00000800
#define URT0_UARTDR_OE_ALIGN                                       0
#define URT0_UARTDR_OE_BITS                                        1
#define URT0_UARTDR_OE_SHIFT                                       11

/* URT0 :: UARTDR :: BE [10:10] */
#define Wr_URT0_UARTDR_BE(x) WriteRegBits(URT0_UARTDR,0x400,10,x)
#define Rd_URT0_UARTDR_BE(x) ReadRegBits(URT0_UARTDR,0x400,10)
#define URT0_UARTDR_BE_MASK                                        0x00000400
#define URT0_UARTDR_BE_ALIGN                                       0
#define URT0_UARTDR_BE_BITS                                        1
#define URT0_UARTDR_BE_SHIFT                                       10

/* URT0 :: UARTDR :: PE [09:09] */
#define Wr_URT0_UARTDR_PE(x) WriteRegBits(URT0_UARTDR,0x200,9,x)
#define Rd_URT0_UARTDR_PE(x) ReadRegBits(URT0_UARTDR,0x200,9)
#define URT0_UARTDR_PE_MASK                                        0x00000200
#define URT0_UARTDR_PE_ALIGN                                       0
#define URT0_UARTDR_PE_BITS                                        1
#define URT0_UARTDR_PE_SHIFT                                       9

/* URT0 :: UARTDR :: FE [08:08] */
#define Wr_URT0_UARTDR_FE(x) WriteRegBits(URT0_UARTDR,0x100,8,x)
#define Rd_URT0_UARTDR_FE(x) ReadRegBits(URT0_UARTDR,0x100,8)
#define URT0_UARTDR_FE_MASK                                        0x00000100
#define URT0_UARTDR_FE_ALIGN                                       0
#define URT0_UARTDR_FE_BITS                                        1
#define URT0_UARTDR_FE_SHIFT                                       8

/* URT0 :: UARTDR :: Data [07:00] */
#define Wr_URT0_UARTDR_Data(x) WriteRegBits(URT0_UARTDR,0xff,0,x)
#define Rd_URT0_UARTDR_Data(x) ReadRegBits(URT0_UARTDR,0xff,0)
#define URT0_UARTDR_DATA_MASK                                      0x000000ff
#define URT0_UARTDR_DATA_ALIGN                                     0
#define URT0_UARTDR_DATA_BITS                                      8
#define URT0_UARTDR_DATA_SHIFT                                     0


/****************************************************************************
 * URT0 :: UARTRSR_UARTECR
 ***************************************************************************/
/* URT0 :: UARTRSR_UARTECR :: reserved0 [31:04] */
#define URT0_UARTRSR_UARTECR_RESERVED0_MASK                        0xfffffff0
#define URT0_UARTRSR_UARTECR_RESERVED0_ALIGN                       0
#define URT0_UARTRSR_UARTECR_RESERVED0_BITS                        28
#define URT0_UARTRSR_UARTECR_RESERVED0_SHIFT                       4

/* URT0 :: UARTRSR_UARTECR :: RECEIVE_OE [03:03] */
#define Wr_URT0_UARTRSR_UARTECR_RECEIVE_OE(x) WriteRegBits(URT0_UARTRSR_UARTECR,0x8,3,x)
#define Rd_URT0_UARTRSR_UARTECR_RECEIVE_OE(x) ReadRegBits(URT0_UARTRSR_UARTECR,0x8,3)
#define URT0_UARTRSR_UARTECR_RECEIVE_OE_MASK                       0x00000008
#define URT0_UARTRSR_UARTECR_RECEIVE_OE_ALIGN                      0
#define URT0_UARTRSR_UARTECR_RECEIVE_OE_BITS                       1
#define URT0_UARTRSR_UARTECR_RECEIVE_OE_SHIFT                      3

/* URT0 :: UARTRSR_UARTECR :: RECEIVE_BE [02:02] */
#define Wr_URT0_UARTRSR_UARTECR_RECEIVE_BE(x) WriteRegBits(URT0_UARTRSR_UARTECR,0x4,2,x)
#define Rd_URT0_UARTRSR_UARTECR_RECEIVE_BE(x) ReadRegBits(URT0_UARTRSR_UARTECR,0x4,2)
#define URT0_UARTRSR_UARTECR_RECEIVE_BE_MASK                       0x00000004
#define URT0_UARTRSR_UARTECR_RECEIVE_BE_ALIGN                      0
#define URT0_UARTRSR_UARTECR_RECEIVE_BE_BITS                       1
#define URT0_UARTRSR_UARTECR_RECEIVE_BE_SHIFT                      2

/* URT0 :: UARTRSR_UARTECR :: RECEIVE_PE [01:01] */
#define Wr_URT0_UARTRSR_UARTECR_RECEIVE_PE(x) WriteRegBits(URT0_UARTRSR_UARTECR,0x2,1,x)
#define Rd_URT0_UARTRSR_UARTECR_RECEIVE_PE(x) ReadRegBits(URT0_UARTRSR_UARTECR,0x2,1)
#define URT0_UARTRSR_UARTECR_RECEIVE_PE_MASK                       0x00000002
#define URT0_UARTRSR_UARTECR_RECEIVE_PE_ALIGN                      0
#define URT0_UARTRSR_UARTECR_RECEIVE_PE_BITS                       1
#define URT0_UARTRSR_UARTECR_RECEIVE_PE_SHIFT                      1

/* URT0 :: UARTRSR_UARTECR :: RECEIVE_FE [00:00] */
#define Wr_URT0_UARTRSR_UARTECR_RECEIVE_FE(x) WriteRegBits(URT0_UARTRSR_UARTECR,0x1,0,x)
#define Rd_URT0_UARTRSR_UARTECR_RECEIVE_FE(x) ReadRegBits(URT0_UARTRSR_UARTECR,0x1,0)
#define URT0_UARTRSR_UARTECR_RECEIVE_FE_MASK                       0x00000001
#define URT0_UARTRSR_UARTECR_RECEIVE_FE_ALIGN                      0
#define URT0_UARTRSR_UARTECR_RECEIVE_FE_BITS                       1
#define URT0_UARTRSR_UARTECR_RECEIVE_FE_SHIFT                      0


/****************************************************************************
 * URT0 :: UARTFR
 ***************************************************************************/
/* URT0 :: UARTFR :: reserved0 [31:09] */
#define URT0_UARTFR_RESERVED0_MASK                                 0xfffffe00
#define URT0_UARTFR_RESERVED0_ALIGN                                0
#define URT0_UARTFR_RESERVED0_BITS                                 23
#define URT0_UARTFR_RESERVED0_SHIFT                                9

/* URT0 :: UARTFR :: RI [08:08] */
#define Wr_URT0_UARTFR_RI(x) WriteRegBits(URT0_UARTFR,0x100,8,x)
#define Rd_URT0_UARTFR_RI(x) ReadRegBits(URT0_UARTFR,0x100,8)
#define URT0_UARTFR_RI_MASK                                        0x00000100
#define URT0_UARTFR_RI_ALIGN                                       0
#define URT0_UARTFR_RI_BITS                                        1
#define URT0_UARTFR_RI_SHIFT                                       8

/* URT0 :: UARTFR :: TXFE [07:07] */
#define Wr_URT0_UARTFR_TXFE(x) WriteRegBits(URT0_UARTFR,0x80,7,x)
#define Rd_URT0_UARTFR_TXFE(x) ReadRegBits(URT0_UARTFR,0x80,7)
#define URT0_UARTFR_TXFE_MASK                                      0x00000080
#define URT0_UARTFR_TXFE_ALIGN                                     0
#define URT0_UARTFR_TXFE_BITS                                      1
#define URT0_UARTFR_TXFE_SHIFT                                     7

/* URT0 :: UARTFR :: RXFF [06:06] */
#define Wr_URT0_UARTFR_RXFF(x) WriteRegBits(URT0_UARTFR,0x40,6,x)
#define Rd_URT0_UARTFR_RXFF(x) ReadRegBits(URT0_UARTFR,0x40,6)
#define URT0_UARTFR_RXFF_MASK                                      0x00000040
#define URT0_UARTFR_RXFF_ALIGN                                     0
#define URT0_UARTFR_RXFF_BITS                                      1
#define URT0_UARTFR_RXFF_SHIFT                                     6

/* URT0 :: UARTFR :: TXFF [05:05] */
#define Wr_URT0_UARTFR_TXFF(x) WriteRegBits(URT0_UARTFR,0x20,5,x)
#define Rd_URT0_UARTFR_TXFF(x) ReadRegBits(URT0_UARTFR,0x20,5)
#define URT0_UARTFR_TXFF_MASK                                      0x00000020
#define URT0_UARTFR_TXFF_ALIGN                                     0
#define URT0_UARTFR_TXFF_BITS                                      1
#define URT0_UARTFR_TXFF_SHIFT                                     5

/* URT0 :: UARTFR :: RXFE [04:04] */
#define Wr_URT0_UARTFR_RXFE(x) WriteRegBits(URT0_UARTFR,0x10,4,x)
#define Rd_URT0_UARTFR_RXFE(x) ReadRegBits(URT0_UARTFR,0x10,4)
#define URT0_UARTFR_RXFE_MASK                                      0x00000010
#define URT0_UARTFR_RXFE_ALIGN                                     0
#define URT0_UARTFR_RXFE_BITS                                      1
#define URT0_UARTFR_RXFE_SHIFT                                     4

/* URT0 :: UARTFR :: BUSY [03:03] */
#define Wr_URT0_UARTFR_BUSY(x) WriteRegBits(URT0_UARTFR,0x8,3,x)
#define Rd_URT0_UARTFR_BUSY(x) ReadRegBits(URT0_UARTFR,0x8,3)
#define URT0_UARTFR_BUSY_MASK                                      0x00000008
#define URT0_UARTFR_BUSY_ALIGN                                     0
#define URT0_UARTFR_BUSY_BITS                                      1
#define URT0_UARTFR_BUSY_SHIFT                                     3

/* URT0 :: UARTFR :: DCD [02:02] */
#define Wr_URT0_UARTFR_DCD(x) WriteRegBits(URT0_UARTFR,0x4,2,x)
#define Rd_URT0_UARTFR_DCD(x) ReadRegBits(URT0_UARTFR,0x4,2)
#define URT0_UARTFR_DCD_MASK                                       0x00000004
#define URT0_UARTFR_DCD_ALIGN                                      0
#define URT0_UARTFR_DCD_BITS                                       1
#define URT0_UARTFR_DCD_SHIFT                                      2

/* URT0 :: UARTFR :: DSR [01:01] */
#define Wr_URT0_UARTFR_DSR(x) WriteRegBits(URT0_UARTFR,0x2,1,x)
#define Rd_URT0_UARTFR_DSR(x) ReadRegBits(URT0_UARTFR,0x2,1)
#define URT0_UARTFR_DSR_MASK                                       0x00000002
#define URT0_UARTFR_DSR_ALIGN                                      0
#define URT0_UARTFR_DSR_BITS                                       1
#define URT0_UARTFR_DSR_SHIFT                                      1

/* URT0 :: UARTFR :: CTS [00:00] */
#define Wr_URT0_UARTFR_CTS(x) WriteRegBits(URT0_UARTFR,0x1,0,x)
#define Rd_URT0_UARTFR_CTS(x) ReadRegBits(URT0_UARTFR,0x1,0)
#define URT0_UARTFR_CTS_MASK                                       0x00000001
#define URT0_UARTFR_CTS_ALIGN                                      0
#define URT0_UARTFR_CTS_BITS                                       1
#define URT0_UARTFR_CTS_SHIFT                                      0


/****************************************************************************
 * URT0 :: UARTILPR
 ***************************************************************************/
/* URT0 :: UARTILPR :: reserved0 [31:08] */
#define URT0_UARTILPR_RESERVED0_MASK                               0xffffff00
#define URT0_UARTILPR_RESERVED0_ALIGN                              0
#define URT0_UARTILPR_RESERVED0_BITS                               24
#define URT0_UARTILPR_RESERVED0_SHIFT                              8

/* URT0 :: UARTILPR :: ILPDVSR [07:00] */
#define Wr_URT0_UARTILPR_ILPDVSR(x) WriteRegBits(URT0_UARTILPR,0xff,0,x)
#define Rd_URT0_UARTILPR_ILPDVSR(x) ReadRegBits(URT0_UARTILPR,0xff,0)
#define URT0_UARTILPR_ILPDVSR_MASK                                 0x000000ff
#define URT0_UARTILPR_ILPDVSR_ALIGN                                0
#define URT0_UARTILPR_ILPDVSR_BITS                                 8
#define URT0_UARTILPR_ILPDVSR_SHIFT                                0


/****************************************************************************
 * URT0 :: UARTIBRD
 ***************************************************************************/
/* URT0 :: UARTIBRD :: reserved0 [31:16] */
#define URT0_UARTIBRD_RESERVED0_MASK                               0xffff0000
#define URT0_UARTIBRD_RESERVED0_ALIGN                              0
#define URT0_UARTIBRD_RESERVED0_BITS                               16
#define URT0_UARTIBRD_RESERVED0_SHIFT                              16

/* URT0 :: UARTIBRD :: BAUD_DIVINT [15:00] */
#define Wr_URT0_UARTIBRD_BAUD_DIVINT(x) WriteRegBits(URT0_UARTIBRD,0xffff,0,x)
#define Rd_URT0_UARTIBRD_BAUD_DIVINT(x) ReadRegBits(URT0_UARTIBRD,0xffff,0)
#define URT0_UARTIBRD_BAUD_DIVINT_MASK                             0x0000ffff
#define URT0_UARTIBRD_BAUD_DIVINT_ALIGN                            0
#define URT0_UARTIBRD_BAUD_DIVINT_BITS                             16
#define URT0_UARTIBRD_BAUD_DIVINT_SHIFT                            0


/****************************************************************************
 * URT0 :: UARTFBRD
 ***************************************************************************/
/* URT0 :: UARTFBRD :: reserved0 [31:06] */
#define URT0_UARTFBRD_RESERVED0_MASK                               0xffffffc0
#define URT0_UARTFBRD_RESERVED0_ALIGN                              0
#define URT0_UARTFBRD_RESERVED0_BITS                               26
#define URT0_UARTFBRD_RESERVED0_SHIFT                              6

/* URT0 :: UARTFBRD :: BAUD_DIVFRAC [05:00] */
#define Wr_URT0_UARTFBRD_BAUD_DIVFRAC(x) WriteRegBits(URT0_UARTFBRD,0x3f,0,x)
#define Rd_URT0_UARTFBRD_BAUD_DIVFRAC(x) ReadRegBits(URT0_UARTFBRD,0x3f,0)
#define URT0_UARTFBRD_BAUD_DIVFRAC_MASK                            0x0000003f
#define URT0_UARTFBRD_BAUD_DIVFRAC_ALIGN                           0
#define URT0_UARTFBRD_BAUD_DIVFRAC_BITS                            6
#define URT0_UARTFBRD_BAUD_DIVFRAC_SHIFT                           0


/****************************************************************************
 * URT0 :: UARTLCR
 ***************************************************************************/
/* URT0 :: UARTLCR :: reserved0 [31:08] */
#define URT0_UARTLCR_RESERVED0_MASK                                0xffffff00
#define URT0_UARTLCR_RESERVED0_ALIGN                               0
#define URT0_UARTLCR_RESERVED0_BITS                                24
#define URT0_UARTLCR_RESERVED0_SHIFT                               8

/* URT0 :: UARTLCR :: SPS [07:07] */
#define Wr_URT0_UARTLCR_SPS(x) WriteRegBits(URT0_UARTLCR,0x80,7,x)
#define Rd_URT0_UARTLCR_SPS(x) ReadRegBits(URT0_UARTLCR,0x80,7)
#define URT0_UARTLCR_SPS_MASK                                      0x00000080
#define URT0_UARTLCR_SPS_ALIGN                                     0
#define URT0_UARTLCR_SPS_BITS                                      1
#define URT0_UARTLCR_SPS_SHIFT                                     7

/* URT0 :: UARTLCR :: reserved1 [06:05] */
#define URT0_UARTLCR_RESERVED1_MASK                                0x00000060
#define URT0_UARTLCR_RESERVED1_ALIGN                               0
#define URT0_UARTLCR_RESERVED1_BITS                                2
#define URT0_UARTLCR_RESERVED1_SHIFT                               5

/* URT0 :: UARTLCR :: FEN [04:04] */
#define Wr_URT0_UARTLCR_FEN(x) WriteRegBits(URT0_UARTLCR,0x10,4,x)
#define Rd_URT0_UARTLCR_FEN(x) ReadRegBits(URT0_UARTLCR,0x10,4)
#define URT0_UARTLCR_FEN_MASK                                      0x00000010
#define URT0_UARTLCR_FEN_ALIGN                                     0
#define URT0_UARTLCR_FEN_BITS                                      1
#define URT0_UARTLCR_FEN_SHIFT                                     4

/* URT0 :: UARTLCR :: STP2 [03:03] */
#define Wr_URT0_UARTLCR_STP2(x) WriteRegBits(URT0_UARTLCR,0x8,3,x)
#define Rd_URT0_UARTLCR_STP2(x) ReadRegBits(URT0_UARTLCR,0x8,3)
#define URT0_UARTLCR_STP2_MASK                                     0x00000008
#define URT0_UARTLCR_STP2_ALIGN                                    0
#define URT0_UARTLCR_STP2_BITS                                     1
#define URT0_UARTLCR_STP2_SHIFT                                    3

/* URT0 :: UARTLCR :: EPS [02:02] */
#define Wr_URT0_UARTLCR_EPS(x) WriteRegBits(URT0_UARTLCR,0x4,2,x)
#define Rd_URT0_UARTLCR_EPS(x) ReadRegBits(URT0_UARTLCR,0x4,2)
#define URT0_UARTLCR_EPS_MASK                                      0x00000004
#define URT0_UARTLCR_EPS_ALIGN                                     0
#define URT0_UARTLCR_EPS_BITS                                      1
#define URT0_UARTLCR_EPS_SHIFT                                     2

/* URT0 :: UARTLCR :: PEN [01:01] */
#define Wr_URT0_UARTLCR_PEN(x) WriteRegBits(URT0_UARTLCR,0x2,1,x)
#define Rd_URT0_UARTLCR_PEN(x) ReadRegBits(URT0_UARTLCR,0x2,1)
#define URT0_UARTLCR_PEN_MASK                                      0x00000002
#define URT0_UARTLCR_PEN_ALIGN                                     0
#define URT0_UARTLCR_PEN_BITS                                      1
#define URT0_UARTLCR_PEN_SHIFT                                     1

/* URT0 :: UARTLCR :: BRK [00:00] */
#define Wr_URT0_UARTLCR_BRK(x) WriteRegBits(URT0_UARTLCR,0x1,0,x)
#define Rd_URT0_UARTLCR_BRK(x) ReadRegBits(URT0_UARTLCR,0x1,0)
#define URT0_UARTLCR_BRK_MASK                                      0x00000001
#define URT0_UARTLCR_BRK_ALIGN                                     0
#define URT0_UARTLCR_BRK_BITS                                      1
#define URT0_UARTLCR_BRK_SHIFT                                     0


/****************************************************************************
 * URT0 :: UARTCR
 ***************************************************************************/
/* URT0 :: UARTCR :: reserved0 [31:16] */
#define URT0_UARTCR_RESERVED0_MASK                                 0xffff0000
#define URT0_UARTCR_RESERVED0_ALIGN                                0
#define URT0_UARTCR_RESERVED0_BITS                                 16
#define URT0_UARTCR_RESERVED0_SHIFT                                16

/* URT0 :: UARTCR :: CTSEn [15:15] */
#define Wr_URT0_UARTCR_CTSEn(x) WriteRegBits(URT0_UARTCR,0x8000,15,x)
#define Rd_URT0_UARTCR_CTSEn(x) ReadRegBits(URT0_UARTCR,0x8000,15)
#define URT0_UARTCR_CTSEN_MASK                                     0x00008000
#define URT0_UARTCR_CTSEN_ALIGN                                    0
#define URT0_UARTCR_CTSEN_BITS                                     1
#define URT0_UARTCR_CTSEN_SHIFT                                    15

/* URT0 :: UARTCR :: reserved1 [14:14] */
#define URT0_UARTCR_RESERVED1_MASK                                 0x00004000
#define URT0_UARTCR_RESERVED1_ALIGN                                0
#define URT0_UARTCR_RESERVED1_BITS                                 1
#define URT0_UARTCR_RESERVED1_SHIFT                                14

/* URT0 :: UARTCR :: Out2 [13:13] */
#define Wr_URT0_UARTCR_Out2(x) WriteRegBits(URT0_UARTCR,0x2000,13,x)
#define Rd_URT0_UARTCR_Out2(x) ReadRegBits(URT0_UARTCR,0x2000,13)
#define URT0_UARTCR_OUT2_MASK                                      0x00002000
#define URT0_UARTCR_OUT2_ALIGN                                     0
#define URT0_UARTCR_OUT2_BITS                                      1
#define URT0_UARTCR_OUT2_SHIFT                                     13

/* URT0 :: UARTCR :: Out1 [12:12] */
#define Wr_URT0_UARTCR_Out1(x) WriteRegBits(URT0_UARTCR,0x1000,12,x)
#define Rd_URT0_UARTCR_Out1(x) ReadRegBits(URT0_UARTCR,0x1000,12)
#define URT0_UARTCR_OUT1_MASK                                      0x00001000
#define URT0_UARTCR_OUT1_ALIGN                                     0
#define URT0_UARTCR_OUT1_BITS                                      1
#define URT0_UARTCR_OUT1_SHIFT                                     12

/* URT0 :: UARTCR :: RTS [11:11] */
#define Wr_URT0_UARTCR_RTS(x) WriteRegBits(URT0_UARTCR,0x800,11,x)
#define Rd_URT0_UARTCR_RTS(x) ReadRegBits(URT0_UARTCR,0x800,11)
#define URT0_UARTCR_RTS_MASK                                       0x00000800
#define URT0_UARTCR_RTS_ALIGN                                      0
#define URT0_UARTCR_RTS_BITS                                       1
#define URT0_UARTCR_RTS_SHIFT                                      11

/* URT0 :: UARTCR :: DTR [10:10] */
#define Wr_URT0_UARTCR_DTR(x) WriteRegBits(URT0_UARTCR,0x400,10,x)
#define Rd_URT0_UARTCR_DTR(x) ReadRegBits(URT0_UARTCR,0x400,10)
#define URT0_UARTCR_DTR_MASK                                       0x00000400
#define URT0_UARTCR_DTR_ALIGN                                      0
#define URT0_UARTCR_DTR_BITS                                       1
#define URT0_UARTCR_DTR_SHIFT                                      10

/* URT0 :: UARTCR :: RXE [09:09] */
#define Wr_URT0_UARTCR_RXE(x) WriteRegBits(URT0_UARTCR,0x200,9,x)
#define Rd_URT0_UARTCR_RXE(x) ReadRegBits(URT0_UARTCR,0x200,9)
#define URT0_UARTCR_RXE_MASK                                       0x00000200
#define URT0_UARTCR_RXE_ALIGN                                      0
#define URT0_UARTCR_RXE_BITS                                       1
#define URT0_UARTCR_RXE_SHIFT                                      9

/* URT0 :: UARTCR :: TXE [08:08] */
#define Wr_URT0_UARTCR_TXE(x) WriteRegBits(URT0_UARTCR,0x100,8,x)
#define Rd_URT0_UARTCR_TXE(x) ReadRegBits(URT0_UARTCR,0x100,8)
#define URT0_UARTCR_TXE_MASK                                       0x00000100
#define URT0_UARTCR_TXE_ALIGN                                      0
#define URT0_UARTCR_TXE_BITS                                       1
#define URT0_UARTCR_TXE_SHIFT                                      8

/* URT0 :: UARTCR :: LBE [07:07] */
#define Wr_URT0_UARTCR_LBE(x) WriteRegBits(URT0_UARTCR,0x80,7,x)
#define Rd_URT0_UARTCR_LBE(x) ReadRegBits(URT0_UARTCR,0x80,7)
#define URT0_UARTCR_LBE_MASK                                       0x00000080
#define URT0_UARTCR_LBE_ALIGN                                      0
#define URT0_UARTCR_LBE_BITS                                       1
#define URT0_UARTCR_LBE_SHIFT                                      7

/* URT0 :: UARTCR :: reserved2 [06:03] */
#define URT0_UARTCR_RESERVED2_MASK                                 0x00000078
#define URT0_UARTCR_RESERVED2_ALIGN                                0
#define URT0_UARTCR_RESERVED2_BITS                                 4
#define URT0_UARTCR_RESERVED2_SHIFT                                3

/* URT0 :: UARTCR :: SIRLP [02:02] */
#define Wr_URT0_UARTCR_SIRLP(x) WriteRegBits(URT0_UARTCR,0x4,2,x)
#define Rd_URT0_UARTCR_SIRLP(x) ReadRegBits(URT0_UARTCR,0x4,2)
#define URT0_UARTCR_SIRLP_MASK                                     0x00000004
#define URT0_UARTCR_SIRLP_ALIGN                                    0
#define URT0_UARTCR_SIRLP_BITS                                     1
#define URT0_UARTCR_SIRLP_SHIFT                                    2

/* URT0 :: UARTCR :: SIREN [01:01] */
#define Wr_URT0_UARTCR_SIREN(x) WriteRegBits(URT0_UARTCR,0x2,1,x)
#define Rd_URT0_UARTCR_SIREN(x) ReadRegBits(URT0_UARTCR,0x2,1)
#define URT0_UARTCR_SIREN_MASK                                     0x00000002
#define URT0_UARTCR_SIREN_ALIGN                                    0
#define URT0_UARTCR_SIREN_BITS                                     1
#define URT0_UARTCR_SIREN_SHIFT                                    1

/* URT0 :: UARTCR :: UARTEN [00:00] */
#define Wr_URT0_UARTCR_UARTEN(x) WriteRegBits(URT0_UARTCR,0x1,0,x)
#define Rd_URT0_UARTCR_UARTEN(x) ReadRegBits(URT0_UARTCR,0x1,0)
#define URT0_UARTCR_UARTEN_MASK                                    0x00000001
#define URT0_UARTCR_UARTEN_ALIGN                                   0
#define URT0_UARTCR_UARTEN_BITS                                    1
#define URT0_UARTCR_UARTEN_SHIFT                                   0


/****************************************************************************
 * URT0 :: UARTIFLS
 ***************************************************************************/
/* URT0 :: UARTIFLS :: reserved0 [31:06] */
#define URT0_UARTIFLS_RESERVED0_MASK                               0xffffffc0
#define URT0_UARTIFLS_RESERVED0_ALIGN                              0
#define URT0_UARTIFLS_RESERVED0_BITS                               26
#define URT0_UARTIFLS_RESERVED0_SHIFT                              6

/* URT0 :: UARTIFLS :: RXIFLSEL [05:03] */
#define Wr_URT0_UARTIFLS_RXIFLSEL(x) WriteRegBits(URT0_UARTIFLS,0x38,3,x)
#define Rd_URT0_UARTIFLS_RXIFLSEL(x) ReadRegBits(URT0_UARTIFLS,0x38,3)
#define URT0_UARTIFLS_RXIFLSEL_MASK                                0x00000038
#define URT0_UARTIFLS_RXIFLSEL_ALIGN                               0
#define URT0_UARTIFLS_RXIFLSEL_BITS                                3
#define URT0_UARTIFLS_RXIFLSEL_SHIFT                               3

/* URT0 :: UARTIFLS :: TXIFLSEL [02:00] */
#define Wr_URT0_UARTIFLS_TXIFLSEL(x) WriteRegBits(URT0_UARTIFLS,0x7,0,x)
#define Rd_URT0_UARTIFLS_TXIFLSEL(x) ReadRegBits(URT0_UARTIFLS,0x7,0)
#define URT0_UARTIFLS_TXIFLSEL_MASK                                0x00000007
#define URT0_UARTIFLS_TXIFLSEL_ALIGN                               0
#define URT0_UARTIFLS_TXIFLSEL_BITS                                3
#define URT0_UARTIFLS_TXIFLSEL_SHIFT                               0


/****************************************************************************
 * URT0 :: UARTIMSC
 ***************************************************************************/
/* URT0 :: UARTIMSC :: reserved0 [31:11] */
#define URT0_UARTIMSC_RESERVED0_MASK                               0xfffff800
#define URT0_UARTIMSC_RESERVED0_ALIGN                              0
#define URT0_UARTIMSC_RESERVED0_BITS                               21
#define URT0_UARTIMSC_RESERVED0_SHIFT                              11

/* URT0 :: UARTIMSC :: OEIM [10:10] */
#define Wr_URT0_UARTIMSC_OEIM(x) WriteRegBits(URT0_UARTIMSC,0x400,10,x)
#define Rd_URT0_UARTIMSC_OEIM(x) ReadRegBits(URT0_UARTIMSC,0x400,10)
#define URT0_UARTIMSC_OEIM_MASK                                    0x00000400
#define URT0_UARTIMSC_OEIM_ALIGN                                   0
#define URT0_UARTIMSC_OEIM_BITS                                    1
#define URT0_UARTIMSC_OEIM_SHIFT                                   10

/* URT0 :: UARTIMSC :: BEIM [09:09] */
#define Wr_URT0_UARTIMSC_BEIM(x) WriteRegBits(URT0_UARTIMSC,0x200,9,x)
#define Rd_URT0_UARTIMSC_BEIM(x) ReadRegBits(URT0_UARTIMSC,0x200,9)
#define URT0_UARTIMSC_BEIM_MASK                                    0x00000200
#define URT0_UARTIMSC_BEIM_ALIGN                                   0
#define URT0_UARTIMSC_BEIM_BITS                                    1
#define URT0_UARTIMSC_BEIM_SHIFT                                   9

/* URT0 :: UARTIMSC :: PEIM [08:08] */
#define Wr_URT0_UARTIMSC_PEIM(x) WriteRegBits(URT0_UARTIMSC,0x100,8,x)
#define Rd_URT0_UARTIMSC_PEIM(x) ReadRegBits(URT0_UARTIMSC,0x100,8)
#define URT0_UARTIMSC_PEIM_MASK                                    0x00000100
#define URT0_UARTIMSC_PEIM_ALIGN                                   0
#define URT0_UARTIMSC_PEIM_BITS                                    1
#define URT0_UARTIMSC_PEIM_SHIFT                                   8

/* URT0 :: UARTIMSC :: FEIM [07:07] */
#define Wr_URT0_UARTIMSC_FEIM(x) WriteRegBits(URT0_UARTIMSC,0x80,7,x)
#define Rd_URT0_UARTIMSC_FEIM(x) ReadRegBits(URT0_UARTIMSC,0x80,7)
#define URT0_UARTIMSC_FEIM_MASK                                    0x00000080
#define URT0_UARTIMSC_FEIM_ALIGN                                   0
#define URT0_UARTIMSC_FEIM_BITS                                    1
#define URT0_UARTIMSC_FEIM_SHIFT                                   7

/* URT0 :: UARTIMSC :: RTIM [06:06] */
#define Wr_URT0_UARTIMSC_RTIM(x) WriteRegBits(URT0_UARTIMSC,0x40,6,x)
#define Rd_URT0_UARTIMSC_RTIM(x) ReadRegBits(URT0_UARTIMSC,0x40,6)
#define URT0_UARTIMSC_RTIM_MASK                                    0x00000040
#define URT0_UARTIMSC_RTIM_ALIGN                                   0
#define URT0_UARTIMSC_RTIM_BITS                                    1
#define URT0_UARTIMSC_RTIM_SHIFT                                   6

/* URT0 :: UARTIMSC :: TXIM [05:05] */
#define Wr_URT0_UARTIMSC_TXIM(x) WriteRegBits(URT0_UARTIMSC,0x20,5,x)
#define Rd_URT0_UARTIMSC_TXIM(x) ReadRegBits(URT0_UARTIMSC,0x20,5)
#define URT0_UARTIMSC_TXIM_MASK                                    0x00000020
#define URT0_UARTIMSC_TXIM_ALIGN                                   0
#define URT0_UARTIMSC_TXIM_BITS                                    1
#define URT0_UARTIMSC_TXIM_SHIFT                                   5

/* URT0 :: UARTIMSC :: RXIM [04:04] */
#define Wr_URT0_UARTIMSC_RXIM(x) WriteRegBits(URT0_UARTIMSC,0x10,4,x)
#define Rd_URT0_UARTIMSC_RXIM(x) ReadRegBits(URT0_UARTIMSC,0x10,4)
#define URT0_UARTIMSC_RXIM_MASK                                    0x00000010
#define URT0_UARTIMSC_RXIM_ALIGN                                   0
#define URT0_UARTIMSC_RXIM_BITS                                    1
#define URT0_UARTIMSC_RXIM_SHIFT                                   4

/* URT0 :: UARTIMSC :: DSRMIM [03:03] */
#define Wr_URT0_UARTIMSC_DSRMIM(x) WriteRegBits(URT0_UARTIMSC,0x8,3,x)
#define Rd_URT0_UARTIMSC_DSRMIM(x) ReadRegBits(URT0_UARTIMSC,0x8,3)
#define URT0_UARTIMSC_DSRMIM_MASK                                  0x00000008
#define URT0_UARTIMSC_DSRMIM_ALIGN                                 0
#define URT0_UARTIMSC_DSRMIM_BITS                                  1
#define URT0_UARTIMSC_DSRMIM_SHIFT                                 3

/* URT0 :: UARTIMSC :: DCDMIM [02:02] */
#define Wr_URT0_UARTIMSC_DCDMIM(x) WriteRegBits(URT0_UARTIMSC,0x4,2,x)
#define Rd_URT0_UARTIMSC_DCDMIM(x) ReadRegBits(URT0_UARTIMSC,0x4,2)
#define URT0_UARTIMSC_DCDMIM_MASK                                  0x00000004
#define URT0_UARTIMSC_DCDMIM_ALIGN                                 0
#define URT0_UARTIMSC_DCDMIM_BITS                                  1
#define URT0_UARTIMSC_DCDMIM_SHIFT                                 2

/* URT0 :: UARTIMSC :: CTSMIM [01:01] */
#define Wr_URT0_UARTIMSC_CTSMIM(x) WriteRegBits(URT0_UARTIMSC,0x2,1,x)
#define Rd_URT0_UARTIMSC_CTSMIM(x) ReadRegBits(URT0_UARTIMSC,0x2,1)
#define URT0_UARTIMSC_CTSMIM_MASK                                  0x00000002
#define URT0_UARTIMSC_CTSMIM_ALIGN                                 0
#define URT0_UARTIMSC_CTSMIM_BITS                                  1
#define URT0_UARTIMSC_CTSMIM_SHIFT                                 1

/* URT0 :: UARTIMSC :: RIMIM [00:00] */
#define Wr_URT0_UARTIMSC_RIMIM(x) WriteRegBits(URT0_UARTIMSC,0x1,0,x)
#define Rd_URT0_UARTIMSC_RIMIM(x) ReadRegBits(URT0_UARTIMSC,0x1,0)
#define URT0_UARTIMSC_RIMIM_MASK                                   0x00000001
#define URT0_UARTIMSC_RIMIM_ALIGN                                  0
#define URT0_UARTIMSC_RIMIM_BITS                                   1
#define URT0_UARTIMSC_RIMIM_SHIFT                                  0


/****************************************************************************
 * URT0 :: UARTRIS
 ***************************************************************************/
/* URT0 :: UARTRIS :: reserved0 [31:11] */
#define URT0_UARTRIS_RESERVED0_MASK                                0xfffff800
#define URT0_UARTRIS_RESERVED0_ALIGN                               0
#define URT0_UARTRIS_RESERVED0_BITS                                21
#define URT0_UARTRIS_RESERVED0_SHIFT                               11

/* URT0 :: UARTRIS :: OERIS [10:10] */
#define Wr_URT0_UARTRIS_OERIS(x) WriteRegBits(URT0_UARTRIS,0x400,10,x)
#define Rd_URT0_UARTRIS_OERIS(x) ReadRegBits(URT0_UARTRIS,0x400,10)
#define URT0_UARTRIS_OERIS_MASK                                    0x00000400
#define URT0_UARTRIS_OERIS_ALIGN                                   0
#define URT0_UARTRIS_OERIS_BITS                                    1
#define URT0_UARTRIS_OERIS_SHIFT                                   10

/* URT0 :: UARTRIS :: BERIS [09:09] */
#define Wr_URT0_UARTRIS_BERIS(x) WriteRegBits(URT0_UARTRIS,0x200,9,x)
#define Rd_URT0_UARTRIS_BERIS(x) ReadRegBits(URT0_UARTRIS,0x200,9)
#define URT0_UARTRIS_BERIS_MASK                                    0x00000200
#define URT0_UARTRIS_BERIS_ALIGN                                   0
#define URT0_UARTRIS_BERIS_BITS                                    1
#define URT0_UARTRIS_BERIS_SHIFT                                   9

/* URT0 :: UARTRIS :: PERIS [08:08] */
#define Wr_URT0_UARTRIS_PERIS(x) WriteRegBits(URT0_UARTRIS,0x100,8,x)
#define Rd_URT0_UARTRIS_PERIS(x) ReadRegBits(URT0_UARTRIS,0x100,8)
#define URT0_UARTRIS_PERIS_MASK                                    0x00000100
#define URT0_UARTRIS_PERIS_ALIGN                                   0
#define URT0_UARTRIS_PERIS_BITS                                    1
#define URT0_UARTRIS_PERIS_SHIFT                                   8

/* URT0 :: UARTRIS :: FERIS [07:07] */
#define Wr_URT0_UARTRIS_FERIS(x) WriteRegBits(URT0_UARTRIS,0x80,7,x)
#define Rd_URT0_UARTRIS_FERIS(x) ReadRegBits(URT0_UARTRIS,0x80,7)
#define URT0_UARTRIS_FERIS_MASK                                    0x00000080
#define URT0_UARTRIS_FERIS_ALIGN                                   0
#define URT0_UARTRIS_FERIS_BITS                                    1
#define URT0_UARTRIS_FERIS_SHIFT                                   7

/* URT0 :: UARTRIS :: RTRIS [06:06] */
#define Wr_URT0_UARTRIS_RTRIS(x) WriteRegBits(URT0_UARTRIS,0x40,6,x)
#define Rd_URT0_UARTRIS_RTRIS(x) ReadRegBits(URT0_UARTRIS,0x40,6)
#define URT0_UARTRIS_RTRIS_MASK                                    0x00000040
#define URT0_UARTRIS_RTRIS_ALIGN                                   0
#define URT0_UARTRIS_RTRIS_BITS                                    1
#define URT0_UARTRIS_RTRIS_SHIFT                                   6

/* URT0 :: UARTRIS :: TXRIS [05:05] */
#define Wr_URT0_UARTRIS_TXRIS(x) WriteRegBits(URT0_UARTRIS,0x20,5,x)
#define Rd_URT0_UARTRIS_TXRIS(x) ReadRegBits(URT0_UARTRIS,0x20,5)
#define URT0_UARTRIS_TXRIS_MASK                                    0x00000020
#define URT0_UARTRIS_TXRIS_ALIGN                                   0
#define URT0_UARTRIS_TXRIS_BITS                                    1
#define URT0_UARTRIS_TXRIS_SHIFT                                   5

/* URT0 :: UARTRIS :: RXRIS [04:04] */
#define Wr_URT0_UARTRIS_RXRIS(x) WriteRegBits(URT0_UARTRIS,0x10,4,x)
#define Rd_URT0_UARTRIS_RXRIS(x) ReadRegBits(URT0_UARTRIS,0x10,4)
#define URT0_UARTRIS_RXRIS_MASK                                    0x00000010
#define URT0_UARTRIS_RXRIS_ALIGN                                   0
#define URT0_UARTRIS_RXRIS_BITS                                    1
#define URT0_UARTRIS_RXRIS_SHIFT                                   4

/* URT0 :: UARTRIS :: DSRRMIS [03:03] */
#define Wr_URT0_UARTRIS_DSRRMIS(x) WriteRegBits(URT0_UARTRIS,0x8,3,x)
#define Rd_URT0_UARTRIS_DSRRMIS(x) ReadRegBits(URT0_UARTRIS,0x8,3)
#define URT0_UARTRIS_DSRRMIS_MASK                                  0x00000008
#define URT0_UARTRIS_DSRRMIS_ALIGN                                 0
#define URT0_UARTRIS_DSRRMIS_BITS                                  1
#define URT0_UARTRIS_DSRRMIS_SHIFT                                 3

/* URT0 :: UARTRIS :: DCDRMIS [02:02] */
#define Wr_URT0_UARTRIS_DCDRMIS(x) WriteRegBits(URT0_UARTRIS,0x4,2,x)
#define Rd_URT0_UARTRIS_DCDRMIS(x) ReadRegBits(URT0_UARTRIS,0x4,2)
#define URT0_UARTRIS_DCDRMIS_MASK                                  0x00000004
#define URT0_UARTRIS_DCDRMIS_ALIGN                                 0
#define URT0_UARTRIS_DCDRMIS_BITS                                  1
#define URT0_UARTRIS_DCDRMIS_SHIFT                                 2

/* URT0 :: UARTRIS :: CTSRMIS [01:01] */
#define Wr_URT0_UARTRIS_CTSRMIS(x) WriteRegBits(URT0_UARTRIS,0x2,1,x)
#define Rd_URT0_UARTRIS_CTSRMIS(x) ReadRegBits(URT0_UARTRIS,0x2,1)
#define URT0_UARTRIS_CTSRMIS_MASK                                  0x00000002
#define URT0_UARTRIS_CTSRMIS_ALIGN                                 0
#define URT0_UARTRIS_CTSRMIS_BITS                                  1
#define URT0_UARTRIS_CTSRMIS_SHIFT                                 1

/* URT0 :: UARTRIS :: RIRMIS [00:00] */
#define Wr_URT0_UARTRIS_RIRMIS(x) WriteRegBits(URT0_UARTRIS,0x1,0,x)
#define Rd_URT0_UARTRIS_RIRMIS(x) ReadRegBits(URT0_UARTRIS,0x1,0)
#define URT0_UARTRIS_RIRMIS_MASK                                   0x00000001
#define URT0_UARTRIS_RIRMIS_ALIGN                                  0
#define URT0_UARTRIS_RIRMIS_BITS                                   1
#define URT0_UARTRIS_RIRMIS_SHIFT                                  0


/****************************************************************************
 * URT0 :: UARTMIS
 ***************************************************************************/
/* URT0 :: UARTMIS :: reserved0 [31:11] */
#define URT0_UARTMIS_RESERVED0_MASK                                0xfffff800
#define URT0_UARTMIS_RESERVED0_ALIGN                               0
#define URT0_UARTMIS_RESERVED0_BITS                                21
#define URT0_UARTMIS_RESERVED0_SHIFT                               11

/* URT0 :: UARTMIS :: OEMIS [10:10] */
#define Wr_URT0_UARTMIS_OEMIS(x) WriteRegBits(URT0_UARTMIS,0x400,10,x)
#define Rd_URT0_UARTMIS_OEMIS(x) ReadRegBits(URT0_UARTMIS,0x400,10)
#define URT0_UARTMIS_OEMIS_MASK                                    0x00000400
#define URT0_UARTMIS_OEMIS_ALIGN                                   0
#define URT0_UARTMIS_OEMIS_BITS                                    1
#define URT0_UARTMIS_OEMIS_SHIFT                                   10

/* URT0 :: UARTMIS :: BEMIS [09:09] */
#define Wr_URT0_UARTMIS_BEMIS(x) WriteRegBits(URT0_UARTMIS,0x200,9,x)
#define Rd_URT0_UARTMIS_BEMIS(x) ReadRegBits(URT0_UARTMIS,0x200,9)
#define URT0_UARTMIS_BEMIS_MASK                                    0x00000200
#define URT0_UARTMIS_BEMIS_ALIGN                                   0
#define URT0_UARTMIS_BEMIS_BITS                                    1
#define URT0_UARTMIS_BEMIS_SHIFT                                   9

/* URT0 :: UARTMIS :: PEMIS [08:08] */
#define Wr_URT0_UARTMIS_PEMIS(x) WriteRegBits(URT0_UARTMIS,0x100,8,x)
#define Rd_URT0_UARTMIS_PEMIS(x) ReadRegBits(URT0_UARTMIS,0x100,8)
#define URT0_UARTMIS_PEMIS_MASK                                    0x00000100
#define URT0_UARTMIS_PEMIS_ALIGN                                   0
#define URT0_UARTMIS_PEMIS_BITS                                    1
#define URT0_UARTMIS_PEMIS_SHIFT                                   8

/* URT0 :: UARTMIS :: FEMIS [07:07] */
#define Wr_URT0_UARTMIS_FEMIS(x) WriteRegBits(URT0_UARTMIS,0x80,7,x)
#define Rd_URT0_UARTMIS_FEMIS(x) ReadRegBits(URT0_UARTMIS,0x80,7)
#define URT0_UARTMIS_FEMIS_MASK                                    0x00000080
#define URT0_UARTMIS_FEMIS_ALIGN                                   0
#define URT0_UARTMIS_FEMIS_BITS                                    1
#define URT0_UARTMIS_FEMIS_SHIFT                                   7

/* URT0 :: UARTMIS :: RTMIS [06:06] */
#define Wr_URT0_UARTMIS_RTMIS(x) WriteRegBits(URT0_UARTMIS,0x40,6,x)
#define Rd_URT0_UARTMIS_RTMIS(x) ReadRegBits(URT0_UARTMIS,0x40,6)
#define URT0_UARTMIS_RTMIS_MASK                                    0x00000040
#define URT0_UARTMIS_RTMIS_ALIGN                                   0
#define URT0_UARTMIS_RTMIS_BITS                                    1
#define URT0_UARTMIS_RTMIS_SHIFT                                   6

/* URT0 :: UARTMIS :: TXMIS [05:05] */
#define Wr_URT0_UARTMIS_TXMIS(x) WriteRegBits(URT0_UARTMIS,0x20,5,x)
#define Rd_URT0_UARTMIS_TXMIS(x) ReadRegBits(URT0_UARTMIS,0x20,5)
#define URT0_UARTMIS_TXMIS_MASK                                    0x00000020
#define URT0_UARTMIS_TXMIS_ALIGN                                   0
#define URT0_UARTMIS_TXMIS_BITS                                    1
#define URT0_UARTMIS_TXMIS_SHIFT                                   5

/* URT0 :: UARTMIS :: RXMIS [04:04] */
#define Wr_URT0_UARTMIS_RXMIS(x) WriteRegBits(URT0_UARTMIS,0x10,4,x)
#define Rd_URT0_UARTMIS_RXMIS(x) ReadRegBits(URT0_UARTMIS,0x10,4)
#define URT0_UARTMIS_RXMIS_MASK                                    0x00000010
#define URT0_UARTMIS_RXMIS_ALIGN                                   0
#define URT0_UARTMIS_RXMIS_BITS                                    1
#define URT0_UARTMIS_RXMIS_SHIFT                                   4

/* URT0 :: UARTMIS :: DSRMMIS [03:03] */
#define Wr_URT0_UARTMIS_DSRMMIS(x) WriteRegBits(URT0_UARTMIS,0x8,3,x)
#define Rd_URT0_UARTMIS_DSRMMIS(x) ReadRegBits(URT0_UARTMIS,0x8,3)
#define URT0_UARTMIS_DSRMMIS_MASK                                  0x00000008
#define URT0_UARTMIS_DSRMMIS_ALIGN                                 0
#define URT0_UARTMIS_DSRMMIS_BITS                                  1
#define URT0_UARTMIS_DSRMMIS_SHIFT                                 3

/* URT0 :: UARTMIS :: DCDMMIS [02:02] */
#define Wr_URT0_UARTMIS_DCDMMIS(x) WriteRegBits(URT0_UARTMIS,0x4,2,x)
#define Rd_URT0_UARTMIS_DCDMMIS(x) ReadRegBits(URT0_UARTMIS,0x4,2)
#define URT0_UARTMIS_DCDMMIS_MASK                                  0x00000004
#define URT0_UARTMIS_DCDMMIS_ALIGN                                 0
#define URT0_UARTMIS_DCDMMIS_BITS                                  1
#define URT0_UARTMIS_DCDMMIS_SHIFT                                 2

/* URT0 :: UARTMIS :: CTSMMIS [01:01] */
#define Wr_URT0_UARTMIS_CTSMMIS(x) WriteRegBits(URT0_UARTMIS,0x2,1,x)
#define Rd_URT0_UARTMIS_CTSMMIS(x) ReadRegBits(URT0_UARTMIS,0x2,1)
#define URT0_UARTMIS_CTSMMIS_MASK                                  0x00000002
#define URT0_UARTMIS_CTSMMIS_ALIGN                                 0
#define URT0_UARTMIS_CTSMMIS_BITS                                  1
#define URT0_UARTMIS_CTSMMIS_SHIFT                                 1

/* URT0 :: UARTMIS :: RIMMIS [00:00] */
#define Wr_URT0_UARTMIS_RIMMIS(x) WriteRegBits(URT0_UARTMIS,0x1,0,x)
#define Rd_URT0_UARTMIS_RIMMIS(x) ReadRegBits(URT0_UARTMIS,0x1,0)
#define URT0_UARTMIS_RIMMIS_MASK                                   0x00000001
#define URT0_UARTMIS_RIMMIS_ALIGN                                  0
#define URT0_UARTMIS_RIMMIS_BITS                                   1
#define URT0_UARTMIS_RIMMIS_SHIFT                                  0


/****************************************************************************
 * URT0 :: UARTICR
 ***************************************************************************/
/* URT0 :: UARTICR :: reserved0 [31:11] */
#define URT0_UARTICR_RESERVED0_MASK                                0xfffff800
#define URT0_UARTICR_RESERVED0_ALIGN                               0
#define URT0_UARTICR_RESERVED0_BITS                                21
#define URT0_UARTICR_RESERVED0_SHIFT                               11

/* URT0 :: UARTICR :: OEIC [10:10] */
#define Wr_URT0_UARTICR_OEIC(x) WriteRegBits(URT0_UARTICR,0x400,10,x)
#define Rd_URT0_UARTICR_OEIC(x) ReadRegBits(URT0_UARTICR,0x400,10)
#define URT0_UARTICR_OEIC_MASK                                     0x00000400
#define URT0_UARTICR_OEIC_ALIGN                                    0
#define URT0_UARTICR_OEIC_BITS                                     1
#define URT0_UARTICR_OEIC_SHIFT                                    10

/* URT0 :: UARTICR :: BEIC [09:09] */
#define Wr_URT0_UARTICR_BEIC(x) WriteRegBits(URT0_UARTICR,0x200,9,x)
#define Rd_URT0_UARTICR_BEIC(x) ReadRegBits(URT0_UARTICR,0x200,9)
#define URT0_UARTICR_BEIC_MASK                                     0x00000200
#define URT0_UARTICR_BEIC_ALIGN                                    0
#define URT0_UARTICR_BEIC_BITS                                     1
#define URT0_UARTICR_BEIC_SHIFT                                    9

/* URT0 :: UARTICR :: PEIC [08:08] */
#define Wr_URT0_UARTICR_PEIC(x) WriteRegBits(URT0_UARTICR,0x100,8,x)
#define Rd_URT0_UARTICR_PEIC(x) ReadRegBits(URT0_UARTICR,0x100,8)
#define URT0_UARTICR_PEIC_MASK                                     0x00000100
#define URT0_UARTICR_PEIC_ALIGN                                    0
#define URT0_UARTICR_PEIC_BITS                                     1
#define URT0_UARTICR_PEIC_SHIFT                                    8

/* URT0 :: UARTICR :: FEIC [07:07] */
#define Wr_URT0_UARTICR_FEIC(x) WriteRegBits(URT0_UARTICR,0x80,7,x)
#define Rd_URT0_UARTICR_FEIC(x) ReadRegBits(URT0_UARTICR,0x80,7)
#define URT0_UARTICR_FEIC_MASK                                     0x00000080
#define URT0_UARTICR_FEIC_ALIGN                                    0
#define URT0_UARTICR_FEIC_BITS                                     1
#define URT0_UARTICR_FEIC_SHIFT                                    7

/* URT0 :: UARTICR :: RTIC [06:06] */
#define Wr_URT0_UARTICR_RTIC(x) WriteRegBits(URT0_UARTICR,0x40,6,x)
#define Rd_URT0_UARTICR_RTIC(x) ReadRegBits(URT0_UARTICR,0x40,6)
#define URT0_UARTICR_RTIC_MASK                                     0x00000040
#define URT0_UARTICR_RTIC_ALIGN                                    0
#define URT0_UARTICR_RTIC_BITS                                     1
#define URT0_UARTICR_RTIC_SHIFT                                    6

/* URT0 :: UARTICR :: TXIC [05:05] */
#define Wr_URT0_UARTICR_TXIC(x) WriteRegBits(URT0_UARTICR,0x20,5,x)
#define Rd_URT0_UARTICR_TXIC(x) ReadRegBits(URT0_UARTICR,0x20,5)
#define URT0_UARTICR_TXIC_MASK                                     0x00000020
#define URT0_UARTICR_TXIC_ALIGN                                    0
#define URT0_UARTICR_TXIC_BITS                                     1
#define URT0_UARTICR_TXIC_SHIFT                                    5

/* URT0 :: UARTICR :: RXIC [04:04] */
#define Wr_URT0_UARTICR_RXIC(x) WriteRegBits(URT0_UARTICR,0x10,4,x)
#define Rd_URT0_UARTICR_RXIC(x) ReadRegBits(URT0_UARTICR,0x10,4)
#define URT0_UARTICR_RXIC_MASK                                     0x00000010
#define URT0_UARTICR_RXIC_ALIGN                                    0
#define URT0_UARTICR_RXIC_BITS                                     1
#define URT0_UARTICR_RXIC_SHIFT                                    4

/* URT0 :: UARTICR :: DSRMIC [03:03] */
#define Wr_URT0_UARTICR_DSRMIC(x) WriteRegBits(URT0_UARTICR,0x8,3,x)
#define Rd_URT0_UARTICR_DSRMIC(x) ReadRegBits(URT0_UARTICR,0x8,3)
#define URT0_UARTICR_DSRMIC_MASK                                   0x00000008
#define URT0_UARTICR_DSRMIC_ALIGN                                  0
#define URT0_UARTICR_DSRMIC_BITS                                   1
#define URT0_UARTICR_DSRMIC_SHIFT                                  3

/* URT0 :: UARTICR :: DCDMIC [02:02] */
#define Wr_URT0_UARTICR_DCDMIC(x) WriteRegBits(URT0_UARTICR,0x4,2,x)
#define Rd_URT0_UARTICR_DCDMIC(x) ReadRegBits(URT0_UARTICR,0x4,2)
#define URT0_UARTICR_DCDMIC_MASK                                   0x00000004
#define URT0_UARTICR_DCDMIC_ALIGN                                  0
#define URT0_UARTICR_DCDMIC_BITS                                   1
#define URT0_UARTICR_DCDMIC_SHIFT                                  2

/* URT0 :: UARTICR :: CTSMIC [01:01] */
#define Wr_URT0_UARTICR_CTSMIC(x) WriteRegBits(URT0_UARTICR,0x2,1,x)
#define Rd_URT0_UARTICR_CTSMIC(x) ReadRegBits(URT0_UARTICR,0x2,1)
#define URT0_UARTICR_CTSMIC_MASK                                   0x00000002
#define URT0_UARTICR_CTSMIC_ALIGN                                  0
#define URT0_UARTICR_CTSMIC_BITS                                   1
#define URT0_UARTICR_CTSMIC_SHIFT                                  1

/* URT0 :: UARTICR :: RIMIC [00:00] */
#define Wr_URT0_UARTICR_RIMIC(x) WriteRegBits(URT0_UARTICR,0x1,0,x)
#define Rd_URT0_UARTICR_RIMIC(x) ReadRegBits(URT0_UARTICR,0x1,0)
#define URT0_UARTICR_RIMIC_MASK                                    0x00000001
#define URT0_UARTICR_RIMIC_ALIGN                                   0
#define URT0_UARTICR_RIMIC_BITS                                    1
#define URT0_UARTICR_RIMIC_SHIFT                                   0


/****************************************************************************
 * URT0 :: UARTDMACR
 ***************************************************************************/
/* URT0 :: UARTDMACR :: reserved0 [31:03] */
#define URT0_UARTDMACR_RESERVED0_MASK                              0xfffffff8
#define URT0_UARTDMACR_RESERVED0_ALIGN                             0
#define URT0_UARTDMACR_RESERVED0_BITS                              29
#define URT0_UARTDMACR_RESERVED0_SHIFT                             3

/* URT0 :: UARTDMACR :: DMAONERR [02:02] */
#define Wr_URT0_UARTDMACR_DMAONERR(x) WriteRegBits(URT0_UARTDMACR,0x4,2,x)
#define Rd_URT0_UARTDMACR_DMAONERR(x) ReadRegBits(URT0_UARTDMACR,0x4,2)
#define URT0_UARTDMACR_DMAONERR_MASK                               0x00000004
#define URT0_UARTDMACR_DMAONERR_ALIGN                              0
#define URT0_UARTDMACR_DMAONERR_BITS                               1
#define URT0_UARTDMACR_DMAONERR_SHIFT                              2

/* URT0 :: UARTDMACR :: TXDMAE [01:01] */
#define Wr_URT0_UARTDMACR_TXDMAE(x) WriteRegBits(URT0_UARTDMACR,0x2,1,x)
#define Rd_URT0_UARTDMACR_TXDMAE(x) ReadRegBits(URT0_UARTDMACR,0x2,1)
#define URT0_UARTDMACR_TXDMAE_MASK                                 0x00000002
#define URT0_UARTDMACR_TXDMAE_ALIGN                                0
#define URT0_UARTDMACR_TXDMAE_BITS                                 1
#define URT0_UARTDMACR_TXDMAE_SHIFT                                1

/* URT0 :: UARTDMACR :: RXDMAE [00:00] */
#define Wr_URT0_UARTDMACR_RXDMAE(x) WriteRegBits(URT0_UARTDMACR,0x1,0,x)
#define Rd_URT0_UARTDMACR_RXDMAE(x) ReadRegBits(URT0_UARTDMACR,0x1,0)
#define URT0_UARTDMACR_RXDMAE_MASK                                 0x00000001
#define URT0_UARTDMACR_RXDMAE_ALIGN                                0
#define URT0_UARTDMACR_RXDMAE_BITS                                 1
#define URT0_UARTDMACR_RXDMAE_SHIFT                                0


/****************************************************************************
 * URT0 :: UARTPeriphID0
 ***************************************************************************/
/* URT0 :: UARTPeriphID0 :: reserved0 [31:08] */
#define URT0_UARTPERIPHID0_RESERVED0_MASK                          0xffffff00
#define URT0_UARTPERIPHID0_RESERVED0_ALIGN                         0
#define URT0_UARTPERIPHID0_RESERVED0_BITS                          24
#define URT0_UARTPERIPHID0_RESERVED0_SHIFT                         8

/* URT0 :: UARTPeriphID0 :: PartNumber0 [07:00] */
#define Wr_URT0_UARTPeriphID0_PartNumber0(x) WriteRegBits(URT0_UARTPERIPHID0,0xff,0,x)
#define Rd_URT0_UARTPeriphID0_PartNumber0(x) ReadRegBits(URT0_UARTPERIPHID0,0xff,0)
#define URT0_UARTPERIPHID0_PARTNUMBER0_MASK                        0x000000ff
#define URT0_UARTPERIPHID0_PARTNUMBER0_ALIGN                       0
#define URT0_UARTPERIPHID0_PARTNUMBER0_BITS                        8
#define URT0_UARTPERIPHID0_PARTNUMBER0_SHIFT                       0


/****************************************************************************
 * URT0 :: UARTPeriphID1
 ***************************************************************************/
/* URT0 :: UARTPeriphID1 :: reserved0 [31:08] */
#define URT0_UARTPERIPHID1_RESERVED0_MASK                          0xffffff00
#define URT0_UARTPERIPHID1_RESERVED0_ALIGN                         0
#define URT0_UARTPERIPHID1_RESERVED0_BITS                          24
#define URT0_UARTPERIPHID1_RESERVED0_SHIFT                         8

/* URT0 :: UARTPeriphID1 :: Designer0 [07:04] */
#define Wr_URT0_UARTPeriphID1_Designer0(x) WriteRegBits(URT0_UARTPERIPHID1,0xf0,4,x)
#define Rd_URT0_UARTPeriphID1_Designer0(x) ReadRegBits(URT0_UARTPERIPHID1,0xf0,4)
#define URT0_UARTPERIPHID1_DESIGNER0_MASK                          0x000000f0
#define URT0_UARTPERIPHID1_DESIGNER0_ALIGN                         0
#define URT0_UARTPERIPHID1_DESIGNER0_BITS                          4
#define URT0_UARTPERIPHID1_DESIGNER0_SHIFT                         4

/* URT0 :: UARTPeriphID1 :: PartNumber1 [03:00] */
#define Wr_URT0_UARTPeriphID1_PartNumber1(x) WriteRegBits(URT0_UARTPERIPHID1,0xf,0,x)
#define Rd_URT0_UARTPeriphID1_PartNumber1(x) ReadRegBits(URT0_UARTPERIPHID1,0xf,0)
#define URT0_UARTPERIPHID1_PARTNUMBER1_MASK                        0x0000000f
#define URT0_UARTPERIPHID1_PARTNUMBER1_ALIGN                       0
#define URT0_UARTPERIPHID1_PARTNUMBER1_BITS                        4
#define URT0_UARTPERIPHID1_PARTNUMBER1_SHIFT                       0


/****************************************************************************
 * URT0 :: UARTPeriphID2
 ***************************************************************************/
/* URT0 :: UARTPeriphID2 :: reserved0 [31:08] */
#define URT0_UARTPERIPHID2_RESERVED0_MASK                          0xffffff00
#define URT0_UARTPERIPHID2_RESERVED0_ALIGN                         0
#define URT0_UARTPERIPHID2_RESERVED0_BITS                          24
#define URT0_UARTPERIPHID2_RESERVED0_SHIFT                         8

/* URT0 :: UARTPeriphID2 :: Revision [07:04] */
#define Wr_URT0_UARTPeriphID2_Revision(x) WriteRegBits(URT0_UARTPERIPHID2,0xf0,4,x)
#define Rd_URT0_UARTPeriphID2_Revision(x) ReadRegBits(URT0_UARTPERIPHID2,0xf0,4)
#define URT0_UARTPERIPHID2_REVISION_MASK                           0x000000f0
#define URT0_UARTPERIPHID2_REVISION_ALIGN                          0
#define URT0_UARTPERIPHID2_REVISION_BITS                           4
#define URT0_UARTPERIPHID2_REVISION_SHIFT                          4

/* URT0 :: UARTPeriphID2 :: Designer1 [03:00] */
#define Wr_URT0_UARTPeriphID2_Designer1(x) WriteRegBits(URT0_UARTPERIPHID2,0xf,0,x)
#define Rd_URT0_UARTPeriphID2_Designer1(x) ReadRegBits(URT0_UARTPERIPHID2,0xf,0)
#define URT0_UARTPERIPHID2_DESIGNER1_MASK                          0x0000000f
#define URT0_UARTPERIPHID2_DESIGNER1_ALIGN                         0
#define URT0_UARTPERIPHID2_DESIGNER1_BITS                          4
#define URT0_UARTPERIPHID2_DESIGNER1_SHIFT                         0


/****************************************************************************
 * URT0 :: UARTPeriphID3
 ***************************************************************************/
/* URT0 :: UARTPeriphID3 :: reserved0 [31:08] */
#define URT0_UARTPERIPHID3_RESERVED0_MASK                          0xffffff00
#define URT0_UARTPERIPHID3_RESERVED0_ALIGN                         0
#define URT0_UARTPERIPHID3_RESERVED0_BITS                          24
#define URT0_UARTPERIPHID3_RESERVED0_SHIFT                         8

/* URT0 :: UARTPeriphID3 :: Configuration [07:00] */
#define Wr_URT0_UARTPeriphID3_Configuration(x) WriteRegBits(URT0_UARTPERIPHID3,0xff,0,x)
#define Rd_URT0_UARTPeriphID3_Configuration(x) ReadRegBits(URT0_UARTPERIPHID3,0xff,0)
#define URT0_UARTPERIPHID3_CONFIGURATION_MASK                      0x000000ff
#define URT0_UARTPERIPHID3_CONFIGURATION_ALIGN                     0
#define URT0_UARTPERIPHID3_CONFIGURATION_BITS                      8
#define URT0_UARTPERIPHID3_CONFIGURATION_SHIFT                     0


/****************************************************************************
 * URT0 :: UARTPCellID0
 ***************************************************************************/
/* URT0 :: UARTPCellID0 :: reserved0 [31:08] */
#define URT0_UARTPCELLID0_RESERVED0_MASK                           0xffffff00
#define URT0_UARTPCELLID0_RESERVED0_ALIGN                          0
#define URT0_UARTPCELLID0_RESERVED0_BITS                           24
#define URT0_UARTPCELLID0_RESERVED0_SHIFT                          8

/* URT0 :: UARTPCellID0 :: UARTPCellID0 [07:00] */
#define Wr_URT0_UARTPCellID0_UARTPCellID0(x) WriteRegBits(URT0_UARTPCELLID0,0xff,0,x)
#define Rd_URT0_UARTPCellID0_UARTPCellID0(x) ReadRegBits(URT0_UARTPCELLID0,0xff,0)
#define URT0_UARTPCELLID0_UARTPCELLID0_MASK                        0x000000ff
#define URT0_UARTPCELLID0_UARTPCELLID0_ALIGN                       0
#define URT0_UARTPCELLID0_UARTPCELLID0_BITS                        8
#define URT0_UARTPCELLID0_UARTPCELLID0_SHIFT                       0


/****************************************************************************
 * URT0 :: UARTPCellID1
 ***************************************************************************/
/* URT0 :: UARTPCellID1 :: reserved0 [31:08] */
#define URT0_UARTPCELLID1_RESERVED0_MASK                           0xffffff00
#define URT0_UARTPCELLID1_RESERVED0_ALIGN                          0
#define URT0_UARTPCELLID1_RESERVED0_BITS                           24
#define URT0_UARTPCELLID1_RESERVED0_SHIFT                          8

/* URT0 :: UARTPCellID1 :: UARTPCellID1 [07:00] */
#define Wr_URT0_UARTPCellID1_UARTPCellID1(x) WriteRegBits(URT0_UARTPCELLID1,0xff,0,x)
#define Rd_URT0_UARTPCellID1_UARTPCellID1(x) ReadRegBits(URT0_UARTPCELLID1,0xff,0)
#define URT0_UARTPCELLID1_UARTPCELLID1_MASK                        0x000000ff
#define URT0_UARTPCELLID1_UARTPCELLID1_ALIGN                       0
#define URT0_UARTPCELLID1_UARTPCELLID1_BITS                        8
#define URT0_UARTPCELLID1_UARTPCELLID1_SHIFT                       0


/****************************************************************************
 * URT0 :: UARTPCellID2
 ***************************************************************************/
/* URT0 :: UARTPCellID2 :: reserved0 [31:08] */
#define URT0_UARTPCELLID2_RESERVED0_MASK                           0xffffff00
#define URT0_UARTPCELLID2_RESERVED0_ALIGN                          0
#define URT0_UARTPCELLID2_RESERVED0_BITS                           24
#define URT0_UARTPCELLID2_RESERVED0_SHIFT                          8

/* URT0 :: UARTPCellID2 :: UARTPCellID2 [07:00] */
#define Wr_URT0_UARTPCellID2_UARTPCellID2(x) WriteRegBits(URT0_UARTPCELLID2,0xff,0,x)
#define Rd_URT0_UARTPCellID2_UARTPCellID2(x) ReadRegBits(URT0_UARTPCELLID2,0xff,0)
#define URT0_UARTPCELLID2_UARTPCELLID2_MASK                        0x000000ff
#define URT0_UARTPCELLID2_UARTPCELLID2_ALIGN                       0
#define URT0_UARTPCELLID2_UARTPCELLID2_BITS                        8
#define URT0_UARTPCELLID2_UARTPCELLID2_SHIFT                       0


/****************************************************************************
 * URT0 :: UARTPCellID3
 ***************************************************************************/
/* URT0 :: UARTPCellID3 :: reserved0 [31:08] */
#define URT0_UARTPCELLID3_RESERVED0_MASK                           0xffffff00
#define URT0_UARTPCELLID3_RESERVED0_ALIGN                          0
#define URT0_UARTPCELLID3_RESERVED0_BITS                           24
#define URT0_UARTPCELLID3_RESERVED0_SHIFT                          8

/* URT0 :: UARTPCellID3 :: UARTPCellID3 [07:00] */
#define Wr_URT0_UARTPCellID3_UARTPCellID3(x) WriteRegBits(URT0_UARTPCELLID3,0xff,0,x)
#define Rd_URT0_UARTPCellID3_UARTPCellID3(x) ReadRegBits(URT0_UARTPCELLID3,0xff,0)
#define URT0_UARTPCELLID3_UARTPCELLID3_MASK                        0x000000ff
#define URT0_UARTPCELLID3_UARTPCELLID3_ALIGN                       0
#define URT0_UARTPCELLID3_UARTPCELLID3_BITS                        8
#define URT0_UARTPCELLID3_UARTPCELLID3_SHIFT                       0


/****************************************************************************
 * bcm89530_sys_cfg_SPI0
 ***************************************************************************/
/****************************************************************************
 * SPI0 :: SSPCR0
 ***************************************************************************/
/* SPI0 :: SSPCR0 :: reserved0 [31:16] */
#define SPI0_SSPCR0_RESERVED0_MASK                                 0xffff0000
#define SPI0_SSPCR0_RESERVED0_ALIGN                                0
#define SPI0_SSPCR0_RESERVED0_BITS                                 16
#define SPI0_SSPCR0_RESERVED0_SHIFT                                16

/* SPI0 :: SSPCR0 :: SCR [15:08] */
#define Wr_SPI0_SSPCR0_SCR(x) WriteRegBits(SPI0_SSPCR0,0xff00,8,x)
#define Rd_SPI0_SSPCR0_SCR(x) ReadRegBits(SPI0_SSPCR0,0xff00,8)
#define SPI0_SSPCR0_SCR_MASK                                       0x0000ff00
#define SPI0_SSPCR0_SCR_ALIGN                                      0
#define SPI0_SSPCR0_SCR_BITS                                       8
#define SPI0_SSPCR0_SCR_SHIFT                                      8

/* SPI0 :: SSPCR0 :: SPH [07:07] */
#define Wr_SPI0_SSPCR0_SPH(x) WriteRegBits(SPI0_SSPCR0,0x80,7,x)
#define Rd_SPI0_SSPCR0_SPH(x) ReadRegBits(SPI0_SSPCR0,0x80,7)
#define SPI0_SSPCR0_SPH_MASK                                       0x00000080
#define SPI0_SSPCR0_SPH_ALIGN                                      0
#define SPI0_SSPCR0_SPH_BITS                                       1
#define SPI0_SSPCR0_SPH_SHIFT                                      7

/* SPI0 :: SSPCR0 :: SPO [06:06] */
#define Wr_SPI0_SSPCR0_SPO(x) WriteRegBits(SPI0_SSPCR0,0x40,6,x)
#define Rd_SPI0_SSPCR0_SPO(x) ReadRegBits(SPI0_SSPCR0,0x40,6)
#define SPI0_SSPCR0_SPO_MASK                                       0x00000040
#define SPI0_SSPCR0_SPO_ALIGN                                      0
#define SPI0_SSPCR0_SPO_BITS                                       1
#define SPI0_SSPCR0_SPO_SHIFT                                      6

/* SPI0 :: SSPCR0 :: FRF [05:04] */
#define Wr_SPI0_SSPCR0_FRF(x) WriteRegBits(SPI0_SSPCR0,0x30,4,x)
#define Rd_SPI0_SSPCR0_FRF(x) ReadRegBits(SPI0_SSPCR0,0x30,4)
#define SPI0_SSPCR0_FRF_MASK                                       0x00000030
#define SPI0_SSPCR0_FRF_ALIGN                                      0
#define SPI0_SSPCR0_FRF_BITS                                       2
#define SPI0_SSPCR0_FRF_SHIFT                                      4

/* SPI0 :: SSPCR0 :: DSS [03:00] */
#define Wr_SPI0_SSPCR0_DSS(x) WriteRegBits(SPI0_SSPCR0,0xf,0,x)
#define Rd_SPI0_SSPCR0_DSS(x) ReadRegBits(SPI0_SSPCR0,0xf,0)
#define SPI0_SSPCR0_DSS_MASK                                       0x0000000f
#define SPI0_SSPCR0_DSS_ALIGN                                      0
#define SPI0_SSPCR0_DSS_BITS                                       4
#define SPI0_SSPCR0_DSS_SHIFT                                      0


/****************************************************************************
 * SPI0 :: SSPCR1
 ***************************************************************************/
/* SPI0 :: SSPCR1 :: reserved0 [31:04] */
#define SPI0_SSPCR1_RESERVED0_MASK                                 0xfffffff0
#define SPI0_SSPCR1_RESERVED0_ALIGN                                0
#define SPI0_SSPCR1_RESERVED0_BITS                                 28
#define SPI0_SSPCR1_RESERVED0_SHIFT                                4

/* SPI0 :: SSPCR1 :: SOD [03:03] */
#define Wr_SPI0_SSPCR1_SOD(x) WriteRegBits(SPI0_SSPCR1,0x8,3,x)
#define Rd_SPI0_SSPCR1_SOD(x) ReadRegBits(SPI0_SSPCR1,0x8,3)
#define SPI0_SSPCR1_SOD_MASK                                       0x00000008
#define SPI0_SSPCR1_SOD_ALIGN                                      0
#define SPI0_SSPCR1_SOD_BITS                                       1
#define SPI0_SSPCR1_SOD_SHIFT                                      3

/* SPI0 :: SSPCR1 :: MS [02:02] */
#define Wr_SPI0_SSPCR1_MS(x) WriteRegBits(SPI0_SSPCR1,0x4,2,x)
#define Rd_SPI0_SSPCR1_MS(x) ReadRegBits(SPI0_SSPCR1,0x4,2)
#define SPI0_SSPCR1_MS_MASK                                        0x00000004
#define SPI0_SSPCR1_MS_ALIGN                                       0
#define SPI0_SSPCR1_MS_BITS                                        1
#define SPI0_SSPCR1_MS_SHIFT                                       2

/* SPI0 :: SSPCR1 :: SSE [01:01] */
#define Wr_SPI0_SSPCR1_SSE(x) WriteRegBits(SPI0_SSPCR1,0x2,1,x)
#define Rd_SPI0_SSPCR1_SSE(x) ReadRegBits(SPI0_SSPCR1,0x2,1)
#define SPI0_SSPCR1_SSE_MASK                                       0x00000002
#define SPI0_SSPCR1_SSE_ALIGN                                      0
#define SPI0_SSPCR1_SSE_BITS                                       1
#define SPI0_SSPCR1_SSE_SHIFT                                      1

/* SPI0 :: SSPCR1 :: reserved1 [00:00] */
#define SPI0_SSPCR1_RESERVED1_MASK                                 0x00000001
#define SPI0_SSPCR1_RESERVED1_ALIGN                                0
#define SPI0_SSPCR1_RESERVED1_BITS                                 1
#define SPI0_SSPCR1_RESERVED1_SHIFT                                0


/****************************************************************************
 * SPI0 :: SSPDR
 ***************************************************************************/
/* SPI0 :: SSPDR :: reserved0 [31:16] */
#define SPI0_SSPDR_RESERVED0_MASK                                  0xffff0000
#define SPI0_SSPDR_RESERVED0_ALIGN                                 0
#define SPI0_SSPDR_RESERVED0_BITS                                  16
#define SPI0_SSPDR_RESERVED0_SHIFT                                 16

/* SPI0 :: SSPDR :: DATA [15:00] */
#define Wr_SPI0_SSPDR_DATA(x) WriteRegBits(SPI0_SSPDR,0xffff,0,x)
#define Rd_SPI0_SSPDR_DATA(x) ReadRegBits(SPI0_SSPDR,0xffff,0)
#define SPI0_SSPDR_DATA_MASK                                       0x0000ffff
#define SPI0_SSPDR_DATA_ALIGN                                      0
#define SPI0_SSPDR_DATA_BITS                                       16
#define SPI0_SSPDR_DATA_SHIFT                                      0


/****************************************************************************
 * SPI0 :: SSPSR
 ***************************************************************************/
/* SPI0 :: SSPSR :: reserved0 [31:05] */
#define SPI0_SSPSR_RESERVED0_MASK                                  0xffffffe0
#define SPI0_SSPSR_RESERVED0_ALIGN                                 0
#define SPI0_SSPSR_RESERVED0_BITS                                  27
#define SPI0_SSPSR_RESERVED0_SHIFT                                 5

/* SPI0 :: SSPSR :: BSY [04:04] */
#define Wr_SPI0_SSPSR_BSY(x) WriteRegBits(SPI0_SSPSR,0x10,4,x)
#define Rd_SPI0_SSPSR_BSY(x) ReadRegBits(SPI0_SSPSR,0x10,4)
#define SPI0_SSPSR_BSY_MASK                                        0x00000010
#define SPI0_SSPSR_BSY_ALIGN                                       0
#define SPI0_SSPSR_BSY_BITS                                        1
#define SPI0_SSPSR_BSY_SHIFT                                       4

/* SPI0 :: SSPSR :: RFF [03:03] */
#define Wr_SPI0_SSPSR_RFF(x) WriteRegBits(SPI0_SSPSR,0x8,3,x)
#define Rd_SPI0_SSPSR_RFF(x) ReadRegBits(SPI0_SSPSR,0x8,3)
#define SPI0_SSPSR_RFF_MASK                                        0x00000008
#define SPI0_SSPSR_RFF_ALIGN                                       0
#define SPI0_SSPSR_RFF_BITS                                        1
#define SPI0_SSPSR_RFF_SHIFT                                       3

/* SPI0 :: SSPSR :: RNE [02:02] */
#define Wr_SPI0_SSPSR_RNE(x) WriteRegBits(SPI0_SSPSR,0x4,2,x)
#define Rd_SPI0_SSPSR_RNE(x) ReadRegBits(SPI0_SSPSR,0x4,2)
#define SPI0_SSPSR_RNE_MASK                                        0x00000004
#define SPI0_SSPSR_RNE_ALIGN                                       0
#define SPI0_SSPSR_RNE_BITS                                        1
#define SPI0_SSPSR_RNE_SHIFT                                       2

/* SPI0 :: SSPSR :: TNF [01:01] */
#define Wr_SPI0_SSPSR_TNF(x) WriteRegBits(SPI0_SSPSR,0x2,1,x)
#define Rd_SPI0_SSPSR_TNF(x) ReadRegBits(SPI0_SSPSR,0x2,1)
#define SPI0_SSPSR_TNF_MASK                                        0x00000002
#define SPI0_SSPSR_TNF_ALIGN                                       0
#define SPI0_SSPSR_TNF_BITS                                        1
#define SPI0_SSPSR_TNF_SHIFT                                       1

/* SPI0 :: SSPSR :: TFE [00:00] */
#define Wr_SPI0_SSPSR_TFE(x) WriteRegBits(SPI0_SSPSR,0x1,0,x)
#define Rd_SPI0_SSPSR_TFE(x) ReadRegBits(SPI0_SSPSR,0x1,0)
#define SPI0_SSPSR_TFE_MASK                                        0x00000001
#define SPI0_SSPSR_TFE_ALIGN                                       0
#define SPI0_SSPSR_TFE_BITS                                        1
#define SPI0_SSPSR_TFE_SHIFT                                       0


/****************************************************************************
 * SPI0 :: SSPCPSR
 ***************************************************************************/
/* SPI0 :: SSPCPSR :: reserved0 [31:08] */
#define SPI0_SSPCPSR_RESERVED0_MASK                                0xffffff00
#define SPI0_SSPCPSR_RESERVED0_ALIGN                               0
#define SPI0_SSPCPSR_RESERVED0_BITS                                24
#define SPI0_SSPCPSR_RESERVED0_SHIFT                               8

/* SPI0 :: SSPCPSR :: CPSDVSR [07:00] */
#define Wr_SPI0_SSPCPSR_CPSDVSR(x) WriteRegBits(SPI0_SSPCPSR,0xff,0,x)
#define Rd_SPI0_SSPCPSR_CPSDVSR(x) ReadRegBits(SPI0_SSPCPSR,0xff,0)
#define SPI0_SSPCPSR_CPSDVSR_MASK                                  0x000000ff
#define SPI0_SSPCPSR_CPSDVSR_ALIGN                                 0
#define SPI0_SSPCPSR_CPSDVSR_BITS                                  8
#define SPI0_SSPCPSR_CPSDVSR_SHIFT                                 0


/****************************************************************************
 * SPI0 :: SSPIMSC
 ***************************************************************************/
/* SPI0 :: SSPIMSC :: reserved0 [31:04] */
#define SPI0_SSPIMSC_RESERVED0_MASK                                0xfffffff0
#define SPI0_SSPIMSC_RESERVED0_ALIGN                               0
#define SPI0_SSPIMSC_RESERVED0_BITS                                28
#define SPI0_SSPIMSC_RESERVED0_SHIFT                               4

/* SPI0 :: SSPIMSC :: TXIM [03:03] */
#define Wr_SPI0_SSPIMSC_TXIM(x) WriteRegBits(SPI0_SSPIMSC,0x8,3,x)
#define Rd_SPI0_SSPIMSC_TXIM(x) ReadRegBits(SPI0_SSPIMSC,0x8,3)
#define SPI0_SSPIMSC_TXIM_MASK                                     0x00000008
#define SPI0_SSPIMSC_TXIM_ALIGN                                    0
#define SPI0_SSPIMSC_TXIM_BITS                                     1
#define SPI0_SSPIMSC_TXIM_SHIFT                                    3

/* SPI0 :: SSPIMSC :: RXIM [02:02] */
#define Wr_SPI0_SSPIMSC_RXIM(x) WriteRegBits(SPI0_SSPIMSC,0x4,2,x)
#define Rd_SPI0_SSPIMSC_RXIM(x) ReadRegBits(SPI0_SSPIMSC,0x4,2)
#define SPI0_SSPIMSC_RXIM_MASK                                     0x00000004
#define SPI0_SSPIMSC_RXIM_ALIGN                                    0
#define SPI0_SSPIMSC_RXIM_BITS                                     1
#define SPI0_SSPIMSC_RXIM_SHIFT                                    2

/* SPI0 :: SSPIMSC :: RTIM [01:01] */
#define Wr_SPI0_SSPIMSC_RTIM(x) WriteRegBits(SPI0_SSPIMSC,0x2,1,x)
#define Rd_SPI0_SSPIMSC_RTIM(x) ReadRegBits(SPI0_SSPIMSC,0x2,1)
#define SPI0_SSPIMSC_RTIM_MASK                                     0x00000002
#define SPI0_SSPIMSC_RTIM_ALIGN                                    0
#define SPI0_SSPIMSC_RTIM_BITS                                     1
#define SPI0_SSPIMSC_RTIM_SHIFT                                    1

/* SPI0 :: SSPIMSC :: RORIM [00:00] */
#define Wr_SPI0_SSPIMSC_RORIM(x) WriteRegBits(SPI0_SSPIMSC,0x1,0,x)
#define Rd_SPI0_SSPIMSC_RORIM(x) ReadRegBits(SPI0_SSPIMSC,0x1,0)
#define SPI0_SSPIMSC_RORIM_MASK                                    0x00000001
#define SPI0_SSPIMSC_RORIM_ALIGN                                   0
#define SPI0_SSPIMSC_RORIM_BITS                                    1
#define SPI0_SSPIMSC_RORIM_SHIFT                                   0


/****************************************************************************
 * SPI0 :: SSPRIS
 ***************************************************************************/
/* SPI0 :: SSPRIS :: reserved0 [31:04] */
#define SPI0_SSPRIS_RESERVED0_MASK                                 0xfffffff0
#define SPI0_SSPRIS_RESERVED0_ALIGN                                0
#define SPI0_SSPRIS_RESERVED0_BITS                                 28
#define SPI0_SSPRIS_RESERVED0_SHIFT                                4

/* SPI0 :: SSPRIS :: TXRIS [03:03] */
#define Wr_SPI0_SSPRIS_TXRIS(x) WriteRegBits(SPI0_SSPRIS,0x8,3,x)
#define Rd_SPI0_SSPRIS_TXRIS(x) ReadRegBits(SPI0_SSPRIS,0x8,3)
#define SPI0_SSPRIS_TXRIS_MASK                                     0x00000008
#define SPI0_SSPRIS_TXRIS_ALIGN                                    0
#define SPI0_SSPRIS_TXRIS_BITS                                     1
#define SPI0_SSPRIS_TXRIS_SHIFT                                    3

/* SPI0 :: SSPRIS :: RXRIS [02:02] */
#define Wr_SPI0_SSPRIS_RXRIS(x) WriteRegBits(SPI0_SSPRIS,0x4,2,x)
#define Rd_SPI0_SSPRIS_RXRIS(x) ReadRegBits(SPI0_SSPRIS,0x4,2)
#define SPI0_SSPRIS_RXRIS_MASK                                     0x00000004
#define SPI0_SSPRIS_RXRIS_ALIGN                                    0
#define SPI0_SSPRIS_RXRIS_BITS                                     1
#define SPI0_SSPRIS_RXRIS_SHIFT                                    2

/* SPI0 :: SSPRIS :: RTRIS [01:01] */
#define Wr_SPI0_SSPRIS_RTRIS(x) WriteRegBits(SPI0_SSPRIS,0x2,1,x)
#define Rd_SPI0_SSPRIS_RTRIS(x) ReadRegBits(SPI0_SSPRIS,0x2,1)
#define SPI0_SSPRIS_RTRIS_MASK                                     0x00000002
#define SPI0_SSPRIS_RTRIS_ALIGN                                    0
#define SPI0_SSPRIS_RTRIS_BITS                                     1
#define SPI0_SSPRIS_RTRIS_SHIFT                                    1

/* SPI0 :: SSPRIS :: RORRIS [00:00] */
#define Wr_SPI0_SSPRIS_RORRIS(x) WriteRegBits(SPI0_SSPRIS,0x1,0,x)
#define Rd_SPI0_SSPRIS_RORRIS(x) ReadRegBits(SPI0_SSPRIS,0x1,0)
#define SPI0_SSPRIS_RORRIS_MASK                                    0x00000001
#define SPI0_SSPRIS_RORRIS_ALIGN                                   0
#define SPI0_SSPRIS_RORRIS_BITS                                    1
#define SPI0_SSPRIS_RORRIS_SHIFT                                   0


/****************************************************************************
 * SPI0 :: SSPMIS
 ***************************************************************************/
/* SPI0 :: SSPMIS :: reserved0 [31:04] */
#define SPI0_SSPMIS_RESERVED0_MASK                                 0xfffffff0
#define SPI0_SSPMIS_RESERVED0_ALIGN                                0
#define SPI0_SSPMIS_RESERVED0_BITS                                 28
#define SPI0_SSPMIS_RESERVED0_SHIFT                                4

/* SPI0 :: SSPMIS :: TXMIS [03:03] */
#define Wr_SPI0_SSPMIS_TXMIS(x) WriteRegBits(SPI0_SSPMIS,0x8,3,x)
#define Rd_SPI0_SSPMIS_TXMIS(x) ReadRegBits(SPI0_SSPMIS,0x8,3)
#define SPI0_SSPMIS_TXMIS_MASK                                     0x00000008
#define SPI0_SSPMIS_TXMIS_ALIGN                                    0
#define SPI0_SSPMIS_TXMIS_BITS                                     1
#define SPI0_SSPMIS_TXMIS_SHIFT                                    3

/* SPI0 :: SSPMIS :: RXMIS [02:02] */
#define Wr_SPI0_SSPMIS_RXMIS(x) WriteRegBits(SPI0_SSPMIS,0x4,2,x)
#define Rd_SPI0_SSPMIS_RXMIS(x) ReadRegBits(SPI0_SSPMIS,0x4,2)
#define SPI0_SSPMIS_RXMIS_MASK                                     0x00000004
#define SPI0_SSPMIS_RXMIS_ALIGN                                    0
#define SPI0_SSPMIS_RXMIS_BITS                                     1
#define SPI0_SSPMIS_RXMIS_SHIFT                                    2

/* SPI0 :: SSPMIS :: RTMIS [01:01] */
#define Wr_SPI0_SSPMIS_RTMIS(x) WriteRegBits(SPI0_SSPMIS,0x2,1,x)
#define Rd_SPI0_SSPMIS_RTMIS(x) ReadRegBits(SPI0_SSPMIS,0x2,1)
#define SPI0_SSPMIS_RTMIS_MASK                                     0x00000002
#define SPI0_SSPMIS_RTMIS_ALIGN                                    0
#define SPI0_SSPMIS_RTMIS_BITS                                     1
#define SPI0_SSPMIS_RTMIS_SHIFT                                    1

/* SPI0 :: SSPMIS :: RORMIS [00:00] */
#define Wr_SPI0_SSPMIS_RORMIS(x) WriteRegBits(SPI0_SSPMIS,0x1,0,x)
#define Rd_SPI0_SSPMIS_RORMIS(x) ReadRegBits(SPI0_SSPMIS,0x1,0)
#define SPI0_SSPMIS_RORMIS_MASK                                    0x00000001
#define SPI0_SSPMIS_RORMIS_ALIGN                                   0
#define SPI0_SSPMIS_RORMIS_BITS                                    1
#define SPI0_SSPMIS_RORMIS_SHIFT                                   0


/****************************************************************************
 * SPI0 :: SSPICR
 ***************************************************************************/
/* SPI0 :: SSPICR :: reserved0 [31:02] */
#define SPI0_SSPICR_RESERVED0_MASK                                 0xfffffffc
#define SPI0_SSPICR_RESERVED0_ALIGN                                0
#define SPI0_SSPICR_RESERVED0_BITS                                 30
#define SPI0_SSPICR_RESERVED0_SHIFT                                2

/* SPI0 :: SSPICR :: RTIC [01:01] */
#define Wr_SPI0_SSPICR_RTIC(x) WriteRegBits(SPI0_SSPICR,0x2,1,x)
#define Rd_SPI0_SSPICR_RTIC(x) ReadRegBits(SPI0_SSPICR,0x2,1)
#define SPI0_SSPICR_RTIC_MASK                                      0x00000002
#define SPI0_SSPICR_RTIC_ALIGN                                     0
#define SPI0_SSPICR_RTIC_BITS                                      1
#define SPI0_SSPICR_RTIC_SHIFT                                     1

/* SPI0 :: SSPICR :: RORIC [00:00] */
#define Wr_SPI0_SSPICR_RORIC(x) WriteRegBits(SPI0_SSPICR,0x1,0,x)
#define Rd_SPI0_SSPICR_RORIC(x) ReadRegBits(SPI0_SSPICR,0x1,0)
#define SPI0_SSPICR_RORIC_MASK                                     0x00000001
#define SPI0_SSPICR_RORIC_ALIGN                                    0
#define SPI0_SSPICR_RORIC_BITS                                     1
#define SPI0_SSPICR_RORIC_SHIFT                                    0


/****************************************************************************
 * SPI0 :: SSPDMACR
 ***************************************************************************/
/* SPI0 :: SSPDMACR :: reserved0 [31:02] */
#define SPI0_SSPDMACR_RESERVED0_MASK                               0xfffffffc
#define SPI0_SSPDMACR_RESERVED0_ALIGN                              0
#define SPI0_SSPDMACR_RESERVED0_BITS                               30
#define SPI0_SSPDMACR_RESERVED0_SHIFT                              2

/* SPI0 :: SSPDMACR :: TXDMAE [01:01] */
#define Wr_SPI0_SSPDMACR_TXDMAE(x) WriteRegBits(SPI0_SSPDMACR,0x2,1,x)
#define Rd_SPI0_SSPDMACR_TXDMAE(x) ReadRegBits(SPI0_SSPDMACR,0x2,1)
#define SPI0_SSPDMACR_TXDMAE_MASK                                  0x00000002
#define SPI0_SSPDMACR_TXDMAE_ALIGN                                 0
#define SPI0_SSPDMACR_TXDMAE_BITS                                  1
#define SPI0_SSPDMACR_TXDMAE_SHIFT                                 1

/* SPI0 :: SSPDMACR :: RXDMAE [00:00] */
#define Wr_SPI0_SSPDMACR_RXDMAE(x) WriteRegBits(SPI0_SSPDMACR,0x1,0,x)
#define Rd_SPI0_SSPDMACR_RXDMAE(x) ReadRegBits(SPI0_SSPDMACR,0x1,0)
#define SPI0_SSPDMACR_RXDMAE_MASK                                  0x00000001
#define SPI0_SSPDMACR_RXDMAE_ALIGN                                 0
#define SPI0_SSPDMACR_RXDMAE_BITS                                  1
#define SPI0_SSPDMACR_RXDMAE_SHIFT                                 0


/****************************************************************************
 * SPI0 :: SSPPeriphID0
 ***************************************************************************/
/* SPI0 :: SSPPeriphID0 :: reserved0 [31:08] */
#define SPI0_SSPPERIPHID0_RESERVED0_MASK                           0xffffff00
#define SPI0_SSPPERIPHID0_RESERVED0_ALIGN                          0
#define SPI0_SSPPERIPHID0_RESERVED0_BITS                           24
#define SPI0_SSPPERIPHID0_RESERVED0_SHIFT                          8

/* SPI0 :: SSPPeriphID0 :: PartNumber0 [07:00] */
#define Wr_SPI0_SSPPeriphID0_PartNumber0(x) WriteRegBits(SPI0_SSPPERIPHID0,0xff,0,x)
#define Rd_SPI0_SSPPeriphID0_PartNumber0(x) ReadRegBits(SPI0_SSPPERIPHID0,0xff,0)
#define SPI0_SSPPERIPHID0_PARTNUMBER0_MASK                         0x000000ff
#define SPI0_SSPPERIPHID0_PARTNUMBER0_ALIGN                        0
#define SPI0_SSPPERIPHID0_PARTNUMBER0_BITS                         8
#define SPI0_SSPPERIPHID0_PARTNUMBER0_SHIFT                        0


/****************************************************************************
 * SPI0 :: SSPPeriphID1
 ***************************************************************************/
/* SPI0 :: SSPPeriphID1 :: reserved0 [31:08] */
#define SPI0_SSPPERIPHID1_RESERVED0_MASK                           0xffffff00
#define SPI0_SSPPERIPHID1_RESERVED0_ALIGN                          0
#define SPI0_SSPPERIPHID1_RESERVED0_BITS                           24
#define SPI0_SSPPERIPHID1_RESERVED0_SHIFT                          8

/* SPI0 :: SSPPeriphID1 :: Designer0 [07:04] */
#define Wr_SPI0_SSPPeriphID1_Designer0(x) WriteRegBits(SPI0_SSPPERIPHID1,0xf0,4,x)
#define Rd_SPI0_SSPPeriphID1_Designer0(x) ReadRegBits(SPI0_SSPPERIPHID1,0xf0,4)
#define SPI0_SSPPERIPHID1_DESIGNER0_MASK                           0x000000f0
#define SPI0_SSPPERIPHID1_DESIGNER0_ALIGN                          0
#define SPI0_SSPPERIPHID1_DESIGNER0_BITS                           4
#define SPI0_SSPPERIPHID1_DESIGNER0_SHIFT                          4

/* SPI0 :: SSPPeriphID1 :: PartNumber1 [03:00] */
#define Wr_SPI0_SSPPeriphID1_PartNumber1(x) WriteRegBits(SPI0_SSPPERIPHID1,0xf,0,x)
#define Rd_SPI0_SSPPeriphID1_PartNumber1(x) ReadRegBits(SPI0_SSPPERIPHID1,0xf,0)
#define SPI0_SSPPERIPHID1_PARTNUMBER1_MASK                         0x0000000f
#define SPI0_SSPPERIPHID1_PARTNUMBER1_ALIGN                        0
#define SPI0_SSPPERIPHID1_PARTNUMBER1_BITS                         4
#define SPI0_SSPPERIPHID1_PARTNUMBER1_SHIFT                        0


/****************************************************************************
 * SPI0 :: SSPPeriphID2
 ***************************************************************************/
/* SPI0 :: SSPPeriphID2 :: reserved0 [31:08] */
#define SPI0_SSPPERIPHID2_RESERVED0_MASK                           0xffffff00
#define SPI0_SSPPERIPHID2_RESERVED0_ALIGN                          0
#define SPI0_SSPPERIPHID2_RESERVED0_BITS                           24
#define SPI0_SSPPERIPHID2_RESERVED0_SHIFT                          8

/* SPI0 :: SSPPeriphID2 :: Revision [07:04] */
#define Wr_SPI0_SSPPeriphID2_Revision(x) WriteRegBits(SPI0_SSPPERIPHID2,0xf0,4,x)
#define Rd_SPI0_SSPPeriphID2_Revision(x) ReadRegBits(SPI0_SSPPERIPHID2,0xf0,4)
#define SPI0_SSPPERIPHID2_REVISION_MASK                            0x000000f0
#define SPI0_SSPPERIPHID2_REVISION_ALIGN                           0
#define SPI0_SSPPERIPHID2_REVISION_BITS                            4
#define SPI0_SSPPERIPHID2_REVISION_SHIFT                           4

/* SPI0 :: SSPPeriphID2 :: Designer1 [03:00] */
#define Wr_SPI0_SSPPeriphID2_Designer1(x) WriteRegBits(SPI0_SSPPERIPHID2,0xf,0,x)
#define Rd_SPI0_SSPPeriphID2_Designer1(x) ReadRegBits(SPI0_SSPPERIPHID2,0xf,0)
#define SPI0_SSPPERIPHID2_DESIGNER1_MASK                           0x0000000f
#define SPI0_SSPPERIPHID2_DESIGNER1_ALIGN                          0
#define SPI0_SSPPERIPHID2_DESIGNER1_BITS                           4
#define SPI0_SSPPERIPHID2_DESIGNER1_SHIFT                          0


/****************************************************************************
 * SPI0 :: SSPPeriphID3
 ***************************************************************************/
/* SPI0 :: SSPPeriphID3 :: reserved0 [31:08] */
#define SPI0_SSPPERIPHID3_RESERVED0_MASK                           0xffffff00
#define SPI0_SSPPERIPHID3_RESERVED0_ALIGN                          0
#define SPI0_SSPPERIPHID3_RESERVED0_BITS                           24
#define SPI0_SSPPERIPHID3_RESERVED0_SHIFT                          8

/* SPI0 :: SSPPeriphID3 :: Configuration [07:00] */
#define Wr_SPI0_SSPPeriphID3_Configuration(x) WriteRegBits(SPI0_SSPPERIPHID3,0xff,0,x)
#define Rd_SPI0_SSPPeriphID3_Configuration(x) ReadRegBits(SPI0_SSPPERIPHID3,0xff,0)
#define SPI0_SSPPERIPHID3_CONFIGURATION_MASK                       0x000000ff
#define SPI0_SSPPERIPHID3_CONFIGURATION_ALIGN                      0
#define SPI0_SSPPERIPHID3_CONFIGURATION_BITS                       8
#define SPI0_SSPPERIPHID3_CONFIGURATION_SHIFT                      0


/****************************************************************************
 * SPI0 :: SSPPCellID0
 ***************************************************************************/
/* SPI0 :: SSPPCellID0 :: reserved0 [31:08] */
#define SPI0_SSPPCELLID0_RESERVED0_MASK                            0xffffff00
#define SPI0_SSPPCELLID0_RESERVED0_ALIGN                           0
#define SPI0_SSPPCELLID0_RESERVED0_BITS                            24
#define SPI0_SSPPCELLID0_RESERVED0_SHIFT                           8

/* SPI0 :: SSPPCellID0 :: SSPPCellID0 [07:00] */
#define Wr_SPI0_SSPPCellID0_SSPPCellID0(x) WriteRegBits(SPI0_SSPPCELLID0,0xff,0,x)
#define Rd_SPI0_SSPPCellID0_SSPPCellID0(x) ReadRegBits(SPI0_SSPPCELLID0,0xff,0)
#define SPI0_SSPPCELLID0_SSPPCELLID0_MASK                          0x000000ff
#define SPI0_SSPPCELLID0_SSPPCELLID0_ALIGN                         0
#define SPI0_SSPPCELLID0_SSPPCELLID0_BITS                          8
#define SPI0_SSPPCELLID0_SSPPCELLID0_SHIFT                         0


/****************************************************************************
 * SPI0 :: SSPPCellID1
 ***************************************************************************/
/* SPI0 :: SSPPCellID1 :: reserved0 [31:08] */
#define SPI0_SSPPCELLID1_RESERVED0_MASK                            0xffffff00
#define SPI0_SSPPCELLID1_RESERVED0_ALIGN                           0
#define SPI0_SSPPCELLID1_RESERVED0_BITS                            24
#define SPI0_SSPPCELLID1_RESERVED0_SHIFT                           8

/* SPI0 :: SSPPCellID1 :: SSPPCellID1 [07:00] */
#define Wr_SPI0_SSPPCellID1_SSPPCellID1(x) WriteRegBits(SPI0_SSPPCELLID1,0xff,0,x)
#define Rd_SPI0_SSPPCellID1_SSPPCellID1(x) ReadRegBits(SPI0_SSPPCELLID1,0xff,0)
#define SPI0_SSPPCELLID1_SSPPCELLID1_MASK                          0x000000ff
#define SPI0_SSPPCELLID1_SSPPCELLID1_ALIGN                         0
#define SPI0_SSPPCELLID1_SSPPCELLID1_BITS                          8
#define SPI0_SSPPCELLID1_SSPPCELLID1_SHIFT                         0


/****************************************************************************
 * SPI0 :: SSPPCellID2
 ***************************************************************************/
/* SPI0 :: SSPPCellID2 :: reserved0 [31:08] */
#define SPI0_SSPPCELLID2_RESERVED0_MASK                            0xffffff00
#define SPI0_SSPPCELLID2_RESERVED0_ALIGN                           0
#define SPI0_SSPPCELLID2_RESERVED0_BITS                            24
#define SPI0_SSPPCELLID2_RESERVED0_SHIFT                           8

/* SPI0 :: SSPPCellID2 :: SSPPCellID2 [07:00] */
#define Wr_SPI0_SSPPCellID2_SSPPCellID2(x) WriteRegBits(SPI0_SSPPCELLID2,0xff,0,x)
#define Rd_SPI0_SSPPCellID2_SSPPCellID2(x) ReadRegBits(SPI0_SSPPCELLID2,0xff,0)
#define SPI0_SSPPCELLID2_SSPPCELLID2_MASK                          0x000000ff
#define SPI0_SSPPCELLID2_SSPPCELLID2_ALIGN                         0
#define SPI0_SSPPCELLID2_SSPPCELLID2_BITS                          8
#define SPI0_SSPPCELLID2_SSPPCELLID2_SHIFT                         0


/****************************************************************************
 * SPI0 :: SSPPCellID3
 ***************************************************************************/
/* SPI0 :: SSPPCellID3 :: reserved0 [31:08] */
#define SPI0_SSPPCELLID3_RESERVED0_MASK                            0xffffff00
#define SPI0_SSPPCELLID3_RESERVED0_ALIGN                           0
#define SPI0_SSPPCELLID3_RESERVED0_BITS                            24
#define SPI0_SSPPCELLID3_RESERVED0_SHIFT                           8

/* SPI0 :: SSPPCellID3 :: SSPPCellID3 [07:00] */
#define Wr_SPI0_SSPPCellID3_SSPPCellID3(x) WriteRegBits(SPI0_SSPPCELLID3,0xff,0,x)
#define Rd_SPI0_SSPPCellID3_SSPPCellID3(x) ReadRegBits(SPI0_SSPPCELLID3,0xff,0)
#define SPI0_SSPPCELLID3_SSPPCELLID3_MASK                          0x000000ff
#define SPI0_SSPPCELLID3_SSPPCELLID3_ALIGN                         0
#define SPI0_SSPPCELLID3_SSPPCELLID3_BITS                          8
#define SPI0_SSPPCELLID3_SSPPCELLID3_SHIFT                         0


/****************************************************************************
 * bcm89530_sys_cfg_PWM
 ***************************************************************************/
/****************************************************************************
 * PWM :: PWMCTL
 ***************************************************************************/
/* PWM :: PWMCTL :: reserved0 [31:19] */
#define PWM_PWMCTL_RESERVED0_MASK                                  0xfff80000
#define PWM_PWMCTL_RESERVED0_ALIGN                                 0
#define PWM_PWMCTL_RESERVED0_BITS                                  13
#define PWM_PWMCTL_RESERVED0_SHIFT                                 19

/* PWM :: PWMCTL :: pwm_opendrain [18:15] */
#define Wr_PWM_PWMCTL_pwm_opendrain(x) WriteRegBits(PWM_PWMCTL,0x78000,15,x)
#define Rd_PWM_PWMCTL_pwm_opendrain(x) ReadRegBits(PWM_PWMCTL,0x78000,15)
#define PWM_PWMCTL_PWM_OPENDRAIN_MASK                              0x00078000
#define PWM_PWMCTL_PWM_OPENDRAIN_ALIGN                             0
#define PWM_PWMCTL_PWM_OPENDRAIN_BITS                              4
#define PWM_PWMCTL_PWM_OPENDRAIN_SHIFT                             15

/* PWM :: PWMCTL :: reserved1 [14:12] */
#define PWM_PWMCTL_RESERVED1_MASK                                  0x00007000
#define PWM_PWMCTL_RESERVED1_ALIGN                                 0
#define PWM_PWMCTL_RESERVED1_BITS                                  3
#define PWM_PWMCTL_RESERVED1_SHIFT                                 12

/* PWM :: PWMCTL :: pwm_out_polarity [11:08] */
#define Wr_PWM_PWMCTL_pwm_out_polarity(x) WriteRegBits(PWM_PWMCTL,0xf00,8,x)
#define Rd_PWM_PWMCTL_pwm_out_polarity(x) ReadRegBits(PWM_PWMCTL,0xf00,8)
#define PWM_PWMCTL_PWM_OUT_POLARITY_MASK                           0x00000f00
#define PWM_PWMCTL_PWM_OUT_POLARITY_ALIGN                          0
#define PWM_PWMCTL_PWM_OUT_POLARITY_BITS                           4
#define PWM_PWMCTL_PWM_OUT_POLARITY_SHIFT                          8

/* PWM :: PWMCTL :: reserved2 [07:04] */
#define PWM_PWMCTL_RESERVED2_MASK                                  0x000000f0
#define PWM_PWMCTL_RESERVED2_ALIGN                                 0
#define PWM_PWMCTL_RESERVED2_BITS                                  4
#define PWM_PWMCTL_RESERVED2_SHIFT                                 4

/* PWM :: PWMCTL :: pwm_enable [03:00] */
#define Wr_PWM_PWMCTL_pwm_enable(x) WriteRegBits(PWM_PWMCTL,0xf,0,x)
#define Rd_PWM_PWMCTL_pwm_enable(x) ReadRegBits(PWM_PWMCTL,0xf,0)
#define PWM_PWMCTL_PWM_ENABLE_MASK                                 0x0000000f
#define PWM_PWMCTL_PWM_ENABLE_ALIGN                                0
#define PWM_PWMCTL_PWM_ENABLE_BITS                                 4
#define PWM_PWMCTL_PWM_ENABLE_SHIFT                                0


/****************************************************************************
 * PWM :: PERIOD_CNT_0
 ***************************************************************************/
/* PWM :: PERIOD_CNT_0 :: reserved0 [31:16] */
#define PWM_PERIOD_CNT_0_RESERVED0_MASK                            0xffff0000
#define PWM_PERIOD_CNT_0_RESERVED0_ALIGN                           0
#define PWM_PERIOD_CNT_0_RESERVED0_BITS                            16
#define PWM_PERIOD_CNT_0_RESERVED0_SHIFT                           16

/* PWM :: PERIOD_CNT_0 :: pwm_period_cnt_0 [15:00] */
#define Wr_PWM_PERIOD_CNT_0_pwm_period_cnt_0(x) WriteRegBits(PWM_PERIOD_CNT_0,0xffff,0,x)
#define Rd_PWM_PERIOD_CNT_0_pwm_period_cnt_0(x) ReadRegBits(PWM_PERIOD_CNT_0,0xffff,0)
#define PWM_PERIOD_CNT_0_PWM_PERIOD_CNT_0_MASK                     0x0000ffff
#define PWM_PERIOD_CNT_0_PWM_PERIOD_CNT_0_ALIGN                    0
#define PWM_PERIOD_CNT_0_PWM_PERIOD_CNT_0_BITS                     16
#define PWM_PERIOD_CNT_0_PWM_PERIOD_CNT_0_SHIFT                    0


/****************************************************************************
 * PWM :: DUTY_CNT_0
 ***************************************************************************/
/* PWM :: DUTY_CNT_0 :: reserved0 [31:16] */
#define PWM_DUTY_CNT_0_RESERVED0_MASK                              0xffff0000
#define PWM_DUTY_CNT_0_RESERVED0_ALIGN                             0
#define PWM_DUTY_CNT_0_RESERVED0_BITS                              16
#define PWM_DUTY_CNT_0_RESERVED0_SHIFT                             16

/* PWM :: DUTY_CNT_0 :: pwm_duty_cnt_0 [15:00] */
#define Wr_PWM_DUTY_CNT_0_pwm_duty_cnt_0(x) WriteRegBits(PWM_DUTY_CNT_0,0xffff,0,x)
#define Rd_PWM_DUTY_CNT_0_pwm_duty_cnt_0(x) ReadRegBits(PWM_DUTY_CNT_0,0xffff,0)
#define PWM_DUTY_CNT_0_PWM_DUTY_CNT_0_MASK                         0x0000ffff
#define PWM_DUTY_CNT_0_PWM_DUTY_CNT_0_ALIGN                        0
#define PWM_DUTY_CNT_0_PWM_DUTY_CNT_0_BITS                         16
#define PWM_DUTY_CNT_0_PWM_DUTY_CNT_0_SHIFT                        0


/****************************************************************************
 * PWM :: PERIOD_CNT_1
 ***************************************************************************/
/* PWM :: PERIOD_CNT_1 :: reserved0 [31:16] */
#define PWM_PERIOD_CNT_1_RESERVED0_MASK                            0xffff0000
#define PWM_PERIOD_CNT_1_RESERVED0_ALIGN                           0
#define PWM_PERIOD_CNT_1_RESERVED0_BITS                            16
#define PWM_PERIOD_CNT_1_RESERVED0_SHIFT                           16

/* PWM :: PERIOD_CNT_1 :: pwm_period_cnt_1 [15:00] */
#define Wr_PWM_PERIOD_CNT_1_pwm_period_cnt_1(x) WriteRegBits(PWM_PERIOD_CNT_1,0xffff,0,x)
#define Rd_PWM_PERIOD_CNT_1_pwm_period_cnt_1(x) ReadRegBits(PWM_PERIOD_CNT_1,0xffff,0)
#define PWM_PERIOD_CNT_1_PWM_PERIOD_CNT_1_MASK                     0x0000ffff
#define PWM_PERIOD_CNT_1_PWM_PERIOD_CNT_1_ALIGN                    0
#define PWM_PERIOD_CNT_1_PWM_PERIOD_CNT_1_BITS                     16
#define PWM_PERIOD_CNT_1_PWM_PERIOD_CNT_1_SHIFT                    0


/****************************************************************************
 * PWM :: DUTY_CNT_1
 ***************************************************************************/
/* PWM :: DUTY_CNT_1 :: reserved0 [31:16] */
#define PWM_DUTY_CNT_1_RESERVED0_MASK                              0xffff0000
#define PWM_DUTY_CNT_1_RESERVED0_ALIGN                             0
#define PWM_DUTY_CNT_1_RESERVED0_BITS                              16
#define PWM_DUTY_CNT_1_RESERVED0_SHIFT                             16

/* PWM :: DUTY_CNT_1 :: pwm_duty_cnt_1 [15:00] */
#define Wr_PWM_DUTY_CNT_1_pwm_duty_cnt_1(x) WriteRegBits(PWM_DUTY_CNT_1,0xffff,0,x)
#define Rd_PWM_DUTY_CNT_1_pwm_duty_cnt_1(x) ReadRegBits(PWM_DUTY_CNT_1,0xffff,0)
#define PWM_DUTY_CNT_1_PWM_DUTY_CNT_1_MASK                         0x0000ffff
#define PWM_DUTY_CNT_1_PWM_DUTY_CNT_1_ALIGN                        0
#define PWM_DUTY_CNT_1_PWM_DUTY_CNT_1_BITS                         16
#define PWM_DUTY_CNT_1_PWM_DUTY_CNT_1_SHIFT                        0


/****************************************************************************
 * PWM :: PERIOD_CNT_2
 ***************************************************************************/
/* PWM :: PERIOD_CNT_2 :: reserved0 [31:16] */
#define PWM_PERIOD_CNT_2_RESERVED0_MASK                            0xffff0000
#define PWM_PERIOD_CNT_2_RESERVED0_ALIGN                           0
#define PWM_PERIOD_CNT_2_RESERVED0_BITS                            16
#define PWM_PERIOD_CNT_2_RESERVED0_SHIFT                           16

/* PWM :: PERIOD_CNT_2 :: pwm_period_cnt_2 [15:00] */
#define Wr_PWM_PERIOD_CNT_2_pwm_period_cnt_2(x) WriteRegBits(PWM_PERIOD_CNT_2,0xffff,0,x)
#define Rd_PWM_PERIOD_CNT_2_pwm_period_cnt_2(x) ReadRegBits(PWM_PERIOD_CNT_2,0xffff,0)
#define PWM_PERIOD_CNT_2_PWM_PERIOD_CNT_2_MASK                     0x0000ffff
#define PWM_PERIOD_CNT_2_PWM_PERIOD_CNT_2_ALIGN                    0
#define PWM_PERIOD_CNT_2_PWM_PERIOD_CNT_2_BITS                     16
#define PWM_PERIOD_CNT_2_PWM_PERIOD_CNT_2_SHIFT                    0


/****************************************************************************
 * PWM :: DUTY_CNT_2
 ***************************************************************************/
/* PWM :: DUTY_CNT_2 :: reserved0 [31:16] */
#define PWM_DUTY_CNT_2_RESERVED0_MASK                              0xffff0000
#define PWM_DUTY_CNT_2_RESERVED0_ALIGN                             0
#define PWM_DUTY_CNT_2_RESERVED0_BITS                              16
#define PWM_DUTY_CNT_2_RESERVED0_SHIFT                             16

/* PWM :: DUTY_CNT_2 :: pwm_duty_cnt_2 [15:00] */
#define Wr_PWM_DUTY_CNT_2_pwm_duty_cnt_2(x) WriteRegBits(PWM_DUTY_CNT_2,0xffff,0,x)
#define Rd_PWM_DUTY_CNT_2_pwm_duty_cnt_2(x) ReadRegBits(PWM_DUTY_CNT_2,0xffff,0)
#define PWM_DUTY_CNT_2_PWM_DUTY_CNT_2_MASK                         0x0000ffff
#define PWM_DUTY_CNT_2_PWM_DUTY_CNT_2_ALIGN                        0
#define PWM_DUTY_CNT_2_PWM_DUTY_CNT_2_BITS                         16
#define PWM_DUTY_CNT_2_PWM_DUTY_CNT_2_SHIFT                        0


/****************************************************************************
 * PWM :: PERIOD_CNT_3
 ***************************************************************************/
/* PWM :: PERIOD_CNT_3 :: reserved0 [31:16] */
#define PWM_PERIOD_CNT_3_RESERVED0_MASK                            0xffff0000
#define PWM_PERIOD_CNT_3_RESERVED0_ALIGN                           0
#define PWM_PERIOD_CNT_3_RESERVED0_BITS                            16
#define PWM_PERIOD_CNT_3_RESERVED0_SHIFT                           16

/* PWM :: PERIOD_CNT_3 :: pwm_period_cnt_3 [15:00] */
#define Wr_PWM_PERIOD_CNT_3_pwm_period_cnt_3(x) WriteRegBits(PWM_PERIOD_CNT_3,0xffff,0,x)
#define Rd_PWM_PERIOD_CNT_3_pwm_period_cnt_3(x) ReadRegBits(PWM_PERIOD_CNT_3,0xffff,0)
#define PWM_PERIOD_CNT_3_PWM_PERIOD_CNT_3_MASK                     0x0000ffff
#define PWM_PERIOD_CNT_3_PWM_PERIOD_CNT_3_ALIGN                    0
#define PWM_PERIOD_CNT_3_PWM_PERIOD_CNT_3_BITS                     16
#define PWM_PERIOD_CNT_3_PWM_PERIOD_CNT_3_SHIFT                    0


/****************************************************************************
 * PWM :: DUTY_CNT_3
 ***************************************************************************/
/* PWM :: DUTY_CNT_3 :: reserved0 [31:16] */
#define PWM_DUTY_CNT_3_RESERVED0_MASK                              0xffff0000
#define PWM_DUTY_CNT_3_RESERVED0_ALIGN                             0
#define PWM_DUTY_CNT_3_RESERVED0_BITS                              16
#define PWM_DUTY_CNT_3_RESERVED0_SHIFT                             16

/* PWM :: DUTY_CNT_3 :: pwm_duty_cnt_3 [15:00] */
#define Wr_PWM_DUTY_CNT_3_pwm_duty_cnt_3(x) WriteRegBits(PWM_DUTY_CNT_3,0xffff,0,x)
#define Rd_PWM_DUTY_CNT_3_pwm_duty_cnt_3(x) ReadRegBits(PWM_DUTY_CNT_3,0xffff,0)
#define PWM_DUTY_CNT_3_PWM_DUTY_CNT_3_MASK                         0x0000ffff
#define PWM_DUTY_CNT_3_PWM_DUTY_CNT_3_ALIGN                        0
#define PWM_DUTY_CNT_3_PWM_DUTY_CNT_3_BITS                         16
#define PWM_DUTY_CNT_3_PWM_DUTY_CNT_3_SHIFT                        0


/****************************************************************************
 * PWM :: PRESCALE
 ***************************************************************************/
/* PWM :: PRESCALE :: reserved0 [31:24] */
#define PWM_PRESCALE_RESERVED0_MASK                                0xff000000
#define PWM_PRESCALE_RESERVED0_ALIGN                               0
#define PWM_PRESCALE_RESERVED0_BITS                                8
#define PWM_PRESCALE_RESERVED0_SHIFT                               24

/* PWM :: PRESCALE :: pwm0_prescale [23:18] */
#define Wr_PWM_PRESCALE_pwm0_prescale(x) WriteRegBits(PWM_PRESCALE,0xfc0000,18,x)
#define Rd_PWM_PRESCALE_pwm0_prescale(x) ReadRegBits(PWM_PRESCALE,0xfc0000,18)
#define PWM_PRESCALE_PWM0_PRESCALE_MASK                            0x00fc0000
#define PWM_PRESCALE_PWM0_PRESCALE_ALIGN                           0
#define PWM_PRESCALE_PWM0_PRESCALE_BITS                            6
#define PWM_PRESCALE_PWM0_PRESCALE_SHIFT                           18

/* PWM :: PRESCALE :: pwm1_prescale [17:12] */
#define Wr_PWM_PRESCALE_pwm1_prescale(x) WriteRegBits(PWM_PRESCALE,0x3f000,12,x)
#define Rd_PWM_PRESCALE_pwm1_prescale(x) ReadRegBits(PWM_PRESCALE,0x3f000,12)
#define PWM_PRESCALE_PWM1_PRESCALE_MASK                            0x0003f000
#define PWM_PRESCALE_PWM1_PRESCALE_ALIGN                           0
#define PWM_PRESCALE_PWM1_PRESCALE_BITS                            6
#define PWM_PRESCALE_PWM1_PRESCALE_SHIFT                           12

/* PWM :: PRESCALE :: pwm2_prescale [11:06] */
#define Wr_PWM_PRESCALE_pwm2_prescale(x) WriteRegBits(PWM_PRESCALE,0xfc0,6,x)
#define Rd_PWM_PRESCALE_pwm2_prescale(x) ReadRegBits(PWM_PRESCALE,0xfc0,6)
#define PWM_PRESCALE_PWM2_PRESCALE_MASK                            0x00000fc0
#define PWM_PRESCALE_PWM2_PRESCALE_ALIGN                           0
#define PWM_PRESCALE_PWM2_PRESCALE_BITS                            6
#define PWM_PRESCALE_PWM2_PRESCALE_SHIFT                           6

/* PWM :: PRESCALE :: pwm3_prescale [05:00] */
#define Wr_PWM_PRESCALE_pwm3_prescale(x) WriteRegBits(PWM_PRESCALE,0x3f,0,x)
#define Rd_PWM_PRESCALE_pwm3_prescale(x) ReadRegBits(PWM_PRESCALE,0x3f,0)
#define PWM_PRESCALE_PWM3_PRESCALE_MASK                            0x0000003f
#define PWM_PRESCALE_PWM3_PRESCALE_ALIGN                           0
#define PWM_PRESCALE_PWM3_PRESCALE_BITS                            6
#define PWM_PRESCALE_PWM3_PRESCALE_SHIFT                           0


/****************************************************************************
 * bcm89530_sys_cfg_GIO0
 ***************************************************************************/
/****************************************************************************
 * GIO0 :: GPIO_G0_DIN
 ***************************************************************************/
/* GIO0 :: GPIO_G0_DIN :: reserved0 [31:04] */
#define GIO0_GPIO_G0_DIN_RESERVED0_MASK                            0xfffffff0
#define GIO0_GPIO_G0_DIN_RESERVED0_ALIGN                           0
#define GIO0_GPIO_G0_DIN_RESERVED0_BITS                            28
#define GIO0_GPIO_G0_DIN_RESERVED0_SHIFT                           4

/* GIO0 :: GPIO_G0_DIN :: GPIO_G0_DIN_GPIO_DATA_IN_reserved [03:02] */
#define GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN_RESERVED_MASK    0x0000000c
#define GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN_RESERVED_ALIGN   0
#define GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN_RESERVED_BITS    2
#define GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN_RESERVED_SHIFT   2

/* GIO0 :: GPIO_G0_DIN :: GPIO_G0_DIN_GPIO_DATA_IN [01:00] */
#define Wr_GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN(x) WriteRegBits(GIO0_GPIO_G0_DIN,0x3,0,x)
#define Rd_GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN(x) ReadRegBits(GIO0_GPIO_G0_DIN,0x3,0)
#define GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN_MASK             0x00000003
#define GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN_ALIGN            0
#define GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN_BITS             2
#define GIO0_GPIO_G0_DIN_GPIO_G0_DIN_GPIO_DATA_IN_SHIFT            0


/****************************************************************************
 * GIO0 :: GPIO_G0_DOUT
 ***************************************************************************/
/* GIO0 :: GPIO_G0_DOUT :: reserved0 [31:04] */
#define GIO0_GPIO_G0_DOUT_RESERVED0_MASK                           0xfffffff0
#define GIO0_GPIO_G0_DOUT_RESERVED0_ALIGN                          0
#define GIO0_GPIO_G0_DOUT_RESERVED0_BITS                           28
#define GIO0_GPIO_G0_DOUT_RESERVED0_SHIFT                          4

/* GIO0 :: GPIO_G0_DOUT :: GPIO_G0_DOUT_GPIO_DATA_OUT_reserved [03:02] */
#define GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT_RESERVED_MASK 0x0000000c
#define GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT_RESERVED_ALIGN 0
#define GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT_RESERVED_BITS 2
#define GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT_RESERVED_SHIFT 2

/* GIO0 :: GPIO_G0_DOUT :: GPIO_G0_DOUT_GPIO_DATA_OUT [01:00] */
#define Wr_GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT(x) WriteRegBits(GIO0_GPIO_G0_DOUT,0x3,0,x)
#define Rd_GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT(x) ReadRegBits(GIO0_GPIO_G0_DOUT,0x3,0)
#define GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT_MASK          0x00000003
#define GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT_ALIGN         0
#define GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT_BITS          2
#define GIO0_GPIO_G0_DOUT_GPIO_G0_DOUT_GPIO_DATA_OUT_SHIFT         0


/****************************************************************************
 * GIO0 :: GPIO_G0_DRV_EN
 ***************************************************************************/
/* GIO0 :: GPIO_G0_DRV_EN :: reserved0 [31:04] */
#define GIO0_GPIO_G0_DRV_EN_RESERVED0_MASK                         0xfffffff0
#define GIO0_GPIO_G0_DRV_EN_RESERVED0_ALIGN                        0
#define GIO0_GPIO_G0_DRV_EN_RESERVED0_BITS                         28
#define GIO0_GPIO_G0_DRV_EN_RESERVED0_SHIFT                        4

/* GIO0 :: GPIO_G0_DRV_EN :: GPIO_G0_DRV_EN_GPIO_DRV_EN_reserved [03:02] */
#define GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN_RESERVED_MASK 0x0000000c
#define GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN_RESERVED_ALIGN 0
#define GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN_RESERVED_BITS 2
#define GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN_RESERVED_SHIFT 2

/* GIO0 :: GPIO_G0_DRV_EN :: GPIO_G0_DRV_EN_GPIO_DRV_EN [01:00] */
#define Wr_GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN(x) WriteRegBits(GIO0_GPIO_G0_DRV_EN,0x3,0,x)
#define Rd_GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN(x) ReadRegBits(GIO0_GPIO_G0_DRV_EN,0x3,0)
#define GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN_MASK        0x00000003
#define GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN_ALIGN       0
#define GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN_BITS        2
#define GIO0_GPIO_G0_DRV_EN_GPIO_G0_DRV_EN_GPIO_DRV_EN_SHIFT       0


/****************************************************************************
 * GIO0 :: GPIO_G0_INT_TYP
 ***************************************************************************/
/* GIO0 :: GPIO_G0_INT_TYP :: reserved0 [31:02] */
#define GIO0_GPIO_G0_INT_TYP_RESERVED0_MASK                        0xfffffffc
#define GIO0_GPIO_G0_INT_TYP_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G0_INT_TYP_RESERVED0_BITS                        30
#define GIO0_GPIO_G0_INT_TYP_RESERVED0_SHIFT                       2

/* GIO0 :: GPIO_G0_INT_TYP :: GPIO_G0_INT_TYP_GPIO_INT_TYP [01:00] */
#define Wr_GIO0_GPIO_G0_INT_TYP_GPIO_G0_INT_TYP_GPIO_INT_TYP(x) WriteRegBits(GIO0_GPIO_G0_INT_TYP,0x3,0,x)
#define Rd_GIO0_GPIO_G0_INT_TYP_GPIO_G0_INT_TYP_GPIO_INT_TYP(x) ReadRegBits(GIO0_GPIO_G0_INT_TYP,0x3,0)
#define GIO0_GPIO_G0_INT_TYP_GPIO_G0_INT_TYP_GPIO_INT_TYP_MASK     0x00000003
#define GIO0_GPIO_G0_INT_TYP_GPIO_G0_INT_TYP_GPIO_INT_TYP_ALIGN    0
#define GIO0_GPIO_G0_INT_TYP_GPIO_G0_INT_TYP_GPIO_INT_TYP_BITS     2
#define GIO0_GPIO_G0_INT_TYP_GPIO_G0_INT_TYP_GPIO_INT_TYP_SHIFT    0


/****************************************************************************
 * GIO0 :: GPIO_G0_INT_DU_EDG
 ***************************************************************************/
/* GIO0 :: GPIO_G0_INT_DU_EDG :: reserved0 [31:02] */
#define GIO0_GPIO_G0_INT_DU_EDG_RESERVED0_MASK                     0xfffffffc
#define GIO0_GPIO_G0_INT_DU_EDG_RESERVED0_ALIGN                    0
#define GIO0_GPIO_G0_INT_DU_EDG_RESERVED0_BITS                     30
#define GIO0_GPIO_G0_INT_DU_EDG_RESERVED0_SHIFT                    2

/* GIO0 :: GPIO_G0_INT_DU_EDG :: GPIO_G0_INT_DU_EDG_GPIO_INT_DU_EDGE [01:00] */
#define Wr_GIO0_GPIO_G0_INT_DU_EDG_GPIO_G0_INT_DU_EDG_GPIO_INT_DU_EDGE(x) WriteRegBits(GIO0_GPIO_G0_INT_DU_EDG,0x3,0,x)
#define Rd_GIO0_GPIO_G0_INT_DU_EDG_GPIO_G0_INT_DU_EDG_GPIO_INT_DU_EDGE(x) ReadRegBits(GIO0_GPIO_G0_INT_DU_EDG,0x3,0)
#define GIO0_GPIO_G0_INT_DU_EDG_GPIO_G0_INT_DU_EDG_GPIO_INT_DU_EDGE_MASK 0x00000003
#define GIO0_GPIO_G0_INT_DU_EDG_GPIO_G0_INT_DU_EDG_GPIO_INT_DU_EDGE_ALIGN 0
#define GIO0_GPIO_G0_INT_DU_EDG_GPIO_G0_INT_DU_EDG_GPIO_INT_DU_EDGE_BITS 2
#define GIO0_GPIO_G0_INT_DU_EDG_GPIO_G0_INT_DU_EDG_GPIO_INT_DU_EDGE_SHIFT 0


/****************************************************************************
 * GIO0 :: GPIO_G0_INT_EDG_LVL_SEL
 ***************************************************************************/
/* GIO0 :: GPIO_G0_INT_EDG_LVL_SEL :: reserved0 [31:02] */
#define GIO0_GPIO_G0_INT_EDG_LVL_SEL_RESERVED0_MASK                0xfffffffc
#define GIO0_GPIO_G0_INT_EDG_LVL_SEL_RESERVED0_ALIGN               0
#define GIO0_GPIO_G0_INT_EDG_LVL_SEL_RESERVED0_BITS                30
#define GIO0_GPIO_G0_INT_EDG_LVL_SEL_RESERVED0_SHIFT               2

/* GIO0 :: GPIO_G0_INT_EDG_LVL_SEL :: GPIO_G0_INT_EDG_LVL_SEL_GPIO_INT_EDGE [01:00] */
#define Wr_GIO0_GPIO_G0_INT_EDG_LVL_SEL_GPIO_G0_INT_EDG_LVL_SEL_GPIO_INT_EDGE(x) WriteRegBits(GIO0_GPIO_G0_INT_EDG_LVL_SEL,0x3,0,x)
#define Rd_GIO0_GPIO_G0_INT_EDG_LVL_SEL_GPIO_G0_INT_EDG_LVL_SEL_GPIO_INT_EDGE(x) ReadRegBits(GIO0_GPIO_G0_INT_EDG_LVL_SEL,0x3,0)
#define GIO0_GPIO_G0_INT_EDG_LVL_SEL_GPIO_G0_INT_EDG_LVL_SEL_GPIO_INT_EDGE_MASK 0x00000003
#define GIO0_GPIO_G0_INT_EDG_LVL_SEL_GPIO_G0_INT_EDG_LVL_SEL_GPIO_INT_EDGE_ALIGN 0
#define GIO0_GPIO_G0_INT_EDG_LVL_SEL_GPIO_G0_INT_EDG_LVL_SEL_GPIO_INT_EDGE_BITS 2
#define GIO0_GPIO_G0_INT_EDG_LVL_SEL_GPIO_G0_INT_EDG_LVL_SEL_GPIO_INT_EDGE_SHIFT 0


/****************************************************************************
 * GIO0 :: GPIO_G0_INT_MSK
 ***************************************************************************/
/* GIO0 :: GPIO_G0_INT_MSK :: reserved0 [31:02] */
#define GIO0_GPIO_G0_INT_MSK_RESERVED0_MASK                        0xfffffffc
#define GIO0_GPIO_G0_INT_MSK_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G0_INT_MSK_RESERVED0_BITS                        30
#define GIO0_GPIO_G0_INT_MSK_RESERVED0_SHIFT                       2

/* GIO0 :: GPIO_G0_INT_MSK :: GPIO_G0_INT_MSK_GPIO_INT_MSK [01:00] */
#define Wr_GIO0_GPIO_G0_INT_MSK_GPIO_G0_INT_MSK_GPIO_INT_MSK(x) WriteRegBits(GIO0_GPIO_G0_INT_MSK,0x3,0,x)
#define Rd_GIO0_GPIO_G0_INT_MSK_GPIO_G0_INT_MSK_GPIO_INT_MSK(x) ReadRegBits(GIO0_GPIO_G0_INT_MSK,0x3,0)
#define GIO0_GPIO_G0_INT_MSK_GPIO_G0_INT_MSK_GPIO_INT_MSK_MASK     0x00000003
#define GIO0_GPIO_G0_INT_MSK_GPIO_G0_INT_MSK_GPIO_INT_MSK_ALIGN    0
#define GIO0_GPIO_G0_INT_MSK_GPIO_G0_INT_MSK_GPIO_INT_MSK_BITS     2
#define GIO0_GPIO_G0_INT_MSK_GPIO_G0_INT_MSK_GPIO_INT_MSK_SHIFT    0


/****************************************************************************
 * GIO0 :: GPIO_G0_INT_STS
 ***************************************************************************/
/* GIO0 :: GPIO_G0_INT_STS :: reserved0 [31:02] */
#define GIO0_GPIO_G0_INT_STS_RESERVED0_MASK                        0xfffffffc
#define GIO0_GPIO_G0_INT_STS_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G0_INT_STS_RESERVED0_BITS                        30
#define GIO0_GPIO_G0_INT_STS_RESERVED0_SHIFT                       2

/* GIO0 :: GPIO_G0_INT_STS :: GPIO_G0_INT_STS_GPIO_INT_STS [01:00] */
#define Wr_GIO0_GPIO_G0_INT_STS_GPIO_G0_INT_STS_GPIO_INT_STS(x) WriteRegBits(GIO0_GPIO_G0_INT_STS,0x3,0,x)
#define Rd_GIO0_GPIO_G0_INT_STS_GPIO_G0_INT_STS_GPIO_INT_STS(x) ReadRegBits(GIO0_GPIO_G0_INT_STS,0x3,0)
#define GIO0_GPIO_G0_INT_STS_GPIO_G0_INT_STS_GPIO_INT_STS_MASK     0x00000003
#define GIO0_GPIO_G0_INT_STS_GPIO_G0_INT_STS_GPIO_INT_STS_ALIGN    0
#define GIO0_GPIO_G0_INT_STS_GPIO_G0_INT_STS_GPIO_INT_STS_BITS     2
#define GIO0_GPIO_G0_INT_STS_GPIO_G0_INT_STS_GPIO_INT_STS_SHIFT    0


/****************************************************************************
 * GIO0 :: GPIO_G0_INT_MSK_STS
 ***************************************************************************/
/* GIO0 :: GPIO_G0_INT_MSK_STS :: reserved0 [31:02] */
#define GIO0_GPIO_G0_INT_MSK_STS_RESERVED0_MASK                    0xfffffffc
#define GIO0_GPIO_G0_INT_MSK_STS_RESERVED0_ALIGN                   0
#define GIO0_GPIO_G0_INT_MSK_STS_RESERVED0_BITS                    30
#define GIO0_GPIO_G0_INT_MSK_STS_RESERVED0_SHIFT                   2

/* GIO0 :: GPIO_G0_INT_MSK_STS :: GPIO_G0_INT_MSK_STS_GPIO_INT_MSK_STS [01:00] */
#define Wr_GIO0_GPIO_G0_INT_MSK_STS_GPIO_G0_INT_MSK_STS_GPIO_INT_MSK_STS(x) WriteRegBits(GIO0_GPIO_G0_INT_MSK_STS,0x3,0,x)
#define Rd_GIO0_GPIO_G0_INT_MSK_STS_GPIO_G0_INT_MSK_STS_GPIO_INT_MSK_STS(x) ReadRegBits(GIO0_GPIO_G0_INT_MSK_STS,0x3,0)
#define GIO0_GPIO_G0_INT_MSK_STS_GPIO_G0_INT_MSK_STS_GPIO_INT_MSK_STS_MASK 0x00000003
#define GIO0_GPIO_G0_INT_MSK_STS_GPIO_G0_INT_MSK_STS_GPIO_INT_MSK_STS_ALIGN 0
#define GIO0_GPIO_G0_INT_MSK_STS_GPIO_G0_INT_MSK_STS_GPIO_INT_MSK_STS_BITS 2
#define GIO0_GPIO_G0_INT_MSK_STS_GPIO_G0_INT_MSK_STS_GPIO_INT_MSK_STS_SHIFT 0


/****************************************************************************
 * GIO0 :: GPIO_G0_INT_CLR
 ***************************************************************************/
/* GIO0 :: GPIO_G0_INT_CLR :: reserved0 [31:02] */
#define GIO0_GPIO_G0_INT_CLR_RESERVED0_MASK                        0xfffffffc
#define GIO0_GPIO_G0_INT_CLR_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G0_INT_CLR_RESERVED0_BITS                        30
#define GIO0_GPIO_G0_INT_CLR_RESERVED0_SHIFT                       2

/* GIO0 :: GPIO_G0_INT_CLR :: GPIO_G0_INT_CLR_GPIO_INT_CLR [01:00] */
#define Wr_GIO0_GPIO_G0_INT_CLR_GPIO_G0_INT_CLR_GPIO_INT_CLR(x) WriteRegBits(GIO0_GPIO_G0_INT_CLR,0x3,0,x)
#define Rd_GIO0_GPIO_G0_INT_CLR_GPIO_G0_INT_CLR_GPIO_INT_CLR(x) ReadRegBits(GIO0_GPIO_G0_INT_CLR,0x3,0)
#define GIO0_GPIO_G0_INT_CLR_GPIO_G0_INT_CLR_GPIO_INT_CLR_MASK     0x00000003
#define GIO0_GPIO_G0_INT_CLR_GPIO_G0_INT_CLR_GPIO_INT_CLR_ALIGN    0
#define GIO0_GPIO_G0_INT_CLR_GPIO_G0_INT_CLR_GPIO_INT_CLR_BITS     2
#define GIO0_GPIO_G0_INT_CLR_GPIO_G0_INT_CLR_GPIO_INT_CLR_SHIFT    0


/****************************************************************************
 * GIO0 :: GPIO_G0_I2C_SEL
 ***************************************************************************/
/* GIO0 :: GPIO_G0_I2C_SEL :: reserved0 [31:04] */
#define GIO0_GPIO_G0_I2C_SEL_RESERVED0_MASK                        0xfffffff0
#define GIO0_GPIO_G0_I2C_SEL_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G0_I2C_SEL_RESERVED0_BITS                        28
#define GIO0_GPIO_G0_I2C_SEL_RESERVED0_SHIFT                       4

/* GIO0 :: GPIO_G0_I2C_SEL :: GPIO_G0_I2C_SEL_RESERVED_1 [03:02] */
#define Wr_GIO0_GPIO_G0_I2C_SEL_GPIO_G0_I2C_SEL_RESERVED_1(x) WriteRegBits(GIO0_GPIO_G0_I2C_SEL,0xc,2,x)
#define Rd_GIO0_GPIO_G0_I2C_SEL_GPIO_G0_I2C_SEL_RESERVED_1(x) ReadRegBits(GIO0_GPIO_G0_I2C_SEL,0xc,2)
#define GIO0_GPIO_G0_I2C_SEL_GPIO_G0_I2C_SEL_RESERVED_1_MASK       0x0000000c
#define GIO0_GPIO_G0_I2C_SEL_GPIO_G0_I2C_SEL_RESERVED_1_ALIGN      0
#define GIO0_GPIO_G0_I2C_SEL_GPIO_G0_I2C_SEL_RESERVED_1_BITS       2
#define GIO0_GPIO_G0_I2C_SEL_GPIO_G0_I2C_SEL_RESERVED_1_SHIFT      2

/* GIO0 :: GPIO_G0_I2C_SEL :: GPIO_I2C_MUX_SEL [01:00] */
#define Wr_GIO0_GPIO_G0_I2C_SEL_GPIO_I2C_MUX_SEL(x) WriteRegBits(GIO0_GPIO_G0_I2C_SEL,0x3,0,x)
#define Rd_GIO0_GPIO_G0_I2C_SEL_GPIO_I2C_MUX_SEL(x) ReadRegBits(GIO0_GPIO_G0_I2C_SEL,0x3,0)
#define GIO0_GPIO_G0_I2C_SEL_GPIO_I2C_MUX_SEL_MASK                 0x00000003
#define GIO0_GPIO_G0_I2C_SEL_GPIO_I2C_MUX_SEL_ALIGN                0
#define GIO0_GPIO_G0_I2C_SEL_GPIO_I2C_MUX_SEL_BITS                 2
#define GIO0_GPIO_G0_I2C_SEL_GPIO_I2C_MUX_SEL_SHIFT                0


/****************************************************************************
 * GIO0 :: GPIO_G0_INT_POL
 ***************************************************************************/
/* GIO0 :: GPIO_G0_INT_POL :: reserved0 [31:05] */
#define GIO0_GPIO_G0_INT_POL_RESERVED0_MASK                        0xffffffe0
#define GIO0_GPIO_G0_INT_POL_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G0_INT_POL_RESERVED0_BITS                        27
#define GIO0_GPIO_G0_INT_POL_RESERVED0_SHIFT                       5

/* GIO0 :: GPIO_G0_INT_POL :: GPIO_G0_INT_POL_RESERVED_1 [04:02] */
#define Wr_GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_RESERVED_1(x) WriteRegBits(GIO0_GPIO_G0_INT_POL,0x1c,2,x)
#define Rd_GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_RESERVED_1(x) ReadRegBits(GIO0_GPIO_G0_INT_POL,0x1c,2)
#define GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_RESERVED_1_MASK       0x0000001c
#define GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_RESERVED_1_ALIGN      0
#define GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_RESERVED_1_BITS       3
#define GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_RESERVED_1_SHIFT      2

/* GIO0 :: GPIO_G0_INT_POL :: GPIO_G0_INT_POL_GPIO_INT_POL [01:01] */
#define Wr_GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_GPIO_INT_POL(x) WriteRegBits(GIO0_GPIO_G0_INT_POL,0x2,1,x)
#define Rd_GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_GPIO_INT_POL(x) ReadRegBits(GIO0_GPIO_G0_INT_POL,0x2,1)
#define GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_GPIO_INT_POL_MASK     0x00000002
#define GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_GPIO_INT_POL_ALIGN    0
#define GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_GPIO_INT_POL_BITS     1
#define GIO0_GPIO_G0_INT_POL_GPIO_G0_INT_POL_GPIO_INT_POL_SHIFT    1

/* GIO0 :: GPIO_G0_INT_POL :: reserved1 [00:00] */
#define GIO0_GPIO_G0_INT_POL_RESERVED1_MASK                        0x00000001
#define GIO0_GPIO_G0_INT_POL_RESERVED1_ALIGN                       0
#define GIO0_GPIO_G0_INT_POL_RESERVED1_BITS                        1
#define GIO0_GPIO_G0_INT_POL_RESERVED1_SHIFT                       0


/****************************************************************************
 * GIO0 :: GPIO_G1_DIN
 ***************************************************************************/
/* GIO0 :: GPIO_G1_DIN :: reserved0 [31:04] */
#define GIO0_GPIO_G1_DIN_RESERVED0_MASK                            0xfffffff0
#define GIO0_GPIO_G1_DIN_RESERVED0_ALIGN                           0
#define GIO0_GPIO_G1_DIN_RESERVED0_BITS                            28
#define GIO0_GPIO_G1_DIN_RESERVED0_SHIFT                           4

/* GIO0 :: GPIO_G1_DIN :: GPIO_DATA_IN [03:00] */
#define Wr_GIO0_GPIO_G1_DIN_GPIO_DATA_IN(x) WriteRegBits(GIO0_GPIO_G1_DIN,0xf,0,x)
#define Rd_GIO0_GPIO_G1_DIN_GPIO_DATA_IN(x) ReadRegBits(GIO0_GPIO_G1_DIN,0xf,0)
#define GIO0_GPIO_G1_DIN_GPIO_DATA_IN_MASK                         0x0000000f
#define GIO0_GPIO_G1_DIN_GPIO_DATA_IN_ALIGN                        0
#define GIO0_GPIO_G1_DIN_GPIO_DATA_IN_BITS                         4
#define GIO0_GPIO_G1_DIN_GPIO_DATA_IN_SHIFT                        0


/****************************************************************************
 * GIO0 :: GPIO_G1_DOUT
 ***************************************************************************/
/* GIO0 :: GPIO_G1_DOUT :: reserved0 [31:04] */
#define GIO0_GPIO_G1_DOUT_RESERVED0_MASK                           0xfffffff0
#define GIO0_GPIO_G1_DOUT_RESERVED0_ALIGN                          0
#define GIO0_GPIO_G1_DOUT_RESERVED0_BITS                           28
#define GIO0_GPIO_G1_DOUT_RESERVED0_SHIFT                          4

/* GIO0 :: GPIO_G1_DOUT :: GPIO_DATA_OUT [03:00] */
#define Wr_GIO0_GPIO_G1_DOUT_GPIO_DATA_OUT(x) WriteRegBits(GIO0_GPIO_G1_DOUT,0xf,0,x)
#define Rd_GIO0_GPIO_G1_DOUT_GPIO_DATA_OUT(x) ReadRegBits(GIO0_GPIO_G1_DOUT,0xf,0)
#define GIO0_GPIO_G1_DOUT_GPIO_DATA_OUT_MASK                       0x0000000f
#define GIO0_GPIO_G1_DOUT_GPIO_DATA_OUT_ALIGN                      0
#define GIO0_GPIO_G1_DOUT_GPIO_DATA_OUT_BITS                       4
#define GIO0_GPIO_G1_DOUT_GPIO_DATA_OUT_SHIFT                      0


/****************************************************************************
 * GIO0 :: GPIO_G1_DRV_EN
 ***************************************************************************/
/* GIO0 :: GPIO_G1_DRV_EN :: reserved0 [31:04] */
#define GIO0_GPIO_G1_DRV_EN_RESERVED0_MASK                         0xfffffff0
#define GIO0_GPIO_G1_DRV_EN_RESERVED0_ALIGN                        0
#define GIO0_GPIO_G1_DRV_EN_RESERVED0_BITS                         28
#define GIO0_GPIO_G1_DRV_EN_RESERVED0_SHIFT                        4

/* GIO0 :: GPIO_G1_DRV_EN :: GPIO_DRV_EN [03:00] */
#define Wr_GIO0_GPIO_G1_DRV_EN_GPIO_DRV_EN(x) WriteRegBits(GIO0_GPIO_G1_DRV_EN,0xf,0,x)
#define Rd_GIO0_GPIO_G1_DRV_EN_GPIO_DRV_EN(x) ReadRegBits(GIO0_GPIO_G1_DRV_EN,0xf,0)
#define GIO0_GPIO_G1_DRV_EN_GPIO_DRV_EN_MASK                       0x0000000f
#define GIO0_GPIO_G1_DRV_EN_GPIO_DRV_EN_ALIGN                      0
#define GIO0_GPIO_G1_DRV_EN_GPIO_DRV_EN_BITS                       4
#define GIO0_GPIO_G1_DRV_EN_GPIO_DRV_EN_SHIFT                      0


/****************************************************************************
 * GIO0 :: GPIO_G1_INT_TYP
 ***************************************************************************/
/* GIO0 :: GPIO_G1_INT_TYP :: reserved0 [31:04] */
#define GIO0_GPIO_G1_INT_TYP_RESERVED0_MASK                        0xfffffff0
#define GIO0_GPIO_G1_INT_TYP_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_INT_TYP_RESERVED0_BITS                        28
#define GIO0_GPIO_G1_INT_TYP_RESERVED0_SHIFT                       4

/* GIO0 :: GPIO_G1_INT_TYP :: GPIO_INT_TYP [03:00] */
#define Wr_GIO0_GPIO_G1_INT_TYP_GPIO_INT_TYP(x) WriteRegBits(GIO0_GPIO_G1_INT_TYP,0xf,0,x)
#define Rd_GIO0_GPIO_G1_INT_TYP_GPIO_INT_TYP(x) ReadRegBits(GIO0_GPIO_G1_INT_TYP,0xf,0)
#define GIO0_GPIO_G1_INT_TYP_GPIO_INT_TYP_MASK                     0x0000000f
#define GIO0_GPIO_G1_INT_TYP_GPIO_INT_TYP_ALIGN                    0
#define GIO0_GPIO_G1_INT_TYP_GPIO_INT_TYP_BITS                     4
#define GIO0_GPIO_G1_INT_TYP_GPIO_INT_TYP_SHIFT                    0


/****************************************************************************
 * GIO0 :: GPIO_G1_INT_DU_EDG
 ***************************************************************************/
/* GIO0 :: GPIO_G1_INT_DU_EDG :: reserved0 [31:04] */
#define GIO0_GPIO_G1_INT_DU_EDG_RESERVED0_MASK                     0xfffffff0
#define GIO0_GPIO_G1_INT_DU_EDG_RESERVED0_ALIGN                    0
#define GIO0_GPIO_G1_INT_DU_EDG_RESERVED0_BITS                     28
#define GIO0_GPIO_G1_INT_DU_EDG_RESERVED0_SHIFT                    4

/* GIO0 :: GPIO_G1_INT_DU_EDG :: GPIO_INT_DU_EDGE [03:00] */
#define Wr_GIO0_GPIO_G1_INT_DU_EDG_GPIO_INT_DU_EDGE(x) WriteRegBits(GIO0_GPIO_G1_INT_DU_EDG,0xf,0,x)
#define Rd_GIO0_GPIO_G1_INT_DU_EDG_GPIO_INT_DU_EDGE(x) ReadRegBits(GIO0_GPIO_G1_INT_DU_EDG,0xf,0)
#define GIO0_GPIO_G1_INT_DU_EDG_GPIO_INT_DU_EDGE_MASK              0x0000000f
#define GIO0_GPIO_G1_INT_DU_EDG_GPIO_INT_DU_EDGE_ALIGN             0
#define GIO0_GPIO_G1_INT_DU_EDG_GPIO_INT_DU_EDGE_BITS              4
#define GIO0_GPIO_G1_INT_DU_EDG_GPIO_INT_DU_EDGE_SHIFT             0


/****************************************************************************
 * GIO0 :: GPIO_G1_INT_EDG_LVL_SEL
 ***************************************************************************/
/* GIO0 :: GPIO_G1_INT_EDG_LVL_SEL :: reserved0 [31:04] */
#define GIO0_GPIO_G1_INT_EDG_LVL_SEL_RESERVED0_MASK                0xfffffff0
#define GIO0_GPIO_G1_INT_EDG_LVL_SEL_RESERVED0_ALIGN               0
#define GIO0_GPIO_G1_INT_EDG_LVL_SEL_RESERVED0_BITS                28
#define GIO0_GPIO_G1_INT_EDG_LVL_SEL_RESERVED0_SHIFT               4

/* GIO0 :: GPIO_G1_INT_EDG_LVL_SEL :: GPIO_INT_EDGE [03:00] */
#define Wr_GIO0_GPIO_G1_INT_EDG_LVL_SEL_GPIO_INT_EDGE(x) WriteRegBits(GIO0_GPIO_G1_INT_EDG_LVL_SEL,0xf,0,x)
#define Rd_GIO0_GPIO_G1_INT_EDG_LVL_SEL_GPIO_INT_EDGE(x) ReadRegBits(GIO0_GPIO_G1_INT_EDG_LVL_SEL,0xf,0)
#define GIO0_GPIO_G1_INT_EDG_LVL_SEL_GPIO_INT_EDGE_MASK            0x0000000f
#define GIO0_GPIO_G1_INT_EDG_LVL_SEL_GPIO_INT_EDGE_ALIGN           0
#define GIO0_GPIO_G1_INT_EDG_LVL_SEL_GPIO_INT_EDGE_BITS            4
#define GIO0_GPIO_G1_INT_EDG_LVL_SEL_GPIO_INT_EDGE_SHIFT           0


/****************************************************************************
 * GIO0 :: GPIO_G1_INT_MSK
 ***************************************************************************/
/* GIO0 :: GPIO_G1_INT_MSK :: reserved0 [31:04] */
#define GIO0_GPIO_G1_INT_MSK_RESERVED0_MASK                        0xfffffff0
#define GIO0_GPIO_G1_INT_MSK_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_INT_MSK_RESERVED0_BITS                        28
#define GIO0_GPIO_G1_INT_MSK_RESERVED0_SHIFT                       4

/* GIO0 :: GPIO_G1_INT_MSK :: GPIO_INT_MSK [03:00] */
#define Wr_GIO0_GPIO_G1_INT_MSK_GPIO_INT_MSK(x) WriteRegBits(GIO0_GPIO_G1_INT_MSK,0xf,0,x)
#define Rd_GIO0_GPIO_G1_INT_MSK_GPIO_INT_MSK(x) ReadRegBits(GIO0_GPIO_G1_INT_MSK,0xf,0)
#define GIO0_GPIO_G1_INT_MSK_GPIO_INT_MSK_MASK                     0x0000000f
#define GIO0_GPIO_G1_INT_MSK_GPIO_INT_MSK_ALIGN                    0
#define GIO0_GPIO_G1_INT_MSK_GPIO_INT_MSK_BITS                     4
#define GIO0_GPIO_G1_INT_MSK_GPIO_INT_MSK_SHIFT                    0


/****************************************************************************
 * GIO0 :: GPIO_G1_INT_STS
 ***************************************************************************/
/* GIO0 :: GPIO_G1_INT_STS :: reserved0 [31:04] */
#define GIO0_GPIO_G1_INT_STS_RESERVED0_MASK                        0xfffffff0
#define GIO0_GPIO_G1_INT_STS_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_INT_STS_RESERVED0_BITS                        28
#define GIO0_GPIO_G1_INT_STS_RESERVED0_SHIFT                       4

/* GIO0 :: GPIO_G1_INT_STS :: GPIO_INT_STS [03:00] */
#define Wr_GIO0_GPIO_G1_INT_STS_GPIO_INT_STS(x) WriteRegBits(GIO0_GPIO_G1_INT_STS,0xf,0,x)
#define Rd_GIO0_GPIO_G1_INT_STS_GPIO_INT_STS(x) ReadRegBits(GIO0_GPIO_G1_INT_STS,0xf,0)
#define GIO0_GPIO_G1_INT_STS_GPIO_INT_STS_MASK                     0x0000000f
#define GIO0_GPIO_G1_INT_STS_GPIO_INT_STS_ALIGN                    0
#define GIO0_GPIO_G1_INT_STS_GPIO_INT_STS_BITS                     4
#define GIO0_GPIO_G1_INT_STS_GPIO_INT_STS_SHIFT                    0


/****************************************************************************
 * GIO0 :: GPIO_G1_INT_MSK_STS
 ***************************************************************************/
/* GIO0 :: GPIO_G1_INT_MSK_STS :: reserved0 [31:04] */
#define GIO0_GPIO_G1_INT_MSK_STS_RESERVED0_MASK                    0xfffffff0
#define GIO0_GPIO_G1_INT_MSK_STS_RESERVED0_ALIGN                   0
#define GIO0_GPIO_G1_INT_MSK_STS_RESERVED0_BITS                    28
#define GIO0_GPIO_G1_INT_MSK_STS_RESERVED0_SHIFT                   4

/* GIO0 :: GPIO_G1_INT_MSK_STS :: GPIO_INT_MSK_STS [03:00] */
#define Wr_GIO0_GPIO_G1_INT_MSK_STS_GPIO_INT_MSK_STS(x) WriteRegBits(GIO0_GPIO_G1_INT_MSK_STS,0xf,0,x)
#define Rd_GIO0_GPIO_G1_INT_MSK_STS_GPIO_INT_MSK_STS(x) ReadRegBits(GIO0_GPIO_G1_INT_MSK_STS,0xf,0)
#define GIO0_GPIO_G1_INT_MSK_STS_GPIO_INT_MSK_STS_MASK             0x0000000f
#define GIO0_GPIO_G1_INT_MSK_STS_GPIO_INT_MSK_STS_ALIGN            0
#define GIO0_GPIO_G1_INT_MSK_STS_GPIO_INT_MSK_STS_BITS             4
#define GIO0_GPIO_G1_INT_MSK_STS_GPIO_INT_MSK_STS_SHIFT            0


/****************************************************************************
 * GIO0 :: GPIO_G1_INT_CLR
 ***************************************************************************/
/* GIO0 :: GPIO_G1_INT_CLR :: reserved0 [31:04] */
#define GIO0_GPIO_G1_INT_CLR_RESERVED0_MASK                        0xfffffff0
#define GIO0_GPIO_G1_INT_CLR_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_INT_CLR_RESERVED0_BITS                        28
#define GIO0_GPIO_G1_INT_CLR_RESERVED0_SHIFT                       4

/* GIO0 :: GPIO_G1_INT_CLR :: GPIO_INT_CLR [03:00] */
#define Wr_GIO0_GPIO_G1_INT_CLR_GPIO_INT_CLR(x) WriteRegBits(GIO0_GPIO_G1_INT_CLR,0xf,0,x)
#define Rd_GIO0_GPIO_G1_INT_CLR_GPIO_INT_CLR(x) ReadRegBits(GIO0_GPIO_G1_INT_CLR,0xf,0)
#define GIO0_GPIO_G1_INT_CLR_GPIO_INT_CLR_MASK                     0x0000000f
#define GIO0_GPIO_G1_INT_CLR_GPIO_INT_CLR_ALIGN                    0
#define GIO0_GPIO_G1_INT_CLR_GPIO_INT_CLR_BITS                     4
#define GIO0_GPIO_G1_INT_CLR_GPIO_INT_CLR_SHIFT                    0


/****************************************************************************
 * GIO0 :: GPIO_G1_PWM_SEL
 ***************************************************************************/
/* GIO0 :: GPIO_G1_PWM_SEL :: reserved0 [31:04] */
#define GIO0_GPIO_G1_PWM_SEL_RESERVED0_MASK                        0xfffffff0
#define GIO0_GPIO_G1_PWM_SEL_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_PWM_SEL_RESERVED0_BITS                        28
#define GIO0_GPIO_G1_PWM_SEL_RESERVED0_SHIFT                       4

/* GIO0 :: GPIO_G1_PWM_SEL :: GPIO_PWM_MUX_SEL [03:00] */
#define Wr_GIO0_GPIO_G1_PWM_SEL_GPIO_PWM_MUX_SEL(x) WriteRegBits(GIO0_GPIO_G1_PWM_SEL,0xf,0,x)
#define Rd_GIO0_GPIO_G1_PWM_SEL_GPIO_PWM_MUX_SEL(x) ReadRegBits(GIO0_GPIO_G1_PWM_SEL,0xf,0)
#define GIO0_GPIO_G1_PWM_SEL_GPIO_PWM_MUX_SEL_MASK                 0x0000000f
#define GIO0_GPIO_G1_PWM_SEL_GPIO_PWM_MUX_SEL_ALIGN                0
#define GIO0_GPIO_G1_PWM_SEL_GPIO_PWM_MUX_SEL_BITS                 4
#define GIO0_GPIO_G1_PWM_SEL_GPIO_PWM_MUX_SEL_SHIFT                0


/****************************************************************************
 * GIO0 :: GPIO_G1_SEC_CFG
 ***************************************************************************/
/* GIO0 :: GPIO_G1_SEC_CFG :: reserved0 [31:05] */
#define GIO0_GPIO_G1_SEC_CFG_RESERVED0_MASK                        0xffffffe0
#define GIO0_GPIO_G1_SEC_CFG_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_SEC_CFG_RESERVED0_BITS                        27
#define GIO0_GPIO_G1_SEC_CFG_RESERVED0_SHIFT                       5

/* GIO0 :: GPIO_G1_SEC_CFG :: GPIO_SEC_CFG [04:00] */
#define Wr_GIO0_GPIO_G1_SEC_CFG_GPIO_SEC_CFG(x) WriteRegBits(GIO0_GPIO_G1_SEC_CFG,0x1f,0,x)
#define Rd_GIO0_GPIO_G1_SEC_CFG_GPIO_SEC_CFG(x) ReadRegBits(GIO0_GPIO_G1_SEC_CFG,0x1f,0)
#define GIO0_GPIO_G1_SEC_CFG_GPIO_SEC_CFG_MASK                     0x0000001f
#define GIO0_GPIO_G1_SEC_CFG_GPIO_SEC_CFG_ALIGN                    0
#define GIO0_GPIO_G1_SEC_CFG_GPIO_SEC_CFG_BITS                     5
#define GIO0_GPIO_G1_SEC_CFG_GPIO_SEC_CFG_SHIFT                    0


/****************************************************************************
 * GIO0 :: GPIO_G1_INIT
 ***************************************************************************/
/* GIO0 :: GPIO_G1_INIT :: reserved0 [31:04] */
#define GIO0_GPIO_G1_INIT_RESERVED0_MASK                           0xfffffff0
#define GIO0_GPIO_G1_INIT_RESERVED0_ALIGN                          0
#define GIO0_GPIO_G1_INIT_RESERVED0_BITS                           28
#define GIO0_GPIO_G1_INIT_RESERVED0_SHIFT                          4

/* GIO0 :: GPIO_G1_INIT :: GPIO_INIT_VAL [03:00] */
#define Wr_GIO0_GPIO_G1_INIT_GPIO_INIT_VAL(x) WriteRegBits(GIO0_GPIO_G1_INIT,0xf,0,x)
#define Rd_GIO0_GPIO_G1_INIT_GPIO_INIT_VAL(x) ReadRegBits(GIO0_GPIO_G1_INIT,0xf,0)
#define GIO0_GPIO_G1_INIT_GPIO_INIT_VAL_MASK                       0x0000000f
#define GIO0_GPIO_G1_INIT_GPIO_INIT_VAL_ALIGN                      0
#define GIO0_GPIO_G1_INIT_GPIO_INIT_VAL_BITS                       4
#define GIO0_GPIO_G1_INIT_GPIO_INIT_VAL_SHIFT                      0


/****************************************************************************
 * GIO0 :: GPIO_G1_PAD_RES
 ***************************************************************************/
/* GIO0 :: GPIO_G1_PAD_RES :: reserved0 [31:04] */
#define GIO0_GPIO_G1_PAD_RES_RESERVED0_MASK                        0xfffffff0
#define GIO0_GPIO_G1_PAD_RES_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_PAD_RES_RESERVED0_BITS                        28
#define GIO0_GPIO_G1_PAD_RES_RESERVED0_SHIFT                       4

/* GIO0 :: GPIO_G1_PAD_RES :: GPIO_PAD_RES [03:00] */
#define Wr_GIO0_GPIO_G1_PAD_RES_GPIO_PAD_RES(x) WriteRegBits(GIO0_GPIO_G1_PAD_RES,0xf,0,x)
#define Rd_GIO0_GPIO_G1_PAD_RES_GPIO_PAD_RES(x) ReadRegBits(GIO0_GPIO_G1_PAD_RES,0xf,0)
#define GIO0_GPIO_G1_PAD_RES_GPIO_PAD_RES_MASK                     0x0000000f
#define GIO0_GPIO_G1_PAD_RES_GPIO_PAD_RES_ALIGN                    0
#define GIO0_GPIO_G1_PAD_RES_GPIO_PAD_RES_BITS                     4
#define GIO0_GPIO_G1_PAD_RES_GPIO_PAD_RES_SHIFT                    0


/****************************************************************************
 * GIO0 :: GPIO_G1_PAD_RESIS_EN
 ***************************************************************************/
/* GIO0 :: GPIO_G1_PAD_RESIS_EN :: reserved0 [31:04] */
#define GIO0_GPIO_G1_PAD_RESIS_EN_RESERVED0_MASK                   0xfffffff0
#define GIO0_GPIO_G1_PAD_RESIS_EN_RESERVED0_ALIGN                  0
#define GIO0_GPIO_G1_PAD_RESIS_EN_RESERVED0_BITS                   28
#define GIO0_GPIO_G1_PAD_RESIS_EN_RESERVED0_SHIFT                  4

/* GIO0 :: GPIO_G1_PAD_RESIS_EN :: GPIO_PAD_RESIS_EN [03:00] */
#define Wr_GIO0_GPIO_G1_PAD_RESIS_EN_GPIO_PAD_RESIS_EN(x) WriteRegBits(GIO0_GPIO_G1_PAD_RESIS_EN,0xf,0,x)
#define Rd_GIO0_GPIO_G1_PAD_RESIS_EN_GPIO_PAD_RESIS_EN(x) ReadRegBits(GIO0_GPIO_G1_PAD_RESIS_EN,0xf,0)
#define GIO0_GPIO_G1_PAD_RESIS_EN_GPIO_PAD_RESIS_EN_MASK           0x0000000f
#define GIO0_GPIO_G1_PAD_RESIS_EN_GPIO_PAD_RESIS_EN_ALIGN          0
#define GIO0_GPIO_G1_PAD_RESIS_EN_GPIO_PAD_RESIS_EN_BITS           4
#define GIO0_GPIO_G1_PAD_RESIS_EN_GPIO_PAD_RESIS_EN_SHIFT          0


/****************************************************************************
 * GIO0 :: GPIO_G1_TST_IN
 ***************************************************************************/
/* GIO0 :: GPIO_G1_TST_IN :: reserved0 [31:04] */
#define GIO0_GPIO_G1_TST_IN_RESERVED0_MASK                         0xfffffff0
#define GIO0_GPIO_G1_TST_IN_RESERVED0_ALIGN                        0
#define GIO0_GPIO_G1_TST_IN_RESERVED0_BITS                         28
#define GIO0_GPIO_G1_TST_IN_RESERVED0_SHIFT                        4

/* GIO0 :: GPIO_G1_TST_IN :: GPIO_TST_IN [03:00] */
#define Wr_GIO0_GPIO_G1_TST_IN_GPIO_TST_IN(x) WriteRegBits(GIO0_GPIO_G1_TST_IN,0xf,0,x)
#define Rd_GIO0_GPIO_G1_TST_IN_GPIO_TST_IN(x) ReadRegBits(GIO0_GPIO_G1_TST_IN,0xf,0)
#define GIO0_GPIO_G1_TST_IN_GPIO_TST_IN_MASK                       0x0000000f
#define GIO0_GPIO_G1_TST_IN_GPIO_TST_IN_ALIGN                      0
#define GIO0_GPIO_G1_TST_IN_GPIO_TST_IN_BITS                       4
#define GIO0_GPIO_G1_TST_IN_GPIO_TST_IN_SHIFT                      0


/****************************************************************************
 * GIO0 :: GPIO_G1_TST_OUT
 ***************************************************************************/
/* GIO0 :: GPIO_G1_TST_OUT :: reserved0 [31:04] */
#define GIO0_GPIO_G1_TST_OUT_RESERVED0_MASK                        0xfffffff0
#define GIO0_GPIO_G1_TST_OUT_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_TST_OUT_RESERVED0_BITS                        28
#define GIO0_GPIO_G1_TST_OUT_RESERVED0_SHIFT                       4

/* GIO0 :: GPIO_G1_TST_OUT :: GPIO_TST_OUT [03:00] */
#define Wr_GIO0_GPIO_G1_TST_OUT_GPIO_TST_OUT(x) WriteRegBits(GIO0_GPIO_G1_TST_OUT,0xf,0,x)
#define Rd_GIO0_GPIO_G1_TST_OUT_GPIO_TST_OUT(x) ReadRegBits(GIO0_GPIO_G1_TST_OUT,0xf,0)
#define GIO0_GPIO_G1_TST_OUT_GPIO_TST_OUT_MASK                     0x0000000f
#define GIO0_GPIO_G1_TST_OUT_GPIO_TST_OUT_ALIGN                    0
#define GIO0_GPIO_G1_TST_OUT_GPIO_TST_OUT_BITS                     4
#define GIO0_GPIO_G1_TST_OUT_GPIO_TST_OUT_SHIFT                    0


/****************************************************************************
 * GIO0 :: GPIO_G1_TST_IN_EN
 ***************************************************************************/
/* GIO0 :: GPIO_G1_TST_IN_EN :: reserved0 [31:04] */
#define GIO0_GPIO_G1_TST_IN_EN_RESERVED0_MASK                      0xfffffff0
#define GIO0_GPIO_G1_TST_IN_EN_RESERVED0_ALIGN                     0
#define GIO0_GPIO_G1_TST_IN_EN_RESERVED0_BITS                      28
#define GIO0_GPIO_G1_TST_IN_EN_RESERVED0_SHIFT                     4

/* GIO0 :: GPIO_G1_TST_IN_EN :: GPIO_TST_EN [03:00] */
#define Wr_GIO0_GPIO_G1_TST_IN_EN_GPIO_TST_EN(x) WriteRegBits(GIO0_GPIO_G1_TST_IN_EN,0xf,0,x)
#define Rd_GIO0_GPIO_G1_TST_IN_EN_GPIO_TST_EN(x) ReadRegBits(GIO0_GPIO_G1_TST_IN_EN,0xf,0)
#define GIO0_GPIO_G1_TST_IN_EN_GPIO_TST_EN_MASK                    0x0000000f
#define GIO0_GPIO_G1_TST_IN_EN_GPIO_TST_EN_ALIGN                   0
#define GIO0_GPIO_G1_TST_IN_EN_GPIO_TST_EN_BITS                    4
#define GIO0_GPIO_G1_TST_IN_EN_GPIO_TST_EN_SHIFT                   0


/****************************************************************************
 * GIO0 :: GPIO_G1_PWR_FAIL_TRI_STS
 ***************************************************************************/
/* GIO0 :: GPIO_G1_PWR_FAIL_TRI_STS :: reserved0 [31:04] */
#define GIO0_GPIO_G1_PWR_FAIL_TRI_STS_RESERVED0_MASK               0xfffffff0
#define GIO0_GPIO_G1_PWR_FAIL_TRI_STS_RESERVED0_ALIGN              0
#define GIO0_GPIO_G1_PWR_FAIL_TRI_STS_RESERVED0_BITS               28
#define GIO0_GPIO_G1_PWR_FAIL_TRI_STS_RESERVED0_SHIFT              4

/* GIO0 :: GPIO_G1_PWR_FAIL_TRI_STS :: GPIO_PWR_FAIL_TRI_STS [03:00] */
#define Wr_GIO0_GPIO_G1_PWR_FAIL_TRI_STS_GPIO_PWR_FAIL_TRI_STS(x) WriteRegBits(GIO0_GPIO_G1_PWR_FAIL_TRI_STS,0xf,0,x)
#define Rd_GIO0_GPIO_G1_PWR_FAIL_TRI_STS_GPIO_PWR_FAIL_TRI_STS(x) ReadRegBits(GIO0_GPIO_G1_PWR_FAIL_TRI_STS,0xf,0)
#define GIO0_GPIO_G1_PWR_FAIL_TRI_STS_GPIO_PWR_FAIL_TRI_STS_MASK   0x0000000f
#define GIO0_GPIO_G1_PWR_FAIL_TRI_STS_GPIO_PWR_FAIL_TRI_STS_ALIGN  0
#define GIO0_GPIO_G1_PWR_FAIL_TRI_STS_GPIO_PWR_FAIL_TRI_STS_BITS   4
#define GIO0_GPIO_G1_PWR_FAIL_TRI_STS_GPIO_PWR_FAIL_TRI_STS_SHIFT  0


/****************************************************************************
 * GIO0 :: GPIO_G1_PWR_FAIL_TRI_EN
 ***************************************************************************/
/* GIO0 :: GPIO_G1_PWR_FAIL_TRI_EN :: reserved0 [31:05] */
#define GIO0_GPIO_G1_PWR_FAIL_TRI_EN_RESERVED0_MASK                0xffffffe0
#define GIO0_GPIO_G1_PWR_FAIL_TRI_EN_RESERVED0_ALIGN               0
#define GIO0_GPIO_G1_PWR_FAIL_TRI_EN_RESERVED0_BITS                27
#define GIO0_GPIO_G1_PWR_FAIL_TRI_EN_RESERVED0_SHIFT               5

/* GIO0 :: GPIO_G1_PWR_FAIL_TRI_EN :: GPIO_PWR_FAIL_TRI_EN [04:00] */
#define Wr_GIO0_GPIO_G1_PWR_FAIL_TRI_EN_GPIO_PWR_FAIL_TRI_EN(x) WriteRegBits(GIO0_GPIO_G1_PWR_FAIL_TRI_EN,0x1f,0,x)
#define Rd_GIO0_GPIO_G1_PWR_FAIL_TRI_EN_GPIO_PWR_FAIL_TRI_EN(x) ReadRegBits(GIO0_GPIO_G1_PWR_FAIL_TRI_EN,0x1f,0)
#define GIO0_GPIO_G1_PWR_FAIL_TRI_EN_GPIO_PWR_FAIL_TRI_EN_MASK     0x0000001f
#define GIO0_GPIO_G1_PWR_FAIL_TRI_EN_GPIO_PWR_FAIL_TRI_EN_ALIGN    0
#define GIO0_GPIO_G1_PWR_FAIL_TRI_EN_GPIO_PWR_FAIL_TRI_EN_BITS     5
#define GIO0_GPIO_G1_PWR_FAIL_TRI_EN_GPIO_PWR_FAIL_TRI_EN_SHIFT    0


/****************************************************************************
 * GIO0 :: GPIO_G1_HYSTER_EN
 ***************************************************************************/
/* GIO0 :: GPIO_G1_HYSTER_EN :: reserved0 [31:04] */
#define GIO0_GPIO_G1_HYSTER_EN_RESERVED0_MASK                      0xfffffff0
#define GIO0_GPIO_G1_HYSTER_EN_RESERVED0_ALIGN                     0
#define GIO0_GPIO_G1_HYSTER_EN_RESERVED0_BITS                      28
#define GIO0_GPIO_G1_HYSTER_EN_RESERVED0_SHIFT                     4

/* GIO0 :: GPIO_G1_HYSTER_EN :: GPIO_HYSTER_EN [03:00] */
#define Wr_GIO0_GPIO_G1_HYSTER_EN_GPIO_HYSTER_EN(x) WriteRegBits(GIO0_GPIO_G1_HYSTER_EN,0xf,0,x)
#define Rd_GIO0_GPIO_G1_HYSTER_EN_GPIO_HYSTER_EN(x) ReadRegBits(GIO0_GPIO_G1_HYSTER_EN,0xf,0)
#define GIO0_GPIO_G1_HYSTER_EN_GPIO_HYSTER_EN_MASK                 0x0000000f
#define GIO0_GPIO_G1_HYSTER_EN_GPIO_HYSTER_EN_ALIGN                0
#define GIO0_GPIO_G1_HYSTER_EN_GPIO_HYSTER_EN_BITS                 4
#define GIO0_GPIO_G1_HYSTER_EN_GPIO_HYSTER_EN_SHIFT                0


/****************************************************************************
 * GIO0 :: GPIO_G1_SLEW_CTRL
 ***************************************************************************/
/* GIO0 :: GPIO_G1_SLEW_CTRL :: reserved0 [31:04] */
#define GIO0_GPIO_G1_SLEW_CTRL_RESERVED0_MASK                      0xfffffff0
#define GIO0_GPIO_G1_SLEW_CTRL_RESERVED0_ALIGN                     0
#define GIO0_GPIO_G1_SLEW_CTRL_RESERVED0_BITS                      28
#define GIO0_GPIO_G1_SLEW_CTRL_RESERVED0_SHIFT                     4

/* GIO0 :: GPIO_G1_SLEW_CTRL :: GPIO_SLEW_CTRL [03:00] */
#define Wr_GIO0_GPIO_G1_SLEW_CTRL_GPIO_SLEW_CTRL(x) WriteRegBits(GIO0_GPIO_G1_SLEW_CTRL,0xf,0,x)
#define Rd_GIO0_GPIO_G1_SLEW_CTRL_GPIO_SLEW_CTRL(x) ReadRegBits(GIO0_GPIO_G1_SLEW_CTRL,0xf,0)
#define GIO0_GPIO_G1_SLEW_CTRL_GPIO_SLEW_CTRL_MASK                 0x0000000f
#define GIO0_GPIO_G1_SLEW_CTRL_GPIO_SLEW_CTRL_ALIGN                0
#define GIO0_GPIO_G1_SLEW_CTRL_GPIO_SLEW_CTRL_BITS                 4
#define GIO0_GPIO_G1_SLEW_CTRL_GPIO_SLEW_CTRL_SHIFT                0


/****************************************************************************
 * GIO0 :: GPIO_G1_DRV_SEL_0
 ***************************************************************************/
/* GIO0 :: GPIO_G1_DRV_SEL_0 :: reserved0 [31:04] */
#define GIO0_GPIO_G1_DRV_SEL_0_RESERVED0_MASK                      0xfffffff0
#define GIO0_GPIO_G1_DRV_SEL_0_RESERVED0_ALIGN                     0
#define GIO0_GPIO_G1_DRV_SEL_0_RESERVED0_BITS                      28
#define GIO0_GPIO_G1_DRV_SEL_0_RESERVED0_SHIFT                     4

/* GIO0 :: GPIO_G1_DRV_SEL_0 :: GPIO_DRV_SEL_0 [03:00] */
#define Wr_GIO0_GPIO_G1_DRV_SEL_0_GPIO_DRV_SEL_0(x) WriteRegBits(GIO0_GPIO_G1_DRV_SEL_0,0xf,0,x)
#define Rd_GIO0_GPIO_G1_DRV_SEL_0_GPIO_DRV_SEL_0(x) ReadRegBits(GIO0_GPIO_G1_DRV_SEL_0,0xf,0)
#define GIO0_GPIO_G1_DRV_SEL_0_GPIO_DRV_SEL_0_MASK                 0x0000000f
#define GIO0_GPIO_G1_DRV_SEL_0_GPIO_DRV_SEL_0_ALIGN                0
#define GIO0_GPIO_G1_DRV_SEL_0_GPIO_DRV_SEL_0_BITS                 4
#define GIO0_GPIO_G1_DRV_SEL_0_GPIO_DRV_SEL_0_SHIFT                0


/****************************************************************************
 * GIO0 :: GPIO_G1_DRV_SEL_1
 ***************************************************************************/
/* GIO0 :: GPIO_G1_DRV_SEL_1 :: reserved0 [31:04] */
#define GIO0_GPIO_G1_DRV_SEL_1_RESERVED0_MASK                      0xfffffff0
#define GIO0_GPIO_G1_DRV_SEL_1_RESERVED0_ALIGN                     0
#define GIO0_GPIO_G1_DRV_SEL_1_RESERVED0_BITS                      28
#define GIO0_GPIO_G1_DRV_SEL_1_RESERVED0_SHIFT                     4

/* GIO0 :: GPIO_G1_DRV_SEL_1 :: GPIO_DRV_SEL_1 [03:00] */
#define Wr_GIO0_GPIO_G1_DRV_SEL_1_GPIO_DRV_SEL_1(x) WriteRegBits(GIO0_GPIO_G1_DRV_SEL_1,0xf,0,x)
#define Rd_GIO0_GPIO_G1_DRV_SEL_1_GPIO_DRV_SEL_1(x) ReadRegBits(GIO0_GPIO_G1_DRV_SEL_1,0xf,0)
#define GIO0_GPIO_G1_DRV_SEL_1_GPIO_DRV_SEL_1_MASK                 0x0000000f
#define GIO0_GPIO_G1_DRV_SEL_1_GPIO_DRV_SEL_1_ALIGN                0
#define GIO0_GPIO_G1_DRV_SEL_1_GPIO_DRV_SEL_1_BITS                 4
#define GIO0_GPIO_G1_DRV_SEL_1_GPIO_DRV_SEL_1_SHIFT                0


/****************************************************************************
 * GIO0 :: GPIO_G1_DRV_SEL_2
 ***************************************************************************/
/* GIO0 :: GPIO_G1_DRV_SEL_2 :: reserved0 [31:04] */
#define GIO0_GPIO_G1_DRV_SEL_2_RESERVED0_MASK                      0xfffffff0
#define GIO0_GPIO_G1_DRV_SEL_2_RESERVED0_ALIGN                     0
#define GIO0_GPIO_G1_DRV_SEL_2_RESERVED0_BITS                      28
#define GIO0_GPIO_G1_DRV_SEL_2_RESERVED0_SHIFT                     4

/* GIO0 :: GPIO_G1_DRV_SEL_2 :: GPIO_DRV_SEL_2 [03:00] */
#define Wr_GIO0_GPIO_G1_DRV_SEL_2_GPIO_DRV_SEL_2(x) WriteRegBits(GIO0_GPIO_G1_DRV_SEL_2,0xf,0,x)
#define Rd_GIO0_GPIO_G1_DRV_SEL_2_GPIO_DRV_SEL_2(x) ReadRegBits(GIO0_GPIO_G1_DRV_SEL_2,0xf,0)
#define GIO0_GPIO_G1_DRV_SEL_2_GPIO_DRV_SEL_2_MASK                 0x0000000f
#define GIO0_GPIO_G1_DRV_SEL_2_GPIO_DRV_SEL_2_ALIGN                0
#define GIO0_GPIO_G1_DRV_SEL_2_GPIO_DRV_SEL_2_BITS                 4
#define GIO0_GPIO_G1_DRV_SEL_2_GPIO_DRV_SEL_2_SHIFT                0


/****************************************************************************
 * GIO0 :: GPIO_G1_AUX_SEL
 ***************************************************************************/
/* GIO0 :: GPIO_G1_AUX_SEL :: reserved0 [31:04] */
#define GIO0_GPIO_G1_AUX_SEL_RESERVED0_MASK                        0xfffffff0
#define GIO0_GPIO_G1_AUX_SEL_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_AUX_SEL_RESERVED0_BITS                        28
#define GIO0_GPIO_G1_AUX_SEL_RESERVED0_SHIFT                       4

/* GIO0 :: GPIO_G1_AUX_SEL :: GPIO_AUX01_SEL [03:00] */
#define Wr_GIO0_GPIO_G1_AUX_SEL_GPIO_AUX01_SEL(x) WriteRegBits(GIO0_GPIO_G1_AUX_SEL,0xf,0,x)
#define Rd_GIO0_GPIO_G1_AUX_SEL_GPIO_AUX01_SEL(x) ReadRegBits(GIO0_GPIO_G1_AUX_SEL,0xf,0)
#define GIO0_GPIO_G1_AUX_SEL_GPIO_AUX01_SEL_MASK                   0x0000000f
#define GIO0_GPIO_G1_AUX_SEL_GPIO_AUX01_SEL_ALIGN                  0
#define GIO0_GPIO_G1_AUX_SEL_GPIO_AUX01_SEL_BITS                   4
#define GIO0_GPIO_G1_AUX_SEL_GPIO_AUX01_SEL_SHIFT                  0


/****************************************************************************
 * GIO0 :: GPIO_G1_INT_POL
 ***************************************************************************/
/* GIO0 :: GPIO_G1_INT_POL :: reserved0 [31:05] */
#define GIO0_GPIO_G1_INT_POL_RESERVED0_MASK                        0xffffffe0
#define GIO0_GPIO_G1_INT_POL_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G1_INT_POL_RESERVED0_BITS                        27
#define GIO0_GPIO_G1_INT_POL_RESERVED0_SHIFT                       5

/* GIO0 :: GPIO_G1_INT_POL :: GPIO_G1_INT_POL_RESERVED_1 [04:02] */
#define Wr_GIO0_GPIO_G1_INT_POL_GPIO_G1_INT_POL_RESERVED_1(x) WriteRegBits(GIO0_GPIO_G1_INT_POL,0x1c,2,x)
#define Rd_GIO0_GPIO_G1_INT_POL_GPIO_G1_INT_POL_RESERVED_1(x) ReadRegBits(GIO0_GPIO_G1_INT_POL,0x1c,2)
#define GIO0_GPIO_G1_INT_POL_GPIO_G1_INT_POL_RESERVED_1_MASK       0x0000001c
#define GIO0_GPIO_G1_INT_POL_GPIO_G1_INT_POL_RESERVED_1_ALIGN      0
#define GIO0_GPIO_G1_INT_POL_GPIO_G1_INT_POL_RESERVED_1_BITS       3
#define GIO0_GPIO_G1_INT_POL_GPIO_G1_INT_POL_RESERVED_1_SHIFT      2

/* GIO0 :: GPIO_G1_INT_POL :: GPIO_INT_POL [01:01] */
#define Wr_GIO0_GPIO_G1_INT_POL_GPIO_INT_POL(x) WriteRegBits(GIO0_GPIO_G1_INT_POL,0x2,1,x)
#define Rd_GIO0_GPIO_G1_INT_POL_GPIO_INT_POL(x) ReadRegBits(GIO0_GPIO_G1_INT_POL,0x2,1)
#define GIO0_GPIO_G1_INT_POL_GPIO_INT_POL_MASK                     0x00000002
#define GIO0_GPIO_G1_INT_POL_GPIO_INT_POL_ALIGN                    0
#define GIO0_GPIO_G1_INT_POL_GPIO_INT_POL_BITS                     1
#define GIO0_GPIO_G1_INT_POL_GPIO_INT_POL_SHIFT                    1

/* GIO0 :: GPIO_G1_INT_POL :: reserved1 [00:00] */
#define GIO0_GPIO_G1_INT_POL_RESERVED1_MASK                        0x00000001
#define GIO0_GPIO_G1_INT_POL_RESERVED1_ALIGN                       0
#define GIO0_GPIO_G1_INT_POL_RESERVED1_BITS                        1
#define GIO0_GPIO_G1_INT_POL_RESERVED1_SHIFT                       0


/****************************************************************************
 * GIO0 :: FLASH_CS_DIN
 ***************************************************************************/
/* GIO0 :: FLASH_CS_DIN :: reserved0 [31:04] */
#define GIO0_FLASH_CS_DIN_RESERVED0_MASK                           0xfffffff0
#define GIO0_FLASH_CS_DIN_RESERVED0_ALIGN                          0
#define GIO0_FLASH_CS_DIN_RESERVED0_BITS                           28
#define GIO0_FLASH_CS_DIN_RESERVED0_SHIFT                          4

/* GIO0 :: FLASH_CS_DIN :: FLASH_CS_DIN_RESERVED_1 [03:01] */
#define Wr_GIO0_FLASH_CS_DIN_FLASH_CS_DIN_RESERVED_1(x) WriteRegBits(GIO0_FLASH_CS_DIN,0xe,1,x)
#define Rd_GIO0_FLASH_CS_DIN_FLASH_CS_DIN_RESERVED_1(x) ReadRegBits(GIO0_FLASH_CS_DIN,0xe,1)
#define GIO0_FLASH_CS_DIN_FLASH_CS_DIN_RESERVED_1_MASK             0x0000000e
#define GIO0_FLASH_CS_DIN_FLASH_CS_DIN_RESERVED_1_ALIGN            0
#define GIO0_FLASH_CS_DIN_FLASH_CS_DIN_RESERVED_1_BITS             3
#define GIO0_FLASH_CS_DIN_FLASH_CS_DIN_RESERVED_1_SHIFT            1

/* GIO0 :: FLASH_CS_DIN :: FLASH_CS_DATA_IN [00:00] */
#define Wr_GIO0_FLASH_CS_DIN_FLASH_CS_DATA_IN(x) WriteRegBits(GIO0_FLASH_CS_DIN,0x1,0,x)
#define Rd_GIO0_FLASH_CS_DIN_FLASH_CS_DATA_IN(x) ReadRegBits(GIO0_FLASH_CS_DIN,0x1,0)
#define GIO0_FLASH_CS_DIN_FLASH_CS_DATA_IN_MASK                    0x00000001
#define GIO0_FLASH_CS_DIN_FLASH_CS_DATA_IN_ALIGN                   0
#define GIO0_FLASH_CS_DIN_FLASH_CS_DATA_IN_BITS                    1
#define GIO0_FLASH_CS_DIN_FLASH_CS_DATA_IN_SHIFT                   0


/****************************************************************************
 * GIO0 :: FLASH_CS_DOUT
 ***************************************************************************/
/* GIO0 :: FLASH_CS_DOUT :: reserved0 [31:04] */
#define GIO0_FLASH_CS_DOUT_RESERVED0_MASK                          0xfffffff0
#define GIO0_FLASH_CS_DOUT_RESERVED0_ALIGN                         0
#define GIO0_FLASH_CS_DOUT_RESERVED0_BITS                          28
#define GIO0_FLASH_CS_DOUT_RESERVED0_SHIFT                         4

/* GIO0 :: FLASH_CS_DOUT :: FLASH_CS_DOUT_RESERVED_1 [03:01] */
#define Wr_GIO0_FLASH_CS_DOUT_FLASH_CS_DOUT_RESERVED_1(x) WriteRegBits(GIO0_FLASH_CS_DOUT,0xe,1,x)
#define Rd_GIO0_FLASH_CS_DOUT_FLASH_CS_DOUT_RESERVED_1(x) ReadRegBits(GIO0_FLASH_CS_DOUT,0xe,1)
#define GIO0_FLASH_CS_DOUT_FLASH_CS_DOUT_RESERVED_1_MASK           0x0000000e
#define GIO0_FLASH_CS_DOUT_FLASH_CS_DOUT_RESERVED_1_ALIGN          0
#define GIO0_FLASH_CS_DOUT_FLASH_CS_DOUT_RESERVED_1_BITS           3
#define GIO0_FLASH_CS_DOUT_FLASH_CS_DOUT_RESERVED_1_SHIFT          1

/* GIO0 :: FLASH_CS_DOUT :: FLASH_CS_DATA_OUT [00:00] */
#define Wr_GIO0_FLASH_CS_DOUT_FLASH_CS_DATA_OUT(x) WriteRegBits(GIO0_FLASH_CS_DOUT,0x1,0,x)
#define Rd_GIO0_FLASH_CS_DOUT_FLASH_CS_DATA_OUT(x) ReadRegBits(GIO0_FLASH_CS_DOUT,0x1,0)
#define GIO0_FLASH_CS_DOUT_FLASH_CS_DATA_OUT_MASK                  0x00000001
#define GIO0_FLASH_CS_DOUT_FLASH_CS_DATA_OUT_ALIGN                 0
#define GIO0_FLASH_CS_DOUT_FLASH_CS_DATA_OUT_BITS                  1
#define GIO0_FLASH_CS_DOUT_FLASH_CS_DATA_OUT_SHIFT                 0


/****************************************************************************
 * GIO0 :: FLASH_CS_OE
 ***************************************************************************/
/* GIO0 :: FLASH_CS_OE :: reserved0 [31:04] */
#define GIO0_FLASH_CS_OE_RESERVED0_MASK                            0xfffffff0
#define GIO0_FLASH_CS_OE_RESERVED0_ALIGN                           0
#define GIO0_FLASH_CS_OE_RESERVED0_BITS                            28
#define GIO0_FLASH_CS_OE_RESERVED0_SHIFT                           4

/* GIO0 :: FLASH_CS_OE :: FLASH_CS_OE_RESERVED_1 [03:01] */
#define Wr_GIO0_FLASH_CS_OE_FLASH_CS_OE_RESERVED_1(x) WriteRegBits(GIO0_FLASH_CS_OE,0xe,1,x)
#define Rd_GIO0_FLASH_CS_OE_FLASH_CS_OE_RESERVED_1(x) ReadRegBits(GIO0_FLASH_CS_OE,0xe,1)
#define GIO0_FLASH_CS_OE_FLASH_CS_OE_RESERVED_1_MASK               0x0000000e
#define GIO0_FLASH_CS_OE_FLASH_CS_OE_RESERVED_1_ALIGN              0
#define GIO0_FLASH_CS_OE_FLASH_CS_OE_RESERVED_1_BITS               3
#define GIO0_FLASH_CS_OE_FLASH_CS_OE_RESERVED_1_SHIFT              1

/* GIO0 :: FLASH_CS_OE :: FLASH_CS_DATA_OE [00:00] */
#define Wr_GIO0_FLASH_CS_OE_FLASH_CS_DATA_OE(x) WriteRegBits(GIO0_FLASH_CS_OE,0x1,0,x)
#define Rd_GIO0_FLASH_CS_OE_FLASH_CS_DATA_OE(x) ReadRegBits(GIO0_FLASH_CS_OE,0x1,0)
#define GIO0_FLASH_CS_OE_FLASH_CS_DATA_OE_MASK                     0x00000001
#define GIO0_FLASH_CS_OE_FLASH_CS_DATA_OE_ALIGN                    0
#define GIO0_FLASH_CS_OE_FLASH_CS_DATA_OE_BITS                     1
#define GIO0_FLASH_CS_OE_FLASH_CS_DATA_OE_SHIFT                    0


/****************************************************************************
 * GIO0 :: GPIO_G2_INT_TYP
 ***************************************************************************/
/* GIO0 :: GPIO_G2_INT_TYP :: reserved0 [31:01] */
#define GIO0_GPIO_G2_INT_TYP_RESERVED0_MASK                        0xfffffffe
#define GIO0_GPIO_G2_INT_TYP_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G2_INT_TYP_RESERVED0_BITS                        31
#define GIO0_GPIO_G2_INT_TYP_RESERVED0_SHIFT                       1

/* GIO0 :: GPIO_G2_INT_TYP :: GPIO_G2_INT_TYP_GPIO_INT_TYP [00:00] */
#define Wr_GIO0_GPIO_G2_INT_TYP_GPIO_G2_INT_TYP_GPIO_INT_TYP(x) WriteRegBits(GIO0_GPIO_G2_INT_TYP,0x1,0,x)
#define Rd_GIO0_GPIO_G2_INT_TYP_GPIO_G2_INT_TYP_GPIO_INT_TYP(x) ReadRegBits(GIO0_GPIO_G2_INT_TYP,0x1,0)
#define GIO0_GPIO_G2_INT_TYP_GPIO_G2_INT_TYP_GPIO_INT_TYP_MASK     0x00000001
#define GIO0_GPIO_G2_INT_TYP_GPIO_G2_INT_TYP_GPIO_INT_TYP_ALIGN    0
#define GIO0_GPIO_G2_INT_TYP_GPIO_G2_INT_TYP_GPIO_INT_TYP_BITS     1
#define GIO0_GPIO_G2_INT_TYP_GPIO_G2_INT_TYP_GPIO_INT_TYP_SHIFT    0


/****************************************************************************
 * GIO0 :: GPIO_G2_INT_DU_EDG
 ***************************************************************************/
/* GIO0 :: GPIO_G2_INT_DU_EDG :: reserved0 [31:01] */
#define GIO0_GPIO_G2_INT_DU_EDG_RESERVED0_MASK                     0xfffffffe
#define GIO0_GPIO_G2_INT_DU_EDG_RESERVED0_ALIGN                    0
#define GIO0_GPIO_G2_INT_DU_EDG_RESERVED0_BITS                     31
#define GIO0_GPIO_G2_INT_DU_EDG_RESERVED0_SHIFT                    1

/* GIO0 :: GPIO_G2_INT_DU_EDG :: GPIO_G2_INT_DU_EDG_GPIO_INT_DU_EDGE [00:00] */
#define Wr_GIO0_GPIO_G2_INT_DU_EDG_GPIO_G2_INT_DU_EDG_GPIO_INT_DU_EDGE(x) WriteRegBits(GIO0_GPIO_G2_INT_DU_EDG,0x1,0,x)
#define Rd_GIO0_GPIO_G2_INT_DU_EDG_GPIO_G2_INT_DU_EDG_GPIO_INT_DU_EDGE(x) ReadRegBits(GIO0_GPIO_G2_INT_DU_EDG,0x1,0)
#define GIO0_GPIO_G2_INT_DU_EDG_GPIO_G2_INT_DU_EDG_GPIO_INT_DU_EDGE_MASK 0x00000001
#define GIO0_GPIO_G2_INT_DU_EDG_GPIO_G2_INT_DU_EDG_GPIO_INT_DU_EDGE_ALIGN 0
#define GIO0_GPIO_G2_INT_DU_EDG_GPIO_G2_INT_DU_EDG_GPIO_INT_DU_EDGE_BITS 1
#define GIO0_GPIO_G2_INT_DU_EDG_GPIO_G2_INT_DU_EDG_GPIO_INT_DU_EDGE_SHIFT 0


/****************************************************************************
 * GIO0 :: GPIO_G2_INT_EDG_LVL_SEL
 ***************************************************************************/
/* GIO0 :: GPIO_G2_INT_EDG_LVL_SEL :: reserved0 [31:01] */
#define GIO0_GPIO_G2_INT_EDG_LVL_SEL_RESERVED0_MASK                0xfffffffe
#define GIO0_GPIO_G2_INT_EDG_LVL_SEL_RESERVED0_ALIGN               0
#define GIO0_GPIO_G2_INT_EDG_LVL_SEL_RESERVED0_BITS                31
#define GIO0_GPIO_G2_INT_EDG_LVL_SEL_RESERVED0_SHIFT               1

/* GIO0 :: GPIO_G2_INT_EDG_LVL_SEL :: GPIO_G2_INT_EDG_LVL_SEL_GPIO_INT_EDGE [00:00] */
#define Wr_GIO0_GPIO_G2_INT_EDG_LVL_SEL_GPIO_G2_INT_EDG_LVL_SEL_GPIO_INT_EDGE(x) WriteRegBits(GIO0_GPIO_G2_INT_EDG_LVL_SEL,0x1,0,x)
#define Rd_GIO0_GPIO_G2_INT_EDG_LVL_SEL_GPIO_G2_INT_EDG_LVL_SEL_GPIO_INT_EDGE(x) ReadRegBits(GIO0_GPIO_G2_INT_EDG_LVL_SEL,0x1,0)
#define GIO0_GPIO_G2_INT_EDG_LVL_SEL_GPIO_G2_INT_EDG_LVL_SEL_GPIO_INT_EDGE_MASK 0x00000001
#define GIO0_GPIO_G2_INT_EDG_LVL_SEL_GPIO_G2_INT_EDG_LVL_SEL_GPIO_INT_EDGE_ALIGN 0
#define GIO0_GPIO_G2_INT_EDG_LVL_SEL_GPIO_G2_INT_EDG_LVL_SEL_GPIO_INT_EDGE_BITS 1
#define GIO0_GPIO_G2_INT_EDG_LVL_SEL_GPIO_G2_INT_EDG_LVL_SEL_GPIO_INT_EDGE_SHIFT 0


/****************************************************************************
 * GIO0 :: GPIO_G2_INT_MSK
 ***************************************************************************/
/* GIO0 :: GPIO_G2_INT_MSK :: reserved0 [31:01] */
#define GIO0_GPIO_G2_INT_MSK_RESERVED0_MASK                        0xfffffffe
#define GIO0_GPIO_G2_INT_MSK_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G2_INT_MSK_RESERVED0_BITS                        31
#define GIO0_GPIO_G2_INT_MSK_RESERVED0_SHIFT                       1

/* GIO0 :: GPIO_G2_INT_MSK :: GPIO_G2_INT_MSK_GPIO_INT_MSK [00:00] */
#define Wr_GIO0_GPIO_G2_INT_MSK_GPIO_G2_INT_MSK_GPIO_INT_MSK(x) WriteRegBits(GIO0_GPIO_G2_INT_MSK,0x1,0,x)
#define Rd_GIO0_GPIO_G2_INT_MSK_GPIO_G2_INT_MSK_GPIO_INT_MSK(x) ReadRegBits(GIO0_GPIO_G2_INT_MSK,0x1,0)
#define GIO0_GPIO_G2_INT_MSK_GPIO_G2_INT_MSK_GPIO_INT_MSK_MASK     0x00000001
#define GIO0_GPIO_G2_INT_MSK_GPIO_G2_INT_MSK_GPIO_INT_MSK_ALIGN    0
#define GIO0_GPIO_G2_INT_MSK_GPIO_G2_INT_MSK_GPIO_INT_MSK_BITS     1
#define GIO0_GPIO_G2_INT_MSK_GPIO_G2_INT_MSK_GPIO_INT_MSK_SHIFT    0


/****************************************************************************
 * GIO0 :: GPIO_G2_INT_STS
 ***************************************************************************/
/* GIO0 :: GPIO_G2_INT_STS :: reserved0 [31:01] */
#define GIO0_GPIO_G2_INT_STS_RESERVED0_MASK                        0xfffffffe
#define GIO0_GPIO_G2_INT_STS_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G2_INT_STS_RESERVED0_BITS                        31
#define GIO0_GPIO_G2_INT_STS_RESERVED0_SHIFT                       1

/* GIO0 :: GPIO_G2_INT_STS :: GPIO_G2_INT_STS_GPIO_INT_STS [00:00] */
#define Wr_GIO0_GPIO_G2_INT_STS_GPIO_G2_INT_STS_GPIO_INT_STS(x) WriteRegBits(GIO0_GPIO_G2_INT_STS,0x1,0,x)
#define Rd_GIO0_GPIO_G2_INT_STS_GPIO_G2_INT_STS_GPIO_INT_STS(x) ReadRegBits(GIO0_GPIO_G2_INT_STS,0x1,0)
#define GIO0_GPIO_G2_INT_STS_GPIO_G2_INT_STS_GPIO_INT_STS_MASK     0x00000001
#define GIO0_GPIO_G2_INT_STS_GPIO_G2_INT_STS_GPIO_INT_STS_ALIGN    0
#define GIO0_GPIO_G2_INT_STS_GPIO_G2_INT_STS_GPIO_INT_STS_BITS     1
#define GIO0_GPIO_G2_INT_STS_GPIO_G2_INT_STS_GPIO_INT_STS_SHIFT    0


/****************************************************************************
 * GIO0 :: GPIO_G2_INT_MSK_STS
 ***************************************************************************/
/* GIO0 :: GPIO_G2_INT_MSK_STS :: reserved0 [31:01] */
#define GIO0_GPIO_G2_INT_MSK_STS_RESERVED0_MASK                    0xfffffffe
#define GIO0_GPIO_G2_INT_MSK_STS_RESERVED0_ALIGN                   0
#define GIO0_GPIO_G2_INT_MSK_STS_RESERVED0_BITS                    31
#define GIO0_GPIO_G2_INT_MSK_STS_RESERVED0_SHIFT                   1

/* GIO0 :: GPIO_G2_INT_MSK_STS :: GPIO_G2_INT_MSK_STS_GPIO_INT_MSK_STS [00:00] */
#define Wr_GIO0_GPIO_G2_INT_MSK_STS_GPIO_G2_INT_MSK_STS_GPIO_INT_MSK_STS(x) WriteRegBits(GIO0_GPIO_G2_INT_MSK_STS,0x1,0,x)
#define Rd_GIO0_GPIO_G2_INT_MSK_STS_GPIO_G2_INT_MSK_STS_GPIO_INT_MSK_STS(x) ReadRegBits(GIO0_GPIO_G2_INT_MSK_STS,0x1,0)
#define GIO0_GPIO_G2_INT_MSK_STS_GPIO_G2_INT_MSK_STS_GPIO_INT_MSK_STS_MASK 0x00000001
#define GIO0_GPIO_G2_INT_MSK_STS_GPIO_G2_INT_MSK_STS_GPIO_INT_MSK_STS_ALIGN 0
#define GIO0_GPIO_G2_INT_MSK_STS_GPIO_G2_INT_MSK_STS_GPIO_INT_MSK_STS_BITS 1
#define GIO0_GPIO_G2_INT_MSK_STS_GPIO_G2_INT_MSK_STS_GPIO_INT_MSK_STS_SHIFT 0


/****************************************************************************
 * GIO0 :: GPIO_G2_INT_CLR
 ***************************************************************************/
/* GIO0 :: GPIO_G2_INT_CLR :: reserved0 [31:01] */
#define GIO0_GPIO_G2_INT_CLR_RESERVED0_MASK                        0xfffffffe
#define GIO0_GPIO_G2_INT_CLR_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G2_INT_CLR_RESERVED0_BITS                        31
#define GIO0_GPIO_G2_INT_CLR_RESERVED0_SHIFT                       1

/* GIO0 :: GPIO_G2_INT_CLR :: GPIO_G2_INT_CLR_GPIO_INT_CLR [00:00] */
#define Wr_GIO0_GPIO_G2_INT_CLR_GPIO_G2_INT_CLR_GPIO_INT_CLR(x) WriteRegBits(GIO0_GPIO_G2_INT_CLR,0x1,0,x)
#define Rd_GIO0_GPIO_G2_INT_CLR_GPIO_G2_INT_CLR_GPIO_INT_CLR(x) ReadRegBits(GIO0_GPIO_G2_INT_CLR,0x1,0)
#define GIO0_GPIO_G2_INT_CLR_GPIO_G2_INT_CLR_GPIO_INT_CLR_MASK     0x00000001
#define GIO0_GPIO_G2_INT_CLR_GPIO_G2_INT_CLR_GPIO_INT_CLR_ALIGN    0
#define GIO0_GPIO_G2_INT_CLR_GPIO_G2_INT_CLR_GPIO_INT_CLR_BITS     1
#define GIO0_GPIO_G2_INT_CLR_GPIO_G2_INT_CLR_GPIO_INT_CLR_SHIFT    0


/****************************************************************************
 * GIO0 :: GPIO_G2_FLASH_SEL
 ***************************************************************************/
/* GIO0 :: GPIO_G2_FLASH_SEL :: reserved0 [31:04] */
#define GIO0_GPIO_G2_FLASH_SEL_RESERVED0_MASK                      0xfffffff0
#define GIO0_GPIO_G2_FLASH_SEL_RESERVED0_ALIGN                     0
#define GIO0_GPIO_G2_FLASH_SEL_RESERVED0_BITS                      28
#define GIO0_GPIO_G2_FLASH_SEL_RESERVED0_SHIFT                     4

/* GIO0 :: GPIO_G2_FLASH_SEL :: GPIO_G2_FLASH_SEL_RESERVED_1 [03:01] */
#define Wr_GIO0_GPIO_G2_FLASH_SEL_GPIO_G2_FLASH_SEL_RESERVED_1(x) WriteRegBits(GIO0_GPIO_G2_FLASH_SEL,0xe,1,x)
#define Rd_GIO0_GPIO_G2_FLASH_SEL_GPIO_G2_FLASH_SEL_RESERVED_1(x) ReadRegBits(GIO0_GPIO_G2_FLASH_SEL,0xe,1)
#define GIO0_GPIO_G2_FLASH_SEL_GPIO_G2_FLASH_SEL_RESERVED_1_MASK   0x0000000e
#define GIO0_GPIO_G2_FLASH_SEL_GPIO_G2_FLASH_SEL_RESERVED_1_ALIGN  0
#define GIO0_GPIO_G2_FLASH_SEL_GPIO_G2_FLASH_SEL_RESERVED_1_BITS   3
#define GIO0_GPIO_G2_FLASH_SEL_GPIO_G2_FLASH_SEL_RESERVED_1_SHIFT  1

/* GIO0 :: GPIO_G2_FLASH_SEL :: GPIO_FLASH_CS_MUX_SEL [00:00] */
#define Wr_GIO0_GPIO_G2_FLASH_SEL_GPIO_FLASH_CS_MUX_SEL(x) WriteRegBits(GIO0_GPIO_G2_FLASH_SEL,0x1,0,x)
#define Rd_GIO0_GPIO_G2_FLASH_SEL_GPIO_FLASH_CS_MUX_SEL(x) ReadRegBits(GIO0_GPIO_G2_FLASH_SEL,0x1,0)
#define GIO0_GPIO_G2_FLASH_SEL_GPIO_FLASH_CS_MUX_SEL_MASK          0x00000001
#define GIO0_GPIO_G2_FLASH_SEL_GPIO_FLASH_CS_MUX_SEL_ALIGN         0
#define GIO0_GPIO_G2_FLASH_SEL_GPIO_FLASH_CS_MUX_SEL_BITS          1
#define GIO0_GPIO_G2_FLASH_SEL_GPIO_FLASH_CS_MUX_SEL_SHIFT         0


/****************************************************************************
 * GIO0 :: GPIO_G2_INT_POL
 ***************************************************************************/
/* GIO0 :: GPIO_G2_INT_POL :: reserved0 [31:05] */
#define GIO0_GPIO_G2_INT_POL_RESERVED0_MASK                        0xffffffe0
#define GIO0_GPIO_G2_INT_POL_RESERVED0_ALIGN                       0
#define GIO0_GPIO_G2_INT_POL_RESERVED0_BITS                        27
#define GIO0_GPIO_G2_INT_POL_RESERVED0_SHIFT                       5

/* GIO0 :: GPIO_G2_INT_POL :: GPIO_G2_INT_POL_RESERVED_1 [04:02] */
#define Wr_GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_RESERVED_1(x) WriteRegBits(GIO0_GPIO_G2_INT_POL,0x1c,2,x)
#define Rd_GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_RESERVED_1(x) ReadRegBits(GIO0_GPIO_G2_INT_POL,0x1c,2)
#define GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_RESERVED_1_MASK       0x0000001c
#define GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_RESERVED_1_ALIGN      0
#define GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_RESERVED_1_BITS       3
#define GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_RESERVED_1_SHIFT      2

/* GIO0 :: GPIO_G2_INT_POL :: GPIO_G2_INT_POL_GPIO_INT_POL [01:01] */
#define Wr_GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_GPIO_INT_POL(x) WriteRegBits(GIO0_GPIO_G2_INT_POL,0x2,1,x)
#define Rd_GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_GPIO_INT_POL(x) ReadRegBits(GIO0_GPIO_G2_INT_POL,0x2,1)
#define GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_GPIO_INT_POL_MASK     0x00000002
#define GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_GPIO_INT_POL_ALIGN    0
#define GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_GPIO_INT_POL_BITS     1
#define GIO0_GPIO_G2_INT_POL_GPIO_G2_INT_POL_GPIO_INT_POL_SHIFT    1

/* GIO0 :: GPIO_G2_INT_POL :: reserved1 [00:00] */
#define GIO0_GPIO_G2_INT_POL_RESERVED1_MASK                        0x00000001
#define GIO0_GPIO_G2_INT_POL_RESERVED1_ALIGN                       0
#define GIO0_GPIO_G2_INT_POL_RESERVED1_BITS                        1
#define GIO0_GPIO_G2_INT_POL_RESERVED1_SHIFT                       0


/****************************************************************************
 * bcm89530_sys_cfg_MMI
 ***************************************************************************/
/****************************************************************************
 * MMI :: mmi_ctrl
 ***************************************************************************/
/* MMI :: mmi_ctrl :: reserved0 [31:11] */
#define MMI_MMI_CTRL_RESERVED0_MASK                                0xfffff800
#define MMI_MMI_CTRL_RESERVED0_ALIGN                               0
#define MMI_MMI_CTRL_RESERVED0_BITS                                21
#define MMI_MMI_CTRL_RESERVED0_SHIFT                               11

/* MMI :: mmi_ctrl :: byp [10:10] */
#define Wr_MMI_mmi_ctrl_byp(x) WriteRegBits(MMI_MMI_CTRL,0x400,10,x)
#define Rd_MMI_mmi_ctrl_byp(x) ReadRegBits(MMI_MMI_CTRL,0x400,10)
#define MMI_MMI_CTRL_BYP_MASK                                      0x00000400
#define MMI_MMI_CTRL_BYP_ALIGN                                     0
#define MMI_MMI_CTRL_BYP_BITS                                      1
#define MMI_MMI_CTRL_BYP_SHIFT                                     10

/* MMI :: mmi_ctrl :: ext [09:09] */
#define Wr_MMI_mmi_ctrl_ext(x) WriteRegBits(MMI_MMI_CTRL,0x200,9,x)
#define Rd_MMI_mmi_ctrl_ext(x) ReadRegBits(MMI_MMI_CTRL,0x200,9)
#define MMI_MMI_CTRL_EXT_MASK                                      0x00000200
#define MMI_MMI_CTRL_EXT_ALIGN                                     0
#define MMI_MMI_CTRL_EXT_BITS                                      1
#define MMI_MMI_CTRL_EXT_SHIFT                                     9

/* MMI :: mmi_ctrl :: bsy [08:08] */
#define Wr_MMI_mmi_ctrl_bsy(x) WriteRegBits(MMI_MMI_CTRL,0x100,8,x)
#define Rd_MMI_mmi_ctrl_bsy(x) ReadRegBits(MMI_MMI_CTRL,0x100,8)
#define MMI_MMI_CTRL_BSY_MASK                                      0x00000100
#define MMI_MMI_CTRL_BSY_ALIGN                                     0
#define MMI_MMI_CTRL_BSY_BITS                                      1
#define MMI_MMI_CTRL_BSY_SHIFT                                     8

/* MMI :: mmi_ctrl :: pre [07:07] */
#define Wr_MMI_mmi_ctrl_pre(x) WriteRegBits(MMI_MMI_CTRL,0x80,7,x)
#define Rd_MMI_mmi_ctrl_pre(x) ReadRegBits(MMI_MMI_CTRL,0x80,7)
#define MMI_MMI_CTRL_PRE_MASK                                      0x00000080
#define MMI_MMI_CTRL_PRE_ALIGN                                     0
#define MMI_MMI_CTRL_PRE_BITS                                      1
#define MMI_MMI_CTRL_PRE_SHIFT                                     7

/* MMI :: mmi_ctrl :: mdcdiv [06:00] */
#define Wr_MMI_mmi_ctrl_mdcdiv(x) WriteRegBits(MMI_MMI_CTRL,0x7f,0,x)
#define Rd_MMI_mmi_ctrl_mdcdiv(x) ReadRegBits(MMI_MMI_CTRL,0x7f,0)
#define MMI_MMI_CTRL_MDCDIV_MASK                                   0x0000007f
#define MMI_MMI_CTRL_MDCDIV_ALIGN                                  0
#define MMI_MMI_CTRL_MDCDIV_BITS                                   7
#define MMI_MMI_CTRL_MDCDIV_SHIFT                                  0


/****************************************************************************
 * MMI :: mmi_cmd
 ***************************************************************************/
/* MMI :: mmi_cmd :: sb [31:30] */
#define Wr_MMI_mmi_cmd_sb(x) WriteRegBits(MMI_MMI_CMD,0xc0000000,30,x)
#define Rd_MMI_mmi_cmd_sb(x) ReadRegBits(MMI_MMI_CMD,0xc0000000,30)
#define MMI_MMI_CMD_SB_MASK                                        0xc0000000
#define MMI_MMI_CMD_SB_ALIGN                                       0
#define MMI_MMI_CMD_SB_BITS                                        2
#define MMI_MMI_CMD_SB_SHIFT                                       30

/* MMI :: mmi_cmd :: op [29:28] */
#define Wr_MMI_mmi_cmd_op(x) WriteRegBits(MMI_MMI_CMD,0x30000000,28,x)
#define Rd_MMI_mmi_cmd_op(x) ReadRegBits(MMI_MMI_CMD,0x30000000,28)
#define MMI_MMI_CMD_OP_MASK                                        0x30000000
#define MMI_MMI_CMD_OP_ALIGN                                       0
#define MMI_MMI_CMD_OP_BITS                                        2
#define MMI_MMI_CMD_OP_SHIFT                                       28

/* MMI :: mmi_cmd :: pa [27:23] */
#define Wr_MMI_mmi_cmd_pa(x) WriteRegBits(MMI_MMI_CMD,0xf800000,23,x)
#define Rd_MMI_mmi_cmd_pa(x) ReadRegBits(MMI_MMI_CMD,0xf800000,23)
#define MMI_MMI_CMD_PA_MASK                                        0x0f800000
#define MMI_MMI_CMD_PA_ALIGN                                       0
#define MMI_MMI_CMD_PA_BITS                                        5
#define MMI_MMI_CMD_PA_SHIFT                                       23

/* MMI :: mmi_cmd :: ra [22:18] */
#define Wr_MMI_mmi_cmd_ra(x) WriteRegBits(MMI_MMI_CMD,0x7c0000,18,x)
#define Rd_MMI_mmi_cmd_ra(x) ReadRegBits(MMI_MMI_CMD,0x7c0000,18)
#define MMI_MMI_CMD_RA_MASK                                        0x007c0000
#define MMI_MMI_CMD_RA_ALIGN                                       0
#define MMI_MMI_CMD_RA_BITS                                        5
#define MMI_MMI_CMD_RA_SHIFT                                       18

/* MMI :: mmi_cmd :: ta [17:16] */
#define Wr_MMI_mmi_cmd_ta(x) WriteRegBits(MMI_MMI_CMD,0x30000,16,x)
#define Rd_MMI_mmi_cmd_ta(x) ReadRegBits(MMI_MMI_CMD,0x30000,16)
#define MMI_MMI_CMD_TA_MASK                                        0x00030000
#define MMI_MMI_CMD_TA_ALIGN                                       0
#define MMI_MMI_CMD_TA_BITS                                        2
#define MMI_MMI_CMD_TA_SHIFT                                       16

/* MMI :: mmi_cmd :: mdata [15:00] */
#define Wr_MMI_mmi_cmd_mdata(x) WriteRegBits(MMI_MMI_CMD,0xffff,0,x)
#define Rd_MMI_mmi_cmd_mdata(x) ReadRegBits(MMI_MMI_CMD,0xffff,0)
#define MMI_MMI_CMD_MDATA_MASK                                     0x0000ffff
#define MMI_MMI_CMD_MDATA_ALIGN                                    0
#define MMI_MMI_CMD_MDATA_BITS                                     16
#define MMI_MMI_CMD_MDATA_SHIFT                                    0


/****************************************************************************
 * bcm89530_sys_cfg_PKA
 ***************************************************************************/
/****************************************************************************
 * PKA :: CONTROL_STATUS
 ***************************************************************************/
/* PKA :: CONTROL_STATUS :: PKA_ERR_UNKNOWN_OPC [31:31] */
#define Wr_PKA_CONTROL_STATUS_PKA_ERR_UNKNOWN_OPC(x) WriteRegBits(PKA_CONTROL_STATUS,0x80000000,31,x)
#define Rd_PKA_CONTROL_STATUS_PKA_ERR_UNKNOWN_OPC(x) ReadRegBits(PKA_CONTROL_STATUS,0x80000000,31)
#define PKA_CONTROL_STATUS_PKA_ERR_UNKNOWN_OPC_MASK                0x80000000
#define PKA_CONTROL_STATUS_PKA_ERR_UNKNOWN_OPC_ALIGN               0
#define PKA_CONTROL_STATUS_PKA_ERR_UNKNOWN_OPC_BITS                1
#define PKA_CONTROL_STATUS_PKA_ERR_UNKNOWN_OPC_SHIFT               31

/* PKA :: CONTROL_STATUS :: PKA_ERR_INVALID_SRC0 [30:30] */
#define Wr_PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC0(x) WriteRegBits(PKA_CONTROL_STATUS,0x40000000,30,x)
#define Rd_PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC0(x) ReadRegBits(PKA_CONTROL_STATUS,0x40000000,30)
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC0_MASK               0x40000000
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC0_ALIGN              0
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC0_BITS               1
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC0_SHIFT              30

/* PKA :: CONTROL_STATUS :: PKA_ERR_INVALID_SRC1 [29:29] */
#define Wr_PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC1(x) WriteRegBits(PKA_CONTROL_STATUS,0x20000000,29,x)
#define Rd_PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC1(x) ReadRegBits(PKA_CONTROL_STATUS,0x20000000,29)
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC1_MASK               0x20000000
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC1_ALIGN              0
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC1_BITS               1
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC1_SHIFT              29

/* PKA :: CONTROL_STATUS :: PKA_ERR_INVALID_SRC2 [28:28] */
#define Wr_PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC2(x) WriteRegBits(PKA_CONTROL_STATUS,0x10000000,28,x)
#define Rd_PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC2(x) ReadRegBits(PKA_CONTROL_STATUS,0x10000000,28)
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC2_MASK               0x10000000
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC2_ALIGN              0
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC2_BITS               1
#define PKA_CONTROL_STATUS_PKA_ERR_INVALID_SRC2_SHIFT              28

/* PKA :: CONTROL_STATUS :: PKA_ERR_CAM_FULL [27:27] */
#define Wr_PKA_CONTROL_STATUS_PKA_ERR_CAM_FULL(x) WriteRegBits(PKA_CONTROL_STATUS,0x8000000,27,x)
#define Rd_PKA_CONTROL_STATUS_PKA_ERR_CAM_FULL(x) ReadRegBits(PKA_CONTROL_STATUS,0x8000000,27)
#define PKA_CONTROL_STATUS_PKA_ERR_CAM_FULL_MASK                   0x08000000
#define PKA_CONTROL_STATUS_PKA_ERR_CAM_FULL_ALIGN                  0
#define PKA_CONTROL_STATUS_PKA_ERR_CAM_FULL_BITS                   1
#define PKA_CONTROL_STATUS_PKA_ERR_CAM_FULL_SHIFT                  27

/* PKA :: CONTROL_STATUS :: PKA_ERR_DIV_BY_0 [26:26] */
#define Wr_PKA_CONTROL_STATUS_PKA_ERR_DIV_BY_0(x) WriteRegBits(PKA_CONTROL_STATUS,0x4000000,26,x)
#define Rd_PKA_CONTROL_STATUS_PKA_ERR_DIV_BY_0(x) ReadRegBits(PKA_CONTROL_STATUS,0x4000000,26)
#define PKA_CONTROL_STATUS_PKA_ERR_DIV_BY_0_MASK                   0x04000000
#define PKA_CONTROL_STATUS_PKA_ERR_DIV_BY_0_ALIGN                  0
#define PKA_CONTROL_STATUS_PKA_ERR_DIV_BY_0_BITS                   1
#define PKA_CONTROL_STATUS_PKA_ERR_DIV_BY_0_SHIFT                  26

/* PKA :: CONTROL_STATUS :: PKA_ERR_OPQ_OVERFLOW [25:25] */
#define Wr_PKA_CONTROL_STATUS_PKA_ERR_OPQ_OVERFLOW(x) WriteRegBits(PKA_CONTROL_STATUS,0x2000000,25,x)
#define Rd_PKA_CONTROL_STATUS_PKA_ERR_OPQ_OVERFLOW(x) ReadRegBits(PKA_CONTROL_STATUS,0x2000000,25)
#define PKA_CONTROL_STATUS_PKA_ERR_OPQ_OVERFLOW_MASK               0x02000000
#define PKA_CONTROL_STATUS_PKA_ERR_OPQ_OVERFLOW_ALIGN              0
#define PKA_CONTROL_STATUS_PKA_ERR_OPQ_OVERFLOW_BITS               1
#define PKA_CONTROL_STATUS_PKA_ERR_OPQ_OVERFLOW_SHIFT              25

/* PKA :: CONTROL_STATUS :: ERR_OPC_INDEX [24:20] */
#define Wr_PKA_CONTROL_STATUS_ERR_OPC_INDEX(x) WriteRegBits(PKA_CONTROL_STATUS,0x1f00000,20,x)
#define Rd_PKA_CONTROL_STATUS_ERR_OPC_INDEX(x) ReadRegBits(PKA_CONTROL_STATUS,0x1f00000,20)
#define PKA_CONTROL_STATUS_ERR_OPC_INDEX_MASK                      0x01f00000
#define PKA_CONTROL_STATUS_ERR_OPC_INDEX_ALIGN                     0
#define PKA_CONTROL_STATUS_ERR_OPC_INDEX_BITS                      5
#define PKA_CONTROL_STATUS_ERR_OPC_INDEX_SHIFT                     20

/* PKA :: CONTROL_STATUS :: ESCAPE [19:16] */
#define Wr_PKA_CONTROL_STATUS_ESCAPE(x) WriteRegBits(PKA_CONTROL_STATUS,0xf0000,16,x)
#define Rd_PKA_CONTROL_STATUS_ESCAPE(x) ReadRegBits(PKA_CONTROL_STATUS,0xf0000,16)
#define PKA_CONTROL_STATUS_ESCAPE_MASK                             0x000f0000
#define PKA_CONTROL_STATUS_ESCAPE_ALIGN                            0
#define PKA_CONTROL_STATUS_ESCAPE_BITS                             4
#define PKA_CONTROL_STATUS_ESCAPE_SHIFT                            16

/* PKA :: CONTROL_STATUS :: reserved0 [15:14] */
#define PKA_CONTROL_STATUS_RESERVED0_MASK                          0x0000c000
#define PKA_CONTROL_STATUS_RESERVED0_ALIGN                         0
#define PKA_CONTROL_STATUS_RESERVED0_BITS                          2
#define PKA_CONTROL_STATUS_RESERVED0_SHIFT                         14

/* PKA :: CONTROL_STATUS :: ENDIAN_SEL [13:13] */
#define Wr_PKA_CONTROL_STATUS_ENDIAN_SEL(x) WriteRegBits(PKA_CONTROL_STATUS,0x2000,13,x)
#define Rd_PKA_CONTROL_STATUS_ENDIAN_SEL(x) ReadRegBits(PKA_CONTROL_STATUS,0x2000,13)
#define PKA_CONTROL_STATUS_ENDIAN_SEL_MASK                         0x00002000
#define PKA_CONTROL_STATUS_ENDIAN_SEL_ALIGN                        0
#define PKA_CONTROL_STATUS_ENDIAN_SEL_BITS                         1
#define PKA_CONTROL_STATUS_ENDIAN_SEL_SHIFT                        13

/* PKA :: CONTROL_STATUS :: MEMCLR_ON_RD [12:12] */
#define Wr_PKA_CONTROL_STATUS_MEMCLR_ON_RD(x) WriteRegBits(PKA_CONTROL_STATUS,0x1000,12,x)
#define Rd_PKA_CONTROL_STATUS_MEMCLR_ON_RD(x) ReadRegBits(PKA_CONTROL_STATUS,0x1000,12)
#define PKA_CONTROL_STATUS_MEMCLR_ON_RD_MASK                       0x00001000
#define PKA_CONTROL_STATUS_MEMCLR_ON_RD_ALIGN                      0
#define PKA_CONTROL_STATUS_MEMCLR_ON_RD_BITS                       1
#define PKA_CONTROL_STATUS_MEMCLR_ON_RD_SHIFT                      12

/* PKA :: CONTROL_STATUS :: reserved1 [11:11] */
#define PKA_CONTROL_STATUS_RESERVED1_MASK                          0x00000800
#define PKA_CONTROL_STATUS_RESERVED1_ALIGN                         0
#define PKA_CONTROL_STATUS_RESERVED1_BITS                          1
#define PKA_CONTROL_STATUS_RESERVED1_SHIFT                         11

/* PKA :: CONTROL_STATUS :: OPQ_FULL [10:10] */
#define Wr_PKA_CONTROL_STATUS_OPQ_FULL(x) WriteRegBits(PKA_CONTROL_STATUS,0x400,10,x)
#define Rd_PKA_CONTROL_STATUS_OPQ_FULL(x) ReadRegBits(PKA_CONTROL_STATUS,0x400,10)
#define PKA_CONTROL_STATUS_OPQ_FULL_MASK                           0x00000400
#define PKA_CONTROL_STATUS_OPQ_FULL_ALIGN                          0
#define PKA_CONTROL_STATUS_OPQ_FULL_BITS                           1
#define PKA_CONTROL_STATUS_OPQ_FULL_SHIFT                          10

/* PKA :: CONTROL_STATUS :: PPSEL_FAILED [09:09] */
#define Wr_PKA_CONTROL_STATUS_PPSEL_FAILED(x) WriteRegBits(PKA_CONTROL_STATUS,0x200,9,x)
#define Rd_PKA_CONTROL_STATUS_PPSEL_FAILED(x) ReadRegBits(PKA_CONTROL_STATUS,0x200,9)
#define PKA_CONTROL_STATUS_PPSEL_FAILED_MASK                       0x00000200
#define PKA_CONTROL_STATUS_PPSEL_FAILED_ALIGN                      0
#define PKA_CONTROL_STATUS_PPSEL_FAILED_BITS                       1
#define PKA_CONTROL_STATUS_PPSEL_FAILED_SHIFT                      9

/* PKA :: CONTROL_STATUS :: LAST_OPC_COUT [08:08] */
#define Wr_PKA_CONTROL_STATUS_LAST_OPC_COUT(x) WriteRegBits(PKA_CONTROL_STATUS,0x100,8,x)
#define Rd_PKA_CONTROL_STATUS_LAST_OPC_COUT(x) ReadRegBits(PKA_CONTROL_STATUS,0x100,8)
#define PKA_CONTROL_STATUS_LAST_OPC_COUT_MASK                      0x00000100
#define PKA_CONTROL_STATUS_LAST_OPC_COUT_ALIGN                     0
#define PKA_CONTROL_STATUS_LAST_OPC_COUT_BITS                      1
#define PKA_CONTROL_STATUS_LAST_OPC_COUT_SHIFT                     8

/* PKA :: CONTROL_STATUS :: PKA_RST [07:07] */
#define Wr_PKA_CONTROL_STATUS_PKA_RST(x) WriteRegBits(PKA_CONTROL_STATUS,0x80,7,x)
#define Rd_PKA_CONTROL_STATUS_PKA_RST(x) ReadRegBits(PKA_CONTROL_STATUS,0x80,7)
#define PKA_CONTROL_STATUS_PKA_RST_MASK                            0x00000080
#define PKA_CONTROL_STATUS_PKA_RST_ALIGN                           0
#define PKA_CONTROL_STATUS_PKA_RST_BITS                            1
#define PKA_CONTROL_STATUS_PKA_RST_SHIFT                           7

/* PKA :: CONTROL_STATUS :: reserved2 [06:04] */
#define PKA_CONTROL_STATUS_RESERVED2_MASK                          0x00000070
#define PKA_CONTROL_STATUS_RESERVED2_ALIGN                         0
#define PKA_CONTROL_STATUS_RESERVED2_BITS                          3
#define PKA_CONTROL_STATUS_RESERVED2_SHIFT                         4

/* PKA :: CONTROL_STATUS :: CMD_ERR [03:03] */
#define Wr_PKA_CONTROL_STATUS_CMD_ERR(x) WriteRegBits(PKA_CONTROL_STATUS,0x8,3,x)
#define Rd_PKA_CONTROL_STATUS_CMD_ERR(x) ReadRegBits(PKA_CONTROL_STATUS,0x8,3)
#define PKA_CONTROL_STATUS_CMD_ERR_MASK                            0x00000008
#define PKA_CONTROL_STATUS_CMD_ERR_ALIGN                           0
#define PKA_CONTROL_STATUS_CMD_ERR_BITS                            1
#define PKA_CONTROL_STATUS_CMD_ERR_SHIFT                           3

/* PKA :: CONTROL_STATUS :: PKA_BUSY [02:02] */
#define Wr_PKA_CONTROL_STATUS_PKA_BUSY(x) WriteRegBits(PKA_CONTROL_STATUS,0x4,2,x)
#define Rd_PKA_CONTROL_STATUS_PKA_BUSY(x) ReadRegBits(PKA_CONTROL_STATUS,0x4,2)
#define PKA_CONTROL_STATUS_PKA_BUSY_MASK                           0x00000004
#define PKA_CONTROL_STATUS_PKA_BUSY_ALIGN                          0
#define PKA_CONTROL_STATUS_PKA_BUSY_BITS                           1
#define PKA_CONTROL_STATUS_PKA_BUSY_SHIFT                          2

/* PKA :: CONTROL_STATUS :: CMD_DONE [01:01] */
#define Wr_PKA_CONTROL_STATUS_CMD_DONE(x) WriteRegBits(PKA_CONTROL_STATUS,0x2,1,x)
#define Rd_PKA_CONTROL_STATUS_CMD_DONE(x) ReadRegBits(PKA_CONTROL_STATUS,0x2,1)
#define PKA_CONTROL_STATUS_CMD_DONE_MASK                           0x00000002
#define PKA_CONTROL_STATUS_CMD_DONE_ALIGN                          0
#define PKA_CONTROL_STATUS_CMD_DONE_BITS                           1
#define PKA_CONTROL_STATUS_CMD_DONE_SHIFT                          1

/* PKA :: CONTROL_STATUS :: PKA_EN [00:00] */
#define Wr_PKA_CONTROL_STATUS_PKA_EN(x) WriteRegBits(PKA_CONTROL_STATUS,0x1,0,x)
#define Rd_PKA_CONTROL_STATUS_PKA_EN(x) ReadRegBits(PKA_CONTROL_STATUS,0x1,0)
#define PKA_CONTROL_STATUS_PKA_EN_MASK                             0x00000001
#define PKA_CONTROL_STATUS_PKA_EN_ALIGN                            0
#define PKA_CONTROL_STATUS_PKA_EN_BITS                             1
#define PKA_CONTROL_STATUS_PKA_EN_SHIFT                            0


/****************************************************************************
 * PKA :: DATA_INPUT
 ***************************************************************************/
/* PKA :: DATA_INPUT :: PKA_DIN [31:00] */
#define Wr_PKA_DATA_INPUT_PKA_DIN(x) WriteReg(PKA_DATA_INPUT,x)
#define Rd_PKA_DATA_INPUT_PKA_DIN(x) ReadReg(PKA_DATA_INPUT)
#define PKA_DATA_INPUT_PKA_DIN_MASK                                0xffffffff
#define PKA_DATA_INPUT_PKA_DIN_ALIGN                               0
#define PKA_DATA_INPUT_PKA_DIN_BITS                                32
#define PKA_DATA_INPUT_PKA_DIN_SHIFT                               0


/****************************************************************************
 * PKA :: DATA_OUTPUT
 ***************************************************************************/
/* PKA :: DATA_OUTPUT :: PKA_DOUT [31:00] */
#define Wr_PKA_DATA_OUTPUT_PKA_DOUT(x) WriteReg(PKA_DATA_OUTPUT,x)
#define Rd_PKA_DATA_OUTPUT_PKA_DOUT(x) ReadReg(PKA_DATA_OUTPUT)
#define PKA_DATA_OUTPUT_PKA_DOUT_MASK                              0xffffffff
#define PKA_DATA_OUTPUT_PKA_DOUT_ALIGN                             0
#define PKA_DATA_OUTPUT_PKA_DOUT_BITS                              32
#define PKA_DATA_OUTPUT_PKA_DOUT_SHIFT                             0


/****************************************************************************
 * PKA :: ACCESS_CONTROL
 ***************************************************************************/
/* PKA :: ACCESS_CONTROL :: PKA_LOCK [31:31] */
#define Wr_PKA_ACCESS_CONTROL_PKA_LOCK(x) WriteRegBits(PKA_ACCESS_CONTROL,0x80000000,31,x)
#define Rd_PKA_ACCESS_CONTROL_PKA_LOCK(x) ReadRegBits(PKA_ACCESS_CONTROL,0x80000000,31)
#define PKA_ACCESS_CONTROL_PKA_LOCK_MASK                           0x80000000
#define PKA_ACCESS_CONTROL_PKA_LOCK_ALIGN                          0
#define PKA_ACCESS_CONTROL_PKA_LOCK_BITS                           1
#define PKA_ACCESS_CONTROL_PKA_LOCK_SHIFT                          31

/* PKA :: ACCESS_CONTROL :: reserved0 [30:16] */
#define PKA_ACCESS_CONTROL_RESERVED0_MASK                          0x7fff0000
#define PKA_ACCESS_CONTROL_RESERVED0_ALIGN                         0
#define PKA_ACCESS_CONTROL_RESERVED0_BITS                          15
#define PKA_ACCESS_CONTROL_RESERVED0_SHIFT                         16

/* PKA :: ACCESS_CONTROL :: LOCKED [15:15] */
#define Wr_PKA_ACCESS_CONTROL_LOCKED(x) WriteRegBits(PKA_ACCESS_CONTROL,0x8000,15,x)
#define Rd_PKA_ACCESS_CONTROL_LOCKED(x) ReadRegBits(PKA_ACCESS_CONTROL,0x8000,15)
#define PKA_ACCESS_CONTROL_LOCKED_MASK                             0x00008000
#define PKA_ACCESS_CONTROL_LOCKED_ALIGN                            0
#define PKA_ACCESS_CONTROL_LOCKED_BITS                             1
#define PKA_ACCESS_CONTROL_LOCKED_SHIFT                            15

/* PKA :: ACCESS_CONTROL :: reserved1 [14:00] */
#define PKA_ACCESS_CONTROL_RESERVED1_MASK                          0x00007fff
#define PKA_ACCESS_CONTROL_RESERVED1_ALIGN                         0
#define PKA_ACCESS_CONTROL_RESERVED1_BITS                          15
#define PKA_ACCESS_CONTROL_RESERVED1_SHIFT                         0


/****************************************************************************
 * PKA :: SCA_LFSR_SEED
 ***************************************************************************/
/* PKA :: SCA_LFSR_SEED :: LFSR_SEED [31:00] */
#define Wr_PKA_SCA_LFSR_SEED_LFSR_SEED(x) WriteReg(PKA_SCA_LFSR_SEED,x)
#define Rd_PKA_SCA_LFSR_SEED_LFSR_SEED(x) ReadReg(PKA_SCA_LFSR_SEED)
#define PKA_SCA_LFSR_SEED_LFSR_SEED_MASK                           0xffffffff
#define PKA_SCA_LFSR_SEED_LFSR_SEED_ALIGN                          0
#define PKA_SCA_LFSR_SEED_LFSR_SEED_BITS                           32
#define PKA_SCA_LFSR_SEED_LFSR_SEED_SHIFT                          0


/****************************************************************************
 * bcm89530_sys_cfg_RNG
 ***************************************************************************/
/****************************************************************************
 * RNG :: CTRL
 ***************************************************************************/
/* RNG :: CTRL :: reserved0 [31:02] */
#define RNG_CTRL_RESERVED0_MASK                                    0xfffffffc
#define RNG_CTRL_RESERVED0_ALIGN                                   0
#define RNG_CTRL_RESERVED0_BITS                                    30
#define RNG_CTRL_RESERVED0_SHIFT                                   2

/* RNG :: CTRL :: RBG_2X [01:01] */
#define Wr_RNG_CTRL_RBG_2X(x) WriteRegBits(RNG_CTRL,0x2,1,x)
#define Rd_RNG_CTRL_RBG_2X(x) ReadRegBits(RNG_CTRL,0x2,1)
#define RNG_CTRL_RBG_2X_MASK                                       0x00000002
#define RNG_CTRL_RBG_2X_ALIGN                                      0
#define RNG_CTRL_RBG_2X_BITS                                       1
#define RNG_CTRL_RBG_2X_SHIFT                                      1

/* RNG :: CTRL :: RBG_EN [00:00] */
#define Wr_RNG_CTRL_RBG_EN(x) WriteRegBits(RNG_CTRL,0x1,0,x)
#define Rd_RNG_CTRL_RBG_EN(x) ReadRegBits(RNG_CTRL,0x1,0)
#define RNG_CTRL_RBG_EN_MASK                                       0x00000001
#define RNG_CTRL_RBG_EN_ALIGN                                      0
#define RNG_CTRL_RBG_EN_BITS                                       1
#define RNG_CTRL_RBG_EN_SHIFT                                      0


/****************************************************************************
 * RNG :: STATUS
 ***************************************************************************/
/* RNG :: STATUS :: RNG_VAL [31:24] */
#define Wr_RNG_STATUS_RNG_VAL(x) WriteRegBits(RNG_STATUS,0xff000000,24,x)
#define Rd_RNG_STATUS_RNG_VAL(x) ReadRegBits(RNG_STATUS,0xff000000,24)
#define RNG_STATUS_RNG_VAL_MASK                                    0xff000000
#define RNG_STATUS_RNG_VAL_ALIGN                                   0
#define RNG_STATUS_RNG_VAL_BITS                                    8
#define RNG_STATUS_RNG_VAL_SHIFT                                   24

/* RNG :: STATUS :: reserved0 [23:20] */
#define RNG_STATUS_RESERVED0_MASK                                  0x00f00000
#define RNG_STATUS_RESERVED0_ALIGN                                 0
#define RNG_STATUS_RESERVED0_BITS                                  4
#define RNG_STATUS_RESERVED0_SHIFT                                 20

/* RNG :: STATUS :: RNG_WARM [19:00] */
#define Wr_RNG_STATUS_RNG_WARM(x) WriteRegBits(RNG_STATUS,0xfffff,0,x)
#define Rd_RNG_STATUS_RNG_WARM(x) ReadRegBits(RNG_STATUS,0xfffff,0)
#define RNG_STATUS_RNG_WARM_MASK                                   0x000fffff
#define RNG_STATUS_RNG_WARM_ALIGN                                  0
#define RNG_STATUS_RNG_WARM_BITS                                   20
#define RNG_STATUS_RNG_WARM_SHIFT                                  0


/****************************************************************************
 * RNG :: DATA0
 ***************************************************************************/
/* RNG :: DATA0 :: RNG_NUM0 [31:00] */
#define Wr_RNG_DATA0_RNG_NUM0(x) WriteReg(RNG_DATA0,x)
#define Rd_RNG_DATA0_RNG_NUM0(x) ReadReg(RNG_DATA0)
#define RNG_DATA0_RNG_NUM0_MASK                                    0xffffffff
#define RNG_DATA0_RNG_NUM0_ALIGN                                   0
#define RNG_DATA0_RNG_NUM0_BITS                                    32
#define RNG_DATA0_RNG_NUM0_SHIFT                                   0


/****************************************************************************
 * RNG :: THRESHOLD
 ***************************************************************************/
/* RNG :: THRESHOLD :: reserved0 [31:05] */
#define RNG_THRESHOLD_RESERVED0_MASK                               0xffffffe0
#define RNG_THRESHOLD_RESERVED0_ALIGN                              0
#define RNG_THRESHOLD_RESERVED0_BITS                               27
#define RNG_THRESHOLD_RESERVED0_SHIFT                              5

/* RNG :: THRESHOLD :: RNG_THRSHLD [04:00] */
#define Wr_RNG_THRESHOLD_RNG_THRSHLD(x) WriteRegBits(RNG_THRESHOLD,0x1f,0,x)
#define Rd_RNG_THRESHOLD_RNG_THRSHLD(x) ReadRegBits(RNG_THRESHOLD,0x1f,0)
#define RNG_THRESHOLD_RNG_THRSHLD_MASK                             0x0000001f
#define RNG_THRESHOLD_RNG_THRSHLD_ALIGN                            0
#define RNG_THRESHOLD_RNG_THRSHLD_BITS                             5
#define RNG_THRESHOLD_RNG_THRSHLD_SHIFT                            0


/****************************************************************************
 * RNG :: INT_MASK
 ***************************************************************************/
/* RNG :: INT_MASK :: reserved0 [31:01] */
#define RNG_INT_MASK_RESERVED0_MASK                                0xfffffffe
#define RNG_INT_MASK_RESERVED0_ALIGN                               0
#define RNG_INT_MASK_RESERVED0_BITS                                31
#define RNG_INT_MASK_RESERVED0_SHIFT                               1

/* RNG :: INT_MASK :: RNG_INT_MASK [00:00] */
#define Wr_RNG_INT_MASK_RNG_INT_MASK(x) WriteRegBits(RNG_INT_MASK,0x1,0,x)
#define Rd_RNG_INT_MASK_RNG_INT_MASK(x) ReadRegBits(RNG_INT_MASK,0x1,0)
#define RNG_INT_MASK_RNG_INT_MASK_MASK                             0x00000001
#define RNG_INT_MASK_RNG_INT_MASK_ALIGN                            0
#define RNG_INT_MASK_RNG_INT_MASK_BITS                             1
#define RNG_INT_MASK_RNG_INT_MASK_SHIFT                            0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_CL45DEV1
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x8000,15)
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESET_BITS                   1
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved0 [14:14] */
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_MASK               0x4000
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_SHIFT              14

/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x2000,13)
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved1 [12:12] */
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_MASK               0x1000
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_BITS               1
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_SHIFT              12

/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x800,11)
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved2 [10:07] */
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_MASK               0x0780
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_BITS               4
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_SHIFT              7

/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x40,6)
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x3c,2)
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved3 [01:01] */
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_MASK               0x0002
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_BITS               1
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_SHIFT              1

/* BRPHY0_CL45DEV1 :: PMD_IEEE_CTL1 :: LPBK [00:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x1,0,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_CTL1,0x1,0)
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LPBK_MASK                    0x0001
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LPBK_ALIGN                   0
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LPBK_BITS                    1
#define BRPHY0_CL45DEV1_PMD_IEEE_CTL1_LPBK_SHIFT                   0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_ST1
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY0_CL45DEV1 :: PMD_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_ST1,0x80,7)
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_FAULT_BITS                    1
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY0_CL45DEV1 :: PMD_IEEE_ST1 :: reserved1 [06:03] */
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED1_MASK                0x0078
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED1_BITS                4
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY0_CL45DEV1 :: PMD_IEEE_ST1 :: RCV_LINK_ST [02:02] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_ST1,0x4,2)
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_MASK              0x0004
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_ALIGN             0
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_BITS              1
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_SHIFT             2

/* BRPHY0_CL45DEV1 :: PMD_IEEE_ST1 :: CAP_LOW_PWR [01:01] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_ST1,0x2,1)
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_MASK              0x0002
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_ALIGN             0
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_BITS              1
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_SHIFT             1

/* BRPHY0_CL45DEV1 :: PMD_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY0_CL45DEV1_PMD_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID0,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID0)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x80,7)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x40,6)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x20,5)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x10,4)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x8,3)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x4,2)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x2,1)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV0,0x1,0)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_DEV1
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV1,0x8000,15)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV1,0x4000,14)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_DEV1,0x2000,13)
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY0_CL45DEV1 :: PMD_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY0_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID0,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID0)
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID1,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID1)
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY0_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY0_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: TX_PMD_TSYNC_EN [01:01] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_MASK    0x0002
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_BITS    1
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_SHIFT   1

/* BRPHY0_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: RX_PMD_TSYNC_EN [00:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_MASK    0x0001
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_BITS    1
#define BRPHY0_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY0_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY0_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY0_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_CL45DEV3
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x8000,15)
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESET_BITS                   1
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1 :: PCS_LPBK [14:14] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x4000,14,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x4000,14)
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_MASK                0x4000
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_ALIGN               0
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_BITS                1
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_SHIFT               14

/* BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x2000,13)
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved0 [12:12] */
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_MASK               0x1000
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_SHIFT              12

/* BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x800,11)
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved1 [10:07] */
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_MASK               0x0780
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_BITS               4
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_SHIFT              7

/* BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x40,6)
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_CTL1,0x3c,2)
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY0_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved2 [01:00] */
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_MASK               0x0003
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_BITS               2
#define BRPHY0_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_SHIFT              0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_ST1
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY0_CL45DEV3 :: PCS_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_ST1,0x80,7)
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_FAULT_BITS                    1
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY0_CL45DEV3 :: PCS_IEEE_ST1 :: CLOCK_STOP_CAPABLE [06:06] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_ST1,0x40,6,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_ST1,0x40,6)
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_MASK       0x0040
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_ALIGN      0
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_BITS       1
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_SHIFT      6

/* BRPHY0_CL45DEV3 :: PCS_IEEE_ST1 :: reserved1 [05:03] */
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED1_MASK                0x0038
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED1_BITS                3
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY0_CL45DEV3 :: PCS_IEEE_ST1 :: PCS_RCV_LINK_ST [02:02] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_ST1,0x4,2)
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_MASK          0x0004
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_ALIGN         0
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_BITS          1
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_SHIFT         2

/* BRPHY0_CL45DEV3 :: PCS_IEEE_ST1 :: LOW_PWR_AB [01:01] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_ST1,0x2,1)
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_MASK               0x0002
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_BITS               1
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_SHIFT              1

/* BRPHY0_CL45DEV3 :: PCS_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY0_CL45DEV3_PCS_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID0,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID0)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x80,7)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x40,6)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x20,5)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x10,4)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x8,3)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x4,2)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x2,1)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV0,0x1,0)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_DEV1
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV1,0x8000,15)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV1,0x4000,14)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_DEV1,0x2000,13)
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY0_CL45DEV3 :: PCS_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY0_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID0,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID0)
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID1,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID1)
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY0_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_EEE_CAP
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_EEE_CAP :: reserved0 [15:07] */
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_RESERVED0_MASK                 0xff80
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_RESERVED0_ALIGN                0
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_RESERVED0_BITS                 9
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_RESERVED0_SHIFT                7

/* BRPHY0_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKR_EEE [06:06] */
#define Wr_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x40,6,x)
#define Rd_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x40,6)
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_MASK         0x0040
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_ALIGN        0
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_BITS         1
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_SHIFT        6

/* BRPHY0_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKX4_EEE [05:05] */
#define Wr_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x20,5,x)
#define Rd_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x20,5)
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_MASK        0x0020
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_ALIGN       0
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_BITS        1
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_SHIFT       5

/* BRPHY0_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASEKX_EEE [04:04] */
#define Wr_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x10,4,x)
#define Rd_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x10,4)
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_MASK        0x0010
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_ALIGN       0
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_BITS        1
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_SHIFT       4

/* BRPHY0_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASET_EEE [03:03] */
#define Wr_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x8,3,x)
#define Rd_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x8,3)
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_MASK          0x0008
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_ALIGN         0
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_BITS          1
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_SHIFT         3

/* BRPHY0_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASET_EEE [02:02] */
#define Wr_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x4,2,x)
#define Rd_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x4,2)
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_MASK         0x0004
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_ALIGN        0
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_BITS         1
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_SHIFT        2

/* BRPHY0_CL45DEV3 :: PCS_EEE_CAP :: PHY_100BASETX_EEE [01:01] */
#define Wr_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x2,1,x)
#define Rd_BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_EEE_CAP,0x2,1)
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_MASK         0x0002
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_ALIGN        0
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_BITS         1
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_SHIFT        1

/* BRPHY0_CL45DEV3 :: PCS_EEE_CAP :: reserved1 [00:00] */
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_RESERVED1_MASK                 0x0001
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_RESERVED1_ALIGN                0
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_RESERVED1_BITS                 1
#define BRPHY0_CL45DEV3_PCS_EEE_CAP_RESERVED1_SHIFT                0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt :: cnt [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) WriteReg16(BRPHY0_CL45DEV3_PCS_EEE_WAKE_ERR_CNT,x)
#define Rd_BRPHY0_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) ReadReg16(BRPHY0_CL45DEV3_PCS_EEE_WAKE_ERR_CNT)
#define BRPHY0_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_MASK              0xffff
#define BRPHY0_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_ALIGN             0
#define BRPHY0_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_BITS              16
#define BRPHY0_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_SHIFT             0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY0_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: TX_PCS_TSYNC_EN [01:01] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_MASK    0x0002
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_BITS    1
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_SHIFT   1

/* BRPHY0_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: RX_PCS_TSYNC_EN [00:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_MASK    0x0001
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_BITS    1
#define BRPHY0_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY0_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY0_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY0_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_CL45DEV7
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_CTRL
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_CTRL :: AN_reset [15:15] */
#define Wr_BRPHY0_CL45DEV7_AN_CTRL_AN_reset(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV7_AN_CTRL_AN_reset(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_CTRL,0x8000,15)
#define BRPHY0_CL45DEV7_AN_CTRL_AN_RESET_MASK                      0x8000
#define BRPHY0_CL45DEV7_AN_CTRL_AN_RESET_ALIGN                     0
#define BRPHY0_CL45DEV7_AN_CTRL_AN_RESET_BITS                      1
#define BRPHY0_CL45DEV7_AN_CTRL_AN_RESET_SHIFT                     15

/* BRPHY0_CL45DEV7 :: AN_CTRL :: reserved0 [14:14] */
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED0_MASK                     0x4000
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED0_ALIGN                    0
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED0_BITS                     1
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED0_SHIFT                    14

/* BRPHY0_CL45DEV7 :: AN_CTRL :: Extended_next_page_control [13:13] */
#define Wr_BRPHY0_CL45DEV7_AN_CTRL_Extended_next_page_control(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV7_AN_CTRL_Extended_next_page_control(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_CTRL,0x2000,13)
#define BRPHY0_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_MASK    0x2000
#define BRPHY0_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_ALIGN   0
#define BRPHY0_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_BITS    1
#define BRPHY0_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_SHIFT   13

/* BRPHY0_CL45DEV7 :: AN_CTRL :: Auto_Negotiation_enable [12:12] */
#define Wr_BRPHY0_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY0_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_CTRL,0x1000,12)
#define BRPHY0_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_MASK       0x1000
#define BRPHY0_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_ALIGN      0
#define BRPHY0_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_BITS       1
#define BRPHY0_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_SHIFT      12

/* BRPHY0_CL45DEV7 :: AN_CTRL :: reserved1 [11:10] */
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED1_MASK                     0x0c00
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED1_ALIGN                    0
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED1_BITS                     2
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED1_SHIFT                    10

/* BRPHY0_CL45DEV7 :: AN_CTRL :: Restart_Auto_Negotiation [09:09] */
#define Wr_BRPHY0_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_CTRL,0x200,9,x)
#define Rd_BRPHY0_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_CTRL,0x200,9)
#define BRPHY0_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_MASK      0x0200
#define BRPHY0_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_ALIGN     0
#define BRPHY0_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_BITS      1
#define BRPHY0_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_SHIFT     9

/* BRPHY0_CL45DEV7 :: AN_CTRL :: reserved2 [08:00] */
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED2_MASK                     0x01ff
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED2_ALIGN                    0
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED2_BITS                     9
#define BRPHY0_CL45DEV7_AN_CTRL_RESERVED2_SHIFT                    0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_STAT
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_STAT :: reserved0 [15:08] */
#define BRPHY0_CL45DEV7_AN_STAT_RESERVED0_MASK                     0xff00
#define BRPHY0_CL45DEV7_AN_STAT_RESERVED0_ALIGN                    0
#define BRPHY0_CL45DEV7_AN_STAT_RESERVED0_BITS                     8
#define BRPHY0_CL45DEV7_AN_STAT_RESERVED0_SHIFT                    8

/* BRPHY0_CL45DEV7 :: AN_STAT :: Extended_next_page_status [07:07] */
#define Wr_BRPHY0_CL45DEV7_AN_STAT_Extended_next_page_status(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x80,7,x)
#define Rd_BRPHY0_CL45DEV7_AN_STAT_Extended_next_page_status(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x80,7)
#define BRPHY0_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_MASK     0x0080
#define BRPHY0_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_ALIGN    0
#define BRPHY0_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_BITS     1
#define BRPHY0_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_SHIFT    7

/* BRPHY0_CL45DEV7 :: AN_STAT :: Page_received [06:06] */
#define Wr_BRPHY0_CL45DEV7_AN_STAT_Page_received(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x40,6,x)
#define Rd_BRPHY0_CL45DEV7_AN_STAT_Page_received(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x40,6)
#define BRPHY0_CL45DEV7_AN_STAT_PAGE_RECEIVED_MASK                 0x0040
#define BRPHY0_CL45DEV7_AN_STAT_PAGE_RECEIVED_ALIGN                0
#define BRPHY0_CL45DEV7_AN_STAT_PAGE_RECEIVED_BITS                 1
#define BRPHY0_CL45DEV7_AN_STAT_PAGE_RECEIVED_SHIFT                6

/* BRPHY0_CL45DEV7 :: AN_STAT :: AN_complete [05:05] */
#define Wr_BRPHY0_CL45DEV7_AN_STAT_AN_complete(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x20,5,x)
#define Rd_BRPHY0_CL45DEV7_AN_STAT_AN_complete(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x20,5)
#define BRPHY0_CL45DEV7_AN_STAT_AN_COMPLETE_MASK                   0x0020
#define BRPHY0_CL45DEV7_AN_STAT_AN_COMPLETE_ALIGN                  0
#define BRPHY0_CL45DEV7_AN_STAT_AN_COMPLETE_BITS                   1
#define BRPHY0_CL45DEV7_AN_STAT_AN_COMPLETE_SHIFT                  5

/* BRPHY0_CL45DEV7 :: AN_STAT :: Remodt_Fault [04:04] */
#define Wr_BRPHY0_CL45DEV7_AN_STAT_Remodt_Fault(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x10,4,x)
#define Rd_BRPHY0_CL45DEV7_AN_STAT_Remodt_Fault(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x10,4)
#define BRPHY0_CL45DEV7_AN_STAT_REMODT_FAULT_MASK                  0x0010
#define BRPHY0_CL45DEV7_AN_STAT_REMODT_FAULT_ALIGN                 0
#define BRPHY0_CL45DEV7_AN_STAT_REMODT_FAULT_BITS                  1
#define BRPHY0_CL45DEV7_AN_STAT_REMODT_FAULT_SHIFT                 4

/* BRPHY0_CL45DEV7 :: AN_STAT :: AN_ability [03:03] */
#define Wr_BRPHY0_CL45DEV7_AN_STAT_AN_ability(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x8,3,x)
#define Rd_BRPHY0_CL45DEV7_AN_STAT_AN_ability(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x8,3)
#define BRPHY0_CL45DEV7_AN_STAT_AN_ABILITY_MASK                    0x0008
#define BRPHY0_CL45DEV7_AN_STAT_AN_ABILITY_ALIGN                   0
#define BRPHY0_CL45DEV7_AN_STAT_AN_ABILITY_BITS                    1
#define BRPHY0_CL45DEV7_AN_STAT_AN_ABILITY_SHIFT                   3

/* BRPHY0_CL45DEV7 :: AN_STAT :: Link_status [02:02] */
#define Wr_BRPHY0_CL45DEV7_AN_STAT_Link_status(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x4,2,x)
#define Rd_BRPHY0_CL45DEV7_AN_STAT_Link_status(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x4,2)
#define BRPHY0_CL45DEV7_AN_STAT_LINK_STATUS_MASK                   0x0004
#define BRPHY0_CL45DEV7_AN_STAT_LINK_STATUS_ALIGN                  0
#define BRPHY0_CL45DEV7_AN_STAT_LINK_STATUS_BITS                   1
#define BRPHY0_CL45DEV7_AN_STAT_LINK_STATUS_SHIFT                  2

/* BRPHY0_CL45DEV7 :: AN_STAT :: reserved1 [01:01] */
#define BRPHY0_CL45DEV7_AN_STAT_RESERVED1_MASK                     0x0002
#define BRPHY0_CL45DEV7_AN_STAT_RESERVED1_ALIGN                    0
#define BRPHY0_CL45DEV7_AN_STAT_RESERVED1_BITS                     1
#define BRPHY0_CL45DEV7_AN_STAT_RESERVED1_SHIFT                    1

/* BRPHY0_CL45DEV7 :: AN_STAT :: Link_partner_AN_ability [00:00] */
#define Wr_BRPHY0_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x1,0,x)
#define Rd_BRPHY0_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_STAT,0x1,0)
#define BRPHY0_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_MASK       0x0001
#define BRPHY0_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY0_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY0_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_SHIFT      0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_DEV_ID_LSB
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_DEV_ID_LSB :: cu_an_device_identifier [15:00] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) WriteReg16(BRPHY0_CL45DEV7_AN_DEV_ID_LSB,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) ReadReg16(BRPHY0_CL45DEV7_AN_DEV_ID_LSB)
#define BRPHY0_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xffff
#define BRPHY0_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY0_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_BITS 16
#define BRPHY0_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_DEV_ID_MSB
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_DEV_ID_MSB :: cu_an_device_identifier [15:10] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10)
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xfc00
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_BITS 6
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 10

/* BRPHY0_CL45DEV7 :: AN_DEV_ID_MSB :: MODEL_NU [09:04] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4)
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_MASK                0x03f0
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_ALIGN               0
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_BITS                6
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_SHIFT               4

/* BRPHY0_CL45DEV7 :: AN_DEV_ID_MSB :: REV_NU [03:00] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_ID_MSB,0xf,0,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_ID_MSB,0xf,0)
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_REV_NU_MASK                  0x000f
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_REV_NU_ALIGN                 0
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_REV_NU_BITS                  4
#define BRPHY0_CL45DEV7_AN_DEV_ID_MSB_REV_NU_SHIFT                 0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: reserved0 [15:08] */
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_MASK           0xff00
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_ALIGN          0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_BITS           8
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_SHIFT          8

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_MASK         0x0080
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_ALIGN        0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_BITS         1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_SHIFT        7

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: TC_PRE [06:06] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_MASK              0x0040
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_ALIGN             0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_BITS              1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_SHIFT             6

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: DTEXS_PRE [05:05] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_MASK           0x0020
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_ALIGN          0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_BITS           1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_SHIFT          5

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PHYXS_PRE [04:04] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_MASK           0x0010
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_ALIGN          0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_BITS           1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_SHIFT          4

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PCS_PRE [03:03] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_MASK             0x0008
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_ALIGN            0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_BITS             1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_SHIFT            3

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: WIS_PRE [02:02] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_MASK             0x0004
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_ALIGN            0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_BITS             1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_SHIFT            2

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PMD_PRE [01:01] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_MASK             0x0002
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_ALIGN            0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_BITS             1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_SHIFT            1

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: CLA22_PRE [00:00] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_MASK           0x0001
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_ALIGN          0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_BITS           1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_SHIFT          0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_MSB
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_MASK      0x8000
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_ALIGN     0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_BITS      1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_SHIFT     15

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_MASK      0x4000
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_ALIGN     0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_BITS      1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_SHIFT     14

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13)
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_MASK       0x2000
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_ALIGN      0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_BITS       1
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_SHIFT      13

/* BRPHY0_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: reserved0 [12:00] */
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_MASK           0x1fff
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_ALIGN          0
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_BITS           13
#define BRPHY0_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_SHIFT          0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_DEV_PKG_ID_LSB
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_DEV_PKG_ID_LSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) WriteReg16(BRPHY0_CL45DEV7_AN_DEV_PKG_ID_LSB,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) ReadReg16(BRPHY0_CL45DEV7_AN_DEV_PKG_ID_LSB)
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_DEV_PKG_ID_MSB
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_DEV_PKG_ID_MSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY0_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) WriteReg16(BRPHY0_CL45DEV7_AN_DEV_PKG_ID_MSB,x)
#define Rd_BRPHY0_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) ReadReg16(BRPHY0_CL45DEV7_AN_DEV_PKG_ID_MSB)
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY0_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_AD
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_AD :: Next_page [15:15] */
#define Wr_BRPHY0_CL45DEV7_AN_AD_Next_page(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_AD,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV7_AN_AD_Next_page(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_AD,0x8000,15)
#define BRPHY0_CL45DEV7_AN_AD_NEXT_PAGE_MASK                       0x8000
#define BRPHY0_CL45DEV7_AN_AD_NEXT_PAGE_ALIGN                      0
#define BRPHY0_CL45DEV7_AN_AD_NEXT_PAGE_BITS                       1
#define BRPHY0_CL45DEV7_AN_AD_NEXT_PAGE_SHIFT                      15

/* BRPHY0_CL45DEV7 :: AN_AD :: Acknowledge [14:14] */
#define Wr_BRPHY0_CL45DEV7_AN_AD_Acknowledge(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_AD,0x4000,14,x)
#define Rd_BRPHY0_CL45DEV7_AN_AD_Acknowledge(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_AD,0x4000,14)
#define BRPHY0_CL45DEV7_AN_AD_ACKNOWLEDGE_MASK                     0x4000
#define BRPHY0_CL45DEV7_AN_AD_ACKNOWLEDGE_ALIGN                    0
#define BRPHY0_CL45DEV7_AN_AD_ACKNOWLEDGE_BITS                     1
#define BRPHY0_CL45DEV7_AN_AD_ACKNOWLEDGE_SHIFT                    14

/* BRPHY0_CL45DEV7 :: AN_AD :: Remote_fault [13:13] */
#define Wr_BRPHY0_CL45DEV7_AN_AD_Remote_fault(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_AD,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV7_AN_AD_Remote_fault(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_AD,0x2000,13)
#define BRPHY0_CL45DEV7_AN_AD_REMOTE_FAULT_MASK                    0x2000
#define BRPHY0_CL45DEV7_AN_AD_REMOTE_FAULT_ALIGN                   0
#define BRPHY0_CL45DEV7_AN_AD_REMOTE_FAULT_BITS                    1
#define BRPHY0_CL45DEV7_AN_AD_REMOTE_FAULT_SHIFT                   13

/* BRPHY0_CL45DEV7 :: AN_AD :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY0_CL45DEV7_AN_AD_Extended_next_page_ability(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_AD,0x1000,12,x)
#define Rd_BRPHY0_CL45DEV7_AN_AD_Extended_next_page_ability(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_AD,0x1000,12)
#define BRPHY0_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_MASK      0x1000
#define BRPHY0_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_ALIGN     0
#define BRPHY0_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_BITS      1
#define BRPHY0_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_SHIFT     12

/* BRPHY0_CL45DEV7 :: AN_AD :: Tech_Field [11:05] */
#define Wr_BRPHY0_CL45DEV7_AN_AD_Tech_Field(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_AD,0xfe0,5,x)
#define Rd_BRPHY0_CL45DEV7_AN_AD_Tech_Field(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_AD,0xfe0,5)
#define BRPHY0_CL45DEV7_AN_AD_TECH_FIELD_MASK                      0x0fe0
#define BRPHY0_CL45DEV7_AN_AD_TECH_FIELD_ALIGN                     0
#define BRPHY0_CL45DEV7_AN_AD_TECH_FIELD_BITS                      7
#define BRPHY0_CL45DEV7_AN_AD_TECH_FIELD_SHIFT                     5

/* BRPHY0_CL45DEV7 :: AN_AD :: Selector_Field [04:00] */
#define Wr_BRPHY0_CL45DEV7_AN_AD_Selector_Field(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_AD,0x1f,0,x)
#define Rd_BRPHY0_CL45DEV7_AN_AD_Selector_Field(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_AD,0x1f,0)
#define BRPHY0_CL45DEV7_AN_AD_SELECTOR_FIELD_MASK                  0x001f
#define BRPHY0_CL45DEV7_AN_AD_SELECTOR_FIELD_ALIGN                 0
#define BRPHY0_CL45DEV7_AN_AD_SELECTOR_FIELD_BITS                  5
#define BRPHY0_CL45DEV7_AN_AD_SELECTOR_FIELD_SHIFT                 0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_LPA
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_LPA :: Next_page [15:15] */
#define Wr_BRPHY0_CL45DEV7_AN_LPA_Next_page(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV7_AN_LPA_Next_page(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x8000,15)
#define BRPHY0_CL45DEV7_AN_LPA_NEXT_PAGE_MASK                      0x8000
#define BRPHY0_CL45DEV7_AN_LPA_NEXT_PAGE_ALIGN                     0
#define BRPHY0_CL45DEV7_AN_LPA_NEXT_PAGE_BITS                      1
#define BRPHY0_CL45DEV7_AN_LPA_NEXT_PAGE_SHIFT                     15

/* BRPHY0_CL45DEV7 :: AN_LPA :: Acknowledge [14:14] */
#define Wr_BRPHY0_CL45DEV7_AN_LPA_Acknowledge(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x4000,14,x)
#define Rd_BRPHY0_CL45DEV7_AN_LPA_Acknowledge(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x4000,14)
#define BRPHY0_CL45DEV7_AN_LPA_ACKNOWLEDGE_MASK                    0x4000
#define BRPHY0_CL45DEV7_AN_LPA_ACKNOWLEDGE_ALIGN                   0
#define BRPHY0_CL45DEV7_AN_LPA_ACKNOWLEDGE_BITS                    1
#define BRPHY0_CL45DEV7_AN_LPA_ACKNOWLEDGE_SHIFT                   14

/* BRPHY0_CL45DEV7 :: AN_LPA :: Remote_fault [13:13] */
#define Wr_BRPHY0_CL45DEV7_AN_LPA_Remote_fault(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV7_AN_LPA_Remote_fault(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x2000,13)
#define BRPHY0_CL45DEV7_AN_LPA_REMOTE_FAULT_MASK                   0x2000
#define BRPHY0_CL45DEV7_AN_LPA_REMOTE_FAULT_ALIGN                  0
#define BRPHY0_CL45DEV7_AN_LPA_REMOTE_FAULT_BITS                   1
#define BRPHY0_CL45DEV7_AN_LPA_REMOTE_FAULT_SHIFT                  13

/* BRPHY0_CL45DEV7 :: AN_LPA :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY0_CL45DEV7_AN_LPA_Extended_next_page_ability(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x1000,12,x)
#define Rd_BRPHY0_CL45DEV7_AN_LPA_Extended_next_page_ability(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x1000,12)
#define BRPHY0_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_MASK     0x1000
#define BRPHY0_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_ALIGN    0
#define BRPHY0_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_BITS     1
#define BRPHY0_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_SHIFT    12

/* BRPHY0_CL45DEV7 :: AN_LPA :: Tech_Field [11:05] */
#define Wr_BRPHY0_CL45DEV7_AN_LPA_Tech_Field(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_LPA,0xfe0,5,x)
#define Rd_BRPHY0_CL45DEV7_AN_LPA_Tech_Field(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_LPA,0xfe0,5)
#define BRPHY0_CL45DEV7_AN_LPA_TECH_FIELD_MASK                     0x0fe0
#define BRPHY0_CL45DEV7_AN_LPA_TECH_FIELD_ALIGN                    0
#define BRPHY0_CL45DEV7_AN_LPA_TECH_FIELD_BITS                     7
#define BRPHY0_CL45DEV7_AN_LPA_TECH_FIELD_SHIFT                    5

/* BRPHY0_CL45DEV7 :: AN_LPA :: Selector_Field [04:00] */
#define Wr_BRPHY0_CL45DEV7_AN_LPA_Selector_Field(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x1f,0,x)
#define Rd_BRPHY0_CL45DEV7_AN_LPA_Selector_Field(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_LPA,0x1f,0)
#define BRPHY0_CL45DEV7_AN_LPA_SELECTOR_FIELD_MASK                 0x001f
#define BRPHY0_CL45DEV7_AN_LPA_SELECTOR_FIELD_ALIGN                0
#define BRPHY0_CL45DEV7_AN_LPA_SELECTOR_FIELD_BITS                 5
#define BRPHY0_CL45DEV7_AN_LPA_SELECTOR_FIELD_SHIFT                0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_XNPA
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_XNPA :: Next_page [15:15] */
#define Wr_BRPHY0_CL45DEV7_AN_XNPA_Next_page(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV7_AN_XNPA_Next_page(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x8000,15)
#define BRPHY0_CL45DEV7_AN_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY0_CL45DEV7_AN_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY0_CL45DEV7_AN_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY0_CL45DEV7_AN_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY0_CL45DEV7 :: AN_XNPA :: reserved0 [14:14] */
#define BRPHY0_CL45DEV7_AN_XNPA_RESERVED0_MASK                     0x4000
#define BRPHY0_CL45DEV7_AN_XNPA_RESERVED0_ALIGN                    0
#define BRPHY0_CL45DEV7_AN_XNPA_RESERVED0_BITS                     1
#define BRPHY0_CL45DEV7_AN_XNPA_RESERVED0_SHIFT                    14

/* BRPHY0_CL45DEV7 :: AN_XNPA :: Message_page [13:13] */
#define Wr_BRPHY0_CL45DEV7_AN_XNPA_Message_page(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV7_AN_XNPA_Message_page(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x2000,13)
#define BRPHY0_CL45DEV7_AN_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY0_CL45DEV7_AN_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY0_CL45DEV7_AN_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY0_CL45DEV7_AN_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY0_CL45DEV7 :: AN_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY0_CL45DEV7_AN_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x1000,12,x)
#define Rd_BRPHY0_CL45DEV7_AN_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x1000,12)
#define BRPHY0_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY0_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY0_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY0_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY0_CL45DEV7 :: AN_XNPA :: Toggle [11:11] */
#define Wr_BRPHY0_CL45DEV7_AN_XNPA_Toggle(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x800,11,x)
#define Rd_BRPHY0_CL45DEV7_AN_XNPA_Toggle(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x800,11)
#define BRPHY0_CL45DEV7_AN_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY0_CL45DEV7_AN_XNPA_TOGGLE_ALIGN                       0
#define BRPHY0_CL45DEV7_AN_XNPA_TOGGLE_BITS                        1
#define BRPHY0_CL45DEV7_AN_XNPA_TOGGLE_SHIFT                       11

/* BRPHY0_CL45DEV7 :: AN_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY0_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x7ff,0,x)
#define Rd_BRPHY0_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY0_CL45DEV7_AN_XNPA,0x7ff,0)
#define BRPHY0_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY0_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY0_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY0_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_XNPB
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY0_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY0_CL45DEV7_AN_XNPB,x)
#define Rd_BRPHY0_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY0_CL45DEV7_AN_XNPB)
#define BRPHY0_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY0_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY0_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY0_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: AN_XNPC
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: AN_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY0_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY0_CL45DEV7_AN_XNPC,x)
#define Rd_BRPHY0_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY0_CL45DEV7_AN_XNPC)
#define BRPHY0_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY0_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY0_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY0_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: LP_XNPA
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: LP_XNPA :: Next_page [15:15] */
#define Wr_BRPHY0_CL45DEV7_LP_XNPA_Next_page(x) WriteRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV7_LP_XNPA_Next_page(x) ReadRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x8000,15)
#define BRPHY0_CL45DEV7_LP_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY0_CL45DEV7_LP_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY0_CL45DEV7_LP_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY0_CL45DEV7_LP_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY0_CL45DEV7 :: LP_XNPA :: Acknowledge [14:14] */
#define Wr_BRPHY0_CL45DEV7_LP_XNPA_Acknowledge(x) WriteRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x4000,14,x)
#define Rd_BRPHY0_CL45DEV7_LP_XNPA_Acknowledge(x) ReadRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x4000,14)
#define BRPHY0_CL45DEV7_LP_XNPA_ACKNOWLEDGE_MASK                   0x4000
#define BRPHY0_CL45DEV7_LP_XNPA_ACKNOWLEDGE_ALIGN                  0
#define BRPHY0_CL45DEV7_LP_XNPA_ACKNOWLEDGE_BITS                   1
#define BRPHY0_CL45DEV7_LP_XNPA_ACKNOWLEDGE_SHIFT                  14

/* BRPHY0_CL45DEV7 :: LP_XNPA :: Message_page [13:13] */
#define Wr_BRPHY0_CL45DEV7_LP_XNPA_Message_page(x) WriteRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV7_LP_XNPA_Message_page(x) ReadRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x2000,13)
#define BRPHY0_CL45DEV7_LP_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY0_CL45DEV7_LP_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY0_CL45DEV7_LP_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY0_CL45DEV7_LP_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY0_CL45DEV7 :: LP_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY0_CL45DEV7_LP_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x1000,12,x)
#define Rd_BRPHY0_CL45DEV7_LP_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x1000,12)
#define BRPHY0_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY0_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY0_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY0_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY0_CL45DEV7 :: LP_XNPA :: Toggle [11:11] */
#define Wr_BRPHY0_CL45DEV7_LP_XNPA_Toggle(x) WriteRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x800,11,x)
#define Rd_BRPHY0_CL45DEV7_LP_XNPA_Toggle(x) ReadRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x800,11)
#define BRPHY0_CL45DEV7_LP_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY0_CL45DEV7_LP_XNPA_TOGGLE_ALIGN                       0
#define BRPHY0_CL45DEV7_LP_XNPA_TOGGLE_BITS                        1
#define BRPHY0_CL45DEV7_LP_XNPA_TOGGLE_SHIFT                       11

/* BRPHY0_CL45DEV7 :: LP_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY0_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x7ff,0,x)
#define Rd_BRPHY0_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY0_CL45DEV7_LP_XNPA,0x7ff,0)
#define BRPHY0_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY0_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY0_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY0_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: LP_XNPB
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: LP_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY0_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY0_CL45DEV7_LP_XNPB,x)
#define Rd_BRPHY0_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY0_CL45DEV7_LP_XNPB)
#define BRPHY0_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY0_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY0_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY0_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: LP_XNPC
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: LP_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY0_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY0_CL45DEV7_LP_XNPC,x)
#define Rd_BRPHY0_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY0_CL45DEV7_LP_XNPC)
#define BRPHY0_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY0_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY0_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY0_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: TENG_AN_CTRL
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_MAN_CONFIG_EN [15:15] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x8000,15)
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_MASK   0x8000
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_ALIGN  0
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_BITS   1
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_SHIFT  15

/* BRPHY0_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_CONFIG_VAL [14:14] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x4000,14,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x4000,14)
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_MASK      0x4000
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_ALIGN     0
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_BITS      1
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_SHIFT     14

/* BRPHY0_CL45DEV7 :: TENG_AN_CTRL :: PORT_TYPE [13:13] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x2000,13)
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_MASK                0x2000
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_ALIGN               0
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_BITS                1
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_SHIFT               13

/* BRPHY0_CL45DEV7 :: TENG_AN_CTRL :: PHY10GBASET_ABLE [12:12] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x1000,12)
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_MASK         0x1000
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_ALIGN        0
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_BITS         1
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_SHIFT        12

/* BRPHY0_CL45DEV7 :: TENG_AN_CTRL :: reserved0 [11:03] */
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_RESERVED0_MASK                0x0ff8
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_RESERVED0_ALIGN               0
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_RESERVED0_BITS                9
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_RESERVED0_SHIFT               3

/* BRPHY0_CL45DEV7 :: TENG_AN_CTRL :: LD_PMA_TRAIN_RST_SEQ [02:02] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x4,2,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x4,2)
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_MASK     0x0004
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_ALIGN    0
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_BITS     1
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_SHIFT    2

/* BRPHY0_CL45DEV7 :: TENG_AN_CTRL :: reserved1 [01:01] */
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_RESERVED1_MASK                0x0002
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_RESERVED1_ALIGN               0
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_RESERVED1_BITS                1
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_RESERVED1_SHIFT               1

/* BRPHY0_CL45DEV7 :: TENG_AN_CTRL :: LD_LOOP_TIMING_ABLE [00:00] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x1,0,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_CTRL,0x1,0)
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_MASK      0x0001
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_BITS      1
#define BRPHY0_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_SHIFT     0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: TENG_AN_STAT
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_FAULT [15:15] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x8000,15,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x8000,15)
#define BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_MASK    0x8000
#define BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_ALIGN   0
#define BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_BITS    1
#define BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_SHIFT   15

/* BRPHY0_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_RES [14:14] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x4000,14,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x4000,14)
#define BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_MASK      0x4000
#define BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_ALIGN     0
#define BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_BITS      1
#define BRPHY0_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_SHIFT     14

/* BRPHY0_CL45DEV7 :: TENG_AN_STAT :: LOCAL_RCVR_STAT [13:13] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x2000,13,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x2000,13)
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_MASK          0x2000
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_ALIGN         0
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_BITS          1
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_SHIFT         13

/* BRPHY0_CL45DEV7 :: TENG_AN_STAT :: REMOTE_RCVR_STAT [12:12] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x1000,12,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x1000,12)
#define BRPHY0_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_MASK         0x1000
#define BRPHY0_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_ALIGN        0
#define BRPHY0_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_BITS         1
#define BRPHY0_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_SHIFT        12

/* BRPHY0_CL45DEV7 :: TENG_AN_STAT :: LNK_PRTNR_10GBASET_CAP [11:11] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x800,11,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x800,11)
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_MASK   0x0800
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_ALIGN  0
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_BITS   1
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_SHIFT  11

/* BRPHY0_CL45DEV7 :: TENG_AN_STAT :: LP_LOOP_TIMING_ABLE [10:10] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x400,10,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x400,10)
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_MASK      0x0400
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_BITS      1
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_SHIFT     10

/* BRPHY0_CL45DEV7 :: TENG_AN_STAT :: LP_PMA_TRAIN_RST_REQ [09:09] */
#define Wr_BRPHY0_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) WriteRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x200,9,x)
#define Rd_BRPHY0_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) ReadRegBits16(BRPHY0_CL45DEV7_TENG_AN_STAT,0x200,9)
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_MASK     0x0200
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_ALIGN    0
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_BITS     1
#define BRPHY0_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_SHIFT    9

/* BRPHY0_CL45DEV7 :: TENG_AN_STAT :: reserved0 [08:00] */
#define BRPHY0_CL45DEV7_TENG_AN_STAT_RESERVED0_MASK                0x01ff
#define BRPHY0_CL45DEV7_TENG_AN_STAT_RESERVED0_ALIGN               0
#define BRPHY0_CL45DEV7_TENG_AN_STAT_RESERVED0_BITS                9
#define BRPHY0_CL45DEV7_TENG_AN_STAT_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: EEE_ADV
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: EEE_ADV :: reserved0 [15:11] */
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED0_MASK                     0xf800
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED0_ALIGN                    0
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED0_BITS                     5
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED0_SHIFT                    11

/* BRPHY0_CL45DEV7 :: EEE_ADV :: Next_page [10:10] */
#define Wr_BRPHY0_CL45DEV7_EEE_ADV_Next_page(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x400,10,x)
#define Rd_BRPHY0_CL45DEV7_EEE_ADV_Next_page(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x400,10)
#define BRPHY0_CL45DEV7_EEE_ADV_NEXT_PAGE_MASK                     0x0400
#define BRPHY0_CL45DEV7_EEE_ADV_NEXT_PAGE_ALIGN                    0
#define BRPHY0_CL45DEV7_EEE_ADV_NEXT_PAGE_BITS                     1
#define BRPHY0_CL45DEV7_EEE_ADV_NEXT_PAGE_SHIFT                    10

/* BRPHY0_CL45DEV7 :: EEE_ADV :: reserved1 [09:07] */
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED1_MASK                     0x0380
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED1_ALIGN                    0
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED1_BITS                     3
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED1_SHIFT                    7

/* BRPHY0_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KR_EEE [06:06] */
#define Wr_BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x40,6,x)
#define Rd_BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x40,6)
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_MASK            0x0040
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_ALIGN           0
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_BITS            1
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_SHIFT           6

/* BRPHY0_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KX4_EEE [05:05] */
#define Wr_BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x20,5,x)
#define Rd_BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x20,5)
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_MASK           0x0020
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_ALIGN          0
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_BITS           1
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_SHIFT          5

/* BRPHY0_CL45DEV7 :: EEE_ADV :: reserved2 [04:04] */
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED2_MASK                     0x0010
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED2_ALIGN                    0
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED2_BITS                     1
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED2_SHIFT                    4

/* BRPHY0_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_T_EEE [03:03] */
#define Wr_BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x8,3,x)
#define Rd_BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x8,3)
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_MASK             0x0008
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_ALIGN            0
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_BITS             1
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_SHIFT            3

/* BRPHY0_CL45DEV7 :: EEE_ADV :: PHY_1000BASE_T_EEE [02:02] */
#define Wr_BRPHY0_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x4,2,x)
#define Rd_BRPHY0_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x4,2)
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_MASK            0x0004
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_ALIGN           0
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_BITS            1
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_SHIFT           2

/* BRPHY0_CL45DEV7 :: EEE_ADV :: PHY_100BASE_T_EEE [01:01] */
#define Wr_BRPHY0_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x2,1,x)
#define Rd_BRPHY0_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_ADV,0x2,1)
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_MASK             0x0002
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_ALIGN            0
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_BITS             1
#define BRPHY0_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_SHIFT            1

/* BRPHY0_CL45DEV7 :: EEE_ADV :: reserved3 [00:00] */
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED3_MASK                     0x0001
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED3_ALIGN                    0
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED3_BITS                     1
#define BRPHY0_CL45DEV7_EEE_ADV_RESERVED3_SHIFT                    0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: EEE_LP_ADV
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: EEE_LP_ADV :: status [15:00] */
#define Wr_BRPHY0_CL45DEV7_EEE_LP_ADV_status(x) WriteReg16(BRPHY0_CL45DEV7_EEE_LP_ADV,x)
#define Rd_BRPHY0_CL45DEV7_EEE_LP_ADV_status(x) ReadReg16(BRPHY0_CL45DEV7_EEE_LP_ADV)
#define BRPHY0_CL45DEV7_EEE_LP_ADV_STATUS_MASK                     0xffff
#define BRPHY0_CL45DEV7_EEE_LP_ADV_STATUS_ALIGN                    0
#define BRPHY0_CL45DEV7_EEE_LP_ADV_STATUS_BITS                     16
#define BRPHY0_CL45DEV7_EEE_LP_ADV_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY0_CL45DEV7 :: EEE_MODE_CTL
 ***************************************************************************/
/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: reserved0 [15:11] */
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED0_MASK                0xf800
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED0_ALIGN               0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED0_BITS                5
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED0_SHIFT               11

/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: Next_page [10:10] */
#define Wr_BRPHY0_CL45DEV7_EEE_MODE_CTL_Next_page(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x400,10,x)
#define Rd_BRPHY0_CL45DEV7_EEE_MODE_CTL_Next_page(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x400,10)
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_MASK                0x0400
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_ALIGN               0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_BITS                1
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_SHIFT               10

/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: reserved1 [09:07] */
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED1_MASK                0x0380
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED1_ALIGN               0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED1_BITS                3
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED1_SHIFT               7

/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KR_reduced_energy [06:06] */
#define Wr_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x40,6,x)
#define Rd_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x40,6)
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_MASK 0x0040
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_ALIGN 0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_BITS 1
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_SHIFT 6

/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KX4_reduced_energy [05:05] */
#define Wr_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x20,5,x)
#define Rd_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x20,5)
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_MASK 0x0020
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_ALIGN 0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_BITS 1
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_SHIFT 5

/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: reserved2 [04:04] */
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED2_MASK                0x0010
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED2_ALIGN               0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED2_BITS                1
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED2_SHIFT               4

/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_T_reduced_energy [03:03] */
#define Wr_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x8,3,x)
#define Rd_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x8,3)
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_MASK 0x0008
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_SHIFT 3

/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: PHY_1000BASE_T_reduced_energy [02:02] */
#define Wr_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x4,2,x)
#define Rd_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x4,2)
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_MASK 0x0004
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_SHIFT 2

/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: PHY_100BASE_T_reduced_energy [01:01] */
#define Wr_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) WriteRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x2,1,x)
#define Rd_BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) ReadRegBits16(BRPHY0_CL45DEV7_EEE_MODE_CTL,0x2,1)
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_MASK 0x0002
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_SHIFT 1

/* BRPHY0_CL45DEV7 :: EEE_MODE_CTL :: reserved3 [00:00] */
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED3_MASK                0x0001
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED3_ALIGN               0
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED3_BITS                1
#define BRPHY0_CL45DEV7_EEE_MODE_CTL_RESERVED3_SHIFT               0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_CL45VEN
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_CL45VEN :: FORCE_LINK
 ***************************************************************************/
/* BRPHY0_CL45VEN :: FORCE_LINK :: FORCE_LINK_MODE [15:15] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x8000,15,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x8000,15)
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_MASK             0x8000
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_ALIGN            0
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_BITS             1
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_SHIFT            15

/* BRPHY0_CL45VEN :: FORCE_LINK :: CHNG_10GBASET_AN_CTRL_BEHAV [14:14] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x4000,14,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x4000,14)
#define BRPHY0_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_MASK 0x4000
#define BRPHY0_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_ALIGN 0
#define BRPHY0_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_BITS 1
#define BRPHY0_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_SHIFT 14

/* BRPHY0_CL45VEN :: FORCE_LINK :: CHNG_BIT13_MCTRL_RD_BEHAV [13:13] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x2000,13,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x2000,13)
#define BRPHY0_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_MASK   0x2000
#define BRPHY0_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_ALIGN  0
#define BRPHY0_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_BITS   1
#define BRPHY0_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_SHIFT  13

/* BRPHY0_CL45VEN :: FORCE_LINK :: AN_FLP_BTB_TMR_MODE [12:12] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x1000,12,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x1000,12)
#define BRPHY0_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_MASK         0x1000
#define BRPHY0_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_ALIGN        0
#define BRPHY0_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_BITS         1
#define BRPHY0_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_SHIFT        12

/* BRPHY0_CL45VEN :: FORCE_LINK :: SWP_UFORMATED_CODE_FLDS [11:11] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x800,11,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x800,11)
#define BRPHY0_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_MASK     0x0800
#define BRPHY0_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_ALIGN    0
#define BRPHY0_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_BITS     1
#define BRPHY0_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_SHIFT    11

/* BRPHY0_CL45VEN :: FORCE_LINK :: BRK_LNK_TMR_MODE [10:10] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x400,10,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x400,10)
#define BRPHY0_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_MASK            0x0400
#define BRPHY0_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_ALIGN           0
#define BRPHY0_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_BITS            1
#define BRPHY0_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_SHIFT           10

/* BRPHY0_CL45VEN :: FORCE_LINK :: PREAMBLE_IGNORE [09:09] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x200,9,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x200,9)
#define BRPHY0_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_MASK             0x0200
#define BRPHY0_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_ALIGN            0
#define BRPHY0_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_BITS             1
#define BRPHY0_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_SHIFT            9

/* BRPHY0_CL45VEN :: FORCE_LINK :: FORCE_LNK_10GBASET_FDX [08:08] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x100,8,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x100,8)
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_MASK      0x0100
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_ALIGN     0
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_BITS      1
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_SHIFT     8

/* BRPHY0_CL45VEN :: FORCE_LINK :: FORCE_LNK_1000BASET_FDX_HDX [07:07] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x80,7,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x80,7)
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_MASK 0x0080
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_ALIGN 0
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_BITS 1
#define BRPHY0_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_SHIFT 7

/* BRPHY0_CL45VEN :: FORCE_LINK :: IGNORE_ACK2 [06:06] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x40,6,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x40,6)
#define BRPHY0_CL45VEN_FORCE_LINK_IGNORE_ACK2_MASK                 0x0040
#define BRPHY0_CL45VEN_FORCE_LINK_IGNORE_ACK2_ALIGN                0
#define BRPHY0_CL45VEN_FORCE_LINK_IGNORE_ACK2_BITS                 1
#define BRPHY0_CL45VEN_FORCE_LINK_IGNORE_ACK2_SHIFT                6

/* BRPHY0_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_OK [05:05] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x20,5,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x20,5)
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_MASK       0x0020
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_ALIGN      0
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_BITS       1
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_SHIFT      5

/* BRPHY0_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_RDY [04:04] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x10,4,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x10,4)
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_MASK      0x0010
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_ALIGN     0
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_BITS      1
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_SHIFT     4

/* BRPHY0_CL45VEN :: FORCE_LINK :: DIS_REG7P0_BIT13_AUTO_UPDATE [03:03] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x8,3,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x8,3)
#define BRPHY0_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_MASK 0x0008
#define BRPHY0_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_ALIGN 0
#define BRPHY0_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_BITS 1
#define BRPHY0_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_SHIFT 3

/* BRPHY0_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_OK [02:02] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x4,2,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x4,2)
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_MASK        0x0004
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_ALIGN       0
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_BITS        1
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_SHIFT       2

/* BRPHY0_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_RDY [01:01] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x2,1,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x2,1)
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_MASK       0x0002
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_ALIGN      0
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_BITS       1
#define BRPHY0_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_SHIFT      1

/* BRPHY0_CL45VEN :: FORCE_LINK :: LAST_PG_TO_EN [00:00] */
#define Wr_BRPHY0_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) WriteRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x1,0,x)
#define Rd_BRPHY0_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) ReadRegBits16(BRPHY0_CL45VEN_FORCE_LINK,0x1,0)
#define BRPHY0_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_MASK               0x0001
#define BRPHY0_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_ALIGN              0
#define BRPHY0_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_BITS               1
#define BRPHY0_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_SHIFT              0


/****************************************************************************
 * BRPHY0_CL45VEN :: SELECTIVE_RESET
 ***************************************************************************/
/* BRPHY0_CL45VEN :: SELECTIVE_RESET :: DSP_RESET [15:15] */
#define Wr_BRPHY0_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) WriteRegBits16(BRPHY0_CL45VEN_SELECTIVE_RESET,0x8000,15,x)
#define Rd_BRPHY0_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) ReadRegBits16(BRPHY0_CL45VEN_SELECTIVE_RESET,0x8000,15)
#define BRPHY0_CL45VEN_SELECTIVE_RESET_DSP_RESET_MASK              0x8000
#define BRPHY0_CL45VEN_SELECTIVE_RESET_DSP_RESET_ALIGN             0
#define BRPHY0_CL45VEN_SELECTIVE_RESET_DSP_RESET_BITS              1
#define BRPHY0_CL45VEN_SELECTIVE_RESET_DSP_RESET_SHIFT             15

/* BRPHY0_CL45VEN :: SELECTIVE_RESET :: SM_DSP_RESET [14:14] */
#define Wr_BRPHY0_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) WriteRegBits16(BRPHY0_CL45VEN_SELECTIVE_RESET,0x4000,14,x)
#define Rd_BRPHY0_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) ReadRegBits16(BRPHY0_CL45VEN_SELECTIVE_RESET,0x4000,14)
#define BRPHY0_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_MASK           0x4000
#define BRPHY0_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_ALIGN          0
#define BRPHY0_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_BITS           1
#define BRPHY0_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_SHIFT          14

/* BRPHY0_CL45VEN :: SELECTIVE_RESET :: reserved0 [13:08] */
#define BRPHY0_CL45VEN_SELECTIVE_RESET_RESERVED0_MASK              0x3f00
#define BRPHY0_CL45VEN_SELECTIVE_RESET_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_SELECTIVE_RESET_RESERVED0_BITS              6
#define BRPHY0_CL45VEN_SELECTIVE_RESET_RESERVED0_SHIFT             8

/* BRPHY0_CL45VEN :: SELECTIVE_RESET :: DIG100_RESET [07:07] */
#define Wr_BRPHY0_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) WriteRegBits16(BRPHY0_CL45VEN_SELECTIVE_RESET,0x80,7,x)
#define Rd_BRPHY0_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) ReadRegBits16(BRPHY0_CL45VEN_SELECTIVE_RESET,0x80,7)
#define BRPHY0_CL45VEN_SELECTIVE_RESET_DIG100_RESET_MASK           0x0080
#define BRPHY0_CL45VEN_SELECTIVE_RESET_DIG100_RESET_ALIGN          0
#define BRPHY0_CL45VEN_SELECTIVE_RESET_DIG100_RESET_BITS           1
#define BRPHY0_CL45VEN_SELECTIVE_RESET_DIG100_RESET_SHIFT          7

/* BRPHY0_CL45VEN :: SELECTIVE_RESET :: reserved1 [06:00] */
#define BRPHY0_CL45VEN_SELECTIVE_RESET_RESERVED1_MASK              0x007f
#define BRPHY0_CL45VEN_SELECTIVE_RESET_RESERVED1_ALIGN             0
#define BRPHY0_CL45VEN_SELECTIVE_RESET_RESERVED1_BITS              7
#define BRPHY0_CL45VEN_SELECTIVE_RESET_RESERVED1_SHIFT             0


/****************************************************************************
 * BRPHY0_CL45VEN :: TEST_FSM_EXT_NXT_PGS
 ***************************************************************************/
/* BRPHY0_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved0 [15:15] */
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_MASK         0x8000
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_ALIGN        0
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_BITS         1
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_SHIFT        15

/* BRPHY0_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_XMTR_STATE [14:12] */
#define Wr_BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) WriteRegBits16(BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12,x)
#define Rd_BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) ReadRegBits16(BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12)
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_MASK    0x7000
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_ALIGN   0
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_BITS    3
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_SHIFT   12

/* BRPHY0_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved1 [11:11] */
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_MASK         0x0800
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_ALIGN        0
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_BITS         1
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_SHIFT        11

/* BRPHY0_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_RCVR_STATE [10:08] */
#define Wr_BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) WriteRegBits16(BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8,x)
#define Rd_BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) ReadRegBits16(BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8)
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_MASK    0x0700
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_ALIGN   0
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_BITS    3
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_SHIFT   8

/* BRPHY0_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: ARB_STATE [07:04] */
#define Wr_BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) WriteRegBits16(BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4,x)
#define Rd_BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) ReadRegBits16(BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4)
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_MASK         0x00f0
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_ALIGN        0
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_BITS         4
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_SHIFT        4

/* BRPHY0_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: HCD_STATE [03:00] */
#define Wr_BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) WriteRegBits16(BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0,x)
#define Rd_BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) ReadRegBits16(BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0)
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_MASK         0x000f
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_ALIGN        0
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_BITS         4
#define BRPHY0_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_SHIFT        0


/****************************************************************************
 * BRPHY0_CL45VEN :: TEST_FSM_NXT_PGS
 ***************************************************************************/
/* BRPHY0_CL45VEN :: TEST_FSM_NXT_PGS :: reserved0 [15:10] */
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_MASK             0xfc00
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_ALIGN            0
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_BITS             6
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_SHIFT            10

/* BRPHY0_CL45VEN :: TEST_FSM_NXT_PGS :: NP_XMTR_STATE [09:05] */
#define Wr_BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) WriteRegBits16(BRPHY0_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5,x)
#define Rd_BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) ReadRegBits16(BRPHY0_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5)
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_MASK         0x03e0
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_ALIGN        0
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_BITS         5
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_SHIFT        5

/* BRPHY0_CL45VEN :: TEST_FSM_NXT_PGS :: reserved1 [04:04] */
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_MASK             0x0010
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_ALIGN            0
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_BITS             1
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_SHIFT            4

/* BRPHY0_CL45VEN :: TEST_FSM_NXT_PGS :: NP_RCVR_STATE [03:00] */
#define Wr_BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) WriteRegBits16(BRPHY0_CL45VEN_TEST_FSM_NXT_PGS,0xf,0,x)
#define Rd_BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) ReadRegBits16(BRPHY0_CL45VEN_TEST_FSM_NXT_PGS,0xf,0)
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_MASK         0x000f
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_ALIGN        0
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_BITS         4
#define BRPHY0_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_SHIFT        0


/****************************************************************************
 * BRPHY0_CL45VEN :: AN_MAN_TEST
 ***************************************************************************/
/* BRPHY0_CL45VEN :: AN_MAN_TEST :: reserved0 [15:12] */
#define BRPHY0_CL45VEN_AN_MAN_TEST_RESERVED0_MASK                  0xf000
#define BRPHY0_CL45VEN_AN_MAN_TEST_RESERVED0_ALIGN                 0
#define BRPHY0_CL45VEN_AN_MAN_TEST_RESERVED0_BITS                  4
#define BRPHY0_CL45VEN_AN_MAN_TEST_RESERVED0_SHIFT                 12

/* BRPHY0_CL45VEN :: AN_MAN_TEST :: LP_PG_TO_CAPTURE [11:08] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_TEST,0xf00,8,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_TEST,0xf00,8)
#define BRPHY0_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_MASK           0x0f00
#define BRPHY0_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_ALIGN          0
#define BRPHY0_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_BITS           4
#define BRPHY0_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_SHIFT          8

/* BRPHY0_CL45VEN :: AN_MAN_TEST :: reserved1 [07:03] */
#define BRPHY0_CL45VEN_AN_MAN_TEST_RESERVED1_MASK                  0x00f8
#define BRPHY0_CL45VEN_AN_MAN_TEST_RESERVED1_ALIGN                 0
#define BRPHY0_CL45VEN_AN_MAN_TEST_RESERVED1_BITS                  5
#define BRPHY0_CL45VEN_AN_MAN_TEST_RESERVED1_SHIFT                 3

/* BRPHY0_CL45VEN :: AN_MAN_TEST :: LNK_PARTNR_NXT_PG_TEST_MODE [02:02] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_TEST,0x4,2,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_TEST,0x4,2)
#define BRPHY0_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_MASK 0x0004
#define BRPHY0_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_SHIFT 2

/* BRPHY0_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN_SEED [01:01] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_TEST,0x2,1,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_TEST,0x2,1)
#define BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_MASK           0x0002
#define BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_ALIGN          0
#define BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_BITS           1
#define BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_SHIFT          1

/* BRPHY0_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN [00:00] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_TEST,0x1,0,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_TEST,0x1,0)
#define BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_MASK                0x0001
#define BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_ALIGN               0
#define BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_BITS                1
#define BRPHY0_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SHIFT               0


/****************************************************************************
 * BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A
 ***************************************************************************/
/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_HDX [15:15] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_MASK 0x8000
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_SHIFT 15

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_FDX [14:14] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_MASK 0x4000
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_SHIFT 14

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_PORT_TYPE [13:13] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_MASK 0x2000
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_SHIFT 13

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_CONFIG_VALUE [12:12] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_MASK 0x1000
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_SHIFT 12

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_MANUAL_CONFIG_EN [11:11] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_MASK 0x0800
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_SHIFT 11

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_SEED [10:00] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_MASK    0x07ff
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_ALIGN   0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_BITS    11
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_SHIFT   0


/****************************************************************************
 * BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B
 ***************************************************************************/
/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved0 [15:05] */
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_MASK      0xffe0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_ALIGN     0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_BITS      11
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_SHIFT     5

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PMA_TRAINING_RESET_REQ [04:04] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_MASK 0x0010
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_SHIFT 4

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved1 [03:03] */
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_MASK      0x0008
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_ALIGN     0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_BITS      1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_SHIFT     3

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PHY_SHORT_REACH_MODE [02:02] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_MASK 0x0004
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_SHIFT 2

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_LOOP_TIMING_ABILITY [01:01] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_MASK 0x0002
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_SHIFT 1

/* BRPHY0_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_10GBASET_CAPABILITY [00:00] */
#define Wr_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) WriteRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0,x)
#define Rd_BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) ReadRegBits16(BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0)
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_MASK 0x0001
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_ALIGN 0
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_BITS 1
#define BRPHY0_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_A
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_A :: LP_NP_A [15:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) WriteReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_A,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) ReadReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_A)
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_MASK            0xffff
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_ALIGN           0
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_BITS            16
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_SHIFT           0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_B
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_B :: LP_NP_B [15:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) WriteReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_B,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) ReadReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_B)
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_MASK            0xffff
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_ALIGN           0
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_BITS            16
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_SHIFT           0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_C
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_C :: LP_NP_C [15:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) WriteReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_C,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) ReadReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_C)
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_MASK            0xffff
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_ALIGN           0
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_BITS            16
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_SHIFT           0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_D
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_D :: LP_NP_D [15:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) WriteReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_D,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) ReadReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_D)
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_MASK            0xffff
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_ALIGN           0
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_BITS            16
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_SHIFT           0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_E
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_E :: LP_NP_E [15:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) WriteReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_E,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) ReadReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_E)
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_MASK            0xffff
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_ALIGN           0
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_BITS            16
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_SHIFT           0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_F
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_NXT_PG_F :: LP_NP_F [15:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) WriteReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_F,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) ReadReg16(BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_F)
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_MASK            0xffff
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_ALIGN           0
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_BITS            16
#define BRPHY0_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_SHIFT           0


/****************************************************************************
 * BRPHY0_CL45VEN :: EPON_CTRL_REG
 ***************************************************************************/
/* BRPHY0_CL45VEN :: EPON_CTRL_REG :: reserved0 [15:10] */
#define BRPHY0_CL45VEN_EPON_CTRL_REG_RESERVED0_MASK                0xfc00
#define BRPHY0_CL45VEN_EPON_CTRL_REG_RESERVED0_ALIGN               0
#define BRPHY0_CL45VEN_EPON_CTRL_REG_RESERVED0_BITS                6
#define BRPHY0_CL45VEN_EPON_CTRL_REG_RESERVED0_SHIFT               10

/* BRPHY0_CL45VEN :: EPON_CTRL_REG :: EPON_MODE [09:09] */
#define Wr_BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) WriteRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x200,9,x)
#define Rd_BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) ReadRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x200,9)
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_MASK                0x0200
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_ALIGN               0
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_BITS                1
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_SHIFT               9

/* BRPHY0_CL45VEN :: EPON_CTRL_REG :: EOC_PACKET_NORM [08:08] */
#define Wr_BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) WriteRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x100,8,x)
#define Rd_BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) ReadRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x100,8)
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_MASK          0x0100
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_ALIGN         0
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_BITS          1
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_SHIFT         8

/* BRPHY0_CL45VEN :: EPON_CTRL_REG :: EPON_MODE_CRCCHECK [07:07] */
#define Wr_BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) WriteRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x80,7,x)
#define Rd_BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) ReadRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x80,7)
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_MASK       0x0080
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_ALIGN      0
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_BITS       1
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_SHIFT      7

/* BRPHY0_CL45VEN :: EPON_CTRL_REG :: TX_EN_EXTEND [06:06] */
#define Wr_BRPHY0_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) WriteRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x40,6,x)
#define Rd_BRPHY0_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) ReadRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x40,6)
#define BRPHY0_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_MASK             0x0040
#define BRPHY0_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_ALIGN            0
#define BRPHY0_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_BITS             1
#define BRPHY0_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_SHIFT            6

/* BRPHY0_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POLARITY [05:05] */
#define Wr_BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) WriteRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x20,5,x)
#define Rd_BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) ReadRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x20,5)
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_MASK        0x0020
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_ALIGN       0
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_BITS        1
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_SHIFT       5

/* BRPHY0_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POL_CORR [04:04] */
#define Wr_BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) WriteRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x10,4,x)
#define Rd_BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) ReadRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0x10,4)
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_MASK        0x0010
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_ALIGN       0
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_BITS        1
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_SHIFT       4

/* BRPHY0_CL45VEN :: EPON_CTRL_REG :: EOC_SPEED_DET_THLD [03:00] */
#define Wr_BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) WriteRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0xf,0,x)
#define Rd_BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) ReadRegBits16(BRPHY0_CL45VEN_EPON_CTRL_REG,0xf,0)
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_MASK       0x000f
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_ALIGN      0
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_BITS       4
#define BRPHY0_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_SHIFT      0


/****************************************************************************
 * BRPHY0_CL45VEN :: EEE_TEST_CTRL_A
 ***************************************************************************/
/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: reserved0 [15:12] */
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_MASK              0xf000
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_BITS              4
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_SHIFT             12

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_RX_EN [11:11] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x800,11,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x800,11)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_MASK        0x0800
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_ALIGN       0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_BITS        1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_SHIFT       11

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_TX_EN [10:10] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x400,10,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x400,10)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_MASK        0x0400
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_ALIGN       0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_BITS        1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_SHIFT       10

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_RX_EN [09:09] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x200,9,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x200,9)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_MASK           0x0200
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_ALIGN          0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_BITS           1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_SHIFT          9

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_TX_EN [08:08] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x100,8,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x100,8)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_MASK           0x0100
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_ALIGN          0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_BITS           1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_SHIFT          8

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: LPI_GPCS_TEST_BUS_EN [07:07] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x80,7,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x80,7)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_MASK   0x0080
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_ALIGN  0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_BITS   1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_SHIFT  7

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: MACSEC_PK_MODE [06:06] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x40,6,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x40,6)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_MASK         0x0040
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_ALIGN        0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_BITS         1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_SHIFT        6

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: MSG_11_VS_10 [05:05] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x20,5,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x20,5)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_MASK           0x0020
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_ALIGN          0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_BITS           1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_SHIFT          5

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE [04:04] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x10,4,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x10,4)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_MASK              0x0010
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_ALIGN             0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_BITS              1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFT             4

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE_SHIFTED [03:03] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x8,3,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x8,3)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_MASK      0x0008
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_ALIGN     0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_BITS      1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_SHIFT     3

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: reserved1 [02:02] */
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_MASK              0x0004
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_ALIGN             0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_BITS              1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_SHIFT             2

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LP_M10 [01:01] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x2,1,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x2,1)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_MASK        0x0002
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_ALIGN       0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_BITS        1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_SHIFT       1

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LD_M10 [00:00] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x1,0,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_A,0x1,0)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_MASK        0x0001
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_ALIGN       0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_BITS        1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_SHIFT       0


/****************************************************************************
 * BRPHY0_CL45VEN :: EEE_TEST_CTRL_B
 ***************************************************************************/
/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x8000,15,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x8000,15)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_MASK         0x8000
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_ALIGN        0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_BITS         1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_SHIFT        15

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x4000,14,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x4000,14)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_MASK 0x4000
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_ALIGN 0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_BITS 1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_SHIFT 14

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_LPI_QUALIFIERS [13:13] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x2000,13,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x2000,13)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_MASK 0x2000
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_ALIGN 0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_BITS 1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_SHIFT 13

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_REG_3_20 [12:12] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x1000,12,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x1000,12)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_MASK 0x1000
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_ALIGN 0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_BITS 1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_SHIFT 12

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_RES [11:11] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x800,11,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x800,11)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_MASK       0x0800
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_ALIGN      0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_BITS       1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_SHIFT      11

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_10BASE_T_RES [10:10] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x400,10,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x400,10)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_MASK 0x0400
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_ALIGN 0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_BITS 1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_SHIFT 10

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: DET_SEND_Z [09:09] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x200,9,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x200,9)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_MASK             0x0200
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_ALIGN            0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_BITS             1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_SHIFT            9

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: EN_DET_SEND_Z_OVERRIDE [08:08] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x100,8,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x100,8)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_MASK 0x0100
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_ALIGN 0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_BITS 1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_SHIFT 8

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: REM_UPD_DONE_TEST [07:07] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x80,7,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x80,7)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_MASK      0x0080
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_ALIGN     0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_BITS      1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_SHIFT     7

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: REM_LPI_REQ_TEST [06:06] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x40,6,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x40,6)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_MASK       0x0040
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_ALIGN      0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_BITS       1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_SHIFT      6

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: LOC_UPD_DONE_TEST [05:05] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x20,5,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x20,5)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_MASK      0x0020
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_ALIGN     0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_BITS      1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_SHIFT     5

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: LOC_LPI_REQ_TEST [04:04] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x10,4,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x10,4)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_MASK       0x0010
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_ALIGN      0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_BITS       1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_SHIFT      4

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_UPD_DONE_OVERRIDE [03:03] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x8,3,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x8,3)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_MASK 0x0008
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_SHIFT 3

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_LPI_REQ_OVERRIDE [02:02] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x4,2,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x4,2)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_MASK 0x0004
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_SHIFT 2

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_UPD_DONE_OVERRIDE [01:01] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x2,1,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x2,1)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_MASK 0x0002
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_SHIFT 1

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_LPI_REQ_OVERRIDE [00:00] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x1,0,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_B,0x1,0)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_MASK 0x0001
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: EEE_TEST_CTRL_C
 ***************************************************************************/
/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_RX_EN [15:15] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x8000,15,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x8000,15)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_MASK        0x8000
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_ALIGN       0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_BITS        1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_SHIFT       15

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_TX_EN [14:14] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x4000,14,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x4000,14)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_MASK        0x4000
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_ALIGN       0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_BITS        1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_SHIFT       14

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_RX_EN [13:13] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x2000,13,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x2000,13)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_MASK            0x2000
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_ALIGN           0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_BITS            1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_SHIFT           13

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_TX_EN [12:12] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x1000,12,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x1000,12)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_MASK            0x1000
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_ALIGN           0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_BITS            1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_SHIFT           12

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_RX_EN [11:11] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x800,11,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x800,11)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_MASK        0x0800
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_ALIGN       0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_BITS        1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_SHIFT       11

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_TX_EN [10:10] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x400,10,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x400,10)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_MASK        0x0400
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_ALIGN       0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_BITS        1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_SHIFT       10

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_RX_EN [09:09] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x200,9,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x200,9)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_MASK            0x0200
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_ALIGN           0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_BITS            1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_SHIFT           9

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_TX_EN [08:08] */
#define Wr_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x100,8,x)
#define Rd_BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_TEST_CTRL_C,0x100,8)
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_MASK            0x0100
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_ALIGN           0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_BITS            1
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_SHIFT           8

/* BRPHY0_CL45VEN :: EEE_TEST_CTRL_C :: reserved0 [07:00] */
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_MASK              0x00ff
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_BITS              8
#define BRPHY0_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_SHIFT             0


/****************************************************************************
 * BRPHY0_CL45VEN :: EEE_SPARE_1
 ***************************************************************************/
/* BRPHY0_CL45VEN :: EEE_SPARE_1 :: SPARE [15:00] */
#define Wr_BRPHY0_CL45VEN_EEE_SPARE_1_SPARE(x) WriteReg16(BRPHY0_CL45VEN_EEE_SPARE_1,x)
#define Rd_BRPHY0_CL45VEN_EEE_SPARE_1_SPARE(x) ReadReg16(BRPHY0_CL45VEN_EEE_SPARE_1)
#define BRPHY0_CL45VEN_EEE_SPARE_1_SPARE_MASK                      0xffff
#define BRPHY0_CL45VEN_EEE_SPARE_1_SPARE_ALIGN                     0
#define BRPHY0_CL45VEN_EEE_SPARE_1_SPARE_BITS                      16
#define BRPHY0_CL45VEN_EEE_SPARE_1_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY0_CL45VEN :: EEE_SPARE_2
 ***************************************************************************/
/* BRPHY0_CL45VEN :: EEE_SPARE_2 :: SPARE [15:00] */
#define Wr_BRPHY0_CL45VEN_EEE_SPARE_2_SPARE(x) WriteReg16(BRPHY0_CL45VEN_EEE_SPARE_2,x)
#define Rd_BRPHY0_CL45VEN_EEE_SPARE_2_SPARE(x) ReadReg16(BRPHY0_CL45VEN_EEE_SPARE_2)
#define BRPHY0_CL45VEN_EEE_SPARE_2_SPARE_MASK                      0xffff
#define BRPHY0_CL45VEN_EEE_SPARE_2_SPARE_ALIGN                     0
#define BRPHY0_CL45VEN_EEE_SPARE_2_SPARE_BITS                      16
#define BRPHY0_CL45VEN_EEE_SPARE_2_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY0_CL45VEN :: EEE_CONTROL
 ***************************************************************************/
/* BRPHY0_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x8000,15,x)
#define Rd_BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x8000,15)
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_MASK             0x8000
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_ALIGN            0
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_BITS             1
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_SHIFT            15

/* BRPHY0_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x4000,14,x)
#define Rd_BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x4000,14)
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_MASK    0x4000
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_ALIGN   0
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_BITS    1
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_SHIFT   14

/* BRPHY0_CL45VEN :: EEE_CONTROL :: LPI_RES_IN_FORCE_MODE_EN [13:13] */
#define Wr_BRPHY0_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x2000,13,x)
#define Rd_BRPHY0_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x2000,13)
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_MASK   0x2000
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_ALIGN  0
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_BITS   1
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_SHIFT  13

/* BRPHY0_CL45VEN :: EEE_CONTROL :: SPARE [12:03] */
#define Wr_BRPHY0_CL45VEN_EEE_CONTROL_SPARE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x1ff8,3,x)
#define Rd_BRPHY0_CL45VEN_EEE_CONTROL_SPARE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x1ff8,3)
#define BRPHY0_CL45VEN_EEE_CONTROL_SPARE_MASK                      0x1ff8
#define BRPHY0_CL45VEN_EEE_CONTROL_SPARE_ALIGN                     0
#define BRPHY0_CL45VEN_EEE_CONTROL_SPARE_BITS                      10
#define BRPHY0_CL45VEN_EEE_CONTROL_SPARE_SHIFT                     3

/* BRPHY0_CL45VEN :: EEE_CONTROL :: LPI_LINKUP_DISABLE [02:02] */
#define Wr_BRPHY0_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x4,2,x)
#define Rd_BRPHY0_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x4,2)
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_MASK         0x0004
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_ALIGN        0
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_BITS         1
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_SHIFT        2

/* BRPHY0_CL45VEN :: EEE_CONTROL :: EEE_DOWNGRADE_ENABLE [01:01] */
#define Wr_BRPHY0_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x2,1,x)
#define Rd_BRPHY0_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x2,1)
#define BRPHY0_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_MASK       0x0002
#define BRPHY0_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_ALIGN      0
#define BRPHY0_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_BITS       1
#define BRPHY0_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_SHIFT      1

/* BRPHY0_CL45VEN :: EEE_CONTROL :: LPI_100TX_BRCM_LINK [00:00] */
#define Wr_BRPHY0_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x1,0,x)
#define Rd_BRPHY0_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_CONTROL,0x1,0)
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_MASK        0x0001
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_ALIGN       0
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_BITS        1
#define BRPHY0_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_SHIFT       0


/****************************************************************************
 * BRPHY0_CL45VEN :: EEE_RES_STAT
 ***************************************************************************/
/* BRPHY0_CL45VEN :: EEE_RES_STAT :: reserved0 [15:07] */
#define BRPHY0_CL45VEN_EEE_RES_STAT_RESERVED0_MASK                 0xff80
#define BRPHY0_CL45VEN_EEE_RES_STAT_RESERVED0_ALIGN                0
#define BRPHY0_CL45VEN_EEE_RES_STAT_RESERVED0_BITS                 9
#define BRPHY0_CL45VEN_EEE_RES_STAT_RESERVED0_SHIFT                7

/* BRPHY0_CL45VEN :: EEE_RES_STAT :: MASK_1000T_EEE [06:06] */
#define Wr_BRPHY0_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x40,6,x)
#define Rd_BRPHY0_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x40,6)
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_MASK            0x0040
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_ALIGN           0
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_BITS            1
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_SHIFT           6

/* BRPHY0_CL45VEN :: EEE_RES_STAT :: MASK_100TX_EEE [05:05] */
#define Wr_BRPHY0_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x20,5,x)
#define Rd_BRPHY0_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x20,5)
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_MASK            0x0020
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_ALIGN           0
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_BITS            1
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_SHIFT           5

/* BRPHY0_CL45VEN :: EEE_RES_STAT :: MASK_10T_EEE [04:04] */
#define Wr_BRPHY0_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x10,4,x)
#define Rd_BRPHY0_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x10,4)
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_MASK              0x0010
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_ALIGN             0
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_BITS              1
#define BRPHY0_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_SHIFT             4

/* BRPHY0_CL45VEN :: EEE_RES_STAT :: reserved1 [03:03] */
#define BRPHY0_CL45VEN_EEE_RES_STAT_RESERVED1_MASK                 0x0008
#define BRPHY0_CL45VEN_EEE_RES_STAT_RESERVED1_ALIGN                0
#define BRPHY0_CL45VEN_EEE_RES_STAT_RESERVED1_BITS                 1
#define BRPHY0_CL45VEN_EEE_RES_STAT_RESERVED1_SHIFT                3

/* BRPHY0_CL45VEN :: EEE_RES_STAT :: EEE_1000T_RES [02:02] */
#define Wr_BRPHY0_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x4,2,x)
#define Rd_BRPHY0_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x4,2)
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_MASK             0x0004
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_ALIGN            0
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_BITS             1
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_SHIFT            2

/* BRPHY0_CL45VEN :: EEE_RES_STAT :: EEE_100TX_RES [01:01] */
#define Wr_BRPHY0_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x2,1,x)
#define Rd_BRPHY0_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x2,1)
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_MASK             0x0002
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_ALIGN            0
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_BITS             1
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_SHIFT            1

/* BRPHY0_CL45VEN :: EEE_RES_STAT :: EEE_10BASE_TE_RES [00:00] */
#define Wr_BRPHY0_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) WriteRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x1,0,x)
#define Rd_BRPHY0_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) ReadRegBits16(BRPHY0_CL45VEN_EEE_RES_STAT,0x1,0)
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_MASK         0x0001
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_ALIGN        0
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_BITS         1
#define BRPHY0_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_SHIFT        0


/****************************************************************************
 * BRPHY0_CL45VEN :: LPI_MODE_CNTR
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LPI_MODE_CNTR :: LPI_MODE_COUNTER [15:00] */
#define Wr_BRPHY0_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) WriteReg16(BRPHY0_CL45VEN_LPI_MODE_CNTR,x)
#define Rd_BRPHY0_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) ReadReg16(BRPHY0_CL45VEN_LPI_MODE_CNTR)
#define BRPHY0_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_MASK         0xffff
#define BRPHY0_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_ALIGN        0
#define BRPHY0_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_BITS         16
#define BRPHY0_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_SHIFT        0


/****************************************************************************
 * BRPHY0_CL45VEN :: LOC_DEV_MSG_5_A
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LOC_DEV_MSG_5_A :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_MASK              0xf800
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_BITS              5
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_SHIFT             11

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_5_A :: BITS_10_0_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LOC_DEV_MSG_5_B
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LOC_DEV_MSG_5_B :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_MASK              0xf800
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_BITS              5
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_SHIFT             11

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_5_B :: BITS_21_11_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LOC_DEV_MSG_5_C
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LOC_DEV_MSG_5_C :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_MASK              0xf800
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_BITS              5
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_SHIFT             11

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_5_C :: BITS_32_22_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LOC_DEV_MSG_5_D
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LOC_DEV_MSG_5_D :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_MASK              0xf800
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_BITS              5
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_SHIFT             11

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_5_D :: BITS_43_33_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY0_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_A
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_A :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_MASK           0xf800
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_ALIGN          0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_BITS           5
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_SHIFT          11

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_A :: BITS_10_0_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_B
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_B :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_MASK           0xf800
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_ALIGN          0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_BITS           5
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_SHIFT          11

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_B :: BITS_21_11_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_C
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_C :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_MASK           0xf800
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_ALIGN          0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_BITS           5
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_SHIFT          11

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_C :: BITS_32_22_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_D
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_D :: MSG_5_OUI_MATCH [15:15] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_MASK     0x8000
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_ALIGN    0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_BITS     1
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_SHIFT    15

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_D :: reserved0 [14:11] */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_MASK           0x7800
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_ALIGN          0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_BITS           4
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_SHIFT          11

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_5_D :: BITS_43_33_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LOC_DEV_MSG_6_A
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_A :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_MASK              0xf800
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_BITS              5
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_SHIFT             11

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_A :: BITS_10_0_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LOC_DEV_MSG_6_B
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_B :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_MASK              0xf800
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_BITS              5
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_SHIFT             11

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_21_17_OF_LOC_DEV_MSG_6 [10:06] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_MASK 0x07c0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_BITS 5
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_SHIFT 6

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_16_11_OF_LOC_DEV_MSG_6 [05:00] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_MASK 0x003f
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_BITS 6
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LOC_DEV_MSG_6_C
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_C :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_MASK              0xf800
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_BITS              5
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_SHIFT             11

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_32_23_OF_LOC_DEV_MSG_6 [10:01] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_MASK 0x07fe
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_BITS 10
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_SHIFT 1

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_22_22_OF_LOC_DEV_MSG_6 [00:00] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_C,0x1,0,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_C,0x1,0)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_MASK 0x0001
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_BITS 1
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LOC_DEV_MSG_6_D
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_D :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_MASK              0xf800
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_ALIGN             0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_BITS              5
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_SHIFT             11

/* BRPHY0_CL45VEN :: LOC_DEV_MSG_6_D :: BITS_43_33_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0)
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY0_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_A
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_A :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_MASK           0xf800
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_ALIGN          0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_BITS           5
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_SHIFT          11

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_A :: BITS_10_0_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_B
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_B :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_MASK           0xf800
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_ALIGN          0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_BITS           5
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_SHIFT          11

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_B :: BITS_21_11_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_C
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_C :: reserved0 [15:11] */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_MASK           0xf800
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_ALIGN          0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_BITS           5
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_SHIFT          11

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_C :: BITS_32_22_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_D
 ***************************************************************************/
/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_OUI_MATCH [15:15] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_MASK     0x8000
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_ALIGN    0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_BITS     1
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_SHIFT    15

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_MODEL_MATCH [14:14] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_MASK   0x4000
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_ALIGN  0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_BITS   1
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_SHIFT  14

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_REV_MATCH [13:13] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_MASK     0x2000
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_ALIGN    0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_BITS     1
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_SHIFT    13

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_D :: reserved0 [12:11] */
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_MASK           0x1800
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_ALIGN          0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_BITS           2
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_SHIFT          11

/* BRPHY0_CL45VEN :: LNK_PARTNR_MSG_6_D :: BITS_43_33_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0)
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY0_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_GPHY_CORE
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE10
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE10 :: MAC_PHY_IF [15:15] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_MAC_PHY_IF(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_MAC_PHY_IF(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x8000,15)
#define BRPHY0_GPHY_CORE_BASE10_MAC_PHY_IF_MASK                    0x8000
#define BRPHY0_GPHY_CORE_BASE10_MAC_PHY_IF_ALIGN                   0
#define BRPHY0_GPHY_CORE_BASE10_MAC_PHY_IF_BITS                    1
#define BRPHY0_GPHY_CORE_BASE10_MAC_PHY_IF_SHIFT                   15

/* BRPHY0_GPHY_CORE :: BASE10 :: AUTO_MDIX_DIS [14:14] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x4000,14)
#define BRPHY0_GPHY_CORE_BASE10_AUTO_MDIX_DIS_MASK                 0x4000
#define BRPHY0_GPHY_CORE_BASE10_AUTO_MDIX_DIS_ALIGN                0
#define BRPHY0_GPHY_CORE_BASE10_AUTO_MDIX_DIS_BITS                 1
#define BRPHY0_GPHY_CORE_BASE10_AUTO_MDIX_DIS_SHIFT                14

/* BRPHY0_GPHY_CORE :: BASE10 :: TX_DIS [13:13] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_TX_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_TX_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x2000,13)
#define BRPHY0_GPHY_CORE_BASE10_TX_DIS_MASK                        0x2000
#define BRPHY0_GPHY_CORE_BASE10_TX_DIS_ALIGN                       0
#define BRPHY0_GPHY_CORE_BASE10_TX_DIS_BITS                        1
#define BRPHY0_GPHY_CORE_BASE10_TX_DIS_SHIFT                       13

/* BRPHY0_GPHY_CORE :: BASE10 :: INT_DIS [12:12] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_INT_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_INT_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x1000,12)
#define BRPHY0_GPHY_CORE_BASE10_INT_DIS_MASK                       0x1000
#define BRPHY0_GPHY_CORE_BASE10_INT_DIS_ALIGN                      0
#define BRPHY0_GPHY_CORE_BASE10_INT_DIS_BITS                       1
#define BRPHY0_GPHY_CORE_BASE10_INT_DIS_SHIFT                      12

/* BRPHY0_GPHY_CORE :: BASE10 :: FORCE_INT [11:11] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_FORCE_INT(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_FORCE_INT(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x800,11)
#define BRPHY0_GPHY_CORE_BASE10_FORCE_INT_MASK                     0x0800
#define BRPHY0_GPHY_CORE_BASE10_FORCE_INT_ALIGN                    0
#define BRPHY0_GPHY_CORE_BASE10_FORCE_INT_BITS                     1
#define BRPHY0_GPHY_CORE_BASE10_FORCE_INT_SHIFT                    11

/* BRPHY0_GPHY_CORE :: BASE10 :: BYPASS_ENCODER [10:10] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_BYPASS_ENCODER(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_BYPASS_ENCODER(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x400,10)
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_ENCODER_MASK                0x0400
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_ENCODER_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_ENCODER_BITS                1
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_ENCODER_SHIFT               10

/* BRPHY0_GPHY_CORE :: BASE10 :: BYPASS_SCRAMBLER [09:09] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x200,9)
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_MASK              0x0200
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_ALIGN             0
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_BITS              1
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_SHIFT             9

/* BRPHY0_GPHY_CORE :: BASE10 :: BYPASS_NRZI_MLT3 [08:08] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x100,8)
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_MASK              0x0100
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_ALIGN             0
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_BITS              1
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_SHIFT             8

/* BRPHY0_GPHY_CORE :: BASE10 :: BYPASS_ALIGNMENT [07:07] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x80,7)
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_MASK              0x0080
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_ALIGN             0
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_BITS              1
#define BRPHY0_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_SHIFT             7

/* BRPHY0_GPHY_CORE :: BASE10 :: RESET_SCRAMBLER [06:06] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x40,6)
#define BRPHY0_GPHY_CORE_BASE10_RESET_SCRAMBLER_MASK               0x0040
#define BRPHY0_GPHY_CORE_BASE10_RESET_SCRAMBLER_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE10_RESET_SCRAMBLER_BITS               1
#define BRPHY0_GPHY_CORE_BASE10_RESET_SCRAMBLER_SHIFT              6

/* BRPHY0_GPHY_CORE :: BASE10 :: LED_TRAFFIC_EN [05:05] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x20,5)
#define BRPHY0_GPHY_CORE_BASE10_LED_TRAFFIC_EN_MASK                0x0020
#define BRPHY0_GPHY_CORE_BASE10_LED_TRAFFIC_EN_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE10_LED_TRAFFIC_EN_BITS                1
#define BRPHY0_GPHY_CORE_BASE10_LED_TRAFFIC_EN_SHIFT               5

/* BRPHY0_GPHY_CORE :: BASE10 :: FORCE_LEDS_ON [04:04] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x10,4)
#define BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_ON_MASK                 0x0010
#define BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_ON_ALIGN                0
#define BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_ON_BITS                 1
#define BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_ON_SHIFT                4

/* BRPHY0_GPHY_CORE :: BASE10 :: FORCE_LEDS_OFF [03:03] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x8,3)
#define BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_OFF_MASK                0x0008
#define BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_OFF_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_OFF_BITS                1
#define BRPHY0_GPHY_CORE_BASE10_FORCE_LEDS_OFF_SHIFT               3

/* BRPHY0_GPHY_CORE :: BASE10 :: BLOCK_TXEN [02:02] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_BLOCK_TXEN(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_BLOCK_TXEN(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x4,2)
#define BRPHY0_GPHY_CORE_BASE10_BLOCK_TXEN_MASK                    0x0004
#define BRPHY0_GPHY_CORE_BASE10_BLOCK_TXEN_ALIGN                   0
#define BRPHY0_GPHY_CORE_BASE10_BLOCK_TXEN_BITS                    1
#define BRPHY0_GPHY_CORE_BASE10_BLOCK_TXEN_SHIFT                   2

/* BRPHY0_GPHY_CORE :: BASE10 :: UNIDIR_EN [01:01] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_UNIDIR_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_UNIDIR_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x2,1)
#define BRPHY0_GPHY_CORE_BASE10_UNIDIR_EN_MASK                     0x0002
#define BRPHY0_GPHY_CORE_BASE10_UNIDIR_EN_ALIGN                    0
#define BRPHY0_GPHY_CORE_BASE10_UNIDIR_EN_BITS                     1
#define BRPHY0_GPHY_CORE_BASE10_UNIDIR_EN_SHIFT                    1

/* BRPHY0_GPHY_CORE :: BASE10 :: GMII_RGMII_FIFO_ELASTICITY [00:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE10,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE10,0x1,0)
#define BRPHY0_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_MASK    0x0001
#define BRPHY0_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_ALIGN   0
#define BRPHY0_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_BITS    1
#define BRPHY0_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_SHIFT   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE11
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE11 :: AUTONEG_FIELD_MISMATCH [15:15] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x8000,15)
#define BRPHY0_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_MASK        0x8000
#define BRPHY0_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_ALIGN       0
#define BRPHY0_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_BITS        1
#define BRPHY0_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_SHIFT       15

/* BRPHY0_GPHY_CORE :: BASE11 :: WIRESPD_DOWNGRADE [14:14] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x4000,14)
#define BRPHY0_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_MASK             0x4000
#define BRPHY0_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_ALIGN            0
#define BRPHY0_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_BITS             1
#define BRPHY0_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_SHIFT            14

/* BRPHY0_GPHY_CORE :: BASE11 :: MDIX_STATE [13:13] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_MDIX_STATE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_MDIX_STATE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x2000,13)
#define BRPHY0_GPHY_CORE_BASE11_MDIX_STATE_MASK                    0x2000
#define BRPHY0_GPHY_CORE_BASE11_MDIX_STATE_ALIGN                   0
#define BRPHY0_GPHY_CORE_BASE11_MDIX_STATE_BITS                    1
#define BRPHY0_GPHY_CORE_BASE11_MDIX_STATE_SHIFT                   13

/* BRPHY0_GPHY_CORE :: BASE11 :: INT_STATUS [12:12] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_INT_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_INT_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x1000,12)
#define BRPHY0_GPHY_CORE_BASE11_INT_STATUS_MASK                    0x1000
#define BRPHY0_GPHY_CORE_BASE11_INT_STATUS_ALIGN                   0
#define BRPHY0_GPHY_CORE_BASE11_INT_STATUS_BITS                    1
#define BRPHY0_GPHY_CORE_BASE11_INT_STATUS_SHIFT                   12

/* BRPHY0_GPHY_CORE :: BASE11 :: RMT_RCVR_STATUS [11:11] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x800,11)
#define BRPHY0_GPHY_CORE_BASE11_RMT_RCVR_STATUS_MASK               0x0800
#define BRPHY0_GPHY_CORE_BASE11_RMT_RCVR_STATUS_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE11_RMT_RCVR_STATUS_BITS               1
#define BRPHY0_GPHY_CORE_BASE11_RMT_RCVR_STATUS_SHIFT              11

/* BRPHY0_GPHY_CORE :: BASE11 :: LOCAL_RCVR_STATUS [10:10] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x400,10)
#define BRPHY0_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_MASK             0x0400
#define BRPHY0_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_ALIGN            0
#define BRPHY0_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_BITS             1
#define BRPHY0_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_SHIFT            10

/* BRPHY0_GPHY_CORE :: BASE11 :: LOCKED [09:09] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_LOCKED(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_LOCKED(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x200,9)
#define BRPHY0_GPHY_CORE_BASE11_LOCKED_MASK                        0x0200
#define BRPHY0_GPHY_CORE_BASE11_LOCKED_ALIGN                       0
#define BRPHY0_GPHY_CORE_BASE11_LOCKED_BITS                        1
#define BRPHY0_GPHY_CORE_BASE11_LOCKED_SHIFT                       9

/* BRPHY0_GPHY_CORE :: BASE11 :: LINK_STATUS [08:08] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_LINK_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_LINK_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x100,8)
#define BRPHY0_GPHY_CORE_BASE11_LINK_STATUS_MASK                   0x0100
#define BRPHY0_GPHY_CORE_BASE11_LINK_STATUS_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE11_LINK_STATUS_BITS                   1
#define BRPHY0_GPHY_CORE_BASE11_LINK_STATUS_SHIFT                  8

/* BRPHY0_GPHY_CORE :: BASE11 :: CRC_ERR_DET [07:07] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_CRC_ERR_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_CRC_ERR_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x80,7)
#define BRPHY0_GPHY_CORE_BASE11_CRC_ERR_DET_MASK                   0x0080
#define BRPHY0_GPHY_CORE_BASE11_CRC_ERR_DET_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE11_CRC_ERR_DET_BITS                   1
#define BRPHY0_GPHY_CORE_BASE11_CRC_ERR_DET_SHIFT                  7

/* BRPHY0_GPHY_CORE :: BASE11 :: CR_EXT_ERR_DET [06:06] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x40,6)
#define BRPHY0_GPHY_CORE_BASE11_CR_EXT_ERR_DET_MASK                0x0040
#define BRPHY0_GPHY_CORE_BASE11_CR_EXT_ERR_DET_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE11_CR_EXT_ERR_DET_BITS                1
#define BRPHY0_GPHY_CORE_BASE11_CR_EXT_ERR_DET_SHIFT               6

/* BRPHY0_GPHY_CORE :: BASE11 :: BAD_SSD_DET_CR [05:05] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x20,5)
#define BRPHY0_GPHY_CORE_BASE11_BAD_SSD_DET_CR_MASK                0x0020
#define BRPHY0_GPHY_CORE_BASE11_BAD_SSD_DET_CR_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE11_BAD_SSD_DET_CR_BITS                1
#define BRPHY0_GPHY_CORE_BASE11_BAD_SSD_DET_CR_SHIFT               5

/* BRPHY0_GPHY_CORE :: BASE11 :: BAD_ESD_DET_END [04:04] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x10,4)
#define BRPHY0_GPHY_CORE_BASE11_BAD_ESD_DET_END_MASK               0x0010
#define BRPHY0_GPHY_CORE_BASE11_BAD_ESD_DET_END_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE11_BAD_ESD_DET_END_BITS               1
#define BRPHY0_GPHY_CORE_BASE11_BAD_ESD_DET_END_SHIFT              4

/* BRPHY0_GPHY_CORE :: BASE11 :: RCV_ERR_DET [03:03] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_RCV_ERR_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_RCV_ERR_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x8,3)
#define BRPHY0_GPHY_CORE_BASE11_RCV_ERR_DET_MASK                   0x0008
#define BRPHY0_GPHY_CORE_BASE11_RCV_ERR_DET_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE11_RCV_ERR_DET_BITS                   1
#define BRPHY0_GPHY_CORE_BASE11_RCV_ERR_DET_SHIFT                  3

/* BRPHY0_GPHY_CORE :: BASE11 :: TX_ERR_DET [02:02] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_TX_ERR_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_TX_ERR_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x4,2)
#define BRPHY0_GPHY_CORE_BASE11_TX_ERR_DET_MASK                    0x0004
#define BRPHY0_GPHY_CORE_BASE11_TX_ERR_DET_ALIGN                   0
#define BRPHY0_GPHY_CORE_BASE11_TX_ERR_DET_BITS                    1
#define BRPHY0_GPHY_CORE_BASE11_TX_ERR_DET_SHIFT                   2

/* BRPHY0_GPHY_CORE :: BASE11 :: LOCK_ERR_DET [01:01] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_LOCK_ERR_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_LOCK_ERR_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x2,1)
#define BRPHY0_GPHY_CORE_BASE11_LOCK_ERR_DET_MASK                  0x0002
#define BRPHY0_GPHY_CORE_BASE11_LOCK_ERR_DET_ALIGN                 0
#define BRPHY0_GPHY_CORE_BASE11_LOCK_ERR_DET_BITS                  1
#define BRPHY0_GPHY_CORE_BASE11_LOCK_ERR_DET_SHIFT                 1

/* BRPHY0_GPHY_CORE :: BASE11 :: MLT3_ERR_DET [00:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE11_MLT3_ERR_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE11,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE11_MLT3_ERR_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE11,0x1,0)
#define BRPHY0_GPHY_CORE_BASE11_MLT3_ERR_DET_MASK                  0x0001
#define BRPHY0_GPHY_CORE_BASE11_MLT3_ERR_DET_ALIGN                 0
#define BRPHY0_GPHY_CORE_BASE11_MLT3_ERR_DET_BITS                  1
#define BRPHY0_GPHY_CORE_BASE11_MLT3_ERR_DET_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE12
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE12 :: RCV_ERR_CNTR [15:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) WriteReg16(BRPHY0_GPHY_CORE_BASE12,x)
#define Rd_BRPHY0_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) ReadReg16(BRPHY0_GPHY_CORE_BASE12)
#define BRPHY0_GPHY_CORE_BASE12_RCV_ERR_CNTR_MASK                  0xffff
#define BRPHY0_GPHY_CORE_BASE12_RCV_ERR_CNTR_ALIGN                 0
#define BRPHY0_GPHY_CORE_BASE12_RCV_ERR_CNTR_BITS                  16
#define BRPHY0_GPHY_CORE_BASE12_RCV_ERR_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE13
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE13 :: SERDES_BER_CNTR [15:08] */
#define Wr_BRPHY0_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE13,0xff00,8,x)
#define Rd_BRPHY0_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE13,0xff00,8)
#define BRPHY0_GPHY_CORE_BASE13_SERDES_BER_CNTR_MASK               0xff00
#define BRPHY0_GPHY_CORE_BASE13_SERDES_BER_CNTR_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE13_SERDES_BER_CNTR_BITS               8
#define BRPHY0_GPHY_CORE_BASE13_SERDES_BER_CNTR_SHIFT              8

/* BRPHY0_GPHY_CORE :: BASE13 :: FALSE_CRS_CNTR [07:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE13,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE13,0xff,0)
#define BRPHY0_GPHY_CORE_BASE13_FALSE_CRS_CNTR_MASK                0x00ff
#define BRPHY0_GPHY_CORE_BASE13_FALSE_CRS_CNTR_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE13_FALSE_CRS_CNTR_BITS                8
#define BRPHY0_GPHY_CORE_BASE13_FALSE_CRS_CNTR_SHIFT               0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE14
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE14 :: LOCAL_RCVR_NOK_CNTR [15:08] */
#define Wr_BRPHY0_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE14,0xff00,8,x)
#define Rd_BRPHY0_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE14,0xff00,8)
#define BRPHY0_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_MASK           0xff00
#define BRPHY0_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_ALIGN          0
#define BRPHY0_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_BITS           8
#define BRPHY0_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_SHIFT          8

/* BRPHY0_GPHY_CORE :: BASE14 :: REMOTE_RCVR_NOK_CNTR [07:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE14,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE14,0xff,0)
#define BRPHY0_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_MASK          0x00ff
#define BRPHY0_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_ALIGN         0
#define BRPHY0_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_BITS          8
#define BRPHY0_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_SHIFT         0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP45
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP45 :: SEL_SERDES_TX [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXP45_SEL_SERDES_TX(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP45,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXP45_SEL_SERDES_TX(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP45,0x8000,15)
#define BRPHY0_GPHY_CORE_EXP45_SEL_SERDES_TX_MASK                  0x8000
#define BRPHY0_GPHY_CORE_EXP45_SEL_SERDES_TX_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP45_SEL_SERDES_TX_BITS                  1
#define BRPHY0_GPHY_CORE_EXP45_SEL_SERDES_TX_SHIFT                 15

/* BRPHY0_GPHY_CORE :: EXP45 :: TX_ERR [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXP45_TX_ERR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP45,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXP45_TX_ERR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP45,0x4000,14)
#define BRPHY0_GPHY_CORE_EXP45_TX_ERR_MASK                         0x4000
#define BRPHY0_GPHY_CORE_EXP45_TX_ERR_ALIGN                        0
#define BRPHY0_GPHY_CORE_EXP45_TX_ERR_BITS                         1
#define BRPHY0_GPHY_CORE_EXP45_TX_ERR_SHIFT                        14

/* BRPHY0_GPHY_CORE :: EXP45 :: SKIP_CRC [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXP45_SKIP_CRC(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP45,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXP45_SKIP_CRC(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP45,0x2000,13)
#define BRPHY0_GPHY_CORE_EXP45_SKIP_CRC_MASK                       0x2000
#define BRPHY0_GPHY_CORE_EXP45_SKIP_CRC_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP45_SKIP_CRC_BITS                       1
#define BRPHY0_GPHY_CORE_EXP45_SKIP_CRC_SHIFT                      13

/* BRPHY0_GPHY_CORE :: EXP45 :: TX_CRC_CHECKER_EN [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP45,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP45,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_MASK              0x1000
#define BRPHY0_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_BITS              1
#define BRPHY0_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_SHIFT             12

/* BRPHY0_GPHY_CORE :: EXP45 :: IPG_SEL [11:09] */
#define Wr_BRPHY0_GPHY_CORE_EXP45_IPG_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP45,0xe00,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXP45_IPG_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP45,0xe00,9)
#define BRPHY0_GPHY_CORE_EXP45_IPG_SEL_MASK                        0x0e00
#define BRPHY0_GPHY_CORE_EXP45_IPG_SEL_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP45_IPG_SEL_BITS                        3
#define BRPHY0_GPHY_CORE_EXP45_IPG_SEL_SHIFT                       9

/* BRPHY0_GPHY_CORE :: EXP45 :: PKT_SIZE [08:03] */
#define Wr_BRPHY0_GPHY_CORE_EXP45_PKT_SIZE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP45,0x1f8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXP45_PKT_SIZE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP45,0x1f8,3)
#define BRPHY0_GPHY_CORE_EXP45_PKT_SIZE_MASK                       0x01f8
#define BRPHY0_GPHY_CORE_EXP45_PKT_SIZE_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP45_PKT_SIZE_BITS                       6
#define BRPHY0_GPHY_CORE_EXP45_PKT_SIZE_SHIFT                      3

/* BRPHY0_GPHY_CORE :: EXP45 :: SINGLE_PASS [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP45_SINGLE_PASS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP45,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP45_SINGLE_PASS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP45,0x4,2)
#define BRPHY0_GPHY_CORE_EXP45_SINGLE_PASS_MASK                    0x0004
#define BRPHY0_GPHY_CORE_EXP45_SINGLE_PASS_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP45_SINGLE_PASS_BITS                    1
#define BRPHY0_GPHY_CORE_EXP45_SINGLE_PASS_SHIFT                   2

/* BRPHY0_GPHY_CORE :: EXP45 :: RUN_PAT_GEN [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP45_RUN_PAT_GEN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP45,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP45_RUN_PAT_GEN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP45,0x2,1)
#define BRPHY0_GPHY_CORE_EXP45_RUN_PAT_GEN_MASK                    0x0002
#define BRPHY0_GPHY_CORE_EXP45_RUN_PAT_GEN_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP45_RUN_PAT_GEN_BITS                    1
#define BRPHY0_GPHY_CORE_EXP45_RUN_PAT_GEN_SHIFT                   1

/* BRPHY0_GPHY_CORE :: EXP45 :: SEL_PAT_GEN_DATA [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP45,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP45,0x1,0)
#define BRPHY0_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_MASK               0x0001
#define BRPHY0_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_BITS               1
#define BRPHY0_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP46
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP46 :: GMII_FIFO_ELASTICITY_1 [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP46,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP46,0x8000,15)
#define BRPHY0_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_MASK         0x8000
#define BRPHY0_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_ALIGN        0
#define BRPHY0_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_BITS         1
#define BRPHY0_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_SHIFT        15

/* BRPHY0_GPHY_CORE :: EXP46 :: GMII_RGMII_FIFO_ELASTICITY_1 [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP46,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP46,0x4000,14)
#define BRPHY0_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_MASK   0x4000
#define BRPHY0_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_ALIGN  0
#define BRPHY0_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_BITS   1
#define BRPHY0_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_SHIFT  14

/* BRPHY0_GPHY_CORE :: EXP46 :: PKT_SIZE_6 [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXP46_PKT_SIZE_6(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP46,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXP46_PKT_SIZE_6(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP46,0x2000,13)
#define BRPHY0_GPHY_CORE_EXP46_PKT_SIZE_6_MASK                     0x2000
#define BRPHY0_GPHY_CORE_EXP46_PKT_SIZE_6_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP46_PKT_SIZE_6_BITS                     1
#define BRPHY0_GPHY_CORE_EXP46_PKT_SIZE_6_SHIFT                    13

/* BRPHY0_GPHY_CORE :: EXP46 :: CR_EXT [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP46_CR_EXT(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP46,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP46_CR_EXT(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP46,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP46_CR_EXT_MASK                         0x1000
#define BRPHY0_GPHY_CORE_EXP46_CR_EXT_ALIGN                        0
#define BRPHY0_GPHY_CORE_EXP46_CR_EXT_BITS                         1
#define BRPHY0_GPHY_CORE_EXP46_CR_EXT_SHIFT                        12

/* BRPHY0_GPHY_CORE :: EXP46 :: reserved0 [11:07] */
#define BRPHY0_GPHY_CORE_EXP46_RESERVED0_MASK                      0x0f80
#define BRPHY0_GPHY_CORE_EXP46_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP46_RESERVED0_BITS                      5
#define BRPHY0_GPHY_CORE_EXP46_RESERVED0_SHIFT                     7

/* BRPHY0_GPHY_CORE :: EXP46 :: RGMII_FIFO_FREQ_LOCK [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP46,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP46,0x40,6)
#define BRPHY0_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_MASK           0x0040
#define BRPHY0_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_ALIGN          0
#define BRPHY0_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_BITS           1
#define BRPHY0_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_SHIFT          6

/* BRPHY0_GPHY_CORE :: EXP46 :: reserved1 [05:05] */
#define BRPHY0_GPHY_CORE_EXP46_RESERVED1_MASK                      0x0020
#define BRPHY0_GPHY_CORE_EXP46_RESERVED1_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP46_RESERVED1_BITS                      1
#define BRPHY0_GPHY_CORE_EXP46_RESERVED1_SHIFT                     5

/* BRPHY0_GPHY_CORE :: EXP46 :: SEL_PATGEN_ON_RXD [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP46,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP46,0x10,4)
#define BRPHY0_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_MASK              0x0010
#define BRPHY0_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_BITS              1
#define BRPHY0_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_SHIFT             4

/* BRPHY0_GPHY_CORE :: EXP46 :: PAT_GEN_ACTIVE [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP46,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP46,0x8,3)
#define BRPHY0_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_MASK                 0x0008
#define BRPHY0_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_BITS                 1
#define BRPHY0_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_SHIFT                3

/* BRPHY0_GPHY_CORE :: EXP46 :: PAT_GEN_FSM [02:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP46_PAT_GEN_FSM(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP46,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP46_PAT_GEN_FSM(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP46,0x7,0)
#define BRPHY0_GPHY_CORE_EXP46_PAT_GEN_FSM_MASK                    0x0007
#define BRPHY0_GPHY_CORE_EXP46_PAT_GEN_FSM_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP46_PAT_GEN_FSM_BITS                    3
#define BRPHY0_GPHY_CORE_EXP46_PAT_GEN_FSM_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE19
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE [15:15] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x8000,15)
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_MASK              0x8000
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ALIGN             0
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_BITS              1
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_SHIFT             15

/* BRPHY0_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE_ACK [14:14] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x4000,14)
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_MASK          0x4000
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_ALIGN         0
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_BITS          1
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_SHIFT         14

/* BRPHY0_GPHY_CORE :: BASE19 :: AUTONEG_ACK_DET [13:13] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x2000,13)
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_ACK_DET_MASK               0x2000
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_ACK_DET_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_ACK_DET_BITS               1
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_ACK_DET_SHIFT              13

/* BRPHY0_GPHY_CORE :: BASE19 :: AUTONEG_ABILITY_DET [12:12] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x1000,12)
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_MASK           0x1000
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_ALIGN          0
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_BITS           1
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_SHIFT          12

/* BRPHY0_GPHY_CORE :: BASE19 :: AUTONEG_NEXT_PAGE_WAIT [11:11] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x800,11)
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_MASK        0x0800
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_ALIGN       0
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_BITS        1
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_SHIFT       11

/* BRPHY0_GPHY_CORE :: BASE19 :: AUTONEG_HCD [10:08] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_AUTONEG_HCD(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x700,8,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_AUTONEG_HCD(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x700,8)
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_HCD_MASK                   0x0700
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_HCD_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_HCD_BITS                   3
#define BRPHY0_GPHY_CORE_BASE19_AUTONEG_HCD_SHIFT                  8

/* BRPHY0_GPHY_CORE :: BASE19 :: PARALLEL_DET_FAULT [07:07] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x80,7)
#define BRPHY0_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_MASK            0x0080
#define BRPHY0_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_ALIGN           0
#define BRPHY0_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_BITS            1
#define BRPHY0_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_SHIFT           7

/* BRPHY0_GPHY_CORE :: BASE19 :: REMOTE_FAULT [06:06] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_REMOTE_FAULT(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_REMOTE_FAULT(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x40,6)
#define BRPHY0_GPHY_CORE_BASE19_REMOTE_FAULT_MASK                  0x0040
#define BRPHY0_GPHY_CORE_BASE19_REMOTE_FAULT_ALIGN                 0
#define BRPHY0_GPHY_CORE_BASE19_REMOTE_FAULT_BITS                  1
#define BRPHY0_GPHY_CORE_BASE19_REMOTE_FAULT_SHIFT                 6

/* BRPHY0_GPHY_CORE :: BASE19 :: PAGE_RECEIVED [05:05] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_PAGE_RECEIVED(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_PAGE_RECEIVED(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x20,5)
#define BRPHY0_GPHY_CORE_BASE19_PAGE_RECEIVED_MASK                 0x0020
#define BRPHY0_GPHY_CORE_BASE19_PAGE_RECEIVED_ALIGN                0
#define BRPHY0_GPHY_CORE_BASE19_PAGE_RECEIVED_BITS                 1
#define BRPHY0_GPHY_CORE_BASE19_PAGE_RECEIVED_SHIFT                5

/* BRPHY0_GPHY_CORE :: BASE19 :: LINK_PARTNER_AN_ABILITY [04:04] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x10,4)
#define BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_MASK       0x0010
#define BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_SHIFT      4

/* BRPHY0_GPHY_CORE :: BASE19 :: LINK_PARTNER_NP_ABILITY [03:03] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x8,3)
#define BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_MASK       0x0008
#define BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_ALIGN      0
#define BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_BITS       1
#define BRPHY0_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_SHIFT      3

/* BRPHY0_GPHY_CORE :: BASE19 :: LINK_STATUS [02:02] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_LINK_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_LINK_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x4,2)
#define BRPHY0_GPHY_CORE_BASE19_LINK_STATUS_MASK                   0x0004
#define BRPHY0_GPHY_CORE_BASE19_LINK_STATUS_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE19_LINK_STATUS_BITS                   1
#define BRPHY0_GPHY_CORE_BASE19_LINK_STATUS_SHIFT                  2

/* BRPHY0_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_RX [01:01] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x2,1)
#define BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_MASK           0x0002
#define BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_ALIGN          0
#define BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_BITS           1
#define BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_SHIFT          1

/* BRPHY0_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_TX [00:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE19,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE19,0x1,0)
#define BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_MASK           0x0001
#define BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_ALIGN          0
#define BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_BITS           1
#define BRPHY0_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_SHIFT          0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE1A
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE1A :: IP_STATUS_CHANGE [15:15] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x8000,15)
#define BRPHY0_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_MASK              0x8000
#define BRPHY0_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_ALIGN             0
#define BRPHY0_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_BITS              1
#define BRPHY0_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_SHIFT             15

/* BRPHY0_GPHY_CORE :: BASE1A :: ILLEGAL_PAIR_SWAP [14:14] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x4000,14)
#define BRPHY0_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_MASK             0x4000
#define BRPHY0_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_ALIGN            0
#define BRPHY0_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_BITS             1
#define BRPHY0_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_SHIFT            14

/* BRPHY0_GPHY_CORE :: BASE1A :: MDIX_STATUS_CHANGE [13:13] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x2000,13)
#define BRPHY0_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_MASK            0x2000
#define BRPHY0_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_ALIGN           0
#define BRPHY0_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_BITS            1
#define BRPHY0_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_SHIFT           13

/* BRPHY0_GPHY_CORE :: BASE1A :: EXCEED_HIGH_CNTR_THD [12:12] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x1000,12)
#define BRPHY0_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_MASK          0x1000
#define BRPHY0_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_ALIGN         0
#define BRPHY0_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_BITS          1
#define BRPHY0_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_SHIFT         12

/* BRPHY0_GPHY_CORE :: BASE1A :: EXCEED_LOW_CNTR_THD [11:11] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x800,11)
#define BRPHY0_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_MASK           0x0800
#define BRPHY0_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_ALIGN          0
#define BRPHY0_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_BITS           1
#define BRPHY0_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_SHIFT          11

/* BRPHY0_GPHY_CORE :: BASE1A :: AUTONEG_PAGE_RX [10:10] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x400,10)
#define BRPHY0_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_MASK               0x0400
#define BRPHY0_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_BITS               1
#define BRPHY0_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_SHIFT              10

/* BRPHY0_GPHY_CORE :: BASE1A :: HCD_NO_LINK [09:09] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_HCD_NO_LINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_HCD_NO_LINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x200,9)
#define BRPHY0_GPHY_CORE_BASE1A_HCD_NO_LINK_MASK                   0x0200
#define BRPHY0_GPHY_CORE_BASE1A_HCD_NO_LINK_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE1A_HCD_NO_LINK_BITS                   1
#define BRPHY0_GPHY_CORE_BASE1A_HCD_NO_LINK_SHIFT                  9

/* BRPHY0_GPHY_CORE :: BASE1A :: NO_HCD [08:08] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_NO_HCD(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_NO_HCD(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x100,8)
#define BRPHY0_GPHY_CORE_BASE1A_NO_HCD_MASK                        0x0100
#define BRPHY0_GPHY_CORE_BASE1A_NO_HCD_ALIGN                       0
#define BRPHY0_GPHY_CORE_BASE1A_NO_HCD_BITS                        1
#define BRPHY0_GPHY_CORE_BASE1A_NO_HCD_SHIFT                       8

/* BRPHY0_GPHY_CORE :: BASE1A :: NEGOTIATED_UNSUPPORTED_HCD [07:07] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x80,7)
#define BRPHY0_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_MASK    0x0080
#define BRPHY0_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_ALIGN   0
#define BRPHY0_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_BITS    1
#define BRPHY0_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_SHIFT   7

/* BRPHY0_GPHY_CORE :: BASE1A :: SCR_SYNC_ERROR [06:06] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x40,6)
#define BRPHY0_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_MASK                0x0040
#define BRPHY0_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_BITS                1
#define BRPHY0_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_SHIFT               6

/* BRPHY0_GPHY_CORE :: BASE1A :: RMT_RCVR_STATUS_CHANGE [05:05] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x20,5)
#define BRPHY0_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_MASK        0x0020
#define BRPHY0_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_ALIGN       0
#define BRPHY0_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_BITS        1
#define BRPHY0_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_SHIFT       5

/* BRPHY0_GPHY_CORE :: BASE1A :: LOCAL_RCVR_STATUS_CHANGE [04:04] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x10,4)
#define BRPHY0_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_MASK      0x0010
#define BRPHY0_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_ALIGN     0
#define BRPHY0_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_BITS      1
#define BRPHY0_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_SHIFT     4

/* BRPHY0_GPHY_CORE :: BASE1A :: DUPLEX_CHANGE [03:03] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x8,3)
#define BRPHY0_GPHY_CORE_BASE1A_DUPLEX_CHANGE_MASK                 0x0008
#define BRPHY0_GPHY_CORE_BASE1A_DUPLEX_CHANGE_ALIGN                0
#define BRPHY0_GPHY_CORE_BASE1A_DUPLEX_CHANGE_BITS                 1
#define BRPHY0_GPHY_CORE_BASE1A_DUPLEX_CHANGE_SHIFT                3

/* BRPHY0_GPHY_CORE :: BASE1A :: LINK_SPEED_CHANGE [02:02] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x4,2)
#define BRPHY0_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_MASK             0x0004
#define BRPHY0_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_ALIGN            0
#define BRPHY0_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_BITS             1
#define BRPHY0_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_SHIFT            2

/* BRPHY0_GPHY_CORE :: BASE1A :: LINK_STATUS_CHANGE [01:01] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x2,1)
#define BRPHY0_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_MASK            0x0002
#define BRPHY0_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_ALIGN           0
#define BRPHY0_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_BITS            1
#define BRPHY0_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_SHIFT           1

/* BRPHY0_GPHY_CORE :: BASE1A :: CRC_ERROR [00:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE1A_CRC_ERROR(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1A_CRC_ERROR(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1A,0x1,0)
#define BRPHY0_GPHY_CORE_BASE1A_CRC_ERROR_MASK                     0x0001
#define BRPHY0_GPHY_CORE_BASE1A_CRC_ERROR_ALIGN                    0
#define BRPHY0_GPHY_CORE_BASE1A_CRC_ERROR_BITS                     1
#define BRPHY0_GPHY_CORE_BASE1A_CRC_ERROR_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE1B
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE1B :: INT_MASK_VECTOR [15:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) WriteReg16(BRPHY0_GPHY_CORE_BASE1B,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) ReadReg16(BRPHY0_GPHY_CORE_BASE1B)
#define BRPHY0_GPHY_CORE_BASE1B_INT_MASK_VECTOR_MASK               0xffff
#define BRPHY0_GPHY_CORE_BASE1B_INT_MASK_VECTOR_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE1B_INT_MASK_VECTOR_BITS               16
#define BRPHY0_GPHY_CORE_BASE1B_INT_MASK_VECTOR_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE1D_SHD
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x8000,15)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_MASK    0x8000
#define BRPHY0_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_ALIGN   0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_BITS    1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_SHIFT   15

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: GB_ADV_DIS [14:14] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x4000,14)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_MASK                0x4000
#define BRPHY0_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_BITS                1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_SHIFT               14

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: TX_ADV_DIS [13:13] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x2000,13)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_MASK                0x2000
#define BRPHY0_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_BITS                1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_SHIFT               13

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: WIRESPEED_DOWNGRADE [12:12] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x1000,12)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_MASK       0x1000
#define BRPHY0_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_ALIGN      0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_BITS       1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_SHIFT      12

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX [11:11] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x800,11)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_MASK             0x0800
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_ALIGN            0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_BITS             1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_SHIFT            11

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_1000T [10:10] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x400,10)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_MASK                 0x0400
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_ALIGN                0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_BITS                 1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_SHIFT                10

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX [09:09] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x200,9)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_MASK              0x0200
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_ALIGN             0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_BITS              1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_SHIFT             9

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_100T [08:08] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x100,8)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_MASK                  0x0100
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_ALIGN                 0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_BITS                  1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_SHIFT                 8

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX [07:07] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x80,7)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_MASK               0x0080
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_BITS               1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_SHIFT              7

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_10T [06:06] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x40,6)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_MASK                   0x0040
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_BITS                   1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_SHIFT                  6

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX_NL [05:05] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x20,5)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_MASK          0x0020
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_ALIGN         0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_BITS          1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_SHIFT         5

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_NL [04:04] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x10,4)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_MASK              0x0010
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_ALIGN             0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_BITS              1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_SHIFT             4

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX_NL [03:03] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x8,3)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_MASK           0x0008
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_ALIGN          0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_BITS           1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_SHIFT          3

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_100T_NL [02:02] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x4,2)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_MASK               0x0004
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_BITS               1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_SHIFT              2

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX_NL [01:01] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x2,1)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_MASK            0x0002
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_ALIGN           0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_BITS            1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_SHIFT           1

/* BRPHY0_GPHY_CORE :: BASE1D_SHD :: HCD_10T_NL [00:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D_SHD,0x1,0)
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_MASK                0x0001
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_BITS                1
#define BRPHY0_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_SHIFT               0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE1D
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE1D :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x8000,15)
#define BRPHY0_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_MASK        0x8000
#define BRPHY0_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_ALIGN       0
#define BRPHY0_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_BITS        1
#define BRPHY0_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_SHIFT       15

/* BRPHY0_GPHY_CORE :: BASE1D :: MASTER_SLAVE_SEED_MATCH [14:14] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x4000,14)
#define BRPHY0_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_MASK       0x4000
#define BRPHY0_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_ALIGN      0
#define BRPHY0_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_BITS       1
#define BRPHY0_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_SHIFT      14

/* BRPHY0_GPHY_CORE :: BASE1D :: LINK_PARTNER_RD_BIT [13:13] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x2000,13)
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_MASK           0x2000
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_ALIGN          0
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_BITS           1
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_SHIFT          13

/* BRPHY0_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_VALUE [12:12] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x1000,12)
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_MASK         0x1000
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_ALIGN        0
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_BITS         1
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_SHIFT        12

/* BRPHY0_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_CFG_EN [11:11] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x800,11)
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_MASK        0x0800
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_ALIGN       0
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_BITS        1
#define BRPHY0_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_SHIFT       11

/* BRPHY0_GPHY_CORE :: BASE1D :: LOCAL_MS_SEED_VALUE [10:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x7ff,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1D,0x7ff,0)
#define BRPHY0_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_MASK           0x07ff
#define BRPHY0_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_ALIGN          0
#define BRPHY0_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_BITS           11
#define BRPHY0_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_SHIFT          0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE1E
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE1E :: CRC_ERR_CNT [15:15] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x8000,15)
#define BRPHY0_GPHY_CORE_BASE1E_CRC_ERR_CNT_MASK                   0x8000
#define BRPHY0_GPHY_CORE_BASE1E_CRC_ERR_CNT_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE1E_CRC_ERR_CNT_BITS                   1
#define BRPHY0_GPHY_CORE_BASE1E_CRC_ERR_CNT_SHIFT                  15

/* BRPHY0_GPHY_CORE :: BASE1E :: TX_ERR_CODE [14:14] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_TX_ERR_CODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_TX_ERR_CODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x4000,14)
#define BRPHY0_GPHY_CORE_BASE1E_TX_ERR_CODE_MASK                   0x4000
#define BRPHY0_GPHY_CORE_BASE1E_TX_ERR_CODE_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE1E_TX_ERR_CODE_BITS                   1
#define BRPHY0_GPHY_CORE_BASE1E_TX_ERR_CODE_SHIFT                  14

/* BRPHY0_GPHY_CORE :: BASE1E :: CNTR_TEST [13:13] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_CNTR_TEST(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_CNTR_TEST(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x2000,13)
#define BRPHY0_GPHY_CORE_BASE1E_CNTR_TEST_MASK                     0x2000
#define BRPHY0_GPHY_CORE_BASE1E_CNTR_TEST_ALIGN                    0
#define BRPHY0_GPHY_CORE_BASE1E_CNTR_TEST_BITS                     1
#define BRPHY0_GPHY_CORE_BASE1E_CNTR_TEST_SHIFT                    13

/* BRPHY0_GPHY_CORE :: BASE1E :: FORCE_LINK [12:12] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_FORCE_LINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_FORCE_LINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x1000,12)
#define BRPHY0_GPHY_CORE_BASE1E_FORCE_LINK_MASK                    0x1000
#define BRPHY0_GPHY_CORE_BASE1E_FORCE_LINK_ALIGN                   0
#define BRPHY0_GPHY_CORE_BASE1E_FORCE_LINK_BITS                    1
#define BRPHY0_GPHY_CORE_BASE1E_FORCE_LINK_SHIFT                   12

/* BRPHY0_GPHY_CORE :: BASE1E :: FORCE_LOCK [11:11] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_FORCE_LOCK(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_FORCE_LOCK(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x800,11)
#define BRPHY0_GPHY_CORE_BASE1E_FORCE_LOCK_MASK                    0x0800
#define BRPHY0_GPHY_CORE_BASE1E_FORCE_LOCK_ALIGN                   0
#define BRPHY0_GPHY_CORE_BASE1E_FORCE_LOCK_BITS                    1
#define BRPHY0_GPHY_CORE_BASE1E_FORCE_LOCK_SHIFT                   11

/* BRPHY0_GPHY_CORE :: BASE1E :: SCR_TEST [10:10] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_SCR_TEST(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_SCR_TEST(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x400,10)
#define BRPHY0_GPHY_CORE_BASE1E_SCR_TEST_MASK                      0x0400
#define BRPHY0_GPHY_CORE_BASE1E_SCR_TEST_ALIGN                     0
#define BRPHY0_GPHY_CORE_BASE1E_SCR_TEST_BITS                      1
#define BRPHY0_GPHY_CORE_BASE1E_SCR_TEST_SHIFT                     10

/* BRPHY0_GPHY_CORE :: BASE1E :: EXT_LINK [09:09] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_EXT_LINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_EXT_LINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x200,9)
#define BRPHY0_GPHY_CORE_BASE1E_EXT_LINK_MASK                      0x0200
#define BRPHY0_GPHY_CORE_BASE1E_EXT_LINK_ALIGN                     0
#define BRPHY0_GPHY_CORE_BASE1E_EXT_LINK_BITS                      1
#define BRPHY0_GPHY_CORE_BASE1E_EXT_LINK_SHIFT                     9

/* BRPHY0_GPHY_CORE :: BASE1E :: FAST_TIMERS [08:08] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_FAST_TIMERS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_FAST_TIMERS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x100,8)
#define BRPHY0_GPHY_CORE_BASE1E_FAST_TIMERS_MASK                   0x0100
#define BRPHY0_GPHY_CORE_BASE1E_FAST_TIMERS_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE1E_FAST_TIMERS_BITS                   1
#define BRPHY0_GPHY_CORE_BASE1E_FAST_TIMERS_SHIFT                  8

/* BRPHY0_GPHY_CORE :: BASE1E :: MANUAL_SWAP_MDI [07:07] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x80,7)
#define BRPHY0_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_MASK               0x0080
#define BRPHY0_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_BITS               1
#define BRPHY0_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_SHIFT              7

/* BRPHY0_GPHY_CORE :: BASE1E :: RX_WATCHDOG_TIMER_DIS [06:06] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x40,6)
#define BRPHY0_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_MASK         0x0040
#define BRPHY0_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_ALIGN        0
#define BRPHY0_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_BITS         1
#define BRPHY0_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_SHIFT        6

/* BRPHY0_GPHY_CORE :: BASE1E :: POLARITY_ENCODE_DIS [05:05] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x20,5)
#define BRPHY0_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_MASK           0x0020
#define BRPHY0_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_ALIGN          0
#define BRPHY0_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_BITS           1
#define BRPHY0_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_SHIFT          5

/* BRPHY0_GPHY_CORE :: BASE1E :: SOFT_TRIM_SETTING_EN [04:04] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0x10,4)
#define BRPHY0_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_MASK          0x0010
#define BRPHY0_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_ALIGN         0
#define BRPHY0_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_BITS          1
#define BRPHY0_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_SHIFT         4

/* BRPHY0_GPHY_CORE :: BASE1E :: TRIM_MAIN_DAC [03:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1E,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1E,0xf,0)
#define BRPHY0_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_MASK                 0x000f
#define BRPHY0_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_ALIGN                0
#define BRPHY0_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_BITS                 4
#define BRPHY0_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_SHIFT                0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BASE1F
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BASE1F :: TEST_SEL_AUTONEG_FSM [15:13] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0xe000,13,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0xe000,13)
#define BRPHY0_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_MASK          0xe000
#define BRPHY0_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_ALIGN         0
#define BRPHY0_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_BITS          3
#define BRPHY0_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_SHIFT         13

/* BRPHY0_GPHY_CORE :: BASE1F :: TEST_AUTONEG_TIMER [12:12] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x1000,12)
#define BRPHY0_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_MASK            0x1000
#define BRPHY0_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_ALIGN           0
#define BRPHY0_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_BITS            1
#define BRPHY0_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_SHIFT           12

/* BRPHY0_GPHY_CORE :: BASE1F :: TEST_MS_SEED [11:11] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_TEST_MS_SEED(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_TEST_MS_SEED(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x800,11)
#define BRPHY0_GPHY_CORE_BASE1F_TEST_MS_SEED_MASK                  0x0800
#define BRPHY0_GPHY_CORE_BASE1F_TEST_MS_SEED_ALIGN                 0
#define BRPHY0_GPHY_CORE_BASE1F_TEST_MS_SEED_BITS                  1
#define BRPHY0_GPHY_CORE_BASE1F_TEST_MS_SEED_SHIFT                 11

/* BRPHY0_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_ABILITY_EN [10:10] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x400,10)
#define BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_MASK    0x0400
#define BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_ALIGN   0
#define BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_BITS    1
#define BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_SHIFT   10

/* BRPHY0_GPHY_CORE :: BASE1F :: FORCE_HCD [09:09] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_FORCE_HCD(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_FORCE_HCD(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x200,9)
#define BRPHY0_GPHY_CORE_BASE1F_FORCE_HCD_MASK                     0x0200
#define BRPHY0_GPHY_CORE_BASE1F_FORCE_HCD_ALIGN                    0
#define BRPHY0_GPHY_CORE_BASE1F_FORCE_HCD_BITS                     1
#define BRPHY0_GPHY_CORE_BASE1F_FORCE_HCD_SHIFT                    9

/* BRPHY0_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_MS_SEED_EN [08:08] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x100,8)
#define BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_MASK    0x0100
#define BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_ALIGN   0
#define BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_BITS    1
#define BRPHY0_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_SHIFT   8

/* BRPHY0_GPHY_CORE :: BASE1F :: TX_10B [07:07] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_TX_10B(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_TX_10B(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x80,7)
#define BRPHY0_GPHY_CORE_BASE1F_TX_10B_MASK                        0x0080
#define BRPHY0_GPHY_CORE_BASE1F_TX_10B_ALIGN                       0
#define BRPHY0_GPHY_CORE_BASE1F_TX_10B_BITS                        1
#define BRPHY0_GPHY_CORE_BASE1F_TX_10B_SHIFT                       7

/* BRPHY0_GPHY_CORE :: BASE1F :: RX_10B [06:06] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_RX_10B(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_RX_10B(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x40,6)
#define BRPHY0_GPHY_CORE_BASE1F_RX_10B_MASK                        0x0040
#define BRPHY0_GPHY_CORE_BASE1F_RX_10B_ALIGN                       0
#define BRPHY0_GPHY_CORE_BASE1F_RX_10B_BITS                        1
#define BRPHY0_GPHY_CORE_BASE1F_RX_10B_SHIFT                       6

/* BRPHY0_GPHY_CORE :: BASE1F :: BYPASS_TXFIFO [05:05] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x20,5)
#define BRPHY0_GPHY_CORE_BASE1F_BYPASS_TXFIFO_MASK                 0x0020
#define BRPHY0_GPHY_CORE_BASE1F_BYPASS_TXFIFO_ALIGN                0
#define BRPHY0_GPHY_CORE_BASE1F_BYPASS_TXFIFO_BITS                 1
#define BRPHY0_GPHY_CORE_BASE1F_BYPASS_TXFIFO_SHIFT                5

/* BRPHY0_GPHY_CORE :: BASE1F :: SAME_SCR_SEEDS [04:04] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x10,4)
#define BRPHY0_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_MASK                0x0010
#define BRPHY0_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_BITS                1
#define BRPHY0_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_SHIFT               4

/* BRPHY0_GPHY_CORE :: BASE1F :: JITTER_TEST [03:03] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_JITTER_TEST(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_JITTER_TEST(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x8,3)
#define BRPHY0_GPHY_CORE_BASE1F_JITTER_TEST_MASK                   0x0008
#define BRPHY0_GPHY_CORE_BASE1F_JITTER_TEST_ALIGN                  0
#define BRPHY0_GPHY_CORE_BASE1F_JITTER_TEST_BITS                   1
#define BRPHY0_GPHY_CORE_BASE1F_JITTER_TEST_SHIFT                  3

/* BRPHY0_GPHY_CORE :: BASE1F :: TEST_ATMP_CNTR [02:02] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x4,2)
#define BRPHY0_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_MASK                0x0004
#define BRPHY0_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_ALIGN               0
#define BRPHY0_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_BITS                1
#define BRPHY0_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_SHIFT               2

/* BRPHY0_GPHY_CORE :: BASE1F :: LATENCY_MEASURE [01:01] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x2,1)
#define BRPHY0_GPHY_CORE_BASE1F_LATENCY_MEASURE_MASK               0x0002
#define BRPHY0_GPHY_CORE_BASE1F_LATENCY_MEASURE_ALIGN              0
#define BRPHY0_GPHY_CORE_BASE1F_LATENCY_MEASURE_BITS               1
#define BRPHY0_GPHY_CORE_BASE1F_LATENCY_MEASURE_SHIFT              1

/* BRPHY0_GPHY_CORE :: BASE1F :: ACTIVE_HYBRID_DIS [00:00] */
#define Wr_BRPHY0_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_BASE1F,0x1,0)
#define BRPHY0_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_MASK             0x0001
#define BRPHY0_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_ALIGN            0
#define BRPHY0_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_BITS             1
#define BRPHY0_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_SHIFT            0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_00
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_00 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_00_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_00_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_00_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_00_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_00 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_00,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_00,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_00_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_00_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_00_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_00_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_00 :: reserved1 [09:08] */
#define BRPHY0_GPHY_CORE_SHD1C_00_RESERVED1_MASK                   0x0300
#define BRPHY0_GPHY_CORE_SHD1C_00_RESERVED1_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_00_RESERVED1_BITS                   2
#define BRPHY0_GPHY_CORE_SHD1C_00_RESERVED1_SHIFT                  8

/* BRPHY0_GPHY_CORE :: SHD1C_00 :: CABLETRON_LED [07:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_00,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_00,0xff,0)
#define BRPHY0_GPHY_CORE_SHD1C_00_CABLETRON_LED_MASK               0x00ff
#define BRPHY0_GPHY_CORE_SHD1C_00_CABLETRON_LED_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD1C_00_CABLETRON_LED_BITS               8
#define BRPHY0_GPHY_CORE_SHD1C_00_CABLETRON_LED_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_01
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_01 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_01_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_01_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_01_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_01_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_01 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_01,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_01,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_01_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_01_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_01_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_01_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_01 :: reserved1 [09:07] */
#define BRPHY0_GPHY_CORE_SHD1C_01_RESERVED1_MASK                   0x0380
#define BRPHY0_GPHY_CORE_SHD1C_01_RESERVED1_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_01_RESERVED1_BITS                   3
#define BRPHY0_GPHY_CORE_SHD1C_01_RESERVED1_SHIFT                  7

/* BRPHY0_GPHY_CORE :: SHD1C_01 :: TVCO_OUTPUT [06:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_01,0x7f,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_01,0x7f,0)
#define BRPHY0_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_MASK                 0x007f
#define BRPHY0_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_BITS                 7
#define BRPHY0_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_SHIFT                0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_02
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_02 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_02_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_02_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_02_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_02_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_02_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_02_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_02_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_02_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: SD_STATUS [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_SD_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_SD_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x200,9)
#define BRPHY0_GPHY_CORE_SHD1C_02_SD_STATUS_MASK                   0x0200
#define BRPHY0_GPHY_CORE_SHD1C_02_SD_STATUS_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_02_SD_STATUS_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_02_SD_STATUS_SHIFT                  9

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: FORCE_SD_ON [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x100,8)
#define BRPHY0_GPHY_CORE_SHD1C_02_FORCE_SD_ON_MASK                 0x0100
#define BRPHY0_GPHY_CORE_SHD1C_02_FORCE_SD_ON_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD1C_02_FORCE_SD_ON_BITS                 1
#define BRPHY0_GPHY_CORE_SHD1C_02_FORCE_SD_ON_SHIFT                8

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: INVERT_SD_PIN [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_MASK               0x0080
#define BRPHY0_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_BITS               1
#define BRPHY0_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_SHIFT              7

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: CFC_INITFILTER_EN [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x40,6)
#define BRPHY0_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_MASK           0x0040
#define BRPHY0_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_ALIGN          0
#define BRPHY0_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_BITS           1
#define BRPHY0_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_SHIFT          6

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: USE_FILTERED_SD [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x20,5)
#define BRPHY0_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_MASK             0x0020
#define BRPHY0_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_BITS             1
#define BRPHY0_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_SHIFT            5

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: FX_COPPER_PATH [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x10,4)
#define BRPHY0_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_MASK              0x0010
#define BRPHY0_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_BITS              1
#define BRPHY0_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_SHIFT             4

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: SPARE_REG [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x8,3)
#define BRPHY0_GPHY_CORE_SHD1C_02_SPARE_REG_MASK                   0x0008
#define BRPHY0_GPHY_CORE_SHD1C_02_SPARE_REG_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_02_SPARE_REG_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_02_SPARE_REG_SHIFT                  3

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: BC_LINK_SPEED_LED [02:02] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x4,2)
#define BRPHY0_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_MASK           0x0004
#define BRPHY0_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_ALIGN          0
#define BRPHY0_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_BITS           1
#define BRPHY0_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_SHIFT          2

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: LOST_TOKEN_FIX_DIS [01:01] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x2,1)
#define BRPHY0_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_MASK          0x0002
#define BRPHY0_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_BITS          1
#define BRPHY0_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_SHIFT         1

/* BRPHY0_GPHY_CORE :: SHD1C_02 :: LINK_LED [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_02_LINK_LED(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_02_LINK_LED(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_02,0x1,0)
#define BRPHY0_GPHY_CORE_SHD1C_02_LINK_LED_MASK                    0x0001
#define BRPHY0_GPHY_CORE_SHD1C_02_LINK_LED_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD1C_02_LINK_LED_BITS                    1
#define BRPHY0_GPHY_CORE_SHD1C_02_LINK_LED_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_03
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_03 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_03_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_03_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_03_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_03_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_03 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_03_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_03_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_03_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_03_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_03 :: GTXCLK_DLY_EN [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x200,9)
#define BRPHY0_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_MASK               0x0200
#define BRPHY0_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_BITS               1
#define BRPHY0_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_SHIFT              9

/* BRPHY0_GPHY_CORE :: SHD1C_03 :: GMII_CLK_ALIGN_STRB [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x100,8)
#define BRPHY0_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_MASK         0x0100
#define BRPHY0_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_BITS         1
#define BRPHY0_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_SHIFT        8

/* BRPHY0_GPHY_CORE :: SHD1C_03 :: RXCLK_ALIGN_STRB [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_MASK            0x0080
#define BRPHY0_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_BITS            1
#define BRPHY0_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_SHIFT           7

/* BRPHY0_GPHY_CORE :: SHD1C_03 :: DLY_VALUE [06:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_03_DLY_VALUE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x70,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_03_DLY_VALUE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0x70,4)
#define BRPHY0_GPHY_CORE_SHD1C_03_DLY_VALUE_MASK                   0x0070
#define BRPHY0_GPHY_CORE_SHD1C_03_DLY_VALUE_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_03_DLY_VALUE_BITS                   3
#define BRPHY0_GPHY_CORE_SHD1C_03_DLY_VALUE_SHIFT                  4

/* BRPHY0_GPHY_CORE :: SHD1C_03 :: DLY_LINE_SEL [03:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_03,0xf,0)
#define BRPHY0_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_MASK                0x000f
#define BRPHY0_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_BITS                4
#define BRPHY0_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_SHIFT               0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_04
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_04 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_04_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_04_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_04_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_04_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_04 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_04_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_04_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_04_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_04_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_04 :: SPARE_REG [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_04_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_04_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x200,9)
#define BRPHY0_GPHY_CORE_SHD1C_04_SPARE_REG_MASK                   0x0200
#define BRPHY0_GPHY_CORE_SHD1C_04_SPARE_REG_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_04_SPARE_REG_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_04_SPARE_REG_SHIFT                  9

/* BRPHY0_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_DIS [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x100,8)
#define BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_MASK         0x0100
#define BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_BITS         1
#define BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_SHIFT        8

/* BRPHY0_GPHY_CORE :: SHD1C_04 :: SELECT_TPOUT_RXD [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_MASK            0x0080
#define BRPHY0_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_BITS            1
#define BRPHY0_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_SHIFT           7

/* BRPHY0_GPHY_CORE :: SHD1C_04 :: DISABLE_PHYA2 [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x40,6)
#define BRPHY0_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_MASK               0x0040
#define BRPHY0_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_BITS               1
#define BRPHY0_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_SHIFT              6

/* BRPHY0_GPHY_CORE :: SHD1C_04 :: RBC_TXC_RXC_TRI [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x20,5)
#define BRPHY0_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_MASK             0x0020
#define BRPHY0_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_BITS             1
#define BRPHY0_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_SHIFT            5

/* BRPHY0_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_LIMIT [04:02] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x1c,2,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x1c,2)
#define BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_MASK       0x001c
#define BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_ALIGN      0
#define BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_BITS       3
#define BRPHY0_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_SHIFT      2

/* BRPHY0_GPHY_CORE :: SHD1C_04 :: ENG_DET_ON_INTR_PIN [01:01] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x2,1)
#define BRPHY0_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_MASK         0x0002
#define BRPHY0_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_BITS         1
#define BRPHY0_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_SHIFT        1

/* BRPHY0_GPHY_CORE :: SHD1C_04 :: TESTONBYTE7_0 [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_04,0x1,0)
#define BRPHY0_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_MASK               0x0001
#define BRPHY0_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_BITS               1
#define BRPHY0_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_05
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_05 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_05_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_05_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_05_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_05_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_05_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_05_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_05_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_05_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: DLL_LOCK_EN [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x200,9)
#define BRPHY0_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_MASK                 0x0200
#define BRPHY0_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_BITS                 1
#define BRPHY0_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_SHIFT                9

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: TXC_RXC_DIS [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x100,8)
#define BRPHY0_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_MASK                 0x0100
#define BRPHY0_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_BITS                 1
#define BRPHY0_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_SHIFT                8

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: BT_R_REJECT_FILTER [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_MASK          0x0080
#define BRPHY0_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_BITS          1
#define BRPHY0_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_SHIFT         7

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: TXC_OFF_EN [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x40,6)
#define BRPHY0_GPHY_CORE_SHD1C_05_TXC_OFF_EN_MASK                  0x0040
#define BRPHY0_GPHY_CORE_SHD1C_05_TXC_OFF_EN_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD1C_05_TXC_OFF_EN_BITS                  1
#define BRPHY0_GPHY_CORE_SHD1C_05_TXC_OFF_EN_SHIFT                 6

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: SD_CHANGE_MUX_SEL [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x20,5)
#define BRPHY0_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_MASK           0x0020
#define BRPHY0_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_ALIGN          0
#define BRPHY0_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_BITS           1
#define BRPHY0_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_SHIFT          5

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: LOW_POWER_ENC_DIS [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x10,4)
#define BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_MASK           0x0010
#define BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_ALIGN          0
#define BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_BITS           1
#define BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_SHIFT          4

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: LOW_POWER_BT_DIS [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x8,3)
#define BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_MASK            0x0008
#define BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_BITS            1
#define BRPHY0_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_SHIFT           3

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: SD_DEASSERT_TIMER_LEN [02:02] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x4,2)
#define BRPHY0_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_MASK       0x0004
#define BRPHY0_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_ALIGN      0
#define BRPHY0_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_BITS       1
#define BRPHY0_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_SHIFT      2

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: AUTO_PWRDN_DLL_DIS [01:01] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x2,1)
#define BRPHY0_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_MASK          0x0002
#define BRPHY0_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_BITS          1
#define BRPHY0_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_SHIFT         1

/* BRPHY0_GPHY_CORE :: SHD1C_05 :: CLK125_OUTPUT_EN [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_05,0x1,0)
#define BRPHY0_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_MASK            0x0001
#define BRPHY0_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_BITS            1
#define BRPHY0_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_SHIFT           0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_06
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_06 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_06_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_06_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_06_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_06_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_06 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_06_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_06_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_06_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_06_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_06 :: SPARE_REG [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_06_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_06_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x200,9)
#define BRPHY0_GPHY_CORE_SHD1C_06_SPARE_REG_MASK                   0x0200
#define BRPHY0_GPHY_CORE_SHD1C_06_SPARE_REG_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_06_SPARE_REG_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_06_SPARE_REG_SHIFT                  9

/* BRPHY0_GPHY_CORE :: SHD1C_06 :: TDR_LINK_TIME_OUT [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x100,8)
#define BRPHY0_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_MASK           0x0100
#define BRPHY0_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_ALIGN          0
#define BRPHY0_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_BITS           1
#define BRPHY0_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_SHIFT          8

/* BRPHY0_GPHY_CORE :: SHD1C_06 :: TEST_PULSE_SIZE [07:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0xe0,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0xe0,5)
#define BRPHY0_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_MASK             0x00e0
#define BRPHY0_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_BITS             3
#define BRPHY0_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_SHIFT            5

/* BRPHY0_GPHY_CORE :: SHD1C_06 :: TX_CHANNEL_SEL [04:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x18,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x18,3)
#define BRPHY0_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_MASK              0x0018
#define BRPHY0_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_BITS              2
#define BRPHY0_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_SHIFT             3

/* BRPHY0_GPHY_CORE :: SHD1C_06 :: RX_CHANNEL_SEL [02:01] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x6,1,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x6,1)
#define BRPHY0_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_MASK              0x0006
#define BRPHY0_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_BITS              2
#define BRPHY0_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_SHIFT             1

/* BRPHY0_GPHY_CORE :: SHD1C_06 :: TDR_START [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_06_TDR_START(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_06_TDR_START(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_06,0x1,0)
#define BRPHY0_GPHY_CORE_SHD1C_06_TDR_START_MASK                   0x0001
#define BRPHY0_GPHY_CORE_SHD1C_06_TDR_START_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_06_TDR_START_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_06_TDR_START_SHIFT                  0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_07
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_07 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_07_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_07_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_07_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_07_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_07_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_07_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_07_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_07_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: SPARE_REG [09:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x300,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x300,8)
#define BRPHY0_GPHY_CORE_SHD1C_07_SPARE_REG_MASK                   0x0300
#define BRPHY0_GPHY_CORE_SHD1C_07_SPARE_REG_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_07_SPARE_REG_BITS                   2
#define BRPHY0_GPHY_CORE_SHD1C_07_SPARE_REG_SHIFT                  8

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_MASK                0x0080
#define BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_BITS                1
#define BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_SHIFT               7

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS_CLEAR [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x40,6)
#define BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_MASK          0x0040
#define BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_BITS          1
#define BRPHY0_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_SHIFT         6

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: FASTTIMERS [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_FASTTIMERS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_FASTTIMERS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x20,5)
#define BRPHY0_GPHY_CORE_SHD1C_07_FASTTIMERS_MASK                  0x0020
#define BRPHY0_GPHY_CORE_SHD1C_07_FASTTIMERS_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD1C_07_FASTTIMERS_BITS                  1
#define BRPHY0_GPHY_CORE_SHD1C_07_FASTTIMERS_SHIFT                 5

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: FEXT [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_FEXT(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_FEXT(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x10,4)
#define BRPHY0_GPHY_CORE_SHD1C_07_FEXT_MASK                        0x0010
#define BRPHY0_GPHY_CORE_SHD1C_07_FEXT_ALIGN                       0
#define BRPHY0_GPHY_CORE_SHD1C_07_FEXT_BITS                        1
#define BRPHY0_GPHY_CORE_SHD1C_07_FEXT_SHIFT                       4

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: MASTER [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_MASTER(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_MASTER(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x8,3)
#define BRPHY0_GPHY_CORE_SHD1C_07_MASTER_MASK                      0x0008
#define BRPHY0_GPHY_CORE_SHD1C_07_MASTER_ALIGN                     0
#define BRPHY0_GPHY_CORE_SHD1C_07_MASTER_BITS                      1
#define BRPHY0_GPHY_CORE_SHD1C_07_MASTER_SHIFT                     3

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: EXT_PHY_NO_AUTONEG [02:02] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x4,2)
#define BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_MASK          0x0004
#define BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_BITS          1
#define BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_SHIFT         2

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: EXT_PHY [01:01] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x2,1)
#define BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_MASK                     0x0002
#define BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_ALIGN                    0
#define BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_BITS                     1
#define BRPHY0_GPHY_CORE_SHD1C_07_EXT_PHY_SHIFT                    1

/* BRPHY0_GPHY_CORE :: SHD1C_07 :: TDR_EN [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_07_TDR_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_07_TDR_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_07,0x1,0)
#define BRPHY0_GPHY_CORE_SHD1C_07_TDR_EN_MASK                      0x0001
#define BRPHY0_GPHY_CORE_SHD1C_07_TDR_EN_ALIGN                     0
#define BRPHY0_GPHY_CORE_SHD1C_07_TDR_EN_BITS                      1
#define BRPHY0_GPHY_CORE_SHD1C_07_TDR_EN_SHIFT                     0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_08
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_08 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_08_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_08_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_08_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_08_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: reserved1 [09:09] */
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED1_MASK                   0x0200
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED1_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED1_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED1_SHIFT                  9

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: SLAVE_N [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_08_SLAVE_N(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_08_SLAVE_N(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x100,8)
#define BRPHY0_GPHY_CORE_SHD1C_08_SLAVE_N_MASK                     0x0100
#define BRPHY0_GPHY_CORE_SHD1C_08_SLAVE_N_ALIGN                    0
#define BRPHY0_GPHY_CORE_SHD1C_08_SLAVE_N_BITS                     1
#define BRPHY0_GPHY_CORE_SHD1C_08_SLAVE_N_SHIFT                    8

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: FDXLED_N [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_08_FDXLED_N(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_08_FDXLED_N(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_08_FDXLED_N_MASK                    0x0080
#define BRPHY0_GPHY_CORE_SHD1C_08_FDXLED_N_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD1C_08_FDXLED_N_BITS                    1
#define BRPHY0_GPHY_CORE_SHD1C_08_FDXLED_N_SHIFT                   7

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: INTR_N [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_08_INTR_N(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_08_INTR_N(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x40,6)
#define BRPHY0_GPHY_CORE_SHD1C_08_INTR_N_MASK                      0x0040
#define BRPHY0_GPHY_CORE_SHD1C_08_INTR_N_ALIGN                     0
#define BRPHY0_GPHY_CORE_SHD1C_08_INTR_N_BITS                      1
#define BRPHY0_GPHY_CORE_SHD1C_08_INTR_N_SHIFT                     6

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: reserved2 [05:05] */
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED2_MASK                   0x0020
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED2_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED2_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_08_RESERVED2_SHIFT                  5

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: LINKSPD_N [04:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_08_LINKSPD_N(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x18,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_08_LINKSPD_N(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x18,3)
#define BRPHY0_GPHY_CORE_SHD1C_08_LINKSPD_N_MASK                   0x0018
#define BRPHY0_GPHY_CORE_SHD1C_08_LINKSPD_N_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_08_LINKSPD_N_BITS                   2
#define BRPHY0_GPHY_CORE_SHD1C_08_LINKSPD_N_SHIFT                  3

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: TRANSMIT_LED [02:02] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x4,2)
#define BRPHY0_GPHY_CORE_SHD1C_08_TRANSMIT_LED_MASK                0x0004
#define BRPHY0_GPHY_CORE_SHD1C_08_TRANSMIT_LED_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD1C_08_TRANSMIT_LED_BITS                1
#define BRPHY0_GPHY_CORE_SHD1C_08_TRANSMIT_LED_SHIFT               2

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: RECEIVE_LED [01:01] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x2,1)
#define BRPHY0_GPHY_CORE_SHD1C_08_RECEIVE_LED_MASK                 0x0002
#define BRPHY0_GPHY_CORE_SHD1C_08_RECEIVE_LED_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD1C_08_RECEIVE_LED_BITS                 1
#define BRPHY0_GPHY_CORE_SHD1C_08_RECEIVE_LED_SHIFT                1

/* BRPHY0_GPHY_CORE :: SHD1C_08 :: QUALITY_LED [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_08_QUALITY_LED(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_08_QUALITY_LED(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_08,0x1,0)
#define BRPHY0_GPHY_CORE_SHD1C_08_QUALITY_LED_MASK                 0x0001
#define BRPHY0_GPHY_CORE_SHD1C_08_QUALITY_LED_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD1C_08_QUALITY_LED_BITS                 1
#define BRPHY0_GPHY_CORE_SHD1C_08_QUALITY_LED_SHIFT                0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_09
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_09 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_09_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_09_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_09_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_09_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_09_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_09_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_09_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_09_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: COL_BLINK [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_COL_BLINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_COL_BLINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x200,9)
#define BRPHY0_GPHY_CORE_SHD1C_09_COL_BLINK_MASK                   0x0200
#define BRPHY0_GPHY_CORE_SHD1C_09_COL_BLINK_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_09_COL_BLINK_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_09_COL_BLINK_SHIFT                  9

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: ACT_LINK_MSB [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x100,8)
#define BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_MASK                0x0100
#define BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_BITS                1
#define BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_SHIFT               8

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: SPARE_REG [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_09_SPARE_REG_MASK                   0x0080
#define BRPHY0_GPHY_CORE_SHD1C_09_SPARE_REG_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_09_SPARE_REG_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_09_SPARE_REG_SHIFT                  7

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: EXT_SERDES_INUSE [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x40,6)
#define BRPHY0_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_MASK            0x0040
#define BRPHY0_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_BITS            1
#define BRPHY0_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_SHIFT           6

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: OV_GBIC_LED [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x20,5)
#define BRPHY0_GPHY_CORE_SHD1C_09_OV_GBIC_LED_MASK                 0x0020
#define BRPHY0_GPHY_CORE_SHD1C_09_OV_GBIC_LED_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD1C_09_OV_GBIC_LED_BITS                 1
#define BRPHY0_GPHY_CORE_SHD1C_09_OV_GBIC_LED_SHIFT                5

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: ACT_LINK_LSB [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x10,4)
#define BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_MASK                0x0010
#define BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_BITS                1
#define BRPHY0_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_SHIFT               4

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: ACTIVITY_LED_EN [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x8,3)
#define BRPHY0_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_MASK             0x0008
#define BRPHY0_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_BITS             1
#define BRPHY0_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_SHIFT            3

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: RMT_FAULT_LED_EN [02:02] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x4,2)
#define BRPHY0_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_MASK            0x0004
#define BRPHY0_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_BITS            1
#define BRPHY0_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_SHIFT           2

/* BRPHY0_GPHY_CORE :: SHD1C_09 :: LINK_UTIL_LED_SEL [01:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x3,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_09,0x3,0)
#define BRPHY0_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_MASK           0x0003
#define BRPHY0_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_ALIGN          0
#define BRPHY0_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_BITS           2
#define BRPHY0_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_SHIFT          0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_0A
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_0A :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_0A_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_0A_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0A_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_0A_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_0A :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_0A_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_0A_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0A_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_0A_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_0A :: reserved1 [09:09] */
#define BRPHY0_GPHY_CORE_SHD1C_0A_RESERVED1_MASK                   0x0200
#define BRPHY0_GPHY_CORE_SHD1C_0A_RESERVED1_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0A_RESERVED1_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_0A_RESERVED1_SHIFT                  9

/* BRPHY0_GPHY_CORE :: SHD1C_0A :: APD_SINGLELP_ENABLE [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x100,8)
#define BRPHY0_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_MASK         0x0100
#define BRPHY0_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_BITS         1
#define BRPHY0_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_SHIFT        8

/* BRPHY0_GPHY_CORE :: SHD1C_0A :: LOWPWR136_ENC_EN [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_MASK            0x0080
#define BRPHY0_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_BITS            1
#define BRPHY0_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_SHIFT           7

/* BRPHY0_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_IGNORE_AUTONEG [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x40,6)
#define BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_MASK   0x0040
#define BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_ALIGN  0
#define BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_BITS   1
#define BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_SHIFT  6

/* BRPHY0_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_EN [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x20,5)
#define BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_MASK               0x0020
#define BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_BITS               1
#define BRPHY0_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_SHIFT              5

/* BRPHY0_GPHY_CORE :: SHD1C_0A :: SLEEP_TIMER_SEL [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0x10,4)
#define BRPHY0_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_MASK             0x0010
#define BRPHY0_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_BITS             1
#define BRPHY0_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_SHIFT            4

/* BRPHY0_GPHY_CORE :: SHD1C_0A :: WAKE_UP_TIMER_SEL [03:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0A,0xf,0)
#define BRPHY0_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_MASK           0x000f
#define BRPHY0_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_ALIGN          0
#define BRPHY0_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_BITS           4
#define BRPHY0_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_SHIFT          0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_0B
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_0B :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_0B_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_0B_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0B_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_0B_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_0B :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0B,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0B,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_0B_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_0B_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0B_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_0B_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_0B :: reserved1 [09:08] */
#define BRPHY0_GPHY_CORE_SHD1C_0B_RESERVED1_MASK                   0x0300
#define BRPHY0_GPHY_CORE_SHD1C_0B_RESERVED1_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0B_RESERVED1_BITS                   2
#define BRPHY0_GPHY_CORE_SHD1C_0B_RESERVED1_SHIFT                  8

/* BRPHY0_GPHY_CORE :: SHD1C_0B :: SPARE_CTL4 [07:01] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0B,0xfe,1,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0B,0xfe,1)
#define BRPHY0_GPHY_CORE_SHD1C_0B_SPARE_CTL4_MASK                  0x00fe
#define BRPHY0_GPHY_CORE_SHD1C_0B_SPARE_CTL4_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD1C_0B_SPARE_CTL4_BITS                  7
#define BRPHY0_GPHY_CORE_SHD1C_0B_SPARE_CTL4_SHIFT                 1

/* BRPHY0_GPHY_CORE :: SHD1C_0B :: dis_cl45 [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0B_dis_cl45(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0B,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0B_dis_cl45(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0B,0x1,0)
#define BRPHY0_GPHY_CORE_SHD1C_0B_DIS_CL45_MASK                    0x0001
#define BRPHY0_GPHY_CORE_SHD1C_0B_DIS_CL45_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD1C_0B_DIS_CL45_BITS                    1
#define BRPHY0_GPHY_CORE_SHD1C_0B_DIS_CL45_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_0D
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_0D :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_0D_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_0D_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0D_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_0D_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_0D :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0D,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0D,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_0D_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_0D_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0D_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_0D_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_0D :: reserved1 [09:08] */
#define BRPHY0_GPHY_CORE_SHD1C_0D_RESERVED1_MASK                   0x0300
#define BRPHY0_GPHY_CORE_SHD1C_0D_RESERVED1_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0D_RESERVED1_BITS                   2
#define BRPHY0_GPHY_CORE_SHD1C_0D_RESERVED1_SHIFT                  8

/* BRPHY0_GPHY_CORE :: SHD1C_0D :: LED2_SEL [07:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0D_LED2_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0D,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0D_LED2_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0D,0xf0,4)
#define BRPHY0_GPHY_CORE_SHD1C_0D_LED2_SEL_MASK                    0x00f0
#define BRPHY0_GPHY_CORE_SHD1C_0D_LED2_SEL_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD1C_0D_LED2_SEL_BITS                    4
#define BRPHY0_GPHY_CORE_SHD1C_0D_LED2_SEL_SHIFT                   4

/* BRPHY0_GPHY_CORE :: SHD1C_0D :: LED1_SEL [03:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0D_LED1_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0D,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0D_LED1_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0D,0xf,0)
#define BRPHY0_GPHY_CORE_SHD1C_0D_LED1_SEL_MASK                    0x000f
#define BRPHY0_GPHY_CORE_SHD1C_0D_LED1_SEL_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD1C_0D_LED1_SEL_BITS                    4
#define BRPHY0_GPHY_CORE_SHD1C_0D_LED1_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_0E
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_0E :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_0E_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_0E_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0E_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_0E_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_0E :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0E,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0E,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_0E_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_0E_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0E_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_0E_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_0E :: reserved1 [09:08] */
#define BRPHY0_GPHY_CORE_SHD1C_0E_RESERVED1_MASK                   0x0300
#define BRPHY0_GPHY_CORE_SHD1C_0E_RESERVED1_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0E_RESERVED1_BITS                   2
#define BRPHY0_GPHY_CORE_SHD1C_0E_RESERVED1_SHIFT                  8

/* BRPHY0_GPHY_CORE :: SHD1C_0E :: LED4_SEL [07:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0E_LED4_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0E,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0E_LED4_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0E,0xf0,4)
#define BRPHY0_GPHY_CORE_SHD1C_0E_LED4_SEL_MASK                    0x00f0
#define BRPHY0_GPHY_CORE_SHD1C_0E_LED4_SEL_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD1C_0E_LED4_SEL_BITS                    4
#define BRPHY0_GPHY_CORE_SHD1C_0E_LED4_SEL_SHIFT                   4

/* BRPHY0_GPHY_CORE :: SHD1C_0E :: LED3_SEL [03:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0E_LED3_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0E,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0E_LED3_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0E,0xf,0)
#define BRPHY0_GPHY_CORE_SHD1C_0E_LED3_SEL_MASK                    0x000f
#define BRPHY0_GPHY_CORE_SHD1C_0E_LED3_SEL_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD1C_0E_LED3_SEL_BITS                    4
#define BRPHY0_GPHY_CORE_SHD1C_0E_LED3_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_0F
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_0F :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_0F_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_0F_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0F_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_0F_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_0F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0F,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0F,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_0F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_0F_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0F_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_0F_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_0F :: reserved1 [09:04] */
#define BRPHY0_GPHY_CORE_SHD1C_0F_RESERVED1_MASK                   0x03f0
#define BRPHY0_GPHY_CORE_SHD1C_0F_RESERVED1_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_0F_RESERVED1_BITS                   6
#define BRPHY0_GPHY_CORE_SHD1C_0F_RESERVED1_SHIFT                  4

/* BRPHY0_GPHY_CORE :: SHD1C_0F :: CURRENT_MODE_LED_EN [03:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_0F,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_0F,0xf,0)
#define BRPHY0_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_MASK         0x000f
#define BRPHY0_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_BITS         4
#define BRPHY0_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_SHIFT        0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_10
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_10 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_10_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_10_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_10_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_10_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_10 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_10_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_10_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_10_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_10_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_10 :: reserved1 [09:08] */
#define BRPHY0_GPHY_CORE_SHD1C_10_RESERVED1_MASK                   0x0300
#define BRPHY0_GPHY_CORE_SHD1C_10_RESERVED1_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_10_RESERVED1_BITS                   2
#define BRPHY0_GPHY_CORE_SHD1C_10_RESERVED1_SHIFT                  8

/* BRPHY0_GPHY_CORE :: SHD1C_10 :: SPARE_REG [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_10_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_10_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_10_SPARE_REG_MASK                   0x0080
#define BRPHY0_GPHY_CORE_SHD1C_10_SPARE_REG_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_10_SPARE_REG_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_10_SPARE_REG_SHIFT                  7

/* BRPHY0_GPHY_CORE :: SHD1C_10 :: USE_ALT_LINKFLT [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x40,6)
#define BRPHY0_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_MASK             0x0040
#define BRPHY0_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_BITS             1
#define BRPHY0_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_SHIFT            6

/* BRPHY0_GPHY_CORE :: SHD1C_10 :: VISIBLE_BLINK [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x20,5)
#define BRPHY0_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_MASK               0x0020
#define BRPHY0_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_BITS               1
#define BRPHY0_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_SHIFT              5

/* BRPHY0_GPHY_CORE :: SHD1C_10 :: ENHANCED_PWR [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0x10,4)
#define BRPHY0_GPHY_CORE_SHD1C_10_ENHANCED_PWR_MASK                0x0010
#define BRPHY0_GPHY_CORE_SHD1C_10_ENHANCED_PWR_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD1C_10_ENHANCED_PWR_BITS                1
#define BRPHY0_GPHY_CORE_SHD1C_10_ENHANCED_PWR_SHIFT               4

/* BRPHY0_GPHY_CORE :: SHD1C_10 :: DISCONNECT_TIMER_VALUE [03:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_10,0xf,0)
#define BRPHY0_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_MASK      0x000f
#define BRPHY0_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_ALIGN     0
#define BRPHY0_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_BITS      4
#define BRPHY0_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_SHIFT     0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD1C_1F
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD1C_1F :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD1C_1F_RESERVED0_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD1C_1F_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_1F_RESERVED0_BITS                   1
#define BRPHY0_GPHY_CORE_SHD1C_1F_RESERVED0_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD1C_1F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY0_GPHY_CORE_SHD1C_1F_SHD1C_SEL_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD1C_1F_SHD1C_SEL_BITS                   5
#define BRPHY0_GPHY_CORE_SHD1C_1F_SHD1C_SEL_SHIFT                  10

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: DUAL_SERDES_CAPABLE [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x200,9)
#define BRPHY0_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_MASK         0x0200
#define BRPHY0_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_BITS         1
#define BRPHY0_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_SHIFT        9

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: MODE_SEL_CHANGE [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x100,8)
#define BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_MASK             0x0100
#define BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_BITS             1
#define BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_SHIFT            8

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: COPPER_LINK [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x80,7)
#define BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_LINK_MASK                 0x0080
#define BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_LINK_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_LINK_BITS                 1
#define BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_LINK_SHIFT                7

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: SERDES_LINK [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x40,6)
#define BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_LINK_MASK                 0x0040
#define BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_LINK_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_LINK_BITS                 1
#define BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_LINK_SHIFT                6

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: COPPER_ENG_DET [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x20,5)
#define BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_MASK              0x0020
#define BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_BITS              1
#define BRPHY0_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_SHIFT             5

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: FIBER_SIGNAL_DET [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x10,4)
#define BRPHY0_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_MASK            0x0010
#define BRPHY0_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_BITS            1
#define BRPHY0_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_SHIFT           4

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: SERDES_CAPABLE [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x8,3)
#define BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_MASK              0x0008
#define BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_BITS              1
#define BRPHY0_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_SHIFT             3

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: MODE_SEL [02:01] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x6,1,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x6,1)
#define BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_MASK                    0x0006
#define BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_BITS                    2
#define BRPHY0_GPHY_CORE_SHD1C_1F_MODE_SEL_SHIFT                   1

/* BRPHY0_GPHY_CORE :: SHD1C_1F :: REG_1000X_EN [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD1C_1F,0x1,0)
#define BRPHY0_GPHY_CORE_SHD1C_1F_REG_1000X_EN_MASK                0x0001
#define BRPHY0_GPHY_CORE_SHD1C_1F_REG_1000X_EN_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD1C_1F_REG_1000X_EN_BITS                1
#define BRPHY0_GPHY_CORE_SHD1C_1F_REG_1000X_EN_SHIFT               0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD18_000
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD18_000 :: EXT_LPBK [15:15] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_EXT_LPBK(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_EXT_LPBK(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x8000,15)
#define BRPHY0_GPHY_CORE_SHD18_000_EXT_LPBK_MASK                   0x8000
#define BRPHY0_GPHY_CORE_SHD18_000_EXT_LPBK_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD18_000_EXT_LPBK_BITS                   1
#define BRPHY0_GPHY_CORE_SHD18_000_EXT_LPBK_SHIFT                  15

/* BRPHY0_GPHY_CORE :: SHD18_000 :: EXT_PKT_LEN [14:14] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x4000,14)
#define BRPHY0_GPHY_CORE_SHD18_000_EXT_PKT_LEN_MASK                0x4000
#define BRPHY0_GPHY_CORE_SHD18_000_EXT_PKT_LEN_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_000_EXT_PKT_LEN_BITS                1
#define BRPHY0_GPHY_CORE_SHD18_000_EXT_PKT_LEN_SHIFT               14

/* BRPHY0_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_1000T [13:12] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x3000,12,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x3000,12)
#define BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_MASK         0x3000
#define BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_BITS         2
#define BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_SHIFT        12

/* BRPHY0_GPHY_CORE :: SHD18_000 :: SM_DSP_CLK_EN [11:11] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x800,11)
#define BRPHY0_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_MASK              0x0800
#define BRPHY0_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_BITS              1
#define BRPHY0_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_SHIFT             11

/* BRPHY0_GPHY_CORE :: SHD18_000 :: TX_6DB_CODING [10:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x400,10)
#define BRPHY0_GPHY_CORE_SHD18_000_TX_6DB_CODING_MASK              0x0400
#define BRPHY0_GPHY_CORE_SHD18_000_TX_6DB_CODING_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD18_000_TX_6DB_CODING_BITS              1
#define BRPHY0_GPHY_CORE_SHD18_000_TX_6DB_CODING_SHIFT             10

/* BRPHY0_GPHY_CORE :: SHD18_000 :: RCV_SLICING [09:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_RCV_SLICING(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x300,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_RCV_SLICING(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x300,8)
#define BRPHY0_GPHY_CORE_SHD18_000_RCV_SLICING_MASK                0x0300
#define BRPHY0_GPHY_CORE_SHD18_000_RCV_SLICING_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_000_RCV_SLICING_BITS                2
#define BRPHY0_GPHY_CORE_SHD18_000_RCV_SLICING_SHIFT               8

/* BRPHY0_GPHY_CORE :: SHD18_000 :: PRF_DIS [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_PRF_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_PRF_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x80,7)
#define BRPHY0_GPHY_CORE_SHD18_000_PRF_DIS_MASK                    0x0080
#define BRPHY0_GPHY_CORE_SHD18_000_PRF_DIS_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD18_000_PRF_DIS_BITS                    1
#define BRPHY0_GPHY_CORE_SHD18_000_PRF_DIS_SHIFT                   7

/* BRPHY0_GPHY_CORE :: SHD18_000 :: INVERSE_PRF_DIS [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x40,6)
#define BRPHY0_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_MASK            0x0040
#define BRPHY0_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_SHIFT           6

/* BRPHY0_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_100TX [05:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x30,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x30,4)
#define BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_MASK         0x0030
#define BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_BITS         2
#define BRPHY0_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_SHIFT        4

/* BRPHY0_GPHY_CORE :: SHD18_000 :: DIAGNOSTIC [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x8,3)
#define BRPHY0_GPHY_CORE_SHD18_000_DIAGNOSTIC_MASK                 0x0008
#define BRPHY0_GPHY_CORE_SHD18_000_DIAGNOSTIC_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD18_000_DIAGNOSTIC_BITS                 1
#define BRPHY0_GPHY_CORE_SHD18_000_DIAGNOSTIC_SHIFT                3

/* BRPHY0_GPHY_CORE :: SHD18_000 :: SHD18_SEL [02:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_000_SHD18_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_000_SHD18_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_000,0x7,0)
#define BRPHY0_GPHY_CORE_SHD18_000_SHD18_SEL_MASK                  0x0007
#define BRPHY0_GPHY_CORE_SHD18_000_SHD18_SEL_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_000_SHD18_SEL_BITS                  3
#define BRPHY0_GPHY_CORE_SHD18_000_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD18_001
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD18_001 :: MANCHESTER_CODE_ERR [15:15] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x8000,15)
#define BRPHY0_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_MASK        0x8000
#define BRPHY0_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_ALIGN       0
#define BRPHY0_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_BITS        1
#define BRPHY0_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_SHIFT       15

/* BRPHY0_GPHY_CORE :: SHD18_001 :: EOF_ERR [14:14] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_EOF_ERR(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_EOF_ERR(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x4000,14)
#define BRPHY0_GPHY_CORE_SHD18_001_EOF_ERR_MASK                    0x4000
#define BRPHY0_GPHY_CORE_SHD18_001_EOF_ERR_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD18_001_EOF_ERR_BITS                    1
#define BRPHY0_GPHY_CORE_SHD18_001_EOF_ERR_SHIFT                   14

/* BRPHY0_GPHY_CORE :: SHD18_001 :: POLARITY_ERR [13:13] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_POLARITY_ERR(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_POLARITY_ERR(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x2000,13)
#define BRPHY0_GPHY_CORE_SHD18_001_POLARITY_ERR_MASK               0x2000
#define BRPHY0_GPHY_CORE_SHD18_001_POLARITY_ERR_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD18_001_POLARITY_ERR_BITS               1
#define BRPHY0_GPHY_CORE_SHD18_001_POLARITY_ERR_SHIFT              13

/* BRPHY0_GPHY_CORE :: SHD18_001 :: BLOCK_RXDV_EXT [12:12] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x1000,12)
#define BRPHY0_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_MASK             0x1000
#define BRPHY0_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_BITS             1
#define BRPHY0_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_SHIFT            12

/* BRPHY0_GPHY_CORE :: SHD18_001 :: BT_TXC_INV [11:11] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_BT_TXC_INV(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_BT_TXC_INV(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x800,11)
#define BRPHY0_GPHY_CORE_SHD18_001_BT_TXC_INV_MASK                 0x0800
#define BRPHY0_GPHY_CORE_SHD18_001_BT_TXC_INV_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD18_001_BT_TXC_INV_BITS                 1
#define BRPHY0_GPHY_CORE_SHD18_001_BT_TXC_INV_SHIFT                11

/* BRPHY0_GPHY_CORE :: SHD18_001 :: CLASS_AB_DRIVER_SEL [10:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x400,10)
#define BRPHY0_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_MASK        0x0400
#define BRPHY0_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_ALIGN       0
#define BRPHY0_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_BITS        1
#define BRPHY0_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_SHIFT       10

/* BRPHY0_GPHY_CORE :: SHD18_001 :: JABBER_DIS [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_JABBER_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_JABBER_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x200,9)
#define BRPHY0_GPHY_CORE_SHD18_001_JABBER_DIS_MASK                 0x0200
#define BRPHY0_GPHY_CORE_SHD18_001_JABBER_DIS_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD18_001_JABBER_DIS_BITS                 1
#define BRPHY0_GPHY_CORE_SHD18_001_JABBER_DIS_SHIFT                9

/* BRPHY0_GPHY_CORE :: SHD18_001 :: BT_SIG_DET_AUTOSWITCH [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x100,8)
#define BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_MASK      0x0100
#define BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_ALIGN     0
#define BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_BITS      1
#define BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_SHIFT     8

/* BRPHY0_GPHY_CORE :: SHD18_001 :: BT_SIG_DETECT_THD [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x80,7)
#define BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_MASK          0x0080
#define BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_BITS          1
#define BRPHY0_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_SHIFT         7

/* BRPHY0_GPHY_CORE :: SHD18_001 :: BT_ECHO [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_BT_ECHO(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_BT_ECHO(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x40,6)
#define BRPHY0_GPHY_CORE_SHD18_001_BT_ECHO_MASK                    0x0040
#define BRPHY0_GPHY_CORE_SHD18_001_BT_ECHO_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD18_001_BT_ECHO_BITS                    1
#define BRPHY0_GPHY_CORE_SHD18_001_BT_ECHO_SHIFT                   6

/* BRPHY0_GPHY_CORE :: SHD18_001 :: SQE_EN [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_SQE_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_SQE_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x20,5)
#define BRPHY0_GPHY_CORE_SHD18_001_SQE_EN_MASK                     0x0020
#define BRPHY0_GPHY_CORE_SHD18_001_SQE_EN_ALIGN                    0
#define BRPHY0_GPHY_CORE_SHD18_001_SQE_EN_BITS                     1
#define BRPHY0_GPHY_CORE_SHD18_001_SQE_EN_SHIFT                    5

/* BRPHY0_GPHY_CORE :: SHD18_001 :: BT_NO_DRIBBLE [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x10,4)
#define BRPHY0_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_MASK              0x0010
#define BRPHY0_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_BITS              1
#define BRPHY0_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_SHIFT             4

/* BRPHY0_GPHY_CORE :: SHD18_001 :: BT_POL_ERR_CNT_MAX [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x8,3)
#define BRPHY0_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_MASK         0x0008
#define BRPHY0_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_BITS         1
#define BRPHY0_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_SHIFT        3

/* BRPHY0_GPHY_CORE :: SHD18_001 :: SHD18_SEL [02:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_001_SHD18_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_001_SHD18_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_001,0x7,0)
#define BRPHY0_GPHY_CORE_SHD18_001_SHD18_SEL_MASK                  0x0007
#define BRPHY0_GPHY_CORE_SHD18_001_SHD18_SEL_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_001_SHD18_SEL_BITS                  3
#define BRPHY0_GPHY_CORE_SHD18_001_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD18_010
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD18_010 :: SPARE_REG_3 [15:11] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_3(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0xf800,11,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_3(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0xf800,11)
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_3_MASK                0xf800
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_3_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_3_BITS                5
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_3_SHIFT               11

/* BRPHY0_GPHY_CORE :: SHD18_010 :: SPARE_REG_2 [10:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_2(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x7c0,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_2(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x7c0,6)
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_2_MASK                0x07c0
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_2_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_2_BITS                5
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_2_SHIFT               6

/* BRPHY0_GPHY_CORE :: SHD18_010 :: SUPER_ISOLATE [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x20,5)
#define BRPHY0_GPHY_CORE_SHD18_010_SUPER_ISOLATE_MASK              0x0020
#define BRPHY0_GPHY_CORE_SHD18_010_SUPER_ISOLATE_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD18_010_SUPER_ISOLATE_BITS              1
#define BRPHY0_GPHY_CORE_SHD18_010_SUPER_ISOLATE_SHIFT             5

/* BRPHY0_GPHY_CORE :: SHD18_010 :: SPARE_REG_1 [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_1(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_1(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x10,4)
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_1_MASK                0x0010
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_1_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_1_BITS                1
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_1_SHIFT               4

/* BRPHY0_GPHY_CORE :: SHD18_010 :: SPARE_REG_0 [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_0(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_0(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x8,3)
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_0_MASK                0x0008
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_0_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_0_BITS                1
#define BRPHY0_GPHY_CORE_SHD18_010_SPARE_REG_0_SHIFT               3

/* BRPHY0_GPHY_CORE :: SHD18_010 :: SHD18_SEL [02:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_010_SHD18_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_010_SHD18_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_010,0x7,0)
#define BRPHY0_GPHY_CORE_SHD18_010_SHD18_SEL_MASK                  0x0007
#define BRPHY0_GPHY_CORE_SHD18_010_SHD18_SEL_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_010_SHD18_SEL_BITS                  3
#define BRPHY0_GPHY_CORE_SHD18_010_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD18_011
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD18_011 :: IP_PHONE_DETECT [15:15] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x8000,15)
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_MASK            0x8000
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_SHIFT           15

/* BRPHY0_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_CNTR [14:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x7c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x7c00,10)
#define BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_MASK          0x7c00
#define BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_BITS          5
#define BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_SHIFT         10

/* BRPHY0_GPHY_CORE :: SHD18_011 :: ALT_RANDOM_SEED [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x200,9)
#define BRPHY0_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_MASK            0x0200
#define BRPHY0_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_SHIFT           9

/* BRPHY0_GPHY_CORE :: SHD18_011 :: RESTART_AUTONEG [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x100,8)
#define BRPHY0_GPHY_CORE_SHD18_011_RESTART_AUTONEG_MASK            0x0100
#define BRPHY0_GPHY_CORE_SHD18_011_RESTART_AUTONEG_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_011_RESTART_AUTONEG_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_011_RESTART_AUTONEG_SHIFT           8

/* BRPHY0_GPHY_CORE :: SHD18_011 :: IP_PHONE_WINDOW [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x80,7)
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_MASK            0x0080
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_SHIFT           7

/* BRPHY0_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_EN [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x40,6)
#define BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_MASK            0x0040
#define BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_SHIFT           6

/* BRPHY0_GPHY_CORE :: SHD18_011 :: IP_PHONE_DET_EN [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x20,5)
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_MASK            0x0020
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_SHIFT           5

/* BRPHY0_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_DIS [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x10,4)
#define BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_MASK      0x0010
#define BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_ALIGN     0
#define BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_BITS      1
#define BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_SHIFT     4

/* BRPHY0_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_SW [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x8,3)
#define BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_MASK       0x0008
#define BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_ALIGN      0
#define BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_BITS       1
#define BRPHY0_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_SHIFT      3

/* BRPHY0_GPHY_CORE :: SHD18_011 :: SHD18_SEL [02:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_011_SHD18_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_011_SHD18_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_011,0x7,0)
#define BRPHY0_GPHY_CORE_SHD18_011_SHD18_SEL_MASK                  0x0007
#define BRPHY0_GPHY_CORE_SHD18_011_SHD18_SEL_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_011_SHD18_SEL_BITS                  3
#define BRPHY0_GPHY_CORE_SHD18_011_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD18_100
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD18_100 :: RMT_LPBK_EN [15:15] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x8000,15)
#define BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_EN_MASK                0x8000
#define BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_EN_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_EN_BITS                1
#define BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_EN_SHIFT               15

/* BRPHY0_GPHY_CORE :: SHD18_100 :: TDK_FIX_EN [14:14] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x4000,14)
#define BRPHY0_GPHY_CORE_SHD18_100_TDK_FIX_EN_MASK                 0x4000
#define BRPHY0_GPHY_CORE_SHD18_100_TDK_FIX_EN_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD18_100_TDK_FIX_EN_BITS                 1
#define BRPHY0_GPHY_CORE_SHD18_100_TDK_FIX_EN_SHIFT                14

/* BRPHY0_GPHY_CORE :: SHD18_100 :: BT_DLL_BYPASS_CLK [13:13] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x2000,13)
#define BRPHY0_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_MASK          0x2000
#define BRPHY0_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_BITS          1
#define BRPHY0_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_SHIFT         13

/* BRPHY0_GPHY_CORE :: SHD18_100 :: BLOCK_10BT_RESTART_AUTONEG [12:12] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x1000,12)
#define BRPHY0_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_MASK 0x1000
#define BRPHY0_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_ALIGN 0
#define BRPHY0_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_BITS 1
#define BRPHY0_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_SHIFT 12

/* BRPHY0_GPHY_CORE :: SHD18_100 :: RMT_LPBK_TRISTATE [11:11] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x800,11)
#define BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_MASK          0x0800
#define BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_BITS          1
#define BRPHY0_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_SHIFT         11

/* BRPHY0_GPHY_CORE :: SHD18_100 :: BT_WAKEUP [10:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_BT_WAKEUP(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_BT_WAKEUP(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x400,10)
#define BRPHY0_GPHY_CORE_SHD18_100_BT_WAKEUP_MASK                  0x0400
#define BRPHY0_GPHY_CORE_SHD18_100_BT_WAKEUP_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_100_BT_WAKEUP_BITS                  1
#define BRPHY0_GPHY_CORE_SHD18_100_BT_WAKEUP_SHIFT                 10

/* BRPHY0_GPHY_CORE :: SHD18_100 :: BT_POLARITY_BYPASS [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x200,9)
#define BRPHY0_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_MASK         0x0200
#define BRPHY0_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_ALIGN        0
#define BRPHY0_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_BITS         1
#define BRPHY0_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_SHIFT        9

/* BRPHY0_GPHY_CORE :: SHD18_100 :: BT_IDLE_BYPASS [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x100,8)
#define BRPHY0_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_MASK             0x0100
#define BRPHY0_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_BITS             1
#define BRPHY0_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_SHIFT            8

/* BRPHY0_GPHY_CORE :: SHD18_100 :: BT_CLK_RESET_EN [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x80,7)
#define BRPHY0_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_MASK            0x0080
#define BRPHY0_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_SHIFT           7

/* BRPHY0_GPHY_CORE :: SHD18_100 :: BT_BYPASS_ADC [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x40,6)
#define BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_MASK              0x0040
#define BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_BITS              1
#define BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_SHIFT             6

/* BRPHY0_GPHY_CORE :: SHD18_100 :: BT_BYPASS_CRS [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x20,5)
#define BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_MASK              0x0020
#define BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_BITS              1
#define BRPHY0_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_SHIFT             5

/* BRPHY0_GPHY_CORE :: SHD18_100 :: SWAP_RXMDIX [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x10,4)
#define BRPHY0_GPHY_CORE_SHD18_100_SWAP_RXMDIX_MASK                0x0010
#define BRPHY0_GPHY_CORE_SHD18_100_SWAP_RXMDIX_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_100_SWAP_RXMDIX_BITS                1
#define BRPHY0_GPHY_CORE_SHD18_100_SWAP_RXMDIX_SHIFT               4

/* BRPHY0_GPHY_CORE :: SHD18_100 :: HALFOUT [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_HALFOUT(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_HALFOUT(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x8,3)
#define BRPHY0_GPHY_CORE_SHD18_100_HALFOUT_MASK                    0x0008
#define BRPHY0_GPHY_CORE_SHD18_100_HALFOUT_ALIGN                   0
#define BRPHY0_GPHY_CORE_SHD18_100_HALFOUT_BITS                    1
#define BRPHY0_GPHY_CORE_SHD18_100_HALFOUT_SHIFT                   3

/* BRPHY0_GPHY_CORE :: SHD18_100 :: SHD18_SEL [02:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_100_SHD18_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_100_SHD18_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_100,0x7,0)
#define BRPHY0_GPHY_CORE_SHD18_100_SHD18_SEL_MASK                  0x0007
#define BRPHY0_GPHY_CORE_SHD18_100_SHD18_SEL_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_100_SHD18_SEL_BITS                  3
#define BRPHY0_GPHY_CORE_SHD18_100_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD18_101
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD18_101 :: COPPER_ENG_DET_OV [15:15] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x8000,15)
#define BRPHY0_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_MASK          0x8000
#define BRPHY0_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_BITS          1
#define BRPHY0_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_SHIFT         15

/* BRPHY0_GPHY_CORE :: SHD18_101 :: ADCFIFO_TX_FIX [14:14] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x4000,14)
#define BRPHY0_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_MASK             0x4000
#define BRPHY0_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_ALIGN            0
#define BRPHY0_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_BITS             1
#define BRPHY0_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_SHIFT            14

/* BRPHY0_GPHY_CORE :: SHD18_101 :: CLASS_AB_DVT_EN [13:13] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x2000,13)
#define BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_MASK            0x2000
#define BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_SHIFT           13

/* BRPHY0_GPHY_CORE :: SHD18_101 :: CLASS_AB_EN [12:12] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x1000,12)
#define BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_EN_MASK                0x1000
#define BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_EN_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_EN_BITS                1
#define BRPHY0_GPHY_CORE_SHD18_101_CLASS_AB_EN_SHIFT               12

/* BRPHY0_GPHY_CORE :: SHD18_101 :: ENC_ERR_SCALE [11:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0xc00,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0xc00,10)
#define BRPHY0_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_MASK              0x0c00
#define BRPHY0_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_ALIGN             0
#define BRPHY0_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_BITS              2
#define BRPHY0_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_SHIFT             10

/* BRPHY0_GPHY_CORE :: SHD18_101 :: SPARE_REG [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x200,9)
#define BRPHY0_GPHY_CORE_SHD18_101_SPARE_REG_MASK                  0x0200
#define BRPHY0_GPHY_CORE_SHD18_101_SPARE_REG_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_101_SPARE_REG_BITS                  1
#define BRPHY0_GPHY_CORE_SHD18_101_SPARE_REG_SHIFT                 9

/* BRPHY0_GPHY_CORE :: SHD18_101 :: AUTO_ENCODING_CORRECTION [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x100,8)
#define BRPHY0_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_MASK   0x0100
#define BRPHY0_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_ALIGN  0
#define BRPHY0_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_BITS   1
#define BRPHY0_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_SHIFT  8

/* BRPHY0_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_RX [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x80,7)
#define BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_MASK        0x0080
#define BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_ALIGN       0
#define BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_BITS        1
#define BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_SHIFT       7

/* BRPHY0_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_TX [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x40,6)
#define BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_MASK        0x0040
#define BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_ALIGN       0
#define BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_BITS        1
#define BRPHY0_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_SHIFT       6

/* BRPHY0_GPHY_CORE :: SHD18_101 :: EC_AS_NEXT [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x20,5)
#define BRPHY0_GPHY_CORE_SHD18_101_EC_AS_NEXT_MASK                 0x0020
#define BRPHY0_GPHY_CORE_SHD18_101_EC_AS_NEXT_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD18_101_EC_AS_NEXT_BITS                 1
#define BRPHY0_GPHY_CORE_SHD18_101_EC_AS_NEXT_SHIFT                5

/* BRPHY0_GPHY_CORE :: SHD18_101 :: FORCE_MDIX [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_FORCE_MDIX(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_FORCE_MDIX(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x10,4)
#define BRPHY0_GPHY_CORE_SHD18_101_FORCE_MDIX_MASK                 0x0010
#define BRPHY0_GPHY_CORE_SHD18_101_FORCE_MDIX_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD18_101_FORCE_MDIX_BITS                 1
#define BRPHY0_GPHY_CORE_SHD18_101_FORCE_MDIX_SHIFT                4

/* BRPHY0_GPHY_CORE :: SHD18_101 :: EN_PWRDNTDAC [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x8,3)
#define BRPHY0_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_MASK               0x0008
#define BRPHY0_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_BITS               1
#define BRPHY0_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_SHIFT              3

/* BRPHY0_GPHY_CORE :: SHD18_101 :: SHD18_SEL [02:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_101_SHD18_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_101_SHD18_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_101,0x7,0)
#define BRPHY0_GPHY_CORE_SHD18_101_SHD18_SEL_MASK                  0x0007
#define BRPHY0_GPHY_CORE_SHD18_101_SHD18_SEL_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_101_SHD18_SEL_BITS                  3
#define BRPHY0_GPHY_CORE_SHD18_101_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD18_110
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD18_110 :: IP_PHONE_SEED_WR_EN [15:15] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_110,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_110,0x8000,15)
#define BRPHY0_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_MASK        0x8000
#define BRPHY0_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_ALIGN       0
#define BRPHY0_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_BITS        1
#define BRPHY0_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_SHIFT       15

/* BRPHY0_GPHY_CORE :: SHD18_110 :: SPARE_REG [14:14] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_110_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_110,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_110_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_110,0x4000,14)
#define BRPHY0_GPHY_CORE_SHD18_110_SPARE_REG_MASK                  0x4000
#define BRPHY0_GPHY_CORE_SHD18_110_SPARE_REG_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_110_SPARE_REG_BITS                  1
#define BRPHY0_GPHY_CORE_SHD18_110_SPARE_REG_SHIFT                 14

/* BRPHY0_GPHY_CORE :: SHD18_110 :: LOC_IP_PHONE_SEED [13:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_110,0x3ff8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_110,0x3ff8,3)
#define BRPHY0_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_MASK          0x3ff8
#define BRPHY0_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_ALIGN         0
#define BRPHY0_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_BITS          11
#define BRPHY0_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_SHIFT         3

/* BRPHY0_GPHY_CORE :: SHD18_110 :: SHD18_SEL [02:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_110_SHD18_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_110,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_110_SHD18_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_110,0x7,0)
#define BRPHY0_GPHY_CORE_SHD18_110_SHD18_SEL_MASK                  0x0007
#define BRPHY0_GPHY_CORE_SHD18_110_SHD18_SEL_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_110_SHD18_SEL_BITS                  3
#define BRPHY0_GPHY_CORE_SHD18_110_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SHD18_111
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SHD18_111 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_SHD18_111_RESERVED0_MASK                  0x8000
#define BRPHY0_GPHY_CORE_SHD18_111_RESERVED0_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_111_RESERVED0_BITS                  1
#define BRPHY0_GPHY_CORE_SHD18_111_RESERVED0_SHIFT                 15

/* BRPHY0_GPHY_CORE :: SHD18_111 :: SHD18_RDSEL [14:12] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x7000,12,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x7000,12)
#define BRPHY0_GPHY_CORE_SHD18_111_SHD18_RDSEL_MASK                0x7000
#define BRPHY0_GPHY_CORE_SHD18_111_SHD18_RDSEL_ALIGN               0
#define BRPHY0_GPHY_CORE_SHD18_111_SHD18_RDSEL_BITS                3
#define BRPHY0_GPHY_CORE_SHD18_111_SHD18_RDSEL_SHIFT               12

/* BRPHY0_GPHY_CORE :: SHD18_111 :: PKT_CNTR [11:11] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_PKT_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_PKT_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x800,11)
#define BRPHY0_GPHY_CORE_SHD18_111_PKT_CNTR_MASK                   0x0800
#define BRPHY0_GPHY_CORE_SHD18_111_PKT_CNTR_ALIGN                  0
#define BRPHY0_GPHY_CORE_SHD18_111_PKT_CNTR_BITS                   1
#define BRPHY0_GPHY_CORE_SHD18_111_PKT_CNTR_SHIFT                  11

/* BRPHY0_GPHY_CORE :: SHD18_111 :: BYPASS_WIRESPEED_TIMER [10:10] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x400,10)
#define BRPHY0_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_MASK     0x0400
#define BRPHY0_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_ALIGN    0
#define BRPHY0_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_BITS     1
#define BRPHY0_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_SHIFT    10

/* BRPHY0_GPHY_CORE :: SHD18_111 :: FORCE_AUTO_MDIX [09:09] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x200,9)
#define BRPHY0_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_MASK            0x0200
#define BRPHY0_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_ALIGN           0
#define BRPHY0_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_BITS            1
#define BRPHY0_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_SHIFT           9

/* BRPHY0_GPHY_CORE :: SHD18_111 :: RGMII_TIMING [08:08] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_RGMII_TIMING(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_RGMII_TIMING(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x100,8)
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_TIMING_MASK               0x0100
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_TIMING_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_TIMING_BITS               1
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_TIMING_SHIFT              8

/* BRPHY0_GPHY_CORE :: SHD18_111 :: RGMII [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_RGMII(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_RGMII(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x80,7)
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_MASK                      0x0080
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_ALIGN                     0
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_BITS                      1
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_SHIFT                     7

/* BRPHY0_GPHY_CORE :: SHD18_111 :: RGMII_RXER [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_RGMII_RXER(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_RGMII_RXER(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x40,6)
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_RXER_MASK                 0x0040
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_RXER_ALIGN                0
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_RXER_BITS                 1
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_RXER_SHIFT                6

/* BRPHY0_GPHY_CORE :: SHD18_111 :: RGMII_OB_STATUS_DIS [05:05] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x20,5)
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_MASK        0x0020
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_ALIGN       0
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_BITS        1
#define BRPHY0_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_SHIFT       5

/* BRPHY0_GPHY_CORE :: SHD18_111 :: WIRESPEED_EN [04:04] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x10,4)
#define BRPHY0_GPHY_CORE_SHD18_111_WIRESPEED_EN_MASK               0x0010
#define BRPHY0_GPHY_CORE_SHD18_111_WIRESPEED_EN_ALIGN              0
#define BRPHY0_GPHY_CORE_SHD18_111_WIRESPEED_EN_BITS               1
#define BRPHY0_GPHY_CORE_SHD18_111_WIRESPEED_EN_SHIFT              4

/* BRPHY0_GPHY_CORE :: SHD18_111 :: MDIO_ALL_PHY_SEL [03:03] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x8,3)
#define BRPHY0_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_MASK           0x0008
#define BRPHY0_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_ALIGN          0
#define BRPHY0_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_BITS           1
#define BRPHY0_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_SHIFT          3

/* BRPHY0_GPHY_CORE :: SHD18_111 :: SHD18_SEL [02:00] */
#define Wr_BRPHY0_GPHY_CORE_SHD18_111_SHD18_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_SHD18_111_SHD18_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SHD18_111,0x7,0)
#define BRPHY0_GPHY_CORE_SHD18_111_SHD18_SEL_MASK                  0x0007
#define BRPHY0_GPHY_CORE_SHD18_111_SHD18_SEL_ALIGN                 0
#define BRPHY0_GPHY_CORE_SHD18_111_SHD18_SEL_BITS                  3
#define BRPHY0_GPHY_CORE_SHD18_111_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP00
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP00 :: PKT_CNTR [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP00_PKT_CNTR(x) WriteReg16(BRPHY0_GPHY_CORE_EXP00,x)
#define Rd_BRPHY0_GPHY_CORE_EXP00_PKT_CNTR(x) ReadReg16(BRPHY0_GPHY_CORE_EXP00)
#define BRPHY0_GPHY_CORE_EXP00_PKT_CNTR_MASK                       0xffff
#define BRPHY0_GPHY_CORE_EXP00_PKT_CNTR_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP00_PKT_CNTR_BITS                       16
#define BRPHY0_GPHY_CORE_EXP00_PKT_CNTR_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP01
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP01 :: LATE_COL_CNTR [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_LATE_COL_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_LATE_COL_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x8000,15)
#define BRPHY0_GPHY_CORE_EXP01_LATE_COL_CNTR_MASK                  0x8000
#define BRPHY0_GPHY_CORE_EXP01_LATE_COL_CNTR_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP01_LATE_COL_CNTR_BITS                  1
#define BRPHY0_GPHY_CORE_EXP01_LATE_COL_CNTR_SHIFT                 15

/* BRPHY0_GPHY_CORE :: EXP01 :: RMT_COPPER_ERR [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x4000,14)
#define BRPHY0_GPHY_CORE_EXP01_RMT_COPPER_ERR_MASK                 0x4000
#define BRPHY0_GPHY_CORE_EXP01_RMT_COPPER_ERR_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP01_RMT_COPPER_ERR_BITS                 1
#define BRPHY0_GPHY_CORE_EXP01_RMT_COPPER_ERR_SHIFT                14

/* BRPHY0_GPHY_CORE :: EXP01 :: SERDES_LINK_PARTNER_RESTARTED [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x2000,13)
#define BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_MASK  0x2000
#define BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_ALIGN 0
#define BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_BITS  1
#define BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_SHIFT 13

/* BRPHY0_GPHY_CORE :: EXP01 :: SERDES_CRC_ERR [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP01_SERDES_CRC_ERR_MASK                 0x1000
#define BRPHY0_GPHY_CORE_EXP01_SERDES_CRC_ERR_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP01_SERDES_CRC_ERR_BITS                 1
#define BRPHY0_GPHY_CORE_EXP01_SERDES_CRC_ERR_SHIFT                12

/* BRPHY0_GPHY_CORE :: EXP01 :: SGMII_SLAVE_CHANGE [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x800,11)
#define BRPHY0_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_MASK             0x0800
#define BRPHY0_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_ALIGN            0
#define BRPHY0_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_BITS             1
#define BRPHY0_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_SHIFT            11

/* BRPHY0_GPHY_CORE :: EXP01 :: FX_SERDES_CHANGE [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x400,10)
#define BRPHY0_GPHY_CORE_EXP01_FX_SERDES_CHANGE_MASK               0x0400
#define BRPHY0_GPHY_CORE_EXP01_FX_SERDES_CHANGE_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP01_FX_SERDES_CHANGE_BITS               1
#define BRPHY0_GPHY_CORE_EXP01_FX_SERDES_CHANGE_SHIFT              10

/* BRPHY0_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_PAGE_RCVD [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x200,9)
#define BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_MASK       0x0200
#define BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_ALIGN      0
#define BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_BITS       1
#define BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_SHIFT      9

/* BRPHY0_GPHY_CORE :: EXP01 :: EXT_SERDES_SEL_CHANGE [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x100,8)
#define BRPHY0_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_MASK          0x0100
#define BRPHY0_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_ALIGN         0
#define BRPHY0_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_BITS          1
#define BRPHY0_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_SHIFT         8

/* BRPHY0_GPHY_CORE :: EXP01 :: MODE_SEL_CHANGE [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x80,7)
#define BRPHY0_GPHY_CORE_EXP01_MODE_SEL_CHANGE_MASK                0x0080
#define BRPHY0_GPHY_CORE_EXP01_MODE_SEL_CHANGE_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP01_MODE_SEL_CHANGE_BITS                1
#define BRPHY0_GPHY_CORE_EXP01_MODE_SEL_CHANGE_SHIFT               7

/* BRPHY0_GPHY_CORE :: EXP01 :: SERDES_LINK_STATUS_CHANGE [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x40,6)
#define BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_MASK      0x0040
#define BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_ALIGN     0
#define BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_BITS      1
#define BRPHY0_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_SHIFT     6

/* BRPHY0_GPHY_CORE :: EXP01 :: RUDI_C_DET [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_RUDI_C_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_RUDI_C_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x20,5)
#define BRPHY0_GPHY_CORE_EXP01_RUDI_C_DET_MASK                     0x0020
#define BRPHY0_GPHY_CORE_EXP01_RUDI_C_DET_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP01_RUDI_C_DET_BITS                     1
#define BRPHY0_GPHY_CORE_EXP01_RUDI_C_DET_SHIFT                    5

/* BRPHY0_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_ERR [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x10,4)
#define BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_MASK             0x0010
#define BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_ALIGN            0
#define BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_BITS             1
#define BRPHY0_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_SHIFT            4

/* BRPHY0_GPHY_CORE :: EXP01 :: RUDI_I_DET [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_RUDI_I_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_RUDI_I_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x8,3)
#define BRPHY0_GPHY_CORE_EXP01_RUDI_I_DET_MASK                     0x0008
#define BRPHY0_GPHY_CORE_EXP01_RUDI_I_DET_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP01_RUDI_I_DET_BITS                     1
#define BRPHY0_GPHY_CORE_EXP01_RUDI_I_DET_SHIFT                    3

/* BRPHY0_GPHY_CORE :: EXP01 :: SERDES_RCVD_BREAK_LINK_CONDITION [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x4,2)
#define BRPHY0_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_MASK 0x0004
#define BRPHY0_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_ALIGN 0
#define BRPHY0_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_BITS 1
#define BRPHY0_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_SHIFT 2

/* BRPHY0_GPHY_CORE :: EXP01 :: ABIST_COMPLETE [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_ABIST_COMPLETE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_ABIST_COMPLETE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x2,1)
#define BRPHY0_GPHY_CORE_EXP01_ABIST_COMPLETE_MASK                 0x0002
#define BRPHY0_GPHY_CORE_EXP01_ABIST_COMPLETE_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP01_ABIST_COMPLETE_BITS                 1
#define BRPHY0_GPHY_CORE_EXP01_ABIST_COMPLETE_SHIFT                1

/* BRPHY0_GPHY_CORE :: EXP01 :: TX_CRC_ERR [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP01_TX_CRC_ERR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP01,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP01_TX_CRC_ERR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP01,0x1,0)
#define BRPHY0_GPHY_CORE_EXP01_TX_CRC_ERR_MASK                     0x0001
#define BRPHY0_GPHY_CORE_EXP01_TX_CRC_ERR_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP01_TX_CRC_ERR_BITS                     1
#define BRPHY0_GPHY_CORE_EXP01_TX_CRC_ERR_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP02
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP02 :: EXP_INT_MASK [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP02_EXP_INT_MASK(x) WriteReg16(BRPHY0_GPHY_CORE_EXP02,x)
#define Rd_BRPHY0_GPHY_CORE_EXP02_EXP_INT_MASK(x) ReadReg16(BRPHY0_GPHY_CORE_EXP02)
#define BRPHY0_GPHY_CORE_EXP02_EXP_INT_MASK_MASK                   0xffff
#define BRPHY0_GPHY_CORE_EXP02_EXP_INT_MASK_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP02_EXP_INT_MASK_BITS                   16
#define BRPHY0_GPHY_CORE_EXP02_EXP_INT_MASK_SHIFT                  0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP03
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP03 :: SPARE_REG [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP03_SPARE_REG(x) WriteReg16(BRPHY0_GPHY_CORE_EXP03,x)
#define Rd_BRPHY0_GPHY_CORE_EXP03_SPARE_REG(x) ReadReg16(BRPHY0_GPHY_CORE_EXP03)
#define BRPHY0_GPHY_CORE_EXP03_SPARE_REG_MASK                      0xffff
#define BRPHY0_GPHY_CORE_EXP03_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP03_SPARE_REG_BITS                      16
#define BRPHY0_GPHY_CORE_EXP03_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP04
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP04 :: reserved0 [15:11] */
#define BRPHY0_GPHY_CORE_EXP04_RESERVED0_MASK                      0xf800
#define BRPHY0_GPHY_CORE_EXP04_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP04_RESERVED0_BITS                      5
#define BRPHY0_GPHY_CORE_EXP04_RESERVED0_SHIFT                     11

/* BRPHY0_GPHY_CORE :: EXP04 :: BC_LED_EN [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXP04_BC_LED_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP04,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXP04_BC_LED_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP04,0x400,10)
#define BRPHY0_GPHY_CORE_EXP04_BC_LED_EN_MASK                      0x0400
#define BRPHY0_GPHY_CORE_EXP04_BC_LED_EN_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP04_BC_LED_EN_BITS                      1
#define BRPHY0_GPHY_CORE_EXP04_BC_LED_EN_SHIFT                     10

/* BRPHY0_GPHY_CORE :: EXP04 :: FLASHNOW [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXP04_FLASHNOW(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP04,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXP04_FLASHNOW(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP04,0x200,9)
#define BRPHY0_GPHY_CORE_EXP04_FLASHNOW_MASK                       0x0200
#define BRPHY0_GPHY_CORE_EXP04_FLASHNOW_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP04_FLASHNOW_BITS                       1
#define BRPHY0_GPHY_CORE_EXP04_FLASHNOW_SHIFT                      9

/* BRPHY0_GPHY_CORE :: EXP04 :: INPHASE [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP04_INPHASE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP04,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP04_INPHASE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP04,0x100,8)
#define BRPHY0_GPHY_CORE_EXP04_INPHASE_MASK                        0x0100
#define BRPHY0_GPHY_CORE_EXP04_INPHASE_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP04_INPHASE_BITS                        1
#define BRPHY0_GPHY_CORE_EXP04_INPHASE_SHIFT                       8

/* BRPHY0_GPHY_CORE :: EXP04 :: BC_SEL_1 [07:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP04_BC_SEL_1(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP04,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP04_BC_SEL_1(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP04,0xf0,4)
#define BRPHY0_GPHY_CORE_EXP04_BC_SEL_1_MASK                       0x00f0
#define BRPHY0_GPHY_CORE_EXP04_BC_SEL_1_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP04_BC_SEL_1_BITS                       4
#define BRPHY0_GPHY_CORE_EXP04_BC_SEL_1_SHIFT                      4

/* BRPHY0_GPHY_CORE :: EXP04 :: BC_SEL_0 [03:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP04_BC_SEL_0(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP04,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP04_BC_SEL_0(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP04,0xf,0)
#define BRPHY0_GPHY_CORE_EXP04_BC_SEL_0_MASK                       0x000f
#define BRPHY0_GPHY_CORE_EXP04_BC_SEL_0_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP04_BC_SEL_0_BITS                       4
#define BRPHY0_GPHY_CORE_EXP04_BC_SEL_0_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP05
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP05 :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_EXP05_RESERVED0_MASK                      0xf000
#define BRPHY0_GPHY_CORE_EXP05_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP05_RESERVED0_BITS                      4
#define BRPHY0_GPHY_CORE_EXP05_RESERVED0_SHIFT                     12

/* BRPHY0_GPHY_CORE :: EXP05 :: ALTERNATION_RATE [11:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP05_ALTERNATION_RATE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP05,0xfc0,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP05_ALTERNATION_RATE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP05,0xfc0,6)
#define BRPHY0_GPHY_CORE_EXP05_ALTERNATION_RATE_MASK               0x0fc0
#define BRPHY0_GPHY_CORE_EXP05_ALTERNATION_RATE_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP05_ALTERNATION_RATE_BITS               6
#define BRPHY0_GPHY_CORE_EXP05_ALTERNATION_RATE_SHIFT              6

/* BRPHY0_GPHY_CORE :: EXP05 :: FLASH_RATE [05:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP05_FLASH_RATE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP05,0x3f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP05_FLASH_RATE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP05,0x3f,0)
#define BRPHY0_GPHY_CORE_EXP05_FLASH_RATE_MASK                     0x003f
#define BRPHY0_GPHY_CORE_EXP05_FLASH_RATE_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP05_FLASH_RATE_BITS                     6
#define BRPHY0_GPHY_CORE_EXP05_FLASH_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP06
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP06 :: reserved0 [15:08] */
#define BRPHY0_GPHY_CORE_EXP06_RESERVED0_MASK                      0xff00
#define BRPHY0_GPHY_CORE_EXP06_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP06_RESERVED0_BITS                      8
#define BRPHY0_GPHY_CORE_EXP06_RESERVED0_SHIFT                     8

/* BRPHY0_GPHY_CORE :: EXP06 :: SPARE_REG [07:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP06_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP06,0xc0,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP06_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP06,0xc0,6)
#define BRPHY0_GPHY_CORE_EXP06_SPARE_REG_MASK                      0x00c0
#define BRPHY0_GPHY_CORE_EXP06_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP06_SPARE_REG_BITS                      2
#define BRPHY0_GPHY_CORE_EXP06_SPARE_REG_SHIFT                     6

/* BRPHY0_GPHY_CORE :: EXP06 :: BLINK_UPDATE_NOW [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP06,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP06,0x20,5)
#define BRPHY0_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_MASK               0x0020
#define BRPHY0_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_BITS               1
#define BRPHY0_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_SHIFT              5

/* BRPHY0_GPHY_CORE :: EXP06 :: BLINK_RATE [04:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP06_BLINK_RATE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP06,0x1f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP06_BLINK_RATE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP06,0x1f,0)
#define BRPHY0_GPHY_CORE_EXP06_BLINK_RATE_MASK                     0x001f
#define BRPHY0_GPHY_CORE_EXP06_BLINK_RATE_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP06_BLINK_RATE_BITS                     5
#define BRPHY0_GPHY_CORE_EXP06_BLINK_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP07
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP07 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_EXP07_RESERVED0_MASK                      0x8000
#define BRPHY0_GPHY_CORE_EXP07_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP07_RESERVED0_BITS                      1
#define BRPHY0_GPHY_CORE_EXP07_RESERVED0_SHIFT                     15

/* BRPHY0_GPHY_CORE :: EXP07 :: EXT_MAX_LP_WIDTH [14:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP07,0x7f00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP07,0x7f00,8)
#define BRPHY0_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_MASK               0x7f00
#define BRPHY0_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_BITS               7
#define BRPHY0_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_SHIFT              8

/* BRPHY0_GPHY_CORE :: EXP07 :: SPARE_REG [07:03] */
#define Wr_BRPHY0_GPHY_CORE_EXP07_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP07,0xf8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXP07_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP07,0xf8,3)
#define BRPHY0_GPHY_CORE_EXP07_SPARE_REG_MASK                      0x00f8
#define BRPHY0_GPHY_CORE_EXP07_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP07_SPARE_REG_BITS                      5
#define BRPHY0_GPHY_CORE_EXP07_SPARE_REG_SHIFT                     3

/* BRPHY0_GPHY_CORE :: EXP07 :: COPPER_FX_SIGSTAT_SEL [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP07,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP07,0x4,2)
#define BRPHY0_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_MASK          0x0004
#define BRPHY0_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_ALIGN         0
#define BRPHY0_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_BITS          1
#define BRPHY0_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_SHIFT         2

/* BRPHY0_GPHY_CORE :: EXP07 :: FAULTING [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP07_FAULTING(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP07,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP07_FAULTING(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP07,0x2,1)
#define BRPHY0_GPHY_CORE_EXP07_FAULTING_MASK                       0x0002
#define BRPHY0_GPHY_CORE_EXP07_FAULTING_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP07_FAULTING_BITS                       1
#define BRPHY0_GPHY_CORE_EXP07_FAULTING_SHIFT                      1

/* BRPHY0_GPHY_CORE :: EXP07 :: FEF_EN [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP07_FEF_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP07,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP07_FEF_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP07,0x1,0)
#define BRPHY0_GPHY_CORE_EXP07_FEF_EN_MASK                         0x0001
#define BRPHY0_GPHY_CORE_EXP07_FEF_EN_ALIGN                        0
#define BRPHY0_GPHY_CORE_EXP07_FEF_EN_BITS                         1
#define BRPHY0_GPHY_CORE_EXP07_FEF_EN_SHIFT                        0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP08
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP08 :: SILENT_LPBK [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_SILENT_LPBK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_SILENT_LPBK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x8000,15)
#define BRPHY0_GPHY_CORE_EXP08_SILENT_LPBK_MASK                    0x8000
#define BRPHY0_GPHY_CORE_EXP08_SILENT_LPBK_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP08_SILENT_LPBK_BITS                    1
#define BRPHY0_GPHY_CORE_EXP08_SILENT_LPBK_SHIFT                   15

/* BRPHY0_GPHY_CORE :: EXP08 :: RX_POLARITY_OV [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x4000,14)
#define BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_MASK                 0x4000
#define BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_BITS                 1
#define BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_SHIFT                14

/* BRPHY0_GPHY_CORE :: EXP08 :: RX_POLARITY_OV_VAL [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x2000,13)
#define BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_MASK             0x2000
#define BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_ALIGN            0
#define BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_BITS             1
#define BRPHY0_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_SHIFT            13

/* BRPHY0_GPHY_CORE :: EXP08 :: BT_BYTE_ALIGN_PREAM [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_MASK            0x1000
#define BRPHY0_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_ALIGN           0
#define BRPHY0_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_BITS            1
#define BRPHY0_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_SHIFT           12

/* BRPHY0_GPHY_CORE :: EXP08 :: BT_PREAM_SUPPRESS [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x800,11)
#define BRPHY0_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_MASK              0x0800
#define BRPHY0_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_BITS              1
#define BRPHY0_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_SHIFT             11

/* BRPHY0_GPHY_CORE :: EXP08 :: EXT_MAX_LP_WIDTH_EN [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x400,10)
#define BRPHY0_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_MASK            0x0400
#define BRPHY0_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_BITS            1
#define BRPHY0_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_SHIFT           10

/* BRPHY0_GPHY_CORE :: EXP08 :: AUTO_EARLY_DAC_WAKE [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x200,9)
#define BRPHY0_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_MASK            0x0200
#define BRPHY0_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_ALIGN           0
#define BRPHY0_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_BITS            1
#define BRPHY0_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_SHIFT           9

/* BRPHY0_GPHY_CORE :: EXP08 :: FORCE_EARLY_DAC_WAKE [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x100,8)
#define BRPHY0_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_MASK           0x0100
#define BRPHY0_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_ALIGN          0
#define BRPHY0_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_BITS           1
#define BRPHY0_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_SHIFT          8

/* BRPHY0_GPHY_CORE :: EXP08 :: SUPPRESS_CRS_HDX [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x80,7)
#define BRPHY0_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_MASK               0x0080
#define BRPHY0_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_BITS               1
#define BRPHY0_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_SHIFT              7

/* BRPHY0_GPHY_CORE :: EXP08 :: REJECT_MORE_15MHZ [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x40,6)
#define BRPHY0_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_MASK              0x0040
#define BRPHY0_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_BITS              1
#define BRPHY0_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_SHIFT             6

/* BRPHY0_GPHY_CORE :: EXP08 :: POLARITY_INVERT [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_POLARITY_INVERT(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_POLARITY_INVERT(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x20,5)
#define BRPHY0_GPHY_CORE_EXP08_POLARITY_INVERT_MASK                0x0020
#define BRPHY0_GPHY_CORE_EXP08_POLARITY_INVERT_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP08_POLARITY_INVERT_BITS                1
#define BRPHY0_GPHY_CORE_EXP08_POLARITY_INVERT_SHIFT               5

/* BRPHY0_GPHY_CORE :: EXP08 :: BLOCK_NARROW_LP [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x10,4)
#define BRPHY0_GPHY_CORE_EXP08_BLOCK_NARROW_LP_MASK                0x0010
#define BRPHY0_GPHY_CORE_EXP08_BLOCK_NARROW_LP_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP08_BLOCK_NARROW_LP_BITS                1
#define BRPHY0_GPHY_CORE_EXP08_BLOCK_NARROW_LP_SHIFT               4

/* BRPHY0_GPHY_CORE :: EXP08 :: USE_OLD_LPDET [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_USE_OLD_LPDET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_USE_OLD_LPDET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x8,3)
#define BRPHY0_GPHY_CORE_EXP08_USE_OLD_LPDET_MASK                  0x0008
#define BRPHY0_GPHY_CORE_EXP08_USE_OLD_LPDET_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP08_USE_OLD_LPDET_BITS                  1
#define BRPHY0_GPHY_CORE_EXP08_USE_OLD_LPDET_SHIFT                 3

/* BRPHY0_GPHY_CORE :: EXP08 :: EDGESTATE_REFINE [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x4,2)
#define BRPHY0_GPHY_CORE_EXP08_EDGESTATE_REFINE_MASK               0x0004
#define BRPHY0_GPHY_CORE_EXP08_EDGESTATE_REFINE_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP08_EDGESTATE_REFINE_BITS               1
#define BRPHY0_GPHY_CORE_EXP08_EDGESTATE_REFINE_SHIFT              2

/* BRPHY0_GPHY_CORE :: EXP08 :: REJECT_15MHZ [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_REJECT_15MHZ(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_REJECT_15MHZ(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x2,1)
#define BRPHY0_GPHY_CORE_EXP08_REJECT_15MHZ_MASK                   0x0002
#define BRPHY0_GPHY_CORE_EXP08_REJECT_15MHZ_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP08_REJECT_15MHZ_BITS                   1
#define BRPHY0_GPHY_CORE_EXP08_REJECT_15MHZ_SHIFT                  1

/* BRPHY0_GPHY_CORE :: EXP08 :: REJECT_2MHZ [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP08_REJECT_2MHZ(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP08,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP08_REJECT_2MHZ(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP08,0x1,0)
#define BRPHY0_GPHY_CORE_EXP08_REJECT_2MHZ_MASK                    0x0001
#define BRPHY0_GPHY_CORE_EXP08_REJECT_2MHZ_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP08_REJECT_2MHZ_BITS                    1
#define BRPHY0_GPHY_CORE_EXP08_REJECT_2MHZ_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP09
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP09 :: GIGABIT_POL_INV [15:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP09,0xf000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP09,0xf000,12)
#define BRPHY0_GPHY_CORE_EXP09_GIGABIT_POL_INV_MASK                0xf000
#define BRPHY0_GPHY_CORE_EXP09_GIGABIT_POL_INV_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP09_GIGABIT_POL_INV_BITS                4
#define BRPHY0_GPHY_CORE_EXP09_GIGABIT_POL_INV_SHIFT               12

/* BRPHY0_GPHY_CORE :: EXP09 :: SPARE_REG [11:09] */
#define Wr_BRPHY0_GPHY_CORE_EXP09_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP09,0xe00,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXP09_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP09,0xe00,9)
#define BRPHY0_GPHY_CORE_EXP09_SPARE_REG_MASK                      0x0e00
#define BRPHY0_GPHY_CORE_EXP09_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP09_SPARE_REG_BITS                      3
#define BRPHY0_GPHY_CORE_EXP09_SPARE_REG_SHIFT                     9

/* BRPHY0_GPHY_CORE :: EXP09 :: ALLOW_SWAP [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP09_ALLOW_SWAP(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP09,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP09_ALLOW_SWAP(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP09,0x100,8)
#define BRPHY0_GPHY_CORE_EXP09_ALLOW_SWAP_MASK                     0x0100
#define BRPHY0_GPHY_CORE_EXP09_ALLOW_SWAP_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP09_ALLOW_SWAP_BITS                     1
#define BRPHY0_GPHY_CORE_EXP09_ALLOW_SWAP_SHIFT                    8

/* BRPHY0_GPHY_CORE :: EXP09 :: CH3_SEL [07:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP09_CH3_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP09,0xc0,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP09_CH3_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP09,0xc0,6)
#define BRPHY0_GPHY_CORE_EXP09_CH3_SEL_MASK                        0x00c0
#define BRPHY0_GPHY_CORE_EXP09_CH3_SEL_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP09_CH3_SEL_BITS                        2
#define BRPHY0_GPHY_CORE_EXP09_CH3_SEL_SHIFT                       6

/* BRPHY0_GPHY_CORE :: EXP09 :: CH2_SEL [05:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP09_CH2_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP09,0x30,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP09_CH2_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP09,0x30,4)
#define BRPHY0_GPHY_CORE_EXP09_CH2_SEL_MASK                        0x0030
#define BRPHY0_GPHY_CORE_EXP09_CH2_SEL_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP09_CH2_SEL_BITS                        2
#define BRPHY0_GPHY_CORE_EXP09_CH2_SEL_SHIFT                       4

/* BRPHY0_GPHY_CORE :: EXP09 :: CH1_SEL [03:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP09_CH1_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP09,0xc,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP09_CH1_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP09,0xc,2)
#define BRPHY0_GPHY_CORE_EXP09_CH1_SEL_MASK                        0x000c
#define BRPHY0_GPHY_CORE_EXP09_CH1_SEL_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP09_CH1_SEL_BITS                        2
#define BRPHY0_GPHY_CORE_EXP09_CH1_SEL_SHIFT                       2

/* BRPHY0_GPHY_CORE :: EXP09 :: CH0_SEL [01:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP09_CH0_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP09,0x3,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP09_CH0_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP09,0x3,0)
#define BRPHY0_GPHY_CORE_EXP09_CH0_SEL_MASK                        0x0003
#define BRPHY0_GPHY_CORE_EXP09_CH0_SEL_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP09_CH0_SEL_BITS                        2
#define BRPHY0_GPHY_CORE_EXP09_CH0_SEL_SHIFT                       0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP0A
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP0A :: reserved0 [15:13] */
#define BRPHY0_GPHY_CORE_EXP0A_RESERVED0_MASK                      0xe000
#define BRPHY0_GPHY_CORE_EXP0A_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP0A_RESERVED0_BITS                      3
#define BRPHY0_GPHY_CORE_EXP0A_RESERVED0_SHIFT                     13

/* BRPHY0_GPHY_CORE :: EXP0A :: SYNC_IN_EN [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP0A_SYNC_IN_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP0A_SYNC_IN_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP0A_SYNC_IN_EN_MASK                     0x1000
#define BRPHY0_GPHY_CORE_EXP0A_SYNC_IN_EN_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP0A_SYNC_IN_EN_BITS                     1
#define BRPHY0_GPHY_CORE_EXP0A_SYNC_IN_EN_SHIFT                    12

/* BRPHY0_GPHY_CORE :: EXP0A :: CHANNEL_KILL [11:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP0A_CHANNEL_KILL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP0A,0xf00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP0A_CHANNEL_KILL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP0A,0xf00,8)
#define BRPHY0_GPHY_CORE_EXP0A_CHANNEL_KILL_MASK                   0x0f00
#define BRPHY0_GPHY_CORE_EXP0A_CHANNEL_KILL_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP0A_CHANNEL_KILL_BITS                   4
#define BRPHY0_GPHY_CORE_EXP0A_CHANNEL_KILL_SHIFT                  8

/* BRPHY0_GPHY_CORE :: EXP0A :: SYNC_KILL [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXP0A_SYNC_KILL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXP0A_SYNC_KILL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x80,7)
#define BRPHY0_GPHY_CORE_EXP0A_SYNC_KILL_MASK                      0x0080
#define BRPHY0_GPHY_CORE_EXP0A_SYNC_KILL_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP0A_SYNC_KILL_BITS                      1
#define BRPHY0_GPHY_CORE_EXP0A_SYNC_KILL_SHIFT                     7

/* BRPHY0_GPHY_CORE :: EXP0A :: BYPASS_ENE [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP0A_BYPASS_ENE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP0A_BYPASS_ENE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x40,6)
#define BRPHY0_GPHY_CORE_EXP0A_BYPASS_ENE_MASK                     0x0040
#define BRPHY0_GPHY_CORE_EXP0A_BYPASS_ENE_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP0A_BYPASS_ENE_BITS                     1
#define BRPHY0_GPHY_CORE_EXP0A_BYPASS_ENE_SHIFT                    6

/* BRPHY0_GPHY_CORE :: EXP0A :: PAT_DURATION [05:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP0A_PAT_DURATION(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x30,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP0A_PAT_DURATION(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x30,4)
#define BRPHY0_GPHY_CORE_EXP0A_PAT_DURATION_MASK                   0x0030
#define BRPHY0_GPHY_CORE_EXP0A_PAT_DURATION_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP0A_PAT_DURATION_BITS                   2
#define BRPHY0_GPHY_CORE_EXP0A_PAT_DURATION_SHIFT                  4

/* BRPHY0_GPHY_CORE :: EXP0A :: PAT_SEL [03:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP0A_PAT_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP0A,0xe,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP0A_PAT_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP0A,0xe,1)
#define BRPHY0_GPHY_CORE_EXP0A_PAT_SEL_MASK                        0x000e
#define BRPHY0_GPHY_CORE_EXP0A_PAT_SEL_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP0A_PAT_SEL_BITS                        3
#define BRPHY0_GPHY_CORE_EXP0A_PAT_SEL_SHIFT                       1

/* BRPHY0_GPHY_CORE :: EXP0A :: TEMPLATE_EN [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP0A_TEMPLATE_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP0A_TEMPLATE_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP0A,0x1,0)
#define BRPHY0_GPHY_CORE_EXP0A_TEMPLATE_EN_MASK                    0x0001
#define BRPHY0_GPHY_CORE_EXP0A_TEMPLATE_EN_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP0A_TEMPLATE_EN_BITS                    1
#define BRPHY0_GPHY_CORE_EXP0A_TEMPLATE_EN_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP0B
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP0B :: EXT_STATUS [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP0B_EXT_STATUS(x) WriteReg16(BRPHY0_GPHY_CORE_EXP0B,x)
#define Rd_BRPHY0_GPHY_CORE_EXP0B_EXT_STATUS(x) ReadReg16(BRPHY0_GPHY_CORE_EXP0B)
#define BRPHY0_GPHY_CORE_EXP0B_EXT_STATUS_MASK                     0xffff
#define BRPHY0_GPHY_CORE_EXP0B_EXT_STATUS_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP0B_EXT_STATUS_BITS                     16
#define BRPHY0_GPHY_CORE_EXP0B_EXT_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP0C
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP0C :: SPARE_REG [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP0C_SPARE_REG(x) WriteReg16(BRPHY0_GPHY_CORE_EXP0C,x)
#define Rd_BRPHY0_GPHY_CORE_EXP0C_SPARE_REG(x) ReadReg16(BRPHY0_GPHY_CORE_EXP0C)
#define BRPHY0_GPHY_CORE_EXP0C_SPARE_REG_MASK                      0xffff
#define BRPHY0_GPHY_CORE_EXP0C_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP0C_SPARE_REG_BITS                      16
#define BRPHY0_GPHY_CORE_EXP0C_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP30
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP30 :: reserved0 [15:05] */
#define BRPHY0_GPHY_CORE_EXP30_RESERVED0_MASK                      0xffe0
#define BRPHY0_GPHY_CORE_EXP30_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP30_RESERVED0_BITS                      11
#define BRPHY0_GPHY_CORE_EXP30_RESERVED0_SHIFT                     5

/* BRPHY0_GPHY_CORE :: EXP30 :: DEADMAN_RESET [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP30_DEADMAN_RESET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP30,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP30_DEADMAN_RESET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP30,0x10,4)
#define BRPHY0_GPHY_CORE_EXP30_DEADMAN_RESET_MASK                  0x0010
#define BRPHY0_GPHY_CORE_EXP30_DEADMAN_RESET_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP30_DEADMAN_RESET_BITS                  1
#define BRPHY0_GPHY_CORE_EXP30_DEADMAN_RESET_SHIFT                 4

/* BRPHY0_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_128_TO_255 [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP30,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP30,0x8,3)
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_MASK       0x0008
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_ALIGN      0
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_BITS       1
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_SHIFT      3

/* BRPHY0_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_64_TO_127 [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP30,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP30,0x4,2)
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_MASK        0x0004
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_ALIGN       0
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_BITS        1
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_SHIFT       2

/* BRPHY0_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_32_TO_63 [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP30,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP30,0x2,1)
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_MASK         0x0002
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_ALIGN        0
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_BITS         1
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_SHIFT        1

/* BRPHY0_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_0_TO_31 [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP30,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP30,0x1,0)
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_MASK          0x0001
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_ALIGN         0
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_BITS          1
#define BRPHY0_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_SHIFT         0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP31
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP31 :: reserved0 [15:08] */
#define BRPHY0_GPHY_CORE_EXP31_RESERVED0_MASK                      0xff00
#define BRPHY0_GPHY_CORE_EXP31_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP31_RESERVED0_BITS                      8
#define BRPHY0_GPHY_CORE_EXP31_RESERVED0_SHIFT                     8

/* BRPHY0_GPHY_CORE :: EXP31 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP31_LATE_COL_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP31,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP31_LATE_COL_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP31,0xff,0)
#define BRPHY0_GPHY_CORE_EXP31_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY0_GPHY_CORE_EXP31_LATE_COL_CNTR_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP31_LATE_COL_CNTR_BITS                  8
#define BRPHY0_GPHY_CORE_EXP31_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP32
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP32 :: reserved0 [15:08] */
#define BRPHY0_GPHY_CORE_EXP32_RESERVED0_MASK                      0xff00
#define BRPHY0_GPHY_CORE_EXP32_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP32_RESERVED0_BITS                      8
#define BRPHY0_GPHY_CORE_EXP32_RESERVED0_SHIFT                     8

/* BRPHY0_GPHY_CORE :: EXP32 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP32_LATE_COL_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP32,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP32_LATE_COL_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP32,0xff,0)
#define BRPHY0_GPHY_CORE_EXP32_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY0_GPHY_CORE_EXP32_LATE_COL_CNTR_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP32_LATE_COL_CNTR_BITS                  8
#define BRPHY0_GPHY_CORE_EXP32_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP33
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP33 :: reserved0 [15:08] */
#define BRPHY0_GPHY_CORE_EXP33_RESERVED0_MASK                      0xff00
#define BRPHY0_GPHY_CORE_EXP33_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP33_RESERVED0_BITS                      8
#define BRPHY0_GPHY_CORE_EXP33_RESERVED0_SHIFT                     8

/* BRPHY0_GPHY_CORE :: EXP33 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP33_LATE_COL_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP33,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP33_LATE_COL_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP33,0xff,0)
#define BRPHY0_GPHY_CORE_EXP33_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY0_GPHY_CORE_EXP33_LATE_COL_CNTR_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP33_LATE_COL_CNTR_BITS                  8
#define BRPHY0_GPHY_CORE_EXP33_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP34
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP34 :: reserved0 [15:08] */
#define BRPHY0_GPHY_CORE_EXP34_RESERVED0_MASK                      0xff00
#define BRPHY0_GPHY_CORE_EXP34_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP34_RESERVED0_BITS                      8
#define BRPHY0_GPHY_CORE_EXP34_RESERVED0_SHIFT                     8

/* BRPHY0_GPHY_CORE :: EXP34 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP34_LATE_COL_CNTR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP34,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP34_LATE_COL_CNTR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP34,0xff,0)
#define BRPHY0_GPHY_CORE_EXP34_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY0_GPHY_CORE_EXP34_LATE_COL_CNTR_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP34_LATE_COL_CNTR_BITS                  8
#define BRPHY0_GPHY_CORE_EXP34_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP35
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP35 :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_EXP35_RESERVED0_MASK                      0xf000
#define BRPHY0_GPHY_CORE_EXP35_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP35_RESERVED0_BITS                      4
#define BRPHY0_GPHY_CORE_EXP35_RESERVED0_SHIFT                     12

/* BRPHY0_GPHY_CORE :: EXP35 :: MII_INTERFACE_MODES [11:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP35,0xf00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP35,0xf00,8)
#define BRPHY0_GPHY_CORE_EXP35_MII_INTERFACE_MODES_MASK            0x0f00
#define BRPHY0_GPHY_CORE_EXP35_MII_INTERFACE_MODES_ALIGN           0
#define BRPHY0_GPHY_CORE_EXP35_MII_INTERFACE_MODES_BITS            4
#define BRPHY0_GPHY_CORE_EXP35_MII_INTERFACE_MODES_SHIFT           8

/* BRPHY0_GPHY_CORE :: EXP35 :: LATE_COL_CNTR_THD [07:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP35,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP35,0xff,0)
#define BRPHY0_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_MASK              0x00ff
#define BRPHY0_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_BITS              8
#define BRPHY0_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_SHIFT             0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP36
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP36 :: PPM_DET_PWRDN [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP36,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP36,0x8000,15)
#define BRPHY0_GPHY_CORE_EXP36_PPM_DET_PWRDN_MASK                  0x8000
#define BRPHY0_GPHY_CORE_EXP36_PPM_DET_PWRDN_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP36_PPM_DET_PWRDN_BITS                  1
#define BRPHY0_GPHY_CORE_EXP36_PPM_DET_PWRDN_SHIFT                 15

/* BRPHY0_GPHY_CORE :: EXP36 :: PPM_DET_TEST [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXP36_PPM_DET_TEST(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP36,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXP36_PPM_DET_TEST(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP36,0x4000,14)
#define BRPHY0_GPHY_CORE_EXP36_PPM_DET_TEST_MASK                   0x4000
#define BRPHY0_GPHY_CORE_EXP36_PPM_DET_TEST_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP36_PPM_DET_TEST_BITS                   1
#define BRPHY0_GPHY_CORE_EXP36_PPM_DET_TEST_SHIFT                  14

/* BRPHY0_GPHY_CORE :: EXP36 :: reserved0 [13:10] */
#define BRPHY0_GPHY_CORE_EXP36_RESERVED0_MASK                      0x3c00
#define BRPHY0_GPHY_CORE_EXP36_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP36_RESERVED0_BITS                      4
#define BRPHY0_GPHY_CORE_EXP36_RESERVED0_SHIFT                     10

/* BRPHY0_GPHY_CORE :: EXP36 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP36_PPM_OFFSET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP36,0x3ff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP36_PPM_OFFSET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP36,0x3ff,0)
#define BRPHY0_GPHY_CORE_EXP36_PPM_OFFSET_MASK                     0x03ff
#define BRPHY0_GPHY_CORE_EXP36_PPM_OFFSET_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP36_PPM_OFFSET_BITS                     10
#define BRPHY0_GPHY_CORE_EXP36_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP37
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP37 :: reserved0 [15:10] */
#define BRPHY0_GPHY_CORE_EXP37_RESERVED0_MASK                      0xfc00
#define BRPHY0_GPHY_CORE_EXP37_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP37_RESERVED0_BITS                      6
#define BRPHY0_GPHY_CORE_EXP37_RESERVED0_SHIFT                     10

/* BRPHY0_GPHY_CORE :: EXP37 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP37_PPM_OFFSET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP37,0x3ff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP37_PPM_OFFSET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP37,0x3ff,0)
#define BRPHY0_GPHY_CORE_EXP37_PPM_OFFSET_MASK                     0x03ff
#define BRPHY0_GPHY_CORE_EXP37_PPM_OFFSET_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP37_PPM_OFFSET_BITS                     10
#define BRPHY0_GPHY_CORE_EXP37_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP38
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP38 :: IP_PHONE_DET_CHANGE [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP38,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP38,0x8000,15)
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_MASK            0x8000
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_ALIGN           0
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_BITS            1
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_SHIFT           15

/* BRPHY0_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH_CHANGE [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP38,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP38,0x4000,14)
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_MASK       0x4000
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_ALIGN      0
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_BITS       1
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_SHIFT      14

/* BRPHY0_GPHY_CORE :: EXP38 :: IP_PHONE_FLP_BURST_TX [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP38,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP38,0x2000,13)
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_MASK          0x2000
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_ALIGN         0
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_BITS          1
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_SHIFT         13

/* BRPHY0_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP38,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP38,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_MASK              0x1000
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_BITS              1
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_SHIFT             12

/* BRPHY0_GPHY_CORE :: EXP38 :: IP_PHONE_DET [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP38,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP38,0x800,11)
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_MASK                   0x0800
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_BITS                   1
#define BRPHY0_GPHY_CORE_EXP38_IP_PHONE_DET_SHIFT                  11

/* BRPHY0_GPHY_CORE :: EXP38 :: NO_RESPSONSE [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXP38_NO_RESPSONSE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP38,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXP38_NO_RESPSONSE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP38,0x400,10)
#define BRPHY0_GPHY_CORE_EXP38_NO_RESPSONSE_MASK                   0x0400
#define BRPHY0_GPHY_CORE_EXP38_NO_RESPSONSE_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP38_NO_RESPSONSE_BITS                   1
#define BRPHY0_GPHY_CORE_EXP38_NO_RESPSONSE_SHIFT                  10

/* BRPHY0_GPHY_CORE :: EXP38 :: TOTAL_RT_DLY [09:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP38,0x3ff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP38,0x3ff,0)
#define BRPHY0_GPHY_CORE_EXP38_TOTAL_RT_DLY_MASK                   0x03ff
#define BRPHY0_GPHY_CORE_EXP38_TOTAL_RT_DLY_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP38_TOTAL_RT_DLY_BITS                   10
#define BRPHY0_GPHY_CORE_EXP38_TOTAL_RT_DLY_SHIFT                  0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP42
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP42 :: SERDES_LINK [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_SERDES_LINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_SERDES_LINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x8000,15)
#define BRPHY0_GPHY_CORE_EXP42_SERDES_LINK_MASK                    0x8000
#define BRPHY0_GPHY_CORE_EXP42_SERDES_LINK_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP42_SERDES_LINK_BITS                    1
#define BRPHY0_GPHY_CORE_EXP42_SERDES_LINK_SHIFT                   15

/* BRPHY0_GPHY_CORE :: EXP42 :: SERDES_SPEED [14:13] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_SERDES_SPEED(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x6000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_SERDES_SPEED(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x6000,13)
#define BRPHY0_GPHY_CORE_EXP42_SERDES_SPEED_MASK                   0x6000
#define BRPHY0_GPHY_CORE_EXP42_SERDES_SPEED_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP42_SERDES_SPEED_BITS                   2
#define BRPHY0_GPHY_CORE_EXP42_SERDES_SPEED_SHIFT                  13

/* BRPHY0_GPHY_CORE :: EXP42 :: SERDES_DUPLEX [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_SERDES_DUPLEX(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_SERDES_DUPLEX(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP42_SERDES_DUPLEX_MASK                  0x1000
#define BRPHY0_GPHY_CORE_EXP42_SERDES_DUPLEX_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP42_SERDES_DUPLEX_BITS                  1
#define BRPHY0_GPHY_CORE_EXP42_SERDES_DUPLEX_SHIFT                 12

/* BRPHY0_GPHY_CORE :: EXP42 :: COPPER_LINK [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_COPPER_LINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_COPPER_LINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x800,11)
#define BRPHY0_GPHY_CORE_EXP42_COPPER_LINK_MASK                    0x0800
#define BRPHY0_GPHY_CORE_EXP42_COPPER_LINK_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP42_COPPER_LINK_BITS                    1
#define BRPHY0_GPHY_CORE_EXP42_COPPER_LINK_SHIFT                   11

/* BRPHY0_GPHY_CORE :: EXP42 :: COPPER_SPEED [10:09] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_COPPER_SPEED(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x600,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_COPPER_SPEED(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x600,9)
#define BRPHY0_GPHY_CORE_EXP42_COPPER_SPEED_MASK                   0x0600
#define BRPHY0_GPHY_CORE_EXP42_COPPER_SPEED_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP42_COPPER_SPEED_BITS                   2
#define BRPHY0_GPHY_CORE_EXP42_COPPER_SPEED_SHIFT                  9

/* BRPHY0_GPHY_CORE :: EXP42 :: COPPER_DUPLEX [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_COPPER_DUPLEX(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_COPPER_DUPLEX(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x100,8)
#define BRPHY0_GPHY_CORE_EXP42_COPPER_DUPLEX_MASK                  0x0100
#define BRPHY0_GPHY_CORE_EXP42_COPPER_DUPLEX_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP42_COPPER_DUPLEX_BITS                  1
#define BRPHY0_GPHY_CORE_EXP42_COPPER_DUPLEX_SHIFT                 8

/* BRPHY0_GPHY_CORE :: EXP42 :: COPPER_ENERGY_DETECT [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x80,7)
#define BRPHY0_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_MASK           0x0080
#define BRPHY0_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_ALIGN          0
#define BRPHY0_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_BITS           1
#define BRPHY0_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_SHIFT          7

/* BRPHY0_GPHY_CORE :: EXP42 :: FIBER_SIGNAL_DETECT [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x40,6)
#define BRPHY0_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_MASK            0x0040
#define BRPHY0_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_ALIGN           0
#define BRPHY0_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_BITS            1
#define BRPHY0_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_SHIFT           6

/* BRPHY0_GPHY_CORE :: EXP42 :: SYNC_STATUS [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_SYNC_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_SYNC_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x20,5)
#define BRPHY0_GPHY_CORE_EXP42_SYNC_STATUS_MASK                    0x0020
#define BRPHY0_GPHY_CORE_EXP42_SYNC_STATUS_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP42_SYNC_STATUS_BITS                    1
#define BRPHY0_GPHY_CORE_EXP42_SYNC_STATUS_SHIFT                   5

/* BRPHY0_GPHY_CORE :: EXP42 :: OPERATING_MODE_STATUS [04:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP42,0x1f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP42,0x1f,0)
#define BRPHY0_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_MASK          0x001f
#define BRPHY0_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_ALIGN         0
#define BRPHY0_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_BITS          5
#define BRPHY0_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_SHIFT         0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP5F
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP5F :: PLL_TCLK_OFFSET [15:10] */
#define Wr_BRPHY0_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP5F,0xfc00,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP5F,0xfc00,10)
#define BRPHY0_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_MASK                0xfc00
#define BRPHY0_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_BITS                6
#define BRPHY0_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_SHIFT               10

/* BRPHY0_GPHY_CORE :: EXP5F :: PLL_RCLK_OFFSET [09:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP5F,0x3f0,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP5F,0x3f0,4)
#define BRPHY0_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_MASK                0x03f0
#define BRPHY0_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_BITS                6
#define BRPHY0_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_SHIFT               4

/* BRPHY0_GPHY_CORE :: EXP5F :: PLLTEST_CNT [03:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP5F_PLLTEST_CNT(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP5F,0xc,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP5F_PLLTEST_CNT(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP5F,0xc,2)
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_CNT_MASK                    0x000c
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_CNT_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_CNT_BITS                    2
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_CNT_SHIFT                   2

/* BRPHY0_GPHY_CORE :: EXP5F :: PLLTEST [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP5F_PLLTEST(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP5F,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP5F_PLLTEST(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP5F,0x2,1)
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_MASK                        0x0002
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_BITS                        1
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_SHIFT                       1

/* BRPHY0_GPHY_CORE :: EXP5F :: PLLTEST_EN [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP5F_PLLTEST_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP5F,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP5F_PLLTEST_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP5F,0x1,0)
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_EN_MASK                     0x0001
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_EN_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_EN_BITS                     1
#define BRPHY0_GPHY_CORE_EXP5F_PLLTEST_EN_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP70
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP70 :: reserved0 [15:01] */
#define BRPHY0_GPHY_CORE_EXP70_RESERVED0_MASK                      0xfffe
#define BRPHY0_GPHY_CORE_EXP70_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP70_RESERVED0_BITS                      15
#define BRPHY0_GPHY_CORE_EXP70_RESERVED0_SHIFT                     1

/* BRPHY0_GPHY_CORE :: EXP70 :: SOFT_RESET [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP70_SOFT_RESET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP70,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP70_SOFT_RESET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP70,0x1,0)
#define BRPHY0_GPHY_CORE_EXP70_SOFT_RESET_MASK                     0x0001
#define BRPHY0_GPHY_CORE_EXP70_SOFT_RESET_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP70_SOFT_RESET_BITS                     1
#define BRPHY0_GPHY_CORE_EXP70_SOFT_RESET_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP71
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP71 :: reserved0 [15:14] */
#define BRPHY0_GPHY_CORE_EXP71_RESERVED0_MASK                      0xc000
#define BRPHY0_GPHY_CORE_EXP71_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP71_RESERVED0_BITS                      2
#define BRPHY0_GPHY_CORE_EXP71_RESERVED0_SHIFT                     14

/* BRPHY0_GPHY_CORE :: EXP71 :: SERIAL_LED_EN [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP71,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP71,0x2000,13)
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_EN_MASK                  0x2000
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_EN_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_EN_BITS                  1
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_EN_SHIFT                 13

/* BRPHY0_GPHY_CORE :: EXP71 :: LOW_COST_LED_EN [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP71,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP71,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP71_LOW_COST_LED_EN_MASK                0x1000
#define BRPHY0_GPHY_CORE_EXP71_LOW_COST_LED_EN_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP71_LOW_COST_LED_EN_BITS                1
#define BRPHY0_GPHY_CORE_EXP71_LOW_COST_LED_EN_SHIFT               12

/* BRPHY0_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_6 [11:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP71,0xf00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP71,0xf00,8)
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_MASK               0x0f00
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_BITS               4
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_SHIFT              8

/* BRPHY0_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_5 [07:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP71,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP71,0xf0,4)
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_MASK               0x00f0
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_BITS               4
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_SHIFT              4

/* BRPHY0_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_4 [03:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP71,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP71,0xf,0)
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_MASK               0x000f
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_BITS               4
#define BRPHY0_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP72
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP72 :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_EXP72_RESERVED0_MASK                      0xf000
#define BRPHY0_GPHY_CORE_EXP72_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP72_RESERVED0_BITS                      4
#define BRPHY0_GPHY_CORE_EXP72_RESERVED0_SHIFT                     12

/* BRPHY0_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_3 [11:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP72,0xf00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP72,0xf00,8)
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_MASK               0x0f00
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_BITS               4
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_SHIFT              8

/* BRPHY0_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_2 [07:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP72,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP72,0xf0,4)
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_MASK               0x00f0
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_BITS               4
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_SHIFT              4

/* BRPHY0_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_1 [03:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP72,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP72,0xf,0)
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_MASK               0x000f
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_BITS               4
#define BRPHY0_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP73
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP73 :: reserved0 [15:08] */
#define BRPHY0_GPHY_CORE_EXP73_RESERVED0_MASK                      0xff00
#define BRPHY0_GPHY_CORE_EXP73_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP73_RESERVED0_BITS                      8
#define BRPHY0_GPHY_CORE_EXP73_RESERVED0_SHIFT                     8

/* BRPHY0_GPHY_CORE :: EXP73 :: LED_6_TO_1_COPPER [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP73,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP73,0x80,7)
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_MASK              0x0080
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_BITS              1
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_SHIFT             7

/* BRPHY0_GPHY_CORE :: EXP73 :: LED_5_TO_1_COPPER [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP73,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP73,0x40,6)
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_MASK              0x0040
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_BITS              1
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_SHIFT             6

/* BRPHY0_GPHY_CORE :: EXP73 :: LED_6_TO_0_COPPER [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP73,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP73,0x20,5)
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_MASK              0x0020
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_BITS              1
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_SHIFT             5

/* BRPHY0_GPHY_CORE :: EXP73 :: LED_5_TO_0_COPPER [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP73,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP73,0x10,4)
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_MASK              0x0010
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_ALIGN             0
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_BITS              1
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_SHIFT             4

/* BRPHY0_GPHY_CORE :: EXP73 :: LED_6_TO_1_FIBER [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP73,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP73,0x8,3)
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_MASK               0x0008
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_BITS               1
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_SHIFT              3

/* BRPHY0_GPHY_CORE :: EXP73 :: LED_5_TO_1_FIBER [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP73,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP73,0x4,2)
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_MASK               0x0004
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_BITS               1
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_SHIFT              2

/* BRPHY0_GPHY_CORE :: EXP73 :: LED_6_TO_0_FIBER [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP73,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP73,0x2,1)
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_MASK               0x0002
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_BITS               1
#define BRPHY0_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_SHIFT              1

/* BRPHY0_GPHY_CORE :: EXP73 :: LED_5_TO_0_FIBER [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP73,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP73,0x1,0)
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_MASK               0x0001
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_BITS               1
#define BRPHY0_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP74
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP74 :: LED4_CM_SW_VAL [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP74,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP74,0x8000,15)
#define BRPHY0_GPHY_CORE_EXP74_LED4_CM_SW_VAL_MASK                 0x8000
#define BRPHY0_GPHY_CORE_EXP74_LED4_CM_SW_VAL_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP74_LED4_CM_SW_VAL_BITS                 1
#define BRPHY0_GPHY_CORE_EXP74_LED4_CM_SW_VAL_SHIFT                15

/* BRPHY0_GPHY_CORE :: EXP74 :: LED4_CM_CTRL [14:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP74_LED4_CM_CTRL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP74,0x7000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP74_LED4_CM_CTRL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP74,0x7000,12)
#define BRPHY0_GPHY_CORE_EXP74_LED4_CM_CTRL_MASK                   0x7000
#define BRPHY0_GPHY_CORE_EXP74_LED4_CM_CTRL_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP74_LED4_CM_CTRL_BITS                   3
#define BRPHY0_GPHY_CORE_EXP74_LED4_CM_CTRL_SHIFT                  12

/* BRPHY0_GPHY_CORE :: EXP74 :: LED3_CM_SW_VAL [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP74,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP74,0x800,11)
#define BRPHY0_GPHY_CORE_EXP74_LED3_CM_SW_VAL_MASK                 0x0800
#define BRPHY0_GPHY_CORE_EXP74_LED3_CM_SW_VAL_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP74_LED3_CM_SW_VAL_BITS                 1
#define BRPHY0_GPHY_CORE_EXP74_LED3_CM_SW_VAL_SHIFT                11

/* BRPHY0_GPHY_CORE :: EXP74 :: LED3_CM_CTRL [10:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP74_LED3_CM_CTRL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP74,0x700,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP74_LED3_CM_CTRL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP74,0x700,8)
#define BRPHY0_GPHY_CORE_EXP74_LED3_CM_CTRL_MASK                   0x0700
#define BRPHY0_GPHY_CORE_EXP74_LED3_CM_CTRL_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP74_LED3_CM_CTRL_BITS                   3
#define BRPHY0_GPHY_CORE_EXP74_LED3_CM_CTRL_SHIFT                  8

/* BRPHY0_GPHY_CORE :: EXP74 :: LED2_CM_SW_VAL [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP74,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP74,0x80,7)
#define BRPHY0_GPHY_CORE_EXP74_LED2_CM_SW_VAL_MASK                 0x0080
#define BRPHY0_GPHY_CORE_EXP74_LED2_CM_SW_VAL_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP74_LED2_CM_SW_VAL_BITS                 1
#define BRPHY0_GPHY_CORE_EXP74_LED2_CM_SW_VAL_SHIFT                7

/* BRPHY0_GPHY_CORE :: EXP74 :: LED2_CM_CTRL [06:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP74_LED2_CM_CTRL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP74,0x70,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP74_LED2_CM_CTRL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP74,0x70,4)
#define BRPHY0_GPHY_CORE_EXP74_LED2_CM_CTRL_MASK                   0x0070
#define BRPHY0_GPHY_CORE_EXP74_LED2_CM_CTRL_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP74_LED2_CM_CTRL_BITS                   3
#define BRPHY0_GPHY_CORE_EXP74_LED2_CM_CTRL_SHIFT                  4

/* BRPHY0_GPHY_CORE :: EXP74 :: LED1_CM_SW_VAL [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP74,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP74,0x8,3)
#define BRPHY0_GPHY_CORE_EXP74_LED1_CM_SW_VAL_MASK                 0x0008
#define BRPHY0_GPHY_CORE_EXP74_LED1_CM_SW_VAL_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP74_LED1_CM_SW_VAL_BITS                 1
#define BRPHY0_GPHY_CORE_EXP74_LED1_CM_SW_VAL_SHIFT                3

/* BRPHY0_GPHY_CORE :: EXP74 :: LED1_CM_CTRL [02:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP74_LED1_CM_CTRL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP74,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP74_LED1_CM_CTRL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP74,0x7,0)
#define BRPHY0_GPHY_CORE_EXP74_LED1_CM_CTRL_MASK                   0x0007
#define BRPHY0_GPHY_CORE_EXP74_LED1_CM_CTRL_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXP74_LED1_CM_CTRL_BITS                   3
#define BRPHY0_GPHY_CORE_EXP74_LED1_CM_CTRL_SHIFT                  0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP75
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP75 :: reserved0 [15:10] */
#define BRPHY0_GPHY_CORE_EXP75_RESERVED0_MASK                      0xfc00
#define BRPHY0_GPHY_CORE_EXP75_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP75_RESERVED0_BITS                      6
#define BRPHY0_GPHY_CORE_EXP75_RESERVED0_SHIFT                     10

/* BRPHY0_GPHY_CORE :: EXP75 :: CED_LED_ERR_MASK [09:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP75,0x3ff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP75,0x3ff,0)
#define BRPHY0_GPHY_CORE_EXP75_CED_LED_ERR_MASK_MASK               0x03ff
#define BRPHY0_GPHY_CORE_EXP75_CED_LED_ERR_MASK_ALIGN              0
#define BRPHY0_GPHY_CORE_EXP75_CED_LED_ERR_MASK_BITS               10
#define BRPHY0_GPHY_CORE_EXP75_CED_LED_ERR_MASK_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP78
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP78 :: DAC_ANA_TEST_EN [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP78,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP78,0x8000,15)
#define BRPHY0_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_MASK                0x8000
#define BRPHY0_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_BITS                1
#define BRPHY0_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_SHIFT               15

/* BRPHY0_GPHY_CORE :: EXP78 :: BR_TXPR_EN [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXP78_BR_TXPR_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP78,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXP78_BR_TXPR_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP78,0x4000,14)
#define BRPHY0_GPHY_CORE_EXP78_BR_TXPR_EN_MASK                     0x4000
#define BRPHY0_GPHY_CORE_EXP78_BR_TXPR_EN_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP78_BR_TXPR_EN_BITS                     1
#define BRPHY0_GPHY_CORE_EXP78_BR_TXPR_EN_SHIFT                    14

/* BRPHY0_GPHY_CORE :: EXP78 :: BR_IRP_EN [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXP78_BR_IRP_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP78,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXP78_BR_IRP_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP78,0x2000,13)
#define BRPHY0_GPHY_CORE_EXP78_BR_IRP_EN_MASK                      0x2000
#define BRPHY0_GPHY_CORE_EXP78_BR_IRP_EN_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP78_BR_IRP_EN_BITS                      1
#define BRPHY0_GPHY_CORE_EXP78_BR_IRP_EN_SHIFT                     13

/* BRPHY0_GPHY_CORE :: EXP78 :: PTE_BYPASS_EN [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP78,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP78,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP78_PTE_BYPASS_EN_MASK                  0x1000
#define BRPHY0_GPHY_CORE_EXP78_PTE_BYPASS_EN_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP78_PTE_BYPASS_EN_BITS                  1
#define BRPHY0_GPHY_CORE_EXP78_PTE_BYPASS_EN_SHIFT                 12

/* BRPHY0_GPHY_CORE :: EXP78 :: PTE_DISTORT [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXP78_PTE_DISTORT(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP78,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXP78_PTE_DISTORT(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP78,0x800,11)
#define BRPHY0_GPHY_CORE_EXP78_PTE_DISTORT_MASK                    0x0800
#define BRPHY0_GPHY_CORE_EXP78_PTE_DISTORT_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP78_PTE_DISTORT_BITS                    1
#define BRPHY0_GPHY_CORE_EXP78_PTE_DISTORT_SHIFT                   11

/* BRPHY0_GPHY_CORE :: EXP78 :: LP_SEL [10:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP78_LP_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP78,0x700,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP78_LP_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP78,0x700,8)
#define BRPHY0_GPHY_CORE_EXP78_LP_SEL_MASK                         0x0700
#define BRPHY0_GPHY_CORE_EXP78_LP_SEL_ALIGN                        0
#define BRPHY0_GPHY_CORE_EXP78_LP_SEL_BITS                         3
#define BRPHY0_GPHY_CORE_EXP78_LP_SEL_SHIFT                        8

/* BRPHY0_GPHY_CORE :: EXP78 :: HP_PGA_BYPASS [07:04] */
#define Wr_BRPHY0_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP78,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP78,0xf0,4)
#define BRPHY0_GPHY_CORE_EXP78_HP_PGA_BYPASS_MASK                  0x00f0
#define BRPHY0_GPHY_CORE_EXP78_HP_PGA_BYPASS_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP78_HP_PGA_BYPASS_BITS                  4
#define BRPHY0_GPHY_CORE_EXP78_HP_PGA_BYPASS_SHIFT                 4

/* BRPHY0_GPHY_CORE :: EXP78 :: TDR_GAIN [03:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP78_TDR_GAIN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP78,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP78_TDR_GAIN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP78,0xf,0)
#define BRPHY0_GPHY_CORE_EXP78_TDR_GAIN_MASK                       0x000f
#define BRPHY0_GPHY_CORE_EXP78_TDR_GAIN_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP78_TDR_GAIN_BITS                       4
#define BRPHY0_GPHY_CORE_EXP78_TDR_GAIN_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP7B
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP7B :: I2C_CMD [15:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP7B_I2C_CMD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP7B,0xf000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP7B_I2C_CMD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP7B,0xf000,12)
#define BRPHY0_GPHY_CORE_EXP7B_I2C_CMD_MASK                        0xf000
#define BRPHY0_GPHY_CORE_EXP7B_I2C_CMD_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP7B_I2C_CMD_BITS                        4
#define BRPHY0_GPHY_CORE_EXP7B_I2C_CMD_SHIFT                       12

/* BRPHY0_GPHY_CORE :: EXP7B :: I2C_CTL [11:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP7B_I2C_CTL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP7B,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP7B_I2C_CTL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP7B,0xfff,0)
#define BRPHY0_GPHY_CORE_EXP7B_I2C_CTL_MASK                        0x0fff
#define BRPHY0_GPHY_CORE_EXP7B_I2C_CTL_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP7B_I2C_CTL_BITS                        12
#define BRPHY0_GPHY_CORE_EXP7B_I2C_CTL_SHIFT                       0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP7C
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP7C :: I2C_STATUS [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP7C_I2C_STATUS(x) WriteReg16(BRPHY0_GPHY_CORE_EXP7C,x)
#define Rd_BRPHY0_GPHY_CORE_EXP7C_I2C_STATUS(x) ReadReg16(BRPHY0_GPHY_CORE_EXP7C)
#define BRPHY0_GPHY_CORE_EXP7C_I2C_STATUS_MASK                     0xffff
#define BRPHY0_GPHY_CORE_EXP7C_I2C_STATUS_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP7C_I2C_STATUS_BITS                     16
#define BRPHY0_GPHY_CORE_EXP7C_I2C_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP7F
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP7F :: reserved0 [15:13] */
#define BRPHY0_GPHY_CORE_EXP7F_RESERVED0_MASK                      0xe000
#define BRPHY0_GPHY_CORE_EXP7F_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP7F_RESERVED0_BITS                      3
#define BRPHY0_GPHY_CORE_EXP7F_RESERVED0_SHIFT                     13

/* BRPHY0_GPHY_CORE :: EXP7F :: BR_PSD_PIN_DISABLE [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x1000,12)
#define BRPHY0_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_MASK             0x1000
#define BRPHY0_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_ALIGN            0
#define BRPHY0_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_BITS             1
#define BRPHY0_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_SHIFT            12

/* BRPHY0_GPHY_CORE :: EXP7F :: BR_PSD_OFF [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXP7F_BR_PSD_OFF(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXP7F_BR_PSD_OFF(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x800,11)
#define BRPHY0_GPHY_CORE_EXP7F_BR_PSD_OFF_MASK                     0x0800
#define BRPHY0_GPHY_CORE_EXP7F_BR_PSD_OFF_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP7F_BR_PSD_OFF_BITS                     1
#define BRPHY0_GPHY_CORE_EXP7F_BR_PSD_OFF_SHIFT                    11

/* BRPHY0_GPHY_CORE :: EXP7F :: ECD_DC_OFFSET [10:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x7fc,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x7fc,2)
#define BRPHY0_GPHY_CORE_EXP7F_ECD_DC_OFFSET_MASK                  0x07fc
#define BRPHY0_GPHY_CORE_EXP7F_ECD_DC_OFFSET_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXP7F_ECD_DC_OFFSET_BITS                  9
#define BRPHY0_GPHY_CORE_EXP7F_ECD_DC_OFFSET_SHIFT                 2

/* BRPHY0_GPHY_CORE :: EXP7F :: FIBER_UNIDIR_OV [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x2,1)
#define BRPHY0_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_MASK                0x0002
#define BRPHY0_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_BITS                1
#define BRPHY0_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_SHIFT               1

/* BRPHY0_GPHY_CORE :: EXP7F :: MACSEC_EN [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP7F_MACSEC_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP7F_MACSEC_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP7F,0x1,0)
#define BRPHY0_GPHY_CORE_EXP7F_MACSEC_EN_MASK                      0x0001
#define BRPHY0_GPHY_CORE_EXP7F_MACSEC_EN_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP7F_MACSEC_EN_BITS                      1
#define BRPHY0_GPHY_CORE_EXP7F_MACSEC_EN_SHIFT                     0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: ALIAS_18
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: ALIAS_18 :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_ALIAS_18_RESERVED0_MASK                   0xf000
#define BRPHY0_GPHY_CORE_ALIAS_18_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_ALIAS_18_RESERVED0_BITS                   4
#define BRPHY0_GPHY_CORE_ALIAS_18_RESERVED0_SHIFT                  12

/* BRPHY0_GPHY_CORE :: ALIAS_18 :: ALIAS [11:00] */
#define Wr_BRPHY0_GPHY_CORE_ALIAS_18_ALIAS(x) WriteRegBits16(BRPHY0_GPHY_CORE_ALIAS_18,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_ALIAS_18_ALIAS(x) ReadRegBits16(BRPHY0_GPHY_CORE_ALIAS_18,0xfff,0)
#define BRPHY0_GPHY_CORE_ALIAS_18_ALIAS_MASK                       0x0fff
#define BRPHY0_GPHY_CORE_ALIAS_18_ALIAS_ALIGN                      0
#define BRPHY0_GPHY_CORE_ALIAS_18_ALIAS_BITS                       12
#define BRPHY0_GPHY_CORE_ALIAS_18_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: ALIAS_19
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: ALIAS_19 :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_ALIAS_19_RESERVED0_MASK                   0xf000
#define BRPHY0_GPHY_CORE_ALIAS_19_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_ALIAS_19_RESERVED0_BITS                   4
#define BRPHY0_GPHY_CORE_ALIAS_19_RESERVED0_SHIFT                  12

/* BRPHY0_GPHY_CORE :: ALIAS_19 :: ALIAS [11:00] */
#define Wr_BRPHY0_GPHY_CORE_ALIAS_19_ALIAS(x) WriteRegBits16(BRPHY0_GPHY_CORE_ALIAS_19,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_ALIAS_19_ALIAS(x) ReadRegBits16(BRPHY0_GPHY_CORE_ALIAS_19,0xfff,0)
#define BRPHY0_GPHY_CORE_ALIAS_19_ALIAS_MASK                       0x0fff
#define BRPHY0_GPHY_CORE_ALIAS_19_ALIAS_ALIGN                      0
#define BRPHY0_GPHY_CORE_ALIAS_19_ALIAS_BITS                       12
#define BRPHY0_GPHY_CORE_ALIAS_19_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: ALIAS_1a
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: ALIAS_1a :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_ALIAS_1A_RESERVED0_MASK                   0xf000
#define BRPHY0_GPHY_CORE_ALIAS_1A_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_ALIAS_1A_RESERVED0_BITS                   4
#define BRPHY0_GPHY_CORE_ALIAS_1A_RESERVED0_SHIFT                  12

/* BRPHY0_GPHY_CORE :: ALIAS_1a :: ALIAS [11:00] */
#define Wr_BRPHY0_GPHY_CORE_ALIAS_1a_ALIAS(x) WriteRegBits16(BRPHY0_GPHY_CORE_ALIAS_1A,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_ALIAS_1a_ALIAS(x) ReadRegBits16(BRPHY0_GPHY_CORE_ALIAS_1A,0xfff,0)
#define BRPHY0_GPHY_CORE_ALIAS_1A_ALIAS_MASK                       0x0fff
#define BRPHY0_GPHY_CORE_ALIAS_1A_ALIAS_ALIGN                      0
#define BRPHY0_GPHY_CORE_ALIAS_1A_ALIAS_BITS                       12
#define BRPHY0_GPHY_CORE_ALIAS_1A_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: ALIAS_1b
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: ALIAS_1b :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_ALIAS_1B_RESERVED0_MASK                   0xf000
#define BRPHY0_GPHY_CORE_ALIAS_1B_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_ALIAS_1B_RESERVED0_BITS                   4
#define BRPHY0_GPHY_CORE_ALIAS_1B_RESERVED0_SHIFT                  12

/* BRPHY0_GPHY_CORE :: ALIAS_1b :: ALIAS [11:00] */
#define Wr_BRPHY0_GPHY_CORE_ALIAS_1b_ALIAS(x) WriteRegBits16(BRPHY0_GPHY_CORE_ALIAS_1B,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_ALIAS_1b_ALIAS(x) ReadRegBits16(BRPHY0_GPHY_CORE_ALIAS_1B,0xfff,0)
#define BRPHY0_GPHY_CORE_ALIAS_1B_ALIAS_MASK                       0x0fff
#define BRPHY0_GPHY_CORE_ALIAS_1B_ALIAS_ALIGN                      0
#define BRPHY0_GPHY_CORE_ALIAS_1B_ALIAS_BITS                       12
#define BRPHY0_GPHY_CORE_ALIAS_1B_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: ALIAS_1c
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: ALIAS_1c :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_ALIAS_1C_RESERVED0_MASK                   0xf000
#define BRPHY0_GPHY_CORE_ALIAS_1C_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_ALIAS_1C_RESERVED0_BITS                   4
#define BRPHY0_GPHY_CORE_ALIAS_1C_RESERVED0_SHIFT                  12

/* BRPHY0_GPHY_CORE :: ALIAS_1c :: ALIAS [11:00] */
#define Wr_BRPHY0_GPHY_CORE_ALIAS_1c_ALIAS(x) WriteRegBits16(BRPHY0_GPHY_CORE_ALIAS_1C,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_ALIAS_1c_ALIAS(x) ReadRegBits16(BRPHY0_GPHY_CORE_ALIAS_1C,0xfff,0)
#define BRPHY0_GPHY_CORE_ALIAS_1C_ALIAS_MASK                       0x0fff
#define BRPHY0_GPHY_CORE_ALIAS_1C_ALIAS_ALIGN                      0
#define BRPHY0_GPHY_CORE_ALIAS_1C_ALIAS_BITS                       12
#define BRPHY0_GPHY_CORE_ALIAS_1C_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: ALIAS_1d
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: ALIAS_1d :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_ALIAS_1D_RESERVED0_MASK                   0xf000
#define BRPHY0_GPHY_CORE_ALIAS_1D_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_ALIAS_1D_RESERVED0_BITS                   4
#define BRPHY0_GPHY_CORE_ALIAS_1D_RESERVED0_SHIFT                  12

/* BRPHY0_GPHY_CORE :: ALIAS_1d :: ALIAS [11:00] */
#define Wr_BRPHY0_GPHY_CORE_ALIAS_1d_ALIAS(x) WriteRegBits16(BRPHY0_GPHY_CORE_ALIAS_1D,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_ALIAS_1d_ALIAS(x) ReadRegBits16(BRPHY0_GPHY_CORE_ALIAS_1D,0xfff,0)
#define BRPHY0_GPHY_CORE_ALIAS_1D_ALIAS_MASK                       0x0fff
#define BRPHY0_GPHY_CORE_ALIAS_1D_ALIAS_ALIGN                      0
#define BRPHY0_GPHY_CORE_ALIAS_1D_ALIAS_BITS                       12
#define BRPHY0_GPHY_CORE_ALIAS_1D_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: REG_MAP_CTL
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: REG_MAP_CTL :: REG_LEGACY_EN [15:15] */
#define Wr_BRPHY0_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_REG_MAP_CTL,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_REG_MAP_CTL,0x8000,15)
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_MASK            0x8000
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_BITS            1
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_SHIFT           15

/* BRPHY0_GPHY_CORE :: REG_MAP_CTL :: ALIAS_MODE [14:13] */
#define Wr_BRPHY0_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_REG_MAP_CTL,0x6000,13,x)
#define Rd_BRPHY0_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_REG_MAP_CTL,0x6000,13)
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_MASK               0x6000
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_ALIGN              0
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_BITS               2
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_SHIFT              13

/* BRPHY0_GPHY_CORE :: REG_MAP_CTL :: reserved0 [12:12] */
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_RESERVED0_MASK                0x1000
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_RESERVED0_ALIGN               0
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_RESERVED0_BITS                1
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_RESERVED0_SHIFT               12

/* BRPHY0_GPHY_CORE :: REG_MAP_CTL :: RANGE_OFFSET [11:00] */
#define Wr_BRPHY0_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) WriteRegBits16(BRPHY0_GPHY_CORE_REG_MAP_CTL,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) ReadRegBits16(BRPHY0_GPHY_CORE_REG_MAP_CTL,0xfff,0)
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_MASK             0x0fff
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_ALIGN            0
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_BITS             12
#define BRPHY0_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_SHIFT            0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP98
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP98 :: reserved0 [15:11] */
#define BRPHY0_GPHY_CORE_EXP98_RESERVED0_MASK                      0xf800
#define BRPHY0_GPHY_CORE_EXP98_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXP98_RESERVED0_BITS                      5
#define BRPHY0_GPHY_CORE_EXP98_RESERVED0_SHIFT                     11

/* BRPHY0_GPHY_CORE :: EXP98 :: RC_CAL [10:06] */
#define Wr_BRPHY0_GPHY_CORE_EXP98_RC_CAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP98,0x7c0,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXP98_RC_CAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP98,0x7c0,6)
#define BRPHY0_GPHY_CORE_EXP98_RC_CAL_MASK                         0x07c0
#define BRPHY0_GPHY_CORE_EXP98_RC_CAL_ALIGN                        0
#define BRPHY0_GPHY_CORE_EXP98_RC_CAL_BITS                         5
#define BRPHY0_GPHY_CORE_EXP98_RC_CAL_SHIFT                        6

/* BRPHY0_GPHY_CORE :: EXP98 :: R_CAL [05:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP98_R_CAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP98,0x3e,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP98_R_CAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP98,0x3e,1)
#define BRPHY0_GPHY_CORE_EXP98_R_CAL_MASK                          0x003e
#define BRPHY0_GPHY_CORE_EXP98_R_CAL_ALIGN                         0
#define BRPHY0_GPHY_CORE_EXP98_R_CAL_BITS                          5
#define BRPHY0_GPHY_CORE_EXP98_R_CAL_SHIFT                         1

/* BRPHY0_GPHY_CORE :: EXP98 :: CAL_DONE [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP98_CAL_DONE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP98,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP98_CAL_DONE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP98,0x1,0)
#define BRPHY0_GPHY_CORE_EXP98_CAL_DONE_MASK                       0x0001
#define BRPHY0_GPHY_CORE_EXP98_CAL_DONE_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP98_CAL_DONE_BITS                       1
#define BRPHY0_GPHY_CORE_EXP98_CAL_DONE_SHIFT                      0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXP9C
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXP9C :: MII_REG1C_BNK1 [15:12] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0xf000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0xf000,12)
#define BRPHY0_GPHY_CORE_EXP9C_MII_REG1C_BNK1_MASK                 0xf000
#define BRPHY0_GPHY_CORE_EXP9C_MII_REG1C_BNK1_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP9C_MII_REG1C_BNK1_BITS                 4
#define BRPHY0_GPHY_CORE_EXP9C_MII_REG1C_BNK1_SHIFT                12

/* BRPHY0_GPHY_CORE :: EXP9C :: RSMII_LOAD_XMT [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x800,11)
#define BRPHY0_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_MASK                 0x0800
#define BRPHY0_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_BITS                 1
#define BRPHY0_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_SHIFT                11

/* BRPHY0_GPHY_CORE :: EXP9C :: FIFO_OV_UN [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_FIFO_OV_UN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_FIFO_OV_UN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x400,10)
#define BRPHY0_GPHY_CORE_EXP9C_FIFO_OV_UN_MASK                     0x0400
#define BRPHY0_GPHY_CORE_EXP9C_FIFO_OV_UN_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP9C_FIFO_OV_UN_BITS                     1
#define BRPHY0_GPHY_CORE_EXP9C_FIFO_OV_UN_SHIFT                    10

/* BRPHY0_GPHY_CORE :: EXP9C :: TEST_EN [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_TEST_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_TEST_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x200,9)
#define BRPHY0_GPHY_CORE_EXP9C_TEST_EN_MASK                        0x0200
#define BRPHY0_GPHY_CORE_EXP9C_TEST_EN_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXP9C_TEST_EN_BITS                        1
#define BRPHY0_GPHY_CORE_EXP9C_TEST_EN_SHIFT                       9

/* BRPHY0_GPHY_CORE :: EXP9C :: PTEST [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_PTEST(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_PTEST(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x100,8)
#define BRPHY0_GPHY_CORE_EXP9C_PTEST_MASK                          0x0100
#define BRPHY0_GPHY_CORE_EXP9C_PTEST_ALIGN                         0
#define BRPHY0_GPHY_CORE_EXP9C_PTEST_BITS                          1
#define BRPHY0_GPHY_CORE_EXP9C_PTEST_SHIFT                         8

/* BRPHY0_GPHY_CORE :: EXP9C :: EXRMIIFE [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_EXRMIIFE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_EXRMIIFE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x80,7)
#define BRPHY0_GPHY_CORE_EXP9C_EXRMIIFE_MASK                       0x0080
#define BRPHY0_GPHY_CORE_EXP9C_EXRMIIFE_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXP9C_EXRMIIFE_BITS                       1
#define BRPHY0_GPHY_CORE_EXP9C_EXRMIIFE_SHIFT                      7

/* BRPHY0_GPHY_CORE :: EXP9C :: FIFO_SIZE_CNTL [06:03] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x78,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x78,3)
#define BRPHY0_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_MASK                 0x0078
#define BRPHY0_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_ALIGN                0
#define BRPHY0_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_BITS                 4
#define BRPHY0_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_SHIFT                3

/* BRPHY0_GPHY_CORE :: EXP9C :: BIG_FIFO_EN [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x4,2)
#define BRPHY0_GPHY_CORE_EXP9C_BIG_FIFO_EN_MASK                    0x0004
#define BRPHY0_GPHY_CORE_EXP9C_BIG_FIFO_EN_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXP9C_BIG_FIFO_EN_BITS                    1
#define BRPHY0_GPHY_CORE_EXP9C_BIG_FIFO_EN_SHIFT                   2

/* BRPHY0_GPHY_CORE :: EXP9C :: SMII_S3MII_MODE [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x2,1)
#define BRPHY0_GPHY_CORE_EXP9C_SMII_S3MII_MODE_MASK                0x0002
#define BRPHY0_GPHY_CORE_EXP9C_SMII_S3MII_MODE_ALIGN               0
#define BRPHY0_GPHY_CORE_EXP9C_SMII_S3MII_MODE_BITS                1
#define BRPHY0_GPHY_CORE_EXP9C_SMII_S3MII_MODE_SHIFT               1

/* BRPHY0_GPHY_CORE :: EXP9C :: SSSMII_DIS [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXP9C_SSSMII_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXP9C_SSSMII_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXP9C,0x1,0)
#define BRPHY0_GPHY_CORE_EXP9C_SSSMII_DIS_MASK                     0x0001
#define BRPHY0_GPHY_CORE_EXP9C_SSSMII_DIS_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXP9C_SSSMII_DIS_BITS                     1
#define BRPHY0_GPHY_CORE_EXP9C_SSSMII_DIS_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: BT_LINK_FIX
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: BT_LINK_FIX :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RESERVED0_MASK                0x8000
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RESERVED0_ALIGN               0
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RESERVED0_BITS                1
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RESERVED0_SHIFT               15

/* BRPHY0_GPHY_CORE :: BT_LINK_FIX :: rxc_byp_rclk_dll_div2 [14:14] */
#define Wr_BRPHY0_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) WriteRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) ReadRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0x4000,14)
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_MASK    0x4000
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_ALIGN   0
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_BITS    1
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_SHIFT   14

/* BRPHY0_GPHY_CORE :: BT_LINK_FIX :: rxc_shamoo_tst_en [13:13] */
#define Wr_BRPHY0_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) WriteRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) ReadRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0x2000,13)
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_MASK        0x2000
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_ALIGN       0
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_BITS        1
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_SHIFT       13

/* BRPHY0_GPHY_CORE :: BT_LINK_FIX :: sig_10bt_upp_limit [12:08] */
#define Wr_BRPHY0_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) WriteRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0x1f00,8,x)
#define Rd_BRPHY0_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) ReadRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0x1f00,8)
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_MASK       0x1f00
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_ALIGN      0
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_BITS       5
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_SHIFT      8

/* BRPHY0_GPHY_CORE :: BT_LINK_FIX :: threshold_2mhz [07:01] */
#define Wr_BRPHY0_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) WriteRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0xfe,1,x)
#define Rd_BRPHY0_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) ReadRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0xfe,1)
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_MASK           0x00fe
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_ALIGN          0
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_BITS           7
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_SHIFT          1

/* BRPHY0_GPHY_CORE :: BT_LINK_FIX :: break_link10bt_disable [00:00] */
#define Wr_BRPHY0_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) WriteRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) ReadRegBits16(BRPHY0_GPHY_CORE_BT_LINK_FIX,0x1,0)
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_MASK   0x0001
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_ALIGN  0
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_BITS   1
#define BRPHY0_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_SHIFT  0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SYNCE_PLUS_DBG
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_DBG [15:02] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_MASK             0xfffc
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_ALIGN            0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_BITS             14
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_SHIFT            2

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_BRUTEFORCE_TM [01:01] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_MASK   0x0002
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_ALIGN  0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_BITS   1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_SHIFT  1

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_HSTIMEOUT_CTL [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_MASK   0x0001
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_ALIGN  0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_BITS   1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_SHIFT  0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: SYNCE_PLUS
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: TIMING_CONFIG [15:15] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x8000,15)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_MASK             0x8000
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_ALIGN            0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_BITS             1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_SHIFT            15

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_ONGOING [14:14] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x4000,14)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_MASK     0x4000
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_ALIGN    0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_BITS     1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_SHIFT    14

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: SYNCE_AUTO_ACK [13:13] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x2000,13)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_MASK            0x2000
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_ALIGN           0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_BITS            1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_SHIFT           13

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: SYNCE_WAIT_FOR_IDLE [12:12] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x1000,12)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_MASK       0x1000
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_ALIGN      0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_BITS       1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_SHIFT      12

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_COMPLETE [11:11] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x800,11)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_MASK    0x0800
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_ALIGN   0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_BITS    1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_SHIFT   11

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_PENDING [10:10] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x400,10)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_MASK     0x0400
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_ALIGN    0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_BITS     1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_SHIFT    10

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ERROR_STATUS [09:08] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x300,8,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x300,8)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_MASK        0x0300
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_ALIGN       0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_BITS        2
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_SHIFT       8

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_FAIL [07:07] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x80,7)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_MASK        0x0080
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_ALIGN       0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_BITS        1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_SHIFT       7

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: SYNCE_FTIMEOUT_CTL [06:06] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x40,6)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_MASK        0x0040
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_ALIGN       0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_BITS        1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_SHIFT       6

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: SYNCE_DBG_MUX_CTL [05:04] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x30,4,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x30,4)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_MASK         0x0030
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_ALIGN        0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_BITS         2
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_SHIFT        4

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: SYNCE_INTERRUPT_MASK [03:02] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0xc,2,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0xc,2)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_MASK      0x000c
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_ALIGN     0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_BITS      2
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_SHIFT     2

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: SYNCE_TIMING_SWITCH_START [01:01] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x2,1)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_MASK 0x0002
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_ALIGN 0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_BITS 1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_SHIFT 1

/* BRPHY0_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ENABLE [00:00] */
#define Wr_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_SYNCE_PLUS,0x1,0)
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_MASK              0x0001
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_ALIGN             0
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_BITS              1
#define BRPHY0_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_SHIFT             0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPA8
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPA8 :: ADAPTIVE_BIAS_CTRL [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) WriteReg16(BRPHY0_GPHY_CORE_EXPA8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) ReadReg16(BRPHY0_GPHY_CORE_EXPA8)
#define BRPHY0_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_MASK             0xffff
#define BRPHY0_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_BITS             16
#define BRPHY0_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_SHIFT            0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPA9
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPA9 :: SPARE_REG [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPA9_SPARE_REG(x) WriteReg16(BRPHY0_GPHY_CORE_EXPA9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPA9_SPARE_REG(x) ReadReg16(BRPHY0_GPHY_CORE_EXPA9)
#define BRPHY0_GPHY_CORE_EXPA9_SPARE_REG_MASK                      0xffff
#define BRPHY0_GPHY_CORE_EXPA9_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPA9_SPARE_REG_BITS                      16
#define BRPHY0_GPHY_CORE_EXPA9_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPAA
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPAA :: STATISTIC_TIMER_12HOURS_LPI [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) WriteReg16(BRPHY0_GPHY_CORE_EXPAA,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) ReadReg16(BRPHY0_GPHY_CORE_EXPAA)
#define BRPHY0_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_MASK    0xffff
#define BRPHY0_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_ALIGN   0
#define BRPHY0_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_BITS    16
#define BRPHY0_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_SHIFT   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPAB
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPAB :: STATISTIC_TIMER_12HOURS_LOCAL [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) WriteReg16(BRPHY0_GPHY_CORE_EXPAB,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) ReadReg16(BRPHY0_GPHY_CORE_EXPAB)
#define BRPHY0_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_MASK  0xffff
#define BRPHY0_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_ALIGN 0
#define BRPHY0_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_BITS  16
#define BRPHY0_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_SHIFT 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPAC
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPAC :: STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY0_GPHY_CORE_EXPAC,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY0_GPHY_CORE_EXPAC)
#define BRPHY0_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY0_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY0_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY0_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPAD
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPAD :: STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY0_GPHY_CORE_EXPAD,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY0_GPHY_CORE_EXPAD)
#define BRPHY0_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY0_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY0_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY0_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPAE
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPAE :: SPARE_REG [15:09] */
#define Wr_BRPHY0_GPHY_CORE_EXPAE_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAE,0xfe00,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAE_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAE,0xfe00,9)
#define BRPHY0_GPHY_CORE_EXPAE_SPARE_REG_MASK                      0xfe00
#define BRPHY0_GPHY_CORE_EXPAE_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPAE_SPARE_REG_BITS                      7
#define BRPHY0_GPHY_CORE_EXPAE_SPARE_REG_SHIFT                     9

/* BRPHY0_GPHY_CORE :: EXPAE :: TXBIAS_VAL2 [08:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAE,0x1e0,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAE,0x1e0,5)
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL2_MASK                    0x01e0
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL2_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL2_BITS                    4
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL2_SHIFT                   5

/* BRPHY0_GPHY_CORE :: EXPAE :: TXBIAS_VAL1 [04:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAE,0x1e,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAE,0x1e,1)
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL1_MASK                    0x001e
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL1_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL1_BITS                    4
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_VAL1_SHIFT                   1

/* BRPHY0_GPHY_CORE :: EXPAE :: TXBIAS_PLUS_MODE [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAE,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAE,0x1,0)
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_MASK               0x0001
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_BITS               1
#define BRPHY0_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPAF
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPAF :: STATISTIC_1000BT_MODE [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x8000,15)
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_MASK          0x8000
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_ALIGN         0
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_BITS          1
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_SHIFT         15

/* BRPHY0_GPHY_CORE :: EXPAF :: STATISTIC_UPPER_16BITS_SEL [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x4000,14)
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_MASK     0x4000
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_ALIGN    0
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_BITS     1
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_SHIFT    14

/* BRPHY0_GPHY_CORE :: EXPAF :: STATISTIC_SATURATE_MODE [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x2000,13)
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_MASK        0x2000
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_ALIGN       0
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_BITS        1
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_SHIFT       13

/* BRPHY0_GPHY_CORE :: EXPAF :: STATISTIC_ACCESS_MODE [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_MASK          0x1000
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_ALIGN         0
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_BITS          1
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_SHIFT         12

/* BRPHY0_GPHY_CORE :: EXPAF :: SPARE_REG [11:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0xfe0,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0xfe0,5)
#define BRPHY0_GPHY_CORE_EXPAF_SPARE_REG_MASK                      0x0fe0
#define BRPHY0_GPHY_CORE_EXPAF_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPAF_SPARE_REG_BITS                      7
#define BRPHY0_GPHY_CORE_EXPAF_SPARE_REG_SHIFT                     5

/* BRPHY0_GPHY_CORE :: EXPAF :: EEE_REM_RCVR_STATUS_DIS [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x10,4)
#define BRPHY0_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_MASK        0x0010
#define BRPHY0_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY0_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_BITS        1
#define BRPHY0_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_SHIFT       4

/* BRPHY0_GPHY_CORE :: EXPAF :: EEE_LOC_RCVR_STATUS_DIS [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x8,3)
#define BRPHY0_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_MASK        0x0008
#define BRPHY0_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY0_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_BITS        1
#define BRPHY0_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_SHIFT       3

/* BRPHY0_GPHY_CORE :: EXPAF :: STATISTIC_ADAPTX_EN [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x4,2)
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_MASK            0x0004
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_ALIGN           0
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_BITS            1
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_SHIFT           2

/* BRPHY0_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_RESET [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x2,1)
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_MASK       0x0002
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_ALIGN      0
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_BITS       1
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_SHIFT      1

/* BRPHY0_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_ENABLE [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPAF,0x1,0)
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_MASK      0x0001
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_ALIGN     0
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_BITS      1
#define BRPHY0_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_SHIFT     0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPB0
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPB0 :: BIAS_CTL_0 [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPB0_BIAS_CTL_0(x) WriteReg16(BRPHY0_GPHY_CORE_EXPB0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPB0_BIAS_CTL_0(x) ReadReg16(BRPHY0_GPHY_CORE_EXPB0)
#define BRPHY0_GPHY_CORE_EXPB0_BIAS_CTL_0_MASK                     0xffff
#define BRPHY0_GPHY_CORE_EXPB0_BIAS_CTL_0_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPB0_BIAS_CTL_0_BITS                     16
#define BRPHY0_GPHY_CORE_EXPB0_BIAS_CTL_0_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPB1
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPB1 :: BIAS_CTL_1 [15:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPB1_BIAS_CTL_1(x) WriteReg16(BRPHY0_GPHY_CORE_EXPB1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPB1_BIAS_CTL_1(x) ReadReg16(BRPHY0_GPHY_CORE_EXPB1)
#define BRPHY0_GPHY_CORE_EXPB1_BIAS_CTL_1_MASK                     0xffff
#define BRPHY0_GPHY_CORE_EXPB1_BIAS_CTL_1_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPB1_BIAS_CTL_1_BITS                     16
#define BRPHY0_GPHY_CORE_EXPB1_BIAS_CTL_1_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPB2
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPB2 :: CLK200_SEL_OV [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPB2,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPB2,0x8000,15)
#define BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_OV_MASK                  0x8000
#define BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_OV_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_OV_BITS                  1
#define BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_OV_SHIFT                 15

/* BRPHY0_GPHY_CORE :: EXPB2 :: CLK200_SEL [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPB2,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPB2,0x4000,14)
#define BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_MASK                     0x4000
#define BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_BITS                     1
#define BRPHY0_GPHY_CORE_EXPB2_CLK200_SEL_SHIFT                    14

/* BRPHY0_GPHY_CORE :: EXPB2 :: CK25_SEL [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPB2_CK25_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPB2,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPB2_CK25_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPB2,0x2000,13)
#define BRPHY0_GPHY_CORE_EXPB2_CK25_SEL_MASK                       0x2000
#define BRPHY0_GPHY_CORE_EXPB2_CK25_SEL_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXPB2_CK25_SEL_BITS                       1
#define BRPHY0_GPHY_CORE_EXPB2_CK25_SEL_SHIFT                      13

/* BRPHY0_GPHY_CORE :: EXPB2 :: REG_B2_SPARE [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPB2_REG_B2_SPARE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPB2,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPB2_REG_B2_SPARE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPB2,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPB2_REG_B2_SPARE_MASK                   0x1000
#define BRPHY0_GPHY_CORE_EXPB2_REG_B2_SPARE_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPB2_REG_B2_SPARE_BITS                   1
#define BRPHY0_GPHY_CORE_EXPB2_REG_B2_SPARE_SHIFT                  12

/* BRPHY0_GPHY_CORE :: EXPB2 :: I_RC_OFFSET_PHY [11:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPB2,0xf00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPB2,0xf00,8)
#define BRPHY0_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_MASK                0x0f00
#define BRPHY0_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_BITS                4
#define BRPHY0_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_SHIFT               8

/* BRPHY0_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_1000_100 [07:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPB2,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPB2,0xf0,4)
#define BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_MASK        0x00f0
#define BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_ALIGN       0
#define BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_BITS        4
#define BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_SHIFT       4

/* BRPHY0_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_10 [03:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPB2,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPB2,0xf,0)
#define BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_MASK              0x000f
#define BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_BITS              4
#define BRPHY0_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_SHIFT             0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE3
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE3,0xff00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE3,0xff00,8)
#define BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_100_MASK                 0xff00
#define BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_100_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_100_BITS                 8
#define BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_100_SHIFT                8

/* BRPHY0_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE3,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE3,0xff,0)
#define BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_BITS                8
#define BRPHY0_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE4
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE4 :: TX_PCS_SOP_TSYNC_ERR [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE4,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE4,0x8000,15)
#define BRPHY0_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_MASK           0x8000
#define BRPHY0_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_BITS           1
#define BRPHY0_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_SHIFT          15

/* BRPHY0_GPHY_CORE :: EXPE4 :: reserved0 [14:12] */
#define BRPHY0_GPHY_CORE_EXPE4_RESERVED0_MASK                      0x7000
#define BRPHY0_GPHY_CORE_EXPE4_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPE4_RESERVED0_BITS                      3
#define BRPHY0_GPHY_CORE_EXPE4_RESERVED0_SHIFT                     12

/* BRPHY0_GPHY_CORE :: EXPE4 :: TX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE4,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE4,0xfff,0)
#define BRPHY0_GPHY_CORE_EXPE4_TX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY0_GPHY_CORE_EXPE4_TX_PCS_DLY_10_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXPE4_TX_PCS_DLY_10_BITS                  12
#define BRPHY0_GPHY_CORE_EXPE4_TX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE5
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE5,0xff00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE5,0xff00,8)
#define BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_BITS               8
#define BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_SHIFT              8

/* BRPHY0_GPHY_CORE :: EXPE5 :: reserved0 [07:07] */
#define BRPHY0_GPHY_CORE_EXPE5_RESERVED0_MASK                      0x0080
#define BRPHY0_GPHY_CORE_EXPE5_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPE5_RESERVED0_BITS                      1
#define BRPHY0_GPHY_CORE_EXPE5_RESERVED0_SHIFT                     7

/* BRPHY0_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE5,0x7f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE5,0x7f,0)
#define BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_BITS               7
#define BRPHY0_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE6
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE6,0xff00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE6,0xff00,8)
#define BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_100_MASK                 0xff00
#define BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_100_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_100_BITS                 8
#define BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_100_SHIFT                8

/* BRPHY0_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE6,0xff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE6,0xff,0)
#define BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_BITS                8
#define BRPHY0_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE7
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE7 :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_EXPE7_RESERVED0_MASK                      0xf000
#define BRPHY0_GPHY_CORE_EXPE7_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPE7_RESERVED0_BITS                      4
#define BRPHY0_GPHY_CORE_EXPE7_RESERVED0_SHIFT                     12

/* BRPHY0_GPHY_CORE :: EXPE7 :: RX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE7,0xfff,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE7,0xfff,0)
#define BRPHY0_GPHY_CORE_EXPE7_RX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY0_GPHY_CORE_EXPE7_RX_PCS_DLY_10_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXPE7_RX_PCS_DLY_10_BITS                  12
#define BRPHY0_GPHY_CORE_EXPE7_RX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE8
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE8,0xff00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE8,0xff00,8)
#define BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_BITS               8
#define BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_SHIFT              8

/* BRPHY0_GPHY_CORE :: EXPE8 :: reserved0 [07:07] */
#define BRPHY0_GPHY_CORE_EXPE8_RESERVED0_MASK                      0x0080
#define BRPHY0_GPHY_CORE_EXPE8_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPE8_RESERVED0_BITS                      1
#define BRPHY0_GPHY_CORE_EXPE8_RESERVED0_SHIFT                     7

/* BRPHY0_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE8,0x7f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE8,0x7f,0)
#define BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_BITS               7
#define BRPHY0_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE9
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE9 :: reserved0 [15:14] */
#define BRPHY0_GPHY_CORE_EXPE9_RESERVED0_MASK                      0xc000
#define BRPHY0_GPHY_CORE_EXPE9_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPE9_RESERVED0_BITS                      2
#define BRPHY0_GPHY_CORE_EXPE9_RESERVED0_SHIFT                     14

/* BRPHY0_GPHY_CORE :: EXPE9 :: P1588_TX_DLY_CYCLE [13:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE9,0x3f00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE9,0x3f00,8)
#define BRPHY0_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_MASK             0x3f00
#define BRPHY0_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_BITS             6
#define BRPHY0_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_SHIFT            8

/* BRPHY0_GPHY_CORE :: EXPE9 :: reserved1 [07:06] */
#define BRPHY0_GPHY_CORE_EXPE9_RESERVED1_MASK                      0x00c0
#define BRPHY0_GPHY_CORE_EXPE9_RESERVED1_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPE9_RESERVED1_BITS                      2
#define BRPHY0_GPHY_CORE_EXPE9_RESERVED1_SHIFT                     6

/* BRPHY0_GPHY_CORE :: EXPE9 :: P1588_RX_DLY_CYCLE [05:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE9,0x3f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE9,0x3f,0)
#define BRPHY0_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_MASK             0x003f
#define BRPHY0_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_BITS             6
#define BRPHY0_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_SHIFT            0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE0
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_10 [15:10] */
#define Wr_BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE0,0xfc00,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE0,0xfc00,10)
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_MASK              0xfc00
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_BITS              6
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_SHIFT             10

/* BRPHY0_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_100 [09:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE0,0x3e0,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE0,0x3e0,5)
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_MASK             0x03e0
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_BITS             5
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_SHIFT            5

/* BRPHY0_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_1000 [04:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE0,0x1f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE0,0x1f,0)
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_MASK            0x001f
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_ALIGN           0
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_BITS            5
#define BRPHY0_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_SHIFT           0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE1
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE1 :: reserved0 [15:12] */
#define BRPHY0_GPHY_CORE_EXPE1_RESERVED0_MASK                      0xf000
#define BRPHY0_GPHY_CORE_EXPE1_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPE1_RESERVED0_BITS                      4
#define BRPHY0_GPHY_CORE_EXPE1_RESERVED0_SHIFT                     12

/* BRPHY0_GPHY_CORE :: EXPE1 :: RX_PMA_PMD_DLY_FIBER [11:06] */
#define Wr_BRPHY0_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE1,0xfc0,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE1,0xfc0,6)
#define BRPHY0_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_MASK           0x0fc0
#define BRPHY0_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY0_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_SHIFT          6

/* BRPHY0_GPHY_CORE :: EXPE1 :: TX_PMA_PMD_DLY_FIBER [05:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE1,0x3f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE1,0x3f,0)
#define BRPHY0_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_MASK           0x003f
#define BRPHY0_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY0_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_SHIFT          0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPE2
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPE2 :: reserved0 [15:14] */
#define BRPHY0_GPHY_CORE_EXPE2_RESERVED0_MASK                      0xc000
#define BRPHY0_GPHY_CORE_EXPE2_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPE2_RESERVED0_BITS                      2
#define BRPHY0_GPHY_CORE_EXPE2_RESERVED0_SHIFT                     14

/* BRPHY0_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_10 [13:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE2,0x3f80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE2,0x3f80,7)
#define BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_MASK              0x3f80
#define BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_BITS              7
#define BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_SHIFT             7

/* BRPHY0_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_100_1000 [06:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPE2,0x7f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPE2,0x7f,0)
#define BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_MASK        0x007f
#define BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_ALIGN       0
#define BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_BITS        7
#define BRPHY0_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_SHIFT       0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPEA
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPEA :: reserved0 [15:13] */
#define BRPHY0_GPHY_CORE_EXPEA_RESERVED0_MASK                      0xe000
#define BRPHY0_GPHY_CORE_EXPEA_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPEA_RESERVED0_BITS                      3
#define BRPHY0_GPHY_CORE_EXPEA_RESERVED0_SHIFT                     13

/* BRPHY0_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MAX_DLY_CYCLE [12:10] */
#define Wr_BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPEA,0x1c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPEA,0x1c00,10)
#define BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x1c00
#define BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      10

/* BRPHY0_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MIN_DLY_CYCLE [09:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPEA,0x380,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPEA,0x380,7)
#define BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x0380
#define BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY0_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      7

/* BRPHY0_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MAX_DLY_CYCLE [06:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPEA,0x70,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPEA,0x70,4)
#define BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x0070
#define BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      4

/* BRPHY0_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MIN_DLY_CYCLE [03:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPEA,0xe,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPEA,0xe,1)
#define BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x000e
#define BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY0_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      1

/* BRPHY0_GPHY_CORE :: EXPEA :: FEATURE_802_3BF_ENABLE [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPEA,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPEA,0x1,0)
#define BRPHY0_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_MASK         0x0001
#define BRPHY0_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_ALIGN        0
#define BRPHY0_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_BITS         1
#define BRPHY0_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_SHIFT        0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: LED_PRA_MODE
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: LED_PRA_MODE :: reserved0 [15:04] */
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_RESERVED0_MASK               0xfff0
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_RESERVED0_ALIGN              0
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_RESERVED0_BITS               12
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_RESERVED0_SHIFT              4

/* BRPHY0_GPHY_CORE :: LED_PRA_MODE :: SAT_MODE [03:03] */
#define Wr_BRPHY0_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_LED_PRA_MODE,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_LED_PRA_MODE,0x8,3)
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_SAT_MODE_MASK                0x0008
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_SAT_MODE_ALIGN               0
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_SAT_MODE_BITS                1
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_SAT_MODE_SHIFT               3

/* BRPHY0_GPHY_CORE :: LED_PRA_MODE :: PRA_MODE [02:00] */
#define Wr_BRPHY0_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_LED_PRA_MODE,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_LED_PRA_MODE,0x7,0)
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_PRA_MODE_MASK                0x0007
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_PRA_MODE_ALIGN               0
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_PRA_MODE_BITS                3
#define BRPHY0_GPHY_CORE_LED_PRA_MODE_PRA_MODE_SHIFT               0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: FIFO_CTL
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: FIFO_CTL :: SFT_RST [15:15] */
#define Wr_BRPHY0_GPHY_CORE_FIFO_CTL_SFT_RST(x) WriteRegBits16(BRPHY0_GPHY_CORE_FIFO_CTL,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_FIFO_CTL_SFT_RST(x) ReadRegBits16(BRPHY0_GPHY_CORE_FIFO_CTL,0x8000,15)
#define BRPHY0_GPHY_CORE_FIFO_CTL_SFT_RST_MASK                     0x8000
#define BRPHY0_GPHY_CORE_FIFO_CTL_SFT_RST_ALIGN                    0
#define BRPHY0_GPHY_CORE_FIFO_CTL_SFT_RST_BITS                     1
#define BRPHY0_GPHY_CORE_FIFO_CTL_SFT_RST_SHIFT                    15

/* BRPHY0_GPHY_CORE :: FIFO_CTL :: reserved0 [14:09] */
#define BRPHY0_GPHY_CORE_FIFO_CTL_RESERVED0_MASK                   0x7e00
#define BRPHY0_GPHY_CORE_FIFO_CTL_RESERVED0_ALIGN                  0
#define BRPHY0_GPHY_CORE_FIFO_CTL_RESERVED0_BITS                   6
#define BRPHY0_GPHY_CORE_FIFO_CTL_RESERVED0_SHIFT                  9

/* BRPHY0_GPHY_CORE :: FIFO_CTL :: WRBLOCK_MODE [08:08] */
#define Wr_BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) WriteRegBits16(BRPHY0_GPHY_CORE_FIFO_CTL,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) ReadRegBits16(BRPHY0_GPHY_CORE_FIFO_CTL,0x100,8)
#define BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_MASK                0x0100
#define BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_ALIGN               0
#define BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_BITS                1
#define BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_SHIFT               8

/* BRPHY0_GPHY_CORE :: FIFO_CTL :: WRBLOCK_OVR [07:04] */
#define Wr_BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) WriteRegBits16(BRPHY0_GPHY_CORE_FIFO_CTL,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) ReadRegBits16(BRPHY0_GPHY_CORE_FIFO_CTL,0xf0,4)
#define BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_MASK                 0x00f0
#define BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_ALIGN                0
#define BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_BITS                 4
#define BRPHY0_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_SHIFT                4

/* BRPHY0_GPHY_CORE :: FIFO_CTL :: MIN_IPG [03:00] */
#define Wr_BRPHY0_GPHY_CORE_FIFO_CTL_MIN_IPG(x) WriteRegBits16(BRPHY0_GPHY_CORE_FIFO_CTL,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_FIFO_CTL_MIN_IPG(x) ReadRegBits16(BRPHY0_GPHY_CORE_FIFO_CTL,0xf,0)
#define BRPHY0_GPHY_CORE_FIFO_CTL_MIN_IPG_MASK                     0x000f
#define BRPHY0_GPHY_CORE_FIFO_CTL_MIN_IPG_ALIGN                    0
#define BRPHY0_GPHY_CORE_FIFO_CTL_MIN_IPG_BITS                     4
#define BRPHY0_GPHY_CORE_FIFO_CTL_MIN_IPG_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPD8
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPD8 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_EXPD8_RESERVED0_MASK                      0x8000
#define BRPHY0_GPHY_CORE_EXPD8_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPD8_RESERVED0_BITS                      1
#define BRPHY0_GPHY_CORE_EXPD8_RESERVED0_SHIFT                     15

/* BRPHY0_GPHY_CORE :: EXPD8 :: FORCE_ACD_ON [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x4000,14)
#define BRPHY0_GPHY_CORE_EXPD8_FORCE_ACD_ON_MASK                   0x4000
#define BRPHY0_GPHY_CORE_EXPD8_FORCE_ACD_ON_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPD8_FORCE_ACD_ON_BITS                   1
#define BRPHY0_GPHY_CORE_EXPD8_FORCE_ACD_ON_SHIFT                  14

/* BRPHY0_GPHY_CORE :: EXPD8 :: ACD_PHASE_SEL [13:11] */
#define Wr_BRPHY0_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x3800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x3800,11)
#define BRPHY0_GPHY_CORE_EXPD8_ACD_PHASE_SEL_MASK                  0x3800
#define BRPHY0_GPHY_CORE_EXPD8_ACD_PHASE_SEL_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXPD8_ACD_PHASE_SEL_BITS                  3
#define BRPHY0_GPHY_CORE_EXPD8_ACD_PHASE_SEL_SHIFT                 11

/* BRPHY0_GPHY_CORE :: EXPD8 :: AGC_FSCALE [10:09] */
#define Wr_BRPHY0_GPHY_CORE_EXPD8_AGC_FSCALE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x600,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPD8_AGC_FSCALE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x600,9)
#define BRPHY0_GPHY_CORE_EXPD8_AGC_FSCALE_MASK                     0x0600
#define BRPHY0_GPHY_CORE_EXPD8_AGC_FSCALE_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPD8_AGC_FSCALE_BITS                     2
#define BRPHY0_GPHY_CORE_EXPD8_AGC_FSCALE_SHIFT                    9

/* BRPHY0_GPHY_CORE :: EXPD8 :: STOP_AGC_AFTER_LINK [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x100,8)
#define BRPHY0_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_MASK            0x0100
#define BRPHY0_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_ALIGN           0
#define BRPHY0_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_BITS            1
#define BRPHY0_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_SHIFT           8

/* BRPHY0_GPHY_CORE :: EXPD8 :: UPDATE_FROM_FFE_EN [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x80,7)
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_MASK             0x0080
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_BITS             1
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_SHIFT            7

/* BRPHY0_GPHY_CORE :: EXPD8 :: UPDATE_AGC_WHEN_IDLE [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x40,6)
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_MASK           0x0040
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_BITS           1
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_SHIFT          6

/* BRPHY0_GPHY_CORE :: EXPD8 :: UPDATE_ENC_WHEN_IDLE [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x20,5)
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_MASK           0x0020
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_BITS           1
#define BRPHY0_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_SHIFT          5

/* BRPHY0_GPHY_CORE :: EXPD8 :: FFE_DYN_THD [04:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPD8_FFE_DYN_THD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x1f,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPD8_FFE_DYN_THD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPD8,0x1f,0)
#define BRPHY0_GPHY_CORE_EXPD8_FFE_DYN_THD_MASK                    0x001f
#define BRPHY0_GPHY_CORE_EXPD8_FFE_DYN_THD_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPD8_FFE_DYN_THD_BITS                    5
#define BRPHY0_GPHY_CORE_EXPD8_FFE_DYN_THD_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPF0
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPF0 :: IBS_RX_SEND [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXPF0_IBS_RX_SEND(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF0_IBS_RX_SEND(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x8000,15)
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RX_SEND_MASK                    0x8000
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RX_SEND_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RX_SEND_BITS                    1
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RX_SEND_SHIFT                   15

/* BRPHY0_GPHY_CORE :: EXPF0 :: IBS_TX_EN [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPF0_IBS_TX_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF0_IBS_TX_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x4000,14)
#define BRPHY0_GPHY_CORE_EXPF0_IBS_TX_EN_MASK                      0x4000
#define BRPHY0_GPHY_CORE_EXPF0_IBS_TX_EN_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPF0_IBS_TX_EN_BITS                      1
#define BRPHY0_GPHY_CORE_EXPF0_IBS_TX_EN_SHIFT                     14

/* BRPHY0_GPHY_CORE :: EXPF0 :: IBS_RXCLK_OV_EN [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x2000,13)
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_MASK                0x2000
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_BITS                1
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_SHIFT               13

/* BRPHY0_GPHY_CORE :: EXPF0 :: IBS_RXCLK_SW_OV [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_MASK                0x1000
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_BITS                1
#define BRPHY0_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_SHIFT               12

/* BRPHY0_GPHY_CORE :: EXPF0 :: reserved0 [11:05] */
#define BRPHY0_GPHY_CORE_EXPF0_RESERVED0_MASK                      0x0fe0
#define BRPHY0_GPHY_CORE_EXPF0_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPF0_RESERVED0_BITS                      7
#define BRPHY0_GPHY_CORE_EXPF0_RESERVED0_SHIFT                     5

/* BRPHY0_GPHY_CORE :: EXPF0 :: IBS_PWRDN [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x10,4)
#define BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_MASK                      0x0010
#define BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_BITS                      1
#define BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_SHIFT                     4

/* BRPHY0_GPHY_CORE :: EXPF0 :: IBS_PWRDN_SD [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x8,3)
#define BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_SD_MASK                   0x0008
#define BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_SD_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_SD_BITS                   1
#define BRPHY0_GPHY_CORE_EXPF0_IBS_PWRDN_SD_SHIFT                  3

/* BRPHY0_GPHY_CORE :: EXPF0 :: IBS_AUTO_PWRDN [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x4,2)
#define BRPHY0_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_MASK                 0x0004
#define BRPHY0_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_BITS                 1
#define BRPHY0_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_SHIFT                2

/* BRPHY0_GPHY_CORE :: EXPF0 :: IBS_EARLY_DAC_WAKE [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x2,1)
#define BRPHY0_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_MASK             0x0002
#define BRPHY0_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_BITS             1
#define BRPHY0_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_SHIFT            1

/* BRPHY0_GPHY_CORE :: EXPF0 :: IBS_CK25_DIS [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF0,0x1,0)
#define BRPHY0_GPHY_CORE_EXPF0_IBS_CK25_DIS_MASK                   0x0001
#define BRPHY0_GPHY_CORE_EXPF0_IBS_CK25_DIS_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPF0_IBS_CK25_DIS_BITS                   1
#define BRPHY0_GPHY_CORE_EXPF0_IBS_CK25_DIS_SHIFT                  0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPF5
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_COPPER [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x8000,15)
#define BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_MASK           0x8000
#define BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_BITS           1
#define BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_SHIFT          15

/* BRPHY0_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_FIBER [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x4000,14)
#define BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_MASK            0x4000
#define BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_ALIGN           0
#define BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_BITS            1
#define BRPHY0_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_SHIFT           14

/* BRPHY0_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_COPPER [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x2000,13)
#define BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_MASK           0x2000
#define BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_BITS           1
#define BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_SHIFT          13

/* BRPHY0_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_FIBER [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_MASK            0x1000
#define BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_ALIGN           0
#define BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_BITS            1
#define BRPHY0_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_SHIFT           12

/* BRPHY0_GPHY_CORE :: EXPF5 :: RX_SOP_SEL [11:10] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0xc00,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0xc00,10)
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_MASK                     0x0c00
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_BITS                     2
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_SHIFT                    10

/* BRPHY0_GPHY_CORE :: EXPF5 :: RX_SOP_SEL_OV [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x200,9)
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_MASK                  0x0200
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_BITS                  1
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_SHIFT                 9

/* BRPHY0_GPHY_CORE :: EXPF5 :: TX_SOP_10BT_ENABLE [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x100,8)
#define BRPHY0_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_MASK             0x0100
#define BRPHY0_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_BITS             1
#define BRPHY0_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_SHIFT            8

/* BRPHY0_GPHY_CORE :: EXPF5 :: RX_SOP_10BT_ENABLE [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x80,7)
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_MASK             0x0080
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_BITS             1
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_SHIFT            7

/* BRPHY0_GPHY_CORE :: EXPF5 :: TX_SOP_ERR_STATUS [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x40,6)
#define BRPHY0_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_MASK              0x0040
#define BRPHY0_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_BITS              1
#define BRPHY0_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_SHIFT             6

/* BRPHY0_GPHY_CORE :: EXPF5 :: USE_TXEN_TX_SOP [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x20,5)
#define BRPHY0_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_MASK                0x0020
#define BRPHY0_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_BITS                1
#define BRPHY0_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_SHIFT               5

/* BRPHY0_GPHY_CORE :: EXPF5 :: RX_SOP_ERR_STATUS [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x10,4)
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_MASK              0x0010
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_BITS              1
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_SHIFT             4

/* BRPHY0_GPHY_CORE :: EXPF5 :: RX_SOP_OPTION [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x8,3)
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_OPTION_MASK                  0x0008
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_OPTION_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_OPTION_BITS                  1
#define BRPHY0_GPHY_CORE_EXPF5_RX_SOP_OPTION_SHIFT                 3

/* BRPHY0_GPHY_CORE :: EXPF5 :: USE_RXDV_RX_SOP [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x4,2)
#define BRPHY0_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_MASK                0x0004
#define BRPHY0_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_BITS                1
#define BRPHY0_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_SHIFT               2

/* BRPHY0_GPHY_CORE :: EXPF5 :: RECOVERY_CLK_SEL [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x2,1)
#define BRPHY0_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_MASK               0x0002
#define BRPHY0_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_BITS               1
#define BRPHY0_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_SHIFT              1

/* BRPHY0_GPHY_CORE :: EXPF5 :: TIMESYNC_EN [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPF5_TIMESYNC_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF5_TIMESYNC_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF5,0x1,0)
#define BRPHY0_GPHY_CORE_EXPF5_TIMESYNC_EN_MASK                    0x0001
#define BRPHY0_GPHY_CORE_EXPF5_TIMESYNC_EN_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPF5_TIMESYNC_EN_BITS                    1
#define BRPHY0_GPHY_CORE_EXPF5_TIMESYNC_EN_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPF6
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPF6 :: reserved0 [15:15] */
#define BRPHY0_GPHY_CORE_EXPF6_RESERVED0_MASK                      0x8000
#define BRPHY0_GPHY_CORE_EXPF6_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPF6_RESERVED0_BITS                      1
#define BRPHY0_GPHY_CORE_EXPF6_RESERVED0_SHIFT                     15

/* BRPHY0_GPHY_CORE :: EXPF6 :: PWRDN_DLL [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPF6_PWRDN_DLL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF6,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF6_PWRDN_DLL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF6,0x4000,14)
#define BRPHY0_GPHY_CORE_EXPF6_PWRDN_DLL_MASK                      0x4000
#define BRPHY0_GPHY_CORE_EXPF6_PWRDN_DLL_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPF6_PWRDN_DLL_BITS                      1
#define BRPHY0_GPHY_CORE_EXPF6_PWRDN_DLL_SHIFT                     14

/* BRPHY0_GPHY_CORE :: EXPF6 :: PWRDNBT_DLL [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF6,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF6,0x2000,13)
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNBT_DLL_MASK                    0x2000
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNBT_DLL_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNBT_DLL_BITS                    1
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNBT_DLL_SHIFT                   13

/* BRPHY0_GPHY_CORE :: EXPF6 :: COMMON_PWROFF [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPF6_COMMON_PWROFF(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF6,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF6_COMMON_PWROFF(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF6,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPF6_COMMON_PWROFF_MASK                  0x1000
#define BRPHY0_GPHY_CORE_EXPF6_COMMON_PWROFF_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXPF6_COMMON_PWROFF_BITS                  1
#define BRPHY0_GPHY_CORE_EXPF6_COMMON_PWROFF_SHIFT                 12

/* BRPHY0_GPHY_CORE :: EXPF6 :: PWRDN_SD [11:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPF6_PWRDN_SD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF6,0xf00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF6_PWRDN_SD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF6,0xf00,8)
#define BRPHY0_GPHY_CORE_EXPF6_PWRDN_SD_MASK                       0x0f00
#define BRPHY0_GPHY_CORE_EXPF6_PWRDN_SD_ALIGN                      0
#define BRPHY0_GPHY_CORE_EXPF6_PWRDN_SD_BITS                       4
#define BRPHY0_GPHY_CORE_EXPF6_PWRDN_SD_SHIFT                      8

/* BRPHY0_GPHY_CORE :: EXPF6 :: PWRDNRX [07:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPF6_PWRDNRX(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF6,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF6_PWRDNRX(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF6,0xf0,4)
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNRX_MASK                        0x00f0
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNRX_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNRX_BITS                        4
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNRX_SHIFT                       4

/* BRPHY0_GPHY_CORE :: EXPF6 :: PWRDNTX [03:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPF6_PWRDNTX(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF6,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF6_PWRDNTX(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF6,0xf,0)
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNTX_MASK                        0x000f
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNTX_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNTX_BITS                        4
#define BRPHY0_GPHY_CORE_EXPF6_PWRDNTX_SHIFT                       0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPF7
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPF7 :: reserved0 [15:14] */
#define BRPHY0_GPHY_CORE_EXPF7_RESERVED0_MASK                      0xc000
#define BRPHY0_GPHY_CORE_EXPF7_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPF7_RESERVED0_BITS                      2
#define BRPHY0_GPHY_CORE_EXPF7_RESERVED0_SHIFT                     14

/* BRPHY0_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_DPWR [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x2000,13)
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_MASK              0x2000
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_BITS              1
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_SHIFT             13

/* BRPHY0_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_APWR [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_MASK              0x1000
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_BITS              1
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_SHIFT             12

/* BRPHY0_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_DPWR [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x800,11)
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_MASK              0x0800
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_BITS              1
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_SHIFT             11

/* BRPHY0_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_APWR [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x400,10)
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_MASK              0x0400
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_BITS              1
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_SHIFT             10

/* BRPHY0_GPHY_CORE :: EXPF7 :: R0PWRDN_DPWR [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x200,9)
#define BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_DPWR_MASK                   0x0200
#define BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_DPWR_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_DPWR_BITS                   1
#define BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_DPWR_SHIFT                  9

/* BRPHY0_GPHY_CORE :: EXPF7 :: R0PWRDN_APWR [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x100,8)
#define BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_APWR_MASK                   0x0100
#define BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_APWR_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_APWR_BITS                   1
#define BRPHY0_GPHY_CORE_EXPF7_R0PWRDN_APWR_SHIFT                  8

/* BRPHY0_GPHY_CORE :: EXPF7 :: AUTO_PWRDN_DLL [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x80,7)
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_MASK                 0x0080
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_BITS                 1
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_SHIFT                7

/* BRPHY0_GPHY_CORE :: EXPF7 :: PWRDN_DPWR_EARLY_INT [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x40,6)
#define BRPHY0_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_MASK           0x0040
#define BRPHY0_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_BITS           1
#define BRPHY0_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_SHIFT          6

/* BRPHY0_GPHY_CORE :: EXPF7 :: REAL_ENERGY [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_REAL_ENERGY(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_REAL_ENERGY(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x20,5)
#define BRPHY0_GPHY_CORE_EXPF7_REAL_ENERGY_MASK                    0x0020
#define BRPHY0_GPHY_CORE_EXPF7_REAL_ENERGY_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPF7_REAL_ENERGY_BITS                    1
#define BRPHY0_GPHY_CORE_EXPF7_REAL_ENERGY_SHIFT                   5

/* BRPHY0_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_RAW [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x10,4)
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_MASK               0x0010
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_BITS               1
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_SHIFT              4

/* BRPHY0_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_RAW [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x8,3)
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_MASK               0x0008
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_BITS               1
#define BRPHY0_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_SHIFT              3

/* BRPHY0_GPHY_CORE :: EXPF7 :: CUR_STATE [02:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPF7_CUR_STATE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x7,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF7_CUR_STATE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF7,0x7,0)
#define BRPHY0_GPHY_CORE_EXPF7_CUR_STATE_MASK                      0x0007
#define BRPHY0_GPHY_CORE_EXPF7_CUR_STATE_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPF7_CUR_STATE_BITS                      3
#define BRPHY0_GPHY_CORE_EXPF7_CUR_STATE_SHIFT                     0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPF8
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPF8 :: TRIM_DAC_FROM_FUSE [15:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF8,0xf000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF8,0xf000,12)
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_MASK             0xf000
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_BITS             4
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_SHIFT            12

/* BRPHY0_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_FROM_FUSE [11:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF8,0xf00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF8,0xf00,8)
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_MASK          0x0f00
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_ALIGN         0
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_BITS          4
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_SHIFT         8

/* BRPHY0_GPHY_CORE :: EXPF8 :: TRIM_DAC_TO_BIAS_BLOCK [07:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF8,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF8,0xf0,4)
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_MASK         0x00f0
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_ALIGN        0
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_BITS         4
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_SHIFT        4

/* BRPHY0_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_TO_BIAS_BLOCK [03:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF8,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF8,0xf,0)
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_MASK      0x000f
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_ALIGN     0
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_BITS      4
#define BRPHY0_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_SHIFT     0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPF9
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPF9 :: EXT_CTL [15:11] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_EXT_CTL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0xf800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_EXT_CTL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0xf800,11)
#define BRPHY0_GPHY_CORE_EXPF9_EXT_CTL_MASK                        0xf800
#define BRPHY0_GPHY_CORE_EXPF9_EXT_CTL_ALIGN                       0
#define BRPHY0_GPHY_CORE_EXPF9_EXT_CTL_BITS                        5
#define BRPHY0_GPHY_CORE_EXPF9_EXT_CTL_SHIFT                       11

/* BRPHY0_GPHY_CORE :: EXPF9 :: BT_NIBBLE_VAL [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x400,10)
#define BRPHY0_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_MASK                  0x0400
#define BRPHY0_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_BITS                  1
#define BRPHY0_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_SHIFT                 10

/* BRPHY0_GPHY_CORE :: EXPF9 :: BT_DRIB_RMV [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x200,9)
#define BRPHY0_GPHY_CORE_EXPF9_BT_DRIB_RMV_MASK                    0x0200
#define BRPHY0_GPHY_CORE_EXPF9_BT_DRIB_RMV_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPF9_BT_DRIB_RMV_BITS                    1
#define BRPHY0_GPHY_CORE_EXPF9_BT_DRIB_RMV_SHIFT                   9

/* BRPHY0_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_MDIX_EN [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x100,8)
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_MASK          0x0100
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_ALIGN         0
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_BITS          1
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_SHIFT         8

/* BRPHY0_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SEED_EN [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x80,7)
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_MASK          0x0080
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_ALIGN         0
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_BITS          1
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_SHIFT         7

/* BRPHY0_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_EN [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x40,6)
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_MASK               0x0040
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_BITS               1
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_SHIFT              6

/* BRPHY0_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SIG [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x20,5)
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_MASK              0x0020
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_BITS              1
#define BRPHY0_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_SHIFT             5

/* BRPHY0_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_VAL [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x10,4)
#define BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_MASK          0x0010
#define BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_ALIGN         0
#define BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_BITS          1
#define BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_SHIFT         4

/* BRPHY0_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_EN [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x8,3)
#define BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_MASK           0x0008
#define BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_BITS           1
#define BRPHY0_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_SHIFT          3

/* BRPHY0_GPHY_CORE :: EXPF9 :: ABIST_INF_CONV [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x4,2)
#define BRPHY0_GPHY_CORE_EXPF9_ABIST_INF_CONV_MASK                 0x0004
#define BRPHY0_GPHY_CORE_EXPF9_ABIST_INF_CONV_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPF9_ABIST_INF_CONV_BITS                 1
#define BRPHY0_GPHY_CORE_EXPF9_ABIST_INF_CONV_SHIFT                2

/* BRPHY0_GPHY_CORE :: EXPF9 :: GIGA_ONLY_HALFOUT [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x2,1)
#define BRPHY0_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_MASK              0x0002
#define BRPHY0_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_BITS              1
#define BRPHY0_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_SHIFT             1

/* BRPHY0_GPHY_CORE :: EXPF9 :: SPARE_REG0 [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPF9_SPARE_REG0(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPF9_SPARE_REG0(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPF9,0x1,0)
#define BRPHY0_GPHY_CORE_EXPF9_SPARE_REG0_MASK                     0x0001
#define BRPHY0_GPHY_CORE_EXPF9_SPARE_REG0_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPF9_SPARE_REG0_BITS                     1
#define BRPHY0_GPHY_CORE_EXPF9_SPARE_REG0_SHIFT                    0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPFA
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPFA :: reserved0 [15:04] */
#define BRPHY0_GPHY_CORE_EXPFA_RESERVED0_MASK                      0xfff0
#define BRPHY0_GPHY_CORE_EXPFA_RESERVED0_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPFA_RESERVED0_BITS                      12
#define BRPHY0_GPHY_CORE_EXPFA_RESERVED0_SHIFT                     4

/* BRPHY0_GPHY_CORE :: EXPFA :: HIDDEN_REV_NUM [03:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFA,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFA,0xf,0)
#define BRPHY0_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_MASK                 0x000f
#define BRPHY0_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_BITS                 4
#define BRPHY0_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_SHIFT                0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPFB
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPFB :: TEST_IDDQCLKBIAS [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x8000,15)
#define BRPHY0_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_MASK               0x8000
#define BRPHY0_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_BITS               1
#define BRPHY0_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_SHIFT              15

/* BRPHY0_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x4000,14)
#define BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_MASK                 0x4000
#define BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_BITS                 1
#define BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_SHIFT                14

/* BRPHY0_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV_VAL [13:10] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x3c00,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x3c00,10)
#define BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_MASK             0x3c00
#define BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_BITS             4
#define BRPHY0_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_SHIFT            10

/* BRPHY0_GPHY_CORE :: EXPFB :: TDR_SLAVE_DFE_CONV_VAL [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x200,9)
#define BRPHY0_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_MASK         0x0200
#define BRPHY0_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_ALIGN        0
#define BRPHY0_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_BITS         1
#define BRPHY0_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_SHIFT        9

/* BRPHY0_GPHY_CORE :: EXPFB :: FEXT_INPUTS_OV [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x100,8)
#define BRPHY0_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_MASK                 0x0100
#define BRPHY0_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_BITS                 1
#define BRPHY0_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_SHIFT                8

/* BRPHY0_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_OV [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x80,7)
#define BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_MASK               0x0080
#define BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_BITS               1
#define BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_SHIFT              7

/* BRPHY0_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_VAL [06:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x60,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x60,5)
#define BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_MASK              0x0060
#define BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_BITS              2
#define BRPHY0_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_SHIFT             5

/* BRPHY0_GPHY_CORE :: EXPFB :: LINK_DET_OV [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_LINK_DET_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_LINK_DET_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x10,4)
#define BRPHY0_GPHY_CORE_EXPFB_LINK_DET_OV_MASK                    0x0010
#define BRPHY0_GPHY_CORE_EXPFB_LINK_DET_OV_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPFB_LINK_DET_OV_BITS                    1
#define BRPHY0_GPHY_CORE_EXPFB_LINK_DET_OV_SHIFT                   4

/* BRPHY0_GPHY_CORE :: EXPFB :: LINK_DET_VAL [03:02] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_LINK_DET_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0xc,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_LINK_DET_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0xc,2)
#define BRPHY0_GPHY_CORE_EXPFB_LINK_DET_VAL_MASK                   0x000c
#define BRPHY0_GPHY_CORE_EXPFB_LINK_DET_VAL_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPFB_LINK_DET_VAL_BITS                   2
#define BRPHY0_GPHY_CORE_EXPFB_LINK_DET_VAL_SHIFT                  2

/* BRPHY0_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_OV [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x2,1)
#define BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_MASK               0x0002
#define BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_BITS               1
#define BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_SHIFT              1

/* BRPHY0_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_VAL [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFB,0x1,0)
#define BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_MASK              0x0001
#define BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_BITS              1
#define BRPHY0_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_SHIFT             0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPFC
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPFC :: PASSIVE_TERM_OV [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x8000,15)
#define BRPHY0_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_MASK                0x8000
#define BRPHY0_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_BITS                1
#define BRPHY0_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_SHIFT               15

/* BRPHY0_GPHY_CORE :: EXPFC :: APD_CLKOFF_OV [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x4000,14)
#define BRPHY0_GPHY_CORE_EXPFC_APD_CLKOFF_OV_MASK                  0x4000
#define BRPHY0_GPHY_CORE_EXPFC_APD_CLKOFF_OV_ALIGN                 0
#define BRPHY0_GPHY_CORE_EXPFC_APD_CLKOFF_OV_BITS                  1
#define BRPHY0_GPHY_CORE_EXPFC_APD_CLKOFF_OV_SHIFT                 14

/* BRPHY0_GPHY_CORE :: EXPFC :: TDR_TSD_PTE_OV_VAL_CHD [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x2000,13)
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_MASK         0x2000
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_ALIGN        0
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_BITS         1
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_SHIFT        13

/* BRPHY0_GPHY_CORE :: EXPFC :: TDR_TSC_PTE_OV_VAL_CHC [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_MASK         0x1000
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_ALIGN        0
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_BITS         1
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_SHIFT        12

/* BRPHY0_GPHY_CORE :: EXPFC :: TDR_TSB_PTE_OV_VAL_CHB [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x800,11)
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_MASK         0x0800
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_ALIGN        0
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_BITS         1
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_SHIFT        11

/* BRPHY0_GPHY_CORE :: EXPFC :: TDR_TSA_PTE_OV_VAL_CHA [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x400,10)
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_MASK         0x0400
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_ALIGN        0
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_BITS         1
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_SHIFT        10

/* BRPHY0_GPHY_CORE :: EXPFC :: TDR_TS_EN_OV [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x200,9)
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TS_EN_OV_MASK                   0x0200
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TS_EN_OV_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TS_EN_OV_BITS                   1
#define BRPHY0_GPHY_CORE_EXPFC_TDR_TS_EN_OV_SHIFT                  9

/* BRPHY0_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x100,8)
#define BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_MASK                   0x0100
#define BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_BITS                   1
#define BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_SHIFT                  8

/* BRPHY0_GPHY_CORE :: EXPFC :: BASET_DLL_CLK_OV_VAL [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x80,7)
#define BRPHY0_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_MASK           0x0080
#define BRPHY0_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_ALIGN          0
#define BRPHY0_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_BITS           1
#define BRPHY0_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_SHIFT          7

/* BRPHY0_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV_VAL [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x40,6)
#define BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_MASK               0x0040
#define BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_BITS               1
#define BRPHY0_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_SHIFT              6

/* BRPHY0_GPHY_CORE :: EXPFC :: AUTONEG_1000T_CLK_GATING_DIS [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x20,5)
#define BRPHY0_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_MASK   0x0020
#define BRPHY0_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_ALIGN  0
#define BRPHY0_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_BITS   1
#define BRPHY0_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_SHIFT  5

/* BRPHY0_GPHY_CORE :: EXPFC :: AUTONEG_10BT_LP_DIS [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x10,4)
#define BRPHY0_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_MASK            0x0010
#define BRPHY0_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_ALIGN           0
#define BRPHY0_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_BITS            1
#define BRPHY0_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_SHIFT           4

/* BRPHY0_GPHY_CORE :: EXPFC :: AUTO_PWRDN_CLK_OFF_OV_VAL [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x8,3)
#define BRPHY0_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_MASK      0x0008
#define BRPHY0_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_ALIGN     0
#define BRPHY0_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_BITS      1
#define BRPHY0_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_SHIFT     3

/* BRPHY0_GPHY_CORE :: EXPFC :: LP1000_DIS [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_LP1000_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_LP1000_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x4,2)
#define BRPHY0_GPHY_CORE_EXPFC_LP1000_DIS_MASK                     0x0004
#define BRPHY0_GPHY_CORE_EXPFC_LP1000_DIS_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPFC_LP1000_DIS_BITS                     1
#define BRPHY0_GPHY_CORE_EXPFC_LP1000_DIS_SHIFT                    2

/* BRPHY0_GPHY_CORE :: EXPFC :: LP100_DIS [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_LP100_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_LP100_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x2,1)
#define BRPHY0_GPHY_CORE_EXPFC_LP100_DIS_MASK                      0x0002
#define BRPHY0_GPHY_CORE_EXPFC_LP100_DIS_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPFC_LP100_DIS_BITS                      1
#define BRPHY0_GPHY_CORE_EXPFC_LP100_DIS_SHIFT                     1

/* BRPHY0_GPHY_CORE :: EXPFC :: LP10_DIABLE [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPFC_LP10_DIABLE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFC_LP10_DIABLE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFC,0x1,0)
#define BRPHY0_GPHY_CORE_EXPFC_LP10_DIABLE_MASK                    0x0001
#define BRPHY0_GPHY_CORE_EXPFC_LP10_DIABLE_ALIGN                   0
#define BRPHY0_GPHY_CORE_EXPFC_LP10_DIABLE_BITS                    1
#define BRPHY0_GPHY_CORE_EXPFC_LP10_DIABLE_SHIFT                   0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPFD
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPFD :: SPARE_REG [15:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0xe000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0xe000,13)
#define BRPHY0_GPHY_CORE_EXPFD_SPARE_REG_MASK                      0xe000
#define BRPHY0_GPHY_CORE_EXPFD_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPFD_SPARE_REG_BITS                      3
#define BRPHY0_GPHY_CORE_EXPFD_SPARE_REG_SHIFT                     13

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x800,11)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x400,10)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x200,9)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_BITS               1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x100,8)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_BITS               1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x80,7)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x40,6)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x20,5)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x10,4)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x8,3)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x4,2)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x2,1)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_BITS                1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY0_GPHY_CORE :: EXPFD :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFD,0x1,0)
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_BITS               1
#define BRPHY0_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPFE
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPFE :: SPARE_REG [15:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_SPARE_REG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0xc000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_SPARE_REG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0xc000,14)
#define BRPHY0_GPHY_CORE_EXPFE_SPARE_REG_MASK                      0xc000
#define BRPHY0_GPHY_CORE_EXPFE_SPARE_REG_ALIGN                     0
#define BRPHY0_GPHY_CORE_EXPFE_SPARE_REG_BITS                      2
#define BRPHY0_GPHY_CORE_EXPFE_SPARE_REG_SHIFT                     14

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_DFE_LPI_EN [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x2000,13)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_MASK              0x2000
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_BITS              1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_SHIFT             13

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x800,11,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x800,11)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x400,10,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x400,10)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x200,9,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x200,9)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_BITS               1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x100,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x100,8)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_BITS               1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x80,7,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x80,7)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x40,6,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x40,6)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x20,5,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x20,5)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x10,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x10,4)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x8,3,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x8,3)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x4,2,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x4,2)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x2,1,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x2,1)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_BITS                1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY0_GPHY_CORE :: EXPFE :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x1,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFE,0x1,0)
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_BITS               1
#define BRPHY0_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY0_GPHY_CORE :: EXPFF
 ***************************************************************************/
/* BRPHY0_GPHY_CORE :: EXPFF :: PWRDN_SD_DIS [15:15] */
#define Wr_BRPHY0_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFF,0x8000,15,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFF,0x8000,15)
#define BRPHY0_GPHY_CORE_EXPFF_PWRDN_SD_DIS_MASK                   0x8000
#define BRPHY0_GPHY_CORE_EXPFF_PWRDN_SD_DIS_ALIGN                  0
#define BRPHY0_GPHY_CORE_EXPFF_PWRDN_SD_DIS_BITS                   1
#define BRPHY0_GPHY_CORE_EXPFF_PWRDN_SD_DIS_SHIFT                  15

/* BRPHY0_GPHY_CORE :: EXPFF :: PWRDNSD_OV [14:14] */
#define Wr_BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFF,0x4000,14,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFF,0x4000,14)
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_MASK                     0x4000
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_BITS                     1
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_SHIFT                    14

/* BRPHY0_GPHY_CORE :: EXPFF :: PWRDNTX_OV [13:13] */
#define Wr_BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFF,0x2000,13,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFF,0x2000,13)
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_MASK                     0x2000
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_BITS                     1
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_SHIFT                    13

/* BRPHY0_GPHY_CORE :: EXPFF :: PWRDNRX_OV [12:12] */
#define Wr_BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFF,0x1000,12,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFF,0x1000,12)
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_MASK                     0x1000
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_ALIGN                    0
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_BITS                     1
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_SHIFT                    12

/* BRPHY0_GPHY_CORE :: EXPFF :: PWRDNSD_OV_VAL [11:08] */
#define Wr_BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFF,0xf00,8,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFF,0xf00,8)
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_MASK                 0x0f00
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_BITS                 4
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_SHIFT                8

/* BRPHY0_GPHY_CORE :: EXPFF :: PWRDNTX_OV_VAL [07:04] */
#define Wr_BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFF,0xf0,4,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFF,0xf0,4)
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_MASK                 0x00f0
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_BITS                 4
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_SHIFT                4

/* BRPHY0_GPHY_CORE :: EXPFF :: PWRDNRX_OV_VAL [03:00] */
#define Wr_BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) WriteRegBits16(BRPHY0_GPHY_CORE_EXPFF,0xf,0,x)
#define Rd_BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) ReadRegBits16(BRPHY0_GPHY_CORE_EXPFF,0xf,0)
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_MASK                 0x000f
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_ALIGN                0
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_BITS                 4
#define BRPHY0_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_DSP_TAP
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP0_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP0_C0 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x8000,15)
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY0_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x4000,14)
#define BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY0_DSP_TAP :: TAP0_C0 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x2000,13)
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY0_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x1000,12)
#define BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY0_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY0_DSP_TAP :: TAP0_C0 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x800,11)
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_BITS                1
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY0_DSP_TAP :: TAP0_C0 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x700,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x700,8)
#define BRPHY0_DSP_TAP_TAP0_C0_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY0_DSP_TAP_TAP0_C0_BR_PGA_GAIN_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP0_C0_BR_PGA_GAIN_BITS                    3
#define BRPHY0_DSP_TAP_TAP0_C0_BR_PGA_GAIN_SHIFT                   8

/* BRPHY0_DSP_TAP :: TAP0_C0 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x80,7)
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_OV_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_OV_BITS                    1
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_OV_SHIFT                   7

/* BRPHY0_DSP_TAP :: TAP0_C0 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x7f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C0,0x7f,0)
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_BITS                 7
#define BRPHY0_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP0_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP0_C1 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x8000,15)
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY0_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x4000,14)
#define BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY0_DSP_TAP :: TAP0_C1 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x2000,13)
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY0_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x1000,12)
#define BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY0_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY0_DSP_TAP :: TAP0_C1 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x800,11)
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_BITS                1
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY0_DSP_TAP :: TAP0_C1 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x700,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x700,8)
#define BRPHY0_DSP_TAP_TAP0_C1_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY0_DSP_TAP_TAP0_C1_BR_PGA_GAIN_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP0_C1_BR_PGA_GAIN_BITS                    3
#define BRPHY0_DSP_TAP_TAP0_C1_BR_PGA_GAIN_SHIFT                   8

/* BRPHY0_DSP_TAP :: TAP0_C1 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x80,7)
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_OV_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_OV_BITS                    1
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_OV_SHIFT                   7

/* BRPHY0_DSP_TAP :: TAP0_C1 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x7f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C1,0x7f,0)
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_BITS                 7
#define BRPHY0_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP0_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP0_C2 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x8000,15)
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY0_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x4000,14)
#define BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY0_DSP_TAP :: TAP0_C2 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x2000,13)
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY0_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x1000,12)
#define BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY0_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY0_DSP_TAP :: TAP0_C2 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x800,11)
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_BITS                1
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY0_DSP_TAP :: TAP0_C2 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x700,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x700,8)
#define BRPHY0_DSP_TAP_TAP0_C2_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY0_DSP_TAP_TAP0_C2_BR_PGA_GAIN_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP0_C2_BR_PGA_GAIN_BITS                    3
#define BRPHY0_DSP_TAP_TAP0_C2_BR_PGA_GAIN_SHIFT                   8

/* BRPHY0_DSP_TAP :: TAP0_C2 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x80,7)
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_OV_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_OV_BITS                    1
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_OV_SHIFT                   7

/* BRPHY0_DSP_TAP :: TAP0_C2 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x7f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C2,0x7f,0)
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_BITS                 7
#define BRPHY0_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP0_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP0_C3 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x8000,15)
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY0_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x4000,14)
#define BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY0_DSP_TAP :: TAP0_C3 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x2000,13)
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY0_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x1000,12)
#define BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY0_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY0_DSP_TAP :: TAP0_C3 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x800,11)
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_BITS                1
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY0_DSP_TAP :: TAP0_C3 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x700,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x700,8)
#define BRPHY0_DSP_TAP_TAP0_C3_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY0_DSP_TAP_TAP0_C3_BR_PGA_GAIN_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP0_C3_BR_PGA_GAIN_BITS                    3
#define BRPHY0_DSP_TAP_TAP0_C3_BR_PGA_GAIN_SHIFT                   8

/* BRPHY0_DSP_TAP :: TAP0_C3 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x80,7)
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_OV_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_OV_BITS                    1
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_OV_SHIFT                   7

/* BRPHY0_DSP_TAP :: TAP0_C3 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x7f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP0_C3,0x7f,0)
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_BITS                 7
#define BRPHY0_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP1 :: reserved0 [15:14] */
#define BRPHY0_DSP_TAP_TAP1_RESERVED0_MASK                         0xc000
#define BRPHY0_DSP_TAP_TAP1_RESERVED0_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP1_RESERVED0_BITS                         2
#define BRPHY0_DSP_TAP_TAP1_RESERVED0_SHIFT                        14

/* BRPHY0_DSP_TAP :: TAP1 :: DIG_GAIN_LMS_MODE [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP1,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP1,0x2000,13)
#define BRPHY0_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_MASK                 0x2000
#define BRPHY0_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_BITS                 1
#define BRPHY0_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_SHIFT                13

/* BRPHY0_DSP_TAP :: TAP1 :: IPRF_K_OV_EN [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP1,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP1,0x1000,12)
#define BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_EN_MASK                      0x1000
#define BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_EN_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_EN_BITS                      1
#define BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_EN_SHIFT                     12

/* BRPHY0_DSP_TAP :: TAP1 :: IPRF_K_OV_VALUE [11:07] */
#define Wr_BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP1,0xf80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP1,0xf80,7)
#define BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_VALUE_MASK                   0x0f80
#define BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_VALUE_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_VALUE_BITS                   5
#define BRPHY0_DSP_TAP_TAP1_IPRF_K_OV_VALUE_SHIFT                  7

/* BRPHY0_DSP_TAP :: TAP1 :: GBT_AGC_TARGET_LVL [06:04] */
#define Wr_BRPHY0_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP1,0x70,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP1,0x70,4)
#define BRPHY0_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_MASK                0x0070
#define BRPHY0_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_ALIGN               0
#define BRPHY0_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_BITS                3
#define BRPHY0_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_SHIFT               4

/* BRPHY0_DSP_TAP :: TAP1 :: TX_AGC_TARGET_LVL [03:00] */
#define Wr_BRPHY0_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP1,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP1,0xf,0)
#define BRPHY0_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_MASK                 0x000f
#define BRPHY0_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_ALIGN                0
#define BRPHY0_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_BITS                 4
#define BRPHY0_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP2_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP2_C0 :: MSE [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP2_C0_MSE(x) WriteReg16(BRPHY0_DSP_TAP_TAP2_C0,x)
#define Rd_BRPHY0_DSP_TAP_TAP2_C0_MSE(x) ReadReg16(BRPHY0_DSP_TAP_TAP2_C0)
#define BRPHY0_DSP_TAP_TAP2_C0_MSE_MASK                            0xffff
#define BRPHY0_DSP_TAP_TAP2_C0_MSE_ALIGN                           0
#define BRPHY0_DSP_TAP_TAP2_C0_MSE_BITS                            16
#define BRPHY0_DSP_TAP_TAP2_C0_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP2_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP2_C1 :: MSE [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP2_C1_MSE(x) WriteReg16(BRPHY0_DSP_TAP_TAP2_C1,x)
#define Rd_BRPHY0_DSP_TAP_TAP2_C1_MSE(x) ReadReg16(BRPHY0_DSP_TAP_TAP2_C1)
#define BRPHY0_DSP_TAP_TAP2_C1_MSE_MASK                            0xffff
#define BRPHY0_DSP_TAP_TAP2_C1_MSE_ALIGN                           0
#define BRPHY0_DSP_TAP_TAP2_C1_MSE_BITS                            16
#define BRPHY0_DSP_TAP_TAP2_C1_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP2_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP2_C2 :: MSE [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP2_C2_MSE(x) WriteReg16(BRPHY0_DSP_TAP_TAP2_C2,x)
#define Rd_BRPHY0_DSP_TAP_TAP2_C2_MSE(x) ReadReg16(BRPHY0_DSP_TAP_TAP2_C2)
#define BRPHY0_DSP_TAP_TAP2_C2_MSE_MASK                            0xffff
#define BRPHY0_DSP_TAP_TAP2_C2_MSE_ALIGN                           0
#define BRPHY0_DSP_TAP_TAP2_C2_MSE_BITS                            16
#define BRPHY0_DSP_TAP_TAP2_C2_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP2_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP2_C3 :: MSE [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP2_C3_MSE(x) WriteReg16(BRPHY0_DSP_TAP_TAP2_C3,x)
#define Rd_BRPHY0_DSP_TAP_TAP2_C3_MSE(x) ReadReg16(BRPHY0_DSP_TAP_TAP2_C3)
#define BRPHY0_DSP_TAP_TAP2_C3_MSE_MASK                            0xffff
#define BRPHY0_DSP_TAP_TAP2_C3_MSE_ALIGN                           0
#define BRPHY0_DSP_TAP_TAP2_C3_MSE_BITS                            16
#define BRPHY0_DSP_TAP_TAP2_C3_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP3_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP3_C0 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP3_C0_SOFT_DECISION(x) WriteReg16(BRPHY0_DSP_TAP_TAP3_C0,x)
#define Rd_BRPHY0_DSP_TAP_TAP3_C0_SOFT_DECISION(x) ReadReg16(BRPHY0_DSP_TAP_TAP3_C0)
#define BRPHY0_DSP_TAP_TAP3_C0_SOFT_DECISION_MASK                  0xffff
#define BRPHY0_DSP_TAP_TAP3_C0_SOFT_DECISION_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP3_C0_SOFT_DECISION_BITS                  16
#define BRPHY0_DSP_TAP_TAP3_C0_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP3_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP3_C1 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP3_C1_SOFT_DECISION(x) WriteReg16(BRPHY0_DSP_TAP_TAP3_C1,x)
#define Rd_BRPHY0_DSP_TAP_TAP3_C1_SOFT_DECISION(x) ReadReg16(BRPHY0_DSP_TAP_TAP3_C1)
#define BRPHY0_DSP_TAP_TAP3_C1_SOFT_DECISION_MASK                  0xffff
#define BRPHY0_DSP_TAP_TAP3_C1_SOFT_DECISION_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP3_C1_SOFT_DECISION_BITS                  16
#define BRPHY0_DSP_TAP_TAP3_C1_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP3_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP3_C2 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP3_C2_SOFT_DECISION(x) WriteReg16(BRPHY0_DSP_TAP_TAP3_C2,x)
#define Rd_BRPHY0_DSP_TAP_TAP3_C2_SOFT_DECISION(x) ReadReg16(BRPHY0_DSP_TAP_TAP3_C2)
#define BRPHY0_DSP_TAP_TAP3_C2_SOFT_DECISION_MASK                  0xffff
#define BRPHY0_DSP_TAP_TAP3_C2_SOFT_DECISION_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP3_C2_SOFT_DECISION_BITS                  16
#define BRPHY0_DSP_TAP_TAP3_C2_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP3_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP3_C3 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP3_C3_SOFT_DECISION(x) WriteReg16(BRPHY0_DSP_TAP_TAP3_C3,x)
#define Rd_BRPHY0_DSP_TAP_TAP3_C3_SOFT_DECISION(x) ReadReg16(BRPHY0_DSP_TAP_TAP3_C3)
#define BRPHY0_DSP_TAP_TAP3_C3_SOFT_DECISION_MASK                  0xffff
#define BRPHY0_DSP_TAP_TAP3_C3_SOFT_DECISION_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP3_C3_SOFT_DECISION_BITS                  16
#define BRPHY0_DSP_TAP_TAP3_C3_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP4_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP4_C0 :: reserved0 [15:15] */
#define BRPHY0_DSP_TAP_TAP4_C0_RESERVED0_MASK                      0x8000
#define BRPHY0_DSP_TAP_TAP4_C0_RESERVED0_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C0_RESERVED0_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C0_RESERVED0_SHIFT                     15

/* BRPHY0_DSP_TAP :: TAP4_C0 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x7000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x7000,12)
#define BRPHY0_DSP_TAP_TAP4_C0_PAIR_OFFSET_MASK                    0x7000
#define BRPHY0_DSP_TAP_TAP4_C0_PAIR_OFFSET_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP4_C0_PAIR_OFFSET_BITS                    3
#define BRPHY0_DSP_TAP_TAP4_C0_PAIR_OFFSET_SHIFT                   12

/* BRPHY0_DSP_TAP :: TAP4_C0 :: GAMMA16 [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C0_GAMMA16(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C0_GAMMA16(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x800,11)
#define BRPHY0_DSP_TAP_TAP4_C0_GAMMA16_MASK                        0x0800
#define BRPHY0_DSP_TAP_TAP4_C0_GAMMA16_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP4_C0_GAMMA16_BITS                        1
#define BRPHY0_DSP_TAP_TAP4_C0_GAMMA16_SHIFT                       11

/* BRPHY0_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x400,10)
#define BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY0_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x200,9)
#define BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY0_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY0_DSP_TAP :: TAP4_C0 :: INC_PHASE [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C0_INC_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C0_INC_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x100,8)
#define BRPHY0_DSP_TAP_TAP4_C0_INC_PHASE_MASK                      0x0100
#define BRPHY0_DSP_TAP_TAP4_C0_INC_PHASE_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C0_INC_PHASE_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C0_INC_PHASE_SHIFT                     8

/* BRPHY0_DSP_TAP :: TAP4_C0 :: DEC_PHASE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C0_DEC_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C0_DEC_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x80,7)
#define BRPHY0_DSP_TAP_TAP4_C0_DEC_PHASE_MASK                      0x0080
#define BRPHY0_DSP_TAP_TAP4_C0_DEC_PHASE_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C0_DEC_PHASE_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C0_DEC_PHASE_SHIFT                     7

/* BRPHY0_DSP_TAP :: TAP4_C0 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x40,6)
#define BRPHY0_DSP_TAP_TAP4_C0_PHASE_FREEZE_MASK                   0x0040
#define BRPHY0_DSP_TAP_TAP4_C0_PHASE_FREEZE_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP4_C0_PHASE_FREEZE_BITS                   1
#define BRPHY0_DSP_TAP_TAP4_C0_PHASE_FREEZE_SHIFT                  6

/* BRPHY0_DSP_TAP :: TAP4_C0 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C0,0x3f,0)
#define BRPHY0_DSP_TAP_TAP4_C0_CURRENT_PHASE_MASK                  0x003f
#define BRPHY0_DSP_TAP_TAP4_C0_CURRENT_PHASE_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP4_C0_CURRENT_PHASE_BITS                  6
#define BRPHY0_DSP_TAP_TAP4_C0_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP4_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP4_C1 :: reserved0 [15:15] */
#define BRPHY0_DSP_TAP_TAP4_C1_RESERVED0_MASK                      0x8000
#define BRPHY0_DSP_TAP_TAP4_C1_RESERVED0_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C1_RESERVED0_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C1_RESERVED0_SHIFT                     15

/* BRPHY0_DSP_TAP :: TAP4_C1 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x7000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x7000,12)
#define BRPHY0_DSP_TAP_TAP4_C1_PAIR_OFFSET_MASK                    0x7000
#define BRPHY0_DSP_TAP_TAP4_C1_PAIR_OFFSET_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP4_C1_PAIR_OFFSET_BITS                    3
#define BRPHY0_DSP_TAP_TAP4_C1_PAIR_OFFSET_SHIFT                   12

/* BRPHY0_DSP_TAP :: TAP4_C1 :: GAMMA16 [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C1_GAMMA16(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C1_GAMMA16(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x800,11)
#define BRPHY0_DSP_TAP_TAP4_C1_GAMMA16_MASK                        0x0800
#define BRPHY0_DSP_TAP_TAP4_C1_GAMMA16_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP4_C1_GAMMA16_BITS                        1
#define BRPHY0_DSP_TAP_TAP4_C1_GAMMA16_SHIFT                       11

/* BRPHY0_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x400,10)
#define BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY0_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x200,9)
#define BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY0_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY0_DSP_TAP :: TAP4_C1 :: INC_PHASE [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C1_INC_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C1_INC_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x100,8)
#define BRPHY0_DSP_TAP_TAP4_C1_INC_PHASE_MASK                      0x0100
#define BRPHY0_DSP_TAP_TAP4_C1_INC_PHASE_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C1_INC_PHASE_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C1_INC_PHASE_SHIFT                     8

/* BRPHY0_DSP_TAP :: TAP4_C1 :: DEC_PHASE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C1_DEC_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C1_DEC_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x80,7)
#define BRPHY0_DSP_TAP_TAP4_C1_DEC_PHASE_MASK                      0x0080
#define BRPHY0_DSP_TAP_TAP4_C1_DEC_PHASE_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C1_DEC_PHASE_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C1_DEC_PHASE_SHIFT                     7

/* BRPHY0_DSP_TAP :: TAP4_C1 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x40,6)
#define BRPHY0_DSP_TAP_TAP4_C1_PHASE_FREEZE_MASK                   0x0040
#define BRPHY0_DSP_TAP_TAP4_C1_PHASE_FREEZE_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP4_C1_PHASE_FREEZE_BITS                   1
#define BRPHY0_DSP_TAP_TAP4_C1_PHASE_FREEZE_SHIFT                  6

/* BRPHY0_DSP_TAP :: TAP4_C1 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C1,0x3f,0)
#define BRPHY0_DSP_TAP_TAP4_C1_CURRENT_PHASE_MASK                  0x003f
#define BRPHY0_DSP_TAP_TAP4_C1_CURRENT_PHASE_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP4_C1_CURRENT_PHASE_BITS                  6
#define BRPHY0_DSP_TAP_TAP4_C1_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP4_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP4_C2 :: reserved0 [15:15] */
#define BRPHY0_DSP_TAP_TAP4_C2_RESERVED0_MASK                      0x8000
#define BRPHY0_DSP_TAP_TAP4_C2_RESERVED0_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C2_RESERVED0_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C2_RESERVED0_SHIFT                     15

/* BRPHY0_DSP_TAP :: TAP4_C2 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x7000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x7000,12)
#define BRPHY0_DSP_TAP_TAP4_C2_PAIR_OFFSET_MASK                    0x7000
#define BRPHY0_DSP_TAP_TAP4_C2_PAIR_OFFSET_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP4_C2_PAIR_OFFSET_BITS                    3
#define BRPHY0_DSP_TAP_TAP4_C2_PAIR_OFFSET_SHIFT                   12

/* BRPHY0_DSP_TAP :: TAP4_C2 :: GAMMA16 [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C2_GAMMA16(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C2_GAMMA16(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x800,11)
#define BRPHY0_DSP_TAP_TAP4_C2_GAMMA16_MASK                        0x0800
#define BRPHY0_DSP_TAP_TAP4_C2_GAMMA16_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP4_C2_GAMMA16_BITS                        1
#define BRPHY0_DSP_TAP_TAP4_C2_GAMMA16_SHIFT                       11

/* BRPHY0_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x400,10)
#define BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY0_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x200,9)
#define BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY0_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY0_DSP_TAP :: TAP4_C2 :: INC_PHASE [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C2_INC_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C2_INC_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x100,8)
#define BRPHY0_DSP_TAP_TAP4_C2_INC_PHASE_MASK                      0x0100
#define BRPHY0_DSP_TAP_TAP4_C2_INC_PHASE_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C2_INC_PHASE_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C2_INC_PHASE_SHIFT                     8

/* BRPHY0_DSP_TAP :: TAP4_C2 :: DEC_PHASE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C2_DEC_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C2_DEC_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x80,7)
#define BRPHY0_DSP_TAP_TAP4_C2_DEC_PHASE_MASK                      0x0080
#define BRPHY0_DSP_TAP_TAP4_C2_DEC_PHASE_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C2_DEC_PHASE_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C2_DEC_PHASE_SHIFT                     7

/* BRPHY0_DSP_TAP :: TAP4_C2 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x40,6)
#define BRPHY0_DSP_TAP_TAP4_C2_PHASE_FREEZE_MASK                   0x0040
#define BRPHY0_DSP_TAP_TAP4_C2_PHASE_FREEZE_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP4_C2_PHASE_FREEZE_BITS                   1
#define BRPHY0_DSP_TAP_TAP4_C2_PHASE_FREEZE_SHIFT                  6

/* BRPHY0_DSP_TAP :: TAP4_C2 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C2,0x3f,0)
#define BRPHY0_DSP_TAP_TAP4_C2_CURRENT_PHASE_MASK                  0x003f
#define BRPHY0_DSP_TAP_TAP4_C2_CURRENT_PHASE_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP4_C2_CURRENT_PHASE_BITS                  6
#define BRPHY0_DSP_TAP_TAP4_C2_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP4_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP4_C3 :: reserved0 [15:15] */
#define BRPHY0_DSP_TAP_TAP4_C3_RESERVED0_MASK                      0x8000
#define BRPHY0_DSP_TAP_TAP4_C3_RESERVED0_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C3_RESERVED0_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C3_RESERVED0_SHIFT                     15

/* BRPHY0_DSP_TAP :: TAP4_C3 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x7000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x7000,12)
#define BRPHY0_DSP_TAP_TAP4_C3_PAIR_OFFSET_MASK                    0x7000
#define BRPHY0_DSP_TAP_TAP4_C3_PAIR_OFFSET_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP4_C3_PAIR_OFFSET_BITS                    3
#define BRPHY0_DSP_TAP_TAP4_C3_PAIR_OFFSET_SHIFT                   12

/* BRPHY0_DSP_TAP :: TAP4_C3 :: GAMMA16 [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C3_GAMMA16(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C3_GAMMA16(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x800,11)
#define BRPHY0_DSP_TAP_TAP4_C3_GAMMA16_MASK                        0x0800
#define BRPHY0_DSP_TAP_TAP4_C3_GAMMA16_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP4_C3_GAMMA16_BITS                        1
#define BRPHY0_DSP_TAP_TAP4_C3_GAMMA16_SHIFT                       11

/* BRPHY0_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x400,10)
#define BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY0_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x200,9)
#define BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY0_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY0_DSP_TAP :: TAP4_C3 :: INC_PHASE [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C3_INC_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C3_INC_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x100,8)
#define BRPHY0_DSP_TAP_TAP4_C3_INC_PHASE_MASK                      0x0100
#define BRPHY0_DSP_TAP_TAP4_C3_INC_PHASE_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C3_INC_PHASE_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C3_INC_PHASE_SHIFT                     8

/* BRPHY0_DSP_TAP :: TAP4_C3 :: DEC_PHASE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C3_DEC_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C3_DEC_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x80,7)
#define BRPHY0_DSP_TAP_TAP4_C3_DEC_PHASE_MASK                      0x0080
#define BRPHY0_DSP_TAP_TAP4_C3_DEC_PHASE_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP4_C3_DEC_PHASE_BITS                      1
#define BRPHY0_DSP_TAP_TAP4_C3_DEC_PHASE_SHIFT                     7

/* BRPHY0_DSP_TAP :: TAP4_C3 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x40,6)
#define BRPHY0_DSP_TAP_TAP4_C3_PHASE_FREEZE_MASK                   0x0040
#define BRPHY0_DSP_TAP_TAP4_C3_PHASE_FREEZE_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP4_C3_PHASE_FREEZE_BITS                   1
#define BRPHY0_DSP_TAP_TAP4_C3_PHASE_FREEZE_SHIFT                  6

/* BRPHY0_DSP_TAP :: TAP4_C3 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP4_C3,0x3f,0)
#define BRPHY0_DSP_TAP_TAP4_C3_CURRENT_PHASE_MASK                  0x003f
#define BRPHY0_DSP_TAP_TAP4_C3_CURRENT_PHASE_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP4_C3_CURRENT_PHASE_BITS                  6
#define BRPHY0_DSP_TAP_TAP4_C3_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP5_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP5_C0 :: reserved0 [15:14] */
#define BRPHY0_DSP_TAP_TAP5_C0_RESERVED0_MASK                      0xc000
#define BRPHY0_DSP_TAP_TAP5_C0_RESERVED0_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP5_C0_RESERVED0_BITS                      2
#define BRPHY0_DSP_TAP_TAP5_C0_RESERVED0_SHIFT                     14

/* BRPHY0_DSP_TAP :: TAP5_C0 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_SLICE_ZERO(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_SLICE_ZERO(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x2000,13)
#define BRPHY0_DSP_TAP_TAP5_C0_SLICE_ZERO_MASK                     0x2000
#define BRPHY0_DSP_TAP_TAP5_C0_SLICE_ZERO_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP5_C0_SLICE_ZERO_BITS                     1
#define BRPHY0_DSP_TAP_TAP5_C0_SLICE_ZERO_SHIFT                    13

/* BRPHY0_DSP_TAP :: TAP5_C0 :: DISABLE_TX [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_DISABLE_TX(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_DISABLE_TX(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x1000,12)
#define BRPHY0_DSP_TAP_TAP5_C0_DISABLE_TX_MASK                     0x1000
#define BRPHY0_DSP_TAP_TAP5_C0_DISABLE_TX_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP5_C0_DISABLE_TX_BITS                     1
#define BRPHY0_DSP_TAP_TAP5_C0_DISABLE_TX_SHIFT                    12

/* BRPHY0_DSP_TAP :: TAP5_C0 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x800,11)
#define BRPHY0_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY0_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY0_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY0_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY0_DSP_TAP :: TAP5_C0 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x400,10)
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY0_DSP_TAP :: TAP5_C0 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x3c0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x3c0,6)
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_MASK                      0x03c0
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_BITS                      4
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SKEW_SHIFT                     6

/* BRPHY0_DSP_TAP :: TAP5_C0 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x20,5)
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_BITS              1
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY0_DSP_TAP :: TAP5_C0 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_PAIR_SELECT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x18,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_PAIR_SELECT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x18,3)
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SELECT_MASK                    0x0018
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SELECT_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SELECT_BITS                    2
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_SELECT_SHIFT                   3

/* BRPHY0_DSP_TAP :: TAP5_C0 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x4,2)
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_POLARITY_MASK                  0x0004
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_POLARITY_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_POLARITY_BITS                  1
#define BRPHY0_DSP_TAP_TAP5_C0_PAIR_POLARITY_SHIFT                 2

/* BRPHY0_DSP_TAP :: TAP5_C0 :: SWAPCD [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_SWAPCD(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_SWAPCD(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x2,1)
#define BRPHY0_DSP_TAP_TAP5_C0_SWAPCD_MASK                         0x0002
#define BRPHY0_DSP_TAP_TAP5_C0_SWAPCD_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP5_C0_SWAPCD_BITS                         1
#define BRPHY0_DSP_TAP_TAP5_C0_SWAPCD_SHIFT                        1

/* BRPHY0_DSP_TAP :: TAP5_C0 :: SWAPAB [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C0_SWAPAB(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C0_SWAPAB(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C0,0x1,0)
#define BRPHY0_DSP_TAP_TAP5_C0_SWAPAB_MASK                         0x0001
#define BRPHY0_DSP_TAP_TAP5_C0_SWAPAB_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP5_C0_SWAPAB_BITS                         1
#define BRPHY0_DSP_TAP_TAP5_C0_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP5_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP5_C1 :: reserved0 [15:14] */
#define BRPHY0_DSP_TAP_TAP5_C1_RESERVED0_MASK                      0xc000
#define BRPHY0_DSP_TAP_TAP5_C1_RESERVED0_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP5_C1_RESERVED0_BITS                      2
#define BRPHY0_DSP_TAP_TAP5_C1_RESERVED0_SHIFT                     14

/* BRPHY0_DSP_TAP :: TAP5_C1 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_SLICE_ZERO(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_SLICE_ZERO(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x2000,13)
#define BRPHY0_DSP_TAP_TAP5_C1_SLICE_ZERO_MASK                     0x2000
#define BRPHY0_DSP_TAP_TAP5_C1_SLICE_ZERO_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP5_C1_SLICE_ZERO_BITS                     1
#define BRPHY0_DSP_TAP_TAP5_C1_SLICE_ZERO_SHIFT                    13

/* BRPHY0_DSP_TAP :: TAP5_C1 :: DISABLE_TX [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_DISABLE_TX(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_DISABLE_TX(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x1000,12)
#define BRPHY0_DSP_TAP_TAP5_C1_DISABLE_TX_MASK                     0x1000
#define BRPHY0_DSP_TAP_TAP5_C1_DISABLE_TX_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP5_C1_DISABLE_TX_BITS                     1
#define BRPHY0_DSP_TAP_TAP5_C1_DISABLE_TX_SHIFT                    12

/* BRPHY0_DSP_TAP :: TAP5_C1 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x800,11)
#define BRPHY0_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY0_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY0_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY0_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY0_DSP_TAP :: TAP5_C1 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x400,10)
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY0_DSP_TAP :: TAP5_C1 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x3c0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x3c0,6)
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_MASK                      0x03c0
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_BITS                      4
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SKEW_SHIFT                     6

/* BRPHY0_DSP_TAP :: TAP5_C1 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x20,5)
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_BITS              1
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY0_DSP_TAP :: TAP5_C1 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_PAIR_SELECT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x18,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_PAIR_SELECT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x18,3)
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SELECT_MASK                    0x0018
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SELECT_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SELECT_BITS                    2
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_SELECT_SHIFT                   3

/* BRPHY0_DSP_TAP :: TAP5_C1 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x4,2)
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_POLARITY_MASK                  0x0004
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_POLARITY_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_POLARITY_BITS                  1
#define BRPHY0_DSP_TAP_TAP5_C1_PAIR_POLARITY_SHIFT                 2

/* BRPHY0_DSP_TAP :: TAP5_C1 :: SWAPCD [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_SWAPCD(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_SWAPCD(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x2,1)
#define BRPHY0_DSP_TAP_TAP5_C1_SWAPCD_MASK                         0x0002
#define BRPHY0_DSP_TAP_TAP5_C1_SWAPCD_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP5_C1_SWAPCD_BITS                         1
#define BRPHY0_DSP_TAP_TAP5_C1_SWAPCD_SHIFT                        1

/* BRPHY0_DSP_TAP :: TAP5_C1 :: SWAPAB [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C1_SWAPAB(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C1_SWAPAB(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C1,0x1,0)
#define BRPHY0_DSP_TAP_TAP5_C1_SWAPAB_MASK                         0x0001
#define BRPHY0_DSP_TAP_TAP5_C1_SWAPAB_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP5_C1_SWAPAB_BITS                         1
#define BRPHY0_DSP_TAP_TAP5_C1_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP5_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP5_C2 :: reserved0 [15:14] */
#define BRPHY0_DSP_TAP_TAP5_C2_RESERVED0_MASK                      0xc000
#define BRPHY0_DSP_TAP_TAP5_C2_RESERVED0_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP5_C2_RESERVED0_BITS                      2
#define BRPHY0_DSP_TAP_TAP5_C2_RESERVED0_SHIFT                     14

/* BRPHY0_DSP_TAP :: TAP5_C2 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_SLICE_ZERO(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_SLICE_ZERO(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x2000,13)
#define BRPHY0_DSP_TAP_TAP5_C2_SLICE_ZERO_MASK                     0x2000
#define BRPHY0_DSP_TAP_TAP5_C2_SLICE_ZERO_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP5_C2_SLICE_ZERO_BITS                     1
#define BRPHY0_DSP_TAP_TAP5_C2_SLICE_ZERO_SHIFT                    13

/* BRPHY0_DSP_TAP :: TAP5_C2 :: DISABLE_TX [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_DISABLE_TX(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_DISABLE_TX(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x1000,12)
#define BRPHY0_DSP_TAP_TAP5_C2_DISABLE_TX_MASK                     0x1000
#define BRPHY0_DSP_TAP_TAP5_C2_DISABLE_TX_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP5_C2_DISABLE_TX_BITS                     1
#define BRPHY0_DSP_TAP_TAP5_C2_DISABLE_TX_SHIFT                    12

/* BRPHY0_DSP_TAP :: TAP5_C2 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x800,11)
#define BRPHY0_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY0_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY0_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY0_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY0_DSP_TAP :: TAP5_C2 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x400,10)
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY0_DSP_TAP :: TAP5_C2 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x3c0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x3c0,6)
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_MASK                      0x03c0
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_BITS                      4
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SKEW_SHIFT                     6

/* BRPHY0_DSP_TAP :: TAP5_C2 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x20,5)
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_BITS              1
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY0_DSP_TAP :: TAP5_C2 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_PAIR_SELECT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x18,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_PAIR_SELECT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x18,3)
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SELECT_MASK                    0x0018
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SELECT_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SELECT_BITS                    2
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_SELECT_SHIFT                   3

/* BRPHY0_DSP_TAP :: TAP5_C2 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x4,2)
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_POLARITY_MASK                  0x0004
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_POLARITY_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_POLARITY_BITS                  1
#define BRPHY0_DSP_TAP_TAP5_C2_PAIR_POLARITY_SHIFT                 2

/* BRPHY0_DSP_TAP :: TAP5_C2 :: SWAPCD [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_SWAPCD(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_SWAPCD(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x2,1)
#define BRPHY0_DSP_TAP_TAP5_C2_SWAPCD_MASK                         0x0002
#define BRPHY0_DSP_TAP_TAP5_C2_SWAPCD_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP5_C2_SWAPCD_BITS                         1
#define BRPHY0_DSP_TAP_TAP5_C2_SWAPCD_SHIFT                        1

/* BRPHY0_DSP_TAP :: TAP5_C2 :: SWAPAB [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C2_SWAPAB(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C2_SWAPAB(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C2,0x1,0)
#define BRPHY0_DSP_TAP_TAP5_C2_SWAPAB_MASK                         0x0001
#define BRPHY0_DSP_TAP_TAP5_C2_SWAPAB_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP5_C2_SWAPAB_BITS                         1
#define BRPHY0_DSP_TAP_TAP5_C2_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP5_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP5_C3 :: reserved0 [15:14] */
#define BRPHY0_DSP_TAP_TAP5_C3_RESERVED0_MASK                      0xc000
#define BRPHY0_DSP_TAP_TAP5_C3_RESERVED0_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP5_C3_RESERVED0_BITS                      2
#define BRPHY0_DSP_TAP_TAP5_C3_RESERVED0_SHIFT                     14

/* BRPHY0_DSP_TAP :: TAP5_C3 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_SLICE_ZERO(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_SLICE_ZERO(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x2000,13)
#define BRPHY0_DSP_TAP_TAP5_C3_SLICE_ZERO_MASK                     0x2000
#define BRPHY0_DSP_TAP_TAP5_C3_SLICE_ZERO_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP5_C3_SLICE_ZERO_BITS                     1
#define BRPHY0_DSP_TAP_TAP5_C3_SLICE_ZERO_SHIFT                    13

/* BRPHY0_DSP_TAP :: TAP5_C3 :: DISABLE_TX [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_DISABLE_TX(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_DISABLE_TX(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x1000,12)
#define BRPHY0_DSP_TAP_TAP5_C3_DISABLE_TX_MASK                     0x1000
#define BRPHY0_DSP_TAP_TAP5_C3_DISABLE_TX_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP5_C3_DISABLE_TX_BITS                     1
#define BRPHY0_DSP_TAP_TAP5_C3_DISABLE_TX_SHIFT                    12

/* BRPHY0_DSP_TAP :: TAP5_C3 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x800,11)
#define BRPHY0_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY0_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY0_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY0_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY0_DSP_TAP :: TAP5_C3 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x400,10)
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY0_DSP_TAP :: TAP5_C3 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x3c0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x3c0,6)
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_MASK                      0x03c0
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_BITS                      4
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SKEW_SHIFT                     6

/* BRPHY0_DSP_TAP :: TAP5_C3 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x20,5)
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_BITS              1
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY0_DSP_TAP :: TAP5_C3 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_PAIR_SELECT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x18,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_PAIR_SELECT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x18,3)
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SELECT_MASK                    0x0018
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SELECT_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SELECT_BITS                    2
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_SELECT_SHIFT                   3

/* BRPHY0_DSP_TAP :: TAP5_C3 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x4,2)
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_POLARITY_MASK                  0x0004
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_POLARITY_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_POLARITY_BITS                  1
#define BRPHY0_DSP_TAP_TAP5_C3_PAIR_POLARITY_SHIFT                 2

/* BRPHY0_DSP_TAP :: TAP5_C3 :: SWAPCD [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_SWAPCD(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_SWAPCD(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x2,1)
#define BRPHY0_DSP_TAP_TAP5_C3_SWAPCD_MASK                         0x0002
#define BRPHY0_DSP_TAP_TAP5_C3_SWAPCD_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP5_C3_SWAPCD_BITS                         1
#define BRPHY0_DSP_TAP_TAP5_C3_SWAPCD_SHIFT                        1

/* BRPHY0_DSP_TAP :: TAP5_C3 :: SWAPAB [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP5_C3_SWAPAB(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP5_C3_SWAPAB(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP5_C3,0x1,0)
#define BRPHY0_DSP_TAP_TAP5_C3_SWAPAB_MASK                         0x0001
#define BRPHY0_DSP_TAP_TAP5_C3_SWAPAB_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP5_C3_SWAPAB_BITS                         1
#define BRPHY0_DSP_TAP_TAP5_C3_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP6
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP6 :: CFCDEADMAN_DIS [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP6,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP6,0x8000,15)
#define BRPHY0_DSP_TAP_TAP6_CFCDEADMAN_DIS_MASK                    0x8000
#define BRPHY0_DSP_TAP_TAP6_CFCDEADMAN_DIS_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP6_CFCDEADMAN_DIS_BITS                    1
#define BRPHY0_DSP_TAP_TAP6_CFCDEADMAN_DIS_SHIFT                   15

/* BRPHY0_DSP_TAP :: TAP6 :: AGC_FREEZ_EN [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP6_AGC_FREEZ_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP6,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP6_AGC_FREEZ_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP6,0x4000,14)
#define BRPHY0_DSP_TAP_TAP6_AGC_FREEZ_EN_MASK                      0x4000
#define BRPHY0_DSP_TAP_TAP6_AGC_FREEZ_EN_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP6_AGC_FREEZ_EN_BITS                      1
#define BRPHY0_DSP_TAP_TAP6_AGC_FREEZ_EN_SHIFT                     14

/* BRPHY0_DSP_TAP :: TAP6 :: DAC_GAIN_INV_EN [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP6,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP6,0x2000,13)
#define BRPHY0_DSP_TAP_TAP6_DAC_GAIN_INV_EN_MASK                   0x2000
#define BRPHY0_DSP_TAP_TAP6_DAC_GAIN_INV_EN_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP6_DAC_GAIN_INV_EN_BITS                   1
#define BRPHY0_DSP_TAP_TAP6_DAC_GAIN_INV_EN_SHIFT                  13

/* BRPHY0_DSP_TAP :: TAP6 :: SPARE_REG_B12 [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP6_SPARE_REG_B12(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP6,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP6_SPARE_REG_B12(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP6,0x1000,12)
#define BRPHY0_DSP_TAP_TAP6_SPARE_REG_B12_MASK                     0x1000
#define BRPHY0_DSP_TAP_TAP6_SPARE_REG_B12_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP6_SPARE_REG_B12_BITS                     1
#define BRPHY0_DSP_TAP_TAP6_SPARE_REG_B12_SHIFT                    12

/* BRPHY0_DSP_TAP :: TAP6 :: FORCE_FSM_IDLE [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP6,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP6,0x800,11)
#define BRPHY0_DSP_TAP_TAP6_FORCE_FSM_IDLE_MASK                    0x0800
#define BRPHY0_DSP_TAP_TAP6_FORCE_FSM_IDLE_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP6_FORCE_FSM_IDLE_BITS                    1
#define BRPHY0_DSP_TAP_TAP6_FORCE_FSM_IDLE_SHIFT                   11

/* BRPHY0_DSP_TAP :: TAP6 :: SPARE_REG [10:00] */
#define Wr_BRPHY0_DSP_TAP_TAP6_SPARE_REG(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP6,0x7ff,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP6_SPARE_REG(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP6,0x7ff,0)
#define BRPHY0_DSP_TAP_TAP6_SPARE_REG_MASK                         0x07ff
#define BRPHY0_DSP_TAP_TAP6_SPARE_REG_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP6_SPARE_REG_BITS                         11
#define BRPHY0_DSP_TAP_TAP6_SPARE_REG_SHIFT                        0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP7_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP7_C0 :: TEST_LENGTH [15:09] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_TEST_LENGTH(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0xfe00,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_TEST_LENGTH(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0xfe00,9)
#define BRPHY0_DSP_TAP_TAP7_C0_TEST_LENGTH_MASK                    0xfe00
#define BRPHY0_DSP_TAP_TAP7_C0_TEST_LENGTH_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP7_C0_TEST_LENGTH_BITS                    7
#define BRPHY0_DSP_TAP_TAP7_C0_TEST_LENGTH_SHIFT                   9

/* BRPHY0_DSP_TAP :: TAP7_C0 :: SINGLE_TAP_MODE [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x100,8)
#define BRPHY0_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_MASK                0x0100
#define BRPHY0_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_ALIGN               0
#define BRPHY0_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_BITS                1
#define BRPHY0_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_SHIFT               8

/* BRPHY0_DSP_TAP :: TAP7_C0 :: UPDATE_MODE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x80,7)
#define BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MODE_MASK                    0x0080
#define BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MODE_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MODE_BITS                    1
#define BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MODE_SHIFT                   7

/* BRPHY0_DSP_TAP :: TAP7_C0 :: UPDATE_MAGNITUDE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x40,6)
#define BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_MASK               0x0040
#define BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_BITS               1
#define BRPHY0_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_SHIFT              6

/* BRPHY0_DSP_TAP :: TAP7_C0 :: START_TEST [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_START_TEST(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_START_TEST(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x20,5)
#define BRPHY0_DSP_TAP_TAP7_C0_START_TEST_MASK                     0x0020
#define BRPHY0_DSP_TAP_TAP7_C0_START_TEST_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP7_C0_START_TEST_BITS                     1
#define BRPHY0_DSP_TAP_TAP7_C0_START_TEST_SHIFT                    5

/* BRPHY0_DSP_TAP :: TAP7_C0 :: ZERO_DFE_D [04:04] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x10,4)
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_D_MASK                     0x0010
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_D_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_D_BITS                     1
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_D_SHIFT                    4

/* BRPHY0_DSP_TAP :: TAP7_C0 :: ZERO_DFE_C [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x8,3)
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_C_MASK                     0x0008
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_C_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_C_BITS                     1
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_C_SHIFT                    3

/* BRPHY0_DSP_TAP :: TAP7_C0 :: ZERO_DFE_B [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x4,2)
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_B_MASK                     0x0004
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_B_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_B_BITS                     1
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_B_SHIFT                    2

/* BRPHY0_DSP_TAP :: TAP7_C0 :: ZERO_DFE_A [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x2,1)
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_A_MASK                     0x0002
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_A_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_A_BITS                     1
#define BRPHY0_DSP_TAP_TAP7_C0_ZERO_DFE_A_SHIFT                    1

/* BRPHY0_DSP_TAP :: TAP7_C0 :: ENABLE_BIST_MODE [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C0,0x1,0)
#define BRPHY0_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_MASK               0x0001
#define BRPHY0_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_BITS               1
#define BRPHY0_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_SHIFT              0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP7_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP7_C1 :: TAP_NUMBER [15:08] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C1_TAP_NUMBER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C1,0xff00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C1_TAP_NUMBER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C1,0xff00,8)
#define BRPHY0_DSP_TAP_TAP7_C1_TAP_NUMBER_MASK                     0xff00
#define BRPHY0_DSP_TAP_TAP7_C1_TAP_NUMBER_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP7_C1_TAP_NUMBER_BITS                     8
#define BRPHY0_DSP_TAP_TAP7_C1_TAP_NUMBER_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP7_C1 :: POLARITY_MASK_LSB [07:00] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C1,0xff,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C1,0xff,0)
#define BRPHY0_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_MASK              0x00ff
#define BRPHY0_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_ALIGN             0
#define BRPHY0_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_BITS              8
#define BRPHY0_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_SHIFT             0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP7_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP7_C2 :: SPARE [15:08] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C2_SPARE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0xff00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C2_SPARE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0xff00,8)
#define BRPHY0_DSP_TAP_TAP7_C2_SPARE_MASK                          0xff00
#define BRPHY0_DSP_TAP_TAP7_C2_SPARE_ALIGN                         0
#define BRPHY0_DSP_TAP_TAP7_C2_SPARE_BITS                          8
#define BRPHY0_DSP_TAP_TAP7_C2_SPARE_SHIFT                         8

/* BRPHY0_DSP_TAP :: TAP7_C2 :: BIST_FFE_UPDATE_EN [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x80,7)
#define BRPHY0_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_MASK             0x0080
#define BRPHY0_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_ALIGN            0
#define BRPHY0_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_BITS             1
#define BRPHY0_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_SHIFT            7

/* BRPHY0_DSP_TAP :: TAP7_C2 :: DISABLE_RANDOM_BIST_ADC [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x40,6)
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_MASK        0x0040
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_ALIGN       0
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_BITS        1
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_SHIFT       6

/* BRPHY0_DSP_TAP :: TAP7_C2 :: DISABLE_VITERBI_TO_BIST [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x20,5)
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_MASK        0x0020
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_ALIGN       0
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_BITS        1
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_SHIFT       5

/* BRPHY0_DSP_TAP :: TAP7_C2 :: USE_BIST_FOR_DFE [04:04] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x10,4)
#define BRPHY0_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_MASK               0x0010
#define BRPHY0_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_BITS               1
#define BRPHY0_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_SHIFT              4

/* BRPHY0_DSP_TAP :: TAP7_C2 :: FORCE_VITERBI_MODE [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x8,3)
#define BRPHY0_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_MASK             0x0008
#define BRPHY0_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_ALIGN            0
#define BRPHY0_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_BITS             1
#define BRPHY0_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_SHIFT            3

/* BRPHY0_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_IPRK_OV [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x4,2)
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_MASK           0x0004
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_ALIGN          0
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_BITS           1
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_SHIFT          2

/* BRPHY0_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_GAMMA_OV [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x2,1)
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_MASK          0x0002
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_ALIGN         0
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_BITS          1
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_SHIFT         1

/* BRPHY0_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_ADC_OV [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP7_C2,0x1,0)
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_MASK            0x0001
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_ALIGN           0
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_BITS            1
#define BRPHY0_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_SHIFT           0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP8_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP8_C0 :: PGA_OV [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_PGA_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_PGA_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x8000,15)
#define BRPHY0_DSP_TAP_TAP8_C0_PGA_OV_MASK                         0x8000
#define BRPHY0_DSP_TAP_TAP8_C0_PGA_OV_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP8_C0_PGA_OV_BITS                         1
#define BRPHY0_DSP_TAP_TAP8_C0_PGA_OV_SHIFT                        15

/* BRPHY0_DSP_TAP :: TAP8_C0 :: TIMER_OV [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_TIMER_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_TIMER_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x4000,14)
#define BRPHY0_DSP_TAP_TAP8_C0_TIMER_OV_MASK                       0x4000
#define BRPHY0_DSP_TAP_TAP8_C0_TIMER_OV_ALIGN                      0
#define BRPHY0_DSP_TAP_TAP8_C0_TIMER_OV_BITS                       1
#define BRPHY0_DSP_TAP_TAP8_C0_TIMER_OV_SHIFT                      14

/* BRPHY0_DSP_TAP :: TAP8_C0 :: MONOTONICITY_MODE [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x2000,13)
#define BRPHY0_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_MASK              0x2000
#define BRPHY0_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_ALIGN             0
#define BRPHY0_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_BITS              1
#define BRPHY0_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_SHIFT             13

/* BRPHY0_DSP_TAP :: TAP8_C0 :: FREEZE_ERROR_ON_FAIL [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x1000,12)
#define BRPHY0_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_MASK           0x1000
#define BRPHY0_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_ALIGN          0
#define BRPHY0_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_BITS           1
#define BRPHY0_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_SHIFT          12

/* BRPHY0_DSP_TAP :: TAP8_C0 :: FREEZE_MSE_ON_FAIL [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x800,11)
#define BRPHY0_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_MASK             0x0800
#define BRPHY0_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_ALIGN            0
#define BRPHY0_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_BITS             1
#define BRPHY0_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_SHIFT            11

/* BRPHY0_DSP_TAP :: TAP8_C0 :: FAST_CONV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x400,10)
#define BRPHY0_DSP_TAP_TAP8_C0_FAST_CONV_EN_MASK                   0x0400
#define BRPHY0_DSP_TAP_TAP8_C0_FAST_CONV_EN_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP8_C0_FAST_CONV_EN_BITS                   1
#define BRPHY0_DSP_TAP_TAP8_C0_FAST_CONV_EN_SHIFT                  10

/* BRPHY0_DSP_TAP :: TAP8_C0 :: PGA_TOGGLE_MODE_EN [09:09] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x200,9)
#define BRPHY0_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_MASK             0x0200
#define BRPHY0_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_ALIGN            0
#define BRPHY0_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_BITS             1
#define BRPHY0_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_SHIFT            9

/* BRPHY0_DSP_TAP :: TAP8_C0 :: PAT_GEN_EN [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x100,8)
#define BRPHY0_DSP_TAP_TAP8_C0_PAT_GEN_EN_MASK                     0x0100
#define BRPHY0_DSP_TAP_TAP8_C0_PAT_GEN_EN_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP8_C0_PAT_GEN_EN_BITS                     1
#define BRPHY0_DSP_TAP_TAP8_C0_PAT_GEN_EN_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP8_C0 :: MAX_OFFSET_CHECK_EN [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x80,7)
#define BRPHY0_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_MASK            0x0080
#define BRPHY0_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_ALIGN           0
#define BRPHY0_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_BITS            1
#define BRPHY0_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_SHIFT           7

/* BRPHY0_DSP_TAP :: TAP8_C0 :: SYM_ERR_CHECK_EN [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x40,6)
#define BRPHY0_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_MASK               0x0040
#define BRPHY0_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_ALIGN              0
#define BRPHY0_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_BITS               1
#define BRPHY0_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_SHIFT              6

/* BRPHY0_DSP_TAP :: TAP8_C0 :: PEAK_ERR_CHECK_EN [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x20,5)
#define BRPHY0_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_MASK              0x0020
#define BRPHY0_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_ALIGN             0
#define BRPHY0_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_BITS              1
#define BRPHY0_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_SHIFT             5

/* BRPHY0_DSP_TAP :: TAP8_C0 :: MSE_CHECK_EN [04:04] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x10,4)
#define BRPHY0_DSP_TAP_TAP8_C0_MSE_CHECK_EN_MASK                   0x0010
#define BRPHY0_DSP_TAP_TAP8_C0_MSE_CHECK_EN_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP8_C0_MSE_CHECK_EN_BITS                   1
#define BRPHY0_DSP_TAP_TAP8_C0_MSE_CHECK_EN_SHIFT                  4

/* BRPHY0_DSP_TAP :: TAP8_C0 :: GAIN_AMP_CHECK_EN [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x8,3)
#define BRPHY0_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_MASK              0x0008
#define BRPHY0_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_ALIGN             0
#define BRPHY0_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_BITS              1
#define BRPHY0_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_SHIFT             3

/* BRPHY0_DSP_TAP :: TAP8_C0 :: HALT_ON_ERROR [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x4,2)
#define BRPHY0_DSP_TAP_TAP8_C0_HALT_ON_ERROR_MASK                  0x0004
#define BRPHY0_DSP_TAP_TAP8_C0_HALT_ON_ERROR_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP8_C0_HALT_ON_ERROR_BITS                  1
#define BRPHY0_DSP_TAP_TAP8_C0_HALT_ON_ERROR_SHIFT                 2

/* BRPHY0_DSP_TAP :: TAP8_C0 :: START_ABIST [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_START_ABIST(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_START_ABIST(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x2,1)
#define BRPHY0_DSP_TAP_TAP8_C0_START_ABIST_MASK                    0x0002
#define BRPHY0_DSP_TAP_TAP8_C0_START_ABIST_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP8_C0_START_ABIST_BITS                    1
#define BRPHY0_DSP_TAP_TAP8_C0_START_ABIST_SHIFT                   1

/* BRPHY0_DSP_TAP :: TAP8_C0 :: ABIST_EN [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C0_ABIST_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C0_ABIST_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C0,0x1,0)
#define BRPHY0_DSP_TAP_TAP8_C0_ABIST_EN_MASK                       0x0001
#define BRPHY0_DSP_TAP_TAP8_C0_ABIST_EN_ALIGN                      0
#define BRPHY0_DSP_TAP_TAP8_C0_ABIST_EN_BITS                       1
#define BRPHY0_DSP_TAP_TAP8_C0_ABIST_EN_SHIFT                      0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP8_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP8_C1 :: MAJOR_MODE [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_MAJOR_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_MAJOR_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x8000,15)
#define BRPHY0_DSP_TAP_TAP8_C1_MAJOR_MODE_MASK                     0x8000
#define BRPHY0_DSP_TAP_TAP8_C1_MAJOR_MODE_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP8_C1_MAJOR_MODE_BITS                     1
#define BRPHY0_DSP_TAP_TAP8_C1_MAJOR_MODE_SHIFT                    15

/* BRPHY0_DSP_TAP :: TAP8_C1 :: MULTIPLE_MSE [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x4000,14)
#define BRPHY0_DSP_TAP_TAP8_C1_MULTIPLE_MSE_MASK                   0x4000
#define BRPHY0_DSP_TAP_TAP8_C1_MULTIPLE_MSE_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP8_C1_MULTIPLE_MSE_BITS                   1
#define BRPHY0_DSP_TAP_TAP8_C1_MULTIPLE_MSE_SHIFT                  14

/* BRPHY0_DSP_TAP :: TAP8_C1 :: GAMMA_OV [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_GAMMA_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_GAMMA_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x2000,13)
#define BRPHY0_DSP_TAP_TAP8_C1_GAMMA_OV_MASK                       0x2000
#define BRPHY0_DSP_TAP_TAP8_C1_GAMMA_OV_ALIGN                      0
#define BRPHY0_DSP_TAP_TAP8_C1_GAMMA_OV_BITS                       1
#define BRPHY0_DSP_TAP_TAP8_C1_GAMMA_OV_SHIFT                      13

/* BRPHY0_DSP_TAP :: TAP8_C1 :: FFE_COARSE_OV [12:08] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x1f00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x1f00,8)
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_COARSE_OV_MASK                  0x1f00
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_COARSE_OV_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_COARSE_OV_BITS                  5
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_COARSE_OV_SHIFT                 8

/* BRPHY0_DSP_TAP :: TAP8_C1 :: FFE_PF_OV_INIT [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x80,7)
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_MASK                 0x0080
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_ALIGN                0
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_BITS                 1
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_SHIFT                7

/* BRPHY0_DSP_TAP :: TAP8_C1 :: SINGLE_STEP_MODE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x40,6)
#define BRPHY0_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_MASK               0x0040
#define BRPHY0_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_BITS               1
#define BRPHY0_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_SHIFT              6

/* BRPHY0_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SEL [05:04] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x30,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x30,4)
#define BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_MASK               0x0030
#define BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_ALIGN              0
#define BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_BITS               2
#define BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_SHIFT              4

/* BRPHY0_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SE_EN [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x8,3)
#define BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_MASK             0x0008
#define BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_ALIGN            0
#define BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_BITS             1
#define BRPHY0_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_SHIFT            3

/* BRPHY0_DSP_TAP :: TAP8_C1 :: TX_HALFOUT_OV [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x4,2)
#define BRPHY0_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_MASK                  0x0004
#define BRPHY0_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_BITS                  1
#define BRPHY0_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_SHIFT                 2

/* BRPHY0_DSP_TAP :: TAP8_C1 :: TX_ADJ_EN [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x2,1)
#define BRPHY0_DSP_TAP_TAP8_C1_TX_ADJ_EN_MASK                      0x0002
#define BRPHY0_DSP_TAP_TAP8_C1_TX_ADJ_EN_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP8_C1_TX_ADJ_EN_BITS                      1
#define BRPHY0_DSP_TAP_TAP8_C1_TX_ADJ_EN_SHIFT                     1

/* BRPHY0_DSP_TAP :: TAP8_C1 :: FFE_BUMP_EN [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C1,0x1,0)
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_BUMP_EN_MASK                    0x0001
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_BUMP_EN_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_BUMP_EN_BITS                    1
#define BRPHY0_DSP_TAP_TAP8_C1_FFE_BUMP_EN_SHIFT                   0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP8_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP8_C2 :: LEVELSELECT [15:13] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_LEVELSELECT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0xe000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_LEVELSELECT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0xe000,13)
#define BRPHY0_DSP_TAP_TAP8_C2_LEVELSELECT_MASK                    0xe000
#define BRPHY0_DSP_TAP_TAP8_C2_LEVELSELECT_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP8_C2_LEVELSELECT_BITS                    3
#define BRPHY0_DSP_TAP_TAP8_C2_LEVELSELECT_SHIFT                   13

/* BRPHY0_DSP_TAP :: TAP8_C2 :: FAILING_CHANNEL [12:11] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x1800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x1800,11)
#define BRPHY0_DSP_TAP_TAP8_C2_FAILING_CHANNEL_MASK                0x1800
#define BRPHY0_DSP_TAP_TAP8_C2_FAILING_CHANNEL_ALIGN               0
#define BRPHY0_DSP_TAP_TAP8_C2_FAILING_CHANNEL_BITS                2
#define BRPHY0_DSP_TAP_TAP8_C2_FAILING_CHANNEL_SHIFT               11

/* BRPHY0_DSP_TAP :: TAP8_C2 :: CONV_FAIL_FLAG [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x400,10)
#define BRPHY0_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_MASK                 0x0400
#define BRPHY0_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_ALIGN                0
#define BRPHY0_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_BITS                 1
#define BRPHY0_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_SHIFT                10

/* BRPHY0_DSP_TAP :: TAP8_C2 :: SYM_ERR_FAIL_FLAG [09:09] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x200,9)
#define BRPHY0_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_MASK              0x0200
#define BRPHY0_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_ALIGN             0
#define BRPHY0_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_BITS              1
#define BRPHY0_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_SHIFT             9

/* BRPHY0_DSP_TAP :: TAP8_C2 :: MAX_OFFSET_FAIL_FLAG [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x100,8)
#define BRPHY0_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_MASK           0x0100
#define BRPHY0_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_ALIGN          0
#define BRPHY0_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_BITS           1
#define BRPHY0_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_SHIFT          8

/* BRPHY0_DSP_TAP :: TAP8_C2 :: PEAK_ERR_FAIL_FLAG [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x80,7)
#define BRPHY0_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_MASK             0x0080
#define BRPHY0_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_ALIGN            0
#define BRPHY0_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_BITS             1
#define BRPHY0_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_SHIFT            7

/* BRPHY0_DSP_TAP :: TAP8_C2 :: MSE_FAIL_FLAG [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x40,6)
#define BRPHY0_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_MASK                  0x0040
#define BRPHY0_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_BITS                  1
#define BRPHY0_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_SHIFT                 6

/* BRPHY0_DSP_TAP :: TAP8_C2 :: GAIN_AMP_FAIL_FLAG [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x20,5)
#define BRPHY0_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_MASK             0x0020
#define BRPHY0_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_ALIGN            0
#define BRPHY0_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_BITS             1
#define BRPHY0_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_SHIFT            5

/* BRPHY0_DSP_TAP :: TAP8_C2 :: ABIST_COMPLETE_FLAG [04:04] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0x10,4)
#define BRPHY0_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_MASK            0x0010
#define BRPHY0_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_ALIGN           0
#define BRPHY0_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_BITS            1
#define BRPHY0_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_SHIFT           4

/* BRPHY0_DSP_TAP :: TAP8_C2 :: ADC_OVERFLOW [03:00] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C2,0xf,0)
#define BRPHY0_DSP_TAP_TAP8_C2_ADC_OVERFLOW_MASK                   0x000f
#define BRPHY0_DSP_TAP_TAP8_C2_ADC_OVERFLOW_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP8_C2_ADC_OVERFLOW_BITS                   4
#define BRPHY0_DSP_TAP_TAP8_C2_ADC_OVERFLOW_SHIFT                  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP8_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP8_C3 :: SPARE [15:12] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C3_SPARE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C3,0xf000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C3_SPARE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C3,0xf000,12)
#define BRPHY0_DSP_TAP_TAP8_C3_SPARE_MASK                          0xf000
#define BRPHY0_DSP_TAP_TAP8_C3_SPARE_ALIGN                         0
#define BRPHY0_DSP_TAP_TAP8_C3_SPARE_BITS                          4
#define BRPHY0_DSP_TAP_TAP8_C3_SPARE_SHIFT                         12

/* BRPHY0_DSP_TAP :: TAP8_C3 :: BR_AGC_RST_VAL [11:10] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C3,0xc00,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C3,0xc00,10)
#define BRPHY0_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_MASK                 0x0c00
#define BRPHY0_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_ALIGN                0
#define BRPHY0_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_BITS                 2
#define BRPHY0_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_SHIFT                10

/* BRPHY0_DSP_TAP :: TAP8_C3 :: BR_HPF_CTL [09:00] */
#define Wr_BRPHY0_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP8_C3,0x3ff,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP8_C3,0x3ff,0)
#define BRPHY0_DSP_TAP_TAP8_C3_BR_HPF_CTL_MASK                     0x03ff
#define BRPHY0_DSP_TAP_TAP8_C3_BR_HPF_CTL_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP8_C3_BR_HPF_CTL_BITS                     10
#define BRPHY0_DSP_TAP_TAP8_C3_BR_HPF_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP9
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP9 :: FREQ_REG [15:04] */
#define Wr_BRPHY0_DSP_TAP_TAP9_FREQ_REG(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP9,0xfff0,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP9_FREQ_REG(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP9,0xfff0,4)
#define BRPHY0_DSP_TAP_TAP9_FREQ_REG_MASK                          0xfff0
#define BRPHY0_DSP_TAP_TAP9_FREQ_REG_ALIGN                         0
#define BRPHY0_DSP_TAP_TAP9_FREQ_REG_BITS                          12
#define BRPHY0_DSP_TAP_TAP9_FREQ_REG_SHIFT                         4

/* BRPHY0_DSP_TAP :: TAP9 :: FREQ_REG_OV_EN_ABCD [03:00] */
#define Wr_BRPHY0_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP9,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP9,0xf,0)
#define BRPHY0_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_MASK               0x000f
#define BRPHY0_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_ALIGN              0
#define BRPHY0_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_BITS               4
#define BRPHY0_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_SHIFT              0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP10
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP10 :: SLAVEENCCONVADJUST [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP10,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP10,0x8000,15)
#define BRPHY0_DSP_TAP_TAP10_SLAVEENCCONVADJUST_MASK               0x8000
#define BRPHY0_DSP_TAP_TAP10_SLAVEENCCONVADJUST_ALIGN              0
#define BRPHY0_DSP_TAP_TAP10_SLAVEENCCONVADJUST_BITS               1
#define BRPHY0_DSP_TAP_TAP10_SLAVEENCCONVADJUST_SHIFT              15

/* BRPHY0_DSP_TAP :: TAP10 :: TRIM_HYB [14:11] */
#define Wr_BRPHY0_DSP_TAP_TAP10_TRIM_HYB(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP10,0x7800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP10_TRIM_HYB(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP10,0x7800,11)
#define BRPHY0_DSP_TAP_TAP10_TRIM_HYB_MASK                         0x7800
#define BRPHY0_DSP_TAP_TAP10_TRIM_HYB_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP10_TRIM_HYB_BITS                         4
#define BRPHY0_DSP_TAP_TAP10_TRIM_HYB_SHIFT                        11

/* BRPHY0_DSP_TAP :: TAP10 :: FFE_GAMMA_OV [10:09] */
#define Wr_BRPHY0_DSP_TAP_TAP10_FFE_GAMMA_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP10,0x600,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP10_FFE_GAMMA_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP10,0x600,9)
#define BRPHY0_DSP_TAP_TAP10_FFE_GAMMA_OV_MASK                     0x0600
#define BRPHY0_DSP_TAP_TAP10_FFE_GAMMA_OV_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP10_FFE_GAMMA_OV_BITS                     2
#define BRPHY0_DSP_TAP_TAP10_FFE_GAMMA_OV_SHIFT                    9

/* BRPHY0_DSP_TAP :: TAP10 :: TX_PHASE_CTL_BW_SEL [08:07] */
#define Wr_BRPHY0_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP10,0x180,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP10,0x180,7)
#define BRPHY0_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_MASK              0x0180
#define BRPHY0_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_ALIGN             0
#define BRPHY0_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_BITS              2
#define BRPHY0_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_SHIFT             7

/* BRPHY0_DSP_TAP :: TAP10 :: RESET_PATH_METRICS [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP10_RESET_PATH_METRICS(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP10,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP10_RESET_PATH_METRICS(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP10,0x40,6)
#define BRPHY0_DSP_TAP_TAP10_RESET_PATH_METRICS_MASK               0x0040
#define BRPHY0_DSP_TAP_TAP10_RESET_PATH_METRICS_ALIGN              0
#define BRPHY0_DSP_TAP_TAP10_RESET_PATH_METRICS_BITS               1
#define BRPHY0_DSP_TAP_TAP10_RESET_PATH_METRICS_SHIFT              6

/* BRPHY0_DSP_TAP :: TAP10 :: GBT_PLL_BW_CTL_STARTUP [05:03] */
#define Wr_BRPHY0_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP10,0x38,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP10,0x38,3)
#define BRPHY0_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_MASK           0x0038
#define BRPHY0_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_ALIGN          0
#define BRPHY0_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_BITS           3
#define BRPHY0_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_SHIFT          3

/* BRPHY0_DSP_TAP :: TAP10 :: BGT_PLL_BW_CTL_NORMAL_OP [02:00] */
#define Wr_BRPHY0_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP10,0x7,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP10,0x7,0)
#define BRPHY0_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_MASK         0x0007
#define BRPHY0_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_ALIGN        0
#define BRPHY0_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_BITS         3
#define BRPHY0_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_SHIFT        0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP11
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP11 :: TCLK_OFFSET_STROBE [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP11,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP11,0x8000,15)
#define BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_MASK               0x8000
#define BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_BITS               1
#define BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_SHIFT              15

/* BRPHY0_DSP_TAP :: TAP11 :: RCLK_OFFSET_STROBE [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP11,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP11,0x4000,14)
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_MASK               0x4000
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_BITS               1
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_SHIFT              14

/* BRPHY0_DSP_TAP :: TAP11 :: reserved0 [13:13] */
#define BRPHY0_DSP_TAP_TAP11_RESERVED0_MASK                        0x2000
#define BRPHY0_DSP_TAP_TAP11_RESERVED0_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP11_RESERVED0_BITS                        1
#define BRPHY0_DSP_TAP_TAP11_RESERVED0_SHIFT                       13

/* BRPHY0_DSP_TAP :: TAP11 :: RCLK_OFFSET_FREEZE [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP11,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP11,0x1000,12)
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_MASK               0x1000
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_BITS               1
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_SHIFT              12

/* BRPHY0_DSP_TAP :: TAP11 :: TCLK_OFFSET [11:06] */
#define Wr_BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP11,0xfc0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP11,0xfc0,6)
#define BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_MASK                      0x0fc0
#define BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_BITS                      6
#define BRPHY0_DSP_TAP_TAP11_TCLK_OFFSET_SHIFT                     6

/* BRPHY0_DSP_TAP :: TAP11 :: RCLK_OFFSET [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP11,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP11,0x3f,0)
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_MASK                      0x003f
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_BITS                      6
#define BRPHY0_DSP_TAP_TAP11_RCLK_OFFSET_SHIFT                     0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP12_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP12_C0 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_TAP12_C0_RESERVED0_MASK                     0xff00
#define BRPHY0_DSP_TAP_TAP12_C0_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP12_C0_RESERVED0_BITS                     8
#define BRPHY0_DSP_TAP_TAP12_C0_RESERVED0_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C0,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C0,0x80,7)
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY0_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C0,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C0,0x40,6)
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY0_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C0,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C0,0x3f,0)
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_MASK                   0x003f
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_BITS                   6
#define BRPHY0_DSP_TAP_TAP12_C0_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP12_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP12_C1 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_TAP12_C1_RESERVED0_MASK                     0xff00
#define BRPHY0_DSP_TAP_TAP12_C1_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP12_C1_RESERVED0_BITS                     8
#define BRPHY0_DSP_TAP_TAP12_C1_RESERVED0_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C1,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C1,0x80,7)
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY0_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C1,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C1,0x40,6)
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY0_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C1,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C1,0x3f,0)
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_MASK                   0x003f
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_BITS                   6
#define BRPHY0_DSP_TAP_TAP12_C1_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP12_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP12_C2 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_TAP12_C2_RESERVED0_MASK                     0xff00
#define BRPHY0_DSP_TAP_TAP12_C2_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP12_C2_RESERVED0_BITS                     8
#define BRPHY0_DSP_TAP_TAP12_C2_RESERVED0_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C2,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C2,0x80,7)
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY0_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C2,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C2,0x40,6)
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY0_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C2,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C2,0x3f,0)
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_MASK                   0x003f
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_BITS                   6
#define BRPHY0_DSP_TAP_TAP12_C2_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP12_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP12_C3 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_TAP12_C3_RESERVED0_MASK                     0xff00
#define BRPHY0_DSP_TAP_TAP12_C3_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP12_C3_RESERVED0_BITS                     8
#define BRPHY0_DSP_TAP_TAP12_C3_RESERVED0_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C3,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C3,0x80,7)
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY0_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C3,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C3,0x40,6)
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY0_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP12_C3,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP12_C3,0x3f,0)
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_MASK                   0x003f
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_BITS                   6
#define BRPHY0_DSP_TAP_TAP12_C3_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP13
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP13 :: TMPLATE_EN [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP13_TMPLATE_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_TMPLATE_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0x8000,15)
#define BRPHY0_DSP_TAP_TAP13_TMPLATE_EN_MASK                       0x8000
#define BRPHY0_DSP_TAP_TAP13_TMPLATE_EN_ALIGN                      0
#define BRPHY0_DSP_TAP_TAP13_TMPLATE_EN_BITS                       1
#define BRPHY0_DSP_TAP_TAP13_TMPLATE_EN_SHIFT                      15

/* BRPHY0_DSP_TAP :: TAP13 :: PATTERN_DURATION [14:13] */
#define Wr_BRPHY0_DSP_TAP_TAP13_PATTERN_DURATION(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0x6000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_PATTERN_DURATION(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0x6000,13)
#define BRPHY0_DSP_TAP_TAP13_PATTERN_DURATION_MASK                 0x6000
#define BRPHY0_DSP_TAP_TAP13_PATTERN_DURATION_ALIGN                0
#define BRPHY0_DSP_TAP_TAP13_PATTERN_DURATION_BITS                 2
#define BRPHY0_DSP_TAP_TAP13_PATTERN_DURATION_SHIFT                13

/* BRPHY0_DSP_TAP :: TAP13 :: PATTERN_SEL [12:11] */
#define Wr_BRPHY0_DSP_TAP_TAP13_PATTERN_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0x1800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_PATTERN_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0x1800,11)
#define BRPHY0_DSP_TAP_TAP13_PATTERN_SEL_MASK                      0x1800
#define BRPHY0_DSP_TAP_TAP13_PATTERN_SEL_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP13_PATTERN_SEL_BITS                      2
#define BRPHY0_DSP_TAP_TAP13_PATTERN_SEL_SHIFT                     11

/* BRPHY0_DSP_TAP :: TAP13 :: PATTERN_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP13_PATTERN_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_PATTERN_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0x400,10)
#define BRPHY0_DSP_TAP_TAP13_PATTERN_EN_MASK                       0x0400
#define BRPHY0_DSP_TAP_TAP13_PATTERN_EN_ALIGN                      0
#define BRPHY0_DSP_TAP_TAP13_PATTERN_EN_BITS                       1
#define BRPHY0_DSP_TAP_TAP13_PATTERN_EN_SHIFT                      10

/* BRPHY0_DSP_TAP :: TAP13 :: DISABLETRRRGEN [09:09] */
#define Wr_BRPHY0_DSP_TAP_TAP13_DISABLETRRRGEN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_DISABLETRRRGEN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0x200,9)
#define BRPHY0_DSP_TAP_TAP13_DISABLETRRRGEN_MASK                   0x0200
#define BRPHY0_DSP_TAP_TAP13_DISABLETRRRGEN_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP13_DISABLETRRRGEN_BITS                   1
#define BRPHY0_DSP_TAP_TAP13_DISABLETRRRGEN_SHIFT                  9

/* BRPHY0_DSP_TAP :: TAP13 :: DISABLE10BEXTENSION [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0x100,8)
#define BRPHY0_DSP_TAP_TAP13_DISABLE10BEXTENSION_MASK              0x0100
#define BRPHY0_DSP_TAP_TAP13_DISABLE10BEXTENSION_ALIGN             0
#define BRPHY0_DSP_TAP_TAP13_DISABLE10BEXTENSION_BITS              1
#define BRPHY0_DSP_TAP_TAP13_DISABLE10BEXTENSION_SHIFT             8

/* BRPHY0_DSP_TAP :: TAP13 :: ALIGN_OK1_DISABLE [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0x80,7)
#define BRPHY0_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_MASK                0x0080
#define BRPHY0_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_ALIGN               0
#define BRPHY0_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_BITS                1
#define BRPHY0_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_SHIFT               7

/* BRPHY0_DSP_TAP :: TAP13 :: ALIGN_OK2_DISABLE [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0x40,6)
#define BRPHY0_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_MASK                0x0040
#define BRPHY0_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_ALIGN               0
#define BRPHY0_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_BITS                1
#define BRPHY0_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_SHIFT               6

/* BRPHY0_DSP_TAP :: TAP13 :: DISABLE_ADC_LSBS [05:04] */
#define Wr_BRPHY0_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0x30,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0x30,4)
#define BRPHY0_DSP_TAP_TAP13_DISABLE_ADC_LSBS_MASK                 0x0030
#define BRPHY0_DSP_TAP_TAP13_DISABLE_ADC_LSBS_ALIGN                0
#define BRPHY0_DSP_TAP_TAP13_DISABLE_ADC_LSBS_BITS                 2
#define BRPHY0_DSP_TAP_TAP13_DISABLE_ADC_LSBS_SHIFT                4

/* BRPHY0_DSP_TAP :: TAP13 :: IDLE_EXT_MASK [03:02] */
#define Wr_BRPHY0_DSP_TAP_TAP13_IDLE_EXT_MASK(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP13,0xc,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP13_IDLE_EXT_MASK(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP13,0xc,2)
#define BRPHY0_DSP_TAP_TAP13_IDLE_EXT_MASK_MASK                    0x000c
#define BRPHY0_DSP_TAP_TAP13_IDLE_EXT_MASK_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP13_IDLE_EXT_MASK_BITS                    2
#define BRPHY0_DSP_TAP_TAP13_IDLE_EXT_MASK_SHIFT                   2

/* BRPHY0_DSP_TAP :: TAP13 :: reserved0 [01:00] */
#define BRPHY0_DSP_TAP_TAP13_RESERVED0_MASK                        0x0003
#define BRPHY0_DSP_TAP_TAP13_RESERVED0_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP13_RESERVED0_BITS                        2
#define BRPHY0_DSP_TAP_TAP13_RESERVED0_SHIFT                       0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP14
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP14 :: MSE_THD_1_LSB [15:08] */
#define Wr_BRPHY0_DSP_TAP_TAP14_MSE_THD_1_LSB(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP14,0xff00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP14_MSE_THD_1_LSB(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP14,0xff00,8)
#define BRPHY0_DSP_TAP_TAP14_MSE_THD_1_LSB_MASK                    0xff00
#define BRPHY0_DSP_TAP_TAP14_MSE_THD_1_LSB_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP14_MSE_THD_1_LSB_BITS                    8
#define BRPHY0_DSP_TAP_TAP14_MSE_THD_1_LSB_SHIFT                   8

/* BRPHY0_DSP_TAP :: TAP14 :: ENERGY_DET_THD [07:00] */
#define Wr_BRPHY0_DSP_TAP_TAP14_ENERGY_DET_THD(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP14,0xff,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP14_ENERGY_DET_THD(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP14,0xff,0)
#define BRPHY0_DSP_TAP_TAP14_ENERGY_DET_THD_MASK                   0x00ff
#define BRPHY0_DSP_TAP_TAP14_ENERGY_DET_THD_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP14_ENERGY_DET_THD_BITS                   8
#define BRPHY0_DSP_TAP_TAP14_ENERGY_DET_THD_SHIFT                  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP15
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP15 :: MSE_THD_3_SEL [15:14] */
#define Wr_BRPHY0_DSP_TAP_TAP15_MSE_THD_3_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP15,0xc000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP15_MSE_THD_3_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP15,0xc000,14)
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_3_SEL_MASK                    0xc000
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_3_SEL_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_3_SEL_BITS                    2
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_3_SEL_SHIFT                   14

/* BRPHY0_DSP_TAP :: TAP15 :: MSE_THD_2 [13:02] */
#define Wr_BRPHY0_DSP_TAP_TAP15_MSE_THD_2(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP15,0x3ffc,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP15_MSE_THD_2(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP15,0x3ffc,2)
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_2_MASK                        0x3ffc
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_2_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_2_BITS                        12
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_2_SHIFT                       2

/* BRPHY0_DSP_TAP :: TAP15 :: MSE_THD_1_MSB [01:00] */
#define Wr_BRPHY0_DSP_TAP_TAP15_MSE_THD_1_MSB(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP15,0x3,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP15_MSE_THD_1_MSB(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP15,0x3,0)
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_1_MSB_MASK                    0x0003
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_1_MSB_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_1_MSB_BITS                    2
#define BRPHY0_DSP_TAP_TAP15_MSE_THD_1_MSB_SHIFT                   0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP16_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP16_C0 :: LA_TRIGGER_DELAY [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) WriteReg16(BRPHY0_DSP_TAP_TAP16_C0,x)
#define Rd_BRPHY0_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) ReadReg16(BRPHY0_DSP_TAP_TAP16_C0)
#define BRPHY0_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_MASK              0xffff
#define BRPHY0_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_ALIGN             0
#define BRPHY0_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_BITS              16
#define BRPHY0_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_SHIFT             0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP16_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP16_C1 :: BIST_CRC [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP16_C1_BIST_CRC(x) WriteReg16(BRPHY0_DSP_TAP_TAP16_C1,x)
#define Rd_BRPHY0_DSP_TAP_TAP16_C1_BIST_CRC(x) ReadReg16(BRPHY0_DSP_TAP_TAP16_C1)
#define BRPHY0_DSP_TAP_TAP16_C1_BIST_CRC_MASK                      0xffff
#define BRPHY0_DSP_TAP_TAP16_C1_BIST_CRC_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP16_C1_BIST_CRC_BITS                      16
#define BRPHY0_DSP_TAP_TAP16_C1_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP16_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP16_C2 :: BIST_CRC [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP16_C2_BIST_CRC(x) WriteReg16(BRPHY0_DSP_TAP_TAP16_C2,x)
#define Rd_BRPHY0_DSP_TAP_TAP16_C2_BIST_CRC(x) ReadReg16(BRPHY0_DSP_TAP_TAP16_C2)
#define BRPHY0_DSP_TAP_TAP16_C2_BIST_CRC_MASK                      0xffff
#define BRPHY0_DSP_TAP_TAP16_C2_BIST_CRC_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP16_C2_BIST_CRC_BITS                      16
#define BRPHY0_DSP_TAP_TAP16_C2_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP16_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP16_C3 :: BIST_CRC [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP16_C3_BIST_CRC(x) WriteReg16(BRPHY0_DSP_TAP_TAP16_C3,x)
#define Rd_BRPHY0_DSP_TAP_TAP16_C3_BIST_CRC(x) ReadReg16(BRPHY0_DSP_TAP_TAP16_C3)
#define BRPHY0_DSP_TAP_TAP16_C3_BIST_CRC_MASK                      0xffff
#define BRPHY0_DSP_TAP_TAP16_C3_BIST_CRC_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP16_C3_BIST_CRC_BITS                      16
#define BRPHY0_DSP_TAP_TAP16_C3_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP17_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP17_C0 :: TESTVALUE [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C0_TESTVALUE(x) WriteReg16(BRPHY0_DSP_TAP_TAP17_C0,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C0_TESTVALUE(x) ReadReg16(BRPHY0_DSP_TAP_TAP17_C0)
#define BRPHY0_DSP_TAP_TAP17_C0_TESTVALUE_MASK                     0xffff
#define BRPHY0_DSP_TAP_TAP17_C0_TESTVALUE_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP17_C0_TESTVALUE_BITS                     16
#define BRPHY0_DSP_TAP_TAP17_C0_TESTVALUE_SHIFT                    0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP17_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP17_C1 :: LA_ACQ_DONE [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x8000,15)
#define BRPHY0_DSP_TAP_TAP17_C1_LA_ACQ_DONE_MASK                   0x8000
#define BRPHY0_DSP_TAP_TAP17_C1_LA_ACQ_DONE_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP17_C1_LA_ACQ_DONE_BITS                   1
#define BRPHY0_DSP_TAP_TAP17_C1_LA_ACQ_DONE_SHIFT                  15

/* BRPHY0_DSP_TAP :: TAP17_C1 :: LA_TPOUT_SEL [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x4000,14)
#define BRPHY0_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_MASK                  0x4000
#define BRPHY0_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_BITS                  1
#define BRPHY0_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_SHIFT                 14

/* BRPHY0_DSP_TAP :: TAP17_C1 :: LA_CLK_DIVISOR [13:11] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x3800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x3800,11)
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_MASK                0x3800
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_ALIGN               0
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_BITS                3
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_SHIFT               11

/* BRPHY0_DSP_TAP :: TAP17_C1 :: LA_CLK_DELAY [10:09] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x600,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x600,9)
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DELAY_MASK                  0x0600
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DELAY_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DELAY_BITS                  2
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_DELAY_SHIFT                 9

/* BRPHY0_DSP_TAP :: TAP17_C1 :: LA_CLK_EDGE [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x100,8)
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_EDGE_MASK                   0x0100
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_EDGE_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_EDGE_BITS                   1
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_EDGE_SHIFT                  8

/* BRPHY0_DSP_TAP :: TAP17_C1 :: LA_CLK_SEL [07:03] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0xf8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0xf8,3)
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_SEL_MASK                    0x00f8
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_SEL_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_SEL_BITS                    5
#define BRPHY0_DSP_TAP_TAP17_C1_LA_CLK_SEL_SHIFT                   3

/* BRPHY0_DSP_TAP :: TAP17_C1 :: LA_ENABLE [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C1_LA_ENABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C1_LA_ENABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x4,2)
#define BRPHY0_DSP_TAP_TAP17_C1_LA_ENABLE_MASK                     0x0004
#define BRPHY0_DSP_TAP_TAP17_C1_LA_ENABLE_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP17_C1_LA_ENABLE_BITS                     1
#define BRPHY0_DSP_TAP_TAP17_C1_LA_ENABLE_SHIFT                    2

/* BRPHY0_DSP_TAP :: TAP17_C1 :: TESTMODE_STROBE [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x2,1)
#define BRPHY0_DSP_TAP_TAP17_C1_TESTMODE_STROBE_MASK               0x0002
#define BRPHY0_DSP_TAP_TAP17_C1_TESTMODE_STROBE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP17_C1_TESTMODE_STROBE_BITS               1
#define BRPHY0_DSP_TAP_TAP17_C1_TESTMODE_STROBE_SHIFT              1

/* BRPHY0_DSP_TAP :: TAP17_C1 :: LSITEST_SMDSP [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C1,0x1,0)
#define BRPHY0_DSP_TAP_TAP17_C1_LSITEST_SMDSP_MASK                 0x0001
#define BRPHY0_DSP_TAP_TAP17_C1_LSITEST_SMDSP_ALIGN                0
#define BRPHY0_DSP_TAP_TAP17_C1_LSITEST_SMDSP_BITS                 1
#define BRPHY0_DSP_TAP_TAP17_C1_LSITEST_SMDSP_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP17_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP17_C2 :: TRIGGER2_LAT [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x8000,15)
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_LAT_MASK                  0x8000
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_LAT_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_LAT_BITS                  1
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_LAT_SHIFT                 15

/* BRPHY0_DSP_TAP :: TAP17_C2 :: TRIGGER2_INV [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x4000,14)
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_INV_MASK                  0x4000
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_INV_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_INV_BITS                  1
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_INV_SHIFT                 14

/* BRPHY0_DSP_TAP :: TAP17_C2 :: TRIGGER2_SEL [13:08] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x3f00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x3f00,8)
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_SEL_MASK                  0x3f00
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_SEL_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_SEL_BITS                  6
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER2_SEL_SHIFT                 8

/* BRPHY0_DSP_TAP :: TAP17_C2 :: TRIGGER1_LAT [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x80,7)
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_LAT_MASK                  0x0080
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_LAT_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_LAT_BITS                  1
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_LAT_SHIFT                 7

/* BRPHY0_DSP_TAP :: TAP17_C2 :: TRIGGER1_INV [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x40,6)
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_INV_MASK                  0x0040
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_INV_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_INV_BITS                  1
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_INV_SHIFT                 6

/* BRPHY0_DSP_TAP :: TAP17_C2 :: TRIGGER1_SEL [05:00] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x3f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C2,0x3f,0)
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_SEL_MASK                  0x003f
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_SEL_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_SEL_BITS                  6
#define BRPHY0_DSP_TAP_TAP17_C2_TRIGGER1_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP17_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP17_C3 :: LA_REARM_ACQ [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x8000,15)
#define BRPHY0_DSP_TAP_TAP17_C3_LA_REARM_ACQ_MASK                  0x8000
#define BRPHY0_DSP_TAP_TAP17_C3_LA_REARM_ACQ_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C3_LA_REARM_ACQ_BITS                  1
#define BRPHY0_DSP_TAP_TAP17_C3_LA_REARM_ACQ_SHIFT                 15

/* BRPHY0_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_DELAY_EN [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x4000,14)
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_MASK           0x4000
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_ALIGN          0
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_BITS           1
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_SHIFT          14

/* BRPHY0_DSP_TAP :: TAP17_C3 :: LA_POSTSTORE [13:06] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x3fc0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x3fc0,6)
#define BRPHY0_DSP_TAP_TAP17_C3_LA_POSTSTORE_MASK                  0x3fc0
#define BRPHY0_DSP_TAP_TAP17_C3_LA_POSTSTORE_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C3_LA_POSTSTORE_BITS                  8
#define BRPHY0_DSP_TAP_TAP17_C3_LA_POSTSTORE_SHIFT                 6

/* BRPHY0_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_TYPE [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x20,5)
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_MASK               0x0020
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_BITS               1
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_SHIFT              5

/* BRPHY0_DSP_TAP :: TAP17_C3 :: SPARE [04:04] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C3_SPARE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C3_SPARE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x10,4)
#define BRPHY0_DSP_TAP_TAP17_C3_SPARE_MASK                         0x0010
#define BRPHY0_DSP_TAP_TAP17_C3_SPARE_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP17_C3_SPARE_BITS                         1
#define BRPHY0_DSP_TAP_TAP17_C3_SPARE_SHIFT                        4

/* BRPHY0_DSP_TAP :: TAP17_C3 :: LA_CLKENABLE [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x8,3)
#define BRPHY0_DSP_TAP_TAP17_C3_LA_CLKENABLE_MASK                  0x0008
#define BRPHY0_DSP_TAP_TAP17_C3_LA_CLKENABLE_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP17_C3_LA_CLKENABLE_BITS                  1
#define BRPHY0_DSP_TAP_TAP17_C3_LA_CLKENABLE_SHIFT                 3

/* BRPHY0_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_INV [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x4,2)
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_MASK                0x0004
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_ALIGN               0
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_BITS                1
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_SHIFT               2

/* BRPHY0_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_GATE [01:00] */
#define Wr_BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x3,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP17_C3,0x3,0)
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_MASK               0x0003
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_BITS               2
#define BRPHY0_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_SHIFT              0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP18_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP18_C0 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_TAP18_C0_RESERVED0_MASK                     0xff00
#define BRPHY0_DSP_TAP_TAP18_C0_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP18_C0_RESERVED0_BITS                     8
#define BRPHY0_DSP_TAP_TAP18_C0_RESERVED0_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP18_C0 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY0_DSP_TAP_TAP18_C0_PEAK_NOISE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP18_C0,0xff,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP18_C0_PEAK_NOISE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP18_C0,0xff,0)
#define BRPHY0_DSP_TAP_TAP18_C0_PEAK_NOISE_MASK                    0x00ff
#define BRPHY0_DSP_TAP_TAP18_C0_PEAK_NOISE_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP18_C0_PEAK_NOISE_BITS                    8
#define BRPHY0_DSP_TAP_TAP18_C0_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP18_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP18_C1 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_TAP18_C1_RESERVED0_MASK                     0xff00
#define BRPHY0_DSP_TAP_TAP18_C1_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP18_C1_RESERVED0_BITS                     8
#define BRPHY0_DSP_TAP_TAP18_C1_RESERVED0_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP18_C1 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY0_DSP_TAP_TAP18_C1_PEAK_NOISE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP18_C1,0xff,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP18_C1_PEAK_NOISE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP18_C1,0xff,0)
#define BRPHY0_DSP_TAP_TAP18_C1_PEAK_NOISE_MASK                    0x00ff
#define BRPHY0_DSP_TAP_TAP18_C1_PEAK_NOISE_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP18_C1_PEAK_NOISE_BITS                    8
#define BRPHY0_DSP_TAP_TAP18_C1_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP18_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP18_C2 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_TAP18_C2_RESERVED0_MASK                     0xff00
#define BRPHY0_DSP_TAP_TAP18_C2_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP18_C2_RESERVED0_BITS                     8
#define BRPHY0_DSP_TAP_TAP18_C2_RESERVED0_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP18_C2 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY0_DSP_TAP_TAP18_C2_PEAK_NOISE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP18_C2,0xff,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP18_C2_PEAK_NOISE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP18_C2,0xff,0)
#define BRPHY0_DSP_TAP_TAP18_C2_PEAK_NOISE_MASK                    0x00ff
#define BRPHY0_DSP_TAP_TAP18_C2_PEAK_NOISE_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP18_C2_PEAK_NOISE_BITS                    8
#define BRPHY0_DSP_TAP_TAP18_C2_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP18_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP18_C3 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_TAP18_C3_RESERVED0_MASK                     0xff00
#define BRPHY0_DSP_TAP_TAP18_C3_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP18_C3_RESERVED0_BITS                     8
#define BRPHY0_DSP_TAP_TAP18_C3_RESERVED0_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP18_C3 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY0_DSP_TAP_TAP18_C3_PEAK_NOISE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP18_C3,0xff,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP18_C3_PEAK_NOISE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP18_C3,0xff,0)
#define BRPHY0_DSP_TAP_TAP18_C3_PEAK_NOISE_MASK                    0x00ff
#define BRPHY0_DSP_TAP_TAP18_C3_PEAK_NOISE_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP18_C3_PEAK_NOISE_BITS                    8
#define BRPHY0_DSP_TAP_TAP18_C3_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP20
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP20 :: reserved0 [15:14] */
#define BRPHY0_DSP_TAP_TAP20_RESERVED0_MASK                        0xc000
#define BRPHY0_DSP_TAP_TAP20_RESERVED0_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP20_RESERVED0_BITS                        2
#define BRPHY0_DSP_TAP_TAP20_RESERVED0_SHIFT                       14

/* BRPHY0_DSP_TAP :: TAP20 :: ENC_FIR_PATH_DELAY_ADJ [13:11] */
#define Wr_BRPHY0_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP20,0x3800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP20,0x3800,11)
#define BRPHY0_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_MASK           0x3800
#define BRPHY0_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY0_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_BITS           3
#define BRPHY0_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_SHIFT          11

/* BRPHY0_DSP_TAP :: TAP20 :: ENC_LMS_PATH_DELAY_ADJ [10:08] */
#define Wr_BRPHY0_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP20,0x700,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP20,0x700,8)
#define BRPHY0_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_MASK           0x0700
#define BRPHY0_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY0_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_BITS           3
#define BRPHY0_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_SHIFT          8

/* BRPHY0_DSP_TAP :: TAP20 :: ECHO_LMS_GAIN [07:06] */
#define Wr_BRPHY0_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP20,0xc0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP20,0xc0,6)
#define BRPHY0_DSP_TAP_TAP20_ECHO_LMS_GAIN_MASK                    0x00c0
#define BRPHY0_DSP_TAP_TAP20_ECHO_LMS_GAIN_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP20_ECHO_LMS_GAIN_BITS                    2
#define BRPHY0_DSP_TAP_TAP20_ECHO_LMS_GAIN_SHIFT                   6

/* BRPHY0_DSP_TAP :: TAP20 :: reserved1 [05:04] */
#define BRPHY0_DSP_TAP_TAP20_RESERVED1_MASK                        0x0030
#define BRPHY0_DSP_TAP_TAP20_RESERVED1_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP20_RESERVED1_BITS                        2
#define BRPHY0_DSP_TAP_TAP20_RESERVED1_SHIFT                       4

/* BRPHY0_DSP_TAP :: TAP20 :: TXDIG_PATH_DELAY_CTL [03:00] */
#define Wr_BRPHY0_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP20,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP20,0xf,0)
#define BRPHY0_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_MASK             0x000f
#define BRPHY0_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_ALIGN            0
#define BRPHY0_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_BITS             4
#define BRPHY0_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_SHIFT            0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP21
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP21 :: reserved0 [15:13] */
#define BRPHY0_DSP_TAP_TAP21_RESERVED0_MASK                        0xe000
#define BRPHY0_DSP_TAP_TAP21_RESERVED0_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP21_RESERVED0_BITS                        3
#define BRPHY0_DSP_TAP_TAP21_RESERVED0_SHIFT                       13

/* BRPHY0_DSP_TAP :: TAP21 :: PAUSEPCTPM_ABCD [12:09] */
#define Wr_BRPHY0_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP21,0x1e00,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP21,0x1e00,9)
#define BRPHY0_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_MASK                  0x1e00
#define BRPHY0_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_BITS                  4
#define BRPHY0_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_SHIFT                 9

/* BRPHY0_DSP_TAP :: TAP21 :: TX_EN_MON [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP21_TX_EN_MON(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP21,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP21_TX_EN_MON(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP21,0x100,8)
#define BRPHY0_DSP_TAP_TAP21_TX_EN_MON_MASK                        0x0100
#define BRPHY0_DSP_TAP_TAP21_TX_EN_MON_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP21_TX_EN_MON_BITS                        1
#define BRPHY0_DSP_TAP_TAP21_TX_EN_MON_SHIFT                       8

/* BRPHY0_DSP_TAP :: TAP21 :: LINK_CTL_1000T_MON [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP21,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP21,0x80,7)
#define BRPHY0_DSP_TAP_TAP21_LINK_CTL_1000T_MON_MASK               0x0080
#define BRPHY0_DSP_TAP_TAP21_LINK_CTL_1000T_MON_ALIGN              0
#define BRPHY0_DSP_TAP_TAP21_LINK_CTL_1000T_MON_BITS               1
#define BRPHY0_DSP_TAP_TAP21_LINK_CTL_1000T_MON_SHIFT              7

/* BRPHY0_DSP_TAP :: TAP21 :: REM_RCVR_STATUS_MON [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP21,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP21,0x40,6)
#define BRPHY0_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_MASK              0x0040
#define BRPHY0_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_ALIGN             0
#define BRPHY0_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_BITS              1
#define BRPHY0_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_SHIFT             6

/* BRPHY0_DSP_TAP :: TAP21 :: ALIGN_OK_MON [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP21_ALIGN_OK_MON(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP21,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP21_ALIGN_OK_MON(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP21,0x20,5)
#define BRPHY0_DSP_TAP_TAP21_ALIGN_OK_MON_MASK                     0x0020
#define BRPHY0_DSP_TAP_TAP21_ALIGN_OK_MON_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP21_ALIGN_OK_MON_BITS                     1
#define BRPHY0_DSP_TAP_TAP21_ALIGN_OK_MON_SHIFT                    5

/* BRPHY0_DSP_TAP :: TAP21 :: MAIN_PHYC_STATE [04:00] */
#define Wr_BRPHY0_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP21,0x1f,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP21,0x1f,0)
#define BRPHY0_DSP_TAP_TAP21_MAIN_PHYC_STATE_MASK                  0x001f
#define BRPHY0_DSP_TAP_TAP21_MAIN_PHYC_STATE_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP21_MAIN_PHYC_STATE_BITS                  5
#define BRPHY0_DSP_TAP_TAP21_MAIN_PHYC_STATE_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP22
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP22 :: KRDONE [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP22_KRDONE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP22,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP22_KRDONE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP22,0x8000,15)
#define BRPHY0_DSP_TAP_TAP22_KRDONE_MASK                           0x8000
#define BRPHY0_DSP_TAP_TAP22_KRDONE_ALIGN                          0
#define BRPHY0_DSP_TAP_TAP22_KRDONE_BITS                           1
#define BRPHY0_DSP_TAP_TAP22_KRDONE_SHIFT                          15

/* BRPHY0_DSP_TAP :: TAP22 :: MAXWAIT_TIMER_DONE [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP22,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP22,0x4000,14)
#define BRPHY0_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_MASK               0x4000
#define BRPHY0_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_BITS               1
#define BRPHY0_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_SHIFT              14

/* BRPHY0_DSP_TAP :: TAP22 :: LINK_MONITOR_STATE_MON [13:12] */
#define Wr_BRPHY0_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP22,0x3000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP22,0x3000,12)
#define BRPHY0_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_MASK           0x3000
#define BRPHY0_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_ALIGN          0
#define BRPHY0_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_BITS           2
#define BRPHY0_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_SHIFT          12

/* BRPHY0_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_D [11:09] */
#define Wr_BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP22,0xe00,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP22,0xe00,9)
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_D_MASK                  0x0e00
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_D_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_D_BITS                  3
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_D_SHIFT                 9

/* BRPHY0_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_C [08:06] */
#define Wr_BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP22,0x1c0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP22,0x1c0,6)
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_C_MASK                  0x01c0
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_C_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_C_BITS                  3
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_C_SHIFT                 6

/* BRPHY0_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_B [05:03] */
#define Wr_BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP22,0x38,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP22,0x38,3)
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_B_MASK                  0x0038
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_B_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_B_BITS                  3
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_B_SHIFT                 3

/* BRPHY0_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_A [02:00] */
#define Wr_BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP22,0x7,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP22,0x7,0)
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_A_MASK                  0x0007
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_A_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_A_BITS                  3
#define BRPHY0_DSP_TAP_TAP22_PHYC_SUBSTATE_A_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP23
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP23 :: reserved0 [15:13] */
#define BRPHY0_DSP_TAP_TAP23_RESERVED0_MASK                        0xe000
#define BRPHY0_DSP_TAP_TAP23_RESERVED0_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP23_RESERVED0_BITS                        3
#define BRPHY0_DSP_TAP_TAP23_RESERVED0_SHIFT                       13

/* BRPHY0_DSP_TAP :: TAP23 :: ALIGN_REDO_MON [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP23_ALIGN_REDO_MON(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP23,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP23_ALIGN_REDO_MON(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP23,0x1000,12)
#define BRPHY0_DSP_TAP_TAP23_ALIGN_REDO_MON_MASK                   0x1000
#define BRPHY0_DSP_TAP_TAP23_ALIGN_REDO_MON_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP23_ALIGN_REDO_MON_BITS                   1
#define BRPHY0_DSP_TAP_TAP23_ALIGN_REDO_MON_SHIFT                  12

/* BRPHY0_DSP_TAP :: TAP23 :: MSEOK2_MON [11:08] */
#define Wr_BRPHY0_DSP_TAP_TAP23_MSEOK2_MON(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP23,0xf00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP23_MSEOK2_MON(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP23,0xf00,8)
#define BRPHY0_DSP_TAP_TAP23_MSEOK2_MON_MASK                       0x0f00
#define BRPHY0_DSP_TAP_TAP23_MSEOK2_MON_ALIGN                      0
#define BRPHY0_DSP_TAP_TAP23_MSEOK2_MON_BITS                       4
#define BRPHY0_DSP_TAP_TAP23_MSEOK2_MON_SHIFT                      8

/* BRPHY0_DSP_TAP :: TAP23 :: MSEOK1_MON [07:04] */
#define Wr_BRPHY0_DSP_TAP_TAP23_MSEOK1_MON(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP23,0xf0,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP23_MSEOK1_MON(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP23,0xf0,4)
#define BRPHY0_DSP_TAP_TAP23_MSEOK1_MON_MASK                       0x00f0
#define BRPHY0_DSP_TAP_TAP23_MSEOK1_MON_ALIGN                      0
#define BRPHY0_DSP_TAP_TAP23_MSEOK1_MON_BITS                       4
#define BRPHY0_DSP_TAP_TAP23_MSEOK1_MON_SHIFT                      4

/* BRPHY0_DSP_TAP :: TAP23 :: ENERGY_DETECT [03:00] */
#define Wr_BRPHY0_DSP_TAP_TAP23_ENERGY_DETECT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP23,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP23_ENERGY_DETECT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP23,0xf,0)
#define BRPHY0_DSP_TAP_TAP23_ENERGY_DETECT_MASK                    0x000f
#define BRPHY0_DSP_TAP_TAP23_ENERGY_DETECT_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP23_ENERGY_DETECT_BITS                    4
#define BRPHY0_DSP_TAP_TAP23_ENERGY_DETECT_SHIFT                   0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP24
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP24 :: PHYC_OUTPUT_OV [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x8000,15)
#define BRPHY0_DSP_TAP_TAP24_PHYC_OUTPUT_OV_MASK                   0x8000
#define BRPHY0_DSP_TAP_TAP24_PHYC_OUTPUT_OV_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP24_PHYC_OUTPUT_OV_BITS                   1
#define BRPHY0_DSP_TAP_TAP24_PHYC_OUTPUT_OV_SHIFT                  15

/* BRPHY0_DSP_TAP :: TAP24 :: STABLE_RECENTER_EN [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x4000,14)
#define BRPHY0_DSP_TAP_TAP24_STABLE_RECENTER_EN_MASK               0x4000
#define BRPHY0_DSP_TAP_TAP24_STABLE_RECENTER_EN_ALIGN              0
#define BRPHY0_DSP_TAP_TAP24_STABLE_RECENTER_EN_BITS               1
#define BRPHY0_DSP_TAP_TAP24_STABLE_RECENTER_EN_SHIFT              14

/* BRPHY0_DSP_TAP :: TAP24 :: PHYC_MSE_FIX [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP24_PHYC_MSE_FIX(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_PHYC_MSE_FIX(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x2000,13)
#define BRPHY0_DSP_TAP_TAP24_PHYC_MSE_FIX_MASK                     0x2000
#define BRPHY0_DSP_TAP_TAP24_PHYC_MSE_FIX_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP24_PHYC_MSE_FIX_BITS                     1
#define BRPHY0_DSP_TAP_TAP24_PHYC_MSE_FIX_SHIFT                    13

/* BRPHY0_DSP_TAP :: TAP24 :: DEGATEDFEPC_ABCD_OV [12:09] */
#define Wr_BRPHY0_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x1e00,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x1e00,9)
#define BRPHY0_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_MASK              0x1e00
#define BRPHY0_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_ALIGN             0
#define BRPHY0_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_BITS              4
#define BRPHY0_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_SHIFT             9

/* BRPHY0_DSP_TAP :: TAP24 :: NBRSTWTCH_OV [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP24_NBRSTWTCH_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_NBRSTWTCH_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x100,8)
#define BRPHY0_DSP_TAP_TAP24_NBRSTWTCH_OV_MASK                     0x0100
#define BRPHY0_DSP_TAP_TAP24_NBRSTWTCH_OV_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP24_NBRSTWTCH_OV_BITS                     1
#define BRPHY0_DSP_TAP_TAP24_NBRSTWTCH_OV_SHIFT                    8

/* BRPHY0_DSP_TAP :: TAP24 :: RC_LPBKFIFO_T_OV [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x80,7)
#define BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_MASK                 0x0080
#define BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_ALIGN                0
#define BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_BITS                 1
#define BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_SHIFT                7

/* BRPHY0_DSP_TAP :: TAP24 :: RC_LPBKFIFO_N_OV [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x40,6)
#define BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_MASK                 0x0040
#define BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_ALIGN                0
#define BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_BITS                 1
#define BRPHY0_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_SHIFT                6

/* BRPHY0_DSP_TAP :: TAP24 :: PCS_RESET_OV [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP24_PCS_RESET_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_PCS_RESET_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x20,5)
#define BRPHY0_DSP_TAP_TAP24_PCS_RESET_OV_MASK                     0x0020
#define BRPHY0_DSP_TAP_TAP24_PCS_RESET_OV_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP24_PCS_RESET_OV_BITS                     1
#define BRPHY0_DSP_TAP_TAP24_PCS_RESET_OV_SHIFT                    5

/* BRPHY0_DSP_TAP :: TAP24 :: PHYC_PCS_RSTATE_OV [04:03] */
#define Wr_BRPHY0_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x18,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x18,3)
#define BRPHY0_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_MASK               0x0018
#define BRPHY0_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_ALIGN              0
#define BRPHY0_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_BITS               2
#define BRPHY0_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_SHIFT              3

/* BRPHY0_DSP_TAP :: TAP24 :: LOC_RCVR_STATUS_OV [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x4,2)
#define BRPHY0_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_MASK               0x0004
#define BRPHY0_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_ALIGN              0
#define BRPHY0_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_BITS               1
#define BRPHY0_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_SHIFT              2

/* BRPHY0_DSP_TAP :: TAP24 :: PHYC_TXMODE_OV [01:00] */
#define Wr_BRPHY0_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP24,0x3,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP24,0x3,0)
#define BRPHY0_DSP_TAP_TAP24_PHYC_TXMODE_OV_MASK                   0x0003
#define BRPHY0_DSP_TAP_TAP24_PHYC_TXMODE_OV_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP24_PHYC_TXMODE_OV_BITS                   2
#define BRPHY0_DSP_TAP_TAP24_PHYC_TXMODE_OV_SHIFT                  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP25
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP25 :: reserved0 [15:15] */
#define BRPHY0_DSP_TAP_TAP25_RESERVED0_MASK                        0x8000
#define BRPHY0_DSP_TAP_TAP25_RESERVED0_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP25_RESERVED0_BITS                        1
#define BRPHY0_DSP_TAP_TAP25_RESERVED0_SHIFT                       15

/* BRPHY0_DSP_TAP :: TAP25 :: KRDONE_OV [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP25_KRDONE_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP25,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP25_KRDONE_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP25,0x4000,14)
#define BRPHY0_DSP_TAP_TAP25_KRDONE_OV_MASK                        0x4000
#define BRPHY0_DSP_TAP_TAP25_KRDONE_OV_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP25_KRDONE_OV_BITS                        1
#define BRPHY0_DSP_TAP_TAP25_KRDONE_OV_SHIFT                       14

/* BRPHY0_DSP_TAP :: TAP25 :: ALIGN_REDO_OV [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP25_ALIGN_REDO_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP25,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP25_ALIGN_REDO_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP25,0x2000,13)
#define BRPHY0_DSP_TAP_TAP25_ALIGN_REDO_OV_MASK                    0x2000
#define BRPHY0_DSP_TAP_TAP25_ALIGN_REDO_OV_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP25_ALIGN_REDO_OV_BITS                    1
#define BRPHY0_DSP_TAP_TAP25_ALIGN_REDO_OV_SHIFT                   13

/* BRPHY0_DSP_TAP :: TAP25 :: RC_ADCFIFO_N_OV [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP25,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP25,0x1000,12)
#define BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_MASK                  0x1000
#define BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_BITS                  1
#define BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_SHIFT                 12

/* BRPHY0_DSP_TAP :: TAP25 :: RC_ADCFIFO_T_OV [11:08] */
#define Wr_BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP25,0xf00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP25,0xf00,8)
#define BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_MASK                  0x0f00
#define BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_BITS                  4
#define BRPHY0_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_SHIFT                 8

/* BRPHY0_DSP_TAP :: TAP25 :: reserved1 [07:00] */
#define BRPHY0_DSP_TAP_TAP25_RESERVED1_MASK                        0x00ff
#define BRPHY0_DSP_TAP_TAP25_RESERVED1_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP25_RESERVED1_BITS                        8
#define BRPHY0_DSP_TAP_TAP25_RESERVED1_SHIFT                       0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP26
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP26 :: MSE_INPUT_OV [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP26_MSE_INPUT_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP26,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP26_MSE_INPUT_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP26,0x8000,15)
#define BRPHY0_DSP_TAP_TAP26_MSE_INPUT_OV_MASK                     0x8000
#define BRPHY0_DSP_TAP_TAP26_MSE_INPUT_OV_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP26_MSE_INPUT_OV_BITS                     1
#define BRPHY0_DSP_TAP_TAP26_MSE_INPUT_OV_SHIFT                    15

/* BRPHY0_DSP_TAP :: TAP26 :: MSEOK2_OV [14:11] */
#define Wr_BRPHY0_DSP_TAP_TAP26_MSEOK2_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP26,0x7800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP26_MSEOK2_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP26,0x7800,11)
#define BRPHY0_DSP_TAP_TAP26_MSEOK2_OV_MASK                        0x7800
#define BRPHY0_DSP_TAP_TAP26_MSEOK2_OV_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP26_MSEOK2_OV_BITS                        4
#define BRPHY0_DSP_TAP_TAP26_MSEOK2_OV_SHIFT                       11

/* BRPHY0_DSP_TAP :: TAP26 :: MSEOK1_OV [10:07] */
#define Wr_BRPHY0_DSP_TAP_TAP26_MSEOK1_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP26,0x780,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP26_MSEOK1_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP26,0x780,7)
#define BRPHY0_DSP_TAP_TAP26_MSEOK1_OV_MASK                        0x0780
#define BRPHY0_DSP_TAP_TAP26_MSEOK1_OV_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP26_MSEOK1_OV_BITS                        4
#define BRPHY0_DSP_TAP_TAP26_MSEOK1_OV_SHIFT                       7

/* BRPHY0_DSP_TAP :: TAP26 :: ENERGY_DETECT_OV [06:03] */
#define Wr_BRPHY0_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP26,0x78,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP26,0x78,3)
#define BRPHY0_DSP_TAP_TAP26_ENERGY_DETECT_OV_MASK                 0x0078
#define BRPHY0_DSP_TAP_TAP26_ENERGY_DETECT_OV_ALIGN                0
#define BRPHY0_DSP_TAP_TAP26_ENERGY_DETECT_OV_BITS                 4
#define BRPHY0_DSP_TAP_TAP26_ENERGY_DETECT_OV_SHIFT                3

/* BRPHY0_DSP_TAP :: TAP26 :: PCS_INPUT_OV [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP26_PCS_INPUT_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP26,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP26_PCS_INPUT_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP26,0x4,2)
#define BRPHY0_DSP_TAP_TAP26_PCS_INPUT_OV_MASK                     0x0004
#define BRPHY0_DSP_TAP_TAP26_PCS_INPUT_OV_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP26_PCS_INPUT_OV_BITS                     1
#define BRPHY0_DSP_TAP_TAP26_PCS_INPUT_OV_SHIFT                    2

/* BRPHY0_DSP_TAP :: TAP26 :: REM_RCVR_STATUS_OV [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP26,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP26,0x2,1)
#define BRPHY0_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_MASK               0x0002
#define BRPHY0_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_ALIGN              0
#define BRPHY0_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_BITS               1
#define BRPHY0_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_SHIFT              1

/* BRPHY0_DSP_TAP :: TAP26 :: ALIGN_OK_OV [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP26_ALIGN_OK_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP26,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP26_ALIGN_OK_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP26,0x1,0)
#define BRPHY0_DSP_TAP_TAP26_ALIGN_OK_OV_MASK                      0x0001
#define BRPHY0_DSP_TAP_TAP26_ALIGN_OK_OV_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP26_ALIGN_OK_OV_BITS                      1
#define BRPHY0_DSP_TAP_TAP26_ALIGN_OK_OV_SHIFT                     0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP27
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP27 :: reserved0 [15:09] */
#define BRPHY0_DSP_TAP_TAP27_RESERVED0_MASK                        0xfe00
#define BRPHY0_DSP_TAP_TAP27_RESERVED0_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP27_RESERVED0_BITS                        7
#define BRPHY0_DSP_TAP_TAP27_RESERVED0_SHIFT                       9

/* BRPHY0_DSP_TAP :: TAP27 :: FILTER_CTL_PAUSE_OV [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP27,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP27,0x100,8)
#define BRPHY0_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_MASK              0x0100
#define BRPHY0_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_ALIGN             0
#define BRPHY0_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_BITS              1
#define BRPHY0_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_SHIFT             8

/* BRPHY0_DSP_TAP :: TAP27 :: PAUSEPCTPM_ABCD_OV [07:04] */
#define Wr_BRPHY0_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP27,0xf0,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP27,0xf0,4)
#define BRPHY0_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_MASK               0x00f0
#define BRPHY0_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_ALIGN              0
#define BRPHY0_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_BITS               4
#define BRPHY0_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_SHIFT              4

/* BRPHY0_DSP_TAP :: TAP27 :: AUTONEG_INPUT_OV [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP27,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP27,0x8,3)
#define BRPHY0_DSP_TAP_TAP27_AUTONEG_INPUT_OV_MASK                 0x0008
#define BRPHY0_DSP_TAP_TAP27_AUTONEG_INPUT_OV_ALIGN                0
#define BRPHY0_DSP_TAP_TAP27_AUTONEG_INPUT_OV_BITS                 1
#define BRPHY0_DSP_TAP_TAP27_AUTONEG_INPUT_OV_SHIFT                3

/* BRPHY0_DSP_TAP :: TAP27 :: LINK_SCAN_100TX_OV [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP27,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP27,0x4,2)
#define BRPHY0_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_MASK               0x0004
#define BRPHY0_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_ALIGN              0
#define BRPHY0_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_BITS               1
#define BRPHY0_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_SHIFT              2

/* BRPHY0_DSP_TAP :: TAP27 :: LINK_ENAB_100TX_OV [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP27,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP27,0x2,1)
#define BRPHY0_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_MASK               0x0002
#define BRPHY0_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_ALIGN              0
#define BRPHY0_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_BITS               1
#define BRPHY0_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_SHIFT              1

/* BRPHY0_DSP_TAP :: TAP27 :: LINK_CTL_1000T_OV [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP27,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP27,0x1,0)
#define BRPHY0_DSP_TAP_TAP27_LINK_CTL_1000T_OV_MASK                0x0001
#define BRPHY0_DSP_TAP_TAP27_LINK_CTL_1000T_OV_ALIGN               0
#define BRPHY0_DSP_TAP_TAP27_LINK_CTL_1000T_OV_BITS                1
#define BRPHY0_DSP_TAP_TAP27_LINK_CTL_1000T_OV_SHIFT               0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP28
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP28 :: reserved0 [15:04] */
#define BRPHY0_DSP_TAP_TAP28_RESERVED0_MASK                        0xfff0
#define BRPHY0_DSP_TAP_TAP28_RESERVED0_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP28_RESERVED0_BITS                        12
#define BRPHY0_DSP_TAP_TAP28_RESERVED0_SHIFT                       4

/* BRPHY0_DSP_TAP :: TAP28 :: PLLPRAMP_ABCD_OV [03:00] */
#define Wr_BRPHY0_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP28,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP28,0xf,0)
#define BRPHY0_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_MASK                 0x000f
#define BRPHY0_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_ALIGN                0
#define BRPHY0_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_BITS                 4
#define BRPHY0_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP29
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP29 :: TIMER_MODE_D_FORCE [15:14] */
#define Wr_BRPHY0_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP29,0xc000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP29,0xc000,14)
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_MASK               0xc000
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_BITS               2
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_SHIFT              14

/* BRPHY0_DSP_TAP :: TAP29 :: TIMER_MODE_C_FORCE [13:12] */
#define Wr_BRPHY0_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP29,0x3000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP29,0x3000,12)
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_MASK               0x3000
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_BITS               2
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_SHIFT              12

/* BRPHY0_DSP_TAP :: TAP29 :: TIMER_MODE_B_FORCE [11:10] */
#define Wr_BRPHY0_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP29,0xc00,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP29,0xc00,10)
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_MASK               0x0c00
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_BITS               2
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_SHIFT              10

/* BRPHY0_DSP_TAP :: TAP29 :: TIMER_MODE_A_FORCE [09:08] */
#define Wr_BRPHY0_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP29,0x300,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP29,0x300,8)
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_MASK               0x0300
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_BITS               2
#define BRPHY0_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_SHIFT              8

/* BRPHY0_DSP_TAP :: TAP29 :: MAINSTATE_FORCE [07:04] */
#define Wr_BRPHY0_DSP_TAP_TAP29_MAINSTATE_FORCE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP29,0xf0,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP29_MAINSTATE_FORCE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP29,0xf0,4)
#define BRPHY0_DSP_TAP_TAP29_MAINSTATE_FORCE_MASK                  0x00f0
#define BRPHY0_DSP_TAP_TAP29_MAINSTATE_FORCE_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP29_MAINSTATE_FORCE_BITS                  4
#define BRPHY0_DSP_TAP_TAP29_MAINSTATE_FORCE_SHIFT                 4

/* BRPHY0_DSP_TAP :: TAP29 :: FORCE_PHYC_STATE [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP29,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP29,0x8,3)
#define BRPHY0_DSP_TAP_TAP29_FORCE_PHYC_STATE_MASK                 0x0008
#define BRPHY0_DSP_TAP_TAP29_FORCE_PHYC_STATE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP29_FORCE_PHYC_STATE_BITS                 1
#define BRPHY0_DSP_TAP_TAP29_FORCE_PHYC_STATE_SHIFT                3

/* BRPHY0_DSP_TAP :: TAP29 :: HOLD_IN_ALT [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP29_HOLD_IN_ALT(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP29,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP29_HOLD_IN_ALT(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP29,0x4,2)
#define BRPHY0_DSP_TAP_TAP29_HOLD_IN_ALT_MASK                      0x0004
#define BRPHY0_DSP_TAP_TAP29_HOLD_IN_ALT_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP29_HOLD_IN_ALT_BITS                      1
#define BRPHY0_DSP_TAP_TAP29_HOLD_IN_ALT_SHIFT                     2

/* BRPHY0_DSP_TAP :: TAP29 :: FORCE_ALT_STATE_PATH [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP29,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP29,0x2,1)
#define BRPHY0_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_MASK             0x0002
#define BRPHY0_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_ALIGN            0
#define BRPHY0_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_BITS             1
#define BRPHY0_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_SHIFT            1

/* BRPHY0_DSP_TAP :: TAP29 :: PHYC_FAST_STATE_MODE [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP29,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP29,0x1,0)
#define BRPHY0_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_MASK             0x0001
#define BRPHY0_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_ALIGN            0
#define BRPHY0_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_BITS             1
#define BRPHY0_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_SHIFT            0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP30
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP30 :: reserved0 [15:12] */
#define BRPHY0_DSP_TAP_TAP30_RESERVED0_MASK                        0xf000
#define BRPHY0_DSP_TAP_TAP30_RESERVED0_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP30_RESERVED0_BITS                        4
#define BRPHY0_DSP_TAP_TAP30_RESERVED0_SHIFT                       12

/* BRPHY0_DSP_TAP :: TAP30 :: SUBSTATE_D_FORCE [11:09] */
#define Wr_BRPHY0_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP30,0xe00,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP30,0xe00,9)
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_D_FORCE_MASK                 0x0e00
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_D_FORCE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_D_FORCE_BITS                 3
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_D_FORCE_SHIFT                9

/* BRPHY0_DSP_TAP :: TAP30 :: SUBSTATE_C_FORCE [08:06] */
#define Wr_BRPHY0_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP30,0x1c0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP30,0x1c0,6)
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_C_FORCE_MASK                 0x01c0
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_C_FORCE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_C_FORCE_BITS                 3
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_C_FORCE_SHIFT                6

/* BRPHY0_DSP_TAP :: TAP30 :: SUBSTATE_B_FORCE [05:03] */
#define Wr_BRPHY0_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP30,0x38,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP30,0x38,3)
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_B_FORCE_MASK                 0x0038
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_B_FORCE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_B_FORCE_BITS                 3
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_B_FORCE_SHIFT                3

/* BRPHY0_DSP_TAP :: TAP30 :: SUBSTATE_A_FORCE [02:00] */
#define Wr_BRPHY0_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP30,0x7,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP30,0x7,0)
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_A_FORCE_MASK                 0x0007
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_A_FORCE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_A_FORCE_BITS                 3
#define BRPHY0_DSP_TAP_TAP30_SUBSTATE_A_FORCE_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP31_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP31_C0 :: SDSEL_OV [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x8000,15)
#define BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_MASK                      0x8000
#define BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_ALIGN                     0
#define BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_BITS                      1
#define BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_SHIFT                     15

/* BRPHY0_DSP_TAP :: TAP31_C0 :: SDSEL_OV_EN [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x4000,14)
#define BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_EN_MASK                   0x4000
#define BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_EN_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_EN_BITS                   1
#define BRPHY0_DSP_TAP_TAP31_C0_SDSEL_OV_EN_SHIFT                  14

/* BRPHY0_DSP_TAP :: TAP31_C0 :: ADC_BER_TPOUT_EN [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x2000,13)
#define BRPHY0_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_MASK              0x2000
#define BRPHY0_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_ALIGN             0
#define BRPHY0_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_BITS              1
#define BRPHY0_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_SHIFT             13

/* BRPHY0_DSP_TAP :: TAP31_C0 :: SWAPCD_OV [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP31_C0_SWAPCD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP31_C0_SWAPCD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x1000,12)
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPCD_OV_MASK                     0x1000
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPCD_OV_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPCD_OV_BITS                     1
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPCD_OV_SHIFT                    12

/* BRPHY0_DSP_TAP :: TAP31_C0 :: SWAPAB_OV [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x800,11)
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_OV_MASK                     0x0800
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_OV_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_OV_BITS                     1
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_OV_SHIFT                    11

/* BRPHY0_DSP_TAP :: TAP31_C0 :: SWAPAB_CD_OV_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP31_C0,0x400,10)
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_MASK               0x0400
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_ALIGN              0
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_BITS               1
#define BRPHY0_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_SHIFT              10

/* BRPHY0_DSP_TAP :: TAP31_C0 :: reserved0 [09:00] */
#define BRPHY0_DSP_TAP_TAP31_C0_RESERVED0_MASK                     0x03ff
#define BRPHY0_DSP_TAP_TAP31_C0_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP31_C0_RESERVED0_BITS                     10
#define BRPHY0_DSP_TAP_TAP31_C0_RESERVED0_SHIFT                    0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP32_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP32_C0 :: reserved0 [15:09] */
#define BRPHY0_DSP_TAP_TAP32_C0_RESERVED0_MASK                     0xfe00
#define BRPHY0_DSP_TAP_TAP32_C0_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP32_C0_RESERVED0_BITS                     7
#define BRPHY0_DSP_TAP_TAP32_C0_RESERVED0_SHIFT                    9

/* BRPHY0_DSP_TAP :: TAP32_C0 :: COEFF_RAM_TM_CTRL [08:04] */
#define Wr_BRPHY0_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x1f0,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x1f0,4)
#define BRPHY0_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_MASK             0x01f0
#define BRPHY0_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_ALIGN            0
#define BRPHY0_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_BITS             5
#define BRPHY0_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_SHIFT            4

/* BRPHY0_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_D [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x8,3)
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_MASK         0x0008
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_ALIGN        0
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_BITS         1
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_SHIFT        3

/* BRPHY0_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_C [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x4,2)
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_MASK         0x0004
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_ALIGN        0
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_BITS         1
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_SHIFT        2

/* BRPHY0_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_AB [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x2,1)
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_MASK        0x0002
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_ALIGN       0
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_BITS        1
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_SHIFT       1

/* BRPHY0_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_A [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP32_C0,0x1,0)
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_MASK         0x0001
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_ALIGN        0
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_BITS         1
#define BRPHY0_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_SHIFT        0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FDFE_OV_RD
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_MSB [15:14] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0xc000,14,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0xc000,14)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_MASK             0xc000
#define BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_ALIGN            0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_BITS             2
#define BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_SHIFT            14

/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_LSB [13:13] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x2000,13)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_MASK             0x2000
#define BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_ALIGN            0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_BITS             1
#define BRPHY0_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_SHIFT            13

/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: BETA_OV [12:12] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x1000,12)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_MASK                     0x1000
#define BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_ALIGN                    0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_BITS                     1
#define BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_SHIFT                    12

/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: BETA_OV_VAL [11:09] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0xe00,9,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0xe00,9)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_MASK                 0x0e00
#define BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_ALIGN                0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_BITS                 3
#define BRPHY0_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_SHIFT                9

/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: FDFE_MSE_SEL_OV [08:08] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x100,8)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_MASK             0x0100
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_ALIGN            0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_BITS             1
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_SHIFT            8

/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: FDFE_CLEAR_OV [07:07] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x80,7)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_MASK               0x0080
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_ALIGN              0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_BITS               1
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_SHIFT              7

/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: FDFE_OUTEN_OV [06:06] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x40,6)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_MASK               0x0040
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_ALIGN              0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_BITS               1
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_SHIFT              6

/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: FDFE_UPEN_OV [05:05] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x20,5)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_MASK                0x0020
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_ALIGN               0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_BITS                1
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_SHIFT               5

/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: FDFE_OV_EN [04:04] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0x10,4)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_MASK                  0x0010
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_ALIGN                 0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_BITS                  1
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_SHIFT                 4

/* BRPHY0_DSP_TAP :: FDFE_OV_RD :: FDFE_RD_SEL [03:00] */
#define Wr_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_OV_RD,0xf,0)
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_MASK                 0x000f
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_ALIGN                0
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_BITS                 4
#define BRPHY0_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FDFE_COEFF
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FDFE_COEFF :: FDFE_COEFF [15:00] */
#define Wr_BRPHY0_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) WriteReg16(BRPHY0_DSP_TAP_FDFE_COEFF,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) ReadReg16(BRPHY0_DSP_TAP_FDFE_COEFF)
#define BRPHY0_DSP_TAP_FDFE_COEFF_FDFE_COEFF_MASK                  0xffff
#define BRPHY0_DSP_TAP_FDFE_COEFF_FDFE_COEFF_ALIGN                 0
#define BRPHY0_DSP_TAP_FDFE_COEFF_FDFE_COEFF_BITS                  16
#define BRPHY0_DSP_TAP_FDFE_COEFF_FDFE_COEFF_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FDFE_BETA_THRESHOLD
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_3 [15:12] */
#define Wr_BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12)
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_MASK   0xf000
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_ALIGN  0
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_BITS   4
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_SHIFT  12

/* BRPHY0_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_2 [11:08] */
#define Wr_BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8)
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_MASK   0x0f00
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_ALIGN  0
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_BITS   4
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_SHIFT  8

/* BRPHY0_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_1 [07:04] */
#define Wr_BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4)
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_MASK   0x00f0
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_ALIGN  0
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_BITS   4
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_SHIFT  4

/* BRPHY0_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_0 [03:00] */
#define Wr_BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) WriteRegBits16(BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) ReadRegBits16(BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0)
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_MASK   0x000f
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_ALIGN  0
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_BITS   4
#define BRPHY0_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_SHIFT  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP33_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SD_EN [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x8000,15)
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_MASK               0x8000
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_ALIGN              0
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_BITS               1
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_SHIFT              15

/* BRPHY0_DSP_TAP :: TAP33_C0 :: EEE_MASK_MSE_EN [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x4000,14)
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_MASK               0x4000
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_ALIGN              0
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_BITS               1
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_SHIFT              14

/* BRPHY0_DSP_TAP :: TAP33_C0 :: EEE_PHYC_STATUS_TO_LED [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x2000,13)
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_MASK        0x2000
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_ALIGN       0
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_BITS        1
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_SHIFT       13

/* BRPHY0_DSP_TAP :: TAP33_C0 :: EEE_PLL_TEST_MODE [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x1000,12)
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_MASK             0x1000
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_ALIGN            0
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_BITS             1
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_SHIFT            12

/* BRPHY0_DSP_TAP :: TAP33_C0 :: SPARE11 [11:11] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_SPARE11(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_SPARE11(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x800,11)
#define BRPHY0_DSP_TAP_TAP33_C0_SPARE11_MASK                       0x0800
#define BRPHY0_DSP_TAP_TAP33_C0_SPARE11_ALIGN                      0
#define BRPHY0_DSP_TAP_TAP33_C0_SPARE11_BITS                       1
#define BRPHY0_DSP_TAP_TAP33_C0_SPARE11_SHIFT                      11

/* BRPHY0_DSP_TAP :: TAP33_C0 :: EEE_AFE_STOPPABLE [10:10] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x400,10)
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_MASK             0x0400
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_ALIGN            0
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_BITS             1
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_SHIFT            10

/* BRPHY0_DSP_TAP :: TAP33_C0 :: EEE_CLOCK_STOPPABLE [09:09] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x200,9)
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_MASK           0x0200
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_ALIGN          0
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_BITS           1
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_SHIFT          9

/* BRPHY0_DSP_TAP :: TAP33_C0 :: EEE_SD_SEL [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x100,8)
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_SD_SEL_MASK                    0x0100
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_SD_SEL_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_SD_SEL_BITS                    1
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_SD_SEL_SHIFT                   8

/* BRPHY0_DSP_TAP :: TAP33_C0 :: MAXMSEOK1_CHG_EN [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x80,7)
#define BRPHY0_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_MASK              0x0080
#define BRPHY0_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_ALIGN             0
#define BRPHY0_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_BITS              1
#define BRPHY0_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_SHIFT             7

/* BRPHY0_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SCALE [06:05] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x60,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x60,5)
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_MASK               0x0060
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_BITS               2
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_SHIFT              5

/* BRPHY0_DSP_TAP :: TAP33_C0 :: LPI_TRACK_MODE [04:03] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x18,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x18,3)
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_MASK                0x0018
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_ALIGN               0
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_BITS                2
#define BRPHY0_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_SHIFT               3

/* BRPHY0_DSP_TAP :: TAP33_C0 :: EEE_FREQ_UNLOCK [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x4,2)
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_MASK               0x0004
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_ALIGN              0
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_BITS               1
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_SHIFT              2

/* BRPHY0_DSP_TAP :: TAP33_C0 :: EEE_QUICK_ALIGN [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x2,1)
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_MASK               0x0002
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_ALIGN              0
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_BITS               1
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_SHIFT              1

/* BRPHY0_DSP_TAP :: TAP33_C0 :: EEE_SD300 [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C0_EEE_SD300(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C0_EEE_SD300(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C0,0x1,0)
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_SD300_MASK                     0x0001
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_SD300_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_SD300_BITS                     1
#define BRPHY0_DSP_TAP_TAP33_C0_EEE_SD300_SHIFT                    0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP33_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP33_C1 :: SD_ASSERT_THD [15:08] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C1,0xff00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C1,0xff00,8)
#define BRPHY0_DSP_TAP_TAP33_C1_SD_ASSERT_THD_MASK                 0xff00
#define BRPHY0_DSP_TAP_TAP33_C1_SD_ASSERT_THD_ALIGN                0
#define BRPHY0_DSP_TAP_TAP33_C1_SD_ASSERT_THD_BITS                 8
#define BRPHY0_DSP_TAP_TAP33_C1_SD_ASSERT_THD_SHIFT                8

/* BRPHY0_DSP_TAP :: TAP33_C1 :: SD_DEASSERT_THD [07:00] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C1,0xff,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C1,0xff,0)
#define BRPHY0_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_MASK               0x00ff
#define BRPHY0_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_ALIGN              0
#define BRPHY0_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_BITS               8
#define BRPHY0_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_SHIFT              0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP33_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP33_C2 :: EEE_PHASE_REACQ_TUNE [15:14] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0xc000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0xc000,14)
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_MASK          0xc000
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_ALIGN         0
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_BITS          2
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_SHIFT         14

/* BRPHY0_DSP_TAP :: TAP33_C2 :: EEE_WAIT_SCR_LOCK_N [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0x2000,13)
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_MASK           0x2000
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_ALIGN          0
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_BITS           1
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_SHIFT          13

/* BRPHY0_DSP_TAP :: TAP33_C2 :: LOC_RCVR_WAIT_ALIGNC_N [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0x1000,12)
#define BRPHY0_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_MASK        0x1000
#define BRPHY0_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_ALIGN       0
#define BRPHY0_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_BITS        1
#define BRPHY0_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_SHIFT       12

/* BRPHY0_DSP_TAP :: TAP33_C2 :: EEE_WAKEMZ_TUNE [11:08] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0xf00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0xf00,8)
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_MASK               0x0f00
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_BITS               4
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_SHIFT              8

/* BRPHY0_DSP_TAP :: TAP33_C2 :: EEE_RX_ON_TUNE [07:04] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0xf0,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0xf0,4)
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_MASK                0x00f0
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_ALIGN               0
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_BITS                4
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_SHIFT               4

/* BRPHY0_DSP_TAP :: TAP33_C2 :: EEE_SLAVE_WAIT_TUNE [03:00] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C2,0xf,0)
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_MASK           0x000f
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_ALIGN          0
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_BITS           4
#define BRPHY0_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_SHIFT          0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP33_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP33_C3 :: spare_reg [15:02] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C3_spare_reg(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C3,0xfffc,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C3_spare_reg(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C3,0xfffc,2)
#define BRPHY0_DSP_TAP_TAP33_C3_SPARE_REG_MASK                     0xfffc
#define BRPHY0_DSP_TAP_TAP33_C3_SPARE_REG_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP33_C3_SPARE_REG_BITS                     14
#define BRPHY0_DSP_TAP_TAP33_C3_SPARE_REG_SHIFT                    2

/* BRPHY0_DSP_TAP :: TAP33_C3 :: PWRDNTX_STAGGER_EN [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C3,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C3,0x2,1)
#define BRPHY0_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_MASK            0x0002
#define BRPHY0_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_ALIGN           0
#define BRPHY0_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_BITS            1
#define BRPHY0_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_SHIFT           1

/* BRPHY0_DSP_TAP :: TAP33_C3 :: PWRDNRX_STAGGER_EN [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP33_C3,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP33_C3,0x1,0)
#define BRPHY0_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_MASK            0x0001
#define BRPHY0_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_ALIGN           0
#define BRPHY0_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_BITS            1
#define BRPHY0_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_SHIFT           0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP34_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP34_C0 :: EEE_PLLILPFRZ [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x8000,15)
#define BRPHY0_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_MASK                 0x8000
#define BRPHY0_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_ALIGN                0
#define BRPHY0_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_BITS                 1
#define BRPHY0_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_SHIFT                15

/* BRPHY0_DSP_TAP :: TAP34_C0 :: PLLILPFRZ_OV [14:14] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x4000,14)
#define BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_MASK                  0x4000
#define BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_BITS                  1
#define BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_SHIFT                 14

/* BRPHY0_DSP_TAP :: TAP34_C0 :: PLLILPFRZ [13:13] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x2000,13)
#define BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_MASK                     0x2000
#define BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_BITS                     1
#define BRPHY0_DSP_TAP_TAP34_C0_PLLILPFRZ_SHIFT                    13

/* BRPHY0_DSP_TAP :: TAP34_C0 :: EEE_100TX_UP16_SEL [12:12] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x1000,12)
#define BRPHY0_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_MASK            0x1000
#define BRPHY0_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_ALIGN           0
#define BRPHY0_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_BITS            1
#define BRPHY0_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_SHIFT           12

/* BRPHY0_DSP_TAP :: TAP34_C0 :: PLLFRST_SCALE [11:10] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0xc00,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0xc00,10)
#define BRPHY0_DSP_TAP_TAP34_C0_PLLFRST_SCALE_MASK                 0x0c00
#define BRPHY0_DSP_TAP_TAP34_C0_PLLFRST_SCALE_ALIGN                0
#define BRPHY0_DSP_TAP_TAP34_C0_PLLFRST_SCALE_BITS                 2
#define BRPHY0_DSP_TAP_TAP34_C0_PLLFRST_SCALE_SHIFT                10

/* BRPHY0_DSP_TAP :: TAP34_C0 :: INT_LP_GAIN [09:08] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x300,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x300,8)
#define BRPHY0_DSP_TAP_TAP34_C0_INT_LP_GAIN_MASK                   0x0300
#define BRPHY0_DSP_TAP_TAP34_C0_INT_LP_GAIN_ALIGN                  0
#define BRPHY0_DSP_TAP_TAP34_C0_INT_LP_GAIN_BITS                   2
#define BRPHY0_DSP_TAP_TAP34_C0_INT_LP_GAIN_SHIFT                  8

/* BRPHY0_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_EST_AVERAGE_SEL [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x80,7)
#define BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_MASK    0x0080
#define BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_ALIGN   0
#define BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_BITS    1
#define BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_SHIFT   7

/* BRPHY0_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_SCALE [06:04] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x70,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x70,4)
#define BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_MASK              0x0070
#define BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_ALIGN             0
#define BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_BITS              3
#define BRPHY0_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_SHIFT             4

/* BRPHY0_DSP_TAP :: TAP34_C0 :: KI [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_KI(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_KI(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x8,3)
#define BRPHY0_DSP_TAP_TAP34_C0_KI_MASK                            0x0008
#define BRPHY0_DSP_TAP_TAP34_C0_KI_ALIGN                           0
#define BRPHY0_DSP_TAP_TAP34_C0_KI_BITS                            1
#define BRPHY0_DSP_TAP_TAP34_C0_KI_SHIFT                           3

/* BRPHY0_DSP_TAP :: TAP34_C0 :: KP [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_KP(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_KP(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x4,2)
#define BRPHY0_DSP_TAP_TAP34_C0_KP_MASK                            0x0004
#define BRPHY0_DSP_TAP_TAP34_C0_KP_ALIGN                           0
#define BRPHY0_DSP_TAP_TAP34_C0_KP_BITS                            1
#define BRPHY0_DSP_TAP_TAP34_C0_KP_SHIFT                           2

/* BRPHY0_DSP_TAP :: TAP34_C0 :: KV [01:00] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C0_KV(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x3,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C0_KV(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C0,0x3,0)
#define BRPHY0_DSP_TAP_TAP34_C0_KV_MASK                            0x0003
#define BRPHY0_DSP_TAP_TAP34_C0_KV_ALIGN                           0
#define BRPHY0_DSP_TAP_TAP34_C0_KV_BITS                            2
#define BRPHY0_DSP_TAP_TAP34_C0_KV_SHIFT                           0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP34_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP34_C1 :: SPARE [15:12] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C1_SPARE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C1,0xf000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C1_SPARE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C1,0xf000,12)
#define BRPHY0_DSP_TAP_TAP34_C1_SPARE_MASK                         0xf000
#define BRPHY0_DSP_TAP_TAP34_C1_SPARE_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP34_C1_SPARE_BITS                         4
#define BRPHY0_DSP_TAP_TAP34_C1_SPARE_SHIFT                        12

/* BRPHY0_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_10 [11:08] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C1,0xf00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C1,0xf00,8)
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_MASK             0x0f00
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_ALIGN            0
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_BITS             4
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_SHIFT            8

/* BRPHY0_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_01 [07:04] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C1,0xf0,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C1,0xf0,4)
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_MASK             0x00f0
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_ALIGN            0
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_BITS             4
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_SHIFT            4

/* BRPHY0_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_00 [03:00] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C1,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C1,0xf,0)
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_MASK             0x000f
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_ALIGN            0
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_BITS             4
#define BRPHY0_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_SHIFT            0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP34_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_CH_SEL [15:14] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0xc000,14,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0xc000,14)
#define BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_MASK           0xc000
#define BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_ALIGN          0
#define BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_BITS           2
#define BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_SHIFT          14

/* BRPHY0_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_BUS_SEL [13:11] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0x3800,11,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0x3800,11)
#define BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_MASK          0x3800
#define BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_ALIGN         0
#define BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_BITS          3
#define BRPHY0_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_SHIFT         11

/* BRPHY0_DSP_TAP :: TAP34_C2 :: reserved0 [10:09] */
#define BRPHY0_DSP_TAP_TAP34_C2_RESERVED0_MASK                     0x0600
#define BRPHY0_DSP_TAP_TAP34_C2_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP34_C2_RESERVED0_BITS                     2
#define BRPHY0_DSP_TAP_TAP34_C2_RESERVED0_SHIFT                    9

/* BRPHY0_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_10 [08:06] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0x1c0,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0x1c0,6)
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_MASK               0x01c0
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_ALIGN              0
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_BITS               3
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_SHIFT              6

/* BRPHY0_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_01 [05:03] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0x38,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0x38,3)
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_MASK               0x0038
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_ALIGN              0
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_BITS               3
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_SHIFT              3

/* BRPHY0_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_00 [02:00] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0x7,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP34_C2,0x7,0)
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_MASK               0x0007
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_ALIGN              0
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_BITS               3
#define BRPHY0_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_SHIFT              0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP34_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP34_C3 :: PHASECTL_TPO [15:00] */
#define Wr_BRPHY0_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) WriteReg16(BRPHY0_DSP_TAP_TAP34_C3,x)
#define Rd_BRPHY0_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) ReadReg16(BRPHY0_DSP_TAP_TAP34_C3)
#define BRPHY0_DSP_TAP_TAP34_C3_PHASECTL_TPO_MASK                  0xffff
#define BRPHY0_DSP_TAP_TAP34_C3_PHASECTL_TPO_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP34_C3_PHASECTL_TPO_BITS                  16
#define BRPHY0_DSP_TAP_TAP34_C3_PHASECTL_TPO_SHIFT                 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP35_C0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP35_C0 :: LPI_RX_TW3_TIMER [15:13] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0xe000,13,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0xe000,13)
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_MASK              0xe000
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_ALIGN             0
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_BITS              3
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_SHIFT             13

/* BRPHY0_DSP_TAP :: TAP35_C0 :: LPI_RX_TW2_TIMER [12:10] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0x1c00,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0x1c00,10)
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_MASK              0x1c00
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_ALIGN             0
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_BITS              3
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_SHIFT             10

/* BRPHY0_DSP_TAP :: TAP35_C0 :: LPI_RX_TW1_TIMER [09:07] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0x380,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0x380,7)
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_MASK              0x0380
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_ALIGN             0
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_BITS              3
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_SHIFT             7

/* BRPHY0_DSP_TAP :: TAP35_C0 :: LPI_TX_TQ_TIMER [06:04] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0x70,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0x70,4)
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_MASK               0x0070
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_ALIGN              0
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_BITS               3
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_SHIFT              4

/* BRPHY0_DSP_TAP :: TAP35_C0 :: LPI_TX_TS_TIMER [03:02] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0xc,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0xc,2)
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_MASK               0x000c
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_ALIGN              0
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_BITS               2
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_SHIFT              2

/* BRPHY0_DSP_TAP :: TAP35_C0 :: LPI_TX_TR_TIMER [01:00] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0x3,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C0,0x3,0)
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_MASK               0x0003
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_ALIGN              0
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_BITS               2
#define BRPHY0_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_SHIFT              0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP35_C1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP35_C1 :: LPI_RX_TS3_TIMER [15:10] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C1,0xfc00,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C1,0xfc00,10)
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_MASK              0xfc00
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_ALIGN             0
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_BITS              6
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_SHIFT             10

/* BRPHY0_DSP_TAP :: TAP35_C1 :: LPI_RX_TS2_TIMER [09:04] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C1,0x3f0,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C1,0x3f0,4)
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_MASK              0x03f0
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_ALIGN             0
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_BITS              6
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_SHIFT             4

/* BRPHY0_DSP_TAP :: TAP35_C1 :: LPI_RX_TS1_TIMER [03:00] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C1,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C1,0xf,0)
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_MASK              0x000f
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_ALIGN             0
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_BITS              4
#define BRPHY0_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_SHIFT             0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP35_C2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP35_C2 :: reserved0 [15:14] */
#define BRPHY0_DSP_TAP_TAP35_C2_RESERVED0_MASK                     0xc000
#define BRPHY0_DSP_TAP_TAP35_C2_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP35_C2_RESERVED0_BITS                     2
#define BRPHY0_DSP_TAP_TAP35_C2_RESERVED0_SHIFT                    14

/* BRPHY0_DSP_TAP :: TAP35_C2 :: SPARE [13:10] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C2_SPARE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x3c00,10,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C2_SPARE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x3c00,10)
#define BRPHY0_DSP_TAP_TAP35_C2_SPARE_MASK                         0x3c00
#define BRPHY0_DSP_TAP_TAP35_C2_SPARE_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP35_C2_SPARE_BITS                         4
#define BRPHY0_DSP_TAP_TAP35_C2_SPARE_SHIFT                        10

/* BRPHY0_DSP_TAP :: TAP35_C2 :: LPI_TX_BRCM_MODE [09:09] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x200,9)
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_MASK              0x0200
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_ALIGN             0
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_BITS              1
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_SHIFT             9

/* BRPHY0_DSP_TAP :: TAP35_C2 :: LPI_RX_TI_TIMER [08:08] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x100,8)
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_MASK               0x0100
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_ALIGN              0
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_BITS               1
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_SHIFT              8

/* BRPHY0_DSP_TAP :: TAP35_C2 :: GPCS_ERRTH_SEL [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x80,7)
#define BRPHY0_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_MASK                0x0080
#define BRPHY0_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_ALIGN               0
#define BRPHY0_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_BITS                1
#define BRPHY0_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_SHIFT               7

/* BRPHY0_DSP_TAP :: TAP35_C2 :: PCS_LPI_TEST_CTL [06:04] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x70,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x70,4)
#define BRPHY0_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_MASK              0x0070
#define BRPHY0_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_ALIGN             0
#define BRPHY0_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_BITS              3
#define BRPHY0_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_SHIFT             4

/* BRPHY0_DSP_TAP :: TAP35_C2 :: reserved1 [03:03] */
#define BRPHY0_DSP_TAP_TAP35_C2_RESERVED1_MASK                     0x0008
#define BRPHY0_DSP_TAP_TAP35_C2_RESERVED1_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP35_C2_RESERVED1_BITS                     1
#define BRPHY0_DSP_TAP_TAP35_C2_RESERVED1_SHIFT                    3

/* BRPHY0_DSP_TAP :: TAP35_C2 :: LPI_RX_SQCNTR [02:00] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x7,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C2,0x7,0)
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_MASK                 0x0007
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_ALIGN                0
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_BITS                 3
#define BRPHY0_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: TAP35_C3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: TAP35_C3 :: UNASSIGNED [15:15] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_UNASSIGNED(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_UNASSIGNED(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x8000,15)
#define BRPHY0_DSP_TAP_TAP35_C3_UNASSIGNED_MASK                    0x8000
#define BRPHY0_DSP_TAP_TAP35_C3_UNASSIGNED_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP35_C3_UNASSIGNED_BITS                    1
#define BRPHY0_DSP_TAP_TAP35_C3_UNASSIGNED_SHIFT                   15

/* BRPHY0_DSP_TAP :: TAP35_C3 :: LPI_100TX_STATE [14:12] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x7000,12,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x7000,12)
#define BRPHY0_DSP_TAP_TAP35_C3_LPI_100TX_STATE_MASK               0x7000
#define BRPHY0_DSP_TAP_TAP35_C3_LPI_100TX_STATE_ALIGN              0
#define BRPHY0_DSP_TAP_TAP35_C3_LPI_100TX_STATE_BITS               3
#define BRPHY0_DSP_TAP_TAP35_C3_LPI_100TX_STATE_SHIFT              12

/* BRPHY0_DSP_TAP :: TAP35_C3 :: RXSM_STATE [11:08] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_RXSM_STATE(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0xf00,8,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_RXSM_STATE(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0xf00,8)
#define BRPHY0_DSP_TAP_TAP35_C3_RXSM_STATE_MASK                    0x0f00
#define BRPHY0_DSP_TAP_TAP35_C3_RXSM_STATE_ALIGN                   0
#define BRPHY0_DSP_TAP_TAP35_C3_RXSM_STATE_BITS                    4
#define BRPHY0_DSP_TAP_TAP35_C3_RXSM_STATE_SHIFT                   8

/* BRPHY0_DSP_TAP :: TAP35_C3 :: SEED_INV_CTL [07:07] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x80,7)
#define BRPHY0_DSP_TAP_TAP35_C3_SEED_INV_CTL_MASK                  0x0080
#define BRPHY0_DSP_TAP_TAP35_C3_SEED_INV_CTL_ALIGN                 0
#define BRPHY0_DSP_TAP_TAP35_C3_SEED_INV_CTL_BITS                  1
#define BRPHY0_DSP_TAP_TAP35_C3_SEED_INV_CTL_SHIFT                 7

/* BRPHY0_DSP_TAP :: TAP35_C3 :: LOAD_N [06:06] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_LOAD_N(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_LOAD_N(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x40,6)
#define BRPHY0_DSP_TAP_TAP35_C3_LOAD_N_MASK                        0x0040
#define BRPHY0_DSP_TAP_TAP35_C3_LOAD_N_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP35_C3_LOAD_N_BITS                        1
#define BRPHY0_DSP_TAP_TAP35_C3_LOAD_N_SHIFT                       6

/* BRPHY0_DSP_TAP :: TAP35_C3 :: DET_IDLES [05:05] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_DET_IDLES(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_DET_IDLES(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x20,5)
#define BRPHY0_DSP_TAP_TAP35_C3_DET_IDLES_MASK                     0x0020
#define BRPHY0_DSP_TAP_TAP35_C3_DET_IDLES_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP35_C3_DET_IDLES_BITS                     1
#define BRPHY0_DSP_TAP_TAP35_C3_DET_IDLES_SHIFT                    5

/* BRPHY0_DSP_TAP :: TAP35_C3 :: DET_SLEEP [04:04] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_DET_SLEEP(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_DET_SLEEP(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x10,4)
#define BRPHY0_DSP_TAP_TAP35_C3_DET_SLEEP_MASK                     0x0010
#define BRPHY0_DSP_TAP_TAP35_C3_DET_SLEEP_ALIGN                    0
#define BRPHY0_DSP_TAP_TAP35_C3_DET_SLEEP_BITS                     1
#define BRPHY0_DSP_TAP_TAP35_C3_DET_SLEEP_SHIFT                    4

/* BRPHY0_DSP_TAP :: TAP35_C3 :: FUBAR [03:03] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_FUBAR(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_FUBAR(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x8,3)
#define BRPHY0_DSP_TAP_TAP35_C3_FUBAR_MASK                         0x0008
#define BRPHY0_DSP_TAP_TAP35_C3_FUBAR_ALIGN                        0
#define BRPHY0_DSP_TAP_TAP35_C3_FUBAR_BITS                         1
#define BRPHY0_DSP_TAP_TAP35_C3_FUBAR_SHIFT                        3

/* BRPHY0_DSP_TAP :: TAP35_C3 :: SR_NRZI [02:02] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_SR_NRZI(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_SR_NRZI(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x4,2)
#define BRPHY0_DSP_TAP_TAP35_C3_SR_NRZI_MASK                       0x0004
#define BRPHY0_DSP_TAP_TAP35_C3_SR_NRZI_ALIGN                      0
#define BRPHY0_DSP_TAP_TAP35_C3_SR_NRZI_BITS                       1
#define BRPHY0_DSP_TAP_TAP35_C3_SR_NRZI_SHIFT                      2

/* BRPHY0_DSP_TAP :: TAP35_C3 :: R_USCR [01:01] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_R_USCR(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_R_USCR(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x2,1)
#define BRPHY0_DSP_TAP_TAP35_C3_R_USCR_MASK                        0x0002
#define BRPHY0_DSP_TAP_TAP35_C3_R_USCR_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP35_C3_R_USCR_BITS                        1
#define BRPHY0_DSP_TAP_TAP35_C3_R_USCR_SHIFT                       1

/* BRPHY0_DSP_TAP :: TAP35_C3 :: LOCKED [00:00] */
#define Wr_BRPHY0_DSP_TAP_TAP35_C3_LOCKED(x) WriteRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_TAP35_C3_LOCKED(x) ReadRegBits16(BRPHY0_DSP_TAP_TAP35_C3,0x1,0)
#define BRPHY0_DSP_TAP_TAP35_C3_LOCKED_MASK                        0x0001
#define BRPHY0_DSP_TAP_TAP35_C3_LOCKED_ALIGN                       0
#define BRPHY0_DSP_TAP_TAP35_C3_LOCKED_BITS                        1
#define BRPHY0_DSP_TAP_TAP35_C3_LOCKED_SHIFT                       0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_CTL_CH0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x8000,15)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_MASK              0x8000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_SHIFT             15

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: DC_FREEZE [14:14] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x4000,14)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_MASK               0x4000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_ALIGN              0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_BITS               1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_SHIFT              14

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x2000,13)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_MASK             0x2000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_SHIFT            13

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x1000,12)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_MASK            0x1000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_SHIFT           12

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x800,11)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_MASK            0x0800
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_SHIFT           11

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x400,10)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_MASK            0x0400
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_SHIFT           10

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x200,9)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_MASK            0x0200
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_SHIFT           9

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x100,8)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_MASK              0x0100
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_SHIFT             8

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x80,7)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_MASK             0x0080
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_SHIFT            7

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: DC_DISABLE [06:06] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x40,6)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_MASK              0x0040
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_SHIFT             6

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x20,5)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_MASK            0x0020
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_SHIFT           5

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x10,4)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_MASK           0x0010
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_SHIFT          4

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x8,3)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_MASK           0x0008
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_SHIFT          3

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x4,2)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_MASK           0x0004
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_SHIFT          2

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x2,1)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_MASK           0x0002
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_SHIFT          1

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH0 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH0,0x1,0)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_MASK             0x0001
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_CTL_CH1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x8000,15)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_MASK              0x8000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_SHIFT             15

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: DC_FREEZE [14:14] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x4000,14)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_MASK               0x4000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_ALIGN              0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_BITS               1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_SHIFT              14

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x2000,13)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_MASK             0x2000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_SHIFT            13

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x1000,12)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_MASK            0x1000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_SHIFT           12

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x800,11)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_MASK            0x0800
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_SHIFT           11

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x400,10)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_MASK            0x0400
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_SHIFT           10

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x200,9)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_MASK            0x0200
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_SHIFT           9

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x100,8)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_MASK              0x0100
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_SHIFT             8

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x80,7)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_MASK             0x0080
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_SHIFT            7

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: DC_DISABLE [06:06] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x40,6)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_MASK              0x0040
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_SHIFT             6

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x20,5)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_MASK            0x0020
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_SHIFT           5

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x10,4)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_MASK           0x0010
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_SHIFT          4

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x8,3)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_MASK           0x0008
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_SHIFT          3

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x4,2)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_MASK           0x0004
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_SHIFT          2

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x2,1)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_MASK           0x0002
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_SHIFT          1

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH1 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH1,0x1,0)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_MASK             0x0001
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_CTL_CH2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x8000,15)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_MASK              0x8000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_SHIFT             15

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: DC_FREEZE [14:14] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x4000,14)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_MASK               0x4000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_ALIGN              0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_BITS               1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_SHIFT              14

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x2000,13)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_MASK             0x2000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_SHIFT            13

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x1000,12)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_MASK            0x1000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_SHIFT           12

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x800,11)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_MASK            0x0800
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_SHIFT           11

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x400,10)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_MASK            0x0400
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_SHIFT           10

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x200,9)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_MASK            0x0200
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_SHIFT           9

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x100,8)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_MASK              0x0100
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_SHIFT             8

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x80,7)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_MASK             0x0080
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_SHIFT            7

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: DC_DISABLE [06:06] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x40,6)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_MASK              0x0040
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_SHIFT             6

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x20,5)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_MASK            0x0020
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_SHIFT           5

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x10,4)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_MASK           0x0010
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_SHIFT          4

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x8,3)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_MASK           0x0008
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_SHIFT          3

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x4,2)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_MASK           0x0004
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_SHIFT          2

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x2,1)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_MASK           0x0002
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_SHIFT          1

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH2 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH2,0x1,0)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_MASK             0x0001
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_CTL_CH3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x8000,15)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_MASK              0x8000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_SHIFT             15

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: DC_FREEZE [14:14] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x4000,14)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_MASK               0x4000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_ALIGN              0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_BITS               1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_SHIFT              14

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x2000,13)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_MASK             0x2000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_SHIFT            13

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x1000,12)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_MASK            0x1000
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_SHIFT           12

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x800,11)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_MASK            0x0800
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_SHIFT           11

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x400,10)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_MASK            0x0400
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_SHIFT           10

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x200,9)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_MASK            0x0200
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_SHIFT           9

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x100,8)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_MASK              0x0100
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_SHIFT             8

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x80,7)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_MASK             0x0080
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_SHIFT            7

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: DC_DISABLE [06:06] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x40,6)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_MASK              0x0040
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_SHIFT             6

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x20,5)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_MASK            0x0020
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_SHIFT           5

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x10,4)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_MASK           0x0010
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_SHIFT          4

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x8,3)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_MASK           0x0008
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_SHIFT          3

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x4,2)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_MASK           0x0004
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_SHIFT          2

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x2,1)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_MASK           0x0002
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_ALIGN          0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_BITS           1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_SHIFT          1

/* BRPHY0_DSP_TAP :: FILTER_CTL_CH3 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_CH3,0x1,0)
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_MASK             0x0001
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_ALIGN            0
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_BITS             1
#define BRPHY0_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_MASK          0xff00
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_ALIGN         0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_BITS          8
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_SHIFT         8

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_MASK          0xff00
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_ALIGN         0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_BITS          8
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_SHIFT         8

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_MASK          0xff00
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_ALIGN         0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_BITS          8
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_SHIFT         8

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: reserved0 [15:08] */
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_MASK          0xff00
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_ALIGN         0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_BITS          8
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_SHIFT         8

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY0_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0)
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY0_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: reserved0 [15:15] */
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_MASK             0x8000
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_ALIGN            0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_BITS             1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_SHIFT            15

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT01_PRE1_DIS [14:14] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_MASK  0x4000
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_ALIGN 0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_BITS  1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_SHIFT 14

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: PHYC_SKIP_PHASE_ADJ [13:13] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_MASK   0x2000
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_ALIGN  0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_BITS   1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_SHIFT  13

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: LOCAL_TRAIN_DIS [12:12] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_MASK       0x1000
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_ALIGN      0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_BITS       1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_SHIFT      12

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: SLAVE_FDX_LOCAL_TRAIN_EN [11:11] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x800,11)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_MASK 0x0800
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_ALIGN 0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_BITS 1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_SHIFT 11

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: AUTO_LPF_EN [10:10] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x400,10)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_MASK           0x0400
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_ALIGN          0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_BITS           1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_SHIFT          10

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_PROTECT_EN [09:09] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x200,9)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_MASK        0x0200
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_ALIGN       0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_BITS        1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_SHIFT       9

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT1_DIS [08:08] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x100,8)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_MASK        0x0100
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_ALIGN       0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_BITS        1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_SHIFT       8

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_IDLEDATA_UPD_EN [07:04] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_MASK  0x00f0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_ALIGN 0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_BITS  4
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_SHIFT 4

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_EMI_UPD_EN [03:03] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x8,3)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_MASK       0x0008
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_ALIGN      0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_BITS       1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_SHIFT      3

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_VAL [02:02] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x4,2)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_MASK       0x0004
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_ALIGN      0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_BITS       1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_SHIFT      2

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_OV [01:01] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x2,1)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_MASK        0x0002
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_ALIGN       0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_BITS        1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_SHIFT       1

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_DATAPATH_EN [00:00] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL,0x1,0)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_MASK       0x0001
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_ALIGN      0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_BITS       1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_SHIFT      0


/****************************************************************************
 * BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL2
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL2 :: LPFREQ_SEL_STATUS [15:15] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_MASK    0x8000
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_ALIGN   0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_BITS    1
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_SHIFT   15

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL2 :: reserved0 [14:04] */
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_MASK            0x7ff0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_ALIGN           0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_BITS            11
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_SHIFT           4

/* BRPHY0_DSP_TAP :: EMI_DATAPATH_CTL2 :: GAMMA_LPF_THRESHOLD [03:00] */
#define Wr_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) WriteRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0,x)
#define Rd_BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) ReadRegBits16(BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0)
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_MASK  0x000f
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_ALIGN 0
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_BITS  4
#define BRPHY0_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_SHIFT 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FFEX_CTL
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FFEX_CTL :: reserved0 [15:12] */
#define BRPHY0_DSP_TAP_FFEX_CTL_RESERVED0_MASK                     0xf000
#define BRPHY0_DSP_TAP_FFEX_CTL_RESERVED0_ALIGN                    0
#define BRPHY0_DSP_TAP_FFEX_CTL_RESERVED0_BITS                     4
#define BRPHY0_DSP_TAP_FFEX_CTL_RESERVED0_SHIFT                    12

/* BRPHY0_DSP_TAP :: FFEX_CTL :: ENC_SLOW_LMS_CTL [11:10] */
#define Wr_BRPHY0_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) WriteRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0xc00,10,x)
#define Rd_BRPHY0_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) ReadRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0xc00,10)
#define BRPHY0_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_MASK              0x0c00
#define BRPHY0_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_ALIGN             0
#define BRPHY0_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_BITS              2
#define BRPHY0_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_SHIFT             10

/* BRPHY0_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV_VAL [09:09] */
#define Wr_BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x200,9)
#define BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_MASK               0x0200
#define BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_ALIGN              0
#define BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_BITS               1
#define BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_SHIFT              9

/* BRPHY0_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV [08:08] */
#define Wr_BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x100,8)
#define BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_MASK                   0x0100
#define BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_ALIGN                  0
#define BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_BITS                   1
#define BRPHY0_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_SHIFT                  8

/* BRPHY0_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_VAL [07:07] */
#define Wr_BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) WriteRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) ReadRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x80,7)
#define BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_MASK          0x0080
#define BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_ALIGN         0
#define BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_BITS          1
#define BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_SHIFT         7

/* BRPHY0_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_OV [06:06] */
#define Wr_BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) WriteRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) ReadRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x40,6)
#define BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_MASK           0x0040
#define BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_ALIGN          0
#define BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_BITS           1
#define BRPHY0_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_SHIFT          6

/* BRPHY0_DSP_TAP :: FFEX_CTL :: FFEX_MAINTAP [05:03] */
#define Wr_BRPHY0_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) WriteRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x38,3,x)
#define Rd_BRPHY0_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) ReadRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x38,3)
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_MASK                  0x0038
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_ALIGN                 0
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_BITS                  3
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_SHIFT                 3

/* BRPHY0_DSP_TAP :: FFEX_CTL :: FFEX_LMS_MODE [02:01] */
#define Wr_BRPHY0_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) WriteRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x6,1,x)
#define Rd_BRPHY0_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) ReadRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x6,1)
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_MASK                 0x0006
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_ALIGN                0
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_BITS                 2
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_SHIFT                1

/* BRPHY0_DSP_TAP :: FFEX_CTL :: FFEX_EN [00:00] */
#define Wr_BRPHY0_DSP_TAP_FFEX_CTL_FFEX_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_FFEX_CTL_FFEX_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_FFEX_CTL,0x1,0)
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_EN_MASK                       0x0001
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_EN_ALIGN                      0
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_EN_BITS                       1
#define BRPHY0_DSP_TAP_FFEX_CTL_FFEX_EN_SHIFT                      0


/****************************************************************************
 * BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL0
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_STOP [15:15] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_MASK 0x8000
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_BITS 1
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_SHIFT 15

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: reserved0 [14:07] */
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_MASK         0x7f80
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_ALIGN        0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_BITS         8
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_SHIFT        7

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_MAINSTATE [06:02] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_MASK 0x007c
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_BITS 5
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_SHIFT 2

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_CLR [01:01] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_MASK 0x0002
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_BITS 1
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_SHIFT 1

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_EN [00:00] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_MASK 0x0001
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_BITS 1
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_SHIFT 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL1
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D_EN [15:15] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_MASK 0x8000
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_BITS 1
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_SHIFT 15

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D [14:12] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_MASK 0x7000
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_BITS 3
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_SHIFT 12

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C_EN [11:11] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_MASK 0x0800
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_BITS 1
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_SHIFT 11

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C [10:08] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_MASK 0x0700
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_BITS 3
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_SHIFT 8

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B_EN [07:07] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_MASK 0x0080
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_BITS 1
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_SHIFT 7

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B [06:04] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_MASK 0x0070
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_BITS 3
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_SHIFT 4

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A_EN [03:03] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_MASK 0x0008
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_BITS 1
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_SHIFT 3

/* BRPHY0_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A [02:00] */
#define Wr_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) WriteRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0,x)
#define Rd_BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) ReadRegBits16(BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0)
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_MASK 0x0007
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_ALIGN 0
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_BITS 3
#define BRPHY0_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_SHIFT 0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_ADDR
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_ADDR :: CTL_ALL_CH [15:15] */
#define Wr_BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0x8000,15,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0x8000,15)
#define BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_MASK                 0x8000
#define BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_ALIGN                0
#define BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_BITS                 1
#define BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_SHIFT                15

/* BRPHY0_DSP_TAP :: FILTER_ADDR :: CH_SEL [14:13] */
#define Wr_BRPHY0_DSP_TAP_FILTER_ADDR_CH_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0x6000,13,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_ADDR_CH_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0x6000,13)
#define BRPHY0_DSP_TAP_FILTER_ADDR_CH_SEL_MASK                     0x6000
#define BRPHY0_DSP_TAP_FILTER_ADDR_CH_SEL_ALIGN                    0
#define BRPHY0_DSP_TAP_FILTER_ADDR_CH_SEL_BITS                     2
#define BRPHY0_DSP_TAP_FILTER_ADDR_CH_SEL_SHIFT                    13

/* BRPHY0_DSP_TAP :: FILTER_ADDR :: CTL_ALL_FILTERS [12:12] */
#define Wr_BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0x1000,12)
#define BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_MASK            0x1000
#define BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_BITS            1
#define BRPHY0_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_SHIFT           12

/* BRPHY0_DSP_TAP :: FILTER_ADDR :: FILTER_SEL [11:08] */
#define Wr_BRPHY0_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0xf00,8,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0xf00,8)
#define BRPHY0_DSP_TAP_FILTER_ADDR_FILTER_SEL_MASK                 0x0f00
#define BRPHY0_DSP_TAP_FILTER_ADDR_FILTER_SEL_ALIGN                0
#define BRPHY0_DSP_TAP_FILTER_ADDR_FILTER_SEL_BITS                 4
#define BRPHY0_DSP_TAP_FILTER_ADDR_FILTER_SEL_SHIFT                8

/* BRPHY0_DSP_TAP :: FILTER_ADDR :: TAP_NUMBER [07:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0xff,0,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_ADDR,0xff,0)
#define BRPHY0_DSP_TAP_FILTER_ADDR_TAP_NUMBER_MASK                 0x00ff
#define BRPHY0_DSP_TAP_FILTER_ADDR_TAP_NUMBER_ALIGN                0
#define BRPHY0_DSP_TAP_FILTER_ADDR_TAP_NUMBER_BITS                 8
#define BRPHY0_DSP_TAP_FILTER_ADDR_TAP_NUMBER_SHIFT                0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_CTL
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_CTL :: reserved0 [15:13] */
#define BRPHY0_DSP_TAP_FILTER_CTL_RESERVED0_MASK                   0xe000
#define BRPHY0_DSP_TAP_FILTER_CTL_RESERVED0_ALIGN                  0
#define BRPHY0_DSP_TAP_FILTER_CTL_RESERVED0_BITS                   3
#define BRPHY0_DSP_TAP_FILTER_CTL_RESERVED0_SHIFT                  13

/* BRPHY0_DSP_TAP :: FILTER_CTL :: BUSY [12:12] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_BUSY(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x1000,12,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_BUSY(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x1000,12)
#define BRPHY0_DSP_TAP_FILTER_CTL_BUSY_MASK                        0x1000
#define BRPHY0_DSP_TAP_FILTER_CTL_BUSY_ALIGN                       0
#define BRPHY0_DSP_TAP_FILTER_CTL_BUSY_BITS                        1
#define BRPHY0_DSP_TAP_FILTER_CTL_BUSY_SHIFT                       12

/* BRPHY0_DSP_TAP :: FILTER_CTL :: TAP_PREFETCH [11:11] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x800,11,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x800,11)
#define BRPHY0_DSP_TAP_FILTER_CTL_TAP_PREFETCH_MASK                0x0800
#define BRPHY0_DSP_TAP_FILTER_CTL_TAP_PREFETCH_ALIGN               0
#define BRPHY0_DSP_TAP_FILTER_CTL_TAP_PREFETCH_BITS                1
#define BRPHY0_DSP_TAP_FILTER_CTL_TAP_PREFETCH_SHIFT               11

/* BRPHY0_DSP_TAP :: FILTER_CTL :: UPPER_WORD_SEL [10:10] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x400,10,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x400,10)
#define BRPHY0_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_MASK              0x0400
#define BRPHY0_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_SHIFT             10

/* BRPHY0_DSP_TAP :: FILTER_CTL :: WR_COEFF [09:09] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_WR_COEFF(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x200,9,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_WR_COEFF(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x200,9)
#define BRPHY0_DSP_TAP_FILTER_CTL_WR_COEFF_MASK                    0x0200
#define BRPHY0_DSP_TAP_FILTER_CTL_WR_COEFF_ALIGN                   0
#define BRPHY0_DSP_TAP_FILTER_CTL_WR_COEFF_BITS                    1
#define BRPHY0_DSP_TAP_FILTER_CTL_WR_COEFF_SHIFT                   9

/* BRPHY0_DSP_TAP :: FILTER_CTL :: WR_ALL_NEXT_COEF [08:08] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x100,8,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x100,8)
#define BRPHY0_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_MASK            0x0100
#define BRPHY0_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_ALIGN           0
#define BRPHY0_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_BITS            1
#define BRPHY0_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_SHIFT           8

/* BRPHY0_DSP_TAP :: FILTER_CTL :: RD_COEFF [07:07] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_RD_COEFF(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x80,7,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_RD_COEFF(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x80,7)
#define BRPHY0_DSP_TAP_FILTER_CTL_RD_COEFF_MASK                    0x0080
#define BRPHY0_DSP_TAP_FILTER_CTL_RD_COEFF_ALIGN                   0
#define BRPHY0_DSP_TAP_FILTER_CTL_RD_COEFF_BITS                    1
#define BRPHY0_DSP_TAP_FILTER_CTL_RD_COEFF_SHIFT                   7

/* BRPHY0_DSP_TAP :: FILTER_CTL :: INIT_RAM [06:06] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_INIT_RAM(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x40,6,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_INIT_RAM(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x40,6)
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_RAM_MASK                    0x0040
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_RAM_ALIGN                   0
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_RAM_BITS                    1
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_RAM_SHIFT                   6

/* BRPHY0_DSP_TAP :: FILTER_CTL :: INIT_ENC [05:05] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_INIT_ENC(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x20,5,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_INIT_ENC(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x20,5)
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_ENC_MASK                    0x0020
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_ENC_ALIGN                   0
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_ENC_BITS                    1
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_ENC_SHIFT                   5

/* BRPHY0_DSP_TAP :: FILTER_CTL :: INIT_DFE [04:04] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_INIT_DFE(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x10,4,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_INIT_DFE(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x10,4)
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_DFE_MASK                    0x0010
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_DFE_ALIGN                   0
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_DFE_BITS                    1
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_DFE_SHIFT                   4

/* BRPHY0_DSP_TAP :: FILTER_CTL :: INIT_FFEXTAP [03:03] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x8,3,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x8,3)
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_MASK                0x0008
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_ALIGN               0
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_BITS                1
#define BRPHY0_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_SHIFT               3

/* BRPHY0_DSP_TAP :: FILTER_CTL :: DISABLE_FILTER [02:02] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x4,2,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x4,2)
#define BRPHY0_DSP_TAP_FILTER_CTL_DISABLE_FILTER_MASK              0x0004
#define BRPHY0_DSP_TAP_FILTER_CTL_DISABLE_FILTER_ALIGN             0
#define BRPHY0_DSP_TAP_FILTER_CTL_DISABLE_FILTER_BITS              1
#define BRPHY0_DSP_TAP_FILTER_CTL_DISABLE_FILTER_SHIFT             2

/* BRPHY0_DSP_TAP :: FILTER_CTL :: FREEZE_FILTER [01:01] */
#define Wr_BRPHY0_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) WriteRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x2,1,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) ReadRegBits16(BRPHY0_DSP_TAP_FILTER_CTL,0x2,1)
#define BRPHY0_DSP_TAP_FILTER_CTL_FREEZE_FILTER_MASK               0x0002
#define BRPHY0_DSP_TAP_FILTER_CTL_FREEZE_FILTER_ALIGN              0
#define BRPHY0_DSP_TAP_FILTER_CTL_FREEZE_FILTER_BITS               1
#define BRPHY0_DSP_TAP_FILTER_CTL_FREEZE_FILTER_SHIFT              1

/* BRPHY0_DSP_TAP :: FILTER_CTL :: reserved1 [00:00] */
#define BRPHY0_DSP_TAP_FILTER_CTL_RESERVED1_MASK                   0x0001
#define BRPHY0_DSP_TAP_FILTER_CTL_RESERVED1_ALIGN                  0
#define BRPHY0_DSP_TAP_FILTER_CTL_RESERVED1_BITS                   1
#define BRPHY0_DSP_TAP_FILTER_CTL_RESERVED1_SHIFT                  0


/****************************************************************************
 * BRPHY0_DSP_TAP :: FILTER_DATA
 ***************************************************************************/
/* BRPHY0_DSP_TAP :: FILTER_DATA :: TAP_COEFF [15:00] */
#define Wr_BRPHY0_DSP_TAP_FILTER_DATA_TAP_COEFF(x) WriteReg16(BRPHY0_DSP_TAP_FILTER_DATA,x)
#define Rd_BRPHY0_DSP_TAP_FILTER_DATA_TAP_COEFF(x) ReadReg16(BRPHY0_DSP_TAP_FILTER_DATA)
#define BRPHY0_DSP_TAP_FILTER_DATA_TAP_COEFF_MASK                  0xffff
#define BRPHY0_DSP_TAP_FILTER_DATA_TAP_COEFF_ALIGN                 0
#define BRPHY0_DSP_TAP_FILTER_DATA_TAP_COEFF_BITS                  16
#define BRPHY0_DSP_TAP_FILTER_DATA_TAP_COEFF_SHIFT                 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_PLL_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLLCTRL_0
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLLCTRL_0 :: PLL_CTL [15:00] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) WriteReg16(BRPHY0_PLL_CTRL_PLLCTRL_0,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) ReadReg16(BRPHY0_PLL_CTRL_PLLCTRL_0)
#define BRPHY0_PLL_CTRL_PLLCTRL_0_PLL_CTL_MASK                     0xffff
#define BRPHY0_PLL_CTRL_PLLCTRL_0_PLL_CTL_ALIGN                    0
#define BRPHY0_PLL_CTRL_PLLCTRL_0_PLL_CTL_BITS                     16
#define BRPHY0_PLL_CTRL_PLLCTRL_0_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLLCTRL_1
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLLCTRL_1 :: PLL_CTL [15:00] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) WriteReg16(BRPHY0_PLL_CTRL_PLLCTRL_1,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) ReadReg16(BRPHY0_PLL_CTRL_PLLCTRL_1)
#define BRPHY0_PLL_CTRL_PLLCTRL_1_PLL_CTL_MASK                     0xffff
#define BRPHY0_PLL_CTRL_PLLCTRL_1_PLL_CTL_ALIGN                    0
#define BRPHY0_PLL_CTRL_PLLCTRL_1_PLL_CTL_BITS                     16
#define BRPHY0_PLL_CTRL_PLLCTRL_1_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLLCTRL_2
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2 [15:14] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_2,0xc000,14,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_2,0xc000,14)
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_MASK                  0xc000
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_ALIGN                 0
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_BITS                  2
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_SHIFT                 14

/* BRPHY0_PLL_CTRL :: PLLCTRL_2 :: PLL_PDIV [13:10] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_2,0x3c00,10,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_2,0x3c00,10)
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_PDIV_MASK                    0x3c00
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_PDIV_ALIGN                   0
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_PDIV_BITS                    4
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_PDIV_SHIFT                   10

/* BRPHY0_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2_2 [09:00] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_2,0x3ff,0,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_2,0x3ff,0)
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_MASK                0x03ff
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_ALIGN               0
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_BITS                10
#define BRPHY0_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_SHIFT               0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLLCTRL_3
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLLCTRL_3 :: PLL_SPARE3 [15:10] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_3,0xfc00,10,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_3,0xfc00,10)
#define BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_MASK                  0xfc00
#define BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_ALIGN                 0
#define BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_BITS                  6
#define BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_SHIFT                 10

/* BRPHY0_PLL_CTRL :: PLLCTRL_3 :: PLL_NDIV_INT_MS [09:00] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_3,0x3ff,0,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_3,0x3ff,0)
#define BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_MASK             0x03ff
#define BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_ALIGN            0
#define BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_BITS             10
#define BRPHY0_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_SHIFT            0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLLCTRL_4
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4 [15:15] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x8000,15,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x8000,15)
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_MASK                  0x8000
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_ALIGN                 0
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_BITS                  1
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_SHIFT                 15

/* BRPHY0_PLL_CTRL :: PLLCTRL_4 :: SD_SEL_300mV [14:14] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x4000,14,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x4000,14)
#define BRPHY0_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_MASK                0x4000
#define BRPHY0_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_ALIGN               0
#define BRPHY0_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_BITS                1
#define BRPHY0_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_SHIFT               14

/* BRPHY0_PLL_CTRL :: PLLCTRL_4 :: CML_BUF_TUNE [13:12] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x3000,12,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x3000,12)
#define BRPHY0_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_MASK                0x3000
#define BRPHY0_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_ALIGN               0
#define BRPHY0_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_BITS                2
#define BRPHY0_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_SHIFT               12

/* BRPHY0_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_BANDGAP [11:09] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0xe00,9,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0xe00,9)
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_MASK            0x0e00
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_ALIGN           0
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_BITS            3
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_SHIFT           9

/* BRPHY0_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4a [08:06] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x1c0,6,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x1c0,6)
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_MASK                 0x01c0
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_ALIGN                0
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_BITS                 3
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_SHIFT                6

/* BRPHY0_PLL_CTRL :: PLLCTRL_4 :: ATEST_OR_BIAS_TEST_OUTPUT [05:05] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x20,5,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x20,5)
#define BRPHY0_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_MASK   0x0020
#define BRPHY0_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_ALIGN  0
#define BRPHY0_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_BITS   1
#define BRPHY0_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_SHIFT  5

/* BRPHY0_PLL_CTRL :: PLLCTRL_4 :: PLL_MUX_ATEST [04:03] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x18,3,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x18,3)
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_MASK               0x0018
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_ALIGN              0
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_BITS               2
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_SHIFT              3

/* BRPHY0_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_TEST_MUX [02:00] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x7,0,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_4,0x7,0)
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_MASK           0x0007
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_ALIGN          0
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_BITS           3
#define BRPHY0_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_SHIFT          0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLLCTRL_5
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLLCTRL_5 :: PLL_SPARE5 [15:14] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0xc000,14,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0xc000,14)
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_MASK                  0xc000
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_ALIGN                 0
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_BITS                  2
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_SHIFT                 14

/* BRPHY0_PLL_CTRL :: PLLCTRL_5 :: PLL_CP [13:13] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x2000,13,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x2000,13)
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP_MASK                      0x2000
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP_ALIGN                     0
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP_BITS                      1
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP_SHIFT                     13

/* BRPHY0_PLL_CTRL :: PLLCTRL_5 :: PLL_CP1 [12:12] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x1000,12,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x1000,12)
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP1_MASK                     0x1000
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP1_ALIGN                    0
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP1_BITS                     1
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CP1_SHIFT                    12

/* BRPHY0_PLL_CTRL :: PLLCTRL_5 :: PLL_CZ [11:11] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x800,11,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x800,11)
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CZ_MASK                      0x0800
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CZ_ALIGN                     0
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CZ_BITS                      1
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_CZ_SHIFT                     11

/* BRPHY0_PLL_CTRL :: PLLCTRL_5 :: PLL_RZ [10:07] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x780,7,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x780,7)
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_RZ_MASK                      0x0780
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_RZ_ALIGN                     0
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_RZ_BITS                      4
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_RZ_SHIFT                     7

/* BRPHY0_PLL_CTRL :: PLLCTRL_5 :: PLL_ICP [06:03] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x78,3,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x78,3)
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_ICP_MASK                     0x0078
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_ICP_ALIGN                    0
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_ICP_BITS                     4
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_ICP_SHIFT                    3

/* BRPHY0_PLL_CTRL :: PLLCTRL_5 :: PLL_VCO_GAIN [02:00] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x7,0,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_5,0x7,0)
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_MASK                0x0007
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_ALIGN               0
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_BITS                3
#define BRPHY0_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_SHIFT               0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLLCTRL_6
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLLCTRL_6 :: PLL_SPARE6 [15:09] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0xfe00,9,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0xfe00,9)
#define BRPHY0_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_MASK                  0xfe00
#define BRPHY0_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_ALIGN                 0
#define BRPHY0_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_BITS                  7
#define BRPHY0_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_SHIFT                 9

/* BRPHY0_PLL_CTRL :: PLLCTRL_6 :: POR_CONFIG [08:07] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0x180,7,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0x180,7)
#define BRPHY0_PLL_CTRL_PLLCTRL_6_POR_CONFIG_MASK                  0x0180
#define BRPHY0_PLL_CTRL_PLLCTRL_6_POR_CONFIG_ALIGN                 0
#define BRPHY0_PLL_CTRL_PLLCTRL_6_POR_CONFIG_BITS                  2
#define BRPHY0_PLL_CTRL_PLLCTRL_6_POR_CONFIG_SHIFT                 7

/* BRPHY0_PLL_CTRL :: PLLCTRL_6 :: CLK500_EN [06:06] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0x40,6,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0x40,6)
#define BRPHY0_PLL_CTRL_PLLCTRL_6_CLK500_EN_MASK                   0x0040
#define BRPHY0_PLL_CTRL_PLLCTRL_6_CLK500_EN_ALIGN                  0
#define BRPHY0_PLL_CTRL_PLLCTRL_6_CLK500_EN_BITS                   1
#define BRPHY0_PLL_CTRL_PLLCTRL_6_CLK500_EN_SHIFT                  6

/* BRPHY0_PLL_CTRL :: PLLCTRL_6 :: RCAL_OFFSET [05:03] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0x38,3,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0x38,3)
#define BRPHY0_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_MASK                 0x0038
#define BRPHY0_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_ALIGN                0
#define BRPHY0_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_BITS                 3
#define BRPHY0_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_SHIFT                3

/* BRPHY0_PLL_CTRL :: PLLCTRL_6 :: RCCAL_OFFSET [02:00] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0x7,0,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_6,0x7,0)
#define BRPHY0_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_MASK                0x0007
#define BRPHY0_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_ALIGN               0
#define BRPHY0_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_BITS                3
#define BRPHY0_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_SHIFT               0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLL_STATUS_0
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLL_STATUS_0 :: reserved0 [15:12] */
#define BRPHY0_PLL_CTRL_PLL_STATUS_0_RESERVED0_MASK                0xf000
#define BRPHY0_PLL_CTRL_PLL_STATUS_0_RESERVED0_ALIGN               0
#define BRPHY0_PLL_CTRL_PLL_STATUS_0_RESERVED0_BITS                4
#define BRPHY0_PLL_CTRL_PLL_STATUS_0_RESERVED0_SHIFT               12

/* BRPHY0_PLL_CTRL :: PLL_STATUS_0 :: PLL_STATUS_WORD [11:00] */
#define Wr_BRPHY0_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLL_STATUS_0,0xfff,0,x)
#define Rd_BRPHY0_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLL_STATUS_0,0xfff,0)
#define BRPHY0_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_MASK          0x0fff
#define BRPHY0_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_ALIGN         0
#define BRPHY0_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_BITS          12
#define BRPHY0_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_SHIFT         0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLL_STATUS_1
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLL_STATUS_1 :: reserved0 [15:09] */
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_RESERVED0_MASK                0xfe00
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_RESERVED0_ALIGN               0
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_RESERVED0_BITS                7
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_RESERVED0_SHIFT               9

/* BRPHY0_PLL_CTRL :: PLL_STATUS_1 :: PLL_LOCK [08:08] */
#define Wr_BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLL_STATUS_1,0x100,8,x)
#define Rd_BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLL_STATUS_1,0x100,8)
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_MASK                 0x0100
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_ALIGN                0
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_BITS                 1
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_SHIFT                8

/* BRPHY0_PLL_CTRL :: PLL_STATUS_1 :: reserved1 [07:04] */
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_RESERVED1_MASK                0x00f0
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_RESERVED1_ALIGN               0
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_RESERVED1_BITS                4
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_RESERVED1_SHIFT               4

/* BRPHY0_PLL_CTRL :: PLL_STATUS_1 :: PLL_BER [03:00] */
#define Wr_BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLL_STATUS_1,0xf,0,x)
#define Rd_BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLL_STATUS_1,0xf,0)
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_BER_MASK                  0x000f
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_BER_ALIGN                 0
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_BER_BITS                  4
#define BRPHY0_PLL_CTRL_PLL_STATUS_1_PLL_BER_SHIFT                 0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: AFE_SIGDET_STATUS
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: AFE_SIGDET_STATUS :: reserved0 [15:07] */
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_MASK           0xff80
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_ALIGN          0
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_BITS           9
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_SHIFT          7

/* BRPHY0_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_SIGSTATE [06:01] */
#define Wr_BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) WriteRegBits16(BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1,x)
#define Rd_BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) ReadRegBits16(BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1)
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_MASK    0x007e
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_ALIGN   0
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_BITS    6
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_SHIFT   1

/* BRPHY0_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_Select [00:00] */
#define Wr_BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) WriteRegBits16(BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0,x)
#define Rd_BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) ReadRegBits16(BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0)
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_MASK      0x0001
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_ALIGN     0
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_BITS      1
#define BRPHY0_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_SHIFT     0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLLCTRL_7
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLLCTRL_7 :: TVCO_MUX_EN [15:15] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x8000,15,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x8000,15)
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_MASK                 0x8000
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_ALIGN                0
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_BITS                 1
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_SHIFT                15

/* BRPHY0_PLL_CTRL :: PLLCTRL_7 :: TVCO_PAD [14:12] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x7000,12,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x7000,12)
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_PAD_MASK                    0x7000
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_PAD_ALIGN                   0
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_PAD_BITS                    3
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TVCO_PAD_SHIFT                   12

/* BRPHY0_PLL_CTRL :: PLLCTRL_7 :: ADJUST_AUX_LDO [11:11] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x800,11,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x800,11)
#define BRPHY0_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_MASK              0x0800
#define BRPHY0_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_ALIGN             0
#define BRPHY0_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_BITS              1
#define BRPHY0_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_SHIFT             11

/* BRPHY0_PLL_CTRL :: PLLCTRL_7 :: CLAMP_REFERENCE [10:09] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x600,9,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x600,9)
#define BRPHY0_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_MASK             0x0600
#define BRPHY0_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_ALIGN            0
#define BRPHY0_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_BITS             2
#define BRPHY0_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_SHIFT            9

/* BRPHY0_PLL_CTRL :: PLLCTRL_7 :: CML_BUFFER_PWRDN [08:08] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x100,8,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0x100,8)
#define BRPHY0_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_MASK            0x0100
#define BRPHY0_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_ALIGN           0
#define BRPHY0_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_BITS            1
#define BRPHY0_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_SHIFT           8

/* BRPHY0_PLL_CTRL :: PLLCTRL_7 :: TXCLK_PWRDN [07:04] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0xf0,4,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0xf0,4)
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_MASK                 0x00f0
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_ALIGN                0
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_BITS                 4
#define BRPHY0_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_SHIFT                4

/* BRPHY0_PLL_CTRL :: PLLCTRL_7 :: RXCLK_PWRDN [03:00] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0xf,0,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_7,0xf,0)
#define BRPHY0_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_MASK                 0x000f
#define BRPHY0_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_ALIGN                0
#define BRPHY0_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_BITS                 4
#define BRPHY0_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_SHIFT                0


/****************************************************************************
 * BRPHY0_PLL_CTRL :: PLLCTRL_8
 ***************************************************************************/
/* BRPHY0_PLL_CTRL :: PLLCTRL_8 :: PLL_SPARE5 [15:01] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_8,0xfffe,1,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_8,0xfffe,1)
#define BRPHY0_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_MASK                  0xfffe
#define BRPHY0_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_ALIGN                 0
#define BRPHY0_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_BITS                  15
#define BRPHY0_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_SHIFT                 1

/* BRPHY0_PLL_CTRL :: PLLCTRL_8 :: PC_CLK_1G_PWRDN [00:00] */
#define Wr_BRPHY0_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) WriteRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_8,0x1,0,x)
#define Rd_BRPHY0_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) ReadRegBits16(BRPHY0_PLL_CTRL_PLLCTRL_8,0x1,0)
#define BRPHY0_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_MASK             0x0001
#define BRPHY0_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_ALIGN            0
#define BRPHY0_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_BITS             1
#define BRPHY0_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_SHIFT            0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_AFE_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_AFE_CTRL :: RXCONFIG_0
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: RXCONFIG_0 :: RXCONFIG_15_0 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) WriteReg16(BRPHY0_AFE_CTRL_RXCONFIG_0,x)
#define Rd_BRPHY0_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) ReadReg16(BRPHY0_AFE_CTRL_RXCONFIG_0)
#define BRPHY0_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_MASK              0xffff
#define BRPHY0_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_ALIGN             0
#define BRPHY0_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_BITS              16
#define BRPHY0_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_SHIFT             0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: RXCONFIG_1
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: RXCONFIG_1 :: RXCONFIG_31_23 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) WriteReg16(BRPHY0_AFE_CTRL_RXCONFIG_1,x)
#define Rd_BRPHY0_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) ReadReg16(BRPHY0_AFE_CTRL_RXCONFIG_1)
#define BRPHY0_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_MASK             0xffff
#define BRPHY0_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_ALIGN            0
#define BRPHY0_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_BITS             16
#define BRPHY0_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_SHIFT            0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: RXCONFIG_2
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: RXCONFIG_2 :: RXCONFIG_47_32 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) WriteReg16(BRPHY0_AFE_CTRL_RXCONFIG_2,x)
#define Rd_BRPHY0_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) ReadReg16(BRPHY0_AFE_CTRL_RXCONFIG_2)
#define BRPHY0_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_MASK             0xffff
#define BRPHY0_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_ALIGN            0
#define BRPHY0_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_BITS             16
#define BRPHY0_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_SHIFT            0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: RXCONFIG_3
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: RXCONFIG_3 :: RXCONFIG_63_48 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) WriteReg16(BRPHY0_AFE_CTRL_RXCONFIG_3,x)
#define Rd_BRPHY0_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) ReadReg16(BRPHY0_AFE_CTRL_RXCONFIG_3)
#define BRPHY0_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_MASK             0xffff
#define BRPHY0_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_ALIGN            0
#define BRPHY0_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_BITS             16
#define BRPHY0_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_SHIFT            0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: RXCONFIG_4
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: RXCONFIG_4 :: RXCONFIG_79_64 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) WriteReg16(BRPHY0_AFE_CTRL_RXCONFIG_4,x)
#define Rd_BRPHY0_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) ReadReg16(BRPHY0_AFE_CTRL_RXCONFIG_4)
#define BRPHY0_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_MASK             0xffff
#define BRPHY0_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_ALIGN            0
#define BRPHY0_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_BITS             16
#define BRPHY0_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_SHIFT            0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: RXCONFIG5_LP
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: RXCONFIG5_LP :: RXCONFIG_86_80 [15:09] */
#define Wr_BRPHY0_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) WriteRegBits16(BRPHY0_AFE_CTRL_RXCONFIG5_LP,0xfe00,9,x)
#define Rd_BRPHY0_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) ReadRegBits16(BRPHY0_AFE_CTRL_RXCONFIG5_LP,0xfe00,9)
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_MASK           0xfe00
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_ALIGN          0
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_BITS           7
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_SHIFT          9

/* BRPHY0_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_0 [08:06] */
#define Wr_BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) WriteRegBits16(BRPHY0_AFE_CTRL_RXCONFIG5_LP,0x1c0,6,x)
#define Rd_BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) ReadRegBits16(BRPHY0_AFE_CTRL_RXCONFIG5_LP,0x1c0,6)
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_MASK                  0x01c0
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_ALIGN                 0
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_BITS                  3
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_SHIFT                 6

/* BRPHY0_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_1 [05:03] */
#define Wr_BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) WriteRegBits16(BRPHY0_AFE_CTRL_RXCONFIG5_LP,0x38,3,x)
#define Rd_BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) ReadRegBits16(BRPHY0_AFE_CTRL_RXCONFIG5_LP,0x38,3)
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_MASK                  0x0038
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_ALIGN                 0
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_BITS                  3
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_SHIFT                 3

/* BRPHY0_AFE_CTRL :: RXCONFIG5_LP :: MODE_force [02:00] */
#define Wr_BRPHY0_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) WriteRegBits16(BRPHY0_AFE_CTRL_RXCONFIG5_LP,0x7,0,x)
#define Rd_BRPHY0_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) ReadRegBits16(BRPHY0_AFE_CTRL_RXCONFIG5_LP,0x7,0)
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_MASK               0x0007
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_ALIGN              0
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_BITS               3
#define BRPHY0_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_SHIFT              0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: TX_CONFIG_0
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: TX_CONFIG_0 :: TX_CONFIG_15_0 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) WriteReg16(BRPHY0_AFE_CTRL_TX_CONFIG_0,x)
#define Rd_BRPHY0_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) ReadReg16(BRPHY0_AFE_CTRL_TX_CONFIG_0)
#define BRPHY0_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_MASK            0xffff
#define BRPHY0_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_ALIGN           0
#define BRPHY0_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_BITS            16
#define BRPHY0_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_SHIFT           0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: TX_CONFIG_1
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: TX_CONFIG_1 :: TX_BW_TUNE [15:11] */
#define Wr_BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) WriteRegBits16(BRPHY0_AFE_CTRL_TX_CONFIG_1,0xf800,11,x)
#define Rd_BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) ReadRegBits16(BRPHY0_AFE_CTRL_TX_CONFIG_1,0xf800,11)
#define BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_MASK                0xf800
#define BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_ALIGN               0
#define BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_BITS                5
#define BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_SHIFT               11

/* BRPHY0_AFE_CTRL :: TX_CONFIG_1 :: TX_CONFIG_26_16 [10:00] */
#define Wr_BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) WriteRegBits16(BRPHY0_AFE_CTRL_TX_CONFIG_1,0x7ff,0,x)
#define Rd_BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) ReadRegBits16(BRPHY0_AFE_CTRL_TX_CONFIG_1,0x7ff,0)
#define BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_MASK           0x07ff
#define BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_ALIGN          0
#define BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_BITS           11
#define BRPHY0_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_SHIFT          0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: VDAC_ICTRL_0
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: VDAC_ICTRL_0 :: VDAC_current_ctrl_15_0 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) WriteReg16(BRPHY0_AFE_CTRL_VDAC_ICTRL_0,x)
#define Rd_BRPHY0_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) ReadReg16(BRPHY0_AFE_CTRL_VDAC_ICTRL_0)
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_MASK   0xffff
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_ALIGN  0
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_BITS   16
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_SHIFT  0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: VDAC_ICTRL_1
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: VDAC_ICTRL_1 :: VDAC_current_ctrl_31_16 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) WriteReg16(BRPHY0_AFE_CTRL_VDAC_ICTRL_1,x)
#define Rd_BRPHY0_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) ReadReg16(BRPHY0_AFE_CTRL_VDAC_ICTRL_1)
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_MASK  0xffff
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_ALIGN 0
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_BITS  16
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_SHIFT 0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: VDAC_ICTRL_2
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: VDAC_ICTRL_2 :: VDAC_current_ctrl_51_36 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) WriteReg16(BRPHY0_AFE_CTRL_VDAC_ICTRL_2,x)
#define Rd_BRPHY0_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) ReadReg16(BRPHY0_AFE_CTRL_VDAC_ICTRL_2)
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_MASK  0xffff
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_ALIGN 0
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_BITS  16
#define BRPHY0_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_SHIFT 0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: VDAC_OTHERS_0
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: VDAC_OTHERS_0 :: current_ctrl_35_32_others [15:00] */
#define Wr_BRPHY0_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) WriteReg16(BRPHY0_AFE_CTRL_VDAC_OTHERS_0,x)
#define Rd_BRPHY0_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) ReadReg16(BRPHY0_AFE_CTRL_VDAC_OTHERS_0)
#define BRPHY0_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_MASK 0xffff
#define BRPHY0_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_ALIGN 0
#define BRPHY0_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_BITS 16
#define BRPHY0_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_SHIFT 0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: HPF_TRIM_OTHERS
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: HPF_TRIM_OTHERS :: Reserved [15:10] */
#define Wr_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) WriteRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10,x)
#define Rd_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) ReadRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10)
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_MASK              0xfc00
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_ALIGN             0
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_BITS              6
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_SHIFT             10

/* BRPHY0_AFE_CTRL :: HPF_TRIM_OTHERS :: RX_SAMPLE_WIDTH [09:07] */
#define Wr_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) WriteRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7,x)
#define Rd_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) ReadRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7)
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_MASK       0x0380
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_ALIGN      0
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_BITS       3
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_SHIFT      7

/* BRPHY0_AFE_CTRL :: HPF_TRIM_OTHERS :: IDAC_fine_tune [06:04] */
#define Wr_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) WriteRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4,x)
#define Rd_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) ReadRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4)
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_MASK        0x0070
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_ALIGN       0
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_BITS        3
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_SHIFT       4

/* BRPHY0_AFE_CTRL :: HPF_TRIM_OTHERS :: SOFT_SEL_TRIM_HPF [03:03] */
#define Wr_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) WriteRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3,x)
#define Rd_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) ReadRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3)
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_MASK     0x0008
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_ALIGN    0
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_BITS     1
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_SHIFT    3

/* BRPHY0_AFE_CTRL :: HPF_TRIM_OTHERS :: TRIM_HPF [02:00] */
#define Wr_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) WriteRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0,x)
#define Rd_BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) ReadRegBits16(BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0)
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_MASK              0x0007
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_ALIGN             0
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_BITS              3
#define BRPHY0_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_SHIFT             0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: TX_EXTRA_CONFIG_0
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: TX_EXTRA_CONFIG_0 :: TX_EXTRA_CONFIG_15_0 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) WriteReg16(BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_0,x)
#define Rd_BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) ReadReg16(BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_0)
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_MASK 0xffff
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_ALIGN 0
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_BITS 16
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_SHIFT 0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: TX_EXTRA_CONFIG_1
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: TX_EXTRA_CONFIG_1 :: TX_EXTRA_CONFIG_31_16 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) WriteReg16(BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_1,x)
#define Rd_BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) ReadReg16(BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_1)
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_MASK 0xffff
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_ALIGN 0
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_BITS 16
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_SHIFT 0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: TX_EXTRA_CONFIG_2
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: TX_EXTRA_CONFIG_2 :: TX_EXTRA_CONFIG_47_32 [15:00] */
#define Wr_BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) WriteReg16(BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_2,x)
#define Rd_BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) ReadReg16(BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_2)
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_MASK 0xffff
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_ALIGN 0
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_BITS 16
#define BRPHY0_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_SHIFT 0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: TEMPSEN_OTHERS
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: TEMPSEN_OTHERS :: TEMPSEN [15:02] */
#define Wr_BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) WriteRegBits16(BRPHY0_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2,x)
#define Rd_BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) ReadRegBits16(BRPHY0_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2)
#define BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_MASK                0xfffc
#define BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_ALIGN               0
#define BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_BITS                14
#define BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_SHIFT               2

/* BRPHY0_AFE_CTRL :: TEMPSEN_OTHERS :: EXTRA_10BT [01:00] */
#define Wr_BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) WriteRegBits16(BRPHY0_AFE_CTRL_TEMPSEN_OTHERS,0x3,0,x)
#define Rd_BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) ReadRegBits16(BRPHY0_AFE_CTRL_TEMPSEN_OTHERS,0x3,0)
#define BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_MASK             0x0003
#define BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_ALIGN            0
#define BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_BITS             2
#define BRPHY0_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_SHIFT            0


/****************************************************************************
 * BRPHY0_AFE_CTRL :: FUTURE_RSV
 ***************************************************************************/
/* BRPHY0_AFE_CTRL :: FUTURE_RSV :: FUTURE_RSV [15:00] */
#define Wr_BRPHY0_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) WriteReg16(BRPHY0_AFE_CTRL_FUTURE_RSV,x)
#define Rd_BRPHY0_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) ReadReg16(BRPHY0_AFE_CTRL_FUTURE_RSV)
#define BRPHY0_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_MASK                 0xffff
#define BRPHY0_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_ALIGN                0
#define BRPHY0_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_BITS                 16
#define BRPHY0_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_ECD_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC0
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC0 :: RUN_IMMEDIATE [15:15] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x8000,15,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x8000,15)
#define BRPHY0_ECD_CTRL_EXPC0_RUN_IMMEDIATE_MASK                   0x8000
#define BRPHY0_ECD_CTRL_EXPC0_RUN_IMMEDIATE_ALIGN                  0
#define BRPHY0_ECD_CTRL_EXPC0_RUN_IMMEDIATE_BITS                   1
#define BRPHY0_ECD_CTRL_EXPC0_RUN_IMMEDIATE_SHIFT                  15

/* BRPHY0_ECD_CTRL :: EXPC0 :: RUN_AT_AUTONEG [14:14] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x4000,14,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x4000,14)
#define BRPHY0_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_MASK                  0x4000
#define BRPHY0_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_ALIGN                 0
#define BRPHY0_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_BITS                  1
#define BRPHY0_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_SHIFT                 14

/* BRPHY0_ECD_CTRL :: EXPC0 :: INTER_PAIR_SHORT_DIS [13:13] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x2000,13,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x2000,13)
#define BRPHY0_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_MASK            0x2000
#define BRPHY0_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_ALIGN           0
#define BRPHY0_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_BITS            1
#define BRPHY0_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_SHIFT           13

/* BRPHY0_ECD_CTRL :: EXPC0 :: BREAK_LINK [12:12] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_BREAK_LINK(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x1000,12,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_BREAK_LINK(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x1000,12)
#define BRPHY0_ECD_CTRL_EXPC0_BREAK_LINK_MASK                      0x1000
#define BRPHY0_ECD_CTRL_EXPC0_BREAK_LINK_ALIGN                     0
#define BRPHY0_ECD_CTRL_EXPC0_BREAK_LINK_BITS                      1
#define BRPHY0_ECD_CTRL_EXPC0_BREAK_LINK_SHIFT                     12

/* BRPHY0_ECD_CTRL :: EXPC0 :: CABLE_DIAG_STATUS [11:11] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x800,11,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x800,11)
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_MASK               0x0800
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_ALIGN              0
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_BITS               1
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_SHIFT              11

/* BRPHY0_ECD_CTRL :: EXPC0 :: CABLE_LEN_UNIT [10:10] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x400,10,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x400,10)
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_MASK                  0x0400
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_ALIGN                 0
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_BITS                  1
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_SHIFT                 10

/* BRPHY0_ECD_CTRL :: EXPC0 :: reserved0 [09:09] */
#define BRPHY0_ECD_CTRL_EXPC0_RESERVED0_MASK                       0x0200
#define BRPHY0_ECD_CTRL_EXPC0_RESERVED0_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPC0_RESERVED0_BITS                       1
#define BRPHY0_ECD_CTRL_EXPC0_RESERVED0_SHIFT                      9

/* BRPHY0_ECD_CTRL :: EXPC0 :: FAST_TIMER_ENABLE [08:08] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x100,8,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x100,8)
#define BRPHY0_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_MASK               0x0100
#define BRPHY0_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_ALIGN              0
#define BRPHY0_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_BITS               1
#define BRPHY0_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_SHIFT              8

/* BRPHY0_ECD_CTRL :: EXPC0 :: INTRPT_ENABLE [07:07] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x80,7,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x80,7)
#define BRPHY0_ECD_CTRL_EXPC0_INTRPT_ENABLE_MASK                   0x0080
#define BRPHY0_ECD_CTRL_EXPC0_INTRPT_ENABLE_ALIGN                  0
#define BRPHY0_ECD_CTRL_EXPC0_INTRPT_ENABLE_BITS                   1
#define BRPHY0_ECD_CTRL_EXPC0_INTRPT_ENABLE_SHIFT                  7

/* BRPHY0_ECD_CTRL :: EXPC0 :: STOP_PLL_CLK [06:06] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x40,6,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x40,6)
#define BRPHY0_ECD_CTRL_EXPC0_STOP_PLL_CLK_MASK                    0x0040
#define BRPHY0_ECD_CTRL_EXPC0_STOP_PLL_CLK_ALIGN                   0
#define BRPHY0_ECD_CTRL_EXPC0_STOP_PLL_CLK_BITS                    1
#define BRPHY0_ECD_CTRL_EXPC0_STOP_PLL_CLK_SHIFT                   6

/* BRPHY0_ECD_CTRL :: EXPC0 :: reserved1 [05:04] */
#define BRPHY0_ECD_CTRL_EXPC0_RESERVED1_MASK                       0x0030
#define BRPHY0_ECD_CTRL_EXPC0_RESERVED1_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPC0_RESERVED1_BITS                       2
#define BRPHY0_ECD_CTRL_EXPC0_RESERVED1_SHIFT                      4

/* BRPHY0_ECD_CTRL :: EXPC0 :: INVALID_RESULT [03:03] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_INVALID_RESULT(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x8,3,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_INVALID_RESULT(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x8,3)
#define BRPHY0_ECD_CTRL_EXPC0_INVALID_RESULT_MASK                  0x0008
#define BRPHY0_ECD_CTRL_EXPC0_INVALID_RESULT_ALIGN                 0
#define BRPHY0_ECD_CTRL_EXPC0_INVALID_RESULT_BITS                  1
#define BRPHY0_ECD_CTRL_EXPC0_INVALID_RESULT_SHIFT                 3

/* BRPHY0_ECD_CTRL :: EXPC0 :: CABLE_DIAG_EXE [02:02] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x4,2,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x4,2)
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_MASK                  0x0004
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_ALIGN                 0
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_BITS                  1
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_SHIFT                 2

/* BRPHY0_ECD_CTRL :: EXPC0 :: AUTO_RUN_FOR_BROKEN_ANG [01:01] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x2,1,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x2,1)
#define BRPHY0_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_MASK         0x0002
#define BRPHY0_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_ALIGN        0
#define BRPHY0_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_BITS         1
#define BRPHY0_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_SHIFT        1

/* BRPHY0_ECD_CTRL :: EXPC0 :: CABLE_TYPE [00:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC0_CABLE_TYPE(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x1,0,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC0_CABLE_TYPE(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC0,0x1,0)
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_TYPE_MASK                      0x0001
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_TYPE_ALIGN                     0
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_TYPE_BITS                      1
#define BRPHY0_ECD_CTRL_EXPC0_CABLE_TYPE_SHIFT                     0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC1
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC1 :: PA_CD_CODE [15:12] */
#define Wr_BRPHY0_ECD_CTRL_EXPC1_PA_CD_CODE(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC1,0xf000,12,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC1_PA_CD_CODE(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC1,0xf000,12)
#define BRPHY0_ECD_CTRL_EXPC1_PA_CD_CODE_MASK                      0xf000
#define BRPHY0_ECD_CTRL_EXPC1_PA_CD_CODE_ALIGN                     0
#define BRPHY0_ECD_CTRL_EXPC1_PA_CD_CODE_BITS                      4
#define BRPHY0_ECD_CTRL_EXPC1_PA_CD_CODE_SHIFT                     12

/* BRPHY0_ECD_CTRL :: EXPC1 :: PB_CD_CODE [11:08] */
#define Wr_BRPHY0_ECD_CTRL_EXPC1_PB_CD_CODE(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC1,0xf00,8,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC1_PB_CD_CODE(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC1,0xf00,8)
#define BRPHY0_ECD_CTRL_EXPC1_PB_CD_CODE_MASK                      0x0f00
#define BRPHY0_ECD_CTRL_EXPC1_PB_CD_CODE_ALIGN                     0
#define BRPHY0_ECD_CTRL_EXPC1_PB_CD_CODE_BITS                      4
#define BRPHY0_ECD_CTRL_EXPC1_PB_CD_CODE_SHIFT                     8

/* BRPHY0_ECD_CTRL :: EXPC1 :: PC_CD_CODE [07:04] */
#define Wr_BRPHY0_ECD_CTRL_EXPC1_PC_CD_CODE(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC1,0xf0,4,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC1_PC_CD_CODE(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC1,0xf0,4)
#define BRPHY0_ECD_CTRL_EXPC1_PC_CD_CODE_MASK                      0x00f0
#define BRPHY0_ECD_CTRL_EXPC1_PC_CD_CODE_ALIGN                     0
#define BRPHY0_ECD_CTRL_EXPC1_PC_CD_CODE_BITS                      4
#define BRPHY0_ECD_CTRL_EXPC1_PC_CD_CODE_SHIFT                     4

/* BRPHY0_ECD_CTRL :: EXPC1 :: PD_CD_CODE [03:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC1_PD_CD_CODE(x) WriteRegBits16(BRPHY0_ECD_CTRL_EXPC1,0xf,0,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC1_PD_CD_CODE(x) ReadRegBits16(BRPHY0_ECD_CTRL_EXPC1,0xf,0)
#define BRPHY0_ECD_CTRL_EXPC1_PD_CD_CODE_MASK                      0x000f
#define BRPHY0_ECD_CTRL_EXPC1_PD_CD_CODE_ALIGN                     0
#define BRPHY0_ECD_CTRL_EXPC1_PD_CD_CODE_BITS                      4
#define BRPHY0_ECD_CTRL_EXPC1_PD_CD_CODE_SHIFT                     0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC2
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC2 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) WriteReg16(BRPHY0_ECD_CTRL_EXPC2,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) ReadReg16(BRPHY0_ECD_CTRL_EXPC2)
#define BRPHY0_ECD_CTRL_EXPC2_LENGTH_INDICATION_MASK               0xffff
#define BRPHY0_ECD_CTRL_EXPC2_LENGTH_INDICATION_ALIGN              0
#define BRPHY0_ECD_CTRL_EXPC2_LENGTH_INDICATION_BITS               16
#define BRPHY0_ECD_CTRL_EXPC2_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC3
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC3 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) WriteReg16(BRPHY0_ECD_CTRL_EXPC3,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) ReadReg16(BRPHY0_ECD_CTRL_EXPC3)
#define BRPHY0_ECD_CTRL_EXPC3_LENGTH_INDICATION_MASK               0xffff
#define BRPHY0_ECD_CTRL_EXPC3_LENGTH_INDICATION_ALIGN              0
#define BRPHY0_ECD_CTRL_EXPC3_LENGTH_INDICATION_BITS               16
#define BRPHY0_ECD_CTRL_EXPC3_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC4
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC4 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) WriteReg16(BRPHY0_ECD_CTRL_EXPC4,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) ReadReg16(BRPHY0_ECD_CTRL_EXPC4)
#define BRPHY0_ECD_CTRL_EXPC4_LENGTH_INDICATION_MASK               0xffff
#define BRPHY0_ECD_CTRL_EXPC4_LENGTH_INDICATION_ALIGN              0
#define BRPHY0_ECD_CTRL_EXPC4_LENGTH_INDICATION_BITS               16
#define BRPHY0_ECD_CTRL_EXPC4_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC5
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC5 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) WriteReg16(BRPHY0_ECD_CTRL_EXPC5,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) ReadReg16(BRPHY0_ECD_CTRL_EXPC5)
#define BRPHY0_ECD_CTRL_EXPC5_LENGTH_INDICATION_MASK               0xffff
#define BRPHY0_ECD_CTRL_EXPC5_LENGTH_INDICATION_ALIGN              0
#define BRPHY0_ECD_CTRL_EXPC5_LENGTH_INDICATION_BITS               16
#define BRPHY0_ECD_CTRL_EXPC5_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC6
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC6 :: F_COUNT_0 [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC6_F_COUNT_0(x) WriteReg16(BRPHY0_ECD_CTRL_EXPC6,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC6_F_COUNT_0(x) ReadReg16(BRPHY0_ECD_CTRL_EXPC6)
#define BRPHY0_ECD_CTRL_EXPC6_F_COUNT_0_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPC6_F_COUNT_0_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPC6_F_COUNT_0_BITS                       16
#define BRPHY0_ECD_CTRL_EXPC6_F_COUNT_0_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC7
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC7 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC7_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPC7,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC7_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPC7)
#define BRPHY0_ECD_CTRL_EXPC7_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPC7_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPC7_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPC7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC8
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC8 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC8_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPC8,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC8_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPC8)
#define BRPHY0_ECD_CTRL_EXPC8_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPC8_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPC8_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPC8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPC9
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPC9 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPC9_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPC9,x)
#define Rd_BRPHY0_ECD_CTRL_EXPC9_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPC9)
#define BRPHY0_ECD_CTRL_EXPC9_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPC9_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPC9_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPC9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPCA
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPCA :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPCA_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPCA,x)
#define Rd_BRPHY0_ECD_CTRL_EXPCA_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPCA)
#define BRPHY0_ECD_CTRL_EXPCA_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPCA_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPCA_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPCA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPCB
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPCB :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPCB_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPCB,x)
#define Rd_BRPHY0_ECD_CTRL_EXPCB_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPCB)
#define BRPHY0_ECD_CTRL_EXPCB_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPCB_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPCB_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPCB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPCC
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPCC :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPCC_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPCC,x)
#define Rd_BRPHY0_ECD_CTRL_EXPCC_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPCC)
#define BRPHY0_ECD_CTRL_EXPCC_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPCC_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPCC_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPCC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPCD
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPCD :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPCD_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPCD,x)
#define Rd_BRPHY0_ECD_CTRL_EXPCD_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPCD)
#define BRPHY0_ECD_CTRL_EXPCD_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPCD_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPCD_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPCD_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPCE
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPCE :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPCE_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPCE,x)
#define Rd_BRPHY0_ECD_CTRL_EXPCE_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPCE)
#define BRPHY0_ECD_CTRL_EXPCE_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPCE_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPCE_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPCE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPCF
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPCF :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPCF_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPCF,x)
#define Rd_BRPHY0_ECD_CTRL_EXPCF_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPCF)
#define BRPHY0_ECD_CTRL_EXPCF_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPCF_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPCF_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPCF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE0
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE0 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE0_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE0,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE0_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE0)
#define BRPHY0_ECD_CTRL_EXPE0_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE0_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE0_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE0_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE1
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE1 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE1_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE1,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE1_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE1)
#define BRPHY0_ECD_CTRL_EXPE1_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE1_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE1_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE1_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE2
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE2 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE2_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE2,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE2_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE2)
#define BRPHY0_ECD_CTRL_EXPE2_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE2_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE2_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE2_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE3
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE3 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE3_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE3,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE3_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE3)
#define BRPHY0_ECD_CTRL_EXPE3_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE3_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE3_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE3_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE4
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE4 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE4_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE4,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE4_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE4)
#define BRPHY0_ECD_CTRL_EXPE4_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE4_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE4_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE4_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE5
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE5 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE5_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE5,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE5_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE5)
#define BRPHY0_ECD_CTRL_EXPE5_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE5_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE5_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE5_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE6
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE6 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE6_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE6,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE6_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE6)
#define BRPHY0_ECD_CTRL_EXPE6_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE6_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE6_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE6_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE7
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE7 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE7_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE7,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE7_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE7)
#define BRPHY0_ECD_CTRL_EXPE7_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE7_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE7_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE8
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE8 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE8_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE8,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE8_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE8)
#define BRPHY0_ECD_CTRL_EXPE8_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE8_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE8_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPE9
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPE9 :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPE9_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPE9,x)
#define Rd_BRPHY0_ECD_CTRL_EXPE9_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPE9)
#define BRPHY0_ECD_CTRL_EXPE9_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPE9_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPE9_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPE9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPEA
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPEA :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPEA_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPEA,x)
#define Rd_BRPHY0_ECD_CTRL_EXPEA_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPEA)
#define BRPHY0_ECD_CTRL_EXPEA_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPEA_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPEA_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPEA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPEB
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPEB :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPEB_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPEB,x)
#define Rd_BRPHY0_ECD_CTRL_EXPEB_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPEB)
#define BRPHY0_ECD_CTRL_EXPEB_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPEB_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPEB_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPEB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPEC
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPEC :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPEC_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPEC,x)
#define Rd_BRPHY0_ECD_CTRL_EXPEC_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPEC)
#define BRPHY0_ECD_CTRL_EXPEC_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPEC_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPEC_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPEC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPED
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPED :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPED_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPED,x)
#define Rd_BRPHY0_ECD_CTRL_EXPED_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPED)
#define BRPHY0_ECD_CTRL_EXPED_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPED_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPED_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPED_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPEE
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPEE :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPEE_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPEE,x)
#define Rd_BRPHY0_ECD_CTRL_EXPEE_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPEE)
#define BRPHY0_ECD_CTRL_EXPEE_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPEE_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPEE_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPEE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY0_ECD_CTRL :: EXPEF
 ***************************************************************************/
/* BRPHY0_ECD_CTRL :: EXPEF :: UNDEFINED [15:00] */
#define Wr_BRPHY0_ECD_CTRL_EXPEF_UNDEFINED(x) WriteReg16(BRPHY0_ECD_CTRL_EXPEF,x)
#define Rd_BRPHY0_ECD_CTRL_EXPEF_UNDEFINED(x) ReadReg16(BRPHY0_ECD_CTRL_EXPEF)
#define BRPHY0_ECD_CTRL_EXPEF_UNDEFINED_MASK                       0xffff
#define BRPHY0_ECD_CTRL_EXPEF_UNDEFINED_ALIGN                      0
#define BRPHY0_ECD_CTRL_EXPEF_UNDEFINED_BITS                       16
#define BRPHY0_ECD_CTRL_EXPEF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_BR_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP90
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP90 :: DIG_HPF_EN [15:15] */
#define Wr_BRPHY0_BR_CTRL_EXP90_DIG_HPF_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP90,0x8000,15,x)
#define Rd_BRPHY0_BR_CTRL_EXP90_DIG_HPF_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP90,0x8000,15)
#define BRPHY0_BR_CTRL_EXP90_DIG_HPF_EN_MASK                       0x8000
#define BRPHY0_BR_CTRL_EXP90_DIG_HPF_EN_ALIGN                      0
#define BRPHY0_BR_CTRL_EXP90_DIG_HPF_EN_BITS                       1
#define BRPHY0_BR_CTRL_EXP90_DIG_HPF_EN_SHIFT                      15

/* BRPHY0_BR_CTRL :: EXP90 :: BR_SCR_STATUS [14:13] */
#define Wr_BRPHY0_BR_CTRL_EXP90_BR_SCR_STATUS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP90,0x6000,13,x)
#define Rd_BRPHY0_BR_CTRL_EXP90_BR_SCR_STATUS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP90,0x6000,13)
#define BRPHY0_BR_CTRL_EXP90_BR_SCR_STATUS_MASK                    0x6000
#define BRPHY0_BR_CTRL_EXP90_BR_SCR_STATUS_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP90_BR_SCR_STATUS_BITS                    2
#define BRPHY0_BR_CTRL_EXP90_BR_SCR_STATUS_SHIFT                   13

/* BRPHY0_BR_CTRL :: EXP90 :: BR_ALIGN_STATE [12:10] */
#define Wr_BRPHY0_BR_CTRL_EXP90_BR_ALIGN_STATE(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP90,0x1c00,10,x)
#define Rd_BRPHY0_BR_CTRL_EXP90_BR_ALIGN_STATE(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP90,0x1c00,10)
#define BRPHY0_BR_CTRL_EXP90_BR_ALIGN_STATE_MASK                   0x1c00
#define BRPHY0_BR_CTRL_EXP90_BR_ALIGN_STATE_ALIGN                  0
#define BRPHY0_BR_CTRL_EXP90_BR_ALIGN_STATE_BITS                   3
#define BRPHY0_BR_CTRL_EXP90_BR_ALIGN_STATE_SHIFT                  10

/* BRPHY0_BR_CTRL :: EXP90 :: BR_RX_STATE [09:06] */
#define Wr_BRPHY0_BR_CTRL_EXP90_BR_RX_STATE(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP90,0x3c0,6,x)
#define Rd_BRPHY0_BR_CTRL_EXP90_BR_RX_STATE(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP90,0x3c0,6)
#define BRPHY0_BR_CTRL_EXP90_BR_RX_STATE_MASK                      0x03c0
#define BRPHY0_BR_CTRL_EXP90_BR_RX_STATE_ALIGN                     0
#define BRPHY0_BR_CTRL_EXP90_BR_RX_STATE_BITS                      4
#define BRPHY0_BR_CTRL_EXP90_BR_RX_STATE_SHIFT                     6

/* BRPHY0_BR_CTRL :: EXP90 :: BR_PCS_STATE [05:02] */
#define Wr_BRPHY0_BR_CTRL_EXP90_BR_PCS_STATE(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP90,0x3c,2,x)
#define Rd_BRPHY0_BR_CTRL_EXP90_BR_PCS_STATE(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP90,0x3c,2)
#define BRPHY0_BR_CTRL_EXP90_BR_PCS_STATE_MASK                     0x003c
#define BRPHY0_BR_CTRL_EXP90_BR_PCS_STATE_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP90_BR_PCS_STATE_BITS                     4
#define BRPHY0_BR_CTRL_EXP90_BR_PCS_STATE_SHIFT                    2

/* BRPHY0_BR_CTRL :: EXP90 :: BR_FORCE_LINK_CTL [01:01] */
#define Wr_BRPHY0_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP90,0x2,1,x)
#define Rd_BRPHY0_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP90,0x2,1)
#define BRPHY0_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_MASK                0x0002
#define BRPHY0_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_ALIGN               0
#define BRPHY0_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_BITS                1
#define BRPHY0_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_SHIFT               1

/* BRPHY0_BR_CTRL :: EXP90 :: BR_EN [00:00] */
#define Wr_BRPHY0_BR_CTRL_EXP90_BR_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP90,0x1,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP90_BR_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP90,0x1,0)
#define BRPHY0_BR_CTRL_EXP90_BR_EN_MASK                            0x0001
#define BRPHY0_BR_CTRL_EXP90_BR_EN_ALIGN                           0
#define BRPHY0_BR_CTRL_EXP90_BR_EN_BITS                            1
#define BRPHY0_BR_CTRL_EXP90_BR_EN_SHIFT                           0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP91
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP91 :: DIG_HPF_OV [15:15] */
#define Wr_BRPHY0_BR_CTRL_EXP91_DIG_HPF_OV(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0x8000,15,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_DIG_HPF_OV(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0x8000,15)
#define BRPHY0_BR_CTRL_EXP91_DIG_HPF_OV_MASK                       0x8000
#define BRPHY0_BR_CTRL_EXP91_DIG_HPF_OV_ALIGN                      0
#define BRPHY0_BR_CTRL_EXP91_DIG_HPF_OV_BITS                       1
#define BRPHY0_BR_CTRL_EXP91_DIG_HPF_OV_SHIFT                      15

/* BRPHY0_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV [14:14] */
#define Wr_BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0x4000,14,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0x4000,14)
#define BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_MASK               0x4000
#define BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_ALIGN              0
#define BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_BITS               1
#define BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_SHIFT              14

/* BRPHY0_BR_CTRL :: EXP91 :: INV_LRE_GMII_TXC [13:13] */
#define Wr_BRPHY0_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0x2000,13,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0x2000,13)
#define BRPHY0_BR_CTRL_EXP91_INV_LRE_GMII_TXC_MASK                 0x2000
#define BRPHY0_BR_CTRL_EXP91_INV_LRE_GMII_TXC_ALIGN                0
#define BRPHY0_BR_CTRL_EXP91_INV_LRE_GMII_TXC_BITS                 1
#define BRPHY0_BR_CTRL_EXP91_INV_LRE_GMII_TXC_SHIFT                13

/* BRPHY0_BR_CTRL :: EXP91 :: AGC_AUTOSTAGING_DIS [12:12] */
#define Wr_BRPHY0_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0x1000,12,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0x1000,12)
#define BRPHY0_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_MASK              0x1000
#define BRPHY0_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_ALIGN             0
#define BRPHY0_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_BITS              1
#define BRPHY0_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_SHIFT             12

/* BRPHY0_BR_CTRL :: EXP91 :: BRPGA [11:09] */
#define Wr_BRPHY0_BR_CTRL_EXP91_BRPGA(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0xe00,9,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_BRPGA(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0xe00,9)
#define BRPHY0_BR_CTRL_EXP91_BRPGA_MASK                            0x0e00
#define BRPHY0_BR_CTRL_EXP91_BRPGA_ALIGN                           0
#define BRPHY0_BR_CTRL_EXP91_BRPGA_BITS                            3
#define BRPHY0_BR_CTRL_EXP91_BRPGA_SHIFT                           9

/* BRPHY0_BR_CTRL :: EXP91 :: BRCONFIG [08:04] */
#define Wr_BRPHY0_BR_CTRL_EXP91_BRCONFIG(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0x1f0,4,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_BRCONFIG(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0x1f0,4)
#define BRPHY0_BR_CTRL_EXP91_BRCONFIG_MASK                         0x01f0
#define BRPHY0_BR_CTRL_EXP91_BRCONFIG_ALIGN                        0
#define BRPHY0_BR_CTRL_EXP91_BRCONFIG_BITS                         5
#define BRPHY0_BR_CTRL_EXP91_BRCONFIG_SHIFT                        4

/* BRPHY0_BR_CTRL :: EXP91 :: ACQP_EN_ECO_DIS [03:03] */
#define Wr_BRPHY0_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0x8,3,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0x8,3)
#define BRPHY0_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_MASK                  0x0008
#define BRPHY0_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_ALIGN                 0
#define BRPHY0_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_BITS                  1
#define BRPHY0_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_SHIFT                 3

/* BRPHY0_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV_VAL [02:02] */
#define Wr_BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0x4,2,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0x4,2)
#define BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_MASK           0x0004
#define BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_ALIGN          0
#define BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_BITS           1
#define BRPHY0_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_SHIFT          2

/* BRPHY0_BR_CTRL :: EXP91 :: TXSCR_ZERO_SEED [01:01] */
#define Wr_BRPHY0_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0x2,1,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0x2,1)
#define BRPHY0_BR_CTRL_EXP91_TXSCR_ZERO_SEED_MASK                  0x0002
#define BRPHY0_BR_CTRL_EXP91_TXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY0_BR_CTRL_EXP91_TXSCR_ZERO_SEED_BITS                  1
#define BRPHY0_BR_CTRL_EXP91_TXSCR_ZERO_SEED_SHIFT                 1

/* BRPHY0_BR_CTRL :: EXP91 :: RXSCR_ZERO_SEED [00:00] */
#define Wr_BRPHY0_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP91,0x1,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP91,0x1,0)
#define BRPHY0_BR_CTRL_EXP91_RXSCR_ZERO_SEED_MASK                  0x0001
#define BRPHY0_BR_CTRL_EXP91_RXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY0_BR_CTRL_EXP91_RXSCR_ZERO_SEED_BITS                  1
#define BRPHY0_BR_CTRL_EXP91_RXSCR_ZERO_SEED_SHIFT                 0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP92
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP92 :: DLLCONV_OV_EN [15:15] */
#define Wr_BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x8000,15,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x8000,15)
#define BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_EN_MASK                    0x8000
#define BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_EN_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_EN_BITS                    1
#define BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_EN_SHIFT                   15

/* BRPHY0_BR_CTRL :: EXP92 :: DLLCONV_OV_VAL [14:14] */
#define Wr_BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x4000,14,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x4000,14)
#define BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_VAL_MASK                   0x4000
#define BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_VAL_ALIGN                  0
#define BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_VAL_BITS                   1
#define BRPHY0_BR_CTRL_EXP92_DLLCONV_OV_VAL_SHIFT                  14

/* BRPHY0_BR_CTRL :: EXP92 :: BR_SLAVE_POL_COR_EN [13:13] */
#define Wr_BRPHY0_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x2000,13,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x2000,13)
#define BRPHY0_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_MASK              0x2000
#define BRPHY0_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_ALIGN             0
#define BRPHY0_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_BITS              1
#define BRPHY0_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_SHIFT             13

/* BRPHY0_BR_CTRL :: EXP92 :: BR_EDGE_RATE_SEL [12:11] */
#define Wr_BRPHY0_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x1800,11,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x1800,11)
#define BRPHY0_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_MASK                 0x1800
#define BRPHY0_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_ALIGN                0
#define BRPHY0_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_BITS                 2
#define BRPHY0_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_SHIFT                11

/* BRPHY0_BR_CTRL :: EXP92 :: BR_PCS_RRNOK_POL_EN [10:10] */
#define Wr_BRPHY0_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x400,10,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x400,10)
#define BRPHY0_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_MASK              0x0400
#define BRPHY0_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_ALIGN             0
#define BRPHY0_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_BITS              1
#define BRPHY0_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_SHIFT             10

/* BRPHY0_BR_CTRL :: EXP92 :: LDS_LNK_CHK_ECO_DIS [09:09] */
#define Wr_BRPHY0_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x200,9,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x200,9)
#define BRPHY0_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_MASK              0x0200
#define BRPHY0_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_ALIGN             0
#define BRPHY0_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_BITS              1
#define BRPHY0_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_SHIFT             9

/* BRPHY0_BR_CTRL :: EXP92 :: BR_PCS_POL_EN [08:08] */
#define Wr_BRPHY0_BR_CTRL_EXP92_BR_PCS_POL_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x100,8,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_BR_PCS_POL_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x100,8)
#define BRPHY0_BR_CTRL_EXP92_BR_PCS_POL_EN_MASK                    0x0100
#define BRPHY0_BR_CTRL_EXP92_BR_PCS_POL_EN_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP92_BR_PCS_POL_EN_BITS                    1
#define BRPHY0_BR_CTRL_EXP92_BR_PCS_POL_EN_SHIFT                   8

/* BRPHY0_BR_CTRL :: EXP92 :: JAB_MON_DIS [07:07] */
#define Wr_BRPHY0_BR_CTRL_EXP92_JAB_MON_DIS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x80,7,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_JAB_MON_DIS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x80,7)
#define BRPHY0_BR_CTRL_EXP92_JAB_MON_DIS_MASK                      0x0080
#define BRPHY0_BR_CTRL_EXP92_JAB_MON_DIS_ALIGN                     0
#define BRPHY0_BR_CTRL_EXP92_JAB_MON_DIS_BITS                      1
#define BRPHY0_BR_CTRL_EXP92_JAB_MON_DIS_SHIFT                     7

/* BRPHY0_BR_CTRL :: EXP92 :: BR_AGCSID_TMR_EN [06:06] */
#define Wr_BRPHY0_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x40,6,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x40,6)
#define BRPHY0_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_MASK                 0x0040
#define BRPHY0_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_ALIGN                0
#define BRPHY0_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_BITS                 1
#define BRPHY0_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_SHIFT                6

/* BRPHY0_BR_CTRL :: EXP92 :: BR_SYM_XSCR_EN [05:05] */
#define Wr_BRPHY0_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x20,5,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x20,5)
#define BRPHY0_BR_CTRL_EXP92_BR_SYM_XSCR_EN_MASK                   0x0020
#define BRPHY0_BR_CTRL_EXP92_BR_SYM_XSCR_EN_ALIGN                  0
#define BRPHY0_BR_CTRL_EXP92_BR_SYM_XSCR_EN_BITS                   1
#define BRPHY0_BR_CTRL_EXP92_BR_SYM_XSCR_EN_SHIFT                  5

/* BRPHY0_BR_CTRL :: EXP92 :: CHK_DELIMITER [04:04] */
#define Wr_BRPHY0_BR_CTRL_EXP92_CHK_DELIMITER(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x10,4,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_CHK_DELIMITER(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x10,4)
#define BRPHY0_BR_CTRL_EXP92_CHK_DELIMITER_MASK                    0x0010
#define BRPHY0_BR_CTRL_EXP92_CHK_DELIMITER_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP92_CHK_DELIMITER_BITS                    1
#define BRPHY0_BR_CTRL_EXP92_CHK_DELIMITER_SHIFT                   4

/* BRPHY0_BR_CTRL :: EXP92 :: TX_READ_DLY [03:02] */
#define Wr_BRPHY0_BR_CTRL_EXP92_TX_READ_DLY(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0xc,2,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_TX_READ_DLY(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0xc,2)
#define BRPHY0_BR_CTRL_EXP92_TX_READ_DLY_MASK                      0x000c
#define BRPHY0_BR_CTRL_EXP92_TX_READ_DLY_ALIGN                     0
#define BRPHY0_BR_CTRL_EXP92_TX_READ_DLY_BITS                      2
#define BRPHY0_BR_CTRL_EXP92_TX_READ_DLY_SHIFT                     2

/* BRPHY0_BR_CTRL :: EXP92 :: RX_READ_DLY [01:00] */
#define Wr_BRPHY0_BR_CTRL_EXP92_RX_READ_DLY(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP92,0x3,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP92_RX_READ_DLY(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP92,0x3,0)
#define BRPHY0_BR_CTRL_EXP92_RX_READ_DLY_MASK                      0x0003
#define BRPHY0_BR_CTRL_EXP92_RX_READ_DLY_ALIGN                     0
#define BRPHY0_BR_CTRL_EXP92_RX_READ_DLY_BITS                      2
#define BRPHY0_BR_CTRL_EXP92_RX_READ_DLY_SHIFT                     0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP93
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP93 :: LDS_CAP_DOWNGRADE_DIS [15:15] */
#define Wr_BRPHY0_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP93,0x8000,15,x)
#define Rd_BRPHY0_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP93,0x8000,15)
#define BRPHY0_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_MASK            0x8000
#define BRPHY0_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_ALIGN           0
#define BRPHY0_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_BITS            1
#define BRPHY0_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_SHIFT           15

/* BRPHY0_BR_CTRL :: EXP93 :: LDS_REORDER_DIS [14:14] */
#define Wr_BRPHY0_BR_CTRL_EXP93_LDS_REORDER_DIS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP93,0x4000,14,x)
#define Rd_BRPHY0_BR_CTRL_EXP93_LDS_REORDER_DIS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP93,0x4000,14)
#define BRPHY0_BR_CTRL_EXP93_LDS_REORDER_DIS_MASK                  0x4000
#define BRPHY0_BR_CTRL_EXP93_LDS_REORDER_DIS_ALIGN                 0
#define BRPHY0_BR_CTRL_EXP93_LDS_REORDER_DIS_BITS                  1
#define BRPHY0_BR_CTRL_EXP93_LDS_REORDER_DIS_SHIFT                 14

/* BRPHY0_BR_CTRL :: EXP93 :: LDS_SIM [13:13] */
#define Wr_BRPHY0_BR_CTRL_EXP93_LDS_SIM(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP93,0x2000,13,x)
#define Rd_BRPHY0_BR_CTRL_EXP93_LDS_SIM(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP93,0x2000,13)
#define BRPHY0_BR_CTRL_EXP93_LDS_SIM_MASK                          0x2000
#define BRPHY0_BR_CTRL_EXP93_LDS_SIM_ALIGN                         0
#define BRPHY0_BR_CTRL_EXP93_LDS_SIM_BITS                          1
#define BRPHY0_BR_CTRL_EXP93_LDS_SIM_SHIFT                         13

/* BRPHY0_BR_CTRL :: EXP93 :: LDS_SCR_ON [12:12] */
#define Wr_BRPHY0_BR_CTRL_EXP93_LDS_SCR_ON(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP93,0x1000,12,x)
#define Rd_BRPHY0_BR_CTRL_EXP93_LDS_SCR_ON(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP93,0x1000,12)
#define BRPHY0_BR_CTRL_EXP93_LDS_SCR_ON_MASK                       0x1000
#define BRPHY0_BR_CTRL_EXP93_LDS_SCR_ON_ALIGN                      0
#define BRPHY0_BR_CTRL_EXP93_LDS_SCR_ON_BITS                       1
#define BRPHY0_BR_CTRL_EXP93_LDS_SCR_ON_SHIFT                      12

/* BRPHY0_BR_CTRL :: EXP93 :: LDS_PHASE_BYP [11:11] */
#define Wr_BRPHY0_BR_CTRL_EXP93_LDS_PHASE_BYP(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP93,0x800,11,x)
#define Rd_BRPHY0_BR_CTRL_EXP93_LDS_PHASE_BYP(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP93,0x800,11)
#define BRPHY0_BR_CTRL_EXP93_LDS_PHASE_BYP_MASK                    0x0800
#define BRPHY0_BR_CTRL_EXP93_LDS_PHASE_BYP_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP93_LDS_PHASE_BYP_BITS                    1
#define BRPHY0_BR_CTRL_EXP93_LDS_PHASE_BYP_SHIFT                   11

/* BRPHY0_BR_CTRL :: EXP93 :: LDS_PHASE_INIT [10:08] */
#define Wr_BRPHY0_BR_CTRL_EXP93_LDS_PHASE_INIT(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP93,0x700,8,x)
#define Rd_BRPHY0_BR_CTRL_EXP93_LDS_PHASE_INIT(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP93,0x700,8)
#define BRPHY0_BR_CTRL_EXP93_LDS_PHASE_INIT_MASK                   0x0700
#define BRPHY0_BR_CTRL_EXP93_LDS_PHASE_INIT_ALIGN                  0
#define BRPHY0_BR_CTRL_EXP93_LDS_PHASE_INIT_BITS                   3
#define BRPHY0_BR_CTRL_EXP93_LDS_PHASE_INIT_SHIFT                  8

/* BRPHY0_BR_CTRL :: EXP93 :: LDS_PEAK_THR [07:00] */
#define Wr_BRPHY0_BR_CTRL_EXP93_LDS_PEAK_THR(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP93,0xff,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP93_LDS_PEAK_THR(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP93,0xff,0)
#define BRPHY0_BR_CTRL_EXP93_LDS_PEAK_THR_MASK                     0x00ff
#define BRPHY0_BR_CTRL_EXP93_LDS_PEAK_THR_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP93_LDS_PEAK_THR_BITS                     8
#define BRPHY0_BR_CTRL_EXP93_LDS_PEAK_THR_SHIFT                    0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP94
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP94 :: LDS_LEN_THR1 [15:08] */
#define Wr_BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR1(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP94,0xff00,8,x)
#define Rd_BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR1(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP94,0xff00,8)
#define BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR1_MASK                     0xff00
#define BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR1_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR1_BITS                     8
#define BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR1_SHIFT                    8

/* BRPHY0_BR_CTRL :: EXP94 :: LDS_LEN_THR0 [07:00] */
#define Wr_BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR0(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP94,0xff,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR0(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP94,0xff,0)
#define BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR0_MASK                     0x00ff
#define BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR0_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR0_BITS                     8
#define BRPHY0_BR_CTRL_EXP94_LDS_LEN_THR0_SHIFT                    0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP95
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP95 :: LDS_LEN_THR3 [15:08] */
#define Wr_BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR3(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP95,0xff00,8,x)
#define Rd_BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR3(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP95,0xff00,8)
#define BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR3_MASK                     0xff00
#define BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR3_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR3_BITS                     8
#define BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR3_SHIFT                    8

/* BRPHY0_BR_CTRL :: EXP95 :: LDS_LEN_THR2 [07:00] */
#define Wr_BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR2(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP95,0xff,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR2(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP95,0xff,0)
#define BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR2_MASK                     0x00ff
#define BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR2_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR2_BITS                     8
#define BRPHY0_BR_CTRL_EXP95_LDS_LEN_THR2_SHIFT                    0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP96
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP96 :: LDS_TONE_FREQ [15:15] */
#define Wr_BRPHY0_BR_CTRL_EXP96_LDS_TONE_FREQ(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP96,0x8000,15,x)
#define Rd_BRPHY0_BR_CTRL_EXP96_LDS_TONE_FREQ(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP96,0x8000,15)
#define BRPHY0_BR_CTRL_EXP96_LDS_TONE_FREQ_MASK                    0x8000
#define BRPHY0_BR_CTRL_EXP96_LDS_TONE_FREQ_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP96_LDS_TONE_FREQ_BITS                    1
#define BRPHY0_BR_CTRL_EXP96_LDS_TONE_FREQ_SHIFT                   15

/* BRPHY0_BR_CTRL :: EXP96 :: LDS_EXT_AB_DWNGRD [14:14] */
#define Wr_BRPHY0_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP96,0x4000,14,x)
#define Rd_BRPHY0_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP96,0x4000,14)
#define BRPHY0_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_MASK                0x4000
#define BRPHY0_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_ALIGN               0
#define BRPHY0_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_BITS                1
#define BRPHY0_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_SHIFT               14

/* BRPHY0_BR_CTRL :: EXP96 :: LDS_SCAN_FSM [13:12] */
#define Wr_BRPHY0_BR_CTRL_EXP96_LDS_SCAN_FSM(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP96,0x3000,12,x)
#define Rd_BRPHY0_BR_CTRL_EXP96_LDS_SCAN_FSM(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP96,0x3000,12)
#define BRPHY0_BR_CTRL_EXP96_LDS_SCAN_FSM_MASK                     0x3000
#define BRPHY0_BR_CTRL_EXP96_LDS_SCAN_FSM_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP96_LDS_SCAN_FSM_BITS                     2
#define BRPHY0_BR_CTRL_EXP96_LDS_SCAN_FSM_SHIFT                    12

/* BRPHY0_BR_CTRL :: EXP96 :: CUR_LOC_FNUM [11:04] */
#define Wr_BRPHY0_BR_CTRL_EXP96_CUR_LOC_FNUM(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP96,0xff0,4,x)
#define Rd_BRPHY0_BR_CTRL_EXP96_CUR_LOC_FNUM(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP96,0xff0,4)
#define BRPHY0_BR_CTRL_EXP96_CUR_LOC_FNUM_MASK                     0x0ff0
#define BRPHY0_BR_CTRL_EXP96_CUR_LOC_FNUM_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP96_CUR_LOC_FNUM_BITS                     8
#define BRPHY0_BR_CTRL_EXP96_CUR_LOC_FNUM_SHIFT                    4

/* BRPHY0_BR_CTRL :: EXP96 :: LDS_SPD [03:00] */
#define Wr_BRPHY0_BR_CTRL_EXP96_LDS_SPD(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP96,0xf,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP96_LDS_SPD(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP96,0xf,0)
#define BRPHY0_BR_CTRL_EXP96_LDS_SPD_MASK                          0x000f
#define BRPHY0_BR_CTRL_EXP96_LDS_SPD_ALIGN                         0
#define BRPHY0_BR_CTRL_EXP96_LDS_SPD_BITS                          4
#define BRPHY0_BR_CTRL_EXP96_LDS_SPD_SHIFT                         0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP97
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP97 :: LDS_TX_FSM_H [15:12] */
#define Wr_BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_H(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP97,0xf000,12,x)
#define Rd_BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_H(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP97,0xf000,12)
#define BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_H_MASK                     0xf000
#define BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_H_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_H_BITS                     4
#define BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_H_SHIFT                    12

/* BRPHY0_BR_CTRL :: EXP97 :: LDS_TX_FSM_L [11:08] */
#define Wr_BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_L(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP97,0xf00,8,x)
#define Rd_BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_L(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP97,0xf00,8)
#define BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_L_MASK                     0x0f00
#define BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_L_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_L_BITS                     4
#define BRPHY0_BR_CTRL_EXP97_LDS_TX_FSM_L_SHIFT                    8

/* BRPHY0_BR_CTRL :: EXP97 :: LDS_ARB_FSM_H [07:04] */
#define Wr_BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP97,0xf0,4,x)
#define Rd_BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP97,0xf0,4)
#define BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_H_MASK                    0x00f0
#define BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_H_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_H_BITS                    4
#define BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_H_SHIFT                   4

/* BRPHY0_BR_CTRL :: EXP97 :: LDS_ARB_FSM_L [03:00] */
#define Wr_BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP97,0xf,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP97,0xf,0)
#define BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_L_MASK                    0x000f
#define BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_L_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_L_BITS                    4
#define BRPHY0_BR_CTRL_EXP97_LDS_ARB_FSM_L_SHIFT                   0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP99
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP99 :: LDS_PGACTRL [15:10] */
#define Wr_BRPHY0_BR_CTRL_EXP99_LDS_PGACTRL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP99,0xfc00,10,x)
#define Rd_BRPHY0_BR_CTRL_EXP99_LDS_PGACTRL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP99,0xfc00,10)
#define BRPHY0_BR_CTRL_EXP99_LDS_PGACTRL_MASK                      0xfc00
#define BRPHY0_BR_CTRL_EXP99_LDS_PGACTRL_ALIGN                     0
#define BRPHY0_BR_CTRL_EXP99_LDS_PGACTRL_BITS                      6
#define BRPHY0_BR_CTRL_EXP99_LDS_PGACTRL_SHIFT                     10

/* BRPHY0_BR_CTRL :: EXP99 :: TXDIS_TMR_OPT [09:07] */
#define Wr_BRPHY0_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP99,0x380,7,x)
#define Rd_BRPHY0_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP99,0x380,7)
#define BRPHY0_BR_CTRL_EXP99_TXDIS_TMR_OPT_MASK                    0x0380
#define BRPHY0_BR_CTRL_EXP99_TXDIS_TMR_OPT_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP99_TXDIS_TMR_OPT_BITS                    3
#define BRPHY0_BR_CTRL_EXP99_TXDIS_TMR_OPT_SHIFT                   7

/* BRPHY0_BR_CTRL :: EXP99 :: LNK_TMR_OPT [06:04] */
#define Wr_BRPHY0_BR_CTRL_EXP99_LNK_TMR_OPT(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP99,0x70,4,x)
#define Rd_BRPHY0_BR_CTRL_EXP99_LNK_TMR_OPT(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP99,0x70,4)
#define BRPHY0_BR_CTRL_EXP99_LNK_TMR_OPT_MASK                      0x0070
#define BRPHY0_BR_CTRL_EXP99_LNK_TMR_OPT_ALIGN                     0
#define BRPHY0_BR_CTRL_EXP99_LNK_TMR_OPT_BITS                      3
#define BRPHY0_BR_CTRL_EXP99_LNK_TMR_OPT_SHIFT                     4

/* BRPHY0_BR_CTRL :: EXP99 :: BST_TMR_OPT [03:01] */
#define Wr_BRPHY0_BR_CTRL_EXP99_BST_TMR_OPT(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP99,0xe,1,x)
#define Rd_BRPHY0_BR_CTRL_EXP99_BST_TMR_OPT(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP99,0xe,1)
#define BRPHY0_BR_CTRL_EXP99_BST_TMR_OPT_MASK                      0x000e
#define BRPHY0_BR_CTRL_EXP99_BST_TMR_OPT_ALIGN                     0
#define BRPHY0_BR_CTRL_EXP99_BST_TMR_OPT_BITS                      3
#define BRPHY0_BR_CTRL_EXP99_BST_TMR_OPT_SHIFT                     1

/* BRPHY0_BR_CTRL :: EXP99 :: FASTBST [00:00] */
#define Wr_BRPHY0_BR_CTRL_EXP99_FASTBST(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP99,0x1,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP99_FASTBST(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP99,0x1,0)
#define BRPHY0_BR_CTRL_EXP99_FASTBST_MASK                          0x0001
#define BRPHY0_BR_CTRL_EXP99_FASTBST_ALIGN                         0
#define BRPHY0_BR_CTRL_EXP99_FASTBST_BITS                          1
#define BRPHY0_BR_CTRL_EXP99_FASTBST_SHIFT                         0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP9A
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP9A :: LRE_REG_OV_EN [15:15] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x8000,15,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x8000,15)
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_EN_MASK                    0x8000
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_EN_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_EN_BITS                    1
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_EN_SHIFT                   15

/* BRPHY0_BR_CTRL :: EXP9A :: LRE_REG_OV_VAL [14:14] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x4000,14,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x4000,14)
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_VAL_MASK                   0x4000
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_VAL_ALIGN                  0
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_VAL_BITS                   1
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_OV_VAL_SHIFT                  14

/* BRPHY0_BR_CTRL :: EXP9A :: LRE_REG_ACCESS_STAT [13:13] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x2000,13,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x2000,13)
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_MASK              0x2000
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_ALIGN             0
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_BITS              1
#define BRPHY0_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_SHIFT             13

/* BRPHY0_BR_CTRL :: EXP9A :: LDS_LINK_CHK_EN [12:12] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x1000,12,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x1000,12)
#define BRPHY0_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_MASK                  0x1000
#define BRPHY0_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_ALIGN                 0
#define BRPHY0_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_BITS                  1
#define BRPHY0_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_SHIFT                 12

/* BRPHY0_BR_CTRL :: EXP9A :: BR_AGC_TAR_OV_EN [11:11] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x800,11,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x800,11)
#define BRPHY0_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_MASK                 0x0800
#define BRPHY0_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_ALIGN                0
#define BRPHY0_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_BITS                 1
#define BRPHY0_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_SHIFT                11

/* BRPHY0_BR_CTRL :: EXP9A :: LDS_TIMER_OV_EN [10:10] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x400,10,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x400,10)
#define BRPHY0_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_MASK                  0x0400
#define BRPHY0_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_ALIGN                 0
#define BRPHY0_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_BITS                  1
#define BRPHY0_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_SHIFT                 10

/* BRPHY0_BR_CTRL :: EXP9A :: BR_LOST_TOKEN_FIX [09:09] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x200,9,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x200,9)
#define BRPHY0_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_MASK                0x0200
#define BRPHY0_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_ALIGN               0
#define BRPHY0_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_BITS                1
#define BRPHY0_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_SHIFT               9

/* BRPHY0_BR_CTRL :: EXP9A :: DLLCONV_EN_MSTR [08:08] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x100,8,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x100,8)
#define BRPHY0_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_MASK                  0x0100
#define BRPHY0_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_ALIGN                 0
#define BRPHY0_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_BITS                  1
#define BRPHY0_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_SHIFT                 8

/* BRPHY0_BR_CTRL :: EXP9A :: BR_10M1P_HALFOUT_EN [07:07] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x80,7,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x80,7)
#define BRPHY0_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_MASK              0x0080
#define BRPHY0_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_ALIGN             0
#define BRPHY0_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_BITS              1
#define BRPHY0_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_SHIFT             7

/* BRPHY0_BR_CTRL :: EXP9A :: BR_10M2P_HALFOUT_EN [06:06] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x40,6,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x40,6)
#define BRPHY0_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_MASK              0x0040
#define BRPHY0_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_ALIGN             0
#define BRPHY0_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_BITS              1
#define BRPHY0_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_SHIFT             6

/* BRPHY0_BR_CTRL :: EXP9A :: BR_HALFOUT_EN [05:05] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x20,5,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x20,5)
#define BRPHY0_BR_CTRL_EXP9A_BR_HALFOUT_EN_MASK                    0x0020
#define BRPHY0_BR_CTRL_EXP9A_BR_HALFOUT_EN_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP9A_BR_HALFOUT_EN_BITS                    1
#define BRPHY0_BR_CTRL_EXP9A_BR_HALFOUT_EN_SHIFT                   5

/* BRPHY0_BR_CTRL :: EXP9A :: CLK100T_ECO_DIS [04:04] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0x10,4,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0x10,4)
#define BRPHY0_BR_CTRL_EXP9A_CLK100T_ECO_DIS_MASK                  0x0010
#define BRPHY0_BR_CTRL_EXP9A_CLK100T_ECO_DIS_ALIGN                 0
#define BRPHY0_BR_CTRL_EXP9A_CLK100T_ECO_DIS_BITS                  1
#define BRPHY0_BR_CTRL_EXP9A_CLK100T_ECO_DIS_SHIFT                 4

/* BRPHY0_BR_CTRL :: EXP9A :: CH_STATUS [03:00] */
#define Wr_BRPHY0_BR_CTRL_EXP9A_CH_STATUS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9A,0xf,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP9A_CH_STATUS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9A,0xf,0)
#define BRPHY0_BR_CTRL_EXP9A_CH_STATUS_MASK                        0x000f
#define BRPHY0_BR_CTRL_EXP9A_CH_STATUS_ALIGN                       0
#define BRPHY0_BR_CTRL_EXP9A_CH_STATUS_BITS                        4
#define BRPHY0_BR_CTRL_EXP9A_CH_STATUS_SHIFT                       0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP9B
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP9B :: BR_RATE_OV [15:13] */
#define Wr_BRPHY0_BR_CTRL_EXP9B_BR_RATE_OV(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9B,0xe000,13,x)
#define Rd_BRPHY0_BR_CTRL_EXP9B_BR_RATE_OV(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9B,0xe000,13)
#define BRPHY0_BR_CTRL_EXP9B_BR_RATE_OV_MASK                       0xe000
#define BRPHY0_BR_CTRL_EXP9B_BR_RATE_OV_ALIGN                      0
#define BRPHY0_BR_CTRL_EXP9B_BR_RATE_OV_BITS                       3
#define BRPHY0_BR_CTRL_EXP9B_BR_RATE_OV_SHIFT                      13

/* BRPHY0_BR_CTRL :: EXP9B :: BR_200MBPS_CLK_EN [12:12] */
#define Wr_BRPHY0_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9B,0x1000,12,x)
#define Rd_BRPHY0_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9B,0x1000,12)
#define BRPHY0_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_MASK                0x1000
#define BRPHY0_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_ALIGN               0
#define BRPHY0_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_BITS                1
#define BRPHY0_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_SHIFT               12

/* BRPHY0_BR_CTRL :: EXP9B :: BR_TXCLK_EN [11:11] */
#define Wr_BRPHY0_BR_CTRL_EXP9B_BR_TXCLK_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9B,0x800,11,x)
#define Rd_BRPHY0_BR_CTRL_EXP9B_BR_TXCLK_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9B,0x800,11)
#define BRPHY0_BR_CTRL_EXP9B_BR_TXCLK_EN_MASK                      0x0800
#define BRPHY0_BR_CTRL_EXP9B_BR_TXCLK_EN_ALIGN                     0
#define BRPHY0_BR_CTRL_EXP9B_BR_TXCLK_EN_BITS                      1
#define BRPHY0_BR_CTRL_EXP9B_BR_TXCLK_EN_SHIFT                     11

/* BRPHY0_BR_CTRL :: EXP9B :: BR_TXRXICLK_EN [10:10] */
#define Wr_BRPHY0_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9B,0x400,10,x)
#define Rd_BRPHY0_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9B,0x400,10)
#define BRPHY0_BR_CTRL_EXP9B_BR_TXRXICLK_EN_MASK                   0x0400
#define BRPHY0_BR_CTRL_EXP9B_BR_TXRXICLK_EN_ALIGN                  0
#define BRPHY0_BR_CTRL_EXP9B_BR_TXRXICLK_EN_BITS                   1
#define BRPHY0_BR_CTRL_EXP9B_BR_TXRXICLK_EN_SHIFT                  10

/* BRPHY0_BR_CTRL :: EXP9B :: CLK_1G_DIV20 [09:09] */
#define Wr_BRPHY0_BR_CTRL_EXP9B_CLK_1G_DIV20(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9B,0x200,9,x)
#define Rd_BRPHY0_BR_CTRL_EXP9B_CLK_1G_DIV20(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9B,0x200,9)
#define BRPHY0_BR_CTRL_EXP9B_CLK_1G_DIV20_MASK                     0x0200
#define BRPHY0_BR_CTRL_EXP9B_CLK_1G_DIV20_ALIGN                    0
#define BRPHY0_BR_CTRL_EXP9B_CLK_1G_DIV20_BITS                     1
#define BRPHY0_BR_CTRL_EXP9B_CLK_1G_DIV20_SHIFT                    9

/* BRPHY0_BR_CTRL :: EXP9B :: LVL1_PROG_FREQ_DIV [08:05] */
#define Wr_BRPHY0_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9B,0x1e0,5,x)
#define Rd_BRPHY0_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9B,0x1e0,5)
#define BRPHY0_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_MASK               0x01e0
#define BRPHY0_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_ALIGN              0
#define BRPHY0_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_BITS               4
#define BRPHY0_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_SHIFT              5

/* BRPHY0_BR_CTRL :: EXP9B :: LVL2_PROG_FREQ_DIV [04:01] */
#define Wr_BRPHY0_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9B,0x1e,1,x)
#define Rd_BRPHY0_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9B,0x1e,1)
#define BRPHY0_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_MASK               0x001e
#define BRPHY0_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_ALIGN              0
#define BRPHY0_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_BITS               4
#define BRPHY0_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_SHIFT              1

/* BRPHY0_BR_CTRL :: EXP9B :: BR_PLL_CTL_EN [00:00] */
#define Wr_BRPHY0_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9B,0x1,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9B,0x1,0)
#define BRPHY0_BR_CTRL_EXP9B_BR_PLL_CTL_EN_MASK                    0x0001
#define BRPHY0_BR_CTRL_EXP9B_BR_PLL_CTL_EN_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP9B_BR_PLL_CTL_EN_BITS                    1
#define BRPHY0_BR_CTRL_EXP9B_BR_PLL_CTL_EN_SHIFT                   0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP9D
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP9D :: BR_IPR_BYPASS [15:15] */
#define Wr_BRPHY0_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9D,0x8000,15,x)
#define Rd_BRPHY0_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9D,0x8000,15)
#define BRPHY0_BR_CTRL_EXP9D_BR_IPR_BYPASS_MASK                    0x8000
#define BRPHY0_BR_CTRL_EXP9D_BR_IPR_BYPASS_ALIGN                   0
#define BRPHY0_BR_CTRL_EXP9D_BR_IPR_BYPASS_BITS                    1
#define BRPHY0_BR_CTRL_EXP9D_BR_IPR_BYPASS_SHIFT                   15

/* BRPHY0_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_VAL [14:14] */
#define Wr_BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9D,0x4000,14,x)
#define Rd_BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9D,0x4000,14)
#define BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_MASK               0x4000
#define BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_ALIGN              0
#define BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_BITS               1
#define BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_SHIFT              14

/* BRPHY0_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_EN [13:13] */
#define Wr_BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9D,0x2000,13,x)
#define Rd_BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9D,0x2000,13)
#define BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_MASK                0x2000
#define BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_ALIGN               0
#define BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_BITS                1
#define BRPHY0_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_SHIFT               13

/* BRPHY0_BR_CTRL :: EXP9D :: LDS_SD_THR [12:08] */
#define Wr_BRPHY0_BR_CTRL_EXP9D_LDS_SD_THR(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9D,0x1f00,8,x)
#define Rd_BRPHY0_BR_CTRL_EXP9D_LDS_SD_THR(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9D,0x1f00,8)
#define BRPHY0_BR_CTRL_EXP9D_LDS_SD_THR_MASK                       0x1f00
#define BRPHY0_BR_CTRL_EXP9D_LDS_SD_THR_ALIGN                      0
#define BRPHY0_BR_CTRL_EXP9D_LDS_SD_THR_BITS                       5
#define BRPHY0_BR_CTRL_EXP9D_LDS_SD_THR_SHIFT                      8

/* BRPHY0_BR_CTRL :: EXP9D :: LDS_PEAK_THR_T125 [07:00] */
#define Wr_BRPHY0_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9D,0xff,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9D,0xff,0)
#define BRPHY0_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_MASK                0x00ff
#define BRPHY0_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_ALIGN               0
#define BRPHY0_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_BITS                8
#define BRPHY0_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_SHIFT               0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP9E
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP9E :: LDS_LEN_THR1_T125 [15:08] */
#define Wr_BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9E,0xff00,8,x)
#define Rd_BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9E,0xff00,8)
#define BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_MASK                0xff00
#define BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_ALIGN               0
#define BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_BITS                8
#define BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_SHIFT               8

/* BRPHY0_BR_CTRL :: EXP9E :: LDS_LEN_THR0_T125 [07:00] */
#define Wr_BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9E,0xff,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9E,0xff,0)
#define BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_MASK                0x00ff
#define BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_ALIGN               0
#define BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_BITS                8
#define BRPHY0_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_SHIFT               0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXP9F
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXP9F :: LDS_LEN_THR3_T125 [15:08] */
#define Wr_BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9F,0xff00,8,x)
#define Rd_BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9F,0xff00,8)
#define BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_MASK                0xff00
#define BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_ALIGN               0
#define BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_BITS                8
#define BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_SHIFT               8

/* BRPHY0_BR_CTRL :: EXP9F :: LDS_LEN_THR2_T125 [07:00] */
#define Wr_BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) WriteRegBits16(BRPHY0_BR_CTRL_EXP9F,0xff,0,x)
#define Rd_BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) ReadRegBits16(BRPHY0_BR_CTRL_EXP9F,0xff,0)
#define BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_MASK                0x00ff
#define BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_ALIGN               0
#define BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_BITS                8
#define BRPHY0_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_SHIFT               0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXPA0
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXPA0 :: EPAGE_SPARE [15:02] */
#define Wr_BRPHY0_BR_CTRL_EXPA0_EPAGE_SPARE(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA0,0xfffc,2,x)
#define Rd_BRPHY0_BR_CTRL_EXPA0_EPAGE_SPARE(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA0,0xfffc,2)
#define BRPHY0_BR_CTRL_EXPA0_EPAGE_SPARE_MASK                      0xfffc
#define BRPHY0_BR_CTRL_EXPA0_EPAGE_SPARE_ALIGN                     0
#define BRPHY0_BR_CTRL_EXPA0_EPAGE_SPARE_BITS                      14
#define BRPHY0_BR_CTRL_EXPA0_EPAGE_SPARE_SHIFT                     2

/* BRPHY0_BR_CTRL :: EXPA0 :: PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY0_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA0,0x2,1,x)
#define Rd_BRPHY0_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA0,0x2,1)
#define BRPHY0_BR_CTRL_EXPA0_PAIR_1_250MBPS_MASK                   0x0002
#define BRPHY0_BR_CTRL_EXPA0_PAIR_1_250MBPS_ALIGN                  0
#define BRPHY0_BR_CTRL_EXPA0_PAIR_1_250MBPS_BITS                   1
#define BRPHY0_BR_CTRL_EXPA0_PAIR_1_250MBPS_SHIFT                  1

/* BRPHY0_BR_CTRL :: EXPA0 :: PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY0_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA0,0x1,0,x)
#define Rd_BRPHY0_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA0,0x1,0)
#define BRPHY0_BR_CTRL_EXPA0_PAIR_1_200MBPS_MASK                   0x0001
#define BRPHY0_BR_CTRL_EXPA0_PAIR_1_200MBPS_ALIGN                  0
#define BRPHY0_BR_CTRL_EXPA0_PAIR_1_200MBPS_BITS                   1
#define BRPHY0_BR_CTRL_EXPA0_PAIR_1_200MBPS_SHIFT                  0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXPA1
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXPA1 :: LP_EPAGE_SPARE [15:02] */
#define Wr_BRPHY0_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA1,0xfffc,2,x)
#define Rd_BRPHY0_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA1,0xfffc,2)
#define BRPHY0_BR_CTRL_EXPA1_LP_EPAGE_SPARE_MASK                   0xfffc
#define BRPHY0_BR_CTRL_EXPA1_LP_EPAGE_SPARE_ALIGN                  0
#define BRPHY0_BR_CTRL_EXPA1_LP_EPAGE_SPARE_BITS                   14
#define BRPHY0_BR_CTRL_EXPA1_LP_EPAGE_SPARE_SHIFT                  2

/* BRPHY0_BR_CTRL :: EXPA1 :: LP_PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA1,0x2,1,x)
#define Rd_BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA1,0x2,1)
#define BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_MASK                0x0002
#define BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_ALIGN               0
#define BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_BITS                1
#define BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_SHIFT               1

/* BRPHY0_BR_CTRL :: EXPA1 :: LP_PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA1,0x1,0,x)
#define Rd_BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA1,0x1,0)
#define BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_MASK                0x0001
#define BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_ALIGN               0
#define BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_BITS                1
#define BRPHY0_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_SHIFT               0


/****************************************************************************
 * BRPHY0_BR_CTRL :: EXPA2
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV_EN [15:15] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0x8000,15,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0x8000,15)
#define BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_MASK                  0x8000
#define BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_ALIGN                 0
#define BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_BITS                  1
#define BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_SHIFT                 15

/* BRPHY0_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV [14:14] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0x4000,14,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0x4000,14)
#define BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_MASK                     0x4000
#define BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_ALIGN                    0
#define BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_BITS                     1
#define BRPHY0_BR_CTRL_EXPA2_TFREQ_SEL_OV_SHIFT                    14

/* BRPHY0_BR_CTRL :: EXPA2 :: LOW_FREQ_TONE [13:13] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0x2000,13,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0x2000,13)
#define BRPHY0_BR_CTRL_EXPA2_LOW_FREQ_TONE_MASK                    0x2000
#define BRPHY0_BR_CTRL_EXPA2_LOW_FREQ_TONE_ALIGN                   0
#define BRPHY0_BR_CTRL_EXPA2_LOW_FREQ_TONE_BITS                    1
#define BRPHY0_BR_CTRL_EXPA2_LOW_FREQ_TONE_SHIFT                   13

/* BRPHY0_BR_CTRL :: EXPA2 :: BR_MAXWAIT_CTL [12:11] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0x1800,11,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0x1800,11)
#define BRPHY0_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_MASK                   0x1800
#define BRPHY0_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_ALIGN                  0
#define BRPHY0_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_BITS                   2
#define BRPHY0_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_SHIFT                  11

/* BRPHY0_BR_CTRL :: EXPA2 :: BR_M2S2_TMR_CTL [10:10] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0x400,10,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0x400,10)
#define BRPHY0_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_MASK                  0x0400
#define BRPHY0_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_ALIGN                 0
#define BRPHY0_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_BITS                  1
#define BRPHY0_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_SHIFT                 10

/* BRPHY0_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_FDX_S [09:09] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0x200,9,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0x200,9)
#define BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_MASK               0x0200
#define BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_ALIGN              0
#define BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_BITS               1
#define BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_SHIFT              9

/* BRPHY0_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_HDX [08:08] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0x100,8,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0x100,8)
#define BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_MASK                 0x0100
#define BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_ALIGN                0
#define BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_BITS                 1
#define BRPHY0_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_SHIFT                8

/* BRPHY0_BR_CTRL :: EXPA2 :: BR_PSD_TIMER_CTL [07:06] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0xc0,6,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0xc0,6)
#define BRPHY0_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_MASK                 0x00c0
#define BRPHY0_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_ALIGN                0
#define BRPHY0_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_BITS                 2
#define BRPHY0_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_SHIFT                6

/* BRPHY0_BR_CTRL :: EXPA2 :: MAN_PHASE_CK1X [05:03] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0x38,3,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0x38,3)
#define BRPHY0_BR_CTRL_EXPA2_MAN_PHASE_CK1X_MASK                   0x0038
#define BRPHY0_BR_CTRL_EXPA2_MAN_PHASE_CK1X_ALIGN                  0
#define BRPHY0_BR_CTRL_EXPA2_MAN_PHASE_CK1X_BITS                   3
#define BRPHY0_BR_CTRL_EXPA2_MAN_PHASE_CK1X_SHIFT                  3

/* BRPHY0_BR_CTRL :: EXPA2 :: LDS_PHASE_CK1X [02:00] */
#define Wr_BRPHY0_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) WriteRegBits16(BRPHY0_BR_CTRL_EXPA2,0x7,0,x)
#define Rd_BRPHY0_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) ReadRegBits16(BRPHY0_BR_CTRL_EXPA2,0x7,0)
#define BRPHY0_BR_CTRL_EXPA2_LDS_PHASE_CK1X_MASK                   0x0007
#define BRPHY0_BR_CTRL_EXPA2_LDS_PHASE_CK1X_ALIGN                  0
#define BRPHY0_BR_CTRL_EXPA2_LDS_PHASE_CK1X_BITS                   3
#define BRPHY0_BR_CTRL_EXPA2_LDS_PHASE_CK1X_SHIFT                  0


/****************************************************************************
 * BRPHY0_BR_CTRL :: BR_MISC_CONTROL_STATUS
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_2ND_FILTER [15:15] */
#define Wr_BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) WriteRegBits16(BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15,x)
#define Rd_BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) ReadRegBits16(BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15)
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_MASK 0x8000
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_ALIGN 0
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_BITS 1
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_SHIFT 15

/* BRPHY0_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_PR_DATAPATH [14:14] */
#define Wr_BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) WriteRegBits16(BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14,x)
#define Rd_BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) ReadRegBits16(BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14)
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_MASK 0x4000
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_ALIGN 0
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_BITS 1
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_SHIFT 14

/* BRPHY0_BR_CTRL :: BR_MISC_CONTROL_STATUS :: reserved0 [13:03] */
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_MASK       0x3ff8
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_ALIGN      0
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_BITS       11
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_SHIFT      3

/* BRPHY0_BR_CTRL :: BR_MISC_CONTROL_STATUS :: BR_1P_PCS_SOL [02:00] */
#define Wr_BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) WriteRegBits16(BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0,x)
#define Rd_BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) ReadRegBits16(BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0)
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_MASK   0x0007
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_ALIGN  0
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_BITS   3
#define BRPHY0_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_SHIFT  0


/****************************************************************************
 * BRPHY0_BR_CTRL :: BR250_CTL
 ***************************************************************************/
/* BRPHY0_BR_CTRL :: BR250_CTL :: BR_CURR_RATE [15:12] */
#define Wr_BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) WriteRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0xf000,12,x)
#define Rd_BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) ReadRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0xf000,12)
#define BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_RATE_MASK                 0xf000
#define BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_RATE_ALIGN                0
#define BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_RATE_BITS                 4
#define BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_RATE_SHIFT                12

/* BRPHY0_BR_CTRL :: BR250_CTL :: BR_CURR_PAIR [11:10] */
#define Wr_BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) WriteRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0xc00,10,x)
#define Rd_BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) ReadRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0xc00,10)
#define BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_PAIR_MASK                 0x0c00
#define BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_PAIR_ALIGN                0
#define BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_PAIR_BITS                 2
#define BRPHY0_BR_CTRL_BR250_CTL_BR_CURR_PAIR_SHIFT                10

/* BRPHY0_BR_CTRL :: BR250_CTL :: reserved0 [09:08] */
#define BRPHY0_BR_CTRL_BR250_CTL_RESERVED0_MASK                    0x0300
#define BRPHY0_BR_CTRL_BR250_CTL_RESERVED0_ALIGN                   0
#define BRPHY0_BR_CTRL_BR250_CTL_RESERVED0_BITS                    2
#define BRPHY0_BR_CTRL_BR250_CTL_RESERVED0_SHIFT                   8

/* BRPHY0_BR_CTRL :: BR250_CTL :: BR_PAM5_200_sel [07:07] */
#define Wr_BRPHY0_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) WriteRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0x80,7,x)
#define Rd_BRPHY0_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) ReadRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0x80,7)
#define BRPHY0_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_MASK              0x0080
#define BRPHY0_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_ALIGN             0
#define BRPHY0_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_BITS              1
#define BRPHY0_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_SHIFT             7

/* BRPHY0_BR_CTRL :: BR250_CTL :: LBKTst2 [06:06] */
#define Wr_BRPHY0_BR_CTRL_BR250_CTL_LBKTst2(x) WriteRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0x40,6,x)
#define Rd_BRPHY0_BR_CTRL_BR250_CTL_LBKTst2(x) ReadRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0x40,6)
#define BRPHY0_BR_CTRL_BR250_CTL_LBKTST2_MASK                      0x0040
#define BRPHY0_BR_CTRL_BR250_CTL_LBKTST2_ALIGN                     0
#define BRPHY0_BR_CTRL_BR250_CTL_LBKTST2_BITS                      1
#define BRPHY0_BR_CTRL_BR250_CTL_LBKTST2_SHIFT                     6

/* BRPHY0_BR_CTRL :: BR250_CTL :: CONF_GPLL_125 [05:05] */
#define Wr_BRPHY0_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) WriteRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0x20,5,x)
#define Rd_BRPHY0_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) ReadRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0x20,5)
#define BRPHY0_BR_CTRL_BR250_CTL_CONF_GPLL_125_MASK                0x0020
#define BRPHY0_BR_CTRL_BR250_CTL_CONF_GPLL_125_ALIGN               0
#define BRPHY0_BR_CTRL_BR250_CTL_CONF_GPLL_125_BITS                1
#define BRPHY0_BR_CTRL_BR250_CTL_CONF_GPLL_125_SHIFT               5

/* BRPHY0_BR_CTRL :: BR250_CTL :: reserved1 [04:04] */
#define BRPHY0_BR_CTRL_BR250_CTL_RESERVED1_MASK                    0x0010
#define BRPHY0_BR_CTRL_BR250_CTL_RESERVED1_ALIGN                   0
#define BRPHY0_BR_CTRL_BR250_CTL_RESERVED1_BITS                    1
#define BRPHY0_BR_CTRL_BR250_CTL_RESERVED1_SHIFT                   4

/* BRPHY0_BR_CTRL :: BR250_CTL :: INTRLV_CTL [03:02] */
#define Wr_BRPHY0_BR_CTRL_BR250_CTL_INTRLV_CTL(x) WriteRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0xc,2,x)
#define Rd_BRPHY0_BR_CTRL_BR250_CTL_INTRLV_CTL(x) ReadRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0xc,2)
#define BRPHY0_BR_CTRL_BR250_CTL_INTRLV_CTL_MASK                   0x000c
#define BRPHY0_BR_CTRL_BR250_CTL_INTRLV_CTL_ALIGN                  0
#define BRPHY0_BR_CTRL_BR250_CTL_INTRLV_CTL_BITS                   2
#define BRPHY0_BR_CTRL_BR250_CTL_INTRLV_CTL_SHIFT                  2

/* BRPHY0_BR_CTRL :: BR250_CTL :: PAIR_CFG [01:00] */
#define Wr_BRPHY0_BR_CTRL_BR250_CTL_PAIR_CFG(x) WriteRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0x3,0,x)
#define Rd_BRPHY0_BR_CTRL_BR250_CTL_PAIR_CFG(x) ReadRegBits16(BRPHY0_BR_CTRL_BR250_CTL,0x3,0)
#define BRPHY0_BR_CTRL_BR250_CTL_PAIR_CFG_MASK                     0x0003
#define BRPHY0_BR_CTRL_BR250_CTL_PAIR_CFG_ALIGN                    0
#define BRPHY0_BR_CTRL_BR250_CTL_PAIR_CFG_BITS                     2
#define BRPHY0_BR_CTRL_BR250_CTL_PAIR_CFG_SHIFT                    0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY_TOP_MISC_0
 ***************************************************************************/
/****************************************************************************
 * BRPHY_TOP_MISC_0 :: SPARE_REG_0
 ***************************************************************************/
/* BRPHY_TOP_MISC_0 :: SPARE_REG_0 :: SPARE_REG [15:00] */
#define Wr_BRPHY_TOP_MISC_0_SPARE_REG_0_SPARE_REG(x) WriteReg16(BRPHY_TOP_MISC_0_SPARE_REG_0,x)
#define Rd_BRPHY_TOP_MISC_0_SPARE_REG_0_SPARE_REG(x) ReadReg16(BRPHY_TOP_MISC_0_SPARE_REG_0)
#define BRPHY_TOP_MISC_0_SPARE_REG_0_SPARE_REG_MASK                0xffff
#define BRPHY_TOP_MISC_0_SPARE_REG_0_SPARE_REG_ALIGN               0
#define BRPHY_TOP_MISC_0_SPARE_REG_0_SPARE_REG_BITS                16
#define BRPHY_TOP_MISC_0_SPARE_REG_0_SPARE_REG_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_MISC_0 :: SPARE_REG_1
 ***************************************************************************/
/* BRPHY_TOP_MISC_0 :: SPARE_REG_1 :: SPARE_REG [15:00] */
#define Wr_BRPHY_TOP_MISC_0_SPARE_REG_1_SPARE_REG(x) WriteReg16(BRPHY_TOP_MISC_0_SPARE_REG_1,x)
#define Rd_BRPHY_TOP_MISC_0_SPARE_REG_1_SPARE_REG(x) ReadReg16(BRPHY_TOP_MISC_0_SPARE_REG_1)
#define BRPHY_TOP_MISC_0_SPARE_REG_1_SPARE_REG_MASK                0xffff
#define BRPHY_TOP_MISC_0_SPARE_REG_1_SPARE_REG_ALIGN               0
#define BRPHY_TOP_MISC_0_SPARE_REG_1_SPARE_REG_BITS                16
#define BRPHY_TOP_MISC_0_SPARE_REG_1_SPARE_REG_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_MISC_0 :: AFE_OVR
 ***************************************************************************/
/* BRPHY_TOP_MISC_0 :: AFE_OVR :: reserved0 [15:09] */
#define BRPHY_TOP_MISC_0_AFE_OVR_RESERVED0_MASK                    0xfe00
#define BRPHY_TOP_MISC_0_AFE_OVR_RESERVED0_ALIGN                   0
#define BRPHY_TOP_MISC_0_AFE_OVR_RESERVED0_BITS                    7
#define BRPHY_TOP_MISC_0_AFE_OVR_RESERVED0_SHIFT                   9

/* BRPHY_TOP_MISC_0 :: AFE_OVR :: TH_POLE [08:08] */
#define Wr_BRPHY_TOP_MISC_0_AFE_OVR_TH_POLE(x) WriteRegBits16(BRPHY_TOP_MISC_0_AFE_OVR,0x100,8,x)
#define Rd_BRPHY_TOP_MISC_0_AFE_OVR_TH_POLE(x) ReadRegBits16(BRPHY_TOP_MISC_0_AFE_OVR,0x100,8)
#define BRPHY_TOP_MISC_0_AFE_OVR_TH_POLE_MASK                      0x0100
#define BRPHY_TOP_MISC_0_AFE_OVR_TH_POLE_ALIGN                     0
#define BRPHY_TOP_MISC_0_AFE_OVR_TH_POLE_BITS                      1
#define BRPHY_TOP_MISC_0_AFE_OVR_TH_POLE_SHIFT                     8

/* BRPHY_TOP_MISC_0 :: AFE_OVR :: TRIMHYB [07:04] */
#define Wr_BRPHY_TOP_MISC_0_AFE_OVR_TRIMHYB(x) WriteRegBits16(BRPHY_TOP_MISC_0_AFE_OVR,0xf0,4,x)
#define Rd_BRPHY_TOP_MISC_0_AFE_OVR_TRIMHYB(x) ReadRegBits16(BRPHY_TOP_MISC_0_AFE_OVR,0xf0,4)
#define BRPHY_TOP_MISC_0_AFE_OVR_TRIMHYB_MASK                      0x00f0
#define BRPHY_TOP_MISC_0_AFE_OVR_TRIMHYB_ALIGN                     0
#define BRPHY_TOP_MISC_0_AFE_OVR_TRIMHYB_BITS                      4
#define BRPHY_TOP_MISC_0_AFE_OVR_TRIMHYB_SHIFT                     4

/* BRPHY_TOP_MISC_0 :: AFE_OVR :: TRIMDAC [03:00] */
#define Wr_BRPHY_TOP_MISC_0_AFE_OVR_TRIMDAC(x) WriteRegBits16(BRPHY_TOP_MISC_0_AFE_OVR,0xf,0,x)
#define Rd_BRPHY_TOP_MISC_0_AFE_OVR_TRIMDAC(x) ReadRegBits16(BRPHY_TOP_MISC_0_AFE_OVR,0xf,0)
#define BRPHY_TOP_MISC_0_AFE_OVR_TRIMDAC_MASK                      0x000f
#define BRPHY_TOP_MISC_0_AFE_OVR_TRIMDAC_ALIGN                     0
#define BRPHY_TOP_MISC_0_AFE_OVR_TRIMDAC_BITS                      4
#define BRPHY_TOP_MISC_0_AFE_OVR_TRIMDAC_SHIFT                     0


/****************************************************************************
 * BRPHY_TOP_MISC_0 :: TEST_REG0
 ***************************************************************************/
/* BRPHY_TOP_MISC_0 :: TEST_REG0 :: reserved0 [15:04] */
#define BRPHY_TOP_MISC_0_TEST_REG0_RESERVED0_MASK                  0xfff0
#define BRPHY_TOP_MISC_0_TEST_REG0_RESERVED0_ALIGN                 0
#define BRPHY_TOP_MISC_0_TEST_REG0_RESERVED0_BITS                  12
#define BRPHY_TOP_MISC_0_TEST_REG0_RESERVED0_SHIFT                 4

/* BRPHY_TOP_MISC_0 :: TEST_REG0 :: FAST_MDIO_EN_SOFT [03:03] */
#define Wr_BRPHY_TOP_MISC_0_TEST_REG0_FAST_MDIO_EN_SOFT(x) WriteRegBits16(BRPHY_TOP_MISC_0_TEST_REG0,0x8,3,x)
#define Rd_BRPHY_TOP_MISC_0_TEST_REG0_FAST_MDIO_EN_SOFT(x) ReadRegBits16(BRPHY_TOP_MISC_0_TEST_REG0,0x8,3)
#define BRPHY_TOP_MISC_0_TEST_REG0_FAST_MDIO_EN_SOFT_MASK          0x0008
#define BRPHY_TOP_MISC_0_TEST_REG0_FAST_MDIO_EN_SOFT_ALIGN         0
#define BRPHY_TOP_MISC_0_TEST_REG0_FAST_MDIO_EN_SOFT_BITS          1
#define BRPHY_TOP_MISC_0_TEST_REG0_FAST_MDIO_EN_SOFT_SHIFT         3

/* BRPHY_TOP_MISC_0 :: TEST_REG0 :: DLLBYPASS_MODE_SOFT [02:02] */
#define Wr_BRPHY_TOP_MISC_0_TEST_REG0_DLLBYPASS_MODE_SOFT(x) WriteRegBits16(BRPHY_TOP_MISC_0_TEST_REG0,0x4,2,x)
#define Rd_BRPHY_TOP_MISC_0_TEST_REG0_DLLBYPASS_MODE_SOFT(x) ReadRegBits16(BRPHY_TOP_MISC_0_TEST_REG0,0x4,2)
#define BRPHY_TOP_MISC_0_TEST_REG0_DLLBYPASS_MODE_SOFT_MASK        0x0004
#define BRPHY_TOP_MISC_0_TEST_REG0_DLLBYPASS_MODE_SOFT_ALIGN       0
#define BRPHY_TOP_MISC_0_TEST_REG0_DLLBYPASS_MODE_SOFT_BITS        1
#define BRPHY_TOP_MISC_0_TEST_REG0_DLLBYPASS_MODE_SOFT_SHIFT       2

/* BRPHY_TOP_MISC_0 :: TEST_REG0 :: TESTTMPL_MODE_SOFT [01:01] */
#define Wr_BRPHY_TOP_MISC_0_TEST_REG0_TESTTMPL_MODE_SOFT(x) WriteRegBits16(BRPHY_TOP_MISC_0_TEST_REG0,0x2,1,x)
#define Rd_BRPHY_TOP_MISC_0_TEST_REG0_TESTTMPL_MODE_SOFT(x) ReadRegBits16(BRPHY_TOP_MISC_0_TEST_REG0,0x2,1)
#define BRPHY_TOP_MISC_0_TEST_REG0_TESTTMPL_MODE_SOFT_MASK         0x0002
#define BRPHY_TOP_MISC_0_TEST_REG0_TESTTMPL_MODE_SOFT_ALIGN        0
#define BRPHY_TOP_MISC_0_TEST_REG0_TESTTMPL_MODE_SOFT_BITS         1
#define BRPHY_TOP_MISC_0_TEST_REG0_TESTTMPL_MODE_SOFT_SHIFT        1

/* BRPHY_TOP_MISC_0 :: TEST_REG0 :: IDDQ_TEST_MODE_SOFT [00:00] */
#define Wr_BRPHY_TOP_MISC_0_TEST_REG0_IDDQ_TEST_MODE_SOFT(x) WriteRegBits16(BRPHY_TOP_MISC_0_TEST_REG0,0x1,0,x)
#define Rd_BRPHY_TOP_MISC_0_TEST_REG0_IDDQ_TEST_MODE_SOFT(x) ReadRegBits16(BRPHY_TOP_MISC_0_TEST_REG0,0x1,0)
#define BRPHY_TOP_MISC_0_TEST_REG0_IDDQ_TEST_MODE_SOFT_MASK        0x0001
#define BRPHY_TOP_MISC_0_TEST_REG0_IDDQ_TEST_MODE_SOFT_ALIGN       0
#define BRPHY_TOP_MISC_0_TEST_REG0_IDDQ_TEST_MODE_SOFT_BITS        1
#define BRPHY_TOP_MISC_0_TEST_REG0_IDDQ_TEST_MODE_SOFT_SHIFT       0


/****************************************************************************
 * BRPHY_TOP_MISC_0 :: TEST_REG1
 ***************************************************************************/
/* BRPHY_TOP_MISC_0 :: TEST_REG1 :: reserved0 [15:12] */
#define BRPHY_TOP_MISC_0_TEST_REG1_RESERVED0_MASK                  0xf000
#define BRPHY_TOP_MISC_0_TEST_REG1_RESERVED0_ALIGN                 0
#define BRPHY_TOP_MISC_0_TEST_REG1_RESERVED0_BITS                  4
#define BRPHY_TOP_MISC_0_TEST_REG1_RESERVED0_SHIFT                 12

/* BRPHY_TOP_MISC_0 :: TEST_REG1 :: LSI_TEST_MODE_SOFT [11:11] */
#define Wr_BRPHY_TOP_MISC_0_TEST_REG1_LSI_TEST_MODE_SOFT(x) WriteRegBits16(BRPHY_TOP_MISC_0_TEST_REG1,0x800,11,x)
#define Rd_BRPHY_TOP_MISC_0_TEST_REG1_LSI_TEST_MODE_SOFT(x) ReadRegBits16(BRPHY_TOP_MISC_0_TEST_REG1,0x800,11)
#define BRPHY_TOP_MISC_0_TEST_REG1_LSI_TEST_MODE_SOFT_MASK         0x0800
#define BRPHY_TOP_MISC_0_TEST_REG1_LSI_TEST_MODE_SOFT_ALIGN        0
#define BRPHY_TOP_MISC_0_TEST_REG1_LSI_TEST_MODE_SOFT_BITS         1
#define BRPHY_TOP_MISC_0_TEST_REG1_LSI_TEST_MODE_SOFT_SHIFT        11

/* BRPHY_TOP_MISC_0 :: TEST_REG1 :: GPHY_TEST_MODE [10:06] */
#define Wr_BRPHY_TOP_MISC_0_TEST_REG1_GPHY_TEST_MODE(x) WriteRegBits16(BRPHY_TOP_MISC_0_TEST_REG1,0x7c0,6,x)
#define Rd_BRPHY_TOP_MISC_0_TEST_REG1_GPHY_TEST_MODE(x) ReadRegBits16(BRPHY_TOP_MISC_0_TEST_REG1,0x7c0,6)
#define BRPHY_TOP_MISC_0_TEST_REG1_GPHY_TEST_MODE_MASK             0x07c0
#define BRPHY_TOP_MISC_0_TEST_REG1_GPHY_TEST_MODE_ALIGN            0
#define BRPHY_TOP_MISC_0_TEST_REG1_GPHY_TEST_MODE_BITS             5
#define BRPHY_TOP_MISC_0_TEST_REG1_GPHY_TEST_MODE_SHIFT            6

/* BRPHY_TOP_MISC_0 :: TEST_REG1 :: TEST_SLICE_SEL [05:03] */
#define Wr_BRPHY_TOP_MISC_0_TEST_REG1_TEST_SLICE_SEL(x) WriteRegBits16(BRPHY_TOP_MISC_0_TEST_REG1,0x38,3,x)
#define Rd_BRPHY_TOP_MISC_0_TEST_REG1_TEST_SLICE_SEL(x) ReadRegBits16(BRPHY_TOP_MISC_0_TEST_REG1,0x38,3)
#define BRPHY_TOP_MISC_0_TEST_REG1_TEST_SLICE_SEL_MASK             0x0038
#define BRPHY_TOP_MISC_0_TEST_REG1_TEST_SLICE_SEL_ALIGN            0
#define BRPHY_TOP_MISC_0_TEST_REG1_TEST_SLICE_SEL_BITS             3
#define BRPHY_TOP_MISC_0_TEST_REG1_TEST_SLICE_SEL_SHIFT            3

/* BRPHY_TOP_MISC_0 :: TEST_REG1 :: TEST_BUS_SEL [02:00] */
#define Wr_BRPHY_TOP_MISC_0_TEST_REG1_TEST_BUS_SEL(x) WriteRegBits16(BRPHY_TOP_MISC_0_TEST_REG1,0x7,0,x)
#define Rd_BRPHY_TOP_MISC_0_TEST_REG1_TEST_BUS_SEL(x) ReadRegBits16(BRPHY_TOP_MISC_0_TEST_REG1,0x7,0)
#define BRPHY_TOP_MISC_0_TEST_REG1_TEST_BUS_SEL_MASK               0x0007
#define BRPHY_TOP_MISC_0_TEST_REG1_TEST_BUS_SEL_ALIGN              0
#define BRPHY_TOP_MISC_0_TEST_REG1_TEST_BUS_SEL_BITS               3
#define BRPHY_TOP_MISC_0_TEST_REG1_TEST_BUS_SEL_SHIFT              0


/****************************************************************************
 * BRPHY_TOP_MISC_0 :: TOP_GLOBAL_RESET_REG
 ***************************************************************************/
/* BRPHY_TOP_MISC_0 :: TOP_GLOBAL_RESET_REG :: TOP_MII_REG_SOFT_RST [15:15] */
#define Wr_BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_TOP_MII_REG_SOFT_RST(x) WriteRegBits16(BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG,0x8000,15,x)
#define Rd_BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_TOP_MII_REG_SOFT_RST(x) ReadRegBits16(BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG,0x8000,15)
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_TOP_MII_REG_SOFT_RST_MASK 0x8000
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_TOP_MII_REG_SOFT_RST_ALIGN 0
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_TOP_MII_REG_SOFT_RST_BITS 1
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_TOP_MII_REG_SOFT_RST_SHIFT 15

/* BRPHY_TOP_MISC_0 :: TOP_GLOBAL_RESET_REG :: reserved0 [14:02] */
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_RESERVED0_MASK       0x7ffc
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_RESERVED0_ALIGN      0
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_RESERVED0_BITS       13
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_RESERVED0_SHIFT      2

/* BRPHY_TOP_MISC_0 :: TOP_GLOBAL_RESET_REG :: WOL_SOFT_RST [01:01] */
#define Wr_BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_WOL_SOFT_RST(x) WriteRegBits16(BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG,0x2,1,x)
#define Rd_BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_WOL_SOFT_RST(x) ReadRegBits16(BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG,0x2,1)
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_WOL_SOFT_RST_MASK    0x0002
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_WOL_SOFT_RST_ALIGN   0
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_WOL_SOFT_RST_BITS    1
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_WOL_SOFT_RST_SHIFT   1

/* BRPHY_TOP_MISC_0 :: TOP_GLOBAL_RESET_REG :: P1588_SOFT_RST [00:00] */
#define Wr_BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_P1588_SOFT_RST(x) WriteRegBits16(BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG,0x1,0,x)
#define Rd_BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_P1588_SOFT_RST(x) ReadRegBits16(BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG,0x1,0)
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_P1588_SOFT_RST_MASK  0x0001
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_P1588_SOFT_RST_ALIGN 0
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_P1588_SOFT_RST_BITS  1
#define BRPHY_TOP_MISC_0_TOP_GLOBAL_RESET_REG_P1588_SOFT_RST_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_MISC_0 :: INTERRUPT_STATUS_REG
 ***************************************************************************/
/* BRPHY_TOP_MISC_0 :: INTERRUPT_STATUS_REG :: reserved0 [15:12] */
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_RESERVED0_MASK       0xf000
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_RESERVED0_ALIGN      0
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_RESERVED0_BITS       4
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_RESERVED0_SHIFT      12

/* BRPHY_TOP_MISC_0 :: INTERRUPT_STATUS_REG :: ENERGY_DET [11:07] */
#define Wr_BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_ENERGY_DET(x) WriteRegBits16(BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG,0xf80,7,x)
#define Rd_BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_ENERGY_DET(x) ReadRegBits16(BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG,0xf80,7)
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_ENERGY_DET_MASK      0x0f80
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_ENERGY_DET_ALIGN     0
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_ENERGY_DET_BITS      5
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_ENERGY_DET_SHIFT     7

/* BRPHY_TOP_MISC_0 :: INTERRUPT_STATUS_REG :: WOL_INTR [06:06] */
#define Wr_BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_WOL_INTR(x) WriteRegBits16(BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG,0x40,6,x)
#define Rd_BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_WOL_INTR(x) ReadRegBits16(BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG,0x40,6)
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_WOL_INTR_MASK        0x0040
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_WOL_INTR_ALIGN       0
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_WOL_INTR_BITS        1
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_WOL_INTR_SHIFT       6

/* BRPHY_TOP_MISC_0 :: INTERRUPT_STATUS_REG :: P1588_TS_INT [05:05] */
#define Wr_BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_P1588_TS_INT(x) WriteRegBits16(BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG,0x20,5,x)
#define Rd_BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_P1588_TS_INT(x) ReadRegBits16(BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG,0x20,5)
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_P1588_TS_INT_MASK    0x0020
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_P1588_TS_INT_ALIGN   0
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_P1588_TS_INT_BITS    1
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_P1588_TS_INT_SHIFT   5

/* BRPHY_TOP_MISC_0 :: INTERRUPT_STATUS_REG :: SLICE_INTERRUPT [04:00] */
#define Wr_BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_SLICE_INTERRUPT(x) WriteRegBits16(BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG,0x1f,0,x)
#define Rd_BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_SLICE_INTERRUPT(x) ReadRegBits16(BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG,0x1f,0)
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_SLICE_INTERRUPT_MASK 0x001f
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_SLICE_INTERRUPT_ALIGN 0
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_SLICE_INTERRUPT_BITS 5
#define BRPHY_TOP_MISC_0_INTERRUPT_STATUS_REG_SLICE_INTERRUPT_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY_WOL
 ***************************************************************************/
/****************************************************************************
 * BRPHY_WOL :: tb_p0_ctrl
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_ctrl :: mask_mode [15:14] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_mask_mode(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0xc000,14,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_mask_mode(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0xc000,14)
#define BRPHY_WOL_TB_P0_CTRL_MASK_MODE_MASK                        0xc000
#define BRPHY_WOL_TB_P0_CTRL_MASK_MODE_ALIGN                       0
#define BRPHY_WOL_TB_P0_CTRL_MASK_MODE_BITS                        2
#define BRPHY_WOL_TB_P0_CTRL_MASK_MODE_SHIFT                       14

/* BRPHY_WOL :: tb_p0_ctrl :: dir_pkt_en [13:13] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_dir_pkt_en(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x2000,13,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_dir_pkt_en(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x2000,13)
#define BRPHY_WOL_TB_P0_CTRL_DIR_PKT_EN_MASK                       0x2000
#define BRPHY_WOL_TB_P0_CTRL_DIR_PKT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P0_CTRL_DIR_PKT_EN_BITS                       1
#define BRPHY_WOL_TB_P0_CTRL_DIR_PKT_EN_SHIFT                      13

/* BRPHY_WOL :: tb_p0_ctrl :: wol_rst [12:12] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_wol_rst(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x1000,12,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_wol_rst(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x1000,12)
#define BRPHY_WOL_TB_P0_CTRL_WOL_RST_MASK                          0x1000
#define BRPHY_WOL_TB_P0_CTRL_WOL_RST_ALIGN                         0
#define BRPHY_WOL_TB_P0_CTRL_WOL_RST_BITS                          1
#define BRPHY_WOL_TB_P0_CTRL_WOL_RST_SHIFT                         12

/* BRPHY_WOL :: tb_p0_ctrl :: seckey_mode [11:11] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_seckey_mode(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x800,11,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_seckey_mode(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x800,11)
#define BRPHY_WOL_TB_P0_CTRL_SECKEY_MODE_MASK                      0x0800
#define BRPHY_WOL_TB_P0_CTRL_SECKEY_MODE_ALIGN                     0
#define BRPHY_WOL_TB_P0_CTRL_SECKEY_MODE_BITS                      1
#define BRPHY_WOL_TB_P0_CTRL_SECKEY_MODE_SHIFT                     11

/* BRPHY_WOL :: tb_p0_ctrl :: crc_en [10:10] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_crc_en(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x400,10,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_crc_en(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x400,10)
#define BRPHY_WOL_TB_P0_CTRL_CRC_EN_MASK                           0x0400
#define BRPHY_WOL_TB_P0_CTRL_CRC_EN_ALIGN                          0
#define BRPHY_WOL_TB_P0_CTRL_CRC_EN_BITS                           1
#define BRPHY_WOL_TB_P0_CTRL_CRC_EN_SHIFT                          10

/* BRPHY_WOL :: tb_p0_ctrl :: udpport_en [09:09] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_udpport_en(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x200,9,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_udpport_en(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x200,9)
#define BRPHY_WOL_TB_P0_CTRL_UDPPORT_EN_MASK                       0x0200
#define BRPHY_WOL_TB_P0_CTRL_UDPPORT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P0_CTRL_UDPPORT_EN_BITS                       1
#define BRPHY_WOL_TB_P0_CTRL_UDPPORT_EN_SHIFT                      9

/* BRPHY_WOL :: tb_p0_ctrl :: l4ipv6udp_en [08:08] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_l4ipv6udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x100,8,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_l4ipv6udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x100,8)
#define BRPHY_WOL_TB_P0_CTRL_L4IPV6UDP_EN_MASK                     0x0100
#define BRPHY_WOL_TB_P0_CTRL_L4IPV6UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P0_CTRL_L4IPV6UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P0_CTRL_L4IPV6UDP_EN_SHIFT                    8

/* BRPHY_WOL :: tb_p0_ctrl :: l4ipv4udp_en [07:07] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_l4ipv4udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x80,7,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_l4ipv4udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x80,7)
#define BRPHY_WOL_TB_P0_CTRL_L4IPV4UDP_EN_MASK                     0x0080
#define BRPHY_WOL_TB_P0_CTRL_L4IPV4UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P0_CTRL_L4IPV4UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P0_CTRL_L4IPV4UDP_EN_SHIFT                    7

/* BRPHY_WOL :: tb_p0_ctrl :: l2_en [06:06] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_l2_en(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x40,6,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_l2_en(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x40,6)
#define BRPHY_WOL_TB_P0_CTRL_L2_EN_MASK                            0x0040
#define BRPHY_WOL_TB_P0_CTRL_L2_EN_ALIGN                           0
#define BRPHY_WOL_TB_P0_CTRL_L2_EN_BITS                            1
#define BRPHY_WOL_TB_P0_CTRL_L2_EN_SHIFT                           6

/* BRPHY_WOL :: tb_p0_ctrl :: seckey_opt [05:04] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_seckey_opt(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x30,4,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_seckey_opt(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x30,4)
#define BRPHY_WOL_TB_P0_CTRL_SECKEY_OPT_MASK                       0x0030
#define BRPHY_WOL_TB_P0_CTRL_SECKEY_OPT_ALIGN                      0
#define BRPHY_WOL_TB_P0_CTRL_SECKEY_OPT_BITS                       2
#define BRPHY_WOL_TB_P0_CTRL_SECKEY_OPT_SHIFT                      4

/* BRPHY_WOL :: tb_p0_ctrl :: mp_msb_ff_en [03:03] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_mp_msb_ff_en(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x8,3,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_mp_msb_ff_en(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x8,3)
#define BRPHY_WOL_TB_P0_CTRL_MP_MSB_FF_EN_MASK                     0x0008
#define BRPHY_WOL_TB_P0_CTRL_MP_MSB_FF_EN_ALIGN                    0
#define BRPHY_WOL_TB_P0_CTRL_MP_MSB_FF_EN_BITS                     1
#define BRPHY_WOL_TB_P0_CTRL_MP_MSB_FF_EN_SHIFT                    3

/* BRPHY_WOL :: tb_p0_ctrl :: mode [02:01] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_mode(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x6,1,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_mode(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x6,1)
#define BRPHY_WOL_TB_P0_CTRL_MODE_MASK                             0x0006
#define BRPHY_WOL_TB_P0_CTRL_MODE_ALIGN                            0
#define BRPHY_WOL_TB_P0_CTRL_MODE_BITS                             2
#define BRPHY_WOL_TB_P0_CTRL_MODE_SHIFT                            1

/* BRPHY_WOL :: tb_p0_ctrl :: wol_en [00:00] */
#define Wr_BRPHY_WOL_tb_p0_ctrl_wol_en(x) WriteRegBits16(BRPHY_WOL_TB_P0_CTRL,0x1,0,x)
#define Rd_BRPHY_WOL_tb_p0_ctrl_wol_en(x) ReadRegBits16(BRPHY_WOL_TB_P0_CTRL,0x1,0)
#define BRPHY_WOL_TB_P0_CTRL_WOL_EN_MASK                           0x0001
#define BRPHY_WOL_TB_P0_CTRL_WOL_EN_ALIGN                          0
#define BRPHY_WOL_TB_P0_CTRL_WOL_EN_BITS                           1
#define BRPHY_WOL_TB_P0_CTRL_WOL_EN_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_itpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_itpid :: itpid [15:00] */
#define Wr_BRPHY_WOL_tb_p0_itpid_itpid(x) WriteReg16(BRPHY_WOL_TB_P0_ITPID,x)
#define Rd_BRPHY_WOL_tb_p0_itpid_itpid(x) ReadReg16(BRPHY_WOL_TB_P0_ITPID)
#define BRPHY_WOL_TB_P0_ITPID_ITPID_MASK                           0xffff
#define BRPHY_WOL_TB_P0_ITPID_ITPID_ALIGN                          0
#define BRPHY_WOL_TB_P0_ITPID_ITPID_BITS                           16
#define BRPHY_WOL_TB_P0_ITPID_ITPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_otpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_otpid :: otpid [15:00] */
#define Wr_BRPHY_WOL_tb_p0_otpid_otpid(x) WriteReg16(BRPHY_WOL_TB_P0_OTPID,x)
#define Rd_BRPHY_WOL_tb_p0_otpid_otpid(x) ReadReg16(BRPHY_WOL_TB_P0_OTPID)
#define BRPHY_WOL_TB_P0_OTPID_OTPID_MASK                           0xffff
#define BRPHY_WOL_TB_P0_OTPID_OTPID_ALIGN                          0
#define BRPHY_WOL_TB_P0_OTPID_OTPID_BITS                           16
#define BRPHY_WOL_TB_P0_OTPID_OTPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_otpid2
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_otpid2 :: otpid2 [15:00] */
#define Wr_BRPHY_WOL_tb_p0_otpid2_otpid2(x) WriteReg16(BRPHY_WOL_TB_P0_OTPID2,x)
#define Rd_BRPHY_WOL_tb_p0_otpid2_otpid2(x) ReadReg16(BRPHY_WOL_TB_P0_OTPID2)
#define BRPHY_WOL_TB_P0_OTPID2_OTPID2_MASK                         0xffff
#define BRPHY_WOL_TB_P0_OTPID2_OTPID2_ALIGN                        0
#define BRPHY_WOL_TB_P0_OTPID2_OTPID2_BITS                         16
#define BRPHY_WOL_TB_P0_OTPID2_OTPID2_SHIFT                        0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_pkt1_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_pkt1_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_pkt1_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P0_PKT1_15_00,x)
#define Rd_BRPHY_WOL_tb_p0_pkt1_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P0_PKT1_15_00)
#define BRPHY_WOL_TB_P0_PKT1_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P0_PKT1_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P0_PKT1_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P0_PKT1_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_pkt1_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_pkt1_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_pkt1_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P0_PKT1_31_16,x)
#define Rd_BRPHY_WOL_tb_p0_pkt1_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P0_PKT1_31_16)
#define BRPHY_WOL_TB_P0_PKT1_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P0_PKT1_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P0_PKT1_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P0_PKT1_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_pkt1_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_pkt1_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_pkt1_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P0_PKT1_47_32,x)
#define Rd_BRPHY_WOL_tb_p0_pkt1_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P0_PKT1_47_32)
#define BRPHY_WOL_TB_P0_PKT1_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P0_PKT1_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P0_PKT1_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P0_PKT1_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_pkt2_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_pkt2_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_pkt2_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P0_PKT2_15_00,x)
#define Rd_BRPHY_WOL_tb_p0_pkt2_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P0_PKT2_15_00)
#define BRPHY_WOL_TB_P0_PKT2_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P0_PKT2_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P0_PKT2_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P0_PKT2_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_pkt2_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_pkt2_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_pkt2_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P0_PKT2_31_16,x)
#define Rd_BRPHY_WOL_tb_p0_pkt2_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P0_PKT2_31_16)
#define BRPHY_WOL_TB_P0_PKT2_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P0_PKT2_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P0_PKT2_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P0_PKT2_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_pkt2_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_pkt2_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_pkt2_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P0_PKT2_47_32,x)
#define Rd_BRPHY_WOL_tb_p0_pkt2_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P0_PKT2_47_32)
#define BRPHY_WOL_TB_P0_PKT2_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P0_PKT2_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P0_PKT2_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P0_PKT2_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_pkt2_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_pkt2_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_pkt2_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P0_PKT2_63_48,x)
#define Rd_BRPHY_WOL_tb_p0_pkt2_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P0_PKT2_63_48)
#define BRPHY_WOL_TB_P0_PKT2_63_48_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P0_PKT2_63_48_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P0_PKT2_63_48_DATA_BITS                       16
#define BRPHY_WOL_TB_P0_PKT2_63_48_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_mskctr_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_mskctr_15_00 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p0_mskctr_15_00_mask(x) WriteReg16(BRPHY_WOL_TB_P0_MSKCTR_15_00,x)
#define Rd_BRPHY_WOL_tb_p0_mskctr_15_00_mask(x) ReadReg16(BRPHY_WOL_TB_P0_MSKCTR_15_00)
#define BRPHY_WOL_TB_P0_MSKCTR_15_00_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P0_MSKCTR_15_00_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P0_MSKCTR_15_00_MASK_BITS                     16
#define BRPHY_WOL_TB_P0_MSKCTR_15_00_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_mskctr_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_mskctr_31_16 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p0_mskctr_31_16_mask(x) WriteReg16(BRPHY_WOL_TB_P0_MSKCTR_31_16,x)
#define Rd_BRPHY_WOL_tb_p0_mskctr_31_16_mask(x) ReadReg16(BRPHY_WOL_TB_P0_MSKCTR_31_16)
#define BRPHY_WOL_TB_P0_MSKCTR_31_16_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P0_MSKCTR_31_16_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P0_MSKCTR_31_16_MASK_BITS                     16
#define BRPHY_WOL_TB_P0_MSKCTR_31_16_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_mskctr_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_mskctr_47_32 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p0_mskctr_47_32_mask(x) WriteReg16(BRPHY_WOL_TB_P0_MSKCTR_47_32,x)
#define Rd_BRPHY_WOL_tb_p0_mskctr_47_32_mask(x) ReadReg16(BRPHY_WOL_TB_P0_MSKCTR_47_32)
#define BRPHY_WOL_TB_P0_MSKCTR_47_32_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P0_MSKCTR_47_32_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P0_MSKCTR_47_32_MASK_BITS                     16
#define BRPHY_WOL_TB_P0_MSKCTR_47_32_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_seckey_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_seckey_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_seckey_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P0_SECKEY_15_00,x)
#define Rd_BRPHY_WOL_tb_p0_seckey_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P0_SECKEY_15_00)
#define BRPHY_WOL_TB_P0_SECKEY_15_00_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P0_SECKEY_15_00_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P0_SECKEY_15_00_DATA_BITS                     16
#define BRPHY_WOL_TB_P0_SECKEY_15_00_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_seckey_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_seckey_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_seckey_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P0_SECKEY_31_16,x)
#define Rd_BRPHY_WOL_tb_p0_seckey_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P0_SECKEY_31_16)
#define BRPHY_WOL_TB_P0_SECKEY_31_16_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P0_SECKEY_31_16_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P0_SECKEY_31_16_DATA_BITS                     16
#define BRPHY_WOL_TB_P0_SECKEY_31_16_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_seckey_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_seckey_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_seckey_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P0_SECKEY_47_32,x)
#define Rd_BRPHY_WOL_tb_p0_seckey_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P0_SECKEY_47_32)
#define BRPHY_WOL_TB_P0_SECKEY_47_32_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P0_SECKEY_47_32_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P0_SECKEY_47_32_DATA_BITS                     16
#define BRPHY_WOL_TB_P0_SECKEY_47_32_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_seckey_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_seckey_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p0_seckey_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P0_SECKEY_63_48,x)
#define Rd_BRPHY_WOL_tb_p0_seckey_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P0_SECKEY_63_48)
#define BRPHY_WOL_TB_P0_SECKEY_63_48_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P0_SECKEY_63_48_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P0_SECKEY_63_48_DATA_BITS                     16
#define BRPHY_WOL_TB_P0_SECKEY_63_48_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p0_pkt_cnt
 ***************************************************************************/
/* BRPHY_WOL :: tb_p0_pkt_cnt :: reserved0 [15:08] */
#define BRPHY_WOL_TB_P0_PKT_CNT_RESERVED0_MASK                     0xff00
#define BRPHY_WOL_TB_P0_PKT_CNT_RESERVED0_ALIGN                    0
#define BRPHY_WOL_TB_P0_PKT_CNT_RESERVED0_BITS                     8
#define BRPHY_WOL_TB_P0_PKT_CNT_RESERVED0_SHIFT                    8

/* BRPHY_WOL :: tb_p0_pkt_cnt :: counter [07:00] */
#define Wr_BRPHY_WOL_tb_p0_pkt_cnt_counter(x) WriteRegBits16(BRPHY_WOL_TB_P0_PKT_CNT,0xff,0,x)
#define Rd_BRPHY_WOL_tb_p0_pkt_cnt_counter(x) ReadRegBits16(BRPHY_WOL_TB_P0_PKT_CNT,0xff,0)
#define BRPHY_WOL_TB_P0_PKT_CNT_COUNTER_MASK                       0x00ff
#define BRPHY_WOL_TB_P0_PKT_CNT_COUNTER_ALIGN                      0
#define BRPHY_WOL_TB_P0_PKT_CNT_COUNTER_BITS                       8
#define BRPHY_WOL_TB_P0_PKT_CNT_COUNTER_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_ctrl
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_ctrl :: mask_mode [15:14] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_mask_mode(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0xc000,14,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_mask_mode(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0xc000,14)
#define BRPHY_WOL_TB_P1_CTRL_MASK_MODE_MASK                        0xc000
#define BRPHY_WOL_TB_P1_CTRL_MASK_MODE_ALIGN                       0
#define BRPHY_WOL_TB_P1_CTRL_MASK_MODE_BITS                        2
#define BRPHY_WOL_TB_P1_CTRL_MASK_MODE_SHIFT                       14

/* BRPHY_WOL :: tb_p1_ctrl :: dir_pkt_en [13:13] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_dir_pkt_en(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x2000,13,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_dir_pkt_en(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x2000,13)
#define BRPHY_WOL_TB_P1_CTRL_DIR_PKT_EN_MASK                       0x2000
#define BRPHY_WOL_TB_P1_CTRL_DIR_PKT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P1_CTRL_DIR_PKT_EN_BITS                       1
#define BRPHY_WOL_TB_P1_CTRL_DIR_PKT_EN_SHIFT                      13

/* BRPHY_WOL :: tb_p1_ctrl :: wol_rst [12:12] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_wol_rst(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x1000,12,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_wol_rst(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x1000,12)
#define BRPHY_WOL_TB_P1_CTRL_WOL_RST_MASK                          0x1000
#define BRPHY_WOL_TB_P1_CTRL_WOL_RST_ALIGN                         0
#define BRPHY_WOL_TB_P1_CTRL_WOL_RST_BITS                          1
#define BRPHY_WOL_TB_P1_CTRL_WOL_RST_SHIFT                         12

/* BRPHY_WOL :: tb_p1_ctrl :: seckey_mode [11:11] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_seckey_mode(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x800,11,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_seckey_mode(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x800,11)
#define BRPHY_WOL_TB_P1_CTRL_SECKEY_MODE_MASK                      0x0800
#define BRPHY_WOL_TB_P1_CTRL_SECKEY_MODE_ALIGN                     0
#define BRPHY_WOL_TB_P1_CTRL_SECKEY_MODE_BITS                      1
#define BRPHY_WOL_TB_P1_CTRL_SECKEY_MODE_SHIFT                     11

/* BRPHY_WOL :: tb_p1_ctrl :: crc_en [10:10] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_crc_en(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x400,10,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_crc_en(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x400,10)
#define BRPHY_WOL_TB_P1_CTRL_CRC_EN_MASK                           0x0400
#define BRPHY_WOL_TB_P1_CTRL_CRC_EN_ALIGN                          0
#define BRPHY_WOL_TB_P1_CTRL_CRC_EN_BITS                           1
#define BRPHY_WOL_TB_P1_CTRL_CRC_EN_SHIFT                          10

/* BRPHY_WOL :: tb_p1_ctrl :: udpport_en [09:09] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_udpport_en(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x200,9,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_udpport_en(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x200,9)
#define BRPHY_WOL_TB_P1_CTRL_UDPPORT_EN_MASK                       0x0200
#define BRPHY_WOL_TB_P1_CTRL_UDPPORT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P1_CTRL_UDPPORT_EN_BITS                       1
#define BRPHY_WOL_TB_P1_CTRL_UDPPORT_EN_SHIFT                      9

/* BRPHY_WOL :: tb_p1_ctrl :: l4ipv6udp_en [08:08] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_l4ipv6udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x100,8,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_l4ipv6udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x100,8)
#define BRPHY_WOL_TB_P1_CTRL_L4IPV6UDP_EN_MASK                     0x0100
#define BRPHY_WOL_TB_P1_CTRL_L4IPV6UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P1_CTRL_L4IPV6UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P1_CTRL_L4IPV6UDP_EN_SHIFT                    8

/* BRPHY_WOL :: tb_p1_ctrl :: l4ipv4udp_en [07:07] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_l4ipv4udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x80,7,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_l4ipv4udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x80,7)
#define BRPHY_WOL_TB_P1_CTRL_L4IPV4UDP_EN_MASK                     0x0080
#define BRPHY_WOL_TB_P1_CTRL_L4IPV4UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P1_CTRL_L4IPV4UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P1_CTRL_L4IPV4UDP_EN_SHIFT                    7

/* BRPHY_WOL :: tb_p1_ctrl :: l2_en [06:06] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_l2_en(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x40,6,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_l2_en(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x40,6)
#define BRPHY_WOL_TB_P1_CTRL_L2_EN_MASK                            0x0040
#define BRPHY_WOL_TB_P1_CTRL_L2_EN_ALIGN                           0
#define BRPHY_WOL_TB_P1_CTRL_L2_EN_BITS                            1
#define BRPHY_WOL_TB_P1_CTRL_L2_EN_SHIFT                           6

/* BRPHY_WOL :: tb_p1_ctrl :: seckey_opt [05:04] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_seckey_opt(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x30,4,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_seckey_opt(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x30,4)
#define BRPHY_WOL_TB_P1_CTRL_SECKEY_OPT_MASK                       0x0030
#define BRPHY_WOL_TB_P1_CTRL_SECKEY_OPT_ALIGN                      0
#define BRPHY_WOL_TB_P1_CTRL_SECKEY_OPT_BITS                       2
#define BRPHY_WOL_TB_P1_CTRL_SECKEY_OPT_SHIFT                      4

/* BRPHY_WOL :: tb_p1_ctrl :: mp_msb_ff_en [03:03] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_mp_msb_ff_en(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x8,3,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_mp_msb_ff_en(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x8,3)
#define BRPHY_WOL_TB_P1_CTRL_MP_MSB_FF_EN_MASK                     0x0008
#define BRPHY_WOL_TB_P1_CTRL_MP_MSB_FF_EN_ALIGN                    0
#define BRPHY_WOL_TB_P1_CTRL_MP_MSB_FF_EN_BITS                     1
#define BRPHY_WOL_TB_P1_CTRL_MP_MSB_FF_EN_SHIFT                    3

/* BRPHY_WOL :: tb_p1_ctrl :: mode [02:01] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_mode(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x6,1,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_mode(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x6,1)
#define BRPHY_WOL_TB_P1_CTRL_MODE_MASK                             0x0006
#define BRPHY_WOL_TB_P1_CTRL_MODE_ALIGN                            0
#define BRPHY_WOL_TB_P1_CTRL_MODE_BITS                             2
#define BRPHY_WOL_TB_P1_CTRL_MODE_SHIFT                            1

/* BRPHY_WOL :: tb_p1_ctrl :: wol_en [00:00] */
#define Wr_BRPHY_WOL_tb_p1_ctrl_wol_en(x) WriteRegBits16(BRPHY_WOL_TB_P1_CTRL,0x1,0,x)
#define Rd_BRPHY_WOL_tb_p1_ctrl_wol_en(x) ReadRegBits16(BRPHY_WOL_TB_P1_CTRL,0x1,0)
#define BRPHY_WOL_TB_P1_CTRL_WOL_EN_MASK                           0x0001
#define BRPHY_WOL_TB_P1_CTRL_WOL_EN_ALIGN                          0
#define BRPHY_WOL_TB_P1_CTRL_WOL_EN_BITS                           1
#define BRPHY_WOL_TB_P1_CTRL_WOL_EN_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_itpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_itpid :: itpid [15:00] */
#define Wr_BRPHY_WOL_tb_p1_itpid_itpid(x) WriteReg16(BRPHY_WOL_TB_P1_ITPID,x)
#define Rd_BRPHY_WOL_tb_p1_itpid_itpid(x) ReadReg16(BRPHY_WOL_TB_P1_ITPID)
#define BRPHY_WOL_TB_P1_ITPID_ITPID_MASK                           0xffff
#define BRPHY_WOL_TB_P1_ITPID_ITPID_ALIGN                          0
#define BRPHY_WOL_TB_P1_ITPID_ITPID_BITS                           16
#define BRPHY_WOL_TB_P1_ITPID_ITPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_otpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_otpid :: otpid [15:00] */
#define Wr_BRPHY_WOL_tb_p1_otpid_otpid(x) WriteReg16(BRPHY_WOL_TB_P1_OTPID,x)
#define Rd_BRPHY_WOL_tb_p1_otpid_otpid(x) ReadReg16(BRPHY_WOL_TB_P1_OTPID)
#define BRPHY_WOL_TB_P1_OTPID_OTPID_MASK                           0xffff
#define BRPHY_WOL_TB_P1_OTPID_OTPID_ALIGN                          0
#define BRPHY_WOL_TB_P1_OTPID_OTPID_BITS                           16
#define BRPHY_WOL_TB_P1_OTPID_OTPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_otpid2
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_otpid2 :: otpid2 [15:00] */
#define Wr_BRPHY_WOL_tb_p1_otpid2_otpid2(x) WriteReg16(BRPHY_WOL_TB_P1_OTPID2,x)
#define Rd_BRPHY_WOL_tb_p1_otpid2_otpid2(x) ReadReg16(BRPHY_WOL_TB_P1_OTPID2)
#define BRPHY_WOL_TB_P1_OTPID2_OTPID2_MASK                         0xffff
#define BRPHY_WOL_TB_P1_OTPID2_OTPID2_ALIGN                        0
#define BRPHY_WOL_TB_P1_OTPID2_OTPID2_BITS                         16
#define BRPHY_WOL_TB_P1_OTPID2_OTPID2_SHIFT                        0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_pkt1_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_pkt1_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_pkt1_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P1_PKT1_15_00,x)
#define Rd_BRPHY_WOL_tb_p1_pkt1_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P1_PKT1_15_00)
#define BRPHY_WOL_TB_P1_PKT1_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P1_PKT1_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P1_PKT1_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P1_PKT1_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_pkt1_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_pkt1_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_pkt1_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P1_PKT1_31_16,x)
#define Rd_BRPHY_WOL_tb_p1_pkt1_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P1_PKT1_31_16)
#define BRPHY_WOL_TB_P1_PKT1_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P1_PKT1_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P1_PKT1_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P1_PKT1_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_pkt1_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_pkt1_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_pkt1_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P1_PKT1_47_32,x)
#define Rd_BRPHY_WOL_tb_p1_pkt1_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P1_PKT1_47_32)
#define BRPHY_WOL_TB_P1_PKT1_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P1_PKT1_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P1_PKT1_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P1_PKT1_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_pkt2_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_pkt2_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_pkt2_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P1_PKT2_15_00,x)
#define Rd_BRPHY_WOL_tb_p1_pkt2_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P1_PKT2_15_00)
#define BRPHY_WOL_TB_P1_PKT2_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P1_PKT2_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P1_PKT2_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P1_PKT2_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_pkt2_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_pkt2_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_pkt2_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P1_PKT2_31_16,x)
#define Rd_BRPHY_WOL_tb_p1_pkt2_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P1_PKT2_31_16)
#define BRPHY_WOL_TB_P1_PKT2_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P1_PKT2_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P1_PKT2_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P1_PKT2_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_pkt2_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_pkt2_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_pkt2_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P1_PKT2_47_32,x)
#define Rd_BRPHY_WOL_tb_p1_pkt2_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P1_PKT2_47_32)
#define BRPHY_WOL_TB_P1_PKT2_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P1_PKT2_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P1_PKT2_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P1_PKT2_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_pkt2_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_pkt2_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_pkt2_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P1_PKT2_63_48,x)
#define Rd_BRPHY_WOL_tb_p1_pkt2_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P1_PKT2_63_48)
#define BRPHY_WOL_TB_P1_PKT2_63_48_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P1_PKT2_63_48_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P1_PKT2_63_48_DATA_BITS                       16
#define BRPHY_WOL_TB_P1_PKT2_63_48_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_mskctr_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_mskctr_15_00 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p1_mskctr_15_00_mask(x) WriteReg16(BRPHY_WOL_TB_P1_MSKCTR_15_00,x)
#define Rd_BRPHY_WOL_tb_p1_mskctr_15_00_mask(x) ReadReg16(BRPHY_WOL_TB_P1_MSKCTR_15_00)
#define BRPHY_WOL_TB_P1_MSKCTR_15_00_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P1_MSKCTR_15_00_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P1_MSKCTR_15_00_MASK_BITS                     16
#define BRPHY_WOL_TB_P1_MSKCTR_15_00_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_mskctr_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_mskctr_31_16 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p1_mskctr_31_16_mask(x) WriteReg16(BRPHY_WOL_TB_P1_MSKCTR_31_16,x)
#define Rd_BRPHY_WOL_tb_p1_mskctr_31_16_mask(x) ReadReg16(BRPHY_WOL_TB_P1_MSKCTR_31_16)
#define BRPHY_WOL_TB_P1_MSKCTR_31_16_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P1_MSKCTR_31_16_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P1_MSKCTR_31_16_MASK_BITS                     16
#define BRPHY_WOL_TB_P1_MSKCTR_31_16_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_mskctr_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_mskctr_47_32 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p1_mskctr_47_32_mask(x) WriteReg16(BRPHY_WOL_TB_P1_MSKCTR_47_32,x)
#define Rd_BRPHY_WOL_tb_p1_mskctr_47_32_mask(x) ReadReg16(BRPHY_WOL_TB_P1_MSKCTR_47_32)
#define BRPHY_WOL_TB_P1_MSKCTR_47_32_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P1_MSKCTR_47_32_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P1_MSKCTR_47_32_MASK_BITS                     16
#define BRPHY_WOL_TB_P1_MSKCTR_47_32_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_seckey_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_seckey_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_seckey_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P1_SECKEY_15_00,x)
#define Rd_BRPHY_WOL_tb_p1_seckey_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P1_SECKEY_15_00)
#define BRPHY_WOL_TB_P1_SECKEY_15_00_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P1_SECKEY_15_00_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P1_SECKEY_15_00_DATA_BITS                     16
#define BRPHY_WOL_TB_P1_SECKEY_15_00_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_seckey_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_seckey_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_seckey_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P1_SECKEY_31_16,x)
#define Rd_BRPHY_WOL_tb_p1_seckey_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P1_SECKEY_31_16)
#define BRPHY_WOL_TB_P1_SECKEY_31_16_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P1_SECKEY_31_16_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P1_SECKEY_31_16_DATA_BITS                     16
#define BRPHY_WOL_TB_P1_SECKEY_31_16_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_seckey_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_seckey_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_seckey_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P1_SECKEY_47_32,x)
#define Rd_BRPHY_WOL_tb_p1_seckey_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P1_SECKEY_47_32)
#define BRPHY_WOL_TB_P1_SECKEY_47_32_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P1_SECKEY_47_32_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P1_SECKEY_47_32_DATA_BITS                     16
#define BRPHY_WOL_TB_P1_SECKEY_47_32_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_seckey_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_seckey_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p1_seckey_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P1_SECKEY_63_48,x)
#define Rd_BRPHY_WOL_tb_p1_seckey_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P1_SECKEY_63_48)
#define BRPHY_WOL_TB_P1_SECKEY_63_48_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P1_SECKEY_63_48_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P1_SECKEY_63_48_DATA_BITS                     16
#define BRPHY_WOL_TB_P1_SECKEY_63_48_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p1_pkt_cnt
 ***************************************************************************/
/* BRPHY_WOL :: tb_p1_pkt_cnt :: reserved0 [15:08] */
#define BRPHY_WOL_TB_P1_PKT_CNT_RESERVED0_MASK                     0xff00
#define BRPHY_WOL_TB_P1_PKT_CNT_RESERVED0_ALIGN                    0
#define BRPHY_WOL_TB_P1_PKT_CNT_RESERVED0_BITS                     8
#define BRPHY_WOL_TB_P1_PKT_CNT_RESERVED0_SHIFT                    8

/* BRPHY_WOL :: tb_p1_pkt_cnt :: counter [07:00] */
#define Wr_BRPHY_WOL_tb_p1_pkt_cnt_counter(x) WriteRegBits16(BRPHY_WOL_TB_P1_PKT_CNT,0xff,0,x)
#define Rd_BRPHY_WOL_tb_p1_pkt_cnt_counter(x) ReadRegBits16(BRPHY_WOL_TB_P1_PKT_CNT,0xff,0)
#define BRPHY_WOL_TB_P1_PKT_CNT_COUNTER_MASK                       0x00ff
#define BRPHY_WOL_TB_P1_PKT_CNT_COUNTER_ALIGN                      0
#define BRPHY_WOL_TB_P1_PKT_CNT_COUNTER_BITS                       8
#define BRPHY_WOL_TB_P1_PKT_CNT_COUNTER_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_ctrl
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_ctrl :: mask_mode [15:14] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_mask_mode(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0xc000,14,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_mask_mode(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0xc000,14)
#define BRPHY_WOL_TB_P2_CTRL_MASK_MODE_MASK                        0xc000
#define BRPHY_WOL_TB_P2_CTRL_MASK_MODE_ALIGN                       0
#define BRPHY_WOL_TB_P2_CTRL_MASK_MODE_BITS                        2
#define BRPHY_WOL_TB_P2_CTRL_MASK_MODE_SHIFT                       14

/* BRPHY_WOL :: tb_p2_ctrl :: dir_pkt_en [13:13] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_dir_pkt_en(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x2000,13,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_dir_pkt_en(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x2000,13)
#define BRPHY_WOL_TB_P2_CTRL_DIR_PKT_EN_MASK                       0x2000
#define BRPHY_WOL_TB_P2_CTRL_DIR_PKT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P2_CTRL_DIR_PKT_EN_BITS                       1
#define BRPHY_WOL_TB_P2_CTRL_DIR_PKT_EN_SHIFT                      13

/* BRPHY_WOL :: tb_p2_ctrl :: wol_rst [12:12] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_wol_rst(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x1000,12,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_wol_rst(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x1000,12)
#define BRPHY_WOL_TB_P2_CTRL_WOL_RST_MASK                          0x1000
#define BRPHY_WOL_TB_P2_CTRL_WOL_RST_ALIGN                         0
#define BRPHY_WOL_TB_P2_CTRL_WOL_RST_BITS                          1
#define BRPHY_WOL_TB_P2_CTRL_WOL_RST_SHIFT                         12

/* BRPHY_WOL :: tb_p2_ctrl :: seckey_mode [11:11] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_seckey_mode(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x800,11,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_seckey_mode(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x800,11)
#define BRPHY_WOL_TB_P2_CTRL_SECKEY_MODE_MASK                      0x0800
#define BRPHY_WOL_TB_P2_CTRL_SECKEY_MODE_ALIGN                     0
#define BRPHY_WOL_TB_P2_CTRL_SECKEY_MODE_BITS                      1
#define BRPHY_WOL_TB_P2_CTRL_SECKEY_MODE_SHIFT                     11

/* BRPHY_WOL :: tb_p2_ctrl :: crc_en [10:10] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_crc_en(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x400,10,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_crc_en(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x400,10)
#define BRPHY_WOL_TB_P2_CTRL_CRC_EN_MASK                           0x0400
#define BRPHY_WOL_TB_P2_CTRL_CRC_EN_ALIGN                          0
#define BRPHY_WOL_TB_P2_CTRL_CRC_EN_BITS                           1
#define BRPHY_WOL_TB_P2_CTRL_CRC_EN_SHIFT                          10

/* BRPHY_WOL :: tb_p2_ctrl :: udpport_en [09:09] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_udpport_en(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x200,9,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_udpport_en(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x200,9)
#define BRPHY_WOL_TB_P2_CTRL_UDPPORT_EN_MASK                       0x0200
#define BRPHY_WOL_TB_P2_CTRL_UDPPORT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P2_CTRL_UDPPORT_EN_BITS                       1
#define BRPHY_WOL_TB_P2_CTRL_UDPPORT_EN_SHIFT                      9

/* BRPHY_WOL :: tb_p2_ctrl :: l4ipv6udp_en [08:08] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_l4ipv6udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x100,8,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_l4ipv6udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x100,8)
#define BRPHY_WOL_TB_P2_CTRL_L4IPV6UDP_EN_MASK                     0x0100
#define BRPHY_WOL_TB_P2_CTRL_L4IPV6UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P2_CTRL_L4IPV6UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P2_CTRL_L4IPV6UDP_EN_SHIFT                    8

/* BRPHY_WOL :: tb_p2_ctrl :: l4ipv4udp_en [07:07] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_l4ipv4udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x80,7,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_l4ipv4udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x80,7)
#define BRPHY_WOL_TB_P2_CTRL_L4IPV4UDP_EN_MASK                     0x0080
#define BRPHY_WOL_TB_P2_CTRL_L4IPV4UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P2_CTRL_L4IPV4UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P2_CTRL_L4IPV4UDP_EN_SHIFT                    7

/* BRPHY_WOL :: tb_p2_ctrl :: l2_en [06:06] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_l2_en(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x40,6,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_l2_en(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x40,6)
#define BRPHY_WOL_TB_P2_CTRL_L2_EN_MASK                            0x0040
#define BRPHY_WOL_TB_P2_CTRL_L2_EN_ALIGN                           0
#define BRPHY_WOL_TB_P2_CTRL_L2_EN_BITS                            1
#define BRPHY_WOL_TB_P2_CTRL_L2_EN_SHIFT                           6

/* BRPHY_WOL :: tb_p2_ctrl :: seckey_opt [05:04] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_seckey_opt(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x30,4,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_seckey_opt(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x30,4)
#define BRPHY_WOL_TB_P2_CTRL_SECKEY_OPT_MASK                       0x0030
#define BRPHY_WOL_TB_P2_CTRL_SECKEY_OPT_ALIGN                      0
#define BRPHY_WOL_TB_P2_CTRL_SECKEY_OPT_BITS                       2
#define BRPHY_WOL_TB_P2_CTRL_SECKEY_OPT_SHIFT                      4

/* BRPHY_WOL :: tb_p2_ctrl :: mp_msb_ff_en [03:03] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_mp_msb_ff_en(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x8,3,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_mp_msb_ff_en(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x8,3)
#define BRPHY_WOL_TB_P2_CTRL_MP_MSB_FF_EN_MASK                     0x0008
#define BRPHY_WOL_TB_P2_CTRL_MP_MSB_FF_EN_ALIGN                    0
#define BRPHY_WOL_TB_P2_CTRL_MP_MSB_FF_EN_BITS                     1
#define BRPHY_WOL_TB_P2_CTRL_MP_MSB_FF_EN_SHIFT                    3

/* BRPHY_WOL :: tb_p2_ctrl :: mode [02:01] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_mode(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x6,1,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_mode(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x6,1)
#define BRPHY_WOL_TB_P2_CTRL_MODE_MASK                             0x0006
#define BRPHY_WOL_TB_P2_CTRL_MODE_ALIGN                            0
#define BRPHY_WOL_TB_P2_CTRL_MODE_BITS                             2
#define BRPHY_WOL_TB_P2_CTRL_MODE_SHIFT                            1

/* BRPHY_WOL :: tb_p2_ctrl :: wol_en [00:00] */
#define Wr_BRPHY_WOL_tb_p2_ctrl_wol_en(x) WriteRegBits16(BRPHY_WOL_TB_P2_CTRL,0x1,0,x)
#define Rd_BRPHY_WOL_tb_p2_ctrl_wol_en(x) ReadRegBits16(BRPHY_WOL_TB_P2_CTRL,0x1,0)
#define BRPHY_WOL_TB_P2_CTRL_WOL_EN_MASK                           0x0001
#define BRPHY_WOL_TB_P2_CTRL_WOL_EN_ALIGN                          0
#define BRPHY_WOL_TB_P2_CTRL_WOL_EN_BITS                           1
#define BRPHY_WOL_TB_P2_CTRL_WOL_EN_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_itpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_itpid :: itpid [15:00] */
#define Wr_BRPHY_WOL_tb_p2_itpid_itpid(x) WriteReg16(BRPHY_WOL_TB_P2_ITPID,x)
#define Rd_BRPHY_WOL_tb_p2_itpid_itpid(x) ReadReg16(BRPHY_WOL_TB_P2_ITPID)
#define BRPHY_WOL_TB_P2_ITPID_ITPID_MASK                           0xffff
#define BRPHY_WOL_TB_P2_ITPID_ITPID_ALIGN                          0
#define BRPHY_WOL_TB_P2_ITPID_ITPID_BITS                           16
#define BRPHY_WOL_TB_P2_ITPID_ITPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_otpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_otpid :: otpid [15:00] */
#define Wr_BRPHY_WOL_tb_p2_otpid_otpid(x) WriteReg16(BRPHY_WOL_TB_P2_OTPID,x)
#define Rd_BRPHY_WOL_tb_p2_otpid_otpid(x) ReadReg16(BRPHY_WOL_TB_P2_OTPID)
#define BRPHY_WOL_TB_P2_OTPID_OTPID_MASK                           0xffff
#define BRPHY_WOL_TB_P2_OTPID_OTPID_ALIGN                          0
#define BRPHY_WOL_TB_P2_OTPID_OTPID_BITS                           16
#define BRPHY_WOL_TB_P2_OTPID_OTPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_otpid2
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_otpid2 :: otpid2 [15:00] */
#define Wr_BRPHY_WOL_tb_p2_otpid2_otpid2(x) WriteReg16(BRPHY_WOL_TB_P2_OTPID2,x)
#define Rd_BRPHY_WOL_tb_p2_otpid2_otpid2(x) ReadReg16(BRPHY_WOL_TB_P2_OTPID2)
#define BRPHY_WOL_TB_P2_OTPID2_OTPID2_MASK                         0xffff
#define BRPHY_WOL_TB_P2_OTPID2_OTPID2_ALIGN                        0
#define BRPHY_WOL_TB_P2_OTPID2_OTPID2_BITS                         16
#define BRPHY_WOL_TB_P2_OTPID2_OTPID2_SHIFT                        0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_pkt1_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_pkt1_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_pkt1_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P2_PKT1_15_00,x)
#define Rd_BRPHY_WOL_tb_p2_pkt1_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P2_PKT1_15_00)
#define BRPHY_WOL_TB_P2_PKT1_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P2_PKT1_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P2_PKT1_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P2_PKT1_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_pkt1_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_pkt1_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_pkt1_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P2_PKT1_31_16,x)
#define Rd_BRPHY_WOL_tb_p2_pkt1_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P2_PKT1_31_16)
#define BRPHY_WOL_TB_P2_PKT1_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P2_PKT1_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P2_PKT1_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P2_PKT1_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_pkt1_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_pkt1_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_pkt1_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P2_PKT1_47_32,x)
#define Rd_BRPHY_WOL_tb_p2_pkt1_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P2_PKT1_47_32)
#define BRPHY_WOL_TB_P2_PKT1_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P2_PKT1_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P2_PKT1_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P2_PKT1_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_pkt2_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_pkt2_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_pkt2_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P2_PKT2_15_00,x)
#define Rd_BRPHY_WOL_tb_p2_pkt2_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P2_PKT2_15_00)
#define BRPHY_WOL_TB_P2_PKT2_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P2_PKT2_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P2_PKT2_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P2_PKT2_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_pkt2_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_pkt2_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_pkt2_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P2_PKT2_31_16,x)
#define Rd_BRPHY_WOL_tb_p2_pkt2_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P2_PKT2_31_16)
#define BRPHY_WOL_TB_P2_PKT2_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P2_PKT2_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P2_PKT2_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P2_PKT2_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_pkt2_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_pkt2_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_pkt2_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P2_PKT2_47_32,x)
#define Rd_BRPHY_WOL_tb_p2_pkt2_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P2_PKT2_47_32)
#define BRPHY_WOL_TB_P2_PKT2_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P2_PKT2_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P2_PKT2_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P2_PKT2_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_pkt2_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_pkt2_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_pkt2_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P2_PKT2_63_48,x)
#define Rd_BRPHY_WOL_tb_p2_pkt2_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P2_PKT2_63_48)
#define BRPHY_WOL_TB_P2_PKT2_63_48_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P2_PKT2_63_48_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P2_PKT2_63_48_DATA_BITS                       16
#define BRPHY_WOL_TB_P2_PKT2_63_48_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_mskctr_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_mskctr_15_00 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p2_mskctr_15_00_mask(x) WriteReg16(BRPHY_WOL_TB_P2_MSKCTR_15_00,x)
#define Rd_BRPHY_WOL_tb_p2_mskctr_15_00_mask(x) ReadReg16(BRPHY_WOL_TB_P2_MSKCTR_15_00)
#define BRPHY_WOL_TB_P2_MSKCTR_15_00_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P2_MSKCTR_15_00_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P2_MSKCTR_15_00_MASK_BITS                     16
#define BRPHY_WOL_TB_P2_MSKCTR_15_00_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_mskctr_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_mskctr_31_16 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p2_mskctr_31_16_mask(x) WriteReg16(BRPHY_WOL_TB_P2_MSKCTR_31_16,x)
#define Rd_BRPHY_WOL_tb_p2_mskctr_31_16_mask(x) ReadReg16(BRPHY_WOL_TB_P2_MSKCTR_31_16)
#define BRPHY_WOL_TB_P2_MSKCTR_31_16_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P2_MSKCTR_31_16_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P2_MSKCTR_31_16_MASK_BITS                     16
#define BRPHY_WOL_TB_P2_MSKCTR_31_16_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_mskctr_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_mskctr_47_32 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p2_mskctr_47_32_mask(x) WriteReg16(BRPHY_WOL_TB_P2_MSKCTR_47_32,x)
#define Rd_BRPHY_WOL_tb_p2_mskctr_47_32_mask(x) ReadReg16(BRPHY_WOL_TB_P2_MSKCTR_47_32)
#define BRPHY_WOL_TB_P2_MSKCTR_47_32_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P2_MSKCTR_47_32_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P2_MSKCTR_47_32_MASK_BITS                     16
#define BRPHY_WOL_TB_P2_MSKCTR_47_32_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_seckey_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_seckey_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_seckey_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P2_SECKEY_15_00,x)
#define Rd_BRPHY_WOL_tb_p2_seckey_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P2_SECKEY_15_00)
#define BRPHY_WOL_TB_P2_SECKEY_15_00_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P2_SECKEY_15_00_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P2_SECKEY_15_00_DATA_BITS                     16
#define BRPHY_WOL_TB_P2_SECKEY_15_00_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_seckey_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_seckey_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_seckey_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P2_SECKEY_31_16,x)
#define Rd_BRPHY_WOL_tb_p2_seckey_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P2_SECKEY_31_16)
#define BRPHY_WOL_TB_P2_SECKEY_31_16_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P2_SECKEY_31_16_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P2_SECKEY_31_16_DATA_BITS                     16
#define BRPHY_WOL_TB_P2_SECKEY_31_16_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_seckey_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_seckey_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_seckey_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P2_SECKEY_47_32,x)
#define Rd_BRPHY_WOL_tb_p2_seckey_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P2_SECKEY_47_32)
#define BRPHY_WOL_TB_P2_SECKEY_47_32_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P2_SECKEY_47_32_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P2_SECKEY_47_32_DATA_BITS                     16
#define BRPHY_WOL_TB_P2_SECKEY_47_32_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_seckey_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_seckey_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p2_seckey_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P2_SECKEY_63_48,x)
#define Rd_BRPHY_WOL_tb_p2_seckey_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P2_SECKEY_63_48)
#define BRPHY_WOL_TB_P2_SECKEY_63_48_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P2_SECKEY_63_48_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P2_SECKEY_63_48_DATA_BITS                     16
#define BRPHY_WOL_TB_P2_SECKEY_63_48_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p2_pkt_cnt
 ***************************************************************************/
/* BRPHY_WOL :: tb_p2_pkt_cnt :: reserved0 [15:08] */
#define BRPHY_WOL_TB_P2_PKT_CNT_RESERVED0_MASK                     0xff00
#define BRPHY_WOL_TB_P2_PKT_CNT_RESERVED0_ALIGN                    0
#define BRPHY_WOL_TB_P2_PKT_CNT_RESERVED0_BITS                     8
#define BRPHY_WOL_TB_P2_PKT_CNT_RESERVED0_SHIFT                    8

/* BRPHY_WOL :: tb_p2_pkt_cnt :: counter [07:00] */
#define Wr_BRPHY_WOL_tb_p2_pkt_cnt_counter(x) WriteRegBits16(BRPHY_WOL_TB_P2_PKT_CNT,0xff,0,x)
#define Rd_BRPHY_WOL_tb_p2_pkt_cnt_counter(x) ReadRegBits16(BRPHY_WOL_TB_P2_PKT_CNT,0xff,0)
#define BRPHY_WOL_TB_P2_PKT_CNT_COUNTER_MASK                       0x00ff
#define BRPHY_WOL_TB_P2_PKT_CNT_COUNTER_ALIGN                      0
#define BRPHY_WOL_TB_P2_PKT_CNT_COUNTER_BITS                       8
#define BRPHY_WOL_TB_P2_PKT_CNT_COUNTER_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_ctrl
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_ctrl :: mask_mode [15:14] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_mask_mode(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0xc000,14,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_mask_mode(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0xc000,14)
#define BRPHY_WOL_TB_P3_CTRL_MASK_MODE_MASK                        0xc000
#define BRPHY_WOL_TB_P3_CTRL_MASK_MODE_ALIGN                       0
#define BRPHY_WOL_TB_P3_CTRL_MASK_MODE_BITS                        2
#define BRPHY_WOL_TB_P3_CTRL_MASK_MODE_SHIFT                       14

/* BRPHY_WOL :: tb_p3_ctrl :: dir_pkt_en [13:13] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_dir_pkt_en(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x2000,13,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_dir_pkt_en(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x2000,13)
#define BRPHY_WOL_TB_P3_CTRL_DIR_PKT_EN_MASK                       0x2000
#define BRPHY_WOL_TB_P3_CTRL_DIR_PKT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P3_CTRL_DIR_PKT_EN_BITS                       1
#define BRPHY_WOL_TB_P3_CTRL_DIR_PKT_EN_SHIFT                      13

/* BRPHY_WOL :: tb_p3_ctrl :: wol_rst [12:12] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_wol_rst(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x1000,12,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_wol_rst(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x1000,12)
#define BRPHY_WOL_TB_P3_CTRL_WOL_RST_MASK                          0x1000
#define BRPHY_WOL_TB_P3_CTRL_WOL_RST_ALIGN                         0
#define BRPHY_WOL_TB_P3_CTRL_WOL_RST_BITS                          1
#define BRPHY_WOL_TB_P3_CTRL_WOL_RST_SHIFT                         12

/* BRPHY_WOL :: tb_p3_ctrl :: seckey_mode [11:11] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_seckey_mode(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x800,11,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_seckey_mode(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x800,11)
#define BRPHY_WOL_TB_P3_CTRL_SECKEY_MODE_MASK                      0x0800
#define BRPHY_WOL_TB_P3_CTRL_SECKEY_MODE_ALIGN                     0
#define BRPHY_WOL_TB_P3_CTRL_SECKEY_MODE_BITS                      1
#define BRPHY_WOL_TB_P3_CTRL_SECKEY_MODE_SHIFT                     11

/* BRPHY_WOL :: tb_p3_ctrl :: crc_en [10:10] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_crc_en(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x400,10,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_crc_en(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x400,10)
#define BRPHY_WOL_TB_P3_CTRL_CRC_EN_MASK                           0x0400
#define BRPHY_WOL_TB_P3_CTRL_CRC_EN_ALIGN                          0
#define BRPHY_WOL_TB_P3_CTRL_CRC_EN_BITS                           1
#define BRPHY_WOL_TB_P3_CTRL_CRC_EN_SHIFT                          10

/* BRPHY_WOL :: tb_p3_ctrl :: udpport_en [09:09] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_udpport_en(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x200,9,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_udpport_en(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x200,9)
#define BRPHY_WOL_TB_P3_CTRL_UDPPORT_EN_MASK                       0x0200
#define BRPHY_WOL_TB_P3_CTRL_UDPPORT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P3_CTRL_UDPPORT_EN_BITS                       1
#define BRPHY_WOL_TB_P3_CTRL_UDPPORT_EN_SHIFT                      9

/* BRPHY_WOL :: tb_p3_ctrl :: l4ipv6udp_en [08:08] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_l4ipv6udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x100,8,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_l4ipv6udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x100,8)
#define BRPHY_WOL_TB_P3_CTRL_L4IPV6UDP_EN_MASK                     0x0100
#define BRPHY_WOL_TB_P3_CTRL_L4IPV6UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P3_CTRL_L4IPV6UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P3_CTRL_L4IPV6UDP_EN_SHIFT                    8

/* BRPHY_WOL :: tb_p3_ctrl :: l4ipv4udp_en [07:07] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_l4ipv4udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x80,7,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_l4ipv4udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x80,7)
#define BRPHY_WOL_TB_P3_CTRL_L4IPV4UDP_EN_MASK                     0x0080
#define BRPHY_WOL_TB_P3_CTRL_L4IPV4UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P3_CTRL_L4IPV4UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P3_CTRL_L4IPV4UDP_EN_SHIFT                    7

/* BRPHY_WOL :: tb_p3_ctrl :: l2_en [06:06] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_l2_en(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x40,6,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_l2_en(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x40,6)
#define BRPHY_WOL_TB_P3_CTRL_L2_EN_MASK                            0x0040
#define BRPHY_WOL_TB_P3_CTRL_L2_EN_ALIGN                           0
#define BRPHY_WOL_TB_P3_CTRL_L2_EN_BITS                            1
#define BRPHY_WOL_TB_P3_CTRL_L2_EN_SHIFT                           6

/* BRPHY_WOL :: tb_p3_ctrl :: seckey_opt [05:04] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_seckey_opt(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x30,4,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_seckey_opt(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x30,4)
#define BRPHY_WOL_TB_P3_CTRL_SECKEY_OPT_MASK                       0x0030
#define BRPHY_WOL_TB_P3_CTRL_SECKEY_OPT_ALIGN                      0
#define BRPHY_WOL_TB_P3_CTRL_SECKEY_OPT_BITS                       2
#define BRPHY_WOL_TB_P3_CTRL_SECKEY_OPT_SHIFT                      4

/* BRPHY_WOL :: tb_p3_ctrl :: mp_msb_ff_en [03:03] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_mp_msb_ff_en(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x8,3,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_mp_msb_ff_en(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x8,3)
#define BRPHY_WOL_TB_P3_CTRL_MP_MSB_FF_EN_MASK                     0x0008
#define BRPHY_WOL_TB_P3_CTRL_MP_MSB_FF_EN_ALIGN                    0
#define BRPHY_WOL_TB_P3_CTRL_MP_MSB_FF_EN_BITS                     1
#define BRPHY_WOL_TB_P3_CTRL_MP_MSB_FF_EN_SHIFT                    3

/* BRPHY_WOL :: tb_p3_ctrl :: mode [02:01] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_mode(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x6,1,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_mode(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x6,1)
#define BRPHY_WOL_TB_P3_CTRL_MODE_MASK                             0x0006
#define BRPHY_WOL_TB_P3_CTRL_MODE_ALIGN                            0
#define BRPHY_WOL_TB_P3_CTRL_MODE_BITS                             2
#define BRPHY_WOL_TB_P3_CTRL_MODE_SHIFT                            1

/* BRPHY_WOL :: tb_p3_ctrl :: wol_en [00:00] */
#define Wr_BRPHY_WOL_tb_p3_ctrl_wol_en(x) WriteRegBits16(BRPHY_WOL_TB_P3_CTRL,0x1,0,x)
#define Rd_BRPHY_WOL_tb_p3_ctrl_wol_en(x) ReadRegBits16(BRPHY_WOL_TB_P3_CTRL,0x1,0)
#define BRPHY_WOL_TB_P3_CTRL_WOL_EN_MASK                           0x0001
#define BRPHY_WOL_TB_P3_CTRL_WOL_EN_ALIGN                          0
#define BRPHY_WOL_TB_P3_CTRL_WOL_EN_BITS                           1
#define BRPHY_WOL_TB_P3_CTRL_WOL_EN_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_itpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_itpid :: itpid [15:00] */
#define Wr_BRPHY_WOL_tb_p3_itpid_itpid(x) WriteReg16(BRPHY_WOL_TB_P3_ITPID,x)
#define Rd_BRPHY_WOL_tb_p3_itpid_itpid(x) ReadReg16(BRPHY_WOL_TB_P3_ITPID)
#define BRPHY_WOL_TB_P3_ITPID_ITPID_MASK                           0xffff
#define BRPHY_WOL_TB_P3_ITPID_ITPID_ALIGN                          0
#define BRPHY_WOL_TB_P3_ITPID_ITPID_BITS                           16
#define BRPHY_WOL_TB_P3_ITPID_ITPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_otpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_otpid :: otpid [15:00] */
#define Wr_BRPHY_WOL_tb_p3_otpid_otpid(x) WriteReg16(BRPHY_WOL_TB_P3_OTPID,x)
#define Rd_BRPHY_WOL_tb_p3_otpid_otpid(x) ReadReg16(BRPHY_WOL_TB_P3_OTPID)
#define BRPHY_WOL_TB_P3_OTPID_OTPID_MASK                           0xffff
#define BRPHY_WOL_TB_P3_OTPID_OTPID_ALIGN                          0
#define BRPHY_WOL_TB_P3_OTPID_OTPID_BITS                           16
#define BRPHY_WOL_TB_P3_OTPID_OTPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_otpid2
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_otpid2 :: otpid2 [15:00] */
#define Wr_BRPHY_WOL_tb_p3_otpid2_otpid2(x) WriteReg16(BRPHY_WOL_TB_P3_OTPID2,x)
#define Rd_BRPHY_WOL_tb_p3_otpid2_otpid2(x) ReadReg16(BRPHY_WOL_TB_P3_OTPID2)
#define BRPHY_WOL_TB_P3_OTPID2_OTPID2_MASK                         0xffff
#define BRPHY_WOL_TB_P3_OTPID2_OTPID2_ALIGN                        0
#define BRPHY_WOL_TB_P3_OTPID2_OTPID2_BITS                         16
#define BRPHY_WOL_TB_P3_OTPID2_OTPID2_SHIFT                        0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_pkt1_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_pkt1_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_pkt1_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P3_PKT1_15_00,x)
#define Rd_BRPHY_WOL_tb_p3_pkt1_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P3_PKT1_15_00)
#define BRPHY_WOL_TB_P3_PKT1_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P3_PKT1_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P3_PKT1_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P3_PKT1_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_pkt1_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_pkt1_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_pkt1_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P3_PKT1_31_16,x)
#define Rd_BRPHY_WOL_tb_p3_pkt1_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P3_PKT1_31_16)
#define BRPHY_WOL_TB_P3_PKT1_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P3_PKT1_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P3_PKT1_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P3_PKT1_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_pkt1_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_pkt1_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_pkt1_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P3_PKT1_47_32,x)
#define Rd_BRPHY_WOL_tb_p3_pkt1_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P3_PKT1_47_32)
#define BRPHY_WOL_TB_P3_PKT1_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P3_PKT1_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P3_PKT1_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P3_PKT1_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_pkt2_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_pkt2_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_pkt2_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P3_PKT2_15_00,x)
#define Rd_BRPHY_WOL_tb_p3_pkt2_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P3_PKT2_15_00)
#define BRPHY_WOL_TB_P3_PKT2_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P3_PKT2_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P3_PKT2_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P3_PKT2_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_pkt2_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_pkt2_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_pkt2_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P3_PKT2_31_16,x)
#define Rd_BRPHY_WOL_tb_p3_pkt2_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P3_PKT2_31_16)
#define BRPHY_WOL_TB_P3_PKT2_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P3_PKT2_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P3_PKT2_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P3_PKT2_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_pkt2_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_pkt2_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_pkt2_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P3_PKT2_47_32,x)
#define Rd_BRPHY_WOL_tb_p3_pkt2_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P3_PKT2_47_32)
#define BRPHY_WOL_TB_P3_PKT2_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P3_PKT2_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P3_PKT2_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P3_PKT2_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_pkt2_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_pkt2_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_pkt2_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P3_PKT2_63_48,x)
#define Rd_BRPHY_WOL_tb_p3_pkt2_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P3_PKT2_63_48)
#define BRPHY_WOL_TB_P3_PKT2_63_48_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P3_PKT2_63_48_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P3_PKT2_63_48_DATA_BITS                       16
#define BRPHY_WOL_TB_P3_PKT2_63_48_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_mskctr_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_mskctr_15_00 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p3_mskctr_15_00_mask(x) WriteReg16(BRPHY_WOL_TB_P3_MSKCTR_15_00,x)
#define Rd_BRPHY_WOL_tb_p3_mskctr_15_00_mask(x) ReadReg16(BRPHY_WOL_TB_P3_MSKCTR_15_00)
#define BRPHY_WOL_TB_P3_MSKCTR_15_00_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P3_MSKCTR_15_00_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P3_MSKCTR_15_00_MASK_BITS                     16
#define BRPHY_WOL_TB_P3_MSKCTR_15_00_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_mskctr_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_mskctr_31_16 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p3_mskctr_31_16_mask(x) WriteReg16(BRPHY_WOL_TB_P3_MSKCTR_31_16,x)
#define Rd_BRPHY_WOL_tb_p3_mskctr_31_16_mask(x) ReadReg16(BRPHY_WOL_TB_P3_MSKCTR_31_16)
#define BRPHY_WOL_TB_P3_MSKCTR_31_16_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P3_MSKCTR_31_16_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P3_MSKCTR_31_16_MASK_BITS                     16
#define BRPHY_WOL_TB_P3_MSKCTR_31_16_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_mskctr_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_mskctr_47_32 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p3_mskctr_47_32_mask(x) WriteReg16(BRPHY_WOL_TB_P3_MSKCTR_47_32,x)
#define Rd_BRPHY_WOL_tb_p3_mskctr_47_32_mask(x) ReadReg16(BRPHY_WOL_TB_P3_MSKCTR_47_32)
#define BRPHY_WOL_TB_P3_MSKCTR_47_32_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P3_MSKCTR_47_32_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P3_MSKCTR_47_32_MASK_BITS                     16
#define BRPHY_WOL_TB_P3_MSKCTR_47_32_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_seckey_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_seckey_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_seckey_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P3_SECKEY_15_00,x)
#define Rd_BRPHY_WOL_tb_p3_seckey_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P3_SECKEY_15_00)
#define BRPHY_WOL_TB_P3_SECKEY_15_00_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P3_SECKEY_15_00_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P3_SECKEY_15_00_DATA_BITS                     16
#define BRPHY_WOL_TB_P3_SECKEY_15_00_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_seckey_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_seckey_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_seckey_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P3_SECKEY_31_16,x)
#define Rd_BRPHY_WOL_tb_p3_seckey_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P3_SECKEY_31_16)
#define BRPHY_WOL_TB_P3_SECKEY_31_16_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P3_SECKEY_31_16_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P3_SECKEY_31_16_DATA_BITS                     16
#define BRPHY_WOL_TB_P3_SECKEY_31_16_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_seckey_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_seckey_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_seckey_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P3_SECKEY_47_32,x)
#define Rd_BRPHY_WOL_tb_p3_seckey_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P3_SECKEY_47_32)
#define BRPHY_WOL_TB_P3_SECKEY_47_32_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P3_SECKEY_47_32_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P3_SECKEY_47_32_DATA_BITS                     16
#define BRPHY_WOL_TB_P3_SECKEY_47_32_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_seckey_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_seckey_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p3_seckey_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P3_SECKEY_63_48,x)
#define Rd_BRPHY_WOL_tb_p3_seckey_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P3_SECKEY_63_48)
#define BRPHY_WOL_TB_P3_SECKEY_63_48_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P3_SECKEY_63_48_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P3_SECKEY_63_48_DATA_BITS                     16
#define BRPHY_WOL_TB_P3_SECKEY_63_48_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p3_pkt_cnt
 ***************************************************************************/
/* BRPHY_WOL :: tb_p3_pkt_cnt :: reserved0 [15:08] */
#define BRPHY_WOL_TB_P3_PKT_CNT_RESERVED0_MASK                     0xff00
#define BRPHY_WOL_TB_P3_PKT_CNT_RESERVED0_ALIGN                    0
#define BRPHY_WOL_TB_P3_PKT_CNT_RESERVED0_BITS                     8
#define BRPHY_WOL_TB_P3_PKT_CNT_RESERVED0_SHIFT                    8

/* BRPHY_WOL :: tb_p3_pkt_cnt :: counter [07:00] */
#define Wr_BRPHY_WOL_tb_p3_pkt_cnt_counter(x) WriteRegBits16(BRPHY_WOL_TB_P3_PKT_CNT,0xff,0,x)
#define Rd_BRPHY_WOL_tb_p3_pkt_cnt_counter(x) ReadRegBits16(BRPHY_WOL_TB_P3_PKT_CNT,0xff,0)
#define BRPHY_WOL_TB_P3_PKT_CNT_COUNTER_MASK                       0x00ff
#define BRPHY_WOL_TB_P3_PKT_CNT_COUNTER_ALIGN                      0
#define BRPHY_WOL_TB_P3_PKT_CNT_COUNTER_BITS                       8
#define BRPHY_WOL_TB_P3_PKT_CNT_COUNTER_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_ctrl
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_ctrl :: mask_mode [15:14] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_mask_mode(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0xc000,14,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_mask_mode(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0xc000,14)
#define BRPHY_WOL_TB_P4_CTRL_MASK_MODE_MASK                        0xc000
#define BRPHY_WOL_TB_P4_CTRL_MASK_MODE_ALIGN                       0
#define BRPHY_WOL_TB_P4_CTRL_MASK_MODE_BITS                        2
#define BRPHY_WOL_TB_P4_CTRL_MASK_MODE_SHIFT                       14

/* BRPHY_WOL :: tb_p4_ctrl :: dir_pkt_en [13:13] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_dir_pkt_en(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x2000,13,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_dir_pkt_en(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x2000,13)
#define BRPHY_WOL_TB_P4_CTRL_DIR_PKT_EN_MASK                       0x2000
#define BRPHY_WOL_TB_P4_CTRL_DIR_PKT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P4_CTRL_DIR_PKT_EN_BITS                       1
#define BRPHY_WOL_TB_P4_CTRL_DIR_PKT_EN_SHIFT                      13

/* BRPHY_WOL :: tb_p4_ctrl :: wol_rst [12:12] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_wol_rst(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x1000,12,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_wol_rst(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x1000,12)
#define BRPHY_WOL_TB_P4_CTRL_WOL_RST_MASK                          0x1000
#define BRPHY_WOL_TB_P4_CTRL_WOL_RST_ALIGN                         0
#define BRPHY_WOL_TB_P4_CTRL_WOL_RST_BITS                          1
#define BRPHY_WOL_TB_P4_CTRL_WOL_RST_SHIFT                         12

/* BRPHY_WOL :: tb_p4_ctrl :: seckey_mode [11:11] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_seckey_mode(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x800,11,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_seckey_mode(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x800,11)
#define BRPHY_WOL_TB_P4_CTRL_SECKEY_MODE_MASK                      0x0800
#define BRPHY_WOL_TB_P4_CTRL_SECKEY_MODE_ALIGN                     0
#define BRPHY_WOL_TB_P4_CTRL_SECKEY_MODE_BITS                      1
#define BRPHY_WOL_TB_P4_CTRL_SECKEY_MODE_SHIFT                     11

/* BRPHY_WOL :: tb_p4_ctrl :: crc_en [10:10] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_crc_en(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x400,10,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_crc_en(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x400,10)
#define BRPHY_WOL_TB_P4_CTRL_CRC_EN_MASK                           0x0400
#define BRPHY_WOL_TB_P4_CTRL_CRC_EN_ALIGN                          0
#define BRPHY_WOL_TB_P4_CTRL_CRC_EN_BITS                           1
#define BRPHY_WOL_TB_P4_CTRL_CRC_EN_SHIFT                          10

/* BRPHY_WOL :: tb_p4_ctrl :: udpport_en [09:09] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_udpport_en(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x200,9,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_udpport_en(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x200,9)
#define BRPHY_WOL_TB_P4_CTRL_UDPPORT_EN_MASK                       0x0200
#define BRPHY_WOL_TB_P4_CTRL_UDPPORT_EN_ALIGN                      0
#define BRPHY_WOL_TB_P4_CTRL_UDPPORT_EN_BITS                       1
#define BRPHY_WOL_TB_P4_CTRL_UDPPORT_EN_SHIFT                      9

/* BRPHY_WOL :: tb_p4_ctrl :: l4ipv6udp_en [08:08] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_l4ipv6udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x100,8,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_l4ipv6udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x100,8)
#define BRPHY_WOL_TB_P4_CTRL_L4IPV6UDP_EN_MASK                     0x0100
#define BRPHY_WOL_TB_P4_CTRL_L4IPV6UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P4_CTRL_L4IPV6UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P4_CTRL_L4IPV6UDP_EN_SHIFT                    8

/* BRPHY_WOL :: tb_p4_ctrl :: l4ipv4udp_en [07:07] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_l4ipv4udp_en(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x80,7,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_l4ipv4udp_en(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x80,7)
#define BRPHY_WOL_TB_P4_CTRL_L4IPV4UDP_EN_MASK                     0x0080
#define BRPHY_WOL_TB_P4_CTRL_L4IPV4UDP_EN_ALIGN                    0
#define BRPHY_WOL_TB_P4_CTRL_L4IPV4UDP_EN_BITS                     1
#define BRPHY_WOL_TB_P4_CTRL_L4IPV4UDP_EN_SHIFT                    7

/* BRPHY_WOL :: tb_p4_ctrl :: l2_en [06:06] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_l2_en(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x40,6,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_l2_en(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x40,6)
#define BRPHY_WOL_TB_P4_CTRL_L2_EN_MASK                            0x0040
#define BRPHY_WOL_TB_P4_CTRL_L2_EN_ALIGN                           0
#define BRPHY_WOL_TB_P4_CTRL_L2_EN_BITS                            1
#define BRPHY_WOL_TB_P4_CTRL_L2_EN_SHIFT                           6

/* BRPHY_WOL :: tb_p4_ctrl :: seckey_opt [05:04] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_seckey_opt(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x30,4,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_seckey_opt(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x30,4)
#define BRPHY_WOL_TB_P4_CTRL_SECKEY_OPT_MASK                       0x0030
#define BRPHY_WOL_TB_P4_CTRL_SECKEY_OPT_ALIGN                      0
#define BRPHY_WOL_TB_P4_CTRL_SECKEY_OPT_BITS                       2
#define BRPHY_WOL_TB_P4_CTRL_SECKEY_OPT_SHIFT                      4

/* BRPHY_WOL :: tb_p4_ctrl :: mp_msb_ff_en [03:03] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_mp_msb_ff_en(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x8,3,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_mp_msb_ff_en(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x8,3)
#define BRPHY_WOL_TB_P4_CTRL_MP_MSB_FF_EN_MASK                     0x0008
#define BRPHY_WOL_TB_P4_CTRL_MP_MSB_FF_EN_ALIGN                    0
#define BRPHY_WOL_TB_P4_CTRL_MP_MSB_FF_EN_BITS                     1
#define BRPHY_WOL_TB_P4_CTRL_MP_MSB_FF_EN_SHIFT                    3

/* BRPHY_WOL :: tb_p4_ctrl :: mode [02:01] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_mode(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x6,1,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_mode(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x6,1)
#define BRPHY_WOL_TB_P4_CTRL_MODE_MASK                             0x0006
#define BRPHY_WOL_TB_P4_CTRL_MODE_ALIGN                            0
#define BRPHY_WOL_TB_P4_CTRL_MODE_BITS                             2
#define BRPHY_WOL_TB_P4_CTRL_MODE_SHIFT                            1

/* BRPHY_WOL :: tb_p4_ctrl :: wol_en [00:00] */
#define Wr_BRPHY_WOL_tb_p4_ctrl_wol_en(x) WriteRegBits16(BRPHY_WOL_TB_P4_CTRL,0x1,0,x)
#define Rd_BRPHY_WOL_tb_p4_ctrl_wol_en(x) ReadRegBits16(BRPHY_WOL_TB_P4_CTRL,0x1,0)
#define BRPHY_WOL_TB_P4_CTRL_WOL_EN_MASK                           0x0001
#define BRPHY_WOL_TB_P4_CTRL_WOL_EN_ALIGN                          0
#define BRPHY_WOL_TB_P4_CTRL_WOL_EN_BITS                           1
#define BRPHY_WOL_TB_P4_CTRL_WOL_EN_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_itpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_itpid :: itpid [15:00] */
#define Wr_BRPHY_WOL_tb_p4_itpid_itpid(x) WriteReg16(BRPHY_WOL_TB_P4_ITPID,x)
#define Rd_BRPHY_WOL_tb_p4_itpid_itpid(x) ReadReg16(BRPHY_WOL_TB_P4_ITPID)
#define BRPHY_WOL_TB_P4_ITPID_ITPID_MASK                           0xffff
#define BRPHY_WOL_TB_P4_ITPID_ITPID_ALIGN                          0
#define BRPHY_WOL_TB_P4_ITPID_ITPID_BITS                           16
#define BRPHY_WOL_TB_P4_ITPID_ITPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_otpid
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_otpid :: otpid [15:00] */
#define Wr_BRPHY_WOL_tb_p4_otpid_otpid(x) WriteReg16(BRPHY_WOL_TB_P4_OTPID,x)
#define Rd_BRPHY_WOL_tb_p4_otpid_otpid(x) ReadReg16(BRPHY_WOL_TB_P4_OTPID)
#define BRPHY_WOL_TB_P4_OTPID_OTPID_MASK                           0xffff
#define BRPHY_WOL_TB_P4_OTPID_OTPID_ALIGN                          0
#define BRPHY_WOL_TB_P4_OTPID_OTPID_BITS                           16
#define BRPHY_WOL_TB_P4_OTPID_OTPID_SHIFT                          0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_otpid2
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_otpid2 :: otpid2 [15:00] */
#define Wr_BRPHY_WOL_tb_p4_otpid2_otpid2(x) WriteReg16(BRPHY_WOL_TB_P4_OTPID2,x)
#define Rd_BRPHY_WOL_tb_p4_otpid2_otpid2(x) ReadReg16(BRPHY_WOL_TB_P4_OTPID2)
#define BRPHY_WOL_TB_P4_OTPID2_OTPID2_MASK                         0xffff
#define BRPHY_WOL_TB_P4_OTPID2_OTPID2_ALIGN                        0
#define BRPHY_WOL_TB_P4_OTPID2_OTPID2_BITS                         16
#define BRPHY_WOL_TB_P4_OTPID2_OTPID2_SHIFT                        0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_pkt1_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_pkt1_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_pkt1_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P4_PKT1_15_00,x)
#define Rd_BRPHY_WOL_tb_p4_pkt1_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P4_PKT1_15_00)
#define BRPHY_WOL_TB_P4_PKT1_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P4_PKT1_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P4_PKT1_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P4_PKT1_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_pkt1_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_pkt1_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_pkt1_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P4_PKT1_31_16,x)
#define Rd_BRPHY_WOL_tb_p4_pkt1_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P4_PKT1_31_16)
#define BRPHY_WOL_TB_P4_PKT1_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P4_PKT1_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P4_PKT1_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P4_PKT1_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_pkt1_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_pkt1_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_pkt1_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P4_PKT1_47_32,x)
#define Rd_BRPHY_WOL_tb_p4_pkt1_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P4_PKT1_47_32)
#define BRPHY_WOL_TB_P4_PKT1_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P4_PKT1_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P4_PKT1_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P4_PKT1_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_pkt2_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_pkt2_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_pkt2_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P4_PKT2_15_00,x)
#define Rd_BRPHY_WOL_tb_p4_pkt2_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P4_PKT2_15_00)
#define BRPHY_WOL_TB_P4_PKT2_15_00_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P4_PKT2_15_00_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P4_PKT2_15_00_DATA_BITS                       16
#define BRPHY_WOL_TB_P4_PKT2_15_00_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_pkt2_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_pkt2_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_pkt2_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P4_PKT2_31_16,x)
#define Rd_BRPHY_WOL_tb_p4_pkt2_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P4_PKT2_31_16)
#define BRPHY_WOL_TB_P4_PKT2_31_16_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P4_PKT2_31_16_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P4_PKT2_31_16_DATA_BITS                       16
#define BRPHY_WOL_TB_P4_PKT2_31_16_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_pkt2_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_pkt2_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_pkt2_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P4_PKT2_47_32,x)
#define Rd_BRPHY_WOL_tb_p4_pkt2_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P4_PKT2_47_32)
#define BRPHY_WOL_TB_P4_PKT2_47_32_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P4_PKT2_47_32_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P4_PKT2_47_32_DATA_BITS                       16
#define BRPHY_WOL_TB_P4_PKT2_47_32_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_pkt2_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_pkt2_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_pkt2_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P4_PKT2_63_48,x)
#define Rd_BRPHY_WOL_tb_p4_pkt2_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P4_PKT2_63_48)
#define BRPHY_WOL_TB_P4_PKT2_63_48_DATA_MASK                       0xffff
#define BRPHY_WOL_TB_P4_PKT2_63_48_DATA_ALIGN                      0
#define BRPHY_WOL_TB_P4_PKT2_63_48_DATA_BITS                       16
#define BRPHY_WOL_TB_P4_PKT2_63_48_DATA_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_mskctr_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_mskctr_15_00 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p4_mskctr_15_00_mask(x) WriteReg16(BRPHY_WOL_TB_P4_MSKCTR_15_00,x)
#define Rd_BRPHY_WOL_tb_p4_mskctr_15_00_mask(x) ReadReg16(BRPHY_WOL_TB_P4_MSKCTR_15_00)
#define BRPHY_WOL_TB_P4_MSKCTR_15_00_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P4_MSKCTR_15_00_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P4_MSKCTR_15_00_MASK_BITS                     16
#define BRPHY_WOL_TB_P4_MSKCTR_15_00_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_mskctr_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_mskctr_31_16 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p4_mskctr_31_16_mask(x) WriteReg16(BRPHY_WOL_TB_P4_MSKCTR_31_16,x)
#define Rd_BRPHY_WOL_tb_p4_mskctr_31_16_mask(x) ReadReg16(BRPHY_WOL_TB_P4_MSKCTR_31_16)
#define BRPHY_WOL_TB_P4_MSKCTR_31_16_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P4_MSKCTR_31_16_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P4_MSKCTR_31_16_MASK_BITS                     16
#define BRPHY_WOL_TB_P4_MSKCTR_31_16_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_mskctr_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_mskctr_47_32 :: mask [15:00] */
#define Wr_BRPHY_WOL_tb_p4_mskctr_47_32_mask(x) WriteReg16(BRPHY_WOL_TB_P4_MSKCTR_47_32,x)
#define Rd_BRPHY_WOL_tb_p4_mskctr_47_32_mask(x) ReadReg16(BRPHY_WOL_TB_P4_MSKCTR_47_32)
#define BRPHY_WOL_TB_P4_MSKCTR_47_32_MASK_MASK                     0xffff
#define BRPHY_WOL_TB_P4_MSKCTR_47_32_MASK_ALIGN                    0
#define BRPHY_WOL_TB_P4_MSKCTR_47_32_MASK_BITS                     16
#define BRPHY_WOL_TB_P4_MSKCTR_47_32_MASK_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_seckey_15_00
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_seckey_15_00 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_seckey_15_00_data(x) WriteReg16(BRPHY_WOL_TB_P4_SECKEY_15_00,x)
#define Rd_BRPHY_WOL_tb_p4_seckey_15_00_data(x) ReadReg16(BRPHY_WOL_TB_P4_SECKEY_15_00)
#define BRPHY_WOL_TB_P4_SECKEY_15_00_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P4_SECKEY_15_00_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P4_SECKEY_15_00_DATA_BITS                     16
#define BRPHY_WOL_TB_P4_SECKEY_15_00_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_seckey_31_16
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_seckey_31_16 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_seckey_31_16_data(x) WriteReg16(BRPHY_WOL_TB_P4_SECKEY_31_16,x)
#define Rd_BRPHY_WOL_tb_p4_seckey_31_16_data(x) ReadReg16(BRPHY_WOL_TB_P4_SECKEY_31_16)
#define BRPHY_WOL_TB_P4_SECKEY_31_16_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P4_SECKEY_31_16_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P4_SECKEY_31_16_DATA_BITS                     16
#define BRPHY_WOL_TB_P4_SECKEY_31_16_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_seckey_47_32
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_seckey_47_32 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_seckey_47_32_data(x) WriteReg16(BRPHY_WOL_TB_P4_SECKEY_47_32,x)
#define Rd_BRPHY_WOL_tb_p4_seckey_47_32_data(x) ReadReg16(BRPHY_WOL_TB_P4_SECKEY_47_32)
#define BRPHY_WOL_TB_P4_SECKEY_47_32_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P4_SECKEY_47_32_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P4_SECKEY_47_32_DATA_BITS                     16
#define BRPHY_WOL_TB_P4_SECKEY_47_32_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_seckey_63_48
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_seckey_63_48 :: data [15:00] */
#define Wr_BRPHY_WOL_tb_p4_seckey_63_48_data(x) WriteReg16(BRPHY_WOL_TB_P4_SECKEY_63_48,x)
#define Rd_BRPHY_WOL_tb_p4_seckey_63_48_data(x) ReadReg16(BRPHY_WOL_TB_P4_SECKEY_63_48)
#define BRPHY_WOL_TB_P4_SECKEY_63_48_DATA_MASK                     0xffff
#define BRPHY_WOL_TB_P4_SECKEY_63_48_DATA_ALIGN                    0
#define BRPHY_WOL_TB_P4_SECKEY_63_48_DATA_BITS                     16
#define BRPHY_WOL_TB_P4_SECKEY_63_48_DATA_SHIFT                    0


/****************************************************************************
 * BRPHY_WOL :: tb_p4_pkt_cnt
 ***************************************************************************/
/* BRPHY_WOL :: tb_p4_pkt_cnt :: reserved0 [15:08] */
#define BRPHY_WOL_TB_P4_PKT_CNT_RESERVED0_MASK                     0xff00
#define BRPHY_WOL_TB_P4_PKT_CNT_RESERVED0_ALIGN                    0
#define BRPHY_WOL_TB_P4_PKT_CNT_RESERVED0_BITS                     8
#define BRPHY_WOL_TB_P4_PKT_CNT_RESERVED0_SHIFT                    8

/* BRPHY_WOL :: tb_p4_pkt_cnt :: counter [07:00] */
#define Wr_BRPHY_WOL_tb_p4_pkt_cnt_counter(x) WriteRegBits16(BRPHY_WOL_TB_P4_PKT_CNT,0xff,0,x)
#define Rd_BRPHY_WOL_tb_p4_pkt_cnt_counter(x) ReadRegBits16(BRPHY_WOL_TB_P4_PKT_CNT,0xff,0)
#define BRPHY_WOL_TB_P4_PKT_CNT_COUNTER_MASK                       0x00ff
#define BRPHY_WOL_TB_P4_PKT_CNT_COUNTER_ALIGN                      0
#define BRPHY_WOL_TB_P4_PKT_CNT_COUNTER_BITS                       8
#define BRPHY_WOL_TB_P4_PKT_CNT_COUNTER_SHIFT                      0


/****************************************************************************
 * BRPHY_WOL :: tb_intr_msk0
 ***************************************************************************/
/* BRPHY_WOL :: tb_intr_msk0 :: reserved0 [15:15] */
#define BRPHY_WOL_TB_INTR_MSK0_RESERVED0_MASK                      0x8000
#define BRPHY_WOL_TB_INTR_MSK0_RESERVED0_ALIGN                     0
#define BRPHY_WOL_TB_INTR_MSK0_RESERVED0_BITS                      1
#define BRPHY_WOL_TB_INTR_MSK0_RESERVED0_SHIFT                     15

/* BRPHY_WOL :: tb_intr_msk0 :: p4_dir_intr_mask [14:14] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p4_dir_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x4000,14,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p4_dir_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x4000,14)
#define BRPHY_WOL_TB_INTR_MSK0_P4_DIR_INTR_MASK_MASK               0x4000
#define BRPHY_WOL_TB_INTR_MSK0_P4_DIR_INTR_MASK_ALIGN              0
#define BRPHY_WOL_TB_INTR_MSK0_P4_DIR_INTR_MASK_BITS               1
#define BRPHY_WOL_TB_INTR_MSK0_P4_DIR_INTR_MASK_SHIFT              14

/* BRPHY_WOL :: tb_intr_msk0 :: p4_pkt2_intr_mask [13:13] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p4_pkt2_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x2000,13,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p4_pkt2_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x2000,13)
#define BRPHY_WOL_TB_INTR_MSK0_P4_PKT2_INTR_MASK_MASK              0x2000
#define BRPHY_WOL_TB_INTR_MSK0_P4_PKT2_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P4_PKT2_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P4_PKT2_INTR_MASK_SHIFT             13

/* BRPHY_WOL :: tb_intr_msk0 :: p4_pkt1_intr_mask [12:12] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p4_pkt1_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x1000,12,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p4_pkt1_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x1000,12)
#define BRPHY_WOL_TB_INTR_MSK0_P4_PKT1_INTR_MASK_MASK              0x1000
#define BRPHY_WOL_TB_INTR_MSK0_P4_PKT1_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P4_PKT1_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P4_PKT1_INTR_MASK_SHIFT             12

/* BRPHY_WOL :: tb_intr_msk0 :: p3_dir_intr_mask [11:11] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p3_dir_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x800,11,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p3_dir_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x800,11)
#define BRPHY_WOL_TB_INTR_MSK0_P3_DIR_INTR_MASK_MASK               0x0800
#define BRPHY_WOL_TB_INTR_MSK0_P3_DIR_INTR_MASK_ALIGN              0
#define BRPHY_WOL_TB_INTR_MSK0_P3_DIR_INTR_MASK_BITS               1
#define BRPHY_WOL_TB_INTR_MSK0_P3_DIR_INTR_MASK_SHIFT              11

/* BRPHY_WOL :: tb_intr_msk0 :: p3_pkt2_intr_mask [10:10] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p3_pkt2_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x400,10,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p3_pkt2_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x400,10)
#define BRPHY_WOL_TB_INTR_MSK0_P3_PKT2_INTR_MASK_MASK              0x0400
#define BRPHY_WOL_TB_INTR_MSK0_P3_PKT2_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P3_PKT2_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P3_PKT2_INTR_MASK_SHIFT             10

/* BRPHY_WOL :: tb_intr_msk0 :: p3_pkt1_intr_mask [09:09] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p3_pkt1_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x200,9,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p3_pkt1_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x200,9)
#define BRPHY_WOL_TB_INTR_MSK0_P3_PKT1_INTR_MASK_MASK              0x0200
#define BRPHY_WOL_TB_INTR_MSK0_P3_PKT1_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P3_PKT1_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P3_PKT1_INTR_MASK_SHIFT             9

/* BRPHY_WOL :: tb_intr_msk0 :: p2_dir_intr_mask [08:08] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p2_dir_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x100,8,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p2_dir_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x100,8)
#define BRPHY_WOL_TB_INTR_MSK0_P2_DIR_INTR_MASK_MASK               0x0100
#define BRPHY_WOL_TB_INTR_MSK0_P2_DIR_INTR_MASK_ALIGN              0
#define BRPHY_WOL_TB_INTR_MSK0_P2_DIR_INTR_MASK_BITS               1
#define BRPHY_WOL_TB_INTR_MSK0_P2_DIR_INTR_MASK_SHIFT              8

/* BRPHY_WOL :: tb_intr_msk0 :: p2_pkt2_intr_mask [07:07] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p2_pkt2_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x80,7,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p2_pkt2_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x80,7)
#define BRPHY_WOL_TB_INTR_MSK0_P2_PKT2_INTR_MASK_MASK              0x0080
#define BRPHY_WOL_TB_INTR_MSK0_P2_PKT2_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P2_PKT2_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P2_PKT2_INTR_MASK_SHIFT             7

/* BRPHY_WOL :: tb_intr_msk0 :: p2_pkt1_intr_mask [06:06] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p2_pkt1_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x40,6,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p2_pkt1_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x40,6)
#define BRPHY_WOL_TB_INTR_MSK0_P2_PKT1_INTR_MASK_MASK              0x0040
#define BRPHY_WOL_TB_INTR_MSK0_P2_PKT1_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P2_PKT1_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P2_PKT1_INTR_MASK_SHIFT             6

/* BRPHY_WOL :: tb_intr_msk0 :: p1_dir_intr_mask [05:05] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p1_dir_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x20,5,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p1_dir_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x20,5)
#define BRPHY_WOL_TB_INTR_MSK0_P1_DIR_INTR_MASK_MASK               0x0020
#define BRPHY_WOL_TB_INTR_MSK0_P1_DIR_INTR_MASK_ALIGN              0
#define BRPHY_WOL_TB_INTR_MSK0_P1_DIR_INTR_MASK_BITS               1
#define BRPHY_WOL_TB_INTR_MSK0_P1_DIR_INTR_MASK_SHIFT              5

/* BRPHY_WOL :: tb_intr_msk0 :: p1_pkt2_intr_mask [04:04] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p1_pkt2_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x10,4,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p1_pkt2_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x10,4)
#define BRPHY_WOL_TB_INTR_MSK0_P1_PKT2_INTR_MASK_MASK              0x0010
#define BRPHY_WOL_TB_INTR_MSK0_P1_PKT2_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P1_PKT2_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P1_PKT2_INTR_MASK_SHIFT             4

/* BRPHY_WOL :: tb_intr_msk0 :: p1_pkt1_intr_mask [03:03] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p1_pkt1_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x8,3,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p1_pkt1_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x8,3)
#define BRPHY_WOL_TB_INTR_MSK0_P1_PKT1_INTR_MASK_MASK              0x0008
#define BRPHY_WOL_TB_INTR_MSK0_P1_PKT1_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P1_PKT1_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P1_PKT1_INTR_MASK_SHIFT             3

/* BRPHY_WOL :: tb_intr_msk0 :: p0_dir_intr_mask [02:02] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p0_dir_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x4,2,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p0_dir_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x4,2)
#define BRPHY_WOL_TB_INTR_MSK0_P0_DIR_INTR_MASK_MASK               0x0004
#define BRPHY_WOL_TB_INTR_MSK0_P0_DIR_INTR_MASK_ALIGN              0
#define BRPHY_WOL_TB_INTR_MSK0_P0_DIR_INTR_MASK_BITS               1
#define BRPHY_WOL_TB_INTR_MSK0_P0_DIR_INTR_MASK_SHIFT              2

/* BRPHY_WOL :: tb_intr_msk0 :: p0_pkt2_intr_mask [01:01] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p0_pkt2_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x2,1,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p0_pkt2_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x2,1)
#define BRPHY_WOL_TB_INTR_MSK0_P0_PKT2_INTR_MASK_MASK              0x0002
#define BRPHY_WOL_TB_INTR_MSK0_P0_PKT2_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P0_PKT2_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P0_PKT2_INTR_MASK_SHIFT             1

/* BRPHY_WOL :: tb_intr_msk0 :: p0_pkt1_intr_mask [00:00] */
#define Wr_BRPHY_WOL_tb_intr_msk0_p0_pkt1_intr_mask(x) WriteRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x1,0,x)
#define Rd_BRPHY_WOL_tb_intr_msk0_p0_pkt1_intr_mask(x) ReadRegBits16(BRPHY_WOL_TB_INTR_MSK0,0x1,0)
#define BRPHY_WOL_TB_INTR_MSK0_P0_PKT1_INTR_MASK_MASK              0x0001
#define BRPHY_WOL_TB_INTR_MSK0_P0_PKT1_INTR_MASK_ALIGN             0
#define BRPHY_WOL_TB_INTR_MSK0_P0_PKT1_INTR_MASK_BITS              1
#define BRPHY_WOL_TB_INTR_MSK0_P0_PKT1_INTR_MASK_SHIFT             0


/****************************************************************************
 * BRPHY_WOL :: tb_intr_sts0
 ***************************************************************************/
/* BRPHY_WOL :: tb_intr_sts0 :: reserved0 [15:15] */
#define BRPHY_WOL_TB_INTR_STS0_RESERVED0_MASK                      0x8000
#define BRPHY_WOL_TB_INTR_STS0_RESERVED0_ALIGN                     0
#define BRPHY_WOL_TB_INTR_STS0_RESERVED0_BITS                      1
#define BRPHY_WOL_TB_INTR_STS0_RESERVED0_SHIFT                     15

/* BRPHY_WOL :: tb_intr_sts0 :: p4_dir_intr [14:14] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p4_dir_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x4000,14,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p4_dir_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x4000,14)
#define BRPHY_WOL_TB_INTR_STS0_P4_DIR_INTR_MASK                    0x4000
#define BRPHY_WOL_TB_INTR_STS0_P4_DIR_INTR_ALIGN                   0
#define BRPHY_WOL_TB_INTR_STS0_P4_DIR_INTR_BITS                    1
#define BRPHY_WOL_TB_INTR_STS0_P4_DIR_INTR_SHIFT                   14

/* BRPHY_WOL :: tb_intr_sts0 :: p4_pkt2_intr [13:13] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p4_pkt2_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x2000,13,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p4_pkt2_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x2000,13)
#define BRPHY_WOL_TB_INTR_STS0_P4_PKT2_INTR_MASK                   0x2000
#define BRPHY_WOL_TB_INTR_STS0_P4_PKT2_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P4_PKT2_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P4_PKT2_INTR_SHIFT                  13

/* BRPHY_WOL :: tb_intr_sts0 :: p4_pkt1_intr [12:12] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p4_pkt1_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x1000,12,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p4_pkt1_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x1000,12)
#define BRPHY_WOL_TB_INTR_STS0_P4_PKT1_INTR_MASK                   0x1000
#define BRPHY_WOL_TB_INTR_STS0_P4_PKT1_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P4_PKT1_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P4_PKT1_INTR_SHIFT                  12

/* BRPHY_WOL :: tb_intr_sts0 :: p3_dir_intr [11:11] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p3_dir_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x800,11,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p3_dir_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x800,11)
#define BRPHY_WOL_TB_INTR_STS0_P3_DIR_INTR_MASK                    0x0800
#define BRPHY_WOL_TB_INTR_STS0_P3_DIR_INTR_ALIGN                   0
#define BRPHY_WOL_TB_INTR_STS0_P3_DIR_INTR_BITS                    1
#define BRPHY_WOL_TB_INTR_STS0_P3_DIR_INTR_SHIFT                   11

/* BRPHY_WOL :: tb_intr_sts0 :: p3_pkt2_intr [10:10] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p3_pkt2_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x400,10,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p3_pkt2_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x400,10)
#define BRPHY_WOL_TB_INTR_STS0_P3_PKT2_INTR_MASK                   0x0400
#define BRPHY_WOL_TB_INTR_STS0_P3_PKT2_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P3_PKT2_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P3_PKT2_INTR_SHIFT                  10

/* BRPHY_WOL :: tb_intr_sts0 :: p3_pkt1_intr [09:09] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p3_pkt1_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x200,9,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p3_pkt1_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x200,9)
#define BRPHY_WOL_TB_INTR_STS0_P3_PKT1_INTR_MASK                   0x0200
#define BRPHY_WOL_TB_INTR_STS0_P3_PKT1_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P3_PKT1_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P3_PKT1_INTR_SHIFT                  9

/* BRPHY_WOL :: tb_intr_sts0 :: p2_dir_intr [08:08] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p2_dir_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x100,8,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p2_dir_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x100,8)
#define BRPHY_WOL_TB_INTR_STS0_P2_DIR_INTR_MASK                    0x0100
#define BRPHY_WOL_TB_INTR_STS0_P2_DIR_INTR_ALIGN                   0
#define BRPHY_WOL_TB_INTR_STS0_P2_DIR_INTR_BITS                    1
#define BRPHY_WOL_TB_INTR_STS0_P2_DIR_INTR_SHIFT                   8

/* BRPHY_WOL :: tb_intr_sts0 :: p2_pkt2_intr [07:07] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p2_pkt2_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x80,7,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p2_pkt2_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x80,7)
#define BRPHY_WOL_TB_INTR_STS0_P2_PKT2_INTR_MASK                   0x0080
#define BRPHY_WOL_TB_INTR_STS0_P2_PKT2_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P2_PKT2_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P2_PKT2_INTR_SHIFT                  7

/* BRPHY_WOL :: tb_intr_sts0 :: p2_pkt1_intr [06:06] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p2_pkt1_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x40,6,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p2_pkt1_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x40,6)
#define BRPHY_WOL_TB_INTR_STS0_P2_PKT1_INTR_MASK                   0x0040
#define BRPHY_WOL_TB_INTR_STS0_P2_PKT1_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P2_PKT1_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P2_PKT1_INTR_SHIFT                  6

/* BRPHY_WOL :: tb_intr_sts0 :: p1_dir_intr [05:05] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p1_dir_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x20,5,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p1_dir_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x20,5)
#define BRPHY_WOL_TB_INTR_STS0_P1_DIR_INTR_MASK                    0x0020
#define BRPHY_WOL_TB_INTR_STS0_P1_DIR_INTR_ALIGN                   0
#define BRPHY_WOL_TB_INTR_STS0_P1_DIR_INTR_BITS                    1
#define BRPHY_WOL_TB_INTR_STS0_P1_DIR_INTR_SHIFT                   5

/* BRPHY_WOL :: tb_intr_sts0 :: p1_pkt2_intr [04:04] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p1_pkt2_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x10,4,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p1_pkt2_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x10,4)
#define BRPHY_WOL_TB_INTR_STS0_P1_PKT2_INTR_MASK                   0x0010
#define BRPHY_WOL_TB_INTR_STS0_P1_PKT2_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P1_PKT2_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P1_PKT2_INTR_SHIFT                  4

/* BRPHY_WOL :: tb_intr_sts0 :: p1_pkt1_intr [03:03] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p1_pkt1_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x8,3,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p1_pkt1_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x8,3)
#define BRPHY_WOL_TB_INTR_STS0_P1_PKT1_INTR_MASK                   0x0008
#define BRPHY_WOL_TB_INTR_STS0_P1_PKT1_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P1_PKT1_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P1_PKT1_INTR_SHIFT                  3

/* BRPHY_WOL :: tb_intr_sts0 :: p0_dir_intr [02:02] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p0_dir_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x4,2,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p0_dir_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x4,2)
#define BRPHY_WOL_TB_INTR_STS0_P0_DIR_INTR_MASK                    0x0004
#define BRPHY_WOL_TB_INTR_STS0_P0_DIR_INTR_ALIGN                   0
#define BRPHY_WOL_TB_INTR_STS0_P0_DIR_INTR_BITS                    1
#define BRPHY_WOL_TB_INTR_STS0_P0_DIR_INTR_SHIFT                   2

/* BRPHY_WOL :: tb_intr_sts0 :: p0_pkt2_intr [01:01] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p0_pkt2_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x2,1,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p0_pkt2_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x2,1)
#define BRPHY_WOL_TB_INTR_STS0_P0_PKT2_INTR_MASK                   0x0002
#define BRPHY_WOL_TB_INTR_STS0_P0_PKT2_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P0_PKT2_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P0_PKT2_INTR_SHIFT                  1

/* BRPHY_WOL :: tb_intr_sts0 :: p0_pkt1_intr [00:00] */
#define Wr_BRPHY_WOL_tb_intr_sts0_p0_pkt1_intr(x) WriteRegBits16(BRPHY_WOL_TB_INTR_STS0,0x1,0,x)
#define Rd_BRPHY_WOL_tb_intr_sts0_p0_pkt1_intr(x) ReadRegBits16(BRPHY_WOL_TB_INTR_STS0,0x1,0)
#define BRPHY_WOL_TB_INTR_STS0_P0_PKT1_INTR_MASK                   0x0001
#define BRPHY_WOL_TB_INTR_STS0_P0_PKT1_INTR_ALIGN                  0
#define BRPHY_WOL_TB_INTR_STS0_P0_PKT1_INTR_BITS                   1
#define BRPHY_WOL_TB_INTR_STS0_P0_PKT1_INTR_SHIFT                  0


/****************************************************************************
 * BRPHY_WOL :: tb_wol_tpo_sel
 ***************************************************************************/
/* BRPHY_WOL :: tb_wol_tpo_sel :: reserved0 [15:03] */
#define BRPHY_WOL_TB_WOL_TPO_SEL_RESERVED0_MASK                    0xfff8
#define BRPHY_WOL_TB_WOL_TPO_SEL_RESERVED0_ALIGN                   0
#define BRPHY_WOL_TB_WOL_TPO_SEL_RESERVED0_BITS                    13
#define BRPHY_WOL_TB_WOL_TPO_SEL_RESERVED0_SHIFT                   3

/* BRPHY_WOL :: tb_wol_tpo_sel :: wol_tpo_sel [02:00] */
#define Wr_BRPHY_WOL_tb_wol_tpo_sel_wol_tpo_sel(x) WriteRegBits16(BRPHY_WOL_TB_WOL_TPO_SEL,0x7,0,x)
#define Rd_BRPHY_WOL_tb_wol_tpo_sel_wol_tpo_sel(x) ReadRegBits16(BRPHY_WOL_TB_WOL_TPO_SEL,0x7,0)
#define BRPHY_WOL_TB_WOL_TPO_SEL_WOL_TPO_SEL_MASK                  0x0007
#define BRPHY_WOL_TB_WOL_TPO_SEL_WOL_TPO_SEL_ALIGN                 0
#define BRPHY_WOL_TB_WOL_TPO_SEL_WOL_TPO_SEL_BITS                  3
#define BRPHY_WOL_TB_WOL_TPO_SEL_WOL_TPO_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY_WOL :: tb_wol_spare
 ***************************************************************************/
/* BRPHY_WOL :: tb_wol_spare :: spare [15:00] */
#define Wr_BRPHY_WOL_tb_wol_spare_spare(x) WriteReg16(BRPHY_WOL_TB_WOL_SPARE,x)
#define Rd_BRPHY_WOL_tb_wol_spare_spare(x) ReadReg16(BRPHY_WOL_TB_WOL_SPARE)
#define BRPHY_WOL_TB_WOL_SPARE_SPARE_MASK                          0xffff
#define BRPHY_WOL_TB_WOL_SPARE_SPARE_ALIGN                         0
#define BRPHY_WOL_TB_WOL_SPARE_SPARE_BITS                          16
#define BRPHY_WOL_TB_WOL_SPARE_SPARE_SHIFT                         0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY_TOP_1588
 ***************************************************************************/
/****************************************************************************
 * BRPHY_TOP_1588 :: SLICE_ENABLE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: SLICE_ENABLE :: RX_SLICE_1588_EN [15:08] */
#define Wr_BRPHY_TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN(x) WriteRegBits16(BRPHY_TOP_1588_SLICE_ENABLE,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN(x) ReadRegBits16(BRPHY_TOP_1588_SLICE_ENABLE,0xff00,8)
#define BRPHY_TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN_MASK          0xff00
#define BRPHY_TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN_ALIGN         0
#define BRPHY_TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN_BITS          8
#define BRPHY_TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN_SHIFT         8

/* BRPHY_TOP_1588 :: SLICE_ENABLE :: TX_SLICE_1588_EN [07:00] */
#define Wr_BRPHY_TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN(x) WriteRegBits16(BRPHY_TOP_1588_SLICE_ENABLE,0xff,0,x)
#define Rd_BRPHY_TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN(x) ReadRegBits16(BRPHY_TOP_1588_SLICE_ENABLE,0xff,0)
#define BRPHY_TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN_MASK          0x00ff
#define BRPHY_TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN_ALIGN         0
#define BRPHY_TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN_BITS          8
#define BRPHY_TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN_SHIFT         0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_MODE_PORT_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0xff00,8)
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE2_BITS                8
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0xc0,6)
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0x30,4,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0x30,4)
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0xc,2,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0xc,2)
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0x3,0,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_0,0x3,0)
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_MODE_PORT_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0xff00,8)
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE2_BITS                8
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0xc0,6)
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0x30,4,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0x30,4)
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0xc,2,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0xc,2)
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0x3,0,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_1,0x3,0)
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_MODE_PORT_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0xff00,8)
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE2_BITS                8
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0xc0,6)
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0x30,4,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0x30,4)
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0xc,2,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0xc,2)
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0x3,0,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_2,0x3,0)
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_MODE_PORT_3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0xff00,8)
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE2_BITS                8
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0xc0,6)
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0x30,4,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0x30,4)
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0xc,2,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0xc,2)
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0x3,0,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_3,0x3,0)
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_MODE_PORT_4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0xff00,8)
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE2_BITS                8
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0xc0,6)
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0x30,4,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0x30,4)
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0xc,2,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0xc,2)
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0x3,0,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_4,0x3,0)
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_MODE_PORT_5
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0xff00,8)
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE2_BITS                8
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0xc0,6)
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0x30,4,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0x30,4)
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0xc,2,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0xc,2)
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0x3,0,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_5,0x3,0)
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_MODE_PORT_6
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0xff00,8)
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE2_BITS                8
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0xc0,6)
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0x30,4,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0x30,4)
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0xc,2,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0xc,2)
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0x3,0,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_6,0x3,0)
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_MODE_PORT_7
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0xff00,8)
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE2_BITS                8
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0xc0,6)
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0x30,4,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0x30,4)
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0xc,2,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0xc,2)
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0x3,0,x)
#define Rd_BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_TX_MODE_PORT_7,0x3,0)
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_MODE_PORT_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0xff00,8)
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE2_BITS                8
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0xc0,6)
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0x30,4,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0x30,4)
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0xc,2,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0xc,2)
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0x3,0,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_0,0x3,0)
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_MODE_PORT_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0xff00,8)
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE2_BITS                8
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0xc0,6)
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0x30,4,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0x30,4)
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0xc,2,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0xc,2)
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0x3,0,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_1,0x3,0)
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_MODE_PORT_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0xff00,8)
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE2_BITS                8
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0xc0,6)
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0x30,4,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0x30,4)
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0xc,2,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0xc,2)
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0x3,0,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_2,0x3,0)
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_MODE_PORT_3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0xff00,8)
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE2_BITS                8
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0xc0,6)
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0x30,4,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0x30,4)
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0xc,2,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0xc,2)
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0x3,0,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_3,0x3,0)
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_MODE_PORT_4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0xff00,8)
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE2_BITS                8
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0xc0,6)
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0x30,4,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0x30,4)
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0xc,2,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0xc,2)
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0x3,0,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_4,0x3,0)
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_MODE_PORT_5
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0xff00,8)
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE2_BITS                8
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0xc0,6)
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0x30,4,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0x30,4)
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0xc,2,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0xc,2)
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0x3,0,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_5,0x3,0)
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_MODE_PORT_6
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0xff00,8)
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE2_BITS                8
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0xc0,6)
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0x30,4,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0x30,4)
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0xc,2,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0xc,2)
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0x3,0,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_6,0x3,0)
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_MODE_PORT_7
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE2 [15:08] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0xff00,8)
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE2_MASK                0xff00
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE2_ALIGN               0
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE2_BITS                8
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE2_SHIFT               8

/* BRPHY_TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE1_M3 [07:06] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0xc0,6,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0xc0,6)
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3_MASK             0x00c0
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3_SHIFT            6

/* BRPHY_TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE1_M2 [05:04] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0x30,4,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0x30,4)
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2_MASK             0x0030
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2_SHIFT            4

/* BRPHY_TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE1_M1 [03:02] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0xc,2,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0xc,2)
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1_MASK             0x000c
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1_SHIFT            2

/* BRPHY_TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE1_M0 [01:00] */
#define Wr_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0(x) WriteRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0x3,0,x)
#define Rd_BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0(x) ReadRegBits16(BRPHY_TOP_1588_RX_MODE_PORT_7,0x3,0)
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0_MASK             0x0003
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0_ALIGN            0
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0_BITS             2
#define BRPHY_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_TS_CAP
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_TS_CAP :: TX_CS_DIS [15:08] */
#define Wr_BRPHY_TOP_1588_TX_TS_CAP_TX_CS_DIS(x) WriteRegBits16(BRPHY_TOP_1588_TX_TS_CAP,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_TS_CAP_TX_CS_DIS(x) ReadRegBits16(BRPHY_TOP_1588_TX_TS_CAP,0xff00,8)
#define BRPHY_TOP_1588_TX_TS_CAP_TX_CS_DIS_MASK                    0xff00
#define BRPHY_TOP_1588_TX_TS_CAP_TX_CS_DIS_ALIGN                   0
#define BRPHY_TOP_1588_TX_TS_CAP_TX_CS_DIS_BITS                    8
#define BRPHY_TOP_1588_TX_TS_CAP_TX_CS_DIS_SHIFT                   8

/* BRPHY_TOP_1588 :: TX_TS_CAP :: TX_TS_CAP [07:00] */
#define Wr_BRPHY_TOP_1588_TX_TS_CAP_TX_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_TX_TS_CAP,0xff,0,x)
#define Rd_BRPHY_TOP_1588_TX_TS_CAP_TX_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_TX_TS_CAP,0xff,0)
#define BRPHY_TOP_1588_TX_TS_CAP_TX_TS_CAP_MASK                    0x00ff
#define BRPHY_TOP_1588_TX_TS_CAP_TX_TS_CAP_ALIGN                   0
#define BRPHY_TOP_1588_TX_TS_CAP_TX_TS_CAP_BITS                    8
#define BRPHY_TOP_1588_TX_TS_CAP_TX_TS_CAP_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_TS_CAP
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_TS_CAP :: RX_CS_DIS [15:08] */
#define Wr_BRPHY_TOP_1588_RX_TS_CAP_RX_CS_DIS(x) WriteRegBits16(BRPHY_TOP_1588_RX_TS_CAP,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_TS_CAP_RX_CS_DIS(x) ReadRegBits16(BRPHY_TOP_1588_RX_TS_CAP,0xff00,8)
#define BRPHY_TOP_1588_RX_TS_CAP_RX_CS_DIS_MASK                    0xff00
#define BRPHY_TOP_1588_RX_TS_CAP_RX_CS_DIS_ALIGN                   0
#define BRPHY_TOP_1588_RX_TS_CAP_RX_CS_DIS_BITS                    8
#define BRPHY_TOP_1588_RX_TS_CAP_RX_CS_DIS_SHIFT                   8

/* BRPHY_TOP_1588 :: RX_TS_CAP :: RX_TS_CAP [07:00] */
#define Wr_BRPHY_TOP_1588_RX_TS_CAP_RX_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_RX_TS_CAP,0xff,0,x)
#define Rd_BRPHY_TOP_1588_RX_TS_CAP_RX_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_RX_TS_CAP,0xff,0)
#define BRPHY_TOP_1588_RX_TS_CAP_RX_TS_CAP_MASK                    0x00ff
#define BRPHY_TOP_1588_RX_TS_CAP_RX_TS_CAP_ALIGN                   0
#define BRPHY_TOP_1588_RX_TS_CAP_RX_TS_CAP_BITS                    8
#define BRPHY_TOP_1588_RX_TS_CAP_RX_TS_CAP_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_TX_OPTION
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_TX_OPTION :: SPARE_REG1 [15:11] */
#define Wr_BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG1(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0xf800,11,x)
#define Rd_BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG1(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0xf800,11)
#define BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG1_MASK                0xf800
#define BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG1_ALIGN               0
#define BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG1_BITS                5
#define BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG1_SHIFT               11

/* BRPHY_TOP_1588 :: RX_TX_OPTION :: RX_PTP_VER_DIS [10:10] */
#define Wr_BRPHY_TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x400,10,x)
#define Rd_BRPHY_TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x400,10)
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS_MASK            0x0400
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS_ALIGN           0
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS_BITS            1
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS_SHIFT           10

/* BRPHY_TOP_1588 :: RX_TX_OPTION :: RX_TIMECODE_ADD_IN [09:09] */
#define Wr_BRPHY_TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x200,9,x)
#define Rd_BRPHY_TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x200,9)
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN_MASK        0x0200
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN_ALIGN       0
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN_BITS        1
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN_SHIFT       9

/* BRPHY_TOP_1588 :: RX_TX_OPTION :: RX_CRC_KEEP [08:08] */
#define Wr_BRPHY_TOP_1588_RX_TX_OPTION_RX_CRC_KEEP(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x100,8,x)
#define Rd_BRPHY_TOP_1588_RX_TX_OPTION_RX_CRC_KEEP(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x100,8)
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_CRC_KEEP_MASK               0x0100
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_CRC_KEEP_ALIGN              0
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_CRC_KEEP_BITS               1
#define BRPHY_TOP_1588_RX_TX_OPTION_RX_CRC_KEEP_SHIFT              8

/* BRPHY_TOP_1588 :: RX_TX_OPTION :: SPARE_REG0 [07:03] */
#define Wr_BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG0(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0xf8,3,x)
#define Rd_BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG0(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0xf8,3)
#define BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG0_MASK                0x00f8
#define BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG0_ALIGN               0
#define BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG0_BITS                5
#define BRPHY_TOP_1588_RX_TX_OPTION_SPARE_REG0_SHIFT               3

/* BRPHY_TOP_1588 :: RX_TX_OPTION :: TX_PTP_VER_DIS [02:02] */
#define Wr_BRPHY_TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x4,2,x)
#define Rd_BRPHY_TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x4,2)
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS_MASK            0x0004
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS_ALIGN           0
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS_BITS            1
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS_SHIFT           2

/* BRPHY_TOP_1588 :: RX_TX_OPTION :: TX_TIMECODE_ADD_IN [01:01] */
#define Wr_BRPHY_TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x2,1,x)
#define Rd_BRPHY_TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x2,1)
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN_MASK        0x0002
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN_ALIGN       0
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN_BITS        1
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN_SHIFT       1

/* BRPHY_TOP_1588 :: RX_TX_OPTION :: TX_CRC_KEEP [00:00] */
#define Wr_BRPHY_TOP_1588_RX_TX_OPTION_TX_CRC_KEEP(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x1,0,x)
#define Rd_BRPHY_TOP_1588_RX_TX_OPTION_TX_CRC_KEEP(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_OPTION,0x1,0)
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_CRC_KEEP_MASK               0x0001
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_CRC_KEEP_ALIGN              0
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_CRC_KEEP_BITS               1
#define BRPHY_TOP_1588_RX_TX_OPTION_TX_CRC_KEEP_SHIFT              0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_0_LINK_DELAY_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_0_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_LSB)
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_0_LINK_DELAY_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_0_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_MSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_MSB)
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_1_LINK_DELAY_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_1_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_LSB)
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_1_LINK_DELAY_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_1_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_MSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_MSB)
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_2_LINK_DELAY_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_2_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_LSB)
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_2_LINK_DELAY_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_2_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_MSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_MSB)
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_3_LINK_DELAY_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_3_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_LSB)
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_3_LINK_DELAY_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_3_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_MSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_MSB)
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_4_LINK_DELAY_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_4_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_LSB)
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_4_LINK_DELAY_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_4_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_MSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_MSB)
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_5_LINK_DELAY_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_5_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_LSB)
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_5_LINK_DELAY_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_5_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_MSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_MSB)
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_6_LINK_DELAY_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_6_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_LSB)
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_6_LINK_DELAY_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_6_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_MSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_MSB)
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_7_LINK_DELAY_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_7_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_LSB)
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_7_LINK_DELAY_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_7_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_MSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_MSB)
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_0_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_0_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS 16
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_0_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_0_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: TX_PORT_0_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: TX_PORT_0_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS 4
#define BRPHY_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_1_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_1_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS 16
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_1_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_1_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: TX_PORT_1_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: TX_PORT_1_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS 4
#define BRPHY_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_2_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_2_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS 16
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_2_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_2_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: TX_PORT_2_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: TX_PORT_2_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS 4
#define BRPHY_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_3_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_3_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS 16
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_3_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_3_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: TX_PORT_3_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: TX_PORT_3_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS 4
#define BRPHY_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_4_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_4_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS 16
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_4_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_4_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: TX_PORT_4_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: TX_PORT_4_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS 4
#define BRPHY_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_5_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_5_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS 16
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_5_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_5_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: TX_PORT_5_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: TX_PORT_5_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS 4
#define BRPHY_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_6_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_6_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS 16
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_6_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_6_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: TX_PORT_6_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: TX_PORT_6_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS 4
#define BRPHY_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_7_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_7_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS 16
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_PORT_7_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_PORT_7_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: TX_PORT_7_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: TX_PORT_7_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN 0
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS 4
#define BRPHY_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_0_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_0_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_0_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_0_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: RX_PORT_0_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: RX_PORT_0_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS 4
#define BRPHY_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_1_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_1_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_1_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_1_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: RX_PORT_1_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: RX_PORT_1_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS 4
#define BRPHY_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_2_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_2_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_2_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_2_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: RX_PORT_2_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: RX_PORT_2_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS 4
#define BRPHY_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_3_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_3_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_3_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_3_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: RX_PORT_3_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: RX_PORT_3_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS 4
#define BRPHY_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_4_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_4_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_4_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_4_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: RX_PORT_4_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: RX_PORT_4_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS 4
#define BRPHY_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_5_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_5_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_5_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_5_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: RX_PORT_5_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: RX_PORT_5_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS 4
#define BRPHY_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_6_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_6_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_6_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_6_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: RX_PORT_6_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: RX_PORT_6_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS 4
#define BRPHY_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_7_TS_OFFSET_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_7_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_LSB,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_LSB)
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK 0xffff
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS 16
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_PORT_7_TS_OFFSET_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_PORT_7_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xff00,8)
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP_MASK         0xff00
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP_ALIGN        0
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP_BITS         8
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP_SHIFT        8

/* BRPHY_TOP_1588 :: RX_PORT_7_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xf0,4)
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD_MASK          0x00f0
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD_ALIGN         0
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD_BITS          4
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD_SHIFT         4

/* BRPHY_TOP_1588 :: RX_PORT_7_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xf,0,x)
#define Rd_BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xf,0)
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK 0x000f
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN 0
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS 4
#define BRPHY_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_CODE_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_CODE_0 :: TIME_CODE_0 [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_CODE_0_TIME_CODE_0(x) WriteReg16(BRPHY_TOP_1588_TIME_CODE_0,x)
#define Rd_BRPHY_TOP_1588_TIME_CODE_0_TIME_CODE_0(x) ReadReg16(BRPHY_TOP_1588_TIME_CODE_0)
#define BRPHY_TOP_1588_TIME_CODE_0_TIME_CODE_0_MASK                0xffff
#define BRPHY_TOP_1588_TIME_CODE_0_TIME_CODE_0_ALIGN               0
#define BRPHY_TOP_1588_TIME_CODE_0_TIME_CODE_0_BITS                16
#define BRPHY_TOP_1588_TIME_CODE_0_TIME_CODE_0_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_CODE_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_CODE_1 :: TIME_CODE_1 [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_CODE_1_TIME_CODE_1(x) WriteReg16(BRPHY_TOP_1588_TIME_CODE_1,x)
#define Rd_BRPHY_TOP_1588_TIME_CODE_1_TIME_CODE_1(x) ReadReg16(BRPHY_TOP_1588_TIME_CODE_1)
#define BRPHY_TOP_1588_TIME_CODE_1_TIME_CODE_1_MASK                0xffff
#define BRPHY_TOP_1588_TIME_CODE_1_TIME_CODE_1_ALIGN               0
#define BRPHY_TOP_1588_TIME_CODE_1_TIME_CODE_1_BITS                16
#define BRPHY_TOP_1588_TIME_CODE_1_TIME_CODE_1_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_CODE_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_CODE_2 :: TIME_CODE_2 [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_CODE_2_TIME_CODE_2(x) WriteReg16(BRPHY_TOP_1588_TIME_CODE_2,x)
#define Rd_BRPHY_TOP_1588_TIME_CODE_2_TIME_CODE_2(x) ReadReg16(BRPHY_TOP_1588_TIME_CODE_2)
#define BRPHY_TOP_1588_TIME_CODE_2_TIME_CODE_2_MASK                0xffff
#define BRPHY_TOP_1588_TIME_CODE_2_TIME_CODE_2_ALIGN               0
#define BRPHY_TOP_1588_TIME_CODE_2_TIME_CODE_2_BITS                16
#define BRPHY_TOP_1588_TIME_CODE_2_TIME_CODE_2_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_CODE_3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_CODE_3 :: TIME_CODE_3 [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_CODE_3_TIME_CODE_3(x) WriteReg16(BRPHY_TOP_1588_TIME_CODE_3,x)
#define Rd_BRPHY_TOP_1588_TIME_CODE_3_TIME_CODE_3(x) ReadReg16(BRPHY_TOP_1588_TIME_CODE_3)
#define BRPHY_TOP_1588_TIME_CODE_3_TIME_CODE_3_MASK                0xffff
#define BRPHY_TOP_1588_TIME_CODE_3_TIME_CODE_3_ALIGN               0
#define BRPHY_TOP_1588_TIME_CODE_3_TIME_CODE_3_BITS                16
#define BRPHY_TOP_1588_TIME_CODE_3_TIME_CODE_3_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_CODE_4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_CODE_4 :: TIME_CODE_4 [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_CODE_4_TIME_CODE_4(x) WriteReg16(BRPHY_TOP_1588_TIME_CODE_4,x)
#define Rd_BRPHY_TOP_1588_TIME_CODE_4_TIME_CODE_4(x) ReadReg16(BRPHY_TOP_1588_TIME_CODE_4)
#define BRPHY_TOP_1588_TIME_CODE_4_TIME_CODE_4_MASK                0xffff
#define BRPHY_TOP_1588_TIME_CODE_4_TIME_CODE_4_ALIGN               0
#define BRPHY_TOP_1588_TIME_CODE_4_TIME_CODE_4_BITS                16
#define BRPHY_TOP_1588_TIME_CODE_4_TIME_CODE_4_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DPLL_DB_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DPLL_DB_LSB :: DPLL_DB_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB(x) WriteReg16(BRPHY_TOP_1588_DPLL_DB_LSB,x)
#define Rd_BRPHY_TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB(x) ReadReg16(BRPHY_TOP_1588_DPLL_DB_LSB)
#define BRPHY_TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB_MASK                0xffff
#define BRPHY_TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB_ALIGN               0
#define BRPHY_TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB_BITS                16
#define BRPHY_TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DPLL_DB_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DPLL_DB_MSB :: DPLL_DB_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB(x) WriteReg16(BRPHY_TOP_1588_DPLL_DB_MSB,x)
#define Rd_BRPHY_TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB(x) ReadReg16(BRPHY_TOP_1588_DPLL_DB_MSB)
#define BRPHY_TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB_MASK                0xffff
#define BRPHY_TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB_ALIGN               0
#define BRPHY_TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB_BITS                16
#define BRPHY_TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DPLL_DB_SEL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DPLL_DB_SEL :: SPARE_REG [15:01] */
#define Wr_BRPHY_TOP_1588_DPLL_DB_SEL_SPARE_REG(x) WriteRegBits16(BRPHY_TOP_1588_DPLL_DB_SEL,0xfffe,1,x)
#define Rd_BRPHY_TOP_1588_DPLL_DB_SEL_SPARE_REG(x) ReadRegBits16(BRPHY_TOP_1588_DPLL_DB_SEL,0xfffe,1)
#define BRPHY_TOP_1588_DPLL_DB_SEL_SPARE_REG_MASK                  0xfffe
#define BRPHY_TOP_1588_DPLL_DB_SEL_SPARE_REG_ALIGN                 0
#define BRPHY_TOP_1588_DPLL_DB_SEL_SPARE_REG_BITS                  15
#define BRPHY_TOP_1588_DPLL_DB_SEL_SPARE_REG_SHIFT                 1

/* BRPHY_TOP_1588 :: DPLL_DB_SEL :: DPLL_DB_SEL [00:00] */
#define Wr_BRPHY_TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL(x) WriteRegBits16(BRPHY_TOP_1588_DPLL_DB_SEL,0x1,0,x)
#define Rd_BRPHY_TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL(x) ReadRegBits16(BRPHY_TOP_1588_DPLL_DB_SEL,0x1,0)
#define BRPHY_TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL_MASK                0x0001
#define BRPHY_TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL_ALIGN               0
#define BRPHY_TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL_BITS                1
#define BRPHY_TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: SHD_CTL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: SHD_CTL :: F16_C [15:15] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F16_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x8000,15,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F16_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x8000,15)
#define BRPHY_TOP_1588_SHD_CTL_F16_C_MASK                          0x8000
#define BRPHY_TOP_1588_SHD_CTL_F16_C_ALIGN                         0
#define BRPHY_TOP_1588_SHD_CTL_F16_C_BITS                          1
#define BRPHY_TOP_1588_SHD_CTL_F16_C_SHIFT                         15

/* BRPHY_TOP_1588 :: SHD_CTL :: F15_C [14:14] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F15_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x4000,14,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F15_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x4000,14)
#define BRPHY_TOP_1588_SHD_CTL_F15_C_MASK                          0x4000
#define BRPHY_TOP_1588_SHD_CTL_F15_C_ALIGN                         0
#define BRPHY_TOP_1588_SHD_CTL_F15_C_BITS                          1
#define BRPHY_TOP_1588_SHD_CTL_F15_C_SHIFT                         14

/* BRPHY_TOP_1588 :: SHD_CTL :: F14_C [13:13] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F14_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x2000,13,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F14_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x2000,13)
#define BRPHY_TOP_1588_SHD_CTL_F14_C_MASK                          0x2000
#define BRPHY_TOP_1588_SHD_CTL_F14_C_ALIGN                         0
#define BRPHY_TOP_1588_SHD_CTL_F14_C_BITS                          1
#define BRPHY_TOP_1588_SHD_CTL_F14_C_SHIFT                         13

/* BRPHY_TOP_1588 :: SHD_CTL :: F13_C [12:12] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F13_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x1000,12,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F13_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x1000,12)
#define BRPHY_TOP_1588_SHD_CTL_F13_C_MASK                          0x1000
#define BRPHY_TOP_1588_SHD_CTL_F13_C_ALIGN                         0
#define BRPHY_TOP_1588_SHD_CTL_F13_C_BITS                          1
#define BRPHY_TOP_1588_SHD_CTL_F13_C_SHIFT                         12

/* BRPHY_TOP_1588 :: SHD_CTL :: F12_C [11:11] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F12_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x800,11,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F12_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x800,11)
#define BRPHY_TOP_1588_SHD_CTL_F12_C_MASK                          0x0800
#define BRPHY_TOP_1588_SHD_CTL_F12_C_ALIGN                         0
#define BRPHY_TOP_1588_SHD_CTL_F12_C_BITS                          1
#define BRPHY_TOP_1588_SHD_CTL_F12_C_SHIFT                         11

/* BRPHY_TOP_1588 :: SHD_CTL :: F11_C [10:10] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F11_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x400,10,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F11_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x400,10)
#define BRPHY_TOP_1588_SHD_CTL_F11_C_MASK                          0x0400
#define BRPHY_TOP_1588_SHD_CTL_F11_C_ALIGN                         0
#define BRPHY_TOP_1588_SHD_CTL_F11_C_BITS                          1
#define BRPHY_TOP_1588_SHD_CTL_F11_C_SHIFT                         10

/* BRPHY_TOP_1588 :: SHD_CTL :: F10_C [09:09] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F10_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x200,9,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F10_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x200,9)
#define BRPHY_TOP_1588_SHD_CTL_F10_C_MASK                          0x0200
#define BRPHY_TOP_1588_SHD_CTL_F10_C_ALIGN                         0
#define BRPHY_TOP_1588_SHD_CTL_F10_C_BITS                          1
#define BRPHY_TOP_1588_SHD_CTL_F10_C_SHIFT                         9

/* BRPHY_TOP_1588 :: SHD_CTL :: F9_C [08:08] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F9_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x100,8,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F9_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x100,8)
#define BRPHY_TOP_1588_SHD_CTL_F9_C_MASK                           0x0100
#define BRPHY_TOP_1588_SHD_CTL_F9_C_ALIGN                          0
#define BRPHY_TOP_1588_SHD_CTL_F9_C_BITS                           1
#define BRPHY_TOP_1588_SHD_CTL_F9_C_SHIFT                          8

/* BRPHY_TOP_1588 :: SHD_CTL :: F8_C [07:07] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F8_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x80,7,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F8_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x80,7)
#define BRPHY_TOP_1588_SHD_CTL_F8_C_MASK                           0x0080
#define BRPHY_TOP_1588_SHD_CTL_F8_C_ALIGN                          0
#define BRPHY_TOP_1588_SHD_CTL_F8_C_BITS                           1
#define BRPHY_TOP_1588_SHD_CTL_F8_C_SHIFT                          7

/* BRPHY_TOP_1588 :: SHD_CTL :: F7_C [06:06] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F7_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x40,6,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F7_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x40,6)
#define BRPHY_TOP_1588_SHD_CTL_F7_C_MASK                           0x0040
#define BRPHY_TOP_1588_SHD_CTL_F7_C_ALIGN                          0
#define BRPHY_TOP_1588_SHD_CTL_F7_C_BITS                           1
#define BRPHY_TOP_1588_SHD_CTL_F7_C_SHIFT                          6

/* BRPHY_TOP_1588 :: SHD_CTL :: F6_C [05:05] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F6_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x20,5,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F6_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x20,5)
#define BRPHY_TOP_1588_SHD_CTL_F6_C_MASK                           0x0020
#define BRPHY_TOP_1588_SHD_CTL_F6_C_ALIGN                          0
#define BRPHY_TOP_1588_SHD_CTL_F6_C_BITS                           1
#define BRPHY_TOP_1588_SHD_CTL_F6_C_SHIFT                          5

/* BRPHY_TOP_1588 :: SHD_CTL :: F5_C [04:04] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F5_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x10,4,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F5_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x10,4)
#define BRPHY_TOP_1588_SHD_CTL_F5_C_MASK                           0x0010
#define BRPHY_TOP_1588_SHD_CTL_F5_C_ALIGN                          0
#define BRPHY_TOP_1588_SHD_CTL_F5_C_BITS                           1
#define BRPHY_TOP_1588_SHD_CTL_F5_C_SHIFT                          4

/* BRPHY_TOP_1588 :: SHD_CTL :: F4_C [03:03] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F4_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x8,3,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F4_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x8,3)
#define BRPHY_TOP_1588_SHD_CTL_F4_C_MASK                           0x0008
#define BRPHY_TOP_1588_SHD_CTL_F4_C_ALIGN                          0
#define BRPHY_TOP_1588_SHD_CTL_F4_C_BITS                           1
#define BRPHY_TOP_1588_SHD_CTL_F4_C_SHIFT                          3

/* BRPHY_TOP_1588 :: SHD_CTL :: F3_C [02:02] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F3_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x4,2,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F3_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x4,2)
#define BRPHY_TOP_1588_SHD_CTL_F3_C_MASK                           0x0004
#define BRPHY_TOP_1588_SHD_CTL_F3_C_ALIGN                          0
#define BRPHY_TOP_1588_SHD_CTL_F3_C_BITS                           1
#define BRPHY_TOP_1588_SHD_CTL_F3_C_SHIFT                          2

/* BRPHY_TOP_1588 :: SHD_CTL :: F2_C [01:01] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F2_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x2,1,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F2_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x2,1)
#define BRPHY_TOP_1588_SHD_CTL_F2_C_MASK                           0x0002
#define BRPHY_TOP_1588_SHD_CTL_F2_C_ALIGN                          0
#define BRPHY_TOP_1588_SHD_CTL_F2_C_BITS                           1
#define BRPHY_TOP_1588_SHD_CTL_F2_C_SHIFT                          1

/* BRPHY_TOP_1588 :: SHD_CTL :: F1_C [00:00] */
#define Wr_BRPHY_TOP_1588_SHD_CTL_F1_C(x) WriteRegBits16(BRPHY_TOP_1588_SHD_CTL,0x1,0,x)
#define Rd_BRPHY_TOP_1588_SHD_CTL_F1_C(x) ReadRegBits16(BRPHY_TOP_1588_SHD_CTL,0x1,0)
#define BRPHY_TOP_1588_SHD_CTL_F1_C_MASK                           0x0001
#define BRPHY_TOP_1588_SHD_CTL_F1_C_ALIGN                          0
#define BRPHY_TOP_1588_SHD_CTL_F1_C_BITS                           1
#define BRPHY_TOP_1588_SHD_CTL_F1_C_SHIFT                          0


/****************************************************************************
 * BRPHY_TOP_1588 :: SHD_LD
 ***************************************************************************/
/* BRPHY_TOP_1588 :: SHD_LD :: F16_L [15:15] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F16_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x8000,15,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F16_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x8000,15)
#define BRPHY_TOP_1588_SHD_LD_F16_L_MASK                           0x8000
#define BRPHY_TOP_1588_SHD_LD_F16_L_ALIGN                          0
#define BRPHY_TOP_1588_SHD_LD_F16_L_BITS                           1
#define BRPHY_TOP_1588_SHD_LD_F16_L_SHIFT                          15

/* BRPHY_TOP_1588 :: SHD_LD :: F15_L [14:14] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F15_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x4000,14,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F15_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x4000,14)
#define BRPHY_TOP_1588_SHD_LD_F15_L_MASK                           0x4000
#define BRPHY_TOP_1588_SHD_LD_F15_L_ALIGN                          0
#define BRPHY_TOP_1588_SHD_LD_F15_L_BITS                           1
#define BRPHY_TOP_1588_SHD_LD_F15_L_SHIFT                          14

/* BRPHY_TOP_1588 :: SHD_LD :: F14_L [13:13] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F14_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x2000,13,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F14_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x2000,13)
#define BRPHY_TOP_1588_SHD_LD_F14_L_MASK                           0x2000
#define BRPHY_TOP_1588_SHD_LD_F14_L_ALIGN                          0
#define BRPHY_TOP_1588_SHD_LD_F14_L_BITS                           1
#define BRPHY_TOP_1588_SHD_LD_F14_L_SHIFT                          13

/* BRPHY_TOP_1588 :: SHD_LD :: F13_L [12:12] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F13_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x1000,12,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F13_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x1000,12)
#define BRPHY_TOP_1588_SHD_LD_F13_L_MASK                           0x1000
#define BRPHY_TOP_1588_SHD_LD_F13_L_ALIGN                          0
#define BRPHY_TOP_1588_SHD_LD_F13_L_BITS                           1
#define BRPHY_TOP_1588_SHD_LD_F13_L_SHIFT                          12

/* BRPHY_TOP_1588 :: SHD_LD :: F12_L [11:11] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F12_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x800,11,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F12_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x800,11)
#define BRPHY_TOP_1588_SHD_LD_F12_L_MASK                           0x0800
#define BRPHY_TOP_1588_SHD_LD_F12_L_ALIGN                          0
#define BRPHY_TOP_1588_SHD_LD_F12_L_BITS                           1
#define BRPHY_TOP_1588_SHD_LD_F12_L_SHIFT                          11

/* BRPHY_TOP_1588 :: SHD_LD :: F11_L [10:10] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F11_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x400,10,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F11_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x400,10)
#define BRPHY_TOP_1588_SHD_LD_F11_L_MASK                           0x0400
#define BRPHY_TOP_1588_SHD_LD_F11_L_ALIGN                          0
#define BRPHY_TOP_1588_SHD_LD_F11_L_BITS                           1
#define BRPHY_TOP_1588_SHD_LD_F11_L_SHIFT                          10

/* BRPHY_TOP_1588 :: SHD_LD :: F10_L [09:09] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F10_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x200,9,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F10_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x200,9)
#define BRPHY_TOP_1588_SHD_LD_F10_L_MASK                           0x0200
#define BRPHY_TOP_1588_SHD_LD_F10_L_ALIGN                          0
#define BRPHY_TOP_1588_SHD_LD_F10_L_BITS                           1
#define BRPHY_TOP_1588_SHD_LD_F10_L_SHIFT                          9

/* BRPHY_TOP_1588 :: SHD_LD :: F9_L [08:08] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F9_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x100,8,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F9_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x100,8)
#define BRPHY_TOP_1588_SHD_LD_F9_L_MASK                            0x0100
#define BRPHY_TOP_1588_SHD_LD_F9_L_ALIGN                           0
#define BRPHY_TOP_1588_SHD_LD_F9_L_BITS                            1
#define BRPHY_TOP_1588_SHD_LD_F9_L_SHIFT                           8

/* BRPHY_TOP_1588 :: SHD_LD :: F8_L [07:07] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F8_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x80,7,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F8_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x80,7)
#define BRPHY_TOP_1588_SHD_LD_F8_L_MASK                            0x0080
#define BRPHY_TOP_1588_SHD_LD_F8_L_ALIGN                           0
#define BRPHY_TOP_1588_SHD_LD_F8_L_BITS                            1
#define BRPHY_TOP_1588_SHD_LD_F8_L_SHIFT                           7

/* BRPHY_TOP_1588 :: SHD_LD :: F7_L [06:06] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F7_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x40,6,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F7_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x40,6)
#define BRPHY_TOP_1588_SHD_LD_F7_L_MASK                            0x0040
#define BRPHY_TOP_1588_SHD_LD_F7_L_ALIGN                           0
#define BRPHY_TOP_1588_SHD_LD_F7_L_BITS                            1
#define BRPHY_TOP_1588_SHD_LD_F7_L_SHIFT                           6

/* BRPHY_TOP_1588 :: SHD_LD :: F6_L [05:05] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F6_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x20,5,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F6_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x20,5)
#define BRPHY_TOP_1588_SHD_LD_F6_L_MASK                            0x0020
#define BRPHY_TOP_1588_SHD_LD_F6_L_ALIGN                           0
#define BRPHY_TOP_1588_SHD_LD_F6_L_BITS                            1
#define BRPHY_TOP_1588_SHD_LD_F6_L_SHIFT                           5

/* BRPHY_TOP_1588 :: SHD_LD :: F5_L [04:04] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F5_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x10,4,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F5_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x10,4)
#define BRPHY_TOP_1588_SHD_LD_F5_L_MASK                            0x0010
#define BRPHY_TOP_1588_SHD_LD_F5_L_ALIGN                           0
#define BRPHY_TOP_1588_SHD_LD_F5_L_BITS                            1
#define BRPHY_TOP_1588_SHD_LD_F5_L_SHIFT                           4

/* BRPHY_TOP_1588 :: SHD_LD :: F4_L [03:03] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F4_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x8,3,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F4_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x8,3)
#define BRPHY_TOP_1588_SHD_LD_F4_L_MASK                            0x0008
#define BRPHY_TOP_1588_SHD_LD_F4_L_ALIGN                           0
#define BRPHY_TOP_1588_SHD_LD_F4_L_BITS                            1
#define BRPHY_TOP_1588_SHD_LD_F4_L_SHIFT                           3

/* BRPHY_TOP_1588 :: SHD_LD :: F3_L [02:02] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F3_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x4,2,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F3_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x4,2)
#define BRPHY_TOP_1588_SHD_LD_F3_L_MASK                            0x0004
#define BRPHY_TOP_1588_SHD_LD_F3_L_ALIGN                           0
#define BRPHY_TOP_1588_SHD_LD_F3_L_BITS                            1
#define BRPHY_TOP_1588_SHD_LD_F3_L_SHIFT                           2

/* BRPHY_TOP_1588 :: SHD_LD :: F2_L [01:01] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F2_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x2,1,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F2_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x2,1)
#define BRPHY_TOP_1588_SHD_LD_F2_L_MASK                            0x0002
#define BRPHY_TOP_1588_SHD_LD_F2_L_ALIGN                           0
#define BRPHY_TOP_1588_SHD_LD_F2_L_BITS                            1
#define BRPHY_TOP_1588_SHD_LD_F2_L_SHIFT                           1

/* BRPHY_TOP_1588 :: SHD_LD :: F1_L [00:00] */
#define Wr_BRPHY_TOP_1588_SHD_LD_F1_L(x) WriteRegBits16(BRPHY_TOP_1588_SHD_LD,0x1,0,x)
#define Rd_BRPHY_TOP_1588_SHD_LD_F1_L(x) ReadRegBits16(BRPHY_TOP_1588_SHD_LD,0x1,0)
#define BRPHY_TOP_1588_SHD_LD_F1_L_MASK                            0x0001
#define BRPHY_TOP_1588_SHD_LD_F1_L_ALIGN                           0
#define BRPHY_TOP_1588_SHD_LD_F1_L_BITS                            1
#define BRPHY_TOP_1588_SHD_LD_F1_L_SHIFT                           0


/****************************************************************************
 * BRPHY_TOP_1588 :: INT_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INT_MASK :: reserved0 [15:11] */
#define BRPHY_TOP_1588_INT_MASK_RESERVED0_MASK                     0xf800
#define BRPHY_TOP_1588_INT_MASK_RESERVED0_ALIGN                    0
#define BRPHY_TOP_1588_INT_MASK_RESERVED0_BITS                     5
#define BRPHY_TOP_1588_INT_MASK_RESERVED0_SHIFT                    11

/* BRPHY_TOP_1588 :: INT_MASK :: SPARE_REG [10:09] */
#define Wr_BRPHY_TOP_1588_INT_MASK_SPARE_REG(x) WriteRegBits16(BRPHY_TOP_1588_INT_MASK,0x600,9,x)
#define Rd_BRPHY_TOP_1588_INT_MASK_SPARE_REG(x) ReadRegBits16(BRPHY_TOP_1588_INT_MASK,0x600,9)
#define BRPHY_TOP_1588_INT_MASK_SPARE_REG_MASK                     0x0600
#define BRPHY_TOP_1588_INT_MASK_SPARE_REG_ALIGN                    0
#define BRPHY_TOP_1588_INT_MASK_SPARE_REG_BITS                     2
#define BRPHY_TOP_1588_INT_MASK_SPARE_REG_SHIFT                    9

/* BRPHY_TOP_1588 :: INT_MASK :: INTC_SOP_MASK [08:01] */
#define Wr_BRPHY_TOP_1588_INT_MASK_INTC_SOP_MASK(x) WriteRegBits16(BRPHY_TOP_1588_INT_MASK,0x1fe,1,x)
#define Rd_BRPHY_TOP_1588_INT_MASK_INTC_SOP_MASK(x) ReadRegBits16(BRPHY_TOP_1588_INT_MASK,0x1fe,1)
#define BRPHY_TOP_1588_INT_MASK_INTC_SOP_MASK_MASK                 0x01fe
#define BRPHY_TOP_1588_INT_MASK_INTC_SOP_MASK_ALIGN                0
#define BRPHY_TOP_1588_INT_MASK_INTC_SOP_MASK_BITS                 8
#define BRPHY_TOP_1588_INT_MASK_INTC_SOP_MASK_SHIFT                1

/* BRPHY_TOP_1588 :: INT_MASK :: INTC_FSYNC_MASK [00:00] */
#define Wr_BRPHY_TOP_1588_INT_MASK_INTC_FSYNC_MASK(x) WriteRegBits16(BRPHY_TOP_1588_INT_MASK,0x1,0,x)
#define Rd_BRPHY_TOP_1588_INT_MASK_INTC_FSYNC_MASK(x) ReadRegBits16(BRPHY_TOP_1588_INT_MASK,0x1,0)
#define BRPHY_TOP_1588_INT_MASK_INTC_FSYNC_MASK_MASK               0x0001
#define BRPHY_TOP_1588_INT_MASK_INTC_FSYNC_MASK_ALIGN              0
#define BRPHY_TOP_1588_INT_MASK_INTC_FSYNC_MASK_BITS               1
#define BRPHY_TOP_1588_INT_MASK_INTC_FSYNC_MASK_SHIFT              0


/****************************************************************************
 * BRPHY_TOP_1588 :: INT_STAT
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INT_STAT :: reserved0 [15:11] */
#define BRPHY_TOP_1588_INT_STAT_RESERVED0_MASK                     0xf800
#define BRPHY_TOP_1588_INT_STAT_RESERVED0_ALIGN                    0
#define BRPHY_TOP_1588_INT_STAT_RESERVED0_BITS                     5
#define BRPHY_TOP_1588_INT_STAT_RESERVED0_SHIFT                    11

/* BRPHY_TOP_1588 :: INT_STAT :: INTC_RESERVED [10:09] */
#define Wr_BRPHY_TOP_1588_INT_STAT_INTC_RESERVED(x) WriteRegBits16(BRPHY_TOP_1588_INT_STAT,0x600,9,x)
#define Rd_BRPHY_TOP_1588_INT_STAT_INTC_RESERVED(x) ReadRegBits16(BRPHY_TOP_1588_INT_STAT,0x600,9)
#define BRPHY_TOP_1588_INT_STAT_INTC_RESERVED_MASK                 0x0600
#define BRPHY_TOP_1588_INT_STAT_INTC_RESERVED_ALIGN                0
#define BRPHY_TOP_1588_INT_STAT_INTC_RESERVED_BITS                 2
#define BRPHY_TOP_1588_INT_STAT_INTC_RESERVED_SHIFT                9

/* BRPHY_TOP_1588 :: INT_STAT :: INTC_SOP [08:01] */
#define Wr_BRPHY_TOP_1588_INT_STAT_INTC_SOP(x) WriteRegBits16(BRPHY_TOP_1588_INT_STAT,0x1fe,1,x)
#define Rd_BRPHY_TOP_1588_INT_STAT_INTC_SOP(x) ReadRegBits16(BRPHY_TOP_1588_INT_STAT,0x1fe,1)
#define BRPHY_TOP_1588_INT_STAT_INTC_SOP_MASK                      0x01fe
#define BRPHY_TOP_1588_INT_STAT_INTC_SOP_ALIGN                     0
#define BRPHY_TOP_1588_INT_STAT_INTC_SOP_BITS                      8
#define BRPHY_TOP_1588_INT_STAT_INTC_SOP_SHIFT                     1

/* BRPHY_TOP_1588 :: INT_STAT :: INTC_FSYNC [00:00] */
#define Wr_BRPHY_TOP_1588_INT_STAT_INTC_FSYNC(x) WriteRegBits16(BRPHY_TOP_1588_INT_STAT,0x1,0,x)
#define Rd_BRPHY_TOP_1588_INT_STAT_INTC_FSYNC(x) ReadRegBits16(BRPHY_TOP_1588_INT_STAT,0x1,0)
#define BRPHY_TOP_1588_INT_STAT_INTC_FSYNC_MASK                    0x0001
#define BRPHY_TOP_1588_INT_STAT_INTC_FSYNC_ALIGN                   0
#define BRPHY_TOP_1588_INT_STAT_INTC_FSYNC_BITS                    1
#define BRPHY_TOP_1588_INT_STAT_INTC_FSYNC_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_CTL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_CTL :: TX_OFFSET [15:08] */
#define Wr_BRPHY_TOP_1588_TX_CTL_TX_OFFSET(x) WriteRegBits16(BRPHY_TOP_1588_TX_CTL,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_TX_CTL_TX_OFFSET(x) ReadRegBits16(BRPHY_TOP_1588_TX_CTL,0xff00,8)
#define BRPHY_TOP_1588_TX_CTL_TX_OFFSET_MASK                       0xff00
#define BRPHY_TOP_1588_TX_CTL_TX_OFFSET_ALIGN                      0
#define BRPHY_TOP_1588_TX_CTL_TX_OFFSET_BITS                       8
#define BRPHY_TOP_1588_TX_CTL_TX_OFFSET_SHIFT                      8

/* BRPHY_TOP_1588 :: TX_CTL :: TX_AS_DS_EN [07:07] */
#define Wr_BRPHY_TOP_1588_TX_CTL_TX_AS_DS_EN(x) WriteRegBits16(BRPHY_TOP_1588_TX_CTL,0x80,7,x)
#define Rd_BRPHY_TOP_1588_TX_CTL_TX_AS_DS_EN(x) ReadRegBits16(BRPHY_TOP_1588_TX_CTL,0x80,7)
#define BRPHY_TOP_1588_TX_CTL_TX_AS_DS_EN_MASK                     0x0080
#define BRPHY_TOP_1588_TX_CTL_TX_AS_DS_EN_ALIGN                    0
#define BRPHY_TOP_1588_TX_CTL_TX_AS_DS_EN_BITS                     1
#define BRPHY_TOP_1588_TX_CTL_TX_AS_DS_EN_SHIFT                    7

/* BRPHY_TOP_1588 :: TX_CTL :: TX_L2_DS_EN [06:06] */
#define Wr_BRPHY_TOP_1588_TX_CTL_TX_L2_DS_EN(x) WriteRegBits16(BRPHY_TOP_1588_TX_CTL,0x40,6,x)
#define Rd_BRPHY_TOP_1588_TX_CTL_TX_L2_DS_EN(x) ReadRegBits16(BRPHY_TOP_1588_TX_CTL,0x40,6)
#define BRPHY_TOP_1588_TX_CTL_TX_L2_DS_EN_MASK                     0x0040
#define BRPHY_TOP_1588_TX_CTL_TX_L2_DS_EN_ALIGN                    0
#define BRPHY_TOP_1588_TX_CTL_TX_L2_DS_EN_BITS                     1
#define BRPHY_TOP_1588_TX_CTL_TX_L2_DS_EN_SHIFT                    6

/* BRPHY_TOP_1588 :: TX_CTL :: TX_L4_IP_ADDRESS_EN [05:05] */
#define Wr_BRPHY_TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN(x) WriteRegBits16(BRPHY_TOP_1588_TX_CTL,0x20,5,x)
#define Rd_BRPHY_TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN(x) ReadRegBits16(BRPHY_TOP_1588_TX_CTL,0x20,5)
#define BRPHY_TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN_MASK             0x0020
#define BRPHY_TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN_ALIGN            0
#define BRPHY_TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN_BITS             1
#define BRPHY_TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN_SHIFT            5

/* BRPHY_TOP_1588 :: TX_CTL :: TX_L4_IPV6_ADDRESS_EN [04:04] */
#define Wr_BRPHY_TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN(x) WriteRegBits16(BRPHY_TOP_1588_TX_CTL,0x10,4,x)
#define Rd_BRPHY_TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN(x) ReadRegBits16(BRPHY_TOP_1588_TX_CTL,0x10,4)
#define BRPHY_TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN_MASK           0x0010
#define BRPHY_TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN_ALIGN          0
#define BRPHY_TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN_BITS           1
#define BRPHY_TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN_SHIFT          4

/* BRPHY_TOP_1588 :: TX_CTL :: TX_AS_EN [03:03] */
#define Wr_BRPHY_TOP_1588_TX_CTL_TX_AS_EN(x) WriteRegBits16(BRPHY_TOP_1588_TX_CTL,0x8,3,x)
#define Rd_BRPHY_TOP_1588_TX_CTL_TX_AS_EN(x) ReadRegBits16(BRPHY_TOP_1588_TX_CTL,0x8,3)
#define BRPHY_TOP_1588_TX_CTL_TX_AS_EN_MASK                        0x0008
#define BRPHY_TOP_1588_TX_CTL_TX_AS_EN_ALIGN                       0
#define BRPHY_TOP_1588_TX_CTL_TX_AS_EN_BITS                        1
#define BRPHY_TOP_1588_TX_CTL_TX_AS_EN_SHIFT                       3

/* BRPHY_TOP_1588 :: TX_CTL :: TX_L2_EN [02:02] */
#define Wr_BRPHY_TOP_1588_TX_CTL_TX_L2_EN(x) WriteRegBits16(BRPHY_TOP_1588_TX_CTL,0x4,2,x)
#define Rd_BRPHY_TOP_1588_TX_CTL_TX_L2_EN(x) ReadRegBits16(BRPHY_TOP_1588_TX_CTL,0x4,2)
#define BRPHY_TOP_1588_TX_CTL_TX_L2_EN_MASK                        0x0004
#define BRPHY_TOP_1588_TX_CTL_TX_L2_EN_ALIGN                       0
#define BRPHY_TOP_1588_TX_CTL_TX_L2_EN_BITS                        1
#define BRPHY_TOP_1588_TX_CTL_TX_L2_EN_SHIFT                       2

/* BRPHY_TOP_1588 :: TX_CTL :: TX_IPV4_UDP_EN [01:01] */
#define Wr_BRPHY_TOP_1588_TX_CTL_TX_IPV4_UDP_EN(x) WriteRegBits16(BRPHY_TOP_1588_TX_CTL,0x2,1,x)
#define Rd_BRPHY_TOP_1588_TX_CTL_TX_IPV4_UDP_EN(x) ReadRegBits16(BRPHY_TOP_1588_TX_CTL,0x2,1)
#define BRPHY_TOP_1588_TX_CTL_TX_IPV4_UDP_EN_MASK                  0x0002
#define BRPHY_TOP_1588_TX_CTL_TX_IPV4_UDP_EN_ALIGN                 0
#define BRPHY_TOP_1588_TX_CTL_TX_IPV4_UDP_EN_BITS                  1
#define BRPHY_TOP_1588_TX_CTL_TX_IPV4_UDP_EN_SHIFT                 1

/* BRPHY_TOP_1588 :: TX_CTL :: TX_IPV6_UDP_EN [00:00] */
#define Wr_BRPHY_TOP_1588_TX_CTL_TX_IPV6_UDP_EN(x) WriteRegBits16(BRPHY_TOP_1588_TX_CTL,0x1,0,x)
#define Rd_BRPHY_TOP_1588_TX_CTL_TX_IPV6_UDP_EN(x) ReadRegBits16(BRPHY_TOP_1588_TX_CTL,0x1,0)
#define BRPHY_TOP_1588_TX_CTL_TX_IPV6_UDP_EN_MASK                  0x0001
#define BRPHY_TOP_1588_TX_CTL_TX_IPV6_UDP_EN_ALIGN                 0
#define BRPHY_TOP_1588_TX_CTL_TX_IPV6_UDP_EN_BITS                  1
#define BRPHY_TOP_1588_TX_CTL_TX_IPV6_UDP_EN_SHIFT                 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_CTL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_CTL :: RX_OFFSET [15:08] */
#define Wr_BRPHY_TOP_1588_RX_CTL_RX_OFFSET(x) WriteRegBits16(BRPHY_TOP_1588_RX_CTL,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_CTL_RX_OFFSET(x) ReadRegBits16(BRPHY_TOP_1588_RX_CTL,0xff00,8)
#define BRPHY_TOP_1588_RX_CTL_RX_OFFSET_MASK                       0xff00
#define BRPHY_TOP_1588_RX_CTL_RX_OFFSET_ALIGN                      0
#define BRPHY_TOP_1588_RX_CTL_RX_OFFSET_BITS                       8
#define BRPHY_TOP_1588_RX_CTL_RX_OFFSET_SHIFT                      8

/* BRPHY_TOP_1588 :: RX_CTL :: RX_AS_DS_EN [07:07] */
#define Wr_BRPHY_TOP_1588_RX_CTL_RX_AS_DS_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_CTL,0x80,7,x)
#define Rd_BRPHY_TOP_1588_RX_CTL_RX_AS_DS_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_CTL,0x80,7)
#define BRPHY_TOP_1588_RX_CTL_RX_AS_DS_EN_MASK                     0x0080
#define BRPHY_TOP_1588_RX_CTL_RX_AS_DS_EN_ALIGN                    0
#define BRPHY_TOP_1588_RX_CTL_RX_AS_DS_EN_BITS                     1
#define BRPHY_TOP_1588_RX_CTL_RX_AS_DS_EN_SHIFT                    7

/* BRPHY_TOP_1588 :: RX_CTL :: RX_L2_DS_EN [06:06] */
#define Wr_BRPHY_TOP_1588_RX_CTL_RX_L2_DS_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_CTL,0x40,6,x)
#define Rd_BRPHY_TOP_1588_RX_CTL_RX_L2_DS_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_CTL,0x40,6)
#define BRPHY_TOP_1588_RX_CTL_RX_L2_DS_EN_MASK                     0x0040
#define BRPHY_TOP_1588_RX_CTL_RX_L2_DS_EN_ALIGN                    0
#define BRPHY_TOP_1588_RX_CTL_RX_L2_DS_EN_BITS                     1
#define BRPHY_TOP_1588_RX_CTL_RX_L2_DS_EN_SHIFT                    6

/* BRPHY_TOP_1588 :: RX_CTL :: RX_L4_IP_ADDRESS_EN [05:05] */
#define Wr_BRPHY_TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_CTL,0x20,5,x)
#define Rd_BRPHY_TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_CTL,0x20,5)
#define BRPHY_TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN_MASK             0x0020
#define BRPHY_TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN_ALIGN            0
#define BRPHY_TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN_BITS             1
#define BRPHY_TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN_SHIFT            5

/* BRPHY_TOP_1588 :: RX_CTL :: RX_L4_IPV6_ADDRESS_EN [04:04] */
#define Wr_BRPHY_TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_CTL,0x10,4,x)
#define Rd_BRPHY_TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_CTL,0x10,4)
#define BRPHY_TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN_MASK           0x0010
#define BRPHY_TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN_ALIGN          0
#define BRPHY_TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN_BITS           1
#define BRPHY_TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN_SHIFT          4

/* BRPHY_TOP_1588 :: RX_CTL :: RX_AS_EN [03:03] */
#define Wr_BRPHY_TOP_1588_RX_CTL_RX_AS_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_CTL,0x8,3,x)
#define Rd_BRPHY_TOP_1588_RX_CTL_RX_AS_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_CTL,0x8,3)
#define BRPHY_TOP_1588_RX_CTL_RX_AS_EN_MASK                        0x0008
#define BRPHY_TOP_1588_RX_CTL_RX_AS_EN_ALIGN                       0
#define BRPHY_TOP_1588_RX_CTL_RX_AS_EN_BITS                        1
#define BRPHY_TOP_1588_RX_CTL_RX_AS_EN_SHIFT                       3

/* BRPHY_TOP_1588 :: RX_CTL :: RX_L2_EN [02:02] */
#define Wr_BRPHY_TOP_1588_RX_CTL_RX_L2_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_CTL,0x4,2,x)
#define Rd_BRPHY_TOP_1588_RX_CTL_RX_L2_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_CTL,0x4,2)
#define BRPHY_TOP_1588_RX_CTL_RX_L2_EN_MASK                        0x0004
#define BRPHY_TOP_1588_RX_CTL_RX_L2_EN_ALIGN                       0
#define BRPHY_TOP_1588_RX_CTL_RX_L2_EN_BITS                        1
#define BRPHY_TOP_1588_RX_CTL_RX_L2_EN_SHIFT                       2

/* BRPHY_TOP_1588 :: RX_CTL :: RX_IPV4_UDP_EN [01:01] */
#define Wr_BRPHY_TOP_1588_RX_CTL_RX_IPV4_UDP_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_CTL,0x2,1,x)
#define Rd_BRPHY_TOP_1588_RX_CTL_RX_IPV4_UDP_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_CTL,0x2,1)
#define BRPHY_TOP_1588_RX_CTL_RX_IPV4_UDP_EN_MASK                  0x0002
#define BRPHY_TOP_1588_RX_CTL_RX_IPV4_UDP_EN_ALIGN                 0
#define BRPHY_TOP_1588_RX_CTL_RX_IPV4_UDP_EN_BITS                  1
#define BRPHY_TOP_1588_RX_CTL_RX_IPV4_UDP_EN_SHIFT                 1

/* BRPHY_TOP_1588 :: RX_CTL :: RX_IPV6_UDP_EN [00:00] */
#define Wr_BRPHY_TOP_1588_RX_CTL_RX_IPV6_UDP_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_CTL,0x1,0,x)
#define Rd_BRPHY_TOP_1588_RX_CTL_RX_IPV6_UDP_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_CTL,0x1,0)
#define BRPHY_TOP_1588_RX_CTL_RX_IPV6_UDP_EN_MASK                  0x0001
#define BRPHY_TOP_1588_RX_CTL_RX_IPV6_UDP_EN_ALIGN                 0
#define BRPHY_TOP_1588_RX_CTL_RX_IPV6_UDP_EN_BITS                  1
#define BRPHY_TOP_1588_RX_CTL_RX_IPV6_UDP_EN_SHIFT                 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_TX_CTL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_TX_CTL :: reserved0 [15:08] */
#define BRPHY_TOP_1588_RX_TX_CTL_RESERVED0_MASK                    0xff00
#define BRPHY_TOP_1588_RX_TX_CTL_RESERVED0_ALIGN                   0
#define BRPHY_TOP_1588_RX_TX_CTL_RESERVED0_BITS                    8
#define BRPHY_TOP_1588_RX_TX_CTL_RESERVED0_SHIFT                   8

/* BRPHY_TOP_1588 :: RX_TX_CTL :: TX_CRC_EN [07:07] */
#define Wr_BRPHY_TOP_1588_RX_TX_CTL_TX_CRC_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_CTL,0x80,7,x)
#define Rd_BRPHY_TOP_1588_RX_TX_CTL_TX_CRC_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_CTL,0x80,7)
#define BRPHY_TOP_1588_RX_TX_CTL_TX_CRC_EN_MASK                    0x0080
#define BRPHY_TOP_1588_RX_TX_CTL_TX_CRC_EN_ALIGN                   0
#define BRPHY_TOP_1588_RX_TX_CTL_TX_CRC_EN_BITS                    1
#define BRPHY_TOP_1588_RX_TX_CTL_TX_CRC_EN_SHIFT                   7

/* BRPHY_TOP_1588 :: RX_TX_CTL :: TX_L4_IP_ADDRESS_SEL [06:04] */
#define Wr_BRPHY_TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_CTL,0x70,4,x)
#define Rd_BRPHY_TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_CTL,0x70,4)
#define BRPHY_TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL_MASK         0x0070
#define BRPHY_TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL_ALIGN        0
#define BRPHY_TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL_BITS         3
#define BRPHY_TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL_SHIFT        4

/* BRPHY_TOP_1588 :: RX_TX_CTL :: RX_CRC_EN [03:03] */
#define Wr_BRPHY_TOP_1588_RX_TX_CTL_RX_CRC_EN(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_CTL,0x8,3,x)
#define Rd_BRPHY_TOP_1588_RX_TX_CTL_RX_CRC_EN(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_CTL,0x8,3)
#define BRPHY_TOP_1588_RX_TX_CTL_RX_CRC_EN_MASK                    0x0008
#define BRPHY_TOP_1588_RX_TX_CTL_RX_CRC_EN_ALIGN                   0
#define BRPHY_TOP_1588_RX_TX_CTL_RX_CRC_EN_BITS                    1
#define BRPHY_TOP_1588_RX_TX_CTL_RX_CRC_EN_SHIFT                   3

/* BRPHY_TOP_1588 :: RX_TX_CTL :: RX_L4_IP_ADDRESS_SEL [02:00] */
#define Wr_BRPHY_TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_CTL,0x7,0,x)
#define Rd_BRPHY_TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_CTL,0x7,0)
#define BRPHY_TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL_MASK         0x0007
#define BRPHY_TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL_ALIGN        0
#define BRPHY_TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL_BITS         3
#define BRPHY_TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL_SHIFT        0


/****************************************************************************
 * BRPHY_TOP_1588 :: VLAN_ITPID
 ***************************************************************************/
/* BRPHY_TOP_1588 :: VLAN_ITPID :: ITPID [15:00] */
#define Wr_BRPHY_TOP_1588_VLAN_ITPID_ITPID(x) WriteReg16(BRPHY_TOP_1588_VLAN_ITPID,x)
#define Rd_BRPHY_TOP_1588_VLAN_ITPID_ITPID(x) ReadReg16(BRPHY_TOP_1588_VLAN_ITPID)
#define BRPHY_TOP_1588_VLAN_ITPID_ITPID_MASK                       0xffff
#define BRPHY_TOP_1588_VLAN_ITPID_ITPID_ALIGN                      0
#define BRPHY_TOP_1588_VLAN_ITPID_ITPID_BITS                       16
#define BRPHY_TOP_1588_VLAN_ITPID_ITPID_SHIFT                      0


/****************************************************************************
 * BRPHY_TOP_1588 :: VLAN_OTPID
 ***************************************************************************/
/* BRPHY_TOP_1588 :: VLAN_OTPID :: OTPID [15:00] */
#define Wr_BRPHY_TOP_1588_VLAN_OTPID_OTPID(x) WriteReg16(BRPHY_TOP_1588_VLAN_OTPID,x)
#define Rd_BRPHY_TOP_1588_VLAN_OTPID_OTPID(x) ReadReg16(BRPHY_TOP_1588_VLAN_OTPID)
#define BRPHY_TOP_1588_VLAN_OTPID_OTPID_MASK                       0xffff
#define BRPHY_TOP_1588_VLAN_OTPID_OTPID_ALIGN                      0
#define BRPHY_TOP_1588_VLAN_OTPID_OTPID_BITS                       16
#define BRPHY_TOP_1588_VLAN_OTPID_OTPID_SHIFT                      0


/****************************************************************************
 * BRPHY_TOP_1588 :: OTHER_OTPID
 ***************************************************************************/
/* BRPHY_TOP_1588 :: OTHER_OTPID :: OTPID_2 [15:00] */
#define Wr_BRPHY_TOP_1588_OTHER_OTPID_OTPID_2(x) WriteReg16(BRPHY_TOP_1588_OTHER_OTPID,x)
#define Rd_BRPHY_TOP_1588_OTHER_OTPID_OTPID_2(x) ReadReg16(BRPHY_TOP_1588_OTHER_OTPID)
#define BRPHY_TOP_1588_OTHER_OTPID_OTPID_2_MASK                    0xffff
#define BRPHY_TOP_1588_OTHER_OTPID_OTPID_2_ALIGN                   0
#define BRPHY_TOP_1588_OTHER_OTPID_OTPID_2_BITS                    16
#define BRPHY_TOP_1588_OTHER_OTPID_OTPID_2_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_1 :: SPARE_REG1 [15:12] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG1(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0xf000,12,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG1(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0xf000,12)
#define BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG1_MASK                  0xf000
#define BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG1_ALIGN                 0
#define BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG1_BITS                  4
#define BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG1_SHIFT                 12

/* BRPHY_TOP_1588 :: NSE_DPLL_1 :: TS_DEBUG [11:09] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0xe00,9,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0xe00,9)
#define BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_MASK                    0x0e00
#define BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_ALIGN                   0
#define BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_BITS                    3
#define BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_SHIFT                   9

/* BRPHY_TOP_1588 :: NSE_DPLL_1 :: TS_DEBUG_EN [08:08] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_EN(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x100,8,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_EN(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x100,8)
#define BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_EN_MASK                 0x0100
#define BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_EN_ALIGN                0
#define BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_EN_BITS                 1
#define BRPHY_TOP_1588_NSE_DPLL_1_TS_DEBUG_EN_SHIFT                8

/* BRPHY_TOP_1588 :: NSE_DPLL_1 :: RX_TEST_SEL [07:07] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_1_RX_TEST_SEL(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x80,7,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_1_RX_TEST_SEL(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x80,7)
#define BRPHY_TOP_1588_NSE_DPLL_1_RX_TEST_SEL_MASK                 0x0080
#define BRPHY_TOP_1588_NSE_DPLL_1_RX_TEST_SEL_ALIGN                0
#define BRPHY_TOP_1588_NSE_DPLL_1_RX_TEST_SEL_BITS                 1
#define BRPHY_TOP_1588_NSE_DPLL_1_RX_TEST_SEL_SHIFT                7

/* BRPHY_TOP_1588 :: NSE_DPLL_1 :: SPARE_REG0 [06:06] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG0(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x40,6,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG0(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x40,6)
#define BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG0_MASK                  0x0040
#define BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG0_ALIGN                 0
#define BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG0_BITS                  1
#define BRPHY_TOP_1588_NSE_DPLL_1_SPARE_REG0_SHIFT                 6

/* BRPHY_TOP_1588 :: NSE_DPLL_1 :: TEST_BUS_SEL [05:01] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_1_TEST_BUS_SEL(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x3e,1,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_1_TEST_BUS_SEL(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x3e,1)
#define BRPHY_TOP_1588_NSE_DPLL_1_TEST_BUS_SEL_MASK                0x003e
#define BRPHY_TOP_1588_NSE_DPLL_1_TEST_BUS_SEL_ALIGN               0
#define BRPHY_TOP_1588_NSE_DPLL_1_TEST_BUS_SEL_BITS                5
#define BRPHY_TOP_1588_NSE_DPLL_1_TEST_BUS_SEL_SHIFT               1

/* BRPHY_TOP_1588 :: NSE_DPLL_1 :: DPLL_SELECT_MODE [00:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x1,0,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_1,0x1,0)
#define BRPHY_TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE_MASK            0x0001
#define BRPHY_TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE_ALIGN           0
#define BRPHY_TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE_BITS            1
#define BRPHY_TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE_SHIFT           0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_2_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_2_0 :: REF_PHASE_0 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_2_0_REF_PHASE_0(x) WriteReg16(BRPHY_TOP_1588_NSE_DPLL_2_0,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_2_0_REF_PHASE_0(x) ReadReg16(BRPHY_TOP_1588_NSE_DPLL_2_0)
#define BRPHY_TOP_1588_NSE_DPLL_2_0_REF_PHASE_0_MASK               0xffff
#define BRPHY_TOP_1588_NSE_DPLL_2_0_REF_PHASE_0_ALIGN              0
#define BRPHY_TOP_1588_NSE_DPLL_2_0_REF_PHASE_0_BITS               16
#define BRPHY_TOP_1588_NSE_DPLL_2_0_REF_PHASE_0_SHIFT              0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_2_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_2_1 :: REF_PHASE_1 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_2_1_REF_PHASE_1(x) WriteReg16(BRPHY_TOP_1588_NSE_DPLL_2_1,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_2_1_REF_PHASE_1(x) ReadReg16(BRPHY_TOP_1588_NSE_DPLL_2_1)
#define BRPHY_TOP_1588_NSE_DPLL_2_1_REF_PHASE_1_MASK               0xffff
#define BRPHY_TOP_1588_NSE_DPLL_2_1_REF_PHASE_1_ALIGN              0
#define BRPHY_TOP_1588_NSE_DPLL_2_1_REF_PHASE_1_BITS               16
#define BRPHY_TOP_1588_NSE_DPLL_2_1_REF_PHASE_1_SHIFT              0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_2_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_2_2 :: REF_PHASE_2 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_2_2_REF_PHASE_2(x) WriteReg16(BRPHY_TOP_1588_NSE_DPLL_2_2,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_2_2_REF_PHASE_2(x) ReadReg16(BRPHY_TOP_1588_NSE_DPLL_2_2)
#define BRPHY_TOP_1588_NSE_DPLL_2_2_REF_PHASE_2_MASK               0xffff
#define BRPHY_TOP_1588_NSE_DPLL_2_2_REF_PHASE_2_ALIGN              0
#define BRPHY_TOP_1588_NSE_DPLL_2_2_REF_PHASE_2_BITS               16
#define BRPHY_TOP_1588_NSE_DPLL_2_2_REF_PHASE_2_SHIFT              0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_3_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_3_LSB :: REF_PHASE_DELTA_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB(x) WriteReg16(BRPHY_TOP_1588_NSE_DPLL_3_LSB,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB(x) ReadReg16(BRPHY_TOP_1588_NSE_DPLL_3_LSB)
#define BRPHY_TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB_MASK     0xffff
#define BRPHY_TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB_ALIGN    0
#define BRPHY_TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB_BITS     16
#define BRPHY_TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB_SHIFT    0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_3_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_3_MSB :: REF_PHASE_DELTA_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB(x) WriteReg16(BRPHY_TOP_1588_NSE_DPLL_3_MSB,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB(x) ReadReg16(BRPHY_TOP_1588_NSE_DPLL_3_MSB)
#define BRPHY_TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB_MASK     0xffff
#define BRPHY_TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB_ALIGN    0
#define BRPHY_TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB_BITS     16
#define BRPHY_TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB_SHIFT    0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_4 :: reserved0 [15:08] */
#define BRPHY_TOP_1588_NSE_DPLL_4_RESERVED0_MASK                   0xff00
#define BRPHY_TOP_1588_NSE_DPLL_4_RESERVED0_ALIGN                  0
#define BRPHY_TOP_1588_NSE_DPLL_4_RESERVED0_BITS                   8
#define BRPHY_TOP_1588_NSE_DPLL_4_RESERVED0_SHIFT                  8

/* BRPHY_TOP_1588 :: NSE_DPLL_4 :: DPLL_K1 [07:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_4_DPLL_K1(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_4,0xff,0,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_4_DPLL_K1(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_4,0xff,0)
#define BRPHY_TOP_1588_NSE_DPLL_4_DPLL_K1_MASK                     0x00ff
#define BRPHY_TOP_1588_NSE_DPLL_4_DPLL_K1_ALIGN                    0
#define BRPHY_TOP_1588_NSE_DPLL_4_DPLL_K1_BITS                     8
#define BRPHY_TOP_1588_NSE_DPLL_4_DPLL_K1_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_5
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_5 :: reserved0 [15:08] */
#define BRPHY_TOP_1588_NSE_DPLL_5_RESERVED0_MASK                   0xff00
#define BRPHY_TOP_1588_NSE_DPLL_5_RESERVED0_ALIGN                  0
#define BRPHY_TOP_1588_NSE_DPLL_5_RESERVED0_BITS                   8
#define BRPHY_TOP_1588_NSE_DPLL_5_RESERVED0_SHIFT                  8

/* BRPHY_TOP_1588 :: NSE_DPLL_5 :: DPLL_K2 [07:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_5_DPLL_K2(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_5,0xff,0,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_5_DPLL_K2(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_5,0xff,0)
#define BRPHY_TOP_1588_NSE_DPLL_5_DPLL_K2_MASK                     0x00ff
#define BRPHY_TOP_1588_NSE_DPLL_5_DPLL_K2_ALIGN                    0
#define BRPHY_TOP_1588_NSE_DPLL_5_DPLL_K2_BITS                     8
#define BRPHY_TOP_1588_NSE_DPLL_5_DPLL_K2_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_6
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_6 :: reserved0 [15:08] */
#define BRPHY_TOP_1588_NSE_DPLL_6_RESERVED0_MASK                   0xff00
#define BRPHY_TOP_1588_NSE_DPLL_6_RESERVED0_ALIGN                  0
#define BRPHY_TOP_1588_NSE_DPLL_6_RESERVED0_BITS                   8
#define BRPHY_TOP_1588_NSE_DPLL_6_RESERVED0_SHIFT                  8

/* BRPHY_TOP_1588 :: NSE_DPLL_6 :: DPLL_K3 [07:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_6_DPLL_K3(x) WriteRegBits16(BRPHY_TOP_1588_NSE_DPLL_6,0xff,0,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_6_DPLL_K3(x) ReadRegBits16(BRPHY_TOP_1588_NSE_DPLL_6,0xff,0)
#define BRPHY_TOP_1588_NSE_DPLL_6_DPLL_K3_MASK                     0x00ff
#define BRPHY_TOP_1588_NSE_DPLL_6_DPLL_K3_ALIGN                    0
#define BRPHY_TOP_1588_NSE_DPLL_6_DPLL_K3_BITS                     8
#define BRPHY_TOP_1588_NSE_DPLL_6_DPLL_K3_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_7_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_7_0 :: LOOP_FILTER_0 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0(x) WriteReg16(BRPHY_TOP_1588_NSE_DPLL_7_0,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0(x) ReadReg16(BRPHY_TOP_1588_NSE_DPLL_7_0)
#define BRPHY_TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0_MASK             0xffff
#define BRPHY_TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0_ALIGN            0
#define BRPHY_TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0_BITS             16
#define BRPHY_TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_7_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_7_1 :: LOOP_FILTER_1 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1(x) WriteReg16(BRPHY_TOP_1588_NSE_DPLL_7_1,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1(x) ReadReg16(BRPHY_TOP_1588_NSE_DPLL_7_1)
#define BRPHY_TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1_MASK             0xffff
#define BRPHY_TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1_ALIGN            0
#define BRPHY_TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1_BITS             16
#define BRPHY_TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_7_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_7_2 :: LOOP_FILTER_2 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2(x) WriteReg16(BRPHY_TOP_1588_NSE_DPLL_7_2,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2(x) ReadReg16(BRPHY_TOP_1588_NSE_DPLL_7_2)
#define BRPHY_TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2_MASK             0xffff
#define BRPHY_TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2_ALIGN            0
#define BRPHY_TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2_BITS             16
#define BRPHY_TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_DPLL_7_3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_DPLL_7_3 :: LOOP_FILTER_3 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3(x) WriteReg16(BRPHY_TOP_1588_NSE_DPLL_7_3,x)
#define Rd_BRPHY_TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3(x) ReadReg16(BRPHY_TOP_1588_NSE_DPLL_7_3)
#define BRPHY_TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3_MASK             0xffff
#define BRPHY_TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3_ALIGN            0
#define BRPHY_TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3_BITS             16
#define BRPHY_TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3_SHIFT            0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_1_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_1_LSB :: NSE_REG_NCO_FREQCNTRL_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB(x) WriteReg16(BRPHY_TOP_1588_NSE_NCO_1_LSB,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB(x) ReadReg16(BRPHY_TOP_1588_NSE_NCO_1_LSB)
#define BRPHY_TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB_MASK 0xffff
#define BRPHY_TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB_ALIGN 0
#define BRPHY_TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB_BITS 16
#define BRPHY_TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_1_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_1_MSB :: NSE_REG_NCO_FREQCNTRL_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB(x) WriteReg16(BRPHY_TOP_1588_NSE_NCO_1_MSB,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB(x) ReadReg16(BRPHY_TOP_1588_NSE_NCO_1_MSB)
#define BRPHY_TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB_MASK 0xffff
#define BRPHY_TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB_ALIGN 0
#define BRPHY_TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB_BITS 16
#define BRPHY_TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_2_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_2_0 :: LOCAL_TIME_UP_0 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0(x) WriteReg16(BRPHY_TOP_1588_NSE_NCO_2_0,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0(x) ReadReg16(BRPHY_TOP_1588_NSE_NCO_2_0)
#define BRPHY_TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0_MASK            0xffff
#define BRPHY_TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0_ALIGN           0
#define BRPHY_TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0_BITS            16
#define BRPHY_TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0_SHIFT           0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_2_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_2_1 :: LOCAL_TIME_UP_1 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1(x) WriteReg16(BRPHY_TOP_1588_NSE_NCO_2_1,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1(x) ReadReg16(BRPHY_TOP_1588_NSE_NCO_2_1)
#define BRPHY_TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1_MASK            0xffff
#define BRPHY_TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1_ALIGN           0
#define BRPHY_TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1_BITS            16
#define BRPHY_TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1_SHIFT           0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_2_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_2_2 :: SPARE_REG2 [15:15] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG2(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_2_2,0x8000,15,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG2(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_2_2,0x8000,15)
#define BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG2_MASK                 0x8000
#define BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG2_ALIGN                0
#define BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG2_BITS                 1
#define BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG2_SHIFT                15

/* BRPHY_TOP_1588 :: NSE_NCO_2_2 :: FREQ_MDIO_SEL [14:14] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_2_2,0x4000,14,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_2_2,0x4000,14)
#define BRPHY_TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL_MASK              0x4000
#define BRPHY_TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL_ALIGN             0
#define BRPHY_TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL_BITS              1
#define BRPHY_TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL_SHIFT             14

/* BRPHY_TOP_1588 :: NSE_NCO_2_2 :: SPARE_REG1 [13:12] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG1(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_2_2,0x3000,12,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG1(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_2_2,0x3000,12)
#define BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG1_MASK                 0x3000
#define BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG1_ALIGN                0
#define BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG1_BITS                 2
#define BRPHY_TOP_1588_NSE_NCO_2_2_SPARE_REG1_SHIFT                12

/* BRPHY_TOP_1588 :: NSE_NCO_2_2 :: LOCAL_TIME_UP_2 [11:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_2_2,0xfff,0,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_2_2,0xfff,0)
#define BRPHY_TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2_MASK            0x0fff
#define BRPHY_TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2_ALIGN           0
#define BRPHY_TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2_BITS            12
#define BRPHY_TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2_SHIFT           0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_3_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_3_0 :: INTERVAL_LENGTH_0 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0(x) WriteReg16(BRPHY_TOP_1588_NSE_NCO_3_0,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0(x) ReadReg16(BRPHY_TOP_1588_NSE_NCO_3_0)
#define BRPHY_TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0_MASK          0xffff
#define BRPHY_TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0_ALIGN         0
#define BRPHY_TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0_BITS          16
#define BRPHY_TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0_SHIFT         0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_3_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_3_1 :: PULSE_TRAIN_LENGTH_0 [15:14] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_3_1,0xc000,14,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_3_1,0xc000,14)
#define BRPHY_TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0_MASK       0xc000
#define BRPHY_TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0_ALIGN      0
#define BRPHY_TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0_BITS       2
#define BRPHY_TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0_SHIFT      14

/* BRPHY_TOP_1588 :: NSE_NCO_3_1 :: INTERVAL_LENGTH_1 [13:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_3_1,0x3fff,0,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_3_1,0x3fff,0)
#define BRPHY_TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1_MASK          0x3fff
#define BRPHY_TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1_ALIGN         0
#define BRPHY_TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1_BITS          14
#define BRPHY_TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1_SHIFT         0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_3_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_3_2 :: FRMSYNC_PULSE_LENGTH [15:07] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_3_2,0xff80,7,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_3_2,0xff80,7)
#define BRPHY_TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH_MASK       0xff80
#define BRPHY_TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH_ALIGN      0
#define BRPHY_TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH_BITS       9
#define BRPHY_TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH_SHIFT      7

/* BRPHY_TOP_1588 :: NSE_NCO_3_2 :: PULSE_TRAIN_LENGTH_1 [06:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_3_2,0x7f,0,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_3_2,0x7f,0)
#define BRPHY_TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1_MASK       0x007f
#define BRPHY_TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1_ALIGN      0
#define BRPHY_TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1_BITS       7
#define BRPHY_TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1_SHIFT      0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_4 :: reserved0 [15:12] */
#define BRPHY_TOP_1588_NSE_NCO_4_RESERVED0_MASK                    0xf000
#define BRPHY_TOP_1588_NSE_NCO_4_RESERVED0_ALIGN                   0
#define BRPHY_TOP_1588_NSE_NCO_4_RESERVED0_BITS                    4
#define BRPHY_TOP_1588_NSE_NCO_4_RESERVED0_SHIFT                   12

/* BRPHY_TOP_1588 :: NSE_NCO_4 :: NSE_REG_TS_DIVIDER [11:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_4,0xfff,0,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_4,0xfff,0)
#define BRPHY_TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER_MASK           0x0fff
#define BRPHY_TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER_ALIGN          0
#define BRPHY_TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER_BITS           12
#define BRPHY_TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER_SHIFT          0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_5_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_5_0 :: SYNOUT_TS_REG_0 [15:04] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_5_0,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_5_0,0xfff0,4)
#define BRPHY_TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0_MASK            0xfff0
#define BRPHY_TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0_ALIGN           0
#define BRPHY_TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0_BITS            12
#define BRPHY_TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0_SHIFT           4

/* BRPHY_TOP_1588 :: NSE_NCO_5_0 :: SPARE_REG [03:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_5_0_SPARE_REG(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_5_0,0xf,0,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_5_0_SPARE_REG(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_5_0,0xf,0)
#define BRPHY_TOP_1588_NSE_NCO_5_0_SPARE_REG_MASK                  0x000f
#define BRPHY_TOP_1588_NSE_NCO_5_0_SPARE_REG_ALIGN                 0
#define BRPHY_TOP_1588_NSE_NCO_5_0_SPARE_REG_BITS                  4
#define BRPHY_TOP_1588_NSE_NCO_5_0_SPARE_REG_SHIFT                 0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_5_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_5_1 :: SYNOUT_TS_REG_1 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1(x) WriteReg16(BRPHY_TOP_1588_NSE_NCO_5_1,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1(x) ReadReg16(BRPHY_TOP_1588_NSE_NCO_5_1)
#define BRPHY_TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1_MASK            0xffff
#define BRPHY_TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1_ALIGN           0
#define BRPHY_TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1_BITS            16
#define BRPHY_TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1_SHIFT           0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_5_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_5_2 :: SYNOUT_TS_REG_2 [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2(x) WriteReg16(BRPHY_TOP_1588_NSE_NCO_5_2,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2(x) ReadReg16(BRPHY_TOP_1588_NSE_NCO_5_2)
#define BRPHY_TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2_MASK            0xffff
#define BRPHY_TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2_ALIGN           0
#define BRPHY_TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2_BITS            16
#define BRPHY_TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2_SHIFT           0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_6
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_6 :: GMODE [15:14] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_GMODE(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0xc000,14,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_GMODE(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0xc000,14)
#define BRPHY_TOP_1588_NSE_NCO_6_GMODE_MASK                        0xc000
#define BRPHY_TOP_1588_NSE_NCO_6_GMODE_ALIGN                       0
#define BRPHY_TOP_1588_NSE_NCO_6_GMODE_BITS                        2
#define BRPHY_TOP_1588_NSE_NCO_6_GMODE_SHIFT                       14

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: TS_CAPTURE [13:13] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_TS_CAPTURE(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x2000,13,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_TS_CAPTURE(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x2000,13)
#define BRPHY_TOP_1588_NSE_NCO_6_TS_CAPTURE_MASK                   0x2000
#define BRPHY_TOP_1588_NSE_NCO_6_TS_CAPTURE_ALIGN                  0
#define BRPHY_TOP_1588_NSE_NCO_6_TS_CAPTURE_BITS                   1
#define BRPHY_TOP_1588_NSE_NCO_6_TS_CAPTURE_SHIFT                  13

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: NSE_INIT [12:12] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_NSE_INIT(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x1000,12,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_NSE_INIT(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x1000,12)
#define BRPHY_TOP_1588_NSE_NCO_6_NSE_INIT_MASK                     0x1000
#define BRPHY_TOP_1588_NSE_NCO_6_NSE_INIT_ALIGN                    0
#define BRPHY_TOP_1588_NSE_NCO_6_NSE_INIT_BITS                     1
#define BRPHY_TOP_1588_NSE_NCO_6_NSE_INIT_SHIFT                    12

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: M34_LOCAL_SYNC_DIS [11:11] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x800,11,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x800,11)
#define BRPHY_TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS_MASK           0x0800
#define BRPHY_TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS_ALIGN          0
#define BRPHY_TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS_BITS           1
#define BRPHY_TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS_SHIFT          11

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: SPARE_REG1 [10:10] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG1(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x400,10,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG1(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x400,10)
#define BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG1_MASK                   0x0400
#define BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG1_ALIGN                  0
#define BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG1_BITS                   1
#define BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG1_SHIFT                  10

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: RESET_LOCK_STATE [09:09] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_RESET_LOCK_STATE(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x200,9,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_RESET_LOCK_STATE(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x200,9)
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_LOCK_STATE_MASK             0x0200
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_LOCK_STATE_ALIGN            0
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_LOCK_STATE_BITS             1
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_LOCK_STATE_SHIFT            9

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: RESET_SYNCIN_STATE [08:08] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x100,8,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x100,8)
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE_MASK           0x0100
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE_ALIGN          0
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE_BITS           1
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE_SHIFT          8

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: RESET_SYNC_STATE [07:07] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNC_STATE(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x80,7,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNC_STATE(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x80,7)
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNC_STATE_MASK             0x0080
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNC_STATE_ALIGN            0
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNC_STATE_BITS             1
#define BRPHY_TOP_1588_NSE_NCO_6_RESET_SYNC_STATE_SHIFT            7

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: SPARE_REG0 [06:06] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG0(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x40,6,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG0(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x40,6)
#define BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG0_MASK                   0x0040
#define BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG0_ALIGN                  0
#define BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG0_BITS                   1
#define BRPHY_TOP_1588_NSE_NCO_6_SPARE_REG0_SHIFT                  6

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: FRAMESYN_MODE [05:02] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_FRAMESYN_MODE(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x3c,2,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_FRAMESYN_MODE(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x3c,2)
#define BRPHY_TOP_1588_NSE_NCO_6_FRAMESYN_MODE_MASK                0x003c
#define BRPHY_TOP_1588_NSE_NCO_6_FRAMESYN_MODE_ALIGN               0
#define BRPHY_TOP_1588_NSE_NCO_6_FRAMESYN_MODE_BITS                4
#define BRPHY_TOP_1588_NSE_NCO_6_FRAMESYN_MODE_SHIFT               2

/* BRPHY_TOP_1588 :: NSE_NCO_6 :: SYNOUT_MODE [01:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_6_SYNOUT_MODE(x) WriteRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x3,0,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_6_SYNOUT_MODE(x) ReadRegBits16(BRPHY_TOP_1588_NSE_NCO_6,0x3,0)
#define BRPHY_TOP_1588_NSE_NCO_6_SYNOUT_MODE_MASK                  0x0003
#define BRPHY_TOP_1588_NSE_NCO_6_SYNOUT_MODE_ALIGN                 0
#define BRPHY_TOP_1588_NSE_NCO_6_SYNOUT_MODE_BITS                  2
#define BRPHY_TOP_1588_NSE_NCO_6_SYNOUT_MODE_SHIFT                 0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_7_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_7_0 :: LENGTH_THRESHOLD [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD(x) WriteReg16(BRPHY_TOP_1588_NSE_NCO_7_0,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD(x) ReadReg16(BRPHY_TOP_1588_NSE_NCO_7_0)
#define BRPHY_TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD_MASK           0xffff
#define BRPHY_TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD_ALIGN          0
#define BRPHY_TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD_BITS           16
#define BRPHY_TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD_SHIFT          0


/****************************************************************************
 * BRPHY_TOP_1588 :: NSE_NCO_7_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NSE_NCO_7_1 :: EVENT_OFFSET [15:00] */
#define Wr_BRPHY_TOP_1588_NSE_NCO_7_1_EVENT_OFFSET(x) WriteReg16(BRPHY_TOP_1588_NSE_NCO_7_1,x)
#define Rd_BRPHY_TOP_1588_NSE_NCO_7_1_EVENT_OFFSET(x) ReadReg16(BRPHY_TOP_1588_NSE_NCO_7_1)
#define BRPHY_TOP_1588_NSE_NCO_7_1_EVENT_OFFSET_MASK               0xffff
#define BRPHY_TOP_1588_NSE_NCO_7_1_EVENT_OFFSET_ALIGN              0
#define BRPHY_TOP_1588_NSE_NCO_7_1_EVENT_OFFSET_BITS               16
#define BRPHY_TOP_1588_NSE_NCO_7_1_EVENT_OFFSET_SHIFT              0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_COUNTER
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_COUNTER :: TX_COUNTER [15:00] */
#define Wr_BRPHY_TOP_1588_TX_COUNTER_TX_COUNTER(x) WriteReg16(BRPHY_TOP_1588_TX_COUNTER,x)
#define Rd_BRPHY_TOP_1588_TX_COUNTER_TX_COUNTER(x) ReadReg16(BRPHY_TOP_1588_TX_COUNTER)
#define BRPHY_TOP_1588_TX_COUNTER_TX_COUNTER_MASK                  0xffff
#define BRPHY_TOP_1588_TX_COUNTER_TX_COUNTER_ALIGN                 0
#define BRPHY_TOP_1588_TX_COUNTER_TX_COUNTER_BITS                  16
#define BRPHY_TOP_1588_TX_COUNTER_TX_COUNTER_SHIFT                 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_COUNTER
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_COUNTER :: RX_COUNTER [15:00] */
#define Wr_BRPHY_TOP_1588_RX_COUNTER_RX_COUNTER(x) WriteReg16(BRPHY_TOP_1588_RX_COUNTER,x)
#define Rd_BRPHY_TOP_1588_RX_COUNTER_RX_COUNTER(x) ReadReg16(BRPHY_TOP_1588_RX_COUNTER)
#define BRPHY_TOP_1588_RX_COUNTER_RX_COUNTER_MASK                  0xffff
#define BRPHY_TOP_1588_RX_COUNTER_RX_COUNTER_ALIGN                 0
#define BRPHY_TOP_1588_RX_COUNTER_RX_COUNTER_BITS                  16
#define BRPHY_TOP_1588_RX_COUNTER_RX_COUNTER_SHIFT                 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_TX_1588_COUNTER
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_TX_1588_COUNTER :: RX_1588_COUNTER [15:08] */
#define Wr_BRPHY_TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_1588_COUNTER,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_1588_COUNTER,0xff00,8)
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER_MASK     0xff00
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER_ALIGN    0
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER_BITS     8
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER_SHIFT    8

/* BRPHY_TOP_1588 :: RX_TX_1588_COUNTER :: TX_1588_COUNTER [07:00] */
#define Wr_BRPHY_TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_1588_COUNTER,0xff,0,x)
#define Rd_BRPHY_TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_1588_COUNTER,0xff,0)
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER_MASK     0x00ff
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER_ALIGN    0
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER_BITS     8
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER_SHIFT    0


/****************************************************************************
 * BRPHY_TOP_1588 :: TS_READ_START_END
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TS_READ_START_END :: TS [15:00] */
#define Wr_BRPHY_TOP_1588_TS_READ_START_END_TS(x) WriteReg16(BRPHY_TOP_1588_TS_READ_START_END,x)
#define Rd_BRPHY_TOP_1588_TS_READ_START_END_TS(x) ReadReg16(BRPHY_TOP_1588_TS_READ_START_END)
#define BRPHY_TOP_1588_TS_READ_START_END_TS_MASK                   0xffff
#define BRPHY_TOP_1588_TS_READ_START_END_TS_ALIGN                  0
#define BRPHY_TOP_1588_TS_READ_START_END_TS_BITS                   16
#define BRPHY_TOP_1588_TS_READ_START_END_TS_SHIFT                  0


/****************************************************************************
 * BRPHY_TOP_1588 :: HEARTBEAT_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: HEARTBEAT_0 :: HEARTBEAT_0 [15:00] */
#define Wr_BRPHY_TOP_1588_HEARTBEAT_0_HEARTBEAT_0(x) WriteReg16(BRPHY_TOP_1588_HEARTBEAT_0,x)
#define Rd_BRPHY_TOP_1588_HEARTBEAT_0_HEARTBEAT_0(x) ReadReg16(BRPHY_TOP_1588_HEARTBEAT_0)
#define BRPHY_TOP_1588_HEARTBEAT_0_HEARTBEAT_0_MASK                0xffff
#define BRPHY_TOP_1588_HEARTBEAT_0_HEARTBEAT_0_ALIGN               0
#define BRPHY_TOP_1588_HEARTBEAT_0_HEARTBEAT_0_BITS                16
#define BRPHY_TOP_1588_HEARTBEAT_0_HEARTBEAT_0_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: HEARTBEAT_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: HEARTBEAT_1 :: HEARTBEAT_1 [15:00] */
#define Wr_BRPHY_TOP_1588_HEARTBEAT_1_HEARTBEAT_1(x) WriteReg16(BRPHY_TOP_1588_HEARTBEAT_1,x)
#define Rd_BRPHY_TOP_1588_HEARTBEAT_1_HEARTBEAT_1(x) ReadReg16(BRPHY_TOP_1588_HEARTBEAT_1)
#define BRPHY_TOP_1588_HEARTBEAT_1_HEARTBEAT_1_MASK                0xffff
#define BRPHY_TOP_1588_HEARTBEAT_1_HEARTBEAT_1_ALIGN               0
#define BRPHY_TOP_1588_HEARTBEAT_1_HEARTBEAT_1_BITS                16
#define BRPHY_TOP_1588_HEARTBEAT_1_HEARTBEAT_1_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: HEARTBEAT_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: HEARTBEAT_2 :: HEARTBEAT_2 [15:00] */
#define Wr_BRPHY_TOP_1588_HEARTBEAT_2_HEARTBEAT_2(x) WriteReg16(BRPHY_TOP_1588_HEARTBEAT_2,x)
#define Rd_BRPHY_TOP_1588_HEARTBEAT_2_HEARTBEAT_2(x) ReadReg16(BRPHY_TOP_1588_HEARTBEAT_2)
#define BRPHY_TOP_1588_HEARTBEAT_2_HEARTBEAT_2_MASK                0xffff
#define BRPHY_TOP_1588_HEARTBEAT_2_HEARTBEAT_2_ALIGN               0
#define BRPHY_TOP_1588_HEARTBEAT_2_HEARTBEAT_2_BITS                16
#define BRPHY_TOP_1588_HEARTBEAT_2_HEARTBEAT_2_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_0 :: TIME_STAMP_0 [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_0_TIME_STAMP_0(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_0,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_0_TIME_STAMP_0(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_0)
#define BRPHY_TOP_1588_TIME_STAMP_0_TIME_STAMP_0_MASK              0xffff
#define BRPHY_TOP_1588_TIME_STAMP_0_TIME_STAMP_0_ALIGN             0
#define BRPHY_TOP_1588_TIME_STAMP_0_TIME_STAMP_0_BITS              16
#define BRPHY_TOP_1588_TIME_STAMP_0_TIME_STAMP_0_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_1 :: TIME_STAMP_1 [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_1_TIME_STAMP_1(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_1,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_1_TIME_STAMP_1(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_1)
#define BRPHY_TOP_1588_TIME_STAMP_1_TIME_STAMP_1_MASK              0xffff
#define BRPHY_TOP_1588_TIME_STAMP_1_TIME_STAMP_1_ALIGN             0
#define BRPHY_TOP_1588_TIME_STAMP_1_TIME_STAMP_1_BITS              16
#define BRPHY_TOP_1588_TIME_STAMP_1_TIME_STAMP_1_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_2 :: TIME_STAMP_2 [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_2_TIME_STAMP_2(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_2,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_2_TIME_STAMP_2(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_2)
#define BRPHY_TOP_1588_TIME_STAMP_2_TIME_STAMP_2_MASK              0xffff
#define BRPHY_TOP_1588_TIME_STAMP_2_TIME_STAMP_2_ALIGN             0
#define BRPHY_TOP_1588_TIME_STAMP_2_TIME_STAMP_2_BITS              16
#define BRPHY_TOP_1588_TIME_STAMP_2_TIME_STAMP_2_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_INFO_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_INFO_1 :: TIME_STAMP_INFO [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_1,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_1)
#define BRPHY_TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO_MASK      0xffff
#define BRPHY_TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO_ALIGN     0
#define BRPHY_TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO_BITS      16
#define BRPHY_TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_INFO_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_INFO_2 :: TIME_STAMP_INFO [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_2,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_2)
#define BRPHY_TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO_MASK      0xffff
#define BRPHY_TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO_ALIGN     0
#define BRPHY_TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO_BITS      16
#define BRPHY_TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: CNTR_DBG
 ***************************************************************************/
/* BRPHY_TOP_1588 :: CNTR_DBG :: SPARE_REG [15:14] */
#define Wr_BRPHY_TOP_1588_CNTR_DBG_SPARE_REG(x) WriteRegBits16(BRPHY_TOP_1588_CNTR_DBG,0xc000,14,x)
#define Rd_BRPHY_TOP_1588_CNTR_DBG_SPARE_REG(x) ReadRegBits16(BRPHY_TOP_1588_CNTR_DBG,0xc000,14)
#define BRPHY_TOP_1588_CNTR_DBG_SPARE_REG_MASK                     0xc000
#define BRPHY_TOP_1588_CNTR_DBG_SPARE_REG_ALIGN                    0
#define BRPHY_TOP_1588_CNTR_DBG_SPARE_REG_BITS                     2
#define BRPHY_TOP_1588_CNTR_DBG_SPARE_REG_SHIFT                    14

/* BRPHY_TOP_1588 :: CNTR_DBG :: TC_64_LEAP [13:12] */
#define Wr_BRPHY_TOP_1588_CNTR_DBG_TC_64_LEAP(x) WriteRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x3000,12,x)
#define Rd_BRPHY_TOP_1588_CNTR_DBG_TC_64_LEAP(x) ReadRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x3000,12)
#define BRPHY_TOP_1588_CNTR_DBG_TC_64_LEAP_MASK                    0x3000
#define BRPHY_TOP_1588_CNTR_DBG_TC_64_LEAP_ALIGN                   0
#define BRPHY_TOP_1588_CNTR_DBG_TC_64_LEAP_BITS                    2
#define BRPHY_TOP_1588_CNTR_DBG_TC_64_LEAP_SHIFT                   12

/* BRPHY_TOP_1588 :: CNTR_DBG :: HB_CNTL [11:10] */
#define Wr_BRPHY_TOP_1588_CNTR_DBG_HB_CNTL(x) WriteRegBits16(BRPHY_TOP_1588_CNTR_DBG,0xc00,10,x)
#define Rd_BRPHY_TOP_1588_CNTR_DBG_HB_CNTL(x) ReadRegBits16(BRPHY_TOP_1588_CNTR_DBG,0xc00,10)
#define BRPHY_TOP_1588_CNTR_DBG_HB_CNTL_MASK                       0x0c00
#define BRPHY_TOP_1588_CNTR_DBG_HB_CNTL_ALIGN                      0
#define BRPHY_TOP_1588_CNTR_DBG_HB_CNTL_BITS                       2
#define BRPHY_TOP_1588_CNTR_DBG_HB_CNTL_SHIFT                      10

/* BRPHY_TOP_1588 :: CNTR_DBG :: TS_SLICE_SEL [09:07] */
#define Wr_BRPHY_TOP_1588_CNTR_DBG_TS_SLICE_SEL(x) WriteRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x380,7,x)
#define Rd_BRPHY_TOP_1588_CNTR_DBG_TS_SLICE_SEL(x) ReadRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x380,7)
#define BRPHY_TOP_1588_CNTR_DBG_TS_SLICE_SEL_MASK                  0x0380
#define BRPHY_TOP_1588_CNTR_DBG_TS_SLICE_SEL_ALIGN                 0
#define BRPHY_TOP_1588_CNTR_DBG_TS_SLICE_SEL_BITS                  3
#define BRPHY_TOP_1588_CNTR_DBG_TS_SLICE_SEL_SHIFT                 7

/* BRPHY_TOP_1588 :: CNTR_DBG :: TC_80_LEAP [06:05] */
#define Wr_BRPHY_TOP_1588_CNTR_DBG_TC_80_LEAP(x) WriteRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x60,5,x)
#define Rd_BRPHY_TOP_1588_CNTR_DBG_TC_80_LEAP(x) ReadRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x60,5)
#define BRPHY_TOP_1588_CNTR_DBG_TC_80_LEAP_MASK                    0x0060
#define BRPHY_TOP_1588_CNTR_DBG_TC_80_LEAP_ALIGN                   0
#define BRPHY_TOP_1588_CNTR_DBG_TC_80_LEAP_BITS                    2
#define BRPHY_TOP_1588_CNTR_DBG_TC_80_LEAP_SHIFT                   5

/* BRPHY_TOP_1588 :: CNTR_DBG :: CNTR_SLICE_SEL [04:02] */
#define Wr_BRPHY_TOP_1588_CNTR_DBG_CNTR_SLICE_SEL(x) WriteRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x1c,2,x)
#define Rd_BRPHY_TOP_1588_CNTR_DBG_CNTR_SLICE_SEL(x) ReadRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x1c,2)
#define BRPHY_TOP_1588_CNTR_DBG_CNTR_SLICE_SEL_MASK                0x001c
#define BRPHY_TOP_1588_CNTR_DBG_CNTR_SLICE_SEL_ALIGN               0
#define BRPHY_TOP_1588_CNTR_DBG_CNTR_SLICE_SEL_BITS                3
#define BRPHY_TOP_1588_CNTR_DBG_CNTR_SLICE_SEL_SHIFT               2

/* BRPHY_TOP_1588 :: CNTR_DBG :: RST_RX_CNTR [01:01] */
#define Wr_BRPHY_TOP_1588_CNTR_DBG_RST_RX_CNTR(x) WriteRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x2,1,x)
#define Rd_BRPHY_TOP_1588_CNTR_DBG_RST_RX_CNTR(x) ReadRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x2,1)
#define BRPHY_TOP_1588_CNTR_DBG_RST_RX_CNTR_MASK                   0x0002
#define BRPHY_TOP_1588_CNTR_DBG_RST_RX_CNTR_ALIGN                  0
#define BRPHY_TOP_1588_CNTR_DBG_RST_RX_CNTR_BITS                   1
#define BRPHY_TOP_1588_CNTR_DBG_RST_RX_CNTR_SHIFT                  1

/* BRPHY_TOP_1588 :: CNTR_DBG :: RST_TX_CNTR [00:00] */
#define Wr_BRPHY_TOP_1588_CNTR_DBG_RST_TX_CNTR(x) WriteRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x1,0,x)
#define Rd_BRPHY_TOP_1588_CNTR_DBG_RST_TX_CNTR(x) ReadRegBits16(BRPHY_TOP_1588_CNTR_DBG,0x1,0)
#define BRPHY_TOP_1588_CNTR_DBG_RST_TX_CNTR_MASK                   0x0001
#define BRPHY_TOP_1588_CNTR_DBG_RST_TX_CNTR_ALIGN                  0
#define BRPHY_TOP_1588_CNTR_DBG_RST_TX_CNTR_BITS                   1
#define BRPHY_TOP_1588_CNTR_DBG_RST_TX_CNTR_SHIFT                  0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_SPARE1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_SPARE1 :: CPU_MODE_PORT_ENABLE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE(x) WriteReg16(BRPHY_TOP_1588_MPLS_SPARE1,x)
#define Rd_BRPHY_TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE(x) ReadReg16(BRPHY_TOP_1588_MPLS_SPARE1)
#define BRPHY_TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE_MASK       0xffff
#define BRPHY_TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE_ALIGN      0
#define BRPHY_TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE_BITS       16
#define BRPHY_TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE_SHIFT      0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_SPARE2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_SPARE2 :: CPU_DA1 [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_SPARE2_CPU_DA1(x) WriteReg16(BRPHY_TOP_1588_MPLS_SPARE2,x)
#define Rd_BRPHY_TOP_1588_MPLS_SPARE2_CPU_DA1(x) ReadReg16(BRPHY_TOP_1588_MPLS_SPARE2)
#define BRPHY_TOP_1588_MPLS_SPARE2_CPU_DA1_MASK                    0xffff
#define BRPHY_TOP_1588_MPLS_SPARE2_CPU_DA1_ALIGN                   0
#define BRPHY_TOP_1588_MPLS_SPARE2_CPU_DA1_BITS                    16
#define BRPHY_TOP_1588_MPLS_SPARE2_CPU_DA1_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_SPARE3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_SPARE3 :: CPU_DA2 [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_SPARE3_CPU_DA2(x) WriteReg16(BRPHY_TOP_1588_MPLS_SPARE3,x)
#define Rd_BRPHY_TOP_1588_MPLS_SPARE3_CPU_DA2(x) ReadReg16(BRPHY_TOP_1588_MPLS_SPARE3)
#define BRPHY_TOP_1588_MPLS_SPARE3_CPU_DA2_MASK                    0xffff
#define BRPHY_TOP_1588_MPLS_SPARE3_CPU_DA2_ALIGN                   0
#define BRPHY_TOP_1588_MPLS_SPARE3_CPU_DA2_BITS                    16
#define BRPHY_TOP_1588_MPLS_SPARE3_CPU_DA2_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_SPARE4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_SPARE4 :: CPU_DA3 [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_SPARE4_CPU_DA3(x) WriteReg16(BRPHY_TOP_1588_MPLS_SPARE4,x)
#define Rd_BRPHY_TOP_1588_MPLS_SPARE4_CPU_DA3(x) ReadReg16(BRPHY_TOP_1588_MPLS_SPARE4)
#define BRPHY_TOP_1588_MPLS_SPARE4_CPU_DA3_MASK                    0xffff
#define BRPHY_TOP_1588_MPLS_SPARE4_CPU_DA3_ALIGN                   0
#define BRPHY_TOP_1588_MPLS_SPARE4_CPU_DA3_BITS                    16
#define BRPHY_TOP_1588_MPLS_SPARE4_CPU_DA3_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_SPARE5
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_SPARE5 :: MPLS_SPEC_LABEL1 [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1(x) WriteReg16(BRPHY_TOP_1588_MPLS_SPARE5,x)
#define Rd_BRPHY_TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1(x) ReadReg16(BRPHY_TOP_1588_MPLS_SPARE5)
#define BRPHY_TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1_MASK           0xffff
#define BRPHY_TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1_ALIGN          0
#define BRPHY_TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1_BITS           16
#define BRPHY_TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1_SHIFT          0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_SPARE6
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_SPARE6 :: MPLS_SPEC_LABEL2 [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2(x) WriteReg16(BRPHY_TOP_1588_MPLS_SPARE6,x)
#define Rd_BRPHY_TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2(x) ReadReg16(BRPHY_TOP_1588_MPLS_SPARE6)
#define BRPHY_TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2_MASK           0xffff
#define BRPHY_TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2_ALIGN          0
#define BRPHY_TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2_BITS           16
#define BRPHY_TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2_SHIFT          0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_TX_CNTL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_TX_CNTL :: MPLS_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_TX_CNTL_MPLS_CNTL(x) WriteReg16(BRPHY_TOP_1588_MPLS_TX_CNTL,x)
#define Rd_BRPHY_TOP_1588_MPLS_TX_CNTL_MPLS_CNTL(x) ReadReg16(BRPHY_TOP_1588_MPLS_TX_CNTL)
#define BRPHY_TOP_1588_MPLS_TX_CNTL_MPLS_CNTL_MASK                 0xffff
#define BRPHY_TOP_1588_MPLS_TX_CNTL_MPLS_CNTL_ALIGN                0
#define BRPHY_TOP_1588_MPLS_TX_CNTL_MPLS_CNTL_BITS                 16
#define BRPHY_TOP_1588_MPLS_TX_CNTL_MPLS_CNTL_SHIFT                0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_RX_CNTL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_RX_CNTL :: MPLS_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_RX_CNTL_MPLS_CNTL(x) WriteReg16(BRPHY_TOP_1588_MPLS_RX_CNTL,x)
#define Rd_BRPHY_TOP_1588_MPLS_RX_CNTL_MPLS_CNTL(x) ReadReg16(BRPHY_TOP_1588_MPLS_RX_CNTL)
#define BRPHY_TOP_1588_MPLS_RX_CNTL_MPLS_CNTL_MASK                 0xffff
#define BRPHY_TOP_1588_MPLS_RX_CNTL_MPLS_CNTL_ALIGN                0
#define BRPHY_TOP_1588_MPLS_RX_CNTL_MPLS_CNTL_BITS                 16
#define BRPHY_TOP_1588_MPLS_RX_CNTL_MPLS_CNTL_SHIFT                0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL1_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL1_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL1_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL1_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL1_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL1_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL1_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL1_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL1_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL1_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL1_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL1_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL1_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL1_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL2_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL2_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL2_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL2_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL2_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL2_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL2_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL2_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL2_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL2_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL2_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL2_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL2_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL2_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL3_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL3_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL3_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL3_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL3_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL3_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL3_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL3_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL3_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL3_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL3_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL3_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL3_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL3_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL4_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL4_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL4_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL4_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL4_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL4_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL4_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL4_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL4_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL4_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL4_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL4_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL4_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL4_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL5_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL5_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL5_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL5_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL5_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL5_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL5_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL5_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL5_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL5_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL5_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL5_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL5_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL5_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL6_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL6_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL6_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL6_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL6_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL6_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL6_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL6_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL6_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL6_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL6_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL6_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL6_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL6_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL7_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL7_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL7_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL7_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL7_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL7_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL7_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL7_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL7_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL7_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL7_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL7_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL7_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL7_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL8_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL8_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL8_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL8_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL8_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL8_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL8_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL8_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL8_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL8_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL8_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL8_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL8_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL8_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL9_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL9_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL9_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL9_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL9_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL9_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL9_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL9_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL9_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL9_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL9_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL9_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL9_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL9_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL10_LSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL10_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL10_LSB_MASK,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL10_LSB_MASK)
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL10_MSB_MASK
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL10_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL10_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL10_LSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL10_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(BRPHY_TOP_1588_MPLS_LABEL10_LSB_VALUE,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(BRPHY_TOP_1588_MPLS_LABEL10_LSB_VALUE)
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK 0xffff
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS 16
#define BRPHY_TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_LABEL10_MSB_VALUE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_LABEL10_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE,0xfff0,4,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE,0xfff0,4)
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK 0xfff0
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS 12
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* BRPHY_TOP_1588 :: MPLS_LABEL10_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE,0xf,0,x)
#define Rd_BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE,0xf,0)
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK 0x000f
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS 4
#define BRPHY_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_TX_1588_COUNTER1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_TX_1588_COUNTER1 :: RX_1588_COUNTER1 [15:08] */
#define Wr_BRPHY_TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_1588_COUNTER1,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_1588_COUNTER1,0xff00,8)
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1_MASK   0xff00
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1_ALIGN  0
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1_BITS   8
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1_SHIFT  8

/* BRPHY_TOP_1588 :: RX_TX_1588_COUNTER1 :: TX_1588_COUNTER1 [07:00] */
#define Wr_BRPHY_TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1(x) WriteRegBits16(BRPHY_TOP_1588_RX_TX_1588_COUNTER1,0xff,0,x)
#define Rd_BRPHY_TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1(x) ReadRegBits16(BRPHY_TOP_1588_RX_TX_1588_COUNTER1,0xff,0)
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1_MASK   0x00ff
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1_ALIGN  0
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1_BITS   8
#define BRPHY_TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1_SHIFT  0


/****************************************************************************
 * BRPHY_TOP_1588 :: RX_CF_SPEC
 ***************************************************************************/
/* BRPHY_TOP_1588 :: RX_CF_SPEC :: RX_CF_SPEC [15:00] */
#define Wr_BRPHY_TOP_1588_RX_CF_SPEC_RX_CF_SPEC(x) WriteReg16(BRPHY_TOP_1588_RX_CF_SPEC,x)
#define Rd_BRPHY_TOP_1588_RX_CF_SPEC_RX_CF_SPEC(x) ReadReg16(BRPHY_TOP_1588_RX_CF_SPEC)
#define BRPHY_TOP_1588_RX_CF_SPEC_RX_CF_SPEC_MASK                  0xffff
#define BRPHY_TOP_1588_RX_CF_SPEC_RX_CF_SPEC_ALIGN                 0
#define BRPHY_TOP_1588_RX_CF_SPEC_RX_CF_SPEC_BITS                  16
#define BRPHY_TOP_1588_RX_CF_SPEC_RX_CF_SPEC_SHIFT                 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TX_CF_SPEC
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TX_CF_SPEC :: TX_CF_SPEC [15:00] */
#define Wr_BRPHY_TOP_1588_TX_CF_SPEC_TX_CF_SPEC(x) WriteReg16(BRPHY_TOP_1588_TX_CF_SPEC,x)
#define Rd_BRPHY_TOP_1588_TX_CF_SPEC_TX_CF_SPEC(x) ReadReg16(BRPHY_TOP_1588_TX_CF_SPEC)
#define BRPHY_TOP_1588_TX_CF_SPEC_TX_CF_SPEC_MASK                  0xffff
#define BRPHY_TOP_1588_TX_CF_SPEC_TX_CF_SPEC_ALIGN                 0
#define BRPHY_TOP_1588_TX_CF_SPEC_TX_CF_SPEC_BITS                  16
#define BRPHY_TOP_1588_TX_CF_SPEC_TX_CF_SPEC_SHIFT                 0


/****************************************************************************
 * BRPHY_TOP_1588 :: MPLS_PACKET_ENABLE
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MPLS_PACKET_ENABLE :: MPLS_PACKET_ENABLE [15:00] */
#define Wr_BRPHY_TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE(x) WriteReg16(BRPHY_TOP_1588_MPLS_PACKET_ENABLE,x)
#define Rd_BRPHY_TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE(x) ReadReg16(BRPHY_TOP_1588_MPLS_PACKET_ENABLE)
#define BRPHY_TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE_MASK  0xffff
#define BRPHY_TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE_ALIGN 0
#define BRPHY_TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE_BITS  16
#define BRPHY_TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE_SHIFT 0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIMECODE_SEL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIMECODE_SEL :: TIMECODE_SEL [15:00] */
#define Wr_BRPHY_TOP_1588_TIMECODE_SEL_TIMECODE_SEL(x) WriteReg16(BRPHY_TOP_1588_TIMECODE_SEL,x)
#define Rd_BRPHY_TOP_1588_TIMECODE_SEL_TIMECODE_SEL(x) ReadReg16(BRPHY_TOP_1588_TIMECODE_SEL)
#define BRPHY_TOP_1588_TIMECODE_SEL_TIMECODE_SEL_MASK              0xffff
#define BRPHY_TOP_1588_TIMECODE_SEL_TIMECODE_SEL_ALIGN             0
#define BRPHY_TOP_1588_TIMECODE_SEL_TIMECODE_SEL_BITS              16
#define BRPHY_TOP_1588_TIMECODE_SEL_TIMECODE_SEL_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_3 :: TIME_STAMP_3 [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_3_TIME_STAMP_3(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_3,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_3_TIME_STAMP_3(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_3)
#define BRPHY_TOP_1588_TIME_STAMP_3_TIME_STAMP_3_MASK              0xffff
#define BRPHY_TOP_1588_TIME_STAMP_3_TIME_STAMP_3_ALIGN             0
#define BRPHY_TOP_1588_TIME_STAMP_3_TIME_STAMP_3_BITS              16
#define BRPHY_TOP_1588_TIME_STAMP_3_TIME_STAMP_3_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP :: TIME_STAMP [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_TIME_STAMP(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_TIME_STAMP(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP)
#define BRPHY_TOP_1588_TIME_STAMP_TIME_STAMP_MASK                  0xffff
#define BRPHY_TOP_1588_TIME_STAMP_TIME_STAMP_ALIGN                 0
#define BRPHY_TOP_1588_TIME_STAMP_TIME_STAMP_BITS                  16
#define BRPHY_TOP_1588_TIME_STAMP_TIME_STAMP_SHIFT                 0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_TX_CNTL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_TX_CNTL :: SPARE_REG [15:10] */
#define Wr_BRPHY_TOP_1588_DM_TX_CNTL_SPARE_REG(x) WriteRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0xfc00,10,x)
#define Rd_BRPHY_TOP_1588_DM_TX_CNTL_SPARE_REG(x) ReadRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0xfc00,10)
#define BRPHY_TOP_1588_DM_TX_CNTL_SPARE_REG_MASK                   0xfc00
#define BRPHY_TOP_1588_DM_TX_CNTL_SPARE_REG_ALIGN                  0
#define BRPHY_TOP_1588_DM_TX_CNTL_SPARE_REG_BITS                   6
#define BRPHY_TOP_1588_DM_TX_CNTL_SPARE_REG_SHIFT                  10

/* BRPHY_TOP_1588 :: DM_TX_CNTL :: IETF_SEL [09:06] */
#define Wr_BRPHY_TOP_1588_DM_TX_CNTL_IETF_SEL(x) WriteRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x3c0,6,x)
#define Rd_BRPHY_TOP_1588_DM_TX_CNTL_IETF_SEL(x) ReadRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x3c0,6)
#define BRPHY_TOP_1588_DM_TX_CNTL_IETF_SEL_MASK                    0x03c0
#define BRPHY_TOP_1588_DM_TX_CNTL_IETF_SEL_ALIGN                   0
#define BRPHY_TOP_1588_DM_TX_CNTL_IETF_SEL_BITS                    4
#define BRPHY_TOP_1588_DM_TX_CNTL_IETF_SEL_SHIFT                   6

/* BRPHY_TOP_1588 :: DM_TX_CNTL :: BHH_TS_SEL [05:05] */
#define Wr_BRPHY_TOP_1588_DM_TX_CNTL_BHH_TS_SEL(x) WriteRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x20,5,x)
#define Rd_BRPHY_TOP_1588_DM_TX_CNTL_BHH_TS_SEL(x) ReadRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x20,5)
#define BRPHY_TOP_1588_DM_TX_CNTL_BHH_TS_SEL_MASK                  0x0020
#define BRPHY_TOP_1588_DM_TX_CNTL_BHH_TS_SEL_ALIGN                 0
#define BRPHY_TOP_1588_DM_TX_CNTL_BHH_TS_SEL_BITS                  1
#define BRPHY_TOP_1588_DM_TX_CNTL_BHH_TS_SEL_SHIFT                 5

/* BRPHY_TOP_1588 :: DM_TX_CNTL :: Y1731_TS_SEL [04:04] */
#define Wr_BRPHY_TOP_1588_DM_TX_CNTL_Y1731_TS_SEL(x) WriteRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x10,4,x)
#define Rd_BRPHY_TOP_1588_DM_TX_CNTL_Y1731_TS_SEL(x) ReadRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x10,4)
#define BRPHY_TOP_1588_DM_TX_CNTL_Y1731_TS_SEL_MASK                0x0010
#define BRPHY_TOP_1588_DM_TX_CNTL_Y1731_TS_SEL_ALIGN               0
#define BRPHY_TOP_1588_DM_TX_CNTL_Y1731_TS_SEL_BITS                1
#define BRPHY_TOP_1588_DM_TX_CNTL_Y1731_TS_SEL_SHIFT               4

/* BRPHY_TOP_1588 :: DM_TX_CNTL :: ENTROPY_EN [03:03] */
#define Wr_BRPHY_TOP_1588_DM_TX_CNTL_ENTROPY_EN(x) WriteRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x8,3,x)
#define Rd_BRPHY_TOP_1588_DM_TX_CNTL_ENTROPY_EN(x) ReadRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x8,3)
#define BRPHY_TOP_1588_DM_TX_CNTL_ENTROPY_EN_MASK                  0x0008
#define BRPHY_TOP_1588_DM_TX_CNTL_ENTROPY_EN_ALIGN                 0
#define BRPHY_TOP_1588_DM_TX_CNTL_ENTROPY_EN_BITS                  1
#define BRPHY_TOP_1588_DM_TX_CNTL_ENTROPY_EN_SHIFT                 3

/* BRPHY_TOP_1588 :: DM_TX_CNTL :: CW_EN [02:02] */
#define Wr_BRPHY_TOP_1588_DM_TX_CNTL_CW_EN(x) WriteRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x4,2,x)
#define Rd_BRPHY_TOP_1588_DM_TX_CNTL_CW_EN(x) ReadRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x4,2)
#define BRPHY_TOP_1588_DM_TX_CNTL_CW_EN_MASK                       0x0004
#define BRPHY_TOP_1588_DM_TX_CNTL_CW_EN_ALIGN                      0
#define BRPHY_TOP_1588_DM_TX_CNTL_CW_EN_BITS                       1
#define BRPHY_TOP_1588_DM_TX_CNTL_CW_EN_SHIFT                      2

/* BRPHY_TOP_1588 :: DM_TX_CNTL :: MAC_EN [01:01] */
#define Wr_BRPHY_TOP_1588_DM_TX_CNTL_MAC_EN(x) WriteRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x2,1,x)
#define Rd_BRPHY_TOP_1588_DM_TX_CNTL_MAC_EN(x) ReadRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x2,1)
#define BRPHY_TOP_1588_DM_TX_CNTL_MAC_EN_MASK                      0x0002
#define BRPHY_TOP_1588_DM_TX_CNTL_MAC_EN_ALIGN                     0
#define BRPHY_TOP_1588_DM_TX_CNTL_MAC_EN_BITS                      1
#define BRPHY_TOP_1588_DM_TX_CNTL_MAC_EN_SHIFT                     1

/* BRPHY_TOP_1588 :: DM_TX_CNTL :: EN [00:00] */
#define Wr_BRPHY_TOP_1588_DM_TX_CNTL_EN(x) WriteRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x1,0,x)
#define Rd_BRPHY_TOP_1588_DM_TX_CNTL_EN(x) ReadRegBits16(BRPHY_TOP_1588_DM_TX_CNTL,0x1,0)
#define BRPHY_TOP_1588_DM_TX_CNTL_EN_MASK                          0x0001
#define BRPHY_TOP_1588_DM_TX_CNTL_EN_ALIGN                         0
#define BRPHY_TOP_1588_DM_TX_CNTL_EN_BITS                          1
#define BRPHY_TOP_1588_DM_TX_CNTL_EN_SHIFT                         0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_RX_CNTL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_RX_CNTL :: SPARE_REG [15:10] */
#define Wr_BRPHY_TOP_1588_DM_RX_CNTL_SPARE_REG(x) WriteRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0xfc00,10,x)
#define Rd_BRPHY_TOP_1588_DM_RX_CNTL_SPARE_REG(x) ReadRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0xfc00,10)
#define BRPHY_TOP_1588_DM_RX_CNTL_SPARE_REG_MASK                   0xfc00
#define BRPHY_TOP_1588_DM_RX_CNTL_SPARE_REG_ALIGN                  0
#define BRPHY_TOP_1588_DM_RX_CNTL_SPARE_REG_BITS                   6
#define BRPHY_TOP_1588_DM_RX_CNTL_SPARE_REG_SHIFT                  10

/* BRPHY_TOP_1588 :: DM_RX_CNTL :: IETF_SEL [09:06] */
#define Wr_BRPHY_TOP_1588_DM_RX_CNTL_IETF_SEL(x) WriteRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x3c0,6,x)
#define Rd_BRPHY_TOP_1588_DM_RX_CNTL_IETF_SEL(x) ReadRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x3c0,6)
#define BRPHY_TOP_1588_DM_RX_CNTL_IETF_SEL_MASK                    0x03c0
#define BRPHY_TOP_1588_DM_RX_CNTL_IETF_SEL_ALIGN                   0
#define BRPHY_TOP_1588_DM_RX_CNTL_IETF_SEL_BITS                    4
#define BRPHY_TOP_1588_DM_RX_CNTL_IETF_SEL_SHIFT                   6

/* BRPHY_TOP_1588 :: DM_RX_CNTL :: BHH_TS_SEL [05:05] */
#define Wr_BRPHY_TOP_1588_DM_RX_CNTL_BHH_TS_SEL(x) WriteRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x20,5,x)
#define Rd_BRPHY_TOP_1588_DM_RX_CNTL_BHH_TS_SEL(x) ReadRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x20,5)
#define BRPHY_TOP_1588_DM_RX_CNTL_BHH_TS_SEL_MASK                  0x0020
#define BRPHY_TOP_1588_DM_RX_CNTL_BHH_TS_SEL_ALIGN                 0
#define BRPHY_TOP_1588_DM_RX_CNTL_BHH_TS_SEL_BITS                  1
#define BRPHY_TOP_1588_DM_RX_CNTL_BHH_TS_SEL_SHIFT                 5

/* BRPHY_TOP_1588 :: DM_RX_CNTL :: Y1731_TS_SEL [04:04] */
#define Wr_BRPHY_TOP_1588_DM_RX_CNTL_Y1731_TS_SEL(x) WriteRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x10,4,x)
#define Rd_BRPHY_TOP_1588_DM_RX_CNTL_Y1731_TS_SEL(x) ReadRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x10,4)
#define BRPHY_TOP_1588_DM_RX_CNTL_Y1731_TS_SEL_MASK                0x0010
#define BRPHY_TOP_1588_DM_RX_CNTL_Y1731_TS_SEL_ALIGN               0
#define BRPHY_TOP_1588_DM_RX_CNTL_Y1731_TS_SEL_BITS                1
#define BRPHY_TOP_1588_DM_RX_CNTL_Y1731_TS_SEL_SHIFT               4

/* BRPHY_TOP_1588 :: DM_RX_CNTL :: ENTROPY_EN [03:03] */
#define Wr_BRPHY_TOP_1588_DM_RX_CNTL_ENTROPY_EN(x) WriteRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x8,3,x)
#define Rd_BRPHY_TOP_1588_DM_RX_CNTL_ENTROPY_EN(x) ReadRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x8,3)
#define BRPHY_TOP_1588_DM_RX_CNTL_ENTROPY_EN_MASK                  0x0008
#define BRPHY_TOP_1588_DM_RX_CNTL_ENTROPY_EN_ALIGN                 0
#define BRPHY_TOP_1588_DM_RX_CNTL_ENTROPY_EN_BITS                  1
#define BRPHY_TOP_1588_DM_RX_CNTL_ENTROPY_EN_SHIFT                 3

/* BRPHY_TOP_1588 :: DM_RX_CNTL :: CW_EN [02:02] */
#define Wr_BRPHY_TOP_1588_DM_RX_CNTL_CW_EN(x) WriteRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x4,2,x)
#define Rd_BRPHY_TOP_1588_DM_RX_CNTL_CW_EN(x) ReadRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x4,2)
#define BRPHY_TOP_1588_DM_RX_CNTL_CW_EN_MASK                       0x0004
#define BRPHY_TOP_1588_DM_RX_CNTL_CW_EN_ALIGN                      0
#define BRPHY_TOP_1588_DM_RX_CNTL_CW_EN_BITS                       1
#define BRPHY_TOP_1588_DM_RX_CNTL_CW_EN_SHIFT                      2

/* BRPHY_TOP_1588 :: DM_RX_CNTL :: MAC_EN [01:01] */
#define Wr_BRPHY_TOP_1588_DM_RX_CNTL_MAC_EN(x) WriteRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x2,1,x)
#define Rd_BRPHY_TOP_1588_DM_RX_CNTL_MAC_EN(x) ReadRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x2,1)
#define BRPHY_TOP_1588_DM_RX_CNTL_MAC_EN_MASK                      0x0002
#define BRPHY_TOP_1588_DM_RX_CNTL_MAC_EN_ALIGN                     0
#define BRPHY_TOP_1588_DM_RX_CNTL_MAC_EN_BITS                      1
#define BRPHY_TOP_1588_DM_RX_CNTL_MAC_EN_SHIFT                     1

/* BRPHY_TOP_1588 :: DM_RX_CNTL :: EN [00:00] */
#define Wr_BRPHY_TOP_1588_DM_RX_CNTL_EN(x) WriteRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x1,0,x)
#define Rd_BRPHY_TOP_1588_DM_RX_CNTL_EN(x) ReadRegBits16(BRPHY_TOP_1588_DM_RX_CNTL,0x1,0)
#define BRPHY_TOP_1588_DM_RX_CNTL_EN_MASK                          0x0001
#define BRPHY_TOP_1588_DM_RX_CNTL_EN_ALIGN                         0
#define BRPHY_TOP_1588_DM_RX_CNTL_EN_BITS                          1
#define BRPHY_TOP_1588_DM_RX_CNTL_EN_SHIFT                         0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE1 :: DM_ETHTYPE1 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE1,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE1)
#define BRPHY_TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1_MASK                0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1_ALIGN               0
#define BRPHY_TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1_BITS                16
#define BRPHY_TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE2 :: DM_ETHTYPE2 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE2,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE2)
#define BRPHY_TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2_MASK                0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2_ALIGN               0
#define BRPHY_TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2_BITS                16
#define BRPHY_TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE3 :: DM_ETHTYPE3 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE3,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE3)
#define BRPHY_TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3_MASK                0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3_ALIGN               0
#define BRPHY_TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3_BITS                16
#define BRPHY_TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE4 :: DM_ETHTYPE4 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE4,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE4)
#define BRPHY_TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4_MASK                0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4_ALIGN               0
#define BRPHY_TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4_BITS                16
#define BRPHY_TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE5
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE5 :: DM_ETHTYPE5 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE5,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE5)
#define BRPHY_TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5_MASK                0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5_ALIGN               0
#define BRPHY_TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5_BITS                16
#define BRPHY_TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE6
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE6 :: DM_ETHTYPE6 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE6,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE6)
#define BRPHY_TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6_MASK                0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6_ALIGN               0
#define BRPHY_TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6_BITS                16
#define BRPHY_TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE7
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE7 :: DM_ETHTYPE7 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE7,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE7)
#define BRPHY_TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7_MASK                0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7_ALIGN               0
#define BRPHY_TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7_BITS                16
#define BRPHY_TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE8
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE8 :: DM_ETHTYPE8 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE8,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE8)
#define BRPHY_TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8_MASK                0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8_ALIGN               0
#define BRPHY_TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8_BITS                16
#define BRPHY_TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE9
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE9 :: DM_ETHTYPE9 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE9,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE9)
#define BRPHY_TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9_MASK                0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9_ALIGN               0
#define BRPHY_TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9_BITS                16
#define BRPHY_TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE10
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE10 :: DM_ETHTYPE10 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE10,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE10)
#define BRPHY_TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10_MASK              0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10_ALIGN             0
#define BRPHY_TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10_BITS              16
#define BRPHY_TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE11
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE11 :: DM_ETHTYPE11 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE11,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE11)
#define BRPHY_TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11_MASK              0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11_ALIGN             0
#define BRPHY_TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11_BITS              16
#define BRPHY_TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE12
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE12 :: DM_ETHTYPE12 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE12,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE12)
#define BRPHY_TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12_MASK              0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12_ALIGN             0
#define BRPHY_TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12_BITS              16
#define BRPHY_TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_ETHTYPE13
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_ETHTYPE13 :: DM_ETHTYPE13 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13(x) WriteReg16(BRPHY_TOP_1588_DM_ETHTYPE13,x)
#define Rd_BRPHY_TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13(x) ReadReg16(BRPHY_TOP_1588_DM_ETHTYPE13)
#define BRPHY_TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13_MASK              0xffff
#define BRPHY_TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13_ALIGN             0
#define BRPHY_TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13_BITS              16
#define BRPHY_TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_IETF_OFFSET
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_IETF_OFFSET :: RX_OFFSET [15:08] */
#define Wr_BRPHY_TOP_1588_DM_IETF_OFFSET_RX_OFFSET(x) WriteRegBits16(BRPHY_TOP_1588_DM_IETF_OFFSET,0xff00,8,x)
#define Rd_BRPHY_TOP_1588_DM_IETF_OFFSET_RX_OFFSET(x) ReadRegBits16(BRPHY_TOP_1588_DM_IETF_OFFSET,0xff00,8)
#define BRPHY_TOP_1588_DM_IETF_OFFSET_RX_OFFSET_MASK               0xff00
#define BRPHY_TOP_1588_DM_IETF_OFFSET_RX_OFFSET_ALIGN              0
#define BRPHY_TOP_1588_DM_IETF_OFFSET_RX_OFFSET_BITS               8
#define BRPHY_TOP_1588_DM_IETF_OFFSET_RX_OFFSET_SHIFT              8

/* BRPHY_TOP_1588 :: DM_IETF_OFFSET :: TX_OFFSET [07:00] */
#define Wr_BRPHY_TOP_1588_DM_IETF_OFFSET_TX_OFFSET(x) WriteRegBits16(BRPHY_TOP_1588_DM_IETF_OFFSET,0xff,0,x)
#define Rd_BRPHY_TOP_1588_DM_IETF_OFFSET_TX_OFFSET(x) ReadRegBits16(BRPHY_TOP_1588_DM_IETF_OFFSET,0xff,0)
#define BRPHY_TOP_1588_DM_IETF_OFFSET_TX_OFFSET_MASK               0x00ff
#define BRPHY_TOP_1588_DM_IETF_OFFSET_TX_OFFSET_ALIGN              0
#define BRPHY_TOP_1588_DM_IETF_OFFSET_TX_OFFSET_BITS               8
#define BRPHY_TOP_1588_DM_IETF_OFFSET_TX_OFFSET_SHIFT              0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_TIME_STAMP_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_TIME_STAMP_0 :: NTP_TIME_STAMP_0 [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0(x) WriteReg16(BRPHY_TOP_1588_NTP_TIME_STAMP_0,x)
#define Rd_BRPHY_TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0(x) ReadReg16(BRPHY_TOP_1588_NTP_TIME_STAMP_0)
#define BRPHY_TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0_MASK      0xffff
#define BRPHY_TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0_ALIGN     0
#define BRPHY_TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0_BITS      16
#define BRPHY_TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_TIME_STAMP_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_TIME_STAMP_1 :: NTP_TIME_STAMP_1 [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1(x) WriteReg16(BRPHY_TOP_1588_NTP_TIME_STAMP_1,x)
#define Rd_BRPHY_TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1(x) ReadReg16(BRPHY_TOP_1588_NTP_TIME_STAMP_1)
#define BRPHY_TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1_MASK      0xffff
#define BRPHY_TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1_ALIGN     0
#define BRPHY_TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1_BITS      16
#define BRPHY_TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_TIME_STAMP_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_TIME_STAMP_2 :: NTP_TIME_STAMP_2 [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2(x) WriteReg16(BRPHY_TOP_1588_NTP_TIME_STAMP_2,x)
#define Rd_BRPHY_TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2(x) ReadReg16(BRPHY_TOP_1588_NTP_TIME_STAMP_2)
#define BRPHY_TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2_MASK      0xffff
#define BRPHY_TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2_ALIGN     0
#define BRPHY_TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2_BITS      16
#define BRPHY_TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_TIME_STAMP_3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_TIME_STAMP_3 :: NTP_TIME_STAMP_3 [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3(x) WriteReg16(BRPHY_TOP_1588_NTP_TIME_STAMP_3,x)
#define Rd_BRPHY_TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3(x) ReadReg16(BRPHY_TOP_1588_NTP_TIME_STAMP_3)
#define BRPHY_TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3_MASK      0xffff
#define BRPHY_TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3_ALIGN     0
#define BRPHY_TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3_BITS      16
#define BRPHY_TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_NCO_FREQ_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_NCO_FREQ_0 :: NTP_NCO_FREQ_0 [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0(x) WriteReg16(BRPHY_TOP_1588_NTP_NCO_FREQ_0,x)
#define Rd_BRPHY_TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0(x) ReadReg16(BRPHY_TOP_1588_NTP_NCO_FREQ_0)
#define BRPHY_TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0_MASK          0xffff
#define BRPHY_TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0_ALIGN         0
#define BRPHY_TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0_BITS          16
#define BRPHY_TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0_SHIFT         0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_NCO_FREQ_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_NCO_FREQ_1 :: NTP_NCO_FREQ_1 [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1(x) WriteReg16(BRPHY_TOP_1588_NTP_NCO_FREQ_1,x)
#define Rd_BRPHY_TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1(x) ReadReg16(BRPHY_TOP_1588_NTP_NCO_FREQ_1)
#define BRPHY_TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1_MASK          0xffff
#define BRPHY_TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1_ALIGN         0
#define BRPHY_TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1_BITS          16
#define BRPHY_TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1_SHIFT         0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_DOWN_CNTER_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_DOWN_CNTER_0 :: NTP_DOWN_CNTER_0 [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0(x) WriteReg16(BRPHY_TOP_1588_NTP_DOWN_CNTER_0,x)
#define Rd_BRPHY_TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0(x) ReadReg16(BRPHY_TOP_1588_NTP_DOWN_CNTER_0)
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0_MASK      0xffff
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0_ALIGN     0
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0_BITS      16
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_DOWN_CNTER_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_DOWN_CNTER_1 :: NTP_DOWN_CNTER_1 [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1(x) WriteReg16(BRPHY_TOP_1588_NTP_DOWN_CNTER_1,x)
#define Rd_BRPHY_TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1(x) ReadReg16(BRPHY_TOP_1588_NTP_DOWN_CNTER_1)
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1_MASK      0xffff
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1_ALIGN     0
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1_BITS      16
#define BRPHY_TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_ERR_LSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_ERR_LSB :: NTP_ERR_LSB [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB(x) WriteReg16(BRPHY_TOP_1588_NTP_ERR_LSB,x)
#define Rd_BRPHY_TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB(x) ReadReg16(BRPHY_TOP_1588_NTP_ERR_LSB)
#define BRPHY_TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB_MASK                0xffff
#define BRPHY_TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB_ALIGN               0
#define BRPHY_TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB_BITS                16
#define BRPHY_TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: NTP_ERR_MSB
 ***************************************************************************/
/* BRPHY_TOP_1588 :: NTP_ERR_MSB :: NTP_ERR_MSB [15:00] */
#define Wr_BRPHY_TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB(x) WriteReg16(BRPHY_TOP_1588_NTP_ERR_MSB,x)
#define Rd_BRPHY_TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB(x) ReadReg16(BRPHY_TOP_1588_NTP_ERR_MSB)
#define BRPHY_TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB_MASK                0xffff
#define BRPHY_TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB_ALIGN               0
#define BRPHY_TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB_BITS                16
#define BRPHY_TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_L1_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_L1_0 :: DM_DA1 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_L1_0_DM_DA1(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_L1_0,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_L1_0_DM_DA1(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_L1_0)
#define BRPHY_TOP_1588_DM_MAC_L1_0_DM_DA1_MASK                     0xffff
#define BRPHY_TOP_1588_DM_MAC_L1_0_DM_DA1_ALIGN                    0
#define BRPHY_TOP_1588_DM_MAC_L1_0_DM_DA1_BITS                     16
#define BRPHY_TOP_1588_DM_MAC_L1_0_DM_DA1_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_L1_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_L1_1 :: DM_DA2 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_L1_1_DM_DA2(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_L1_1,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_L1_1_DM_DA2(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_L1_1)
#define BRPHY_TOP_1588_DM_MAC_L1_1_DM_DA2_MASK                     0xffff
#define BRPHY_TOP_1588_DM_MAC_L1_1_DM_DA2_ALIGN                    0
#define BRPHY_TOP_1588_DM_MAC_L1_1_DM_DA2_BITS                     16
#define BRPHY_TOP_1588_DM_MAC_L1_1_DM_DA2_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_L1_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_L1_2 :: DM_DA3 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_L1_2_DM_DA3(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_L1_2,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_L1_2_DM_DA3(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_L1_2)
#define BRPHY_TOP_1588_DM_MAC_L1_2_DM_DA3_MASK                     0xffff
#define BRPHY_TOP_1588_DM_MAC_L1_2_DM_DA3_ALIGN                    0
#define BRPHY_TOP_1588_DM_MAC_L1_2_DM_DA3_BITS                     16
#define BRPHY_TOP_1588_DM_MAC_L1_2_DM_DA3_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_L2_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_L2_0 :: DM_DA1 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_L2_0_DM_DA1(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_L2_0,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_L2_0_DM_DA1(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_L2_0)
#define BRPHY_TOP_1588_DM_MAC_L2_0_DM_DA1_MASK                     0xffff
#define BRPHY_TOP_1588_DM_MAC_L2_0_DM_DA1_ALIGN                    0
#define BRPHY_TOP_1588_DM_MAC_L2_0_DM_DA1_BITS                     16
#define BRPHY_TOP_1588_DM_MAC_L2_0_DM_DA1_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_L2_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_L2_1 :: DM_DA2 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_L2_1_DM_DA2(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_L2_1,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_L2_1_DM_DA2(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_L2_1)
#define BRPHY_TOP_1588_DM_MAC_L2_1_DM_DA2_MASK                     0xffff
#define BRPHY_TOP_1588_DM_MAC_L2_1_DM_DA2_ALIGN                    0
#define BRPHY_TOP_1588_DM_MAC_L2_1_DM_DA2_BITS                     16
#define BRPHY_TOP_1588_DM_MAC_L2_1_DM_DA2_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_L2_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_L2_2 :: DM_DA3 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_L2_2_DM_DA3(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_L2_2,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_L2_2_DM_DA3(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_L2_2)
#define BRPHY_TOP_1588_DM_MAC_L2_2_DM_DA3_MASK                     0xffff
#define BRPHY_TOP_1588_DM_MAC_L2_2_DM_DA3_ALIGN                    0
#define BRPHY_TOP_1588_DM_MAC_L2_2_DM_DA3_BITS                     16
#define BRPHY_TOP_1588_DM_MAC_L2_2_DM_DA3_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_L3_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_L3_0 :: DM_DA1 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_L3_0_DM_DA1(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_L3_0,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_L3_0_DM_DA1(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_L3_0)
#define BRPHY_TOP_1588_DM_MAC_L3_0_DM_DA1_MASK                     0xffff
#define BRPHY_TOP_1588_DM_MAC_L3_0_DM_DA1_ALIGN                    0
#define BRPHY_TOP_1588_DM_MAC_L3_0_DM_DA1_BITS                     16
#define BRPHY_TOP_1588_DM_MAC_L3_0_DM_DA1_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_L3_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_L3_1 :: DM_DA2 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_L3_1_DM_DA2(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_L3_1,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_L3_1_DM_DA2(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_L3_1)
#define BRPHY_TOP_1588_DM_MAC_L3_1_DM_DA2_MASK                     0xffff
#define BRPHY_TOP_1588_DM_MAC_L3_1_DM_DA2_ALIGN                    0
#define BRPHY_TOP_1588_DM_MAC_L3_1_DM_DA2_BITS                     16
#define BRPHY_TOP_1588_DM_MAC_L3_1_DM_DA2_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_L3_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_L3_2 :: DM_DA3 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_L3_2_DM_DA3(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_L3_2,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_L3_2_DM_DA3(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_L3_2)
#define BRPHY_TOP_1588_DM_MAC_L3_2_DM_DA3_MASK                     0xffff
#define BRPHY_TOP_1588_DM_MAC_L3_2_DM_DA3_ALIGN                    0
#define BRPHY_TOP_1588_DM_MAC_L3_2_DM_DA3_BITS                     16
#define BRPHY_TOP_1588_DM_MAC_L3_2_DM_DA3_SHIFT                    0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_CTL_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_CTL_0 :: DM_DA1 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_CTL_0_DM_DA1(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_CTL_0,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_CTL_0_DM_DA1(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_CTL_0)
#define BRPHY_TOP_1588_DM_MAC_CTL_0_DM_DA1_MASK                    0xffff
#define BRPHY_TOP_1588_DM_MAC_CTL_0_DM_DA1_ALIGN                   0
#define BRPHY_TOP_1588_DM_MAC_CTL_0_DM_DA1_BITS                    16
#define BRPHY_TOP_1588_DM_MAC_CTL_0_DM_DA1_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_CTL_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_CTL_1 :: DM_DA2 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_CTL_1_DM_DA2(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_CTL_1,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_CTL_1_DM_DA2(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_CTL_1)
#define BRPHY_TOP_1588_DM_MAC_CTL_1_DM_DA2_MASK                    0xffff
#define BRPHY_TOP_1588_DM_MAC_CTL_1_DM_DA2_ALIGN                   0
#define BRPHY_TOP_1588_DM_MAC_CTL_1_DM_DA2_BITS                    16
#define BRPHY_TOP_1588_DM_MAC_CTL_1_DM_DA2_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: DM_MAC_CTL_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: DM_MAC_CTL_2 :: DM_DA3 [15:00] */
#define Wr_BRPHY_TOP_1588_DM_MAC_CTL_2_DM_DA3(x) WriteReg16(BRPHY_TOP_1588_DM_MAC_CTL_2,x)
#define Rd_BRPHY_TOP_1588_DM_MAC_CTL_2_DM_DA3(x) ReadReg16(BRPHY_TOP_1588_DM_MAC_CTL_2)
#define BRPHY_TOP_1588_DM_MAC_CTL_2_DM_DA3_MASK                    0xffff
#define BRPHY_TOP_1588_DM_MAC_CTL_2_DM_DA3_ALIGN                   0
#define BRPHY_TOP_1588_DM_MAC_CTL_2_DM_DA3_BITS                    16
#define BRPHY_TOP_1588_DM_MAC_CTL_2_DM_DA3_SHIFT                   0


/****************************************************************************
 * BRPHY_TOP_1588 :: HEARTBEAT_3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: HEARTBEAT_3 :: HEARTBEAT_3 [15:00] */
#define Wr_BRPHY_TOP_1588_HEARTBEAT_3_HEARTBEAT_3(x) WriteReg16(BRPHY_TOP_1588_HEARTBEAT_3,x)
#define Rd_BRPHY_TOP_1588_HEARTBEAT_3_HEARTBEAT_3(x) ReadReg16(BRPHY_TOP_1588_HEARTBEAT_3)
#define BRPHY_TOP_1588_HEARTBEAT_3_HEARTBEAT_3_MASK                0xffff
#define BRPHY_TOP_1588_HEARTBEAT_3_HEARTBEAT_3_ALIGN               0
#define BRPHY_TOP_1588_HEARTBEAT_3_HEARTBEAT_3_BITS                16
#define BRPHY_TOP_1588_HEARTBEAT_3_HEARTBEAT_3_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: HEARTBEAT_4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: HEARTBEAT_4 :: HEARTBEAT_4 [15:00] */
#define Wr_BRPHY_TOP_1588_HEARTBEAT_4_HEARTBEAT_4(x) WriteReg16(BRPHY_TOP_1588_HEARTBEAT_4,x)
#define Rd_BRPHY_TOP_1588_HEARTBEAT_4_HEARTBEAT_4(x) ReadReg16(BRPHY_TOP_1588_HEARTBEAT_4)
#define BRPHY_TOP_1588_HEARTBEAT_4_HEARTBEAT_4_MASK                0xffff
#define BRPHY_TOP_1588_HEARTBEAT_4_HEARTBEAT_4_ALIGN               0
#define BRPHY_TOP_1588_HEARTBEAT_4_HEARTBEAT_4_BITS                16
#define BRPHY_TOP_1588_HEARTBEAT_4_HEARTBEAT_4_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: INBAND_CNTL_0
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INBAND_CNTL_0 :: INBAND_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_INBAND_CNTL_0_INBAND_CNTL(x) WriteReg16(BRPHY_TOP_1588_INBAND_CNTL_0,x)
#define Rd_BRPHY_TOP_1588_INBAND_CNTL_0_INBAND_CNTL(x) ReadReg16(BRPHY_TOP_1588_INBAND_CNTL_0)
#define BRPHY_TOP_1588_INBAND_CNTL_0_INBAND_CNTL_MASK              0xffff
#define BRPHY_TOP_1588_INBAND_CNTL_0_INBAND_CNTL_ALIGN             0
#define BRPHY_TOP_1588_INBAND_CNTL_0_INBAND_CNTL_BITS              16
#define BRPHY_TOP_1588_INBAND_CNTL_0_INBAND_CNTL_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: INBAND_CNTL_1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INBAND_CNTL_1 :: INBAND_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_INBAND_CNTL_1_INBAND_CNTL(x) WriteReg16(BRPHY_TOP_1588_INBAND_CNTL_1,x)
#define Rd_BRPHY_TOP_1588_INBAND_CNTL_1_INBAND_CNTL(x) ReadReg16(BRPHY_TOP_1588_INBAND_CNTL_1)
#define BRPHY_TOP_1588_INBAND_CNTL_1_INBAND_CNTL_MASK              0xffff
#define BRPHY_TOP_1588_INBAND_CNTL_1_INBAND_CNTL_ALIGN             0
#define BRPHY_TOP_1588_INBAND_CNTL_1_INBAND_CNTL_BITS              16
#define BRPHY_TOP_1588_INBAND_CNTL_1_INBAND_CNTL_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: INBAND_CNTL_2
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INBAND_CNTL_2 :: INBAND_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_INBAND_CNTL_2_INBAND_CNTL(x) WriteReg16(BRPHY_TOP_1588_INBAND_CNTL_2,x)
#define Rd_BRPHY_TOP_1588_INBAND_CNTL_2_INBAND_CNTL(x) ReadReg16(BRPHY_TOP_1588_INBAND_CNTL_2)
#define BRPHY_TOP_1588_INBAND_CNTL_2_INBAND_CNTL_MASK              0xffff
#define BRPHY_TOP_1588_INBAND_CNTL_2_INBAND_CNTL_ALIGN             0
#define BRPHY_TOP_1588_INBAND_CNTL_2_INBAND_CNTL_BITS              16
#define BRPHY_TOP_1588_INBAND_CNTL_2_INBAND_CNTL_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: INBAND_CNTL_3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INBAND_CNTL_3 :: INBAND_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_INBAND_CNTL_3_INBAND_CNTL(x) WriteReg16(BRPHY_TOP_1588_INBAND_CNTL_3,x)
#define Rd_BRPHY_TOP_1588_INBAND_CNTL_3_INBAND_CNTL(x) ReadReg16(BRPHY_TOP_1588_INBAND_CNTL_3)
#define BRPHY_TOP_1588_INBAND_CNTL_3_INBAND_CNTL_MASK              0xffff
#define BRPHY_TOP_1588_INBAND_CNTL_3_INBAND_CNTL_ALIGN             0
#define BRPHY_TOP_1588_INBAND_CNTL_3_INBAND_CNTL_BITS              16
#define BRPHY_TOP_1588_INBAND_CNTL_3_INBAND_CNTL_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: INBAND_CNTL_4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INBAND_CNTL_4 :: INBAND_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_INBAND_CNTL_4_INBAND_CNTL(x) WriteReg16(BRPHY_TOP_1588_INBAND_CNTL_4,x)
#define Rd_BRPHY_TOP_1588_INBAND_CNTL_4_INBAND_CNTL(x) ReadReg16(BRPHY_TOP_1588_INBAND_CNTL_4)
#define BRPHY_TOP_1588_INBAND_CNTL_4_INBAND_CNTL_MASK              0xffff
#define BRPHY_TOP_1588_INBAND_CNTL_4_INBAND_CNTL_ALIGN             0
#define BRPHY_TOP_1588_INBAND_CNTL_4_INBAND_CNTL_BITS              16
#define BRPHY_TOP_1588_INBAND_CNTL_4_INBAND_CNTL_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: INBAND_CNTL_5
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INBAND_CNTL_5 :: INBAND_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_INBAND_CNTL_5_INBAND_CNTL(x) WriteReg16(BRPHY_TOP_1588_INBAND_CNTL_5,x)
#define Rd_BRPHY_TOP_1588_INBAND_CNTL_5_INBAND_CNTL(x) ReadReg16(BRPHY_TOP_1588_INBAND_CNTL_5)
#define BRPHY_TOP_1588_INBAND_CNTL_5_INBAND_CNTL_MASK              0xffff
#define BRPHY_TOP_1588_INBAND_CNTL_5_INBAND_CNTL_ALIGN             0
#define BRPHY_TOP_1588_INBAND_CNTL_5_INBAND_CNTL_BITS              16
#define BRPHY_TOP_1588_INBAND_CNTL_5_INBAND_CNTL_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: INBAND_CNTL_6
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INBAND_CNTL_6 :: INBAND_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_INBAND_CNTL_6_INBAND_CNTL(x) WriteReg16(BRPHY_TOP_1588_INBAND_CNTL_6,x)
#define Rd_BRPHY_TOP_1588_INBAND_CNTL_6_INBAND_CNTL(x) ReadReg16(BRPHY_TOP_1588_INBAND_CNTL_6)
#define BRPHY_TOP_1588_INBAND_CNTL_6_INBAND_CNTL_MASK              0xffff
#define BRPHY_TOP_1588_INBAND_CNTL_6_INBAND_CNTL_ALIGN             0
#define BRPHY_TOP_1588_INBAND_CNTL_6_INBAND_CNTL_BITS              16
#define BRPHY_TOP_1588_INBAND_CNTL_6_INBAND_CNTL_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: INBAND_CNTL_7
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INBAND_CNTL_7 :: INBAND_CNTL [15:00] */
#define Wr_BRPHY_TOP_1588_INBAND_CNTL_7_INBAND_CNTL(x) WriteReg16(BRPHY_TOP_1588_INBAND_CNTL_7,x)
#define Rd_BRPHY_TOP_1588_INBAND_CNTL_7_INBAND_CNTL(x) ReadReg16(BRPHY_TOP_1588_INBAND_CNTL_7)
#define BRPHY_TOP_1588_INBAND_CNTL_7_INBAND_CNTL_MASK              0xffff
#define BRPHY_TOP_1588_INBAND_CNTL_7_INBAND_CNTL_ALIGN             0
#define BRPHY_TOP_1588_INBAND_CNTL_7_INBAND_CNTL_BITS              16
#define BRPHY_TOP_1588_INBAND_CNTL_7_INBAND_CNTL_SHIFT             0


/****************************************************************************
 * BRPHY_TOP_1588 :: MEM_COUNTER
 ***************************************************************************/
/* BRPHY_TOP_1588 :: MEM_COUNTER :: MEM_COUNTER [15:00] */
#define Wr_BRPHY_TOP_1588_MEM_COUNTER_MEM_COUNTER(x) WriteReg16(BRPHY_TOP_1588_MEM_COUNTER,x)
#define Rd_BRPHY_TOP_1588_MEM_COUNTER_MEM_COUNTER(x) ReadReg16(BRPHY_TOP_1588_MEM_COUNTER)
#define BRPHY_TOP_1588_MEM_COUNTER_MEM_COUNTER_MASK                0xffff
#define BRPHY_TOP_1588_MEM_COUNTER_MEM_COUNTER_ALIGN               0
#define BRPHY_TOP_1588_MEM_COUNTER_MEM_COUNTER_BITS                16
#define BRPHY_TOP_1588_MEM_COUNTER_MEM_COUNTER_SHIFT               0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIMESTAMP_DELTA
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIMESTAMP_DELTA :: TIMESTAMP_DELTA1 [15:15] */
#define Wr_BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1(x) WriteRegBits16(BRPHY_TOP_1588_TIMESTAMP_DELTA,0x8000,15,x)
#define Rd_BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1(x) ReadRegBits16(BRPHY_TOP_1588_TIMESTAMP_DELTA,0x8000,15)
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1_MASK       0x8000
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1_ALIGN      0
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1_BITS       1
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1_SHIFT      15

/* BRPHY_TOP_1588 :: TIMESTAMP_DELTA :: TIMESTAMP_DELTA2 [14:14] */
#define Wr_BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2(x) WriteRegBits16(BRPHY_TOP_1588_TIMESTAMP_DELTA,0x4000,14,x)
#define Rd_BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2(x) ReadRegBits16(BRPHY_TOP_1588_TIMESTAMP_DELTA,0x4000,14)
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2_MASK       0x4000
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2_ALIGN      0
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2_BITS       1
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2_SHIFT      14

/* BRPHY_TOP_1588 :: TIMESTAMP_DELTA :: TIMESTAMP_DELTA3 [13:00] */
#define Wr_BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3(x) WriteRegBits16(BRPHY_TOP_1588_TIMESTAMP_DELTA,0x3fff,0,x)
#define Rd_BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3(x) ReadRegBits16(BRPHY_TOP_1588_TIMESTAMP_DELTA,0x3fff,0)
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3_MASK       0x3fff
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3_ALIGN      0
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3_BITS       14
#define BRPHY_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3_SHIFT      0


/****************************************************************************
 * BRPHY_TOP_1588 :: SOP_SEL
 ***************************************************************************/
/* BRPHY_TOP_1588 :: SOP_SEL :: SOP_SEL [15:00] */
#define Wr_BRPHY_TOP_1588_SOP_SEL_SOP_SEL(x) WriteReg16(BRPHY_TOP_1588_SOP_SEL,x)
#define Rd_BRPHY_TOP_1588_SOP_SEL_SOP_SEL(x) ReadReg16(BRPHY_TOP_1588_SOP_SEL)
#define BRPHY_TOP_1588_SOP_SEL_SOP_SEL_MASK                        0xffff
#define BRPHY_TOP_1588_SOP_SEL_SOP_SEL_ALIGN                       0
#define BRPHY_TOP_1588_SOP_SEL_SOP_SEL_BITS                        16
#define BRPHY_TOP_1588_SOP_SEL_SOP_SEL_SHIFT                       0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_INFO_3
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_INFO_3 :: TIME_STAMP_INFO [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_3,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_3)
#define BRPHY_TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO_MASK      0xffff
#define BRPHY_TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO_ALIGN     0
#define BRPHY_TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO_BITS      16
#define BRPHY_TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_INFO_4
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_INFO_4 :: TIME_STAMP_INFO [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_4,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_4)
#define BRPHY_TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO_MASK      0xffff
#define BRPHY_TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO_ALIGN     0
#define BRPHY_TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO_BITS      16
#define BRPHY_TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_INFO_5
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_INFO_5 :: TIME_STAMP_INFO [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_5,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_5)
#define BRPHY_TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO_MASK      0xffff
#define BRPHY_TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO_ALIGN     0
#define BRPHY_TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO_BITS      16
#define BRPHY_TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_INFO_6
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_INFO_6 :: TIME_STAMP_INFO [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_6,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_6)
#define BRPHY_TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO_MASK      0xffff
#define BRPHY_TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO_ALIGN     0
#define BRPHY_TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO_BITS      16
#define BRPHY_TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_INFO_7
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_INFO_7 :: TIME_STAMP_INFO [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_7,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_7)
#define BRPHY_TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO_MASK      0xffff
#define BRPHY_TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO_ALIGN     0
#define BRPHY_TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO_BITS      16
#define BRPHY_TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: TIME_STAMP_INFO_8
 ***************************************************************************/
/* BRPHY_TOP_1588 :: TIME_STAMP_INFO_8 :: TIME_STAMP_INFO [15:00] */
#define Wr_BRPHY_TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO(x) WriteReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_8,x)
#define Rd_BRPHY_TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO(x) ReadReg16(BRPHY_TOP_1588_TIME_STAMP_INFO_8)
#define BRPHY_TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO_MASK      0xffff
#define BRPHY_TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO_ALIGN     0
#define BRPHY_TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO_BITS      16
#define BRPHY_TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO_SHIFT     0


/****************************************************************************
 * BRPHY_TOP_1588 :: INBAND_SPARE1
 ***************************************************************************/
/* BRPHY_TOP_1588 :: INBAND_SPARE1 :: INBAND_SPARE [15:00] */
#define Wr_BRPHY_TOP_1588_INBAND_SPARE1_INBAND_SPARE(x) WriteReg16(BRPHY_TOP_1588_INBAND_SPARE1,x)
#define Rd_BRPHY_TOP_1588_INBAND_SPARE1_INBAND_SPARE(x) ReadReg16(BRPHY_TOP_1588_INBAND_SPARE1)
#define BRPHY_TOP_1588_INBAND_SPARE1_INBAND_SPARE_MASK             0xffff
#define BRPHY_TOP_1588_INBAND_SPARE1_INBAND_SPARE_ALIGN            0
#define BRPHY_TOP_1588_INBAND_SPARE1_INBAND_SPARE_BITS             16
#define BRPHY_TOP_1588_INBAND_SPARE1_INBAND_SPARE_SHIFT            0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys0_BRPHY0_BR_CL22_IEEE
 ***************************************************************************/
/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: MII_CTRL
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: RESET [15:15] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_RESET(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x8000,15,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_RESET(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x8000,15)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESET_MASK                    0x8000
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESET_ALIGN                   0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESET_BITS                    1
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESET_SHIFT                   15

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: LOOPBACK [14:14] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x4000,14,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x4000,14)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_LOOPBACK_MASK                 0x4000
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_LOOPBACK_ALIGN                0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_LOOPBACK_BITS                 1
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_LOOPBACK_SHIFT                14

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: RESTART_LDS [13:13] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x2000,13,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x2000,13)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_MASK              0x2000
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_ALIGN             0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_BITS              1
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_SHIFT             13

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: LDS_ENABLE [12:12] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x1000,12,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x1000,12)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_MASK               0x1000
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_ALIGN              0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_BITS               1
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_SHIFT              12

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: POWER_DOWN [11:11] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x800,11,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x800,11)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_MASK               0x0800
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_ALIGN              0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_BITS               1
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_SHIFT              11

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: ISOLATE [10:10] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x400,10,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x400,10)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_ISOLATE_MASK                  0x0400
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_ISOLATE_ALIGN                 0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_ISOLATE_BITS                  1
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_ISOLATE_SHIFT                 10

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: manual_speed_select_enable [09:09] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x200,9,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x200,9)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_MASK 0x0200
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_BITS 1
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_SHIFT 9

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: Speed_Selection [08:06] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x1c0,6,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x1c0,6)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_MASK          0x01c0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_ALIGN         0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_BITS          3
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_SHIFT         6

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: Pair_Selection [05:04] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x30,4,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x30,4)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_MASK           0x0030
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_ALIGN          0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_BITS           2
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_SHIFT          4

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: Master_mode [03:03] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_Master_mode(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x8,3,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_Master_mode(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x8,3)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_MASK              0x0008
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_ALIGN             0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_BITS              1
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_SHIFT             3

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: Unidirection_Enable [02:02] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x4,2,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_CTRL,0x4,2)
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_MASK      0x0004
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_ALIGN     0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_BITS      1
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_SHIFT     2

/* BRPHY0_BR_CL22_IEEE :: MII_CTRL :: reserved0 [01:00] */
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESERVED0_MASK                0x0003
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESERVED0_ALIGN               0
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESERVED0_BITS                2
#define BRPHY0_BR_CL22_IEEE_MII_CTRL_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: MII_STAT
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: MII_STAT :: reserved0 [15:15] */
#define BRPHY0_BR_CL22_IEEE_MII_STAT_RESERVED0_MASK                0x8000
#define BRPHY0_BR_CL22_IEEE_MII_STAT_RESERVED0_ALIGN               0
#define BRPHY0_BR_CL22_IEEE_MII_STAT_RESERVED0_BITS                1
#define BRPHY0_BR_CL22_IEEE_MII_STAT_RESERVED0_SHIFT               15

/* BRPHY0_BR_CL22_IEEE :: MII_STAT :: Capability [14:09] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_STAT_Capability(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x7e00,9,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_STAT_Capability(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x7e00,9)
#define BRPHY0_BR_CL22_IEEE_MII_STAT_CAPABILITY_MASK               0x7e00
#define BRPHY0_BR_CL22_IEEE_MII_STAT_CAPABILITY_ALIGN              0
#define BRPHY0_BR_CL22_IEEE_MII_STAT_CAPABILITY_BITS               6
#define BRPHY0_BR_CL22_IEEE_MII_STAT_CAPABILITY_SHIFT              9

/* BRPHY0_BR_CL22_IEEE :: MII_STAT :: EXTENDED_STAT [08:06] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x1c0,6,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x1c0,6)
#define BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_MASK            0x01c0
#define BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_ALIGN           0
#define BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_BITS            3
#define BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_SHIFT           6

/* BRPHY0_BR_CL22_IEEE :: MII_STAT :: LDS_complete [05:05] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_STAT_LDS_complete(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x20,5,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_STAT_LDS_complete(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x20,5)
#define BRPHY0_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_MASK             0x0020
#define BRPHY0_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_ALIGN            0
#define BRPHY0_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_BITS             1
#define BRPHY0_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_SHIFT            5

/* BRPHY0_BR_CL22_IEEE :: MII_STAT :: reserved1 [04:03] */
#define BRPHY0_BR_CL22_IEEE_MII_STAT_RESERVED1_MASK                0x0018
#define BRPHY0_BR_CL22_IEEE_MII_STAT_RESERVED1_ALIGN               0
#define BRPHY0_BR_CL22_IEEE_MII_STAT_RESERVED1_BITS                2
#define BRPHY0_BR_CL22_IEEE_MII_STAT_RESERVED1_SHIFT               3

/* BRPHY0_BR_CL22_IEEE :: MII_STAT :: LNK_STAT [02:02] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x4,2,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x4,2)
#define BRPHY0_BR_CL22_IEEE_MII_STAT_LNK_STAT_MASK                 0x0004
#define BRPHY0_BR_CL22_IEEE_MII_STAT_LNK_STAT_ALIGN                0
#define BRPHY0_BR_CL22_IEEE_MII_STAT_LNK_STAT_BITS                 1
#define BRPHY0_BR_CL22_IEEE_MII_STAT_LNK_STAT_SHIFT                2

/* BRPHY0_BR_CL22_IEEE :: MII_STAT :: JABBER_DETECT [01:01] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x2,1,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x2,1)
#define BRPHY0_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_MASK            0x0002
#define BRPHY0_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_ALIGN           0
#define BRPHY0_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_BITS            1
#define BRPHY0_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_SHIFT           1

/* BRPHY0_BR_CL22_IEEE :: MII_STAT :: EXTENDED_CAPABILITY [00:00] */
#define Wr_BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x1,0,x)
#define Rd_BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_MII_STAT,0x1,0)
#define BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_MASK      0x0001
#define BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_ALIGN     0
#define BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_BITS      1
#define BRPHY0_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_SHIFT     0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: PHY_ID_MSB
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: PHY_ID_MSB :: OUI_MSB [15:00] */
#define Wr_BRPHY0_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) WriteReg16(BRPHY0_BR_CL22_IEEE_PHY_ID_MSB,x)
#define Rd_BRPHY0_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) ReadReg16(BRPHY0_BR_CL22_IEEE_PHY_ID_MSB)
#define BRPHY0_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_MASK                0xffff
#define BRPHY0_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_ALIGN               0
#define BRPHY0_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_BITS                16
#define BRPHY0_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_SHIFT               0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: PHY_ID_LSB
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: PHY_ID_LSB :: OUI_LSB [15:10] */
#define Wr_BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10,x)
#define Rd_BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10)
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_MASK                0xfc00
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_ALIGN               0
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_BITS                6
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_SHIFT               10

/* BRPHY0_BR_CL22_IEEE :: PHY_ID_LSB :: MODEL [09:04] */
#define Wr_BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4,x)
#define Rd_BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4)
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_MODEL_MASK                  0x03f0
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_MODEL_ALIGN                 0
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_MODEL_BITS                  6
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_MODEL_SHIFT                 4

/* BRPHY0_BR_CL22_IEEE :: PHY_ID_LSB :: REVISION [03:00] */
#define Wr_BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_PHY_ID_LSB,0xf,0,x)
#define Rd_BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_PHY_ID_LSB,0xf,0)
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_REVISION_MASK               0x000f
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_REVISION_ALIGN              0
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_REVISION_BITS               4
#define BRPHY0_BR_CL22_IEEE_PHY_ID_LSB_REVISION_SHIFT              0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved0 [13:06] */
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_MASK      0x3fc0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_ALIGN     0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_BITS      8
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_SHIFT     6

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_MASK   0x0020
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_ALIGN  0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_BITS   1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_SHIFT  5

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved1 [00:00] */
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_MASK      0x0001
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_ALIGN     0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_BITS      1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_SHIFT     0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: LDS_Adv_Control
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Control :: Test_Mode [15:13] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_MASK         0xe000
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_ALIGN        0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_BITS         3
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_SHIFT        13

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Control :: reserved0 [12:10] */
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_MASK         0x1c00
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_ALIGN        0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_BITS         3
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_SHIFT        10

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Control :: Port_Type [09:09] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_MASK         0x0200
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_ALIGN        0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_BITS         1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_SHIFT        9

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Control :: Abilities_Field_Update [08:08] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_MASK 0x0100
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_SHIFT 8

/* BRPHY0_BR_CL22_IEEE :: LDS_Adv_Control :: Local_Field_Number [07:00] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0)
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_MASK 0x00ff
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_BITS 8
#define BRPHY0_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: LDS_Ability
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: LDS_Ability :: LDS_Ability [15:00] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) WriteReg16(BRPHY0_BR_CL22_IEEE_LDS_ABILITY,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) ReadReg16(BRPHY0_BR_CL22_IEEE_LDS_ABILITY)
#define BRPHY0_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_MASK           0xffff
#define BRPHY0_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_ALIGN          0
#define BRPHY0_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_BITS           16
#define BRPHY0_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_SHIFT          0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved0 [13:06] */
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_MASK       0x3fc0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_ALIGN      0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_BITS       8
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_SHIFT      6

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_MASK    0x0020
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_ALIGN   0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_BITS    1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_SHIFT   5

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved1 [00:00] */
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_MASK       0x0001
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_ALIGN      0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_BITS       1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_SHIFT      0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: LDS_LP_MSG_NxtP
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: LDS_LP_MSG_NxtP :: Link_Partner_Nxt_Pg_Msg [15:00] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) WriteReg16(BRPHY0_BR_CL22_IEEE_LDS_LP_MSG_NXTP,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) ReadReg16(BRPHY0_BR_CL22_IEEE_LDS_LP_MSG_NXTP)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_MASK 0xffff
#define BRPHY0_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_BITS 16
#define BRPHY0_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_SHIFT 0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_NxtP
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: NextPage_Read_Flag [15:15] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_MASK 0x8000
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_BITS 1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_SHIFT 15

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: reserved0 [14:09] */
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_MASK     0x7e00
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_ALIGN    0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_BITS     6
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_SHIFT    9

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_ACQ [08:08] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_MASK    0x0100
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_ALIGN   0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_BITS    1
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_SHIFT   8

/* BRPHY0_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_Field_Number [07:00] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0)
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_MASK 0x00ff
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_BITS 8
#define BRPHY0_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: LDS_LDS_EXP
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: LDS_LDS_EXP :: Downgrade_Ability [15:15] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15)
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_MASK     0x8000
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_ALIGN    0
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_BITS     1
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_SHIFT    15

/* BRPHY0_BR_CL22_IEEE :: LDS_LDS_EXP :: Master_Slave [14:14] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14)
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_MASK          0x4000
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_ALIGN         0
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_BITS          1
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_SHIFT         14

/* BRPHY0_BR_CL22_IEEE :: LDS_LDS_EXP :: Pair_Number [13:12] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12)
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_MASK           0x3000
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_ALIGN          0
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_BITS           2
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_SHIFT          12

/* BRPHY0_BR_CL22_IEEE :: LDS_LDS_EXP :: Estimated_Wire_Length [11:00] */
#define Wr_BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0)
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_MASK 0x0fff
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_BITS 12
#define BRPHY0_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_SHIFT 0


/****************************************************************************
 * BRPHY0_BR_CL22_IEEE :: LRE_EXTENDED_STAT
 ***************************************************************************/
/* BRPHY0_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: reserved0 [15:10] */
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_MASK       0xfc00
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_ALIGN      0
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_BITS       6
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_SHIFT      10

/* BRPHY0_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: LOCAL_RECEIVE_STATUS [09:09] */
#define Wr_BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9)
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_MASK 0x0200
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_SHIFT 9

/* BRPHY0_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: REMOTE_RECEIVE_STATUS [08:08] */
#define Wr_BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8)
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_MASK 0x0100
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_BITS 1
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_SHIFT 8

/* BRPHY0_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: IDLE_ERROR_CNTR [07:00] */
#define Wr_BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) WriteRegBits16(BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0,x)
#define Rd_BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) ReadRegBits16(BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0)
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_MASK 0x00ff
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_ALIGN 0
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_BITS 8
#define BRPHY0_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_CL45DEV1
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x8000,15)
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESET_BITS                   1
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved0 [14:14] */
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_MASK               0x4000
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_SHIFT              14

/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x2000,13)
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved1 [12:12] */
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_MASK               0x1000
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_BITS               1
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_SHIFT              12

/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x800,11)
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved2 [10:07] */
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_MASK               0x0780
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_BITS               4
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_SHIFT              7

/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x40,6)
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x3c,2)
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved3 [01:01] */
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_MASK               0x0002
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_BITS               1
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_SHIFT              1

/* BRPHY1_CL45DEV1 :: PMD_IEEE_CTL1 :: LPBK [00:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x1,0,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_CTL1,0x1,0)
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LPBK_MASK                    0x0001
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LPBK_ALIGN                   0
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LPBK_BITS                    1
#define BRPHY1_CL45DEV1_PMD_IEEE_CTL1_LPBK_SHIFT                   0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_ST1
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY1_CL45DEV1 :: PMD_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_ST1,0x80,7)
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_FAULT_BITS                    1
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY1_CL45DEV1 :: PMD_IEEE_ST1 :: reserved1 [06:03] */
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED1_MASK                0x0078
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED1_BITS                4
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY1_CL45DEV1 :: PMD_IEEE_ST1 :: RCV_LINK_ST [02:02] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_ST1,0x4,2)
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_MASK              0x0004
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_ALIGN             0
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_BITS              1
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_SHIFT             2

/* BRPHY1_CL45DEV1 :: PMD_IEEE_ST1 :: CAP_LOW_PWR [01:01] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_ST1,0x2,1)
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_MASK              0x0002
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_ALIGN             0
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_BITS              1
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_SHIFT             1

/* BRPHY1_CL45DEV1 :: PMD_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY1_CL45DEV1_PMD_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID0,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID0)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x80,7)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x40,6)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x20,5)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x10,4)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x8,3)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x4,2)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x2,1)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV0,0x1,0)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_DEV1
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV1,0x8000,15)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV1,0x4000,14)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_DEV1,0x2000,13)
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY1_CL45DEV1 :: PMD_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY1_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID0,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID0)
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID1,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID1)
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY1_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY1_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: TX_PMD_TSYNC_EN [01:01] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_MASK    0x0002
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_BITS    1
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_SHIFT   1

/* BRPHY1_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: RX_PMD_TSYNC_EN [00:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_MASK    0x0001
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_BITS    1
#define BRPHY1_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY1_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY1_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY1_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_CL45DEV3
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x8000,15)
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESET_BITS                   1
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1 :: PCS_LPBK [14:14] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x4000,14,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x4000,14)
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_MASK                0x4000
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_ALIGN               0
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_BITS                1
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_SHIFT               14

/* BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x2000,13)
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved0 [12:12] */
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_MASK               0x1000
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_SHIFT              12

/* BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x800,11)
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved1 [10:07] */
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_MASK               0x0780
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_BITS               4
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_SHIFT              7

/* BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x40,6)
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_CTL1,0x3c,2)
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY1_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved2 [01:00] */
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_MASK               0x0003
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_BITS               2
#define BRPHY1_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_SHIFT              0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_ST1
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY1_CL45DEV3 :: PCS_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_ST1,0x80,7)
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_FAULT_BITS                    1
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY1_CL45DEV3 :: PCS_IEEE_ST1 :: CLOCK_STOP_CAPABLE [06:06] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_ST1,0x40,6,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_ST1,0x40,6)
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_MASK       0x0040
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_ALIGN      0
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_BITS       1
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_SHIFT      6

/* BRPHY1_CL45DEV3 :: PCS_IEEE_ST1 :: reserved1 [05:03] */
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED1_MASK                0x0038
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED1_BITS                3
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY1_CL45DEV3 :: PCS_IEEE_ST1 :: PCS_RCV_LINK_ST [02:02] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_ST1,0x4,2)
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_MASK          0x0004
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_ALIGN         0
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_BITS          1
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_SHIFT         2

/* BRPHY1_CL45DEV3 :: PCS_IEEE_ST1 :: LOW_PWR_AB [01:01] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_ST1,0x2,1)
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_MASK               0x0002
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_BITS               1
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_SHIFT              1

/* BRPHY1_CL45DEV3 :: PCS_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY1_CL45DEV3_PCS_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID0,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID0)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x80,7)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x40,6)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x20,5)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x10,4)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x8,3)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x4,2)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x2,1)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV0,0x1,0)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_DEV1
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV1,0x8000,15)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV1,0x4000,14)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_DEV1,0x2000,13)
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY1_CL45DEV3 :: PCS_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY1_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID0,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID0)
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID1,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID1)
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY1_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_EEE_CAP
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_EEE_CAP :: reserved0 [15:07] */
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_RESERVED0_MASK                 0xff80
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_RESERVED0_ALIGN                0
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_RESERVED0_BITS                 9
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_RESERVED0_SHIFT                7

/* BRPHY1_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKR_EEE [06:06] */
#define Wr_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x40,6,x)
#define Rd_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x40,6)
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_MASK         0x0040
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_ALIGN        0
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_BITS         1
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_SHIFT        6

/* BRPHY1_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKX4_EEE [05:05] */
#define Wr_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x20,5,x)
#define Rd_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x20,5)
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_MASK        0x0020
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_ALIGN       0
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_BITS        1
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_SHIFT       5

/* BRPHY1_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASEKX_EEE [04:04] */
#define Wr_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x10,4,x)
#define Rd_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x10,4)
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_MASK        0x0010
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_ALIGN       0
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_BITS        1
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_SHIFT       4

/* BRPHY1_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASET_EEE [03:03] */
#define Wr_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x8,3,x)
#define Rd_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x8,3)
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_MASK          0x0008
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_ALIGN         0
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_BITS          1
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_SHIFT         3

/* BRPHY1_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASET_EEE [02:02] */
#define Wr_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x4,2,x)
#define Rd_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x4,2)
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_MASK         0x0004
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_ALIGN        0
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_BITS         1
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_SHIFT        2

/* BRPHY1_CL45DEV3 :: PCS_EEE_CAP :: PHY_100BASETX_EEE [01:01] */
#define Wr_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x2,1,x)
#define Rd_BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_EEE_CAP,0x2,1)
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_MASK         0x0002
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_ALIGN        0
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_BITS         1
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_SHIFT        1

/* BRPHY1_CL45DEV3 :: PCS_EEE_CAP :: reserved1 [00:00] */
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_RESERVED1_MASK                 0x0001
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_RESERVED1_ALIGN                0
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_RESERVED1_BITS                 1
#define BRPHY1_CL45DEV3_PCS_EEE_CAP_RESERVED1_SHIFT                0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt :: cnt [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) WriteReg16(BRPHY1_CL45DEV3_PCS_EEE_WAKE_ERR_CNT,x)
#define Rd_BRPHY1_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) ReadReg16(BRPHY1_CL45DEV3_PCS_EEE_WAKE_ERR_CNT)
#define BRPHY1_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_MASK              0xffff
#define BRPHY1_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_ALIGN             0
#define BRPHY1_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_BITS              16
#define BRPHY1_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_SHIFT             0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY1_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: TX_PCS_TSYNC_EN [01:01] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_MASK    0x0002
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_BITS    1
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_SHIFT   1

/* BRPHY1_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: RX_PCS_TSYNC_EN [00:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_MASK    0x0001
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_BITS    1
#define BRPHY1_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY1_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY1_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY1_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_CL45DEV7
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_CTRL
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_CTRL :: AN_reset [15:15] */
#define Wr_BRPHY1_CL45DEV7_AN_CTRL_AN_reset(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV7_AN_CTRL_AN_reset(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_CTRL,0x8000,15)
#define BRPHY1_CL45DEV7_AN_CTRL_AN_RESET_MASK                      0x8000
#define BRPHY1_CL45DEV7_AN_CTRL_AN_RESET_ALIGN                     0
#define BRPHY1_CL45DEV7_AN_CTRL_AN_RESET_BITS                      1
#define BRPHY1_CL45DEV7_AN_CTRL_AN_RESET_SHIFT                     15

/* BRPHY1_CL45DEV7 :: AN_CTRL :: reserved0 [14:14] */
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED0_MASK                     0x4000
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED0_ALIGN                    0
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED0_BITS                     1
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED0_SHIFT                    14

/* BRPHY1_CL45DEV7 :: AN_CTRL :: Extended_next_page_control [13:13] */
#define Wr_BRPHY1_CL45DEV7_AN_CTRL_Extended_next_page_control(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV7_AN_CTRL_Extended_next_page_control(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_CTRL,0x2000,13)
#define BRPHY1_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_MASK    0x2000
#define BRPHY1_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_ALIGN   0
#define BRPHY1_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_BITS    1
#define BRPHY1_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_SHIFT   13

/* BRPHY1_CL45DEV7 :: AN_CTRL :: Auto_Negotiation_enable [12:12] */
#define Wr_BRPHY1_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY1_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_CTRL,0x1000,12)
#define BRPHY1_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_MASK       0x1000
#define BRPHY1_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_ALIGN      0
#define BRPHY1_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_BITS       1
#define BRPHY1_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_SHIFT      12

/* BRPHY1_CL45DEV7 :: AN_CTRL :: reserved1 [11:10] */
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED1_MASK                     0x0c00
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED1_ALIGN                    0
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED1_BITS                     2
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED1_SHIFT                    10

/* BRPHY1_CL45DEV7 :: AN_CTRL :: Restart_Auto_Negotiation [09:09] */
#define Wr_BRPHY1_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_CTRL,0x200,9,x)
#define Rd_BRPHY1_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_CTRL,0x200,9)
#define BRPHY1_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_MASK      0x0200
#define BRPHY1_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_ALIGN     0
#define BRPHY1_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_BITS      1
#define BRPHY1_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_SHIFT     9

/* BRPHY1_CL45DEV7 :: AN_CTRL :: reserved2 [08:00] */
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED2_MASK                     0x01ff
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED2_ALIGN                    0
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED2_BITS                     9
#define BRPHY1_CL45DEV7_AN_CTRL_RESERVED2_SHIFT                    0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_STAT
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_STAT :: reserved0 [15:08] */
#define BRPHY1_CL45DEV7_AN_STAT_RESERVED0_MASK                     0xff00
#define BRPHY1_CL45DEV7_AN_STAT_RESERVED0_ALIGN                    0
#define BRPHY1_CL45DEV7_AN_STAT_RESERVED0_BITS                     8
#define BRPHY1_CL45DEV7_AN_STAT_RESERVED0_SHIFT                    8

/* BRPHY1_CL45DEV7 :: AN_STAT :: Extended_next_page_status [07:07] */
#define Wr_BRPHY1_CL45DEV7_AN_STAT_Extended_next_page_status(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x80,7,x)
#define Rd_BRPHY1_CL45DEV7_AN_STAT_Extended_next_page_status(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x80,7)
#define BRPHY1_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_MASK     0x0080
#define BRPHY1_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_ALIGN    0
#define BRPHY1_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_BITS     1
#define BRPHY1_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_SHIFT    7

/* BRPHY1_CL45DEV7 :: AN_STAT :: Page_received [06:06] */
#define Wr_BRPHY1_CL45DEV7_AN_STAT_Page_received(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x40,6,x)
#define Rd_BRPHY1_CL45DEV7_AN_STAT_Page_received(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x40,6)
#define BRPHY1_CL45DEV7_AN_STAT_PAGE_RECEIVED_MASK                 0x0040
#define BRPHY1_CL45DEV7_AN_STAT_PAGE_RECEIVED_ALIGN                0
#define BRPHY1_CL45DEV7_AN_STAT_PAGE_RECEIVED_BITS                 1
#define BRPHY1_CL45DEV7_AN_STAT_PAGE_RECEIVED_SHIFT                6

/* BRPHY1_CL45DEV7 :: AN_STAT :: AN_complete [05:05] */
#define Wr_BRPHY1_CL45DEV7_AN_STAT_AN_complete(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x20,5,x)
#define Rd_BRPHY1_CL45DEV7_AN_STAT_AN_complete(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x20,5)
#define BRPHY1_CL45DEV7_AN_STAT_AN_COMPLETE_MASK                   0x0020
#define BRPHY1_CL45DEV7_AN_STAT_AN_COMPLETE_ALIGN                  0
#define BRPHY1_CL45DEV7_AN_STAT_AN_COMPLETE_BITS                   1
#define BRPHY1_CL45DEV7_AN_STAT_AN_COMPLETE_SHIFT                  5

/* BRPHY1_CL45DEV7 :: AN_STAT :: Remodt_Fault [04:04] */
#define Wr_BRPHY1_CL45DEV7_AN_STAT_Remodt_Fault(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x10,4,x)
#define Rd_BRPHY1_CL45DEV7_AN_STAT_Remodt_Fault(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x10,4)
#define BRPHY1_CL45DEV7_AN_STAT_REMODT_FAULT_MASK                  0x0010
#define BRPHY1_CL45DEV7_AN_STAT_REMODT_FAULT_ALIGN                 0
#define BRPHY1_CL45DEV7_AN_STAT_REMODT_FAULT_BITS                  1
#define BRPHY1_CL45DEV7_AN_STAT_REMODT_FAULT_SHIFT                 4

/* BRPHY1_CL45DEV7 :: AN_STAT :: AN_ability [03:03] */
#define Wr_BRPHY1_CL45DEV7_AN_STAT_AN_ability(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x8,3,x)
#define Rd_BRPHY1_CL45DEV7_AN_STAT_AN_ability(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x8,3)
#define BRPHY1_CL45DEV7_AN_STAT_AN_ABILITY_MASK                    0x0008
#define BRPHY1_CL45DEV7_AN_STAT_AN_ABILITY_ALIGN                   0
#define BRPHY1_CL45DEV7_AN_STAT_AN_ABILITY_BITS                    1
#define BRPHY1_CL45DEV7_AN_STAT_AN_ABILITY_SHIFT                   3

/* BRPHY1_CL45DEV7 :: AN_STAT :: Link_status [02:02] */
#define Wr_BRPHY1_CL45DEV7_AN_STAT_Link_status(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x4,2,x)
#define Rd_BRPHY1_CL45DEV7_AN_STAT_Link_status(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x4,2)
#define BRPHY1_CL45DEV7_AN_STAT_LINK_STATUS_MASK                   0x0004
#define BRPHY1_CL45DEV7_AN_STAT_LINK_STATUS_ALIGN                  0
#define BRPHY1_CL45DEV7_AN_STAT_LINK_STATUS_BITS                   1
#define BRPHY1_CL45DEV7_AN_STAT_LINK_STATUS_SHIFT                  2

/* BRPHY1_CL45DEV7 :: AN_STAT :: reserved1 [01:01] */
#define BRPHY1_CL45DEV7_AN_STAT_RESERVED1_MASK                     0x0002
#define BRPHY1_CL45DEV7_AN_STAT_RESERVED1_ALIGN                    0
#define BRPHY1_CL45DEV7_AN_STAT_RESERVED1_BITS                     1
#define BRPHY1_CL45DEV7_AN_STAT_RESERVED1_SHIFT                    1

/* BRPHY1_CL45DEV7 :: AN_STAT :: Link_partner_AN_ability [00:00] */
#define Wr_BRPHY1_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x1,0,x)
#define Rd_BRPHY1_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_STAT,0x1,0)
#define BRPHY1_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_MASK       0x0001
#define BRPHY1_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY1_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY1_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_SHIFT      0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_DEV_ID_LSB
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_DEV_ID_LSB :: cu_an_device_identifier [15:00] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) WriteReg16(BRPHY1_CL45DEV7_AN_DEV_ID_LSB,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) ReadReg16(BRPHY1_CL45DEV7_AN_DEV_ID_LSB)
#define BRPHY1_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xffff
#define BRPHY1_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY1_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_BITS 16
#define BRPHY1_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_DEV_ID_MSB
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_DEV_ID_MSB :: cu_an_device_identifier [15:10] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10)
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xfc00
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_BITS 6
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 10

/* BRPHY1_CL45DEV7 :: AN_DEV_ID_MSB :: MODEL_NU [09:04] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4)
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_MASK                0x03f0
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_ALIGN               0
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_BITS                6
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_SHIFT               4

/* BRPHY1_CL45DEV7 :: AN_DEV_ID_MSB :: REV_NU [03:00] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_ID_MSB,0xf,0,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_ID_MSB,0xf,0)
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_REV_NU_MASK                  0x000f
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_REV_NU_ALIGN                 0
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_REV_NU_BITS                  4
#define BRPHY1_CL45DEV7_AN_DEV_ID_MSB_REV_NU_SHIFT                 0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: reserved0 [15:08] */
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_MASK           0xff00
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_ALIGN          0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_BITS           8
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_SHIFT          8

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_MASK         0x0080
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_ALIGN        0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_BITS         1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_SHIFT        7

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: TC_PRE [06:06] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_MASK              0x0040
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_ALIGN             0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_BITS              1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_SHIFT             6

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: DTEXS_PRE [05:05] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_MASK           0x0020
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_ALIGN          0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_BITS           1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_SHIFT          5

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PHYXS_PRE [04:04] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_MASK           0x0010
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_ALIGN          0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_BITS           1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_SHIFT          4

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PCS_PRE [03:03] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_MASK             0x0008
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_ALIGN            0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_BITS             1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_SHIFT            3

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: WIS_PRE [02:02] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_MASK             0x0004
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_ALIGN            0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_BITS             1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_SHIFT            2

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PMD_PRE [01:01] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_MASK             0x0002
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_ALIGN            0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_BITS             1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_SHIFT            1

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: CLA22_PRE [00:00] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_MASK           0x0001
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_ALIGN          0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_BITS           1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_SHIFT          0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_MSB
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_MASK      0x8000
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_ALIGN     0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_BITS      1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_SHIFT     15

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_MASK      0x4000
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_ALIGN     0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_BITS      1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_SHIFT     14

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13)
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_MASK       0x2000
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_ALIGN      0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_BITS       1
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_SHIFT      13

/* BRPHY1_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: reserved0 [12:00] */
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_MASK           0x1fff
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_ALIGN          0
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_BITS           13
#define BRPHY1_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_SHIFT          0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_DEV_PKG_ID_LSB
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_DEV_PKG_ID_LSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) WriteReg16(BRPHY1_CL45DEV7_AN_DEV_PKG_ID_LSB,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) ReadReg16(BRPHY1_CL45DEV7_AN_DEV_PKG_ID_LSB)
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_DEV_PKG_ID_MSB
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_DEV_PKG_ID_MSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY1_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) WriteReg16(BRPHY1_CL45DEV7_AN_DEV_PKG_ID_MSB,x)
#define Rd_BRPHY1_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) ReadReg16(BRPHY1_CL45DEV7_AN_DEV_PKG_ID_MSB)
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY1_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_AD
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_AD :: Next_page [15:15] */
#define Wr_BRPHY1_CL45DEV7_AN_AD_Next_page(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_AD,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV7_AN_AD_Next_page(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_AD,0x8000,15)
#define BRPHY1_CL45DEV7_AN_AD_NEXT_PAGE_MASK                       0x8000
#define BRPHY1_CL45DEV7_AN_AD_NEXT_PAGE_ALIGN                      0
#define BRPHY1_CL45DEV7_AN_AD_NEXT_PAGE_BITS                       1
#define BRPHY1_CL45DEV7_AN_AD_NEXT_PAGE_SHIFT                      15

/* BRPHY1_CL45DEV7 :: AN_AD :: Acknowledge [14:14] */
#define Wr_BRPHY1_CL45DEV7_AN_AD_Acknowledge(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_AD,0x4000,14,x)
#define Rd_BRPHY1_CL45DEV7_AN_AD_Acknowledge(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_AD,0x4000,14)
#define BRPHY1_CL45DEV7_AN_AD_ACKNOWLEDGE_MASK                     0x4000
#define BRPHY1_CL45DEV7_AN_AD_ACKNOWLEDGE_ALIGN                    0
#define BRPHY1_CL45DEV7_AN_AD_ACKNOWLEDGE_BITS                     1
#define BRPHY1_CL45DEV7_AN_AD_ACKNOWLEDGE_SHIFT                    14

/* BRPHY1_CL45DEV7 :: AN_AD :: Remote_fault [13:13] */
#define Wr_BRPHY1_CL45DEV7_AN_AD_Remote_fault(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_AD,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV7_AN_AD_Remote_fault(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_AD,0x2000,13)
#define BRPHY1_CL45DEV7_AN_AD_REMOTE_FAULT_MASK                    0x2000
#define BRPHY1_CL45DEV7_AN_AD_REMOTE_FAULT_ALIGN                   0
#define BRPHY1_CL45DEV7_AN_AD_REMOTE_FAULT_BITS                    1
#define BRPHY1_CL45DEV7_AN_AD_REMOTE_FAULT_SHIFT                   13

/* BRPHY1_CL45DEV7 :: AN_AD :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY1_CL45DEV7_AN_AD_Extended_next_page_ability(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_AD,0x1000,12,x)
#define Rd_BRPHY1_CL45DEV7_AN_AD_Extended_next_page_ability(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_AD,0x1000,12)
#define BRPHY1_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_MASK      0x1000
#define BRPHY1_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_ALIGN     0
#define BRPHY1_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_BITS      1
#define BRPHY1_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_SHIFT     12

/* BRPHY1_CL45DEV7 :: AN_AD :: Tech_Field [11:05] */
#define Wr_BRPHY1_CL45DEV7_AN_AD_Tech_Field(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_AD,0xfe0,5,x)
#define Rd_BRPHY1_CL45DEV7_AN_AD_Tech_Field(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_AD,0xfe0,5)
#define BRPHY1_CL45DEV7_AN_AD_TECH_FIELD_MASK                      0x0fe0
#define BRPHY1_CL45DEV7_AN_AD_TECH_FIELD_ALIGN                     0
#define BRPHY1_CL45DEV7_AN_AD_TECH_FIELD_BITS                      7
#define BRPHY1_CL45DEV7_AN_AD_TECH_FIELD_SHIFT                     5

/* BRPHY1_CL45DEV7 :: AN_AD :: Selector_Field [04:00] */
#define Wr_BRPHY1_CL45DEV7_AN_AD_Selector_Field(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_AD,0x1f,0,x)
#define Rd_BRPHY1_CL45DEV7_AN_AD_Selector_Field(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_AD,0x1f,0)
#define BRPHY1_CL45DEV7_AN_AD_SELECTOR_FIELD_MASK                  0x001f
#define BRPHY1_CL45DEV7_AN_AD_SELECTOR_FIELD_ALIGN                 0
#define BRPHY1_CL45DEV7_AN_AD_SELECTOR_FIELD_BITS                  5
#define BRPHY1_CL45DEV7_AN_AD_SELECTOR_FIELD_SHIFT                 0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_LPA
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_LPA :: Next_page [15:15] */
#define Wr_BRPHY1_CL45DEV7_AN_LPA_Next_page(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV7_AN_LPA_Next_page(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x8000,15)
#define BRPHY1_CL45DEV7_AN_LPA_NEXT_PAGE_MASK                      0x8000
#define BRPHY1_CL45DEV7_AN_LPA_NEXT_PAGE_ALIGN                     0
#define BRPHY1_CL45DEV7_AN_LPA_NEXT_PAGE_BITS                      1
#define BRPHY1_CL45DEV7_AN_LPA_NEXT_PAGE_SHIFT                     15

/* BRPHY1_CL45DEV7 :: AN_LPA :: Acknowledge [14:14] */
#define Wr_BRPHY1_CL45DEV7_AN_LPA_Acknowledge(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x4000,14,x)
#define Rd_BRPHY1_CL45DEV7_AN_LPA_Acknowledge(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x4000,14)
#define BRPHY1_CL45DEV7_AN_LPA_ACKNOWLEDGE_MASK                    0x4000
#define BRPHY1_CL45DEV7_AN_LPA_ACKNOWLEDGE_ALIGN                   0
#define BRPHY1_CL45DEV7_AN_LPA_ACKNOWLEDGE_BITS                    1
#define BRPHY1_CL45DEV7_AN_LPA_ACKNOWLEDGE_SHIFT                   14

/* BRPHY1_CL45DEV7 :: AN_LPA :: Remote_fault [13:13] */
#define Wr_BRPHY1_CL45DEV7_AN_LPA_Remote_fault(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV7_AN_LPA_Remote_fault(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x2000,13)
#define BRPHY1_CL45DEV7_AN_LPA_REMOTE_FAULT_MASK                   0x2000
#define BRPHY1_CL45DEV7_AN_LPA_REMOTE_FAULT_ALIGN                  0
#define BRPHY1_CL45DEV7_AN_LPA_REMOTE_FAULT_BITS                   1
#define BRPHY1_CL45DEV7_AN_LPA_REMOTE_FAULT_SHIFT                  13

/* BRPHY1_CL45DEV7 :: AN_LPA :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY1_CL45DEV7_AN_LPA_Extended_next_page_ability(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x1000,12,x)
#define Rd_BRPHY1_CL45DEV7_AN_LPA_Extended_next_page_ability(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x1000,12)
#define BRPHY1_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_MASK     0x1000
#define BRPHY1_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_ALIGN    0
#define BRPHY1_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_BITS     1
#define BRPHY1_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_SHIFT    12

/* BRPHY1_CL45DEV7 :: AN_LPA :: Tech_Field [11:05] */
#define Wr_BRPHY1_CL45DEV7_AN_LPA_Tech_Field(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_LPA,0xfe0,5,x)
#define Rd_BRPHY1_CL45DEV7_AN_LPA_Tech_Field(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_LPA,0xfe0,5)
#define BRPHY1_CL45DEV7_AN_LPA_TECH_FIELD_MASK                     0x0fe0
#define BRPHY1_CL45DEV7_AN_LPA_TECH_FIELD_ALIGN                    0
#define BRPHY1_CL45DEV7_AN_LPA_TECH_FIELD_BITS                     7
#define BRPHY1_CL45DEV7_AN_LPA_TECH_FIELD_SHIFT                    5

/* BRPHY1_CL45DEV7 :: AN_LPA :: Selector_Field [04:00] */
#define Wr_BRPHY1_CL45DEV7_AN_LPA_Selector_Field(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x1f,0,x)
#define Rd_BRPHY1_CL45DEV7_AN_LPA_Selector_Field(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_LPA,0x1f,0)
#define BRPHY1_CL45DEV7_AN_LPA_SELECTOR_FIELD_MASK                 0x001f
#define BRPHY1_CL45DEV7_AN_LPA_SELECTOR_FIELD_ALIGN                0
#define BRPHY1_CL45DEV7_AN_LPA_SELECTOR_FIELD_BITS                 5
#define BRPHY1_CL45DEV7_AN_LPA_SELECTOR_FIELD_SHIFT                0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_XNPA
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_XNPA :: Next_page [15:15] */
#define Wr_BRPHY1_CL45DEV7_AN_XNPA_Next_page(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV7_AN_XNPA_Next_page(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x8000,15)
#define BRPHY1_CL45DEV7_AN_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY1_CL45DEV7_AN_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY1_CL45DEV7_AN_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY1_CL45DEV7_AN_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY1_CL45DEV7 :: AN_XNPA :: reserved0 [14:14] */
#define BRPHY1_CL45DEV7_AN_XNPA_RESERVED0_MASK                     0x4000
#define BRPHY1_CL45DEV7_AN_XNPA_RESERVED0_ALIGN                    0
#define BRPHY1_CL45DEV7_AN_XNPA_RESERVED0_BITS                     1
#define BRPHY1_CL45DEV7_AN_XNPA_RESERVED0_SHIFT                    14

/* BRPHY1_CL45DEV7 :: AN_XNPA :: Message_page [13:13] */
#define Wr_BRPHY1_CL45DEV7_AN_XNPA_Message_page(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV7_AN_XNPA_Message_page(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x2000,13)
#define BRPHY1_CL45DEV7_AN_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY1_CL45DEV7_AN_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY1_CL45DEV7_AN_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY1_CL45DEV7_AN_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY1_CL45DEV7 :: AN_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY1_CL45DEV7_AN_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x1000,12,x)
#define Rd_BRPHY1_CL45DEV7_AN_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x1000,12)
#define BRPHY1_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY1_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY1_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY1_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY1_CL45DEV7 :: AN_XNPA :: Toggle [11:11] */
#define Wr_BRPHY1_CL45DEV7_AN_XNPA_Toggle(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x800,11,x)
#define Rd_BRPHY1_CL45DEV7_AN_XNPA_Toggle(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x800,11)
#define BRPHY1_CL45DEV7_AN_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY1_CL45DEV7_AN_XNPA_TOGGLE_ALIGN                       0
#define BRPHY1_CL45DEV7_AN_XNPA_TOGGLE_BITS                        1
#define BRPHY1_CL45DEV7_AN_XNPA_TOGGLE_SHIFT                       11

/* BRPHY1_CL45DEV7 :: AN_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY1_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x7ff,0,x)
#define Rd_BRPHY1_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY1_CL45DEV7_AN_XNPA,0x7ff,0)
#define BRPHY1_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY1_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY1_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY1_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_XNPB
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY1_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY1_CL45DEV7_AN_XNPB,x)
#define Rd_BRPHY1_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY1_CL45DEV7_AN_XNPB)
#define BRPHY1_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY1_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY1_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY1_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: AN_XNPC
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: AN_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY1_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY1_CL45DEV7_AN_XNPC,x)
#define Rd_BRPHY1_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY1_CL45DEV7_AN_XNPC)
#define BRPHY1_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY1_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY1_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY1_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: LP_XNPA
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: LP_XNPA :: Next_page [15:15] */
#define Wr_BRPHY1_CL45DEV7_LP_XNPA_Next_page(x) WriteRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV7_LP_XNPA_Next_page(x) ReadRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x8000,15)
#define BRPHY1_CL45DEV7_LP_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY1_CL45DEV7_LP_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY1_CL45DEV7_LP_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY1_CL45DEV7_LP_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY1_CL45DEV7 :: LP_XNPA :: Acknowledge [14:14] */
#define Wr_BRPHY1_CL45DEV7_LP_XNPA_Acknowledge(x) WriteRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x4000,14,x)
#define Rd_BRPHY1_CL45DEV7_LP_XNPA_Acknowledge(x) ReadRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x4000,14)
#define BRPHY1_CL45DEV7_LP_XNPA_ACKNOWLEDGE_MASK                   0x4000
#define BRPHY1_CL45DEV7_LP_XNPA_ACKNOWLEDGE_ALIGN                  0
#define BRPHY1_CL45DEV7_LP_XNPA_ACKNOWLEDGE_BITS                   1
#define BRPHY1_CL45DEV7_LP_XNPA_ACKNOWLEDGE_SHIFT                  14

/* BRPHY1_CL45DEV7 :: LP_XNPA :: Message_page [13:13] */
#define Wr_BRPHY1_CL45DEV7_LP_XNPA_Message_page(x) WriteRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV7_LP_XNPA_Message_page(x) ReadRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x2000,13)
#define BRPHY1_CL45DEV7_LP_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY1_CL45DEV7_LP_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY1_CL45DEV7_LP_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY1_CL45DEV7_LP_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY1_CL45DEV7 :: LP_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY1_CL45DEV7_LP_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x1000,12,x)
#define Rd_BRPHY1_CL45DEV7_LP_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x1000,12)
#define BRPHY1_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY1_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY1_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY1_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY1_CL45DEV7 :: LP_XNPA :: Toggle [11:11] */
#define Wr_BRPHY1_CL45DEV7_LP_XNPA_Toggle(x) WriteRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x800,11,x)
#define Rd_BRPHY1_CL45DEV7_LP_XNPA_Toggle(x) ReadRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x800,11)
#define BRPHY1_CL45DEV7_LP_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY1_CL45DEV7_LP_XNPA_TOGGLE_ALIGN                       0
#define BRPHY1_CL45DEV7_LP_XNPA_TOGGLE_BITS                        1
#define BRPHY1_CL45DEV7_LP_XNPA_TOGGLE_SHIFT                       11

/* BRPHY1_CL45DEV7 :: LP_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY1_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x7ff,0,x)
#define Rd_BRPHY1_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY1_CL45DEV7_LP_XNPA,0x7ff,0)
#define BRPHY1_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY1_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY1_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY1_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: LP_XNPB
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: LP_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY1_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY1_CL45DEV7_LP_XNPB,x)
#define Rd_BRPHY1_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY1_CL45DEV7_LP_XNPB)
#define BRPHY1_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY1_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY1_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY1_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: LP_XNPC
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: LP_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY1_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY1_CL45DEV7_LP_XNPC,x)
#define Rd_BRPHY1_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY1_CL45DEV7_LP_XNPC)
#define BRPHY1_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY1_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY1_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY1_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: TENG_AN_CTRL
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_MAN_CONFIG_EN [15:15] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x8000,15)
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_MASK   0x8000
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_ALIGN  0
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_BITS   1
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_SHIFT  15

/* BRPHY1_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_CONFIG_VAL [14:14] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x4000,14,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x4000,14)
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_MASK      0x4000
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_ALIGN     0
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_BITS      1
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_SHIFT     14

/* BRPHY1_CL45DEV7 :: TENG_AN_CTRL :: PORT_TYPE [13:13] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x2000,13)
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_MASK                0x2000
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_ALIGN               0
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_BITS                1
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_SHIFT               13

/* BRPHY1_CL45DEV7 :: TENG_AN_CTRL :: PHY10GBASET_ABLE [12:12] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x1000,12)
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_MASK         0x1000
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_ALIGN        0
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_BITS         1
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_SHIFT        12

/* BRPHY1_CL45DEV7 :: TENG_AN_CTRL :: reserved0 [11:03] */
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_RESERVED0_MASK                0x0ff8
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_RESERVED0_ALIGN               0
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_RESERVED0_BITS                9
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_RESERVED0_SHIFT               3

/* BRPHY1_CL45DEV7 :: TENG_AN_CTRL :: LD_PMA_TRAIN_RST_SEQ [02:02] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x4,2,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x4,2)
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_MASK     0x0004
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_ALIGN    0
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_BITS     1
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_SHIFT    2

/* BRPHY1_CL45DEV7 :: TENG_AN_CTRL :: reserved1 [01:01] */
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_RESERVED1_MASK                0x0002
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_RESERVED1_ALIGN               0
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_RESERVED1_BITS                1
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_RESERVED1_SHIFT               1

/* BRPHY1_CL45DEV7 :: TENG_AN_CTRL :: LD_LOOP_TIMING_ABLE [00:00] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x1,0,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_CTRL,0x1,0)
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_MASK      0x0001
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_BITS      1
#define BRPHY1_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_SHIFT     0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: TENG_AN_STAT
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_FAULT [15:15] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x8000,15,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x8000,15)
#define BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_MASK    0x8000
#define BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_ALIGN   0
#define BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_BITS    1
#define BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_SHIFT   15

/* BRPHY1_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_RES [14:14] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x4000,14,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x4000,14)
#define BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_MASK      0x4000
#define BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_ALIGN     0
#define BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_BITS      1
#define BRPHY1_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_SHIFT     14

/* BRPHY1_CL45DEV7 :: TENG_AN_STAT :: LOCAL_RCVR_STAT [13:13] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x2000,13,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x2000,13)
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_MASK          0x2000
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_ALIGN         0
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_BITS          1
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_SHIFT         13

/* BRPHY1_CL45DEV7 :: TENG_AN_STAT :: REMOTE_RCVR_STAT [12:12] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x1000,12,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x1000,12)
#define BRPHY1_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_MASK         0x1000
#define BRPHY1_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_ALIGN        0
#define BRPHY1_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_BITS         1
#define BRPHY1_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_SHIFT        12

/* BRPHY1_CL45DEV7 :: TENG_AN_STAT :: LNK_PRTNR_10GBASET_CAP [11:11] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x800,11,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x800,11)
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_MASK   0x0800
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_ALIGN  0
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_BITS   1
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_SHIFT  11

/* BRPHY1_CL45DEV7 :: TENG_AN_STAT :: LP_LOOP_TIMING_ABLE [10:10] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x400,10,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x400,10)
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_MASK      0x0400
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_BITS      1
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_SHIFT     10

/* BRPHY1_CL45DEV7 :: TENG_AN_STAT :: LP_PMA_TRAIN_RST_REQ [09:09] */
#define Wr_BRPHY1_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) WriteRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x200,9,x)
#define Rd_BRPHY1_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) ReadRegBits16(BRPHY1_CL45DEV7_TENG_AN_STAT,0x200,9)
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_MASK     0x0200
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_ALIGN    0
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_BITS     1
#define BRPHY1_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_SHIFT    9

/* BRPHY1_CL45DEV7 :: TENG_AN_STAT :: reserved0 [08:00] */
#define BRPHY1_CL45DEV7_TENG_AN_STAT_RESERVED0_MASK                0x01ff
#define BRPHY1_CL45DEV7_TENG_AN_STAT_RESERVED0_ALIGN               0
#define BRPHY1_CL45DEV7_TENG_AN_STAT_RESERVED0_BITS                9
#define BRPHY1_CL45DEV7_TENG_AN_STAT_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: EEE_ADV
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: EEE_ADV :: reserved0 [15:11] */
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED0_MASK                     0xf800
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED0_ALIGN                    0
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED0_BITS                     5
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED0_SHIFT                    11

/* BRPHY1_CL45DEV7 :: EEE_ADV :: Next_page [10:10] */
#define Wr_BRPHY1_CL45DEV7_EEE_ADV_Next_page(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x400,10,x)
#define Rd_BRPHY1_CL45DEV7_EEE_ADV_Next_page(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x400,10)
#define BRPHY1_CL45DEV7_EEE_ADV_NEXT_PAGE_MASK                     0x0400
#define BRPHY1_CL45DEV7_EEE_ADV_NEXT_PAGE_ALIGN                    0
#define BRPHY1_CL45DEV7_EEE_ADV_NEXT_PAGE_BITS                     1
#define BRPHY1_CL45DEV7_EEE_ADV_NEXT_PAGE_SHIFT                    10

/* BRPHY1_CL45DEV7 :: EEE_ADV :: reserved1 [09:07] */
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED1_MASK                     0x0380
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED1_ALIGN                    0
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED1_BITS                     3
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED1_SHIFT                    7

/* BRPHY1_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KR_EEE [06:06] */
#define Wr_BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x40,6,x)
#define Rd_BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x40,6)
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_MASK            0x0040
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_ALIGN           0
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_BITS            1
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_SHIFT           6

/* BRPHY1_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KX4_EEE [05:05] */
#define Wr_BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x20,5,x)
#define Rd_BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x20,5)
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_MASK           0x0020
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_ALIGN          0
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_BITS           1
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_SHIFT          5

/* BRPHY1_CL45DEV7 :: EEE_ADV :: reserved2 [04:04] */
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED2_MASK                     0x0010
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED2_ALIGN                    0
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED2_BITS                     1
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED2_SHIFT                    4

/* BRPHY1_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_T_EEE [03:03] */
#define Wr_BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x8,3,x)
#define Rd_BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x8,3)
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_MASK             0x0008
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_ALIGN            0
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_BITS             1
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_SHIFT            3

/* BRPHY1_CL45DEV7 :: EEE_ADV :: PHY_1000BASE_T_EEE [02:02] */
#define Wr_BRPHY1_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x4,2,x)
#define Rd_BRPHY1_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x4,2)
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_MASK            0x0004
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_ALIGN           0
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_BITS            1
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_SHIFT           2

/* BRPHY1_CL45DEV7 :: EEE_ADV :: PHY_100BASE_T_EEE [01:01] */
#define Wr_BRPHY1_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x2,1,x)
#define Rd_BRPHY1_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_ADV,0x2,1)
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_MASK             0x0002
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_ALIGN            0
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_BITS             1
#define BRPHY1_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_SHIFT            1

/* BRPHY1_CL45DEV7 :: EEE_ADV :: reserved3 [00:00] */
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED3_MASK                     0x0001
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED3_ALIGN                    0
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED3_BITS                     1
#define BRPHY1_CL45DEV7_EEE_ADV_RESERVED3_SHIFT                    0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: EEE_LP_ADV
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: EEE_LP_ADV :: status [15:00] */
#define Wr_BRPHY1_CL45DEV7_EEE_LP_ADV_status(x) WriteReg16(BRPHY1_CL45DEV7_EEE_LP_ADV,x)
#define Rd_BRPHY1_CL45DEV7_EEE_LP_ADV_status(x) ReadReg16(BRPHY1_CL45DEV7_EEE_LP_ADV)
#define BRPHY1_CL45DEV7_EEE_LP_ADV_STATUS_MASK                     0xffff
#define BRPHY1_CL45DEV7_EEE_LP_ADV_STATUS_ALIGN                    0
#define BRPHY1_CL45DEV7_EEE_LP_ADV_STATUS_BITS                     16
#define BRPHY1_CL45DEV7_EEE_LP_ADV_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY1_CL45DEV7 :: EEE_MODE_CTL
 ***************************************************************************/
/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: reserved0 [15:11] */
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED0_MASK                0xf800
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED0_ALIGN               0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED0_BITS                5
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED0_SHIFT               11

/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: Next_page [10:10] */
#define Wr_BRPHY1_CL45DEV7_EEE_MODE_CTL_Next_page(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x400,10,x)
#define Rd_BRPHY1_CL45DEV7_EEE_MODE_CTL_Next_page(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x400,10)
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_MASK                0x0400
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_ALIGN               0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_BITS                1
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_SHIFT               10

/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: reserved1 [09:07] */
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED1_MASK                0x0380
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED1_ALIGN               0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED1_BITS                3
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED1_SHIFT               7

/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KR_reduced_energy [06:06] */
#define Wr_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x40,6,x)
#define Rd_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x40,6)
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_MASK 0x0040
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_ALIGN 0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_BITS 1
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_SHIFT 6

/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KX4_reduced_energy [05:05] */
#define Wr_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x20,5,x)
#define Rd_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x20,5)
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_MASK 0x0020
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_ALIGN 0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_BITS 1
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_SHIFT 5

/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: reserved2 [04:04] */
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED2_MASK                0x0010
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED2_ALIGN               0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED2_BITS                1
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED2_SHIFT               4

/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_T_reduced_energy [03:03] */
#define Wr_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x8,3,x)
#define Rd_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x8,3)
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_MASK 0x0008
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_SHIFT 3

/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: PHY_1000BASE_T_reduced_energy [02:02] */
#define Wr_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x4,2,x)
#define Rd_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x4,2)
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_MASK 0x0004
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_SHIFT 2

/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: PHY_100BASE_T_reduced_energy [01:01] */
#define Wr_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) WriteRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x2,1,x)
#define Rd_BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) ReadRegBits16(BRPHY1_CL45DEV7_EEE_MODE_CTL,0x2,1)
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_MASK 0x0002
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_SHIFT 1

/* BRPHY1_CL45DEV7 :: EEE_MODE_CTL :: reserved3 [00:00] */
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED3_MASK                0x0001
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED3_ALIGN               0
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED3_BITS                1
#define BRPHY1_CL45DEV7_EEE_MODE_CTL_RESERVED3_SHIFT               0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_CL45VEN
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_CL45VEN :: FORCE_LINK
 ***************************************************************************/
/* BRPHY1_CL45VEN :: FORCE_LINK :: FORCE_LINK_MODE [15:15] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x8000,15,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x8000,15)
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_MASK             0x8000
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_ALIGN            0
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_BITS             1
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_SHIFT            15

/* BRPHY1_CL45VEN :: FORCE_LINK :: CHNG_10GBASET_AN_CTRL_BEHAV [14:14] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x4000,14,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x4000,14)
#define BRPHY1_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_MASK 0x4000
#define BRPHY1_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_ALIGN 0
#define BRPHY1_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_BITS 1
#define BRPHY1_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_SHIFT 14

/* BRPHY1_CL45VEN :: FORCE_LINK :: CHNG_BIT13_MCTRL_RD_BEHAV [13:13] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x2000,13,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x2000,13)
#define BRPHY1_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_MASK   0x2000
#define BRPHY1_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_ALIGN  0
#define BRPHY1_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_BITS   1
#define BRPHY1_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_SHIFT  13

/* BRPHY1_CL45VEN :: FORCE_LINK :: AN_FLP_BTB_TMR_MODE [12:12] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x1000,12,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x1000,12)
#define BRPHY1_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_MASK         0x1000
#define BRPHY1_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_ALIGN        0
#define BRPHY1_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_BITS         1
#define BRPHY1_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_SHIFT        12

/* BRPHY1_CL45VEN :: FORCE_LINK :: SWP_UFORMATED_CODE_FLDS [11:11] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x800,11,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x800,11)
#define BRPHY1_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_MASK     0x0800
#define BRPHY1_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_ALIGN    0
#define BRPHY1_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_BITS     1
#define BRPHY1_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_SHIFT    11

/* BRPHY1_CL45VEN :: FORCE_LINK :: BRK_LNK_TMR_MODE [10:10] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x400,10,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x400,10)
#define BRPHY1_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_MASK            0x0400
#define BRPHY1_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_ALIGN           0
#define BRPHY1_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_BITS            1
#define BRPHY1_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_SHIFT           10

/* BRPHY1_CL45VEN :: FORCE_LINK :: PREAMBLE_IGNORE [09:09] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x200,9,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x200,9)
#define BRPHY1_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_MASK             0x0200
#define BRPHY1_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_ALIGN            0
#define BRPHY1_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_BITS             1
#define BRPHY1_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_SHIFT            9

/* BRPHY1_CL45VEN :: FORCE_LINK :: FORCE_LNK_10GBASET_FDX [08:08] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x100,8,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x100,8)
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_MASK      0x0100
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_ALIGN     0
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_BITS      1
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_SHIFT     8

/* BRPHY1_CL45VEN :: FORCE_LINK :: FORCE_LNK_1000BASET_FDX_HDX [07:07] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x80,7,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x80,7)
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_MASK 0x0080
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_ALIGN 0
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_BITS 1
#define BRPHY1_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_SHIFT 7

/* BRPHY1_CL45VEN :: FORCE_LINK :: IGNORE_ACK2 [06:06] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x40,6,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x40,6)
#define BRPHY1_CL45VEN_FORCE_LINK_IGNORE_ACK2_MASK                 0x0040
#define BRPHY1_CL45VEN_FORCE_LINK_IGNORE_ACK2_ALIGN                0
#define BRPHY1_CL45VEN_FORCE_LINK_IGNORE_ACK2_BITS                 1
#define BRPHY1_CL45VEN_FORCE_LINK_IGNORE_ACK2_SHIFT                6

/* BRPHY1_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_OK [05:05] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x20,5,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x20,5)
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_MASK       0x0020
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_ALIGN      0
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_BITS       1
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_SHIFT      5

/* BRPHY1_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_RDY [04:04] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x10,4,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x10,4)
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_MASK      0x0010
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_ALIGN     0
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_BITS      1
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_SHIFT     4

/* BRPHY1_CL45VEN :: FORCE_LINK :: DIS_REG7P0_BIT13_AUTO_UPDATE [03:03] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x8,3,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x8,3)
#define BRPHY1_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_MASK 0x0008
#define BRPHY1_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_ALIGN 0
#define BRPHY1_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_BITS 1
#define BRPHY1_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_SHIFT 3

/* BRPHY1_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_OK [02:02] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x4,2,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x4,2)
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_MASK        0x0004
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_ALIGN       0
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_BITS        1
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_SHIFT       2

/* BRPHY1_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_RDY [01:01] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x2,1,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x2,1)
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_MASK       0x0002
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_ALIGN      0
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_BITS       1
#define BRPHY1_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_SHIFT      1

/* BRPHY1_CL45VEN :: FORCE_LINK :: LAST_PG_TO_EN [00:00] */
#define Wr_BRPHY1_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) WriteRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x1,0,x)
#define Rd_BRPHY1_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) ReadRegBits16(BRPHY1_CL45VEN_FORCE_LINK,0x1,0)
#define BRPHY1_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_MASK               0x0001
#define BRPHY1_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_ALIGN              0
#define BRPHY1_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_BITS               1
#define BRPHY1_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_SHIFT              0


/****************************************************************************
 * BRPHY1_CL45VEN :: SELECTIVE_RESET
 ***************************************************************************/
/* BRPHY1_CL45VEN :: SELECTIVE_RESET :: DSP_RESET [15:15] */
#define Wr_BRPHY1_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) WriteRegBits16(BRPHY1_CL45VEN_SELECTIVE_RESET,0x8000,15,x)
#define Rd_BRPHY1_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) ReadRegBits16(BRPHY1_CL45VEN_SELECTIVE_RESET,0x8000,15)
#define BRPHY1_CL45VEN_SELECTIVE_RESET_DSP_RESET_MASK              0x8000
#define BRPHY1_CL45VEN_SELECTIVE_RESET_DSP_RESET_ALIGN             0
#define BRPHY1_CL45VEN_SELECTIVE_RESET_DSP_RESET_BITS              1
#define BRPHY1_CL45VEN_SELECTIVE_RESET_DSP_RESET_SHIFT             15

/* BRPHY1_CL45VEN :: SELECTIVE_RESET :: SM_DSP_RESET [14:14] */
#define Wr_BRPHY1_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) WriteRegBits16(BRPHY1_CL45VEN_SELECTIVE_RESET,0x4000,14,x)
#define Rd_BRPHY1_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) ReadRegBits16(BRPHY1_CL45VEN_SELECTIVE_RESET,0x4000,14)
#define BRPHY1_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_MASK           0x4000
#define BRPHY1_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_ALIGN          0
#define BRPHY1_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_BITS           1
#define BRPHY1_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_SHIFT          14

/* BRPHY1_CL45VEN :: SELECTIVE_RESET :: reserved0 [13:08] */
#define BRPHY1_CL45VEN_SELECTIVE_RESET_RESERVED0_MASK              0x3f00
#define BRPHY1_CL45VEN_SELECTIVE_RESET_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_SELECTIVE_RESET_RESERVED0_BITS              6
#define BRPHY1_CL45VEN_SELECTIVE_RESET_RESERVED0_SHIFT             8

/* BRPHY1_CL45VEN :: SELECTIVE_RESET :: DIG100_RESET [07:07] */
#define Wr_BRPHY1_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) WriteRegBits16(BRPHY1_CL45VEN_SELECTIVE_RESET,0x80,7,x)
#define Rd_BRPHY1_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) ReadRegBits16(BRPHY1_CL45VEN_SELECTIVE_RESET,0x80,7)
#define BRPHY1_CL45VEN_SELECTIVE_RESET_DIG100_RESET_MASK           0x0080
#define BRPHY1_CL45VEN_SELECTIVE_RESET_DIG100_RESET_ALIGN          0
#define BRPHY1_CL45VEN_SELECTIVE_RESET_DIG100_RESET_BITS           1
#define BRPHY1_CL45VEN_SELECTIVE_RESET_DIG100_RESET_SHIFT          7

/* BRPHY1_CL45VEN :: SELECTIVE_RESET :: reserved1 [06:00] */
#define BRPHY1_CL45VEN_SELECTIVE_RESET_RESERVED1_MASK              0x007f
#define BRPHY1_CL45VEN_SELECTIVE_RESET_RESERVED1_ALIGN             0
#define BRPHY1_CL45VEN_SELECTIVE_RESET_RESERVED1_BITS              7
#define BRPHY1_CL45VEN_SELECTIVE_RESET_RESERVED1_SHIFT             0


/****************************************************************************
 * BRPHY1_CL45VEN :: TEST_FSM_EXT_NXT_PGS
 ***************************************************************************/
/* BRPHY1_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved0 [15:15] */
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_MASK         0x8000
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_ALIGN        0
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_BITS         1
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_SHIFT        15

/* BRPHY1_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_XMTR_STATE [14:12] */
#define Wr_BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) WriteRegBits16(BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12,x)
#define Rd_BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) ReadRegBits16(BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12)
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_MASK    0x7000
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_ALIGN   0
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_BITS    3
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_SHIFT   12

/* BRPHY1_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved1 [11:11] */
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_MASK         0x0800
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_ALIGN        0
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_BITS         1
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_SHIFT        11

/* BRPHY1_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_RCVR_STATE [10:08] */
#define Wr_BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) WriteRegBits16(BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8,x)
#define Rd_BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) ReadRegBits16(BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8)
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_MASK    0x0700
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_ALIGN   0
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_BITS    3
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_SHIFT   8

/* BRPHY1_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: ARB_STATE [07:04] */
#define Wr_BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) WriteRegBits16(BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4,x)
#define Rd_BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) ReadRegBits16(BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4)
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_MASK         0x00f0
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_ALIGN        0
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_BITS         4
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_SHIFT        4

/* BRPHY1_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: HCD_STATE [03:00] */
#define Wr_BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) WriteRegBits16(BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0,x)
#define Rd_BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) ReadRegBits16(BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0)
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_MASK         0x000f
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_ALIGN        0
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_BITS         4
#define BRPHY1_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_SHIFT        0


/****************************************************************************
 * BRPHY1_CL45VEN :: TEST_FSM_NXT_PGS
 ***************************************************************************/
/* BRPHY1_CL45VEN :: TEST_FSM_NXT_PGS :: reserved0 [15:10] */
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_MASK             0xfc00
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_ALIGN            0
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_BITS             6
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_SHIFT            10

/* BRPHY1_CL45VEN :: TEST_FSM_NXT_PGS :: NP_XMTR_STATE [09:05] */
#define Wr_BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) WriteRegBits16(BRPHY1_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5,x)
#define Rd_BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) ReadRegBits16(BRPHY1_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5)
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_MASK         0x03e0
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_ALIGN        0
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_BITS         5
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_SHIFT        5

/* BRPHY1_CL45VEN :: TEST_FSM_NXT_PGS :: reserved1 [04:04] */
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_MASK             0x0010
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_ALIGN            0
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_BITS             1
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_SHIFT            4

/* BRPHY1_CL45VEN :: TEST_FSM_NXT_PGS :: NP_RCVR_STATE [03:00] */
#define Wr_BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) WriteRegBits16(BRPHY1_CL45VEN_TEST_FSM_NXT_PGS,0xf,0,x)
#define Rd_BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) ReadRegBits16(BRPHY1_CL45VEN_TEST_FSM_NXT_PGS,0xf,0)
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_MASK         0x000f
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_ALIGN        0
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_BITS         4
#define BRPHY1_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_SHIFT        0


/****************************************************************************
 * BRPHY1_CL45VEN :: AN_MAN_TEST
 ***************************************************************************/
/* BRPHY1_CL45VEN :: AN_MAN_TEST :: reserved0 [15:12] */
#define BRPHY1_CL45VEN_AN_MAN_TEST_RESERVED0_MASK                  0xf000
#define BRPHY1_CL45VEN_AN_MAN_TEST_RESERVED0_ALIGN                 0
#define BRPHY1_CL45VEN_AN_MAN_TEST_RESERVED0_BITS                  4
#define BRPHY1_CL45VEN_AN_MAN_TEST_RESERVED0_SHIFT                 12

/* BRPHY1_CL45VEN :: AN_MAN_TEST :: LP_PG_TO_CAPTURE [11:08] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_TEST,0xf00,8,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_TEST,0xf00,8)
#define BRPHY1_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_MASK           0x0f00
#define BRPHY1_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_ALIGN          0
#define BRPHY1_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_BITS           4
#define BRPHY1_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_SHIFT          8

/* BRPHY1_CL45VEN :: AN_MAN_TEST :: reserved1 [07:03] */
#define BRPHY1_CL45VEN_AN_MAN_TEST_RESERVED1_MASK                  0x00f8
#define BRPHY1_CL45VEN_AN_MAN_TEST_RESERVED1_ALIGN                 0
#define BRPHY1_CL45VEN_AN_MAN_TEST_RESERVED1_BITS                  5
#define BRPHY1_CL45VEN_AN_MAN_TEST_RESERVED1_SHIFT                 3

/* BRPHY1_CL45VEN :: AN_MAN_TEST :: LNK_PARTNR_NXT_PG_TEST_MODE [02:02] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_TEST,0x4,2,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_TEST,0x4,2)
#define BRPHY1_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_MASK 0x0004
#define BRPHY1_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_SHIFT 2

/* BRPHY1_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN_SEED [01:01] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_TEST,0x2,1,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_TEST,0x2,1)
#define BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_MASK           0x0002
#define BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_ALIGN          0
#define BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_BITS           1
#define BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_SHIFT          1

/* BRPHY1_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN [00:00] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_TEST,0x1,0,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_TEST,0x1,0)
#define BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_MASK                0x0001
#define BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_ALIGN               0
#define BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_BITS                1
#define BRPHY1_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SHIFT               0


/****************************************************************************
 * BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A
 ***************************************************************************/
/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_HDX [15:15] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_MASK 0x8000
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_SHIFT 15

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_FDX [14:14] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_MASK 0x4000
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_SHIFT 14

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_PORT_TYPE [13:13] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_MASK 0x2000
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_SHIFT 13

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_CONFIG_VALUE [12:12] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_MASK 0x1000
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_SHIFT 12

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_MANUAL_CONFIG_EN [11:11] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_MASK 0x0800
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_SHIFT 11

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_SEED [10:00] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_MASK    0x07ff
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_ALIGN   0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_BITS    11
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_SHIFT   0


/****************************************************************************
 * BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B
 ***************************************************************************/
/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved0 [15:05] */
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_MASK      0xffe0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_ALIGN     0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_BITS      11
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_SHIFT     5

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PMA_TRAINING_RESET_REQ [04:04] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_MASK 0x0010
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_SHIFT 4

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved1 [03:03] */
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_MASK      0x0008
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_ALIGN     0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_BITS      1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_SHIFT     3

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PHY_SHORT_REACH_MODE [02:02] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_MASK 0x0004
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_SHIFT 2

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_LOOP_TIMING_ABILITY [01:01] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_MASK 0x0002
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_SHIFT 1

/* BRPHY1_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_10GBASET_CAPABILITY [00:00] */
#define Wr_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) WriteRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0,x)
#define Rd_BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) ReadRegBits16(BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0)
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_MASK 0x0001
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_ALIGN 0
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_BITS 1
#define BRPHY1_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_A
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_A :: LP_NP_A [15:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) WriteReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_A,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) ReadReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_A)
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_MASK            0xffff
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_ALIGN           0
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_BITS            16
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_SHIFT           0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_B
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_B :: LP_NP_B [15:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) WriteReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_B,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) ReadReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_B)
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_MASK            0xffff
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_ALIGN           0
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_BITS            16
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_SHIFT           0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_C
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_C :: LP_NP_C [15:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) WriteReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_C,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) ReadReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_C)
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_MASK            0xffff
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_ALIGN           0
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_BITS            16
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_SHIFT           0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_D
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_D :: LP_NP_D [15:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) WriteReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_D,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) ReadReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_D)
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_MASK            0xffff
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_ALIGN           0
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_BITS            16
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_SHIFT           0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_E
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_E :: LP_NP_E [15:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) WriteReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_E,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) ReadReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_E)
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_MASK            0xffff
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_ALIGN           0
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_BITS            16
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_SHIFT           0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_F
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_NXT_PG_F :: LP_NP_F [15:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) WriteReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_F,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) ReadReg16(BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_F)
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_MASK            0xffff
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_ALIGN           0
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_BITS            16
#define BRPHY1_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_SHIFT           0


/****************************************************************************
 * BRPHY1_CL45VEN :: EPON_CTRL_REG
 ***************************************************************************/
/* BRPHY1_CL45VEN :: EPON_CTRL_REG :: reserved0 [15:10] */
#define BRPHY1_CL45VEN_EPON_CTRL_REG_RESERVED0_MASK                0xfc00
#define BRPHY1_CL45VEN_EPON_CTRL_REG_RESERVED0_ALIGN               0
#define BRPHY1_CL45VEN_EPON_CTRL_REG_RESERVED0_BITS                6
#define BRPHY1_CL45VEN_EPON_CTRL_REG_RESERVED0_SHIFT               10

/* BRPHY1_CL45VEN :: EPON_CTRL_REG :: EPON_MODE [09:09] */
#define Wr_BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) WriteRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x200,9,x)
#define Rd_BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) ReadRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x200,9)
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_MASK                0x0200
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_ALIGN               0
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_BITS                1
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_SHIFT               9

/* BRPHY1_CL45VEN :: EPON_CTRL_REG :: EOC_PACKET_NORM [08:08] */
#define Wr_BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) WriteRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x100,8,x)
#define Rd_BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) ReadRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x100,8)
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_MASK          0x0100
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_ALIGN         0
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_BITS          1
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_SHIFT         8

/* BRPHY1_CL45VEN :: EPON_CTRL_REG :: EPON_MODE_CRCCHECK [07:07] */
#define Wr_BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) WriteRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x80,7,x)
#define Rd_BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) ReadRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x80,7)
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_MASK       0x0080
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_ALIGN      0
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_BITS       1
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_SHIFT      7

/* BRPHY1_CL45VEN :: EPON_CTRL_REG :: TX_EN_EXTEND [06:06] */
#define Wr_BRPHY1_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) WriteRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x40,6,x)
#define Rd_BRPHY1_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) ReadRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x40,6)
#define BRPHY1_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_MASK             0x0040
#define BRPHY1_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_ALIGN            0
#define BRPHY1_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_BITS             1
#define BRPHY1_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_SHIFT            6

/* BRPHY1_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POLARITY [05:05] */
#define Wr_BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) WriteRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x20,5,x)
#define Rd_BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) ReadRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x20,5)
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_MASK        0x0020
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_ALIGN       0
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_BITS        1
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_SHIFT       5

/* BRPHY1_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POL_CORR [04:04] */
#define Wr_BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) WriteRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x10,4,x)
#define Rd_BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) ReadRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0x10,4)
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_MASK        0x0010
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_ALIGN       0
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_BITS        1
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_SHIFT       4

/* BRPHY1_CL45VEN :: EPON_CTRL_REG :: EOC_SPEED_DET_THLD [03:00] */
#define Wr_BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) WriteRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0xf,0,x)
#define Rd_BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) ReadRegBits16(BRPHY1_CL45VEN_EPON_CTRL_REG,0xf,0)
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_MASK       0x000f
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_ALIGN      0
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_BITS       4
#define BRPHY1_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_SHIFT      0


/****************************************************************************
 * BRPHY1_CL45VEN :: EEE_TEST_CTRL_A
 ***************************************************************************/
/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: reserved0 [15:12] */
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_MASK              0xf000
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_BITS              4
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_SHIFT             12

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_RX_EN [11:11] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x800,11,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x800,11)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_MASK        0x0800
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_ALIGN       0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_BITS        1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_SHIFT       11

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_TX_EN [10:10] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x400,10,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x400,10)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_MASK        0x0400
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_ALIGN       0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_BITS        1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_SHIFT       10

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_RX_EN [09:09] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x200,9,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x200,9)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_MASK           0x0200
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_ALIGN          0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_BITS           1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_SHIFT          9

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_TX_EN [08:08] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x100,8,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x100,8)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_MASK           0x0100
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_ALIGN          0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_BITS           1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_SHIFT          8

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: LPI_GPCS_TEST_BUS_EN [07:07] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x80,7,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x80,7)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_MASK   0x0080
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_ALIGN  0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_BITS   1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_SHIFT  7

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: MACSEC_PK_MODE [06:06] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x40,6,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x40,6)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_MASK         0x0040
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_ALIGN        0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_BITS         1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_SHIFT        6

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: MSG_11_VS_10 [05:05] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x20,5,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x20,5)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_MASK           0x0020
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_ALIGN          0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_BITS           1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_SHIFT          5

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE [04:04] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x10,4,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x10,4)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_MASK              0x0010
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_ALIGN             0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_BITS              1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFT             4

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE_SHIFTED [03:03] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x8,3,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x8,3)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_MASK      0x0008
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_ALIGN     0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_BITS      1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_SHIFT     3

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: reserved1 [02:02] */
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_MASK              0x0004
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_ALIGN             0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_BITS              1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_SHIFT             2

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LP_M10 [01:01] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x2,1,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x2,1)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_MASK        0x0002
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_ALIGN       0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_BITS        1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_SHIFT       1

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LD_M10 [00:00] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x1,0,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_A,0x1,0)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_MASK        0x0001
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_ALIGN       0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_BITS        1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_SHIFT       0


/****************************************************************************
 * BRPHY1_CL45VEN :: EEE_TEST_CTRL_B
 ***************************************************************************/
/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x8000,15,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x8000,15)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_MASK         0x8000
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_ALIGN        0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_BITS         1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_SHIFT        15

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x4000,14,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x4000,14)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_MASK 0x4000
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_ALIGN 0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_BITS 1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_SHIFT 14

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_LPI_QUALIFIERS [13:13] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x2000,13,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x2000,13)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_MASK 0x2000
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_ALIGN 0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_BITS 1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_SHIFT 13

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_REG_3_20 [12:12] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x1000,12,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x1000,12)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_MASK 0x1000
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_ALIGN 0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_BITS 1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_SHIFT 12

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_RES [11:11] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x800,11,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x800,11)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_MASK       0x0800
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_ALIGN      0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_BITS       1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_SHIFT      11

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_10BASE_T_RES [10:10] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x400,10,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x400,10)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_MASK 0x0400
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_ALIGN 0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_BITS 1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_SHIFT 10

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: DET_SEND_Z [09:09] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x200,9,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x200,9)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_MASK             0x0200
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_ALIGN            0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_BITS             1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_SHIFT            9

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: EN_DET_SEND_Z_OVERRIDE [08:08] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x100,8,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x100,8)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_MASK 0x0100
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_ALIGN 0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_BITS 1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_SHIFT 8

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: REM_UPD_DONE_TEST [07:07] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x80,7,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x80,7)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_MASK      0x0080
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_ALIGN     0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_BITS      1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_SHIFT     7

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: REM_LPI_REQ_TEST [06:06] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x40,6,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x40,6)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_MASK       0x0040
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_ALIGN      0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_BITS       1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_SHIFT      6

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: LOC_UPD_DONE_TEST [05:05] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x20,5,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x20,5)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_MASK      0x0020
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_ALIGN     0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_BITS      1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_SHIFT     5

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: LOC_LPI_REQ_TEST [04:04] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x10,4,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x10,4)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_MASK       0x0010
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_ALIGN      0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_BITS       1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_SHIFT      4

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_UPD_DONE_OVERRIDE [03:03] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x8,3,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x8,3)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_MASK 0x0008
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_SHIFT 3

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_LPI_REQ_OVERRIDE [02:02] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x4,2,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x4,2)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_MASK 0x0004
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_SHIFT 2

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_UPD_DONE_OVERRIDE [01:01] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x2,1,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x2,1)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_MASK 0x0002
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_SHIFT 1

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_LPI_REQ_OVERRIDE [00:00] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x1,0,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_B,0x1,0)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_MASK 0x0001
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: EEE_TEST_CTRL_C
 ***************************************************************************/
/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_RX_EN [15:15] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x8000,15,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x8000,15)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_MASK        0x8000
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_ALIGN       0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_BITS        1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_SHIFT       15

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_TX_EN [14:14] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x4000,14,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x4000,14)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_MASK        0x4000
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_ALIGN       0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_BITS        1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_SHIFT       14

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_RX_EN [13:13] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x2000,13,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x2000,13)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_MASK            0x2000
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_ALIGN           0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_BITS            1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_SHIFT           13

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_TX_EN [12:12] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x1000,12,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x1000,12)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_MASK            0x1000
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_ALIGN           0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_BITS            1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_SHIFT           12

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_RX_EN [11:11] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x800,11,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x800,11)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_MASK        0x0800
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_ALIGN       0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_BITS        1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_SHIFT       11

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_TX_EN [10:10] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x400,10,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x400,10)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_MASK        0x0400
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_ALIGN       0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_BITS        1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_SHIFT       10

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_RX_EN [09:09] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x200,9,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x200,9)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_MASK            0x0200
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_ALIGN           0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_BITS            1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_SHIFT           9

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_TX_EN [08:08] */
#define Wr_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x100,8,x)
#define Rd_BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_TEST_CTRL_C,0x100,8)
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_MASK            0x0100
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_ALIGN           0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_BITS            1
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_SHIFT           8

/* BRPHY1_CL45VEN :: EEE_TEST_CTRL_C :: reserved0 [07:00] */
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_MASK              0x00ff
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_BITS              8
#define BRPHY1_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_SHIFT             0


/****************************************************************************
 * BRPHY1_CL45VEN :: EEE_SPARE_1
 ***************************************************************************/
/* BRPHY1_CL45VEN :: EEE_SPARE_1 :: SPARE [15:00] */
#define Wr_BRPHY1_CL45VEN_EEE_SPARE_1_SPARE(x) WriteReg16(BRPHY1_CL45VEN_EEE_SPARE_1,x)
#define Rd_BRPHY1_CL45VEN_EEE_SPARE_1_SPARE(x) ReadReg16(BRPHY1_CL45VEN_EEE_SPARE_1)
#define BRPHY1_CL45VEN_EEE_SPARE_1_SPARE_MASK                      0xffff
#define BRPHY1_CL45VEN_EEE_SPARE_1_SPARE_ALIGN                     0
#define BRPHY1_CL45VEN_EEE_SPARE_1_SPARE_BITS                      16
#define BRPHY1_CL45VEN_EEE_SPARE_1_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY1_CL45VEN :: EEE_SPARE_2
 ***************************************************************************/
/* BRPHY1_CL45VEN :: EEE_SPARE_2 :: SPARE [15:00] */
#define Wr_BRPHY1_CL45VEN_EEE_SPARE_2_SPARE(x) WriteReg16(BRPHY1_CL45VEN_EEE_SPARE_2,x)
#define Rd_BRPHY1_CL45VEN_EEE_SPARE_2_SPARE(x) ReadReg16(BRPHY1_CL45VEN_EEE_SPARE_2)
#define BRPHY1_CL45VEN_EEE_SPARE_2_SPARE_MASK                      0xffff
#define BRPHY1_CL45VEN_EEE_SPARE_2_SPARE_ALIGN                     0
#define BRPHY1_CL45VEN_EEE_SPARE_2_SPARE_BITS                      16
#define BRPHY1_CL45VEN_EEE_SPARE_2_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY1_CL45VEN :: EEE_CONTROL
 ***************************************************************************/
/* BRPHY1_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x8000,15,x)
#define Rd_BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x8000,15)
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_MASK             0x8000
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_ALIGN            0
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_BITS             1
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_SHIFT            15

/* BRPHY1_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x4000,14,x)
#define Rd_BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x4000,14)
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_MASK    0x4000
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_ALIGN   0
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_BITS    1
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_SHIFT   14

/* BRPHY1_CL45VEN :: EEE_CONTROL :: LPI_RES_IN_FORCE_MODE_EN [13:13] */
#define Wr_BRPHY1_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x2000,13,x)
#define Rd_BRPHY1_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x2000,13)
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_MASK   0x2000
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_ALIGN  0
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_BITS   1
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_SHIFT  13

/* BRPHY1_CL45VEN :: EEE_CONTROL :: SPARE [12:03] */
#define Wr_BRPHY1_CL45VEN_EEE_CONTROL_SPARE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x1ff8,3,x)
#define Rd_BRPHY1_CL45VEN_EEE_CONTROL_SPARE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x1ff8,3)
#define BRPHY1_CL45VEN_EEE_CONTROL_SPARE_MASK                      0x1ff8
#define BRPHY1_CL45VEN_EEE_CONTROL_SPARE_ALIGN                     0
#define BRPHY1_CL45VEN_EEE_CONTROL_SPARE_BITS                      10
#define BRPHY1_CL45VEN_EEE_CONTROL_SPARE_SHIFT                     3

/* BRPHY1_CL45VEN :: EEE_CONTROL :: LPI_LINKUP_DISABLE [02:02] */
#define Wr_BRPHY1_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x4,2,x)
#define Rd_BRPHY1_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x4,2)
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_MASK         0x0004
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_ALIGN        0
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_BITS         1
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_SHIFT        2

/* BRPHY1_CL45VEN :: EEE_CONTROL :: EEE_DOWNGRADE_ENABLE [01:01] */
#define Wr_BRPHY1_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x2,1,x)
#define Rd_BRPHY1_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x2,1)
#define BRPHY1_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_MASK       0x0002
#define BRPHY1_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_ALIGN      0
#define BRPHY1_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_BITS       1
#define BRPHY1_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_SHIFT      1

/* BRPHY1_CL45VEN :: EEE_CONTROL :: LPI_100TX_BRCM_LINK [00:00] */
#define Wr_BRPHY1_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x1,0,x)
#define Rd_BRPHY1_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_CONTROL,0x1,0)
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_MASK        0x0001
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_ALIGN       0
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_BITS        1
#define BRPHY1_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_SHIFT       0


/****************************************************************************
 * BRPHY1_CL45VEN :: EEE_RES_STAT
 ***************************************************************************/
/* BRPHY1_CL45VEN :: EEE_RES_STAT :: reserved0 [15:07] */
#define BRPHY1_CL45VEN_EEE_RES_STAT_RESERVED0_MASK                 0xff80
#define BRPHY1_CL45VEN_EEE_RES_STAT_RESERVED0_ALIGN                0
#define BRPHY1_CL45VEN_EEE_RES_STAT_RESERVED0_BITS                 9
#define BRPHY1_CL45VEN_EEE_RES_STAT_RESERVED0_SHIFT                7

/* BRPHY1_CL45VEN :: EEE_RES_STAT :: MASK_1000T_EEE [06:06] */
#define Wr_BRPHY1_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x40,6,x)
#define Rd_BRPHY1_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x40,6)
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_MASK            0x0040
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_ALIGN           0
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_BITS            1
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_SHIFT           6

/* BRPHY1_CL45VEN :: EEE_RES_STAT :: MASK_100TX_EEE [05:05] */
#define Wr_BRPHY1_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x20,5,x)
#define Rd_BRPHY1_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x20,5)
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_MASK            0x0020
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_ALIGN           0
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_BITS            1
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_SHIFT           5

/* BRPHY1_CL45VEN :: EEE_RES_STAT :: MASK_10T_EEE [04:04] */
#define Wr_BRPHY1_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x10,4,x)
#define Rd_BRPHY1_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x10,4)
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_MASK              0x0010
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_ALIGN             0
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_BITS              1
#define BRPHY1_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_SHIFT             4

/* BRPHY1_CL45VEN :: EEE_RES_STAT :: reserved1 [03:03] */
#define BRPHY1_CL45VEN_EEE_RES_STAT_RESERVED1_MASK                 0x0008
#define BRPHY1_CL45VEN_EEE_RES_STAT_RESERVED1_ALIGN                0
#define BRPHY1_CL45VEN_EEE_RES_STAT_RESERVED1_BITS                 1
#define BRPHY1_CL45VEN_EEE_RES_STAT_RESERVED1_SHIFT                3

/* BRPHY1_CL45VEN :: EEE_RES_STAT :: EEE_1000T_RES [02:02] */
#define Wr_BRPHY1_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x4,2,x)
#define Rd_BRPHY1_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x4,2)
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_MASK             0x0004
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_ALIGN            0
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_BITS             1
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_SHIFT            2

/* BRPHY1_CL45VEN :: EEE_RES_STAT :: EEE_100TX_RES [01:01] */
#define Wr_BRPHY1_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x2,1,x)
#define Rd_BRPHY1_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x2,1)
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_MASK             0x0002
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_ALIGN            0
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_BITS             1
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_SHIFT            1

/* BRPHY1_CL45VEN :: EEE_RES_STAT :: EEE_10BASE_TE_RES [00:00] */
#define Wr_BRPHY1_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) WriteRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x1,0,x)
#define Rd_BRPHY1_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) ReadRegBits16(BRPHY1_CL45VEN_EEE_RES_STAT,0x1,0)
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_MASK         0x0001
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_ALIGN        0
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_BITS         1
#define BRPHY1_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_SHIFT        0


/****************************************************************************
 * BRPHY1_CL45VEN :: LPI_MODE_CNTR
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LPI_MODE_CNTR :: LPI_MODE_COUNTER [15:00] */
#define Wr_BRPHY1_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) WriteReg16(BRPHY1_CL45VEN_LPI_MODE_CNTR,x)
#define Rd_BRPHY1_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) ReadReg16(BRPHY1_CL45VEN_LPI_MODE_CNTR)
#define BRPHY1_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_MASK         0xffff
#define BRPHY1_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_ALIGN        0
#define BRPHY1_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_BITS         16
#define BRPHY1_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_SHIFT        0


/****************************************************************************
 * BRPHY1_CL45VEN :: LOC_DEV_MSG_5_A
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LOC_DEV_MSG_5_A :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_MASK              0xf800
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_BITS              5
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_SHIFT             11

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_5_A :: BITS_10_0_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LOC_DEV_MSG_5_B
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LOC_DEV_MSG_5_B :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_MASK              0xf800
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_BITS              5
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_SHIFT             11

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_5_B :: BITS_21_11_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LOC_DEV_MSG_5_C
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LOC_DEV_MSG_5_C :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_MASK              0xf800
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_BITS              5
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_SHIFT             11

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_5_C :: BITS_32_22_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LOC_DEV_MSG_5_D
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LOC_DEV_MSG_5_D :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_MASK              0xf800
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_BITS              5
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_SHIFT             11

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_5_D :: BITS_43_33_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY1_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_A
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_A :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_MASK           0xf800
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_ALIGN          0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_BITS           5
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_SHIFT          11

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_A :: BITS_10_0_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_B
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_B :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_MASK           0xf800
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_ALIGN          0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_BITS           5
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_SHIFT          11

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_B :: BITS_21_11_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_C
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_C :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_MASK           0xf800
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_ALIGN          0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_BITS           5
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_SHIFT          11

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_C :: BITS_32_22_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_D
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_D :: MSG_5_OUI_MATCH [15:15] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_MASK     0x8000
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_ALIGN    0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_BITS     1
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_SHIFT    15

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_D :: reserved0 [14:11] */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_MASK           0x7800
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_ALIGN          0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_BITS           4
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_SHIFT          11

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_5_D :: BITS_43_33_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LOC_DEV_MSG_6_A
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_A :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_MASK              0xf800
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_BITS              5
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_SHIFT             11

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_A :: BITS_10_0_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LOC_DEV_MSG_6_B
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_B :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_MASK              0xf800
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_BITS              5
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_SHIFT             11

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_21_17_OF_LOC_DEV_MSG_6 [10:06] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_MASK 0x07c0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_BITS 5
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_SHIFT 6

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_16_11_OF_LOC_DEV_MSG_6 [05:00] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_MASK 0x003f
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_BITS 6
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LOC_DEV_MSG_6_C
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_C :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_MASK              0xf800
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_BITS              5
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_SHIFT             11

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_32_23_OF_LOC_DEV_MSG_6 [10:01] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_MASK 0x07fe
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_BITS 10
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_SHIFT 1

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_22_22_OF_LOC_DEV_MSG_6 [00:00] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_C,0x1,0,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_C,0x1,0)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_MASK 0x0001
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_BITS 1
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LOC_DEV_MSG_6_D
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_D :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_MASK              0xf800
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_ALIGN             0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_BITS              5
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_SHIFT             11

/* BRPHY1_CL45VEN :: LOC_DEV_MSG_6_D :: BITS_43_33_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0)
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY1_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_A
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_A :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_MASK           0xf800
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_ALIGN          0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_BITS           5
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_SHIFT          11

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_A :: BITS_10_0_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_B
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_B :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_MASK           0xf800
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_ALIGN          0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_BITS           5
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_SHIFT          11

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_B :: BITS_21_11_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_C
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_C :: reserved0 [15:11] */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_MASK           0xf800
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_ALIGN          0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_BITS           5
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_SHIFT          11

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_C :: BITS_32_22_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_D
 ***************************************************************************/
/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_OUI_MATCH [15:15] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_MASK     0x8000
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_ALIGN    0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_BITS     1
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_SHIFT    15

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_MODEL_MATCH [14:14] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_MASK   0x4000
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_ALIGN  0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_BITS   1
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_SHIFT  14

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_REV_MATCH [13:13] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_MASK     0x2000
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_ALIGN    0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_BITS     1
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_SHIFT    13

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_D :: reserved0 [12:11] */
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_MASK           0x1800
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_ALIGN          0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_BITS           2
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_SHIFT          11

/* BRPHY1_CL45VEN :: LNK_PARTNR_MSG_6_D :: BITS_43_33_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0)
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY1_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_GPHY_CORE
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE10
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE10 :: MAC_PHY_IF [15:15] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_MAC_PHY_IF(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_MAC_PHY_IF(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x8000,15)
#define BRPHY1_GPHY_CORE_BASE10_MAC_PHY_IF_MASK                    0x8000
#define BRPHY1_GPHY_CORE_BASE10_MAC_PHY_IF_ALIGN                   0
#define BRPHY1_GPHY_CORE_BASE10_MAC_PHY_IF_BITS                    1
#define BRPHY1_GPHY_CORE_BASE10_MAC_PHY_IF_SHIFT                   15

/* BRPHY1_GPHY_CORE :: BASE10 :: AUTO_MDIX_DIS [14:14] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x4000,14)
#define BRPHY1_GPHY_CORE_BASE10_AUTO_MDIX_DIS_MASK                 0x4000
#define BRPHY1_GPHY_CORE_BASE10_AUTO_MDIX_DIS_ALIGN                0
#define BRPHY1_GPHY_CORE_BASE10_AUTO_MDIX_DIS_BITS                 1
#define BRPHY1_GPHY_CORE_BASE10_AUTO_MDIX_DIS_SHIFT                14

/* BRPHY1_GPHY_CORE :: BASE10 :: TX_DIS [13:13] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_TX_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_TX_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x2000,13)
#define BRPHY1_GPHY_CORE_BASE10_TX_DIS_MASK                        0x2000
#define BRPHY1_GPHY_CORE_BASE10_TX_DIS_ALIGN                       0
#define BRPHY1_GPHY_CORE_BASE10_TX_DIS_BITS                        1
#define BRPHY1_GPHY_CORE_BASE10_TX_DIS_SHIFT                       13

/* BRPHY1_GPHY_CORE :: BASE10 :: INT_DIS [12:12] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_INT_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_INT_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x1000,12)
#define BRPHY1_GPHY_CORE_BASE10_INT_DIS_MASK                       0x1000
#define BRPHY1_GPHY_CORE_BASE10_INT_DIS_ALIGN                      0
#define BRPHY1_GPHY_CORE_BASE10_INT_DIS_BITS                       1
#define BRPHY1_GPHY_CORE_BASE10_INT_DIS_SHIFT                      12

/* BRPHY1_GPHY_CORE :: BASE10 :: FORCE_INT [11:11] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_FORCE_INT(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_FORCE_INT(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x800,11)
#define BRPHY1_GPHY_CORE_BASE10_FORCE_INT_MASK                     0x0800
#define BRPHY1_GPHY_CORE_BASE10_FORCE_INT_ALIGN                    0
#define BRPHY1_GPHY_CORE_BASE10_FORCE_INT_BITS                     1
#define BRPHY1_GPHY_CORE_BASE10_FORCE_INT_SHIFT                    11

/* BRPHY1_GPHY_CORE :: BASE10 :: BYPASS_ENCODER [10:10] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_BYPASS_ENCODER(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_BYPASS_ENCODER(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x400,10)
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_ENCODER_MASK                0x0400
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_ENCODER_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_ENCODER_BITS                1
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_ENCODER_SHIFT               10

/* BRPHY1_GPHY_CORE :: BASE10 :: BYPASS_SCRAMBLER [09:09] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x200,9)
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_MASK              0x0200
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_ALIGN             0
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_BITS              1
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_SHIFT             9

/* BRPHY1_GPHY_CORE :: BASE10 :: BYPASS_NRZI_MLT3 [08:08] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x100,8)
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_MASK              0x0100
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_ALIGN             0
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_BITS              1
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_SHIFT             8

/* BRPHY1_GPHY_CORE :: BASE10 :: BYPASS_ALIGNMENT [07:07] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x80,7)
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_MASK              0x0080
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_ALIGN             0
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_BITS              1
#define BRPHY1_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_SHIFT             7

/* BRPHY1_GPHY_CORE :: BASE10 :: RESET_SCRAMBLER [06:06] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x40,6)
#define BRPHY1_GPHY_CORE_BASE10_RESET_SCRAMBLER_MASK               0x0040
#define BRPHY1_GPHY_CORE_BASE10_RESET_SCRAMBLER_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE10_RESET_SCRAMBLER_BITS               1
#define BRPHY1_GPHY_CORE_BASE10_RESET_SCRAMBLER_SHIFT              6

/* BRPHY1_GPHY_CORE :: BASE10 :: LED_TRAFFIC_EN [05:05] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x20,5)
#define BRPHY1_GPHY_CORE_BASE10_LED_TRAFFIC_EN_MASK                0x0020
#define BRPHY1_GPHY_CORE_BASE10_LED_TRAFFIC_EN_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE10_LED_TRAFFIC_EN_BITS                1
#define BRPHY1_GPHY_CORE_BASE10_LED_TRAFFIC_EN_SHIFT               5

/* BRPHY1_GPHY_CORE :: BASE10 :: FORCE_LEDS_ON [04:04] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x10,4)
#define BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_ON_MASK                 0x0010
#define BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_ON_ALIGN                0
#define BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_ON_BITS                 1
#define BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_ON_SHIFT                4

/* BRPHY1_GPHY_CORE :: BASE10 :: FORCE_LEDS_OFF [03:03] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x8,3)
#define BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_OFF_MASK                0x0008
#define BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_OFF_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_OFF_BITS                1
#define BRPHY1_GPHY_CORE_BASE10_FORCE_LEDS_OFF_SHIFT               3

/* BRPHY1_GPHY_CORE :: BASE10 :: BLOCK_TXEN [02:02] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_BLOCK_TXEN(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_BLOCK_TXEN(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x4,2)
#define BRPHY1_GPHY_CORE_BASE10_BLOCK_TXEN_MASK                    0x0004
#define BRPHY1_GPHY_CORE_BASE10_BLOCK_TXEN_ALIGN                   0
#define BRPHY1_GPHY_CORE_BASE10_BLOCK_TXEN_BITS                    1
#define BRPHY1_GPHY_CORE_BASE10_BLOCK_TXEN_SHIFT                   2

/* BRPHY1_GPHY_CORE :: BASE10 :: UNIDIR_EN [01:01] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_UNIDIR_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_UNIDIR_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x2,1)
#define BRPHY1_GPHY_CORE_BASE10_UNIDIR_EN_MASK                     0x0002
#define BRPHY1_GPHY_CORE_BASE10_UNIDIR_EN_ALIGN                    0
#define BRPHY1_GPHY_CORE_BASE10_UNIDIR_EN_BITS                     1
#define BRPHY1_GPHY_CORE_BASE10_UNIDIR_EN_SHIFT                    1

/* BRPHY1_GPHY_CORE :: BASE10 :: GMII_RGMII_FIFO_ELASTICITY [00:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE10,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE10,0x1,0)
#define BRPHY1_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_MASK    0x0001
#define BRPHY1_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_ALIGN   0
#define BRPHY1_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_BITS    1
#define BRPHY1_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_SHIFT   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE11
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE11 :: AUTONEG_FIELD_MISMATCH [15:15] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x8000,15)
#define BRPHY1_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_MASK        0x8000
#define BRPHY1_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_ALIGN       0
#define BRPHY1_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_BITS        1
#define BRPHY1_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_SHIFT       15

/* BRPHY1_GPHY_CORE :: BASE11 :: WIRESPD_DOWNGRADE [14:14] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x4000,14)
#define BRPHY1_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_MASK             0x4000
#define BRPHY1_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_ALIGN            0
#define BRPHY1_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_BITS             1
#define BRPHY1_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_SHIFT            14

/* BRPHY1_GPHY_CORE :: BASE11 :: MDIX_STATE [13:13] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_MDIX_STATE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_MDIX_STATE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x2000,13)
#define BRPHY1_GPHY_CORE_BASE11_MDIX_STATE_MASK                    0x2000
#define BRPHY1_GPHY_CORE_BASE11_MDIX_STATE_ALIGN                   0
#define BRPHY1_GPHY_CORE_BASE11_MDIX_STATE_BITS                    1
#define BRPHY1_GPHY_CORE_BASE11_MDIX_STATE_SHIFT                   13

/* BRPHY1_GPHY_CORE :: BASE11 :: INT_STATUS [12:12] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_INT_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_INT_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x1000,12)
#define BRPHY1_GPHY_CORE_BASE11_INT_STATUS_MASK                    0x1000
#define BRPHY1_GPHY_CORE_BASE11_INT_STATUS_ALIGN                   0
#define BRPHY1_GPHY_CORE_BASE11_INT_STATUS_BITS                    1
#define BRPHY1_GPHY_CORE_BASE11_INT_STATUS_SHIFT                   12

/* BRPHY1_GPHY_CORE :: BASE11 :: RMT_RCVR_STATUS [11:11] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x800,11)
#define BRPHY1_GPHY_CORE_BASE11_RMT_RCVR_STATUS_MASK               0x0800
#define BRPHY1_GPHY_CORE_BASE11_RMT_RCVR_STATUS_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE11_RMT_RCVR_STATUS_BITS               1
#define BRPHY1_GPHY_CORE_BASE11_RMT_RCVR_STATUS_SHIFT              11

/* BRPHY1_GPHY_CORE :: BASE11 :: LOCAL_RCVR_STATUS [10:10] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x400,10)
#define BRPHY1_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_MASK             0x0400
#define BRPHY1_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_ALIGN            0
#define BRPHY1_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_BITS             1
#define BRPHY1_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_SHIFT            10

/* BRPHY1_GPHY_CORE :: BASE11 :: LOCKED [09:09] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_LOCKED(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_LOCKED(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x200,9)
#define BRPHY1_GPHY_CORE_BASE11_LOCKED_MASK                        0x0200
#define BRPHY1_GPHY_CORE_BASE11_LOCKED_ALIGN                       0
#define BRPHY1_GPHY_CORE_BASE11_LOCKED_BITS                        1
#define BRPHY1_GPHY_CORE_BASE11_LOCKED_SHIFT                       9

/* BRPHY1_GPHY_CORE :: BASE11 :: LINK_STATUS [08:08] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_LINK_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_LINK_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x100,8)
#define BRPHY1_GPHY_CORE_BASE11_LINK_STATUS_MASK                   0x0100
#define BRPHY1_GPHY_CORE_BASE11_LINK_STATUS_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE11_LINK_STATUS_BITS                   1
#define BRPHY1_GPHY_CORE_BASE11_LINK_STATUS_SHIFT                  8

/* BRPHY1_GPHY_CORE :: BASE11 :: CRC_ERR_DET [07:07] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_CRC_ERR_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_CRC_ERR_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x80,7)
#define BRPHY1_GPHY_CORE_BASE11_CRC_ERR_DET_MASK                   0x0080
#define BRPHY1_GPHY_CORE_BASE11_CRC_ERR_DET_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE11_CRC_ERR_DET_BITS                   1
#define BRPHY1_GPHY_CORE_BASE11_CRC_ERR_DET_SHIFT                  7

/* BRPHY1_GPHY_CORE :: BASE11 :: CR_EXT_ERR_DET [06:06] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x40,6)
#define BRPHY1_GPHY_CORE_BASE11_CR_EXT_ERR_DET_MASK                0x0040
#define BRPHY1_GPHY_CORE_BASE11_CR_EXT_ERR_DET_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE11_CR_EXT_ERR_DET_BITS                1
#define BRPHY1_GPHY_CORE_BASE11_CR_EXT_ERR_DET_SHIFT               6

/* BRPHY1_GPHY_CORE :: BASE11 :: BAD_SSD_DET_CR [05:05] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x20,5)
#define BRPHY1_GPHY_CORE_BASE11_BAD_SSD_DET_CR_MASK                0x0020
#define BRPHY1_GPHY_CORE_BASE11_BAD_SSD_DET_CR_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE11_BAD_SSD_DET_CR_BITS                1
#define BRPHY1_GPHY_CORE_BASE11_BAD_SSD_DET_CR_SHIFT               5

/* BRPHY1_GPHY_CORE :: BASE11 :: BAD_ESD_DET_END [04:04] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x10,4)
#define BRPHY1_GPHY_CORE_BASE11_BAD_ESD_DET_END_MASK               0x0010
#define BRPHY1_GPHY_CORE_BASE11_BAD_ESD_DET_END_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE11_BAD_ESD_DET_END_BITS               1
#define BRPHY1_GPHY_CORE_BASE11_BAD_ESD_DET_END_SHIFT              4

/* BRPHY1_GPHY_CORE :: BASE11 :: RCV_ERR_DET [03:03] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_RCV_ERR_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_RCV_ERR_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x8,3)
#define BRPHY1_GPHY_CORE_BASE11_RCV_ERR_DET_MASK                   0x0008
#define BRPHY1_GPHY_CORE_BASE11_RCV_ERR_DET_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE11_RCV_ERR_DET_BITS                   1
#define BRPHY1_GPHY_CORE_BASE11_RCV_ERR_DET_SHIFT                  3

/* BRPHY1_GPHY_CORE :: BASE11 :: TX_ERR_DET [02:02] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_TX_ERR_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_TX_ERR_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x4,2)
#define BRPHY1_GPHY_CORE_BASE11_TX_ERR_DET_MASK                    0x0004
#define BRPHY1_GPHY_CORE_BASE11_TX_ERR_DET_ALIGN                   0
#define BRPHY1_GPHY_CORE_BASE11_TX_ERR_DET_BITS                    1
#define BRPHY1_GPHY_CORE_BASE11_TX_ERR_DET_SHIFT                   2

/* BRPHY1_GPHY_CORE :: BASE11 :: LOCK_ERR_DET [01:01] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_LOCK_ERR_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_LOCK_ERR_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x2,1)
#define BRPHY1_GPHY_CORE_BASE11_LOCK_ERR_DET_MASK                  0x0002
#define BRPHY1_GPHY_CORE_BASE11_LOCK_ERR_DET_ALIGN                 0
#define BRPHY1_GPHY_CORE_BASE11_LOCK_ERR_DET_BITS                  1
#define BRPHY1_GPHY_CORE_BASE11_LOCK_ERR_DET_SHIFT                 1

/* BRPHY1_GPHY_CORE :: BASE11 :: MLT3_ERR_DET [00:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE11_MLT3_ERR_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE11,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE11_MLT3_ERR_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE11,0x1,0)
#define BRPHY1_GPHY_CORE_BASE11_MLT3_ERR_DET_MASK                  0x0001
#define BRPHY1_GPHY_CORE_BASE11_MLT3_ERR_DET_ALIGN                 0
#define BRPHY1_GPHY_CORE_BASE11_MLT3_ERR_DET_BITS                  1
#define BRPHY1_GPHY_CORE_BASE11_MLT3_ERR_DET_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE12
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE12 :: RCV_ERR_CNTR [15:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) WriteReg16(BRPHY1_GPHY_CORE_BASE12,x)
#define Rd_BRPHY1_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) ReadReg16(BRPHY1_GPHY_CORE_BASE12)
#define BRPHY1_GPHY_CORE_BASE12_RCV_ERR_CNTR_MASK                  0xffff
#define BRPHY1_GPHY_CORE_BASE12_RCV_ERR_CNTR_ALIGN                 0
#define BRPHY1_GPHY_CORE_BASE12_RCV_ERR_CNTR_BITS                  16
#define BRPHY1_GPHY_CORE_BASE12_RCV_ERR_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE13
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE13 :: SERDES_BER_CNTR [15:08] */
#define Wr_BRPHY1_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE13,0xff00,8,x)
#define Rd_BRPHY1_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE13,0xff00,8)
#define BRPHY1_GPHY_CORE_BASE13_SERDES_BER_CNTR_MASK               0xff00
#define BRPHY1_GPHY_CORE_BASE13_SERDES_BER_CNTR_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE13_SERDES_BER_CNTR_BITS               8
#define BRPHY1_GPHY_CORE_BASE13_SERDES_BER_CNTR_SHIFT              8

/* BRPHY1_GPHY_CORE :: BASE13 :: FALSE_CRS_CNTR [07:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE13,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE13,0xff,0)
#define BRPHY1_GPHY_CORE_BASE13_FALSE_CRS_CNTR_MASK                0x00ff
#define BRPHY1_GPHY_CORE_BASE13_FALSE_CRS_CNTR_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE13_FALSE_CRS_CNTR_BITS                8
#define BRPHY1_GPHY_CORE_BASE13_FALSE_CRS_CNTR_SHIFT               0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE14
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE14 :: LOCAL_RCVR_NOK_CNTR [15:08] */
#define Wr_BRPHY1_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE14,0xff00,8,x)
#define Rd_BRPHY1_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE14,0xff00,8)
#define BRPHY1_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_MASK           0xff00
#define BRPHY1_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_ALIGN          0
#define BRPHY1_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_BITS           8
#define BRPHY1_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_SHIFT          8

/* BRPHY1_GPHY_CORE :: BASE14 :: REMOTE_RCVR_NOK_CNTR [07:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE14,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE14,0xff,0)
#define BRPHY1_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_MASK          0x00ff
#define BRPHY1_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_ALIGN         0
#define BRPHY1_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_BITS          8
#define BRPHY1_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_SHIFT         0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP45
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP45 :: SEL_SERDES_TX [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXP45_SEL_SERDES_TX(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP45,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXP45_SEL_SERDES_TX(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP45,0x8000,15)
#define BRPHY1_GPHY_CORE_EXP45_SEL_SERDES_TX_MASK                  0x8000
#define BRPHY1_GPHY_CORE_EXP45_SEL_SERDES_TX_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP45_SEL_SERDES_TX_BITS                  1
#define BRPHY1_GPHY_CORE_EXP45_SEL_SERDES_TX_SHIFT                 15

/* BRPHY1_GPHY_CORE :: EXP45 :: TX_ERR [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXP45_TX_ERR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP45,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXP45_TX_ERR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP45,0x4000,14)
#define BRPHY1_GPHY_CORE_EXP45_TX_ERR_MASK                         0x4000
#define BRPHY1_GPHY_CORE_EXP45_TX_ERR_ALIGN                        0
#define BRPHY1_GPHY_CORE_EXP45_TX_ERR_BITS                         1
#define BRPHY1_GPHY_CORE_EXP45_TX_ERR_SHIFT                        14

/* BRPHY1_GPHY_CORE :: EXP45 :: SKIP_CRC [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXP45_SKIP_CRC(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP45,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXP45_SKIP_CRC(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP45,0x2000,13)
#define BRPHY1_GPHY_CORE_EXP45_SKIP_CRC_MASK                       0x2000
#define BRPHY1_GPHY_CORE_EXP45_SKIP_CRC_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP45_SKIP_CRC_BITS                       1
#define BRPHY1_GPHY_CORE_EXP45_SKIP_CRC_SHIFT                      13

/* BRPHY1_GPHY_CORE :: EXP45 :: TX_CRC_CHECKER_EN [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP45,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP45,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_MASK              0x1000
#define BRPHY1_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_BITS              1
#define BRPHY1_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_SHIFT             12

/* BRPHY1_GPHY_CORE :: EXP45 :: IPG_SEL [11:09] */
#define Wr_BRPHY1_GPHY_CORE_EXP45_IPG_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP45,0xe00,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXP45_IPG_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP45,0xe00,9)
#define BRPHY1_GPHY_CORE_EXP45_IPG_SEL_MASK                        0x0e00
#define BRPHY1_GPHY_CORE_EXP45_IPG_SEL_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP45_IPG_SEL_BITS                        3
#define BRPHY1_GPHY_CORE_EXP45_IPG_SEL_SHIFT                       9

/* BRPHY1_GPHY_CORE :: EXP45 :: PKT_SIZE [08:03] */
#define Wr_BRPHY1_GPHY_CORE_EXP45_PKT_SIZE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP45,0x1f8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXP45_PKT_SIZE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP45,0x1f8,3)
#define BRPHY1_GPHY_CORE_EXP45_PKT_SIZE_MASK                       0x01f8
#define BRPHY1_GPHY_CORE_EXP45_PKT_SIZE_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP45_PKT_SIZE_BITS                       6
#define BRPHY1_GPHY_CORE_EXP45_PKT_SIZE_SHIFT                      3

/* BRPHY1_GPHY_CORE :: EXP45 :: SINGLE_PASS [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP45_SINGLE_PASS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP45,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP45_SINGLE_PASS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP45,0x4,2)
#define BRPHY1_GPHY_CORE_EXP45_SINGLE_PASS_MASK                    0x0004
#define BRPHY1_GPHY_CORE_EXP45_SINGLE_PASS_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP45_SINGLE_PASS_BITS                    1
#define BRPHY1_GPHY_CORE_EXP45_SINGLE_PASS_SHIFT                   2

/* BRPHY1_GPHY_CORE :: EXP45 :: RUN_PAT_GEN [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP45_RUN_PAT_GEN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP45,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP45_RUN_PAT_GEN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP45,0x2,1)
#define BRPHY1_GPHY_CORE_EXP45_RUN_PAT_GEN_MASK                    0x0002
#define BRPHY1_GPHY_CORE_EXP45_RUN_PAT_GEN_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP45_RUN_PAT_GEN_BITS                    1
#define BRPHY1_GPHY_CORE_EXP45_RUN_PAT_GEN_SHIFT                   1

/* BRPHY1_GPHY_CORE :: EXP45 :: SEL_PAT_GEN_DATA [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP45,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP45,0x1,0)
#define BRPHY1_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_MASK               0x0001
#define BRPHY1_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_BITS               1
#define BRPHY1_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP46
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP46 :: GMII_FIFO_ELASTICITY_1 [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP46,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP46,0x8000,15)
#define BRPHY1_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_MASK         0x8000
#define BRPHY1_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_ALIGN        0
#define BRPHY1_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_BITS         1
#define BRPHY1_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_SHIFT        15

/* BRPHY1_GPHY_CORE :: EXP46 :: GMII_RGMII_FIFO_ELASTICITY_1 [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP46,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP46,0x4000,14)
#define BRPHY1_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_MASK   0x4000
#define BRPHY1_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_ALIGN  0
#define BRPHY1_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_BITS   1
#define BRPHY1_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_SHIFT  14

/* BRPHY1_GPHY_CORE :: EXP46 :: PKT_SIZE_6 [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXP46_PKT_SIZE_6(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP46,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXP46_PKT_SIZE_6(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP46,0x2000,13)
#define BRPHY1_GPHY_CORE_EXP46_PKT_SIZE_6_MASK                     0x2000
#define BRPHY1_GPHY_CORE_EXP46_PKT_SIZE_6_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP46_PKT_SIZE_6_BITS                     1
#define BRPHY1_GPHY_CORE_EXP46_PKT_SIZE_6_SHIFT                    13

/* BRPHY1_GPHY_CORE :: EXP46 :: CR_EXT [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP46_CR_EXT(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP46,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP46_CR_EXT(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP46,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP46_CR_EXT_MASK                         0x1000
#define BRPHY1_GPHY_CORE_EXP46_CR_EXT_ALIGN                        0
#define BRPHY1_GPHY_CORE_EXP46_CR_EXT_BITS                         1
#define BRPHY1_GPHY_CORE_EXP46_CR_EXT_SHIFT                        12

/* BRPHY1_GPHY_CORE :: EXP46 :: reserved0 [11:07] */
#define BRPHY1_GPHY_CORE_EXP46_RESERVED0_MASK                      0x0f80
#define BRPHY1_GPHY_CORE_EXP46_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP46_RESERVED0_BITS                      5
#define BRPHY1_GPHY_CORE_EXP46_RESERVED0_SHIFT                     7

/* BRPHY1_GPHY_CORE :: EXP46 :: RGMII_FIFO_FREQ_LOCK [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP46,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP46,0x40,6)
#define BRPHY1_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_MASK           0x0040
#define BRPHY1_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_ALIGN          0
#define BRPHY1_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_BITS           1
#define BRPHY1_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_SHIFT          6

/* BRPHY1_GPHY_CORE :: EXP46 :: reserved1 [05:05] */
#define BRPHY1_GPHY_CORE_EXP46_RESERVED1_MASK                      0x0020
#define BRPHY1_GPHY_CORE_EXP46_RESERVED1_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP46_RESERVED1_BITS                      1
#define BRPHY1_GPHY_CORE_EXP46_RESERVED1_SHIFT                     5

/* BRPHY1_GPHY_CORE :: EXP46 :: SEL_PATGEN_ON_RXD [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP46,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP46,0x10,4)
#define BRPHY1_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_MASK              0x0010
#define BRPHY1_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_BITS              1
#define BRPHY1_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_SHIFT             4

/* BRPHY1_GPHY_CORE :: EXP46 :: PAT_GEN_ACTIVE [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP46,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP46,0x8,3)
#define BRPHY1_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_MASK                 0x0008
#define BRPHY1_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_BITS                 1
#define BRPHY1_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_SHIFT                3

/* BRPHY1_GPHY_CORE :: EXP46 :: PAT_GEN_FSM [02:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP46_PAT_GEN_FSM(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP46,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP46_PAT_GEN_FSM(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP46,0x7,0)
#define BRPHY1_GPHY_CORE_EXP46_PAT_GEN_FSM_MASK                    0x0007
#define BRPHY1_GPHY_CORE_EXP46_PAT_GEN_FSM_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP46_PAT_GEN_FSM_BITS                    3
#define BRPHY1_GPHY_CORE_EXP46_PAT_GEN_FSM_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE19
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE [15:15] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x8000,15)
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_MASK              0x8000
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ALIGN             0
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_BITS              1
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_SHIFT             15

/* BRPHY1_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE_ACK [14:14] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x4000,14)
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_MASK          0x4000
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_ALIGN         0
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_BITS          1
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_SHIFT         14

/* BRPHY1_GPHY_CORE :: BASE19 :: AUTONEG_ACK_DET [13:13] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x2000,13)
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_ACK_DET_MASK               0x2000
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_ACK_DET_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_ACK_DET_BITS               1
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_ACK_DET_SHIFT              13

/* BRPHY1_GPHY_CORE :: BASE19 :: AUTONEG_ABILITY_DET [12:12] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x1000,12)
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_MASK           0x1000
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_ALIGN          0
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_BITS           1
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_SHIFT          12

/* BRPHY1_GPHY_CORE :: BASE19 :: AUTONEG_NEXT_PAGE_WAIT [11:11] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x800,11)
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_MASK        0x0800
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_ALIGN       0
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_BITS        1
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_SHIFT       11

/* BRPHY1_GPHY_CORE :: BASE19 :: AUTONEG_HCD [10:08] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_AUTONEG_HCD(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x700,8,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_AUTONEG_HCD(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x700,8)
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_HCD_MASK                   0x0700
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_HCD_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_HCD_BITS                   3
#define BRPHY1_GPHY_CORE_BASE19_AUTONEG_HCD_SHIFT                  8

/* BRPHY1_GPHY_CORE :: BASE19 :: PARALLEL_DET_FAULT [07:07] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x80,7)
#define BRPHY1_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_MASK            0x0080
#define BRPHY1_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_ALIGN           0
#define BRPHY1_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_BITS            1
#define BRPHY1_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_SHIFT           7

/* BRPHY1_GPHY_CORE :: BASE19 :: REMOTE_FAULT [06:06] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_REMOTE_FAULT(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_REMOTE_FAULT(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x40,6)
#define BRPHY1_GPHY_CORE_BASE19_REMOTE_FAULT_MASK                  0x0040
#define BRPHY1_GPHY_CORE_BASE19_REMOTE_FAULT_ALIGN                 0
#define BRPHY1_GPHY_CORE_BASE19_REMOTE_FAULT_BITS                  1
#define BRPHY1_GPHY_CORE_BASE19_REMOTE_FAULT_SHIFT                 6

/* BRPHY1_GPHY_CORE :: BASE19 :: PAGE_RECEIVED [05:05] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_PAGE_RECEIVED(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_PAGE_RECEIVED(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x20,5)
#define BRPHY1_GPHY_CORE_BASE19_PAGE_RECEIVED_MASK                 0x0020
#define BRPHY1_GPHY_CORE_BASE19_PAGE_RECEIVED_ALIGN                0
#define BRPHY1_GPHY_CORE_BASE19_PAGE_RECEIVED_BITS                 1
#define BRPHY1_GPHY_CORE_BASE19_PAGE_RECEIVED_SHIFT                5

/* BRPHY1_GPHY_CORE :: BASE19 :: LINK_PARTNER_AN_ABILITY [04:04] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x10,4)
#define BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_MASK       0x0010
#define BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_SHIFT      4

/* BRPHY1_GPHY_CORE :: BASE19 :: LINK_PARTNER_NP_ABILITY [03:03] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x8,3)
#define BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_MASK       0x0008
#define BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_ALIGN      0
#define BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_BITS       1
#define BRPHY1_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_SHIFT      3

/* BRPHY1_GPHY_CORE :: BASE19 :: LINK_STATUS [02:02] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_LINK_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_LINK_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x4,2)
#define BRPHY1_GPHY_CORE_BASE19_LINK_STATUS_MASK                   0x0004
#define BRPHY1_GPHY_CORE_BASE19_LINK_STATUS_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE19_LINK_STATUS_BITS                   1
#define BRPHY1_GPHY_CORE_BASE19_LINK_STATUS_SHIFT                  2

/* BRPHY1_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_RX [01:01] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x2,1)
#define BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_MASK           0x0002
#define BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_ALIGN          0
#define BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_BITS           1
#define BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_SHIFT          1

/* BRPHY1_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_TX [00:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE19,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE19,0x1,0)
#define BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_MASK           0x0001
#define BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_ALIGN          0
#define BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_BITS           1
#define BRPHY1_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_SHIFT          0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE1A
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE1A :: IP_STATUS_CHANGE [15:15] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x8000,15)
#define BRPHY1_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_MASK              0x8000
#define BRPHY1_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_ALIGN             0
#define BRPHY1_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_BITS              1
#define BRPHY1_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_SHIFT             15

/* BRPHY1_GPHY_CORE :: BASE1A :: ILLEGAL_PAIR_SWAP [14:14] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x4000,14)
#define BRPHY1_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_MASK             0x4000
#define BRPHY1_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_ALIGN            0
#define BRPHY1_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_BITS             1
#define BRPHY1_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_SHIFT            14

/* BRPHY1_GPHY_CORE :: BASE1A :: MDIX_STATUS_CHANGE [13:13] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x2000,13)
#define BRPHY1_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_MASK            0x2000
#define BRPHY1_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_ALIGN           0
#define BRPHY1_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_BITS            1
#define BRPHY1_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_SHIFT           13

/* BRPHY1_GPHY_CORE :: BASE1A :: EXCEED_HIGH_CNTR_THD [12:12] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x1000,12)
#define BRPHY1_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_MASK          0x1000
#define BRPHY1_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_ALIGN         0
#define BRPHY1_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_BITS          1
#define BRPHY1_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_SHIFT         12

/* BRPHY1_GPHY_CORE :: BASE1A :: EXCEED_LOW_CNTR_THD [11:11] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x800,11)
#define BRPHY1_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_MASK           0x0800
#define BRPHY1_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_ALIGN          0
#define BRPHY1_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_BITS           1
#define BRPHY1_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_SHIFT          11

/* BRPHY1_GPHY_CORE :: BASE1A :: AUTONEG_PAGE_RX [10:10] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x400,10)
#define BRPHY1_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_MASK               0x0400
#define BRPHY1_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_BITS               1
#define BRPHY1_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_SHIFT              10

/* BRPHY1_GPHY_CORE :: BASE1A :: HCD_NO_LINK [09:09] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_HCD_NO_LINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_HCD_NO_LINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x200,9)
#define BRPHY1_GPHY_CORE_BASE1A_HCD_NO_LINK_MASK                   0x0200
#define BRPHY1_GPHY_CORE_BASE1A_HCD_NO_LINK_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE1A_HCD_NO_LINK_BITS                   1
#define BRPHY1_GPHY_CORE_BASE1A_HCD_NO_LINK_SHIFT                  9

/* BRPHY1_GPHY_CORE :: BASE1A :: NO_HCD [08:08] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_NO_HCD(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_NO_HCD(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x100,8)
#define BRPHY1_GPHY_CORE_BASE1A_NO_HCD_MASK                        0x0100
#define BRPHY1_GPHY_CORE_BASE1A_NO_HCD_ALIGN                       0
#define BRPHY1_GPHY_CORE_BASE1A_NO_HCD_BITS                        1
#define BRPHY1_GPHY_CORE_BASE1A_NO_HCD_SHIFT                       8

/* BRPHY1_GPHY_CORE :: BASE1A :: NEGOTIATED_UNSUPPORTED_HCD [07:07] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x80,7)
#define BRPHY1_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_MASK    0x0080
#define BRPHY1_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_ALIGN   0
#define BRPHY1_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_BITS    1
#define BRPHY1_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_SHIFT   7

/* BRPHY1_GPHY_CORE :: BASE1A :: SCR_SYNC_ERROR [06:06] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x40,6)
#define BRPHY1_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_MASK                0x0040
#define BRPHY1_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_BITS                1
#define BRPHY1_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_SHIFT               6

/* BRPHY1_GPHY_CORE :: BASE1A :: RMT_RCVR_STATUS_CHANGE [05:05] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x20,5)
#define BRPHY1_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_MASK        0x0020
#define BRPHY1_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_ALIGN       0
#define BRPHY1_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_BITS        1
#define BRPHY1_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_SHIFT       5

/* BRPHY1_GPHY_CORE :: BASE1A :: LOCAL_RCVR_STATUS_CHANGE [04:04] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x10,4)
#define BRPHY1_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_MASK      0x0010
#define BRPHY1_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_ALIGN     0
#define BRPHY1_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_BITS      1
#define BRPHY1_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_SHIFT     4

/* BRPHY1_GPHY_CORE :: BASE1A :: DUPLEX_CHANGE [03:03] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x8,3)
#define BRPHY1_GPHY_CORE_BASE1A_DUPLEX_CHANGE_MASK                 0x0008
#define BRPHY1_GPHY_CORE_BASE1A_DUPLEX_CHANGE_ALIGN                0
#define BRPHY1_GPHY_CORE_BASE1A_DUPLEX_CHANGE_BITS                 1
#define BRPHY1_GPHY_CORE_BASE1A_DUPLEX_CHANGE_SHIFT                3

/* BRPHY1_GPHY_CORE :: BASE1A :: LINK_SPEED_CHANGE [02:02] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x4,2)
#define BRPHY1_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_MASK             0x0004
#define BRPHY1_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_ALIGN            0
#define BRPHY1_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_BITS             1
#define BRPHY1_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_SHIFT            2

/* BRPHY1_GPHY_CORE :: BASE1A :: LINK_STATUS_CHANGE [01:01] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x2,1)
#define BRPHY1_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_MASK            0x0002
#define BRPHY1_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_ALIGN           0
#define BRPHY1_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_BITS            1
#define BRPHY1_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_SHIFT           1

/* BRPHY1_GPHY_CORE :: BASE1A :: CRC_ERROR [00:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE1A_CRC_ERROR(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1A_CRC_ERROR(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1A,0x1,0)
#define BRPHY1_GPHY_CORE_BASE1A_CRC_ERROR_MASK                     0x0001
#define BRPHY1_GPHY_CORE_BASE1A_CRC_ERROR_ALIGN                    0
#define BRPHY1_GPHY_CORE_BASE1A_CRC_ERROR_BITS                     1
#define BRPHY1_GPHY_CORE_BASE1A_CRC_ERROR_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE1B
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE1B :: INT_MASK_VECTOR [15:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) WriteReg16(BRPHY1_GPHY_CORE_BASE1B,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) ReadReg16(BRPHY1_GPHY_CORE_BASE1B)
#define BRPHY1_GPHY_CORE_BASE1B_INT_MASK_VECTOR_MASK               0xffff
#define BRPHY1_GPHY_CORE_BASE1B_INT_MASK_VECTOR_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE1B_INT_MASK_VECTOR_BITS               16
#define BRPHY1_GPHY_CORE_BASE1B_INT_MASK_VECTOR_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE1D_SHD
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x8000,15)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_MASK    0x8000
#define BRPHY1_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_ALIGN   0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_BITS    1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_SHIFT   15

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: GB_ADV_DIS [14:14] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x4000,14)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_MASK                0x4000
#define BRPHY1_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_BITS                1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_SHIFT               14

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: TX_ADV_DIS [13:13] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x2000,13)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_MASK                0x2000
#define BRPHY1_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_BITS                1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_SHIFT               13

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: WIRESPEED_DOWNGRADE [12:12] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x1000,12)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_MASK       0x1000
#define BRPHY1_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_ALIGN      0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_BITS       1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_SHIFT      12

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX [11:11] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x800,11)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_MASK             0x0800
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_ALIGN            0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_BITS             1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_SHIFT            11

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_1000T [10:10] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x400,10)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_MASK                 0x0400
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_ALIGN                0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_BITS                 1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_SHIFT                10

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX [09:09] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x200,9)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_MASK              0x0200
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_ALIGN             0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_BITS              1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_SHIFT             9

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_100T [08:08] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x100,8)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_MASK                  0x0100
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_ALIGN                 0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_BITS                  1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_SHIFT                 8

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX [07:07] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x80,7)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_MASK               0x0080
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_BITS               1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_SHIFT              7

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_10T [06:06] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x40,6)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_MASK                   0x0040
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_BITS                   1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_SHIFT                  6

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX_NL [05:05] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x20,5)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_MASK          0x0020
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_ALIGN         0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_BITS          1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_SHIFT         5

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_NL [04:04] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x10,4)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_MASK              0x0010
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_ALIGN             0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_BITS              1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_SHIFT             4

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX_NL [03:03] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x8,3)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_MASK           0x0008
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_ALIGN          0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_BITS           1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_SHIFT          3

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_100T_NL [02:02] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x4,2)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_MASK               0x0004
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_BITS               1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_SHIFT              2

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX_NL [01:01] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x2,1)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_MASK            0x0002
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_ALIGN           0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_BITS            1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_SHIFT           1

/* BRPHY1_GPHY_CORE :: BASE1D_SHD :: HCD_10T_NL [00:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D_SHD,0x1,0)
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_MASK                0x0001
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_BITS                1
#define BRPHY1_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_SHIFT               0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE1D
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE1D :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x8000,15)
#define BRPHY1_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_MASK        0x8000
#define BRPHY1_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_ALIGN       0
#define BRPHY1_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_BITS        1
#define BRPHY1_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_SHIFT       15

/* BRPHY1_GPHY_CORE :: BASE1D :: MASTER_SLAVE_SEED_MATCH [14:14] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x4000,14)
#define BRPHY1_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_MASK       0x4000
#define BRPHY1_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_ALIGN      0
#define BRPHY1_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_BITS       1
#define BRPHY1_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_SHIFT      14

/* BRPHY1_GPHY_CORE :: BASE1D :: LINK_PARTNER_RD_BIT [13:13] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x2000,13)
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_MASK           0x2000
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_ALIGN          0
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_BITS           1
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_SHIFT          13

/* BRPHY1_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_VALUE [12:12] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x1000,12)
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_MASK         0x1000
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_ALIGN        0
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_BITS         1
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_SHIFT        12

/* BRPHY1_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_CFG_EN [11:11] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x800,11)
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_MASK        0x0800
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_ALIGN       0
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_BITS        1
#define BRPHY1_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_SHIFT       11

/* BRPHY1_GPHY_CORE :: BASE1D :: LOCAL_MS_SEED_VALUE [10:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x7ff,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1D,0x7ff,0)
#define BRPHY1_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_MASK           0x07ff
#define BRPHY1_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_ALIGN          0
#define BRPHY1_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_BITS           11
#define BRPHY1_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_SHIFT          0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE1E
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE1E :: CRC_ERR_CNT [15:15] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x8000,15)
#define BRPHY1_GPHY_CORE_BASE1E_CRC_ERR_CNT_MASK                   0x8000
#define BRPHY1_GPHY_CORE_BASE1E_CRC_ERR_CNT_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE1E_CRC_ERR_CNT_BITS                   1
#define BRPHY1_GPHY_CORE_BASE1E_CRC_ERR_CNT_SHIFT                  15

/* BRPHY1_GPHY_CORE :: BASE1E :: TX_ERR_CODE [14:14] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_TX_ERR_CODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_TX_ERR_CODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x4000,14)
#define BRPHY1_GPHY_CORE_BASE1E_TX_ERR_CODE_MASK                   0x4000
#define BRPHY1_GPHY_CORE_BASE1E_TX_ERR_CODE_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE1E_TX_ERR_CODE_BITS                   1
#define BRPHY1_GPHY_CORE_BASE1E_TX_ERR_CODE_SHIFT                  14

/* BRPHY1_GPHY_CORE :: BASE1E :: CNTR_TEST [13:13] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_CNTR_TEST(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_CNTR_TEST(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x2000,13)
#define BRPHY1_GPHY_CORE_BASE1E_CNTR_TEST_MASK                     0x2000
#define BRPHY1_GPHY_CORE_BASE1E_CNTR_TEST_ALIGN                    0
#define BRPHY1_GPHY_CORE_BASE1E_CNTR_TEST_BITS                     1
#define BRPHY1_GPHY_CORE_BASE1E_CNTR_TEST_SHIFT                    13

/* BRPHY1_GPHY_CORE :: BASE1E :: FORCE_LINK [12:12] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_FORCE_LINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_FORCE_LINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x1000,12)
#define BRPHY1_GPHY_CORE_BASE1E_FORCE_LINK_MASK                    0x1000
#define BRPHY1_GPHY_CORE_BASE1E_FORCE_LINK_ALIGN                   0
#define BRPHY1_GPHY_CORE_BASE1E_FORCE_LINK_BITS                    1
#define BRPHY1_GPHY_CORE_BASE1E_FORCE_LINK_SHIFT                   12

/* BRPHY1_GPHY_CORE :: BASE1E :: FORCE_LOCK [11:11] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_FORCE_LOCK(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_FORCE_LOCK(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x800,11)
#define BRPHY1_GPHY_CORE_BASE1E_FORCE_LOCK_MASK                    0x0800
#define BRPHY1_GPHY_CORE_BASE1E_FORCE_LOCK_ALIGN                   0
#define BRPHY1_GPHY_CORE_BASE1E_FORCE_LOCK_BITS                    1
#define BRPHY1_GPHY_CORE_BASE1E_FORCE_LOCK_SHIFT                   11

/* BRPHY1_GPHY_CORE :: BASE1E :: SCR_TEST [10:10] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_SCR_TEST(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_SCR_TEST(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x400,10)
#define BRPHY1_GPHY_CORE_BASE1E_SCR_TEST_MASK                      0x0400
#define BRPHY1_GPHY_CORE_BASE1E_SCR_TEST_ALIGN                     0
#define BRPHY1_GPHY_CORE_BASE1E_SCR_TEST_BITS                      1
#define BRPHY1_GPHY_CORE_BASE1E_SCR_TEST_SHIFT                     10

/* BRPHY1_GPHY_CORE :: BASE1E :: EXT_LINK [09:09] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_EXT_LINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_EXT_LINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x200,9)
#define BRPHY1_GPHY_CORE_BASE1E_EXT_LINK_MASK                      0x0200
#define BRPHY1_GPHY_CORE_BASE1E_EXT_LINK_ALIGN                     0
#define BRPHY1_GPHY_CORE_BASE1E_EXT_LINK_BITS                      1
#define BRPHY1_GPHY_CORE_BASE1E_EXT_LINK_SHIFT                     9

/* BRPHY1_GPHY_CORE :: BASE1E :: FAST_TIMERS [08:08] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_FAST_TIMERS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_FAST_TIMERS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x100,8)
#define BRPHY1_GPHY_CORE_BASE1E_FAST_TIMERS_MASK                   0x0100
#define BRPHY1_GPHY_CORE_BASE1E_FAST_TIMERS_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE1E_FAST_TIMERS_BITS                   1
#define BRPHY1_GPHY_CORE_BASE1E_FAST_TIMERS_SHIFT                  8

/* BRPHY1_GPHY_CORE :: BASE1E :: MANUAL_SWAP_MDI [07:07] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x80,7)
#define BRPHY1_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_MASK               0x0080
#define BRPHY1_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_BITS               1
#define BRPHY1_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_SHIFT              7

/* BRPHY1_GPHY_CORE :: BASE1E :: RX_WATCHDOG_TIMER_DIS [06:06] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x40,6)
#define BRPHY1_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_MASK         0x0040
#define BRPHY1_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_ALIGN        0
#define BRPHY1_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_BITS         1
#define BRPHY1_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_SHIFT        6

/* BRPHY1_GPHY_CORE :: BASE1E :: POLARITY_ENCODE_DIS [05:05] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x20,5)
#define BRPHY1_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_MASK           0x0020
#define BRPHY1_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_ALIGN          0
#define BRPHY1_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_BITS           1
#define BRPHY1_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_SHIFT          5

/* BRPHY1_GPHY_CORE :: BASE1E :: SOFT_TRIM_SETTING_EN [04:04] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0x10,4)
#define BRPHY1_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_MASK          0x0010
#define BRPHY1_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_ALIGN         0
#define BRPHY1_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_BITS          1
#define BRPHY1_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_SHIFT         4

/* BRPHY1_GPHY_CORE :: BASE1E :: TRIM_MAIN_DAC [03:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1E,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1E,0xf,0)
#define BRPHY1_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_MASK                 0x000f
#define BRPHY1_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_ALIGN                0
#define BRPHY1_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_BITS                 4
#define BRPHY1_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_SHIFT                0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BASE1F
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BASE1F :: TEST_SEL_AUTONEG_FSM [15:13] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0xe000,13,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0xe000,13)
#define BRPHY1_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_MASK          0xe000
#define BRPHY1_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_ALIGN         0
#define BRPHY1_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_BITS          3
#define BRPHY1_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_SHIFT         13

/* BRPHY1_GPHY_CORE :: BASE1F :: TEST_AUTONEG_TIMER [12:12] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x1000,12)
#define BRPHY1_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_MASK            0x1000
#define BRPHY1_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_ALIGN           0
#define BRPHY1_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_BITS            1
#define BRPHY1_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_SHIFT           12

/* BRPHY1_GPHY_CORE :: BASE1F :: TEST_MS_SEED [11:11] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_TEST_MS_SEED(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_TEST_MS_SEED(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x800,11)
#define BRPHY1_GPHY_CORE_BASE1F_TEST_MS_SEED_MASK                  0x0800
#define BRPHY1_GPHY_CORE_BASE1F_TEST_MS_SEED_ALIGN                 0
#define BRPHY1_GPHY_CORE_BASE1F_TEST_MS_SEED_BITS                  1
#define BRPHY1_GPHY_CORE_BASE1F_TEST_MS_SEED_SHIFT                 11

/* BRPHY1_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_ABILITY_EN [10:10] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x400,10)
#define BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_MASK    0x0400
#define BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_ALIGN   0
#define BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_BITS    1
#define BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_SHIFT   10

/* BRPHY1_GPHY_CORE :: BASE1F :: FORCE_HCD [09:09] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_FORCE_HCD(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_FORCE_HCD(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x200,9)
#define BRPHY1_GPHY_CORE_BASE1F_FORCE_HCD_MASK                     0x0200
#define BRPHY1_GPHY_CORE_BASE1F_FORCE_HCD_ALIGN                    0
#define BRPHY1_GPHY_CORE_BASE1F_FORCE_HCD_BITS                     1
#define BRPHY1_GPHY_CORE_BASE1F_FORCE_HCD_SHIFT                    9

/* BRPHY1_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_MS_SEED_EN [08:08] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x100,8)
#define BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_MASK    0x0100
#define BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_ALIGN   0
#define BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_BITS    1
#define BRPHY1_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_SHIFT   8

/* BRPHY1_GPHY_CORE :: BASE1F :: TX_10B [07:07] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_TX_10B(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_TX_10B(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x80,7)
#define BRPHY1_GPHY_CORE_BASE1F_TX_10B_MASK                        0x0080
#define BRPHY1_GPHY_CORE_BASE1F_TX_10B_ALIGN                       0
#define BRPHY1_GPHY_CORE_BASE1F_TX_10B_BITS                        1
#define BRPHY1_GPHY_CORE_BASE1F_TX_10B_SHIFT                       7

/* BRPHY1_GPHY_CORE :: BASE1F :: RX_10B [06:06] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_RX_10B(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_RX_10B(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x40,6)
#define BRPHY1_GPHY_CORE_BASE1F_RX_10B_MASK                        0x0040
#define BRPHY1_GPHY_CORE_BASE1F_RX_10B_ALIGN                       0
#define BRPHY1_GPHY_CORE_BASE1F_RX_10B_BITS                        1
#define BRPHY1_GPHY_CORE_BASE1F_RX_10B_SHIFT                       6

/* BRPHY1_GPHY_CORE :: BASE1F :: BYPASS_TXFIFO [05:05] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x20,5)
#define BRPHY1_GPHY_CORE_BASE1F_BYPASS_TXFIFO_MASK                 0x0020
#define BRPHY1_GPHY_CORE_BASE1F_BYPASS_TXFIFO_ALIGN                0
#define BRPHY1_GPHY_CORE_BASE1F_BYPASS_TXFIFO_BITS                 1
#define BRPHY1_GPHY_CORE_BASE1F_BYPASS_TXFIFO_SHIFT                5

/* BRPHY1_GPHY_CORE :: BASE1F :: SAME_SCR_SEEDS [04:04] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x10,4)
#define BRPHY1_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_MASK                0x0010
#define BRPHY1_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_BITS                1
#define BRPHY1_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_SHIFT               4

/* BRPHY1_GPHY_CORE :: BASE1F :: JITTER_TEST [03:03] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_JITTER_TEST(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_JITTER_TEST(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x8,3)
#define BRPHY1_GPHY_CORE_BASE1F_JITTER_TEST_MASK                   0x0008
#define BRPHY1_GPHY_CORE_BASE1F_JITTER_TEST_ALIGN                  0
#define BRPHY1_GPHY_CORE_BASE1F_JITTER_TEST_BITS                   1
#define BRPHY1_GPHY_CORE_BASE1F_JITTER_TEST_SHIFT                  3

/* BRPHY1_GPHY_CORE :: BASE1F :: TEST_ATMP_CNTR [02:02] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x4,2)
#define BRPHY1_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_MASK                0x0004
#define BRPHY1_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_ALIGN               0
#define BRPHY1_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_BITS                1
#define BRPHY1_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_SHIFT               2

/* BRPHY1_GPHY_CORE :: BASE1F :: LATENCY_MEASURE [01:01] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x2,1)
#define BRPHY1_GPHY_CORE_BASE1F_LATENCY_MEASURE_MASK               0x0002
#define BRPHY1_GPHY_CORE_BASE1F_LATENCY_MEASURE_ALIGN              0
#define BRPHY1_GPHY_CORE_BASE1F_LATENCY_MEASURE_BITS               1
#define BRPHY1_GPHY_CORE_BASE1F_LATENCY_MEASURE_SHIFT              1

/* BRPHY1_GPHY_CORE :: BASE1F :: ACTIVE_HYBRID_DIS [00:00] */
#define Wr_BRPHY1_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_BASE1F,0x1,0)
#define BRPHY1_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_MASK             0x0001
#define BRPHY1_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_ALIGN            0
#define BRPHY1_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_BITS             1
#define BRPHY1_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_SHIFT            0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_00
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_00 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_00_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_00_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_00_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_00_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_00 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_00,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_00,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_00_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_00_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_00_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_00_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_00 :: reserved1 [09:08] */
#define BRPHY1_GPHY_CORE_SHD1C_00_RESERVED1_MASK                   0x0300
#define BRPHY1_GPHY_CORE_SHD1C_00_RESERVED1_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_00_RESERVED1_BITS                   2
#define BRPHY1_GPHY_CORE_SHD1C_00_RESERVED1_SHIFT                  8

/* BRPHY1_GPHY_CORE :: SHD1C_00 :: CABLETRON_LED [07:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_00,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_00,0xff,0)
#define BRPHY1_GPHY_CORE_SHD1C_00_CABLETRON_LED_MASK               0x00ff
#define BRPHY1_GPHY_CORE_SHD1C_00_CABLETRON_LED_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD1C_00_CABLETRON_LED_BITS               8
#define BRPHY1_GPHY_CORE_SHD1C_00_CABLETRON_LED_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_01
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_01 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_01_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_01_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_01_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_01_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_01 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_01,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_01,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_01_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_01_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_01_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_01_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_01 :: reserved1 [09:07] */
#define BRPHY1_GPHY_CORE_SHD1C_01_RESERVED1_MASK                   0x0380
#define BRPHY1_GPHY_CORE_SHD1C_01_RESERVED1_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_01_RESERVED1_BITS                   3
#define BRPHY1_GPHY_CORE_SHD1C_01_RESERVED1_SHIFT                  7

/* BRPHY1_GPHY_CORE :: SHD1C_01 :: TVCO_OUTPUT [06:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_01,0x7f,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_01,0x7f,0)
#define BRPHY1_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_MASK                 0x007f
#define BRPHY1_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_BITS                 7
#define BRPHY1_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_SHIFT                0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_02
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_02 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_02_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_02_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_02_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_02_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_02_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_02_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_02_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_02_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: SD_STATUS [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_SD_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_SD_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x200,9)
#define BRPHY1_GPHY_CORE_SHD1C_02_SD_STATUS_MASK                   0x0200
#define BRPHY1_GPHY_CORE_SHD1C_02_SD_STATUS_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_02_SD_STATUS_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_02_SD_STATUS_SHIFT                  9

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: FORCE_SD_ON [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x100,8)
#define BRPHY1_GPHY_CORE_SHD1C_02_FORCE_SD_ON_MASK                 0x0100
#define BRPHY1_GPHY_CORE_SHD1C_02_FORCE_SD_ON_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD1C_02_FORCE_SD_ON_BITS                 1
#define BRPHY1_GPHY_CORE_SHD1C_02_FORCE_SD_ON_SHIFT                8

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: INVERT_SD_PIN [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_MASK               0x0080
#define BRPHY1_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_BITS               1
#define BRPHY1_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_SHIFT              7

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: CFC_INITFILTER_EN [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x40,6)
#define BRPHY1_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_MASK           0x0040
#define BRPHY1_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_ALIGN          0
#define BRPHY1_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_BITS           1
#define BRPHY1_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_SHIFT          6

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: USE_FILTERED_SD [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x20,5)
#define BRPHY1_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_MASK             0x0020
#define BRPHY1_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_BITS             1
#define BRPHY1_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_SHIFT            5

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: FX_COPPER_PATH [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x10,4)
#define BRPHY1_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_MASK              0x0010
#define BRPHY1_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_BITS              1
#define BRPHY1_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_SHIFT             4

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: SPARE_REG [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x8,3)
#define BRPHY1_GPHY_CORE_SHD1C_02_SPARE_REG_MASK                   0x0008
#define BRPHY1_GPHY_CORE_SHD1C_02_SPARE_REG_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_02_SPARE_REG_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_02_SPARE_REG_SHIFT                  3

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: BC_LINK_SPEED_LED [02:02] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x4,2)
#define BRPHY1_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_MASK           0x0004
#define BRPHY1_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_ALIGN          0
#define BRPHY1_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_BITS           1
#define BRPHY1_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_SHIFT          2

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: LOST_TOKEN_FIX_DIS [01:01] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x2,1)
#define BRPHY1_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_MASK          0x0002
#define BRPHY1_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_BITS          1
#define BRPHY1_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_SHIFT         1

/* BRPHY1_GPHY_CORE :: SHD1C_02 :: LINK_LED [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_02_LINK_LED(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_02_LINK_LED(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_02,0x1,0)
#define BRPHY1_GPHY_CORE_SHD1C_02_LINK_LED_MASK                    0x0001
#define BRPHY1_GPHY_CORE_SHD1C_02_LINK_LED_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD1C_02_LINK_LED_BITS                    1
#define BRPHY1_GPHY_CORE_SHD1C_02_LINK_LED_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_03
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_03 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_03_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_03_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_03_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_03_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_03 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_03_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_03_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_03_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_03_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_03 :: GTXCLK_DLY_EN [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x200,9)
#define BRPHY1_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_MASK               0x0200
#define BRPHY1_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_BITS               1
#define BRPHY1_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_SHIFT              9

/* BRPHY1_GPHY_CORE :: SHD1C_03 :: GMII_CLK_ALIGN_STRB [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x100,8)
#define BRPHY1_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_MASK         0x0100
#define BRPHY1_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_BITS         1
#define BRPHY1_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_SHIFT        8

/* BRPHY1_GPHY_CORE :: SHD1C_03 :: RXCLK_ALIGN_STRB [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_MASK            0x0080
#define BRPHY1_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_BITS            1
#define BRPHY1_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_SHIFT           7

/* BRPHY1_GPHY_CORE :: SHD1C_03 :: DLY_VALUE [06:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_03_DLY_VALUE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x70,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_03_DLY_VALUE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0x70,4)
#define BRPHY1_GPHY_CORE_SHD1C_03_DLY_VALUE_MASK                   0x0070
#define BRPHY1_GPHY_CORE_SHD1C_03_DLY_VALUE_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_03_DLY_VALUE_BITS                   3
#define BRPHY1_GPHY_CORE_SHD1C_03_DLY_VALUE_SHIFT                  4

/* BRPHY1_GPHY_CORE :: SHD1C_03 :: DLY_LINE_SEL [03:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_03,0xf,0)
#define BRPHY1_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_MASK                0x000f
#define BRPHY1_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_BITS                4
#define BRPHY1_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_SHIFT               0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_04
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_04 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_04_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_04_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_04_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_04_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_04 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_04_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_04_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_04_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_04_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_04 :: SPARE_REG [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_04_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_04_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x200,9)
#define BRPHY1_GPHY_CORE_SHD1C_04_SPARE_REG_MASK                   0x0200
#define BRPHY1_GPHY_CORE_SHD1C_04_SPARE_REG_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_04_SPARE_REG_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_04_SPARE_REG_SHIFT                  9

/* BRPHY1_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_DIS [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x100,8)
#define BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_MASK         0x0100
#define BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_BITS         1
#define BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_SHIFT        8

/* BRPHY1_GPHY_CORE :: SHD1C_04 :: SELECT_TPOUT_RXD [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_MASK            0x0080
#define BRPHY1_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_BITS            1
#define BRPHY1_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_SHIFT           7

/* BRPHY1_GPHY_CORE :: SHD1C_04 :: DISABLE_PHYA2 [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x40,6)
#define BRPHY1_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_MASK               0x0040
#define BRPHY1_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_BITS               1
#define BRPHY1_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_SHIFT              6

/* BRPHY1_GPHY_CORE :: SHD1C_04 :: RBC_TXC_RXC_TRI [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x20,5)
#define BRPHY1_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_MASK             0x0020
#define BRPHY1_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_BITS             1
#define BRPHY1_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_SHIFT            5

/* BRPHY1_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_LIMIT [04:02] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x1c,2,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x1c,2)
#define BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_MASK       0x001c
#define BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_ALIGN      0
#define BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_BITS       3
#define BRPHY1_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_SHIFT      2

/* BRPHY1_GPHY_CORE :: SHD1C_04 :: ENG_DET_ON_INTR_PIN [01:01] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x2,1)
#define BRPHY1_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_MASK         0x0002
#define BRPHY1_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_BITS         1
#define BRPHY1_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_SHIFT        1

/* BRPHY1_GPHY_CORE :: SHD1C_04 :: TESTONBYTE7_0 [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_04,0x1,0)
#define BRPHY1_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_MASK               0x0001
#define BRPHY1_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_BITS               1
#define BRPHY1_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_05
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_05 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_05_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_05_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_05_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_05_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_05_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_05_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_05_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_05_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: DLL_LOCK_EN [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x200,9)
#define BRPHY1_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_MASK                 0x0200
#define BRPHY1_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_BITS                 1
#define BRPHY1_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_SHIFT                9

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: TXC_RXC_DIS [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x100,8)
#define BRPHY1_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_MASK                 0x0100
#define BRPHY1_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_BITS                 1
#define BRPHY1_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_SHIFT                8

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: BT_R_REJECT_FILTER [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_MASK          0x0080
#define BRPHY1_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_BITS          1
#define BRPHY1_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_SHIFT         7

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: TXC_OFF_EN [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x40,6)
#define BRPHY1_GPHY_CORE_SHD1C_05_TXC_OFF_EN_MASK                  0x0040
#define BRPHY1_GPHY_CORE_SHD1C_05_TXC_OFF_EN_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD1C_05_TXC_OFF_EN_BITS                  1
#define BRPHY1_GPHY_CORE_SHD1C_05_TXC_OFF_EN_SHIFT                 6

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: SD_CHANGE_MUX_SEL [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x20,5)
#define BRPHY1_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_MASK           0x0020
#define BRPHY1_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_ALIGN          0
#define BRPHY1_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_BITS           1
#define BRPHY1_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_SHIFT          5

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: LOW_POWER_ENC_DIS [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x10,4)
#define BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_MASK           0x0010
#define BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_ALIGN          0
#define BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_BITS           1
#define BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_SHIFT          4

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: LOW_POWER_BT_DIS [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x8,3)
#define BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_MASK            0x0008
#define BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_BITS            1
#define BRPHY1_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_SHIFT           3

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: SD_DEASSERT_TIMER_LEN [02:02] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x4,2)
#define BRPHY1_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_MASK       0x0004
#define BRPHY1_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_ALIGN      0
#define BRPHY1_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_BITS       1
#define BRPHY1_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_SHIFT      2

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: AUTO_PWRDN_DLL_DIS [01:01] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x2,1)
#define BRPHY1_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_MASK          0x0002
#define BRPHY1_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_BITS          1
#define BRPHY1_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_SHIFT         1

/* BRPHY1_GPHY_CORE :: SHD1C_05 :: CLK125_OUTPUT_EN [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_05,0x1,0)
#define BRPHY1_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_MASK            0x0001
#define BRPHY1_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_BITS            1
#define BRPHY1_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_SHIFT           0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_06
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_06 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_06_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_06_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_06_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_06_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_06 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_06_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_06_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_06_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_06_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_06 :: SPARE_REG [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_06_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_06_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x200,9)
#define BRPHY1_GPHY_CORE_SHD1C_06_SPARE_REG_MASK                   0x0200
#define BRPHY1_GPHY_CORE_SHD1C_06_SPARE_REG_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_06_SPARE_REG_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_06_SPARE_REG_SHIFT                  9

/* BRPHY1_GPHY_CORE :: SHD1C_06 :: TDR_LINK_TIME_OUT [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x100,8)
#define BRPHY1_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_MASK           0x0100
#define BRPHY1_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_ALIGN          0
#define BRPHY1_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_BITS           1
#define BRPHY1_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_SHIFT          8

/* BRPHY1_GPHY_CORE :: SHD1C_06 :: TEST_PULSE_SIZE [07:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0xe0,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0xe0,5)
#define BRPHY1_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_MASK             0x00e0
#define BRPHY1_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_BITS             3
#define BRPHY1_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_SHIFT            5

/* BRPHY1_GPHY_CORE :: SHD1C_06 :: TX_CHANNEL_SEL [04:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x18,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x18,3)
#define BRPHY1_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_MASK              0x0018
#define BRPHY1_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_BITS              2
#define BRPHY1_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_SHIFT             3

/* BRPHY1_GPHY_CORE :: SHD1C_06 :: RX_CHANNEL_SEL [02:01] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x6,1,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x6,1)
#define BRPHY1_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_MASK              0x0006
#define BRPHY1_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_BITS              2
#define BRPHY1_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_SHIFT             1

/* BRPHY1_GPHY_CORE :: SHD1C_06 :: TDR_START [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_06_TDR_START(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_06_TDR_START(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_06,0x1,0)
#define BRPHY1_GPHY_CORE_SHD1C_06_TDR_START_MASK                   0x0001
#define BRPHY1_GPHY_CORE_SHD1C_06_TDR_START_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_06_TDR_START_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_06_TDR_START_SHIFT                  0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_07
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_07 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_07_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_07_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_07_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_07_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_07_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_07_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_07_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_07_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: SPARE_REG [09:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x300,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x300,8)
#define BRPHY1_GPHY_CORE_SHD1C_07_SPARE_REG_MASK                   0x0300
#define BRPHY1_GPHY_CORE_SHD1C_07_SPARE_REG_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_07_SPARE_REG_BITS                   2
#define BRPHY1_GPHY_CORE_SHD1C_07_SPARE_REG_SHIFT                  8

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_MASK                0x0080
#define BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_BITS                1
#define BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_SHIFT               7

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS_CLEAR [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x40,6)
#define BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_MASK          0x0040
#define BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_BITS          1
#define BRPHY1_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_SHIFT         6

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: FASTTIMERS [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_FASTTIMERS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_FASTTIMERS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x20,5)
#define BRPHY1_GPHY_CORE_SHD1C_07_FASTTIMERS_MASK                  0x0020
#define BRPHY1_GPHY_CORE_SHD1C_07_FASTTIMERS_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD1C_07_FASTTIMERS_BITS                  1
#define BRPHY1_GPHY_CORE_SHD1C_07_FASTTIMERS_SHIFT                 5

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: FEXT [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_FEXT(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_FEXT(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x10,4)
#define BRPHY1_GPHY_CORE_SHD1C_07_FEXT_MASK                        0x0010
#define BRPHY1_GPHY_CORE_SHD1C_07_FEXT_ALIGN                       0
#define BRPHY1_GPHY_CORE_SHD1C_07_FEXT_BITS                        1
#define BRPHY1_GPHY_CORE_SHD1C_07_FEXT_SHIFT                       4

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: MASTER [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_MASTER(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_MASTER(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x8,3)
#define BRPHY1_GPHY_CORE_SHD1C_07_MASTER_MASK                      0x0008
#define BRPHY1_GPHY_CORE_SHD1C_07_MASTER_ALIGN                     0
#define BRPHY1_GPHY_CORE_SHD1C_07_MASTER_BITS                      1
#define BRPHY1_GPHY_CORE_SHD1C_07_MASTER_SHIFT                     3

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: EXT_PHY_NO_AUTONEG [02:02] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x4,2)
#define BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_MASK          0x0004
#define BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_BITS          1
#define BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_SHIFT         2

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: EXT_PHY [01:01] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x2,1)
#define BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_MASK                     0x0002
#define BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_ALIGN                    0
#define BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_BITS                     1
#define BRPHY1_GPHY_CORE_SHD1C_07_EXT_PHY_SHIFT                    1

/* BRPHY1_GPHY_CORE :: SHD1C_07 :: TDR_EN [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_07_TDR_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_07_TDR_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_07,0x1,0)
#define BRPHY1_GPHY_CORE_SHD1C_07_TDR_EN_MASK                      0x0001
#define BRPHY1_GPHY_CORE_SHD1C_07_TDR_EN_ALIGN                     0
#define BRPHY1_GPHY_CORE_SHD1C_07_TDR_EN_BITS                      1
#define BRPHY1_GPHY_CORE_SHD1C_07_TDR_EN_SHIFT                     0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_08
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_08 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_08_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_08_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_08_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_08_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: reserved1 [09:09] */
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED1_MASK                   0x0200
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED1_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED1_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED1_SHIFT                  9

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: SLAVE_N [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_08_SLAVE_N(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_08_SLAVE_N(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x100,8)
#define BRPHY1_GPHY_CORE_SHD1C_08_SLAVE_N_MASK                     0x0100
#define BRPHY1_GPHY_CORE_SHD1C_08_SLAVE_N_ALIGN                    0
#define BRPHY1_GPHY_CORE_SHD1C_08_SLAVE_N_BITS                     1
#define BRPHY1_GPHY_CORE_SHD1C_08_SLAVE_N_SHIFT                    8

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: FDXLED_N [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_08_FDXLED_N(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_08_FDXLED_N(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_08_FDXLED_N_MASK                    0x0080
#define BRPHY1_GPHY_CORE_SHD1C_08_FDXLED_N_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD1C_08_FDXLED_N_BITS                    1
#define BRPHY1_GPHY_CORE_SHD1C_08_FDXLED_N_SHIFT                   7

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: INTR_N [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_08_INTR_N(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_08_INTR_N(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x40,6)
#define BRPHY1_GPHY_CORE_SHD1C_08_INTR_N_MASK                      0x0040
#define BRPHY1_GPHY_CORE_SHD1C_08_INTR_N_ALIGN                     0
#define BRPHY1_GPHY_CORE_SHD1C_08_INTR_N_BITS                      1
#define BRPHY1_GPHY_CORE_SHD1C_08_INTR_N_SHIFT                     6

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: reserved2 [05:05] */
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED2_MASK                   0x0020
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED2_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED2_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_08_RESERVED2_SHIFT                  5

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: LINKSPD_N [04:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_08_LINKSPD_N(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x18,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_08_LINKSPD_N(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x18,3)
#define BRPHY1_GPHY_CORE_SHD1C_08_LINKSPD_N_MASK                   0x0018
#define BRPHY1_GPHY_CORE_SHD1C_08_LINKSPD_N_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_08_LINKSPD_N_BITS                   2
#define BRPHY1_GPHY_CORE_SHD1C_08_LINKSPD_N_SHIFT                  3

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: TRANSMIT_LED [02:02] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x4,2)
#define BRPHY1_GPHY_CORE_SHD1C_08_TRANSMIT_LED_MASK                0x0004
#define BRPHY1_GPHY_CORE_SHD1C_08_TRANSMIT_LED_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD1C_08_TRANSMIT_LED_BITS                1
#define BRPHY1_GPHY_CORE_SHD1C_08_TRANSMIT_LED_SHIFT               2

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: RECEIVE_LED [01:01] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x2,1)
#define BRPHY1_GPHY_CORE_SHD1C_08_RECEIVE_LED_MASK                 0x0002
#define BRPHY1_GPHY_CORE_SHD1C_08_RECEIVE_LED_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD1C_08_RECEIVE_LED_BITS                 1
#define BRPHY1_GPHY_CORE_SHD1C_08_RECEIVE_LED_SHIFT                1

/* BRPHY1_GPHY_CORE :: SHD1C_08 :: QUALITY_LED [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_08_QUALITY_LED(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_08_QUALITY_LED(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_08,0x1,0)
#define BRPHY1_GPHY_CORE_SHD1C_08_QUALITY_LED_MASK                 0x0001
#define BRPHY1_GPHY_CORE_SHD1C_08_QUALITY_LED_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD1C_08_QUALITY_LED_BITS                 1
#define BRPHY1_GPHY_CORE_SHD1C_08_QUALITY_LED_SHIFT                0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_09
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_09 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_09_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_09_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_09_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_09_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_09_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_09_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_09_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_09_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: COL_BLINK [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_COL_BLINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_COL_BLINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x200,9)
#define BRPHY1_GPHY_CORE_SHD1C_09_COL_BLINK_MASK                   0x0200
#define BRPHY1_GPHY_CORE_SHD1C_09_COL_BLINK_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_09_COL_BLINK_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_09_COL_BLINK_SHIFT                  9

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: ACT_LINK_MSB [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x100,8)
#define BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_MASK                0x0100
#define BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_BITS                1
#define BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_SHIFT               8

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: SPARE_REG [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_09_SPARE_REG_MASK                   0x0080
#define BRPHY1_GPHY_CORE_SHD1C_09_SPARE_REG_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_09_SPARE_REG_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_09_SPARE_REG_SHIFT                  7

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: EXT_SERDES_INUSE [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x40,6)
#define BRPHY1_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_MASK            0x0040
#define BRPHY1_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_BITS            1
#define BRPHY1_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_SHIFT           6

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: OV_GBIC_LED [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x20,5)
#define BRPHY1_GPHY_CORE_SHD1C_09_OV_GBIC_LED_MASK                 0x0020
#define BRPHY1_GPHY_CORE_SHD1C_09_OV_GBIC_LED_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD1C_09_OV_GBIC_LED_BITS                 1
#define BRPHY1_GPHY_CORE_SHD1C_09_OV_GBIC_LED_SHIFT                5

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: ACT_LINK_LSB [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x10,4)
#define BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_MASK                0x0010
#define BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_BITS                1
#define BRPHY1_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_SHIFT               4

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: ACTIVITY_LED_EN [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x8,3)
#define BRPHY1_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_MASK             0x0008
#define BRPHY1_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_BITS             1
#define BRPHY1_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_SHIFT            3

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: RMT_FAULT_LED_EN [02:02] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x4,2)
#define BRPHY1_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_MASK            0x0004
#define BRPHY1_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_BITS            1
#define BRPHY1_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_SHIFT           2

/* BRPHY1_GPHY_CORE :: SHD1C_09 :: LINK_UTIL_LED_SEL [01:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x3,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_09,0x3,0)
#define BRPHY1_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_MASK           0x0003
#define BRPHY1_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_ALIGN          0
#define BRPHY1_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_BITS           2
#define BRPHY1_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_SHIFT          0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_0A
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_0A :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_0A_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_0A_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0A_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_0A_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_0A :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_0A_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_0A_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0A_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_0A_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_0A :: reserved1 [09:09] */
#define BRPHY1_GPHY_CORE_SHD1C_0A_RESERVED1_MASK                   0x0200
#define BRPHY1_GPHY_CORE_SHD1C_0A_RESERVED1_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0A_RESERVED1_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_0A_RESERVED1_SHIFT                  9

/* BRPHY1_GPHY_CORE :: SHD1C_0A :: APD_SINGLELP_ENABLE [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x100,8)
#define BRPHY1_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_MASK         0x0100
#define BRPHY1_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_BITS         1
#define BRPHY1_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_SHIFT        8

/* BRPHY1_GPHY_CORE :: SHD1C_0A :: LOWPWR136_ENC_EN [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_MASK            0x0080
#define BRPHY1_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_BITS            1
#define BRPHY1_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_SHIFT           7

/* BRPHY1_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_IGNORE_AUTONEG [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x40,6)
#define BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_MASK   0x0040
#define BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_ALIGN  0
#define BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_BITS   1
#define BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_SHIFT  6

/* BRPHY1_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_EN [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x20,5)
#define BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_MASK               0x0020
#define BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_BITS               1
#define BRPHY1_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_SHIFT              5

/* BRPHY1_GPHY_CORE :: SHD1C_0A :: SLEEP_TIMER_SEL [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0x10,4)
#define BRPHY1_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_MASK             0x0010
#define BRPHY1_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_BITS             1
#define BRPHY1_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_SHIFT            4

/* BRPHY1_GPHY_CORE :: SHD1C_0A :: WAKE_UP_TIMER_SEL [03:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0A,0xf,0)
#define BRPHY1_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_MASK           0x000f
#define BRPHY1_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_ALIGN          0
#define BRPHY1_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_BITS           4
#define BRPHY1_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_SHIFT          0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_0B
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_0B :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_0B_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_0B_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0B_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_0B_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_0B :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0B,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0B,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_0B_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_0B_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0B_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_0B_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_0B :: reserved1 [09:08] */
#define BRPHY1_GPHY_CORE_SHD1C_0B_RESERVED1_MASK                   0x0300
#define BRPHY1_GPHY_CORE_SHD1C_0B_RESERVED1_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0B_RESERVED1_BITS                   2
#define BRPHY1_GPHY_CORE_SHD1C_0B_RESERVED1_SHIFT                  8

/* BRPHY1_GPHY_CORE :: SHD1C_0B :: SPARE_CTL4 [07:01] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0B,0xfe,1,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0B,0xfe,1)
#define BRPHY1_GPHY_CORE_SHD1C_0B_SPARE_CTL4_MASK                  0x00fe
#define BRPHY1_GPHY_CORE_SHD1C_0B_SPARE_CTL4_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD1C_0B_SPARE_CTL4_BITS                  7
#define BRPHY1_GPHY_CORE_SHD1C_0B_SPARE_CTL4_SHIFT                 1

/* BRPHY1_GPHY_CORE :: SHD1C_0B :: dis_cl45 [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0B_dis_cl45(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0B,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0B_dis_cl45(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0B,0x1,0)
#define BRPHY1_GPHY_CORE_SHD1C_0B_DIS_CL45_MASK                    0x0001
#define BRPHY1_GPHY_CORE_SHD1C_0B_DIS_CL45_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD1C_0B_DIS_CL45_BITS                    1
#define BRPHY1_GPHY_CORE_SHD1C_0B_DIS_CL45_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_0D
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_0D :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_0D_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_0D_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0D_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_0D_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_0D :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0D,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0D,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_0D_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_0D_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0D_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_0D_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_0D :: reserved1 [09:08] */
#define BRPHY1_GPHY_CORE_SHD1C_0D_RESERVED1_MASK                   0x0300
#define BRPHY1_GPHY_CORE_SHD1C_0D_RESERVED1_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0D_RESERVED1_BITS                   2
#define BRPHY1_GPHY_CORE_SHD1C_0D_RESERVED1_SHIFT                  8

/* BRPHY1_GPHY_CORE :: SHD1C_0D :: LED2_SEL [07:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0D_LED2_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0D,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0D_LED2_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0D,0xf0,4)
#define BRPHY1_GPHY_CORE_SHD1C_0D_LED2_SEL_MASK                    0x00f0
#define BRPHY1_GPHY_CORE_SHD1C_0D_LED2_SEL_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD1C_0D_LED2_SEL_BITS                    4
#define BRPHY1_GPHY_CORE_SHD1C_0D_LED2_SEL_SHIFT                   4

/* BRPHY1_GPHY_CORE :: SHD1C_0D :: LED1_SEL [03:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0D_LED1_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0D,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0D_LED1_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0D,0xf,0)
#define BRPHY1_GPHY_CORE_SHD1C_0D_LED1_SEL_MASK                    0x000f
#define BRPHY1_GPHY_CORE_SHD1C_0D_LED1_SEL_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD1C_0D_LED1_SEL_BITS                    4
#define BRPHY1_GPHY_CORE_SHD1C_0D_LED1_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_0E
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_0E :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_0E_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_0E_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0E_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_0E_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_0E :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0E,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0E,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_0E_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_0E_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0E_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_0E_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_0E :: reserved1 [09:08] */
#define BRPHY1_GPHY_CORE_SHD1C_0E_RESERVED1_MASK                   0x0300
#define BRPHY1_GPHY_CORE_SHD1C_0E_RESERVED1_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0E_RESERVED1_BITS                   2
#define BRPHY1_GPHY_CORE_SHD1C_0E_RESERVED1_SHIFT                  8

/* BRPHY1_GPHY_CORE :: SHD1C_0E :: LED4_SEL [07:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0E_LED4_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0E,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0E_LED4_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0E,0xf0,4)
#define BRPHY1_GPHY_CORE_SHD1C_0E_LED4_SEL_MASK                    0x00f0
#define BRPHY1_GPHY_CORE_SHD1C_0E_LED4_SEL_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD1C_0E_LED4_SEL_BITS                    4
#define BRPHY1_GPHY_CORE_SHD1C_0E_LED4_SEL_SHIFT                   4

/* BRPHY1_GPHY_CORE :: SHD1C_0E :: LED3_SEL [03:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0E_LED3_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0E,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0E_LED3_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0E,0xf,0)
#define BRPHY1_GPHY_CORE_SHD1C_0E_LED3_SEL_MASK                    0x000f
#define BRPHY1_GPHY_CORE_SHD1C_0E_LED3_SEL_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD1C_0E_LED3_SEL_BITS                    4
#define BRPHY1_GPHY_CORE_SHD1C_0E_LED3_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_0F
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_0F :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_0F_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_0F_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0F_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_0F_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_0F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0F,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0F,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_0F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_0F_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0F_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_0F_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_0F :: reserved1 [09:04] */
#define BRPHY1_GPHY_CORE_SHD1C_0F_RESERVED1_MASK                   0x03f0
#define BRPHY1_GPHY_CORE_SHD1C_0F_RESERVED1_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_0F_RESERVED1_BITS                   6
#define BRPHY1_GPHY_CORE_SHD1C_0F_RESERVED1_SHIFT                  4

/* BRPHY1_GPHY_CORE :: SHD1C_0F :: CURRENT_MODE_LED_EN [03:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_0F,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_0F,0xf,0)
#define BRPHY1_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_MASK         0x000f
#define BRPHY1_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_BITS         4
#define BRPHY1_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_SHIFT        0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_10
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_10 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_10_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_10_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_10_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_10_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_10 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_10_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_10_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_10_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_10_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_10 :: reserved1 [09:08] */
#define BRPHY1_GPHY_CORE_SHD1C_10_RESERVED1_MASK                   0x0300
#define BRPHY1_GPHY_CORE_SHD1C_10_RESERVED1_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_10_RESERVED1_BITS                   2
#define BRPHY1_GPHY_CORE_SHD1C_10_RESERVED1_SHIFT                  8

/* BRPHY1_GPHY_CORE :: SHD1C_10 :: SPARE_REG [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_10_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_10_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_10_SPARE_REG_MASK                   0x0080
#define BRPHY1_GPHY_CORE_SHD1C_10_SPARE_REG_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_10_SPARE_REG_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_10_SPARE_REG_SHIFT                  7

/* BRPHY1_GPHY_CORE :: SHD1C_10 :: USE_ALT_LINKFLT [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x40,6)
#define BRPHY1_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_MASK             0x0040
#define BRPHY1_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_BITS             1
#define BRPHY1_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_SHIFT            6

/* BRPHY1_GPHY_CORE :: SHD1C_10 :: VISIBLE_BLINK [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x20,5)
#define BRPHY1_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_MASK               0x0020
#define BRPHY1_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_BITS               1
#define BRPHY1_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_SHIFT              5

/* BRPHY1_GPHY_CORE :: SHD1C_10 :: ENHANCED_PWR [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0x10,4)
#define BRPHY1_GPHY_CORE_SHD1C_10_ENHANCED_PWR_MASK                0x0010
#define BRPHY1_GPHY_CORE_SHD1C_10_ENHANCED_PWR_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD1C_10_ENHANCED_PWR_BITS                1
#define BRPHY1_GPHY_CORE_SHD1C_10_ENHANCED_PWR_SHIFT               4

/* BRPHY1_GPHY_CORE :: SHD1C_10 :: DISCONNECT_TIMER_VALUE [03:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_10,0xf,0)
#define BRPHY1_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_MASK      0x000f
#define BRPHY1_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_ALIGN     0
#define BRPHY1_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_BITS      4
#define BRPHY1_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_SHIFT     0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD1C_1F
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD1C_1F :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD1C_1F_RESERVED0_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD1C_1F_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_1F_RESERVED0_BITS                   1
#define BRPHY1_GPHY_CORE_SHD1C_1F_RESERVED0_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD1C_1F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY1_GPHY_CORE_SHD1C_1F_SHD1C_SEL_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD1C_1F_SHD1C_SEL_BITS                   5
#define BRPHY1_GPHY_CORE_SHD1C_1F_SHD1C_SEL_SHIFT                  10

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: DUAL_SERDES_CAPABLE [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x200,9)
#define BRPHY1_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_MASK         0x0200
#define BRPHY1_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_BITS         1
#define BRPHY1_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_SHIFT        9

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: MODE_SEL_CHANGE [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x100,8)
#define BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_MASK             0x0100
#define BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_BITS             1
#define BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_SHIFT            8

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: COPPER_LINK [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x80,7)
#define BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_LINK_MASK                 0x0080
#define BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_LINK_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_LINK_BITS                 1
#define BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_LINK_SHIFT                7

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: SERDES_LINK [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x40,6)
#define BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_LINK_MASK                 0x0040
#define BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_LINK_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_LINK_BITS                 1
#define BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_LINK_SHIFT                6

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: COPPER_ENG_DET [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x20,5)
#define BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_MASK              0x0020
#define BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_BITS              1
#define BRPHY1_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_SHIFT             5

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: FIBER_SIGNAL_DET [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x10,4)
#define BRPHY1_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_MASK            0x0010
#define BRPHY1_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_BITS            1
#define BRPHY1_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_SHIFT           4

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: SERDES_CAPABLE [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x8,3)
#define BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_MASK              0x0008
#define BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_BITS              1
#define BRPHY1_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_SHIFT             3

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: MODE_SEL [02:01] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x6,1,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x6,1)
#define BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_MASK                    0x0006
#define BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_BITS                    2
#define BRPHY1_GPHY_CORE_SHD1C_1F_MODE_SEL_SHIFT                   1

/* BRPHY1_GPHY_CORE :: SHD1C_1F :: REG_1000X_EN [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD1C_1F,0x1,0)
#define BRPHY1_GPHY_CORE_SHD1C_1F_REG_1000X_EN_MASK                0x0001
#define BRPHY1_GPHY_CORE_SHD1C_1F_REG_1000X_EN_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD1C_1F_REG_1000X_EN_BITS                1
#define BRPHY1_GPHY_CORE_SHD1C_1F_REG_1000X_EN_SHIFT               0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD18_000
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD18_000 :: EXT_LPBK [15:15] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_EXT_LPBK(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_EXT_LPBK(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x8000,15)
#define BRPHY1_GPHY_CORE_SHD18_000_EXT_LPBK_MASK                   0x8000
#define BRPHY1_GPHY_CORE_SHD18_000_EXT_LPBK_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD18_000_EXT_LPBK_BITS                   1
#define BRPHY1_GPHY_CORE_SHD18_000_EXT_LPBK_SHIFT                  15

/* BRPHY1_GPHY_CORE :: SHD18_000 :: EXT_PKT_LEN [14:14] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x4000,14)
#define BRPHY1_GPHY_CORE_SHD18_000_EXT_PKT_LEN_MASK                0x4000
#define BRPHY1_GPHY_CORE_SHD18_000_EXT_PKT_LEN_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_000_EXT_PKT_LEN_BITS                1
#define BRPHY1_GPHY_CORE_SHD18_000_EXT_PKT_LEN_SHIFT               14

/* BRPHY1_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_1000T [13:12] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x3000,12,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x3000,12)
#define BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_MASK         0x3000
#define BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_BITS         2
#define BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_SHIFT        12

/* BRPHY1_GPHY_CORE :: SHD18_000 :: SM_DSP_CLK_EN [11:11] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x800,11)
#define BRPHY1_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_MASK              0x0800
#define BRPHY1_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_BITS              1
#define BRPHY1_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_SHIFT             11

/* BRPHY1_GPHY_CORE :: SHD18_000 :: TX_6DB_CODING [10:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x400,10)
#define BRPHY1_GPHY_CORE_SHD18_000_TX_6DB_CODING_MASK              0x0400
#define BRPHY1_GPHY_CORE_SHD18_000_TX_6DB_CODING_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD18_000_TX_6DB_CODING_BITS              1
#define BRPHY1_GPHY_CORE_SHD18_000_TX_6DB_CODING_SHIFT             10

/* BRPHY1_GPHY_CORE :: SHD18_000 :: RCV_SLICING [09:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_RCV_SLICING(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x300,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_RCV_SLICING(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x300,8)
#define BRPHY1_GPHY_CORE_SHD18_000_RCV_SLICING_MASK                0x0300
#define BRPHY1_GPHY_CORE_SHD18_000_RCV_SLICING_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_000_RCV_SLICING_BITS                2
#define BRPHY1_GPHY_CORE_SHD18_000_RCV_SLICING_SHIFT               8

/* BRPHY1_GPHY_CORE :: SHD18_000 :: PRF_DIS [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_PRF_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_PRF_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x80,7)
#define BRPHY1_GPHY_CORE_SHD18_000_PRF_DIS_MASK                    0x0080
#define BRPHY1_GPHY_CORE_SHD18_000_PRF_DIS_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD18_000_PRF_DIS_BITS                    1
#define BRPHY1_GPHY_CORE_SHD18_000_PRF_DIS_SHIFT                   7

/* BRPHY1_GPHY_CORE :: SHD18_000 :: INVERSE_PRF_DIS [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x40,6)
#define BRPHY1_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_MASK            0x0040
#define BRPHY1_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_SHIFT           6

/* BRPHY1_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_100TX [05:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x30,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x30,4)
#define BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_MASK         0x0030
#define BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_BITS         2
#define BRPHY1_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_SHIFT        4

/* BRPHY1_GPHY_CORE :: SHD18_000 :: DIAGNOSTIC [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x8,3)
#define BRPHY1_GPHY_CORE_SHD18_000_DIAGNOSTIC_MASK                 0x0008
#define BRPHY1_GPHY_CORE_SHD18_000_DIAGNOSTIC_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD18_000_DIAGNOSTIC_BITS                 1
#define BRPHY1_GPHY_CORE_SHD18_000_DIAGNOSTIC_SHIFT                3

/* BRPHY1_GPHY_CORE :: SHD18_000 :: SHD18_SEL [02:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_000_SHD18_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_000_SHD18_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_000,0x7,0)
#define BRPHY1_GPHY_CORE_SHD18_000_SHD18_SEL_MASK                  0x0007
#define BRPHY1_GPHY_CORE_SHD18_000_SHD18_SEL_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_000_SHD18_SEL_BITS                  3
#define BRPHY1_GPHY_CORE_SHD18_000_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD18_001
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD18_001 :: MANCHESTER_CODE_ERR [15:15] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x8000,15)
#define BRPHY1_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_MASK        0x8000
#define BRPHY1_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_ALIGN       0
#define BRPHY1_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_BITS        1
#define BRPHY1_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_SHIFT       15

/* BRPHY1_GPHY_CORE :: SHD18_001 :: EOF_ERR [14:14] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_EOF_ERR(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_EOF_ERR(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x4000,14)
#define BRPHY1_GPHY_CORE_SHD18_001_EOF_ERR_MASK                    0x4000
#define BRPHY1_GPHY_CORE_SHD18_001_EOF_ERR_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD18_001_EOF_ERR_BITS                    1
#define BRPHY1_GPHY_CORE_SHD18_001_EOF_ERR_SHIFT                   14

/* BRPHY1_GPHY_CORE :: SHD18_001 :: POLARITY_ERR [13:13] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_POLARITY_ERR(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_POLARITY_ERR(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x2000,13)
#define BRPHY1_GPHY_CORE_SHD18_001_POLARITY_ERR_MASK               0x2000
#define BRPHY1_GPHY_CORE_SHD18_001_POLARITY_ERR_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD18_001_POLARITY_ERR_BITS               1
#define BRPHY1_GPHY_CORE_SHD18_001_POLARITY_ERR_SHIFT              13

/* BRPHY1_GPHY_CORE :: SHD18_001 :: BLOCK_RXDV_EXT [12:12] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x1000,12)
#define BRPHY1_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_MASK             0x1000
#define BRPHY1_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_BITS             1
#define BRPHY1_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_SHIFT            12

/* BRPHY1_GPHY_CORE :: SHD18_001 :: BT_TXC_INV [11:11] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_BT_TXC_INV(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_BT_TXC_INV(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x800,11)
#define BRPHY1_GPHY_CORE_SHD18_001_BT_TXC_INV_MASK                 0x0800
#define BRPHY1_GPHY_CORE_SHD18_001_BT_TXC_INV_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD18_001_BT_TXC_INV_BITS                 1
#define BRPHY1_GPHY_CORE_SHD18_001_BT_TXC_INV_SHIFT                11

/* BRPHY1_GPHY_CORE :: SHD18_001 :: CLASS_AB_DRIVER_SEL [10:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x400,10)
#define BRPHY1_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_MASK        0x0400
#define BRPHY1_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_ALIGN       0
#define BRPHY1_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_BITS        1
#define BRPHY1_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_SHIFT       10

/* BRPHY1_GPHY_CORE :: SHD18_001 :: JABBER_DIS [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_JABBER_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_JABBER_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x200,9)
#define BRPHY1_GPHY_CORE_SHD18_001_JABBER_DIS_MASK                 0x0200
#define BRPHY1_GPHY_CORE_SHD18_001_JABBER_DIS_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD18_001_JABBER_DIS_BITS                 1
#define BRPHY1_GPHY_CORE_SHD18_001_JABBER_DIS_SHIFT                9

/* BRPHY1_GPHY_CORE :: SHD18_001 :: BT_SIG_DET_AUTOSWITCH [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x100,8)
#define BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_MASK      0x0100
#define BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_ALIGN     0
#define BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_BITS      1
#define BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_SHIFT     8

/* BRPHY1_GPHY_CORE :: SHD18_001 :: BT_SIG_DETECT_THD [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x80,7)
#define BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_MASK          0x0080
#define BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_BITS          1
#define BRPHY1_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_SHIFT         7

/* BRPHY1_GPHY_CORE :: SHD18_001 :: BT_ECHO [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_BT_ECHO(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_BT_ECHO(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x40,6)
#define BRPHY1_GPHY_CORE_SHD18_001_BT_ECHO_MASK                    0x0040
#define BRPHY1_GPHY_CORE_SHD18_001_BT_ECHO_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD18_001_BT_ECHO_BITS                    1
#define BRPHY1_GPHY_CORE_SHD18_001_BT_ECHO_SHIFT                   6

/* BRPHY1_GPHY_CORE :: SHD18_001 :: SQE_EN [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_SQE_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_SQE_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x20,5)
#define BRPHY1_GPHY_CORE_SHD18_001_SQE_EN_MASK                     0x0020
#define BRPHY1_GPHY_CORE_SHD18_001_SQE_EN_ALIGN                    0
#define BRPHY1_GPHY_CORE_SHD18_001_SQE_EN_BITS                     1
#define BRPHY1_GPHY_CORE_SHD18_001_SQE_EN_SHIFT                    5

/* BRPHY1_GPHY_CORE :: SHD18_001 :: BT_NO_DRIBBLE [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x10,4)
#define BRPHY1_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_MASK              0x0010
#define BRPHY1_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_BITS              1
#define BRPHY1_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_SHIFT             4

/* BRPHY1_GPHY_CORE :: SHD18_001 :: BT_POL_ERR_CNT_MAX [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x8,3)
#define BRPHY1_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_MASK         0x0008
#define BRPHY1_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_BITS         1
#define BRPHY1_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_SHIFT        3

/* BRPHY1_GPHY_CORE :: SHD18_001 :: SHD18_SEL [02:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_001_SHD18_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_001_SHD18_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_001,0x7,0)
#define BRPHY1_GPHY_CORE_SHD18_001_SHD18_SEL_MASK                  0x0007
#define BRPHY1_GPHY_CORE_SHD18_001_SHD18_SEL_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_001_SHD18_SEL_BITS                  3
#define BRPHY1_GPHY_CORE_SHD18_001_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD18_010
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD18_010 :: SPARE_REG_3 [15:11] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_3(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0xf800,11,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_3(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0xf800,11)
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_3_MASK                0xf800
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_3_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_3_BITS                5
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_3_SHIFT               11

/* BRPHY1_GPHY_CORE :: SHD18_010 :: SPARE_REG_2 [10:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_2(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x7c0,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_2(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x7c0,6)
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_2_MASK                0x07c0
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_2_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_2_BITS                5
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_2_SHIFT               6

/* BRPHY1_GPHY_CORE :: SHD18_010 :: SUPER_ISOLATE [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x20,5)
#define BRPHY1_GPHY_CORE_SHD18_010_SUPER_ISOLATE_MASK              0x0020
#define BRPHY1_GPHY_CORE_SHD18_010_SUPER_ISOLATE_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD18_010_SUPER_ISOLATE_BITS              1
#define BRPHY1_GPHY_CORE_SHD18_010_SUPER_ISOLATE_SHIFT             5

/* BRPHY1_GPHY_CORE :: SHD18_010 :: SPARE_REG_1 [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_1(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_1(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x10,4)
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_1_MASK                0x0010
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_1_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_1_BITS                1
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_1_SHIFT               4

/* BRPHY1_GPHY_CORE :: SHD18_010 :: SPARE_REG_0 [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_0(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_0(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x8,3)
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_0_MASK                0x0008
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_0_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_0_BITS                1
#define BRPHY1_GPHY_CORE_SHD18_010_SPARE_REG_0_SHIFT               3

/* BRPHY1_GPHY_CORE :: SHD18_010 :: SHD18_SEL [02:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_010_SHD18_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_010_SHD18_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_010,0x7,0)
#define BRPHY1_GPHY_CORE_SHD18_010_SHD18_SEL_MASK                  0x0007
#define BRPHY1_GPHY_CORE_SHD18_010_SHD18_SEL_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_010_SHD18_SEL_BITS                  3
#define BRPHY1_GPHY_CORE_SHD18_010_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD18_011
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD18_011 :: IP_PHONE_DETECT [15:15] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x8000,15)
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_MASK            0x8000
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_SHIFT           15

/* BRPHY1_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_CNTR [14:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x7c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x7c00,10)
#define BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_MASK          0x7c00
#define BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_BITS          5
#define BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_SHIFT         10

/* BRPHY1_GPHY_CORE :: SHD18_011 :: ALT_RANDOM_SEED [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x200,9)
#define BRPHY1_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_MASK            0x0200
#define BRPHY1_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_SHIFT           9

/* BRPHY1_GPHY_CORE :: SHD18_011 :: RESTART_AUTONEG [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x100,8)
#define BRPHY1_GPHY_CORE_SHD18_011_RESTART_AUTONEG_MASK            0x0100
#define BRPHY1_GPHY_CORE_SHD18_011_RESTART_AUTONEG_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_011_RESTART_AUTONEG_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_011_RESTART_AUTONEG_SHIFT           8

/* BRPHY1_GPHY_CORE :: SHD18_011 :: IP_PHONE_WINDOW [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x80,7)
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_MASK            0x0080
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_SHIFT           7

/* BRPHY1_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_EN [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x40,6)
#define BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_MASK            0x0040
#define BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_SHIFT           6

/* BRPHY1_GPHY_CORE :: SHD18_011 :: IP_PHONE_DET_EN [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x20,5)
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_MASK            0x0020
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_SHIFT           5

/* BRPHY1_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_DIS [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x10,4)
#define BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_MASK      0x0010
#define BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_ALIGN     0
#define BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_BITS      1
#define BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_SHIFT     4

/* BRPHY1_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_SW [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x8,3)
#define BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_MASK       0x0008
#define BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_ALIGN      0
#define BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_BITS       1
#define BRPHY1_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_SHIFT      3

/* BRPHY1_GPHY_CORE :: SHD18_011 :: SHD18_SEL [02:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_011_SHD18_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_011_SHD18_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_011,0x7,0)
#define BRPHY1_GPHY_CORE_SHD18_011_SHD18_SEL_MASK                  0x0007
#define BRPHY1_GPHY_CORE_SHD18_011_SHD18_SEL_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_011_SHD18_SEL_BITS                  3
#define BRPHY1_GPHY_CORE_SHD18_011_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD18_100
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD18_100 :: RMT_LPBK_EN [15:15] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x8000,15)
#define BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_EN_MASK                0x8000
#define BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_EN_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_EN_BITS                1
#define BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_EN_SHIFT               15

/* BRPHY1_GPHY_CORE :: SHD18_100 :: TDK_FIX_EN [14:14] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x4000,14)
#define BRPHY1_GPHY_CORE_SHD18_100_TDK_FIX_EN_MASK                 0x4000
#define BRPHY1_GPHY_CORE_SHD18_100_TDK_FIX_EN_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD18_100_TDK_FIX_EN_BITS                 1
#define BRPHY1_GPHY_CORE_SHD18_100_TDK_FIX_EN_SHIFT                14

/* BRPHY1_GPHY_CORE :: SHD18_100 :: BT_DLL_BYPASS_CLK [13:13] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x2000,13)
#define BRPHY1_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_MASK          0x2000
#define BRPHY1_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_BITS          1
#define BRPHY1_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_SHIFT         13

/* BRPHY1_GPHY_CORE :: SHD18_100 :: BLOCK_10BT_RESTART_AUTONEG [12:12] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x1000,12)
#define BRPHY1_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_MASK 0x1000
#define BRPHY1_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_ALIGN 0
#define BRPHY1_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_BITS 1
#define BRPHY1_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_SHIFT 12

/* BRPHY1_GPHY_CORE :: SHD18_100 :: RMT_LPBK_TRISTATE [11:11] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x800,11)
#define BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_MASK          0x0800
#define BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_BITS          1
#define BRPHY1_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_SHIFT         11

/* BRPHY1_GPHY_CORE :: SHD18_100 :: BT_WAKEUP [10:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_BT_WAKEUP(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_BT_WAKEUP(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x400,10)
#define BRPHY1_GPHY_CORE_SHD18_100_BT_WAKEUP_MASK                  0x0400
#define BRPHY1_GPHY_CORE_SHD18_100_BT_WAKEUP_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_100_BT_WAKEUP_BITS                  1
#define BRPHY1_GPHY_CORE_SHD18_100_BT_WAKEUP_SHIFT                 10

/* BRPHY1_GPHY_CORE :: SHD18_100 :: BT_POLARITY_BYPASS [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x200,9)
#define BRPHY1_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_MASK         0x0200
#define BRPHY1_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_ALIGN        0
#define BRPHY1_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_BITS         1
#define BRPHY1_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_SHIFT        9

/* BRPHY1_GPHY_CORE :: SHD18_100 :: BT_IDLE_BYPASS [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x100,8)
#define BRPHY1_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_MASK             0x0100
#define BRPHY1_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_BITS             1
#define BRPHY1_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_SHIFT            8

/* BRPHY1_GPHY_CORE :: SHD18_100 :: BT_CLK_RESET_EN [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x80,7)
#define BRPHY1_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_MASK            0x0080
#define BRPHY1_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_SHIFT           7

/* BRPHY1_GPHY_CORE :: SHD18_100 :: BT_BYPASS_ADC [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x40,6)
#define BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_MASK              0x0040
#define BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_BITS              1
#define BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_SHIFT             6

/* BRPHY1_GPHY_CORE :: SHD18_100 :: BT_BYPASS_CRS [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x20,5)
#define BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_MASK              0x0020
#define BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_BITS              1
#define BRPHY1_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_SHIFT             5

/* BRPHY1_GPHY_CORE :: SHD18_100 :: SWAP_RXMDIX [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x10,4)
#define BRPHY1_GPHY_CORE_SHD18_100_SWAP_RXMDIX_MASK                0x0010
#define BRPHY1_GPHY_CORE_SHD18_100_SWAP_RXMDIX_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_100_SWAP_RXMDIX_BITS                1
#define BRPHY1_GPHY_CORE_SHD18_100_SWAP_RXMDIX_SHIFT               4

/* BRPHY1_GPHY_CORE :: SHD18_100 :: HALFOUT [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_HALFOUT(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_HALFOUT(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x8,3)
#define BRPHY1_GPHY_CORE_SHD18_100_HALFOUT_MASK                    0x0008
#define BRPHY1_GPHY_CORE_SHD18_100_HALFOUT_ALIGN                   0
#define BRPHY1_GPHY_CORE_SHD18_100_HALFOUT_BITS                    1
#define BRPHY1_GPHY_CORE_SHD18_100_HALFOUT_SHIFT                   3

/* BRPHY1_GPHY_CORE :: SHD18_100 :: SHD18_SEL [02:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_100_SHD18_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_100_SHD18_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_100,0x7,0)
#define BRPHY1_GPHY_CORE_SHD18_100_SHD18_SEL_MASK                  0x0007
#define BRPHY1_GPHY_CORE_SHD18_100_SHD18_SEL_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_100_SHD18_SEL_BITS                  3
#define BRPHY1_GPHY_CORE_SHD18_100_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD18_101
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD18_101 :: COPPER_ENG_DET_OV [15:15] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x8000,15)
#define BRPHY1_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_MASK          0x8000
#define BRPHY1_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_BITS          1
#define BRPHY1_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_SHIFT         15

/* BRPHY1_GPHY_CORE :: SHD18_101 :: ADCFIFO_TX_FIX [14:14] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x4000,14)
#define BRPHY1_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_MASK             0x4000
#define BRPHY1_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_ALIGN            0
#define BRPHY1_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_BITS             1
#define BRPHY1_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_SHIFT            14

/* BRPHY1_GPHY_CORE :: SHD18_101 :: CLASS_AB_DVT_EN [13:13] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x2000,13)
#define BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_MASK            0x2000
#define BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_SHIFT           13

/* BRPHY1_GPHY_CORE :: SHD18_101 :: CLASS_AB_EN [12:12] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x1000,12)
#define BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_EN_MASK                0x1000
#define BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_EN_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_EN_BITS                1
#define BRPHY1_GPHY_CORE_SHD18_101_CLASS_AB_EN_SHIFT               12

/* BRPHY1_GPHY_CORE :: SHD18_101 :: ENC_ERR_SCALE [11:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0xc00,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0xc00,10)
#define BRPHY1_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_MASK              0x0c00
#define BRPHY1_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_ALIGN             0
#define BRPHY1_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_BITS              2
#define BRPHY1_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_SHIFT             10

/* BRPHY1_GPHY_CORE :: SHD18_101 :: SPARE_REG [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x200,9)
#define BRPHY1_GPHY_CORE_SHD18_101_SPARE_REG_MASK                  0x0200
#define BRPHY1_GPHY_CORE_SHD18_101_SPARE_REG_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_101_SPARE_REG_BITS                  1
#define BRPHY1_GPHY_CORE_SHD18_101_SPARE_REG_SHIFT                 9

/* BRPHY1_GPHY_CORE :: SHD18_101 :: AUTO_ENCODING_CORRECTION [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x100,8)
#define BRPHY1_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_MASK   0x0100
#define BRPHY1_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_ALIGN  0
#define BRPHY1_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_BITS   1
#define BRPHY1_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_SHIFT  8

/* BRPHY1_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_RX [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x80,7)
#define BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_MASK        0x0080
#define BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_ALIGN       0
#define BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_BITS        1
#define BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_SHIFT       7

/* BRPHY1_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_TX [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x40,6)
#define BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_MASK        0x0040
#define BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_ALIGN       0
#define BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_BITS        1
#define BRPHY1_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_SHIFT       6

/* BRPHY1_GPHY_CORE :: SHD18_101 :: EC_AS_NEXT [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x20,5)
#define BRPHY1_GPHY_CORE_SHD18_101_EC_AS_NEXT_MASK                 0x0020
#define BRPHY1_GPHY_CORE_SHD18_101_EC_AS_NEXT_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD18_101_EC_AS_NEXT_BITS                 1
#define BRPHY1_GPHY_CORE_SHD18_101_EC_AS_NEXT_SHIFT                5

/* BRPHY1_GPHY_CORE :: SHD18_101 :: FORCE_MDIX [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_FORCE_MDIX(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_FORCE_MDIX(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x10,4)
#define BRPHY1_GPHY_CORE_SHD18_101_FORCE_MDIX_MASK                 0x0010
#define BRPHY1_GPHY_CORE_SHD18_101_FORCE_MDIX_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD18_101_FORCE_MDIX_BITS                 1
#define BRPHY1_GPHY_CORE_SHD18_101_FORCE_MDIX_SHIFT                4

/* BRPHY1_GPHY_CORE :: SHD18_101 :: EN_PWRDNTDAC [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x8,3)
#define BRPHY1_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_MASK               0x0008
#define BRPHY1_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_BITS               1
#define BRPHY1_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_SHIFT              3

/* BRPHY1_GPHY_CORE :: SHD18_101 :: SHD18_SEL [02:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_101_SHD18_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_101_SHD18_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_101,0x7,0)
#define BRPHY1_GPHY_CORE_SHD18_101_SHD18_SEL_MASK                  0x0007
#define BRPHY1_GPHY_CORE_SHD18_101_SHD18_SEL_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_101_SHD18_SEL_BITS                  3
#define BRPHY1_GPHY_CORE_SHD18_101_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD18_110
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD18_110 :: IP_PHONE_SEED_WR_EN [15:15] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_110,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_110,0x8000,15)
#define BRPHY1_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_MASK        0x8000
#define BRPHY1_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_ALIGN       0
#define BRPHY1_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_BITS        1
#define BRPHY1_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_SHIFT       15

/* BRPHY1_GPHY_CORE :: SHD18_110 :: SPARE_REG [14:14] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_110_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_110,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_110_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_110,0x4000,14)
#define BRPHY1_GPHY_CORE_SHD18_110_SPARE_REG_MASK                  0x4000
#define BRPHY1_GPHY_CORE_SHD18_110_SPARE_REG_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_110_SPARE_REG_BITS                  1
#define BRPHY1_GPHY_CORE_SHD18_110_SPARE_REG_SHIFT                 14

/* BRPHY1_GPHY_CORE :: SHD18_110 :: LOC_IP_PHONE_SEED [13:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_110,0x3ff8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_110,0x3ff8,3)
#define BRPHY1_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_MASK          0x3ff8
#define BRPHY1_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_ALIGN         0
#define BRPHY1_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_BITS          11
#define BRPHY1_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_SHIFT         3

/* BRPHY1_GPHY_CORE :: SHD18_110 :: SHD18_SEL [02:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_110_SHD18_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_110,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_110_SHD18_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_110,0x7,0)
#define BRPHY1_GPHY_CORE_SHD18_110_SHD18_SEL_MASK                  0x0007
#define BRPHY1_GPHY_CORE_SHD18_110_SHD18_SEL_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_110_SHD18_SEL_BITS                  3
#define BRPHY1_GPHY_CORE_SHD18_110_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SHD18_111
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SHD18_111 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_SHD18_111_RESERVED0_MASK                  0x8000
#define BRPHY1_GPHY_CORE_SHD18_111_RESERVED0_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_111_RESERVED0_BITS                  1
#define BRPHY1_GPHY_CORE_SHD18_111_RESERVED0_SHIFT                 15

/* BRPHY1_GPHY_CORE :: SHD18_111 :: SHD18_RDSEL [14:12] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x7000,12,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x7000,12)
#define BRPHY1_GPHY_CORE_SHD18_111_SHD18_RDSEL_MASK                0x7000
#define BRPHY1_GPHY_CORE_SHD18_111_SHD18_RDSEL_ALIGN               0
#define BRPHY1_GPHY_CORE_SHD18_111_SHD18_RDSEL_BITS                3
#define BRPHY1_GPHY_CORE_SHD18_111_SHD18_RDSEL_SHIFT               12

/* BRPHY1_GPHY_CORE :: SHD18_111 :: PKT_CNTR [11:11] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_PKT_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_PKT_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x800,11)
#define BRPHY1_GPHY_CORE_SHD18_111_PKT_CNTR_MASK                   0x0800
#define BRPHY1_GPHY_CORE_SHD18_111_PKT_CNTR_ALIGN                  0
#define BRPHY1_GPHY_CORE_SHD18_111_PKT_CNTR_BITS                   1
#define BRPHY1_GPHY_CORE_SHD18_111_PKT_CNTR_SHIFT                  11

/* BRPHY1_GPHY_CORE :: SHD18_111 :: BYPASS_WIRESPEED_TIMER [10:10] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x400,10)
#define BRPHY1_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_MASK     0x0400
#define BRPHY1_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_ALIGN    0
#define BRPHY1_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_BITS     1
#define BRPHY1_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_SHIFT    10

/* BRPHY1_GPHY_CORE :: SHD18_111 :: FORCE_AUTO_MDIX [09:09] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x200,9)
#define BRPHY1_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_MASK            0x0200
#define BRPHY1_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_ALIGN           0
#define BRPHY1_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_BITS            1
#define BRPHY1_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_SHIFT           9

/* BRPHY1_GPHY_CORE :: SHD18_111 :: RGMII_TIMING [08:08] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_RGMII_TIMING(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_RGMII_TIMING(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x100,8)
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_TIMING_MASK               0x0100
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_TIMING_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_TIMING_BITS               1
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_TIMING_SHIFT              8

/* BRPHY1_GPHY_CORE :: SHD18_111 :: RGMII [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_RGMII(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_RGMII(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x80,7)
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_MASK                      0x0080
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_ALIGN                     0
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_BITS                      1
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_SHIFT                     7

/* BRPHY1_GPHY_CORE :: SHD18_111 :: RGMII_RXER [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_RGMII_RXER(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_RGMII_RXER(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x40,6)
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_RXER_MASK                 0x0040
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_RXER_ALIGN                0
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_RXER_BITS                 1
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_RXER_SHIFT                6

/* BRPHY1_GPHY_CORE :: SHD18_111 :: RGMII_OB_STATUS_DIS [05:05] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x20,5)
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_MASK        0x0020
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_ALIGN       0
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_BITS        1
#define BRPHY1_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_SHIFT       5

/* BRPHY1_GPHY_CORE :: SHD18_111 :: WIRESPEED_EN [04:04] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x10,4)
#define BRPHY1_GPHY_CORE_SHD18_111_WIRESPEED_EN_MASK               0x0010
#define BRPHY1_GPHY_CORE_SHD18_111_WIRESPEED_EN_ALIGN              0
#define BRPHY1_GPHY_CORE_SHD18_111_WIRESPEED_EN_BITS               1
#define BRPHY1_GPHY_CORE_SHD18_111_WIRESPEED_EN_SHIFT              4

/* BRPHY1_GPHY_CORE :: SHD18_111 :: MDIO_ALL_PHY_SEL [03:03] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x8,3)
#define BRPHY1_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_MASK           0x0008
#define BRPHY1_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_ALIGN          0
#define BRPHY1_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_BITS           1
#define BRPHY1_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_SHIFT          3

/* BRPHY1_GPHY_CORE :: SHD18_111 :: SHD18_SEL [02:00] */
#define Wr_BRPHY1_GPHY_CORE_SHD18_111_SHD18_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_SHD18_111_SHD18_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SHD18_111,0x7,0)
#define BRPHY1_GPHY_CORE_SHD18_111_SHD18_SEL_MASK                  0x0007
#define BRPHY1_GPHY_CORE_SHD18_111_SHD18_SEL_ALIGN                 0
#define BRPHY1_GPHY_CORE_SHD18_111_SHD18_SEL_BITS                  3
#define BRPHY1_GPHY_CORE_SHD18_111_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP00
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP00 :: PKT_CNTR [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP00_PKT_CNTR(x) WriteReg16(BRPHY1_GPHY_CORE_EXP00,x)
#define Rd_BRPHY1_GPHY_CORE_EXP00_PKT_CNTR(x) ReadReg16(BRPHY1_GPHY_CORE_EXP00)
#define BRPHY1_GPHY_CORE_EXP00_PKT_CNTR_MASK                       0xffff
#define BRPHY1_GPHY_CORE_EXP00_PKT_CNTR_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP00_PKT_CNTR_BITS                       16
#define BRPHY1_GPHY_CORE_EXP00_PKT_CNTR_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP01
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP01 :: LATE_COL_CNTR [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_LATE_COL_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_LATE_COL_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x8000,15)
#define BRPHY1_GPHY_CORE_EXP01_LATE_COL_CNTR_MASK                  0x8000
#define BRPHY1_GPHY_CORE_EXP01_LATE_COL_CNTR_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP01_LATE_COL_CNTR_BITS                  1
#define BRPHY1_GPHY_CORE_EXP01_LATE_COL_CNTR_SHIFT                 15

/* BRPHY1_GPHY_CORE :: EXP01 :: RMT_COPPER_ERR [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x4000,14)
#define BRPHY1_GPHY_CORE_EXP01_RMT_COPPER_ERR_MASK                 0x4000
#define BRPHY1_GPHY_CORE_EXP01_RMT_COPPER_ERR_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP01_RMT_COPPER_ERR_BITS                 1
#define BRPHY1_GPHY_CORE_EXP01_RMT_COPPER_ERR_SHIFT                14

/* BRPHY1_GPHY_CORE :: EXP01 :: SERDES_LINK_PARTNER_RESTARTED [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x2000,13)
#define BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_MASK  0x2000
#define BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_ALIGN 0
#define BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_BITS  1
#define BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_SHIFT 13

/* BRPHY1_GPHY_CORE :: EXP01 :: SERDES_CRC_ERR [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP01_SERDES_CRC_ERR_MASK                 0x1000
#define BRPHY1_GPHY_CORE_EXP01_SERDES_CRC_ERR_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP01_SERDES_CRC_ERR_BITS                 1
#define BRPHY1_GPHY_CORE_EXP01_SERDES_CRC_ERR_SHIFT                12

/* BRPHY1_GPHY_CORE :: EXP01 :: SGMII_SLAVE_CHANGE [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x800,11)
#define BRPHY1_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_MASK             0x0800
#define BRPHY1_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_ALIGN            0
#define BRPHY1_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_BITS             1
#define BRPHY1_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_SHIFT            11

/* BRPHY1_GPHY_CORE :: EXP01 :: FX_SERDES_CHANGE [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x400,10)
#define BRPHY1_GPHY_CORE_EXP01_FX_SERDES_CHANGE_MASK               0x0400
#define BRPHY1_GPHY_CORE_EXP01_FX_SERDES_CHANGE_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP01_FX_SERDES_CHANGE_BITS               1
#define BRPHY1_GPHY_CORE_EXP01_FX_SERDES_CHANGE_SHIFT              10

/* BRPHY1_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_PAGE_RCVD [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x200,9)
#define BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_MASK       0x0200
#define BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_ALIGN      0
#define BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_BITS       1
#define BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_SHIFT      9

/* BRPHY1_GPHY_CORE :: EXP01 :: EXT_SERDES_SEL_CHANGE [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x100,8)
#define BRPHY1_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_MASK          0x0100
#define BRPHY1_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_ALIGN         0
#define BRPHY1_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_BITS          1
#define BRPHY1_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_SHIFT         8

/* BRPHY1_GPHY_CORE :: EXP01 :: MODE_SEL_CHANGE [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x80,7)
#define BRPHY1_GPHY_CORE_EXP01_MODE_SEL_CHANGE_MASK                0x0080
#define BRPHY1_GPHY_CORE_EXP01_MODE_SEL_CHANGE_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP01_MODE_SEL_CHANGE_BITS                1
#define BRPHY1_GPHY_CORE_EXP01_MODE_SEL_CHANGE_SHIFT               7

/* BRPHY1_GPHY_CORE :: EXP01 :: SERDES_LINK_STATUS_CHANGE [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x40,6)
#define BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_MASK      0x0040
#define BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_ALIGN     0
#define BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_BITS      1
#define BRPHY1_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_SHIFT     6

/* BRPHY1_GPHY_CORE :: EXP01 :: RUDI_C_DET [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_RUDI_C_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_RUDI_C_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x20,5)
#define BRPHY1_GPHY_CORE_EXP01_RUDI_C_DET_MASK                     0x0020
#define BRPHY1_GPHY_CORE_EXP01_RUDI_C_DET_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP01_RUDI_C_DET_BITS                     1
#define BRPHY1_GPHY_CORE_EXP01_RUDI_C_DET_SHIFT                    5

/* BRPHY1_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_ERR [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x10,4)
#define BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_MASK             0x0010
#define BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_ALIGN            0
#define BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_BITS             1
#define BRPHY1_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_SHIFT            4

/* BRPHY1_GPHY_CORE :: EXP01 :: RUDI_I_DET [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_RUDI_I_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_RUDI_I_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x8,3)
#define BRPHY1_GPHY_CORE_EXP01_RUDI_I_DET_MASK                     0x0008
#define BRPHY1_GPHY_CORE_EXP01_RUDI_I_DET_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP01_RUDI_I_DET_BITS                     1
#define BRPHY1_GPHY_CORE_EXP01_RUDI_I_DET_SHIFT                    3

/* BRPHY1_GPHY_CORE :: EXP01 :: SERDES_RCVD_BREAK_LINK_CONDITION [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x4,2)
#define BRPHY1_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_MASK 0x0004
#define BRPHY1_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_ALIGN 0
#define BRPHY1_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_BITS 1
#define BRPHY1_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_SHIFT 2

/* BRPHY1_GPHY_CORE :: EXP01 :: ABIST_COMPLETE [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_ABIST_COMPLETE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_ABIST_COMPLETE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x2,1)
#define BRPHY1_GPHY_CORE_EXP01_ABIST_COMPLETE_MASK                 0x0002
#define BRPHY1_GPHY_CORE_EXP01_ABIST_COMPLETE_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP01_ABIST_COMPLETE_BITS                 1
#define BRPHY1_GPHY_CORE_EXP01_ABIST_COMPLETE_SHIFT                1

/* BRPHY1_GPHY_CORE :: EXP01 :: TX_CRC_ERR [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP01_TX_CRC_ERR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP01,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP01_TX_CRC_ERR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP01,0x1,0)
#define BRPHY1_GPHY_CORE_EXP01_TX_CRC_ERR_MASK                     0x0001
#define BRPHY1_GPHY_CORE_EXP01_TX_CRC_ERR_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP01_TX_CRC_ERR_BITS                     1
#define BRPHY1_GPHY_CORE_EXP01_TX_CRC_ERR_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP02
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP02 :: EXP_INT_MASK [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP02_EXP_INT_MASK(x) WriteReg16(BRPHY1_GPHY_CORE_EXP02,x)
#define Rd_BRPHY1_GPHY_CORE_EXP02_EXP_INT_MASK(x) ReadReg16(BRPHY1_GPHY_CORE_EXP02)
#define BRPHY1_GPHY_CORE_EXP02_EXP_INT_MASK_MASK                   0xffff
#define BRPHY1_GPHY_CORE_EXP02_EXP_INT_MASK_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP02_EXP_INT_MASK_BITS                   16
#define BRPHY1_GPHY_CORE_EXP02_EXP_INT_MASK_SHIFT                  0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP03
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP03 :: SPARE_REG [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP03_SPARE_REG(x) WriteReg16(BRPHY1_GPHY_CORE_EXP03,x)
#define Rd_BRPHY1_GPHY_CORE_EXP03_SPARE_REG(x) ReadReg16(BRPHY1_GPHY_CORE_EXP03)
#define BRPHY1_GPHY_CORE_EXP03_SPARE_REG_MASK                      0xffff
#define BRPHY1_GPHY_CORE_EXP03_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP03_SPARE_REG_BITS                      16
#define BRPHY1_GPHY_CORE_EXP03_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP04
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP04 :: reserved0 [15:11] */
#define BRPHY1_GPHY_CORE_EXP04_RESERVED0_MASK                      0xf800
#define BRPHY1_GPHY_CORE_EXP04_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP04_RESERVED0_BITS                      5
#define BRPHY1_GPHY_CORE_EXP04_RESERVED0_SHIFT                     11

/* BRPHY1_GPHY_CORE :: EXP04 :: BC_LED_EN [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXP04_BC_LED_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP04,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXP04_BC_LED_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP04,0x400,10)
#define BRPHY1_GPHY_CORE_EXP04_BC_LED_EN_MASK                      0x0400
#define BRPHY1_GPHY_CORE_EXP04_BC_LED_EN_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP04_BC_LED_EN_BITS                      1
#define BRPHY1_GPHY_CORE_EXP04_BC_LED_EN_SHIFT                     10

/* BRPHY1_GPHY_CORE :: EXP04 :: FLASHNOW [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXP04_FLASHNOW(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP04,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXP04_FLASHNOW(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP04,0x200,9)
#define BRPHY1_GPHY_CORE_EXP04_FLASHNOW_MASK                       0x0200
#define BRPHY1_GPHY_CORE_EXP04_FLASHNOW_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP04_FLASHNOW_BITS                       1
#define BRPHY1_GPHY_CORE_EXP04_FLASHNOW_SHIFT                      9

/* BRPHY1_GPHY_CORE :: EXP04 :: INPHASE [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP04_INPHASE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP04,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP04_INPHASE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP04,0x100,8)
#define BRPHY1_GPHY_CORE_EXP04_INPHASE_MASK                        0x0100
#define BRPHY1_GPHY_CORE_EXP04_INPHASE_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP04_INPHASE_BITS                        1
#define BRPHY1_GPHY_CORE_EXP04_INPHASE_SHIFT                       8

/* BRPHY1_GPHY_CORE :: EXP04 :: BC_SEL_1 [07:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP04_BC_SEL_1(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP04,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP04_BC_SEL_1(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP04,0xf0,4)
#define BRPHY1_GPHY_CORE_EXP04_BC_SEL_1_MASK                       0x00f0
#define BRPHY1_GPHY_CORE_EXP04_BC_SEL_1_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP04_BC_SEL_1_BITS                       4
#define BRPHY1_GPHY_CORE_EXP04_BC_SEL_1_SHIFT                      4

/* BRPHY1_GPHY_CORE :: EXP04 :: BC_SEL_0 [03:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP04_BC_SEL_0(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP04,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP04_BC_SEL_0(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP04,0xf,0)
#define BRPHY1_GPHY_CORE_EXP04_BC_SEL_0_MASK                       0x000f
#define BRPHY1_GPHY_CORE_EXP04_BC_SEL_0_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP04_BC_SEL_0_BITS                       4
#define BRPHY1_GPHY_CORE_EXP04_BC_SEL_0_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP05
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP05 :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_EXP05_RESERVED0_MASK                      0xf000
#define BRPHY1_GPHY_CORE_EXP05_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP05_RESERVED0_BITS                      4
#define BRPHY1_GPHY_CORE_EXP05_RESERVED0_SHIFT                     12

/* BRPHY1_GPHY_CORE :: EXP05 :: ALTERNATION_RATE [11:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP05_ALTERNATION_RATE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP05,0xfc0,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP05_ALTERNATION_RATE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP05,0xfc0,6)
#define BRPHY1_GPHY_CORE_EXP05_ALTERNATION_RATE_MASK               0x0fc0
#define BRPHY1_GPHY_CORE_EXP05_ALTERNATION_RATE_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP05_ALTERNATION_RATE_BITS               6
#define BRPHY1_GPHY_CORE_EXP05_ALTERNATION_RATE_SHIFT              6

/* BRPHY1_GPHY_CORE :: EXP05 :: FLASH_RATE [05:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP05_FLASH_RATE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP05,0x3f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP05_FLASH_RATE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP05,0x3f,0)
#define BRPHY1_GPHY_CORE_EXP05_FLASH_RATE_MASK                     0x003f
#define BRPHY1_GPHY_CORE_EXP05_FLASH_RATE_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP05_FLASH_RATE_BITS                     6
#define BRPHY1_GPHY_CORE_EXP05_FLASH_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP06
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP06 :: reserved0 [15:08] */
#define BRPHY1_GPHY_CORE_EXP06_RESERVED0_MASK                      0xff00
#define BRPHY1_GPHY_CORE_EXP06_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP06_RESERVED0_BITS                      8
#define BRPHY1_GPHY_CORE_EXP06_RESERVED0_SHIFT                     8

/* BRPHY1_GPHY_CORE :: EXP06 :: SPARE_REG [07:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP06_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP06,0xc0,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP06_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP06,0xc0,6)
#define BRPHY1_GPHY_CORE_EXP06_SPARE_REG_MASK                      0x00c0
#define BRPHY1_GPHY_CORE_EXP06_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP06_SPARE_REG_BITS                      2
#define BRPHY1_GPHY_CORE_EXP06_SPARE_REG_SHIFT                     6

/* BRPHY1_GPHY_CORE :: EXP06 :: BLINK_UPDATE_NOW [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP06,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP06,0x20,5)
#define BRPHY1_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_MASK               0x0020
#define BRPHY1_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_BITS               1
#define BRPHY1_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_SHIFT              5

/* BRPHY1_GPHY_CORE :: EXP06 :: BLINK_RATE [04:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP06_BLINK_RATE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP06,0x1f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP06_BLINK_RATE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP06,0x1f,0)
#define BRPHY1_GPHY_CORE_EXP06_BLINK_RATE_MASK                     0x001f
#define BRPHY1_GPHY_CORE_EXP06_BLINK_RATE_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP06_BLINK_RATE_BITS                     5
#define BRPHY1_GPHY_CORE_EXP06_BLINK_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP07
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP07 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_EXP07_RESERVED0_MASK                      0x8000
#define BRPHY1_GPHY_CORE_EXP07_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP07_RESERVED0_BITS                      1
#define BRPHY1_GPHY_CORE_EXP07_RESERVED0_SHIFT                     15

/* BRPHY1_GPHY_CORE :: EXP07 :: EXT_MAX_LP_WIDTH [14:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP07,0x7f00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP07,0x7f00,8)
#define BRPHY1_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_MASK               0x7f00
#define BRPHY1_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_BITS               7
#define BRPHY1_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_SHIFT              8

/* BRPHY1_GPHY_CORE :: EXP07 :: SPARE_REG [07:03] */
#define Wr_BRPHY1_GPHY_CORE_EXP07_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP07,0xf8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXP07_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP07,0xf8,3)
#define BRPHY1_GPHY_CORE_EXP07_SPARE_REG_MASK                      0x00f8
#define BRPHY1_GPHY_CORE_EXP07_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP07_SPARE_REG_BITS                      5
#define BRPHY1_GPHY_CORE_EXP07_SPARE_REG_SHIFT                     3

/* BRPHY1_GPHY_CORE :: EXP07 :: COPPER_FX_SIGSTAT_SEL [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP07,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP07,0x4,2)
#define BRPHY1_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_MASK          0x0004
#define BRPHY1_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_ALIGN         0
#define BRPHY1_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_BITS          1
#define BRPHY1_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_SHIFT         2

/* BRPHY1_GPHY_CORE :: EXP07 :: FAULTING [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP07_FAULTING(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP07,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP07_FAULTING(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP07,0x2,1)
#define BRPHY1_GPHY_CORE_EXP07_FAULTING_MASK                       0x0002
#define BRPHY1_GPHY_CORE_EXP07_FAULTING_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP07_FAULTING_BITS                       1
#define BRPHY1_GPHY_CORE_EXP07_FAULTING_SHIFT                      1

/* BRPHY1_GPHY_CORE :: EXP07 :: FEF_EN [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP07_FEF_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP07,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP07_FEF_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP07,0x1,0)
#define BRPHY1_GPHY_CORE_EXP07_FEF_EN_MASK                         0x0001
#define BRPHY1_GPHY_CORE_EXP07_FEF_EN_ALIGN                        0
#define BRPHY1_GPHY_CORE_EXP07_FEF_EN_BITS                         1
#define BRPHY1_GPHY_CORE_EXP07_FEF_EN_SHIFT                        0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP08
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP08 :: SILENT_LPBK [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_SILENT_LPBK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_SILENT_LPBK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x8000,15)
#define BRPHY1_GPHY_CORE_EXP08_SILENT_LPBK_MASK                    0x8000
#define BRPHY1_GPHY_CORE_EXP08_SILENT_LPBK_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP08_SILENT_LPBK_BITS                    1
#define BRPHY1_GPHY_CORE_EXP08_SILENT_LPBK_SHIFT                   15

/* BRPHY1_GPHY_CORE :: EXP08 :: RX_POLARITY_OV [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x4000,14)
#define BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_MASK                 0x4000
#define BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_BITS                 1
#define BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_SHIFT                14

/* BRPHY1_GPHY_CORE :: EXP08 :: RX_POLARITY_OV_VAL [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x2000,13)
#define BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_MASK             0x2000
#define BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_ALIGN            0
#define BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_BITS             1
#define BRPHY1_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_SHIFT            13

/* BRPHY1_GPHY_CORE :: EXP08 :: BT_BYTE_ALIGN_PREAM [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_MASK            0x1000
#define BRPHY1_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_ALIGN           0
#define BRPHY1_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_BITS            1
#define BRPHY1_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_SHIFT           12

/* BRPHY1_GPHY_CORE :: EXP08 :: BT_PREAM_SUPPRESS [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x800,11)
#define BRPHY1_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_MASK              0x0800
#define BRPHY1_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_BITS              1
#define BRPHY1_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_SHIFT             11

/* BRPHY1_GPHY_CORE :: EXP08 :: EXT_MAX_LP_WIDTH_EN [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x400,10)
#define BRPHY1_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_MASK            0x0400
#define BRPHY1_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_BITS            1
#define BRPHY1_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_SHIFT           10

/* BRPHY1_GPHY_CORE :: EXP08 :: AUTO_EARLY_DAC_WAKE [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x200,9)
#define BRPHY1_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_MASK            0x0200
#define BRPHY1_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_ALIGN           0
#define BRPHY1_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_BITS            1
#define BRPHY1_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_SHIFT           9

/* BRPHY1_GPHY_CORE :: EXP08 :: FORCE_EARLY_DAC_WAKE [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x100,8)
#define BRPHY1_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_MASK           0x0100
#define BRPHY1_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_ALIGN          0
#define BRPHY1_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_BITS           1
#define BRPHY1_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_SHIFT          8

/* BRPHY1_GPHY_CORE :: EXP08 :: SUPPRESS_CRS_HDX [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x80,7)
#define BRPHY1_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_MASK               0x0080
#define BRPHY1_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_BITS               1
#define BRPHY1_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_SHIFT              7

/* BRPHY1_GPHY_CORE :: EXP08 :: REJECT_MORE_15MHZ [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x40,6)
#define BRPHY1_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_MASK              0x0040
#define BRPHY1_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_BITS              1
#define BRPHY1_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_SHIFT             6

/* BRPHY1_GPHY_CORE :: EXP08 :: POLARITY_INVERT [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_POLARITY_INVERT(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_POLARITY_INVERT(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x20,5)
#define BRPHY1_GPHY_CORE_EXP08_POLARITY_INVERT_MASK                0x0020
#define BRPHY1_GPHY_CORE_EXP08_POLARITY_INVERT_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP08_POLARITY_INVERT_BITS                1
#define BRPHY1_GPHY_CORE_EXP08_POLARITY_INVERT_SHIFT               5

/* BRPHY1_GPHY_CORE :: EXP08 :: BLOCK_NARROW_LP [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x10,4)
#define BRPHY1_GPHY_CORE_EXP08_BLOCK_NARROW_LP_MASK                0x0010
#define BRPHY1_GPHY_CORE_EXP08_BLOCK_NARROW_LP_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP08_BLOCK_NARROW_LP_BITS                1
#define BRPHY1_GPHY_CORE_EXP08_BLOCK_NARROW_LP_SHIFT               4

/* BRPHY1_GPHY_CORE :: EXP08 :: USE_OLD_LPDET [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_USE_OLD_LPDET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_USE_OLD_LPDET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x8,3)
#define BRPHY1_GPHY_CORE_EXP08_USE_OLD_LPDET_MASK                  0x0008
#define BRPHY1_GPHY_CORE_EXP08_USE_OLD_LPDET_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP08_USE_OLD_LPDET_BITS                  1
#define BRPHY1_GPHY_CORE_EXP08_USE_OLD_LPDET_SHIFT                 3

/* BRPHY1_GPHY_CORE :: EXP08 :: EDGESTATE_REFINE [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x4,2)
#define BRPHY1_GPHY_CORE_EXP08_EDGESTATE_REFINE_MASK               0x0004
#define BRPHY1_GPHY_CORE_EXP08_EDGESTATE_REFINE_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP08_EDGESTATE_REFINE_BITS               1
#define BRPHY1_GPHY_CORE_EXP08_EDGESTATE_REFINE_SHIFT              2

/* BRPHY1_GPHY_CORE :: EXP08 :: REJECT_15MHZ [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_REJECT_15MHZ(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_REJECT_15MHZ(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x2,1)
#define BRPHY1_GPHY_CORE_EXP08_REJECT_15MHZ_MASK                   0x0002
#define BRPHY1_GPHY_CORE_EXP08_REJECT_15MHZ_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP08_REJECT_15MHZ_BITS                   1
#define BRPHY1_GPHY_CORE_EXP08_REJECT_15MHZ_SHIFT                  1

/* BRPHY1_GPHY_CORE :: EXP08 :: REJECT_2MHZ [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP08_REJECT_2MHZ(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP08,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP08_REJECT_2MHZ(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP08,0x1,0)
#define BRPHY1_GPHY_CORE_EXP08_REJECT_2MHZ_MASK                    0x0001
#define BRPHY1_GPHY_CORE_EXP08_REJECT_2MHZ_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP08_REJECT_2MHZ_BITS                    1
#define BRPHY1_GPHY_CORE_EXP08_REJECT_2MHZ_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP09
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP09 :: GIGABIT_POL_INV [15:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP09,0xf000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP09,0xf000,12)
#define BRPHY1_GPHY_CORE_EXP09_GIGABIT_POL_INV_MASK                0xf000
#define BRPHY1_GPHY_CORE_EXP09_GIGABIT_POL_INV_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP09_GIGABIT_POL_INV_BITS                4
#define BRPHY1_GPHY_CORE_EXP09_GIGABIT_POL_INV_SHIFT               12

/* BRPHY1_GPHY_CORE :: EXP09 :: SPARE_REG [11:09] */
#define Wr_BRPHY1_GPHY_CORE_EXP09_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP09,0xe00,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXP09_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP09,0xe00,9)
#define BRPHY1_GPHY_CORE_EXP09_SPARE_REG_MASK                      0x0e00
#define BRPHY1_GPHY_CORE_EXP09_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP09_SPARE_REG_BITS                      3
#define BRPHY1_GPHY_CORE_EXP09_SPARE_REG_SHIFT                     9

/* BRPHY1_GPHY_CORE :: EXP09 :: ALLOW_SWAP [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP09_ALLOW_SWAP(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP09,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP09_ALLOW_SWAP(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP09,0x100,8)
#define BRPHY1_GPHY_CORE_EXP09_ALLOW_SWAP_MASK                     0x0100
#define BRPHY1_GPHY_CORE_EXP09_ALLOW_SWAP_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP09_ALLOW_SWAP_BITS                     1
#define BRPHY1_GPHY_CORE_EXP09_ALLOW_SWAP_SHIFT                    8

/* BRPHY1_GPHY_CORE :: EXP09 :: CH3_SEL [07:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP09_CH3_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP09,0xc0,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP09_CH3_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP09,0xc0,6)
#define BRPHY1_GPHY_CORE_EXP09_CH3_SEL_MASK                        0x00c0
#define BRPHY1_GPHY_CORE_EXP09_CH3_SEL_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP09_CH3_SEL_BITS                        2
#define BRPHY1_GPHY_CORE_EXP09_CH3_SEL_SHIFT                       6

/* BRPHY1_GPHY_CORE :: EXP09 :: CH2_SEL [05:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP09_CH2_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP09,0x30,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP09_CH2_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP09,0x30,4)
#define BRPHY1_GPHY_CORE_EXP09_CH2_SEL_MASK                        0x0030
#define BRPHY1_GPHY_CORE_EXP09_CH2_SEL_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP09_CH2_SEL_BITS                        2
#define BRPHY1_GPHY_CORE_EXP09_CH2_SEL_SHIFT                       4

/* BRPHY1_GPHY_CORE :: EXP09 :: CH1_SEL [03:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP09_CH1_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP09,0xc,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP09_CH1_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP09,0xc,2)
#define BRPHY1_GPHY_CORE_EXP09_CH1_SEL_MASK                        0x000c
#define BRPHY1_GPHY_CORE_EXP09_CH1_SEL_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP09_CH1_SEL_BITS                        2
#define BRPHY1_GPHY_CORE_EXP09_CH1_SEL_SHIFT                       2

/* BRPHY1_GPHY_CORE :: EXP09 :: CH0_SEL [01:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP09_CH0_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP09,0x3,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP09_CH0_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP09,0x3,0)
#define BRPHY1_GPHY_CORE_EXP09_CH0_SEL_MASK                        0x0003
#define BRPHY1_GPHY_CORE_EXP09_CH0_SEL_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP09_CH0_SEL_BITS                        2
#define BRPHY1_GPHY_CORE_EXP09_CH0_SEL_SHIFT                       0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP0A
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP0A :: reserved0 [15:13] */
#define BRPHY1_GPHY_CORE_EXP0A_RESERVED0_MASK                      0xe000
#define BRPHY1_GPHY_CORE_EXP0A_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP0A_RESERVED0_BITS                      3
#define BRPHY1_GPHY_CORE_EXP0A_RESERVED0_SHIFT                     13

/* BRPHY1_GPHY_CORE :: EXP0A :: SYNC_IN_EN [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP0A_SYNC_IN_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP0A_SYNC_IN_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP0A_SYNC_IN_EN_MASK                     0x1000
#define BRPHY1_GPHY_CORE_EXP0A_SYNC_IN_EN_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP0A_SYNC_IN_EN_BITS                     1
#define BRPHY1_GPHY_CORE_EXP0A_SYNC_IN_EN_SHIFT                    12

/* BRPHY1_GPHY_CORE :: EXP0A :: CHANNEL_KILL [11:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP0A_CHANNEL_KILL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP0A,0xf00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP0A_CHANNEL_KILL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP0A,0xf00,8)
#define BRPHY1_GPHY_CORE_EXP0A_CHANNEL_KILL_MASK                   0x0f00
#define BRPHY1_GPHY_CORE_EXP0A_CHANNEL_KILL_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP0A_CHANNEL_KILL_BITS                   4
#define BRPHY1_GPHY_CORE_EXP0A_CHANNEL_KILL_SHIFT                  8

/* BRPHY1_GPHY_CORE :: EXP0A :: SYNC_KILL [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXP0A_SYNC_KILL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXP0A_SYNC_KILL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x80,7)
#define BRPHY1_GPHY_CORE_EXP0A_SYNC_KILL_MASK                      0x0080
#define BRPHY1_GPHY_CORE_EXP0A_SYNC_KILL_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP0A_SYNC_KILL_BITS                      1
#define BRPHY1_GPHY_CORE_EXP0A_SYNC_KILL_SHIFT                     7

/* BRPHY1_GPHY_CORE :: EXP0A :: BYPASS_ENE [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP0A_BYPASS_ENE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP0A_BYPASS_ENE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x40,6)
#define BRPHY1_GPHY_CORE_EXP0A_BYPASS_ENE_MASK                     0x0040
#define BRPHY1_GPHY_CORE_EXP0A_BYPASS_ENE_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP0A_BYPASS_ENE_BITS                     1
#define BRPHY1_GPHY_CORE_EXP0A_BYPASS_ENE_SHIFT                    6

/* BRPHY1_GPHY_CORE :: EXP0A :: PAT_DURATION [05:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP0A_PAT_DURATION(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x30,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP0A_PAT_DURATION(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x30,4)
#define BRPHY1_GPHY_CORE_EXP0A_PAT_DURATION_MASK                   0x0030
#define BRPHY1_GPHY_CORE_EXP0A_PAT_DURATION_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP0A_PAT_DURATION_BITS                   2
#define BRPHY1_GPHY_CORE_EXP0A_PAT_DURATION_SHIFT                  4

/* BRPHY1_GPHY_CORE :: EXP0A :: PAT_SEL [03:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP0A_PAT_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP0A,0xe,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP0A_PAT_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP0A,0xe,1)
#define BRPHY1_GPHY_CORE_EXP0A_PAT_SEL_MASK                        0x000e
#define BRPHY1_GPHY_CORE_EXP0A_PAT_SEL_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP0A_PAT_SEL_BITS                        3
#define BRPHY1_GPHY_CORE_EXP0A_PAT_SEL_SHIFT                       1

/* BRPHY1_GPHY_CORE :: EXP0A :: TEMPLATE_EN [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP0A_TEMPLATE_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP0A_TEMPLATE_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP0A,0x1,0)
#define BRPHY1_GPHY_CORE_EXP0A_TEMPLATE_EN_MASK                    0x0001
#define BRPHY1_GPHY_CORE_EXP0A_TEMPLATE_EN_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP0A_TEMPLATE_EN_BITS                    1
#define BRPHY1_GPHY_CORE_EXP0A_TEMPLATE_EN_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP0B
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP0B :: EXT_STATUS [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP0B_EXT_STATUS(x) WriteReg16(BRPHY1_GPHY_CORE_EXP0B,x)
#define Rd_BRPHY1_GPHY_CORE_EXP0B_EXT_STATUS(x) ReadReg16(BRPHY1_GPHY_CORE_EXP0B)
#define BRPHY1_GPHY_CORE_EXP0B_EXT_STATUS_MASK                     0xffff
#define BRPHY1_GPHY_CORE_EXP0B_EXT_STATUS_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP0B_EXT_STATUS_BITS                     16
#define BRPHY1_GPHY_CORE_EXP0B_EXT_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP0C
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP0C :: SPARE_REG [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP0C_SPARE_REG(x) WriteReg16(BRPHY1_GPHY_CORE_EXP0C,x)
#define Rd_BRPHY1_GPHY_CORE_EXP0C_SPARE_REG(x) ReadReg16(BRPHY1_GPHY_CORE_EXP0C)
#define BRPHY1_GPHY_CORE_EXP0C_SPARE_REG_MASK                      0xffff
#define BRPHY1_GPHY_CORE_EXP0C_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP0C_SPARE_REG_BITS                      16
#define BRPHY1_GPHY_CORE_EXP0C_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP30
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP30 :: reserved0 [15:05] */
#define BRPHY1_GPHY_CORE_EXP30_RESERVED0_MASK                      0xffe0
#define BRPHY1_GPHY_CORE_EXP30_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP30_RESERVED0_BITS                      11
#define BRPHY1_GPHY_CORE_EXP30_RESERVED0_SHIFT                     5

/* BRPHY1_GPHY_CORE :: EXP30 :: DEADMAN_RESET [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP30_DEADMAN_RESET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP30,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP30_DEADMAN_RESET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP30,0x10,4)
#define BRPHY1_GPHY_CORE_EXP30_DEADMAN_RESET_MASK                  0x0010
#define BRPHY1_GPHY_CORE_EXP30_DEADMAN_RESET_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP30_DEADMAN_RESET_BITS                  1
#define BRPHY1_GPHY_CORE_EXP30_DEADMAN_RESET_SHIFT                 4

/* BRPHY1_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_128_TO_255 [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP30,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP30,0x8,3)
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_MASK       0x0008
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_ALIGN      0
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_BITS       1
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_SHIFT      3

/* BRPHY1_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_64_TO_127 [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP30,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP30,0x4,2)
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_MASK        0x0004
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_ALIGN       0
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_BITS        1
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_SHIFT       2

/* BRPHY1_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_32_TO_63 [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP30,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP30,0x2,1)
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_MASK         0x0002
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_ALIGN        0
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_BITS         1
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_SHIFT        1

/* BRPHY1_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_0_TO_31 [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP30,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP30,0x1,0)
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_MASK          0x0001
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_ALIGN         0
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_BITS          1
#define BRPHY1_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_SHIFT         0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP31
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP31 :: reserved0 [15:08] */
#define BRPHY1_GPHY_CORE_EXP31_RESERVED0_MASK                      0xff00
#define BRPHY1_GPHY_CORE_EXP31_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP31_RESERVED0_BITS                      8
#define BRPHY1_GPHY_CORE_EXP31_RESERVED0_SHIFT                     8

/* BRPHY1_GPHY_CORE :: EXP31 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP31_LATE_COL_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP31,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP31_LATE_COL_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP31,0xff,0)
#define BRPHY1_GPHY_CORE_EXP31_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY1_GPHY_CORE_EXP31_LATE_COL_CNTR_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP31_LATE_COL_CNTR_BITS                  8
#define BRPHY1_GPHY_CORE_EXP31_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP32
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP32 :: reserved0 [15:08] */
#define BRPHY1_GPHY_CORE_EXP32_RESERVED0_MASK                      0xff00
#define BRPHY1_GPHY_CORE_EXP32_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP32_RESERVED0_BITS                      8
#define BRPHY1_GPHY_CORE_EXP32_RESERVED0_SHIFT                     8

/* BRPHY1_GPHY_CORE :: EXP32 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP32_LATE_COL_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP32,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP32_LATE_COL_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP32,0xff,0)
#define BRPHY1_GPHY_CORE_EXP32_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY1_GPHY_CORE_EXP32_LATE_COL_CNTR_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP32_LATE_COL_CNTR_BITS                  8
#define BRPHY1_GPHY_CORE_EXP32_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP33
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP33 :: reserved0 [15:08] */
#define BRPHY1_GPHY_CORE_EXP33_RESERVED0_MASK                      0xff00
#define BRPHY1_GPHY_CORE_EXP33_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP33_RESERVED0_BITS                      8
#define BRPHY1_GPHY_CORE_EXP33_RESERVED0_SHIFT                     8

/* BRPHY1_GPHY_CORE :: EXP33 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP33_LATE_COL_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP33,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP33_LATE_COL_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP33,0xff,0)
#define BRPHY1_GPHY_CORE_EXP33_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY1_GPHY_CORE_EXP33_LATE_COL_CNTR_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP33_LATE_COL_CNTR_BITS                  8
#define BRPHY1_GPHY_CORE_EXP33_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP34
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP34 :: reserved0 [15:08] */
#define BRPHY1_GPHY_CORE_EXP34_RESERVED0_MASK                      0xff00
#define BRPHY1_GPHY_CORE_EXP34_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP34_RESERVED0_BITS                      8
#define BRPHY1_GPHY_CORE_EXP34_RESERVED0_SHIFT                     8

/* BRPHY1_GPHY_CORE :: EXP34 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP34_LATE_COL_CNTR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP34,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP34_LATE_COL_CNTR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP34,0xff,0)
#define BRPHY1_GPHY_CORE_EXP34_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY1_GPHY_CORE_EXP34_LATE_COL_CNTR_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP34_LATE_COL_CNTR_BITS                  8
#define BRPHY1_GPHY_CORE_EXP34_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP35
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP35 :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_EXP35_RESERVED0_MASK                      0xf000
#define BRPHY1_GPHY_CORE_EXP35_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP35_RESERVED0_BITS                      4
#define BRPHY1_GPHY_CORE_EXP35_RESERVED0_SHIFT                     12

/* BRPHY1_GPHY_CORE :: EXP35 :: MII_INTERFACE_MODES [11:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP35,0xf00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP35,0xf00,8)
#define BRPHY1_GPHY_CORE_EXP35_MII_INTERFACE_MODES_MASK            0x0f00
#define BRPHY1_GPHY_CORE_EXP35_MII_INTERFACE_MODES_ALIGN           0
#define BRPHY1_GPHY_CORE_EXP35_MII_INTERFACE_MODES_BITS            4
#define BRPHY1_GPHY_CORE_EXP35_MII_INTERFACE_MODES_SHIFT           8

/* BRPHY1_GPHY_CORE :: EXP35 :: LATE_COL_CNTR_THD [07:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP35,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP35,0xff,0)
#define BRPHY1_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_MASK              0x00ff
#define BRPHY1_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_BITS              8
#define BRPHY1_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_SHIFT             0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP36
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP36 :: PPM_DET_PWRDN [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP36,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP36,0x8000,15)
#define BRPHY1_GPHY_CORE_EXP36_PPM_DET_PWRDN_MASK                  0x8000
#define BRPHY1_GPHY_CORE_EXP36_PPM_DET_PWRDN_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP36_PPM_DET_PWRDN_BITS                  1
#define BRPHY1_GPHY_CORE_EXP36_PPM_DET_PWRDN_SHIFT                 15

/* BRPHY1_GPHY_CORE :: EXP36 :: PPM_DET_TEST [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXP36_PPM_DET_TEST(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP36,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXP36_PPM_DET_TEST(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP36,0x4000,14)
#define BRPHY1_GPHY_CORE_EXP36_PPM_DET_TEST_MASK                   0x4000
#define BRPHY1_GPHY_CORE_EXP36_PPM_DET_TEST_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP36_PPM_DET_TEST_BITS                   1
#define BRPHY1_GPHY_CORE_EXP36_PPM_DET_TEST_SHIFT                  14

/* BRPHY1_GPHY_CORE :: EXP36 :: reserved0 [13:10] */
#define BRPHY1_GPHY_CORE_EXP36_RESERVED0_MASK                      0x3c00
#define BRPHY1_GPHY_CORE_EXP36_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP36_RESERVED0_BITS                      4
#define BRPHY1_GPHY_CORE_EXP36_RESERVED0_SHIFT                     10

/* BRPHY1_GPHY_CORE :: EXP36 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP36_PPM_OFFSET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP36,0x3ff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP36_PPM_OFFSET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP36,0x3ff,0)
#define BRPHY1_GPHY_CORE_EXP36_PPM_OFFSET_MASK                     0x03ff
#define BRPHY1_GPHY_CORE_EXP36_PPM_OFFSET_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP36_PPM_OFFSET_BITS                     10
#define BRPHY1_GPHY_CORE_EXP36_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP37
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP37 :: reserved0 [15:10] */
#define BRPHY1_GPHY_CORE_EXP37_RESERVED0_MASK                      0xfc00
#define BRPHY1_GPHY_CORE_EXP37_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP37_RESERVED0_BITS                      6
#define BRPHY1_GPHY_CORE_EXP37_RESERVED0_SHIFT                     10

/* BRPHY1_GPHY_CORE :: EXP37 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP37_PPM_OFFSET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP37,0x3ff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP37_PPM_OFFSET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP37,0x3ff,0)
#define BRPHY1_GPHY_CORE_EXP37_PPM_OFFSET_MASK                     0x03ff
#define BRPHY1_GPHY_CORE_EXP37_PPM_OFFSET_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP37_PPM_OFFSET_BITS                     10
#define BRPHY1_GPHY_CORE_EXP37_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP38
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP38 :: IP_PHONE_DET_CHANGE [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP38,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP38,0x8000,15)
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_MASK            0x8000
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_ALIGN           0
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_BITS            1
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_SHIFT           15

/* BRPHY1_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH_CHANGE [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP38,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP38,0x4000,14)
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_MASK       0x4000
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_ALIGN      0
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_BITS       1
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_SHIFT      14

/* BRPHY1_GPHY_CORE :: EXP38 :: IP_PHONE_FLP_BURST_TX [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP38,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP38,0x2000,13)
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_MASK          0x2000
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_ALIGN         0
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_BITS          1
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_SHIFT         13

/* BRPHY1_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP38,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP38,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_MASK              0x1000
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_BITS              1
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_SHIFT             12

/* BRPHY1_GPHY_CORE :: EXP38 :: IP_PHONE_DET [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP38,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP38,0x800,11)
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_MASK                   0x0800
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_BITS                   1
#define BRPHY1_GPHY_CORE_EXP38_IP_PHONE_DET_SHIFT                  11

/* BRPHY1_GPHY_CORE :: EXP38 :: NO_RESPSONSE [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXP38_NO_RESPSONSE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP38,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXP38_NO_RESPSONSE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP38,0x400,10)
#define BRPHY1_GPHY_CORE_EXP38_NO_RESPSONSE_MASK                   0x0400
#define BRPHY1_GPHY_CORE_EXP38_NO_RESPSONSE_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP38_NO_RESPSONSE_BITS                   1
#define BRPHY1_GPHY_CORE_EXP38_NO_RESPSONSE_SHIFT                  10

/* BRPHY1_GPHY_CORE :: EXP38 :: TOTAL_RT_DLY [09:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP38,0x3ff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP38,0x3ff,0)
#define BRPHY1_GPHY_CORE_EXP38_TOTAL_RT_DLY_MASK                   0x03ff
#define BRPHY1_GPHY_CORE_EXP38_TOTAL_RT_DLY_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP38_TOTAL_RT_DLY_BITS                   10
#define BRPHY1_GPHY_CORE_EXP38_TOTAL_RT_DLY_SHIFT                  0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP42
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP42 :: SERDES_LINK [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_SERDES_LINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_SERDES_LINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x8000,15)
#define BRPHY1_GPHY_CORE_EXP42_SERDES_LINK_MASK                    0x8000
#define BRPHY1_GPHY_CORE_EXP42_SERDES_LINK_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP42_SERDES_LINK_BITS                    1
#define BRPHY1_GPHY_CORE_EXP42_SERDES_LINK_SHIFT                   15

/* BRPHY1_GPHY_CORE :: EXP42 :: SERDES_SPEED [14:13] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_SERDES_SPEED(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x6000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_SERDES_SPEED(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x6000,13)
#define BRPHY1_GPHY_CORE_EXP42_SERDES_SPEED_MASK                   0x6000
#define BRPHY1_GPHY_CORE_EXP42_SERDES_SPEED_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP42_SERDES_SPEED_BITS                   2
#define BRPHY1_GPHY_CORE_EXP42_SERDES_SPEED_SHIFT                  13

/* BRPHY1_GPHY_CORE :: EXP42 :: SERDES_DUPLEX [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_SERDES_DUPLEX(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_SERDES_DUPLEX(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP42_SERDES_DUPLEX_MASK                  0x1000
#define BRPHY1_GPHY_CORE_EXP42_SERDES_DUPLEX_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP42_SERDES_DUPLEX_BITS                  1
#define BRPHY1_GPHY_CORE_EXP42_SERDES_DUPLEX_SHIFT                 12

/* BRPHY1_GPHY_CORE :: EXP42 :: COPPER_LINK [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_COPPER_LINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_COPPER_LINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x800,11)
#define BRPHY1_GPHY_CORE_EXP42_COPPER_LINK_MASK                    0x0800
#define BRPHY1_GPHY_CORE_EXP42_COPPER_LINK_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP42_COPPER_LINK_BITS                    1
#define BRPHY1_GPHY_CORE_EXP42_COPPER_LINK_SHIFT                   11

/* BRPHY1_GPHY_CORE :: EXP42 :: COPPER_SPEED [10:09] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_COPPER_SPEED(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x600,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_COPPER_SPEED(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x600,9)
#define BRPHY1_GPHY_CORE_EXP42_COPPER_SPEED_MASK                   0x0600
#define BRPHY1_GPHY_CORE_EXP42_COPPER_SPEED_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP42_COPPER_SPEED_BITS                   2
#define BRPHY1_GPHY_CORE_EXP42_COPPER_SPEED_SHIFT                  9

/* BRPHY1_GPHY_CORE :: EXP42 :: COPPER_DUPLEX [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_COPPER_DUPLEX(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_COPPER_DUPLEX(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x100,8)
#define BRPHY1_GPHY_CORE_EXP42_COPPER_DUPLEX_MASK                  0x0100
#define BRPHY1_GPHY_CORE_EXP42_COPPER_DUPLEX_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP42_COPPER_DUPLEX_BITS                  1
#define BRPHY1_GPHY_CORE_EXP42_COPPER_DUPLEX_SHIFT                 8

/* BRPHY1_GPHY_CORE :: EXP42 :: COPPER_ENERGY_DETECT [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x80,7)
#define BRPHY1_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_MASK           0x0080
#define BRPHY1_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_ALIGN          0
#define BRPHY1_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_BITS           1
#define BRPHY1_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_SHIFT          7

/* BRPHY1_GPHY_CORE :: EXP42 :: FIBER_SIGNAL_DETECT [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x40,6)
#define BRPHY1_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_MASK            0x0040
#define BRPHY1_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_ALIGN           0
#define BRPHY1_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_BITS            1
#define BRPHY1_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_SHIFT           6

/* BRPHY1_GPHY_CORE :: EXP42 :: SYNC_STATUS [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_SYNC_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_SYNC_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x20,5)
#define BRPHY1_GPHY_CORE_EXP42_SYNC_STATUS_MASK                    0x0020
#define BRPHY1_GPHY_CORE_EXP42_SYNC_STATUS_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP42_SYNC_STATUS_BITS                    1
#define BRPHY1_GPHY_CORE_EXP42_SYNC_STATUS_SHIFT                   5

/* BRPHY1_GPHY_CORE :: EXP42 :: OPERATING_MODE_STATUS [04:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP42,0x1f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP42,0x1f,0)
#define BRPHY1_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_MASK          0x001f
#define BRPHY1_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_ALIGN         0
#define BRPHY1_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_BITS          5
#define BRPHY1_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_SHIFT         0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP5F
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP5F :: PLL_TCLK_OFFSET [15:10] */
#define Wr_BRPHY1_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP5F,0xfc00,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP5F,0xfc00,10)
#define BRPHY1_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_MASK                0xfc00
#define BRPHY1_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_BITS                6
#define BRPHY1_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_SHIFT               10

/* BRPHY1_GPHY_CORE :: EXP5F :: PLL_RCLK_OFFSET [09:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP5F,0x3f0,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP5F,0x3f0,4)
#define BRPHY1_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_MASK                0x03f0
#define BRPHY1_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_BITS                6
#define BRPHY1_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_SHIFT               4

/* BRPHY1_GPHY_CORE :: EXP5F :: PLLTEST_CNT [03:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP5F_PLLTEST_CNT(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP5F,0xc,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP5F_PLLTEST_CNT(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP5F,0xc,2)
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_CNT_MASK                    0x000c
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_CNT_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_CNT_BITS                    2
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_CNT_SHIFT                   2

/* BRPHY1_GPHY_CORE :: EXP5F :: PLLTEST [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP5F_PLLTEST(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP5F,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP5F_PLLTEST(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP5F,0x2,1)
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_MASK                        0x0002
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_BITS                        1
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_SHIFT                       1

/* BRPHY1_GPHY_CORE :: EXP5F :: PLLTEST_EN [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP5F_PLLTEST_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP5F,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP5F_PLLTEST_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP5F,0x1,0)
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_EN_MASK                     0x0001
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_EN_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_EN_BITS                     1
#define BRPHY1_GPHY_CORE_EXP5F_PLLTEST_EN_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP70
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP70 :: reserved0 [15:01] */
#define BRPHY1_GPHY_CORE_EXP70_RESERVED0_MASK                      0xfffe
#define BRPHY1_GPHY_CORE_EXP70_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP70_RESERVED0_BITS                      15
#define BRPHY1_GPHY_CORE_EXP70_RESERVED0_SHIFT                     1

/* BRPHY1_GPHY_CORE :: EXP70 :: SOFT_RESET [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP70_SOFT_RESET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP70,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP70_SOFT_RESET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP70,0x1,0)
#define BRPHY1_GPHY_CORE_EXP70_SOFT_RESET_MASK                     0x0001
#define BRPHY1_GPHY_CORE_EXP70_SOFT_RESET_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP70_SOFT_RESET_BITS                     1
#define BRPHY1_GPHY_CORE_EXP70_SOFT_RESET_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP71
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP71 :: reserved0 [15:14] */
#define BRPHY1_GPHY_CORE_EXP71_RESERVED0_MASK                      0xc000
#define BRPHY1_GPHY_CORE_EXP71_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP71_RESERVED0_BITS                      2
#define BRPHY1_GPHY_CORE_EXP71_RESERVED0_SHIFT                     14

/* BRPHY1_GPHY_CORE :: EXP71 :: SERIAL_LED_EN [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP71,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP71,0x2000,13)
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_EN_MASK                  0x2000
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_EN_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_EN_BITS                  1
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_EN_SHIFT                 13

/* BRPHY1_GPHY_CORE :: EXP71 :: LOW_COST_LED_EN [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP71,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP71,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP71_LOW_COST_LED_EN_MASK                0x1000
#define BRPHY1_GPHY_CORE_EXP71_LOW_COST_LED_EN_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP71_LOW_COST_LED_EN_BITS                1
#define BRPHY1_GPHY_CORE_EXP71_LOW_COST_LED_EN_SHIFT               12

/* BRPHY1_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_6 [11:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP71,0xf00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP71,0xf00,8)
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_MASK               0x0f00
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_BITS               4
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_SHIFT              8

/* BRPHY1_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_5 [07:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP71,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP71,0xf0,4)
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_MASK               0x00f0
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_BITS               4
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_SHIFT              4

/* BRPHY1_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_4 [03:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP71,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP71,0xf,0)
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_MASK               0x000f
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_BITS               4
#define BRPHY1_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP72
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP72 :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_EXP72_RESERVED0_MASK                      0xf000
#define BRPHY1_GPHY_CORE_EXP72_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP72_RESERVED0_BITS                      4
#define BRPHY1_GPHY_CORE_EXP72_RESERVED0_SHIFT                     12

/* BRPHY1_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_3 [11:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP72,0xf00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP72,0xf00,8)
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_MASK               0x0f00
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_BITS               4
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_SHIFT              8

/* BRPHY1_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_2 [07:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP72,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP72,0xf0,4)
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_MASK               0x00f0
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_BITS               4
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_SHIFT              4

/* BRPHY1_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_1 [03:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP72,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP72,0xf,0)
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_MASK               0x000f
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_BITS               4
#define BRPHY1_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP73
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP73 :: reserved0 [15:08] */
#define BRPHY1_GPHY_CORE_EXP73_RESERVED0_MASK                      0xff00
#define BRPHY1_GPHY_CORE_EXP73_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP73_RESERVED0_BITS                      8
#define BRPHY1_GPHY_CORE_EXP73_RESERVED0_SHIFT                     8

/* BRPHY1_GPHY_CORE :: EXP73 :: LED_6_TO_1_COPPER [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP73,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP73,0x80,7)
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_MASK              0x0080
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_BITS              1
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_SHIFT             7

/* BRPHY1_GPHY_CORE :: EXP73 :: LED_5_TO_1_COPPER [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP73,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP73,0x40,6)
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_MASK              0x0040
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_BITS              1
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_SHIFT             6

/* BRPHY1_GPHY_CORE :: EXP73 :: LED_6_TO_0_COPPER [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP73,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP73,0x20,5)
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_MASK              0x0020
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_BITS              1
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_SHIFT             5

/* BRPHY1_GPHY_CORE :: EXP73 :: LED_5_TO_0_COPPER [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP73,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP73,0x10,4)
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_MASK              0x0010
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_ALIGN             0
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_BITS              1
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_SHIFT             4

/* BRPHY1_GPHY_CORE :: EXP73 :: LED_6_TO_1_FIBER [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP73,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP73,0x8,3)
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_MASK               0x0008
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_BITS               1
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_SHIFT              3

/* BRPHY1_GPHY_CORE :: EXP73 :: LED_5_TO_1_FIBER [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP73,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP73,0x4,2)
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_MASK               0x0004
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_BITS               1
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_SHIFT              2

/* BRPHY1_GPHY_CORE :: EXP73 :: LED_6_TO_0_FIBER [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP73,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP73,0x2,1)
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_MASK               0x0002
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_BITS               1
#define BRPHY1_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_SHIFT              1

/* BRPHY1_GPHY_CORE :: EXP73 :: LED_5_TO_0_FIBER [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP73,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP73,0x1,0)
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_MASK               0x0001
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_BITS               1
#define BRPHY1_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP74
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP74 :: LED4_CM_SW_VAL [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP74,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP74,0x8000,15)
#define BRPHY1_GPHY_CORE_EXP74_LED4_CM_SW_VAL_MASK                 0x8000
#define BRPHY1_GPHY_CORE_EXP74_LED4_CM_SW_VAL_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP74_LED4_CM_SW_VAL_BITS                 1
#define BRPHY1_GPHY_CORE_EXP74_LED4_CM_SW_VAL_SHIFT                15

/* BRPHY1_GPHY_CORE :: EXP74 :: LED4_CM_CTRL [14:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP74_LED4_CM_CTRL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP74,0x7000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP74_LED4_CM_CTRL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP74,0x7000,12)
#define BRPHY1_GPHY_CORE_EXP74_LED4_CM_CTRL_MASK                   0x7000
#define BRPHY1_GPHY_CORE_EXP74_LED4_CM_CTRL_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP74_LED4_CM_CTRL_BITS                   3
#define BRPHY1_GPHY_CORE_EXP74_LED4_CM_CTRL_SHIFT                  12

/* BRPHY1_GPHY_CORE :: EXP74 :: LED3_CM_SW_VAL [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP74,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP74,0x800,11)
#define BRPHY1_GPHY_CORE_EXP74_LED3_CM_SW_VAL_MASK                 0x0800
#define BRPHY1_GPHY_CORE_EXP74_LED3_CM_SW_VAL_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP74_LED3_CM_SW_VAL_BITS                 1
#define BRPHY1_GPHY_CORE_EXP74_LED3_CM_SW_VAL_SHIFT                11

/* BRPHY1_GPHY_CORE :: EXP74 :: LED3_CM_CTRL [10:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP74_LED3_CM_CTRL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP74,0x700,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP74_LED3_CM_CTRL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP74,0x700,8)
#define BRPHY1_GPHY_CORE_EXP74_LED3_CM_CTRL_MASK                   0x0700
#define BRPHY1_GPHY_CORE_EXP74_LED3_CM_CTRL_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP74_LED3_CM_CTRL_BITS                   3
#define BRPHY1_GPHY_CORE_EXP74_LED3_CM_CTRL_SHIFT                  8

/* BRPHY1_GPHY_CORE :: EXP74 :: LED2_CM_SW_VAL [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP74,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP74,0x80,7)
#define BRPHY1_GPHY_CORE_EXP74_LED2_CM_SW_VAL_MASK                 0x0080
#define BRPHY1_GPHY_CORE_EXP74_LED2_CM_SW_VAL_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP74_LED2_CM_SW_VAL_BITS                 1
#define BRPHY1_GPHY_CORE_EXP74_LED2_CM_SW_VAL_SHIFT                7

/* BRPHY1_GPHY_CORE :: EXP74 :: LED2_CM_CTRL [06:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP74_LED2_CM_CTRL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP74,0x70,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP74_LED2_CM_CTRL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP74,0x70,4)
#define BRPHY1_GPHY_CORE_EXP74_LED2_CM_CTRL_MASK                   0x0070
#define BRPHY1_GPHY_CORE_EXP74_LED2_CM_CTRL_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP74_LED2_CM_CTRL_BITS                   3
#define BRPHY1_GPHY_CORE_EXP74_LED2_CM_CTRL_SHIFT                  4

/* BRPHY1_GPHY_CORE :: EXP74 :: LED1_CM_SW_VAL [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP74,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP74,0x8,3)
#define BRPHY1_GPHY_CORE_EXP74_LED1_CM_SW_VAL_MASK                 0x0008
#define BRPHY1_GPHY_CORE_EXP74_LED1_CM_SW_VAL_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP74_LED1_CM_SW_VAL_BITS                 1
#define BRPHY1_GPHY_CORE_EXP74_LED1_CM_SW_VAL_SHIFT                3

/* BRPHY1_GPHY_CORE :: EXP74 :: LED1_CM_CTRL [02:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP74_LED1_CM_CTRL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP74,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP74_LED1_CM_CTRL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP74,0x7,0)
#define BRPHY1_GPHY_CORE_EXP74_LED1_CM_CTRL_MASK                   0x0007
#define BRPHY1_GPHY_CORE_EXP74_LED1_CM_CTRL_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXP74_LED1_CM_CTRL_BITS                   3
#define BRPHY1_GPHY_CORE_EXP74_LED1_CM_CTRL_SHIFT                  0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP75
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP75 :: reserved0 [15:10] */
#define BRPHY1_GPHY_CORE_EXP75_RESERVED0_MASK                      0xfc00
#define BRPHY1_GPHY_CORE_EXP75_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP75_RESERVED0_BITS                      6
#define BRPHY1_GPHY_CORE_EXP75_RESERVED0_SHIFT                     10

/* BRPHY1_GPHY_CORE :: EXP75 :: CED_LED_ERR_MASK [09:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP75,0x3ff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP75,0x3ff,0)
#define BRPHY1_GPHY_CORE_EXP75_CED_LED_ERR_MASK_MASK               0x03ff
#define BRPHY1_GPHY_CORE_EXP75_CED_LED_ERR_MASK_ALIGN              0
#define BRPHY1_GPHY_CORE_EXP75_CED_LED_ERR_MASK_BITS               10
#define BRPHY1_GPHY_CORE_EXP75_CED_LED_ERR_MASK_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP78
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP78 :: DAC_ANA_TEST_EN [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP78,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP78,0x8000,15)
#define BRPHY1_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_MASK                0x8000
#define BRPHY1_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_BITS                1
#define BRPHY1_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_SHIFT               15

/* BRPHY1_GPHY_CORE :: EXP78 :: BR_TXPR_EN [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXP78_BR_TXPR_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP78,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXP78_BR_TXPR_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP78,0x4000,14)
#define BRPHY1_GPHY_CORE_EXP78_BR_TXPR_EN_MASK                     0x4000
#define BRPHY1_GPHY_CORE_EXP78_BR_TXPR_EN_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP78_BR_TXPR_EN_BITS                     1
#define BRPHY1_GPHY_CORE_EXP78_BR_TXPR_EN_SHIFT                    14

/* BRPHY1_GPHY_CORE :: EXP78 :: BR_IRP_EN [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXP78_BR_IRP_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP78,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXP78_BR_IRP_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP78,0x2000,13)
#define BRPHY1_GPHY_CORE_EXP78_BR_IRP_EN_MASK                      0x2000
#define BRPHY1_GPHY_CORE_EXP78_BR_IRP_EN_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP78_BR_IRP_EN_BITS                      1
#define BRPHY1_GPHY_CORE_EXP78_BR_IRP_EN_SHIFT                     13

/* BRPHY1_GPHY_CORE :: EXP78 :: PTE_BYPASS_EN [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP78,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP78,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP78_PTE_BYPASS_EN_MASK                  0x1000
#define BRPHY1_GPHY_CORE_EXP78_PTE_BYPASS_EN_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP78_PTE_BYPASS_EN_BITS                  1
#define BRPHY1_GPHY_CORE_EXP78_PTE_BYPASS_EN_SHIFT                 12

/* BRPHY1_GPHY_CORE :: EXP78 :: PTE_DISTORT [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXP78_PTE_DISTORT(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP78,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXP78_PTE_DISTORT(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP78,0x800,11)
#define BRPHY1_GPHY_CORE_EXP78_PTE_DISTORT_MASK                    0x0800
#define BRPHY1_GPHY_CORE_EXP78_PTE_DISTORT_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP78_PTE_DISTORT_BITS                    1
#define BRPHY1_GPHY_CORE_EXP78_PTE_DISTORT_SHIFT                   11

/* BRPHY1_GPHY_CORE :: EXP78 :: LP_SEL [10:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP78_LP_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP78,0x700,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP78_LP_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP78,0x700,8)
#define BRPHY1_GPHY_CORE_EXP78_LP_SEL_MASK                         0x0700
#define BRPHY1_GPHY_CORE_EXP78_LP_SEL_ALIGN                        0
#define BRPHY1_GPHY_CORE_EXP78_LP_SEL_BITS                         3
#define BRPHY1_GPHY_CORE_EXP78_LP_SEL_SHIFT                        8

/* BRPHY1_GPHY_CORE :: EXP78 :: HP_PGA_BYPASS [07:04] */
#define Wr_BRPHY1_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP78,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP78,0xf0,4)
#define BRPHY1_GPHY_CORE_EXP78_HP_PGA_BYPASS_MASK                  0x00f0
#define BRPHY1_GPHY_CORE_EXP78_HP_PGA_BYPASS_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP78_HP_PGA_BYPASS_BITS                  4
#define BRPHY1_GPHY_CORE_EXP78_HP_PGA_BYPASS_SHIFT                 4

/* BRPHY1_GPHY_CORE :: EXP78 :: TDR_GAIN [03:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP78_TDR_GAIN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP78,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP78_TDR_GAIN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP78,0xf,0)
#define BRPHY1_GPHY_CORE_EXP78_TDR_GAIN_MASK                       0x000f
#define BRPHY1_GPHY_CORE_EXP78_TDR_GAIN_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP78_TDR_GAIN_BITS                       4
#define BRPHY1_GPHY_CORE_EXP78_TDR_GAIN_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP7B
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP7B :: I2C_CMD [15:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP7B_I2C_CMD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP7B,0xf000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP7B_I2C_CMD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP7B,0xf000,12)
#define BRPHY1_GPHY_CORE_EXP7B_I2C_CMD_MASK                        0xf000
#define BRPHY1_GPHY_CORE_EXP7B_I2C_CMD_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP7B_I2C_CMD_BITS                        4
#define BRPHY1_GPHY_CORE_EXP7B_I2C_CMD_SHIFT                       12

/* BRPHY1_GPHY_CORE :: EXP7B :: I2C_CTL [11:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP7B_I2C_CTL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP7B,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP7B_I2C_CTL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP7B,0xfff,0)
#define BRPHY1_GPHY_CORE_EXP7B_I2C_CTL_MASK                        0x0fff
#define BRPHY1_GPHY_CORE_EXP7B_I2C_CTL_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP7B_I2C_CTL_BITS                        12
#define BRPHY1_GPHY_CORE_EXP7B_I2C_CTL_SHIFT                       0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP7C
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP7C :: I2C_STATUS [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP7C_I2C_STATUS(x) WriteReg16(BRPHY1_GPHY_CORE_EXP7C,x)
#define Rd_BRPHY1_GPHY_CORE_EXP7C_I2C_STATUS(x) ReadReg16(BRPHY1_GPHY_CORE_EXP7C)
#define BRPHY1_GPHY_CORE_EXP7C_I2C_STATUS_MASK                     0xffff
#define BRPHY1_GPHY_CORE_EXP7C_I2C_STATUS_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP7C_I2C_STATUS_BITS                     16
#define BRPHY1_GPHY_CORE_EXP7C_I2C_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP7F
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP7F :: reserved0 [15:13] */
#define BRPHY1_GPHY_CORE_EXP7F_RESERVED0_MASK                      0xe000
#define BRPHY1_GPHY_CORE_EXP7F_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP7F_RESERVED0_BITS                      3
#define BRPHY1_GPHY_CORE_EXP7F_RESERVED0_SHIFT                     13

/* BRPHY1_GPHY_CORE :: EXP7F :: BR_PSD_PIN_DISABLE [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x1000,12)
#define BRPHY1_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_MASK             0x1000
#define BRPHY1_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_ALIGN            0
#define BRPHY1_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_BITS             1
#define BRPHY1_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_SHIFT            12

/* BRPHY1_GPHY_CORE :: EXP7F :: BR_PSD_OFF [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXP7F_BR_PSD_OFF(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXP7F_BR_PSD_OFF(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x800,11)
#define BRPHY1_GPHY_CORE_EXP7F_BR_PSD_OFF_MASK                     0x0800
#define BRPHY1_GPHY_CORE_EXP7F_BR_PSD_OFF_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP7F_BR_PSD_OFF_BITS                     1
#define BRPHY1_GPHY_CORE_EXP7F_BR_PSD_OFF_SHIFT                    11

/* BRPHY1_GPHY_CORE :: EXP7F :: ECD_DC_OFFSET [10:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x7fc,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x7fc,2)
#define BRPHY1_GPHY_CORE_EXP7F_ECD_DC_OFFSET_MASK                  0x07fc
#define BRPHY1_GPHY_CORE_EXP7F_ECD_DC_OFFSET_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXP7F_ECD_DC_OFFSET_BITS                  9
#define BRPHY1_GPHY_CORE_EXP7F_ECD_DC_OFFSET_SHIFT                 2

/* BRPHY1_GPHY_CORE :: EXP7F :: FIBER_UNIDIR_OV [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x2,1)
#define BRPHY1_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_MASK                0x0002
#define BRPHY1_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_BITS                1
#define BRPHY1_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_SHIFT               1

/* BRPHY1_GPHY_CORE :: EXP7F :: MACSEC_EN [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP7F_MACSEC_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP7F_MACSEC_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP7F,0x1,0)
#define BRPHY1_GPHY_CORE_EXP7F_MACSEC_EN_MASK                      0x0001
#define BRPHY1_GPHY_CORE_EXP7F_MACSEC_EN_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP7F_MACSEC_EN_BITS                      1
#define BRPHY1_GPHY_CORE_EXP7F_MACSEC_EN_SHIFT                     0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: ALIAS_18
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: ALIAS_18 :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_ALIAS_18_RESERVED0_MASK                   0xf000
#define BRPHY1_GPHY_CORE_ALIAS_18_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_ALIAS_18_RESERVED0_BITS                   4
#define BRPHY1_GPHY_CORE_ALIAS_18_RESERVED0_SHIFT                  12

/* BRPHY1_GPHY_CORE :: ALIAS_18 :: ALIAS [11:00] */
#define Wr_BRPHY1_GPHY_CORE_ALIAS_18_ALIAS(x) WriteRegBits16(BRPHY1_GPHY_CORE_ALIAS_18,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_ALIAS_18_ALIAS(x) ReadRegBits16(BRPHY1_GPHY_CORE_ALIAS_18,0xfff,0)
#define BRPHY1_GPHY_CORE_ALIAS_18_ALIAS_MASK                       0x0fff
#define BRPHY1_GPHY_CORE_ALIAS_18_ALIAS_ALIGN                      0
#define BRPHY1_GPHY_CORE_ALIAS_18_ALIAS_BITS                       12
#define BRPHY1_GPHY_CORE_ALIAS_18_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: ALIAS_19
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: ALIAS_19 :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_ALIAS_19_RESERVED0_MASK                   0xf000
#define BRPHY1_GPHY_CORE_ALIAS_19_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_ALIAS_19_RESERVED0_BITS                   4
#define BRPHY1_GPHY_CORE_ALIAS_19_RESERVED0_SHIFT                  12

/* BRPHY1_GPHY_CORE :: ALIAS_19 :: ALIAS [11:00] */
#define Wr_BRPHY1_GPHY_CORE_ALIAS_19_ALIAS(x) WriteRegBits16(BRPHY1_GPHY_CORE_ALIAS_19,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_ALIAS_19_ALIAS(x) ReadRegBits16(BRPHY1_GPHY_CORE_ALIAS_19,0xfff,0)
#define BRPHY1_GPHY_CORE_ALIAS_19_ALIAS_MASK                       0x0fff
#define BRPHY1_GPHY_CORE_ALIAS_19_ALIAS_ALIGN                      0
#define BRPHY1_GPHY_CORE_ALIAS_19_ALIAS_BITS                       12
#define BRPHY1_GPHY_CORE_ALIAS_19_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: ALIAS_1a
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: ALIAS_1a :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_ALIAS_1A_RESERVED0_MASK                   0xf000
#define BRPHY1_GPHY_CORE_ALIAS_1A_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_ALIAS_1A_RESERVED0_BITS                   4
#define BRPHY1_GPHY_CORE_ALIAS_1A_RESERVED0_SHIFT                  12

/* BRPHY1_GPHY_CORE :: ALIAS_1a :: ALIAS [11:00] */
#define Wr_BRPHY1_GPHY_CORE_ALIAS_1a_ALIAS(x) WriteRegBits16(BRPHY1_GPHY_CORE_ALIAS_1A,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_ALIAS_1a_ALIAS(x) ReadRegBits16(BRPHY1_GPHY_CORE_ALIAS_1A,0xfff,0)
#define BRPHY1_GPHY_CORE_ALIAS_1A_ALIAS_MASK                       0x0fff
#define BRPHY1_GPHY_CORE_ALIAS_1A_ALIAS_ALIGN                      0
#define BRPHY1_GPHY_CORE_ALIAS_1A_ALIAS_BITS                       12
#define BRPHY1_GPHY_CORE_ALIAS_1A_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: ALIAS_1b
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: ALIAS_1b :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_ALIAS_1B_RESERVED0_MASK                   0xf000
#define BRPHY1_GPHY_CORE_ALIAS_1B_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_ALIAS_1B_RESERVED0_BITS                   4
#define BRPHY1_GPHY_CORE_ALIAS_1B_RESERVED0_SHIFT                  12

/* BRPHY1_GPHY_CORE :: ALIAS_1b :: ALIAS [11:00] */
#define Wr_BRPHY1_GPHY_CORE_ALIAS_1b_ALIAS(x) WriteRegBits16(BRPHY1_GPHY_CORE_ALIAS_1B,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_ALIAS_1b_ALIAS(x) ReadRegBits16(BRPHY1_GPHY_CORE_ALIAS_1B,0xfff,0)
#define BRPHY1_GPHY_CORE_ALIAS_1B_ALIAS_MASK                       0x0fff
#define BRPHY1_GPHY_CORE_ALIAS_1B_ALIAS_ALIGN                      0
#define BRPHY1_GPHY_CORE_ALIAS_1B_ALIAS_BITS                       12
#define BRPHY1_GPHY_CORE_ALIAS_1B_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: ALIAS_1c
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: ALIAS_1c :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_ALIAS_1C_RESERVED0_MASK                   0xf000
#define BRPHY1_GPHY_CORE_ALIAS_1C_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_ALIAS_1C_RESERVED0_BITS                   4
#define BRPHY1_GPHY_CORE_ALIAS_1C_RESERVED0_SHIFT                  12

/* BRPHY1_GPHY_CORE :: ALIAS_1c :: ALIAS [11:00] */
#define Wr_BRPHY1_GPHY_CORE_ALIAS_1c_ALIAS(x) WriteRegBits16(BRPHY1_GPHY_CORE_ALIAS_1C,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_ALIAS_1c_ALIAS(x) ReadRegBits16(BRPHY1_GPHY_CORE_ALIAS_1C,0xfff,0)
#define BRPHY1_GPHY_CORE_ALIAS_1C_ALIAS_MASK                       0x0fff
#define BRPHY1_GPHY_CORE_ALIAS_1C_ALIAS_ALIGN                      0
#define BRPHY1_GPHY_CORE_ALIAS_1C_ALIAS_BITS                       12
#define BRPHY1_GPHY_CORE_ALIAS_1C_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: ALIAS_1d
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: ALIAS_1d :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_ALIAS_1D_RESERVED0_MASK                   0xf000
#define BRPHY1_GPHY_CORE_ALIAS_1D_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_ALIAS_1D_RESERVED0_BITS                   4
#define BRPHY1_GPHY_CORE_ALIAS_1D_RESERVED0_SHIFT                  12

/* BRPHY1_GPHY_CORE :: ALIAS_1d :: ALIAS [11:00] */
#define Wr_BRPHY1_GPHY_CORE_ALIAS_1d_ALIAS(x) WriteRegBits16(BRPHY1_GPHY_CORE_ALIAS_1D,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_ALIAS_1d_ALIAS(x) ReadRegBits16(BRPHY1_GPHY_CORE_ALIAS_1D,0xfff,0)
#define BRPHY1_GPHY_CORE_ALIAS_1D_ALIAS_MASK                       0x0fff
#define BRPHY1_GPHY_CORE_ALIAS_1D_ALIAS_ALIGN                      0
#define BRPHY1_GPHY_CORE_ALIAS_1D_ALIAS_BITS                       12
#define BRPHY1_GPHY_CORE_ALIAS_1D_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: REG_MAP_CTL
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: REG_MAP_CTL :: REG_LEGACY_EN [15:15] */
#define Wr_BRPHY1_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_REG_MAP_CTL,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_REG_MAP_CTL,0x8000,15)
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_MASK            0x8000
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_BITS            1
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_SHIFT           15

/* BRPHY1_GPHY_CORE :: REG_MAP_CTL :: ALIAS_MODE [14:13] */
#define Wr_BRPHY1_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_REG_MAP_CTL,0x6000,13,x)
#define Rd_BRPHY1_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_REG_MAP_CTL,0x6000,13)
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_MASK               0x6000
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_ALIGN              0
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_BITS               2
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_SHIFT              13

/* BRPHY1_GPHY_CORE :: REG_MAP_CTL :: reserved0 [12:12] */
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_RESERVED0_MASK                0x1000
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_RESERVED0_ALIGN               0
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_RESERVED0_BITS                1
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_RESERVED0_SHIFT               12

/* BRPHY1_GPHY_CORE :: REG_MAP_CTL :: RANGE_OFFSET [11:00] */
#define Wr_BRPHY1_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) WriteRegBits16(BRPHY1_GPHY_CORE_REG_MAP_CTL,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) ReadRegBits16(BRPHY1_GPHY_CORE_REG_MAP_CTL,0xfff,0)
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_MASK             0x0fff
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_ALIGN            0
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_BITS             12
#define BRPHY1_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_SHIFT            0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP98
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP98 :: reserved0 [15:11] */
#define BRPHY1_GPHY_CORE_EXP98_RESERVED0_MASK                      0xf800
#define BRPHY1_GPHY_CORE_EXP98_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXP98_RESERVED0_BITS                      5
#define BRPHY1_GPHY_CORE_EXP98_RESERVED0_SHIFT                     11

/* BRPHY1_GPHY_CORE :: EXP98 :: RC_CAL [10:06] */
#define Wr_BRPHY1_GPHY_CORE_EXP98_RC_CAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP98,0x7c0,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXP98_RC_CAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP98,0x7c0,6)
#define BRPHY1_GPHY_CORE_EXP98_RC_CAL_MASK                         0x07c0
#define BRPHY1_GPHY_CORE_EXP98_RC_CAL_ALIGN                        0
#define BRPHY1_GPHY_CORE_EXP98_RC_CAL_BITS                         5
#define BRPHY1_GPHY_CORE_EXP98_RC_CAL_SHIFT                        6

/* BRPHY1_GPHY_CORE :: EXP98 :: R_CAL [05:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP98_R_CAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP98,0x3e,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP98_R_CAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP98,0x3e,1)
#define BRPHY1_GPHY_CORE_EXP98_R_CAL_MASK                          0x003e
#define BRPHY1_GPHY_CORE_EXP98_R_CAL_ALIGN                         0
#define BRPHY1_GPHY_CORE_EXP98_R_CAL_BITS                          5
#define BRPHY1_GPHY_CORE_EXP98_R_CAL_SHIFT                         1

/* BRPHY1_GPHY_CORE :: EXP98 :: CAL_DONE [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP98_CAL_DONE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP98,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP98_CAL_DONE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP98,0x1,0)
#define BRPHY1_GPHY_CORE_EXP98_CAL_DONE_MASK                       0x0001
#define BRPHY1_GPHY_CORE_EXP98_CAL_DONE_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP98_CAL_DONE_BITS                       1
#define BRPHY1_GPHY_CORE_EXP98_CAL_DONE_SHIFT                      0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXP9C
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXP9C :: MII_REG1C_BNK1 [15:12] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0xf000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0xf000,12)
#define BRPHY1_GPHY_CORE_EXP9C_MII_REG1C_BNK1_MASK                 0xf000
#define BRPHY1_GPHY_CORE_EXP9C_MII_REG1C_BNK1_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP9C_MII_REG1C_BNK1_BITS                 4
#define BRPHY1_GPHY_CORE_EXP9C_MII_REG1C_BNK1_SHIFT                12

/* BRPHY1_GPHY_CORE :: EXP9C :: RSMII_LOAD_XMT [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x800,11)
#define BRPHY1_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_MASK                 0x0800
#define BRPHY1_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_BITS                 1
#define BRPHY1_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_SHIFT                11

/* BRPHY1_GPHY_CORE :: EXP9C :: FIFO_OV_UN [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_FIFO_OV_UN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_FIFO_OV_UN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x400,10)
#define BRPHY1_GPHY_CORE_EXP9C_FIFO_OV_UN_MASK                     0x0400
#define BRPHY1_GPHY_CORE_EXP9C_FIFO_OV_UN_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP9C_FIFO_OV_UN_BITS                     1
#define BRPHY1_GPHY_CORE_EXP9C_FIFO_OV_UN_SHIFT                    10

/* BRPHY1_GPHY_CORE :: EXP9C :: TEST_EN [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_TEST_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_TEST_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x200,9)
#define BRPHY1_GPHY_CORE_EXP9C_TEST_EN_MASK                        0x0200
#define BRPHY1_GPHY_CORE_EXP9C_TEST_EN_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXP9C_TEST_EN_BITS                        1
#define BRPHY1_GPHY_CORE_EXP9C_TEST_EN_SHIFT                       9

/* BRPHY1_GPHY_CORE :: EXP9C :: PTEST [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_PTEST(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_PTEST(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x100,8)
#define BRPHY1_GPHY_CORE_EXP9C_PTEST_MASK                          0x0100
#define BRPHY1_GPHY_CORE_EXP9C_PTEST_ALIGN                         0
#define BRPHY1_GPHY_CORE_EXP9C_PTEST_BITS                          1
#define BRPHY1_GPHY_CORE_EXP9C_PTEST_SHIFT                         8

/* BRPHY1_GPHY_CORE :: EXP9C :: EXRMIIFE [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_EXRMIIFE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_EXRMIIFE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x80,7)
#define BRPHY1_GPHY_CORE_EXP9C_EXRMIIFE_MASK                       0x0080
#define BRPHY1_GPHY_CORE_EXP9C_EXRMIIFE_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXP9C_EXRMIIFE_BITS                       1
#define BRPHY1_GPHY_CORE_EXP9C_EXRMIIFE_SHIFT                      7

/* BRPHY1_GPHY_CORE :: EXP9C :: FIFO_SIZE_CNTL [06:03] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x78,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x78,3)
#define BRPHY1_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_MASK                 0x0078
#define BRPHY1_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_ALIGN                0
#define BRPHY1_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_BITS                 4
#define BRPHY1_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_SHIFT                3

/* BRPHY1_GPHY_CORE :: EXP9C :: BIG_FIFO_EN [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x4,2)
#define BRPHY1_GPHY_CORE_EXP9C_BIG_FIFO_EN_MASK                    0x0004
#define BRPHY1_GPHY_CORE_EXP9C_BIG_FIFO_EN_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXP9C_BIG_FIFO_EN_BITS                    1
#define BRPHY1_GPHY_CORE_EXP9C_BIG_FIFO_EN_SHIFT                   2

/* BRPHY1_GPHY_CORE :: EXP9C :: SMII_S3MII_MODE [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x2,1)
#define BRPHY1_GPHY_CORE_EXP9C_SMII_S3MII_MODE_MASK                0x0002
#define BRPHY1_GPHY_CORE_EXP9C_SMII_S3MII_MODE_ALIGN               0
#define BRPHY1_GPHY_CORE_EXP9C_SMII_S3MII_MODE_BITS                1
#define BRPHY1_GPHY_CORE_EXP9C_SMII_S3MII_MODE_SHIFT               1

/* BRPHY1_GPHY_CORE :: EXP9C :: SSSMII_DIS [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXP9C_SSSMII_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXP9C_SSSMII_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXP9C,0x1,0)
#define BRPHY1_GPHY_CORE_EXP9C_SSSMII_DIS_MASK                     0x0001
#define BRPHY1_GPHY_CORE_EXP9C_SSSMII_DIS_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXP9C_SSSMII_DIS_BITS                     1
#define BRPHY1_GPHY_CORE_EXP9C_SSSMII_DIS_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: BT_LINK_FIX
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: BT_LINK_FIX :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RESERVED0_MASK                0x8000
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RESERVED0_ALIGN               0
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RESERVED0_BITS                1
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RESERVED0_SHIFT               15

/* BRPHY1_GPHY_CORE :: BT_LINK_FIX :: rxc_byp_rclk_dll_div2 [14:14] */
#define Wr_BRPHY1_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) WriteRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) ReadRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0x4000,14)
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_MASK    0x4000
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_ALIGN   0
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_BITS    1
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_SHIFT   14

/* BRPHY1_GPHY_CORE :: BT_LINK_FIX :: rxc_shamoo_tst_en [13:13] */
#define Wr_BRPHY1_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) WriteRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) ReadRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0x2000,13)
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_MASK        0x2000
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_ALIGN       0
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_BITS        1
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_SHIFT       13

/* BRPHY1_GPHY_CORE :: BT_LINK_FIX :: sig_10bt_upp_limit [12:08] */
#define Wr_BRPHY1_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) WriteRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0x1f00,8,x)
#define Rd_BRPHY1_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) ReadRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0x1f00,8)
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_MASK       0x1f00
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_ALIGN      0
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_BITS       5
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_SHIFT      8

/* BRPHY1_GPHY_CORE :: BT_LINK_FIX :: threshold_2mhz [07:01] */
#define Wr_BRPHY1_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) WriteRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0xfe,1,x)
#define Rd_BRPHY1_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) ReadRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0xfe,1)
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_MASK           0x00fe
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_ALIGN          0
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_BITS           7
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_SHIFT          1

/* BRPHY1_GPHY_CORE :: BT_LINK_FIX :: break_link10bt_disable [00:00] */
#define Wr_BRPHY1_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) WriteRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) ReadRegBits16(BRPHY1_GPHY_CORE_BT_LINK_FIX,0x1,0)
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_MASK   0x0001
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_ALIGN  0
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_BITS   1
#define BRPHY1_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_SHIFT  0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SYNCE_PLUS_DBG
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_DBG [15:02] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_MASK             0xfffc
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_ALIGN            0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_BITS             14
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_SHIFT            2

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_BRUTEFORCE_TM [01:01] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_MASK   0x0002
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_ALIGN  0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_BITS   1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_SHIFT  1

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_HSTIMEOUT_CTL [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_MASK   0x0001
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_ALIGN  0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_BITS   1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_SHIFT  0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: SYNCE_PLUS
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: TIMING_CONFIG [15:15] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x8000,15)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_MASK             0x8000
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_ALIGN            0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_BITS             1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_SHIFT            15

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_ONGOING [14:14] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x4000,14)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_MASK     0x4000
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_ALIGN    0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_BITS     1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_SHIFT    14

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: SYNCE_AUTO_ACK [13:13] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x2000,13)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_MASK            0x2000
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_ALIGN           0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_BITS            1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_SHIFT           13

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: SYNCE_WAIT_FOR_IDLE [12:12] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x1000,12)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_MASK       0x1000
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_ALIGN      0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_BITS       1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_SHIFT      12

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_COMPLETE [11:11] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x800,11)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_MASK    0x0800
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_ALIGN   0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_BITS    1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_SHIFT   11

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_PENDING [10:10] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x400,10)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_MASK     0x0400
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_ALIGN    0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_BITS     1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_SHIFT    10

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ERROR_STATUS [09:08] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x300,8,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x300,8)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_MASK        0x0300
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_ALIGN       0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_BITS        2
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_SHIFT       8

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_FAIL [07:07] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x80,7)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_MASK        0x0080
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_ALIGN       0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_BITS        1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_SHIFT       7

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: SYNCE_FTIMEOUT_CTL [06:06] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x40,6)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_MASK        0x0040
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_ALIGN       0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_BITS        1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_SHIFT       6

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: SYNCE_DBG_MUX_CTL [05:04] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x30,4,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x30,4)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_MASK         0x0030
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_ALIGN        0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_BITS         2
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_SHIFT        4

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: SYNCE_INTERRUPT_MASK [03:02] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0xc,2,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0xc,2)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_MASK      0x000c
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_ALIGN     0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_BITS      2
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_SHIFT     2

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: SYNCE_TIMING_SWITCH_START [01:01] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x2,1)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_MASK 0x0002
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_ALIGN 0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_BITS 1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_SHIFT 1

/* BRPHY1_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ENABLE [00:00] */
#define Wr_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_SYNCE_PLUS,0x1,0)
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_MASK              0x0001
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_ALIGN             0
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_BITS              1
#define BRPHY1_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_SHIFT             0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPA8
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPA8 :: ADAPTIVE_BIAS_CTRL [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) WriteReg16(BRPHY1_GPHY_CORE_EXPA8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) ReadReg16(BRPHY1_GPHY_CORE_EXPA8)
#define BRPHY1_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_MASK             0xffff
#define BRPHY1_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_BITS             16
#define BRPHY1_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_SHIFT            0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPA9
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPA9 :: SPARE_REG [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPA9_SPARE_REG(x) WriteReg16(BRPHY1_GPHY_CORE_EXPA9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPA9_SPARE_REG(x) ReadReg16(BRPHY1_GPHY_CORE_EXPA9)
#define BRPHY1_GPHY_CORE_EXPA9_SPARE_REG_MASK                      0xffff
#define BRPHY1_GPHY_CORE_EXPA9_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPA9_SPARE_REG_BITS                      16
#define BRPHY1_GPHY_CORE_EXPA9_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPAA
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPAA :: STATISTIC_TIMER_12HOURS_LPI [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) WriteReg16(BRPHY1_GPHY_CORE_EXPAA,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) ReadReg16(BRPHY1_GPHY_CORE_EXPAA)
#define BRPHY1_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_MASK    0xffff
#define BRPHY1_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_ALIGN   0
#define BRPHY1_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_BITS    16
#define BRPHY1_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_SHIFT   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPAB
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPAB :: STATISTIC_TIMER_12HOURS_LOCAL [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) WriteReg16(BRPHY1_GPHY_CORE_EXPAB,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) ReadReg16(BRPHY1_GPHY_CORE_EXPAB)
#define BRPHY1_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_MASK  0xffff
#define BRPHY1_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_ALIGN 0
#define BRPHY1_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_BITS  16
#define BRPHY1_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_SHIFT 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPAC
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPAC :: STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY1_GPHY_CORE_EXPAC,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY1_GPHY_CORE_EXPAC)
#define BRPHY1_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY1_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY1_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY1_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPAD
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPAD :: STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY1_GPHY_CORE_EXPAD,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY1_GPHY_CORE_EXPAD)
#define BRPHY1_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY1_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY1_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY1_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPAE
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPAE :: SPARE_REG [15:09] */
#define Wr_BRPHY1_GPHY_CORE_EXPAE_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAE,0xfe00,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAE_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAE,0xfe00,9)
#define BRPHY1_GPHY_CORE_EXPAE_SPARE_REG_MASK                      0xfe00
#define BRPHY1_GPHY_CORE_EXPAE_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPAE_SPARE_REG_BITS                      7
#define BRPHY1_GPHY_CORE_EXPAE_SPARE_REG_SHIFT                     9

/* BRPHY1_GPHY_CORE :: EXPAE :: TXBIAS_VAL2 [08:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAE,0x1e0,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAE,0x1e0,5)
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL2_MASK                    0x01e0
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL2_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL2_BITS                    4
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL2_SHIFT                   5

/* BRPHY1_GPHY_CORE :: EXPAE :: TXBIAS_VAL1 [04:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAE,0x1e,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAE,0x1e,1)
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL1_MASK                    0x001e
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL1_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL1_BITS                    4
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_VAL1_SHIFT                   1

/* BRPHY1_GPHY_CORE :: EXPAE :: TXBIAS_PLUS_MODE [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAE,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAE,0x1,0)
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_MASK               0x0001
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_BITS               1
#define BRPHY1_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPAF
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPAF :: STATISTIC_1000BT_MODE [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x8000,15)
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_MASK          0x8000
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_ALIGN         0
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_BITS          1
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_SHIFT         15

/* BRPHY1_GPHY_CORE :: EXPAF :: STATISTIC_UPPER_16BITS_SEL [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x4000,14)
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_MASK     0x4000
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_ALIGN    0
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_BITS     1
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_SHIFT    14

/* BRPHY1_GPHY_CORE :: EXPAF :: STATISTIC_SATURATE_MODE [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x2000,13)
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_MASK        0x2000
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_ALIGN       0
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_BITS        1
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_SHIFT       13

/* BRPHY1_GPHY_CORE :: EXPAF :: STATISTIC_ACCESS_MODE [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_MASK          0x1000
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_ALIGN         0
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_BITS          1
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_SHIFT         12

/* BRPHY1_GPHY_CORE :: EXPAF :: SPARE_REG [11:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0xfe0,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0xfe0,5)
#define BRPHY1_GPHY_CORE_EXPAF_SPARE_REG_MASK                      0x0fe0
#define BRPHY1_GPHY_CORE_EXPAF_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPAF_SPARE_REG_BITS                      7
#define BRPHY1_GPHY_CORE_EXPAF_SPARE_REG_SHIFT                     5

/* BRPHY1_GPHY_CORE :: EXPAF :: EEE_REM_RCVR_STATUS_DIS [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x10,4)
#define BRPHY1_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_MASK        0x0010
#define BRPHY1_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY1_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_BITS        1
#define BRPHY1_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_SHIFT       4

/* BRPHY1_GPHY_CORE :: EXPAF :: EEE_LOC_RCVR_STATUS_DIS [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x8,3)
#define BRPHY1_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_MASK        0x0008
#define BRPHY1_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY1_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_BITS        1
#define BRPHY1_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_SHIFT       3

/* BRPHY1_GPHY_CORE :: EXPAF :: STATISTIC_ADAPTX_EN [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x4,2)
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_MASK            0x0004
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_ALIGN           0
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_BITS            1
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_SHIFT           2

/* BRPHY1_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_RESET [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x2,1)
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_MASK       0x0002
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_ALIGN      0
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_BITS       1
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_SHIFT      1

/* BRPHY1_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_ENABLE [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPAF,0x1,0)
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_MASK      0x0001
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_ALIGN     0
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_BITS      1
#define BRPHY1_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_SHIFT     0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPB0
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPB0 :: BIAS_CTL_0 [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPB0_BIAS_CTL_0(x) WriteReg16(BRPHY1_GPHY_CORE_EXPB0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPB0_BIAS_CTL_0(x) ReadReg16(BRPHY1_GPHY_CORE_EXPB0)
#define BRPHY1_GPHY_CORE_EXPB0_BIAS_CTL_0_MASK                     0xffff
#define BRPHY1_GPHY_CORE_EXPB0_BIAS_CTL_0_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPB0_BIAS_CTL_0_BITS                     16
#define BRPHY1_GPHY_CORE_EXPB0_BIAS_CTL_0_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPB1
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPB1 :: BIAS_CTL_1 [15:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPB1_BIAS_CTL_1(x) WriteReg16(BRPHY1_GPHY_CORE_EXPB1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPB1_BIAS_CTL_1(x) ReadReg16(BRPHY1_GPHY_CORE_EXPB1)
#define BRPHY1_GPHY_CORE_EXPB1_BIAS_CTL_1_MASK                     0xffff
#define BRPHY1_GPHY_CORE_EXPB1_BIAS_CTL_1_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPB1_BIAS_CTL_1_BITS                     16
#define BRPHY1_GPHY_CORE_EXPB1_BIAS_CTL_1_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPB2
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPB2 :: CLK200_SEL_OV [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPB2,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPB2,0x8000,15)
#define BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_OV_MASK                  0x8000
#define BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_OV_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_OV_BITS                  1
#define BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_OV_SHIFT                 15

/* BRPHY1_GPHY_CORE :: EXPB2 :: CLK200_SEL [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPB2,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPB2,0x4000,14)
#define BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_MASK                     0x4000
#define BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_BITS                     1
#define BRPHY1_GPHY_CORE_EXPB2_CLK200_SEL_SHIFT                    14

/* BRPHY1_GPHY_CORE :: EXPB2 :: CK25_SEL [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPB2_CK25_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPB2,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPB2_CK25_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPB2,0x2000,13)
#define BRPHY1_GPHY_CORE_EXPB2_CK25_SEL_MASK                       0x2000
#define BRPHY1_GPHY_CORE_EXPB2_CK25_SEL_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXPB2_CK25_SEL_BITS                       1
#define BRPHY1_GPHY_CORE_EXPB2_CK25_SEL_SHIFT                      13

/* BRPHY1_GPHY_CORE :: EXPB2 :: REG_B2_SPARE [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPB2_REG_B2_SPARE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPB2,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPB2_REG_B2_SPARE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPB2,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPB2_REG_B2_SPARE_MASK                   0x1000
#define BRPHY1_GPHY_CORE_EXPB2_REG_B2_SPARE_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPB2_REG_B2_SPARE_BITS                   1
#define BRPHY1_GPHY_CORE_EXPB2_REG_B2_SPARE_SHIFT                  12

/* BRPHY1_GPHY_CORE :: EXPB2 :: I_RC_OFFSET_PHY [11:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPB2,0xf00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPB2,0xf00,8)
#define BRPHY1_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_MASK                0x0f00
#define BRPHY1_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_BITS                4
#define BRPHY1_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_SHIFT               8

/* BRPHY1_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_1000_100 [07:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPB2,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPB2,0xf0,4)
#define BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_MASK        0x00f0
#define BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_ALIGN       0
#define BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_BITS        4
#define BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_SHIFT       4

/* BRPHY1_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_10 [03:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPB2,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPB2,0xf,0)
#define BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_MASK              0x000f
#define BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_BITS              4
#define BRPHY1_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_SHIFT             0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE3
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE3,0xff00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE3,0xff00,8)
#define BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_100_MASK                 0xff00
#define BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_100_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_100_BITS                 8
#define BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_100_SHIFT                8

/* BRPHY1_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE3,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE3,0xff,0)
#define BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_BITS                8
#define BRPHY1_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE4
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE4 :: TX_PCS_SOP_TSYNC_ERR [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE4,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE4,0x8000,15)
#define BRPHY1_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_MASK           0x8000
#define BRPHY1_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_BITS           1
#define BRPHY1_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_SHIFT          15

/* BRPHY1_GPHY_CORE :: EXPE4 :: reserved0 [14:12] */
#define BRPHY1_GPHY_CORE_EXPE4_RESERVED0_MASK                      0x7000
#define BRPHY1_GPHY_CORE_EXPE4_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPE4_RESERVED0_BITS                      3
#define BRPHY1_GPHY_CORE_EXPE4_RESERVED0_SHIFT                     12

/* BRPHY1_GPHY_CORE :: EXPE4 :: TX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE4,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE4,0xfff,0)
#define BRPHY1_GPHY_CORE_EXPE4_TX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY1_GPHY_CORE_EXPE4_TX_PCS_DLY_10_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXPE4_TX_PCS_DLY_10_BITS                  12
#define BRPHY1_GPHY_CORE_EXPE4_TX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE5
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE5,0xff00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE5,0xff00,8)
#define BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_BITS               8
#define BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_SHIFT              8

/* BRPHY1_GPHY_CORE :: EXPE5 :: reserved0 [07:07] */
#define BRPHY1_GPHY_CORE_EXPE5_RESERVED0_MASK                      0x0080
#define BRPHY1_GPHY_CORE_EXPE5_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPE5_RESERVED0_BITS                      1
#define BRPHY1_GPHY_CORE_EXPE5_RESERVED0_SHIFT                     7

/* BRPHY1_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE5,0x7f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE5,0x7f,0)
#define BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_BITS               7
#define BRPHY1_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE6
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE6,0xff00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE6,0xff00,8)
#define BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_100_MASK                 0xff00
#define BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_100_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_100_BITS                 8
#define BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_100_SHIFT                8

/* BRPHY1_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE6,0xff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE6,0xff,0)
#define BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_BITS                8
#define BRPHY1_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE7
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE7 :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_EXPE7_RESERVED0_MASK                      0xf000
#define BRPHY1_GPHY_CORE_EXPE7_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPE7_RESERVED0_BITS                      4
#define BRPHY1_GPHY_CORE_EXPE7_RESERVED0_SHIFT                     12

/* BRPHY1_GPHY_CORE :: EXPE7 :: RX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE7,0xfff,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE7,0xfff,0)
#define BRPHY1_GPHY_CORE_EXPE7_RX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY1_GPHY_CORE_EXPE7_RX_PCS_DLY_10_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXPE7_RX_PCS_DLY_10_BITS                  12
#define BRPHY1_GPHY_CORE_EXPE7_RX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE8
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE8,0xff00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE8,0xff00,8)
#define BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_BITS               8
#define BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_SHIFT              8

/* BRPHY1_GPHY_CORE :: EXPE8 :: reserved0 [07:07] */
#define BRPHY1_GPHY_CORE_EXPE8_RESERVED0_MASK                      0x0080
#define BRPHY1_GPHY_CORE_EXPE8_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPE8_RESERVED0_BITS                      1
#define BRPHY1_GPHY_CORE_EXPE8_RESERVED0_SHIFT                     7

/* BRPHY1_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE8,0x7f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE8,0x7f,0)
#define BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_BITS               7
#define BRPHY1_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE9
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE9 :: reserved0 [15:14] */
#define BRPHY1_GPHY_CORE_EXPE9_RESERVED0_MASK                      0xc000
#define BRPHY1_GPHY_CORE_EXPE9_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPE9_RESERVED0_BITS                      2
#define BRPHY1_GPHY_CORE_EXPE9_RESERVED0_SHIFT                     14

/* BRPHY1_GPHY_CORE :: EXPE9 :: P1588_TX_DLY_CYCLE [13:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE9,0x3f00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE9,0x3f00,8)
#define BRPHY1_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_MASK             0x3f00
#define BRPHY1_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_BITS             6
#define BRPHY1_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_SHIFT            8

/* BRPHY1_GPHY_CORE :: EXPE9 :: reserved1 [07:06] */
#define BRPHY1_GPHY_CORE_EXPE9_RESERVED1_MASK                      0x00c0
#define BRPHY1_GPHY_CORE_EXPE9_RESERVED1_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPE9_RESERVED1_BITS                      2
#define BRPHY1_GPHY_CORE_EXPE9_RESERVED1_SHIFT                     6

/* BRPHY1_GPHY_CORE :: EXPE9 :: P1588_RX_DLY_CYCLE [05:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE9,0x3f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE9,0x3f,0)
#define BRPHY1_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_MASK             0x003f
#define BRPHY1_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_BITS             6
#define BRPHY1_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_SHIFT            0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE0
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_10 [15:10] */
#define Wr_BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE0,0xfc00,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE0,0xfc00,10)
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_MASK              0xfc00
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_BITS              6
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_SHIFT             10

/* BRPHY1_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_100 [09:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE0,0x3e0,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE0,0x3e0,5)
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_MASK             0x03e0
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_BITS             5
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_SHIFT            5

/* BRPHY1_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_1000 [04:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE0,0x1f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE0,0x1f,0)
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_MASK            0x001f
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_ALIGN           0
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_BITS            5
#define BRPHY1_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_SHIFT           0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE1
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE1 :: reserved0 [15:12] */
#define BRPHY1_GPHY_CORE_EXPE1_RESERVED0_MASK                      0xf000
#define BRPHY1_GPHY_CORE_EXPE1_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPE1_RESERVED0_BITS                      4
#define BRPHY1_GPHY_CORE_EXPE1_RESERVED0_SHIFT                     12

/* BRPHY1_GPHY_CORE :: EXPE1 :: RX_PMA_PMD_DLY_FIBER [11:06] */
#define Wr_BRPHY1_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE1,0xfc0,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE1,0xfc0,6)
#define BRPHY1_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_MASK           0x0fc0
#define BRPHY1_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY1_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_SHIFT          6

/* BRPHY1_GPHY_CORE :: EXPE1 :: TX_PMA_PMD_DLY_FIBER [05:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE1,0x3f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE1,0x3f,0)
#define BRPHY1_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_MASK           0x003f
#define BRPHY1_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY1_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_SHIFT          0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPE2
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPE2 :: reserved0 [15:14] */
#define BRPHY1_GPHY_CORE_EXPE2_RESERVED0_MASK                      0xc000
#define BRPHY1_GPHY_CORE_EXPE2_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPE2_RESERVED0_BITS                      2
#define BRPHY1_GPHY_CORE_EXPE2_RESERVED0_SHIFT                     14

/* BRPHY1_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_10 [13:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE2,0x3f80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE2,0x3f80,7)
#define BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_MASK              0x3f80
#define BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_BITS              7
#define BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_SHIFT             7

/* BRPHY1_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_100_1000 [06:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPE2,0x7f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPE2,0x7f,0)
#define BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_MASK        0x007f
#define BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_ALIGN       0
#define BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_BITS        7
#define BRPHY1_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_SHIFT       0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPEA
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPEA :: reserved0 [15:13] */
#define BRPHY1_GPHY_CORE_EXPEA_RESERVED0_MASK                      0xe000
#define BRPHY1_GPHY_CORE_EXPEA_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPEA_RESERVED0_BITS                      3
#define BRPHY1_GPHY_CORE_EXPEA_RESERVED0_SHIFT                     13

/* BRPHY1_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MAX_DLY_CYCLE [12:10] */
#define Wr_BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPEA,0x1c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPEA,0x1c00,10)
#define BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x1c00
#define BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      10

/* BRPHY1_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MIN_DLY_CYCLE [09:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPEA,0x380,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPEA,0x380,7)
#define BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x0380
#define BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY1_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      7

/* BRPHY1_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MAX_DLY_CYCLE [06:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPEA,0x70,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPEA,0x70,4)
#define BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x0070
#define BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      4

/* BRPHY1_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MIN_DLY_CYCLE [03:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPEA,0xe,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPEA,0xe,1)
#define BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x000e
#define BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY1_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      1

/* BRPHY1_GPHY_CORE :: EXPEA :: FEATURE_802_3BF_ENABLE [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPEA,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPEA,0x1,0)
#define BRPHY1_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_MASK         0x0001
#define BRPHY1_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_ALIGN        0
#define BRPHY1_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_BITS         1
#define BRPHY1_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_SHIFT        0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: LED_PRA_MODE
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: LED_PRA_MODE :: reserved0 [15:04] */
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_RESERVED0_MASK               0xfff0
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_RESERVED0_ALIGN              0
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_RESERVED0_BITS               12
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_RESERVED0_SHIFT              4

/* BRPHY1_GPHY_CORE :: LED_PRA_MODE :: SAT_MODE [03:03] */
#define Wr_BRPHY1_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_LED_PRA_MODE,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_LED_PRA_MODE,0x8,3)
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_SAT_MODE_MASK                0x0008
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_SAT_MODE_ALIGN               0
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_SAT_MODE_BITS                1
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_SAT_MODE_SHIFT               3

/* BRPHY1_GPHY_CORE :: LED_PRA_MODE :: PRA_MODE [02:00] */
#define Wr_BRPHY1_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_LED_PRA_MODE,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_LED_PRA_MODE,0x7,0)
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_PRA_MODE_MASK                0x0007
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_PRA_MODE_ALIGN               0
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_PRA_MODE_BITS                3
#define BRPHY1_GPHY_CORE_LED_PRA_MODE_PRA_MODE_SHIFT               0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: FIFO_CTL
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: FIFO_CTL :: SFT_RST [15:15] */
#define Wr_BRPHY1_GPHY_CORE_FIFO_CTL_SFT_RST(x) WriteRegBits16(BRPHY1_GPHY_CORE_FIFO_CTL,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_FIFO_CTL_SFT_RST(x) ReadRegBits16(BRPHY1_GPHY_CORE_FIFO_CTL,0x8000,15)
#define BRPHY1_GPHY_CORE_FIFO_CTL_SFT_RST_MASK                     0x8000
#define BRPHY1_GPHY_CORE_FIFO_CTL_SFT_RST_ALIGN                    0
#define BRPHY1_GPHY_CORE_FIFO_CTL_SFT_RST_BITS                     1
#define BRPHY1_GPHY_CORE_FIFO_CTL_SFT_RST_SHIFT                    15

/* BRPHY1_GPHY_CORE :: FIFO_CTL :: reserved0 [14:09] */
#define BRPHY1_GPHY_CORE_FIFO_CTL_RESERVED0_MASK                   0x7e00
#define BRPHY1_GPHY_CORE_FIFO_CTL_RESERVED0_ALIGN                  0
#define BRPHY1_GPHY_CORE_FIFO_CTL_RESERVED0_BITS                   6
#define BRPHY1_GPHY_CORE_FIFO_CTL_RESERVED0_SHIFT                  9

/* BRPHY1_GPHY_CORE :: FIFO_CTL :: WRBLOCK_MODE [08:08] */
#define Wr_BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) WriteRegBits16(BRPHY1_GPHY_CORE_FIFO_CTL,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) ReadRegBits16(BRPHY1_GPHY_CORE_FIFO_CTL,0x100,8)
#define BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_MASK                0x0100
#define BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_ALIGN               0
#define BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_BITS                1
#define BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_SHIFT               8

/* BRPHY1_GPHY_CORE :: FIFO_CTL :: WRBLOCK_OVR [07:04] */
#define Wr_BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) WriteRegBits16(BRPHY1_GPHY_CORE_FIFO_CTL,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) ReadRegBits16(BRPHY1_GPHY_CORE_FIFO_CTL,0xf0,4)
#define BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_MASK                 0x00f0
#define BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_ALIGN                0
#define BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_BITS                 4
#define BRPHY1_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_SHIFT                4

/* BRPHY1_GPHY_CORE :: FIFO_CTL :: MIN_IPG [03:00] */
#define Wr_BRPHY1_GPHY_CORE_FIFO_CTL_MIN_IPG(x) WriteRegBits16(BRPHY1_GPHY_CORE_FIFO_CTL,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_FIFO_CTL_MIN_IPG(x) ReadRegBits16(BRPHY1_GPHY_CORE_FIFO_CTL,0xf,0)
#define BRPHY1_GPHY_CORE_FIFO_CTL_MIN_IPG_MASK                     0x000f
#define BRPHY1_GPHY_CORE_FIFO_CTL_MIN_IPG_ALIGN                    0
#define BRPHY1_GPHY_CORE_FIFO_CTL_MIN_IPG_BITS                     4
#define BRPHY1_GPHY_CORE_FIFO_CTL_MIN_IPG_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPD8
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPD8 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_EXPD8_RESERVED0_MASK                      0x8000
#define BRPHY1_GPHY_CORE_EXPD8_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPD8_RESERVED0_BITS                      1
#define BRPHY1_GPHY_CORE_EXPD8_RESERVED0_SHIFT                     15

/* BRPHY1_GPHY_CORE :: EXPD8 :: FORCE_ACD_ON [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x4000,14)
#define BRPHY1_GPHY_CORE_EXPD8_FORCE_ACD_ON_MASK                   0x4000
#define BRPHY1_GPHY_CORE_EXPD8_FORCE_ACD_ON_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPD8_FORCE_ACD_ON_BITS                   1
#define BRPHY1_GPHY_CORE_EXPD8_FORCE_ACD_ON_SHIFT                  14

/* BRPHY1_GPHY_CORE :: EXPD8 :: ACD_PHASE_SEL [13:11] */
#define Wr_BRPHY1_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x3800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x3800,11)
#define BRPHY1_GPHY_CORE_EXPD8_ACD_PHASE_SEL_MASK                  0x3800
#define BRPHY1_GPHY_CORE_EXPD8_ACD_PHASE_SEL_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXPD8_ACD_PHASE_SEL_BITS                  3
#define BRPHY1_GPHY_CORE_EXPD8_ACD_PHASE_SEL_SHIFT                 11

/* BRPHY1_GPHY_CORE :: EXPD8 :: AGC_FSCALE [10:09] */
#define Wr_BRPHY1_GPHY_CORE_EXPD8_AGC_FSCALE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x600,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPD8_AGC_FSCALE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x600,9)
#define BRPHY1_GPHY_CORE_EXPD8_AGC_FSCALE_MASK                     0x0600
#define BRPHY1_GPHY_CORE_EXPD8_AGC_FSCALE_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPD8_AGC_FSCALE_BITS                     2
#define BRPHY1_GPHY_CORE_EXPD8_AGC_FSCALE_SHIFT                    9

/* BRPHY1_GPHY_CORE :: EXPD8 :: STOP_AGC_AFTER_LINK [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x100,8)
#define BRPHY1_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_MASK            0x0100
#define BRPHY1_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_ALIGN           0
#define BRPHY1_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_BITS            1
#define BRPHY1_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_SHIFT           8

/* BRPHY1_GPHY_CORE :: EXPD8 :: UPDATE_FROM_FFE_EN [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x80,7)
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_MASK             0x0080
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_BITS             1
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_SHIFT            7

/* BRPHY1_GPHY_CORE :: EXPD8 :: UPDATE_AGC_WHEN_IDLE [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x40,6)
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_MASK           0x0040
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_BITS           1
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_SHIFT          6

/* BRPHY1_GPHY_CORE :: EXPD8 :: UPDATE_ENC_WHEN_IDLE [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x20,5)
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_MASK           0x0020
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_BITS           1
#define BRPHY1_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_SHIFT          5

/* BRPHY1_GPHY_CORE :: EXPD8 :: FFE_DYN_THD [04:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPD8_FFE_DYN_THD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x1f,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPD8_FFE_DYN_THD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPD8,0x1f,0)
#define BRPHY1_GPHY_CORE_EXPD8_FFE_DYN_THD_MASK                    0x001f
#define BRPHY1_GPHY_CORE_EXPD8_FFE_DYN_THD_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPD8_FFE_DYN_THD_BITS                    5
#define BRPHY1_GPHY_CORE_EXPD8_FFE_DYN_THD_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPF0
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPF0 :: IBS_RX_SEND [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXPF0_IBS_RX_SEND(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF0_IBS_RX_SEND(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x8000,15)
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RX_SEND_MASK                    0x8000
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RX_SEND_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RX_SEND_BITS                    1
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RX_SEND_SHIFT                   15

/* BRPHY1_GPHY_CORE :: EXPF0 :: IBS_TX_EN [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPF0_IBS_TX_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF0_IBS_TX_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x4000,14)
#define BRPHY1_GPHY_CORE_EXPF0_IBS_TX_EN_MASK                      0x4000
#define BRPHY1_GPHY_CORE_EXPF0_IBS_TX_EN_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPF0_IBS_TX_EN_BITS                      1
#define BRPHY1_GPHY_CORE_EXPF0_IBS_TX_EN_SHIFT                     14

/* BRPHY1_GPHY_CORE :: EXPF0 :: IBS_RXCLK_OV_EN [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x2000,13)
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_MASK                0x2000
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_BITS                1
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_SHIFT               13

/* BRPHY1_GPHY_CORE :: EXPF0 :: IBS_RXCLK_SW_OV [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_MASK                0x1000
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_BITS                1
#define BRPHY1_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_SHIFT               12

/* BRPHY1_GPHY_CORE :: EXPF0 :: reserved0 [11:05] */
#define BRPHY1_GPHY_CORE_EXPF0_RESERVED0_MASK                      0x0fe0
#define BRPHY1_GPHY_CORE_EXPF0_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPF0_RESERVED0_BITS                      7
#define BRPHY1_GPHY_CORE_EXPF0_RESERVED0_SHIFT                     5

/* BRPHY1_GPHY_CORE :: EXPF0 :: IBS_PWRDN [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x10,4)
#define BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_MASK                      0x0010
#define BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_BITS                      1
#define BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_SHIFT                     4

/* BRPHY1_GPHY_CORE :: EXPF0 :: IBS_PWRDN_SD [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x8,3)
#define BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_SD_MASK                   0x0008
#define BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_SD_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_SD_BITS                   1
#define BRPHY1_GPHY_CORE_EXPF0_IBS_PWRDN_SD_SHIFT                  3

/* BRPHY1_GPHY_CORE :: EXPF0 :: IBS_AUTO_PWRDN [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x4,2)
#define BRPHY1_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_MASK                 0x0004
#define BRPHY1_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_BITS                 1
#define BRPHY1_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_SHIFT                2

/* BRPHY1_GPHY_CORE :: EXPF0 :: IBS_EARLY_DAC_WAKE [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x2,1)
#define BRPHY1_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_MASK             0x0002
#define BRPHY1_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_BITS             1
#define BRPHY1_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_SHIFT            1

/* BRPHY1_GPHY_CORE :: EXPF0 :: IBS_CK25_DIS [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF0,0x1,0)
#define BRPHY1_GPHY_CORE_EXPF0_IBS_CK25_DIS_MASK                   0x0001
#define BRPHY1_GPHY_CORE_EXPF0_IBS_CK25_DIS_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPF0_IBS_CK25_DIS_BITS                   1
#define BRPHY1_GPHY_CORE_EXPF0_IBS_CK25_DIS_SHIFT                  0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPF5
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_COPPER [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x8000,15)
#define BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_MASK           0x8000
#define BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_BITS           1
#define BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_SHIFT          15

/* BRPHY1_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_FIBER [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x4000,14)
#define BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_MASK            0x4000
#define BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_ALIGN           0
#define BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_BITS            1
#define BRPHY1_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_SHIFT           14

/* BRPHY1_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_COPPER [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x2000,13)
#define BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_MASK           0x2000
#define BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_BITS           1
#define BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_SHIFT          13

/* BRPHY1_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_FIBER [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_MASK            0x1000
#define BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_ALIGN           0
#define BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_BITS            1
#define BRPHY1_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_SHIFT           12

/* BRPHY1_GPHY_CORE :: EXPF5 :: RX_SOP_SEL [11:10] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0xc00,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0xc00,10)
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_MASK                     0x0c00
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_BITS                     2
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_SHIFT                    10

/* BRPHY1_GPHY_CORE :: EXPF5 :: RX_SOP_SEL_OV [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x200,9)
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_MASK                  0x0200
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_BITS                  1
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_SHIFT                 9

/* BRPHY1_GPHY_CORE :: EXPF5 :: TX_SOP_10BT_ENABLE [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x100,8)
#define BRPHY1_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_MASK             0x0100
#define BRPHY1_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_BITS             1
#define BRPHY1_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_SHIFT            8

/* BRPHY1_GPHY_CORE :: EXPF5 :: RX_SOP_10BT_ENABLE [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x80,7)
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_MASK             0x0080
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_BITS             1
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_SHIFT            7

/* BRPHY1_GPHY_CORE :: EXPF5 :: TX_SOP_ERR_STATUS [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x40,6)
#define BRPHY1_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_MASK              0x0040
#define BRPHY1_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_BITS              1
#define BRPHY1_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_SHIFT             6

/* BRPHY1_GPHY_CORE :: EXPF5 :: USE_TXEN_TX_SOP [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x20,5)
#define BRPHY1_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_MASK                0x0020
#define BRPHY1_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_BITS                1
#define BRPHY1_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_SHIFT               5

/* BRPHY1_GPHY_CORE :: EXPF5 :: RX_SOP_ERR_STATUS [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x10,4)
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_MASK              0x0010
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_BITS              1
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_SHIFT             4

/* BRPHY1_GPHY_CORE :: EXPF5 :: RX_SOP_OPTION [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x8,3)
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_OPTION_MASK                  0x0008
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_OPTION_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_OPTION_BITS                  1
#define BRPHY1_GPHY_CORE_EXPF5_RX_SOP_OPTION_SHIFT                 3

/* BRPHY1_GPHY_CORE :: EXPF5 :: USE_RXDV_RX_SOP [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x4,2)
#define BRPHY1_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_MASK                0x0004
#define BRPHY1_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_BITS                1
#define BRPHY1_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_SHIFT               2

/* BRPHY1_GPHY_CORE :: EXPF5 :: RECOVERY_CLK_SEL [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x2,1)
#define BRPHY1_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_MASK               0x0002
#define BRPHY1_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_BITS               1
#define BRPHY1_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_SHIFT              1

/* BRPHY1_GPHY_CORE :: EXPF5 :: TIMESYNC_EN [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPF5_TIMESYNC_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF5_TIMESYNC_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF5,0x1,0)
#define BRPHY1_GPHY_CORE_EXPF5_TIMESYNC_EN_MASK                    0x0001
#define BRPHY1_GPHY_CORE_EXPF5_TIMESYNC_EN_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPF5_TIMESYNC_EN_BITS                    1
#define BRPHY1_GPHY_CORE_EXPF5_TIMESYNC_EN_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPF6
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPF6 :: reserved0 [15:15] */
#define BRPHY1_GPHY_CORE_EXPF6_RESERVED0_MASK                      0x8000
#define BRPHY1_GPHY_CORE_EXPF6_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPF6_RESERVED0_BITS                      1
#define BRPHY1_GPHY_CORE_EXPF6_RESERVED0_SHIFT                     15

/* BRPHY1_GPHY_CORE :: EXPF6 :: PWRDN_DLL [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPF6_PWRDN_DLL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF6,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF6_PWRDN_DLL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF6,0x4000,14)
#define BRPHY1_GPHY_CORE_EXPF6_PWRDN_DLL_MASK                      0x4000
#define BRPHY1_GPHY_CORE_EXPF6_PWRDN_DLL_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPF6_PWRDN_DLL_BITS                      1
#define BRPHY1_GPHY_CORE_EXPF6_PWRDN_DLL_SHIFT                     14

/* BRPHY1_GPHY_CORE :: EXPF6 :: PWRDNBT_DLL [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF6,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF6,0x2000,13)
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNBT_DLL_MASK                    0x2000
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNBT_DLL_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNBT_DLL_BITS                    1
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNBT_DLL_SHIFT                   13

/* BRPHY1_GPHY_CORE :: EXPF6 :: COMMON_PWROFF [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPF6_COMMON_PWROFF(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF6,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF6_COMMON_PWROFF(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF6,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPF6_COMMON_PWROFF_MASK                  0x1000
#define BRPHY1_GPHY_CORE_EXPF6_COMMON_PWROFF_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXPF6_COMMON_PWROFF_BITS                  1
#define BRPHY1_GPHY_CORE_EXPF6_COMMON_PWROFF_SHIFT                 12

/* BRPHY1_GPHY_CORE :: EXPF6 :: PWRDN_SD [11:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPF6_PWRDN_SD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF6,0xf00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF6_PWRDN_SD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF6,0xf00,8)
#define BRPHY1_GPHY_CORE_EXPF6_PWRDN_SD_MASK                       0x0f00
#define BRPHY1_GPHY_CORE_EXPF6_PWRDN_SD_ALIGN                      0
#define BRPHY1_GPHY_CORE_EXPF6_PWRDN_SD_BITS                       4
#define BRPHY1_GPHY_CORE_EXPF6_PWRDN_SD_SHIFT                      8

/* BRPHY1_GPHY_CORE :: EXPF6 :: PWRDNRX [07:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPF6_PWRDNRX(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF6,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF6_PWRDNRX(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF6,0xf0,4)
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNRX_MASK                        0x00f0
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNRX_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNRX_BITS                        4
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNRX_SHIFT                       4

/* BRPHY1_GPHY_CORE :: EXPF6 :: PWRDNTX [03:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPF6_PWRDNTX(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF6,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF6_PWRDNTX(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF6,0xf,0)
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNTX_MASK                        0x000f
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNTX_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNTX_BITS                        4
#define BRPHY1_GPHY_CORE_EXPF6_PWRDNTX_SHIFT                       0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPF7
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPF7 :: reserved0 [15:14] */
#define BRPHY1_GPHY_CORE_EXPF7_RESERVED0_MASK                      0xc000
#define BRPHY1_GPHY_CORE_EXPF7_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPF7_RESERVED0_BITS                      2
#define BRPHY1_GPHY_CORE_EXPF7_RESERVED0_SHIFT                     14

/* BRPHY1_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_DPWR [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x2000,13)
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_MASK              0x2000
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_BITS              1
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_SHIFT             13

/* BRPHY1_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_APWR [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_MASK              0x1000
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_BITS              1
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_SHIFT             12

/* BRPHY1_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_DPWR [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x800,11)
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_MASK              0x0800
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_BITS              1
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_SHIFT             11

/* BRPHY1_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_APWR [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x400,10)
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_MASK              0x0400
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_BITS              1
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_SHIFT             10

/* BRPHY1_GPHY_CORE :: EXPF7 :: R0PWRDN_DPWR [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x200,9)
#define BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_DPWR_MASK                   0x0200
#define BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_DPWR_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_DPWR_BITS                   1
#define BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_DPWR_SHIFT                  9

/* BRPHY1_GPHY_CORE :: EXPF7 :: R0PWRDN_APWR [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x100,8)
#define BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_APWR_MASK                   0x0100
#define BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_APWR_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_APWR_BITS                   1
#define BRPHY1_GPHY_CORE_EXPF7_R0PWRDN_APWR_SHIFT                  8

/* BRPHY1_GPHY_CORE :: EXPF7 :: AUTO_PWRDN_DLL [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x80,7)
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_MASK                 0x0080
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_BITS                 1
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_SHIFT                7

/* BRPHY1_GPHY_CORE :: EXPF7 :: PWRDN_DPWR_EARLY_INT [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x40,6)
#define BRPHY1_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_MASK           0x0040
#define BRPHY1_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_BITS           1
#define BRPHY1_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_SHIFT          6

/* BRPHY1_GPHY_CORE :: EXPF7 :: REAL_ENERGY [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_REAL_ENERGY(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_REAL_ENERGY(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x20,5)
#define BRPHY1_GPHY_CORE_EXPF7_REAL_ENERGY_MASK                    0x0020
#define BRPHY1_GPHY_CORE_EXPF7_REAL_ENERGY_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPF7_REAL_ENERGY_BITS                    1
#define BRPHY1_GPHY_CORE_EXPF7_REAL_ENERGY_SHIFT                   5

/* BRPHY1_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_RAW [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x10,4)
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_MASK               0x0010
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_BITS               1
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_SHIFT              4

/* BRPHY1_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_RAW [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x8,3)
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_MASK               0x0008
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_BITS               1
#define BRPHY1_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_SHIFT              3

/* BRPHY1_GPHY_CORE :: EXPF7 :: CUR_STATE [02:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPF7_CUR_STATE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x7,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF7_CUR_STATE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF7,0x7,0)
#define BRPHY1_GPHY_CORE_EXPF7_CUR_STATE_MASK                      0x0007
#define BRPHY1_GPHY_CORE_EXPF7_CUR_STATE_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPF7_CUR_STATE_BITS                      3
#define BRPHY1_GPHY_CORE_EXPF7_CUR_STATE_SHIFT                     0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPF8
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPF8 :: TRIM_DAC_FROM_FUSE [15:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF8,0xf000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF8,0xf000,12)
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_MASK             0xf000
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_BITS             4
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_SHIFT            12

/* BRPHY1_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_FROM_FUSE [11:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF8,0xf00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF8,0xf00,8)
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_MASK          0x0f00
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_ALIGN         0
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_BITS          4
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_SHIFT         8

/* BRPHY1_GPHY_CORE :: EXPF8 :: TRIM_DAC_TO_BIAS_BLOCK [07:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF8,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF8,0xf0,4)
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_MASK         0x00f0
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_ALIGN        0
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_BITS         4
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_SHIFT        4

/* BRPHY1_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_TO_BIAS_BLOCK [03:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF8,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF8,0xf,0)
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_MASK      0x000f
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_ALIGN     0
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_BITS      4
#define BRPHY1_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_SHIFT     0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPF9
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPF9 :: EXT_CTL [15:11] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_EXT_CTL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0xf800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_EXT_CTL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0xf800,11)
#define BRPHY1_GPHY_CORE_EXPF9_EXT_CTL_MASK                        0xf800
#define BRPHY1_GPHY_CORE_EXPF9_EXT_CTL_ALIGN                       0
#define BRPHY1_GPHY_CORE_EXPF9_EXT_CTL_BITS                        5
#define BRPHY1_GPHY_CORE_EXPF9_EXT_CTL_SHIFT                       11

/* BRPHY1_GPHY_CORE :: EXPF9 :: BT_NIBBLE_VAL [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x400,10)
#define BRPHY1_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_MASK                  0x0400
#define BRPHY1_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_BITS                  1
#define BRPHY1_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_SHIFT                 10

/* BRPHY1_GPHY_CORE :: EXPF9 :: BT_DRIB_RMV [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x200,9)
#define BRPHY1_GPHY_CORE_EXPF9_BT_DRIB_RMV_MASK                    0x0200
#define BRPHY1_GPHY_CORE_EXPF9_BT_DRIB_RMV_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPF9_BT_DRIB_RMV_BITS                    1
#define BRPHY1_GPHY_CORE_EXPF9_BT_DRIB_RMV_SHIFT                   9

/* BRPHY1_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_MDIX_EN [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x100,8)
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_MASK          0x0100
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_ALIGN         0
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_BITS          1
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_SHIFT         8

/* BRPHY1_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SEED_EN [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x80,7)
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_MASK          0x0080
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_ALIGN         0
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_BITS          1
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_SHIFT         7

/* BRPHY1_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_EN [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x40,6)
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_MASK               0x0040
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_BITS               1
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_SHIFT              6

/* BRPHY1_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SIG [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x20,5)
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_MASK              0x0020
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_BITS              1
#define BRPHY1_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_SHIFT             5

/* BRPHY1_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_VAL [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x10,4)
#define BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_MASK          0x0010
#define BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_ALIGN         0
#define BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_BITS          1
#define BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_SHIFT         4

/* BRPHY1_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_EN [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x8,3)
#define BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_MASK           0x0008
#define BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_BITS           1
#define BRPHY1_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_SHIFT          3

/* BRPHY1_GPHY_CORE :: EXPF9 :: ABIST_INF_CONV [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x4,2)
#define BRPHY1_GPHY_CORE_EXPF9_ABIST_INF_CONV_MASK                 0x0004
#define BRPHY1_GPHY_CORE_EXPF9_ABIST_INF_CONV_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPF9_ABIST_INF_CONV_BITS                 1
#define BRPHY1_GPHY_CORE_EXPF9_ABIST_INF_CONV_SHIFT                2

/* BRPHY1_GPHY_CORE :: EXPF9 :: GIGA_ONLY_HALFOUT [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x2,1)
#define BRPHY1_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_MASK              0x0002
#define BRPHY1_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_BITS              1
#define BRPHY1_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_SHIFT             1

/* BRPHY1_GPHY_CORE :: EXPF9 :: SPARE_REG0 [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPF9_SPARE_REG0(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPF9_SPARE_REG0(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPF9,0x1,0)
#define BRPHY1_GPHY_CORE_EXPF9_SPARE_REG0_MASK                     0x0001
#define BRPHY1_GPHY_CORE_EXPF9_SPARE_REG0_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPF9_SPARE_REG0_BITS                     1
#define BRPHY1_GPHY_CORE_EXPF9_SPARE_REG0_SHIFT                    0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPFA
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPFA :: reserved0 [15:04] */
#define BRPHY1_GPHY_CORE_EXPFA_RESERVED0_MASK                      0xfff0
#define BRPHY1_GPHY_CORE_EXPFA_RESERVED0_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPFA_RESERVED0_BITS                      12
#define BRPHY1_GPHY_CORE_EXPFA_RESERVED0_SHIFT                     4

/* BRPHY1_GPHY_CORE :: EXPFA :: HIDDEN_REV_NUM [03:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFA,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFA,0xf,0)
#define BRPHY1_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_MASK                 0x000f
#define BRPHY1_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_BITS                 4
#define BRPHY1_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_SHIFT                0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPFB
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPFB :: TEST_IDDQCLKBIAS [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x8000,15)
#define BRPHY1_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_MASK               0x8000
#define BRPHY1_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_BITS               1
#define BRPHY1_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_SHIFT              15

/* BRPHY1_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x4000,14)
#define BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_MASK                 0x4000
#define BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_BITS                 1
#define BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_SHIFT                14

/* BRPHY1_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV_VAL [13:10] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x3c00,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x3c00,10)
#define BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_MASK             0x3c00
#define BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_BITS             4
#define BRPHY1_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_SHIFT            10

/* BRPHY1_GPHY_CORE :: EXPFB :: TDR_SLAVE_DFE_CONV_VAL [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x200,9)
#define BRPHY1_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_MASK         0x0200
#define BRPHY1_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_ALIGN        0
#define BRPHY1_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_BITS         1
#define BRPHY1_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_SHIFT        9

/* BRPHY1_GPHY_CORE :: EXPFB :: FEXT_INPUTS_OV [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x100,8)
#define BRPHY1_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_MASK                 0x0100
#define BRPHY1_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_BITS                 1
#define BRPHY1_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_SHIFT                8

/* BRPHY1_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_OV [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x80,7)
#define BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_MASK               0x0080
#define BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_BITS               1
#define BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_SHIFT              7

/* BRPHY1_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_VAL [06:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x60,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x60,5)
#define BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_MASK              0x0060
#define BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_BITS              2
#define BRPHY1_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_SHIFT             5

/* BRPHY1_GPHY_CORE :: EXPFB :: LINK_DET_OV [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_LINK_DET_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_LINK_DET_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x10,4)
#define BRPHY1_GPHY_CORE_EXPFB_LINK_DET_OV_MASK                    0x0010
#define BRPHY1_GPHY_CORE_EXPFB_LINK_DET_OV_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPFB_LINK_DET_OV_BITS                    1
#define BRPHY1_GPHY_CORE_EXPFB_LINK_DET_OV_SHIFT                   4

/* BRPHY1_GPHY_CORE :: EXPFB :: LINK_DET_VAL [03:02] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_LINK_DET_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0xc,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_LINK_DET_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0xc,2)
#define BRPHY1_GPHY_CORE_EXPFB_LINK_DET_VAL_MASK                   0x000c
#define BRPHY1_GPHY_CORE_EXPFB_LINK_DET_VAL_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPFB_LINK_DET_VAL_BITS                   2
#define BRPHY1_GPHY_CORE_EXPFB_LINK_DET_VAL_SHIFT                  2

/* BRPHY1_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_OV [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x2,1)
#define BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_MASK               0x0002
#define BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_BITS               1
#define BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_SHIFT              1

/* BRPHY1_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_VAL [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFB,0x1,0)
#define BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_MASK              0x0001
#define BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_BITS              1
#define BRPHY1_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_SHIFT             0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPFC
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPFC :: PASSIVE_TERM_OV [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x8000,15)
#define BRPHY1_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_MASK                0x8000
#define BRPHY1_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_BITS                1
#define BRPHY1_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_SHIFT               15

/* BRPHY1_GPHY_CORE :: EXPFC :: APD_CLKOFF_OV [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x4000,14)
#define BRPHY1_GPHY_CORE_EXPFC_APD_CLKOFF_OV_MASK                  0x4000
#define BRPHY1_GPHY_CORE_EXPFC_APD_CLKOFF_OV_ALIGN                 0
#define BRPHY1_GPHY_CORE_EXPFC_APD_CLKOFF_OV_BITS                  1
#define BRPHY1_GPHY_CORE_EXPFC_APD_CLKOFF_OV_SHIFT                 14

/* BRPHY1_GPHY_CORE :: EXPFC :: TDR_TSD_PTE_OV_VAL_CHD [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x2000,13)
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_MASK         0x2000
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_ALIGN        0
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_BITS         1
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_SHIFT        13

/* BRPHY1_GPHY_CORE :: EXPFC :: TDR_TSC_PTE_OV_VAL_CHC [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_MASK         0x1000
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_ALIGN        0
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_BITS         1
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_SHIFT        12

/* BRPHY1_GPHY_CORE :: EXPFC :: TDR_TSB_PTE_OV_VAL_CHB [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x800,11)
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_MASK         0x0800
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_ALIGN        0
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_BITS         1
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_SHIFT        11

/* BRPHY1_GPHY_CORE :: EXPFC :: TDR_TSA_PTE_OV_VAL_CHA [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x400,10)
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_MASK         0x0400
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_ALIGN        0
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_BITS         1
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_SHIFT        10

/* BRPHY1_GPHY_CORE :: EXPFC :: TDR_TS_EN_OV [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x200,9)
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TS_EN_OV_MASK                   0x0200
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TS_EN_OV_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TS_EN_OV_BITS                   1
#define BRPHY1_GPHY_CORE_EXPFC_TDR_TS_EN_OV_SHIFT                  9

/* BRPHY1_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x100,8)
#define BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_MASK                   0x0100
#define BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_BITS                   1
#define BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_SHIFT                  8

/* BRPHY1_GPHY_CORE :: EXPFC :: BASET_DLL_CLK_OV_VAL [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x80,7)
#define BRPHY1_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_MASK           0x0080
#define BRPHY1_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_ALIGN          0
#define BRPHY1_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_BITS           1
#define BRPHY1_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_SHIFT          7

/* BRPHY1_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV_VAL [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x40,6)
#define BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_MASK               0x0040
#define BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_BITS               1
#define BRPHY1_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_SHIFT              6

/* BRPHY1_GPHY_CORE :: EXPFC :: AUTONEG_1000T_CLK_GATING_DIS [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x20,5)
#define BRPHY1_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_MASK   0x0020
#define BRPHY1_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_ALIGN  0
#define BRPHY1_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_BITS   1
#define BRPHY1_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_SHIFT  5

/* BRPHY1_GPHY_CORE :: EXPFC :: AUTONEG_10BT_LP_DIS [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x10,4)
#define BRPHY1_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_MASK            0x0010
#define BRPHY1_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_ALIGN           0
#define BRPHY1_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_BITS            1
#define BRPHY1_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_SHIFT           4

/* BRPHY1_GPHY_CORE :: EXPFC :: AUTO_PWRDN_CLK_OFF_OV_VAL [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x8,3)
#define BRPHY1_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_MASK      0x0008
#define BRPHY1_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_ALIGN     0
#define BRPHY1_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_BITS      1
#define BRPHY1_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_SHIFT     3

/* BRPHY1_GPHY_CORE :: EXPFC :: LP1000_DIS [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_LP1000_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_LP1000_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x4,2)
#define BRPHY1_GPHY_CORE_EXPFC_LP1000_DIS_MASK                     0x0004
#define BRPHY1_GPHY_CORE_EXPFC_LP1000_DIS_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPFC_LP1000_DIS_BITS                     1
#define BRPHY1_GPHY_CORE_EXPFC_LP1000_DIS_SHIFT                    2

/* BRPHY1_GPHY_CORE :: EXPFC :: LP100_DIS [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_LP100_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_LP100_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x2,1)
#define BRPHY1_GPHY_CORE_EXPFC_LP100_DIS_MASK                      0x0002
#define BRPHY1_GPHY_CORE_EXPFC_LP100_DIS_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPFC_LP100_DIS_BITS                      1
#define BRPHY1_GPHY_CORE_EXPFC_LP100_DIS_SHIFT                     1

/* BRPHY1_GPHY_CORE :: EXPFC :: LP10_DIABLE [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPFC_LP10_DIABLE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFC_LP10_DIABLE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFC,0x1,0)
#define BRPHY1_GPHY_CORE_EXPFC_LP10_DIABLE_MASK                    0x0001
#define BRPHY1_GPHY_CORE_EXPFC_LP10_DIABLE_ALIGN                   0
#define BRPHY1_GPHY_CORE_EXPFC_LP10_DIABLE_BITS                    1
#define BRPHY1_GPHY_CORE_EXPFC_LP10_DIABLE_SHIFT                   0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPFD
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPFD :: SPARE_REG [15:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0xe000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0xe000,13)
#define BRPHY1_GPHY_CORE_EXPFD_SPARE_REG_MASK                      0xe000
#define BRPHY1_GPHY_CORE_EXPFD_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPFD_SPARE_REG_BITS                      3
#define BRPHY1_GPHY_CORE_EXPFD_SPARE_REG_SHIFT                     13

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x800,11)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x400,10)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x200,9)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_BITS               1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x100,8)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_BITS               1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x80,7)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x40,6)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x20,5)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x10,4)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x8,3)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x4,2)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x2,1)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_BITS                1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY1_GPHY_CORE :: EXPFD :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFD,0x1,0)
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_BITS               1
#define BRPHY1_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPFE
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPFE :: SPARE_REG [15:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_SPARE_REG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0xc000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_SPARE_REG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0xc000,14)
#define BRPHY1_GPHY_CORE_EXPFE_SPARE_REG_MASK                      0xc000
#define BRPHY1_GPHY_CORE_EXPFE_SPARE_REG_ALIGN                     0
#define BRPHY1_GPHY_CORE_EXPFE_SPARE_REG_BITS                      2
#define BRPHY1_GPHY_CORE_EXPFE_SPARE_REG_SHIFT                     14

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_DFE_LPI_EN [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x2000,13)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_MASK              0x2000
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_BITS              1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_SHIFT             13

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x800,11,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x800,11)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x400,10,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x400,10)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x200,9,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x200,9)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_BITS               1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x100,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x100,8)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_BITS               1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x80,7,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x80,7)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x40,6,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x40,6)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x20,5,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x20,5)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x10,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x10,4)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x8,3,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x8,3)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x4,2,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x4,2)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x2,1,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x2,1)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_BITS                1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY1_GPHY_CORE :: EXPFE :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x1,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFE,0x1,0)
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_BITS               1
#define BRPHY1_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY1_GPHY_CORE :: EXPFF
 ***************************************************************************/
/* BRPHY1_GPHY_CORE :: EXPFF :: PWRDN_SD_DIS [15:15] */
#define Wr_BRPHY1_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFF,0x8000,15,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFF,0x8000,15)
#define BRPHY1_GPHY_CORE_EXPFF_PWRDN_SD_DIS_MASK                   0x8000
#define BRPHY1_GPHY_CORE_EXPFF_PWRDN_SD_DIS_ALIGN                  0
#define BRPHY1_GPHY_CORE_EXPFF_PWRDN_SD_DIS_BITS                   1
#define BRPHY1_GPHY_CORE_EXPFF_PWRDN_SD_DIS_SHIFT                  15

/* BRPHY1_GPHY_CORE :: EXPFF :: PWRDNSD_OV [14:14] */
#define Wr_BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFF,0x4000,14,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFF,0x4000,14)
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_MASK                     0x4000
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_BITS                     1
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_SHIFT                    14

/* BRPHY1_GPHY_CORE :: EXPFF :: PWRDNTX_OV [13:13] */
#define Wr_BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFF,0x2000,13,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFF,0x2000,13)
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_MASK                     0x2000
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_BITS                     1
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_SHIFT                    13

/* BRPHY1_GPHY_CORE :: EXPFF :: PWRDNRX_OV [12:12] */
#define Wr_BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFF,0x1000,12,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFF,0x1000,12)
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_MASK                     0x1000
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_ALIGN                    0
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_BITS                     1
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_SHIFT                    12

/* BRPHY1_GPHY_CORE :: EXPFF :: PWRDNSD_OV_VAL [11:08] */
#define Wr_BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFF,0xf00,8,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFF,0xf00,8)
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_MASK                 0x0f00
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_BITS                 4
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_SHIFT                8

/* BRPHY1_GPHY_CORE :: EXPFF :: PWRDNTX_OV_VAL [07:04] */
#define Wr_BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFF,0xf0,4,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFF,0xf0,4)
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_MASK                 0x00f0
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_BITS                 4
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_SHIFT                4

/* BRPHY1_GPHY_CORE :: EXPFF :: PWRDNRX_OV_VAL [03:00] */
#define Wr_BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) WriteRegBits16(BRPHY1_GPHY_CORE_EXPFF,0xf,0,x)
#define Rd_BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) ReadRegBits16(BRPHY1_GPHY_CORE_EXPFF,0xf,0)
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_MASK                 0x000f
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_ALIGN                0
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_BITS                 4
#define BRPHY1_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_DSP_TAP
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP0_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP0_C0 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x8000,15)
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY1_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x4000,14)
#define BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY1_DSP_TAP :: TAP0_C0 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x2000,13)
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY1_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x1000,12)
#define BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY1_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY1_DSP_TAP :: TAP0_C0 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x800,11)
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_BITS                1
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY1_DSP_TAP :: TAP0_C0 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x700,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x700,8)
#define BRPHY1_DSP_TAP_TAP0_C0_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY1_DSP_TAP_TAP0_C0_BR_PGA_GAIN_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP0_C0_BR_PGA_GAIN_BITS                    3
#define BRPHY1_DSP_TAP_TAP0_C0_BR_PGA_GAIN_SHIFT                   8

/* BRPHY1_DSP_TAP :: TAP0_C0 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x80,7)
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_OV_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_OV_BITS                    1
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_OV_SHIFT                   7

/* BRPHY1_DSP_TAP :: TAP0_C0 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x7f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C0,0x7f,0)
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_BITS                 7
#define BRPHY1_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP0_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP0_C1 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x8000,15)
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY1_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x4000,14)
#define BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY1_DSP_TAP :: TAP0_C1 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x2000,13)
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY1_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x1000,12)
#define BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY1_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY1_DSP_TAP :: TAP0_C1 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x800,11)
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_BITS                1
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY1_DSP_TAP :: TAP0_C1 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x700,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x700,8)
#define BRPHY1_DSP_TAP_TAP0_C1_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY1_DSP_TAP_TAP0_C1_BR_PGA_GAIN_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP0_C1_BR_PGA_GAIN_BITS                    3
#define BRPHY1_DSP_TAP_TAP0_C1_BR_PGA_GAIN_SHIFT                   8

/* BRPHY1_DSP_TAP :: TAP0_C1 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x80,7)
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_OV_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_OV_BITS                    1
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_OV_SHIFT                   7

/* BRPHY1_DSP_TAP :: TAP0_C1 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x7f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C1,0x7f,0)
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_BITS                 7
#define BRPHY1_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP0_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP0_C2 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x8000,15)
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY1_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x4000,14)
#define BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY1_DSP_TAP :: TAP0_C2 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x2000,13)
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY1_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x1000,12)
#define BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY1_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY1_DSP_TAP :: TAP0_C2 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x800,11)
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_BITS                1
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY1_DSP_TAP :: TAP0_C2 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x700,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x700,8)
#define BRPHY1_DSP_TAP_TAP0_C2_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY1_DSP_TAP_TAP0_C2_BR_PGA_GAIN_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP0_C2_BR_PGA_GAIN_BITS                    3
#define BRPHY1_DSP_TAP_TAP0_C2_BR_PGA_GAIN_SHIFT                   8

/* BRPHY1_DSP_TAP :: TAP0_C2 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x80,7)
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_OV_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_OV_BITS                    1
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_OV_SHIFT                   7

/* BRPHY1_DSP_TAP :: TAP0_C2 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x7f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C2,0x7f,0)
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_BITS                 7
#define BRPHY1_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP0_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP0_C3 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x8000,15)
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY1_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x4000,14)
#define BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY1_DSP_TAP :: TAP0_C3 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x2000,13)
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY1_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x1000,12)
#define BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY1_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY1_DSP_TAP :: TAP0_C3 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x800,11)
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_BITS                1
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY1_DSP_TAP :: TAP0_C3 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x700,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x700,8)
#define BRPHY1_DSP_TAP_TAP0_C3_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY1_DSP_TAP_TAP0_C3_BR_PGA_GAIN_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP0_C3_BR_PGA_GAIN_BITS                    3
#define BRPHY1_DSP_TAP_TAP0_C3_BR_PGA_GAIN_SHIFT                   8

/* BRPHY1_DSP_TAP :: TAP0_C3 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x80,7)
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_OV_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_OV_BITS                    1
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_OV_SHIFT                   7

/* BRPHY1_DSP_TAP :: TAP0_C3 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x7f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP0_C3,0x7f,0)
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_BITS                 7
#define BRPHY1_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP1 :: reserved0 [15:14] */
#define BRPHY1_DSP_TAP_TAP1_RESERVED0_MASK                         0xc000
#define BRPHY1_DSP_TAP_TAP1_RESERVED0_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP1_RESERVED0_BITS                         2
#define BRPHY1_DSP_TAP_TAP1_RESERVED0_SHIFT                        14

/* BRPHY1_DSP_TAP :: TAP1 :: DIG_GAIN_LMS_MODE [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP1,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP1,0x2000,13)
#define BRPHY1_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_MASK                 0x2000
#define BRPHY1_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_BITS                 1
#define BRPHY1_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_SHIFT                13

/* BRPHY1_DSP_TAP :: TAP1 :: IPRF_K_OV_EN [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP1,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP1,0x1000,12)
#define BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_EN_MASK                      0x1000
#define BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_EN_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_EN_BITS                      1
#define BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_EN_SHIFT                     12

/* BRPHY1_DSP_TAP :: TAP1 :: IPRF_K_OV_VALUE [11:07] */
#define Wr_BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP1,0xf80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP1,0xf80,7)
#define BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_VALUE_MASK                   0x0f80
#define BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_VALUE_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_VALUE_BITS                   5
#define BRPHY1_DSP_TAP_TAP1_IPRF_K_OV_VALUE_SHIFT                  7

/* BRPHY1_DSP_TAP :: TAP1 :: GBT_AGC_TARGET_LVL [06:04] */
#define Wr_BRPHY1_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP1,0x70,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP1,0x70,4)
#define BRPHY1_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_MASK                0x0070
#define BRPHY1_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_ALIGN               0
#define BRPHY1_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_BITS                3
#define BRPHY1_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_SHIFT               4

/* BRPHY1_DSP_TAP :: TAP1 :: TX_AGC_TARGET_LVL [03:00] */
#define Wr_BRPHY1_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP1,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP1,0xf,0)
#define BRPHY1_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_MASK                 0x000f
#define BRPHY1_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_ALIGN                0
#define BRPHY1_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_BITS                 4
#define BRPHY1_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP2_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP2_C0 :: MSE [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP2_C0_MSE(x) WriteReg16(BRPHY1_DSP_TAP_TAP2_C0,x)
#define Rd_BRPHY1_DSP_TAP_TAP2_C0_MSE(x) ReadReg16(BRPHY1_DSP_TAP_TAP2_C0)
#define BRPHY1_DSP_TAP_TAP2_C0_MSE_MASK                            0xffff
#define BRPHY1_DSP_TAP_TAP2_C0_MSE_ALIGN                           0
#define BRPHY1_DSP_TAP_TAP2_C0_MSE_BITS                            16
#define BRPHY1_DSP_TAP_TAP2_C0_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP2_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP2_C1 :: MSE [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP2_C1_MSE(x) WriteReg16(BRPHY1_DSP_TAP_TAP2_C1,x)
#define Rd_BRPHY1_DSP_TAP_TAP2_C1_MSE(x) ReadReg16(BRPHY1_DSP_TAP_TAP2_C1)
#define BRPHY1_DSP_TAP_TAP2_C1_MSE_MASK                            0xffff
#define BRPHY1_DSP_TAP_TAP2_C1_MSE_ALIGN                           0
#define BRPHY1_DSP_TAP_TAP2_C1_MSE_BITS                            16
#define BRPHY1_DSP_TAP_TAP2_C1_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP2_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP2_C2 :: MSE [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP2_C2_MSE(x) WriteReg16(BRPHY1_DSP_TAP_TAP2_C2,x)
#define Rd_BRPHY1_DSP_TAP_TAP2_C2_MSE(x) ReadReg16(BRPHY1_DSP_TAP_TAP2_C2)
#define BRPHY1_DSP_TAP_TAP2_C2_MSE_MASK                            0xffff
#define BRPHY1_DSP_TAP_TAP2_C2_MSE_ALIGN                           0
#define BRPHY1_DSP_TAP_TAP2_C2_MSE_BITS                            16
#define BRPHY1_DSP_TAP_TAP2_C2_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP2_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP2_C3 :: MSE [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP2_C3_MSE(x) WriteReg16(BRPHY1_DSP_TAP_TAP2_C3,x)
#define Rd_BRPHY1_DSP_TAP_TAP2_C3_MSE(x) ReadReg16(BRPHY1_DSP_TAP_TAP2_C3)
#define BRPHY1_DSP_TAP_TAP2_C3_MSE_MASK                            0xffff
#define BRPHY1_DSP_TAP_TAP2_C3_MSE_ALIGN                           0
#define BRPHY1_DSP_TAP_TAP2_C3_MSE_BITS                            16
#define BRPHY1_DSP_TAP_TAP2_C3_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP3_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP3_C0 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP3_C0_SOFT_DECISION(x) WriteReg16(BRPHY1_DSP_TAP_TAP3_C0,x)
#define Rd_BRPHY1_DSP_TAP_TAP3_C0_SOFT_DECISION(x) ReadReg16(BRPHY1_DSP_TAP_TAP3_C0)
#define BRPHY1_DSP_TAP_TAP3_C0_SOFT_DECISION_MASK                  0xffff
#define BRPHY1_DSP_TAP_TAP3_C0_SOFT_DECISION_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP3_C0_SOFT_DECISION_BITS                  16
#define BRPHY1_DSP_TAP_TAP3_C0_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP3_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP3_C1 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP3_C1_SOFT_DECISION(x) WriteReg16(BRPHY1_DSP_TAP_TAP3_C1,x)
#define Rd_BRPHY1_DSP_TAP_TAP3_C1_SOFT_DECISION(x) ReadReg16(BRPHY1_DSP_TAP_TAP3_C1)
#define BRPHY1_DSP_TAP_TAP3_C1_SOFT_DECISION_MASK                  0xffff
#define BRPHY1_DSP_TAP_TAP3_C1_SOFT_DECISION_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP3_C1_SOFT_DECISION_BITS                  16
#define BRPHY1_DSP_TAP_TAP3_C1_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP3_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP3_C2 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP3_C2_SOFT_DECISION(x) WriteReg16(BRPHY1_DSP_TAP_TAP3_C2,x)
#define Rd_BRPHY1_DSP_TAP_TAP3_C2_SOFT_DECISION(x) ReadReg16(BRPHY1_DSP_TAP_TAP3_C2)
#define BRPHY1_DSP_TAP_TAP3_C2_SOFT_DECISION_MASK                  0xffff
#define BRPHY1_DSP_TAP_TAP3_C2_SOFT_DECISION_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP3_C2_SOFT_DECISION_BITS                  16
#define BRPHY1_DSP_TAP_TAP3_C2_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP3_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP3_C3 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP3_C3_SOFT_DECISION(x) WriteReg16(BRPHY1_DSP_TAP_TAP3_C3,x)
#define Rd_BRPHY1_DSP_TAP_TAP3_C3_SOFT_DECISION(x) ReadReg16(BRPHY1_DSP_TAP_TAP3_C3)
#define BRPHY1_DSP_TAP_TAP3_C3_SOFT_DECISION_MASK                  0xffff
#define BRPHY1_DSP_TAP_TAP3_C3_SOFT_DECISION_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP3_C3_SOFT_DECISION_BITS                  16
#define BRPHY1_DSP_TAP_TAP3_C3_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP4_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP4_C0 :: reserved0 [15:15] */
#define BRPHY1_DSP_TAP_TAP4_C0_RESERVED0_MASK                      0x8000
#define BRPHY1_DSP_TAP_TAP4_C0_RESERVED0_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C0_RESERVED0_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C0_RESERVED0_SHIFT                     15

/* BRPHY1_DSP_TAP :: TAP4_C0 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x7000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x7000,12)
#define BRPHY1_DSP_TAP_TAP4_C0_PAIR_OFFSET_MASK                    0x7000
#define BRPHY1_DSP_TAP_TAP4_C0_PAIR_OFFSET_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP4_C0_PAIR_OFFSET_BITS                    3
#define BRPHY1_DSP_TAP_TAP4_C0_PAIR_OFFSET_SHIFT                   12

/* BRPHY1_DSP_TAP :: TAP4_C0 :: GAMMA16 [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C0_GAMMA16(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C0_GAMMA16(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x800,11)
#define BRPHY1_DSP_TAP_TAP4_C0_GAMMA16_MASK                        0x0800
#define BRPHY1_DSP_TAP_TAP4_C0_GAMMA16_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP4_C0_GAMMA16_BITS                        1
#define BRPHY1_DSP_TAP_TAP4_C0_GAMMA16_SHIFT                       11

/* BRPHY1_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x400,10)
#define BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY1_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x200,9)
#define BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY1_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY1_DSP_TAP :: TAP4_C0 :: INC_PHASE [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C0_INC_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C0_INC_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x100,8)
#define BRPHY1_DSP_TAP_TAP4_C0_INC_PHASE_MASK                      0x0100
#define BRPHY1_DSP_TAP_TAP4_C0_INC_PHASE_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C0_INC_PHASE_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C0_INC_PHASE_SHIFT                     8

/* BRPHY1_DSP_TAP :: TAP4_C0 :: DEC_PHASE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C0_DEC_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C0_DEC_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x80,7)
#define BRPHY1_DSP_TAP_TAP4_C0_DEC_PHASE_MASK                      0x0080
#define BRPHY1_DSP_TAP_TAP4_C0_DEC_PHASE_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C0_DEC_PHASE_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C0_DEC_PHASE_SHIFT                     7

/* BRPHY1_DSP_TAP :: TAP4_C0 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x40,6)
#define BRPHY1_DSP_TAP_TAP4_C0_PHASE_FREEZE_MASK                   0x0040
#define BRPHY1_DSP_TAP_TAP4_C0_PHASE_FREEZE_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP4_C0_PHASE_FREEZE_BITS                   1
#define BRPHY1_DSP_TAP_TAP4_C0_PHASE_FREEZE_SHIFT                  6

/* BRPHY1_DSP_TAP :: TAP4_C0 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C0,0x3f,0)
#define BRPHY1_DSP_TAP_TAP4_C0_CURRENT_PHASE_MASK                  0x003f
#define BRPHY1_DSP_TAP_TAP4_C0_CURRENT_PHASE_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP4_C0_CURRENT_PHASE_BITS                  6
#define BRPHY1_DSP_TAP_TAP4_C0_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP4_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP4_C1 :: reserved0 [15:15] */
#define BRPHY1_DSP_TAP_TAP4_C1_RESERVED0_MASK                      0x8000
#define BRPHY1_DSP_TAP_TAP4_C1_RESERVED0_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C1_RESERVED0_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C1_RESERVED0_SHIFT                     15

/* BRPHY1_DSP_TAP :: TAP4_C1 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x7000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x7000,12)
#define BRPHY1_DSP_TAP_TAP4_C1_PAIR_OFFSET_MASK                    0x7000
#define BRPHY1_DSP_TAP_TAP4_C1_PAIR_OFFSET_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP4_C1_PAIR_OFFSET_BITS                    3
#define BRPHY1_DSP_TAP_TAP4_C1_PAIR_OFFSET_SHIFT                   12

/* BRPHY1_DSP_TAP :: TAP4_C1 :: GAMMA16 [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C1_GAMMA16(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C1_GAMMA16(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x800,11)
#define BRPHY1_DSP_TAP_TAP4_C1_GAMMA16_MASK                        0x0800
#define BRPHY1_DSP_TAP_TAP4_C1_GAMMA16_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP4_C1_GAMMA16_BITS                        1
#define BRPHY1_DSP_TAP_TAP4_C1_GAMMA16_SHIFT                       11

/* BRPHY1_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x400,10)
#define BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY1_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x200,9)
#define BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY1_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY1_DSP_TAP :: TAP4_C1 :: INC_PHASE [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C1_INC_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C1_INC_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x100,8)
#define BRPHY1_DSP_TAP_TAP4_C1_INC_PHASE_MASK                      0x0100
#define BRPHY1_DSP_TAP_TAP4_C1_INC_PHASE_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C1_INC_PHASE_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C1_INC_PHASE_SHIFT                     8

/* BRPHY1_DSP_TAP :: TAP4_C1 :: DEC_PHASE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C1_DEC_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C1_DEC_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x80,7)
#define BRPHY1_DSP_TAP_TAP4_C1_DEC_PHASE_MASK                      0x0080
#define BRPHY1_DSP_TAP_TAP4_C1_DEC_PHASE_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C1_DEC_PHASE_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C1_DEC_PHASE_SHIFT                     7

/* BRPHY1_DSP_TAP :: TAP4_C1 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x40,6)
#define BRPHY1_DSP_TAP_TAP4_C1_PHASE_FREEZE_MASK                   0x0040
#define BRPHY1_DSP_TAP_TAP4_C1_PHASE_FREEZE_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP4_C1_PHASE_FREEZE_BITS                   1
#define BRPHY1_DSP_TAP_TAP4_C1_PHASE_FREEZE_SHIFT                  6

/* BRPHY1_DSP_TAP :: TAP4_C1 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C1,0x3f,0)
#define BRPHY1_DSP_TAP_TAP4_C1_CURRENT_PHASE_MASK                  0x003f
#define BRPHY1_DSP_TAP_TAP4_C1_CURRENT_PHASE_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP4_C1_CURRENT_PHASE_BITS                  6
#define BRPHY1_DSP_TAP_TAP4_C1_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP4_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP4_C2 :: reserved0 [15:15] */
#define BRPHY1_DSP_TAP_TAP4_C2_RESERVED0_MASK                      0x8000
#define BRPHY1_DSP_TAP_TAP4_C2_RESERVED0_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C2_RESERVED0_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C2_RESERVED0_SHIFT                     15

/* BRPHY1_DSP_TAP :: TAP4_C2 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x7000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x7000,12)
#define BRPHY1_DSP_TAP_TAP4_C2_PAIR_OFFSET_MASK                    0x7000
#define BRPHY1_DSP_TAP_TAP4_C2_PAIR_OFFSET_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP4_C2_PAIR_OFFSET_BITS                    3
#define BRPHY1_DSP_TAP_TAP4_C2_PAIR_OFFSET_SHIFT                   12

/* BRPHY1_DSP_TAP :: TAP4_C2 :: GAMMA16 [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C2_GAMMA16(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C2_GAMMA16(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x800,11)
#define BRPHY1_DSP_TAP_TAP4_C2_GAMMA16_MASK                        0x0800
#define BRPHY1_DSP_TAP_TAP4_C2_GAMMA16_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP4_C2_GAMMA16_BITS                        1
#define BRPHY1_DSP_TAP_TAP4_C2_GAMMA16_SHIFT                       11

/* BRPHY1_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x400,10)
#define BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY1_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x200,9)
#define BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY1_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY1_DSP_TAP :: TAP4_C2 :: INC_PHASE [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C2_INC_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C2_INC_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x100,8)
#define BRPHY1_DSP_TAP_TAP4_C2_INC_PHASE_MASK                      0x0100
#define BRPHY1_DSP_TAP_TAP4_C2_INC_PHASE_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C2_INC_PHASE_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C2_INC_PHASE_SHIFT                     8

/* BRPHY1_DSP_TAP :: TAP4_C2 :: DEC_PHASE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C2_DEC_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C2_DEC_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x80,7)
#define BRPHY1_DSP_TAP_TAP4_C2_DEC_PHASE_MASK                      0x0080
#define BRPHY1_DSP_TAP_TAP4_C2_DEC_PHASE_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C2_DEC_PHASE_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C2_DEC_PHASE_SHIFT                     7

/* BRPHY1_DSP_TAP :: TAP4_C2 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x40,6)
#define BRPHY1_DSP_TAP_TAP4_C2_PHASE_FREEZE_MASK                   0x0040
#define BRPHY1_DSP_TAP_TAP4_C2_PHASE_FREEZE_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP4_C2_PHASE_FREEZE_BITS                   1
#define BRPHY1_DSP_TAP_TAP4_C2_PHASE_FREEZE_SHIFT                  6

/* BRPHY1_DSP_TAP :: TAP4_C2 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C2,0x3f,0)
#define BRPHY1_DSP_TAP_TAP4_C2_CURRENT_PHASE_MASK                  0x003f
#define BRPHY1_DSP_TAP_TAP4_C2_CURRENT_PHASE_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP4_C2_CURRENT_PHASE_BITS                  6
#define BRPHY1_DSP_TAP_TAP4_C2_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP4_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP4_C3 :: reserved0 [15:15] */
#define BRPHY1_DSP_TAP_TAP4_C3_RESERVED0_MASK                      0x8000
#define BRPHY1_DSP_TAP_TAP4_C3_RESERVED0_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C3_RESERVED0_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C3_RESERVED0_SHIFT                     15

/* BRPHY1_DSP_TAP :: TAP4_C3 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x7000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x7000,12)
#define BRPHY1_DSP_TAP_TAP4_C3_PAIR_OFFSET_MASK                    0x7000
#define BRPHY1_DSP_TAP_TAP4_C3_PAIR_OFFSET_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP4_C3_PAIR_OFFSET_BITS                    3
#define BRPHY1_DSP_TAP_TAP4_C3_PAIR_OFFSET_SHIFT                   12

/* BRPHY1_DSP_TAP :: TAP4_C3 :: GAMMA16 [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C3_GAMMA16(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C3_GAMMA16(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x800,11)
#define BRPHY1_DSP_TAP_TAP4_C3_GAMMA16_MASK                        0x0800
#define BRPHY1_DSP_TAP_TAP4_C3_GAMMA16_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP4_C3_GAMMA16_BITS                        1
#define BRPHY1_DSP_TAP_TAP4_C3_GAMMA16_SHIFT                       11

/* BRPHY1_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x400,10)
#define BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY1_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x200,9)
#define BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY1_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY1_DSP_TAP :: TAP4_C3 :: INC_PHASE [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C3_INC_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C3_INC_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x100,8)
#define BRPHY1_DSP_TAP_TAP4_C3_INC_PHASE_MASK                      0x0100
#define BRPHY1_DSP_TAP_TAP4_C3_INC_PHASE_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C3_INC_PHASE_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C3_INC_PHASE_SHIFT                     8

/* BRPHY1_DSP_TAP :: TAP4_C3 :: DEC_PHASE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C3_DEC_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C3_DEC_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x80,7)
#define BRPHY1_DSP_TAP_TAP4_C3_DEC_PHASE_MASK                      0x0080
#define BRPHY1_DSP_TAP_TAP4_C3_DEC_PHASE_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP4_C3_DEC_PHASE_BITS                      1
#define BRPHY1_DSP_TAP_TAP4_C3_DEC_PHASE_SHIFT                     7

/* BRPHY1_DSP_TAP :: TAP4_C3 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x40,6)
#define BRPHY1_DSP_TAP_TAP4_C3_PHASE_FREEZE_MASK                   0x0040
#define BRPHY1_DSP_TAP_TAP4_C3_PHASE_FREEZE_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP4_C3_PHASE_FREEZE_BITS                   1
#define BRPHY1_DSP_TAP_TAP4_C3_PHASE_FREEZE_SHIFT                  6

/* BRPHY1_DSP_TAP :: TAP4_C3 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP4_C3,0x3f,0)
#define BRPHY1_DSP_TAP_TAP4_C3_CURRENT_PHASE_MASK                  0x003f
#define BRPHY1_DSP_TAP_TAP4_C3_CURRENT_PHASE_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP4_C3_CURRENT_PHASE_BITS                  6
#define BRPHY1_DSP_TAP_TAP4_C3_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP5_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP5_C0 :: reserved0 [15:14] */
#define BRPHY1_DSP_TAP_TAP5_C0_RESERVED0_MASK                      0xc000
#define BRPHY1_DSP_TAP_TAP5_C0_RESERVED0_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP5_C0_RESERVED0_BITS                      2
#define BRPHY1_DSP_TAP_TAP5_C0_RESERVED0_SHIFT                     14

/* BRPHY1_DSP_TAP :: TAP5_C0 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_SLICE_ZERO(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_SLICE_ZERO(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x2000,13)
#define BRPHY1_DSP_TAP_TAP5_C0_SLICE_ZERO_MASK                     0x2000
#define BRPHY1_DSP_TAP_TAP5_C0_SLICE_ZERO_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP5_C0_SLICE_ZERO_BITS                     1
#define BRPHY1_DSP_TAP_TAP5_C0_SLICE_ZERO_SHIFT                    13

/* BRPHY1_DSP_TAP :: TAP5_C0 :: DISABLE_TX [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_DISABLE_TX(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_DISABLE_TX(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x1000,12)
#define BRPHY1_DSP_TAP_TAP5_C0_DISABLE_TX_MASK                     0x1000
#define BRPHY1_DSP_TAP_TAP5_C0_DISABLE_TX_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP5_C0_DISABLE_TX_BITS                     1
#define BRPHY1_DSP_TAP_TAP5_C0_DISABLE_TX_SHIFT                    12

/* BRPHY1_DSP_TAP :: TAP5_C0 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x800,11)
#define BRPHY1_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY1_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY1_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY1_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY1_DSP_TAP :: TAP5_C0 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x400,10)
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY1_DSP_TAP :: TAP5_C0 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x3c0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x3c0,6)
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_MASK                      0x03c0
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_BITS                      4
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SKEW_SHIFT                     6

/* BRPHY1_DSP_TAP :: TAP5_C0 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x20,5)
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_BITS              1
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY1_DSP_TAP :: TAP5_C0 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_PAIR_SELECT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x18,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_PAIR_SELECT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x18,3)
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SELECT_MASK                    0x0018
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SELECT_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SELECT_BITS                    2
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_SELECT_SHIFT                   3

/* BRPHY1_DSP_TAP :: TAP5_C0 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x4,2)
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_POLARITY_MASK                  0x0004
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_POLARITY_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_POLARITY_BITS                  1
#define BRPHY1_DSP_TAP_TAP5_C0_PAIR_POLARITY_SHIFT                 2

/* BRPHY1_DSP_TAP :: TAP5_C0 :: SWAPCD [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_SWAPCD(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_SWAPCD(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x2,1)
#define BRPHY1_DSP_TAP_TAP5_C0_SWAPCD_MASK                         0x0002
#define BRPHY1_DSP_TAP_TAP5_C0_SWAPCD_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP5_C0_SWAPCD_BITS                         1
#define BRPHY1_DSP_TAP_TAP5_C0_SWAPCD_SHIFT                        1

/* BRPHY1_DSP_TAP :: TAP5_C0 :: SWAPAB [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C0_SWAPAB(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C0_SWAPAB(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C0,0x1,0)
#define BRPHY1_DSP_TAP_TAP5_C0_SWAPAB_MASK                         0x0001
#define BRPHY1_DSP_TAP_TAP5_C0_SWAPAB_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP5_C0_SWAPAB_BITS                         1
#define BRPHY1_DSP_TAP_TAP5_C0_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP5_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP5_C1 :: reserved0 [15:14] */
#define BRPHY1_DSP_TAP_TAP5_C1_RESERVED0_MASK                      0xc000
#define BRPHY1_DSP_TAP_TAP5_C1_RESERVED0_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP5_C1_RESERVED0_BITS                      2
#define BRPHY1_DSP_TAP_TAP5_C1_RESERVED0_SHIFT                     14

/* BRPHY1_DSP_TAP :: TAP5_C1 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_SLICE_ZERO(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_SLICE_ZERO(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x2000,13)
#define BRPHY1_DSP_TAP_TAP5_C1_SLICE_ZERO_MASK                     0x2000
#define BRPHY1_DSP_TAP_TAP5_C1_SLICE_ZERO_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP5_C1_SLICE_ZERO_BITS                     1
#define BRPHY1_DSP_TAP_TAP5_C1_SLICE_ZERO_SHIFT                    13

/* BRPHY1_DSP_TAP :: TAP5_C1 :: DISABLE_TX [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_DISABLE_TX(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_DISABLE_TX(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x1000,12)
#define BRPHY1_DSP_TAP_TAP5_C1_DISABLE_TX_MASK                     0x1000
#define BRPHY1_DSP_TAP_TAP5_C1_DISABLE_TX_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP5_C1_DISABLE_TX_BITS                     1
#define BRPHY1_DSP_TAP_TAP5_C1_DISABLE_TX_SHIFT                    12

/* BRPHY1_DSP_TAP :: TAP5_C1 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x800,11)
#define BRPHY1_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY1_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY1_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY1_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY1_DSP_TAP :: TAP5_C1 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x400,10)
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY1_DSP_TAP :: TAP5_C1 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x3c0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x3c0,6)
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_MASK                      0x03c0
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_BITS                      4
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SKEW_SHIFT                     6

/* BRPHY1_DSP_TAP :: TAP5_C1 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x20,5)
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_BITS              1
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY1_DSP_TAP :: TAP5_C1 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_PAIR_SELECT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x18,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_PAIR_SELECT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x18,3)
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SELECT_MASK                    0x0018
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SELECT_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SELECT_BITS                    2
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_SELECT_SHIFT                   3

/* BRPHY1_DSP_TAP :: TAP5_C1 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x4,2)
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_POLARITY_MASK                  0x0004
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_POLARITY_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_POLARITY_BITS                  1
#define BRPHY1_DSP_TAP_TAP5_C1_PAIR_POLARITY_SHIFT                 2

/* BRPHY1_DSP_TAP :: TAP5_C1 :: SWAPCD [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_SWAPCD(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_SWAPCD(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x2,1)
#define BRPHY1_DSP_TAP_TAP5_C1_SWAPCD_MASK                         0x0002
#define BRPHY1_DSP_TAP_TAP5_C1_SWAPCD_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP5_C1_SWAPCD_BITS                         1
#define BRPHY1_DSP_TAP_TAP5_C1_SWAPCD_SHIFT                        1

/* BRPHY1_DSP_TAP :: TAP5_C1 :: SWAPAB [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C1_SWAPAB(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C1_SWAPAB(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C1,0x1,0)
#define BRPHY1_DSP_TAP_TAP5_C1_SWAPAB_MASK                         0x0001
#define BRPHY1_DSP_TAP_TAP5_C1_SWAPAB_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP5_C1_SWAPAB_BITS                         1
#define BRPHY1_DSP_TAP_TAP5_C1_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP5_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP5_C2 :: reserved0 [15:14] */
#define BRPHY1_DSP_TAP_TAP5_C2_RESERVED0_MASK                      0xc000
#define BRPHY1_DSP_TAP_TAP5_C2_RESERVED0_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP5_C2_RESERVED0_BITS                      2
#define BRPHY1_DSP_TAP_TAP5_C2_RESERVED0_SHIFT                     14

/* BRPHY1_DSP_TAP :: TAP5_C2 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_SLICE_ZERO(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_SLICE_ZERO(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x2000,13)
#define BRPHY1_DSP_TAP_TAP5_C2_SLICE_ZERO_MASK                     0x2000
#define BRPHY1_DSP_TAP_TAP5_C2_SLICE_ZERO_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP5_C2_SLICE_ZERO_BITS                     1
#define BRPHY1_DSP_TAP_TAP5_C2_SLICE_ZERO_SHIFT                    13

/* BRPHY1_DSP_TAP :: TAP5_C2 :: DISABLE_TX [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_DISABLE_TX(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_DISABLE_TX(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x1000,12)
#define BRPHY1_DSP_TAP_TAP5_C2_DISABLE_TX_MASK                     0x1000
#define BRPHY1_DSP_TAP_TAP5_C2_DISABLE_TX_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP5_C2_DISABLE_TX_BITS                     1
#define BRPHY1_DSP_TAP_TAP5_C2_DISABLE_TX_SHIFT                    12

/* BRPHY1_DSP_TAP :: TAP5_C2 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x800,11)
#define BRPHY1_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY1_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY1_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY1_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY1_DSP_TAP :: TAP5_C2 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x400,10)
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY1_DSP_TAP :: TAP5_C2 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x3c0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x3c0,6)
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_MASK                      0x03c0
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_BITS                      4
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SKEW_SHIFT                     6

/* BRPHY1_DSP_TAP :: TAP5_C2 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x20,5)
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_BITS              1
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY1_DSP_TAP :: TAP5_C2 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_PAIR_SELECT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x18,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_PAIR_SELECT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x18,3)
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SELECT_MASK                    0x0018
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SELECT_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SELECT_BITS                    2
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_SELECT_SHIFT                   3

/* BRPHY1_DSP_TAP :: TAP5_C2 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x4,2)
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_POLARITY_MASK                  0x0004
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_POLARITY_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_POLARITY_BITS                  1
#define BRPHY1_DSP_TAP_TAP5_C2_PAIR_POLARITY_SHIFT                 2

/* BRPHY1_DSP_TAP :: TAP5_C2 :: SWAPCD [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_SWAPCD(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_SWAPCD(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x2,1)
#define BRPHY1_DSP_TAP_TAP5_C2_SWAPCD_MASK                         0x0002
#define BRPHY1_DSP_TAP_TAP5_C2_SWAPCD_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP5_C2_SWAPCD_BITS                         1
#define BRPHY1_DSP_TAP_TAP5_C2_SWAPCD_SHIFT                        1

/* BRPHY1_DSP_TAP :: TAP5_C2 :: SWAPAB [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C2_SWAPAB(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C2_SWAPAB(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C2,0x1,0)
#define BRPHY1_DSP_TAP_TAP5_C2_SWAPAB_MASK                         0x0001
#define BRPHY1_DSP_TAP_TAP5_C2_SWAPAB_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP5_C2_SWAPAB_BITS                         1
#define BRPHY1_DSP_TAP_TAP5_C2_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP5_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP5_C3 :: reserved0 [15:14] */
#define BRPHY1_DSP_TAP_TAP5_C3_RESERVED0_MASK                      0xc000
#define BRPHY1_DSP_TAP_TAP5_C3_RESERVED0_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP5_C3_RESERVED0_BITS                      2
#define BRPHY1_DSP_TAP_TAP5_C3_RESERVED0_SHIFT                     14

/* BRPHY1_DSP_TAP :: TAP5_C3 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_SLICE_ZERO(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_SLICE_ZERO(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x2000,13)
#define BRPHY1_DSP_TAP_TAP5_C3_SLICE_ZERO_MASK                     0x2000
#define BRPHY1_DSP_TAP_TAP5_C3_SLICE_ZERO_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP5_C3_SLICE_ZERO_BITS                     1
#define BRPHY1_DSP_TAP_TAP5_C3_SLICE_ZERO_SHIFT                    13

/* BRPHY1_DSP_TAP :: TAP5_C3 :: DISABLE_TX [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_DISABLE_TX(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_DISABLE_TX(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x1000,12)
#define BRPHY1_DSP_TAP_TAP5_C3_DISABLE_TX_MASK                     0x1000
#define BRPHY1_DSP_TAP_TAP5_C3_DISABLE_TX_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP5_C3_DISABLE_TX_BITS                     1
#define BRPHY1_DSP_TAP_TAP5_C3_DISABLE_TX_SHIFT                    12

/* BRPHY1_DSP_TAP :: TAP5_C3 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x800,11)
#define BRPHY1_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY1_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY1_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY1_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY1_DSP_TAP :: TAP5_C3 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x400,10)
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY1_DSP_TAP :: TAP5_C3 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x3c0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x3c0,6)
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_MASK                      0x03c0
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_BITS                      4
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SKEW_SHIFT                     6

/* BRPHY1_DSP_TAP :: TAP5_C3 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x20,5)
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_BITS              1
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY1_DSP_TAP :: TAP5_C3 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_PAIR_SELECT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x18,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_PAIR_SELECT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x18,3)
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SELECT_MASK                    0x0018
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SELECT_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SELECT_BITS                    2
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_SELECT_SHIFT                   3

/* BRPHY1_DSP_TAP :: TAP5_C3 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x4,2)
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_POLARITY_MASK                  0x0004
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_POLARITY_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_POLARITY_BITS                  1
#define BRPHY1_DSP_TAP_TAP5_C3_PAIR_POLARITY_SHIFT                 2

/* BRPHY1_DSP_TAP :: TAP5_C3 :: SWAPCD [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_SWAPCD(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_SWAPCD(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x2,1)
#define BRPHY1_DSP_TAP_TAP5_C3_SWAPCD_MASK                         0x0002
#define BRPHY1_DSP_TAP_TAP5_C3_SWAPCD_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP5_C3_SWAPCD_BITS                         1
#define BRPHY1_DSP_TAP_TAP5_C3_SWAPCD_SHIFT                        1

/* BRPHY1_DSP_TAP :: TAP5_C3 :: SWAPAB [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP5_C3_SWAPAB(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP5_C3_SWAPAB(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP5_C3,0x1,0)
#define BRPHY1_DSP_TAP_TAP5_C3_SWAPAB_MASK                         0x0001
#define BRPHY1_DSP_TAP_TAP5_C3_SWAPAB_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP5_C3_SWAPAB_BITS                         1
#define BRPHY1_DSP_TAP_TAP5_C3_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP6
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP6 :: CFCDEADMAN_DIS [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP6,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP6,0x8000,15)
#define BRPHY1_DSP_TAP_TAP6_CFCDEADMAN_DIS_MASK                    0x8000
#define BRPHY1_DSP_TAP_TAP6_CFCDEADMAN_DIS_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP6_CFCDEADMAN_DIS_BITS                    1
#define BRPHY1_DSP_TAP_TAP6_CFCDEADMAN_DIS_SHIFT                   15

/* BRPHY1_DSP_TAP :: TAP6 :: AGC_FREEZ_EN [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP6_AGC_FREEZ_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP6,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP6_AGC_FREEZ_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP6,0x4000,14)
#define BRPHY1_DSP_TAP_TAP6_AGC_FREEZ_EN_MASK                      0x4000
#define BRPHY1_DSP_TAP_TAP6_AGC_FREEZ_EN_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP6_AGC_FREEZ_EN_BITS                      1
#define BRPHY1_DSP_TAP_TAP6_AGC_FREEZ_EN_SHIFT                     14

/* BRPHY1_DSP_TAP :: TAP6 :: DAC_GAIN_INV_EN [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP6,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP6,0x2000,13)
#define BRPHY1_DSP_TAP_TAP6_DAC_GAIN_INV_EN_MASK                   0x2000
#define BRPHY1_DSP_TAP_TAP6_DAC_GAIN_INV_EN_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP6_DAC_GAIN_INV_EN_BITS                   1
#define BRPHY1_DSP_TAP_TAP6_DAC_GAIN_INV_EN_SHIFT                  13

/* BRPHY1_DSP_TAP :: TAP6 :: SPARE_REG_B12 [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP6_SPARE_REG_B12(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP6,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP6_SPARE_REG_B12(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP6,0x1000,12)
#define BRPHY1_DSP_TAP_TAP6_SPARE_REG_B12_MASK                     0x1000
#define BRPHY1_DSP_TAP_TAP6_SPARE_REG_B12_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP6_SPARE_REG_B12_BITS                     1
#define BRPHY1_DSP_TAP_TAP6_SPARE_REG_B12_SHIFT                    12

/* BRPHY1_DSP_TAP :: TAP6 :: FORCE_FSM_IDLE [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP6,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP6,0x800,11)
#define BRPHY1_DSP_TAP_TAP6_FORCE_FSM_IDLE_MASK                    0x0800
#define BRPHY1_DSP_TAP_TAP6_FORCE_FSM_IDLE_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP6_FORCE_FSM_IDLE_BITS                    1
#define BRPHY1_DSP_TAP_TAP6_FORCE_FSM_IDLE_SHIFT                   11

/* BRPHY1_DSP_TAP :: TAP6 :: SPARE_REG [10:00] */
#define Wr_BRPHY1_DSP_TAP_TAP6_SPARE_REG(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP6,0x7ff,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP6_SPARE_REG(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP6,0x7ff,0)
#define BRPHY1_DSP_TAP_TAP6_SPARE_REG_MASK                         0x07ff
#define BRPHY1_DSP_TAP_TAP6_SPARE_REG_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP6_SPARE_REG_BITS                         11
#define BRPHY1_DSP_TAP_TAP6_SPARE_REG_SHIFT                        0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP7_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP7_C0 :: TEST_LENGTH [15:09] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_TEST_LENGTH(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0xfe00,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_TEST_LENGTH(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0xfe00,9)
#define BRPHY1_DSP_TAP_TAP7_C0_TEST_LENGTH_MASK                    0xfe00
#define BRPHY1_DSP_TAP_TAP7_C0_TEST_LENGTH_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP7_C0_TEST_LENGTH_BITS                    7
#define BRPHY1_DSP_TAP_TAP7_C0_TEST_LENGTH_SHIFT                   9

/* BRPHY1_DSP_TAP :: TAP7_C0 :: SINGLE_TAP_MODE [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x100,8)
#define BRPHY1_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_MASK                0x0100
#define BRPHY1_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_ALIGN               0
#define BRPHY1_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_BITS                1
#define BRPHY1_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_SHIFT               8

/* BRPHY1_DSP_TAP :: TAP7_C0 :: UPDATE_MODE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x80,7)
#define BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MODE_MASK                    0x0080
#define BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MODE_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MODE_BITS                    1
#define BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MODE_SHIFT                   7

/* BRPHY1_DSP_TAP :: TAP7_C0 :: UPDATE_MAGNITUDE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x40,6)
#define BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_MASK               0x0040
#define BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_BITS               1
#define BRPHY1_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_SHIFT              6

/* BRPHY1_DSP_TAP :: TAP7_C0 :: START_TEST [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_START_TEST(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_START_TEST(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x20,5)
#define BRPHY1_DSP_TAP_TAP7_C0_START_TEST_MASK                     0x0020
#define BRPHY1_DSP_TAP_TAP7_C0_START_TEST_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP7_C0_START_TEST_BITS                     1
#define BRPHY1_DSP_TAP_TAP7_C0_START_TEST_SHIFT                    5

/* BRPHY1_DSP_TAP :: TAP7_C0 :: ZERO_DFE_D [04:04] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x10,4)
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_D_MASK                     0x0010
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_D_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_D_BITS                     1
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_D_SHIFT                    4

/* BRPHY1_DSP_TAP :: TAP7_C0 :: ZERO_DFE_C [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x8,3)
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_C_MASK                     0x0008
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_C_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_C_BITS                     1
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_C_SHIFT                    3

/* BRPHY1_DSP_TAP :: TAP7_C0 :: ZERO_DFE_B [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x4,2)
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_B_MASK                     0x0004
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_B_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_B_BITS                     1
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_B_SHIFT                    2

/* BRPHY1_DSP_TAP :: TAP7_C0 :: ZERO_DFE_A [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x2,1)
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_A_MASK                     0x0002
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_A_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_A_BITS                     1
#define BRPHY1_DSP_TAP_TAP7_C0_ZERO_DFE_A_SHIFT                    1

/* BRPHY1_DSP_TAP :: TAP7_C0 :: ENABLE_BIST_MODE [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C0,0x1,0)
#define BRPHY1_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_MASK               0x0001
#define BRPHY1_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_BITS               1
#define BRPHY1_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_SHIFT              0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP7_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP7_C1 :: TAP_NUMBER [15:08] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C1_TAP_NUMBER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C1,0xff00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C1_TAP_NUMBER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C1,0xff00,8)
#define BRPHY1_DSP_TAP_TAP7_C1_TAP_NUMBER_MASK                     0xff00
#define BRPHY1_DSP_TAP_TAP7_C1_TAP_NUMBER_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP7_C1_TAP_NUMBER_BITS                     8
#define BRPHY1_DSP_TAP_TAP7_C1_TAP_NUMBER_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP7_C1 :: POLARITY_MASK_LSB [07:00] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C1,0xff,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C1,0xff,0)
#define BRPHY1_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_MASK              0x00ff
#define BRPHY1_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_ALIGN             0
#define BRPHY1_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_BITS              8
#define BRPHY1_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_SHIFT             0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP7_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP7_C2 :: SPARE [15:08] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C2_SPARE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0xff00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C2_SPARE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0xff00,8)
#define BRPHY1_DSP_TAP_TAP7_C2_SPARE_MASK                          0xff00
#define BRPHY1_DSP_TAP_TAP7_C2_SPARE_ALIGN                         0
#define BRPHY1_DSP_TAP_TAP7_C2_SPARE_BITS                          8
#define BRPHY1_DSP_TAP_TAP7_C2_SPARE_SHIFT                         8

/* BRPHY1_DSP_TAP :: TAP7_C2 :: BIST_FFE_UPDATE_EN [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x80,7)
#define BRPHY1_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_MASK             0x0080
#define BRPHY1_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_ALIGN            0
#define BRPHY1_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_BITS             1
#define BRPHY1_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_SHIFT            7

/* BRPHY1_DSP_TAP :: TAP7_C2 :: DISABLE_RANDOM_BIST_ADC [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x40,6)
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_MASK        0x0040
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_ALIGN       0
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_BITS        1
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_SHIFT       6

/* BRPHY1_DSP_TAP :: TAP7_C2 :: DISABLE_VITERBI_TO_BIST [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x20,5)
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_MASK        0x0020
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_ALIGN       0
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_BITS        1
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_SHIFT       5

/* BRPHY1_DSP_TAP :: TAP7_C2 :: USE_BIST_FOR_DFE [04:04] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x10,4)
#define BRPHY1_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_MASK               0x0010
#define BRPHY1_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_BITS               1
#define BRPHY1_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_SHIFT              4

/* BRPHY1_DSP_TAP :: TAP7_C2 :: FORCE_VITERBI_MODE [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x8,3)
#define BRPHY1_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_MASK             0x0008
#define BRPHY1_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_ALIGN            0
#define BRPHY1_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_BITS             1
#define BRPHY1_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_SHIFT            3

/* BRPHY1_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_IPRK_OV [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x4,2)
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_MASK           0x0004
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_ALIGN          0
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_BITS           1
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_SHIFT          2

/* BRPHY1_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_GAMMA_OV [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x2,1)
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_MASK          0x0002
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_ALIGN         0
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_BITS          1
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_SHIFT         1

/* BRPHY1_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_ADC_OV [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP7_C2,0x1,0)
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_MASK            0x0001
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_ALIGN           0
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_BITS            1
#define BRPHY1_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_SHIFT           0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP8_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP8_C0 :: PGA_OV [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_PGA_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_PGA_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x8000,15)
#define BRPHY1_DSP_TAP_TAP8_C0_PGA_OV_MASK                         0x8000
#define BRPHY1_DSP_TAP_TAP8_C0_PGA_OV_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP8_C0_PGA_OV_BITS                         1
#define BRPHY1_DSP_TAP_TAP8_C0_PGA_OV_SHIFT                        15

/* BRPHY1_DSP_TAP :: TAP8_C0 :: TIMER_OV [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_TIMER_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_TIMER_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x4000,14)
#define BRPHY1_DSP_TAP_TAP8_C0_TIMER_OV_MASK                       0x4000
#define BRPHY1_DSP_TAP_TAP8_C0_TIMER_OV_ALIGN                      0
#define BRPHY1_DSP_TAP_TAP8_C0_TIMER_OV_BITS                       1
#define BRPHY1_DSP_TAP_TAP8_C0_TIMER_OV_SHIFT                      14

/* BRPHY1_DSP_TAP :: TAP8_C0 :: MONOTONICITY_MODE [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x2000,13)
#define BRPHY1_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_MASK              0x2000
#define BRPHY1_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_ALIGN             0
#define BRPHY1_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_BITS              1
#define BRPHY1_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_SHIFT             13

/* BRPHY1_DSP_TAP :: TAP8_C0 :: FREEZE_ERROR_ON_FAIL [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x1000,12)
#define BRPHY1_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_MASK           0x1000
#define BRPHY1_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_ALIGN          0
#define BRPHY1_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_BITS           1
#define BRPHY1_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_SHIFT          12

/* BRPHY1_DSP_TAP :: TAP8_C0 :: FREEZE_MSE_ON_FAIL [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x800,11)
#define BRPHY1_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_MASK             0x0800
#define BRPHY1_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_ALIGN            0
#define BRPHY1_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_BITS             1
#define BRPHY1_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_SHIFT            11

/* BRPHY1_DSP_TAP :: TAP8_C0 :: FAST_CONV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x400,10)
#define BRPHY1_DSP_TAP_TAP8_C0_FAST_CONV_EN_MASK                   0x0400
#define BRPHY1_DSP_TAP_TAP8_C0_FAST_CONV_EN_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP8_C0_FAST_CONV_EN_BITS                   1
#define BRPHY1_DSP_TAP_TAP8_C0_FAST_CONV_EN_SHIFT                  10

/* BRPHY1_DSP_TAP :: TAP8_C0 :: PGA_TOGGLE_MODE_EN [09:09] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x200,9)
#define BRPHY1_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_MASK             0x0200
#define BRPHY1_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_ALIGN            0
#define BRPHY1_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_BITS             1
#define BRPHY1_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_SHIFT            9

/* BRPHY1_DSP_TAP :: TAP8_C0 :: PAT_GEN_EN [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x100,8)
#define BRPHY1_DSP_TAP_TAP8_C0_PAT_GEN_EN_MASK                     0x0100
#define BRPHY1_DSP_TAP_TAP8_C0_PAT_GEN_EN_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP8_C0_PAT_GEN_EN_BITS                     1
#define BRPHY1_DSP_TAP_TAP8_C0_PAT_GEN_EN_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP8_C0 :: MAX_OFFSET_CHECK_EN [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x80,7)
#define BRPHY1_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_MASK            0x0080
#define BRPHY1_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_ALIGN           0
#define BRPHY1_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_BITS            1
#define BRPHY1_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_SHIFT           7

/* BRPHY1_DSP_TAP :: TAP8_C0 :: SYM_ERR_CHECK_EN [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x40,6)
#define BRPHY1_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_MASK               0x0040
#define BRPHY1_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_ALIGN              0
#define BRPHY1_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_BITS               1
#define BRPHY1_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_SHIFT              6

/* BRPHY1_DSP_TAP :: TAP8_C0 :: PEAK_ERR_CHECK_EN [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x20,5)
#define BRPHY1_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_MASK              0x0020
#define BRPHY1_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_ALIGN             0
#define BRPHY1_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_BITS              1
#define BRPHY1_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_SHIFT             5

/* BRPHY1_DSP_TAP :: TAP8_C0 :: MSE_CHECK_EN [04:04] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x10,4)
#define BRPHY1_DSP_TAP_TAP8_C0_MSE_CHECK_EN_MASK                   0x0010
#define BRPHY1_DSP_TAP_TAP8_C0_MSE_CHECK_EN_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP8_C0_MSE_CHECK_EN_BITS                   1
#define BRPHY1_DSP_TAP_TAP8_C0_MSE_CHECK_EN_SHIFT                  4

/* BRPHY1_DSP_TAP :: TAP8_C0 :: GAIN_AMP_CHECK_EN [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x8,3)
#define BRPHY1_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_MASK              0x0008
#define BRPHY1_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_ALIGN             0
#define BRPHY1_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_BITS              1
#define BRPHY1_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_SHIFT             3

/* BRPHY1_DSP_TAP :: TAP8_C0 :: HALT_ON_ERROR [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x4,2)
#define BRPHY1_DSP_TAP_TAP8_C0_HALT_ON_ERROR_MASK                  0x0004
#define BRPHY1_DSP_TAP_TAP8_C0_HALT_ON_ERROR_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP8_C0_HALT_ON_ERROR_BITS                  1
#define BRPHY1_DSP_TAP_TAP8_C0_HALT_ON_ERROR_SHIFT                 2

/* BRPHY1_DSP_TAP :: TAP8_C0 :: START_ABIST [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_START_ABIST(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_START_ABIST(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x2,1)
#define BRPHY1_DSP_TAP_TAP8_C0_START_ABIST_MASK                    0x0002
#define BRPHY1_DSP_TAP_TAP8_C0_START_ABIST_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP8_C0_START_ABIST_BITS                    1
#define BRPHY1_DSP_TAP_TAP8_C0_START_ABIST_SHIFT                   1

/* BRPHY1_DSP_TAP :: TAP8_C0 :: ABIST_EN [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C0_ABIST_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C0_ABIST_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C0,0x1,0)
#define BRPHY1_DSP_TAP_TAP8_C0_ABIST_EN_MASK                       0x0001
#define BRPHY1_DSP_TAP_TAP8_C0_ABIST_EN_ALIGN                      0
#define BRPHY1_DSP_TAP_TAP8_C0_ABIST_EN_BITS                       1
#define BRPHY1_DSP_TAP_TAP8_C0_ABIST_EN_SHIFT                      0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP8_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP8_C1 :: MAJOR_MODE [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_MAJOR_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_MAJOR_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x8000,15)
#define BRPHY1_DSP_TAP_TAP8_C1_MAJOR_MODE_MASK                     0x8000
#define BRPHY1_DSP_TAP_TAP8_C1_MAJOR_MODE_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP8_C1_MAJOR_MODE_BITS                     1
#define BRPHY1_DSP_TAP_TAP8_C1_MAJOR_MODE_SHIFT                    15

/* BRPHY1_DSP_TAP :: TAP8_C1 :: MULTIPLE_MSE [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x4000,14)
#define BRPHY1_DSP_TAP_TAP8_C1_MULTIPLE_MSE_MASK                   0x4000
#define BRPHY1_DSP_TAP_TAP8_C1_MULTIPLE_MSE_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP8_C1_MULTIPLE_MSE_BITS                   1
#define BRPHY1_DSP_TAP_TAP8_C1_MULTIPLE_MSE_SHIFT                  14

/* BRPHY1_DSP_TAP :: TAP8_C1 :: GAMMA_OV [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_GAMMA_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_GAMMA_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x2000,13)
#define BRPHY1_DSP_TAP_TAP8_C1_GAMMA_OV_MASK                       0x2000
#define BRPHY1_DSP_TAP_TAP8_C1_GAMMA_OV_ALIGN                      0
#define BRPHY1_DSP_TAP_TAP8_C1_GAMMA_OV_BITS                       1
#define BRPHY1_DSP_TAP_TAP8_C1_GAMMA_OV_SHIFT                      13

/* BRPHY1_DSP_TAP :: TAP8_C1 :: FFE_COARSE_OV [12:08] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x1f00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x1f00,8)
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_COARSE_OV_MASK                  0x1f00
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_COARSE_OV_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_COARSE_OV_BITS                  5
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_COARSE_OV_SHIFT                 8

/* BRPHY1_DSP_TAP :: TAP8_C1 :: FFE_PF_OV_INIT [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x80,7)
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_MASK                 0x0080
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_ALIGN                0
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_BITS                 1
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_SHIFT                7

/* BRPHY1_DSP_TAP :: TAP8_C1 :: SINGLE_STEP_MODE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x40,6)
#define BRPHY1_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_MASK               0x0040
#define BRPHY1_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_BITS               1
#define BRPHY1_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_SHIFT              6

/* BRPHY1_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SEL [05:04] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x30,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x30,4)
#define BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_MASK               0x0030
#define BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_ALIGN              0
#define BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_BITS               2
#define BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_SHIFT              4

/* BRPHY1_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SE_EN [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x8,3)
#define BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_MASK             0x0008
#define BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_ALIGN            0
#define BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_BITS             1
#define BRPHY1_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_SHIFT            3

/* BRPHY1_DSP_TAP :: TAP8_C1 :: TX_HALFOUT_OV [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x4,2)
#define BRPHY1_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_MASK                  0x0004
#define BRPHY1_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_BITS                  1
#define BRPHY1_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_SHIFT                 2

/* BRPHY1_DSP_TAP :: TAP8_C1 :: TX_ADJ_EN [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x2,1)
#define BRPHY1_DSP_TAP_TAP8_C1_TX_ADJ_EN_MASK                      0x0002
#define BRPHY1_DSP_TAP_TAP8_C1_TX_ADJ_EN_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP8_C1_TX_ADJ_EN_BITS                      1
#define BRPHY1_DSP_TAP_TAP8_C1_TX_ADJ_EN_SHIFT                     1

/* BRPHY1_DSP_TAP :: TAP8_C1 :: FFE_BUMP_EN [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C1,0x1,0)
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_BUMP_EN_MASK                    0x0001
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_BUMP_EN_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_BUMP_EN_BITS                    1
#define BRPHY1_DSP_TAP_TAP8_C1_FFE_BUMP_EN_SHIFT                   0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP8_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP8_C2 :: LEVELSELECT [15:13] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_LEVELSELECT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0xe000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_LEVELSELECT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0xe000,13)
#define BRPHY1_DSP_TAP_TAP8_C2_LEVELSELECT_MASK                    0xe000
#define BRPHY1_DSP_TAP_TAP8_C2_LEVELSELECT_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP8_C2_LEVELSELECT_BITS                    3
#define BRPHY1_DSP_TAP_TAP8_C2_LEVELSELECT_SHIFT                   13

/* BRPHY1_DSP_TAP :: TAP8_C2 :: FAILING_CHANNEL [12:11] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x1800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x1800,11)
#define BRPHY1_DSP_TAP_TAP8_C2_FAILING_CHANNEL_MASK                0x1800
#define BRPHY1_DSP_TAP_TAP8_C2_FAILING_CHANNEL_ALIGN               0
#define BRPHY1_DSP_TAP_TAP8_C2_FAILING_CHANNEL_BITS                2
#define BRPHY1_DSP_TAP_TAP8_C2_FAILING_CHANNEL_SHIFT               11

/* BRPHY1_DSP_TAP :: TAP8_C2 :: CONV_FAIL_FLAG [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x400,10)
#define BRPHY1_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_MASK                 0x0400
#define BRPHY1_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_ALIGN                0
#define BRPHY1_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_BITS                 1
#define BRPHY1_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_SHIFT                10

/* BRPHY1_DSP_TAP :: TAP8_C2 :: SYM_ERR_FAIL_FLAG [09:09] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x200,9)
#define BRPHY1_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_MASK              0x0200
#define BRPHY1_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_ALIGN             0
#define BRPHY1_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_BITS              1
#define BRPHY1_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_SHIFT             9

/* BRPHY1_DSP_TAP :: TAP8_C2 :: MAX_OFFSET_FAIL_FLAG [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x100,8)
#define BRPHY1_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_MASK           0x0100
#define BRPHY1_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_ALIGN          0
#define BRPHY1_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_BITS           1
#define BRPHY1_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_SHIFT          8

/* BRPHY1_DSP_TAP :: TAP8_C2 :: PEAK_ERR_FAIL_FLAG [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x80,7)
#define BRPHY1_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_MASK             0x0080
#define BRPHY1_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_ALIGN            0
#define BRPHY1_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_BITS             1
#define BRPHY1_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_SHIFT            7

/* BRPHY1_DSP_TAP :: TAP8_C2 :: MSE_FAIL_FLAG [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x40,6)
#define BRPHY1_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_MASK                  0x0040
#define BRPHY1_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_BITS                  1
#define BRPHY1_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_SHIFT                 6

/* BRPHY1_DSP_TAP :: TAP8_C2 :: GAIN_AMP_FAIL_FLAG [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x20,5)
#define BRPHY1_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_MASK             0x0020
#define BRPHY1_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_ALIGN            0
#define BRPHY1_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_BITS             1
#define BRPHY1_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_SHIFT            5

/* BRPHY1_DSP_TAP :: TAP8_C2 :: ABIST_COMPLETE_FLAG [04:04] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0x10,4)
#define BRPHY1_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_MASK            0x0010
#define BRPHY1_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_ALIGN           0
#define BRPHY1_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_BITS            1
#define BRPHY1_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_SHIFT           4

/* BRPHY1_DSP_TAP :: TAP8_C2 :: ADC_OVERFLOW [03:00] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C2,0xf,0)
#define BRPHY1_DSP_TAP_TAP8_C2_ADC_OVERFLOW_MASK                   0x000f
#define BRPHY1_DSP_TAP_TAP8_C2_ADC_OVERFLOW_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP8_C2_ADC_OVERFLOW_BITS                   4
#define BRPHY1_DSP_TAP_TAP8_C2_ADC_OVERFLOW_SHIFT                  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP8_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP8_C3 :: SPARE [15:12] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C3_SPARE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C3,0xf000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C3_SPARE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C3,0xf000,12)
#define BRPHY1_DSP_TAP_TAP8_C3_SPARE_MASK                          0xf000
#define BRPHY1_DSP_TAP_TAP8_C3_SPARE_ALIGN                         0
#define BRPHY1_DSP_TAP_TAP8_C3_SPARE_BITS                          4
#define BRPHY1_DSP_TAP_TAP8_C3_SPARE_SHIFT                         12

/* BRPHY1_DSP_TAP :: TAP8_C3 :: BR_AGC_RST_VAL [11:10] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C3,0xc00,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C3,0xc00,10)
#define BRPHY1_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_MASK                 0x0c00
#define BRPHY1_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_ALIGN                0
#define BRPHY1_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_BITS                 2
#define BRPHY1_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_SHIFT                10

/* BRPHY1_DSP_TAP :: TAP8_C3 :: BR_HPF_CTL [09:00] */
#define Wr_BRPHY1_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP8_C3,0x3ff,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP8_C3,0x3ff,0)
#define BRPHY1_DSP_TAP_TAP8_C3_BR_HPF_CTL_MASK                     0x03ff
#define BRPHY1_DSP_TAP_TAP8_C3_BR_HPF_CTL_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP8_C3_BR_HPF_CTL_BITS                     10
#define BRPHY1_DSP_TAP_TAP8_C3_BR_HPF_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP9
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP9 :: FREQ_REG [15:04] */
#define Wr_BRPHY1_DSP_TAP_TAP9_FREQ_REG(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP9,0xfff0,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP9_FREQ_REG(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP9,0xfff0,4)
#define BRPHY1_DSP_TAP_TAP9_FREQ_REG_MASK                          0xfff0
#define BRPHY1_DSP_TAP_TAP9_FREQ_REG_ALIGN                         0
#define BRPHY1_DSP_TAP_TAP9_FREQ_REG_BITS                          12
#define BRPHY1_DSP_TAP_TAP9_FREQ_REG_SHIFT                         4

/* BRPHY1_DSP_TAP :: TAP9 :: FREQ_REG_OV_EN_ABCD [03:00] */
#define Wr_BRPHY1_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP9,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP9,0xf,0)
#define BRPHY1_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_MASK               0x000f
#define BRPHY1_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_ALIGN              0
#define BRPHY1_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_BITS               4
#define BRPHY1_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_SHIFT              0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP10
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP10 :: SLAVEENCCONVADJUST [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP10,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP10,0x8000,15)
#define BRPHY1_DSP_TAP_TAP10_SLAVEENCCONVADJUST_MASK               0x8000
#define BRPHY1_DSP_TAP_TAP10_SLAVEENCCONVADJUST_ALIGN              0
#define BRPHY1_DSP_TAP_TAP10_SLAVEENCCONVADJUST_BITS               1
#define BRPHY1_DSP_TAP_TAP10_SLAVEENCCONVADJUST_SHIFT              15

/* BRPHY1_DSP_TAP :: TAP10 :: TRIM_HYB [14:11] */
#define Wr_BRPHY1_DSP_TAP_TAP10_TRIM_HYB(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP10,0x7800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP10_TRIM_HYB(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP10,0x7800,11)
#define BRPHY1_DSP_TAP_TAP10_TRIM_HYB_MASK                         0x7800
#define BRPHY1_DSP_TAP_TAP10_TRIM_HYB_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP10_TRIM_HYB_BITS                         4
#define BRPHY1_DSP_TAP_TAP10_TRIM_HYB_SHIFT                        11

/* BRPHY1_DSP_TAP :: TAP10 :: FFE_GAMMA_OV [10:09] */
#define Wr_BRPHY1_DSP_TAP_TAP10_FFE_GAMMA_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP10,0x600,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP10_FFE_GAMMA_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP10,0x600,9)
#define BRPHY1_DSP_TAP_TAP10_FFE_GAMMA_OV_MASK                     0x0600
#define BRPHY1_DSP_TAP_TAP10_FFE_GAMMA_OV_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP10_FFE_GAMMA_OV_BITS                     2
#define BRPHY1_DSP_TAP_TAP10_FFE_GAMMA_OV_SHIFT                    9

/* BRPHY1_DSP_TAP :: TAP10 :: TX_PHASE_CTL_BW_SEL [08:07] */
#define Wr_BRPHY1_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP10,0x180,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP10,0x180,7)
#define BRPHY1_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_MASK              0x0180
#define BRPHY1_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_ALIGN             0
#define BRPHY1_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_BITS              2
#define BRPHY1_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_SHIFT             7

/* BRPHY1_DSP_TAP :: TAP10 :: RESET_PATH_METRICS [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP10_RESET_PATH_METRICS(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP10,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP10_RESET_PATH_METRICS(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP10,0x40,6)
#define BRPHY1_DSP_TAP_TAP10_RESET_PATH_METRICS_MASK               0x0040
#define BRPHY1_DSP_TAP_TAP10_RESET_PATH_METRICS_ALIGN              0
#define BRPHY1_DSP_TAP_TAP10_RESET_PATH_METRICS_BITS               1
#define BRPHY1_DSP_TAP_TAP10_RESET_PATH_METRICS_SHIFT              6

/* BRPHY1_DSP_TAP :: TAP10 :: GBT_PLL_BW_CTL_STARTUP [05:03] */
#define Wr_BRPHY1_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP10,0x38,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP10,0x38,3)
#define BRPHY1_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_MASK           0x0038
#define BRPHY1_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_ALIGN          0
#define BRPHY1_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_BITS           3
#define BRPHY1_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_SHIFT          3

/* BRPHY1_DSP_TAP :: TAP10 :: BGT_PLL_BW_CTL_NORMAL_OP [02:00] */
#define Wr_BRPHY1_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP10,0x7,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP10,0x7,0)
#define BRPHY1_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_MASK         0x0007
#define BRPHY1_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_ALIGN        0
#define BRPHY1_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_BITS         3
#define BRPHY1_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_SHIFT        0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP11
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP11 :: TCLK_OFFSET_STROBE [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP11,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP11,0x8000,15)
#define BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_MASK               0x8000
#define BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_BITS               1
#define BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_SHIFT              15

/* BRPHY1_DSP_TAP :: TAP11 :: RCLK_OFFSET_STROBE [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP11,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP11,0x4000,14)
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_MASK               0x4000
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_BITS               1
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_SHIFT              14

/* BRPHY1_DSP_TAP :: TAP11 :: reserved0 [13:13] */
#define BRPHY1_DSP_TAP_TAP11_RESERVED0_MASK                        0x2000
#define BRPHY1_DSP_TAP_TAP11_RESERVED0_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP11_RESERVED0_BITS                        1
#define BRPHY1_DSP_TAP_TAP11_RESERVED0_SHIFT                       13

/* BRPHY1_DSP_TAP :: TAP11 :: RCLK_OFFSET_FREEZE [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP11,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP11,0x1000,12)
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_MASK               0x1000
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_BITS               1
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_SHIFT              12

/* BRPHY1_DSP_TAP :: TAP11 :: TCLK_OFFSET [11:06] */
#define Wr_BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP11,0xfc0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP11,0xfc0,6)
#define BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_MASK                      0x0fc0
#define BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_BITS                      6
#define BRPHY1_DSP_TAP_TAP11_TCLK_OFFSET_SHIFT                     6

/* BRPHY1_DSP_TAP :: TAP11 :: RCLK_OFFSET [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP11,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP11,0x3f,0)
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_MASK                      0x003f
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_BITS                      6
#define BRPHY1_DSP_TAP_TAP11_RCLK_OFFSET_SHIFT                     0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP12_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP12_C0 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_TAP12_C0_RESERVED0_MASK                     0xff00
#define BRPHY1_DSP_TAP_TAP12_C0_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP12_C0_RESERVED0_BITS                     8
#define BRPHY1_DSP_TAP_TAP12_C0_RESERVED0_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C0,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C0,0x80,7)
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY1_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C0,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C0,0x40,6)
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY1_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C0,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C0,0x3f,0)
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_MASK                   0x003f
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_BITS                   6
#define BRPHY1_DSP_TAP_TAP12_C0_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP12_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP12_C1 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_TAP12_C1_RESERVED0_MASK                     0xff00
#define BRPHY1_DSP_TAP_TAP12_C1_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP12_C1_RESERVED0_BITS                     8
#define BRPHY1_DSP_TAP_TAP12_C1_RESERVED0_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C1,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C1,0x80,7)
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY1_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C1,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C1,0x40,6)
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY1_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C1,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C1,0x3f,0)
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_MASK                   0x003f
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_BITS                   6
#define BRPHY1_DSP_TAP_TAP12_C1_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP12_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP12_C2 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_TAP12_C2_RESERVED0_MASK                     0xff00
#define BRPHY1_DSP_TAP_TAP12_C2_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP12_C2_RESERVED0_BITS                     8
#define BRPHY1_DSP_TAP_TAP12_C2_RESERVED0_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C2,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C2,0x80,7)
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY1_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C2,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C2,0x40,6)
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY1_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C2,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C2,0x3f,0)
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_MASK                   0x003f
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_BITS                   6
#define BRPHY1_DSP_TAP_TAP12_C2_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP12_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP12_C3 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_TAP12_C3_RESERVED0_MASK                     0xff00
#define BRPHY1_DSP_TAP_TAP12_C3_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP12_C3_RESERVED0_BITS                     8
#define BRPHY1_DSP_TAP_TAP12_C3_RESERVED0_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C3,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C3,0x80,7)
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY1_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C3,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C3,0x40,6)
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY1_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP12_C3,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP12_C3,0x3f,0)
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_MASK                   0x003f
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_BITS                   6
#define BRPHY1_DSP_TAP_TAP12_C3_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP13
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP13 :: TMPLATE_EN [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP13_TMPLATE_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_TMPLATE_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0x8000,15)
#define BRPHY1_DSP_TAP_TAP13_TMPLATE_EN_MASK                       0x8000
#define BRPHY1_DSP_TAP_TAP13_TMPLATE_EN_ALIGN                      0
#define BRPHY1_DSP_TAP_TAP13_TMPLATE_EN_BITS                       1
#define BRPHY1_DSP_TAP_TAP13_TMPLATE_EN_SHIFT                      15

/* BRPHY1_DSP_TAP :: TAP13 :: PATTERN_DURATION [14:13] */
#define Wr_BRPHY1_DSP_TAP_TAP13_PATTERN_DURATION(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0x6000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_PATTERN_DURATION(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0x6000,13)
#define BRPHY1_DSP_TAP_TAP13_PATTERN_DURATION_MASK                 0x6000
#define BRPHY1_DSP_TAP_TAP13_PATTERN_DURATION_ALIGN                0
#define BRPHY1_DSP_TAP_TAP13_PATTERN_DURATION_BITS                 2
#define BRPHY1_DSP_TAP_TAP13_PATTERN_DURATION_SHIFT                13

/* BRPHY1_DSP_TAP :: TAP13 :: PATTERN_SEL [12:11] */
#define Wr_BRPHY1_DSP_TAP_TAP13_PATTERN_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0x1800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_PATTERN_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0x1800,11)
#define BRPHY1_DSP_TAP_TAP13_PATTERN_SEL_MASK                      0x1800
#define BRPHY1_DSP_TAP_TAP13_PATTERN_SEL_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP13_PATTERN_SEL_BITS                      2
#define BRPHY1_DSP_TAP_TAP13_PATTERN_SEL_SHIFT                     11

/* BRPHY1_DSP_TAP :: TAP13 :: PATTERN_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP13_PATTERN_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_PATTERN_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0x400,10)
#define BRPHY1_DSP_TAP_TAP13_PATTERN_EN_MASK                       0x0400
#define BRPHY1_DSP_TAP_TAP13_PATTERN_EN_ALIGN                      0
#define BRPHY1_DSP_TAP_TAP13_PATTERN_EN_BITS                       1
#define BRPHY1_DSP_TAP_TAP13_PATTERN_EN_SHIFT                      10

/* BRPHY1_DSP_TAP :: TAP13 :: DISABLETRRRGEN [09:09] */
#define Wr_BRPHY1_DSP_TAP_TAP13_DISABLETRRRGEN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_DISABLETRRRGEN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0x200,9)
#define BRPHY1_DSP_TAP_TAP13_DISABLETRRRGEN_MASK                   0x0200
#define BRPHY1_DSP_TAP_TAP13_DISABLETRRRGEN_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP13_DISABLETRRRGEN_BITS                   1
#define BRPHY1_DSP_TAP_TAP13_DISABLETRRRGEN_SHIFT                  9

/* BRPHY1_DSP_TAP :: TAP13 :: DISABLE10BEXTENSION [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0x100,8)
#define BRPHY1_DSP_TAP_TAP13_DISABLE10BEXTENSION_MASK              0x0100
#define BRPHY1_DSP_TAP_TAP13_DISABLE10BEXTENSION_ALIGN             0
#define BRPHY1_DSP_TAP_TAP13_DISABLE10BEXTENSION_BITS              1
#define BRPHY1_DSP_TAP_TAP13_DISABLE10BEXTENSION_SHIFT             8

/* BRPHY1_DSP_TAP :: TAP13 :: ALIGN_OK1_DISABLE [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0x80,7)
#define BRPHY1_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_MASK                0x0080
#define BRPHY1_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_ALIGN               0
#define BRPHY1_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_BITS                1
#define BRPHY1_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_SHIFT               7

/* BRPHY1_DSP_TAP :: TAP13 :: ALIGN_OK2_DISABLE [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0x40,6)
#define BRPHY1_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_MASK                0x0040
#define BRPHY1_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_ALIGN               0
#define BRPHY1_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_BITS                1
#define BRPHY1_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_SHIFT               6

/* BRPHY1_DSP_TAP :: TAP13 :: DISABLE_ADC_LSBS [05:04] */
#define Wr_BRPHY1_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0x30,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0x30,4)
#define BRPHY1_DSP_TAP_TAP13_DISABLE_ADC_LSBS_MASK                 0x0030
#define BRPHY1_DSP_TAP_TAP13_DISABLE_ADC_LSBS_ALIGN                0
#define BRPHY1_DSP_TAP_TAP13_DISABLE_ADC_LSBS_BITS                 2
#define BRPHY1_DSP_TAP_TAP13_DISABLE_ADC_LSBS_SHIFT                4

/* BRPHY1_DSP_TAP :: TAP13 :: IDLE_EXT_MASK [03:02] */
#define Wr_BRPHY1_DSP_TAP_TAP13_IDLE_EXT_MASK(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP13,0xc,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP13_IDLE_EXT_MASK(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP13,0xc,2)
#define BRPHY1_DSP_TAP_TAP13_IDLE_EXT_MASK_MASK                    0x000c
#define BRPHY1_DSP_TAP_TAP13_IDLE_EXT_MASK_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP13_IDLE_EXT_MASK_BITS                    2
#define BRPHY1_DSP_TAP_TAP13_IDLE_EXT_MASK_SHIFT                   2

/* BRPHY1_DSP_TAP :: TAP13 :: reserved0 [01:00] */
#define BRPHY1_DSP_TAP_TAP13_RESERVED0_MASK                        0x0003
#define BRPHY1_DSP_TAP_TAP13_RESERVED0_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP13_RESERVED0_BITS                        2
#define BRPHY1_DSP_TAP_TAP13_RESERVED0_SHIFT                       0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP14
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP14 :: MSE_THD_1_LSB [15:08] */
#define Wr_BRPHY1_DSP_TAP_TAP14_MSE_THD_1_LSB(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP14,0xff00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP14_MSE_THD_1_LSB(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP14,0xff00,8)
#define BRPHY1_DSP_TAP_TAP14_MSE_THD_1_LSB_MASK                    0xff00
#define BRPHY1_DSP_TAP_TAP14_MSE_THD_1_LSB_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP14_MSE_THD_1_LSB_BITS                    8
#define BRPHY1_DSP_TAP_TAP14_MSE_THD_1_LSB_SHIFT                   8

/* BRPHY1_DSP_TAP :: TAP14 :: ENERGY_DET_THD [07:00] */
#define Wr_BRPHY1_DSP_TAP_TAP14_ENERGY_DET_THD(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP14,0xff,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP14_ENERGY_DET_THD(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP14,0xff,0)
#define BRPHY1_DSP_TAP_TAP14_ENERGY_DET_THD_MASK                   0x00ff
#define BRPHY1_DSP_TAP_TAP14_ENERGY_DET_THD_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP14_ENERGY_DET_THD_BITS                   8
#define BRPHY1_DSP_TAP_TAP14_ENERGY_DET_THD_SHIFT                  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP15
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP15 :: MSE_THD_3_SEL [15:14] */
#define Wr_BRPHY1_DSP_TAP_TAP15_MSE_THD_3_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP15,0xc000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP15_MSE_THD_3_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP15,0xc000,14)
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_3_SEL_MASK                    0xc000
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_3_SEL_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_3_SEL_BITS                    2
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_3_SEL_SHIFT                   14

/* BRPHY1_DSP_TAP :: TAP15 :: MSE_THD_2 [13:02] */
#define Wr_BRPHY1_DSP_TAP_TAP15_MSE_THD_2(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP15,0x3ffc,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP15_MSE_THD_2(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP15,0x3ffc,2)
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_2_MASK                        0x3ffc
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_2_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_2_BITS                        12
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_2_SHIFT                       2

/* BRPHY1_DSP_TAP :: TAP15 :: MSE_THD_1_MSB [01:00] */
#define Wr_BRPHY1_DSP_TAP_TAP15_MSE_THD_1_MSB(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP15,0x3,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP15_MSE_THD_1_MSB(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP15,0x3,0)
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_1_MSB_MASK                    0x0003
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_1_MSB_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_1_MSB_BITS                    2
#define BRPHY1_DSP_TAP_TAP15_MSE_THD_1_MSB_SHIFT                   0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP16_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP16_C0 :: LA_TRIGGER_DELAY [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) WriteReg16(BRPHY1_DSP_TAP_TAP16_C0,x)
#define Rd_BRPHY1_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) ReadReg16(BRPHY1_DSP_TAP_TAP16_C0)
#define BRPHY1_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_MASK              0xffff
#define BRPHY1_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_ALIGN             0
#define BRPHY1_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_BITS              16
#define BRPHY1_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_SHIFT             0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP16_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP16_C1 :: BIST_CRC [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP16_C1_BIST_CRC(x) WriteReg16(BRPHY1_DSP_TAP_TAP16_C1,x)
#define Rd_BRPHY1_DSP_TAP_TAP16_C1_BIST_CRC(x) ReadReg16(BRPHY1_DSP_TAP_TAP16_C1)
#define BRPHY1_DSP_TAP_TAP16_C1_BIST_CRC_MASK                      0xffff
#define BRPHY1_DSP_TAP_TAP16_C1_BIST_CRC_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP16_C1_BIST_CRC_BITS                      16
#define BRPHY1_DSP_TAP_TAP16_C1_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP16_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP16_C2 :: BIST_CRC [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP16_C2_BIST_CRC(x) WriteReg16(BRPHY1_DSP_TAP_TAP16_C2,x)
#define Rd_BRPHY1_DSP_TAP_TAP16_C2_BIST_CRC(x) ReadReg16(BRPHY1_DSP_TAP_TAP16_C2)
#define BRPHY1_DSP_TAP_TAP16_C2_BIST_CRC_MASK                      0xffff
#define BRPHY1_DSP_TAP_TAP16_C2_BIST_CRC_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP16_C2_BIST_CRC_BITS                      16
#define BRPHY1_DSP_TAP_TAP16_C2_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP16_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP16_C3 :: BIST_CRC [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP16_C3_BIST_CRC(x) WriteReg16(BRPHY1_DSP_TAP_TAP16_C3,x)
#define Rd_BRPHY1_DSP_TAP_TAP16_C3_BIST_CRC(x) ReadReg16(BRPHY1_DSP_TAP_TAP16_C3)
#define BRPHY1_DSP_TAP_TAP16_C3_BIST_CRC_MASK                      0xffff
#define BRPHY1_DSP_TAP_TAP16_C3_BIST_CRC_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP16_C3_BIST_CRC_BITS                      16
#define BRPHY1_DSP_TAP_TAP16_C3_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP17_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP17_C0 :: TESTVALUE [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C0_TESTVALUE(x) WriteReg16(BRPHY1_DSP_TAP_TAP17_C0,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C0_TESTVALUE(x) ReadReg16(BRPHY1_DSP_TAP_TAP17_C0)
#define BRPHY1_DSP_TAP_TAP17_C0_TESTVALUE_MASK                     0xffff
#define BRPHY1_DSP_TAP_TAP17_C0_TESTVALUE_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP17_C0_TESTVALUE_BITS                     16
#define BRPHY1_DSP_TAP_TAP17_C0_TESTVALUE_SHIFT                    0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP17_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP17_C1 :: LA_ACQ_DONE [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x8000,15)
#define BRPHY1_DSP_TAP_TAP17_C1_LA_ACQ_DONE_MASK                   0x8000
#define BRPHY1_DSP_TAP_TAP17_C1_LA_ACQ_DONE_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP17_C1_LA_ACQ_DONE_BITS                   1
#define BRPHY1_DSP_TAP_TAP17_C1_LA_ACQ_DONE_SHIFT                  15

/* BRPHY1_DSP_TAP :: TAP17_C1 :: LA_TPOUT_SEL [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x4000,14)
#define BRPHY1_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_MASK                  0x4000
#define BRPHY1_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_BITS                  1
#define BRPHY1_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_SHIFT                 14

/* BRPHY1_DSP_TAP :: TAP17_C1 :: LA_CLK_DIVISOR [13:11] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x3800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x3800,11)
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_MASK                0x3800
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_ALIGN               0
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_BITS                3
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_SHIFT               11

/* BRPHY1_DSP_TAP :: TAP17_C1 :: LA_CLK_DELAY [10:09] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x600,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x600,9)
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DELAY_MASK                  0x0600
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DELAY_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DELAY_BITS                  2
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_DELAY_SHIFT                 9

/* BRPHY1_DSP_TAP :: TAP17_C1 :: LA_CLK_EDGE [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x100,8)
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_EDGE_MASK                   0x0100
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_EDGE_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_EDGE_BITS                   1
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_EDGE_SHIFT                  8

/* BRPHY1_DSP_TAP :: TAP17_C1 :: LA_CLK_SEL [07:03] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0xf8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0xf8,3)
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_SEL_MASK                    0x00f8
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_SEL_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_SEL_BITS                    5
#define BRPHY1_DSP_TAP_TAP17_C1_LA_CLK_SEL_SHIFT                   3

/* BRPHY1_DSP_TAP :: TAP17_C1 :: LA_ENABLE [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C1_LA_ENABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C1_LA_ENABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x4,2)
#define BRPHY1_DSP_TAP_TAP17_C1_LA_ENABLE_MASK                     0x0004
#define BRPHY1_DSP_TAP_TAP17_C1_LA_ENABLE_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP17_C1_LA_ENABLE_BITS                     1
#define BRPHY1_DSP_TAP_TAP17_C1_LA_ENABLE_SHIFT                    2

/* BRPHY1_DSP_TAP :: TAP17_C1 :: TESTMODE_STROBE [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x2,1)
#define BRPHY1_DSP_TAP_TAP17_C1_TESTMODE_STROBE_MASK               0x0002
#define BRPHY1_DSP_TAP_TAP17_C1_TESTMODE_STROBE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP17_C1_TESTMODE_STROBE_BITS               1
#define BRPHY1_DSP_TAP_TAP17_C1_TESTMODE_STROBE_SHIFT              1

/* BRPHY1_DSP_TAP :: TAP17_C1 :: LSITEST_SMDSP [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C1,0x1,0)
#define BRPHY1_DSP_TAP_TAP17_C1_LSITEST_SMDSP_MASK                 0x0001
#define BRPHY1_DSP_TAP_TAP17_C1_LSITEST_SMDSP_ALIGN                0
#define BRPHY1_DSP_TAP_TAP17_C1_LSITEST_SMDSP_BITS                 1
#define BRPHY1_DSP_TAP_TAP17_C1_LSITEST_SMDSP_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP17_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP17_C2 :: TRIGGER2_LAT [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x8000,15)
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_LAT_MASK                  0x8000
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_LAT_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_LAT_BITS                  1
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_LAT_SHIFT                 15

/* BRPHY1_DSP_TAP :: TAP17_C2 :: TRIGGER2_INV [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x4000,14)
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_INV_MASK                  0x4000
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_INV_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_INV_BITS                  1
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_INV_SHIFT                 14

/* BRPHY1_DSP_TAP :: TAP17_C2 :: TRIGGER2_SEL [13:08] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x3f00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x3f00,8)
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_SEL_MASK                  0x3f00
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_SEL_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_SEL_BITS                  6
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER2_SEL_SHIFT                 8

/* BRPHY1_DSP_TAP :: TAP17_C2 :: TRIGGER1_LAT [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x80,7)
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_LAT_MASK                  0x0080
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_LAT_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_LAT_BITS                  1
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_LAT_SHIFT                 7

/* BRPHY1_DSP_TAP :: TAP17_C2 :: TRIGGER1_INV [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x40,6)
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_INV_MASK                  0x0040
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_INV_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_INV_BITS                  1
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_INV_SHIFT                 6

/* BRPHY1_DSP_TAP :: TAP17_C2 :: TRIGGER1_SEL [05:00] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x3f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C2,0x3f,0)
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_SEL_MASK                  0x003f
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_SEL_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_SEL_BITS                  6
#define BRPHY1_DSP_TAP_TAP17_C2_TRIGGER1_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP17_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP17_C3 :: LA_REARM_ACQ [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x8000,15)
#define BRPHY1_DSP_TAP_TAP17_C3_LA_REARM_ACQ_MASK                  0x8000
#define BRPHY1_DSP_TAP_TAP17_C3_LA_REARM_ACQ_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C3_LA_REARM_ACQ_BITS                  1
#define BRPHY1_DSP_TAP_TAP17_C3_LA_REARM_ACQ_SHIFT                 15

/* BRPHY1_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_DELAY_EN [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x4000,14)
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_MASK           0x4000
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_ALIGN          0
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_BITS           1
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_SHIFT          14

/* BRPHY1_DSP_TAP :: TAP17_C3 :: LA_POSTSTORE [13:06] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x3fc0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x3fc0,6)
#define BRPHY1_DSP_TAP_TAP17_C3_LA_POSTSTORE_MASK                  0x3fc0
#define BRPHY1_DSP_TAP_TAP17_C3_LA_POSTSTORE_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C3_LA_POSTSTORE_BITS                  8
#define BRPHY1_DSP_TAP_TAP17_C3_LA_POSTSTORE_SHIFT                 6

/* BRPHY1_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_TYPE [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x20,5)
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_MASK               0x0020
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_BITS               1
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_SHIFT              5

/* BRPHY1_DSP_TAP :: TAP17_C3 :: SPARE [04:04] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C3_SPARE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C3_SPARE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x10,4)
#define BRPHY1_DSP_TAP_TAP17_C3_SPARE_MASK                         0x0010
#define BRPHY1_DSP_TAP_TAP17_C3_SPARE_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP17_C3_SPARE_BITS                         1
#define BRPHY1_DSP_TAP_TAP17_C3_SPARE_SHIFT                        4

/* BRPHY1_DSP_TAP :: TAP17_C3 :: LA_CLKENABLE [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x8,3)
#define BRPHY1_DSP_TAP_TAP17_C3_LA_CLKENABLE_MASK                  0x0008
#define BRPHY1_DSP_TAP_TAP17_C3_LA_CLKENABLE_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP17_C3_LA_CLKENABLE_BITS                  1
#define BRPHY1_DSP_TAP_TAP17_C3_LA_CLKENABLE_SHIFT                 3

/* BRPHY1_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_INV [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x4,2)
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_MASK                0x0004
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_ALIGN               0
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_BITS                1
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_SHIFT               2

/* BRPHY1_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_GATE [01:00] */
#define Wr_BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x3,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP17_C3,0x3,0)
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_MASK               0x0003
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_BITS               2
#define BRPHY1_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_SHIFT              0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP18_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP18_C0 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_TAP18_C0_RESERVED0_MASK                     0xff00
#define BRPHY1_DSP_TAP_TAP18_C0_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP18_C0_RESERVED0_BITS                     8
#define BRPHY1_DSP_TAP_TAP18_C0_RESERVED0_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP18_C0 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY1_DSP_TAP_TAP18_C0_PEAK_NOISE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP18_C0,0xff,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP18_C0_PEAK_NOISE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP18_C0,0xff,0)
#define BRPHY1_DSP_TAP_TAP18_C0_PEAK_NOISE_MASK                    0x00ff
#define BRPHY1_DSP_TAP_TAP18_C0_PEAK_NOISE_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP18_C0_PEAK_NOISE_BITS                    8
#define BRPHY1_DSP_TAP_TAP18_C0_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP18_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP18_C1 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_TAP18_C1_RESERVED0_MASK                     0xff00
#define BRPHY1_DSP_TAP_TAP18_C1_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP18_C1_RESERVED0_BITS                     8
#define BRPHY1_DSP_TAP_TAP18_C1_RESERVED0_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP18_C1 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY1_DSP_TAP_TAP18_C1_PEAK_NOISE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP18_C1,0xff,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP18_C1_PEAK_NOISE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP18_C1,0xff,0)
#define BRPHY1_DSP_TAP_TAP18_C1_PEAK_NOISE_MASK                    0x00ff
#define BRPHY1_DSP_TAP_TAP18_C1_PEAK_NOISE_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP18_C1_PEAK_NOISE_BITS                    8
#define BRPHY1_DSP_TAP_TAP18_C1_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP18_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP18_C2 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_TAP18_C2_RESERVED0_MASK                     0xff00
#define BRPHY1_DSP_TAP_TAP18_C2_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP18_C2_RESERVED0_BITS                     8
#define BRPHY1_DSP_TAP_TAP18_C2_RESERVED0_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP18_C2 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY1_DSP_TAP_TAP18_C2_PEAK_NOISE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP18_C2,0xff,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP18_C2_PEAK_NOISE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP18_C2,0xff,0)
#define BRPHY1_DSP_TAP_TAP18_C2_PEAK_NOISE_MASK                    0x00ff
#define BRPHY1_DSP_TAP_TAP18_C2_PEAK_NOISE_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP18_C2_PEAK_NOISE_BITS                    8
#define BRPHY1_DSP_TAP_TAP18_C2_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP18_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP18_C3 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_TAP18_C3_RESERVED0_MASK                     0xff00
#define BRPHY1_DSP_TAP_TAP18_C3_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP18_C3_RESERVED0_BITS                     8
#define BRPHY1_DSP_TAP_TAP18_C3_RESERVED0_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP18_C3 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY1_DSP_TAP_TAP18_C3_PEAK_NOISE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP18_C3,0xff,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP18_C3_PEAK_NOISE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP18_C3,0xff,0)
#define BRPHY1_DSP_TAP_TAP18_C3_PEAK_NOISE_MASK                    0x00ff
#define BRPHY1_DSP_TAP_TAP18_C3_PEAK_NOISE_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP18_C3_PEAK_NOISE_BITS                    8
#define BRPHY1_DSP_TAP_TAP18_C3_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP20
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP20 :: reserved0 [15:14] */
#define BRPHY1_DSP_TAP_TAP20_RESERVED0_MASK                        0xc000
#define BRPHY1_DSP_TAP_TAP20_RESERVED0_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP20_RESERVED0_BITS                        2
#define BRPHY1_DSP_TAP_TAP20_RESERVED0_SHIFT                       14

/* BRPHY1_DSP_TAP :: TAP20 :: ENC_FIR_PATH_DELAY_ADJ [13:11] */
#define Wr_BRPHY1_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP20,0x3800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP20,0x3800,11)
#define BRPHY1_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_MASK           0x3800
#define BRPHY1_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY1_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_BITS           3
#define BRPHY1_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_SHIFT          11

/* BRPHY1_DSP_TAP :: TAP20 :: ENC_LMS_PATH_DELAY_ADJ [10:08] */
#define Wr_BRPHY1_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP20,0x700,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP20,0x700,8)
#define BRPHY1_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_MASK           0x0700
#define BRPHY1_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY1_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_BITS           3
#define BRPHY1_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_SHIFT          8

/* BRPHY1_DSP_TAP :: TAP20 :: ECHO_LMS_GAIN [07:06] */
#define Wr_BRPHY1_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP20,0xc0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP20,0xc0,6)
#define BRPHY1_DSP_TAP_TAP20_ECHO_LMS_GAIN_MASK                    0x00c0
#define BRPHY1_DSP_TAP_TAP20_ECHO_LMS_GAIN_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP20_ECHO_LMS_GAIN_BITS                    2
#define BRPHY1_DSP_TAP_TAP20_ECHO_LMS_GAIN_SHIFT                   6

/* BRPHY1_DSP_TAP :: TAP20 :: reserved1 [05:04] */
#define BRPHY1_DSP_TAP_TAP20_RESERVED1_MASK                        0x0030
#define BRPHY1_DSP_TAP_TAP20_RESERVED1_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP20_RESERVED1_BITS                        2
#define BRPHY1_DSP_TAP_TAP20_RESERVED1_SHIFT                       4

/* BRPHY1_DSP_TAP :: TAP20 :: TXDIG_PATH_DELAY_CTL [03:00] */
#define Wr_BRPHY1_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP20,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP20,0xf,0)
#define BRPHY1_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_MASK             0x000f
#define BRPHY1_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_ALIGN            0
#define BRPHY1_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_BITS             4
#define BRPHY1_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_SHIFT            0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP21
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP21 :: reserved0 [15:13] */
#define BRPHY1_DSP_TAP_TAP21_RESERVED0_MASK                        0xe000
#define BRPHY1_DSP_TAP_TAP21_RESERVED0_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP21_RESERVED0_BITS                        3
#define BRPHY1_DSP_TAP_TAP21_RESERVED0_SHIFT                       13

/* BRPHY1_DSP_TAP :: TAP21 :: PAUSEPCTPM_ABCD [12:09] */
#define Wr_BRPHY1_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP21,0x1e00,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP21,0x1e00,9)
#define BRPHY1_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_MASK                  0x1e00
#define BRPHY1_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_BITS                  4
#define BRPHY1_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_SHIFT                 9

/* BRPHY1_DSP_TAP :: TAP21 :: TX_EN_MON [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP21_TX_EN_MON(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP21,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP21_TX_EN_MON(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP21,0x100,8)
#define BRPHY1_DSP_TAP_TAP21_TX_EN_MON_MASK                        0x0100
#define BRPHY1_DSP_TAP_TAP21_TX_EN_MON_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP21_TX_EN_MON_BITS                        1
#define BRPHY1_DSP_TAP_TAP21_TX_EN_MON_SHIFT                       8

/* BRPHY1_DSP_TAP :: TAP21 :: LINK_CTL_1000T_MON [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP21,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP21,0x80,7)
#define BRPHY1_DSP_TAP_TAP21_LINK_CTL_1000T_MON_MASK               0x0080
#define BRPHY1_DSP_TAP_TAP21_LINK_CTL_1000T_MON_ALIGN              0
#define BRPHY1_DSP_TAP_TAP21_LINK_CTL_1000T_MON_BITS               1
#define BRPHY1_DSP_TAP_TAP21_LINK_CTL_1000T_MON_SHIFT              7

/* BRPHY1_DSP_TAP :: TAP21 :: REM_RCVR_STATUS_MON [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP21,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP21,0x40,6)
#define BRPHY1_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_MASK              0x0040
#define BRPHY1_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_ALIGN             0
#define BRPHY1_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_BITS              1
#define BRPHY1_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_SHIFT             6

/* BRPHY1_DSP_TAP :: TAP21 :: ALIGN_OK_MON [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP21_ALIGN_OK_MON(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP21,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP21_ALIGN_OK_MON(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP21,0x20,5)
#define BRPHY1_DSP_TAP_TAP21_ALIGN_OK_MON_MASK                     0x0020
#define BRPHY1_DSP_TAP_TAP21_ALIGN_OK_MON_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP21_ALIGN_OK_MON_BITS                     1
#define BRPHY1_DSP_TAP_TAP21_ALIGN_OK_MON_SHIFT                    5

/* BRPHY1_DSP_TAP :: TAP21 :: MAIN_PHYC_STATE [04:00] */
#define Wr_BRPHY1_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP21,0x1f,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP21,0x1f,0)
#define BRPHY1_DSP_TAP_TAP21_MAIN_PHYC_STATE_MASK                  0x001f
#define BRPHY1_DSP_TAP_TAP21_MAIN_PHYC_STATE_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP21_MAIN_PHYC_STATE_BITS                  5
#define BRPHY1_DSP_TAP_TAP21_MAIN_PHYC_STATE_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP22
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP22 :: KRDONE [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP22_KRDONE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP22,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP22_KRDONE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP22,0x8000,15)
#define BRPHY1_DSP_TAP_TAP22_KRDONE_MASK                           0x8000
#define BRPHY1_DSP_TAP_TAP22_KRDONE_ALIGN                          0
#define BRPHY1_DSP_TAP_TAP22_KRDONE_BITS                           1
#define BRPHY1_DSP_TAP_TAP22_KRDONE_SHIFT                          15

/* BRPHY1_DSP_TAP :: TAP22 :: MAXWAIT_TIMER_DONE [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP22,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP22,0x4000,14)
#define BRPHY1_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_MASK               0x4000
#define BRPHY1_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_BITS               1
#define BRPHY1_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_SHIFT              14

/* BRPHY1_DSP_TAP :: TAP22 :: LINK_MONITOR_STATE_MON [13:12] */
#define Wr_BRPHY1_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP22,0x3000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP22,0x3000,12)
#define BRPHY1_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_MASK           0x3000
#define BRPHY1_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_ALIGN          0
#define BRPHY1_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_BITS           2
#define BRPHY1_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_SHIFT          12

/* BRPHY1_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_D [11:09] */
#define Wr_BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP22,0xe00,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP22,0xe00,9)
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_D_MASK                  0x0e00
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_D_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_D_BITS                  3
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_D_SHIFT                 9

/* BRPHY1_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_C [08:06] */
#define Wr_BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP22,0x1c0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP22,0x1c0,6)
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_C_MASK                  0x01c0
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_C_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_C_BITS                  3
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_C_SHIFT                 6

/* BRPHY1_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_B [05:03] */
#define Wr_BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP22,0x38,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP22,0x38,3)
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_B_MASK                  0x0038
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_B_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_B_BITS                  3
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_B_SHIFT                 3

/* BRPHY1_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_A [02:00] */
#define Wr_BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP22,0x7,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP22,0x7,0)
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_A_MASK                  0x0007
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_A_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_A_BITS                  3
#define BRPHY1_DSP_TAP_TAP22_PHYC_SUBSTATE_A_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP23
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP23 :: reserved0 [15:13] */
#define BRPHY1_DSP_TAP_TAP23_RESERVED0_MASK                        0xe000
#define BRPHY1_DSP_TAP_TAP23_RESERVED0_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP23_RESERVED0_BITS                        3
#define BRPHY1_DSP_TAP_TAP23_RESERVED0_SHIFT                       13

/* BRPHY1_DSP_TAP :: TAP23 :: ALIGN_REDO_MON [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP23_ALIGN_REDO_MON(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP23,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP23_ALIGN_REDO_MON(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP23,0x1000,12)
#define BRPHY1_DSP_TAP_TAP23_ALIGN_REDO_MON_MASK                   0x1000
#define BRPHY1_DSP_TAP_TAP23_ALIGN_REDO_MON_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP23_ALIGN_REDO_MON_BITS                   1
#define BRPHY1_DSP_TAP_TAP23_ALIGN_REDO_MON_SHIFT                  12

/* BRPHY1_DSP_TAP :: TAP23 :: MSEOK2_MON [11:08] */
#define Wr_BRPHY1_DSP_TAP_TAP23_MSEOK2_MON(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP23,0xf00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP23_MSEOK2_MON(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP23,0xf00,8)
#define BRPHY1_DSP_TAP_TAP23_MSEOK2_MON_MASK                       0x0f00
#define BRPHY1_DSP_TAP_TAP23_MSEOK2_MON_ALIGN                      0
#define BRPHY1_DSP_TAP_TAP23_MSEOK2_MON_BITS                       4
#define BRPHY1_DSP_TAP_TAP23_MSEOK2_MON_SHIFT                      8

/* BRPHY1_DSP_TAP :: TAP23 :: MSEOK1_MON [07:04] */
#define Wr_BRPHY1_DSP_TAP_TAP23_MSEOK1_MON(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP23,0xf0,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP23_MSEOK1_MON(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP23,0xf0,4)
#define BRPHY1_DSP_TAP_TAP23_MSEOK1_MON_MASK                       0x00f0
#define BRPHY1_DSP_TAP_TAP23_MSEOK1_MON_ALIGN                      0
#define BRPHY1_DSP_TAP_TAP23_MSEOK1_MON_BITS                       4
#define BRPHY1_DSP_TAP_TAP23_MSEOK1_MON_SHIFT                      4

/* BRPHY1_DSP_TAP :: TAP23 :: ENERGY_DETECT [03:00] */
#define Wr_BRPHY1_DSP_TAP_TAP23_ENERGY_DETECT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP23,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP23_ENERGY_DETECT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP23,0xf,0)
#define BRPHY1_DSP_TAP_TAP23_ENERGY_DETECT_MASK                    0x000f
#define BRPHY1_DSP_TAP_TAP23_ENERGY_DETECT_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP23_ENERGY_DETECT_BITS                    4
#define BRPHY1_DSP_TAP_TAP23_ENERGY_DETECT_SHIFT                   0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP24
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP24 :: PHYC_OUTPUT_OV [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x8000,15)
#define BRPHY1_DSP_TAP_TAP24_PHYC_OUTPUT_OV_MASK                   0x8000
#define BRPHY1_DSP_TAP_TAP24_PHYC_OUTPUT_OV_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP24_PHYC_OUTPUT_OV_BITS                   1
#define BRPHY1_DSP_TAP_TAP24_PHYC_OUTPUT_OV_SHIFT                  15

/* BRPHY1_DSP_TAP :: TAP24 :: STABLE_RECENTER_EN [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x4000,14)
#define BRPHY1_DSP_TAP_TAP24_STABLE_RECENTER_EN_MASK               0x4000
#define BRPHY1_DSP_TAP_TAP24_STABLE_RECENTER_EN_ALIGN              0
#define BRPHY1_DSP_TAP_TAP24_STABLE_RECENTER_EN_BITS               1
#define BRPHY1_DSP_TAP_TAP24_STABLE_RECENTER_EN_SHIFT              14

/* BRPHY1_DSP_TAP :: TAP24 :: PHYC_MSE_FIX [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP24_PHYC_MSE_FIX(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_PHYC_MSE_FIX(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x2000,13)
#define BRPHY1_DSP_TAP_TAP24_PHYC_MSE_FIX_MASK                     0x2000
#define BRPHY1_DSP_TAP_TAP24_PHYC_MSE_FIX_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP24_PHYC_MSE_FIX_BITS                     1
#define BRPHY1_DSP_TAP_TAP24_PHYC_MSE_FIX_SHIFT                    13

/* BRPHY1_DSP_TAP :: TAP24 :: DEGATEDFEPC_ABCD_OV [12:09] */
#define Wr_BRPHY1_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x1e00,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x1e00,9)
#define BRPHY1_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_MASK              0x1e00
#define BRPHY1_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_ALIGN             0
#define BRPHY1_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_BITS              4
#define BRPHY1_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_SHIFT             9

/* BRPHY1_DSP_TAP :: TAP24 :: NBRSTWTCH_OV [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP24_NBRSTWTCH_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_NBRSTWTCH_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x100,8)
#define BRPHY1_DSP_TAP_TAP24_NBRSTWTCH_OV_MASK                     0x0100
#define BRPHY1_DSP_TAP_TAP24_NBRSTWTCH_OV_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP24_NBRSTWTCH_OV_BITS                     1
#define BRPHY1_DSP_TAP_TAP24_NBRSTWTCH_OV_SHIFT                    8

/* BRPHY1_DSP_TAP :: TAP24 :: RC_LPBKFIFO_T_OV [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x80,7)
#define BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_MASK                 0x0080
#define BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_ALIGN                0
#define BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_BITS                 1
#define BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_SHIFT                7

/* BRPHY1_DSP_TAP :: TAP24 :: RC_LPBKFIFO_N_OV [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x40,6)
#define BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_MASK                 0x0040
#define BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_ALIGN                0
#define BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_BITS                 1
#define BRPHY1_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_SHIFT                6

/* BRPHY1_DSP_TAP :: TAP24 :: PCS_RESET_OV [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP24_PCS_RESET_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_PCS_RESET_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x20,5)
#define BRPHY1_DSP_TAP_TAP24_PCS_RESET_OV_MASK                     0x0020
#define BRPHY1_DSP_TAP_TAP24_PCS_RESET_OV_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP24_PCS_RESET_OV_BITS                     1
#define BRPHY1_DSP_TAP_TAP24_PCS_RESET_OV_SHIFT                    5

/* BRPHY1_DSP_TAP :: TAP24 :: PHYC_PCS_RSTATE_OV [04:03] */
#define Wr_BRPHY1_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x18,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x18,3)
#define BRPHY1_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_MASK               0x0018
#define BRPHY1_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_ALIGN              0
#define BRPHY1_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_BITS               2
#define BRPHY1_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_SHIFT              3

/* BRPHY1_DSP_TAP :: TAP24 :: LOC_RCVR_STATUS_OV [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x4,2)
#define BRPHY1_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_MASK               0x0004
#define BRPHY1_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_ALIGN              0
#define BRPHY1_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_BITS               1
#define BRPHY1_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_SHIFT              2

/* BRPHY1_DSP_TAP :: TAP24 :: PHYC_TXMODE_OV [01:00] */
#define Wr_BRPHY1_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP24,0x3,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP24,0x3,0)
#define BRPHY1_DSP_TAP_TAP24_PHYC_TXMODE_OV_MASK                   0x0003
#define BRPHY1_DSP_TAP_TAP24_PHYC_TXMODE_OV_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP24_PHYC_TXMODE_OV_BITS                   2
#define BRPHY1_DSP_TAP_TAP24_PHYC_TXMODE_OV_SHIFT                  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP25
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP25 :: reserved0 [15:15] */
#define BRPHY1_DSP_TAP_TAP25_RESERVED0_MASK                        0x8000
#define BRPHY1_DSP_TAP_TAP25_RESERVED0_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP25_RESERVED0_BITS                        1
#define BRPHY1_DSP_TAP_TAP25_RESERVED0_SHIFT                       15

/* BRPHY1_DSP_TAP :: TAP25 :: KRDONE_OV [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP25_KRDONE_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP25,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP25_KRDONE_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP25,0x4000,14)
#define BRPHY1_DSP_TAP_TAP25_KRDONE_OV_MASK                        0x4000
#define BRPHY1_DSP_TAP_TAP25_KRDONE_OV_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP25_KRDONE_OV_BITS                        1
#define BRPHY1_DSP_TAP_TAP25_KRDONE_OV_SHIFT                       14

/* BRPHY1_DSP_TAP :: TAP25 :: ALIGN_REDO_OV [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP25_ALIGN_REDO_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP25,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP25_ALIGN_REDO_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP25,0x2000,13)
#define BRPHY1_DSP_TAP_TAP25_ALIGN_REDO_OV_MASK                    0x2000
#define BRPHY1_DSP_TAP_TAP25_ALIGN_REDO_OV_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP25_ALIGN_REDO_OV_BITS                    1
#define BRPHY1_DSP_TAP_TAP25_ALIGN_REDO_OV_SHIFT                   13

/* BRPHY1_DSP_TAP :: TAP25 :: RC_ADCFIFO_N_OV [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP25,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP25,0x1000,12)
#define BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_MASK                  0x1000
#define BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_BITS                  1
#define BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_SHIFT                 12

/* BRPHY1_DSP_TAP :: TAP25 :: RC_ADCFIFO_T_OV [11:08] */
#define Wr_BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP25,0xf00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP25,0xf00,8)
#define BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_MASK                  0x0f00
#define BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_BITS                  4
#define BRPHY1_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_SHIFT                 8

/* BRPHY1_DSP_TAP :: TAP25 :: reserved1 [07:00] */
#define BRPHY1_DSP_TAP_TAP25_RESERVED1_MASK                        0x00ff
#define BRPHY1_DSP_TAP_TAP25_RESERVED1_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP25_RESERVED1_BITS                        8
#define BRPHY1_DSP_TAP_TAP25_RESERVED1_SHIFT                       0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP26
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP26 :: MSE_INPUT_OV [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP26_MSE_INPUT_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP26,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP26_MSE_INPUT_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP26,0x8000,15)
#define BRPHY1_DSP_TAP_TAP26_MSE_INPUT_OV_MASK                     0x8000
#define BRPHY1_DSP_TAP_TAP26_MSE_INPUT_OV_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP26_MSE_INPUT_OV_BITS                     1
#define BRPHY1_DSP_TAP_TAP26_MSE_INPUT_OV_SHIFT                    15

/* BRPHY1_DSP_TAP :: TAP26 :: MSEOK2_OV [14:11] */
#define Wr_BRPHY1_DSP_TAP_TAP26_MSEOK2_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP26,0x7800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP26_MSEOK2_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP26,0x7800,11)
#define BRPHY1_DSP_TAP_TAP26_MSEOK2_OV_MASK                        0x7800
#define BRPHY1_DSP_TAP_TAP26_MSEOK2_OV_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP26_MSEOK2_OV_BITS                        4
#define BRPHY1_DSP_TAP_TAP26_MSEOK2_OV_SHIFT                       11

/* BRPHY1_DSP_TAP :: TAP26 :: MSEOK1_OV [10:07] */
#define Wr_BRPHY1_DSP_TAP_TAP26_MSEOK1_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP26,0x780,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP26_MSEOK1_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP26,0x780,7)
#define BRPHY1_DSP_TAP_TAP26_MSEOK1_OV_MASK                        0x0780
#define BRPHY1_DSP_TAP_TAP26_MSEOK1_OV_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP26_MSEOK1_OV_BITS                        4
#define BRPHY1_DSP_TAP_TAP26_MSEOK1_OV_SHIFT                       7

/* BRPHY1_DSP_TAP :: TAP26 :: ENERGY_DETECT_OV [06:03] */
#define Wr_BRPHY1_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP26,0x78,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP26,0x78,3)
#define BRPHY1_DSP_TAP_TAP26_ENERGY_DETECT_OV_MASK                 0x0078
#define BRPHY1_DSP_TAP_TAP26_ENERGY_DETECT_OV_ALIGN                0
#define BRPHY1_DSP_TAP_TAP26_ENERGY_DETECT_OV_BITS                 4
#define BRPHY1_DSP_TAP_TAP26_ENERGY_DETECT_OV_SHIFT                3

/* BRPHY1_DSP_TAP :: TAP26 :: PCS_INPUT_OV [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP26_PCS_INPUT_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP26,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP26_PCS_INPUT_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP26,0x4,2)
#define BRPHY1_DSP_TAP_TAP26_PCS_INPUT_OV_MASK                     0x0004
#define BRPHY1_DSP_TAP_TAP26_PCS_INPUT_OV_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP26_PCS_INPUT_OV_BITS                     1
#define BRPHY1_DSP_TAP_TAP26_PCS_INPUT_OV_SHIFT                    2

/* BRPHY1_DSP_TAP :: TAP26 :: REM_RCVR_STATUS_OV [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP26,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP26,0x2,1)
#define BRPHY1_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_MASK               0x0002
#define BRPHY1_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_ALIGN              0
#define BRPHY1_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_BITS               1
#define BRPHY1_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_SHIFT              1

/* BRPHY1_DSP_TAP :: TAP26 :: ALIGN_OK_OV [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP26_ALIGN_OK_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP26,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP26_ALIGN_OK_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP26,0x1,0)
#define BRPHY1_DSP_TAP_TAP26_ALIGN_OK_OV_MASK                      0x0001
#define BRPHY1_DSP_TAP_TAP26_ALIGN_OK_OV_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP26_ALIGN_OK_OV_BITS                      1
#define BRPHY1_DSP_TAP_TAP26_ALIGN_OK_OV_SHIFT                     0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP27
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP27 :: reserved0 [15:09] */
#define BRPHY1_DSP_TAP_TAP27_RESERVED0_MASK                        0xfe00
#define BRPHY1_DSP_TAP_TAP27_RESERVED0_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP27_RESERVED0_BITS                        7
#define BRPHY1_DSP_TAP_TAP27_RESERVED0_SHIFT                       9

/* BRPHY1_DSP_TAP :: TAP27 :: FILTER_CTL_PAUSE_OV [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP27,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP27,0x100,8)
#define BRPHY1_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_MASK              0x0100
#define BRPHY1_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_ALIGN             0
#define BRPHY1_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_BITS              1
#define BRPHY1_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_SHIFT             8

/* BRPHY1_DSP_TAP :: TAP27 :: PAUSEPCTPM_ABCD_OV [07:04] */
#define Wr_BRPHY1_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP27,0xf0,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP27,0xf0,4)
#define BRPHY1_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_MASK               0x00f0
#define BRPHY1_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_ALIGN              0
#define BRPHY1_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_BITS               4
#define BRPHY1_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_SHIFT              4

/* BRPHY1_DSP_TAP :: TAP27 :: AUTONEG_INPUT_OV [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP27,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP27,0x8,3)
#define BRPHY1_DSP_TAP_TAP27_AUTONEG_INPUT_OV_MASK                 0x0008
#define BRPHY1_DSP_TAP_TAP27_AUTONEG_INPUT_OV_ALIGN                0
#define BRPHY1_DSP_TAP_TAP27_AUTONEG_INPUT_OV_BITS                 1
#define BRPHY1_DSP_TAP_TAP27_AUTONEG_INPUT_OV_SHIFT                3

/* BRPHY1_DSP_TAP :: TAP27 :: LINK_SCAN_100TX_OV [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP27,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP27,0x4,2)
#define BRPHY1_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_MASK               0x0004
#define BRPHY1_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_ALIGN              0
#define BRPHY1_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_BITS               1
#define BRPHY1_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_SHIFT              2

/* BRPHY1_DSP_TAP :: TAP27 :: LINK_ENAB_100TX_OV [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP27,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP27,0x2,1)
#define BRPHY1_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_MASK               0x0002
#define BRPHY1_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_ALIGN              0
#define BRPHY1_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_BITS               1
#define BRPHY1_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_SHIFT              1

/* BRPHY1_DSP_TAP :: TAP27 :: LINK_CTL_1000T_OV [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP27,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP27,0x1,0)
#define BRPHY1_DSP_TAP_TAP27_LINK_CTL_1000T_OV_MASK                0x0001
#define BRPHY1_DSP_TAP_TAP27_LINK_CTL_1000T_OV_ALIGN               0
#define BRPHY1_DSP_TAP_TAP27_LINK_CTL_1000T_OV_BITS                1
#define BRPHY1_DSP_TAP_TAP27_LINK_CTL_1000T_OV_SHIFT               0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP28
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP28 :: reserved0 [15:04] */
#define BRPHY1_DSP_TAP_TAP28_RESERVED0_MASK                        0xfff0
#define BRPHY1_DSP_TAP_TAP28_RESERVED0_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP28_RESERVED0_BITS                        12
#define BRPHY1_DSP_TAP_TAP28_RESERVED0_SHIFT                       4

/* BRPHY1_DSP_TAP :: TAP28 :: PLLPRAMP_ABCD_OV [03:00] */
#define Wr_BRPHY1_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP28,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP28,0xf,0)
#define BRPHY1_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_MASK                 0x000f
#define BRPHY1_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_ALIGN                0
#define BRPHY1_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_BITS                 4
#define BRPHY1_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP29
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP29 :: TIMER_MODE_D_FORCE [15:14] */
#define Wr_BRPHY1_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP29,0xc000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP29,0xc000,14)
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_MASK               0xc000
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_BITS               2
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_SHIFT              14

/* BRPHY1_DSP_TAP :: TAP29 :: TIMER_MODE_C_FORCE [13:12] */
#define Wr_BRPHY1_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP29,0x3000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP29,0x3000,12)
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_MASK               0x3000
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_BITS               2
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_SHIFT              12

/* BRPHY1_DSP_TAP :: TAP29 :: TIMER_MODE_B_FORCE [11:10] */
#define Wr_BRPHY1_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP29,0xc00,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP29,0xc00,10)
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_MASK               0x0c00
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_BITS               2
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_SHIFT              10

/* BRPHY1_DSP_TAP :: TAP29 :: TIMER_MODE_A_FORCE [09:08] */
#define Wr_BRPHY1_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP29,0x300,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP29,0x300,8)
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_MASK               0x0300
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_BITS               2
#define BRPHY1_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_SHIFT              8

/* BRPHY1_DSP_TAP :: TAP29 :: MAINSTATE_FORCE [07:04] */
#define Wr_BRPHY1_DSP_TAP_TAP29_MAINSTATE_FORCE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP29,0xf0,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP29_MAINSTATE_FORCE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP29,0xf0,4)
#define BRPHY1_DSP_TAP_TAP29_MAINSTATE_FORCE_MASK                  0x00f0
#define BRPHY1_DSP_TAP_TAP29_MAINSTATE_FORCE_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP29_MAINSTATE_FORCE_BITS                  4
#define BRPHY1_DSP_TAP_TAP29_MAINSTATE_FORCE_SHIFT                 4

/* BRPHY1_DSP_TAP :: TAP29 :: FORCE_PHYC_STATE [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP29,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP29,0x8,3)
#define BRPHY1_DSP_TAP_TAP29_FORCE_PHYC_STATE_MASK                 0x0008
#define BRPHY1_DSP_TAP_TAP29_FORCE_PHYC_STATE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP29_FORCE_PHYC_STATE_BITS                 1
#define BRPHY1_DSP_TAP_TAP29_FORCE_PHYC_STATE_SHIFT                3

/* BRPHY1_DSP_TAP :: TAP29 :: HOLD_IN_ALT [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP29_HOLD_IN_ALT(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP29,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP29_HOLD_IN_ALT(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP29,0x4,2)
#define BRPHY1_DSP_TAP_TAP29_HOLD_IN_ALT_MASK                      0x0004
#define BRPHY1_DSP_TAP_TAP29_HOLD_IN_ALT_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP29_HOLD_IN_ALT_BITS                      1
#define BRPHY1_DSP_TAP_TAP29_HOLD_IN_ALT_SHIFT                     2

/* BRPHY1_DSP_TAP :: TAP29 :: FORCE_ALT_STATE_PATH [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP29,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP29,0x2,1)
#define BRPHY1_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_MASK             0x0002
#define BRPHY1_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_ALIGN            0
#define BRPHY1_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_BITS             1
#define BRPHY1_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_SHIFT            1

/* BRPHY1_DSP_TAP :: TAP29 :: PHYC_FAST_STATE_MODE [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP29,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP29,0x1,0)
#define BRPHY1_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_MASK             0x0001
#define BRPHY1_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_ALIGN            0
#define BRPHY1_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_BITS             1
#define BRPHY1_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_SHIFT            0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP30
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP30 :: reserved0 [15:12] */
#define BRPHY1_DSP_TAP_TAP30_RESERVED0_MASK                        0xf000
#define BRPHY1_DSP_TAP_TAP30_RESERVED0_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP30_RESERVED0_BITS                        4
#define BRPHY1_DSP_TAP_TAP30_RESERVED0_SHIFT                       12

/* BRPHY1_DSP_TAP :: TAP30 :: SUBSTATE_D_FORCE [11:09] */
#define Wr_BRPHY1_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP30,0xe00,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP30,0xe00,9)
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_D_FORCE_MASK                 0x0e00
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_D_FORCE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_D_FORCE_BITS                 3
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_D_FORCE_SHIFT                9

/* BRPHY1_DSP_TAP :: TAP30 :: SUBSTATE_C_FORCE [08:06] */
#define Wr_BRPHY1_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP30,0x1c0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP30,0x1c0,6)
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_C_FORCE_MASK                 0x01c0
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_C_FORCE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_C_FORCE_BITS                 3
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_C_FORCE_SHIFT                6

/* BRPHY1_DSP_TAP :: TAP30 :: SUBSTATE_B_FORCE [05:03] */
#define Wr_BRPHY1_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP30,0x38,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP30,0x38,3)
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_B_FORCE_MASK                 0x0038
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_B_FORCE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_B_FORCE_BITS                 3
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_B_FORCE_SHIFT                3

/* BRPHY1_DSP_TAP :: TAP30 :: SUBSTATE_A_FORCE [02:00] */
#define Wr_BRPHY1_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP30,0x7,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP30,0x7,0)
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_A_FORCE_MASK                 0x0007
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_A_FORCE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_A_FORCE_BITS                 3
#define BRPHY1_DSP_TAP_TAP30_SUBSTATE_A_FORCE_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP31_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP31_C0 :: SDSEL_OV [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x8000,15)
#define BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_MASK                      0x8000
#define BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_ALIGN                     0
#define BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_BITS                      1
#define BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_SHIFT                     15

/* BRPHY1_DSP_TAP :: TAP31_C0 :: SDSEL_OV_EN [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x4000,14)
#define BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_EN_MASK                   0x4000
#define BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_EN_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_EN_BITS                   1
#define BRPHY1_DSP_TAP_TAP31_C0_SDSEL_OV_EN_SHIFT                  14

/* BRPHY1_DSP_TAP :: TAP31_C0 :: ADC_BER_TPOUT_EN [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x2000,13)
#define BRPHY1_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_MASK              0x2000
#define BRPHY1_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_ALIGN             0
#define BRPHY1_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_BITS              1
#define BRPHY1_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_SHIFT             13

/* BRPHY1_DSP_TAP :: TAP31_C0 :: SWAPCD_OV [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP31_C0_SWAPCD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP31_C0_SWAPCD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x1000,12)
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPCD_OV_MASK                     0x1000
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPCD_OV_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPCD_OV_BITS                     1
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPCD_OV_SHIFT                    12

/* BRPHY1_DSP_TAP :: TAP31_C0 :: SWAPAB_OV [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x800,11)
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_OV_MASK                     0x0800
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_OV_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_OV_BITS                     1
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_OV_SHIFT                    11

/* BRPHY1_DSP_TAP :: TAP31_C0 :: SWAPAB_CD_OV_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP31_C0,0x400,10)
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_MASK               0x0400
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_ALIGN              0
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_BITS               1
#define BRPHY1_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_SHIFT              10

/* BRPHY1_DSP_TAP :: TAP31_C0 :: reserved0 [09:00] */
#define BRPHY1_DSP_TAP_TAP31_C0_RESERVED0_MASK                     0x03ff
#define BRPHY1_DSP_TAP_TAP31_C0_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP31_C0_RESERVED0_BITS                     10
#define BRPHY1_DSP_TAP_TAP31_C0_RESERVED0_SHIFT                    0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP32_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP32_C0 :: reserved0 [15:09] */
#define BRPHY1_DSP_TAP_TAP32_C0_RESERVED0_MASK                     0xfe00
#define BRPHY1_DSP_TAP_TAP32_C0_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP32_C0_RESERVED0_BITS                     7
#define BRPHY1_DSP_TAP_TAP32_C0_RESERVED0_SHIFT                    9

/* BRPHY1_DSP_TAP :: TAP32_C0 :: COEFF_RAM_TM_CTRL [08:04] */
#define Wr_BRPHY1_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x1f0,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x1f0,4)
#define BRPHY1_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_MASK             0x01f0
#define BRPHY1_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_ALIGN            0
#define BRPHY1_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_BITS             5
#define BRPHY1_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_SHIFT            4

/* BRPHY1_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_D [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x8,3)
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_MASK         0x0008
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_ALIGN        0
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_BITS         1
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_SHIFT        3

/* BRPHY1_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_C [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x4,2)
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_MASK         0x0004
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_ALIGN        0
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_BITS         1
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_SHIFT        2

/* BRPHY1_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_AB [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x2,1)
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_MASK        0x0002
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_ALIGN       0
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_BITS        1
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_SHIFT       1

/* BRPHY1_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_A [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP32_C0,0x1,0)
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_MASK         0x0001
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_ALIGN        0
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_BITS         1
#define BRPHY1_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_SHIFT        0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FDFE_OV_RD
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_MSB [15:14] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0xc000,14,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0xc000,14)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_MASK             0xc000
#define BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_ALIGN            0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_BITS             2
#define BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_SHIFT            14

/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_LSB [13:13] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x2000,13)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_MASK             0x2000
#define BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_ALIGN            0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_BITS             1
#define BRPHY1_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_SHIFT            13

/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: BETA_OV [12:12] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x1000,12)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_MASK                     0x1000
#define BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_ALIGN                    0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_BITS                     1
#define BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_SHIFT                    12

/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: BETA_OV_VAL [11:09] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0xe00,9,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0xe00,9)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_MASK                 0x0e00
#define BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_ALIGN                0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_BITS                 3
#define BRPHY1_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_SHIFT                9

/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: FDFE_MSE_SEL_OV [08:08] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x100,8)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_MASK             0x0100
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_ALIGN            0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_BITS             1
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_SHIFT            8

/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: FDFE_CLEAR_OV [07:07] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x80,7)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_MASK               0x0080
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_ALIGN              0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_BITS               1
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_SHIFT              7

/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: FDFE_OUTEN_OV [06:06] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x40,6)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_MASK               0x0040
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_ALIGN              0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_BITS               1
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_SHIFT              6

/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: FDFE_UPEN_OV [05:05] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x20,5)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_MASK                0x0020
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_ALIGN               0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_BITS                1
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_SHIFT               5

/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: FDFE_OV_EN [04:04] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0x10,4)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_MASK                  0x0010
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_ALIGN                 0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_BITS                  1
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_SHIFT                 4

/* BRPHY1_DSP_TAP :: FDFE_OV_RD :: FDFE_RD_SEL [03:00] */
#define Wr_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_OV_RD,0xf,0)
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_MASK                 0x000f
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_ALIGN                0
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_BITS                 4
#define BRPHY1_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FDFE_COEFF
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FDFE_COEFF :: FDFE_COEFF [15:00] */
#define Wr_BRPHY1_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) WriteReg16(BRPHY1_DSP_TAP_FDFE_COEFF,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) ReadReg16(BRPHY1_DSP_TAP_FDFE_COEFF)
#define BRPHY1_DSP_TAP_FDFE_COEFF_FDFE_COEFF_MASK                  0xffff
#define BRPHY1_DSP_TAP_FDFE_COEFF_FDFE_COEFF_ALIGN                 0
#define BRPHY1_DSP_TAP_FDFE_COEFF_FDFE_COEFF_BITS                  16
#define BRPHY1_DSP_TAP_FDFE_COEFF_FDFE_COEFF_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FDFE_BETA_THRESHOLD
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_3 [15:12] */
#define Wr_BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12)
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_MASK   0xf000
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_ALIGN  0
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_BITS   4
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_SHIFT  12

/* BRPHY1_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_2 [11:08] */
#define Wr_BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8)
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_MASK   0x0f00
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_ALIGN  0
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_BITS   4
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_SHIFT  8

/* BRPHY1_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_1 [07:04] */
#define Wr_BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4)
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_MASK   0x00f0
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_ALIGN  0
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_BITS   4
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_SHIFT  4

/* BRPHY1_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_0 [03:00] */
#define Wr_BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) WriteRegBits16(BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) ReadRegBits16(BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0)
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_MASK   0x000f
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_ALIGN  0
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_BITS   4
#define BRPHY1_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_SHIFT  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP33_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SD_EN [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x8000,15)
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_MASK               0x8000
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_ALIGN              0
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_BITS               1
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_SHIFT              15

/* BRPHY1_DSP_TAP :: TAP33_C0 :: EEE_MASK_MSE_EN [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x4000,14)
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_MASK               0x4000
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_ALIGN              0
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_BITS               1
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_SHIFT              14

/* BRPHY1_DSP_TAP :: TAP33_C0 :: EEE_PHYC_STATUS_TO_LED [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x2000,13)
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_MASK        0x2000
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_ALIGN       0
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_BITS        1
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_SHIFT       13

/* BRPHY1_DSP_TAP :: TAP33_C0 :: EEE_PLL_TEST_MODE [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x1000,12)
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_MASK             0x1000
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_ALIGN            0
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_BITS             1
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_SHIFT            12

/* BRPHY1_DSP_TAP :: TAP33_C0 :: SPARE11 [11:11] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_SPARE11(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_SPARE11(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x800,11)
#define BRPHY1_DSP_TAP_TAP33_C0_SPARE11_MASK                       0x0800
#define BRPHY1_DSP_TAP_TAP33_C0_SPARE11_ALIGN                      0
#define BRPHY1_DSP_TAP_TAP33_C0_SPARE11_BITS                       1
#define BRPHY1_DSP_TAP_TAP33_C0_SPARE11_SHIFT                      11

/* BRPHY1_DSP_TAP :: TAP33_C0 :: EEE_AFE_STOPPABLE [10:10] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x400,10)
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_MASK             0x0400
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_ALIGN            0
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_BITS             1
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_SHIFT            10

/* BRPHY1_DSP_TAP :: TAP33_C0 :: EEE_CLOCK_STOPPABLE [09:09] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x200,9)
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_MASK           0x0200
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_ALIGN          0
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_BITS           1
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_SHIFT          9

/* BRPHY1_DSP_TAP :: TAP33_C0 :: EEE_SD_SEL [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x100,8)
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_SD_SEL_MASK                    0x0100
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_SD_SEL_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_SD_SEL_BITS                    1
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_SD_SEL_SHIFT                   8

/* BRPHY1_DSP_TAP :: TAP33_C0 :: MAXMSEOK1_CHG_EN [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x80,7)
#define BRPHY1_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_MASK              0x0080
#define BRPHY1_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_ALIGN             0
#define BRPHY1_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_BITS              1
#define BRPHY1_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_SHIFT             7

/* BRPHY1_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SCALE [06:05] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x60,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x60,5)
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_MASK               0x0060
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_BITS               2
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_SHIFT              5

/* BRPHY1_DSP_TAP :: TAP33_C0 :: LPI_TRACK_MODE [04:03] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x18,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x18,3)
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_MASK                0x0018
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_ALIGN               0
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_BITS                2
#define BRPHY1_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_SHIFT               3

/* BRPHY1_DSP_TAP :: TAP33_C0 :: EEE_FREQ_UNLOCK [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x4,2)
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_MASK               0x0004
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_ALIGN              0
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_BITS               1
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_SHIFT              2

/* BRPHY1_DSP_TAP :: TAP33_C0 :: EEE_QUICK_ALIGN [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x2,1)
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_MASK               0x0002
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_ALIGN              0
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_BITS               1
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_SHIFT              1

/* BRPHY1_DSP_TAP :: TAP33_C0 :: EEE_SD300 [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C0_EEE_SD300(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C0_EEE_SD300(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C0,0x1,0)
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_SD300_MASK                     0x0001
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_SD300_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_SD300_BITS                     1
#define BRPHY1_DSP_TAP_TAP33_C0_EEE_SD300_SHIFT                    0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP33_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP33_C1 :: SD_ASSERT_THD [15:08] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C1,0xff00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C1,0xff00,8)
#define BRPHY1_DSP_TAP_TAP33_C1_SD_ASSERT_THD_MASK                 0xff00
#define BRPHY1_DSP_TAP_TAP33_C1_SD_ASSERT_THD_ALIGN                0
#define BRPHY1_DSP_TAP_TAP33_C1_SD_ASSERT_THD_BITS                 8
#define BRPHY1_DSP_TAP_TAP33_C1_SD_ASSERT_THD_SHIFT                8

/* BRPHY1_DSP_TAP :: TAP33_C1 :: SD_DEASSERT_THD [07:00] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C1,0xff,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C1,0xff,0)
#define BRPHY1_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_MASK               0x00ff
#define BRPHY1_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_ALIGN              0
#define BRPHY1_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_BITS               8
#define BRPHY1_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_SHIFT              0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP33_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP33_C2 :: EEE_PHASE_REACQ_TUNE [15:14] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0xc000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0xc000,14)
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_MASK          0xc000
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_ALIGN         0
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_BITS          2
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_SHIFT         14

/* BRPHY1_DSP_TAP :: TAP33_C2 :: EEE_WAIT_SCR_LOCK_N [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0x2000,13)
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_MASK           0x2000
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_ALIGN          0
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_BITS           1
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_SHIFT          13

/* BRPHY1_DSP_TAP :: TAP33_C2 :: LOC_RCVR_WAIT_ALIGNC_N [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0x1000,12)
#define BRPHY1_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_MASK        0x1000
#define BRPHY1_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_ALIGN       0
#define BRPHY1_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_BITS        1
#define BRPHY1_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_SHIFT       12

/* BRPHY1_DSP_TAP :: TAP33_C2 :: EEE_WAKEMZ_TUNE [11:08] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0xf00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0xf00,8)
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_MASK               0x0f00
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_BITS               4
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_SHIFT              8

/* BRPHY1_DSP_TAP :: TAP33_C2 :: EEE_RX_ON_TUNE [07:04] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0xf0,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0xf0,4)
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_MASK                0x00f0
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_ALIGN               0
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_BITS                4
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_SHIFT               4

/* BRPHY1_DSP_TAP :: TAP33_C2 :: EEE_SLAVE_WAIT_TUNE [03:00] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C2,0xf,0)
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_MASK           0x000f
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_ALIGN          0
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_BITS           4
#define BRPHY1_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_SHIFT          0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP33_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP33_C3 :: spare_reg [15:02] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C3_spare_reg(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C3,0xfffc,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C3_spare_reg(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C3,0xfffc,2)
#define BRPHY1_DSP_TAP_TAP33_C3_SPARE_REG_MASK                     0xfffc
#define BRPHY1_DSP_TAP_TAP33_C3_SPARE_REG_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP33_C3_SPARE_REG_BITS                     14
#define BRPHY1_DSP_TAP_TAP33_C3_SPARE_REG_SHIFT                    2

/* BRPHY1_DSP_TAP :: TAP33_C3 :: PWRDNTX_STAGGER_EN [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C3,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C3,0x2,1)
#define BRPHY1_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_MASK            0x0002
#define BRPHY1_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_ALIGN           0
#define BRPHY1_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_BITS            1
#define BRPHY1_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_SHIFT           1

/* BRPHY1_DSP_TAP :: TAP33_C3 :: PWRDNRX_STAGGER_EN [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP33_C3,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP33_C3,0x1,0)
#define BRPHY1_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_MASK            0x0001
#define BRPHY1_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_ALIGN           0
#define BRPHY1_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_BITS            1
#define BRPHY1_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_SHIFT           0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP34_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP34_C0 :: EEE_PLLILPFRZ [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x8000,15)
#define BRPHY1_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_MASK                 0x8000
#define BRPHY1_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_ALIGN                0
#define BRPHY1_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_BITS                 1
#define BRPHY1_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_SHIFT                15

/* BRPHY1_DSP_TAP :: TAP34_C0 :: PLLILPFRZ_OV [14:14] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x4000,14)
#define BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_MASK                  0x4000
#define BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_BITS                  1
#define BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_SHIFT                 14

/* BRPHY1_DSP_TAP :: TAP34_C0 :: PLLILPFRZ [13:13] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x2000,13)
#define BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_MASK                     0x2000
#define BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_BITS                     1
#define BRPHY1_DSP_TAP_TAP34_C0_PLLILPFRZ_SHIFT                    13

/* BRPHY1_DSP_TAP :: TAP34_C0 :: EEE_100TX_UP16_SEL [12:12] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x1000,12)
#define BRPHY1_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_MASK            0x1000
#define BRPHY1_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_ALIGN           0
#define BRPHY1_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_BITS            1
#define BRPHY1_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_SHIFT           12

/* BRPHY1_DSP_TAP :: TAP34_C0 :: PLLFRST_SCALE [11:10] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0xc00,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0xc00,10)
#define BRPHY1_DSP_TAP_TAP34_C0_PLLFRST_SCALE_MASK                 0x0c00
#define BRPHY1_DSP_TAP_TAP34_C0_PLLFRST_SCALE_ALIGN                0
#define BRPHY1_DSP_TAP_TAP34_C0_PLLFRST_SCALE_BITS                 2
#define BRPHY1_DSP_TAP_TAP34_C0_PLLFRST_SCALE_SHIFT                10

/* BRPHY1_DSP_TAP :: TAP34_C0 :: INT_LP_GAIN [09:08] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x300,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x300,8)
#define BRPHY1_DSP_TAP_TAP34_C0_INT_LP_GAIN_MASK                   0x0300
#define BRPHY1_DSP_TAP_TAP34_C0_INT_LP_GAIN_ALIGN                  0
#define BRPHY1_DSP_TAP_TAP34_C0_INT_LP_GAIN_BITS                   2
#define BRPHY1_DSP_TAP_TAP34_C0_INT_LP_GAIN_SHIFT                  8

/* BRPHY1_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_EST_AVERAGE_SEL [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x80,7)
#define BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_MASK    0x0080
#define BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_ALIGN   0
#define BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_BITS    1
#define BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_SHIFT   7

/* BRPHY1_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_SCALE [06:04] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x70,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x70,4)
#define BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_MASK              0x0070
#define BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_ALIGN             0
#define BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_BITS              3
#define BRPHY1_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_SHIFT             4

/* BRPHY1_DSP_TAP :: TAP34_C0 :: KI [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_KI(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_KI(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x8,3)
#define BRPHY1_DSP_TAP_TAP34_C0_KI_MASK                            0x0008
#define BRPHY1_DSP_TAP_TAP34_C0_KI_ALIGN                           0
#define BRPHY1_DSP_TAP_TAP34_C0_KI_BITS                            1
#define BRPHY1_DSP_TAP_TAP34_C0_KI_SHIFT                           3

/* BRPHY1_DSP_TAP :: TAP34_C0 :: KP [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_KP(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_KP(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x4,2)
#define BRPHY1_DSP_TAP_TAP34_C0_KP_MASK                            0x0004
#define BRPHY1_DSP_TAP_TAP34_C0_KP_ALIGN                           0
#define BRPHY1_DSP_TAP_TAP34_C0_KP_BITS                            1
#define BRPHY1_DSP_TAP_TAP34_C0_KP_SHIFT                           2

/* BRPHY1_DSP_TAP :: TAP34_C0 :: KV [01:00] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C0_KV(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x3,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C0_KV(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C0,0x3,0)
#define BRPHY1_DSP_TAP_TAP34_C0_KV_MASK                            0x0003
#define BRPHY1_DSP_TAP_TAP34_C0_KV_ALIGN                           0
#define BRPHY1_DSP_TAP_TAP34_C0_KV_BITS                            2
#define BRPHY1_DSP_TAP_TAP34_C0_KV_SHIFT                           0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP34_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP34_C1 :: SPARE [15:12] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C1_SPARE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C1,0xf000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C1_SPARE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C1,0xf000,12)
#define BRPHY1_DSP_TAP_TAP34_C1_SPARE_MASK                         0xf000
#define BRPHY1_DSP_TAP_TAP34_C1_SPARE_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP34_C1_SPARE_BITS                         4
#define BRPHY1_DSP_TAP_TAP34_C1_SPARE_SHIFT                        12

/* BRPHY1_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_10 [11:08] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C1,0xf00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C1,0xf00,8)
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_MASK             0x0f00
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_ALIGN            0
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_BITS             4
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_SHIFT            8

/* BRPHY1_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_01 [07:04] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C1,0xf0,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C1,0xf0,4)
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_MASK             0x00f0
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_ALIGN            0
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_BITS             4
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_SHIFT            4

/* BRPHY1_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_00 [03:00] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C1,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C1,0xf,0)
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_MASK             0x000f
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_ALIGN            0
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_BITS             4
#define BRPHY1_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_SHIFT            0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP34_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_CH_SEL [15:14] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0xc000,14,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0xc000,14)
#define BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_MASK           0xc000
#define BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_ALIGN          0
#define BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_BITS           2
#define BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_SHIFT          14

/* BRPHY1_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_BUS_SEL [13:11] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0x3800,11,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0x3800,11)
#define BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_MASK          0x3800
#define BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_ALIGN         0
#define BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_BITS          3
#define BRPHY1_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_SHIFT         11

/* BRPHY1_DSP_TAP :: TAP34_C2 :: reserved0 [10:09] */
#define BRPHY1_DSP_TAP_TAP34_C2_RESERVED0_MASK                     0x0600
#define BRPHY1_DSP_TAP_TAP34_C2_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP34_C2_RESERVED0_BITS                     2
#define BRPHY1_DSP_TAP_TAP34_C2_RESERVED0_SHIFT                    9

/* BRPHY1_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_10 [08:06] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0x1c0,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0x1c0,6)
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_MASK               0x01c0
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_ALIGN              0
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_BITS               3
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_SHIFT              6

/* BRPHY1_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_01 [05:03] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0x38,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0x38,3)
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_MASK               0x0038
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_ALIGN              0
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_BITS               3
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_SHIFT              3

/* BRPHY1_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_00 [02:00] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0x7,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP34_C2,0x7,0)
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_MASK               0x0007
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_ALIGN              0
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_BITS               3
#define BRPHY1_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_SHIFT              0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP34_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP34_C3 :: PHASECTL_TPO [15:00] */
#define Wr_BRPHY1_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) WriteReg16(BRPHY1_DSP_TAP_TAP34_C3,x)
#define Rd_BRPHY1_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) ReadReg16(BRPHY1_DSP_TAP_TAP34_C3)
#define BRPHY1_DSP_TAP_TAP34_C3_PHASECTL_TPO_MASK                  0xffff
#define BRPHY1_DSP_TAP_TAP34_C3_PHASECTL_TPO_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP34_C3_PHASECTL_TPO_BITS                  16
#define BRPHY1_DSP_TAP_TAP34_C3_PHASECTL_TPO_SHIFT                 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP35_C0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP35_C0 :: LPI_RX_TW3_TIMER [15:13] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0xe000,13,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0xe000,13)
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_MASK              0xe000
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_ALIGN             0
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_BITS              3
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_SHIFT             13

/* BRPHY1_DSP_TAP :: TAP35_C0 :: LPI_RX_TW2_TIMER [12:10] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0x1c00,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0x1c00,10)
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_MASK              0x1c00
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_ALIGN             0
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_BITS              3
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_SHIFT             10

/* BRPHY1_DSP_TAP :: TAP35_C0 :: LPI_RX_TW1_TIMER [09:07] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0x380,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0x380,7)
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_MASK              0x0380
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_ALIGN             0
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_BITS              3
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_SHIFT             7

/* BRPHY1_DSP_TAP :: TAP35_C0 :: LPI_TX_TQ_TIMER [06:04] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0x70,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0x70,4)
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_MASK               0x0070
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_ALIGN              0
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_BITS               3
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_SHIFT              4

/* BRPHY1_DSP_TAP :: TAP35_C0 :: LPI_TX_TS_TIMER [03:02] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0xc,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0xc,2)
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_MASK               0x000c
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_ALIGN              0
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_BITS               2
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_SHIFT              2

/* BRPHY1_DSP_TAP :: TAP35_C0 :: LPI_TX_TR_TIMER [01:00] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0x3,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C0,0x3,0)
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_MASK               0x0003
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_ALIGN              0
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_BITS               2
#define BRPHY1_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_SHIFT              0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP35_C1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP35_C1 :: LPI_RX_TS3_TIMER [15:10] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C1,0xfc00,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C1,0xfc00,10)
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_MASK              0xfc00
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_ALIGN             0
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_BITS              6
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_SHIFT             10

/* BRPHY1_DSP_TAP :: TAP35_C1 :: LPI_RX_TS2_TIMER [09:04] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C1,0x3f0,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C1,0x3f0,4)
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_MASK              0x03f0
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_ALIGN             0
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_BITS              6
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_SHIFT             4

/* BRPHY1_DSP_TAP :: TAP35_C1 :: LPI_RX_TS1_TIMER [03:00] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C1,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C1,0xf,0)
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_MASK              0x000f
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_ALIGN             0
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_BITS              4
#define BRPHY1_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_SHIFT             0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP35_C2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP35_C2 :: reserved0 [15:14] */
#define BRPHY1_DSP_TAP_TAP35_C2_RESERVED0_MASK                     0xc000
#define BRPHY1_DSP_TAP_TAP35_C2_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP35_C2_RESERVED0_BITS                     2
#define BRPHY1_DSP_TAP_TAP35_C2_RESERVED0_SHIFT                    14

/* BRPHY1_DSP_TAP :: TAP35_C2 :: SPARE [13:10] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C2_SPARE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x3c00,10,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C2_SPARE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x3c00,10)
#define BRPHY1_DSP_TAP_TAP35_C2_SPARE_MASK                         0x3c00
#define BRPHY1_DSP_TAP_TAP35_C2_SPARE_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP35_C2_SPARE_BITS                         4
#define BRPHY1_DSP_TAP_TAP35_C2_SPARE_SHIFT                        10

/* BRPHY1_DSP_TAP :: TAP35_C2 :: LPI_TX_BRCM_MODE [09:09] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x200,9)
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_MASK              0x0200
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_ALIGN             0
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_BITS              1
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_SHIFT             9

/* BRPHY1_DSP_TAP :: TAP35_C2 :: LPI_RX_TI_TIMER [08:08] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x100,8)
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_MASK               0x0100
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_ALIGN              0
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_BITS               1
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_SHIFT              8

/* BRPHY1_DSP_TAP :: TAP35_C2 :: GPCS_ERRTH_SEL [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x80,7)
#define BRPHY1_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_MASK                0x0080
#define BRPHY1_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_ALIGN               0
#define BRPHY1_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_BITS                1
#define BRPHY1_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_SHIFT               7

/* BRPHY1_DSP_TAP :: TAP35_C2 :: PCS_LPI_TEST_CTL [06:04] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x70,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x70,4)
#define BRPHY1_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_MASK              0x0070
#define BRPHY1_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_ALIGN             0
#define BRPHY1_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_BITS              3
#define BRPHY1_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_SHIFT             4

/* BRPHY1_DSP_TAP :: TAP35_C2 :: reserved1 [03:03] */
#define BRPHY1_DSP_TAP_TAP35_C2_RESERVED1_MASK                     0x0008
#define BRPHY1_DSP_TAP_TAP35_C2_RESERVED1_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP35_C2_RESERVED1_BITS                     1
#define BRPHY1_DSP_TAP_TAP35_C2_RESERVED1_SHIFT                    3

/* BRPHY1_DSP_TAP :: TAP35_C2 :: LPI_RX_SQCNTR [02:00] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x7,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C2,0x7,0)
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_MASK                 0x0007
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_ALIGN                0
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_BITS                 3
#define BRPHY1_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: TAP35_C3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: TAP35_C3 :: UNASSIGNED [15:15] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_UNASSIGNED(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_UNASSIGNED(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x8000,15)
#define BRPHY1_DSP_TAP_TAP35_C3_UNASSIGNED_MASK                    0x8000
#define BRPHY1_DSP_TAP_TAP35_C3_UNASSIGNED_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP35_C3_UNASSIGNED_BITS                    1
#define BRPHY1_DSP_TAP_TAP35_C3_UNASSIGNED_SHIFT                   15

/* BRPHY1_DSP_TAP :: TAP35_C3 :: LPI_100TX_STATE [14:12] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x7000,12,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x7000,12)
#define BRPHY1_DSP_TAP_TAP35_C3_LPI_100TX_STATE_MASK               0x7000
#define BRPHY1_DSP_TAP_TAP35_C3_LPI_100TX_STATE_ALIGN              0
#define BRPHY1_DSP_TAP_TAP35_C3_LPI_100TX_STATE_BITS               3
#define BRPHY1_DSP_TAP_TAP35_C3_LPI_100TX_STATE_SHIFT              12

/* BRPHY1_DSP_TAP :: TAP35_C3 :: RXSM_STATE [11:08] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_RXSM_STATE(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0xf00,8,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_RXSM_STATE(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0xf00,8)
#define BRPHY1_DSP_TAP_TAP35_C3_RXSM_STATE_MASK                    0x0f00
#define BRPHY1_DSP_TAP_TAP35_C3_RXSM_STATE_ALIGN                   0
#define BRPHY1_DSP_TAP_TAP35_C3_RXSM_STATE_BITS                    4
#define BRPHY1_DSP_TAP_TAP35_C3_RXSM_STATE_SHIFT                   8

/* BRPHY1_DSP_TAP :: TAP35_C3 :: SEED_INV_CTL [07:07] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x80,7)
#define BRPHY1_DSP_TAP_TAP35_C3_SEED_INV_CTL_MASK                  0x0080
#define BRPHY1_DSP_TAP_TAP35_C3_SEED_INV_CTL_ALIGN                 0
#define BRPHY1_DSP_TAP_TAP35_C3_SEED_INV_CTL_BITS                  1
#define BRPHY1_DSP_TAP_TAP35_C3_SEED_INV_CTL_SHIFT                 7

/* BRPHY1_DSP_TAP :: TAP35_C3 :: LOAD_N [06:06] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_LOAD_N(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_LOAD_N(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x40,6)
#define BRPHY1_DSP_TAP_TAP35_C3_LOAD_N_MASK                        0x0040
#define BRPHY1_DSP_TAP_TAP35_C3_LOAD_N_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP35_C3_LOAD_N_BITS                        1
#define BRPHY1_DSP_TAP_TAP35_C3_LOAD_N_SHIFT                       6

/* BRPHY1_DSP_TAP :: TAP35_C3 :: DET_IDLES [05:05] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_DET_IDLES(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_DET_IDLES(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x20,5)
#define BRPHY1_DSP_TAP_TAP35_C3_DET_IDLES_MASK                     0x0020
#define BRPHY1_DSP_TAP_TAP35_C3_DET_IDLES_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP35_C3_DET_IDLES_BITS                     1
#define BRPHY1_DSP_TAP_TAP35_C3_DET_IDLES_SHIFT                    5

/* BRPHY1_DSP_TAP :: TAP35_C3 :: DET_SLEEP [04:04] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_DET_SLEEP(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_DET_SLEEP(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x10,4)
#define BRPHY1_DSP_TAP_TAP35_C3_DET_SLEEP_MASK                     0x0010
#define BRPHY1_DSP_TAP_TAP35_C3_DET_SLEEP_ALIGN                    0
#define BRPHY1_DSP_TAP_TAP35_C3_DET_SLEEP_BITS                     1
#define BRPHY1_DSP_TAP_TAP35_C3_DET_SLEEP_SHIFT                    4

/* BRPHY1_DSP_TAP :: TAP35_C3 :: FUBAR [03:03] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_FUBAR(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_FUBAR(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x8,3)
#define BRPHY1_DSP_TAP_TAP35_C3_FUBAR_MASK                         0x0008
#define BRPHY1_DSP_TAP_TAP35_C3_FUBAR_ALIGN                        0
#define BRPHY1_DSP_TAP_TAP35_C3_FUBAR_BITS                         1
#define BRPHY1_DSP_TAP_TAP35_C3_FUBAR_SHIFT                        3

/* BRPHY1_DSP_TAP :: TAP35_C3 :: SR_NRZI [02:02] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_SR_NRZI(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_SR_NRZI(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x4,2)
#define BRPHY1_DSP_TAP_TAP35_C3_SR_NRZI_MASK                       0x0004
#define BRPHY1_DSP_TAP_TAP35_C3_SR_NRZI_ALIGN                      0
#define BRPHY1_DSP_TAP_TAP35_C3_SR_NRZI_BITS                       1
#define BRPHY1_DSP_TAP_TAP35_C3_SR_NRZI_SHIFT                      2

/* BRPHY1_DSP_TAP :: TAP35_C3 :: R_USCR [01:01] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_R_USCR(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_R_USCR(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x2,1)
#define BRPHY1_DSP_TAP_TAP35_C3_R_USCR_MASK                        0x0002
#define BRPHY1_DSP_TAP_TAP35_C3_R_USCR_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP35_C3_R_USCR_BITS                        1
#define BRPHY1_DSP_TAP_TAP35_C3_R_USCR_SHIFT                       1

/* BRPHY1_DSP_TAP :: TAP35_C3 :: LOCKED [00:00] */
#define Wr_BRPHY1_DSP_TAP_TAP35_C3_LOCKED(x) WriteRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_TAP35_C3_LOCKED(x) ReadRegBits16(BRPHY1_DSP_TAP_TAP35_C3,0x1,0)
#define BRPHY1_DSP_TAP_TAP35_C3_LOCKED_MASK                        0x0001
#define BRPHY1_DSP_TAP_TAP35_C3_LOCKED_ALIGN                       0
#define BRPHY1_DSP_TAP_TAP35_C3_LOCKED_BITS                        1
#define BRPHY1_DSP_TAP_TAP35_C3_LOCKED_SHIFT                       0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_CTL_CH0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x8000,15)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_MASK              0x8000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_SHIFT             15

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: DC_FREEZE [14:14] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x4000,14)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_MASK               0x4000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_ALIGN              0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_BITS               1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_SHIFT              14

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x2000,13)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_MASK             0x2000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_SHIFT            13

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x1000,12)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_MASK            0x1000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_SHIFT           12

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x800,11)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_MASK            0x0800
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_SHIFT           11

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x400,10)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_MASK            0x0400
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_SHIFT           10

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x200,9)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_MASK            0x0200
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_SHIFT           9

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x100,8)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_MASK              0x0100
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_SHIFT             8

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x80,7)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_MASK             0x0080
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_SHIFT            7

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: DC_DISABLE [06:06] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x40,6)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_MASK              0x0040
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_SHIFT             6

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x20,5)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_MASK            0x0020
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_SHIFT           5

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x10,4)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_MASK           0x0010
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_SHIFT          4

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x8,3)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_MASK           0x0008
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_SHIFT          3

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x4,2)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_MASK           0x0004
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_SHIFT          2

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x2,1)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_MASK           0x0002
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_SHIFT          1

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH0 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH0,0x1,0)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_MASK             0x0001
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_CTL_CH1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x8000,15)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_MASK              0x8000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_SHIFT             15

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: DC_FREEZE [14:14] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x4000,14)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_MASK               0x4000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_ALIGN              0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_BITS               1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_SHIFT              14

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x2000,13)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_MASK             0x2000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_SHIFT            13

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x1000,12)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_MASK            0x1000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_SHIFT           12

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x800,11)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_MASK            0x0800
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_SHIFT           11

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x400,10)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_MASK            0x0400
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_SHIFT           10

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x200,9)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_MASK            0x0200
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_SHIFT           9

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x100,8)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_MASK              0x0100
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_SHIFT             8

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x80,7)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_MASK             0x0080
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_SHIFT            7

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: DC_DISABLE [06:06] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x40,6)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_MASK              0x0040
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_SHIFT             6

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x20,5)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_MASK            0x0020
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_SHIFT           5

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x10,4)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_MASK           0x0010
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_SHIFT          4

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x8,3)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_MASK           0x0008
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_SHIFT          3

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x4,2)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_MASK           0x0004
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_SHIFT          2

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x2,1)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_MASK           0x0002
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_SHIFT          1

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH1 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH1,0x1,0)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_MASK             0x0001
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_CTL_CH2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x8000,15)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_MASK              0x8000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_SHIFT             15

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: DC_FREEZE [14:14] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x4000,14)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_MASK               0x4000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_ALIGN              0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_BITS               1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_SHIFT              14

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x2000,13)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_MASK             0x2000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_SHIFT            13

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x1000,12)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_MASK            0x1000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_SHIFT           12

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x800,11)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_MASK            0x0800
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_SHIFT           11

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x400,10)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_MASK            0x0400
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_SHIFT           10

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x200,9)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_MASK            0x0200
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_SHIFT           9

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x100,8)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_MASK              0x0100
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_SHIFT             8

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x80,7)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_MASK             0x0080
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_SHIFT            7

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: DC_DISABLE [06:06] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x40,6)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_MASK              0x0040
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_SHIFT             6

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x20,5)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_MASK            0x0020
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_SHIFT           5

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x10,4)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_MASK           0x0010
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_SHIFT          4

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x8,3)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_MASK           0x0008
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_SHIFT          3

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x4,2)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_MASK           0x0004
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_SHIFT          2

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x2,1)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_MASK           0x0002
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_SHIFT          1

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH2 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH2,0x1,0)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_MASK             0x0001
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_CTL_CH3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x8000,15)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_MASK              0x8000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_SHIFT             15

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: DC_FREEZE [14:14] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x4000,14)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_MASK               0x4000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_ALIGN              0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_BITS               1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_SHIFT              14

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x2000,13)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_MASK             0x2000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_SHIFT            13

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x1000,12)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_MASK            0x1000
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_SHIFT           12

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x800,11)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_MASK            0x0800
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_SHIFT           11

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x400,10)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_MASK            0x0400
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_SHIFT           10

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x200,9)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_MASK            0x0200
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_SHIFT           9

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x100,8)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_MASK              0x0100
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_SHIFT             8

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x80,7)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_MASK             0x0080
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_SHIFT            7

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: DC_DISABLE [06:06] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x40,6)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_MASK              0x0040
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_SHIFT             6

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x20,5)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_MASK            0x0020
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_SHIFT           5

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x10,4)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_MASK           0x0010
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_SHIFT          4

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x8,3)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_MASK           0x0008
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_SHIFT          3

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x4,2)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_MASK           0x0004
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_SHIFT          2

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x2,1)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_MASK           0x0002
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_ALIGN          0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_BITS           1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_SHIFT          1

/* BRPHY1_DSP_TAP :: FILTER_CTL_CH3 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_CH3,0x1,0)
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_MASK             0x0001
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_ALIGN            0
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_BITS             1
#define BRPHY1_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_MASK          0xff00
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_ALIGN         0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_BITS          8
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_SHIFT         8

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_MASK          0xff00
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_ALIGN         0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_BITS          8
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_SHIFT         8

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_MASK          0xff00
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_ALIGN         0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_BITS          8
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_SHIFT         8

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: reserved0 [15:08] */
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_MASK          0xff00
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_ALIGN         0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_BITS          8
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_SHIFT         8

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY1_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0)
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY1_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: reserved0 [15:15] */
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_MASK             0x8000
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_ALIGN            0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_BITS             1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_SHIFT            15

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT01_PRE1_DIS [14:14] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_MASK  0x4000
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_ALIGN 0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_BITS  1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_SHIFT 14

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: PHYC_SKIP_PHASE_ADJ [13:13] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_MASK   0x2000
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_ALIGN  0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_BITS   1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_SHIFT  13

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: LOCAL_TRAIN_DIS [12:12] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_MASK       0x1000
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_ALIGN      0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_BITS       1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_SHIFT      12

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: SLAVE_FDX_LOCAL_TRAIN_EN [11:11] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x800,11)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_MASK 0x0800
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_ALIGN 0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_BITS 1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_SHIFT 11

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: AUTO_LPF_EN [10:10] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x400,10)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_MASK           0x0400
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_ALIGN          0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_BITS           1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_SHIFT          10

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_PROTECT_EN [09:09] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x200,9)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_MASK        0x0200
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_ALIGN       0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_BITS        1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_SHIFT       9

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT1_DIS [08:08] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x100,8)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_MASK        0x0100
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_ALIGN       0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_BITS        1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_SHIFT       8

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_IDLEDATA_UPD_EN [07:04] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_MASK  0x00f0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_ALIGN 0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_BITS  4
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_SHIFT 4

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_EMI_UPD_EN [03:03] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x8,3)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_MASK       0x0008
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_ALIGN      0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_BITS       1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_SHIFT      3

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_VAL [02:02] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x4,2)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_MASK       0x0004
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_ALIGN      0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_BITS       1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_SHIFT      2

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_OV [01:01] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x2,1)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_MASK        0x0002
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_ALIGN       0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_BITS        1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_SHIFT       1

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_DATAPATH_EN [00:00] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL,0x1,0)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_MASK       0x0001
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_ALIGN      0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_BITS       1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_SHIFT      0


/****************************************************************************
 * BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL2
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL2 :: LPFREQ_SEL_STATUS [15:15] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_MASK    0x8000
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_ALIGN   0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_BITS    1
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_SHIFT   15

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL2 :: reserved0 [14:04] */
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_MASK            0x7ff0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_ALIGN           0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_BITS            11
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_SHIFT           4

/* BRPHY1_DSP_TAP :: EMI_DATAPATH_CTL2 :: GAMMA_LPF_THRESHOLD [03:00] */
#define Wr_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) WriteRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0,x)
#define Rd_BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) ReadRegBits16(BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0)
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_MASK  0x000f
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_ALIGN 0
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_BITS  4
#define BRPHY1_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_SHIFT 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FFEX_CTL
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FFEX_CTL :: reserved0 [15:12] */
#define BRPHY1_DSP_TAP_FFEX_CTL_RESERVED0_MASK                     0xf000
#define BRPHY1_DSP_TAP_FFEX_CTL_RESERVED0_ALIGN                    0
#define BRPHY1_DSP_TAP_FFEX_CTL_RESERVED0_BITS                     4
#define BRPHY1_DSP_TAP_FFEX_CTL_RESERVED0_SHIFT                    12

/* BRPHY1_DSP_TAP :: FFEX_CTL :: ENC_SLOW_LMS_CTL [11:10] */
#define Wr_BRPHY1_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) WriteRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0xc00,10,x)
#define Rd_BRPHY1_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) ReadRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0xc00,10)
#define BRPHY1_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_MASK              0x0c00
#define BRPHY1_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_ALIGN             0
#define BRPHY1_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_BITS              2
#define BRPHY1_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_SHIFT             10

/* BRPHY1_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV_VAL [09:09] */
#define Wr_BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x200,9)
#define BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_MASK               0x0200
#define BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_ALIGN              0
#define BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_BITS               1
#define BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_SHIFT              9

/* BRPHY1_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV [08:08] */
#define Wr_BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x100,8)
#define BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_MASK                   0x0100
#define BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_ALIGN                  0
#define BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_BITS                   1
#define BRPHY1_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_SHIFT                  8

/* BRPHY1_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_VAL [07:07] */
#define Wr_BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) WriteRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) ReadRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x80,7)
#define BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_MASK          0x0080
#define BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_ALIGN         0
#define BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_BITS          1
#define BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_SHIFT         7

/* BRPHY1_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_OV [06:06] */
#define Wr_BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) WriteRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) ReadRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x40,6)
#define BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_MASK           0x0040
#define BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_ALIGN          0
#define BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_BITS           1
#define BRPHY1_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_SHIFT          6

/* BRPHY1_DSP_TAP :: FFEX_CTL :: FFEX_MAINTAP [05:03] */
#define Wr_BRPHY1_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) WriteRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x38,3,x)
#define Rd_BRPHY1_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) ReadRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x38,3)
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_MASK                  0x0038
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_ALIGN                 0
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_BITS                  3
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_SHIFT                 3

/* BRPHY1_DSP_TAP :: FFEX_CTL :: FFEX_LMS_MODE [02:01] */
#define Wr_BRPHY1_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) WriteRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x6,1,x)
#define Rd_BRPHY1_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) ReadRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x6,1)
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_MASK                 0x0006
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_ALIGN                0
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_BITS                 2
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_SHIFT                1

/* BRPHY1_DSP_TAP :: FFEX_CTL :: FFEX_EN [00:00] */
#define Wr_BRPHY1_DSP_TAP_FFEX_CTL_FFEX_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_FFEX_CTL_FFEX_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_FFEX_CTL,0x1,0)
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_EN_MASK                       0x0001
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_EN_ALIGN                      0
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_EN_BITS                       1
#define BRPHY1_DSP_TAP_FFEX_CTL_FFEX_EN_SHIFT                      0


/****************************************************************************
 * BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL0
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_STOP [15:15] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_MASK 0x8000
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_BITS 1
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_SHIFT 15

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: reserved0 [14:07] */
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_MASK         0x7f80
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_ALIGN        0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_BITS         8
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_SHIFT        7

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_MAINSTATE [06:02] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_MASK 0x007c
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_BITS 5
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_SHIFT 2

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_CLR [01:01] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_MASK 0x0002
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_BITS 1
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_SHIFT 1

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_EN [00:00] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_MASK 0x0001
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_BITS 1
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_SHIFT 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL1
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D_EN [15:15] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_MASK 0x8000
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_BITS 1
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_SHIFT 15

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D [14:12] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_MASK 0x7000
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_BITS 3
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_SHIFT 12

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C_EN [11:11] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_MASK 0x0800
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_BITS 1
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_SHIFT 11

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C [10:08] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_MASK 0x0700
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_BITS 3
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_SHIFT 8

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B_EN [07:07] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_MASK 0x0080
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_BITS 1
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_SHIFT 7

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B [06:04] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_MASK 0x0070
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_BITS 3
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_SHIFT 4

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A_EN [03:03] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_MASK 0x0008
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_BITS 1
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_SHIFT 3

/* BRPHY1_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A [02:00] */
#define Wr_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) WriteRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0,x)
#define Rd_BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) ReadRegBits16(BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0)
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_MASK 0x0007
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_ALIGN 0
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_BITS 3
#define BRPHY1_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_SHIFT 0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_ADDR
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_ADDR :: CTL_ALL_CH [15:15] */
#define Wr_BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0x8000,15,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0x8000,15)
#define BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_MASK                 0x8000
#define BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_ALIGN                0
#define BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_BITS                 1
#define BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_SHIFT                15

/* BRPHY1_DSP_TAP :: FILTER_ADDR :: CH_SEL [14:13] */
#define Wr_BRPHY1_DSP_TAP_FILTER_ADDR_CH_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0x6000,13,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_ADDR_CH_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0x6000,13)
#define BRPHY1_DSP_TAP_FILTER_ADDR_CH_SEL_MASK                     0x6000
#define BRPHY1_DSP_TAP_FILTER_ADDR_CH_SEL_ALIGN                    0
#define BRPHY1_DSP_TAP_FILTER_ADDR_CH_SEL_BITS                     2
#define BRPHY1_DSP_TAP_FILTER_ADDR_CH_SEL_SHIFT                    13

/* BRPHY1_DSP_TAP :: FILTER_ADDR :: CTL_ALL_FILTERS [12:12] */
#define Wr_BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0x1000,12)
#define BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_MASK            0x1000
#define BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_BITS            1
#define BRPHY1_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_SHIFT           12

/* BRPHY1_DSP_TAP :: FILTER_ADDR :: FILTER_SEL [11:08] */
#define Wr_BRPHY1_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0xf00,8,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0xf00,8)
#define BRPHY1_DSP_TAP_FILTER_ADDR_FILTER_SEL_MASK                 0x0f00
#define BRPHY1_DSP_TAP_FILTER_ADDR_FILTER_SEL_ALIGN                0
#define BRPHY1_DSP_TAP_FILTER_ADDR_FILTER_SEL_BITS                 4
#define BRPHY1_DSP_TAP_FILTER_ADDR_FILTER_SEL_SHIFT                8

/* BRPHY1_DSP_TAP :: FILTER_ADDR :: TAP_NUMBER [07:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0xff,0,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_ADDR,0xff,0)
#define BRPHY1_DSP_TAP_FILTER_ADDR_TAP_NUMBER_MASK                 0x00ff
#define BRPHY1_DSP_TAP_FILTER_ADDR_TAP_NUMBER_ALIGN                0
#define BRPHY1_DSP_TAP_FILTER_ADDR_TAP_NUMBER_BITS                 8
#define BRPHY1_DSP_TAP_FILTER_ADDR_TAP_NUMBER_SHIFT                0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_CTL
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_CTL :: reserved0 [15:13] */
#define BRPHY1_DSP_TAP_FILTER_CTL_RESERVED0_MASK                   0xe000
#define BRPHY1_DSP_TAP_FILTER_CTL_RESERVED0_ALIGN                  0
#define BRPHY1_DSP_TAP_FILTER_CTL_RESERVED0_BITS                   3
#define BRPHY1_DSP_TAP_FILTER_CTL_RESERVED0_SHIFT                  13

/* BRPHY1_DSP_TAP :: FILTER_CTL :: BUSY [12:12] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_BUSY(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x1000,12,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_BUSY(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x1000,12)
#define BRPHY1_DSP_TAP_FILTER_CTL_BUSY_MASK                        0x1000
#define BRPHY1_DSP_TAP_FILTER_CTL_BUSY_ALIGN                       0
#define BRPHY1_DSP_TAP_FILTER_CTL_BUSY_BITS                        1
#define BRPHY1_DSP_TAP_FILTER_CTL_BUSY_SHIFT                       12

/* BRPHY1_DSP_TAP :: FILTER_CTL :: TAP_PREFETCH [11:11] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x800,11,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x800,11)
#define BRPHY1_DSP_TAP_FILTER_CTL_TAP_PREFETCH_MASK                0x0800
#define BRPHY1_DSP_TAP_FILTER_CTL_TAP_PREFETCH_ALIGN               0
#define BRPHY1_DSP_TAP_FILTER_CTL_TAP_PREFETCH_BITS                1
#define BRPHY1_DSP_TAP_FILTER_CTL_TAP_PREFETCH_SHIFT               11

/* BRPHY1_DSP_TAP :: FILTER_CTL :: UPPER_WORD_SEL [10:10] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x400,10,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x400,10)
#define BRPHY1_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_MASK              0x0400
#define BRPHY1_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_SHIFT             10

/* BRPHY1_DSP_TAP :: FILTER_CTL :: WR_COEFF [09:09] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_WR_COEFF(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x200,9,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_WR_COEFF(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x200,9)
#define BRPHY1_DSP_TAP_FILTER_CTL_WR_COEFF_MASK                    0x0200
#define BRPHY1_DSP_TAP_FILTER_CTL_WR_COEFF_ALIGN                   0
#define BRPHY1_DSP_TAP_FILTER_CTL_WR_COEFF_BITS                    1
#define BRPHY1_DSP_TAP_FILTER_CTL_WR_COEFF_SHIFT                   9

/* BRPHY1_DSP_TAP :: FILTER_CTL :: WR_ALL_NEXT_COEF [08:08] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x100,8,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x100,8)
#define BRPHY1_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_MASK            0x0100
#define BRPHY1_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_ALIGN           0
#define BRPHY1_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_BITS            1
#define BRPHY1_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_SHIFT           8

/* BRPHY1_DSP_TAP :: FILTER_CTL :: RD_COEFF [07:07] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_RD_COEFF(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x80,7,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_RD_COEFF(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x80,7)
#define BRPHY1_DSP_TAP_FILTER_CTL_RD_COEFF_MASK                    0x0080
#define BRPHY1_DSP_TAP_FILTER_CTL_RD_COEFF_ALIGN                   0
#define BRPHY1_DSP_TAP_FILTER_CTL_RD_COEFF_BITS                    1
#define BRPHY1_DSP_TAP_FILTER_CTL_RD_COEFF_SHIFT                   7

/* BRPHY1_DSP_TAP :: FILTER_CTL :: INIT_RAM [06:06] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_INIT_RAM(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x40,6,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_INIT_RAM(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x40,6)
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_RAM_MASK                    0x0040
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_RAM_ALIGN                   0
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_RAM_BITS                    1
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_RAM_SHIFT                   6

/* BRPHY1_DSP_TAP :: FILTER_CTL :: INIT_ENC [05:05] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_INIT_ENC(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x20,5,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_INIT_ENC(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x20,5)
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_ENC_MASK                    0x0020
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_ENC_ALIGN                   0
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_ENC_BITS                    1
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_ENC_SHIFT                   5

/* BRPHY1_DSP_TAP :: FILTER_CTL :: INIT_DFE [04:04] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_INIT_DFE(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x10,4,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_INIT_DFE(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x10,4)
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_DFE_MASK                    0x0010
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_DFE_ALIGN                   0
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_DFE_BITS                    1
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_DFE_SHIFT                   4

/* BRPHY1_DSP_TAP :: FILTER_CTL :: INIT_FFEXTAP [03:03] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x8,3,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x8,3)
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_MASK                0x0008
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_ALIGN               0
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_BITS                1
#define BRPHY1_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_SHIFT               3

/* BRPHY1_DSP_TAP :: FILTER_CTL :: DISABLE_FILTER [02:02] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x4,2,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x4,2)
#define BRPHY1_DSP_TAP_FILTER_CTL_DISABLE_FILTER_MASK              0x0004
#define BRPHY1_DSP_TAP_FILTER_CTL_DISABLE_FILTER_ALIGN             0
#define BRPHY1_DSP_TAP_FILTER_CTL_DISABLE_FILTER_BITS              1
#define BRPHY1_DSP_TAP_FILTER_CTL_DISABLE_FILTER_SHIFT             2

/* BRPHY1_DSP_TAP :: FILTER_CTL :: FREEZE_FILTER [01:01] */
#define Wr_BRPHY1_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) WriteRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x2,1,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) ReadRegBits16(BRPHY1_DSP_TAP_FILTER_CTL,0x2,1)
#define BRPHY1_DSP_TAP_FILTER_CTL_FREEZE_FILTER_MASK               0x0002
#define BRPHY1_DSP_TAP_FILTER_CTL_FREEZE_FILTER_ALIGN              0
#define BRPHY1_DSP_TAP_FILTER_CTL_FREEZE_FILTER_BITS               1
#define BRPHY1_DSP_TAP_FILTER_CTL_FREEZE_FILTER_SHIFT              1

/* BRPHY1_DSP_TAP :: FILTER_CTL :: reserved1 [00:00] */
#define BRPHY1_DSP_TAP_FILTER_CTL_RESERVED1_MASK                   0x0001
#define BRPHY1_DSP_TAP_FILTER_CTL_RESERVED1_ALIGN                  0
#define BRPHY1_DSP_TAP_FILTER_CTL_RESERVED1_BITS                   1
#define BRPHY1_DSP_TAP_FILTER_CTL_RESERVED1_SHIFT                  0


/****************************************************************************
 * BRPHY1_DSP_TAP :: FILTER_DATA
 ***************************************************************************/
/* BRPHY1_DSP_TAP :: FILTER_DATA :: TAP_COEFF [15:00] */
#define Wr_BRPHY1_DSP_TAP_FILTER_DATA_TAP_COEFF(x) WriteReg16(BRPHY1_DSP_TAP_FILTER_DATA,x)
#define Rd_BRPHY1_DSP_TAP_FILTER_DATA_TAP_COEFF(x) ReadReg16(BRPHY1_DSP_TAP_FILTER_DATA)
#define BRPHY1_DSP_TAP_FILTER_DATA_TAP_COEFF_MASK                  0xffff
#define BRPHY1_DSP_TAP_FILTER_DATA_TAP_COEFF_ALIGN                 0
#define BRPHY1_DSP_TAP_FILTER_DATA_TAP_COEFF_BITS                  16
#define BRPHY1_DSP_TAP_FILTER_DATA_TAP_COEFF_SHIFT                 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_PLL_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLLCTRL_0
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLLCTRL_0 :: PLL_CTL [15:00] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) WriteReg16(BRPHY1_PLL_CTRL_PLLCTRL_0,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) ReadReg16(BRPHY1_PLL_CTRL_PLLCTRL_0)
#define BRPHY1_PLL_CTRL_PLLCTRL_0_PLL_CTL_MASK                     0xffff
#define BRPHY1_PLL_CTRL_PLLCTRL_0_PLL_CTL_ALIGN                    0
#define BRPHY1_PLL_CTRL_PLLCTRL_0_PLL_CTL_BITS                     16
#define BRPHY1_PLL_CTRL_PLLCTRL_0_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLLCTRL_1
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLLCTRL_1 :: PLL_CTL [15:00] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) WriteReg16(BRPHY1_PLL_CTRL_PLLCTRL_1,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) ReadReg16(BRPHY1_PLL_CTRL_PLLCTRL_1)
#define BRPHY1_PLL_CTRL_PLLCTRL_1_PLL_CTL_MASK                     0xffff
#define BRPHY1_PLL_CTRL_PLLCTRL_1_PLL_CTL_ALIGN                    0
#define BRPHY1_PLL_CTRL_PLLCTRL_1_PLL_CTL_BITS                     16
#define BRPHY1_PLL_CTRL_PLLCTRL_1_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLLCTRL_2
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2 [15:14] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_2,0xc000,14,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_2,0xc000,14)
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_MASK                  0xc000
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_ALIGN                 0
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_BITS                  2
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_SHIFT                 14

/* BRPHY1_PLL_CTRL :: PLLCTRL_2 :: PLL_PDIV [13:10] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_2,0x3c00,10,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_2,0x3c00,10)
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_PDIV_MASK                    0x3c00
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_PDIV_ALIGN                   0
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_PDIV_BITS                    4
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_PDIV_SHIFT                   10

/* BRPHY1_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2_2 [09:00] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_2,0x3ff,0,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_2,0x3ff,0)
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_MASK                0x03ff
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_ALIGN               0
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_BITS                10
#define BRPHY1_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_SHIFT               0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLLCTRL_3
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLLCTRL_3 :: PLL_SPARE3 [15:10] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_3,0xfc00,10,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_3,0xfc00,10)
#define BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_MASK                  0xfc00
#define BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_ALIGN                 0
#define BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_BITS                  6
#define BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_SHIFT                 10

/* BRPHY1_PLL_CTRL :: PLLCTRL_3 :: PLL_NDIV_INT_MS [09:00] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_3,0x3ff,0,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_3,0x3ff,0)
#define BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_MASK             0x03ff
#define BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_ALIGN            0
#define BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_BITS             10
#define BRPHY1_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_SHIFT            0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLLCTRL_4
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4 [15:15] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x8000,15,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x8000,15)
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_MASK                  0x8000
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_ALIGN                 0
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_BITS                  1
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_SHIFT                 15

/* BRPHY1_PLL_CTRL :: PLLCTRL_4 :: SD_SEL_300mV [14:14] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x4000,14,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x4000,14)
#define BRPHY1_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_MASK                0x4000
#define BRPHY1_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_ALIGN               0
#define BRPHY1_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_BITS                1
#define BRPHY1_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_SHIFT               14

/* BRPHY1_PLL_CTRL :: PLLCTRL_4 :: CML_BUF_TUNE [13:12] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x3000,12,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x3000,12)
#define BRPHY1_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_MASK                0x3000
#define BRPHY1_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_ALIGN               0
#define BRPHY1_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_BITS                2
#define BRPHY1_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_SHIFT               12

/* BRPHY1_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_BANDGAP [11:09] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0xe00,9,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0xe00,9)
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_MASK            0x0e00
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_ALIGN           0
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_BITS            3
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_SHIFT           9

/* BRPHY1_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4a [08:06] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x1c0,6,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x1c0,6)
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_MASK                 0x01c0
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_ALIGN                0
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_BITS                 3
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_SHIFT                6

/* BRPHY1_PLL_CTRL :: PLLCTRL_4 :: ATEST_OR_BIAS_TEST_OUTPUT [05:05] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x20,5,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x20,5)
#define BRPHY1_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_MASK   0x0020
#define BRPHY1_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_ALIGN  0
#define BRPHY1_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_BITS   1
#define BRPHY1_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_SHIFT  5

/* BRPHY1_PLL_CTRL :: PLLCTRL_4 :: PLL_MUX_ATEST [04:03] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x18,3,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x18,3)
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_MASK               0x0018
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_ALIGN              0
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_BITS               2
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_SHIFT              3

/* BRPHY1_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_TEST_MUX [02:00] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x7,0,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_4,0x7,0)
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_MASK           0x0007
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_ALIGN          0
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_BITS           3
#define BRPHY1_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_SHIFT          0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLLCTRL_5
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLLCTRL_5 :: PLL_SPARE5 [15:14] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0xc000,14,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0xc000,14)
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_MASK                  0xc000
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_ALIGN                 0
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_BITS                  2
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_SHIFT                 14

/* BRPHY1_PLL_CTRL :: PLLCTRL_5 :: PLL_CP [13:13] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x2000,13,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x2000,13)
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP_MASK                      0x2000
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP_ALIGN                     0
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP_BITS                      1
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP_SHIFT                     13

/* BRPHY1_PLL_CTRL :: PLLCTRL_5 :: PLL_CP1 [12:12] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x1000,12,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x1000,12)
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP1_MASK                     0x1000
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP1_ALIGN                    0
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP1_BITS                     1
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CP1_SHIFT                    12

/* BRPHY1_PLL_CTRL :: PLLCTRL_5 :: PLL_CZ [11:11] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x800,11,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x800,11)
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CZ_MASK                      0x0800
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CZ_ALIGN                     0
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CZ_BITS                      1
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_CZ_SHIFT                     11

/* BRPHY1_PLL_CTRL :: PLLCTRL_5 :: PLL_RZ [10:07] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x780,7,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x780,7)
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_RZ_MASK                      0x0780
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_RZ_ALIGN                     0
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_RZ_BITS                      4
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_RZ_SHIFT                     7

/* BRPHY1_PLL_CTRL :: PLLCTRL_5 :: PLL_ICP [06:03] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x78,3,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x78,3)
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_ICP_MASK                     0x0078
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_ICP_ALIGN                    0
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_ICP_BITS                     4
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_ICP_SHIFT                    3

/* BRPHY1_PLL_CTRL :: PLLCTRL_5 :: PLL_VCO_GAIN [02:00] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x7,0,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_5,0x7,0)
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_MASK                0x0007
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_ALIGN               0
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_BITS                3
#define BRPHY1_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_SHIFT               0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLLCTRL_6
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLLCTRL_6 :: PLL_SPARE6 [15:09] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0xfe00,9,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0xfe00,9)
#define BRPHY1_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_MASK                  0xfe00
#define BRPHY1_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_ALIGN                 0
#define BRPHY1_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_BITS                  7
#define BRPHY1_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_SHIFT                 9

/* BRPHY1_PLL_CTRL :: PLLCTRL_6 :: POR_CONFIG [08:07] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0x180,7,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0x180,7)
#define BRPHY1_PLL_CTRL_PLLCTRL_6_POR_CONFIG_MASK                  0x0180
#define BRPHY1_PLL_CTRL_PLLCTRL_6_POR_CONFIG_ALIGN                 0
#define BRPHY1_PLL_CTRL_PLLCTRL_6_POR_CONFIG_BITS                  2
#define BRPHY1_PLL_CTRL_PLLCTRL_6_POR_CONFIG_SHIFT                 7

/* BRPHY1_PLL_CTRL :: PLLCTRL_6 :: CLK500_EN [06:06] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0x40,6,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0x40,6)
#define BRPHY1_PLL_CTRL_PLLCTRL_6_CLK500_EN_MASK                   0x0040
#define BRPHY1_PLL_CTRL_PLLCTRL_6_CLK500_EN_ALIGN                  0
#define BRPHY1_PLL_CTRL_PLLCTRL_6_CLK500_EN_BITS                   1
#define BRPHY1_PLL_CTRL_PLLCTRL_6_CLK500_EN_SHIFT                  6

/* BRPHY1_PLL_CTRL :: PLLCTRL_6 :: RCAL_OFFSET [05:03] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0x38,3,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0x38,3)
#define BRPHY1_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_MASK                 0x0038
#define BRPHY1_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_ALIGN                0
#define BRPHY1_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_BITS                 3
#define BRPHY1_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_SHIFT                3

/* BRPHY1_PLL_CTRL :: PLLCTRL_6 :: RCCAL_OFFSET [02:00] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0x7,0,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_6,0x7,0)
#define BRPHY1_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_MASK                0x0007
#define BRPHY1_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_ALIGN               0
#define BRPHY1_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_BITS                3
#define BRPHY1_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_SHIFT               0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLL_STATUS_0
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLL_STATUS_0 :: reserved0 [15:12] */
#define BRPHY1_PLL_CTRL_PLL_STATUS_0_RESERVED0_MASK                0xf000
#define BRPHY1_PLL_CTRL_PLL_STATUS_0_RESERVED0_ALIGN               0
#define BRPHY1_PLL_CTRL_PLL_STATUS_0_RESERVED0_BITS                4
#define BRPHY1_PLL_CTRL_PLL_STATUS_0_RESERVED0_SHIFT               12

/* BRPHY1_PLL_CTRL :: PLL_STATUS_0 :: PLL_STATUS_WORD [11:00] */
#define Wr_BRPHY1_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLL_STATUS_0,0xfff,0,x)
#define Rd_BRPHY1_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLL_STATUS_0,0xfff,0)
#define BRPHY1_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_MASK          0x0fff
#define BRPHY1_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_ALIGN         0
#define BRPHY1_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_BITS          12
#define BRPHY1_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_SHIFT         0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLL_STATUS_1
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLL_STATUS_1 :: reserved0 [15:09] */
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_RESERVED0_MASK                0xfe00
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_RESERVED0_ALIGN               0
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_RESERVED0_BITS                7
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_RESERVED0_SHIFT               9

/* BRPHY1_PLL_CTRL :: PLL_STATUS_1 :: PLL_LOCK [08:08] */
#define Wr_BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLL_STATUS_1,0x100,8,x)
#define Rd_BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLL_STATUS_1,0x100,8)
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_MASK                 0x0100
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_ALIGN                0
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_BITS                 1
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_SHIFT                8

/* BRPHY1_PLL_CTRL :: PLL_STATUS_1 :: reserved1 [07:04] */
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_RESERVED1_MASK                0x00f0
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_RESERVED1_ALIGN               0
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_RESERVED1_BITS                4
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_RESERVED1_SHIFT               4

/* BRPHY1_PLL_CTRL :: PLL_STATUS_1 :: PLL_BER [03:00] */
#define Wr_BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLL_STATUS_1,0xf,0,x)
#define Rd_BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLL_STATUS_1,0xf,0)
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_BER_MASK                  0x000f
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_BER_ALIGN                 0
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_BER_BITS                  4
#define BRPHY1_PLL_CTRL_PLL_STATUS_1_PLL_BER_SHIFT                 0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: AFE_SIGDET_STATUS
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: AFE_SIGDET_STATUS :: reserved0 [15:07] */
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_MASK           0xff80
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_ALIGN          0
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_BITS           9
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_SHIFT          7

/* BRPHY1_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_SIGSTATE [06:01] */
#define Wr_BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) WriteRegBits16(BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1,x)
#define Rd_BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) ReadRegBits16(BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1)
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_MASK    0x007e
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_ALIGN   0
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_BITS    6
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_SHIFT   1

/* BRPHY1_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_Select [00:00] */
#define Wr_BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) WriteRegBits16(BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0,x)
#define Rd_BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) ReadRegBits16(BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0)
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_MASK      0x0001
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_ALIGN     0
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_BITS      1
#define BRPHY1_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_SHIFT     0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLLCTRL_7
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLLCTRL_7 :: TVCO_MUX_EN [15:15] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x8000,15,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x8000,15)
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_MASK                 0x8000
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_ALIGN                0
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_BITS                 1
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_SHIFT                15

/* BRPHY1_PLL_CTRL :: PLLCTRL_7 :: TVCO_PAD [14:12] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x7000,12,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x7000,12)
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_PAD_MASK                    0x7000
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_PAD_ALIGN                   0
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_PAD_BITS                    3
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TVCO_PAD_SHIFT                   12

/* BRPHY1_PLL_CTRL :: PLLCTRL_7 :: ADJUST_AUX_LDO [11:11] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x800,11,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x800,11)
#define BRPHY1_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_MASK              0x0800
#define BRPHY1_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_ALIGN             0
#define BRPHY1_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_BITS              1
#define BRPHY1_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_SHIFT             11

/* BRPHY1_PLL_CTRL :: PLLCTRL_7 :: CLAMP_REFERENCE [10:09] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x600,9,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x600,9)
#define BRPHY1_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_MASK             0x0600
#define BRPHY1_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_ALIGN            0
#define BRPHY1_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_BITS             2
#define BRPHY1_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_SHIFT            9

/* BRPHY1_PLL_CTRL :: PLLCTRL_7 :: CML_BUFFER_PWRDN [08:08] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x100,8,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0x100,8)
#define BRPHY1_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_MASK            0x0100
#define BRPHY1_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_ALIGN           0
#define BRPHY1_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_BITS            1
#define BRPHY1_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_SHIFT           8

/* BRPHY1_PLL_CTRL :: PLLCTRL_7 :: TXCLK_PWRDN [07:04] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0xf0,4,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0xf0,4)
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_MASK                 0x00f0
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_ALIGN                0
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_BITS                 4
#define BRPHY1_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_SHIFT                4

/* BRPHY1_PLL_CTRL :: PLLCTRL_7 :: RXCLK_PWRDN [03:00] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0xf,0,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_7,0xf,0)
#define BRPHY1_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_MASK                 0x000f
#define BRPHY1_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_ALIGN                0
#define BRPHY1_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_BITS                 4
#define BRPHY1_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_SHIFT                0


/****************************************************************************
 * BRPHY1_PLL_CTRL :: PLLCTRL_8
 ***************************************************************************/
/* BRPHY1_PLL_CTRL :: PLLCTRL_8 :: PLL_SPARE5 [15:01] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_8,0xfffe,1,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_8,0xfffe,1)
#define BRPHY1_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_MASK                  0xfffe
#define BRPHY1_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_ALIGN                 0
#define BRPHY1_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_BITS                  15
#define BRPHY1_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_SHIFT                 1

/* BRPHY1_PLL_CTRL :: PLLCTRL_8 :: PC_CLK_1G_PWRDN [00:00] */
#define Wr_BRPHY1_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) WriteRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_8,0x1,0,x)
#define Rd_BRPHY1_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) ReadRegBits16(BRPHY1_PLL_CTRL_PLLCTRL_8,0x1,0)
#define BRPHY1_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_MASK             0x0001
#define BRPHY1_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_ALIGN            0
#define BRPHY1_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_BITS             1
#define BRPHY1_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_SHIFT            0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_AFE_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_AFE_CTRL :: RXCONFIG_0
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: RXCONFIG_0 :: RXCONFIG_15_0 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) WriteReg16(BRPHY1_AFE_CTRL_RXCONFIG_0,x)
#define Rd_BRPHY1_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) ReadReg16(BRPHY1_AFE_CTRL_RXCONFIG_0)
#define BRPHY1_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_MASK              0xffff
#define BRPHY1_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_ALIGN             0
#define BRPHY1_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_BITS              16
#define BRPHY1_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_SHIFT             0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: RXCONFIG_1
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: RXCONFIG_1 :: RXCONFIG_31_23 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) WriteReg16(BRPHY1_AFE_CTRL_RXCONFIG_1,x)
#define Rd_BRPHY1_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) ReadReg16(BRPHY1_AFE_CTRL_RXCONFIG_1)
#define BRPHY1_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_MASK             0xffff
#define BRPHY1_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_ALIGN            0
#define BRPHY1_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_BITS             16
#define BRPHY1_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_SHIFT            0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: RXCONFIG_2
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: RXCONFIG_2 :: RXCONFIG_47_32 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) WriteReg16(BRPHY1_AFE_CTRL_RXCONFIG_2,x)
#define Rd_BRPHY1_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) ReadReg16(BRPHY1_AFE_CTRL_RXCONFIG_2)
#define BRPHY1_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_MASK             0xffff
#define BRPHY1_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_ALIGN            0
#define BRPHY1_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_BITS             16
#define BRPHY1_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_SHIFT            0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: RXCONFIG_3
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: RXCONFIG_3 :: RXCONFIG_63_48 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) WriteReg16(BRPHY1_AFE_CTRL_RXCONFIG_3,x)
#define Rd_BRPHY1_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) ReadReg16(BRPHY1_AFE_CTRL_RXCONFIG_3)
#define BRPHY1_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_MASK             0xffff
#define BRPHY1_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_ALIGN            0
#define BRPHY1_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_BITS             16
#define BRPHY1_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_SHIFT            0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: RXCONFIG_4
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: RXCONFIG_4 :: RXCONFIG_79_64 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) WriteReg16(BRPHY1_AFE_CTRL_RXCONFIG_4,x)
#define Rd_BRPHY1_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) ReadReg16(BRPHY1_AFE_CTRL_RXCONFIG_4)
#define BRPHY1_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_MASK             0xffff
#define BRPHY1_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_ALIGN            0
#define BRPHY1_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_BITS             16
#define BRPHY1_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_SHIFT            0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: RXCONFIG5_LP
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: RXCONFIG5_LP :: RXCONFIG_86_80 [15:09] */
#define Wr_BRPHY1_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) WriteRegBits16(BRPHY1_AFE_CTRL_RXCONFIG5_LP,0xfe00,9,x)
#define Rd_BRPHY1_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) ReadRegBits16(BRPHY1_AFE_CTRL_RXCONFIG5_LP,0xfe00,9)
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_MASK           0xfe00
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_ALIGN          0
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_BITS           7
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_SHIFT          9

/* BRPHY1_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_0 [08:06] */
#define Wr_BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) WriteRegBits16(BRPHY1_AFE_CTRL_RXCONFIG5_LP,0x1c0,6,x)
#define Rd_BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) ReadRegBits16(BRPHY1_AFE_CTRL_RXCONFIG5_LP,0x1c0,6)
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_MASK                  0x01c0
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_ALIGN                 0
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_BITS                  3
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_SHIFT                 6

/* BRPHY1_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_1 [05:03] */
#define Wr_BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) WriteRegBits16(BRPHY1_AFE_CTRL_RXCONFIG5_LP,0x38,3,x)
#define Rd_BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) ReadRegBits16(BRPHY1_AFE_CTRL_RXCONFIG5_LP,0x38,3)
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_MASK                  0x0038
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_ALIGN                 0
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_BITS                  3
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_SHIFT                 3

/* BRPHY1_AFE_CTRL :: RXCONFIG5_LP :: MODE_force [02:00] */
#define Wr_BRPHY1_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) WriteRegBits16(BRPHY1_AFE_CTRL_RXCONFIG5_LP,0x7,0,x)
#define Rd_BRPHY1_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) ReadRegBits16(BRPHY1_AFE_CTRL_RXCONFIG5_LP,0x7,0)
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_MASK               0x0007
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_ALIGN              0
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_BITS               3
#define BRPHY1_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_SHIFT              0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: TX_CONFIG_0
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: TX_CONFIG_0 :: TX_CONFIG_15_0 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) WriteReg16(BRPHY1_AFE_CTRL_TX_CONFIG_0,x)
#define Rd_BRPHY1_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) ReadReg16(BRPHY1_AFE_CTRL_TX_CONFIG_0)
#define BRPHY1_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_MASK            0xffff
#define BRPHY1_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_ALIGN           0
#define BRPHY1_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_BITS            16
#define BRPHY1_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_SHIFT           0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: TX_CONFIG_1
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: TX_CONFIG_1 :: TX_BW_TUNE [15:11] */
#define Wr_BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) WriteRegBits16(BRPHY1_AFE_CTRL_TX_CONFIG_1,0xf800,11,x)
#define Rd_BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) ReadRegBits16(BRPHY1_AFE_CTRL_TX_CONFIG_1,0xf800,11)
#define BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_MASK                0xf800
#define BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_ALIGN               0
#define BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_BITS                5
#define BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_SHIFT               11

/* BRPHY1_AFE_CTRL :: TX_CONFIG_1 :: TX_CONFIG_26_16 [10:00] */
#define Wr_BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) WriteRegBits16(BRPHY1_AFE_CTRL_TX_CONFIG_1,0x7ff,0,x)
#define Rd_BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) ReadRegBits16(BRPHY1_AFE_CTRL_TX_CONFIG_1,0x7ff,0)
#define BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_MASK           0x07ff
#define BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_ALIGN          0
#define BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_BITS           11
#define BRPHY1_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_SHIFT          0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: VDAC_ICTRL_0
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: VDAC_ICTRL_0 :: VDAC_current_ctrl_15_0 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) WriteReg16(BRPHY1_AFE_CTRL_VDAC_ICTRL_0,x)
#define Rd_BRPHY1_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) ReadReg16(BRPHY1_AFE_CTRL_VDAC_ICTRL_0)
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_MASK   0xffff
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_ALIGN  0
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_BITS   16
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_SHIFT  0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: VDAC_ICTRL_1
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: VDAC_ICTRL_1 :: VDAC_current_ctrl_31_16 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) WriteReg16(BRPHY1_AFE_CTRL_VDAC_ICTRL_1,x)
#define Rd_BRPHY1_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) ReadReg16(BRPHY1_AFE_CTRL_VDAC_ICTRL_1)
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_MASK  0xffff
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_ALIGN 0
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_BITS  16
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_SHIFT 0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: VDAC_ICTRL_2
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: VDAC_ICTRL_2 :: VDAC_current_ctrl_51_36 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) WriteReg16(BRPHY1_AFE_CTRL_VDAC_ICTRL_2,x)
#define Rd_BRPHY1_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) ReadReg16(BRPHY1_AFE_CTRL_VDAC_ICTRL_2)
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_MASK  0xffff
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_ALIGN 0
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_BITS  16
#define BRPHY1_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_SHIFT 0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: VDAC_OTHERS_0
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: VDAC_OTHERS_0 :: current_ctrl_35_32_others [15:00] */
#define Wr_BRPHY1_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) WriteReg16(BRPHY1_AFE_CTRL_VDAC_OTHERS_0,x)
#define Rd_BRPHY1_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) ReadReg16(BRPHY1_AFE_CTRL_VDAC_OTHERS_0)
#define BRPHY1_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_MASK 0xffff
#define BRPHY1_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_ALIGN 0
#define BRPHY1_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_BITS 16
#define BRPHY1_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_SHIFT 0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: HPF_TRIM_OTHERS
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: HPF_TRIM_OTHERS :: Reserved [15:10] */
#define Wr_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) WriteRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10,x)
#define Rd_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) ReadRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10)
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_MASK              0xfc00
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_ALIGN             0
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_BITS              6
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_SHIFT             10

/* BRPHY1_AFE_CTRL :: HPF_TRIM_OTHERS :: RX_SAMPLE_WIDTH [09:07] */
#define Wr_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) WriteRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7,x)
#define Rd_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) ReadRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7)
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_MASK       0x0380
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_ALIGN      0
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_BITS       3
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_SHIFT      7

/* BRPHY1_AFE_CTRL :: HPF_TRIM_OTHERS :: IDAC_fine_tune [06:04] */
#define Wr_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) WriteRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4,x)
#define Rd_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) ReadRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4)
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_MASK        0x0070
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_ALIGN       0
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_BITS        3
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_SHIFT       4

/* BRPHY1_AFE_CTRL :: HPF_TRIM_OTHERS :: SOFT_SEL_TRIM_HPF [03:03] */
#define Wr_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) WriteRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3,x)
#define Rd_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) ReadRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3)
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_MASK     0x0008
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_ALIGN    0
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_BITS     1
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_SHIFT    3

/* BRPHY1_AFE_CTRL :: HPF_TRIM_OTHERS :: TRIM_HPF [02:00] */
#define Wr_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) WriteRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0,x)
#define Rd_BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) ReadRegBits16(BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0)
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_MASK              0x0007
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_ALIGN             0
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_BITS              3
#define BRPHY1_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_SHIFT             0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: TX_EXTRA_CONFIG_0
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: TX_EXTRA_CONFIG_0 :: TX_EXTRA_CONFIG_15_0 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) WriteReg16(BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_0,x)
#define Rd_BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) ReadReg16(BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_0)
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_MASK 0xffff
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_ALIGN 0
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_BITS 16
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_SHIFT 0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: TX_EXTRA_CONFIG_1
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: TX_EXTRA_CONFIG_1 :: TX_EXTRA_CONFIG_31_16 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) WriteReg16(BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_1,x)
#define Rd_BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) ReadReg16(BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_1)
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_MASK 0xffff
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_ALIGN 0
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_BITS 16
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_SHIFT 0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: TX_EXTRA_CONFIG_2
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: TX_EXTRA_CONFIG_2 :: TX_EXTRA_CONFIG_47_32 [15:00] */
#define Wr_BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) WriteReg16(BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_2,x)
#define Rd_BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) ReadReg16(BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_2)
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_MASK 0xffff
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_ALIGN 0
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_BITS 16
#define BRPHY1_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_SHIFT 0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: TEMPSEN_OTHERS
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: TEMPSEN_OTHERS :: TEMPSEN [15:02] */
#define Wr_BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) WriteRegBits16(BRPHY1_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2,x)
#define Rd_BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) ReadRegBits16(BRPHY1_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2)
#define BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_MASK                0xfffc
#define BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_ALIGN               0
#define BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_BITS                14
#define BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_SHIFT               2

/* BRPHY1_AFE_CTRL :: TEMPSEN_OTHERS :: EXTRA_10BT [01:00] */
#define Wr_BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) WriteRegBits16(BRPHY1_AFE_CTRL_TEMPSEN_OTHERS,0x3,0,x)
#define Rd_BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) ReadRegBits16(BRPHY1_AFE_CTRL_TEMPSEN_OTHERS,0x3,0)
#define BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_MASK             0x0003
#define BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_ALIGN            0
#define BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_BITS             2
#define BRPHY1_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_SHIFT            0


/****************************************************************************
 * BRPHY1_AFE_CTRL :: FUTURE_RSV
 ***************************************************************************/
/* BRPHY1_AFE_CTRL :: FUTURE_RSV :: FUTURE_RSV [15:00] */
#define Wr_BRPHY1_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) WriteReg16(BRPHY1_AFE_CTRL_FUTURE_RSV,x)
#define Rd_BRPHY1_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) ReadReg16(BRPHY1_AFE_CTRL_FUTURE_RSV)
#define BRPHY1_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_MASK                 0xffff
#define BRPHY1_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_ALIGN                0
#define BRPHY1_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_BITS                 16
#define BRPHY1_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_ECD_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC0
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC0 :: RUN_IMMEDIATE [15:15] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x8000,15,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x8000,15)
#define BRPHY1_ECD_CTRL_EXPC0_RUN_IMMEDIATE_MASK                   0x8000
#define BRPHY1_ECD_CTRL_EXPC0_RUN_IMMEDIATE_ALIGN                  0
#define BRPHY1_ECD_CTRL_EXPC0_RUN_IMMEDIATE_BITS                   1
#define BRPHY1_ECD_CTRL_EXPC0_RUN_IMMEDIATE_SHIFT                  15

/* BRPHY1_ECD_CTRL :: EXPC0 :: RUN_AT_AUTONEG [14:14] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x4000,14,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x4000,14)
#define BRPHY1_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_MASK                  0x4000
#define BRPHY1_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_ALIGN                 0
#define BRPHY1_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_BITS                  1
#define BRPHY1_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_SHIFT                 14

/* BRPHY1_ECD_CTRL :: EXPC0 :: INTER_PAIR_SHORT_DIS [13:13] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x2000,13,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x2000,13)
#define BRPHY1_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_MASK            0x2000
#define BRPHY1_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_ALIGN           0
#define BRPHY1_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_BITS            1
#define BRPHY1_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_SHIFT           13

/* BRPHY1_ECD_CTRL :: EXPC0 :: BREAK_LINK [12:12] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_BREAK_LINK(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x1000,12,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_BREAK_LINK(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x1000,12)
#define BRPHY1_ECD_CTRL_EXPC0_BREAK_LINK_MASK                      0x1000
#define BRPHY1_ECD_CTRL_EXPC0_BREAK_LINK_ALIGN                     0
#define BRPHY1_ECD_CTRL_EXPC0_BREAK_LINK_BITS                      1
#define BRPHY1_ECD_CTRL_EXPC0_BREAK_LINK_SHIFT                     12

/* BRPHY1_ECD_CTRL :: EXPC0 :: CABLE_DIAG_STATUS [11:11] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x800,11,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x800,11)
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_MASK               0x0800
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_ALIGN              0
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_BITS               1
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_SHIFT              11

/* BRPHY1_ECD_CTRL :: EXPC0 :: CABLE_LEN_UNIT [10:10] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x400,10,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x400,10)
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_MASK                  0x0400
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_ALIGN                 0
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_BITS                  1
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_SHIFT                 10

/* BRPHY1_ECD_CTRL :: EXPC0 :: reserved0 [09:09] */
#define BRPHY1_ECD_CTRL_EXPC0_RESERVED0_MASK                       0x0200
#define BRPHY1_ECD_CTRL_EXPC0_RESERVED0_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPC0_RESERVED0_BITS                       1
#define BRPHY1_ECD_CTRL_EXPC0_RESERVED0_SHIFT                      9

/* BRPHY1_ECD_CTRL :: EXPC0 :: FAST_TIMER_ENABLE [08:08] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x100,8,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x100,8)
#define BRPHY1_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_MASK               0x0100
#define BRPHY1_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_ALIGN              0
#define BRPHY1_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_BITS               1
#define BRPHY1_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_SHIFT              8

/* BRPHY1_ECD_CTRL :: EXPC0 :: INTRPT_ENABLE [07:07] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x80,7,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x80,7)
#define BRPHY1_ECD_CTRL_EXPC0_INTRPT_ENABLE_MASK                   0x0080
#define BRPHY1_ECD_CTRL_EXPC0_INTRPT_ENABLE_ALIGN                  0
#define BRPHY1_ECD_CTRL_EXPC0_INTRPT_ENABLE_BITS                   1
#define BRPHY1_ECD_CTRL_EXPC0_INTRPT_ENABLE_SHIFT                  7

/* BRPHY1_ECD_CTRL :: EXPC0 :: STOP_PLL_CLK [06:06] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x40,6,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x40,6)
#define BRPHY1_ECD_CTRL_EXPC0_STOP_PLL_CLK_MASK                    0x0040
#define BRPHY1_ECD_CTRL_EXPC0_STOP_PLL_CLK_ALIGN                   0
#define BRPHY1_ECD_CTRL_EXPC0_STOP_PLL_CLK_BITS                    1
#define BRPHY1_ECD_CTRL_EXPC0_STOP_PLL_CLK_SHIFT                   6

/* BRPHY1_ECD_CTRL :: EXPC0 :: reserved1 [05:04] */
#define BRPHY1_ECD_CTRL_EXPC0_RESERVED1_MASK                       0x0030
#define BRPHY1_ECD_CTRL_EXPC0_RESERVED1_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPC0_RESERVED1_BITS                       2
#define BRPHY1_ECD_CTRL_EXPC0_RESERVED1_SHIFT                      4

/* BRPHY1_ECD_CTRL :: EXPC0 :: INVALID_RESULT [03:03] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_INVALID_RESULT(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x8,3,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_INVALID_RESULT(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x8,3)
#define BRPHY1_ECD_CTRL_EXPC0_INVALID_RESULT_MASK                  0x0008
#define BRPHY1_ECD_CTRL_EXPC0_INVALID_RESULT_ALIGN                 0
#define BRPHY1_ECD_CTRL_EXPC0_INVALID_RESULT_BITS                  1
#define BRPHY1_ECD_CTRL_EXPC0_INVALID_RESULT_SHIFT                 3

/* BRPHY1_ECD_CTRL :: EXPC0 :: CABLE_DIAG_EXE [02:02] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x4,2,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x4,2)
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_MASK                  0x0004
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_ALIGN                 0
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_BITS                  1
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_SHIFT                 2

/* BRPHY1_ECD_CTRL :: EXPC0 :: AUTO_RUN_FOR_BROKEN_ANG [01:01] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x2,1,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x2,1)
#define BRPHY1_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_MASK         0x0002
#define BRPHY1_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_ALIGN        0
#define BRPHY1_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_BITS         1
#define BRPHY1_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_SHIFT        1

/* BRPHY1_ECD_CTRL :: EXPC0 :: CABLE_TYPE [00:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC0_CABLE_TYPE(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x1,0,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC0_CABLE_TYPE(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC0,0x1,0)
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_TYPE_MASK                      0x0001
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_TYPE_ALIGN                     0
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_TYPE_BITS                      1
#define BRPHY1_ECD_CTRL_EXPC0_CABLE_TYPE_SHIFT                     0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC1
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC1 :: PA_CD_CODE [15:12] */
#define Wr_BRPHY1_ECD_CTRL_EXPC1_PA_CD_CODE(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC1,0xf000,12,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC1_PA_CD_CODE(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC1,0xf000,12)
#define BRPHY1_ECD_CTRL_EXPC1_PA_CD_CODE_MASK                      0xf000
#define BRPHY1_ECD_CTRL_EXPC1_PA_CD_CODE_ALIGN                     0
#define BRPHY1_ECD_CTRL_EXPC1_PA_CD_CODE_BITS                      4
#define BRPHY1_ECD_CTRL_EXPC1_PA_CD_CODE_SHIFT                     12

/* BRPHY1_ECD_CTRL :: EXPC1 :: PB_CD_CODE [11:08] */
#define Wr_BRPHY1_ECD_CTRL_EXPC1_PB_CD_CODE(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC1,0xf00,8,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC1_PB_CD_CODE(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC1,0xf00,8)
#define BRPHY1_ECD_CTRL_EXPC1_PB_CD_CODE_MASK                      0x0f00
#define BRPHY1_ECD_CTRL_EXPC1_PB_CD_CODE_ALIGN                     0
#define BRPHY1_ECD_CTRL_EXPC1_PB_CD_CODE_BITS                      4
#define BRPHY1_ECD_CTRL_EXPC1_PB_CD_CODE_SHIFT                     8

/* BRPHY1_ECD_CTRL :: EXPC1 :: PC_CD_CODE [07:04] */
#define Wr_BRPHY1_ECD_CTRL_EXPC1_PC_CD_CODE(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC1,0xf0,4,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC1_PC_CD_CODE(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC1,0xf0,4)
#define BRPHY1_ECD_CTRL_EXPC1_PC_CD_CODE_MASK                      0x00f0
#define BRPHY1_ECD_CTRL_EXPC1_PC_CD_CODE_ALIGN                     0
#define BRPHY1_ECD_CTRL_EXPC1_PC_CD_CODE_BITS                      4
#define BRPHY1_ECD_CTRL_EXPC1_PC_CD_CODE_SHIFT                     4

/* BRPHY1_ECD_CTRL :: EXPC1 :: PD_CD_CODE [03:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC1_PD_CD_CODE(x) WriteRegBits16(BRPHY1_ECD_CTRL_EXPC1,0xf,0,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC1_PD_CD_CODE(x) ReadRegBits16(BRPHY1_ECD_CTRL_EXPC1,0xf,0)
#define BRPHY1_ECD_CTRL_EXPC1_PD_CD_CODE_MASK                      0x000f
#define BRPHY1_ECD_CTRL_EXPC1_PD_CD_CODE_ALIGN                     0
#define BRPHY1_ECD_CTRL_EXPC1_PD_CD_CODE_BITS                      4
#define BRPHY1_ECD_CTRL_EXPC1_PD_CD_CODE_SHIFT                     0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC2
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC2 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) WriteReg16(BRPHY1_ECD_CTRL_EXPC2,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) ReadReg16(BRPHY1_ECD_CTRL_EXPC2)
#define BRPHY1_ECD_CTRL_EXPC2_LENGTH_INDICATION_MASK               0xffff
#define BRPHY1_ECD_CTRL_EXPC2_LENGTH_INDICATION_ALIGN              0
#define BRPHY1_ECD_CTRL_EXPC2_LENGTH_INDICATION_BITS               16
#define BRPHY1_ECD_CTRL_EXPC2_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC3
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC3 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) WriteReg16(BRPHY1_ECD_CTRL_EXPC3,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) ReadReg16(BRPHY1_ECD_CTRL_EXPC3)
#define BRPHY1_ECD_CTRL_EXPC3_LENGTH_INDICATION_MASK               0xffff
#define BRPHY1_ECD_CTRL_EXPC3_LENGTH_INDICATION_ALIGN              0
#define BRPHY1_ECD_CTRL_EXPC3_LENGTH_INDICATION_BITS               16
#define BRPHY1_ECD_CTRL_EXPC3_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC4
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC4 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) WriteReg16(BRPHY1_ECD_CTRL_EXPC4,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) ReadReg16(BRPHY1_ECD_CTRL_EXPC4)
#define BRPHY1_ECD_CTRL_EXPC4_LENGTH_INDICATION_MASK               0xffff
#define BRPHY1_ECD_CTRL_EXPC4_LENGTH_INDICATION_ALIGN              0
#define BRPHY1_ECD_CTRL_EXPC4_LENGTH_INDICATION_BITS               16
#define BRPHY1_ECD_CTRL_EXPC4_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC5
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC5 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) WriteReg16(BRPHY1_ECD_CTRL_EXPC5,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) ReadReg16(BRPHY1_ECD_CTRL_EXPC5)
#define BRPHY1_ECD_CTRL_EXPC5_LENGTH_INDICATION_MASK               0xffff
#define BRPHY1_ECD_CTRL_EXPC5_LENGTH_INDICATION_ALIGN              0
#define BRPHY1_ECD_CTRL_EXPC5_LENGTH_INDICATION_BITS               16
#define BRPHY1_ECD_CTRL_EXPC5_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC6
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC6 :: F_COUNT_0 [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC6_F_COUNT_0(x) WriteReg16(BRPHY1_ECD_CTRL_EXPC6,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC6_F_COUNT_0(x) ReadReg16(BRPHY1_ECD_CTRL_EXPC6)
#define BRPHY1_ECD_CTRL_EXPC6_F_COUNT_0_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPC6_F_COUNT_0_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPC6_F_COUNT_0_BITS                       16
#define BRPHY1_ECD_CTRL_EXPC6_F_COUNT_0_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC7
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC7 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC7_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPC7,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC7_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPC7)
#define BRPHY1_ECD_CTRL_EXPC7_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPC7_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPC7_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPC7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC8
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC8 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC8_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPC8,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC8_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPC8)
#define BRPHY1_ECD_CTRL_EXPC8_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPC8_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPC8_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPC8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPC9
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPC9 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPC9_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPC9,x)
#define Rd_BRPHY1_ECD_CTRL_EXPC9_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPC9)
#define BRPHY1_ECD_CTRL_EXPC9_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPC9_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPC9_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPC9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPCA
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPCA :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPCA_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPCA,x)
#define Rd_BRPHY1_ECD_CTRL_EXPCA_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPCA)
#define BRPHY1_ECD_CTRL_EXPCA_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPCA_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPCA_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPCA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPCB
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPCB :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPCB_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPCB,x)
#define Rd_BRPHY1_ECD_CTRL_EXPCB_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPCB)
#define BRPHY1_ECD_CTRL_EXPCB_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPCB_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPCB_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPCB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPCC
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPCC :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPCC_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPCC,x)
#define Rd_BRPHY1_ECD_CTRL_EXPCC_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPCC)
#define BRPHY1_ECD_CTRL_EXPCC_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPCC_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPCC_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPCC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPCD
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPCD :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPCD_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPCD,x)
#define Rd_BRPHY1_ECD_CTRL_EXPCD_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPCD)
#define BRPHY1_ECD_CTRL_EXPCD_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPCD_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPCD_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPCD_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPCE
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPCE :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPCE_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPCE,x)
#define Rd_BRPHY1_ECD_CTRL_EXPCE_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPCE)
#define BRPHY1_ECD_CTRL_EXPCE_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPCE_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPCE_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPCE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPCF
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPCF :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPCF_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPCF,x)
#define Rd_BRPHY1_ECD_CTRL_EXPCF_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPCF)
#define BRPHY1_ECD_CTRL_EXPCF_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPCF_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPCF_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPCF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE0
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE0 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE0_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE0,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE0_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE0)
#define BRPHY1_ECD_CTRL_EXPE0_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE0_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE0_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE0_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE1
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE1 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE1_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE1,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE1_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE1)
#define BRPHY1_ECD_CTRL_EXPE1_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE1_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE1_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE1_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE2
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE2 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE2_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE2,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE2_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE2)
#define BRPHY1_ECD_CTRL_EXPE2_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE2_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE2_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE2_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE3
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE3 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE3_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE3,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE3_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE3)
#define BRPHY1_ECD_CTRL_EXPE3_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE3_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE3_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE3_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE4
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE4 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE4_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE4,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE4_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE4)
#define BRPHY1_ECD_CTRL_EXPE4_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE4_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE4_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE4_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE5
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE5 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE5_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE5,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE5_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE5)
#define BRPHY1_ECD_CTRL_EXPE5_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE5_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE5_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE5_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE6
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE6 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE6_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE6,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE6_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE6)
#define BRPHY1_ECD_CTRL_EXPE6_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE6_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE6_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE6_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE7
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE7 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE7_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE7,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE7_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE7)
#define BRPHY1_ECD_CTRL_EXPE7_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE7_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE7_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE8
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE8 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE8_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE8,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE8_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE8)
#define BRPHY1_ECD_CTRL_EXPE8_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE8_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE8_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPE9
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPE9 :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPE9_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPE9,x)
#define Rd_BRPHY1_ECD_CTRL_EXPE9_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPE9)
#define BRPHY1_ECD_CTRL_EXPE9_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPE9_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPE9_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPE9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPEA
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPEA :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPEA_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPEA,x)
#define Rd_BRPHY1_ECD_CTRL_EXPEA_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPEA)
#define BRPHY1_ECD_CTRL_EXPEA_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPEA_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPEA_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPEA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPEB
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPEB :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPEB_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPEB,x)
#define Rd_BRPHY1_ECD_CTRL_EXPEB_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPEB)
#define BRPHY1_ECD_CTRL_EXPEB_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPEB_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPEB_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPEB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPEC
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPEC :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPEC_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPEC,x)
#define Rd_BRPHY1_ECD_CTRL_EXPEC_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPEC)
#define BRPHY1_ECD_CTRL_EXPEC_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPEC_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPEC_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPEC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPED
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPED :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPED_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPED,x)
#define Rd_BRPHY1_ECD_CTRL_EXPED_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPED)
#define BRPHY1_ECD_CTRL_EXPED_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPED_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPED_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPED_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPEE
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPEE :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPEE_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPEE,x)
#define Rd_BRPHY1_ECD_CTRL_EXPEE_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPEE)
#define BRPHY1_ECD_CTRL_EXPEE_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPEE_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPEE_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPEE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY1_ECD_CTRL :: EXPEF
 ***************************************************************************/
/* BRPHY1_ECD_CTRL :: EXPEF :: UNDEFINED [15:00] */
#define Wr_BRPHY1_ECD_CTRL_EXPEF_UNDEFINED(x) WriteReg16(BRPHY1_ECD_CTRL_EXPEF,x)
#define Rd_BRPHY1_ECD_CTRL_EXPEF_UNDEFINED(x) ReadReg16(BRPHY1_ECD_CTRL_EXPEF)
#define BRPHY1_ECD_CTRL_EXPEF_UNDEFINED_MASK                       0xffff
#define BRPHY1_ECD_CTRL_EXPEF_UNDEFINED_ALIGN                      0
#define BRPHY1_ECD_CTRL_EXPEF_UNDEFINED_BITS                       16
#define BRPHY1_ECD_CTRL_EXPEF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_BR_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP90
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP90 :: DIG_HPF_EN [15:15] */
#define Wr_BRPHY1_BR_CTRL_EXP90_DIG_HPF_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP90,0x8000,15,x)
#define Rd_BRPHY1_BR_CTRL_EXP90_DIG_HPF_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP90,0x8000,15)
#define BRPHY1_BR_CTRL_EXP90_DIG_HPF_EN_MASK                       0x8000
#define BRPHY1_BR_CTRL_EXP90_DIG_HPF_EN_ALIGN                      0
#define BRPHY1_BR_CTRL_EXP90_DIG_HPF_EN_BITS                       1
#define BRPHY1_BR_CTRL_EXP90_DIG_HPF_EN_SHIFT                      15

/* BRPHY1_BR_CTRL :: EXP90 :: BR_SCR_STATUS [14:13] */
#define Wr_BRPHY1_BR_CTRL_EXP90_BR_SCR_STATUS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP90,0x6000,13,x)
#define Rd_BRPHY1_BR_CTRL_EXP90_BR_SCR_STATUS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP90,0x6000,13)
#define BRPHY1_BR_CTRL_EXP90_BR_SCR_STATUS_MASK                    0x6000
#define BRPHY1_BR_CTRL_EXP90_BR_SCR_STATUS_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP90_BR_SCR_STATUS_BITS                    2
#define BRPHY1_BR_CTRL_EXP90_BR_SCR_STATUS_SHIFT                   13

/* BRPHY1_BR_CTRL :: EXP90 :: BR_ALIGN_STATE [12:10] */
#define Wr_BRPHY1_BR_CTRL_EXP90_BR_ALIGN_STATE(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP90,0x1c00,10,x)
#define Rd_BRPHY1_BR_CTRL_EXP90_BR_ALIGN_STATE(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP90,0x1c00,10)
#define BRPHY1_BR_CTRL_EXP90_BR_ALIGN_STATE_MASK                   0x1c00
#define BRPHY1_BR_CTRL_EXP90_BR_ALIGN_STATE_ALIGN                  0
#define BRPHY1_BR_CTRL_EXP90_BR_ALIGN_STATE_BITS                   3
#define BRPHY1_BR_CTRL_EXP90_BR_ALIGN_STATE_SHIFT                  10

/* BRPHY1_BR_CTRL :: EXP90 :: BR_RX_STATE [09:06] */
#define Wr_BRPHY1_BR_CTRL_EXP90_BR_RX_STATE(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP90,0x3c0,6,x)
#define Rd_BRPHY1_BR_CTRL_EXP90_BR_RX_STATE(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP90,0x3c0,6)
#define BRPHY1_BR_CTRL_EXP90_BR_RX_STATE_MASK                      0x03c0
#define BRPHY1_BR_CTRL_EXP90_BR_RX_STATE_ALIGN                     0
#define BRPHY1_BR_CTRL_EXP90_BR_RX_STATE_BITS                      4
#define BRPHY1_BR_CTRL_EXP90_BR_RX_STATE_SHIFT                     6

/* BRPHY1_BR_CTRL :: EXP90 :: BR_PCS_STATE [05:02] */
#define Wr_BRPHY1_BR_CTRL_EXP90_BR_PCS_STATE(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP90,0x3c,2,x)
#define Rd_BRPHY1_BR_CTRL_EXP90_BR_PCS_STATE(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP90,0x3c,2)
#define BRPHY1_BR_CTRL_EXP90_BR_PCS_STATE_MASK                     0x003c
#define BRPHY1_BR_CTRL_EXP90_BR_PCS_STATE_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP90_BR_PCS_STATE_BITS                     4
#define BRPHY1_BR_CTRL_EXP90_BR_PCS_STATE_SHIFT                    2

/* BRPHY1_BR_CTRL :: EXP90 :: BR_FORCE_LINK_CTL [01:01] */
#define Wr_BRPHY1_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP90,0x2,1,x)
#define Rd_BRPHY1_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP90,0x2,1)
#define BRPHY1_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_MASK                0x0002
#define BRPHY1_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_ALIGN               0
#define BRPHY1_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_BITS                1
#define BRPHY1_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_SHIFT               1

/* BRPHY1_BR_CTRL :: EXP90 :: BR_EN [00:00] */
#define Wr_BRPHY1_BR_CTRL_EXP90_BR_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP90,0x1,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP90_BR_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP90,0x1,0)
#define BRPHY1_BR_CTRL_EXP90_BR_EN_MASK                            0x0001
#define BRPHY1_BR_CTRL_EXP90_BR_EN_ALIGN                           0
#define BRPHY1_BR_CTRL_EXP90_BR_EN_BITS                            1
#define BRPHY1_BR_CTRL_EXP90_BR_EN_SHIFT                           0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP91
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP91 :: DIG_HPF_OV [15:15] */
#define Wr_BRPHY1_BR_CTRL_EXP91_DIG_HPF_OV(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0x8000,15,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_DIG_HPF_OV(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0x8000,15)
#define BRPHY1_BR_CTRL_EXP91_DIG_HPF_OV_MASK                       0x8000
#define BRPHY1_BR_CTRL_EXP91_DIG_HPF_OV_ALIGN                      0
#define BRPHY1_BR_CTRL_EXP91_DIG_HPF_OV_BITS                       1
#define BRPHY1_BR_CTRL_EXP91_DIG_HPF_OV_SHIFT                      15

/* BRPHY1_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV [14:14] */
#define Wr_BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0x4000,14,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0x4000,14)
#define BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_MASK               0x4000
#define BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_ALIGN              0
#define BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_BITS               1
#define BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_SHIFT              14

/* BRPHY1_BR_CTRL :: EXP91 :: INV_LRE_GMII_TXC [13:13] */
#define Wr_BRPHY1_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0x2000,13,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0x2000,13)
#define BRPHY1_BR_CTRL_EXP91_INV_LRE_GMII_TXC_MASK                 0x2000
#define BRPHY1_BR_CTRL_EXP91_INV_LRE_GMII_TXC_ALIGN                0
#define BRPHY1_BR_CTRL_EXP91_INV_LRE_GMII_TXC_BITS                 1
#define BRPHY1_BR_CTRL_EXP91_INV_LRE_GMII_TXC_SHIFT                13

/* BRPHY1_BR_CTRL :: EXP91 :: AGC_AUTOSTAGING_DIS [12:12] */
#define Wr_BRPHY1_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0x1000,12,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0x1000,12)
#define BRPHY1_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_MASK              0x1000
#define BRPHY1_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_ALIGN             0
#define BRPHY1_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_BITS              1
#define BRPHY1_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_SHIFT             12

/* BRPHY1_BR_CTRL :: EXP91 :: BRPGA [11:09] */
#define Wr_BRPHY1_BR_CTRL_EXP91_BRPGA(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0xe00,9,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_BRPGA(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0xe00,9)
#define BRPHY1_BR_CTRL_EXP91_BRPGA_MASK                            0x0e00
#define BRPHY1_BR_CTRL_EXP91_BRPGA_ALIGN                           0
#define BRPHY1_BR_CTRL_EXP91_BRPGA_BITS                            3
#define BRPHY1_BR_CTRL_EXP91_BRPGA_SHIFT                           9

/* BRPHY1_BR_CTRL :: EXP91 :: BRCONFIG [08:04] */
#define Wr_BRPHY1_BR_CTRL_EXP91_BRCONFIG(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0x1f0,4,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_BRCONFIG(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0x1f0,4)
#define BRPHY1_BR_CTRL_EXP91_BRCONFIG_MASK                         0x01f0
#define BRPHY1_BR_CTRL_EXP91_BRCONFIG_ALIGN                        0
#define BRPHY1_BR_CTRL_EXP91_BRCONFIG_BITS                         5
#define BRPHY1_BR_CTRL_EXP91_BRCONFIG_SHIFT                        4

/* BRPHY1_BR_CTRL :: EXP91 :: ACQP_EN_ECO_DIS [03:03] */
#define Wr_BRPHY1_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0x8,3,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0x8,3)
#define BRPHY1_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_MASK                  0x0008
#define BRPHY1_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_ALIGN                 0
#define BRPHY1_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_BITS                  1
#define BRPHY1_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_SHIFT                 3

/* BRPHY1_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV_VAL [02:02] */
#define Wr_BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0x4,2,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0x4,2)
#define BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_MASK           0x0004
#define BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_ALIGN          0
#define BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_BITS           1
#define BRPHY1_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_SHIFT          2

/* BRPHY1_BR_CTRL :: EXP91 :: TXSCR_ZERO_SEED [01:01] */
#define Wr_BRPHY1_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0x2,1,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0x2,1)
#define BRPHY1_BR_CTRL_EXP91_TXSCR_ZERO_SEED_MASK                  0x0002
#define BRPHY1_BR_CTRL_EXP91_TXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY1_BR_CTRL_EXP91_TXSCR_ZERO_SEED_BITS                  1
#define BRPHY1_BR_CTRL_EXP91_TXSCR_ZERO_SEED_SHIFT                 1

/* BRPHY1_BR_CTRL :: EXP91 :: RXSCR_ZERO_SEED [00:00] */
#define Wr_BRPHY1_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP91,0x1,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP91,0x1,0)
#define BRPHY1_BR_CTRL_EXP91_RXSCR_ZERO_SEED_MASK                  0x0001
#define BRPHY1_BR_CTRL_EXP91_RXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY1_BR_CTRL_EXP91_RXSCR_ZERO_SEED_BITS                  1
#define BRPHY1_BR_CTRL_EXP91_RXSCR_ZERO_SEED_SHIFT                 0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP92
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP92 :: DLLCONV_OV_EN [15:15] */
#define Wr_BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x8000,15,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x8000,15)
#define BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_EN_MASK                    0x8000
#define BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_EN_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_EN_BITS                    1
#define BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_EN_SHIFT                   15

/* BRPHY1_BR_CTRL :: EXP92 :: DLLCONV_OV_VAL [14:14] */
#define Wr_BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x4000,14,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x4000,14)
#define BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_VAL_MASK                   0x4000
#define BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_VAL_ALIGN                  0
#define BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_VAL_BITS                   1
#define BRPHY1_BR_CTRL_EXP92_DLLCONV_OV_VAL_SHIFT                  14

/* BRPHY1_BR_CTRL :: EXP92 :: BR_SLAVE_POL_COR_EN [13:13] */
#define Wr_BRPHY1_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x2000,13,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x2000,13)
#define BRPHY1_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_MASK              0x2000
#define BRPHY1_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_ALIGN             0
#define BRPHY1_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_BITS              1
#define BRPHY1_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_SHIFT             13

/* BRPHY1_BR_CTRL :: EXP92 :: BR_EDGE_RATE_SEL [12:11] */
#define Wr_BRPHY1_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x1800,11,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x1800,11)
#define BRPHY1_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_MASK                 0x1800
#define BRPHY1_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_ALIGN                0
#define BRPHY1_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_BITS                 2
#define BRPHY1_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_SHIFT                11

/* BRPHY1_BR_CTRL :: EXP92 :: BR_PCS_RRNOK_POL_EN [10:10] */
#define Wr_BRPHY1_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x400,10,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x400,10)
#define BRPHY1_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_MASK              0x0400
#define BRPHY1_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_ALIGN             0
#define BRPHY1_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_BITS              1
#define BRPHY1_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_SHIFT             10

/* BRPHY1_BR_CTRL :: EXP92 :: LDS_LNK_CHK_ECO_DIS [09:09] */
#define Wr_BRPHY1_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x200,9,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x200,9)
#define BRPHY1_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_MASK              0x0200
#define BRPHY1_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_ALIGN             0
#define BRPHY1_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_BITS              1
#define BRPHY1_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_SHIFT             9

/* BRPHY1_BR_CTRL :: EXP92 :: BR_PCS_POL_EN [08:08] */
#define Wr_BRPHY1_BR_CTRL_EXP92_BR_PCS_POL_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x100,8,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_BR_PCS_POL_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x100,8)
#define BRPHY1_BR_CTRL_EXP92_BR_PCS_POL_EN_MASK                    0x0100
#define BRPHY1_BR_CTRL_EXP92_BR_PCS_POL_EN_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP92_BR_PCS_POL_EN_BITS                    1
#define BRPHY1_BR_CTRL_EXP92_BR_PCS_POL_EN_SHIFT                   8

/* BRPHY1_BR_CTRL :: EXP92 :: JAB_MON_DIS [07:07] */
#define Wr_BRPHY1_BR_CTRL_EXP92_JAB_MON_DIS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x80,7,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_JAB_MON_DIS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x80,7)
#define BRPHY1_BR_CTRL_EXP92_JAB_MON_DIS_MASK                      0x0080
#define BRPHY1_BR_CTRL_EXP92_JAB_MON_DIS_ALIGN                     0
#define BRPHY1_BR_CTRL_EXP92_JAB_MON_DIS_BITS                      1
#define BRPHY1_BR_CTRL_EXP92_JAB_MON_DIS_SHIFT                     7

/* BRPHY1_BR_CTRL :: EXP92 :: BR_AGCSID_TMR_EN [06:06] */
#define Wr_BRPHY1_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x40,6,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x40,6)
#define BRPHY1_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_MASK                 0x0040
#define BRPHY1_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_ALIGN                0
#define BRPHY1_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_BITS                 1
#define BRPHY1_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_SHIFT                6

/* BRPHY1_BR_CTRL :: EXP92 :: BR_SYM_XSCR_EN [05:05] */
#define Wr_BRPHY1_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x20,5,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x20,5)
#define BRPHY1_BR_CTRL_EXP92_BR_SYM_XSCR_EN_MASK                   0x0020
#define BRPHY1_BR_CTRL_EXP92_BR_SYM_XSCR_EN_ALIGN                  0
#define BRPHY1_BR_CTRL_EXP92_BR_SYM_XSCR_EN_BITS                   1
#define BRPHY1_BR_CTRL_EXP92_BR_SYM_XSCR_EN_SHIFT                  5

/* BRPHY1_BR_CTRL :: EXP92 :: CHK_DELIMITER [04:04] */
#define Wr_BRPHY1_BR_CTRL_EXP92_CHK_DELIMITER(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x10,4,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_CHK_DELIMITER(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x10,4)
#define BRPHY1_BR_CTRL_EXP92_CHK_DELIMITER_MASK                    0x0010
#define BRPHY1_BR_CTRL_EXP92_CHK_DELIMITER_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP92_CHK_DELIMITER_BITS                    1
#define BRPHY1_BR_CTRL_EXP92_CHK_DELIMITER_SHIFT                   4

/* BRPHY1_BR_CTRL :: EXP92 :: TX_READ_DLY [03:02] */
#define Wr_BRPHY1_BR_CTRL_EXP92_TX_READ_DLY(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0xc,2,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_TX_READ_DLY(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0xc,2)
#define BRPHY1_BR_CTRL_EXP92_TX_READ_DLY_MASK                      0x000c
#define BRPHY1_BR_CTRL_EXP92_TX_READ_DLY_ALIGN                     0
#define BRPHY1_BR_CTRL_EXP92_TX_READ_DLY_BITS                      2
#define BRPHY1_BR_CTRL_EXP92_TX_READ_DLY_SHIFT                     2

/* BRPHY1_BR_CTRL :: EXP92 :: RX_READ_DLY [01:00] */
#define Wr_BRPHY1_BR_CTRL_EXP92_RX_READ_DLY(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP92,0x3,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP92_RX_READ_DLY(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP92,0x3,0)
#define BRPHY1_BR_CTRL_EXP92_RX_READ_DLY_MASK                      0x0003
#define BRPHY1_BR_CTRL_EXP92_RX_READ_DLY_ALIGN                     0
#define BRPHY1_BR_CTRL_EXP92_RX_READ_DLY_BITS                      2
#define BRPHY1_BR_CTRL_EXP92_RX_READ_DLY_SHIFT                     0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP93
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP93 :: LDS_CAP_DOWNGRADE_DIS [15:15] */
#define Wr_BRPHY1_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP93,0x8000,15,x)
#define Rd_BRPHY1_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP93,0x8000,15)
#define BRPHY1_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_MASK            0x8000
#define BRPHY1_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_ALIGN           0
#define BRPHY1_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_BITS            1
#define BRPHY1_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_SHIFT           15

/* BRPHY1_BR_CTRL :: EXP93 :: LDS_REORDER_DIS [14:14] */
#define Wr_BRPHY1_BR_CTRL_EXP93_LDS_REORDER_DIS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP93,0x4000,14,x)
#define Rd_BRPHY1_BR_CTRL_EXP93_LDS_REORDER_DIS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP93,0x4000,14)
#define BRPHY1_BR_CTRL_EXP93_LDS_REORDER_DIS_MASK                  0x4000
#define BRPHY1_BR_CTRL_EXP93_LDS_REORDER_DIS_ALIGN                 0
#define BRPHY1_BR_CTRL_EXP93_LDS_REORDER_DIS_BITS                  1
#define BRPHY1_BR_CTRL_EXP93_LDS_REORDER_DIS_SHIFT                 14

/* BRPHY1_BR_CTRL :: EXP93 :: LDS_SIM [13:13] */
#define Wr_BRPHY1_BR_CTRL_EXP93_LDS_SIM(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP93,0x2000,13,x)
#define Rd_BRPHY1_BR_CTRL_EXP93_LDS_SIM(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP93,0x2000,13)
#define BRPHY1_BR_CTRL_EXP93_LDS_SIM_MASK                          0x2000
#define BRPHY1_BR_CTRL_EXP93_LDS_SIM_ALIGN                         0
#define BRPHY1_BR_CTRL_EXP93_LDS_SIM_BITS                          1
#define BRPHY1_BR_CTRL_EXP93_LDS_SIM_SHIFT                         13

/* BRPHY1_BR_CTRL :: EXP93 :: LDS_SCR_ON [12:12] */
#define Wr_BRPHY1_BR_CTRL_EXP93_LDS_SCR_ON(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP93,0x1000,12,x)
#define Rd_BRPHY1_BR_CTRL_EXP93_LDS_SCR_ON(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP93,0x1000,12)
#define BRPHY1_BR_CTRL_EXP93_LDS_SCR_ON_MASK                       0x1000
#define BRPHY1_BR_CTRL_EXP93_LDS_SCR_ON_ALIGN                      0
#define BRPHY1_BR_CTRL_EXP93_LDS_SCR_ON_BITS                       1
#define BRPHY1_BR_CTRL_EXP93_LDS_SCR_ON_SHIFT                      12

/* BRPHY1_BR_CTRL :: EXP93 :: LDS_PHASE_BYP [11:11] */
#define Wr_BRPHY1_BR_CTRL_EXP93_LDS_PHASE_BYP(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP93,0x800,11,x)
#define Rd_BRPHY1_BR_CTRL_EXP93_LDS_PHASE_BYP(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP93,0x800,11)
#define BRPHY1_BR_CTRL_EXP93_LDS_PHASE_BYP_MASK                    0x0800
#define BRPHY1_BR_CTRL_EXP93_LDS_PHASE_BYP_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP93_LDS_PHASE_BYP_BITS                    1
#define BRPHY1_BR_CTRL_EXP93_LDS_PHASE_BYP_SHIFT                   11

/* BRPHY1_BR_CTRL :: EXP93 :: LDS_PHASE_INIT [10:08] */
#define Wr_BRPHY1_BR_CTRL_EXP93_LDS_PHASE_INIT(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP93,0x700,8,x)
#define Rd_BRPHY1_BR_CTRL_EXP93_LDS_PHASE_INIT(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP93,0x700,8)
#define BRPHY1_BR_CTRL_EXP93_LDS_PHASE_INIT_MASK                   0x0700
#define BRPHY1_BR_CTRL_EXP93_LDS_PHASE_INIT_ALIGN                  0
#define BRPHY1_BR_CTRL_EXP93_LDS_PHASE_INIT_BITS                   3
#define BRPHY1_BR_CTRL_EXP93_LDS_PHASE_INIT_SHIFT                  8

/* BRPHY1_BR_CTRL :: EXP93 :: LDS_PEAK_THR [07:00] */
#define Wr_BRPHY1_BR_CTRL_EXP93_LDS_PEAK_THR(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP93,0xff,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP93_LDS_PEAK_THR(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP93,0xff,0)
#define BRPHY1_BR_CTRL_EXP93_LDS_PEAK_THR_MASK                     0x00ff
#define BRPHY1_BR_CTRL_EXP93_LDS_PEAK_THR_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP93_LDS_PEAK_THR_BITS                     8
#define BRPHY1_BR_CTRL_EXP93_LDS_PEAK_THR_SHIFT                    0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP94
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP94 :: LDS_LEN_THR1 [15:08] */
#define Wr_BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR1(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP94,0xff00,8,x)
#define Rd_BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR1(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP94,0xff00,8)
#define BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR1_MASK                     0xff00
#define BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR1_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR1_BITS                     8
#define BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR1_SHIFT                    8

/* BRPHY1_BR_CTRL :: EXP94 :: LDS_LEN_THR0 [07:00] */
#define Wr_BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR0(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP94,0xff,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR0(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP94,0xff,0)
#define BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR0_MASK                     0x00ff
#define BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR0_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR0_BITS                     8
#define BRPHY1_BR_CTRL_EXP94_LDS_LEN_THR0_SHIFT                    0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP95
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP95 :: LDS_LEN_THR3 [15:08] */
#define Wr_BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR3(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP95,0xff00,8,x)
#define Rd_BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR3(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP95,0xff00,8)
#define BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR3_MASK                     0xff00
#define BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR3_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR3_BITS                     8
#define BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR3_SHIFT                    8

/* BRPHY1_BR_CTRL :: EXP95 :: LDS_LEN_THR2 [07:00] */
#define Wr_BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR2(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP95,0xff,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR2(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP95,0xff,0)
#define BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR2_MASK                     0x00ff
#define BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR2_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR2_BITS                     8
#define BRPHY1_BR_CTRL_EXP95_LDS_LEN_THR2_SHIFT                    0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP96
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP96 :: LDS_TONE_FREQ [15:15] */
#define Wr_BRPHY1_BR_CTRL_EXP96_LDS_TONE_FREQ(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP96,0x8000,15,x)
#define Rd_BRPHY1_BR_CTRL_EXP96_LDS_TONE_FREQ(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP96,0x8000,15)
#define BRPHY1_BR_CTRL_EXP96_LDS_TONE_FREQ_MASK                    0x8000
#define BRPHY1_BR_CTRL_EXP96_LDS_TONE_FREQ_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP96_LDS_TONE_FREQ_BITS                    1
#define BRPHY1_BR_CTRL_EXP96_LDS_TONE_FREQ_SHIFT                   15

/* BRPHY1_BR_CTRL :: EXP96 :: LDS_EXT_AB_DWNGRD [14:14] */
#define Wr_BRPHY1_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP96,0x4000,14,x)
#define Rd_BRPHY1_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP96,0x4000,14)
#define BRPHY1_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_MASK                0x4000
#define BRPHY1_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_ALIGN               0
#define BRPHY1_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_BITS                1
#define BRPHY1_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_SHIFT               14

/* BRPHY1_BR_CTRL :: EXP96 :: LDS_SCAN_FSM [13:12] */
#define Wr_BRPHY1_BR_CTRL_EXP96_LDS_SCAN_FSM(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP96,0x3000,12,x)
#define Rd_BRPHY1_BR_CTRL_EXP96_LDS_SCAN_FSM(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP96,0x3000,12)
#define BRPHY1_BR_CTRL_EXP96_LDS_SCAN_FSM_MASK                     0x3000
#define BRPHY1_BR_CTRL_EXP96_LDS_SCAN_FSM_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP96_LDS_SCAN_FSM_BITS                     2
#define BRPHY1_BR_CTRL_EXP96_LDS_SCAN_FSM_SHIFT                    12

/* BRPHY1_BR_CTRL :: EXP96 :: CUR_LOC_FNUM [11:04] */
#define Wr_BRPHY1_BR_CTRL_EXP96_CUR_LOC_FNUM(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP96,0xff0,4,x)
#define Rd_BRPHY1_BR_CTRL_EXP96_CUR_LOC_FNUM(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP96,0xff0,4)
#define BRPHY1_BR_CTRL_EXP96_CUR_LOC_FNUM_MASK                     0x0ff0
#define BRPHY1_BR_CTRL_EXP96_CUR_LOC_FNUM_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP96_CUR_LOC_FNUM_BITS                     8
#define BRPHY1_BR_CTRL_EXP96_CUR_LOC_FNUM_SHIFT                    4

/* BRPHY1_BR_CTRL :: EXP96 :: LDS_SPD [03:00] */
#define Wr_BRPHY1_BR_CTRL_EXP96_LDS_SPD(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP96,0xf,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP96_LDS_SPD(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP96,0xf,0)
#define BRPHY1_BR_CTRL_EXP96_LDS_SPD_MASK                          0x000f
#define BRPHY1_BR_CTRL_EXP96_LDS_SPD_ALIGN                         0
#define BRPHY1_BR_CTRL_EXP96_LDS_SPD_BITS                          4
#define BRPHY1_BR_CTRL_EXP96_LDS_SPD_SHIFT                         0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP97
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP97 :: LDS_TX_FSM_H [15:12] */
#define Wr_BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_H(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP97,0xf000,12,x)
#define Rd_BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_H(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP97,0xf000,12)
#define BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_H_MASK                     0xf000
#define BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_H_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_H_BITS                     4
#define BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_H_SHIFT                    12

/* BRPHY1_BR_CTRL :: EXP97 :: LDS_TX_FSM_L [11:08] */
#define Wr_BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_L(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP97,0xf00,8,x)
#define Rd_BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_L(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP97,0xf00,8)
#define BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_L_MASK                     0x0f00
#define BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_L_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_L_BITS                     4
#define BRPHY1_BR_CTRL_EXP97_LDS_TX_FSM_L_SHIFT                    8

/* BRPHY1_BR_CTRL :: EXP97 :: LDS_ARB_FSM_H [07:04] */
#define Wr_BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP97,0xf0,4,x)
#define Rd_BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP97,0xf0,4)
#define BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_H_MASK                    0x00f0
#define BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_H_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_H_BITS                    4
#define BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_H_SHIFT                   4

/* BRPHY1_BR_CTRL :: EXP97 :: LDS_ARB_FSM_L [03:00] */
#define Wr_BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP97,0xf,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP97,0xf,0)
#define BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_L_MASK                    0x000f
#define BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_L_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_L_BITS                    4
#define BRPHY1_BR_CTRL_EXP97_LDS_ARB_FSM_L_SHIFT                   0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP99
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP99 :: LDS_PGACTRL [15:10] */
#define Wr_BRPHY1_BR_CTRL_EXP99_LDS_PGACTRL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP99,0xfc00,10,x)
#define Rd_BRPHY1_BR_CTRL_EXP99_LDS_PGACTRL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP99,0xfc00,10)
#define BRPHY1_BR_CTRL_EXP99_LDS_PGACTRL_MASK                      0xfc00
#define BRPHY1_BR_CTRL_EXP99_LDS_PGACTRL_ALIGN                     0
#define BRPHY1_BR_CTRL_EXP99_LDS_PGACTRL_BITS                      6
#define BRPHY1_BR_CTRL_EXP99_LDS_PGACTRL_SHIFT                     10

/* BRPHY1_BR_CTRL :: EXP99 :: TXDIS_TMR_OPT [09:07] */
#define Wr_BRPHY1_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP99,0x380,7,x)
#define Rd_BRPHY1_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP99,0x380,7)
#define BRPHY1_BR_CTRL_EXP99_TXDIS_TMR_OPT_MASK                    0x0380
#define BRPHY1_BR_CTRL_EXP99_TXDIS_TMR_OPT_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP99_TXDIS_TMR_OPT_BITS                    3
#define BRPHY1_BR_CTRL_EXP99_TXDIS_TMR_OPT_SHIFT                   7

/* BRPHY1_BR_CTRL :: EXP99 :: LNK_TMR_OPT [06:04] */
#define Wr_BRPHY1_BR_CTRL_EXP99_LNK_TMR_OPT(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP99,0x70,4,x)
#define Rd_BRPHY1_BR_CTRL_EXP99_LNK_TMR_OPT(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP99,0x70,4)
#define BRPHY1_BR_CTRL_EXP99_LNK_TMR_OPT_MASK                      0x0070
#define BRPHY1_BR_CTRL_EXP99_LNK_TMR_OPT_ALIGN                     0
#define BRPHY1_BR_CTRL_EXP99_LNK_TMR_OPT_BITS                      3
#define BRPHY1_BR_CTRL_EXP99_LNK_TMR_OPT_SHIFT                     4

/* BRPHY1_BR_CTRL :: EXP99 :: BST_TMR_OPT [03:01] */
#define Wr_BRPHY1_BR_CTRL_EXP99_BST_TMR_OPT(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP99,0xe,1,x)
#define Rd_BRPHY1_BR_CTRL_EXP99_BST_TMR_OPT(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP99,0xe,1)
#define BRPHY1_BR_CTRL_EXP99_BST_TMR_OPT_MASK                      0x000e
#define BRPHY1_BR_CTRL_EXP99_BST_TMR_OPT_ALIGN                     0
#define BRPHY1_BR_CTRL_EXP99_BST_TMR_OPT_BITS                      3
#define BRPHY1_BR_CTRL_EXP99_BST_TMR_OPT_SHIFT                     1

/* BRPHY1_BR_CTRL :: EXP99 :: FASTBST [00:00] */
#define Wr_BRPHY1_BR_CTRL_EXP99_FASTBST(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP99,0x1,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP99_FASTBST(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP99,0x1,0)
#define BRPHY1_BR_CTRL_EXP99_FASTBST_MASK                          0x0001
#define BRPHY1_BR_CTRL_EXP99_FASTBST_ALIGN                         0
#define BRPHY1_BR_CTRL_EXP99_FASTBST_BITS                          1
#define BRPHY1_BR_CTRL_EXP99_FASTBST_SHIFT                         0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP9A
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP9A :: LRE_REG_OV_EN [15:15] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x8000,15,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x8000,15)
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_EN_MASK                    0x8000
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_EN_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_EN_BITS                    1
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_EN_SHIFT                   15

/* BRPHY1_BR_CTRL :: EXP9A :: LRE_REG_OV_VAL [14:14] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x4000,14,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x4000,14)
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_VAL_MASK                   0x4000
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_VAL_ALIGN                  0
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_VAL_BITS                   1
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_OV_VAL_SHIFT                  14

/* BRPHY1_BR_CTRL :: EXP9A :: LRE_REG_ACCESS_STAT [13:13] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x2000,13,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x2000,13)
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_MASK              0x2000
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_ALIGN             0
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_BITS              1
#define BRPHY1_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_SHIFT             13

/* BRPHY1_BR_CTRL :: EXP9A :: LDS_LINK_CHK_EN [12:12] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x1000,12,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x1000,12)
#define BRPHY1_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_MASK                  0x1000
#define BRPHY1_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_ALIGN                 0
#define BRPHY1_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_BITS                  1
#define BRPHY1_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_SHIFT                 12

/* BRPHY1_BR_CTRL :: EXP9A :: BR_AGC_TAR_OV_EN [11:11] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x800,11,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x800,11)
#define BRPHY1_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_MASK                 0x0800
#define BRPHY1_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_ALIGN                0
#define BRPHY1_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_BITS                 1
#define BRPHY1_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_SHIFT                11

/* BRPHY1_BR_CTRL :: EXP9A :: LDS_TIMER_OV_EN [10:10] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x400,10,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x400,10)
#define BRPHY1_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_MASK                  0x0400
#define BRPHY1_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_ALIGN                 0
#define BRPHY1_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_BITS                  1
#define BRPHY1_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_SHIFT                 10

/* BRPHY1_BR_CTRL :: EXP9A :: BR_LOST_TOKEN_FIX [09:09] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x200,9,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x200,9)
#define BRPHY1_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_MASK                0x0200
#define BRPHY1_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_ALIGN               0
#define BRPHY1_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_BITS                1
#define BRPHY1_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_SHIFT               9

/* BRPHY1_BR_CTRL :: EXP9A :: DLLCONV_EN_MSTR [08:08] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x100,8,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x100,8)
#define BRPHY1_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_MASK                  0x0100
#define BRPHY1_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_ALIGN                 0
#define BRPHY1_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_BITS                  1
#define BRPHY1_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_SHIFT                 8

/* BRPHY1_BR_CTRL :: EXP9A :: BR_10M1P_HALFOUT_EN [07:07] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x80,7,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x80,7)
#define BRPHY1_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_MASK              0x0080
#define BRPHY1_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_ALIGN             0
#define BRPHY1_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_BITS              1
#define BRPHY1_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_SHIFT             7

/* BRPHY1_BR_CTRL :: EXP9A :: BR_10M2P_HALFOUT_EN [06:06] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x40,6,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x40,6)
#define BRPHY1_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_MASK              0x0040
#define BRPHY1_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_ALIGN             0
#define BRPHY1_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_BITS              1
#define BRPHY1_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_SHIFT             6

/* BRPHY1_BR_CTRL :: EXP9A :: BR_HALFOUT_EN [05:05] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x20,5,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x20,5)
#define BRPHY1_BR_CTRL_EXP9A_BR_HALFOUT_EN_MASK                    0x0020
#define BRPHY1_BR_CTRL_EXP9A_BR_HALFOUT_EN_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP9A_BR_HALFOUT_EN_BITS                    1
#define BRPHY1_BR_CTRL_EXP9A_BR_HALFOUT_EN_SHIFT                   5

/* BRPHY1_BR_CTRL :: EXP9A :: CLK100T_ECO_DIS [04:04] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0x10,4,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0x10,4)
#define BRPHY1_BR_CTRL_EXP9A_CLK100T_ECO_DIS_MASK                  0x0010
#define BRPHY1_BR_CTRL_EXP9A_CLK100T_ECO_DIS_ALIGN                 0
#define BRPHY1_BR_CTRL_EXP9A_CLK100T_ECO_DIS_BITS                  1
#define BRPHY1_BR_CTRL_EXP9A_CLK100T_ECO_DIS_SHIFT                 4

/* BRPHY1_BR_CTRL :: EXP9A :: CH_STATUS [03:00] */
#define Wr_BRPHY1_BR_CTRL_EXP9A_CH_STATUS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9A,0xf,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP9A_CH_STATUS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9A,0xf,0)
#define BRPHY1_BR_CTRL_EXP9A_CH_STATUS_MASK                        0x000f
#define BRPHY1_BR_CTRL_EXP9A_CH_STATUS_ALIGN                       0
#define BRPHY1_BR_CTRL_EXP9A_CH_STATUS_BITS                        4
#define BRPHY1_BR_CTRL_EXP9A_CH_STATUS_SHIFT                       0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP9B
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP9B :: BR_RATE_OV [15:13] */
#define Wr_BRPHY1_BR_CTRL_EXP9B_BR_RATE_OV(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9B,0xe000,13,x)
#define Rd_BRPHY1_BR_CTRL_EXP9B_BR_RATE_OV(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9B,0xe000,13)
#define BRPHY1_BR_CTRL_EXP9B_BR_RATE_OV_MASK                       0xe000
#define BRPHY1_BR_CTRL_EXP9B_BR_RATE_OV_ALIGN                      0
#define BRPHY1_BR_CTRL_EXP9B_BR_RATE_OV_BITS                       3
#define BRPHY1_BR_CTRL_EXP9B_BR_RATE_OV_SHIFT                      13

/* BRPHY1_BR_CTRL :: EXP9B :: BR_200MBPS_CLK_EN [12:12] */
#define Wr_BRPHY1_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9B,0x1000,12,x)
#define Rd_BRPHY1_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9B,0x1000,12)
#define BRPHY1_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_MASK                0x1000
#define BRPHY1_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_ALIGN               0
#define BRPHY1_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_BITS                1
#define BRPHY1_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_SHIFT               12

/* BRPHY1_BR_CTRL :: EXP9B :: BR_TXCLK_EN [11:11] */
#define Wr_BRPHY1_BR_CTRL_EXP9B_BR_TXCLK_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9B,0x800,11,x)
#define Rd_BRPHY1_BR_CTRL_EXP9B_BR_TXCLK_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9B,0x800,11)
#define BRPHY1_BR_CTRL_EXP9B_BR_TXCLK_EN_MASK                      0x0800
#define BRPHY1_BR_CTRL_EXP9B_BR_TXCLK_EN_ALIGN                     0
#define BRPHY1_BR_CTRL_EXP9B_BR_TXCLK_EN_BITS                      1
#define BRPHY1_BR_CTRL_EXP9B_BR_TXCLK_EN_SHIFT                     11

/* BRPHY1_BR_CTRL :: EXP9B :: BR_TXRXICLK_EN [10:10] */
#define Wr_BRPHY1_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9B,0x400,10,x)
#define Rd_BRPHY1_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9B,0x400,10)
#define BRPHY1_BR_CTRL_EXP9B_BR_TXRXICLK_EN_MASK                   0x0400
#define BRPHY1_BR_CTRL_EXP9B_BR_TXRXICLK_EN_ALIGN                  0
#define BRPHY1_BR_CTRL_EXP9B_BR_TXRXICLK_EN_BITS                   1
#define BRPHY1_BR_CTRL_EXP9B_BR_TXRXICLK_EN_SHIFT                  10

/* BRPHY1_BR_CTRL :: EXP9B :: CLK_1G_DIV20 [09:09] */
#define Wr_BRPHY1_BR_CTRL_EXP9B_CLK_1G_DIV20(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9B,0x200,9,x)
#define Rd_BRPHY1_BR_CTRL_EXP9B_CLK_1G_DIV20(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9B,0x200,9)
#define BRPHY1_BR_CTRL_EXP9B_CLK_1G_DIV20_MASK                     0x0200
#define BRPHY1_BR_CTRL_EXP9B_CLK_1G_DIV20_ALIGN                    0
#define BRPHY1_BR_CTRL_EXP9B_CLK_1G_DIV20_BITS                     1
#define BRPHY1_BR_CTRL_EXP9B_CLK_1G_DIV20_SHIFT                    9

/* BRPHY1_BR_CTRL :: EXP9B :: LVL1_PROG_FREQ_DIV [08:05] */
#define Wr_BRPHY1_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9B,0x1e0,5,x)
#define Rd_BRPHY1_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9B,0x1e0,5)
#define BRPHY1_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_MASK               0x01e0
#define BRPHY1_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_ALIGN              0
#define BRPHY1_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_BITS               4
#define BRPHY1_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_SHIFT              5

/* BRPHY1_BR_CTRL :: EXP9B :: LVL2_PROG_FREQ_DIV [04:01] */
#define Wr_BRPHY1_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9B,0x1e,1,x)
#define Rd_BRPHY1_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9B,0x1e,1)
#define BRPHY1_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_MASK               0x001e
#define BRPHY1_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_ALIGN              0
#define BRPHY1_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_BITS               4
#define BRPHY1_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_SHIFT              1

/* BRPHY1_BR_CTRL :: EXP9B :: BR_PLL_CTL_EN [00:00] */
#define Wr_BRPHY1_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9B,0x1,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9B,0x1,0)
#define BRPHY1_BR_CTRL_EXP9B_BR_PLL_CTL_EN_MASK                    0x0001
#define BRPHY1_BR_CTRL_EXP9B_BR_PLL_CTL_EN_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP9B_BR_PLL_CTL_EN_BITS                    1
#define BRPHY1_BR_CTRL_EXP9B_BR_PLL_CTL_EN_SHIFT                   0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP9D
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP9D :: BR_IPR_BYPASS [15:15] */
#define Wr_BRPHY1_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9D,0x8000,15,x)
#define Rd_BRPHY1_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9D,0x8000,15)
#define BRPHY1_BR_CTRL_EXP9D_BR_IPR_BYPASS_MASK                    0x8000
#define BRPHY1_BR_CTRL_EXP9D_BR_IPR_BYPASS_ALIGN                   0
#define BRPHY1_BR_CTRL_EXP9D_BR_IPR_BYPASS_BITS                    1
#define BRPHY1_BR_CTRL_EXP9D_BR_IPR_BYPASS_SHIFT                   15

/* BRPHY1_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_VAL [14:14] */
#define Wr_BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9D,0x4000,14,x)
#define Rd_BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9D,0x4000,14)
#define BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_MASK               0x4000
#define BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_ALIGN              0
#define BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_BITS               1
#define BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_SHIFT              14

/* BRPHY1_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_EN [13:13] */
#define Wr_BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9D,0x2000,13,x)
#define Rd_BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9D,0x2000,13)
#define BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_MASK                0x2000
#define BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_ALIGN               0
#define BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_BITS                1
#define BRPHY1_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_SHIFT               13

/* BRPHY1_BR_CTRL :: EXP9D :: LDS_SD_THR [12:08] */
#define Wr_BRPHY1_BR_CTRL_EXP9D_LDS_SD_THR(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9D,0x1f00,8,x)
#define Rd_BRPHY1_BR_CTRL_EXP9D_LDS_SD_THR(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9D,0x1f00,8)
#define BRPHY1_BR_CTRL_EXP9D_LDS_SD_THR_MASK                       0x1f00
#define BRPHY1_BR_CTRL_EXP9D_LDS_SD_THR_ALIGN                      0
#define BRPHY1_BR_CTRL_EXP9D_LDS_SD_THR_BITS                       5
#define BRPHY1_BR_CTRL_EXP9D_LDS_SD_THR_SHIFT                      8

/* BRPHY1_BR_CTRL :: EXP9D :: LDS_PEAK_THR_T125 [07:00] */
#define Wr_BRPHY1_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9D,0xff,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9D,0xff,0)
#define BRPHY1_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_MASK                0x00ff
#define BRPHY1_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_ALIGN               0
#define BRPHY1_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_BITS                8
#define BRPHY1_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_SHIFT               0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP9E
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP9E :: LDS_LEN_THR1_T125 [15:08] */
#define Wr_BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9E,0xff00,8,x)
#define Rd_BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9E,0xff00,8)
#define BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_MASK                0xff00
#define BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_ALIGN               0
#define BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_BITS                8
#define BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_SHIFT               8

/* BRPHY1_BR_CTRL :: EXP9E :: LDS_LEN_THR0_T125 [07:00] */
#define Wr_BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9E,0xff,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9E,0xff,0)
#define BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_MASK                0x00ff
#define BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_ALIGN               0
#define BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_BITS                8
#define BRPHY1_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_SHIFT               0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXP9F
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXP9F :: LDS_LEN_THR3_T125 [15:08] */
#define Wr_BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9F,0xff00,8,x)
#define Rd_BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9F,0xff00,8)
#define BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_MASK                0xff00
#define BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_ALIGN               0
#define BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_BITS                8
#define BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_SHIFT               8

/* BRPHY1_BR_CTRL :: EXP9F :: LDS_LEN_THR2_T125 [07:00] */
#define Wr_BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) WriteRegBits16(BRPHY1_BR_CTRL_EXP9F,0xff,0,x)
#define Rd_BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) ReadRegBits16(BRPHY1_BR_CTRL_EXP9F,0xff,0)
#define BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_MASK                0x00ff
#define BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_ALIGN               0
#define BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_BITS                8
#define BRPHY1_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_SHIFT               0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXPA0
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXPA0 :: EPAGE_SPARE [15:02] */
#define Wr_BRPHY1_BR_CTRL_EXPA0_EPAGE_SPARE(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA0,0xfffc,2,x)
#define Rd_BRPHY1_BR_CTRL_EXPA0_EPAGE_SPARE(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA0,0xfffc,2)
#define BRPHY1_BR_CTRL_EXPA0_EPAGE_SPARE_MASK                      0xfffc
#define BRPHY1_BR_CTRL_EXPA0_EPAGE_SPARE_ALIGN                     0
#define BRPHY1_BR_CTRL_EXPA0_EPAGE_SPARE_BITS                      14
#define BRPHY1_BR_CTRL_EXPA0_EPAGE_SPARE_SHIFT                     2

/* BRPHY1_BR_CTRL :: EXPA0 :: PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY1_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA0,0x2,1,x)
#define Rd_BRPHY1_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA0,0x2,1)
#define BRPHY1_BR_CTRL_EXPA0_PAIR_1_250MBPS_MASK                   0x0002
#define BRPHY1_BR_CTRL_EXPA0_PAIR_1_250MBPS_ALIGN                  0
#define BRPHY1_BR_CTRL_EXPA0_PAIR_1_250MBPS_BITS                   1
#define BRPHY1_BR_CTRL_EXPA0_PAIR_1_250MBPS_SHIFT                  1

/* BRPHY1_BR_CTRL :: EXPA0 :: PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY1_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA0,0x1,0,x)
#define Rd_BRPHY1_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA0,0x1,0)
#define BRPHY1_BR_CTRL_EXPA0_PAIR_1_200MBPS_MASK                   0x0001
#define BRPHY1_BR_CTRL_EXPA0_PAIR_1_200MBPS_ALIGN                  0
#define BRPHY1_BR_CTRL_EXPA0_PAIR_1_200MBPS_BITS                   1
#define BRPHY1_BR_CTRL_EXPA0_PAIR_1_200MBPS_SHIFT                  0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXPA1
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXPA1 :: LP_EPAGE_SPARE [15:02] */
#define Wr_BRPHY1_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA1,0xfffc,2,x)
#define Rd_BRPHY1_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA1,0xfffc,2)
#define BRPHY1_BR_CTRL_EXPA1_LP_EPAGE_SPARE_MASK                   0xfffc
#define BRPHY1_BR_CTRL_EXPA1_LP_EPAGE_SPARE_ALIGN                  0
#define BRPHY1_BR_CTRL_EXPA1_LP_EPAGE_SPARE_BITS                   14
#define BRPHY1_BR_CTRL_EXPA1_LP_EPAGE_SPARE_SHIFT                  2

/* BRPHY1_BR_CTRL :: EXPA1 :: LP_PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA1,0x2,1,x)
#define Rd_BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA1,0x2,1)
#define BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_MASK                0x0002
#define BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_ALIGN               0
#define BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_BITS                1
#define BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_SHIFT               1

/* BRPHY1_BR_CTRL :: EXPA1 :: LP_PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA1,0x1,0,x)
#define Rd_BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA1,0x1,0)
#define BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_MASK                0x0001
#define BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_ALIGN               0
#define BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_BITS                1
#define BRPHY1_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_SHIFT               0


/****************************************************************************
 * BRPHY1_BR_CTRL :: EXPA2
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV_EN [15:15] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0x8000,15,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0x8000,15)
#define BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_MASK                  0x8000
#define BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_ALIGN                 0
#define BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_BITS                  1
#define BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_SHIFT                 15

/* BRPHY1_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV [14:14] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0x4000,14,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0x4000,14)
#define BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_MASK                     0x4000
#define BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_ALIGN                    0
#define BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_BITS                     1
#define BRPHY1_BR_CTRL_EXPA2_TFREQ_SEL_OV_SHIFT                    14

/* BRPHY1_BR_CTRL :: EXPA2 :: LOW_FREQ_TONE [13:13] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0x2000,13,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0x2000,13)
#define BRPHY1_BR_CTRL_EXPA2_LOW_FREQ_TONE_MASK                    0x2000
#define BRPHY1_BR_CTRL_EXPA2_LOW_FREQ_TONE_ALIGN                   0
#define BRPHY1_BR_CTRL_EXPA2_LOW_FREQ_TONE_BITS                    1
#define BRPHY1_BR_CTRL_EXPA2_LOW_FREQ_TONE_SHIFT                   13

/* BRPHY1_BR_CTRL :: EXPA2 :: BR_MAXWAIT_CTL [12:11] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0x1800,11,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0x1800,11)
#define BRPHY1_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_MASK                   0x1800
#define BRPHY1_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_ALIGN                  0
#define BRPHY1_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_BITS                   2
#define BRPHY1_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_SHIFT                  11

/* BRPHY1_BR_CTRL :: EXPA2 :: BR_M2S2_TMR_CTL [10:10] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0x400,10,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0x400,10)
#define BRPHY1_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_MASK                  0x0400
#define BRPHY1_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_ALIGN                 0
#define BRPHY1_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_BITS                  1
#define BRPHY1_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_SHIFT                 10

/* BRPHY1_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_FDX_S [09:09] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0x200,9,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0x200,9)
#define BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_MASK               0x0200
#define BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_ALIGN              0
#define BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_BITS               1
#define BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_SHIFT              9

/* BRPHY1_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_HDX [08:08] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0x100,8,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0x100,8)
#define BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_MASK                 0x0100
#define BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_ALIGN                0
#define BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_BITS                 1
#define BRPHY1_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_SHIFT                8

/* BRPHY1_BR_CTRL :: EXPA2 :: BR_PSD_TIMER_CTL [07:06] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0xc0,6,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0xc0,6)
#define BRPHY1_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_MASK                 0x00c0
#define BRPHY1_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_ALIGN                0
#define BRPHY1_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_BITS                 2
#define BRPHY1_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_SHIFT                6

/* BRPHY1_BR_CTRL :: EXPA2 :: MAN_PHASE_CK1X [05:03] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0x38,3,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0x38,3)
#define BRPHY1_BR_CTRL_EXPA2_MAN_PHASE_CK1X_MASK                   0x0038
#define BRPHY1_BR_CTRL_EXPA2_MAN_PHASE_CK1X_ALIGN                  0
#define BRPHY1_BR_CTRL_EXPA2_MAN_PHASE_CK1X_BITS                   3
#define BRPHY1_BR_CTRL_EXPA2_MAN_PHASE_CK1X_SHIFT                  3

/* BRPHY1_BR_CTRL :: EXPA2 :: LDS_PHASE_CK1X [02:00] */
#define Wr_BRPHY1_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) WriteRegBits16(BRPHY1_BR_CTRL_EXPA2,0x7,0,x)
#define Rd_BRPHY1_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) ReadRegBits16(BRPHY1_BR_CTRL_EXPA2,0x7,0)
#define BRPHY1_BR_CTRL_EXPA2_LDS_PHASE_CK1X_MASK                   0x0007
#define BRPHY1_BR_CTRL_EXPA2_LDS_PHASE_CK1X_ALIGN                  0
#define BRPHY1_BR_CTRL_EXPA2_LDS_PHASE_CK1X_BITS                   3
#define BRPHY1_BR_CTRL_EXPA2_LDS_PHASE_CK1X_SHIFT                  0


/****************************************************************************
 * BRPHY1_BR_CTRL :: BR_MISC_CONTROL_STATUS
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_2ND_FILTER [15:15] */
#define Wr_BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) WriteRegBits16(BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15,x)
#define Rd_BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) ReadRegBits16(BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15)
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_MASK 0x8000
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_ALIGN 0
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_BITS 1
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_SHIFT 15

/* BRPHY1_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_PR_DATAPATH [14:14] */
#define Wr_BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) WriteRegBits16(BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14,x)
#define Rd_BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) ReadRegBits16(BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14)
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_MASK 0x4000
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_ALIGN 0
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_BITS 1
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_SHIFT 14

/* BRPHY1_BR_CTRL :: BR_MISC_CONTROL_STATUS :: reserved0 [13:03] */
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_MASK       0x3ff8
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_ALIGN      0
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_BITS       11
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_SHIFT      3

/* BRPHY1_BR_CTRL :: BR_MISC_CONTROL_STATUS :: BR_1P_PCS_SOL [02:00] */
#define Wr_BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) WriteRegBits16(BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0,x)
#define Rd_BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) ReadRegBits16(BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0)
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_MASK   0x0007
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_ALIGN  0
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_BITS   3
#define BRPHY1_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_SHIFT  0


/****************************************************************************
 * BRPHY1_BR_CTRL :: BR250_CTL
 ***************************************************************************/
/* BRPHY1_BR_CTRL :: BR250_CTL :: BR_CURR_RATE [15:12] */
#define Wr_BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) WriteRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0xf000,12,x)
#define Rd_BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) ReadRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0xf000,12)
#define BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_RATE_MASK                 0xf000
#define BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_RATE_ALIGN                0
#define BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_RATE_BITS                 4
#define BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_RATE_SHIFT                12

/* BRPHY1_BR_CTRL :: BR250_CTL :: BR_CURR_PAIR [11:10] */
#define Wr_BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) WriteRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0xc00,10,x)
#define Rd_BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) ReadRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0xc00,10)
#define BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_PAIR_MASK                 0x0c00
#define BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_PAIR_ALIGN                0
#define BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_PAIR_BITS                 2
#define BRPHY1_BR_CTRL_BR250_CTL_BR_CURR_PAIR_SHIFT                10

/* BRPHY1_BR_CTRL :: BR250_CTL :: reserved0 [09:08] */
#define BRPHY1_BR_CTRL_BR250_CTL_RESERVED0_MASK                    0x0300
#define BRPHY1_BR_CTRL_BR250_CTL_RESERVED0_ALIGN                   0
#define BRPHY1_BR_CTRL_BR250_CTL_RESERVED0_BITS                    2
#define BRPHY1_BR_CTRL_BR250_CTL_RESERVED0_SHIFT                   8

/* BRPHY1_BR_CTRL :: BR250_CTL :: BR_PAM5_200_sel [07:07] */
#define Wr_BRPHY1_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) WriteRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0x80,7,x)
#define Rd_BRPHY1_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) ReadRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0x80,7)
#define BRPHY1_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_MASK              0x0080
#define BRPHY1_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_ALIGN             0
#define BRPHY1_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_BITS              1
#define BRPHY1_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_SHIFT             7

/* BRPHY1_BR_CTRL :: BR250_CTL :: LBKTst2 [06:06] */
#define Wr_BRPHY1_BR_CTRL_BR250_CTL_LBKTst2(x) WriteRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0x40,6,x)
#define Rd_BRPHY1_BR_CTRL_BR250_CTL_LBKTst2(x) ReadRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0x40,6)
#define BRPHY1_BR_CTRL_BR250_CTL_LBKTST2_MASK                      0x0040
#define BRPHY1_BR_CTRL_BR250_CTL_LBKTST2_ALIGN                     0
#define BRPHY1_BR_CTRL_BR250_CTL_LBKTST2_BITS                      1
#define BRPHY1_BR_CTRL_BR250_CTL_LBKTST2_SHIFT                     6

/* BRPHY1_BR_CTRL :: BR250_CTL :: CONF_GPLL_125 [05:05] */
#define Wr_BRPHY1_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) WriteRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0x20,5,x)
#define Rd_BRPHY1_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) ReadRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0x20,5)
#define BRPHY1_BR_CTRL_BR250_CTL_CONF_GPLL_125_MASK                0x0020
#define BRPHY1_BR_CTRL_BR250_CTL_CONF_GPLL_125_ALIGN               0
#define BRPHY1_BR_CTRL_BR250_CTL_CONF_GPLL_125_BITS                1
#define BRPHY1_BR_CTRL_BR250_CTL_CONF_GPLL_125_SHIFT               5

/* BRPHY1_BR_CTRL :: BR250_CTL :: reserved1 [04:04] */
#define BRPHY1_BR_CTRL_BR250_CTL_RESERVED1_MASK                    0x0010
#define BRPHY1_BR_CTRL_BR250_CTL_RESERVED1_ALIGN                   0
#define BRPHY1_BR_CTRL_BR250_CTL_RESERVED1_BITS                    1
#define BRPHY1_BR_CTRL_BR250_CTL_RESERVED1_SHIFT                   4

/* BRPHY1_BR_CTRL :: BR250_CTL :: INTRLV_CTL [03:02] */
#define Wr_BRPHY1_BR_CTRL_BR250_CTL_INTRLV_CTL(x) WriteRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0xc,2,x)
#define Rd_BRPHY1_BR_CTRL_BR250_CTL_INTRLV_CTL(x) ReadRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0xc,2)
#define BRPHY1_BR_CTRL_BR250_CTL_INTRLV_CTL_MASK                   0x000c
#define BRPHY1_BR_CTRL_BR250_CTL_INTRLV_CTL_ALIGN                  0
#define BRPHY1_BR_CTRL_BR250_CTL_INTRLV_CTL_BITS                   2
#define BRPHY1_BR_CTRL_BR250_CTL_INTRLV_CTL_SHIFT                  2

/* BRPHY1_BR_CTRL :: BR250_CTL :: PAIR_CFG [01:00] */
#define Wr_BRPHY1_BR_CTRL_BR250_CTL_PAIR_CFG(x) WriteRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0x3,0,x)
#define Rd_BRPHY1_BR_CTRL_BR250_CTL_PAIR_CFG(x) ReadRegBits16(BRPHY1_BR_CTRL_BR250_CTL,0x3,0)
#define BRPHY1_BR_CTRL_BR250_CTL_PAIR_CFG_MASK                     0x0003
#define BRPHY1_BR_CTRL_BR250_CTL_PAIR_CFG_ALIGN                    0
#define BRPHY1_BR_CTRL_BR250_CTL_PAIR_CFG_BITS                     2
#define BRPHY1_BR_CTRL_BR250_CTL_PAIR_CFG_SHIFT                    0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_IND_ACC
 ***************************************************************************/
/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_CTRL_SER_L16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_CTRL_SER_L16 :: reserved0 [15:08] */
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RESERVED0_MASK           0xff00
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RESERVED0_ALIGN          0
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RESERVED0_BITS           8
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RESERVED0_SHIFT          8

/* IND_ACC :: RDB_IND_REGS_CTRL_SER_L16 :: DONE [07:07] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_DONE(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x80,7,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_DONE(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x80,7)
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_DONE_MASK                0x0080
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_DONE_ALIGN               0
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_DONE_BITS                1
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_DONE_SHIFT               7

/* IND_ACC :: RDB_IND_REGS_CTRL_SER_L16 :: reserved1 [06:06] */
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RESERVED1_MASK           0x0040
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RESERVED1_ALIGN          0
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RESERVED1_BITS           1
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RESERVED1_SHIFT          6

/* IND_ACC :: RDB_IND_REGS_CTRL_SER_L16 :: COMMIT_ON_RDWR [05:05] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_ON_RDWR(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x20,5,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_ON_RDWR(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x20,5)
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_ON_RDWR_MASK      0x0020
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_ON_RDWR_ALIGN     0
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_ON_RDWR_BITS      1
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_ON_RDWR_SHIFT     5

/* IND_ACC :: RDB_IND_REGS_CTRL_SER_L16 :: COMMIT [04:04] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x10,4,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x10,4)
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_MASK              0x0010
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_ALIGN             0
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_BITS              1
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_COMMIT_SHIFT             4

/* IND_ACC :: RDB_IND_REGS_CTRL_SER_L16 :: AUTO_INCR [03:03] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_AUTO_INCR(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x8,3,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_AUTO_INCR(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x8,3)
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_AUTO_INCR_MASK           0x0008
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_AUTO_INCR_ALIGN          0
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_AUTO_INCR_BITS           1
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_AUTO_INCR_SHIFT          3

/* IND_ACC :: RDB_IND_REGS_CTRL_SER_L16 :: RDB_WR [02:02] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RDB_WR(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x4,2,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RDB_WR(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x4,2)
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RDB_WR_MASK              0x0004
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RDB_WR_ALIGN             0
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RDB_WR_BITS              1
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_RDB_WR_SHIFT             2

/* IND_ACC :: RDB_IND_REGS_CTRL_SER_L16 :: SIZE [01:00] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_SIZE(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x3,0,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_SER_L16_SIZE(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_SER_L16,0x3,0)
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_SIZE_MASK                0x0003
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_SIZE_ALIGN               0
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_SIZE_BITS                2
#define IND_ACC_RDB_IND_REGS_CTRL_SER_L16_SIZE_SHIFT               0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_ADDR_SER_L16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_ADDR_SER_L16 :: ADDRESS_L16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_ADDR_SER_L16_ADDRESS_L16(x) WriteReg16(IND_ACC_RDB_IND_REGS_ADDR_SER_L16,x)
#define Rd_IND_ACC_RDB_IND_REGS_ADDR_SER_L16_ADDRESS_L16(x) ReadReg16(IND_ACC_RDB_IND_REGS_ADDR_SER_L16)
#define IND_ACC_RDB_IND_REGS_ADDR_SER_L16_ADDRESS_L16_MASK         0xffff
#define IND_ACC_RDB_IND_REGS_ADDR_SER_L16_ADDRESS_L16_ALIGN        0
#define IND_ACC_RDB_IND_REGS_ADDR_SER_L16_ADDRESS_L16_BITS         16
#define IND_ACC_RDB_IND_REGS_ADDR_SER_L16_ADDRESS_L16_SHIFT        0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_ADDR_SER_H16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_ADDR_SER_H16 :: ADDRESS_H16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_ADDR_SER_H16_ADDRESS_H16(x) WriteReg16(IND_ACC_RDB_IND_REGS_ADDR_SER_H16,x)
#define Rd_IND_ACC_RDB_IND_REGS_ADDR_SER_H16_ADDRESS_H16(x) ReadReg16(IND_ACC_RDB_IND_REGS_ADDR_SER_H16)
#define IND_ACC_RDB_IND_REGS_ADDR_SER_H16_ADDRESS_H16_MASK         0xffff
#define IND_ACC_RDB_IND_REGS_ADDR_SER_H16_ADDRESS_H16_ALIGN        0
#define IND_ACC_RDB_IND_REGS_ADDR_SER_H16_ADDRESS_H16_BITS         16
#define IND_ACC_RDB_IND_REGS_ADDR_SER_H16_ADDRESS_H16_SHIFT        0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_DATA_SER_L_L16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_DATA_SER_L_L16 :: DATA_L_L16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_DATA_SER_L_L16_DATA_L_L16(x) WriteReg16(IND_ACC_RDB_IND_REGS_DATA_SER_L_L16,x)
#define Rd_IND_ACC_RDB_IND_REGS_DATA_SER_L_L16_DATA_L_L16(x) ReadReg16(IND_ACC_RDB_IND_REGS_DATA_SER_L_L16)
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_L16_DATA_L_L16_MASK        0xffff
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_L16_DATA_L_L16_ALIGN       0
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_L16_DATA_L_L16_BITS        16
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_L16_DATA_L_L16_SHIFT       0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_DATA_SER_L_H16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_DATA_SER_L_H16 :: DATA_L_H16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_DATA_SER_L_H16_DATA_L_H16(x) WriteReg16(IND_ACC_RDB_IND_REGS_DATA_SER_L_H16,x)
#define Rd_IND_ACC_RDB_IND_REGS_DATA_SER_L_H16_DATA_L_H16(x) ReadReg16(IND_ACC_RDB_IND_REGS_DATA_SER_L_H16)
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_H16_DATA_L_H16_MASK        0xffff
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_H16_DATA_L_H16_ALIGN       0
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_H16_DATA_L_H16_BITS        16
#define IND_ACC_RDB_IND_REGS_DATA_SER_L_H16_DATA_L_H16_SHIFT       0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_DATA_SER_H_L16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_DATA_SER_H_L16 :: DATA_H_L16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_DATA_SER_H_L16_DATA_H_L16(x) WriteReg16(IND_ACC_RDB_IND_REGS_DATA_SER_H_L16,x)
#define Rd_IND_ACC_RDB_IND_REGS_DATA_SER_H_L16_DATA_H_L16(x) ReadReg16(IND_ACC_RDB_IND_REGS_DATA_SER_H_L16)
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_L16_DATA_H_L16_MASK        0xffff
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_L16_DATA_H_L16_ALIGN       0
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_L16_DATA_H_L16_BITS        16
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_L16_DATA_H_L16_SHIFT       0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_DATA_SER_H_H16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_DATA_SER_H_H16 :: DATA_H_H16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_DATA_SER_H_H16_DATA_H_H16(x) WriteReg16(IND_ACC_RDB_IND_REGS_DATA_SER_H_H16,x)
#define Rd_IND_ACC_RDB_IND_REGS_DATA_SER_H_H16_DATA_H_H16(x) ReadReg16(IND_ACC_RDB_IND_REGS_DATA_SER_H_H16)
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_H16_DATA_H_H16_MASK        0xffff
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_H16_DATA_H_H16_ALIGN       0
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_H16_DATA_H_H16_BITS        16
#define IND_ACC_RDB_IND_REGS_DATA_SER_H_H16_DATA_H_H16_SHIFT       0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_CTRL_CPU_L16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_CTRL_CPU_L16 :: reserved0 [15:08] */
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RESERVED0_MASK           0xff00
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RESERVED0_ALIGN          0
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RESERVED0_BITS           8
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RESERVED0_SHIFT          8

/* IND_ACC :: RDB_IND_REGS_CTRL_CPU_L16 :: DONE [07:07] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_DONE(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x80,7,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_DONE(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x80,7)
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_DONE_MASK                0x0080
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_DONE_ALIGN               0
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_DONE_BITS                1
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_DONE_SHIFT               7

/* IND_ACC :: RDB_IND_REGS_CTRL_CPU_L16 :: reserved1 [06:06] */
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RESERVED1_MASK           0x0040
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RESERVED1_ALIGN          0
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RESERVED1_BITS           1
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RESERVED1_SHIFT          6

/* IND_ACC :: RDB_IND_REGS_CTRL_CPU_L16 :: COMMIT_ON_RDWR [05:05] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_ON_RDWR(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x20,5,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_ON_RDWR(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x20,5)
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_ON_RDWR_MASK      0x0020
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_ON_RDWR_ALIGN     0
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_ON_RDWR_BITS      1
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_ON_RDWR_SHIFT     5

/* IND_ACC :: RDB_IND_REGS_CTRL_CPU_L16 :: COMMIT [04:04] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x10,4,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x10,4)
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_MASK              0x0010
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_ALIGN             0
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_BITS              1
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_COMMIT_SHIFT             4

/* IND_ACC :: RDB_IND_REGS_CTRL_CPU_L16 :: AUTO_INCR [03:03] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_AUTO_INCR(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x8,3,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_AUTO_INCR(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x8,3)
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_AUTO_INCR_MASK           0x0008
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_AUTO_INCR_ALIGN          0
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_AUTO_INCR_BITS           1
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_AUTO_INCR_SHIFT          3

/* IND_ACC :: RDB_IND_REGS_CTRL_CPU_L16 :: RDB_WR [02:02] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RDB_WR(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x4,2,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RDB_WR(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x4,2)
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RDB_WR_MASK              0x0004
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RDB_WR_ALIGN             0
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RDB_WR_BITS              1
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_RDB_WR_SHIFT             2

/* IND_ACC :: RDB_IND_REGS_CTRL_CPU_L16 :: SIZE [01:00] */
#define Wr_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_SIZE(x) WriteRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x3,0,x)
#define Rd_IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_SIZE(x) ReadRegBits16(IND_ACC_RDB_IND_REGS_CTRL_CPU_L16,0x3,0)
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_SIZE_MASK                0x0003
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_SIZE_ALIGN               0
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_SIZE_BITS                2
#define IND_ACC_RDB_IND_REGS_CTRL_CPU_L16_SIZE_SHIFT               0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_ADDR_CPU_L16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_ADDR_CPU_L16 :: ADDRESS_L16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_ADDR_CPU_L16_ADDRESS_L16(x) WriteReg16(IND_ACC_RDB_IND_REGS_ADDR_CPU_L16,x)
#define Rd_IND_ACC_RDB_IND_REGS_ADDR_CPU_L16_ADDRESS_L16(x) ReadReg16(IND_ACC_RDB_IND_REGS_ADDR_CPU_L16)
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_L16_ADDRESS_L16_MASK         0xffff
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_L16_ADDRESS_L16_ALIGN        0
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_L16_ADDRESS_L16_BITS         16
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_L16_ADDRESS_L16_SHIFT        0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_ADDR_CPU_H16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_ADDR_CPU_H16 :: ADDRESS_H16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_ADDR_CPU_H16_ADDRESS_H16(x) WriteReg16(IND_ACC_RDB_IND_REGS_ADDR_CPU_H16,x)
#define Rd_IND_ACC_RDB_IND_REGS_ADDR_CPU_H16_ADDRESS_H16(x) ReadReg16(IND_ACC_RDB_IND_REGS_ADDR_CPU_H16)
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_H16_ADDRESS_H16_MASK         0xffff
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_H16_ADDRESS_H16_ALIGN        0
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_H16_ADDRESS_H16_BITS         16
#define IND_ACC_RDB_IND_REGS_ADDR_CPU_H16_ADDRESS_H16_SHIFT        0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_DATA_CPU_L_L16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_DATA_CPU_L_L16 :: DATA_L_L16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_DATA_CPU_L_L16_DATA_L_L16(x) WriteReg16(IND_ACC_RDB_IND_REGS_DATA_CPU_L_L16,x)
#define Rd_IND_ACC_RDB_IND_REGS_DATA_CPU_L_L16_DATA_L_L16(x) ReadReg16(IND_ACC_RDB_IND_REGS_DATA_CPU_L_L16)
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_L16_DATA_L_L16_MASK        0xffff
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_L16_DATA_L_L16_ALIGN       0
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_L16_DATA_L_L16_BITS        16
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_L16_DATA_L_L16_SHIFT       0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_DATA_CPU_L_H16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_DATA_CPU_L_H16 :: DATA_L_H16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_DATA_CPU_L_H16_DATA_L_H16(x) WriteReg16(IND_ACC_RDB_IND_REGS_DATA_CPU_L_H16,x)
#define Rd_IND_ACC_RDB_IND_REGS_DATA_CPU_L_H16_DATA_L_H16(x) ReadReg16(IND_ACC_RDB_IND_REGS_DATA_CPU_L_H16)
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_H16_DATA_L_H16_MASK        0xffff
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_H16_DATA_L_H16_ALIGN       0
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_H16_DATA_L_H16_BITS        16
#define IND_ACC_RDB_IND_REGS_DATA_CPU_L_H16_DATA_L_H16_SHIFT       0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_DATA_CPU_H_L16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_DATA_CPU_H_L16 :: DATA_H_L16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_DATA_CPU_H_L16_DATA_H_L16(x) WriteReg16(IND_ACC_RDB_IND_REGS_DATA_CPU_H_L16,x)
#define Rd_IND_ACC_RDB_IND_REGS_DATA_CPU_H_L16_DATA_H_L16(x) ReadReg16(IND_ACC_RDB_IND_REGS_DATA_CPU_H_L16)
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_L16_DATA_H_L16_MASK        0xffff
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_L16_DATA_H_L16_ALIGN       0
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_L16_DATA_H_L16_BITS        16
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_L16_DATA_H_L16_SHIFT       0


/****************************************************************************
 * IND_ACC :: RDB_IND_REGS_DATA_CPU_H_H16
 ***************************************************************************/
/* IND_ACC :: RDB_IND_REGS_DATA_CPU_H_H16 :: DATA_H_H16 [15:00] */
#define Wr_IND_ACC_RDB_IND_REGS_DATA_CPU_H_H16_DATA_H_H16(x) WriteReg16(IND_ACC_RDB_IND_REGS_DATA_CPU_H_H16,x)
#define Rd_IND_ACC_RDB_IND_REGS_DATA_CPU_H_H16_DATA_H_H16(x) ReadReg16(IND_ACC_RDB_IND_REGS_DATA_CPU_H_H16)
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_H16_DATA_H_H16_MASK        0xffff
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_H16_DATA_H_H16_ALIGN       0
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_H16_DATA_H_H16_BITS        16
#define IND_ACC_RDB_IND_REGS_DATA_CPU_H_H16_DATA_H_H16_SHIFT       0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys1_BRPHY1_BR_CL22_IEEE
 ***************************************************************************/
/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: MII_CTRL
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: RESET [15:15] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_RESET(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x8000,15,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_RESET(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x8000,15)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESET_MASK                    0x8000
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESET_ALIGN                   0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESET_BITS                    1
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESET_SHIFT                   15

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: LOOPBACK [14:14] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x4000,14,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x4000,14)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_LOOPBACK_MASK                 0x4000
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_LOOPBACK_ALIGN                0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_LOOPBACK_BITS                 1
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_LOOPBACK_SHIFT                14

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: RESTART_LDS [13:13] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x2000,13,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x2000,13)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_MASK              0x2000
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_ALIGN             0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_BITS              1
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_SHIFT             13

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: LDS_ENABLE [12:12] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x1000,12,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x1000,12)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_MASK               0x1000
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_ALIGN              0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_BITS               1
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_SHIFT              12

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: POWER_DOWN [11:11] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x800,11,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x800,11)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_MASK               0x0800
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_ALIGN              0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_BITS               1
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_SHIFT              11

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: ISOLATE [10:10] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x400,10,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x400,10)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_ISOLATE_MASK                  0x0400
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_ISOLATE_ALIGN                 0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_ISOLATE_BITS                  1
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_ISOLATE_SHIFT                 10

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: manual_speed_select_enable [09:09] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x200,9,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x200,9)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_MASK 0x0200
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_BITS 1
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_SHIFT 9

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: Speed_Selection [08:06] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x1c0,6,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x1c0,6)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_MASK          0x01c0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_ALIGN         0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_BITS          3
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_SHIFT         6

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: Pair_Selection [05:04] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x30,4,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x30,4)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_MASK           0x0030
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_ALIGN          0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_BITS           2
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_SHIFT          4

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: Master_mode [03:03] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_Master_mode(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x8,3,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_Master_mode(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x8,3)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_MASK              0x0008
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_ALIGN             0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_BITS              1
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_SHIFT             3

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: Unidirection_Enable [02:02] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x4,2,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_CTRL,0x4,2)
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_MASK      0x0004
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_ALIGN     0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_BITS      1
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_SHIFT     2

/* BRPHY1_BR_CL22_IEEE :: MII_CTRL :: reserved0 [01:00] */
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESERVED0_MASK                0x0003
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESERVED0_ALIGN               0
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESERVED0_BITS                2
#define BRPHY1_BR_CL22_IEEE_MII_CTRL_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: MII_STAT
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: MII_STAT :: reserved0 [15:15] */
#define BRPHY1_BR_CL22_IEEE_MII_STAT_RESERVED0_MASK                0x8000
#define BRPHY1_BR_CL22_IEEE_MII_STAT_RESERVED0_ALIGN               0
#define BRPHY1_BR_CL22_IEEE_MII_STAT_RESERVED0_BITS                1
#define BRPHY1_BR_CL22_IEEE_MII_STAT_RESERVED0_SHIFT               15

/* BRPHY1_BR_CL22_IEEE :: MII_STAT :: Capability [14:09] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_STAT_Capability(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x7e00,9,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_STAT_Capability(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x7e00,9)
#define BRPHY1_BR_CL22_IEEE_MII_STAT_CAPABILITY_MASK               0x7e00
#define BRPHY1_BR_CL22_IEEE_MII_STAT_CAPABILITY_ALIGN              0
#define BRPHY1_BR_CL22_IEEE_MII_STAT_CAPABILITY_BITS               6
#define BRPHY1_BR_CL22_IEEE_MII_STAT_CAPABILITY_SHIFT              9

/* BRPHY1_BR_CL22_IEEE :: MII_STAT :: EXTENDED_STAT [08:06] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x1c0,6,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x1c0,6)
#define BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_MASK            0x01c0
#define BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_ALIGN           0
#define BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_BITS            3
#define BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_SHIFT           6

/* BRPHY1_BR_CL22_IEEE :: MII_STAT :: LDS_complete [05:05] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_STAT_LDS_complete(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x20,5,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_STAT_LDS_complete(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x20,5)
#define BRPHY1_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_MASK             0x0020
#define BRPHY1_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_ALIGN            0
#define BRPHY1_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_BITS             1
#define BRPHY1_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_SHIFT            5

/* BRPHY1_BR_CL22_IEEE :: MII_STAT :: reserved1 [04:03] */
#define BRPHY1_BR_CL22_IEEE_MII_STAT_RESERVED1_MASK                0x0018
#define BRPHY1_BR_CL22_IEEE_MII_STAT_RESERVED1_ALIGN               0
#define BRPHY1_BR_CL22_IEEE_MII_STAT_RESERVED1_BITS                2
#define BRPHY1_BR_CL22_IEEE_MII_STAT_RESERVED1_SHIFT               3

/* BRPHY1_BR_CL22_IEEE :: MII_STAT :: LNK_STAT [02:02] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x4,2,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x4,2)
#define BRPHY1_BR_CL22_IEEE_MII_STAT_LNK_STAT_MASK                 0x0004
#define BRPHY1_BR_CL22_IEEE_MII_STAT_LNK_STAT_ALIGN                0
#define BRPHY1_BR_CL22_IEEE_MII_STAT_LNK_STAT_BITS                 1
#define BRPHY1_BR_CL22_IEEE_MII_STAT_LNK_STAT_SHIFT                2

/* BRPHY1_BR_CL22_IEEE :: MII_STAT :: JABBER_DETECT [01:01] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x2,1,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x2,1)
#define BRPHY1_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_MASK            0x0002
#define BRPHY1_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_ALIGN           0
#define BRPHY1_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_BITS            1
#define BRPHY1_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_SHIFT           1

/* BRPHY1_BR_CL22_IEEE :: MII_STAT :: EXTENDED_CAPABILITY [00:00] */
#define Wr_BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x1,0,x)
#define Rd_BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_MII_STAT,0x1,0)
#define BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_MASK      0x0001
#define BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_ALIGN     0
#define BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_BITS      1
#define BRPHY1_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_SHIFT     0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: PHY_ID_MSB
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: PHY_ID_MSB :: OUI_MSB [15:00] */
#define Wr_BRPHY1_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) WriteReg16(BRPHY1_BR_CL22_IEEE_PHY_ID_MSB,x)
#define Rd_BRPHY1_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) ReadReg16(BRPHY1_BR_CL22_IEEE_PHY_ID_MSB)
#define BRPHY1_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_MASK                0xffff
#define BRPHY1_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_ALIGN               0
#define BRPHY1_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_BITS                16
#define BRPHY1_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_SHIFT               0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: PHY_ID_LSB
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: PHY_ID_LSB :: OUI_LSB [15:10] */
#define Wr_BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10,x)
#define Rd_BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10)
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_MASK                0xfc00
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_ALIGN               0
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_BITS                6
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_SHIFT               10

/* BRPHY1_BR_CL22_IEEE :: PHY_ID_LSB :: MODEL [09:04] */
#define Wr_BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4,x)
#define Rd_BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4)
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_MODEL_MASK                  0x03f0
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_MODEL_ALIGN                 0
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_MODEL_BITS                  6
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_MODEL_SHIFT                 4

/* BRPHY1_BR_CL22_IEEE :: PHY_ID_LSB :: REVISION [03:00] */
#define Wr_BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_PHY_ID_LSB,0xf,0,x)
#define Rd_BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_PHY_ID_LSB,0xf,0)
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_REVISION_MASK               0x000f
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_REVISION_ALIGN              0
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_REVISION_BITS               4
#define BRPHY1_BR_CL22_IEEE_PHY_ID_LSB_REVISION_SHIFT              0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved0 [13:06] */
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_MASK      0x3fc0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_ALIGN     0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_BITS      8
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_SHIFT     6

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_MASK   0x0020
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_ALIGN  0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_BITS   1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_SHIFT  5

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved1 [00:00] */
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_MASK      0x0001
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_ALIGN     0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_BITS      1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_SHIFT     0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: LDS_Adv_Control
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Control :: Test_Mode [15:13] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_MASK         0xe000
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_ALIGN        0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_BITS         3
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_SHIFT        13

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Control :: reserved0 [12:10] */
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_MASK         0x1c00
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_ALIGN        0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_BITS         3
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_SHIFT        10

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Control :: Port_Type [09:09] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_MASK         0x0200
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_ALIGN        0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_BITS         1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_SHIFT        9

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Control :: Abilities_Field_Update [08:08] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_MASK 0x0100
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_SHIFT 8

/* BRPHY1_BR_CL22_IEEE :: LDS_Adv_Control :: Local_Field_Number [07:00] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0)
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_MASK 0x00ff
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_BITS 8
#define BRPHY1_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: LDS_Ability
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: LDS_Ability :: LDS_Ability [15:00] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) WriteReg16(BRPHY1_BR_CL22_IEEE_LDS_ABILITY,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) ReadReg16(BRPHY1_BR_CL22_IEEE_LDS_ABILITY)
#define BRPHY1_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_MASK           0xffff
#define BRPHY1_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_ALIGN          0
#define BRPHY1_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_BITS           16
#define BRPHY1_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_SHIFT          0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved0 [13:06] */
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_MASK       0x3fc0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_ALIGN      0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_BITS       8
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_SHIFT      6

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_MASK    0x0020
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_ALIGN   0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_BITS    1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_SHIFT   5

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved1 [00:00] */
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_MASK       0x0001
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_ALIGN      0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_BITS       1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_SHIFT      0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: LDS_LP_MSG_NxtP
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: LDS_LP_MSG_NxtP :: Link_Partner_Nxt_Pg_Msg [15:00] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) WriteReg16(BRPHY1_BR_CL22_IEEE_LDS_LP_MSG_NXTP,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) ReadReg16(BRPHY1_BR_CL22_IEEE_LDS_LP_MSG_NXTP)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_MASK 0xffff
#define BRPHY1_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_BITS 16
#define BRPHY1_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_SHIFT 0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_NxtP
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: NextPage_Read_Flag [15:15] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_MASK 0x8000
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_BITS 1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_SHIFT 15

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: reserved0 [14:09] */
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_MASK     0x7e00
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_ALIGN    0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_BITS     6
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_SHIFT    9

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_ACQ [08:08] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_MASK    0x0100
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_ALIGN   0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_BITS    1
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_SHIFT   8

/* BRPHY1_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_Field_Number [07:00] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0)
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_MASK 0x00ff
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_BITS 8
#define BRPHY1_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: LDS_LDS_EXP
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: LDS_LDS_EXP :: Downgrade_Ability [15:15] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15)
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_MASK     0x8000
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_ALIGN    0
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_BITS     1
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_SHIFT    15

/* BRPHY1_BR_CL22_IEEE :: LDS_LDS_EXP :: Master_Slave [14:14] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14)
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_MASK          0x4000
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_ALIGN         0
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_BITS          1
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_SHIFT         14

/* BRPHY1_BR_CL22_IEEE :: LDS_LDS_EXP :: Pair_Number [13:12] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12)
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_MASK           0x3000
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_ALIGN          0
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_BITS           2
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_SHIFT          12

/* BRPHY1_BR_CL22_IEEE :: LDS_LDS_EXP :: Estimated_Wire_Length [11:00] */
#define Wr_BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0)
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_MASK 0x0fff
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_BITS 12
#define BRPHY1_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_SHIFT 0


/****************************************************************************
 * BRPHY1_BR_CL22_IEEE :: LRE_EXTENDED_STAT
 ***************************************************************************/
/* BRPHY1_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: reserved0 [15:10] */
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_MASK       0xfc00
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_ALIGN      0
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_BITS       6
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_SHIFT      10

/* BRPHY1_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: LOCAL_RECEIVE_STATUS [09:09] */
#define Wr_BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9)
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_MASK 0x0200
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_SHIFT 9

/* BRPHY1_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: REMOTE_RECEIVE_STATUS [08:08] */
#define Wr_BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8)
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_MASK 0x0100
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_BITS 1
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_SHIFT 8

/* BRPHY1_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: IDLE_ERROR_CNTR [07:00] */
#define Wr_BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) WriteRegBits16(BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0,x)
#define Rd_BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) ReadRegBits16(BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0)
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_MASK 0x00ff
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_ALIGN 0
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_BITS 8
#define BRPHY1_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_CL45DEV1
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x8000,15)
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESET_BITS                   1
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved0 [14:14] */
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_MASK               0x4000
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_SHIFT              14

/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x2000,13)
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved1 [12:12] */
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_MASK               0x1000
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_BITS               1
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_SHIFT              12

/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x800,11)
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved2 [10:07] */
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_MASK               0x0780
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_BITS               4
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_SHIFT              7

/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x40,6)
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x3c,2)
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved3 [01:01] */
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_MASK               0x0002
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_BITS               1
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_SHIFT              1

/* BRPHY2_CL45DEV1 :: PMD_IEEE_CTL1 :: LPBK [00:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x1,0,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_CTL1,0x1,0)
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LPBK_MASK                    0x0001
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LPBK_ALIGN                   0
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LPBK_BITS                    1
#define BRPHY2_CL45DEV1_PMD_IEEE_CTL1_LPBK_SHIFT                   0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_ST1
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY2_CL45DEV1 :: PMD_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_ST1,0x80,7)
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_FAULT_BITS                    1
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY2_CL45DEV1 :: PMD_IEEE_ST1 :: reserved1 [06:03] */
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED1_MASK                0x0078
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED1_BITS                4
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY2_CL45DEV1 :: PMD_IEEE_ST1 :: RCV_LINK_ST [02:02] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_ST1,0x4,2)
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_MASK              0x0004
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_ALIGN             0
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_BITS              1
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_SHIFT             2

/* BRPHY2_CL45DEV1 :: PMD_IEEE_ST1 :: CAP_LOW_PWR [01:01] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_ST1,0x2,1)
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_MASK              0x0002
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_ALIGN             0
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_BITS              1
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_SHIFT             1

/* BRPHY2_CL45DEV1 :: PMD_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY2_CL45DEV1_PMD_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID0,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID0)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x80,7)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x40,6)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x20,5)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x10,4)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x8,3)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x4,2)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x2,1)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV0,0x1,0)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_DEV1
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV1,0x8000,15)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV1,0x4000,14)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_DEV1,0x2000,13)
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY2_CL45DEV1 :: PMD_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY2_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID0,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID0)
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID1,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID1)
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY2_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY2_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: TX_PMD_TSYNC_EN [01:01] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_MASK    0x0002
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_BITS    1
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_SHIFT   1

/* BRPHY2_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: RX_PMD_TSYNC_EN [00:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_MASK    0x0001
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_BITS    1
#define BRPHY2_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY2_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY2_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY2_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_CL45DEV3
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x8000,15)
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESET_BITS                   1
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1 :: PCS_LPBK [14:14] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x4000,14,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x4000,14)
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_MASK                0x4000
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_ALIGN               0
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_BITS                1
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_SHIFT               14

/* BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x2000,13)
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved0 [12:12] */
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_MASK               0x1000
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_SHIFT              12

/* BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x800,11)
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved1 [10:07] */
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_MASK               0x0780
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_BITS               4
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_SHIFT              7

/* BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x40,6)
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_CTL1,0x3c,2)
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY2_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved2 [01:00] */
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_MASK               0x0003
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_BITS               2
#define BRPHY2_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_SHIFT              0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_ST1
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY2_CL45DEV3 :: PCS_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_ST1,0x80,7)
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_FAULT_BITS                    1
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY2_CL45DEV3 :: PCS_IEEE_ST1 :: CLOCK_STOP_CAPABLE [06:06] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_ST1,0x40,6,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_ST1,0x40,6)
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_MASK       0x0040
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_ALIGN      0
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_BITS       1
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_SHIFT      6

/* BRPHY2_CL45DEV3 :: PCS_IEEE_ST1 :: reserved1 [05:03] */
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED1_MASK                0x0038
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED1_BITS                3
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY2_CL45DEV3 :: PCS_IEEE_ST1 :: PCS_RCV_LINK_ST [02:02] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_ST1,0x4,2)
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_MASK          0x0004
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_ALIGN         0
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_BITS          1
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_SHIFT         2

/* BRPHY2_CL45DEV3 :: PCS_IEEE_ST1 :: LOW_PWR_AB [01:01] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_ST1,0x2,1)
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_MASK               0x0002
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_BITS               1
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_SHIFT              1

/* BRPHY2_CL45DEV3 :: PCS_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY2_CL45DEV3_PCS_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID0,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID0)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x80,7)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x40,6)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x20,5)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x10,4)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x8,3)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x4,2)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x2,1)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV0,0x1,0)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_DEV1
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV1,0x8000,15)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV1,0x4000,14)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_DEV1,0x2000,13)
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY2_CL45DEV3 :: PCS_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY2_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID0,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID0)
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID1,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID1)
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY2_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_EEE_CAP
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_EEE_CAP :: reserved0 [15:07] */
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_RESERVED0_MASK                 0xff80
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_RESERVED0_ALIGN                0
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_RESERVED0_BITS                 9
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_RESERVED0_SHIFT                7

/* BRPHY2_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKR_EEE [06:06] */
#define Wr_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x40,6,x)
#define Rd_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x40,6)
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_MASK         0x0040
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_ALIGN        0
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_BITS         1
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_SHIFT        6

/* BRPHY2_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKX4_EEE [05:05] */
#define Wr_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x20,5,x)
#define Rd_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x20,5)
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_MASK        0x0020
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_ALIGN       0
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_BITS        1
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_SHIFT       5

/* BRPHY2_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASEKX_EEE [04:04] */
#define Wr_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x10,4,x)
#define Rd_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x10,4)
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_MASK        0x0010
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_ALIGN       0
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_BITS        1
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_SHIFT       4

/* BRPHY2_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASET_EEE [03:03] */
#define Wr_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x8,3,x)
#define Rd_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x8,3)
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_MASK          0x0008
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_ALIGN         0
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_BITS          1
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_SHIFT         3

/* BRPHY2_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASET_EEE [02:02] */
#define Wr_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x4,2,x)
#define Rd_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x4,2)
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_MASK         0x0004
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_ALIGN        0
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_BITS         1
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_SHIFT        2

/* BRPHY2_CL45DEV3 :: PCS_EEE_CAP :: PHY_100BASETX_EEE [01:01] */
#define Wr_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x2,1,x)
#define Rd_BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_EEE_CAP,0x2,1)
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_MASK         0x0002
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_ALIGN        0
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_BITS         1
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_SHIFT        1

/* BRPHY2_CL45DEV3 :: PCS_EEE_CAP :: reserved1 [00:00] */
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_RESERVED1_MASK                 0x0001
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_RESERVED1_ALIGN                0
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_RESERVED1_BITS                 1
#define BRPHY2_CL45DEV3_PCS_EEE_CAP_RESERVED1_SHIFT                0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt :: cnt [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) WriteReg16(BRPHY2_CL45DEV3_PCS_EEE_WAKE_ERR_CNT,x)
#define Rd_BRPHY2_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) ReadReg16(BRPHY2_CL45DEV3_PCS_EEE_WAKE_ERR_CNT)
#define BRPHY2_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_MASK              0xffff
#define BRPHY2_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_ALIGN             0
#define BRPHY2_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_BITS              16
#define BRPHY2_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_SHIFT             0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY2_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: TX_PCS_TSYNC_EN [01:01] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_MASK    0x0002
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_BITS    1
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_SHIFT   1

/* BRPHY2_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: RX_PCS_TSYNC_EN [00:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_MASK    0x0001
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_BITS    1
#define BRPHY2_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY2_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY2_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY2_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_CL45DEV7
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_CTRL
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_CTRL :: AN_reset [15:15] */
#define Wr_BRPHY2_CL45DEV7_AN_CTRL_AN_reset(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV7_AN_CTRL_AN_reset(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_CTRL,0x8000,15)
#define BRPHY2_CL45DEV7_AN_CTRL_AN_RESET_MASK                      0x8000
#define BRPHY2_CL45DEV7_AN_CTRL_AN_RESET_ALIGN                     0
#define BRPHY2_CL45DEV7_AN_CTRL_AN_RESET_BITS                      1
#define BRPHY2_CL45DEV7_AN_CTRL_AN_RESET_SHIFT                     15

/* BRPHY2_CL45DEV7 :: AN_CTRL :: reserved0 [14:14] */
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED0_MASK                     0x4000
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED0_ALIGN                    0
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED0_BITS                     1
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED0_SHIFT                    14

/* BRPHY2_CL45DEV7 :: AN_CTRL :: Extended_next_page_control [13:13] */
#define Wr_BRPHY2_CL45DEV7_AN_CTRL_Extended_next_page_control(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV7_AN_CTRL_Extended_next_page_control(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_CTRL,0x2000,13)
#define BRPHY2_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_MASK    0x2000
#define BRPHY2_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_ALIGN   0
#define BRPHY2_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_BITS    1
#define BRPHY2_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_SHIFT   13

/* BRPHY2_CL45DEV7 :: AN_CTRL :: Auto_Negotiation_enable [12:12] */
#define Wr_BRPHY2_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY2_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_CTRL,0x1000,12)
#define BRPHY2_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_MASK       0x1000
#define BRPHY2_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_ALIGN      0
#define BRPHY2_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_BITS       1
#define BRPHY2_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_SHIFT      12

/* BRPHY2_CL45DEV7 :: AN_CTRL :: reserved1 [11:10] */
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED1_MASK                     0x0c00
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED1_ALIGN                    0
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED1_BITS                     2
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED1_SHIFT                    10

/* BRPHY2_CL45DEV7 :: AN_CTRL :: Restart_Auto_Negotiation [09:09] */
#define Wr_BRPHY2_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_CTRL,0x200,9,x)
#define Rd_BRPHY2_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_CTRL,0x200,9)
#define BRPHY2_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_MASK      0x0200
#define BRPHY2_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_ALIGN     0
#define BRPHY2_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_BITS      1
#define BRPHY2_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_SHIFT     9

/* BRPHY2_CL45DEV7 :: AN_CTRL :: reserved2 [08:00] */
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED2_MASK                     0x01ff
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED2_ALIGN                    0
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED2_BITS                     9
#define BRPHY2_CL45DEV7_AN_CTRL_RESERVED2_SHIFT                    0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_STAT
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_STAT :: reserved0 [15:08] */
#define BRPHY2_CL45DEV7_AN_STAT_RESERVED0_MASK                     0xff00
#define BRPHY2_CL45DEV7_AN_STAT_RESERVED0_ALIGN                    0
#define BRPHY2_CL45DEV7_AN_STAT_RESERVED0_BITS                     8
#define BRPHY2_CL45DEV7_AN_STAT_RESERVED0_SHIFT                    8

/* BRPHY2_CL45DEV7 :: AN_STAT :: Extended_next_page_status [07:07] */
#define Wr_BRPHY2_CL45DEV7_AN_STAT_Extended_next_page_status(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x80,7,x)
#define Rd_BRPHY2_CL45DEV7_AN_STAT_Extended_next_page_status(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x80,7)
#define BRPHY2_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_MASK     0x0080
#define BRPHY2_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_ALIGN    0
#define BRPHY2_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_BITS     1
#define BRPHY2_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_SHIFT    7

/* BRPHY2_CL45DEV7 :: AN_STAT :: Page_received [06:06] */
#define Wr_BRPHY2_CL45DEV7_AN_STAT_Page_received(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x40,6,x)
#define Rd_BRPHY2_CL45DEV7_AN_STAT_Page_received(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x40,6)
#define BRPHY2_CL45DEV7_AN_STAT_PAGE_RECEIVED_MASK                 0x0040
#define BRPHY2_CL45DEV7_AN_STAT_PAGE_RECEIVED_ALIGN                0
#define BRPHY2_CL45DEV7_AN_STAT_PAGE_RECEIVED_BITS                 1
#define BRPHY2_CL45DEV7_AN_STAT_PAGE_RECEIVED_SHIFT                6

/* BRPHY2_CL45DEV7 :: AN_STAT :: AN_complete [05:05] */
#define Wr_BRPHY2_CL45DEV7_AN_STAT_AN_complete(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x20,5,x)
#define Rd_BRPHY2_CL45DEV7_AN_STAT_AN_complete(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x20,5)
#define BRPHY2_CL45DEV7_AN_STAT_AN_COMPLETE_MASK                   0x0020
#define BRPHY2_CL45DEV7_AN_STAT_AN_COMPLETE_ALIGN                  0
#define BRPHY2_CL45DEV7_AN_STAT_AN_COMPLETE_BITS                   1
#define BRPHY2_CL45DEV7_AN_STAT_AN_COMPLETE_SHIFT                  5

/* BRPHY2_CL45DEV7 :: AN_STAT :: Remodt_Fault [04:04] */
#define Wr_BRPHY2_CL45DEV7_AN_STAT_Remodt_Fault(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x10,4,x)
#define Rd_BRPHY2_CL45DEV7_AN_STAT_Remodt_Fault(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x10,4)
#define BRPHY2_CL45DEV7_AN_STAT_REMODT_FAULT_MASK                  0x0010
#define BRPHY2_CL45DEV7_AN_STAT_REMODT_FAULT_ALIGN                 0
#define BRPHY2_CL45DEV7_AN_STAT_REMODT_FAULT_BITS                  1
#define BRPHY2_CL45DEV7_AN_STAT_REMODT_FAULT_SHIFT                 4

/* BRPHY2_CL45DEV7 :: AN_STAT :: AN_ability [03:03] */
#define Wr_BRPHY2_CL45DEV7_AN_STAT_AN_ability(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x8,3,x)
#define Rd_BRPHY2_CL45DEV7_AN_STAT_AN_ability(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x8,3)
#define BRPHY2_CL45DEV7_AN_STAT_AN_ABILITY_MASK                    0x0008
#define BRPHY2_CL45DEV7_AN_STAT_AN_ABILITY_ALIGN                   0
#define BRPHY2_CL45DEV7_AN_STAT_AN_ABILITY_BITS                    1
#define BRPHY2_CL45DEV7_AN_STAT_AN_ABILITY_SHIFT                   3

/* BRPHY2_CL45DEV7 :: AN_STAT :: Link_status [02:02] */
#define Wr_BRPHY2_CL45DEV7_AN_STAT_Link_status(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x4,2,x)
#define Rd_BRPHY2_CL45DEV7_AN_STAT_Link_status(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x4,2)
#define BRPHY2_CL45DEV7_AN_STAT_LINK_STATUS_MASK                   0x0004
#define BRPHY2_CL45DEV7_AN_STAT_LINK_STATUS_ALIGN                  0
#define BRPHY2_CL45DEV7_AN_STAT_LINK_STATUS_BITS                   1
#define BRPHY2_CL45DEV7_AN_STAT_LINK_STATUS_SHIFT                  2

/* BRPHY2_CL45DEV7 :: AN_STAT :: reserved1 [01:01] */
#define BRPHY2_CL45DEV7_AN_STAT_RESERVED1_MASK                     0x0002
#define BRPHY2_CL45DEV7_AN_STAT_RESERVED1_ALIGN                    0
#define BRPHY2_CL45DEV7_AN_STAT_RESERVED1_BITS                     1
#define BRPHY2_CL45DEV7_AN_STAT_RESERVED1_SHIFT                    1

/* BRPHY2_CL45DEV7 :: AN_STAT :: Link_partner_AN_ability [00:00] */
#define Wr_BRPHY2_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x1,0,x)
#define Rd_BRPHY2_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_STAT,0x1,0)
#define BRPHY2_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_MASK       0x0001
#define BRPHY2_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY2_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY2_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_SHIFT      0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_DEV_ID_LSB
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_DEV_ID_LSB :: cu_an_device_identifier [15:00] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) WriteReg16(BRPHY2_CL45DEV7_AN_DEV_ID_LSB,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) ReadReg16(BRPHY2_CL45DEV7_AN_DEV_ID_LSB)
#define BRPHY2_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xffff
#define BRPHY2_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY2_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_BITS 16
#define BRPHY2_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_DEV_ID_MSB
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_DEV_ID_MSB :: cu_an_device_identifier [15:10] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10)
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xfc00
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_BITS 6
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 10

/* BRPHY2_CL45DEV7 :: AN_DEV_ID_MSB :: MODEL_NU [09:04] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4)
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_MASK                0x03f0
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_ALIGN               0
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_BITS                6
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_SHIFT               4

/* BRPHY2_CL45DEV7 :: AN_DEV_ID_MSB :: REV_NU [03:00] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_ID_MSB,0xf,0,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_ID_MSB,0xf,0)
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_REV_NU_MASK                  0x000f
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_REV_NU_ALIGN                 0
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_REV_NU_BITS                  4
#define BRPHY2_CL45DEV7_AN_DEV_ID_MSB_REV_NU_SHIFT                 0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: reserved0 [15:08] */
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_MASK           0xff00
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_ALIGN          0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_BITS           8
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_SHIFT          8

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_MASK         0x0080
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_ALIGN        0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_BITS         1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_SHIFT        7

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: TC_PRE [06:06] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_MASK              0x0040
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_ALIGN             0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_BITS              1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_SHIFT             6

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: DTEXS_PRE [05:05] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_MASK           0x0020
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_ALIGN          0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_BITS           1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_SHIFT          5

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PHYXS_PRE [04:04] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_MASK           0x0010
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_ALIGN          0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_BITS           1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_SHIFT          4

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PCS_PRE [03:03] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_MASK             0x0008
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_ALIGN            0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_BITS             1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_SHIFT            3

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: WIS_PRE [02:02] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_MASK             0x0004
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_ALIGN            0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_BITS             1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_SHIFT            2

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PMD_PRE [01:01] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_MASK             0x0002
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_ALIGN            0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_BITS             1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_SHIFT            1

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: CLA22_PRE [00:00] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_MASK           0x0001
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_ALIGN          0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_BITS           1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_SHIFT          0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_MSB
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_MASK      0x8000
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_ALIGN     0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_BITS      1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_SHIFT     15

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_MASK      0x4000
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_ALIGN     0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_BITS      1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_SHIFT     14

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13)
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_MASK       0x2000
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_ALIGN      0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_BITS       1
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_SHIFT      13

/* BRPHY2_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: reserved0 [12:00] */
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_MASK           0x1fff
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_ALIGN          0
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_BITS           13
#define BRPHY2_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_SHIFT          0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_DEV_PKG_ID_LSB
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_DEV_PKG_ID_LSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) WriteReg16(BRPHY2_CL45DEV7_AN_DEV_PKG_ID_LSB,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) ReadReg16(BRPHY2_CL45DEV7_AN_DEV_PKG_ID_LSB)
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_DEV_PKG_ID_MSB
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_DEV_PKG_ID_MSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY2_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) WriteReg16(BRPHY2_CL45DEV7_AN_DEV_PKG_ID_MSB,x)
#define Rd_BRPHY2_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) ReadReg16(BRPHY2_CL45DEV7_AN_DEV_PKG_ID_MSB)
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY2_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_AD
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_AD :: Next_page [15:15] */
#define Wr_BRPHY2_CL45DEV7_AN_AD_Next_page(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_AD,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV7_AN_AD_Next_page(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_AD,0x8000,15)
#define BRPHY2_CL45DEV7_AN_AD_NEXT_PAGE_MASK                       0x8000
#define BRPHY2_CL45DEV7_AN_AD_NEXT_PAGE_ALIGN                      0
#define BRPHY2_CL45DEV7_AN_AD_NEXT_PAGE_BITS                       1
#define BRPHY2_CL45DEV7_AN_AD_NEXT_PAGE_SHIFT                      15

/* BRPHY2_CL45DEV7 :: AN_AD :: Acknowledge [14:14] */
#define Wr_BRPHY2_CL45DEV7_AN_AD_Acknowledge(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_AD,0x4000,14,x)
#define Rd_BRPHY2_CL45DEV7_AN_AD_Acknowledge(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_AD,0x4000,14)
#define BRPHY2_CL45DEV7_AN_AD_ACKNOWLEDGE_MASK                     0x4000
#define BRPHY2_CL45DEV7_AN_AD_ACKNOWLEDGE_ALIGN                    0
#define BRPHY2_CL45DEV7_AN_AD_ACKNOWLEDGE_BITS                     1
#define BRPHY2_CL45DEV7_AN_AD_ACKNOWLEDGE_SHIFT                    14

/* BRPHY2_CL45DEV7 :: AN_AD :: Remote_fault [13:13] */
#define Wr_BRPHY2_CL45DEV7_AN_AD_Remote_fault(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_AD,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV7_AN_AD_Remote_fault(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_AD,0x2000,13)
#define BRPHY2_CL45DEV7_AN_AD_REMOTE_FAULT_MASK                    0x2000
#define BRPHY2_CL45DEV7_AN_AD_REMOTE_FAULT_ALIGN                   0
#define BRPHY2_CL45DEV7_AN_AD_REMOTE_FAULT_BITS                    1
#define BRPHY2_CL45DEV7_AN_AD_REMOTE_FAULT_SHIFT                   13

/* BRPHY2_CL45DEV7 :: AN_AD :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY2_CL45DEV7_AN_AD_Extended_next_page_ability(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_AD,0x1000,12,x)
#define Rd_BRPHY2_CL45DEV7_AN_AD_Extended_next_page_ability(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_AD,0x1000,12)
#define BRPHY2_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_MASK      0x1000
#define BRPHY2_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_ALIGN     0
#define BRPHY2_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_BITS      1
#define BRPHY2_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_SHIFT     12

/* BRPHY2_CL45DEV7 :: AN_AD :: Tech_Field [11:05] */
#define Wr_BRPHY2_CL45DEV7_AN_AD_Tech_Field(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_AD,0xfe0,5,x)
#define Rd_BRPHY2_CL45DEV7_AN_AD_Tech_Field(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_AD,0xfe0,5)
#define BRPHY2_CL45DEV7_AN_AD_TECH_FIELD_MASK                      0x0fe0
#define BRPHY2_CL45DEV7_AN_AD_TECH_FIELD_ALIGN                     0
#define BRPHY2_CL45DEV7_AN_AD_TECH_FIELD_BITS                      7
#define BRPHY2_CL45DEV7_AN_AD_TECH_FIELD_SHIFT                     5

/* BRPHY2_CL45DEV7 :: AN_AD :: Selector_Field [04:00] */
#define Wr_BRPHY2_CL45DEV7_AN_AD_Selector_Field(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_AD,0x1f,0,x)
#define Rd_BRPHY2_CL45DEV7_AN_AD_Selector_Field(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_AD,0x1f,0)
#define BRPHY2_CL45DEV7_AN_AD_SELECTOR_FIELD_MASK                  0x001f
#define BRPHY2_CL45DEV7_AN_AD_SELECTOR_FIELD_ALIGN                 0
#define BRPHY2_CL45DEV7_AN_AD_SELECTOR_FIELD_BITS                  5
#define BRPHY2_CL45DEV7_AN_AD_SELECTOR_FIELD_SHIFT                 0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_LPA
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_LPA :: Next_page [15:15] */
#define Wr_BRPHY2_CL45DEV7_AN_LPA_Next_page(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV7_AN_LPA_Next_page(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x8000,15)
#define BRPHY2_CL45DEV7_AN_LPA_NEXT_PAGE_MASK                      0x8000
#define BRPHY2_CL45DEV7_AN_LPA_NEXT_PAGE_ALIGN                     0
#define BRPHY2_CL45DEV7_AN_LPA_NEXT_PAGE_BITS                      1
#define BRPHY2_CL45DEV7_AN_LPA_NEXT_PAGE_SHIFT                     15

/* BRPHY2_CL45DEV7 :: AN_LPA :: Acknowledge [14:14] */
#define Wr_BRPHY2_CL45DEV7_AN_LPA_Acknowledge(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x4000,14,x)
#define Rd_BRPHY2_CL45DEV7_AN_LPA_Acknowledge(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x4000,14)
#define BRPHY2_CL45DEV7_AN_LPA_ACKNOWLEDGE_MASK                    0x4000
#define BRPHY2_CL45DEV7_AN_LPA_ACKNOWLEDGE_ALIGN                   0
#define BRPHY2_CL45DEV7_AN_LPA_ACKNOWLEDGE_BITS                    1
#define BRPHY2_CL45DEV7_AN_LPA_ACKNOWLEDGE_SHIFT                   14

/* BRPHY2_CL45DEV7 :: AN_LPA :: Remote_fault [13:13] */
#define Wr_BRPHY2_CL45DEV7_AN_LPA_Remote_fault(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV7_AN_LPA_Remote_fault(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x2000,13)
#define BRPHY2_CL45DEV7_AN_LPA_REMOTE_FAULT_MASK                   0x2000
#define BRPHY2_CL45DEV7_AN_LPA_REMOTE_FAULT_ALIGN                  0
#define BRPHY2_CL45DEV7_AN_LPA_REMOTE_FAULT_BITS                   1
#define BRPHY2_CL45DEV7_AN_LPA_REMOTE_FAULT_SHIFT                  13

/* BRPHY2_CL45DEV7 :: AN_LPA :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY2_CL45DEV7_AN_LPA_Extended_next_page_ability(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x1000,12,x)
#define Rd_BRPHY2_CL45DEV7_AN_LPA_Extended_next_page_ability(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x1000,12)
#define BRPHY2_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_MASK     0x1000
#define BRPHY2_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_ALIGN    0
#define BRPHY2_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_BITS     1
#define BRPHY2_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_SHIFT    12

/* BRPHY2_CL45DEV7 :: AN_LPA :: Tech_Field [11:05] */
#define Wr_BRPHY2_CL45DEV7_AN_LPA_Tech_Field(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_LPA,0xfe0,5,x)
#define Rd_BRPHY2_CL45DEV7_AN_LPA_Tech_Field(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_LPA,0xfe0,5)
#define BRPHY2_CL45DEV7_AN_LPA_TECH_FIELD_MASK                     0x0fe0
#define BRPHY2_CL45DEV7_AN_LPA_TECH_FIELD_ALIGN                    0
#define BRPHY2_CL45DEV7_AN_LPA_TECH_FIELD_BITS                     7
#define BRPHY2_CL45DEV7_AN_LPA_TECH_FIELD_SHIFT                    5

/* BRPHY2_CL45DEV7 :: AN_LPA :: Selector_Field [04:00] */
#define Wr_BRPHY2_CL45DEV7_AN_LPA_Selector_Field(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x1f,0,x)
#define Rd_BRPHY2_CL45DEV7_AN_LPA_Selector_Field(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_LPA,0x1f,0)
#define BRPHY2_CL45DEV7_AN_LPA_SELECTOR_FIELD_MASK                 0x001f
#define BRPHY2_CL45DEV7_AN_LPA_SELECTOR_FIELD_ALIGN                0
#define BRPHY2_CL45DEV7_AN_LPA_SELECTOR_FIELD_BITS                 5
#define BRPHY2_CL45DEV7_AN_LPA_SELECTOR_FIELD_SHIFT                0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_XNPA
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_XNPA :: Next_page [15:15] */
#define Wr_BRPHY2_CL45DEV7_AN_XNPA_Next_page(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV7_AN_XNPA_Next_page(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x8000,15)
#define BRPHY2_CL45DEV7_AN_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY2_CL45DEV7_AN_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY2_CL45DEV7_AN_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY2_CL45DEV7_AN_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY2_CL45DEV7 :: AN_XNPA :: reserved0 [14:14] */
#define BRPHY2_CL45DEV7_AN_XNPA_RESERVED0_MASK                     0x4000
#define BRPHY2_CL45DEV7_AN_XNPA_RESERVED0_ALIGN                    0
#define BRPHY2_CL45DEV7_AN_XNPA_RESERVED0_BITS                     1
#define BRPHY2_CL45DEV7_AN_XNPA_RESERVED0_SHIFT                    14

/* BRPHY2_CL45DEV7 :: AN_XNPA :: Message_page [13:13] */
#define Wr_BRPHY2_CL45DEV7_AN_XNPA_Message_page(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV7_AN_XNPA_Message_page(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x2000,13)
#define BRPHY2_CL45DEV7_AN_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY2_CL45DEV7_AN_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY2_CL45DEV7_AN_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY2_CL45DEV7_AN_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY2_CL45DEV7 :: AN_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY2_CL45DEV7_AN_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x1000,12,x)
#define Rd_BRPHY2_CL45DEV7_AN_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x1000,12)
#define BRPHY2_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY2_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY2_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY2_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY2_CL45DEV7 :: AN_XNPA :: Toggle [11:11] */
#define Wr_BRPHY2_CL45DEV7_AN_XNPA_Toggle(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x800,11,x)
#define Rd_BRPHY2_CL45DEV7_AN_XNPA_Toggle(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x800,11)
#define BRPHY2_CL45DEV7_AN_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY2_CL45DEV7_AN_XNPA_TOGGLE_ALIGN                       0
#define BRPHY2_CL45DEV7_AN_XNPA_TOGGLE_BITS                        1
#define BRPHY2_CL45DEV7_AN_XNPA_TOGGLE_SHIFT                       11

/* BRPHY2_CL45DEV7 :: AN_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY2_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x7ff,0,x)
#define Rd_BRPHY2_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY2_CL45DEV7_AN_XNPA,0x7ff,0)
#define BRPHY2_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY2_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY2_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY2_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_XNPB
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY2_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY2_CL45DEV7_AN_XNPB,x)
#define Rd_BRPHY2_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY2_CL45DEV7_AN_XNPB)
#define BRPHY2_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY2_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY2_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY2_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: AN_XNPC
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: AN_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY2_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY2_CL45DEV7_AN_XNPC,x)
#define Rd_BRPHY2_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY2_CL45DEV7_AN_XNPC)
#define BRPHY2_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY2_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY2_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY2_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: LP_XNPA
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: LP_XNPA :: Next_page [15:15] */
#define Wr_BRPHY2_CL45DEV7_LP_XNPA_Next_page(x) WriteRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV7_LP_XNPA_Next_page(x) ReadRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x8000,15)
#define BRPHY2_CL45DEV7_LP_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY2_CL45DEV7_LP_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY2_CL45DEV7_LP_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY2_CL45DEV7_LP_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY2_CL45DEV7 :: LP_XNPA :: Acknowledge [14:14] */
#define Wr_BRPHY2_CL45DEV7_LP_XNPA_Acknowledge(x) WriteRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x4000,14,x)
#define Rd_BRPHY2_CL45DEV7_LP_XNPA_Acknowledge(x) ReadRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x4000,14)
#define BRPHY2_CL45DEV7_LP_XNPA_ACKNOWLEDGE_MASK                   0x4000
#define BRPHY2_CL45DEV7_LP_XNPA_ACKNOWLEDGE_ALIGN                  0
#define BRPHY2_CL45DEV7_LP_XNPA_ACKNOWLEDGE_BITS                   1
#define BRPHY2_CL45DEV7_LP_XNPA_ACKNOWLEDGE_SHIFT                  14

/* BRPHY2_CL45DEV7 :: LP_XNPA :: Message_page [13:13] */
#define Wr_BRPHY2_CL45DEV7_LP_XNPA_Message_page(x) WriteRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV7_LP_XNPA_Message_page(x) ReadRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x2000,13)
#define BRPHY2_CL45DEV7_LP_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY2_CL45DEV7_LP_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY2_CL45DEV7_LP_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY2_CL45DEV7_LP_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY2_CL45DEV7 :: LP_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY2_CL45DEV7_LP_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x1000,12,x)
#define Rd_BRPHY2_CL45DEV7_LP_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x1000,12)
#define BRPHY2_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY2_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY2_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY2_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY2_CL45DEV7 :: LP_XNPA :: Toggle [11:11] */
#define Wr_BRPHY2_CL45DEV7_LP_XNPA_Toggle(x) WriteRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x800,11,x)
#define Rd_BRPHY2_CL45DEV7_LP_XNPA_Toggle(x) ReadRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x800,11)
#define BRPHY2_CL45DEV7_LP_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY2_CL45DEV7_LP_XNPA_TOGGLE_ALIGN                       0
#define BRPHY2_CL45DEV7_LP_XNPA_TOGGLE_BITS                        1
#define BRPHY2_CL45DEV7_LP_XNPA_TOGGLE_SHIFT                       11

/* BRPHY2_CL45DEV7 :: LP_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY2_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x7ff,0,x)
#define Rd_BRPHY2_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY2_CL45DEV7_LP_XNPA,0x7ff,0)
#define BRPHY2_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY2_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY2_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY2_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: LP_XNPB
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: LP_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY2_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY2_CL45DEV7_LP_XNPB,x)
#define Rd_BRPHY2_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY2_CL45DEV7_LP_XNPB)
#define BRPHY2_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY2_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY2_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY2_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: LP_XNPC
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: LP_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY2_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY2_CL45DEV7_LP_XNPC,x)
#define Rd_BRPHY2_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY2_CL45DEV7_LP_XNPC)
#define BRPHY2_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY2_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY2_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY2_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: TENG_AN_CTRL
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_MAN_CONFIG_EN [15:15] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x8000,15)
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_MASK   0x8000
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_ALIGN  0
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_BITS   1
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_SHIFT  15

/* BRPHY2_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_CONFIG_VAL [14:14] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x4000,14,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x4000,14)
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_MASK      0x4000
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_ALIGN     0
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_BITS      1
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_SHIFT     14

/* BRPHY2_CL45DEV7 :: TENG_AN_CTRL :: PORT_TYPE [13:13] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x2000,13)
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_MASK                0x2000
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_ALIGN               0
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_BITS                1
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_SHIFT               13

/* BRPHY2_CL45DEV7 :: TENG_AN_CTRL :: PHY10GBASET_ABLE [12:12] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x1000,12)
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_MASK         0x1000
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_ALIGN        0
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_BITS         1
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_SHIFT        12

/* BRPHY2_CL45DEV7 :: TENG_AN_CTRL :: reserved0 [11:03] */
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_RESERVED0_MASK                0x0ff8
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_RESERVED0_ALIGN               0
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_RESERVED0_BITS                9
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_RESERVED0_SHIFT               3

/* BRPHY2_CL45DEV7 :: TENG_AN_CTRL :: LD_PMA_TRAIN_RST_SEQ [02:02] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x4,2,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x4,2)
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_MASK     0x0004
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_ALIGN    0
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_BITS     1
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_SHIFT    2

/* BRPHY2_CL45DEV7 :: TENG_AN_CTRL :: reserved1 [01:01] */
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_RESERVED1_MASK                0x0002
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_RESERVED1_ALIGN               0
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_RESERVED1_BITS                1
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_RESERVED1_SHIFT               1

/* BRPHY2_CL45DEV7 :: TENG_AN_CTRL :: LD_LOOP_TIMING_ABLE [00:00] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x1,0,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_CTRL,0x1,0)
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_MASK      0x0001
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_BITS      1
#define BRPHY2_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_SHIFT     0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: TENG_AN_STAT
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_FAULT [15:15] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x8000,15,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x8000,15)
#define BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_MASK    0x8000
#define BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_ALIGN   0
#define BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_BITS    1
#define BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_SHIFT   15

/* BRPHY2_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_RES [14:14] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x4000,14,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x4000,14)
#define BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_MASK      0x4000
#define BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_ALIGN     0
#define BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_BITS      1
#define BRPHY2_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_SHIFT     14

/* BRPHY2_CL45DEV7 :: TENG_AN_STAT :: LOCAL_RCVR_STAT [13:13] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x2000,13,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x2000,13)
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_MASK          0x2000
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_ALIGN         0
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_BITS          1
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_SHIFT         13

/* BRPHY2_CL45DEV7 :: TENG_AN_STAT :: REMOTE_RCVR_STAT [12:12] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x1000,12,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x1000,12)
#define BRPHY2_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_MASK         0x1000
#define BRPHY2_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_ALIGN        0
#define BRPHY2_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_BITS         1
#define BRPHY2_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_SHIFT        12

/* BRPHY2_CL45DEV7 :: TENG_AN_STAT :: LNK_PRTNR_10GBASET_CAP [11:11] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x800,11,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x800,11)
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_MASK   0x0800
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_ALIGN  0
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_BITS   1
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_SHIFT  11

/* BRPHY2_CL45DEV7 :: TENG_AN_STAT :: LP_LOOP_TIMING_ABLE [10:10] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x400,10,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x400,10)
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_MASK      0x0400
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_BITS      1
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_SHIFT     10

/* BRPHY2_CL45DEV7 :: TENG_AN_STAT :: LP_PMA_TRAIN_RST_REQ [09:09] */
#define Wr_BRPHY2_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) WriteRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x200,9,x)
#define Rd_BRPHY2_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) ReadRegBits16(BRPHY2_CL45DEV7_TENG_AN_STAT,0x200,9)
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_MASK     0x0200
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_ALIGN    0
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_BITS     1
#define BRPHY2_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_SHIFT    9

/* BRPHY2_CL45DEV7 :: TENG_AN_STAT :: reserved0 [08:00] */
#define BRPHY2_CL45DEV7_TENG_AN_STAT_RESERVED0_MASK                0x01ff
#define BRPHY2_CL45DEV7_TENG_AN_STAT_RESERVED0_ALIGN               0
#define BRPHY2_CL45DEV7_TENG_AN_STAT_RESERVED0_BITS                9
#define BRPHY2_CL45DEV7_TENG_AN_STAT_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: EEE_ADV
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: EEE_ADV :: reserved0 [15:11] */
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED0_MASK                     0xf800
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED0_ALIGN                    0
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED0_BITS                     5
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED0_SHIFT                    11

/* BRPHY2_CL45DEV7 :: EEE_ADV :: Next_page [10:10] */
#define Wr_BRPHY2_CL45DEV7_EEE_ADV_Next_page(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x400,10,x)
#define Rd_BRPHY2_CL45DEV7_EEE_ADV_Next_page(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x400,10)
#define BRPHY2_CL45DEV7_EEE_ADV_NEXT_PAGE_MASK                     0x0400
#define BRPHY2_CL45DEV7_EEE_ADV_NEXT_PAGE_ALIGN                    0
#define BRPHY2_CL45DEV7_EEE_ADV_NEXT_PAGE_BITS                     1
#define BRPHY2_CL45DEV7_EEE_ADV_NEXT_PAGE_SHIFT                    10

/* BRPHY2_CL45DEV7 :: EEE_ADV :: reserved1 [09:07] */
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED1_MASK                     0x0380
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED1_ALIGN                    0
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED1_BITS                     3
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED1_SHIFT                    7

/* BRPHY2_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KR_EEE [06:06] */
#define Wr_BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x40,6,x)
#define Rd_BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x40,6)
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_MASK            0x0040
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_ALIGN           0
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_BITS            1
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_SHIFT           6

/* BRPHY2_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KX4_EEE [05:05] */
#define Wr_BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x20,5,x)
#define Rd_BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x20,5)
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_MASK           0x0020
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_ALIGN          0
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_BITS           1
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_SHIFT          5

/* BRPHY2_CL45DEV7 :: EEE_ADV :: reserved2 [04:04] */
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED2_MASK                     0x0010
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED2_ALIGN                    0
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED2_BITS                     1
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED2_SHIFT                    4

/* BRPHY2_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_T_EEE [03:03] */
#define Wr_BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x8,3,x)
#define Rd_BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x8,3)
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_MASK             0x0008
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_ALIGN            0
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_BITS             1
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_SHIFT            3

/* BRPHY2_CL45DEV7 :: EEE_ADV :: PHY_1000BASE_T_EEE [02:02] */
#define Wr_BRPHY2_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x4,2,x)
#define Rd_BRPHY2_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x4,2)
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_MASK            0x0004
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_ALIGN           0
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_BITS            1
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_SHIFT           2

/* BRPHY2_CL45DEV7 :: EEE_ADV :: PHY_100BASE_T_EEE [01:01] */
#define Wr_BRPHY2_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x2,1,x)
#define Rd_BRPHY2_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_ADV,0x2,1)
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_MASK             0x0002
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_ALIGN            0
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_BITS             1
#define BRPHY2_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_SHIFT            1

/* BRPHY2_CL45DEV7 :: EEE_ADV :: reserved3 [00:00] */
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED3_MASK                     0x0001
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED3_ALIGN                    0
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED3_BITS                     1
#define BRPHY2_CL45DEV7_EEE_ADV_RESERVED3_SHIFT                    0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: EEE_LP_ADV
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: EEE_LP_ADV :: status [15:00] */
#define Wr_BRPHY2_CL45DEV7_EEE_LP_ADV_status(x) WriteReg16(BRPHY2_CL45DEV7_EEE_LP_ADV,x)
#define Rd_BRPHY2_CL45DEV7_EEE_LP_ADV_status(x) ReadReg16(BRPHY2_CL45DEV7_EEE_LP_ADV)
#define BRPHY2_CL45DEV7_EEE_LP_ADV_STATUS_MASK                     0xffff
#define BRPHY2_CL45DEV7_EEE_LP_ADV_STATUS_ALIGN                    0
#define BRPHY2_CL45DEV7_EEE_LP_ADV_STATUS_BITS                     16
#define BRPHY2_CL45DEV7_EEE_LP_ADV_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY2_CL45DEV7 :: EEE_MODE_CTL
 ***************************************************************************/
/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: reserved0 [15:11] */
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED0_MASK                0xf800
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED0_ALIGN               0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED0_BITS                5
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED0_SHIFT               11

/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: Next_page [10:10] */
#define Wr_BRPHY2_CL45DEV7_EEE_MODE_CTL_Next_page(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x400,10,x)
#define Rd_BRPHY2_CL45DEV7_EEE_MODE_CTL_Next_page(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x400,10)
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_MASK                0x0400
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_ALIGN               0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_BITS                1
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_SHIFT               10

/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: reserved1 [09:07] */
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED1_MASK                0x0380
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED1_ALIGN               0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED1_BITS                3
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED1_SHIFT               7

/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KR_reduced_energy [06:06] */
#define Wr_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x40,6,x)
#define Rd_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x40,6)
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_MASK 0x0040
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_ALIGN 0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_BITS 1
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_SHIFT 6

/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KX4_reduced_energy [05:05] */
#define Wr_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x20,5,x)
#define Rd_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x20,5)
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_MASK 0x0020
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_ALIGN 0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_BITS 1
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_SHIFT 5

/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: reserved2 [04:04] */
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED2_MASK                0x0010
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED2_ALIGN               0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED2_BITS                1
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED2_SHIFT               4

/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_T_reduced_energy [03:03] */
#define Wr_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x8,3,x)
#define Rd_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x8,3)
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_MASK 0x0008
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_SHIFT 3

/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: PHY_1000BASE_T_reduced_energy [02:02] */
#define Wr_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x4,2,x)
#define Rd_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x4,2)
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_MASK 0x0004
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_SHIFT 2

/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: PHY_100BASE_T_reduced_energy [01:01] */
#define Wr_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) WriteRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x2,1,x)
#define Rd_BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) ReadRegBits16(BRPHY2_CL45DEV7_EEE_MODE_CTL,0x2,1)
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_MASK 0x0002
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_SHIFT 1

/* BRPHY2_CL45DEV7 :: EEE_MODE_CTL :: reserved3 [00:00] */
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED3_MASK                0x0001
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED3_ALIGN               0
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED3_BITS                1
#define BRPHY2_CL45DEV7_EEE_MODE_CTL_RESERVED3_SHIFT               0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_CL45VEN
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_CL45VEN :: FORCE_LINK
 ***************************************************************************/
/* BRPHY2_CL45VEN :: FORCE_LINK :: FORCE_LINK_MODE [15:15] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x8000,15,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x8000,15)
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_MASK             0x8000
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_ALIGN            0
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_BITS             1
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_SHIFT            15

/* BRPHY2_CL45VEN :: FORCE_LINK :: CHNG_10GBASET_AN_CTRL_BEHAV [14:14] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x4000,14,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x4000,14)
#define BRPHY2_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_MASK 0x4000
#define BRPHY2_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_ALIGN 0
#define BRPHY2_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_BITS 1
#define BRPHY2_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_SHIFT 14

/* BRPHY2_CL45VEN :: FORCE_LINK :: CHNG_BIT13_MCTRL_RD_BEHAV [13:13] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x2000,13,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x2000,13)
#define BRPHY2_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_MASK   0x2000
#define BRPHY2_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_ALIGN  0
#define BRPHY2_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_BITS   1
#define BRPHY2_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_SHIFT  13

/* BRPHY2_CL45VEN :: FORCE_LINK :: AN_FLP_BTB_TMR_MODE [12:12] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x1000,12,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x1000,12)
#define BRPHY2_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_MASK         0x1000
#define BRPHY2_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_ALIGN        0
#define BRPHY2_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_BITS         1
#define BRPHY2_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_SHIFT        12

/* BRPHY2_CL45VEN :: FORCE_LINK :: SWP_UFORMATED_CODE_FLDS [11:11] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x800,11,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x800,11)
#define BRPHY2_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_MASK     0x0800
#define BRPHY2_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_ALIGN    0
#define BRPHY2_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_BITS     1
#define BRPHY2_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_SHIFT    11

/* BRPHY2_CL45VEN :: FORCE_LINK :: BRK_LNK_TMR_MODE [10:10] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x400,10,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x400,10)
#define BRPHY2_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_MASK            0x0400
#define BRPHY2_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_ALIGN           0
#define BRPHY2_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_BITS            1
#define BRPHY2_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_SHIFT           10

/* BRPHY2_CL45VEN :: FORCE_LINK :: PREAMBLE_IGNORE [09:09] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x200,9,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x200,9)
#define BRPHY2_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_MASK             0x0200
#define BRPHY2_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_ALIGN            0
#define BRPHY2_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_BITS             1
#define BRPHY2_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_SHIFT            9

/* BRPHY2_CL45VEN :: FORCE_LINK :: FORCE_LNK_10GBASET_FDX [08:08] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x100,8,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x100,8)
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_MASK      0x0100
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_ALIGN     0
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_BITS      1
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_SHIFT     8

/* BRPHY2_CL45VEN :: FORCE_LINK :: FORCE_LNK_1000BASET_FDX_HDX [07:07] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x80,7,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x80,7)
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_MASK 0x0080
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_ALIGN 0
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_BITS 1
#define BRPHY2_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_SHIFT 7

/* BRPHY2_CL45VEN :: FORCE_LINK :: IGNORE_ACK2 [06:06] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x40,6,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x40,6)
#define BRPHY2_CL45VEN_FORCE_LINK_IGNORE_ACK2_MASK                 0x0040
#define BRPHY2_CL45VEN_FORCE_LINK_IGNORE_ACK2_ALIGN                0
#define BRPHY2_CL45VEN_FORCE_LINK_IGNORE_ACK2_BITS                 1
#define BRPHY2_CL45VEN_FORCE_LINK_IGNORE_ACK2_SHIFT                6

/* BRPHY2_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_OK [05:05] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x20,5,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x20,5)
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_MASK       0x0020
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_ALIGN      0
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_BITS       1
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_SHIFT      5

/* BRPHY2_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_RDY [04:04] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x10,4,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x10,4)
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_MASK      0x0010
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_ALIGN     0
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_BITS      1
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_SHIFT     4

/* BRPHY2_CL45VEN :: FORCE_LINK :: DIS_REG7P0_BIT13_AUTO_UPDATE [03:03] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x8,3,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x8,3)
#define BRPHY2_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_MASK 0x0008
#define BRPHY2_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_ALIGN 0
#define BRPHY2_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_BITS 1
#define BRPHY2_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_SHIFT 3

/* BRPHY2_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_OK [02:02] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x4,2,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x4,2)
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_MASK        0x0004
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_ALIGN       0
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_BITS        1
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_SHIFT       2

/* BRPHY2_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_RDY [01:01] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x2,1,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x2,1)
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_MASK       0x0002
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_ALIGN      0
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_BITS       1
#define BRPHY2_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_SHIFT      1

/* BRPHY2_CL45VEN :: FORCE_LINK :: LAST_PG_TO_EN [00:00] */
#define Wr_BRPHY2_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) WriteRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x1,0,x)
#define Rd_BRPHY2_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) ReadRegBits16(BRPHY2_CL45VEN_FORCE_LINK,0x1,0)
#define BRPHY2_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_MASK               0x0001
#define BRPHY2_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_ALIGN              0
#define BRPHY2_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_BITS               1
#define BRPHY2_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_SHIFT              0


/****************************************************************************
 * BRPHY2_CL45VEN :: SELECTIVE_RESET
 ***************************************************************************/
/* BRPHY2_CL45VEN :: SELECTIVE_RESET :: DSP_RESET [15:15] */
#define Wr_BRPHY2_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) WriteRegBits16(BRPHY2_CL45VEN_SELECTIVE_RESET,0x8000,15,x)
#define Rd_BRPHY2_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) ReadRegBits16(BRPHY2_CL45VEN_SELECTIVE_RESET,0x8000,15)
#define BRPHY2_CL45VEN_SELECTIVE_RESET_DSP_RESET_MASK              0x8000
#define BRPHY2_CL45VEN_SELECTIVE_RESET_DSP_RESET_ALIGN             0
#define BRPHY2_CL45VEN_SELECTIVE_RESET_DSP_RESET_BITS              1
#define BRPHY2_CL45VEN_SELECTIVE_RESET_DSP_RESET_SHIFT             15

/* BRPHY2_CL45VEN :: SELECTIVE_RESET :: SM_DSP_RESET [14:14] */
#define Wr_BRPHY2_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) WriteRegBits16(BRPHY2_CL45VEN_SELECTIVE_RESET,0x4000,14,x)
#define Rd_BRPHY2_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) ReadRegBits16(BRPHY2_CL45VEN_SELECTIVE_RESET,0x4000,14)
#define BRPHY2_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_MASK           0x4000
#define BRPHY2_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_ALIGN          0
#define BRPHY2_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_BITS           1
#define BRPHY2_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_SHIFT          14

/* BRPHY2_CL45VEN :: SELECTIVE_RESET :: reserved0 [13:08] */
#define BRPHY2_CL45VEN_SELECTIVE_RESET_RESERVED0_MASK              0x3f00
#define BRPHY2_CL45VEN_SELECTIVE_RESET_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_SELECTIVE_RESET_RESERVED0_BITS              6
#define BRPHY2_CL45VEN_SELECTIVE_RESET_RESERVED0_SHIFT             8

/* BRPHY2_CL45VEN :: SELECTIVE_RESET :: DIG100_RESET [07:07] */
#define Wr_BRPHY2_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) WriteRegBits16(BRPHY2_CL45VEN_SELECTIVE_RESET,0x80,7,x)
#define Rd_BRPHY2_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) ReadRegBits16(BRPHY2_CL45VEN_SELECTIVE_RESET,0x80,7)
#define BRPHY2_CL45VEN_SELECTIVE_RESET_DIG100_RESET_MASK           0x0080
#define BRPHY2_CL45VEN_SELECTIVE_RESET_DIG100_RESET_ALIGN          0
#define BRPHY2_CL45VEN_SELECTIVE_RESET_DIG100_RESET_BITS           1
#define BRPHY2_CL45VEN_SELECTIVE_RESET_DIG100_RESET_SHIFT          7

/* BRPHY2_CL45VEN :: SELECTIVE_RESET :: reserved1 [06:00] */
#define BRPHY2_CL45VEN_SELECTIVE_RESET_RESERVED1_MASK              0x007f
#define BRPHY2_CL45VEN_SELECTIVE_RESET_RESERVED1_ALIGN             0
#define BRPHY2_CL45VEN_SELECTIVE_RESET_RESERVED1_BITS              7
#define BRPHY2_CL45VEN_SELECTIVE_RESET_RESERVED1_SHIFT             0


/****************************************************************************
 * BRPHY2_CL45VEN :: TEST_FSM_EXT_NXT_PGS
 ***************************************************************************/
/* BRPHY2_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved0 [15:15] */
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_MASK         0x8000
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_ALIGN        0
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_BITS         1
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_SHIFT        15

/* BRPHY2_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_XMTR_STATE [14:12] */
#define Wr_BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) WriteRegBits16(BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12,x)
#define Rd_BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) ReadRegBits16(BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12)
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_MASK    0x7000
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_ALIGN   0
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_BITS    3
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_SHIFT   12

/* BRPHY2_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved1 [11:11] */
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_MASK         0x0800
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_ALIGN        0
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_BITS         1
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_SHIFT        11

/* BRPHY2_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_RCVR_STATE [10:08] */
#define Wr_BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) WriteRegBits16(BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8,x)
#define Rd_BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) ReadRegBits16(BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8)
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_MASK    0x0700
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_ALIGN   0
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_BITS    3
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_SHIFT   8

/* BRPHY2_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: ARB_STATE [07:04] */
#define Wr_BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) WriteRegBits16(BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4,x)
#define Rd_BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) ReadRegBits16(BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4)
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_MASK         0x00f0
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_ALIGN        0
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_BITS         4
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_SHIFT        4

/* BRPHY2_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: HCD_STATE [03:00] */
#define Wr_BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) WriteRegBits16(BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0,x)
#define Rd_BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) ReadRegBits16(BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0)
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_MASK         0x000f
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_ALIGN        0
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_BITS         4
#define BRPHY2_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_SHIFT        0


/****************************************************************************
 * BRPHY2_CL45VEN :: TEST_FSM_NXT_PGS
 ***************************************************************************/
/* BRPHY2_CL45VEN :: TEST_FSM_NXT_PGS :: reserved0 [15:10] */
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_MASK             0xfc00
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_ALIGN            0
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_BITS             6
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_SHIFT            10

/* BRPHY2_CL45VEN :: TEST_FSM_NXT_PGS :: NP_XMTR_STATE [09:05] */
#define Wr_BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) WriteRegBits16(BRPHY2_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5,x)
#define Rd_BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) ReadRegBits16(BRPHY2_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5)
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_MASK         0x03e0
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_ALIGN        0
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_BITS         5
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_SHIFT        5

/* BRPHY2_CL45VEN :: TEST_FSM_NXT_PGS :: reserved1 [04:04] */
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_MASK             0x0010
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_ALIGN            0
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_BITS             1
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_SHIFT            4

/* BRPHY2_CL45VEN :: TEST_FSM_NXT_PGS :: NP_RCVR_STATE [03:00] */
#define Wr_BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) WriteRegBits16(BRPHY2_CL45VEN_TEST_FSM_NXT_PGS,0xf,0,x)
#define Rd_BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) ReadRegBits16(BRPHY2_CL45VEN_TEST_FSM_NXT_PGS,0xf,0)
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_MASK         0x000f
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_ALIGN        0
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_BITS         4
#define BRPHY2_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_SHIFT        0


/****************************************************************************
 * BRPHY2_CL45VEN :: AN_MAN_TEST
 ***************************************************************************/
/* BRPHY2_CL45VEN :: AN_MAN_TEST :: reserved0 [15:12] */
#define BRPHY2_CL45VEN_AN_MAN_TEST_RESERVED0_MASK                  0xf000
#define BRPHY2_CL45VEN_AN_MAN_TEST_RESERVED0_ALIGN                 0
#define BRPHY2_CL45VEN_AN_MAN_TEST_RESERVED0_BITS                  4
#define BRPHY2_CL45VEN_AN_MAN_TEST_RESERVED0_SHIFT                 12

/* BRPHY2_CL45VEN :: AN_MAN_TEST :: LP_PG_TO_CAPTURE [11:08] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_TEST,0xf00,8,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_TEST,0xf00,8)
#define BRPHY2_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_MASK           0x0f00
#define BRPHY2_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_ALIGN          0
#define BRPHY2_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_BITS           4
#define BRPHY2_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_SHIFT          8

/* BRPHY2_CL45VEN :: AN_MAN_TEST :: reserved1 [07:03] */
#define BRPHY2_CL45VEN_AN_MAN_TEST_RESERVED1_MASK                  0x00f8
#define BRPHY2_CL45VEN_AN_MAN_TEST_RESERVED1_ALIGN                 0
#define BRPHY2_CL45VEN_AN_MAN_TEST_RESERVED1_BITS                  5
#define BRPHY2_CL45VEN_AN_MAN_TEST_RESERVED1_SHIFT                 3

/* BRPHY2_CL45VEN :: AN_MAN_TEST :: LNK_PARTNR_NXT_PG_TEST_MODE [02:02] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_TEST,0x4,2,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_TEST,0x4,2)
#define BRPHY2_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_MASK 0x0004
#define BRPHY2_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_SHIFT 2

/* BRPHY2_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN_SEED [01:01] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_TEST,0x2,1,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_TEST,0x2,1)
#define BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_MASK           0x0002
#define BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_ALIGN          0
#define BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_BITS           1
#define BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_SHIFT          1

/* BRPHY2_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN [00:00] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_TEST,0x1,0,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_TEST,0x1,0)
#define BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_MASK                0x0001
#define BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_ALIGN               0
#define BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_BITS                1
#define BRPHY2_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SHIFT               0


/****************************************************************************
 * BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A
 ***************************************************************************/
/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_HDX [15:15] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_MASK 0x8000
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_SHIFT 15

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_FDX [14:14] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_MASK 0x4000
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_SHIFT 14

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_PORT_TYPE [13:13] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_MASK 0x2000
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_SHIFT 13

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_CONFIG_VALUE [12:12] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_MASK 0x1000
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_SHIFT 12

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_MANUAL_CONFIG_EN [11:11] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_MASK 0x0800
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_SHIFT 11

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_SEED [10:00] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_MASK    0x07ff
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_ALIGN   0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_BITS    11
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_SHIFT   0


/****************************************************************************
 * BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B
 ***************************************************************************/
/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved0 [15:05] */
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_MASK      0xffe0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_ALIGN     0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_BITS      11
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_SHIFT     5

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PMA_TRAINING_RESET_REQ [04:04] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_MASK 0x0010
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_SHIFT 4

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved1 [03:03] */
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_MASK      0x0008
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_ALIGN     0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_BITS      1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_SHIFT     3

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PHY_SHORT_REACH_MODE [02:02] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_MASK 0x0004
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_SHIFT 2

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_LOOP_TIMING_ABILITY [01:01] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_MASK 0x0002
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_SHIFT 1

/* BRPHY2_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_10GBASET_CAPABILITY [00:00] */
#define Wr_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) WriteRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0,x)
#define Rd_BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) ReadRegBits16(BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0)
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_MASK 0x0001
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_ALIGN 0
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_BITS 1
#define BRPHY2_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_A
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_A :: LP_NP_A [15:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) WriteReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_A,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) ReadReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_A)
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_MASK            0xffff
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_ALIGN           0
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_BITS            16
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_SHIFT           0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_B
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_B :: LP_NP_B [15:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) WriteReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_B,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) ReadReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_B)
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_MASK            0xffff
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_ALIGN           0
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_BITS            16
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_SHIFT           0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_C
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_C :: LP_NP_C [15:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) WriteReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_C,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) ReadReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_C)
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_MASK            0xffff
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_ALIGN           0
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_BITS            16
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_SHIFT           0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_D
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_D :: LP_NP_D [15:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) WriteReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_D,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) ReadReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_D)
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_MASK            0xffff
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_ALIGN           0
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_BITS            16
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_SHIFT           0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_E
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_E :: LP_NP_E [15:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) WriteReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_E,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) ReadReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_E)
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_MASK            0xffff
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_ALIGN           0
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_BITS            16
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_SHIFT           0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_F
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_NXT_PG_F :: LP_NP_F [15:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) WriteReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_F,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) ReadReg16(BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_F)
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_MASK            0xffff
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_ALIGN           0
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_BITS            16
#define BRPHY2_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_SHIFT           0


/****************************************************************************
 * BRPHY2_CL45VEN :: EPON_CTRL_REG
 ***************************************************************************/
/* BRPHY2_CL45VEN :: EPON_CTRL_REG :: reserved0 [15:10] */
#define BRPHY2_CL45VEN_EPON_CTRL_REG_RESERVED0_MASK                0xfc00
#define BRPHY2_CL45VEN_EPON_CTRL_REG_RESERVED0_ALIGN               0
#define BRPHY2_CL45VEN_EPON_CTRL_REG_RESERVED0_BITS                6
#define BRPHY2_CL45VEN_EPON_CTRL_REG_RESERVED0_SHIFT               10

/* BRPHY2_CL45VEN :: EPON_CTRL_REG :: EPON_MODE [09:09] */
#define Wr_BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) WriteRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x200,9,x)
#define Rd_BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) ReadRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x200,9)
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_MASK                0x0200
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_ALIGN               0
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_BITS                1
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_SHIFT               9

/* BRPHY2_CL45VEN :: EPON_CTRL_REG :: EOC_PACKET_NORM [08:08] */
#define Wr_BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) WriteRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x100,8,x)
#define Rd_BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) ReadRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x100,8)
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_MASK          0x0100
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_ALIGN         0
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_BITS          1
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_SHIFT         8

/* BRPHY2_CL45VEN :: EPON_CTRL_REG :: EPON_MODE_CRCCHECK [07:07] */
#define Wr_BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) WriteRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x80,7,x)
#define Rd_BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) ReadRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x80,7)
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_MASK       0x0080
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_ALIGN      0
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_BITS       1
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_SHIFT      7

/* BRPHY2_CL45VEN :: EPON_CTRL_REG :: TX_EN_EXTEND [06:06] */
#define Wr_BRPHY2_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) WriteRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x40,6,x)
#define Rd_BRPHY2_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) ReadRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x40,6)
#define BRPHY2_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_MASK             0x0040
#define BRPHY2_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_ALIGN            0
#define BRPHY2_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_BITS             1
#define BRPHY2_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_SHIFT            6

/* BRPHY2_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POLARITY [05:05] */
#define Wr_BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) WriteRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x20,5,x)
#define Rd_BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) ReadRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x20,5)
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_MASK        0x0020
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_ALIGN       0
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_BITS        1
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_SHIFT       5

/* BRPHY2_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POL_CORR [04:04] */
#define Wr_BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) WriteRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x10,4,x)
#define Rd_BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) ReadRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0x10,4)
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_MASK        0x0010
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_ALIGN       0
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_BITS        1
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_SHIFT       4

/* BRPHY2_CL45VEN :: EPON_CTRL_REG :: EOC_SPEED_DET_THLD [03:00] */
#define Wr_BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) WriteRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0xf,0,x)
#define Rd_BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) ReadRegBits16(BRPHY2_CL45VEN_EPON_CTRL_REG,0xf,0)
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_MASK       0x000f
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_ALIGN      0
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_BITS       4
#define BRPHY2_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_SHIFT      0


/****************************************************************************
 * BRPHY2_CL45VEN :: EEE_TEST_CTRL_A
 ***************************************************************************/
/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: reserved0 [15:12] */
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_MASK              0xf000
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_BITS              4
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_SHIFT             12

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_RX_EN [11:11] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x800,11,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x800,11)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_MASK        0x0800
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_ALIGN       0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_BITS        1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_SHIFT       11

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_TX_EN [10:10] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x400,10,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x400,10)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_MASK        0x0400
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_ALIGN       0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_BITS        1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_SHIFT       10

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_RX_EN [09:09] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x200,9,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x200,9)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_MASK           0x0200
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_ALIGN          0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_BITS           1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_SHIFT          9

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_TX_EN [08:08] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x100,8,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x100,8)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_MASK           0x0100
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_ALIGN          0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_BITS           1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_SHIFT          8

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: LPI_GPCS_TEST_BUS_EN [07:07] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x80,7,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x80,7)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_MASK   0x0080
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_ALIGN  0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_BITS   1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_SHIFT  7

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: MACSEC_PK_MODE [06:06] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x40,6,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x40,6)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_MASK         0x0040
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_ALIGN        0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_BITS         1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_SHIFT        6

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: MSG_11_VS_10 [05:05] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x20,5,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x20,5)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_MASK           0x0020
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_ALIGN          0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_BITS           1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_SHIFT          5

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE [04:04] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x10,4,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x10,4)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_MASK              0x0010
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_ALIGN             0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_BITS              1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFT             4

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE_SHIFTED [03:03] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x8,3,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x8,3)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_MASK      0x0008
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_ALIGN     0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_BITS      1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_SHIFT     3

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: reserved1 [02:02] */
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_MASK              0x0004
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_ALIGN             0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_BITS              1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_SHIFT             2

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LP_M10 [01:01] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x2,1,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x2,1)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_MASK        0x0002
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_ALIGN       0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_BITS        1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_SHIFT       1

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LD_M10 [00:00] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x1,0,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_A,0x1,0)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_MASK        0x0001
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_ALIGN       0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_BITS        1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_SHIFT       0


/****************************************************************************
 * BRPHY2_CL45VEN :: EEE_TEST_CTRL_B
 ***************************************************************************/
/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x8000,15,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x8000,15)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_MASK         0x8000
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_ALIGN        0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_BITS         1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_SHIFT        15

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x4000,14,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x4000,14)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_MASK 0x4000
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_ALIGN 0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_BITS 1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_SHIFT 14

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_LPI_QUALIFIERS [13:13] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x2000,13,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x2000,13)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_MASK 0x2000
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_ALIGN 0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_BITS 1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_SHIFT 13

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_REG_3_20 [12:12] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x1000,12,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x1000,12)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_MASK 0x1000
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_ALIGN 0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_BITS 1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_SHIFT 12

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_RES [11:11] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x800,11,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x800,11)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_MASK       0x0800
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_ALIGN      0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_BITS       1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_SHIFT      11

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_10BASE_T_RES [10:10] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x400,10,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x400,10)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_MASK 0x0400
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_ALIGN 0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_BITS 1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_SHIFT 10

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: DET_SEND_Z [09:09] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x200,9,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x200,9)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_MASK             0x0200
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_ALIGN            0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_BITS             1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_SHIFT            9

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: EN_DET_SEND_Z_OVERRIDE [08:08] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x100,8,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x100,8)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_MASK 0x0100
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_ALIGN 0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_BITS 1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_SHIFT 8

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: REM_UPD_DONE_TEST [07:07] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x80,7,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x80,7)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_MASK      0x0080
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_ALIGN     0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_BITS      1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_SHIFT     7

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: REM_LPI_REQ_TEST [06:06] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x40,6,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x40,6)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_MASK       0x0040
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_ALIGN      0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_BITS       1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_SHIFT      6

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: LOC_UPD_DONE_TEST [05:05] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x20,5,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x20,5)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_MASK      0x0020
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_ALIGN     0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_BITS      1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_SHIFT     5

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: LOC_LPI_REQ_TEST [04:04] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x10,4,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x10,4)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_MASK       0x0010
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_ALIGN      0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_BITS       1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_SHIFT      4

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_UPD_DONE_OVERRIDE [03:03] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x8,3,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x8,3)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_MASK 0x0008
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_SHIFT 3

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_LPI_REQ_OVERRIDE [02:02] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x4,2,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x4,2)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_MASK 0x0004
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_SHIFT 2

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_UPD_DONE_OVERRIDE [01:01] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x2,1,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x2,1)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_MASK 0x0002
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_SHIFT 1

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_LPI_REQ_OVERRIDE [00:00] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x1,0,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_B,0x1,0)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_MASK 0x0001
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: EEE_TEST_CTRL_C
 ***************************************************************************/
/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_RX_EN [15:15] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x8000,15,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x8000,15)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_MASK        0x8000
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_ALIGN       0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_BITS        1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_SHIFT       15

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_TX_EN [14:14] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x4000,14,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x4000,14)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_MASK        0x4000
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_ALIGN       0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_BITS        1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_SHIFT       14

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_RX_EN [13:13] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x2000,13,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x2000,13)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_MASK            0x2000
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_ALIGN           0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_BITS            1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_SHIFT           13

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_TX_EN [12:12] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x1000,12,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x1000,12)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_MASK            0x1000
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_ALIGN           0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_BITS            1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_SHIFT           12

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_RX_EN [11:11] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x800,11,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x800,11)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_MASK        0x0800
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_ALIGN       0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_BITS        1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_SHIFT       11

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_TX_EN [10:10] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x400,10,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x400,10)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_MASK        0x0400
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_ALIGN       0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_BITS        1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_SHIFT       10

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_RX_EN [09:09] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x200,9,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x200,9)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_MASK            0x0200
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_ALIGN           0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_BITS            1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_SHIFT           9

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_TX_EN [08:08] */
#define Wr_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x100,8,x)
#define Rd_BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_TEST_CTRL_C,0x100,8)
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_MASK            0x0100
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_ALIGN           0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_BITS            1
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_SHIFT           8

/* BRPHY2_CL45VEN :: EEE_TEST_CTRL_C :: reserved0 [07:00] */
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_MASK              0x00ff
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_BITS              8
#define BRPHY2_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_SHIFT             0


/****************************************************************************
 * BRPHY2_CL45VEN :: EEE_SPARE_1
 ***************************************************************************/
/* BRPHY2_CL45VEN :: EEE_SPARE_1 :: SPARE [15:00] */
#define Wr_BRPHY2_CL45VEN_EEE_SPARE_1_SPARE(x) WriteReg16(BRPHY2_CL45VEN_EEE_SPARE_1,x)
#define Rd_BRPHY2_CL45VEN_EEE_SPARE_1_SPARE(x) ReadReg16(BRPHY2_CL45VEN_EEE_SPARE_1)
#define BRPHY2_CL45VEN_EEE_SPARE_1_SPARE_MASK                      0xffff
#define BRPHY2_CL45VEN_EEE_SPARE_1_SPARE_ALIGN                     0
#define BRPHY2_CL45VEN_EEE_SPARE_1_SPARE_BITS                      16
#define BRPHY2_CL45VEN_EEE_SPARE_1_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY2_CL45VEN :: EEE_SPARE_2
 ***************************************************************************/
/* BRPHY2_CL45VEN :: EEE_SPARE_2 :: SPARE [15:00] */
#define Wr_BRPHY2_CL45VEN_EEE_SPARE_2_SPARE(x) WriteReg16(BRPHY2_CL45VEN_EEE_SPARE_2,x)
#define Rd_BRPHY2_CL45VEN_EEE_SPARE_2_SPARE(x) ReadReg16(BRPHY2_CL45VEN_EEE_SPARE_2)
#define BRPHY2_CL45VEN_EEE_SPARE_2_SPARE_MASK                      0xffff
#define BRPHY2_CL45VEN_EEE_SPARE_2_SPARE_ALIGN                     0
#define BRPHY2_CL45VEN_EEE_SPARE_2_SPARE_BITS                      16
#define BRPHY2_CL45VEN_EEE_SPARE_2_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY2_CL45VEN :: EEE_CONTROL
 ***************************************************************************/
/* BRPHY2_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x8000,15,x)
#define Rd_BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x8000,15)
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_MASK             0x8000
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_ALIGN            0
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_BITS             1
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_SHIFT            15

/* BRPHY2_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x4000,14,x)
#define Rd_BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x4000,14)
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_MASK    0x4000
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_ALIGN   0
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_BITS    1
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_SHIFT   14

/* BRPHY2_CL45VEN :: EEE_CONTROL :: LPI_RES_IN_FORCE_MODE_EN [13:13] */
#define Wr_BRPHY2_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x2000,13,x)
#define Rd_BRPHY2_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x2000,13)
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_MASK   0x2000
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_ALIGN  0
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_BITS   1
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_SHIFT  13

/* BRPHY2_CL45VEN :: EEE_CONTROL :: SPARE [12:03] */
#define Wr_BRPHY2_CL45VEN_EEE_CONTROL_SPARE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x1ff8,3,x)
#define Rd_BRPHY2_CL45VEN_EEE_CONTROL_SPARE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x1ff8,3)
#define BRPHY2_CL45VEN_EEE_CONTROL_SPARE_MASK                      0x1ff8
#define BRPHY2_CL45VEN_EEE_CONTROL_SPARE_ALIGN                     0
#define BRPHY2_CL45VEN_EEE_CONTROL_SPARE_BITS                      10
#define BRPHY2_CL45VEN_EEE_CONTROL_SPARE_SHIFT                     3

/* BRPHY2_CL45VEN :: EEE_CONTROL :: LPI_LINKUP_DISABLE [02:02] */
#define Wr_BRPHY2_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x4,2,x)
#define Rd_BRPHY2_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x4,2)
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_MASK         0x0004
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_ALIGN        0
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_BITS         1
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_SHIFT        2

/* BRPHY2_CL45VEN :: EEE_CONTROL :: EEE_DOWNGRADE_ENABLE [01:01] */
#define Wr_BRPHY2_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x2,1,x)
#define Rd_BRPHY2_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x2,1)
#define BRPHY2_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_MASK       0x0002
#define BRPHY2_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_ALIGN      0
#define BRPHY2_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_BITS       1
#define BRPHY2_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_SHIFT      1

/* BRPHY2_CL45VEN :: EEE_CONTROL :: LPI_100TX_BRCM_LINK [00:00] */
#define Wr_BRPHY2_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x1,0,x)
#define Rd_BRPHY2_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_CONTROL,0x1,0)
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_MASK        0x0001
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_ALIGN       0
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_BITS        1
#define BRPHY2_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_SHIFT       0


/****************************************************************************
 * BRPHY2_CL45VEN :: EEE_RES_STAT
 ***************************************************************************/
/* BRPHY2_CL45VEN :: EEE_RES_STAT :: reserved0 [15:07] */
#define BRPHY2_CL45VEN_EEE_RES_STAT_RESERVED0_MASK                 0xff80
#define BRPHY2_CL45VEN_EEE_RES_STAT_RESERVED0_ALIGN                0
#define BRPHY2_CL45VEN_EEE_RES_STAT_RESERVED0_BITS                 9
#define BRPHY2_CL45VEN_EEE_RES_STAT_RESERVED0_SHIFT                7

/* BRPHY2_CL45VEN :: EEE_RES_STAT :: MASK_1000T_EEE [06:06] */
#define Wr_BRPHY2_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x40,6,x)
#define Rd_BRPHY2_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x40,6)
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_MASK            0x0040
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_ALIGN           0
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_BITS            1
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_SHIFT           6

/* BRPHY2_CL45VEN :: EEE_RES_STAT :: MASK_100TX_EEE [05:05] */
#define Wr_BRPHY2_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x20,5,x)
#define Rd_BRPHY2_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x20,5)
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_MASK            0x0020
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_ALIGN           0
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_BITS            1
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_SHIFT           5

/* BRPHY2_CL45VEN :: EEE_RES_STAT :: MASK_10T_EEE [04:04] */
#define Wr_BRPHY2_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x10,4,x)
#define Rd_BRPHY2_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x10,4)
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_MASK              0x0010
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_ALIGN             0
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_BITS              1
#define BRPHY2_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_SHIFT             4

/* BRPHY2_CL45VEN :: EEE_RES_STAT :: reserved1 [03:03] */
#define BRPHY2_CL45VEN_EEE_RES_STAT_RESERVED1_MASK                 0x0008
#define BRPHY2_CL45VEN_EEE_RES_STAT_RESERVED1_ALIGN                0
#define BRPHY2_CL45VEN_EEE_RES_STAT_RESERVED1_BITS                 1
#define BRPHY2_CL45VEN_EEE_RES_STAT_RESERVED1_SHIFT                3

/* BRPHY2_CL45VEN :: EEE_RES_STAT :: EEE_1000T_RES [02:02] */
#define Wr_BRPHY2_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x4,2,x)
#define Rd_BRPHY2_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x4,2)
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_MASK             0x0004
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_ALIGN            0
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_BITS             1
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_SHIFT            2

/* BRPHY2_CL45VEN :: EEE_RES_STAT :: EEE_100TX_RES [01:01] */
#define Wr_BRPHY2_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x2,1,x)
#define Rd_BRPHY2_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x2,1)
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_MASK             0x0002
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_ALIGN            0
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_BITS             1
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_SHIFT            1

/* BRPHY2_CL45VEN :: EEE_RES_STAT :: EEE_10BASE_TE_RES [00:00] */
#define Wr_BRPHY2_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) WriteRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x1,0,x)
#define Rd_BRPHY2_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) ReadRegBits16(BRPHY2_CL45VEN_EEE_RES_STAT,0x1,0)
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_MASK         0x0001
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_ALIGN        0
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_BITS         1
#define BRPHY2_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_SHIFT        0


/****************************************************************************
 * BRPHY2_CL45VEN :: LPI_MODE_CNTR
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LPI_MODE_CNTR :: LPI_MODE_COUNTER [15:00] */
#define Wr_BRPHY2_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) WriteReg16(BRPHY2_CL45VEN_LPI_MODE_CNTR,x)
#define Rd_BRPHY2_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) ReadReg16(BRPHY2_CL45VEN_LPI_MODE_CNTR)
#define BRPHY2_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_MASK         0xffff
#define BRPHY2_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_ALIGN        0
#define BRPHY2_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_BITS         16
#define BRPHY2_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_SHIFT        0


/****************************************************************************
 * BRPHY2_CL45VEN :: LOC_DEV_MSG_5_A
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LOC_DEV_MSG_5_A :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_MASK              0xf800
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_BITS              5
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_SHIFT             11

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_5_A :: BITS_10_0_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LOC_DEV_MSG_5_B
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LOC_DEV_MSG_5_B :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_MASK              0xf800
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_BITS              5
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_SHIFT             11

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_5_B :: BITS_21_11_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LOC_DEV_MSG_5_C
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LOC_DEV_MSG_5_C :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_MASK              0xf800
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_BITS              5
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_SHIFT             11

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_5_C :: BITS_32_22_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LOC_DEV_MSG_5_D
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LOC_DEV_MSG_5_D :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_MASK              0xf800
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_BITS              5
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_SHIFT             11

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_5_D :: BITS_43_33_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY2_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_A
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_A :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_MASK           0xf800
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_ALIGN          0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_BITS           5
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_SHIFT          11

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_A :: BITS_10_0_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_B
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_B :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_MASK           0xf800
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_ALIGN          0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_BITS           5
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_SHIFT          11

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_B :: BITS_21_11_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_C
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_C :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_MASK           0xf800
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_ALIGN          0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_BITS           5
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_SHIFT          11

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_C :: BITS_32_22_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_D
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_D :: MSG_5_OUI_MATCH [15:15] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_MASK     0x8000
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_ALIGN    0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_BITS     1
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_SHIFT    15

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_D :: reserved0 [14:11] */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_MASK           0x7800
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_ALIGN          0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_BITS           4
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_SHIFT          11

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_5_D :: BITS_43_33_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LOC_DEV_MSG_6_A
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_A :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_MASK              0xf800
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_BITS              5
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_SHIFT             11

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_A :: BITS_10_0_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LOC_DEV_MSG_6_B
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_B :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_MASK              0xf800
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_BITS              5
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_SHIFT             11

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_21_17_OF_LOC_DEV_MSG_6 [10:06] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_MASK 0x07c0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_BITS 5
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_SHIFT 6

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_16_11_OF_LOC_DEV_MSG_6 [05:00] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_MASK 0x003f
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_BITS 6
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LOC_DEV_MSG_6_C
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_C :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_MASK              0xf800
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_BITS              5
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_SHIFT             11

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_32_23_OF_LOC_DEV_MSG_6 [10:01] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_MASK 0x07fe
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_BITS 10
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_SHIFT 1

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_22_22_OF_LOC_DEV_MSG_6 [00:00] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_C,0x1,0,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_C,0x1,0)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_MASK 0x0001
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_BITS 1
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LOC_DEV_MSG_6_D
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_D :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_MASK              0xf800
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_ALIGN             0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_BITS              5
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_SHIFT             11

/* BRPHY2_CL45VEN :: LOC_DEV_MSG_6_D :: BITS_43_33_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0)
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY2_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_A
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_A :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_MASK           0xf800
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_ALIGN          0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_BITS           5
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_SHIFT          11

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_A :: BITS_10_0_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_B
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_B :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_MASK           0xf800
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_ALIGN          0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_BITS           5
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_SHIFT          11

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_B :: BITS_21_11_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_C
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_C :: reserved0 [15:11] */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_MASK           0xf800
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_ALIGN          0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_BITS           5
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_SHIFT          11

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_C :: BITS_32_22_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_D
 ***************************************************************************/
/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_OUI_MATCH [15:15] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_MASK     0x8000
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_ALIGN    0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_BITS     1
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_SHIFT    15

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_MODEL_MATCH [14:14] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_MASK   0x4000
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_ALIGN  0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_BITS   1
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_SHIFT  14

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_REV_MATCH [13:13] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_MASK     0x2000
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_ALIGN    0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_BITS     1
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_SHIFT    13

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_D :: reserved0 [12:11] */
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_MASK           0x1800
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_ALIGN          0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_BITS           2
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_SHIFT          11

/* BRPHY2_CL45VEN :: LNK_PARTNR_MSG_6_D :: BITS_43_33_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0)
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY2_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_GPHY_CORE
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE10
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE10 :: MAC_PHY_IF [15:15] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_MAC_PHY_IF(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_MAC_PHY_IF(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x8000,15)
#define BRPHY2_GPHY_CORE_BASE10_MAC_PHY_IF_MASK                    0x8000
#define BRPHY2_GPHY_CORE_BASE10_MAC_PHY_IF_ALIGN                   0
#define BRPHY2_GPHY_CORE_BASE10_MAC_PHY_IF_BITS                    1
#define BRPHY2_GPHY_CORE_BASE10_MAC_PHY_IF_SHIFT                   15

/* BRPHY2_GPHY_CORE :: BASE10 :: AUTO_MDIX_DIS [14:14] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x4000,14)
#define BRPHY2_GPHY_CORE_BASE10_AUTO_MDIX_DIS_MASK                 0x4000
#define BRPHY2_GPHY_CORE_BASE10_AUTO_MDIX_DIS_ALIGN                0
#define BRPHY2_GPHY_CORE_BASE10_AUTO_MDIX_DIS_BITS                 1
#define BRPHY2_GPHY_CORE_BASE10_AUTO_MDIX_DIS_SHIFT                14

/* BRPHY2_GPHY_CORE :: BASE10 :: TX_DIS [13:13] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_TX_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_TX_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x2000,13)
#define BRPHY2_GPHY_CORE_BASE10_TX_DIS_MASK                        0x2000
#define BRPHY2_GPHY_CORE_BASE10_TX_DIS_ALIGN                       0
#define BRPHY2_GPHY_CORE_BASE10_TX_DIS_BITS                        1
#define BRPHY2_GPHY_CORE_BASE10_TX_DIS_SHIFT                       13

/* BRPHY2_GPHY_CORE :: BASE10 :: INT_DIS [12:12] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_INT_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_INT_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x1000,12)
#define BRPHY2_GPHY_CORE_BASE10_INT_DIS_MASK                       0x1000
#define BRPHY2_GPHY_CORE_BASE10_INT_DIS_ALIGN                      0
#define BRPHY2_GPHY_CORE_BASE10_INT_DIS_BITS                       1
#define BRPHY2_GPHY_CORE_BASE10_INT_DIS_SHIFT                      12

/* BRPHY2_GPHY_CORE :: BASE10 :: FORCE_INT [11:11] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_FORCE_INT(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_FORCE_INT(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x800,11)
#define BRPHY2_GPHY_CORE_BASE10_FORCE_INT_MASK                     0x0800
#define BRPHY2_GPHY_CORE_BASE10_FORCE_INT_ALIGN                    0
#define BRPHY2_GPHY_CORE_BASE10_FORCE_INT_BITS                     1
#define BRPHY2_GPHY_CORE_BASE10_FORCE_INT_SHIFT                    11

/* BRPHY2_GPHY_CORE :: BASE10 :: BYPASS_ENCODER [10:10] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_BYPASS_ENCODER(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_BYPASS_ENCODER(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x400,10)
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_ENCODER_MASK                0x0400
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_ENCODER_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_ENCODER_BITS                1
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_ENCODER_SHIFT               10

/* BRPHY2_GPHY_CORE :: BASE10 :: BYPASS_SCRAMBLER [09:09] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x200,9)
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_MASK              0x0200
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_ALIGN             0
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_BITS              1
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_SHIFT             9

/* BRPHY2_GPHY_CORE :: BASE10 :: BYPASS_NRZI_MLT3 [08:08] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x100,8)
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_MASK              0x0100
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_ALIGN             0
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_BITS              1
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_SHIFT             8

/* BRPHY2_GPHY_CORE :: BASE10 :: BYPASS_ALIGNMENT [07:07] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x80,7)
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_MASK              0x0080
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_ALIGN             0
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_BITS              1
#define BRPHY2_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_SHIFT             7

/* BRPHY2_GPHY_CORE :: BASE10 :: RESET_SCRAMBLER [06:06] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x40,6)
#define BRPHY2_GPHY_CORE_BASE10_RESET_SCRAMBLER_MASK               0x0040
#define BRPHY2_GPHY_CORE_BASE10_RESET_SCRAMBLER_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE10_RESET_SCRAMBLER_BITS               1
#define BRPHY2_GPHY_CORE_BASE10_RESET_SCRAMBLER_SHIFT              6

/* BRPHY2_GPHY_CORE :: BASE10 :: LED_TRAFFIC_EN [05:05] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x20,5)
#define BRPHY2_GPHY_CORE_BASE10_LED_TRAFFIC_EN_MASK                0x0020
#define BRPHY2_GPHY_CORE_BASE10_LED_TRAFFIC_EN_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE10_LED_TRAFFIC_EN_BITS                1
#define BRPHY2_GPHY_CORE_BASE10_LED_TRAFFIC_EN_SHIFT               5

/* BRPHY2_GPHY_CORE :: BASE10 :: FORCE_LEDS_ON [04:04] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x10,4)
#define BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_ON_MASK                 0x0010
#define BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_ON_ALIGN                0
#define BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_ON_BITS                 1
#define BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_ON_SHIFT                4

/* BRPHY2_GPHY_CORE :: BASE10 :: FORCE_LEDS_OFF [03:03] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x8,3)
#define BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_OFF_MASK                0x0008
#define BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_OFF_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_OFF_BITS                1
#define BRPHY2_GPHY_CORE_BASE10_FORCE_LEDS_OFF_SHIFT               3

/* BRPHY2_GPHY_CORE :: BASE10 :: BLOCK_TXEN [02:02] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_BLOCK_TXEN(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_BLOCK_TXEN(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x4,2)
#define BRPHY2_GPHY_CORE_BASE10_BLOCK_TXEN_MASK                    0x0004
#define BRPHY2_GPHY_CORE_BASE10_BLOCK_TXEN_ALIGN                   0
#define BRPHY2_GPHY_CORE_BASE10_BLOCK_TXEN_BITS                    1
#define BRPHY2_GPHY_CORE_BASE10_BLOCK_TXEN_SHIFT                   2

/* BRPHY2_GPHY_CORE :: BASE10 :: UNIDIR_EN [01:01] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_UNIDIR_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_UNIDIR_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x2,1)
#define BRPHY2_GPHY_CORE_BASE10_UNIDIR_EN_MASK                     0x0002
#define BRPHY2_GPHY_CORE_BASE10_UNIDIR_EN_ALIGN                    0
#define BRPHY2_GPHY_CORE_BASE10_UNIDIR_EN_BITS                     1
#define BRPHY2_GPHY_CORE_BASE10_UNIDIR_EN_SHIFT                    1

/* BRPHY2_GPHY_CORE :: BASE10 :: GMII_RGMII_FIFO_ELASTICITY [00:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE10,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE10,0x1,0)
#define BRPHY2_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_MASK    0x0001
#define BRPHY2_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_ALIGN   0
#define BRPHY2_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_BITS    1
#define BRPHY2_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_SHIFT   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE11
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE11 :: AUTONEG_FIELD_MISMATCH [15:15] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x8000,15)
#define BRPHY2_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_MASK        0x8000
#define BRPHY2_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_ALIGN       0
#define BRPHY2_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_BITS        1
#define BRPHY2_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_SHIFT       15

/* BRPHY2_GPHY_CORE :: BASE11 :: WIRESPD_DOWNGRADE [14:14] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x4000,14)
#define BRPHY2_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_MASK             0x4000
#define BRPHY2_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_ALIGN            0
#define BRPHY2_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_BITS             1
#define BRPHY2_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_SHIFT            14

/* BRPHY2_GPHY_CORE :: BASE11 :: MDIX_STATE [13:13] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_MDIX_STATE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_MDIX_STATE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x2000,13)
#define BRPHY2_GPHY_CORE_BASE11_MDIX_STATE_MASK                    0x2000
#define BRPHY2_GPHY_CORE_BASE11_MDIX_STATE_ALIGN                   0
#define BRPHY2_GPHY_CORE_BASE11_MDIX_STATE_BITS                    1
#define BRPHY2_GPHY_CORE_BASE11_MDIX_STATE_SHIFT                   13

/* BRPHY2_GPHY_CORE :: BASE11 :: INT_STATUS [12:12] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_INT_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_INT_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x1000,12)
#define BRPHY2_GPHY_CORE_BASE11_INT_STATUS_MASK                    0x1000
#define BRPHY2_GPHY_CORE_BASE11_INT_STATUS_ALIGN                   0
#define BRPHY2_GPHY_CORE_BASE11_INT_STATUS_BITS                    1
#define BRPHY2_GPHY_CORE_BASE11_INT_STATUS_SHIFT                   12

/* BRPHY2_GPHY_CORE :: BASE11 :: RMT_RCVR_STATUS [11:11] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x800,11)
#define BRPHY2_GPHY_CORE_BASE11_RMT_RCVR_STATUS_MASK               0x0800
#define BRPHY2_GPHY_CORE_BASE11_RMT_RCVR_STATUS_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE11_RMT_RCVR_STATUS_BITS               1
#define BRPHY2_GPHY_CORE_BASE11_RMT_RCVR_STATUS_SHIFT              11

/* BRPHY2_GPHY_CORE :: BASE11 :: LOCAL_RCVR_STATUS [10:10] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x400,10)
#define BRPHY2_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_MASK             0x0400
#define BRPHY2_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_ALIGN            0
#define BRPHY2_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_BITS             1
#define BRPHY2_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_SHIFT            10

/* BRPHY2_GPHY_CORE :: BASE11 :: LOCKED [09:09] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_LOCKED(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_LOCKED(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x200,9)
#define BRPHY2_GPHY_CORE_BASE11_LOCKED_MASK                        0x0200
#define BRPHY2_GPHY_CORE_BASE11_LOCKED_ALIGN                       0
#define BRPHY2_GPHY_CORE_BASE11_LOCKED_BITS                        1
#define BRPHY2_GPHY_CORE_BASE11_LOCKED_SHIFT                       9

/* BRPHY2_GPHY_CORE :: BASE11 :: LINK_STATUS [08:08] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_LINK_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_LINK_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x100,8)
#define BRPHY2_GPHY_CORE_BASE11_LINK_STATUS_MASK                   0x0100
#define BRPHY2_GPHY_CORE_BASE11_LINK_STATUS_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE11_LINK_STATUS_BITS                   1
#define BRPHY2_GPHY_CORE_BASE11_LINK_STATUS_SHIFT                  8

/* BRPHY2_GPHY_CORE :: BASE11 :: CRC_ERR_DET [07:07] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_CRC_ERR_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_CRC_ERR_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x80,7)
#define BRPHY2_GPHY_CORE_BASE11_CRC_ERR_DET_MASK                   0x0080
#define BRPHY2_GPHY_CORE_BASE11_CRC_ERR_DET_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE11_CRC_ERR_DET_BITS                   1
#define BRPHY2_GPHY_CORE_BASE11_CRC_ERR_DET_SHIFT                  7

/* BRPHY2_GPHY_CORE :: BASE11 :: CR_EXT_ERR_DET [06:06] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x40,6)
#define BRPHY2_GPHY_CORE_BASE11_CR_EXT_ERR_DET_MASK                0x0040
#define BRPHY2_GPHY_CORE_BASE11_CR_EXT_ERR_DET_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE11_CR_EXT_ERR_DET_BITS                1
#define BRPHY2_GPHY_CORE_BASE11_CR_EXT_ERR_DET_SHIFT               6

/* BRPHY2_GPHY_CORE :: BASE11 :: BAD_SSD_DET_CR [05:05] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x20,5)
#define BRPHY2_GPHY_CORE_BASE11_BAD_SSD_DET_CR_MASK                0x0020
#define BRPHY2_GPHY_CORE_BASE11_BAD_SSD_DET_CR_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE11_BAD_SSD_DET_CR_BITS                1
#define BRPHY2_GPHY_CORE_BASE11_BAD_SSD_DET_CR_SHIFT               5

/* BRPHY2_GPHY_CORE :: BASE11 :: BAD_ESD_DET_END [04:04] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x10,4)
#define BRPHY2_GPHY_CORE_BASE11_BAD_ESD_DET_END_MASK               0x0010
#define BRPHY2_GPHY_CORE_BASE11_BAD_ESD_DET_END_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE11_BAD_ESD_DET_END_BITS               1
#define BRPHY2_GPHY_CORE_BASE11_BAD_ESD_DET_END_SHIFT              4

/* BRPHY2_GPHY_CORE :: BASE11 :: RCV_ERR_DET [03:03] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_RCV_ERR_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_RCV_ERR_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x8,3)
#define BRPHY2_GPHY_CORE_BASE11_RCV_ERR_DET_MASK                   0x0008
#define BRPHY2_GPHY_CORE_BASE11_RCV_ERR_DET_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE11_RCV_ERR_DET_BITS                   1
#define BRPHY2_GPHY_CORE_BASE11_RCV_ERR_DET_SHIFT                  3

/* BRPHY2_GPHY_CORE :: BASE11 :: TX_ERR_DET [02:02] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_TX_ERR_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_TX_ERR_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x4,2)
#define BRPHY2_GPHY_CORE_BASE11_TX_ERR_DET_MASK                    0x0004
#define BRPHY2_GPHY_CORE_BASE11_TX_ERR_DET_ALIGN                   0
#define BRPHY2_GPHY_CORE_BASE11_TX_ERR_DET_BITS                    1
#define BRPHY2_GPHY_CORE_BASE11_TX_ERR_DET_SHIFT                   2

/* BRPHY2_GPHY_CORE :: BASE11 :: LOCK_ERR_DET [01:01] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_LOCK_ERR_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_LOCK_ERR_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x2,1)
#define BRPHY2_GPHY_CORE_BASE11_LOCK_ERR_DET_MASK                  0x0002
#define BRPHY2_GPHY_CORE_BASE11_LOCK_ERR_DET_ALIGN                 0
#define BRPHY2_GPHY_CORE_BASE11_LOCK_ERR_DET_BITS                  1
#define BRPHY2_GPHY_CORE_BASE11_LOCK_ERR_DET_SHIFT                 1

/* BRPHY2_GPHY_CORE :: BASE11 :: MLT3_ERR_DET [00:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE11_MLT3_ERR_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE11,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE11_MLT3_ERR_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE11,0x1,0)
#define BRPHY2_GPHY_CORE_BASE11_MLT3_ERR_DET_MASK                  0x0001
#define BRPHY2_GPHY_CORE_BASE11_MLT3_ERR_DET_ALIGN                 0
#define BRPHY2_GPHY_CORE_BASE11_MLT3_ERR_DET_BITS                  1
#define BRPHY2_GPHY_CORE_BASE11_MLT3_ERR_DET_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE12
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE12 :: RCV_ERR_CNTR [15:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) WriteReg16(BRPHY2_GPHY_CORE_BASE12,x)
#define Rd_BRPHY2_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) ReadReg16(BRPHY2_GPHY_CORE_BASE12)
#define BRPHY2_GPHY_CORE_BASE12_RCV_ERR_CNTR_MASK                  0xffff
#define BRPHY2_GPHY_CORE_BASE12_RCV_ERR_CNTR_ALIGN                 0
#define BRPHY2_GPHY_CORE_BASE12_RCV_ERR_CNTR_BITS                  16
#define BRPHY2_GPHY_CORE_BASE12_RCV_ERR_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE13
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE13 :: SERDES_BER_CNTR [15:08] */
#define Wr_BRPHY2_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE13,0xff00,8,x)
#define Rd_BRPHY2_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE13,0xff00,8)
#define BRPHY2_GPHY_CORE_BASE13_SERDES_BER_CNTR_MASK               0xff00
#define BRPHY2_GPHY_CORE_BASE13_SERDES_BER_CNTR_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE13_SERDES_BER_CNTR_BITS               8
#define BRPHY2_GPHY_CORE_BASE13_SERDES_BER_CNTR_SHIFT              8

/* BRPHY2_GPHY_CORE :: BASE13 :: FALSE_CRS_CNTR [07:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE13,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE13,0xff,0)
#define BRPHY2_GPHY_CORE_BASE13_FALSE_CRS_CNTR_MASK                0x00ff
#define BRPHY2_GPHY_CORE_BASE13_FALSE_CRS_CNTR_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE13_FALSE_CRS_CNTR_BITS                8
#define BRPHY2_GPHY_CORE_BASE13_FALSE_CRS_CNTR_SHIFT               0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE14
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE14 :: LOCAL_RCVR_NOK_CNTR [15:08] */
#define Wr_BRPHY2_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE14,0xff00,8,x)
#define Rd_BRPHY2_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE14,0xff00,8)
#define BRPHY2_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_MASK           0xff00
#define BRPHY2_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_ALIGN          0
#define BRPHY2_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_BITS           8
#define BRPHY2_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_SHIFT          8

/* BRPHY2_GPHY_CORE :: BASE14 :: REMOTE_RCVR_NOK_CNTR [07:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE14,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE14,0xff,0)
#define BRPHY2_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_MASK          0x00ff
#define BRPHY2_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_ALIGN         0
#define BRPHY2_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_BITS          8
#define BRPHY2_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_SHIFT         0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP45
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP45 :: SEL_SERDES_TX [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXP45_SEL_SERDES_TX(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP45,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXP45_SEL_SERDES_TX(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP45,0x8000,15)
#define BRPHY2_GPHY_CORE_EXP45_SEL_SERDES_TX_MASK                  0x8000
#define BRPHY2_GPHY_CORE_EXP45_SEL_SERDES_TX_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP45_SEL_SERDES_TX_BITS                  1
#define BRPHY2_GPHY_CORE_EXP45_SEL_SERDES_TX_SHIFT                 15

/* BRPHY2_GPHY_CORE :: EXP45 :: TX_ERR [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXP45_TX_ERR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP45,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXP45_TX_ERR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP45,0x4000,14)
#define BRPHY2_GPHY_CORE_EXP45_TX_ERR_MASK                         0x4000
#define BRPHY2_GPHY_CORE_EXP45_TX_ERR_ALIGN                        0
#define BRPHY2_GPHY_CORE_EXP45_TX_ERR_BITS                         1
#define BRPHY2_GPHY_CORE_EXP45_TX_ERR_SHIFT                        14

/* BRPHY2_GPHY_CORE :: EXP45 :: SKIP_CRC [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXP45_SKIP_CRC(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP45,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXP45_SKIP_CRC(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP45,0x2000,13)
#define BRPHY2_GPHY_CORE_EXP45_SKIP_CRC_MASK                       0x2000
#define BRPHY2_GPHY_CORE_EXP45_SKIP_CRC_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP45_SKIP_CRC_BITS                       1
#define BRPHY2_GPHY_CORE_EXP45_SKIP_CRC_SHIFT                      13

/* BRPHY2_GPHY_CORE :: EXP45 :: TX_CRC_CHECKER_EN [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP45,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP45,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_MASK              0x1000
#define BRPHY2_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_BITS              1
#define BRPHY2_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_SHIFT             12

/* BRPHY2_GPHY_CORE :: EXP45 :: IPG_SEL [11:09] */
#define Wr_BRPHY2_GPHY_CORE_EXP45_IPG_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP45,0xe00,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXP45_IPG_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP45,0xe00,9)
#define BRPHY2_GPHY_CORE_EXP45_IPG_SEL_MASK                        0x0e00
#define BRPHY2_GPHY_CORE_EXP45_IPG_SEL_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP45_IPG_SEL_BITS                        3
#define BRPHY2_GPHY_CORE_EXP45_IPG_SEL_SHIFT                       9

/* BRPHY2_GPHY_CORE :: EXP45 :: PKT_SIZE [08:03] */
#define Wr_BRPHY2_GPHY_CORE_EXP45_PKT_SIZE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP45,0x1f8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXP45_PKT_SIZE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP45,0x1f8,3)
#define BRPHY2_GPHY_CORE_EXP45_PKT_SIZE_MASK                       0x01f8
#define BRPHY2_GPHY_CORE_EXP45_PKT_SIZE_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP45_PKT_SIZE_BITS                       6
#define BRPHY2_GPHY_CORE_EXP45_PKT_SIZE_SHIFT                      3

/* BRPHY2_GPHY_CORE :: EXP45 :: SINGLE_PASS [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP45_SINGLE_PASS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP45,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP45_SINGLE_PASS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP45,0x4,2)
#define BRPHY2_GPHY_CORE_EXP45_SINGLE_PASS_MASK                    0x0004
#define BRPHY2_GPHY_CORE_EXP45_SINGLE_PASS_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP45_SINGLE_PASS_BITS                    1
#define BRPHY2_GPHY_CORE_EXP45_SINGLE_PASS_SHIFT                   2

/* BRPHY2_GPHY_CORE :: EXP45 :: RUN_PAT_GEN [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP45_RUN_PAT_GEN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP45,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP45_RUN_PAT_GEN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP45,0x2,1)
#define BRPHY2_GPHY_CORE_EXP45_RUN_PAT_GEN_MASK                    0x0002
#define BRPHY2_GPHY_CORE_EXP45_RUN_PAT_GEN_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP45_RUN_PAT_GEN_BITS                    1
#define BRPHY2_GPHY_CORE_EXP45_RUN_PAT_GEN_SHIFT                   1

/* BRPHY2_GPHY_CORE :: EXP45 :: SEL_PAT_GEN_DATA [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP45,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP45,0x1,0)
#define BRPHY2_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_MASK               0x0001
#define BRPHY2_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_BITS               1
#define BRPHY2_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP46
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP46 :: GMII_FIFO_ELASTICITY_1 [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP46,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP46,0x8000,15)
#define BRPHY2_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_MASK         0x8000
#define BRPHY2_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_ALIGN        0
#define BRPHY2_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_BITS         1
#define BRPHY2_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_SHIFT        15

/* BRPHY2_GPHY_CORE :: EXP46 :: GMII_RGMII_FIFO_ELASTICITY_1 [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP46,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP46,0x4000,14)
#define BRPHY2_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_MASK   0x4000
#define BRPHY2_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_ALIGN  0
#define BRPHY2_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_BITS   1
#define BRPHY2_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_SHIFT  14

/* BRPHY2_GPHY_CORE :: EXP46 :: PKT_SIZE_6 [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXP46_PKT_SIZE_6(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP46,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXP46_PKT_SIZE_6(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP46,0x2000,13)
#define BRPHY2_GPHY_CORE_EXP46_PKT_SIZE_6_MASK                     0x2000
#define BRPHY2_GPHY_CORE_EXP46_PKT_SIZE_6_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP46_PKT_SIZE_6_BITS                     1
#define BRPHY2_GPHY_CORE_EXP46_PKT_SIZE_6_SHIFT                    13

/* BRPHY2_GPHY_CORE :: EXP46 :: CR_EXT [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP46_CR_EXT(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP46,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP46_CR_EXT(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP46,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP46_CR_EXT_MASK                         0x1000
#define BRPHY2_GPHY_CORE_EXP46_CR_EXT_ALIGN                        0
#define BRPHY2_GPHY_CORE_EXP46_CR_EXT_BITS                         1
#define BRPHY2_GPHY_CORE_EXP46_CR_EXT_SHIFT                        12

/* BRPHY2_GPHY_CORE :: EXP46 :: reserved0 [11:07] */
#define BRPHY2_GPHY_CORE_EXP46_RESERVED0_MASK                      0x0f80
#define BRPHY2_GPHY_CORE_EXP46_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP46_RESERVED0_BITS                      5
#define BRPHY2_GPHY_CORE_EXP46_RESERVED0_SHIFT                     7

/* BRPHY2_GPHY_CORE :: EXP46 :: RGMII_FIFO_FREQ_LOCK [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP46,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP46,0x40,6)
#define BRPHY2_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_MASK           0x0040
#define BRPHY2_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_ALIGN          0
#define BRPHY2_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_BITS           1
#define BRPHY2_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_SHIFT          6

/* BRPHY2_GPHY_CORE :: EXP46 :: reserved1 [05:05] */
#define BRPHY2_GPHY_CORE_EXP46_RESERVED1_MASK                      0x0020
#define BRPHY2_GPHY_CORE_EXP46_RESERVED1_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP46_RESERVED1_BITS                      1
#define BRPHY2_GPHY_CORE_EXP46_RESERVED1_SHIFT                     5

/* BRPHY2_GPHY_CORE :: EXP46 :: SEL_PATGEN_ON_RXD [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP46,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP46,0x10,4)
#define BRPHY2_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_MASK              0x0010
#define BRPHY2_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_BITS              1
#define BRPHY2_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_SHIFT             4

/* BRPHY2_GPHY_CORE :: EXP46 :: PAT_GEN_ACTIVE [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP46,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP46,0x8,3)
#define BRPHY2_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_MASK                 0x0008
#define BRPHY2_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_BITS                 1
#define BRPHY2_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_SHIFT                3

/* BRPHY2_GPHY_CORE :: EXP46 :: PAT_GEN_FSM [02:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP46_PAT_GEN_FSM(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP46,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP46_PAT_GEN_FSM(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP46,0x7,0)
#define BRPHY2_GPHY_CORE_EXP46_PAT_GEN_FSM_MASK                    0x0007
#define BRPHY2_GPHY_CORE_EXP46_PAT_GEN_FSM_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP46_PAT_GEN_FSM_BITS                    3
#define BRPHY2_GPHY_CORE_EXP46_PAT_GEN_FSM_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE19
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE [15:15] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x8000,15)
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_MASK              0x8000
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ALIGN             0
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_BITS              1
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_SHIFT             15

/* BRPHY2_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE_ACK [14:14] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x4000,14)
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_MASK          0x4000
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_ALIGN         0
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_BITS          1
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_SHIFT         14

/* BRPHY2_GPHY_CORE :: BASE19 :: AUTONEG_ACK_DET [13:13] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x2000,13)
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_ACK_DET_MASK               0x2000
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_ACK_DET_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_ACK_DET_BITS               1
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_ACK_DET_SHIFT              13

/* BRPHY2_GPHY_CORE :: BASE19 :: AUTONEG_ABILITY_DET [12:12] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x1000,12)
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_MASK           0x1000
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_ALIGN          0
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_BITS           1
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_SHIFT          12

/* BRPHY2_GPHY_CORE :: BASE19 :: AUTONEG_NEXT_PAGE_WAIT [11:11] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x800,11)
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_MASK        0x0800
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_ALIGN       0
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_BITS        1
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_SHIFT       11

/* BRPHY2_GPHY_CORE :: BASE19 :: AUTONEG_HCD [10:08] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_AUTONEG_HCD(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x700,8,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_AUTONEG_HCD(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x700,8)
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_HCD_MASK                   0x0700
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_HCD_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_HCD_BITS                   3
#define BRPHY2_GPHY_CORE_BASE19_AUTONEG_HCD_SHIFT                  8

/* BRPHY2_GPHY_CORE :: BASE19 :: PARALLEL_DET_FAULT [07:07] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x80,7)
#define BRPHY2_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_MASK            0x0080
#define BRPHY2_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_ALIGN           0
#define BRPHY2_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_BITS            1
#define BRPHY2_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_SHIFT           7

/* BRPHY2_GPHY_CORE :: BASE19 :: REMOTE_FAULT [06:06] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_REMOTE_FAULT(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_REMOTE_FAULT(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x40,6)
#define BRPHY2_GPHY_CORE_BASE19_REMOTE_FAULT_MASK                  0x0040
#define BRPHY2_GPHY_CORE_BASE19_REMOTE_FAULT_ALIGN                 0
#define BRPHY2_GPHY_CORE_BASE19_REMOTE_FAULT_BITS                  1
#define BRPHY2_GPHY_CORE_BASE19_REMOTE_FAULT_SHIFT                 6

/* BRPHY2_GPHY_CORE :: BASE19 :: PAGE_RECEIVED [05:05] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_PAGE_RECEIVED(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_PAGE_RECEIVED(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x20,5)
#define BRPHY2_GPHY_CORE_BASE19_PAGE_RECEIVED_MASK                 0x0020
#define BRPHY2_GPHY_CORE_BASE19_PAGE_RECEIVED_ALIGN                0
#define BRPHY2_GPHY_CORE_BASE19_PAGE_RECEIVED_BITS                 1
#define BRPHY2_GPHY_CORE_BASE19_PAGE_RECEIVED_SHIFT                5

/* BRPHY2_GPHY_CORE :: BASE19 :: LINK_PARTNER_AN_ABILITY [04:04] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x10,4)
#define BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_MASK       0x0010
#define BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_SHIFT      4

/* BRPHY2_GPHY_CORE :: BASE19 :: LINK_PARTNER_NP_ABILITY [03:03] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x8,3)
#define BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_MASK       0x0008
#define BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_ALIGN      0
#define BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_BITS       1
#define BRPHY2_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_SHIFT      3

/* BRPHY2_GPHY_CORE :: BASE19 :: LINK_STATUS [02:02] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_LINK_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_LINK_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x4,2)
#define BRPHY2_GPHY_CORE_BASE19_LINK_STATUS_MASK                   0x0004
#define BRPHY2_GPHY_CORE_BASE19_LINK_STATUS_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE19_LINK_STATUS_BITS                   1
#define BRPHY2_GPHY_CORE_BASE19_LINK_STATUS_SHIFT                  2

/* BRPHY2_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_RX [01:01] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x2,1)
#define BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_MASK           0x0002
#define BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_ALIGN          0
#define BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_BITS           1
#define BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_SHIFT          1

/* BRPHY2_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_TX [00:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE19,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE19,0x1,0)
#define BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_MASK           0x0001
#define BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_ALIGN          0
#define BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_BITS           1
#define BRPHY2_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_SHIFT          0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE1A
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE1A :: IP_STATUS_CHANGE [15:15] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x8000,15)
#define BRPHY2_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_MASK              0x8000
#define BRPHY2_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_ALIGN             0
#define BRPHY2_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_BITS              1
#define BRPHY2_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_SHIFT             15

/* BRPHY2_GPHY_CORE :: BASE1A :: ILLEGAL_PAIR_SWAP [14:14] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x4000,14)
#define BRPHY2_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_MASK             0x4000
#define BRPHY2_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_ALIGN            0
#define BRPHY2_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_BITS             1
#define BRPHY2_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_SHIFT            14

/* BRPHY2_GPHY_CORE :: BASE1A :: MDIX_STATUS_CHANGE [13:13] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x2000,13)
#define BRPHY2_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_MASK            0x2000
#define BRPHY2_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_ALIGN           0
#define BRPHY2_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_BITS            1
#define BRPHY2_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_SHIFT           13

/* BRPHY2_GPHY_CORE :: BASE1A :: EXCEED_HIGH_CNTR_THD [12:12] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x1000,12)
#define BRPHY2_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_MASK          0x1000
#define BRPHY2_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_ALIGN         0
#define BRPHY2_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_BITS          1
#define BRPHY2_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_SHIFT         12

/* BRPHY2_GPHY_CORE :: BASE1A :: EXCEED_LOW_CNTR_THD [11:11] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x800,11)
#define BRPHY2_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_MASK           0x0800
#define BRPHY2_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_ALIGN          0
#define BRPHY2_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_BITS           1
#define BRPHY2_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_SHIFT          11

/* BRPHY2_GPHY_CORE :: BASE1A :: AUTONEG_PAGE_RX [10:10] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x400,10)
#define BRPHY2_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_MASK               0x0400
#define BRPHY2_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_BITS               1
#define BRPHY2_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_SHIFT              10

/* BRPHY2_GPHY_CORE :: BASE1A :: HCD_NO_LINK [09:09] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_HCD_NO_LINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_HCD_NO_LINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x200,9)
#define BRPHY2_GPHY_CORE_BASE1A_HCD_NO_LINK_MASK                   0x0200
#define BRPHY2_GPHY_CORE_BASE1A_HCD_NO_LINK_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE1A_HCD_NO_LINK_BITS                   1
#define BRPHY2_GPHY_CORE_BASE1A_HCD_NO_LINK_SHIFT                  9

/* BRPHY2_GPHY_CORE :: BASE1A :: NO_HCD [08:08] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_NO_HCD(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_NO_HCD(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x100,8)
#define BRPHY2_GPHY_CORE_BASE1A_NO_HCD_MASK                        0x0100
#define BRPHY2_GPHY_CORE_BASE1A_NO_HCD_ALIGN                       0
#define BRPHY2_GPHY_CORE_BASE1A_NO_HCD_BITS                        1
#define BRPHY2_GPHY_CORE_BASE1A_NO_HCD_SHIFT                       8

/* BRPHY2_GPHY_CORE :: BASE1A :: NEGOTIATED_UNSUPPORTED_HCD [07:07] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x80,7)
#define BRPHY2_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_MASK    0x0080
#define BRPHY2_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_ALIGN   0
#define BRPHY2_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_BITS    1
#define BRPHY2_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_SHIFT   7

/* BRPHY2_GPHY_CORE :: BASE1A :: SCR_SYNC_ERROR [06:06] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x40,6)
#define BRPHY2_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_MASK                0x0040
#define BRPHY2_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_BITS                1
#define BRPHY2_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_SHIFT               6

/* BRPHY2_GPHY_CORE :: BASE1A :: RMT_RCVR_STATUS_CHANGE [05:05] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x20,5)
#define BRPHY2_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_MASK        0x0020
#define BRPHY2_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_ALIGN       0
#define BRPHY2_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_BITS        1
#define BRPHY2_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_SHIFT       5

/* BRPHY2_GPHY_CORE :: BASE1A :: LOCAL_RCVR_STATUS_CHANGE [04:04] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x10,4)
#define BRPHY2_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_MASK      0x0010
#define BRPHY2_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_ALIGN     0
#define BRPHY2_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_BITS      1
#define BRPHY2_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_SHIFT     4

/* BRPHY2_GPHY_CORE :: BASE1A :: DUPLEX_CHANGE [03:03] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x8,3)
#define BRPHY2_GPHY_CORE_BASE1A_DUPLEX_CHANGE_MASK                 0x0008
#define BRPHY2_GPHY_CORE_BASE1A_DUPLEX_CHANGE_ALIGN                0
#define BRPHY2_GPHY_CORE_BASE1A_DUPLEX_CHANGE_BITS                 1
#define BRPHY2_GPHY_CORE_BASE1A_DUPLEX_CHANGE_SHIFT                3

/* BRPHY2_GPHY_CORE :: BASE1A :: LINK_SPEED_CHANGE [02:02] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x4,2)
#define BRPHY2_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_MASK             0x0004
#define BRPHY2_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_ALIGN            0
#define BRPHY2_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_BITS             1
#define BRPHY2_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_SHIFT            2

/* BRPHY2_GPHY_CORE :: BASE1A :: LINK_STATUS_CHANGE [01:01] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x2,1)
#define BRPHY2_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_MASK            0x0002
#define BRPHY2_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_ALIGN           0
#define BRPHY2_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_BITS            1
#define BRPHY2_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_SHIFT           1

/* BRPHY2_GPHY_CORE :: BASE1A :: CRC_ERROR [00:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE1A_CRC_ERROR(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1A_CRC_ERROR(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1A,0x1,0)
#define BRPHY2_GPHY_CORE_BASE1A_CRC_ERROR_MASK                     0x0001
#define BRPHY2_GPHY_CORE_BASE1A_CRC_ERROR_ALIGN                    0
#define BRPHY2_GPHY_CORE_BASE1A_CRC_ERROR_BITS                     1
#define BRPHY2_GPHY_CORE_BASE1A_CRC_ERROR_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE1B
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE1B :: INT_MASK_VECTOR [15:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) WriteReg16(BRPHY2_GPHY_CORE_BASE1B,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) ReadReg16(BRPHY2_GPHY_CORE_BASE1B)
#define BRPHY2_GPHY_CORE_BASE1B_INT_MASK_VECTOR_MASK               0xffff
#define BRPHY2_GPHY_CORE_BASE1B_INT_MASK_VECTOR_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE1B_INT_MASK_VECTOR_BITS               16
#define BRPHY2_GPHY_CORE_BASE1B_INT_MASK_VECTOR_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE1D_SHD
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x8000,15)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_MASK    0x8000
#define BRPHY2_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_ALIGN   0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_BITS    1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_SHIFT   15

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: GB_ADV_DIS [14:14] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x4000,14)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_MASK                0x4000
#define BRPHY2_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_BITS                1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_SHIFT               14

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: TX_ADV_DIS [13:13] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x2000,13)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_MASK                0x2000
#define BRPHY2_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_BITS                1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_SHIFT               13

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: WIRESPEED_DOWNGRADE [12:12] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x1000,12)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_MASK       0x1000
#define BRPHY2_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_ALIGN      0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_BITS       1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_SHIFT      12

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX [11:11] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x800,11)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_MASK             0x0800
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_ALIGN            0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_BITS             1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_SHIFT            11

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_1000T [10:10] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x400,10)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_MASK                 0x0400
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_ALIGN                0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_BITS                 1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_SHIFT                10

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX [09:09] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x200,9)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_MASK              0x0200
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_ALIGN             0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_BITS              1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_SHIFT             9

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_100T [08:08] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x100,8)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_MASK                  0x0100
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_ALIGN                 0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_BITS                  1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_SHIFT                 8

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX [07:07] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x80,7)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_MASK               0x0080
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_BITS               1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_SHIFT              7

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_10T [06:06] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x40,6)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_MASK                   0x0040
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_BITS                   1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_SHIFT                  6

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX_NL [05:05] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x20,5)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_MASK          0x0020
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_ALIGN         0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_BITS          1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_SHIFT         5

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_NL [04:04] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x10,4)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_MASK              0x0010
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_ALIGN             0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_BITS              1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_SHIFT             4

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX_NL [03:03] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x8,3)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_MASK           0x0008
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_ALIGN          0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_BITS           1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_SHIFT          3

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_100T_NL [02:02] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x4,2)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_MASK               0x0004
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_BITS               1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_SHIFT              2

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX_NL [01:01] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x2,1)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_MASK            0x0002
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_ALIGN           0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_BITS            1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_SHIFT           1

/* BRPHY2_GPHY_CORE :: BASE1D_SHD :: HCD_10T_NL [00:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D_SHD,0x1,0)
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_MASK                0x0001
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_BITS                1
#define BRPHY2_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_SHIFT               0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE1D
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE1D :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x8000,15)
#define BRPHY2_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_MASK        0x8000
#define BRPHY2_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_ALIGN       0
#define BRPHY2_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_BITS        1
#define BRPHY2_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_SHIFT       15

/* BRPHY2_GPHY_CORE :: BASE1D :: MASTER_SLAVE_SEED_MATCH [14:14] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x4000,14)
#define BRPHY2_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_MASK       0x4000
#define BRPHY2_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_ALIGN      0
#define BRPHY2_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_BITS       1
#define BRPHY2_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_SHIFT      14

/* BRPHY2_GPHY_CORE :: BASE1D :: LINK_PARTNER_RD_BIT [13:13] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x2000,13)
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_MASK           0x2000
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_ALIGN          0
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_BITS           1
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_SHIFT          13

/* BRPHY2_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_VALUE [12:12] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x1000,12)
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_MASK         0x1000
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_ALIGN        0
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_BITS         1
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_SHIFT        12

/* BRPHY2_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_CFG_EN [11:11] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x800,11)
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_MASK        0x0800
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_ALIGN       0
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_BITS        1
#define BRPHY2_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_SHIFT       11

/* BRPHY2_GPHY_CORE :: BASE1D :: LOCAL_MS_SEED_VALUE [10:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x7ff,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1D,0x7ff,0)
#define BRPHY2_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_MASK           0x07ff
#define BRPHY2_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_ALIGN          0
#define BRPHY2_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_BITS           11
#define BRPHY2_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_SHIFT          0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE1E
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE1E :: CRC_ERR_CNT [15:15] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x8000,15)
#define BRPHY2_GPHY_CORE_BASE1E_CRC_ERR_CNT_MASK                   0x8000
#define BRPHY2_GPHY_CORE_BASE1E_CRC_ERR_CNT_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE1E_CRC_ERR_CNT_BITS                   1
#define BRPHY2_GPHY_CORE_BASE1E_CRC_ERR_CNT_SHIFT                  15

/* BRPHY2_GPHY_CORE :: BASE1E :: TX_ERR_CODE [14:14] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_TX_ERR_CODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_TX_ERR_CODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x4000,14)
#define BRPHY2_GPHY_CORE_BASE1E_TX_ERR_CODE_MASK                   0x4000
#define BRPHY2_GPHY_CORE_BASE1E_TX_ERR_CODE_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE1E_TX_ERR_CODE_BITS                   1
#define BRPHY2_GPHY_CORE_BASE1E_TX_ERR_CODE_SHIFT                  14

/* BRPHY2_GPHY_CORE :: BASE1E :: CNTR_TEST [13:13] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_CNTR_TEST(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_CNTR_TEST(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x2000,13)
#define BRPHY2_GPHY_CORE_BASE1E_CNTR_TEST_MASK                     0x2000
#define BRPHY2_GPHY_CORE_BASE1E_CNTR_TEST_ALIGN                    0
#define BRPHY2_GPHY_CORE_BASE1E_CNTR_TEST_BITS                     1
#define BRPHY2_GPHY_CORE_BASE1E_CNTR_TEST_SHIFT                    13

/* BRPHY2_GPHY_CORE :: BASE1E :: FORCE_LINK [12:12] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_FORCE_LINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_FORCE_LINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x1000,12)
#define BRPHY2_GPHY_CORE_BASE1E_FORCE_LINK_MASK                    0x1000
#define BRPHY2_GPHY_CORE_BASE1E_FORCE_LINK_ALIGN                   0
#define BRPHY2_GPHY_CORE_BASE1E_FORCE_LINK_BITS                    1
#define BRPHY2_GPHY_CORE_BASE1E_FORCE_LINK_SHIFT                   12

/* BRPHY2_GPHY_CORE :: BASE1E :: FORCE_LOCK [11:11] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_FORCE_LOCK(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_FORCE_LOCK(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x800,11)
#define BRPHY2_GPHY_CORE_BASE1E_FORCE_LOCK_MASK                    0x0800
#define BRPHY2_GPHY_CORE_BASE1E_FORCE_LOCK_ALIGN                   0
#define BRPHY2_GPHY_CORE_BASE1E_FORCE_LOCK_BITS                    1
#define BRPHY2_GPHY_CORE_BASE1E_FORCE_LOCK_SHIFT                   11

/* BRPHY2_GPHY_CORE :: BASE1E :: SCR_TEST [10:10] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_SCR_TEST(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_SCR_TEST(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x400,10)
#define BRPHY2_GPHY_CORE_BASE1E_SCR_TEST_MASK                      0x0400
#define BRPHY2_GPHY_CORE_BASE1E_SCR_TEST_ALIGN                     0
#define BRPHY2_GPHY_CORE_BASE1E_SCR_TEST_BITS                      1
#define BRPHY2_GPHY_CORE_BASE1E_SCR_TEST_SHIFT                     10

/* BRPHY2_GPHY_CORE :: BASE1E :: EXT_LINK [09:09] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_EXT_LINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_EXT_LINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x200,9)
#define BRPHY2_GPHY_CORE_BASE1E_EXT_LINK_MASK                      0x0200
#define BRPHY2_GPHY_CORE_BASE1E_EXT_LINK_ALIGN                     0
#define BRPHY2_GPHY_CORE_BASE1E_EXT_LINK_BITS                      1
#define BRPHY2_GPHY_CORE_BASE1E_EXT_LINK_SHIFT                     9

/* BRPHY2_GPHY_CORE :: BASE1E :: FAST_TIMERS [08:08] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_FAST_TIMERS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_FAST_TIMERS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x100,8)
#define BRPHY2_GPHY_CORE_BASE1E_FAST_TIMERS_MASK                   0x0100
#define BRPHY2_GPHY_CORE_BASE1E_FAST_TIMERS_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE1E_FAST_TIMERS_BITS                   1
#define BRPHY2_GPHY_CORE_BASE1E_FAST_TIMERS_SHIFT                  8

/* BRPHY2_GPHY_CORE :: BASE1E :: MANUAL_SWAP_MDI [07:07] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x80,7)
#define BRPHY2_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_MASK               0x0080
#define BRPHY2_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_BITS               1
#define BRPHY2_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_SHIFT              7

/* BRPHY2_GPHY_CORE :: BASE1E :: RX_WATCHDOG_TIMER_DIS [06:06] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x40,6)
#define BRPHY2_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_MASK         0x0040
#define BRPHY2_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_ALIGN        0
#define BRPHY2_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_BITS         1
#define BRPHY2_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_SHIFT        6

/* BRPHY2_GPHY_CORE :: BASE1E :: POLARITY_ENCODE_DIS [05:05] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x20,5)
#define BRPHY2_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_MASK           0x0020
#define BRPHY2_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_ALIGN          0
#define BRPHY2_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_BITS           1
#define BRPHY2_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_SHIFT          5

/* BRPHY2_GPHY_CORE :: BASE1E :: SOFT_TRIM_SETTING_EN [04:04] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0x10,4)
#define BRPHY2_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_MASK          0x0010
#define BRPHY2_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_ALIGN         0
#define BRPHY2_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_BITS          1
#define BRPHY2_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_SHIFT         4

/* BRPHY2_GPHY_CORE :: BASE1E :: TRIM_MAIN_DAC [03:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1E,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1E,0xf,0)
#define BRPHY2_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_MASK                 0x000f
#define BRPHY2_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_ALIGN                0
#define BRPHY2_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_BITS                 4
#define BRPHY2_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_SHIFT                0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BASE1F
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BASE1F :: TEST_SEL_AUTONEG_FSM [15:13] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0xe000,13,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0xe000,13)
#define BRPHY2_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_MASK          0xe000
#define BRPHY2_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_ALIGN         0
#define BRPHY2_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_BITS          3
#define BRPHY2_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_SHIFT         13

/* BRPHY2_GPHY_CORE :: BASE1F :: TEST_AUTONEG_TIMER [12:12] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x1000,12)
#define BRPHY2_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_MASK            0x1000
#define BRPHY2_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_ALIGN           0
#define BRPHY2_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_BITS            1
#define BRPHY2_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_SHIFT           12

/* BRPHY2_GPHY_CORE :: BASE1F :: TEST_MS_SEED [11:11] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_TEST_MS_SEED(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_TEST_MS_SEED(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x800,11)
#define BRPHY2_GPHY_CORE_BASE1F_TEST_MS_SEED_MASK                  0x0800
#define BRPHY2_GPHY_CORE_BASE1F_TEST_MS_SEED_ALIGN                 0
#define BRPHY2_GPHY_CORE_BASE1F_TEST_MS_SEED_BITS                  1
#define BRPHY2_GPHY_CORE_BASE1F_TEST_MS_SEED_SHIFT                 11

/* BRPHY2_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_ABILITY_EN [10:10] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x400,10)
#define BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_MASK    0x0400
#define BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_ALIGN   0
#define BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_BITS    1
#define BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_SHIFT   10

/* BRPHY2_GPHY_CORE :: BASE1F :: FORCE_HCD [09:09] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_FORCE_HCD(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_FORCE_HCD(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x200,9)
#define BRPHY2_GPHY_CORE_BASE1F_FORCE_HCD_MASK                     0x0200
#define BRPHY2_GPHY_CORE_BASE1F_FORCE_HCD_ALIGN                    0
#define BRPHY2_GPHY_CORE_BASE1F_FORCE_HCD_BITS                     1
#define BRPHY2_GPHY_CORE_BASE1F_FORCE_HCD_SHIFT                    9

/* BRPHY2_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_MS_SEED_EN [08:08] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x100,8)
#define BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_MASK    0x0100
#define BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_ALIGN   0
#define BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_BITS    1
#define BRPHY2_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_SHIFT   8

/* BRPHY2_GPHY_CORE :: BASE1F :: TX_10B [07:07] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_TX_10B(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_TX_10B(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x80,7)
#define BRPHY2_GPHY_CORE_BASE1F_TX_10B_MASK                        0x0080
#define BRPHY2_GPHY_CORE_BASE1F_TX_10B_ALIGN                       0
#define BRPHY2_GPHY_CORE_BASE1F_TX_10B_BITS                        1
#define BRPHY2_GPHY_CORE_BASE1F_TX_10B_SHIFT                       7

/* BRPHY2_GPHY_CORE :: BASE1F :: RX_10B [06:06] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_RX_10B(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_RX_10B(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x40,6)
#define BRPHY2_GPHY_CORE_BASE1F_RX_10B_MASK                        0x0040
#define BRPHY2_GPHY_CORE_BASE1F_RX_10B_ALIGN                       0
#define BRPHY2_GPHY_CORE_BASE1F_RX_10B_BITS                        1
#define BRPHY2_GPHY_CORE_BASE1F_RX_10B_SHIFT                       6

/* BRPHY2_GPHY_CORE :: BASE1F :: BYPASS_TXFIFO [05:05] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x20,5)
#define BRPHY2_GPHY_CORE_BASE1F_BYPASS_TXFIFO_MASK                 0x0020
#define BRPHY2_GPHY_CORE_BASE1F_BYPASS_TXFIFO_ALIGN                0
#define BRPHY2_GPHY_CORE_BASE1F_BYPASS_TXFIFO_BITS                 1
#define BRPHY2_GPHY_CORE_BASE1F_BYPASS_TXFIFO_SHIFT                5

/* BRPHY2_GPHY_CORE :: BASE1F :: SAME_SCR_SEEDS [04:04] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x10,4)
#define BRPHY2_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_MASK                0x0010
#define BRPHY2_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_BITS                1
#define BRPHY2_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_SHIFT               4

/* BRPHY2_GPHY_CORE :: BASE1F :: JITTER_TEST [03:03] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_JITTER_TEST(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_JITTER_TEST(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x8,3)
#define BRPHY2_GPHY_CORE_BASE1F_JITTER_TEST_MASK                   0x0008
#define BRPHY2_GPHY_CORE_BASE1F_JITTER_TEST_ALIGN                  0
#define BRPHY2_GPHY_CORE_BASE1F_JITTER_TEST_BITS                   1
#define BRPHY2_GPHY_CORE_BASE1F_JITTER_TEST_SHIFT                  3

/* BRPHY2_GPHY_CORE :: BASE1F :: TEST_ATMP_CNTR [02:02] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x4,2)
#define BRPHY2_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_MASK                0x0004
#define BRPHY2_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_ALIGN               0
#define BRPHY2_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_BITS                1
#define BRPHY2_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_SHIFT               2

/* BRPHY2_GPHY_CORE :: BASE1F :: LATENCY_MEASURE [01:01] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x2,1)
#define BRPHY2_GPHY_CORE_BASE1F_LATENCY_MEASURE_MASK               0x0002
#define BRPHY2_GPHY_CORE_BASE1F_LATENCY_MEASURE_ALIGN              0
#define BRPHY2_GPHY_CORE_BASE1F_LATENCY_MEASURE_BITS               1
#define BRPHY2_GPHY_CORE_BASE1F_LATENCY_MEASURE_SHIFT              1

/* BRPHY2_GPHY_CORE :: BASE1F :: ACTIVE_HYBRID_DIS [00:00] */
#define Wr_BRPHY2_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_BASE1F,0x1,0)
#define BRPHY2_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_MASK             0x0001
#define BRPHY2_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_ALIGN            0
#define BRPHY2_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_BITS             1
#define BRPHY2_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_SHIFT            0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_00
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_00 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_00_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_00_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_00_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_00_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_00 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_00,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_00,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_00_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_00_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_00_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_00_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_00 :: reserved1 [09:08] */
#define BRPHY2_GPHY_CORE_SHD1C_00_RESERVED1_MASK                   0x0300
#define BRPHY2_GPHY_CORE_SHD1C_00_RESERVED1_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_00_RESERVED1_BITS                   2
#define BRPHY2_GPHY_CORE_SHD1C_00_RESERVED1_SHIFT                  8

/* BRPHY2_GPHY_CORE :: SHD1C_00 :: CABLETRON_LED [07:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_00,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_00,0xff,0)
#define BRPHY2_GPHY_CORE_SHD1C_00_CABLETRON_LED_MASK               0x00ff
#define BRPHY2_GPHY_CORE_SHD1C_00_CABLETRON_LED_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD1C_00_CABLETRON_LED_BITS               8
#define BRPHY2_GPHY_CORE_SHD1C_00_CABLETRON_LED_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_01
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_01 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_01_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_01_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_01_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_01_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_01 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_01,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_01,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_01_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_01_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_01_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_01_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_01 :: reserved1 [09:07] */
#define BRPHY2_GPHY_CORE_SHD1C_01_RESERVED1_MASK                   0x0380
#define BRPHY2_GPHY_CORE_SHD1C_01_RESERVED1_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_01_RESERVED1_BITS                   3
#define BRPHY2_GPHY_CORE_SHD1C_01_RESERVED1_SHIFT                  7

/* BRPHY2_GPHY_CORE :: SHD1C_01 :: TVCO_OUTPUT [06:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_01,0x7f,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_01,0x7f,0)
#define BRPHY2_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_MASK                 0x007f
#define BRPHY2_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_BITS                 7
#define BRPHY2_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_SHIFT                0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_02
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_02 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_02_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_02_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_02_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_02_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_02_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_02_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_02_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_02_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: SD_STATUS [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_SD_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_SD_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x200,9)
#define BRPHY2_GPHY_CORE_SHD1C_02_SD_STATUS_MASK                   0x0200
#define BRPHY2_GPHY_CORE_SHD1C_02_SD_STATUS_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_02_SD_STATUS_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_02_SD_STATUS_SHIFT                  9

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: FORCE_SD_ON [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x100,8)
#define BRPHY2_GPHY_CORE_SHD1C_02_FORCE_SD_ON_MASK                 0x0100
#define BRPHY2_GPHY_CORE_SHD1C_02_FORCE_SD_ON_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD1C_02_FORCE_SD_ON_BITS                 1
#define BRPHY2_GPHY_CORE_SHD1C_02_FORCE_SD_ON_SHIFT                8

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: INVERT_SD_PIN [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_MASK               0x0080
#define BRPHY2_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_BITS               1
#define BRPHY2_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_SHIFT              7

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: CFC_INITFILTER_EN [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x40,6)
#define BRPHY2_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_MASK           0x0040
#define BRPHY2_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_ALIGN          0
#define BRPHY2_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_BITS           1
#define BRPHY2_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_SHIFT          6

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: USE_FILTERED_SD [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x20,5)
#define BRPHY2_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_MASK             0x0020
#define BRPHY2_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_BITS             1
#define BRPHY2_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_SHIFT            5

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: FX_COPPER_PATH [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x10,4)
#define BRPHY2_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_MASK              0x0010
#define BRPHY2_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_BITS              1
#define BRPHY2_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_SHIFT             4

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: SPARE_REG [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x8,3)
#define BRPHY2_GPHY_CORE_SHD1C_02_SPARE_REG_MASK                   0x0008
#define BRPHY2_GPHY_CORE_SHD1C_02_SPARE_REG_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_02_SPARE_REG_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_02_SPARE_REG_SHIFT                  3

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: BC_LINK_SPEED_LED [02:02] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x4,2)
#define BRPHY2_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_MASK           0x0004
#define BRPHY2_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_ALIGN          0
#define BRPHY2_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_BITS           1
#define BRPHY2_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_SHIFT          2

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: LOST_TOKEN_FIX_DIS [01:01] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x2,1)
#define BRPHY2_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_MASK          0x0002
#define BRPHY2_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_BITS          1
#define BRPHY2_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_SHIFT         1

/* BRPHY2_GPHY_CORE :: SHD1C_02 :: LINK_LED [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_02_LINK_LED(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_02_LINK_LED(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_02,0x1,0)
#define BRPHY2_GPHY_CORE_SHD1C_02_LINK_LED_MASK                    0x0001
#define BRPHY2_GPHY_CORE_SHD1C_02_LINK_LED_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD1C_02_LINK_LED_BITS                    1
#define BRPHY2_GPHY_CORE_SHD1C_02_LINK_LED_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_03
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_03 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_03_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_03_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_03_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_03_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_03 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_03_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_03_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_03_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_03_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_03 :: GTXCLK_DLY_EN [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x200,9)
#define BRPHY2_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_MASK               0x0200
#define BRPHY2_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_BITS               1
#define BRPHY2_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_SHIFT              9

/* BRPHY2_GPHY_CORE :: SHD1C_03 :: GMII_CLK_ALIGN_STRB [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x100,8)
#define BRPHY2_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_MASK         0x0100
#define BRPHY2_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_BITS         1
#define BRPHY2_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_SHIFT        8

/* BRPHY2_GPHY_CORE :: SHD1C_03 :: RXCLK_ALIGN_STRB [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_MASK            0x0080
#define BRPHY2_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_BITS            1
#define BRPHY2_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_SHIFT           7

/* BRPHY2_GPHY_CORE :: SHD1C_03 :: DLY_VALUE [06:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_03_DLY_VALUE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x70,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_03_DLY_VALUE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0x70,4)
#define BRPHY2_GPHY_CORE_SHD1C_03_DLY_VALUE_MASK                   0x0070
#define BRPHY2_GPHY_CORE_SHD1C_03_DLY_VALUE_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_03_DLY_VALUE_BITS                   3
#define BRPHY2_GPHY_CORE_SHD1C_03_DLY_VALUE_SHIFT                  4

/* BRPHY2_GPHY_CORE :: SHD1C_03 :: DLY_LINE_SEL [03:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_03,0xf,0)
#define BRPHY2_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_MASK                0x000f
#define BRPHY2_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_BITS                4
#define BRPHY2_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_SHIFT               0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_04
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_04 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_04_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_04_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_04_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_04_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_04 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_04_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_04_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_04_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_04_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_04 :: SPARE_REG [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_04_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_04_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x200,9)
#define BRPHY2_GPHY_CORE_SHD1C_04_SPARE_REG_MASK                   0x0200
#define BRPHY2_GPHY_CORE_SHD1C_04_SPARE_REG_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_04_SPARE_REG_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_04_SPARE_REG_SHIFT                  9

/* BRPHY2_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_DIS [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x100,8)
#define BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_MASK         0x0100
#define BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_BITS         1
#define BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_SHIFT        8

/* BRPHY2_GPHY_CORE :: SHD1C_04 :: SELECT_TPOUT_RXD [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_MASK            0x0080
#define BRPHY2_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_BITS            1
#define BRPHY2_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_SHIFT           7

/* BRPHY2_GPHY_CORE :: SHD1C_04 :: DISABLE_PHYA2 [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x40,6)
#define BRPHY2_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_MASK               0x0040
#define BRPHY2_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_BITS               1
#define BRPHY2_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_SHIFT              6

/* BRPHY2_GPHY_CORE :: SHD1C_04 :: RBC_TXC_RXC_TRI [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x20,5)
#define BRPHY2_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_MASK             0x0020
#define BRPHY2_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_BITS             1
#define BRPHY2_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_SHIFT            5

/* BRPHY2_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_LIMIT [04:02] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x1c,2,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x1c,2)
#define BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_MASK       0x001c
#define BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_ALIGN      0
#define BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_BITS       3
#define BRPHY2_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_SHIFT      2

/* BRPHY2_GPHY_CORE :: SHD1C_04 :: ENG_DET_ON_INTR_PIN [01:01] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x2,1)
#define BRPHY2_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_MASK         0x0002
#define BRPHY2_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_BITS         1
#define BRPHY2_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_SHIFT        1

/* BRPHY2_GPHY_CORE :: SHD1C_04 :: TESTONBYTE7_0 [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_04,0x1,0)
#define BRPHY2_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_MASK               0x0001
#define BRPHY2_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_BITS               1
#define BRPHY2_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_05
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_05 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_05_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_05_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_05_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_05_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_05_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_05_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_05_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_05_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: DLL_LOCK_EN [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x200,9)
#define BRPHY2_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_MASK                 0x0200
#define BRPHY2_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_BITS                 1
#define BRPHY2_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_SHIFT                9

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: TXC_RXC_DIS [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x100,8)
#define BRPHY2_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_MASK                 0x0100
#define BRPHY2_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_BITS                 1
#define BRPHY2_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_SHIFT                8

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: BT_R_REJECT_FILTER [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_MASK          0x0080
#define BRPHY2_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_BITS          1
#define BRPHY2_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_SHIFT         7

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: TXC_OFF_EN [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x40,6)
#define BRPHY2_GPHY_CORE_SHD1C_05_TXC_OFF_EN_MASK                  0x0040
#define BRPHY2_GPHY_CORE_SHD1C_05_TXC_OFF_EN_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD1C_05_TXC_OFF_EN_BITS                  1
#define BRPHY2_GPHY_CORE_SHD1C_05_TXC_OFF_EN_SHIFT                 6

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: SD_CHANGE_MUX_SEL [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x20,5)
#define BRPHY2_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_MASK           0x0020
#define BRPHY2_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_ALIGN          0
#define BRPHY2_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_BITS           1
#define BRPHY2_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_SHIFT          5

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: LOW_POWER_ENC_DIS [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x10,4)
#define BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_MASK           0x0010
#define BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_ALIGN          0
#define BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_BITS           1
#define BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_SHIFT          4

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: LOW_POWER_BT_DIS [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x8,3)
#define BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_MASK            0x0008
#define BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_BITS            1
#define BRPHY2_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_SHIFT           3

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: SD_DEASSERT_TIMER_LEN [02:02] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x4,2)
#define BRPHY2_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_MASK       0x0004
#define BRPHY2_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_ALIGN      0
#define BRPHY2_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_BITS       1
#define BRPHY2_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_SHIFT      2

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: AUTO_PWRDN_DLL_DIS [01:01] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x2,1)
#define BRPHY2_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_MASK          0x0002
#define BRPHY2_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_BITS          1
#define BRPHY2_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_SHIFT         1

/* BRPHY2_GPHY_CORE :: SHD1C_05 :: CLK125_OUTPUT_EN [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_05,0x1,0)
#define BRPHY2_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_MASK            0x0001
#define BRPHY2_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_BITS            1
#define BRPHY2_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_SHIFT           0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_06
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_06 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_06_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_06_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_06_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_06_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_06 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_06_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_06_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_06_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_06_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_06 :: SPARE_REG [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_06_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_06_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x200,9)
#define BRPHY2_GPHY_CORE_SHD1C_06_SPARE_REG_MASK                   0x0200
#define BRPHY2_GPHY_CORE_SHD1C_06_SPARE_REG_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_06_SPARE_REG_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_06_SPARE_REG_SHIFT                  9

/* BRPHY2_GPHY_CORE :: SHD1C_06 :: TDR_LINK_TIME_OUT [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x100,8)
#define BRPHY2_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_MASK           0x0100
#define BRPHY2_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_ALIGN          0
#define BRPHY2_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_BITS           1
#define BRPHY2_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_SHIFT          8

/* BRPHY2_GPHY_CORE :: SHD1C_06 :: TEST_PULSE_SIZE [07:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0xe0,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0xe0,5)
#define BRPHY2_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_MASK             0x00e0
#define BRPHY2_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_BITS             3
#define BRPHY2_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_SHIFT            5

/* BRPHY2_GPHY_CORE :: SHD1C_06 :: TX_CHANNEL_SEL [04:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x18,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x18,3)
#define BRPHY2_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_MASK              0x0018
#define BRPHY2_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_BITS              2
#define BRPHY2_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_SHIFT             3

/* BRPHY2_GPHY_CORE :: SHD1C_06 :: RX_CHANNEL_SEL [02:01] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x6,1,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x6,1)
#define BRPHY2_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_MASK              0x0006
#define BRPHY2_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_BITS              2
#define BRPHY2_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_SHIFT             1

/* BRPHY2_GPHY_CORE :: SHD1C_06 :: TDR_START [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_06_TDR_START(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_06_TDR_START(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_06,0x1,0)
#define BRPHY2_GPHY_CORE_SHD1C_06_TDR_START_MASK                   0x0001
#define BRPHY2_GPHY_CORE_SHD1C_06_TDR_START_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_06_TDR_START_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_06_TDR_START_SHIFT                  0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_07
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_07 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_07_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_07_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_07_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_07_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_07_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_07_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_07_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_07_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: SPARE_REG [09:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x300,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x300,8)
#define BRPHY2_GPHY_CORE_SHD1C_07_SPARE_REG_MASK                   0x0300
#define BRPHY2_GPHY_CORE_SHD1C_07_SPARE_REG_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_07_SPARE_REG_BITS                   2
#define BRPHY2_GPHY_CORE_SHD1C_07_SPARE_REG_SHIFT                  8

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_MASK                0x0080
#define BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_BITS                1
#define BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_SHIFT               7

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS_CLEAR [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x40,6)
#define BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_MASK          0x0040
#define BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_BITS          1
#define BRPHY2_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_SHIFT         6

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: FASTTIMERS [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_FASTTIMERS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_FASTTIMERS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x20,5)
#define BRPHY2_GPHY_CORE_SHD1C_07_FASTTIMERS_MASK                  0x0020
#define BRPHY2_GPHY_CORE_SHD1C_07_FASTTIMERS_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD1C_07_FASTTIMERS_BITS                  1
#define BRPHY2_GPHY_CORE_SHD1C_07_FASTTIMERS_SHIFT                 5

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: FEXT [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_FEXT(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_FEXT(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x10,4)
#define BRPHY2_GPHY_CORE_SHD1C_07_FEXT_MASK                        0x0010
#define BRPHY2_GPHY_CORE_SHD1C_07_FEXT_ALIGN                       0
#define BRPHY2_GPHY_CORE_SHD1C_07_FEXT_BITS                        1
#define BRPHY2_GPHY_CORE_SHD1C_07_FEXT_SHIFT                       4

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: MASTER [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_MASTER(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_MASTER(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x8,3)
#define BRPHY2_GPHY_CORE_SHD1C_07_MASTER_MASK                      0x0008
#define BRPHY2_GPHY_CORE_SHD1C_07_MASTER_ALIGN                     0
#define BRPHY2_GPHY_CORE_SHD1C_07_MASTER_BITS                      1
#define BRPHY2_GPHY_CORE_SHD1C_07_MASTER_SHIFT                     3

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: EXT_PHY_NO_AUTONEG [02:02] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x4,2)
#define BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_MASK          0x0004
#define BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_BITS          1
#define BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_SHIFT         2

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: EXT_PHY [01:01] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x2,1)
#define BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_MASK                     0x0002
#define BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_ALIGN                    0
#define BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_BITS                     1
#define BRPHY2_GPHY_CORE_SHD1C_07_EXT_PHY_SHIFT                    1

/* BRPHY2_GPHY_CORE :: SHD1C_07 :: TDR_EN [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_07_TDR_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_07_TDR_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_07,0x1,0)
#define BRPHY2_GPHY_CORE_SHD1C_07_TDR_EN_MASK                      0x0001
#define BRPHY2_GPHY_CORE_SHD1C_07_TDR_EN_ALIGN                     0
#define BRPHY2_GPHY_CORE_SHD1C_07_TDR_EN_BITS                      1
#define BRPHY2_GPHY_CORE_SHD1C_07_TDR_EN_SHIFT                     0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_08
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_08 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_08_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_08_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_08_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_08_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: reserved1 [09:09] */
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED1_MASK                   0x0200
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED1_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED1_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED1_SHIFT                  9

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: SLAVE_N [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_08_SLAVE_N(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_08_SLAVE_N(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x100,8)
#define BRPHY2_GPHY_CORE_SHD1C_08_SLAVE_N_MASK                     0x0100
#define BRPHY2_GPHY_CORE_SHD1C_08_SLAVE_N_ALIGN                    0
#define BRPHY2_GPHY_CORE_SHD1C_08_SLAVE_N_BITS                     1
#define BRPHY2_GPHY_CORE_SHD1C_08_SLAVE_N_SHIFT                    8

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: FDXLED_N [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_08_FDXLED_N(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_08_FDXLED_N(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_08_FDXLED_N_MASK                    0x0080
#define BRPHY2_GPHY_CORE_SHD1C_08_FDXLED_N_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD1C_08_FDXLED_N_BITS                    1
#define BRPHY2_GPHY_CORE_SHD1C_08_FDXLED_N_SHIFT                   7

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: INTR_N [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_08_INTR_N(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_08_INTR_N(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x40,6)
#define BRPHY2_GPHY_CORE_SHD1C_08_INTR_N_MASK                      0x0040
#define BRPHY2_GPHY_CORE_SHD1C_08_INTR_N_ALIGN                     0
#define BRPHY2_GPHY_CORE_SHD1C_08_INTR_N_BITS                      1
#define BRPHY2_GPHY_CORE_SHD1C_08_INTR_N_SHIFT                     6

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: reserved2 [05:05] */
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED2_MASK                   0x0020
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED2_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED2_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_08_RESERVED2_SHIFT                  5

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: LINKSPD_N [04:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_08_LINKSPD_N(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x18,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_08_LINKSPD_N(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x18,3)
#define BRPHY2_GPHY_CORE_SHD1C_08_LINKSPD_N_MASK                   0x0018
#define BRPHY2_GPHY_CORE_SHD1C_08_LINKSPD_N_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_08_LINKSPD_N_BITS                   2
#define BRPHY2_GPHY_CORE_SHD1C_08_LINKSPD_N_SHIFT                  3

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: TRANSMIT_LED [02:02] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x4,2)
#define BRPHY2_GPHY_CORE_SHD1C_08_TRANSMIT_LED_MASK                0x0004
#define BRPHY2_GPHY_CORE_SHD1C_08_TRANSMIT_LED_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD1C_08_TRANSMIT_LED_BITS                1
#define BRPHY2_GPHY_CORE_SHD1C_08_TRANSMIT_LED_SHIFT               2

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: RECEIVE_LED [01:01] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x2,1)
#define BRPHY2_GPHY_CORE_SHD1C_08_RECEIVE_LED_MASK                 0x0002
#define BRPHY2_GPHY_CORE_SHD1C_08_RECEIVE_LED_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD1C_08_RECEIVE_LED_BITS                 1
#define BRPHY2_GPHY_CORE_SHD1C_08_RECEIVE_LED_SHIFT                1

/* BRPHY2_GPHY_CORE :: SHD1C_08 :: QUALITY_LED [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_08_QUALITY_LED(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_08_QUALITY_LED(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_08,0x1,0)
#define BRPHY2_GPHY_CORE_SHD1C_08_QUALITY_LED_MASK                 0x0001
#define BRPHY2_GPHY_CORE_SHD1C_08_QUALITY_LED_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD1C_08_QUALITY_LED_BITS                 1
#define BRPHY2_GPHY_CORE_SHD1C_08_QUALITY_LED_SHIFT                0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_09
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_09 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_09_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_09_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_09_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_09_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_09_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_09_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_09_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_09_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: COL_BLINK [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_COL_BLINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_COL_BLINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x200,9)
#define BRPHY2_GPHY_CORE_SHD1C_09_COL_BLINK_MASK                   0x0200
#define BRPHY2_GPHY_CORE_SHD1C_09_COL_BLINK_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_09_COL_BLINK_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_09_COL_BLINK_SHIFT                  9

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: ACT_LINK_MSB [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x100,8)
#define BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_MASK                0x0100
#define BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_BITS                1
#define BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_SHIFT               8

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: SPARE_REG [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_09_SPARE_REG_MASK                   0x0080
#define BRPHY2_GPHY_CORE_SHD1C_09_SPARE_REG_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_09_SPARE_REG_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_09_SPARE_REG_SHIFT                  7

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: EXT_SERDES_INUSE [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x40,6)
#define BRPHY2_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_MASK            0x0040
#define BRPHY2_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_BITS            1
#define BRPHY2_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_SHIFT           6

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: OV_GBIC_LED [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x20,5)
#define BRPHY2_GPHY_CORE_SHD1C_09_OV_GBIC_LED_MASK                 0x0020
#define BRPHY2_GPHY_CORE_SHD1C_09_OV_GBIC_LED_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD1C_09_OV_GBIC_LED_BITS                 1
#define BRPHY2_GPHY_CORE_SHD1C_09_OV_GBIC_LED_SHIFT                5

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: ACT_LINK_LSB [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x10,4)
#define BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_MASK                0x0010
#define BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_BITS                1
#define BRPHY2_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_SHIFT               4

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: ACTIVITY_LED_EN [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x8,3)
#define BRPHY2_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_MASK             0x0008
#define BRPHY2_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_BITS             1
#define BRPHY2_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_SHIFT            3

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: RMT_FAULT_LED_EN [02:02] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x4,2)
#define BRPHY2_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_MASK            0x0004
#define BRPHY2_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_BITS            1
#define BRPHY2_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_SHIFT           2

/* BRPHY2_GPHY_CORE :: SHD1C_09 :: LINK_UTIL_LED_SEL [01:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x3,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_09,0x3,0)
#define BRPHY2_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_MASK           0x0003
#define BRPHY2_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_ALIGN          0
#define BRPHY2_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_BITS           2
#define BRPHY2_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_SHIFT          0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_0A
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_0A :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_0A_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_0A_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0A_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_0A_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_0A :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_0A_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_0A_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0A_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_0A_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_0A :: reserved1 [09:09] */
#define BRPHY2_GPHY_CORE_SHD1C_0A_RESERVED1_MASK                   0x0200
#define BRPHY2_GPHY_CORE_SHD1C_0A_RESERVED1_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0A_RESERVED1_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_0A_RESERVED1_SHIFT                  9

/* BRPHY2_GPHY_CORE :: SHD1C_0A :: APD_SINGLELP_ENABLE [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x100,8)
#define BRPHY2_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_MASK         0x0100
#define BRPHY2_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_BITS         1
#define BRPHY2_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_SHIFT        8

/* BRPHY2_GPHY_CORE :: SHD1C_0A :: LOWPWR136_ENC_EN [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_MASK            0x0080
#define BRPHY2_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_BITS            1
#define BRPHY2_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_SHIFT           7

/* BRPHY2_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_IGNORE_AUTONEG [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x40,6)
#define BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_MASK   0x0040
#define BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_ALIGN  0
#define BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_BITS   1
#define BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_SHIFT  6

/* BRPHY2_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_EN [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x20,5)
#define BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_MASK               0x0020
#define BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_BITS               1
#define BRPHY2_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_SHIFT              5

/* BRPHY2_GPHY_CORE :: SHD1C_0A :: SLEEP_TIMER_SEL [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0x10,4)
#define BRPHY2_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_MASK             0x0010
#define BRPHY2_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_BITS             1
#define BRPHY2_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_SHIFT            4

/* BRPHY2_GPHY_CORE :: SHD1C_0A :: WAKE_UP_TIMER_SEL [03:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0A,0xf,0)
#define BRPHY2_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_MASK           0x000f
#define BRPHY2_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_ALIGN          0
#define BRPHY2_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_BITS           4
#define BRPHY2_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_SHIFT          0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_0B
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_0B :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_0B_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_0B_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0B_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_0B_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_0B :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0B,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0B,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_0B_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_0B_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0B_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_0B_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_0B :: reserved1 [09:08] */
#define BRPHY2_GPHY_CORE_SHD1C_0B_RESERVED1_MASK                   0x0300
#define BRPHY2_GPHY_CORE_SHD1C_0B_RESERVED1_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0B_RESERVED1_BITS                   2
#define BRPHY2_GPHY_CORE_SHD1C_0B_RESERVED1_SHIFT                  8

/* BRPHY2_GPHY_CORE :: SHD1C_0B :: SPARE_CTL4 [07:01] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0B,0xfe,1,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0B,0xfe,1)
#define BRPHY2_GPHY_CORE_SHD1C_0B_SPARE_CTL4_MASK                  0x00fe
#define BRPHY2_GPHY_CORE_SHD1C_0B_SPARE_CTL4_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD1C_0B_SPARE_CTL4_BITS                  7
#define BRPHY2_GPHY_CORE_SHD1C_0B_SPARE_CTL4_SHIFT                 1

/* BRPHY2_GPHY_CORE :: SHD1C_0B :: dis_cl45 [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0B_dis_cl45(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0B,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0B_dis_cl45(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0B,0x1,0)
#define BRPHY2_GPHY_CORE_SHD1C_0B_DIS_CL45_MASK                    0x0001
#define BRPHY2_GPHY_CORE_SHD1C_0B_DIS_CL45_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD1C_0B_DIS_CL45_BITS                    1
#define BRPHY2_GPHY_CORE_SHD1C_0B_DIS_CL45_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_0D
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_0D :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_0D_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_0D_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0D_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_0D_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_0D :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0D,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0D,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_0D_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_0D_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0D_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_0D_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_0D :: reserved1 [09:08] */
#define BRPHY2_GPHY_CORE_SHD1C_0D_RESERVED1_MASK                   0x0300
#define BRPHY2_GPHY_CORE_SHD1C_0D_RESERVED1_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0D_RESERVED1_BITS                   2
#define BRPHY2_GPHY_CORE_SHD1C_0D_RESERVED1_SHIFT                  8

/* BRPHY2_GPHY_CORE :: SHD1C_0D :: LED2_SEL [07:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0D_LED2_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0D,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0D_LED2_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0D,0xf0,4)
#define BRPHY2_GPHY_CORE_SHD1C_0D_LED2_SEL_MASK                    0x00f0
#define BRPHY2_GPHY_CORE_SHD1C_0D_LED2_SEL_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD1C_0D_LED2_SEL_BITS                    4
#define BRPHY2_GPHY_CORE_SHD1C_0D_LED2_SEL_SHIFT                   4

/* BRPHY2_GPHY_CORE :: SHD1C_0D :: LED1_SEL [03:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0D_LED1_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0D,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0D_LED1_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0D,0xf,0)
#define BRPHY2_GPHY_CORE_SHD1C_0D_LED1_SEL_MASK                    0x000f
#define BRPHY2_GPHY_CORE_SHD1C_0D_LED1_SEL_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD1C_0D_LED1_SEL_BITS                    4
#define BRPHY2_GPHY_CORE_SHD1C_0D_LED1_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_0E
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_0E :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_0E_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_0E_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0E_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_0E_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_0E :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0E,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0E,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_0E_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_0E_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0E_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_0E_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_0E :: reserved1 [09:08] */
#define BRPHY2_GPHY_CORE_SHD1C_0E_RESERVED1_MASK                   0x0300
#define BRPHY2_GPHY_CORE_SHD1C_0E_RESERVED1_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0E_RESERVED1_BITS                   2
#define BRPHY2_GPHY_CORE_SHD1C_0E_RESERVED1_SHIFT                  8

/* BRPHY2_GPHY_CORE :: SHD1C_0E :: LED4_SEL [07:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0E_LED4_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0E,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0E_LED4_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0E,0xf0,4)
#define BRPHY2_GPHY_CORE_SHD1C_0E_LED4_SEL_MASK                    0x00f0
#define BRPHY2_GPHY_CORE_SHD1C_0E_LED4_SEL_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD1C_0E_LED4_SEL_BITS                    4
#define BRPHY2_GPHY_CORE_SHD1C_0E_LED4_SEL_SHIFT                   4

/* BRPHY2_GPHY_CORE :: SHD1C_0E :: LED3_SEL [03:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0E_LED3_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0E,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0E_LED3_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0E,0xf,0)
#define BRPHY2_GPHY_CORE_SHD1C_0E_LED3_SEL_MASK                    0x000f
#define BRPHY2_GPHY_CORE_SHD1C_0E_LED3_SEL_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD1C_0E_LED3_SEL_BITS                    4
#define BRPHY2_GPHY_CORE_SHD1C_0E_LED3_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_0F
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_0F :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_0F_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_0F_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0F_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_0F_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_0F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0F,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0F,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_0F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_0F_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0F_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_0F_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_0F :: reserved1 [09:04] */
#define BRPHY2_GPHY_CORE_SHD1C_0F_RESERVED1_MASK                   0x03f0
#define BRPHY2_GPHY_CORE_SHD1C_0F_RESERVED1_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_0F_RESERVED1_BITS                   6
#define BRPHY2_GPHY_CORE_SHD1C_0F_RESERVED1_SHIFT                  4

/* BRPHY2_GPHY_CORE :: SHD1C_0F :: CURRENT_MODE_LED_EN [03:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_0F,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_0F,0xf,0)
#define BRPHY2_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_MASK         0x000f
#define BRPHY2_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_BITS         4
#define BRPHY2_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_SHIFT        0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_10
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_10 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_10_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_10_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_10_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_10_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_10 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_10_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_10_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_10_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_10_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_10 :: reserved1 [09:08] */
#define BRPHY2_GPHY_CORE_SHD1C_10_RESERVED1_MASK                   0x0300
#define BRPHY2_GPHY_CORE_SHD1C_10_RESERVED1_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_10_RESERVED1_BITS                   2
#define BRPHY2_GPHY_CORE_SHD1C_10_RESERVED1_SHIFT                  8

/* BRPHY2_GPHY_CORE :: SHD1C_10 :: SPARE_REG [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_10_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_10_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_10_SPARE_REG_MASK                   0x0080
#define BRPHY2_GPHY_CORE_SHD1C_10_SPARE_REG_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_10_SPARE_REG_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_10_SPARE_REG_SHIFT                  7

/* BRPHY2_GPHY_CORE :: SHD1C_10 :: USE_ALT_LINKFLT [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x40,6)
#define BRPHY2_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_MASK             0x0040
#define BRPHY2_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_BITS             1
#define BRPHY2_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_SHIFT            6

/* BRPHY2_GPHY_CORE :: SHD1C_10 :: VISIBLE_BLINK [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x20,5)
#define BRPHY2_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_MASK               0x0020
#define BRPHY2_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_BITS               1
#define BRPHY2_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_SHIFT              5

/* BRPHY2_GPHY_CORE :: SHD1C_10 :: ENHANCED_PWR [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0x10,4)
#define BRPHY2_GPHY_CORE_SHD1C_10_ENHANCED_PWR_MASK                0x0010
#define BRPHY2_GPHY_CORE_SHD1C_10_ENHANCED_PWR_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD1C_10_ENHANCED_PWR_BITS                1
#define BRPHY2_GPHY_CORE_SHD1C_10_ENHANCED_PWR_SHIFT               4

/* BRPHY2_GPHY_CORE :: SHD1C_10 :: DISCONNECT_TIMER_VALUE [03:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_10,0xf,0)
#define BRPHY2_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_MASK      0x000f
#define BRPHY2_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_ALIGN     0
#define BRPHY2_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_BITS      4
#define BRPHY2_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_SHIFT     0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD1C_1F
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD1C_1F :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD1C_1F_RESERVED0_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD1C_1F_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_1F_RESERVED0_BITS                   1
#define BRPHY2_GPHY_CORE_SHD1C_1F_RESERVED0_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD1C_1F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY2_GPHY_CORE_SHD1C_1F_SHD1C_SEL_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD1C_1F_SHD1C_SEL_BITS                   5
#define BRPHY2_GPHY_CORE_SHD1C_1F_SHD1C_SEL_SHIFT                  10

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: DUAL_SERDES_CAPABLE [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x200,9)
#define BRPHY2_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_MASK         0x0200
#define BRPHY2_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_BITS         1
#define BRPHY2_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_SHIFT        9

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: MODE_SEL_CHANGE [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x100,8)
#define BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_MASK             0x0100
#define BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_BITS             1
#define BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_SHIFT            8

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: COPPER_LINK [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x80,7)
#define BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_LINK_MASK                 0x0080
#define BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_LINK_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_LINK_BITS                 1
#define BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_LINK_SHIFT                7

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: SERDES_LINK [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x40,6)
#define BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_LINK_MASK                 0x0040
#define BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_LINK_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_LINK_BITS                 1
#define BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_LINK_SHIFT                6

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: COPPER_ENG_DET [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x20,5)
#define BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_MASK              0x0020
#define BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_BITS              1
#define BRPHY2_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_SHIFT             5

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: FIBER_SIGNAL_DET [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x10,4)
#define BRPHY2_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_MASK            0x0010
#define BRPHY2_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_BITS            1
#define BRPHY2_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_SHIFT           4

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: SERDES_CAPABLE [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x8,3)
#define BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_MASK              0x0008
#define BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_BITS              1
#define BRPHY2_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_SHIFT             3

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: MODE_SEL [02:01] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x6,1,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x6,1)
#define BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_MASK                    0x0006
#define BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_BITS                    2
#define BRPHY2_GPHY_CORE_SHD1C_1F_MODE_SEL_SHIFT                   1

/* BRPHY2_GPHY_CORE :: SHD1C_1F :: REG_1000X_EN [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD1C_1F,0x1,0)
#define BRPHY2_GPHY_CORE_SHD1C_1F_REG_1000X_EN_MASK                0x0001
#define BRPHY2_GPHY_CORE_SHD1C_1F_REG_1000X_EN_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD1C_1F_REG_1000X_EN_BITS                1
#define BRPHY2_GPHY_CORE_SHD1C_1F_REG_1000X_EN_SHIFT               0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD18_000
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD18_000 :: EXT_LPBK [15:15] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_EXT_LPBK(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_EXT_LPBK(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x8000,15)
#define BRPHY2_GPHY_CORE_SHD18_000_EXT_LPBK_MASK                   0x8000
#define BRPHY2_GPHY_CORE_SHD18_000_EXT_LPBK_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD18_000_EXT_LPBK_BITS                   1
#define BRPHY2_GPHY_CORE_SHD18_000_EXT_LPBK_SHIFT                  15

/* BRPHY2_GPHY_CORE :: SHD18_000 :: EXT_PKT_LEN [14:14] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x4000,14)
#define BRPHY2_GPHY_CORE_SHD18_000_EXT_PKT_LEN_MASK                0x4000
#define BRPHY2_GPHY_CORE_SHD18_000_EXT_PKT_LEN_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_000_EXT_PKT_LEN_BITS                1
#define BRPHY2_GPHY_CORE_SHD18_000_EXT_PKT_LEN_SHIFT               14

/* BRPHY2_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_1000T [13:12] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x3000,12,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x3000,12)
#define BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_MASK         0x3000
#define BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_BITS         2
#define BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_SHIFT        12

/* BRPHY2_GPHY_CORE :: SHD18_000 :: SM_DSP_CLK_EN [11:11] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x800,11)
#define BRPHY2_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_MASK              0x0800
#define BRPHY2_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_BITS              1
#define BRPHY2_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_SHIFT             11

/* BRPHY2_GPHY_CORE :: SHD18_000 :: TX_6DB_CODING [10:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x400,10)
#define BRPHY2_GPHY_CORE_SHD18_000_TX_6DB_CODING_MASK              0x0400
#define BRPHY2_GPHY_CORE_SHD18_000_TX_6DB_CODING_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD18_000_TX_6DB_CODING_BITS              1
#define BRPHY2_GPHY_CORE_SHD18_000_TX_6DB_CODING_SHIFT             10

/* BRPHY2_GPHY_CORE :: SHD18_000 :: RCV_SLICING [09:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_RCV_SLICING(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x300,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_RCV_SLICING(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x300,8)
#define BRPHY2_GPHY_CORE_SHD18_000_RCV_SLICING_MASK                0x0300
#define BRPHY2_GPHY_CORE_SHD18_000_RCV_SLICING_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_000_RCV_SLICING_BITS                2
#define BRPHY2_GPHY_CORE_SHD18_000_RCV_SLICING_SHIFT               8

/* BRPHY2_GPHY_CORE :: SHD18_000 :: PRF_DIS [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_PRF_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_PRF_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x80,7)
#define BRPHY2_GPHY_CORE_SHD18_000_PRF_DIS_MASK                    0x0080
#define BRPHY2_GPHY_CORE_SHD18_000_PRF_DIS_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD18_000_PRF_DIS_BITS                    1
#define BRPHY2_GPHY_CORE_SHD18_000_PRF_DIS_SHIFT                   7

/* BRPHY2_GPHY_CORE :: SHD18_000 :: INVERSE_PRF_DIS [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x40,6)
#define BRPHY2_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_MASK            0x0040
#define BRPHY2_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_SHIFT           6

/* BRPHY2_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_100TX [05:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x30,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x30,4)
#define BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_MASK         0x0030
#define BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_BITS         2
#define BRPHY2_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_SHIFT        4

/* BRPHY2_GPHY_CORE :: SHD18_000 :: DIAGNOSTIC [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x8,3)
#define BRPHY2_GPHY_CORE_SHD18_000_DIAGNOSTIC_MASK                 0x0008
#define BRPHY2_GPHY_CORE_SHD18_000_DIAGNOSTIC_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD18_000_DIAGNOSTIC_BITS                 1
#define BRPHY2_GPHY_CORE_SHD18_000_DIAGNOSTIC_SHIFT                3

/* BRPHY2_GPHY_CORE :: SHD18_000 :: SHD18_SEL [02:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_000_SHD18_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_000_SHD18_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_000,0x7,0)
#define BRPHY2_GPHY_CORE_SHD18_000_SHD18_SEL_MASK                  0x0007
#define BRPHY2_GPHY_CORE_SHD18_000_SHD18_SEL_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_000_SHD18_SEL_BITS                  3
#define BRPHY2_GPHY_CORE_SHD18_000_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD18_001
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD18_001 :: MANCHESTER_CODE_ERR [15:15] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x8000,15)
#define BRPHY2_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_MASK        0x8000
#define BRPHY2_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_ALIGN       0
#define BRPHY2_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_BITS        1
#define BRPHY2_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_SHIFT       15

/* BRPHY2_GPHY_CORE :: SHD18_001 :: EOF_ERR [14:14] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_EOF_ERR(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_EOF_ERR(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x4000,14)
#define BRPHY2_GPHY_CORE_SHD18_001_EOF_ERR_MASK                    0x4000
#define BRPHY2_GPHY_CORE_SHD18_001_EOF_ERR_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD18_001_EOF_ERR_BITS                    1
#define BRPHY2_GPHY_CORE_SHD18_001_EOF_ERR_SHIFT                   14

/* BRPHY2_GPHY_CORE :: SHD18_001 :: POLARITY_ERR [13:13] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_POLARITY_ERR(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_POLARITY_ERR(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x2000,13)
#define BRPHY2_GPHY_CORE_SHD18_001_POLARITY_ERR_MASK               0x2000
#define BRPHY2_GPHY_CORE_SHD18_001_POLARITY_ERR_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD18_001_POLARITY_ERR_BITS               1
#define BRPHY2_GPHY_CORE_SHD18_001_POLARITY_ERR_SHIFT              13

/* BRPHY2_GPHY_CORE :: SHD18_001 :: BLOCK_RXDV_EXT [12:12] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x1000,12)
#define BRPHY2_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_MASK             0x1000
#define BRPHY2_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_BITS             1
#define BRPHY2_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_SHIFT            12

/* BRPHY2_GPHY_CORE :: SHD18_001 :: BT_TXC_INV [11:11] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_BT_TXC_INV(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_BT_TXC_INV(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x800,11)
#define BRPHY2_GPHY_CORE_SHD18_001_BT_TXC_INV_MASK                 0x0800
#define BRPHY2_GPHY_CORE_SHD18_001_BT_TXC_INV_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD18_001_BT_TXC_INV_BITS                 1
#define BRPHY2_GPHY_CORE_SHD18_001_BT_TXC_INV_SHIFT                11

/* BRPHY2_GPHY_CORE :: SHD18_001 :: CLASS_AB_DRIVER_SEL [10:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x400,10)
#define BRPHY2_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_MASK        0x0400
#define BRPHY2_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_ALIGN       0
#define BRPHY2_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_BITS        1
#define BRPHY2_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_SHIFT       10

/* BRPHY2_GPHY_CORE :: SHD18_001 :: JABBER_DIS [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_JABBER_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_JABBER_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x200,9)
#define BRPHY2_GPHY_CORE_SHD18_001_JABBER_DIS_MASK                 0x0200
#define BRPHY2_GPHY_CORE_SHD18_001_JABBER_DIS_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD18_001_JABBER_DIS_BITS                 1
#define BRPHY2_GPHY_CORE_SHD18_001_JABBER_DIS_SHIFT                9

/* BRPHY2_GPHY_CORE :: SHD18_001 :: BT_SIG_DET_AUTOSWITCH [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x100,8)
#define BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_MASK      0x0100
#define BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_ALIGN     0
#define BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_BITS      1
#define BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_SHIFT     8

/* BRPHY2_GPHY_CORE :: SHD18_001 :: BT_SIG_DETECT_THD [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x80,7)
#define BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_MASK          0x0080
#define BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_BITS          1
#define BRPHY2_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_SHIFT         7

/* BRPHY2_GPHY_CORE :: SHD18_001 :: BT_ECHO [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_BT_ECHO(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_BT_ECHO(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x40,6)
#define BRPHY2_GPHY_CORE_SHD18_001_BT_ECHO_MASK                    0x0040
#define BRPHY2_GPHY_CORE_SHD18_001_BT_ECHO_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD18_001_BT_ECHO_BITS                    1
#define BRPHY2_GPHY_CORE_SHD18_001_BT_ECHO_SHIFT                   6

/* BRPHY2_GPHY_CORE :: SHD18_001 :: SQE_EN [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_SQE_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_SQE_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x20,5)
#define BRPHY2_GPHY_CORE_SHD18_001_SQE_EN_MASK                     0x0020
#define BRPHY2_GPHY_CORE_SHD18_001_SQE_EN_ALIGN                    0
#define BRPHY2_GPHY_CORE_SHD18_001_SQE_EN_BITS                     1
#define BRPHY2_GPHY_CORE_SHD18_001_SQE_EN_SHIFT                    5

/* BRPHY2_GPHY_CORE :: SHD18_001 :: BT_NO_DRIBBLE [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x10,4)
#define BRPHY2_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_MASK              0x0010
#define BRPHY2_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_BITS              1
#define BRPHY2_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_SHIFT             4

/* BRPHY2_GPHY_CORE :: SHD18_001 :: BT_POL_ERR_CNT_MAX [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x8,3)
#define BRPHY2_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_MASK         0x0008
#define BRPHY2_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_BITS         1
#define BRPHY2_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_SHIFT        3

/* BRPHY2_GPHY_CORE :: SHD18_001 :: SHD18_SEL [02:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_001_SHD18_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_001_SHD18_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_001,0x7,0)
#define BRPHY2_GPHY_CORE_SHD18_001_SHD18_SEL_MASK                  0x0007
#define BRPHY2_GPHY_CORE_SHD18_001_SHD18_SEL_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_001_SHD18_SEL_BITS                  3
#define BRPHY2_GPHY_CORE_SHD18_001_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD18_010
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD18_010 :: SPARE_REG_3 [15:11] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_3(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0xf800,11,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_3(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0xf800,11)
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_3_MASK                0xf800
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_3_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_3_BITS                5
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_3_SHIFT               11

/* BRPHY2_GPHY_CORE :: SHD18_010 :: SPARE_REG_2 [10:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_2(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x7c0,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_2(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x7c0,6)
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_2_MASK                0x07c0
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_2_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_2_BITS                5
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_2_SHIFT               6

/* BRPHY2_GPHY_CORE :: SHD18_010 :: SUPER_ISOLATE [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x20,5)
#define BRPHY2_GPHY_CORE_SHD18_010_SUPER_ISOLATE_MASK              0x0020
#define BRPHY2_GPHY_CORE_SHD18_010_SUPER_ISOLATE_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD18_010_SUPER_ISOLATE_BITS              1
#define BRPHY2_GPHY_CORE_SHD18_010_SUPER_ISOLATE_SHIFT             5

/* BRPHY2_GPHY_CORE :: SHD18_010 :: SPARE_REG_1 [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_1(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_1(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x10,4)
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_1_MASK                0x0010
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_1_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_1_BITS                1
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_1_SHIFT               4

/* BRPHY2_GPHY_CORE :: SHD18_010 :: SPARE_REG_0 [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_0(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_0(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x8,3)
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_0_MASK                0x0008
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_0_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_0_BITS                1
#define BRPHY2_GPHY_CORE_SHD18_010_SPARE_REG_0_SHIFT               3

/* BRPHY2_GPHY_CORE :: SHD18_010 :: SHD18_SEL [02:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_010_SHD18_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_010_SHD18_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_010,0x7,0)
#define BRPHY2_GPHY_CORE_SHD18_010_SHD18_SEL_MASK                  0x0007
#define BRPHY2_GPHY_CORE_SHD18_010_SHD18_SEL_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_010_SHD18_SEL_BITS                  3
#define BRPHY2_GPHY_CORE_SHD18_010_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD18_011
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD18_011 :: IP_PHONE_DETECT [15:15] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x8000,15)
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_MASK            0x8000
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_SHIFT           15

/* BRPHY2_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_CNTR [14:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x7c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x7c00,10)
#define BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_MASK          0x7c00
#define BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_BITS          5
#define BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_SHIFT         10

/* BRPHY2_GPHY_CORE :: SHD18_011 :: ALT_RANDOM_SEED [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x200,9)
#define BRPHY2_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_MASK            0x0200
#define BRPHY2_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_SHIFT           9

/* BRPHY2_GPHY_CORE :: SHD18_011 :: RESTART_AUTONEG [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x100,8)
#define BRPHY2_GPHY_CORE_SHD18_011_RESTART_AUTONEG_MASK            0x0100
#define BRPHY2_GPHY_CORE_SHD18_011_RESTART_AUTONEG_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_011_RESTART_AUTONEG_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_011_RESTART_AUTONEG_SHIFT           8

/* BRPHY2_GPHY_CORE :: SHD18_011 :: IP_PHONE_WINDOW [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x80,7)
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_MASK            0x0080
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_SHIFT           7

/* BRPHY2_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_EN [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x40,6)
#define BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_MASK            0x0040
#define BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_SHIFT           6

/* BRPHY2_GPHY_CORE :: SHD18_011 :: IP_PHONE_DET_EN [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x20,5)
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_MASK            0x0020
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_SHIFT           5

/* BRPHY2_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_DIS [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x10,4)
#define BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_MASK      0x0010
#define BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_ALIGN     0
#define BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_BITS      1
#define BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_SHIFT     4

/* BRPHY2_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_SW [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x8,3)
#define BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_MASK       0x0008
#define BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_ALIGN      0
#define BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_BITS       1
#define BRPHY2_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_SHIFT      3

/* BRPHY2_GPHY_CORE :: SHD18_011 :: SHD18_SEL [02:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_011_SHD18_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_011_SHD18_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_011,0x7,0)
#define BRPHY2_GPHY_CORE_SHD18_011_SHD18_SEL_MASK                  0x0007
#define BRPHY2_GPHY_CORE_SHD18_011_SHD18_SEL_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_011_SHD18_SEL_BITS                  3
#define BRPHY2_GPHY_CORE_SHD18_011_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD18_100
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD18_100 :: RMT_LPBK_EN [15:15] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x8000,15)
#define BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_EN_MASK                0x8000
#define BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_EN_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_EN_BITS                1
#define BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_EN_SHIFT               15

/* BRPHY2_GPHY_CORE :: SHD18_100 :: TDK_FIX_EN [14:14] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x4000,14)
#define BRPHY2_GPHY_CORE_SHD18_100_TDK_FIX_EN_MASK                 0x4000
#define BRPHY2_GPHY_CORE_SHD18_100_TDK_FIX_EN_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD18_100_TDK_FIX_EN_BITS                 1
#define BRPHY2_GPHY_CORE_SHD18_100_TDK_FIX_EN_SHIFT                14

/* BRPHY2_GPHY_CORE :: SHD18_100 :: BT_DLL_BYPASS_CLK [13:13] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x2000,13)
#define BRPHY2_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_MASK          0x2000
#define BRPHY2_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_BITS          1
#define BRPHY2_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_SHIFT         13

/* BRPHY2_GPHY_CORE :: SHD18_100 :: BLOCK_10BT_RESTART_AUTONEG [12:12] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x1000,12)
#define BRPHY2_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_MASK 0x1000
#define BRPHY2_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_ALIGN 0
#define BRPHY2_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_BITS 1
#define BRPHY2_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_SHIFT 12

/* BRPHY2_GPHY_CORE :: SHD18_100 :: RMT_LPBK_TRISTATE [11:11] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x800,11)
#define BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_MASK          0x0800
#define BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_BITS          1
#define BRPHY2_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_SHIFT         11

/* BRPHY2_GPHY_CORE :: SHD18_100 :: BT_WAKEUP [10:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_BT_WAKEUP(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_BT_WAKEUP(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x400,10)
#define BRPHY2_GPHY_CORE_SHD18_100_BT_WAKEUP_MASK                  0x0400
#define BRPHY2_GPHY_CORE_SHD18_100_BT_WAKEUP_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_100_BT_WAKEUP_BITS                  1
#define BRPHY2_GPHY_CORE_SHD18_100_BT_WAKEUP_SHIFT                 10

/* BRPHY2_GPHY_CORE :: SHD18_100 :: BT_POLARITY_BYPASS [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x200,9)
#define BRPHY2_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_MASK         0x0200
#define BRPHY2_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_ALIGN        0
#define BRPHY2_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_BITS         1
#define BRPHY2_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_SHIFT        9

/* BRPHY2_GPHY_CORE :: SHD18_100 :: BT_IDLE_BYPASS [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x100,8)
#define BRPHY2_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_MASK             0x0100
#define BRPHY2_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_BITS             1
#define BRPHY2_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_SHIFT            8

/* BRPHY2_GPHY_CORE :: SHD18_100 :: BT_CLK_RESET_EN [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x80,7)
#define BRPHY2_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_MASK            0x0080
#define BRPHY2_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_SHIFT           7

/* BRPHY2_GPHY_CORE :: SHD18_100 :: BT_BYPASS_ADC [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x40,6)
#define BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_MASK              0x0040
#define BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_BITS              1
#define BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_SHIFT             6

/* BRPHY2_GPHY_CORE :: SHD18_100 :: BT_BYPASS_CRS [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x20,5)
#define BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_MASK              0x0020
#define BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_BITS              1
#define BRPHY2_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_SHIFT             5

/* BRPHY2_GPHY_CORE :: SHD18_100 :: SWAP_RXMDIX [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x10,4)
#define BRPHY2_GPHY_CORE_SHD18_100_SWAP_RXMDIX_MASK                0x0010
#define BRPHY2_GPHY_CORE_SHD18_100_SWAP_RXMDIX_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_100_SWAP_RXMDIX_BITS                1
#define BRPHY2_GPHY_CORE_SHD18_100_SWAP_RXMDIX_SHIFT               4

/* BRPHY2_GPHY_CORE :: SHD18_100 :: HALFOUT [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_HALFOUT(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_HALFOUT(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x8,3)
#define BRPHY2_GPHY_CORE_SHD18_100_HALFOUT_MASK                    0x0008
#define BRPHY2_GPHY_CORE_SHD18_100_HALFOUT_ALIGN                   0
#define BRPHY2_GPHY_CORE_SHD18_100_HALFOUT_BITS                    1
#define BRPHY2_GPHY_CORE_SHD18_100_HALFOUT_SHIFT                   3

/* BRPHY2_GPHY_CORE :: SHD18_100 :: SHD18_SEL [02:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_100_SHD18_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_100_SHD18_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_100,0x7,0)
#define BRPHY2_GPHY_CORE_SHD18_100_SHD18_SEL_MASK                  0x0007
#define BRPHY2_GPHY_CORE_SHD18_100_SHD18_SEL_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_100_SHD18_SEL_BITS                  3
#define BRPHY2_GPHY_CORE_SHD18_100_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD18_101
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD18_101 :: COPPER_ENG_DET_OV [15:15] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x8000,15)
#define BRPHY2_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_MASK          0x8000
#define BRPHY2_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_BITS          1
#define BRPHY2_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_SHIFT         15

/* BRPHY2_GPHY_CORE :: SHD18_101 :: ADCFIFO_TX_FIX [14:14] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x4000,14)
#define BRPHY2_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_MASK             0x4000
#define BRPHY2_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_ALIGN            0
#define BRPHY2_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_BITS             1
#define BRPHY2_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_SHIFT            14

/* BRPHY2_GPHY_CORE :: SHD18_101 :: CLASS_AB_DVT_EN [13:13] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x2000,13)
#define BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_MASK            0x2000
#define BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_SHIFT           13

/* BRPHY2_GPHY_CORE :: SHD18_101 :: CLASS_AB_EN [12:12] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x1000,12)
#define BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_EN_MASK                0x1000
#define BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_EN_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_EN_BITS                1
#define BRPHY2_GPHY_CORE_SHD18_101_CLASS_AB_EN_SHIFT               12

/* BRPHY2_GPHY_CORE :: SHD18_101 :: ENC_ERR_SCALE [11:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0xc00,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0xc00,10)
#define BRPHY2_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_MASK              0x0c00
#define BRPHY2_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_ALIGN             0
#define BRPHY2_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_BITS              2
#define BRPHY2_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_SHIFT             10

/* BRPHY2_GPHY_CORE :: SHD18_101 :: SPARE_REG [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x200,9)
#define BRPHY2_GPHY_CORE_SHD18_101_SPARE_REG_MASK                  0x0200
#define BRPHY2_GPHY_CORE_SHD18_101_SPARE_REG_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_101_SPARE_REG_BITS                  1
#define BRPHY2_GPHY_CORE_SHD18_101_SPARE_REG_SHIFT                 9

/* BRPHY2_GPHY_CORE :: SHD18_101 :: AUTO_ENCODING_CORRECTION [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x100,8)
#define BRPHY2_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_MASK   0x0100
#define BRPHY2_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_ALIGN  0
#define BRPHY2_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_BITS   1
#define BRPHY2_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_SHIFT  8

/* BRPHY2_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_RX [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x80,7)
#define BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_MASK        0x0080
#define BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_ALIGN       0
#define BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_BITS        1
#define BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_SHIFT       7

/* BRPHY2_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_TX [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x40,6)
#define BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_MASK        0x0040
#define BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_ALIGN       0
#define BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_BITS        1
#define BRPHY2_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_SHIFT       6

/* BRPHY2_GPHY_CORE :: SHD18_101 :: EC_AS_NEXT [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x20,5)
#define BRPHY2_GPHY_CORE_SHD18_101_EC_AS_NEXT_MASK                 0x0020
#define BRPHY2_GPHY_CORE_SHD18_101_EC_AS_NEXT_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD18_101_EC_AS_NEXT_BITS                 1
#define BRPHY2_GPHY_CORE_SHD18_101_EC_AS_NEXT_SHIFT                5

/* BRPHY2_GPHY_CORE :: SHD18_101 :: FORCE_MDIX [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_FORCE_MDIX(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_FORCE_MDIX(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x10,4)
#define BRPHY2_GPHY_CORE_SHD18_101_FORCE_MDIX_MASK                 0x0010
#define BRPHY2_GPHY_CORE_SHD18_101_FORCE_MDIX_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD18_101_FORCE_MDIX_BITS                 1
#define BRPHY2_GPHY_CORE_SHD18_101_FORCE_MDIX_SHIFT                4

/* BRPHY2_GPHY_CORE :: SHD18_101 :: EN_PWRDNTDAC [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x8,3)
#define BRPHY2_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_MASK               0x0008
#define BRPHY2_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_BITS               1
#define BRPHY2_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_SHIFT              3

/* BRPHY2_GPHY_CORE :: SHD18_101 :: SHD18_SEL [02:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_101_SHD18_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_101_SHD18_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_101,0x7,0)
#define BRPHY2_GPHY_CORE_SHD18_101_SHD18_SEL_MASK                  0x0007
#define BRPHY2_GPHY_CORE_SHD18_101_SHD18_SEL_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_101_SHD18_SEL_BITS                  3
#define BRPHY2_GPHY_CORE_SHD18_101_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD18_110
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD18_110 :: IP_PHONE_SEED_WR_EN [15:15] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_110,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_110,0x8000,15)
#define BRPHY2_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_MASK        0x8000
#define BRPHY2_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_ALIGN       0
#define BRPHY2_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_BITS        1
#define BRPHY2_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_SHIFT       15

/* BRPHY2_GPHY_CORE :: SHD18_110 :: SPARE_REG [14:14] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_110_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_110,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_110_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_110,0x4000,14)
#define BRPHY2_GPHY_CORE_SHD18_110_SPARE_REG_MASK                  0x4000
#define BRPHY2_GPHY_CORE_SHD18_110_SPARE_REG_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_110_SPARE_REG_BITS                  1
#define BRPHY2_GPHY_CORE_SHD18_110_SPARE_REG_SHIFT                 14

/* BRPHY2_GPHY_CORE :: SHD18_110 :: LOC_IP_PHONE_SEED [13:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_110,0x3ff8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_110,0x3ff8,3)
#define BRPHY2_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_MASK          0x3ff8
#define BRPHY2_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_ALIGN         0
#define BRPHY2_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_BITS          11
#define BRPHY2_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_SHIFT         3

/* BRPHY2_GPHY_CORE :: SHD18_110 :: SHD18_SEL [02:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_110_SHD18_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_110,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_110_SHD18_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_110,0x7,0)
#define BRPHY2_GPHY_CORE_SHD18_110_SHD18_SEL_MASK                  0x0007
#define BRPHY2_GPHY_CORE_SHD18_110_SHD18_SEL_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_110_SHD18_SEL_BITS                  3
#define BRPHY2_GPHY_CORE_SHD18_110_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SHD18_111
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SHD18_111 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_SHD18_111_RESERVED0_MASK                  0x8000
#define BRPHY2_GPHY_CORE_SHD18_111_RESERVED0_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_111_RESERVED0_BITS                  1
#define BRPHY2_GPHY_CORE_SHD18_111_RESERVED0_SHIFT                 15

/* BRPHY2_GPHY_CORE :: SHD18_111 :: SHD18_RDSEL [14:12] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x7000,12,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x7000,12)
#define BRPHY2_GPHY_CORE_SHD18_111_SHD18_RDSEL_MASK                0x7000
#define BRPHY2_GPHY_CORE_SHD18_111_SHD18_RDSEL_ALIGN               0
#define BRPHY2_GPHY_CORE_SHD18_111_SHD18_RDSEL_BITS                3
#define BRPHY2_GPHY_CORE_SHD18_111_SHD18_RDSEL_SHIFT               12

/* BRPHY2_GPHY_CORE :: SHD18_111 :: PKT_CNTR [11:11] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_PKT_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_PKT_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x800,11)
#define BRPHY2_GPHY_CORE_SHD18_111_PKT_CNTR_MASK                   0x0800
#define BRPHY2_GPHY_CORE_SHD18_111_PKT_CNTR_ALIGN                  0
#define BRPHY2_GPHY_CORE_SHD18_111_PKT_CNTR_BITS                   1
#define BRPHY2_GPHY_CORE_SHD18_111_PKT_CNTR_SHIFT                  11

/* BRPHY2_GPHY_CORE :: SHD18_111 :: BYPASS_WIRESPEED_TIMER [10:10] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x400,10)
#define BRPHY2_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_MASK     0x0400
#define BRPHY2_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_ALIGN    0
#define BRPHY2_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_BITS     1
#define BRPHY2_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_SHIFT    10

/* BRPHY2_GPHY_CORE :: SHD18_111 :: FORCE_AUTO_MDIX [09:09] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x200,9)
#define BRPHY2_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_MASK            0x0200
#define BRPHY2_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_ALIGN           0
#define BRPHY2_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_BITS            1
#define BRPHY2_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_SHIFT           9

/* BRPHY2_GPHY_CORE :: SHD18_111 :: RGMII_TIMING [08:08] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_RGMII_TIMING(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_RGMII_TIMING(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x100,8)
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_TIMING_MASK               0x0100
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_TIMING_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_TIMING_BITS               1
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_TIMING_SHIFT              8

/* BRPHY2_GPHY_CORE :: SHD18_111 :: RGMII [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_RGMII(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_RGMII(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x80,7)
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_MASK                      0x0080
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_ALIGN                     0
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_BITS                      1
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_SHIFT                     7

/* BRPHY2_GPHY_CORE :: SHD18_111 :: RGMII_RXER [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_RGMII_RXER(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_RGMII_RXER(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x40,6)
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_RXER_MASK                 0x0040
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_RXER_ALIGN                0
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_RXER_BITS                 1
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_RXER_SHIFT                6

/* BRPHY2_GPHY_CORE :: SHD18_111 :: RGMII_OB_STATUS_DIS [05:05] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x20,5)
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_MASK        0x0020
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_ALIGN       0
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_BITS        1
#define BRPHY2_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_SHIFT       5

/* BRPHY2_GPHY_CORE :: SHD18_111 :: WIRESPEED_EN [04:04] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x10,4)
#define BRPHY2_GPHY_CORE_SHD18_111_WIRESPEED_EN_MASK               0x0010
#define BRPHY2_GPHY_CORE_SHD18_111_WIRESPEED_EN_ALIGN              0
#define BRPHY2_GPHY_CORE_SHD18_111_WIRESPEED_EN_BITS               1
#define BRPHY2_GPHY_CORE_SHD18_111_WIRESPEED_EN_SHIFT              4

/* BRPHY2_GPHY_CORE :: SHD18_111 :: MDIO_ALL_PHY_SEL [03:03] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x8,3)
#define BRPHY2_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_MASK           0x0008
#define BRPHY2_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_ALIGN          0
#define BRPHY2_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_BITS           1
#define BRPHY2_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_SHIFT          3

/* BRPHY2_GPHY_CORE :: SHD18_111 :: SHD18_SEL [02:00] */
#define Wr_BRPHY2_GPHY_CORE_SHD18_111_SHD18_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_SHD18_111_SHD18_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SHD18_111,0x7,0)
#define BRPHY2_GPHY_CORE_SHD18_111_SHD18_SEL_MASK                  0x0007
#define BRPHY2_GPHY_CORE_SHD18_111_SHD18_SEL_ALIGN                 0
#define BRPHY2_GPHY_CORE_SHD18_111_SHD18_SEL_BITS                  3
#define BRPHY2_GPHY_CORE_SHD18_111_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP00
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP00 :: PKT_CNTR [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP00_PKT_CNTR(x) WriteReg16(BRPHY2_GPHY_CORE_EXP00,x)
#define Rd_BRPHY2_GPHY_CORE_EXP00_PKT_CNTR(x) ReadReg16(BRPHY2_GPHY_CORE_EXP00)
#define BRPHY2_GPHY_CORE_EXP00_PKT_CNTR_MASK                       0xffff
#define BRPHY2_GPHY_CORE_EXP00_PKT_CNTR_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP00_PKT_CNTR_BITS                       16
#define BRPHY2_GPHY_CORE_EXP00_PKT_CNTR_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP01
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP01 :: LATE_COL_CNTR [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_LATE_COL_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_LATE_COL_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x8000,15)
#define BRPHY2_GPHY_CORE_EXP01_LATE_COL_CNTR_MASK                  0x8000
#define BRPHY2_GPHY_CORE_EXP01_LATE_COL_CNTR_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP01_LATE_COL_CNTR_BITS                  1
#define BRPHY2_GPHY_CORE_EXP01_LATE_COL_CNTR_SHIFT                 15

/* BRPHY2_GPHY_CORE :: EXP01 :: RMT_COPPER_ERR [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x4000,14)
#define BRPHY2_GPHY_CORE_EXP01_RMT_COPPER_ERR_MASK                 0x4000
#define BRPHY2_GPHY_CORE_EXP01_RMT_COPPER_ERR_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP01_RMT_COPPER_ERR_BITS                 1
#define BRPHY2_GPHY_CORE_EXP01_RMT_COPPER_ERR_SHIFT                14

/* BRPHY2_GPHY_CORE :: EXP01 :: SERDES_LINK_PARTNER_RESTARTED [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x2000,13)
#define BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_MASK  0x2000
#define BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_ALIGN 0
#define BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_BITS  1
#define BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_SHIFT 13

/* BRPHY2_GPHY_CORE :: EXP01 :: SERDES_CRC_ERR [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP01_SERDES_CRC_ERR_MASK                 0x1000
#define BRPHY2_GPHY_CORE_EXP01_SERDES_CRC_ERR_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP01_SERDES_CRC_ERR_BITS                 1
#define BRPHY2_GPHY_CORE_EXP01_SERDES_CRC_ERR_SHIFT                12

/* BRPHY2_GPHY_CORE :: EXP01 :: SGMII_SLAVE_CHANGE [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x800,11)
#define BRPHY2_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_MASK             0x0800
#define BRPHY2_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_ALIGN            0
#define BRPHY2_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_BITS             1
#define BRPHY2_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_SHIFT            11

/* BRPHY2_GPHY_CORE :: EXP01 :: FX_SERDES_CHANGE [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x400,10)
#define BRPHY2_GPHY_CORE_EXP01_FX_SERDES_CHANGE_MASK               0x0400
#define BRPHY2_GPHY_CORE_EXP01_FX_SERDES_CHANGE_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP01_FX_SERDES_CHANGE_BITS               1
#define BRPHY2_GPHY_CORE_EXP01_FX_SERDES_CHANGE_SHIFT              10

/* BRPHY2_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_PAGE_RCVD [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x200,9)
#define BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_MASK       0x0200
#define BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_ALIGN      0
#define BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_BITS       1
#define BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_SHIFT      9

/* BRPHY2_GPHY_CORE :: EXP01 :: EXT_SERDES_SEL_CHANGE [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x100,8)
#define BRPHY2_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_MASK          0x0100
#define BRPHY2_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_ALIGN         0
#define BRPHY2_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_BITS          1
#define BRPHY2_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_SHIFT         8

/* BRPHY2_GPHY_CORE :: EXP01 :: MODE_SEL_CHANGE [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x80,7)
#define BRPHY2_GPHY_CORE_EXP01_MODE_SEL_CHANGE_MASK                0x0080
#define BRPHY2_GPHY_CORE_EXP01_MODE_SEL_CHANGE_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP01_MODE_SEL_CHANGE_BITS                1
#define BRPHY2_GPHY_CORE_EXP01_MODE_SEL_CHANGE_SHIFT               7

/* BRPHY2_GPHY_CORE :: EXP01 :: SERDES_LINK_STATUS_CHANGE [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x40,6)
#define BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_MASK      0x0040
#define BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_ALIGN     0
#define BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_BITS      1
#define BRPHY2_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_SHIFT     6

/* BRPHY2_GPHY_CORE :: EXP01 :: RUDI_C_DET [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_RUDI_C_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_RUDI_C_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x20,5)
#define BRPHY2_GPHY_CORE_EXP01_RUDI_C_DET_MASK                     0x0020
#define BRPHY2_GPHY_CORE_EXP01_RUDI_C_DET_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP01_RUDI_C_DET_BITS                     1
#define BRPHY2_GPHY_CORE_EXP01_RUDI_C_DET_SHIFT                    5

/* BRPHY2_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_ERR [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x10,4)
#define BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_MASK             0x0010
#define BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_ALIGN            0
#define BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_BITS             1
#define BRPHY2_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_SHIFT            4

/* BRPHY2_GPHY_CORE :: EXP01 :: RUDI_I_DET [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_RUDI_I_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_RUDI_I_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x8,3)
#define BRPHY2_GPHY_CORE_EXP01_RUDI_I_DET_MASK                     0x0008
#define BRPHY2_GPHY_CORE_EXP01_RUDI_I_DET_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP01_RUDI_I_DET_BITS                     1
#define BRPHY2_GPHY_CORE_EXP01_RUDI_I_DET_SHIFT                    3

/* BRPHY2_GPHY_CORE :: EXP01 :: SERDES_RCVD_BREAK_LINK_CONDITION [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x4,2)
#define BRPHY2_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_MASK 0x0004
#define BRPHY2_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_ALIGN 0
#define BRPHY2_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_BITS 1
#define BRPHY2_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_SHIFT 2

/* BRPHY2_GPHY_CORE :: EXP01 :: ABIST_COMPLETE [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_ABIST_COMPLETE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_ABIST_COMPLETE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x2,1)
#define BRPHY2_GPHY_CORE_EXP01_ABIST_COMPLETE_MASK                 0x0002
#define BRPHY2_GPHY_CORE_EXP01_ABIST_COMPLETE_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP01_ABIST_COMPLETE_BITS                 1
#define BRPHY2_GPHY_CORE_EXP01_ABIST_COMPLETE_SHIFT                1

/* BRPHY2_GPHY_CORE :: EXP01 :: TX_CRC_ERR [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP01_TX_CRC_ERR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP01,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP01_TX_CRC_ERR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP01,0x1,0)
#define BRPHY2_GPHY_CORE_EXP01_TX_CRC_ERR_MASK                     0x0001
#define BRPHY2_GPHY_CORE_EXP01_TX_CRC_ERR_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP01_TX_CRC_ERR_BITS                     1
#define BRPHY2_GPHY_CORE_EXP01_TX_CRC_ERR_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP02
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP02 :: EXP_INT_MASK [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP02_EXP_INT_MASK(x) WriteReg16(BRPHY2_GPHY_CORE_EXP02,x)
#define Rd_BRPHY2_GPHY_CORE_EXP02_EXP_INT_MASK(x) ReadReg16(BRPHY2_GPHY_CORE_EXP02)
#define BRPHY2_GPHY_CORE_EXP02_EXP_INT_MASK_MASK                   0xffff
#define BRPHY2_GPHY_CORE_EXP02_EXP_INT_MASK_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP02_EXP_INT_MASK_BITS                   16
#define BRPHY2_GPHY_CORE_EXP02_EXP_INT_MASK_SHIFT                  0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP03
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP03 :: SPARE_REG [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP03_SPARE_REG(x) WriteReg16(BRPHY2_GPHY_CORE_EXP03,x)
#define Rd_BRPHY2_GPHY_CORE_EXP03_SPARE_REG(x) ReadReg16(BRPHY2_GPHY_CORE_EXP03)
#define BRPHY2_GPHY_CORE_EXP03_SPARE_REG_MASK                      0xffff
#define BRPHY2_GPHY_CORE_EXP03_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP03_SPARE_REG_BITS                      16
#define BRPHY2_GPHY_CORE_EXP03_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP04
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP04 :: reserved0 [15:11] */
#define BRPHY2_GPHY_CORE_EXP04_RESERVED0_MASK                      0xf800
#define BRPHY2_GPHY_CORE_EXP04_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP04_RESERVED0_BITS                      5
#define BRPHY2_GPHY_CORE_EXP04_RESERVED0_SHIFT                     11

/* BRPHY2_GPHY_CORE :: EXP04 :: BC_LED_EN [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXP04_BC_LED_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP04,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXP04_BC_LED_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP04,0x400,10)
#define BRPHY2_GPHY_CORE_EXP04_BC_LED_EN_MASK                      0x0400
#define BRPHY2_GPHY_CORE_EXP04_BC_LED_EN_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP04_BC_LED_EN_BITS                      1
#define BRPHY2_GPHY_CORE_EXP04_BC_LED_EN_SHIFT                     10

/* BRPHY2_GPHY_CORE :: EXP04 :: FLASHNOW [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXP04_FLASHNOW(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP04,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXP04_FLASHNOW(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP04,0x200,9)
#define BRPHY2_GPHY_CORE_EXP04_FLASHNOW_MASK                       0x0200
#define BRPHY2_GPHY_CORE_EXP04_FLASHNOW_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP04_FLASHNOW_BITS                       1
#define BRPHY2_GPHY_CORE_EXP04_FLASHNOW_SHIFT                      9

/* BRPHY2_GPHY_CORE :: EXP04 :: INPHASE [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP04_INPHASE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP04,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP04_INPHASE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP04,0x100,8)
#define BRPHY2_GPHY_CORE_EXP04_INPHASE_MASK                        0x0100
#define BRPHY2_GPHY_CORE_EXP04_INPHASE_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP04_INPHASE_BITS                        1
#define BRPHY2_GPHY_CORE_EXP04_INPHASE_SHIFT                       8

/* BRPHY2_GPHY_CORE :: EXP04 :: BC_SEL_1 [07:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP04_BC_SEL_1(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP04,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP04_BC_SEL_1(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP04,0xf0,4)
#define BRPHY2_GPHY_CORE_EXP04_BC_SEL_1_MASK                       0x00f0
#define BRPHY2_GPHY_CORE_EXP04_BC_SEL_1_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP04_BC_SEL_1_BITS                       4
#define BRPHY2_GPHY_CORE_EXP04_BC_SEL_1_SHIFT                      4

/* BRPHY2_GPHY_CORE :: EXP04 :: BC_SEL_0 [03:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP04_BC_SEL_0(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP04,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP04_BC_SEL_0(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP04,0xf,0)
#define BRPHY2_GPHY_CORE_EXP04_BC_SEL_0_MASK                       0x000f
#define BRPHY2_GPHY_CORE_EXP04_BC_SEL_0_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP04_BC_SEL_0_BITS                       4
#define BRPHY2_GPHY_CORE_EXP04_BC_SEL_0_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP05
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP05 :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_EXP05_RESERVED0_MASK                      0xf000
#define BRPHY2_GPHY_CORE_EXP05_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP05_RESERVED0_BITS                      4
#define BRPHY2_GPHY_CORE_EXP05_RESERVED0_SHIFT                     12

/* BRPHY2_GPHY_CORE :: EXP05 :: ALTERNATION_RATE [11:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP05_ALTERNATION_RATE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP05,0xfc0,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP05_ALTERNATION_RATE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP05,0xfc0,6)
#define BRPHY2_GPHY_CORE_EXP05_ALTERNATION_RATE_MASK               0x0fc0
#define BRPHY2_GPHY_CORE_EXP05_ALTERNATION_RATE_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP05_ALTERNATION_RATE_BITS               6
#define BRPHY2_GPHY_CORE_EXP05_ALTERNATION_RATE_SHIFT              6

/* BRPHY2_GPHY_CORE :: EXP05 :: FLASH_RATE [05:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP05_FLASH_RATE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP05,0x3f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP05_FLASH_RATE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP05,0x3f,0)
#define BRPHY2_GPHY_CORE_EXP05_FLASH_RATE_MASK                     0x003f
#define BRPHY2_GPHY_CORE_EXP05_FLASH_RATE_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP05_FLASH_RATE_BITS                     6
#define BRPHY2_GPHY_CORE_EXP05_FLASH_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP06
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP06 :: reserved0 [15:08] */
#define BRPHY2_GPHY_CORE_EXP06_RESERVED0_MASK                      0xff00
#define BRPHY2_GPHY_CORE_EXP06_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP06_RESERVED0_BITS                      8
#define BRPHY2_GPHY_CORE_EXP06_RESERVED0_SHIFT                     8

/* BRPHY2_GPHY_CORE :: EXP06 :: SPARE_REG [07:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP06_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP06,0xc0,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP06_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP06,0xc0,6)
#define BRPHY2_GPHY_CORE_EXP06_SPARE_REG_MASK                      0x00c0
#define BRPHY2_GPHY_CORE_EXP06_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP06_SPARE_REG_BITS                      2
#define BRPHY2_GPHY_CORE_EXP06_SPARE_REG_SHIFT                     6

/* BRPHY2_GPHY_CORE :: EXP06 :: BLINK_UPDATE_NOW [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP06,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP06,0x20,5)
#define BRPHY2_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_MASK               0x0020
#define BRPHY2_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_BITS               1
#define BRPHY2_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_SHIFT              5

/* BRPHY2_GPHY_CORE :: EXP06 :: BLINK_RATE [04:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP06_BLINK_RATE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP06,0x1f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP06_BLINK_RATE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP06,0x1f,0)
#define BRPHY2_GPHY_CORE_EXP06_BLINK_RATE_MASK                     0x001f
#define BRPHY2_GPHY_CORE_EXP06_BLINK_RATE_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP06_BLINK_RATE_BITS                     5
#define BRPHY2_GPHY_CORE_EXP06_BLINK_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP07
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP07 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_EXP07_RESERVED0_MASK                      0x8000
#define BRPHY2_GPHY_CORE_EXP07_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP07_RESERVED0_BITS                      1
#define BRPHY2_GPHY_CORE_EXP07_RESERVED0_SHIFT                     15

/* BRPHY2_GPHY_CORE :: EXP07 :: EXT_MAX_LP_WIDTH [14:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP07,0x7f00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP07,0x7f00,8)
#define BRPHY2_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_MASK               0x7f00
#define BRPHY2_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_BITS               7
#define BRPHY2_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_SHIFT              8

/* BRPHY2_GPHY_CORE :: EXP07 :: SPARE_REG [07:03] */
#define Wr_BRPHY2_GPHY_CORE_EXP07_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP07,0xf8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXP07_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP07,0xf8,3)
#define BRPHY2_GPHY_CORE_EXP07_SPARE_REG_MASK                      0x00f8
#define BRPHY2_GPHY_CORE_EXP07_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP07_SPARE_REG_BITS                      5
#define BRPHY2_GPHY_CORE_EXP07_SPARE_REG_SHIFT                     3

/* BRPHY2_GPHY_CORE :: EXP07 :: COPPER_FX_SIGSTAT_SEL [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP07,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP07,0x4,2)
#define BRPHY2_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_MASK          0x0004
#define BRPHY2_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_ALIGN         0
#define BRPHY2_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_BITS          1
#define BRPHY2_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_SHIFT         2

/* BRPHY2_GPHY_CORE :: EXP07 :: FAULTING [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP07_FAULTING(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP07,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP07_FAULTING(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP07,0x2,1)
#define BRPHY2_GPHY_CORE_EXP07_FAULTING_MASK                       0x0002
#define BRPHY2_GPHY_CORE_EXP07_FAULTING_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP07_FAULTING_BITS                       1
#define BRPHY2_GPHY_CORE_EXP07_FAULTING_SHIFT                      1

/* BRPHY2_GPHY_CORE :: EXP07 :: FEF_EN [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP07_FEF_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP07,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP07_FEF_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP07,0x1,0)
#define BRPHY2_GPHY_CORE_EXP07_FEF_EN_MASK                         0x0001
#define BRPHY2_GPHY_CORE_EXP07_FEF_EN_ALIGN                        0
#define BRPHY2_GPHY_CORE_EXP07_FEF_EN_BITS                         1
#define BRPHY2_GPHY_CORE_EXP07_FEF_EN_SHIFT                        0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP08
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP08 :: SILENT_LPBK [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_SILENT_LPBK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_SILENT_LPBK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x8000,15)
#define BRPHY2_GPHY_CORE_EXP08_SILENT_LPBK_MASK                    0x8000
#define BRPHY2_GPHY_CORE_EXP08_SILENT_LPBK_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP08_SILENT_LPBK_BITS                    1
#define BRPHY2_GPHY_CORE_EXP08_SILENT_LPBK_SHIFT                   15

/* BRPHY2_GPHY_CORE :: EXP08 :: RX_POLARITY_OV [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x4000,14)
#define BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_MASK                 0x4000
#define BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_BITS                 1
#define BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_SHIFT                14

/* BRPHY2_GPHY_CORE :: EXP08 :: RX_POLARITY_OV_VAL [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x2000,13)
#define BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_MASK             0x2000
#define BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_ALIGN            0
#define BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_BITS             1
#define BRPHY2_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_SHIFT            13

/* BRPHY2_GPHY_CORE :: EXP08 :: BT_BYTE_ALIGN_PREAM [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_MASK            0x1000
#define BRPHY2_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_ALIGN           0
#define BRPHY2_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_BITS            1
#define BRPHY2_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_SHIFT           12

/* BRPHY2_GPHY_CORE :: EXP08 :: BT_PREAM_SUPPRESS [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x800,11)
#define BRPHY2_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_MASK              0x0800
#define BRPHY2_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_BITS              1
#define BRPHY2_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_SHIFT             11

/* BRPHY2_GPHY_CORE :: EXP08 :: EXT_MAX_LP_WIDTH_EN [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x400,10)
#define BRPHY2_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_MASK            0x0400
#define BRPHY2_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_BITS            1
#define BRPHY2_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_SHIFT           10

/* BRPHY2_GPHY_CORE :: EXP08 :: AUTO_EARLY_DAC_WAKE [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x200,9)
#define BRPHY2_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_MASK            0x0200
#define BRPHY2_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_ALIGN           0
#define BRPHY2_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_BITS            1
#define BRPHY2_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_SHIFT           9

/* BRPHY2_GPHY_CORE :: EXP08 :: FORCE_EARLY_DAC_WAKE [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x100,8)
#define BRPHY2_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_MASK           0x0100
#define BRPHY2_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_ALIGN          0
#define BRPHY2_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_BITS           1
#define BRPHY2_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_SHIFT          8

/* BRPHY2_GPHY_CORE :: EXP08 :: SUPPRESS_CRS_HDX [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x80,7)
#define BRPHY2_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_MASK               0x0080
#define BRPHY2_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_BITS               1
#define BRPHY2_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_SHIFT              7

/* BRPHY2_GPHY_CORE :: EXP08 :: REJECT_MORE_15MHZ [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x40,6)
#define BRPHY2_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_MASK              0x0040
#define BRPHY2_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_BITS              1
#define BRPHY2_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_SHIFT             6

/* BRPHY2_GPHY_CORE :: EXP08 :: POLARITY_INVERT [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_POLARITY_INVERT(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_POLARITY_INVERT(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x20,5)
#define BRPHY2_GPHY_CORE_EXP08_POLARITY_INVERT_MASK                0x0020
#define BRPHY2_GPHY_CORE_EXP08_POLARITY_INVERT_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP08_POLARITY_INVERT_BITS                1
#define BRPHY2_GPHY_CORE_EXP08_POLARITY_INVERT_SHIFT               5

/* BRPHY2_GPHY_CORE :: EXP08 :: BLOCK_NARROW_LP [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x10,4)
#define BRPHY2_GPHY_CORE_EXP08_BLOCK_NARROW_LP_MASK                0x0010
#define BRPHY2_GPHY_CORE_EXP08_BLOCK_NARROW_LP_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP08_BLOCK_NARROW_LP_BITS                1
#define BRPHY2_GPHY_CORE_EXP08_BLOCK_NARROW_LP_SHIFT               4

/* BRPHY2_GPHY_CORE :: EXP08 :: USE_OLD_LPDET [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_USE_OLD_LPDET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_USE_OLD_LPDET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x8,3)
#define BRPHY2_GPHY_CORE_EXP08_USE_OLD_LPDET_MASK                  0x0008
#define BRPHY2_GPHY_CORE_EXP08_USE_OLD_LPDET_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP08_USE_OLD_LPDET_BITS                  1
#define BRPHY2_GPHY_CORE_EXP08_USE_OLD_LPDET_SHIFT                 3

/* BRPHY2_GPHY_CORE :: EXP08 :: EDGESTATE_REFINE [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x4,2)
#define BRPHY2_GPHY_CORE_EXP08_EDGESTATE_REFINE_MASK               0x0004
#define BRPHY2_GPHY_CORE_EXP08_EDGESTATE_REFINE_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP08_EDGESTATE_REFINE_BITS               1
#define BRPHY2_GPHY_CORE_EXP08_EDGESTATE_REFINE_SHIFT              2

/* BRPHY2_GPHY_CORE :: EXP08 :: REJECT_15MHZ [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_REJECT_15MHZ(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_REJECT_15MHZ(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x2,1)
#define BRPHY2_GPHY_CORE_EXP08_REJECT_15MHZ_MASK                   0x0002
#define BRPHY2_GPHY_CORE_EXP08_REJECT_15MHZ_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP08_REJECT_15MHZ_BITS                   1
#define BRPHY2_GPHY_CORE_EXP08_REJECT_15MHZ_SHIFT                  1

/* BRPHY2_GPHY_CORE :: EXP08 :: REJECT_2MHZ [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP08_REJECT_2MHZ(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP08,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP08_REJECT_2MHZ(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP08,0x1,0)
#define BRPHY2_GPHY_CORE_EXP08_REJECT_2MHZ_MASK                    0x0001
#define BRPHY2_GPHY_CORE_EXP08_REJECT_2MHZ_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP08_REJECT_2MHZ_BITS                    1
#define BRPHY2_GPHY_CORE_EXP08_REJECT_2MHZ_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP09
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP09 :: GIGABIT_POL_INV [15:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP09,0xf000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP09,0xf000,12)
#define BRPHY2_GPHY_CORE_EXP09_GIGABIT_POL_INV_MASK                0xf000
#define BRPHY2_GPHY_CORE_EXP09_GIGABIT_POL_INV_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP09_GIGABIT_POL_INV_BITS                4
#define BRPHY2_GPHY_CORE_EXP09_GIGABIT_POL_INV_SHIFT               12

/* BRPHY2_GPHY_CORE :: EXP09 :: SPARE_REG [11:09] */
#define Wr_BRPHY2_GPHY_CORE_EXP09_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP09,0xe00,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXP09_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP09,0xe00,9)
#define BRPHY2_GPHY_CORE_EXP09_SPARE_REG_MASK                      0x0e00
#define BRPHY2_GPHY_CORE_EXP09_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP09_SPARE_REG_BITS                      3
#define BRPHY2_GPHY_CORE_EXP09_SPARE_REG_SHIFT                     9

/* BRPHY2_GPHY_CORE :: EXP09 :: ALLOW_SWAP [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP09_ALLOW_SWAP(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP09,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP09_ALLOW_SWAP(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP09,0x100,8)
#define BRPHY2_GPHY_CORE_EXP09_ALLOW_SWAP_MASK                     0x0100
#define BRPHY2_GPHY_CORE_EXP09_ALLOW_SWAP_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP09_ALLOW_SWAP_BITS                     1
#define BRPHY2_GPHY_CORE_EXP09_ALLOW_SWAP_SHIFT                    8

/* BRPHY2_GPHY_CORE :: EXP09 :: CH3_SEL [07:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP09_CH3_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP09,0xc0,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP09_CH3_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP09,0xc0,6)
#define BRPHY2_GPHY_CORE_EXP09_CH3_SEL_MASK                        0x00c0
#define BRPHY2_GPHY_CORE_EXP09_CH3_SEL_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP09_CH3_SEL_BITS                        2
#define BRPHY2_GPHY_CORE_EXP09_CH3_SEL_SHIFT                       6

/* BRPHY2_GPHY_CORE :: EXP09 :: CH2_SEL [05:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP09_CH2_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP09,0x30,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP09_CH2_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP09,0x30,4)
#define BRPHY2_GPHY_CORE_EXP09_CH2_SEL_MASK                        0x0030
#define BRPHY2_GPHY_CORE_EXP09_CH2_SEL_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP09_CH2_SEL_BITS                        2
#define BRPHY2_GPHY_CORE_EXP09_CH2_SEL_SHIFT                       4

/* BRPHY2_GPHY_CORE :: EXP09 :: CH1_SEL [03:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP09_CH1_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP09,0xc,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP09_CH1_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP09,0xc,2)
#define BRPHY2_GPHY_CORE_EXP09_CH1_SEL_MASK                        0x000c
#define BRPHY2_GPHY_CORE_EXP09_CH1_SEL_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP09_CH1_SEL_BITS                        2
#define BRPHY2_GPHY_CORE_EXP09_CH1_SEL_SHIFT                       2

/* BRPHY2_GPHY_CORE :: EXP09 :: CH0_SEL [01:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP09_CH0_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP09,0x3,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP09_CH0_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP09,0x3,0)
#define BRPHY2_GPHY_CORE_EXP09_CH0_SEL_MASK                        0x0003
#define BRPHY2_GPHY_CORE_EXP09_CH0_SEL_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP09_CH0_SEL_BITS                        2
#define BRPHY2_GPHY_CORE_EXP09_CH0_SEL_SHIFT                       0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP0A
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP0A :: reserved0 [15:13] */
#define BRPHY2_GPHY_CORE_EXP0A_RESERVED0_MASK                      0xe000
#define BRPHY2_GPHY_CORE_EXP0A_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP0A_RESERVED0_BITS                      3
#define BRPHY2_GPHY_CORE_EXP0A_RESERVED0_SHIFT                     13

/* BRPHY2_GPHY_CORE :: EXP0A :: SYNC_IN_EN [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP0A_SYNC_IN_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP0A_SYNC_IN_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP0A_SYNC_IN_EN_MASK                     0x1000
#define BRPHY2_GPHY_CORE_EXP0A_SYNC_IN_EN_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP0A_SYNC_IN_EN_BITS                     1
#define BRPHY2_GPHY_CORE_EXP0A_SYNC_IN_EN_SHIFT                    12

/* BRPHY2_GPHY_CORE :: EXP0A :: CHANNEL_KILL [11:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP0A_CHANNEL_KILL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP0A,0xf00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP0A_CHANNEL_KILL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP0A,0xf00,8)
#define BRPHY2_GPHY_CORE_EXP0A_CHANNEL_KILL_MASK                   0x0f00
#define BRPHY2_GPHY_CORE_EXP0A_CHANNEL_KILL_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP0A_CHANNEL_KILL_BITS                   4
#define BRPHY2_GPHY_CORE_EXP0A_CHANNEL_KILL_SHIFT                  8

/* BRPHY2_GPHY_CORE :: EXP0A :: SYNC_KILL [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXP0A_SYNC_KILL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXP0A_SYNC_KILL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x80,7)
#define BRPHY2_GPHY_CORE_EXP0A_SYNC_KILL_MASK                      0x0080
#define BRPHY2_GPHY_CORE_EXP0A_SYNC_KILL_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP0A_SYNC_KILL_BITS                      1
#define BRPHY2_GPHY_CORE_EXP0A_SYNC_KILL_SHIFT                     7

/* BRPHY2_GPHY_CORE :: EXP0A :: BYPASS_ENE [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP0A_BYPASS_ENE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP0A_BYPASS_ENE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x40,6)
#define BRPHY2_GPHY_CORE_EXP0A_BYPASS_ENE_MASK                     0x0040
#define BRPHY2_GPHY_CORE_EXP0A_BYPASS_ENE_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP0A_BYPASS_ENE_BITS                     1
#define BRPHY2_GPHY_CORE_EXP0A_BYPASS_ENE_SHIFT                    6

/* BRPHY2_GPHY_CORE :: EXP0A :: PAT_DURATION [05:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP0A_PAT_DURATION(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x30,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP0A_PAT_DURATION(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x30,4)
#define BRPHY2_GPHY_CORE_EXP0A_PAT_DURATION_MASK                   0x0030
#define BRPHY2_GPHY_CORE_EXP0A_PAT_DURATION_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP0A_PAT_DURATION_BITS                   2
#define BRPHY2_GPHY_CORE_EXP0A_PAT_DURATION_SHIFT                  4

/* BRPHY2_GPHY_CORE :: EXP0A :: PAT_SEL [03:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP0A_PAT_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP0A,0xe,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP0A_PAT_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP0A,0xe,1)
#define BRPHY2_GPHY_CORE_EXP0A_PAT_SEL_MASK                        0x000e
#define BRPHY2_GPHY_CORE_EXP0A_PAT_SEL_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP0A_PAT_SEL_BITS                        3
#define BRPHY2_GPHY_CORE_EXP0A_PAT_SEL_SHIFT                       1

/* BRPHY2_GPHY_CORE :: EXP0A :: TEMPLATE_EN [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP0A_TEMPLATE_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP0A_TEMPLATE_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP0A,0x1,0)
#define BRPHY2_GPHY_CORE_EXP0A_TEMPLATE_EN_MASK                    0x0001
#define BRPHY2_GPHY_CORE_EXP0A_TEMPLATE_EN_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP0A_TEMPLATE_EN_BITS                    1
#define BRPHY2_GPHY_CORE_EXP0A_TEMPLATE_EN_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP0B
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP0B :: EXT_STATUS [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP0B_EXT_STATUS(x) WriteReg16(BRPHY2_GPHY_CORE_EXP0B,x)
#define Rd_BRPHY2_GPHY_CORE_EXP0B_EXT_STATUS(x) ReadReg16(BRPHY2_GPHY_CORE_EXP0B)
#define BRPHY2_GPHY_CORE_EXP0B_EXT_STATUS_MASK                     0xffff
#define BRPHY2_GPHY_CORE_EXP0B_EXT_STATUS_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP0B_EXT_STATUS_BITS                     16
#define BRPHY2_GPHY_CORE_EXP0B_EXT_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP0C
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP0C :: SPARE_REG [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP0C_SPARE_REG(x) WriteReg16(BRPHY2_GPHY_CORE_EXP0C,x)
#define Rd_BRPHY2_GPHY_CORE_EXP0C_SPARE_REG(x) ReadReg16(BRPHY2_GPHY_CORE_EXP0C)
#define BRPHY2_GPHY_CORE_EXP0C_SPARE_REG_MASK                      0xffff
#define BRPHY2_GPHY_CORE_EXP0C_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP0C_SPARE_REG_BITS                      16
#define BRPHY2_GPHY_CORE_EXP0C_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP30
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP30 :: reserved0 [15:05] */
#define BRPHY2_GPHY_CORE_EXP30_RESERVED0_MASK                      0xffe0
#define BRPHY2_GPHY_CORE_EXP30_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP30_RESERVED0_BITS                      11
#define BRPHY2_GPHY_CORE_EXP30_RESERVED0_SHIFT                     5

/* BRPHY2_GPHY_CORE :: EXP30 :: DEADMAN_RESET [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP30_DEADMAN_RESET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP30,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP30_DEADMAN_RESET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP30,0x10,4)
#define BRPHY2_GPHY_CORE_EXP30_DEADMAN_RESET_MASK                  0x0010
#define BRPHY2_GPHY_CORE_EXP30_DEADMAN_RESET_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP30_DEADMAN_RESET_BITS                  1
#define BRPHY2_GPHY_CORE_EXP30_DEADMAN_RESET_SHIFT                 4

/* BRPHY2_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_128_TO_255 [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP30,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP30,0x8,3)
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_MASK       0x0008
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_ALIGN      0
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_BITS       1
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_SHIFT      3

/* BRPHY2_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_64_TO_127 [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP30,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP30,0x4,2)
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_MASK        0x0004
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_ALIGN       0
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_BITS        1
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_SHIFT       2

/* BRPHY2_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_32_TO_63 [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP30,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP30,0x2,1)
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_MASK         0x0002
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_ALIGN        0
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_BITS         1
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_SHIFT        1

/* BRPHY2_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_0_TO_31 [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP30,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP30,0x1,0)
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_MASK          0x0001
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_ALIGN         0
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_BITS          1
#define BRPHY2_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_SHIFT         0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP31
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP31 :: reserved0 [15:08] */
#define BRPHY2_GPHY_CORE_EXP31_RESERVED0_MASK                      0xff00
#define BRPHY2_GPHY_CORE_EXP31_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP31_RESERVED0_BITS                      8
#define BRPHY2_GPHY_CORE_EXP31_RESERVED0_SHIFT                     8

/* BRPHY2_GPHY_CORE :: EXP31 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP31_LATE_COL_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP31,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP31_LATE_COL_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP31,0xff,0)
#define BRPHY2_GPHY_CORE_EXP31_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY2_GPHY_CORE_EXP31_LATE_COL_CNTR_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP31_LATE_COL_CNTR_BITS                  8
#define BRPHY2_GPHY_CORE_EXP31_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP32
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP32 :: reserved0 [15:08] */
#define BRPHY2_GPHY_CORE_EXP32_RESERVED0_MASK                      0xff00
#define BRPHY2_GPHY_CORE_EXP32_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP32_RESERVED0_BITS                      8
#define BRPHY2_GPHY_CORE_EXP32_RESERVED0_SHIFT                     8

/* BRPHY2_GPHY_CORE :: EXP32 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP32_LATE_COL_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP32,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP32_LATE_COL_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP32,0xff,0)
#define BRPHY2_GPHY_CORE_EXP32_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY2_GPHY_CORE_EXP32_LATE_COL_CNTR_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP32_LATE_COL_CNTR_BITS                  8
#define BRPHY2_GPHY_CORE_EXP32_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP33
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP33 :: reserved0 [15:08] */
#define BRPHY2_GPHY_CORE_EXP33_RESERVED0_MASK                      0xff00
#define BRPHY2_GPHY_CORE_EXP33_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP33_RESERVED0_BITS                      8
#define BRPHY2_GPHY_CORE_EXP33_RESERVED0_SHIFT                     8

/* BRPHY2_GPHY_CORE :: EXP33 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP33_LATE_COL_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP33,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP33_LATE_COL_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP33,0xff,0)
#define BRPHY2_GPHY_CORE_EXP33_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY2_GPHY_CORE_EXP33_LATE_COL_CNTR_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP33_LATE_COL_CNTR_BITS                  8
#define BRPHY2_GPHY_CORE_EXP33_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP34
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP34 :: reserved0 [15:08] */
#define BRPHY2_GPHY_CORE_EXP34_RESERVED0_MASK                      0xff00
#define BRPHY2_GPHY_CORE_EXP34_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP34_RESERVED0_BITS                      8
#define BRPHY2_GPHY_CORE_EXP34_RESERVED0_SHIFT                     8

/* BRPHY2_GPHY_CORE :: EXP34 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP34_LATE_COL_CNTR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP34,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP34_LATE_COL_CNTR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP34,0xff,0)
#define BRPHY2_GPHY_CORE_EXP34_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY2_GPHY_CORE_EXP34_LATE_COL_CNTR_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP34_LATE_COL_CNTR_BITS                  8
#define BRPHY2_GPHY_CORE_EXP34_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP35
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP35 :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_EXP35_RESERVED0_MASK                      0xf000
#define BRPHY2_GPHY_CORE_EXP35_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP35_RESERVED0_BITS                      4
#define BRPHY2_GPHY_CORE_EXP35_RESERVED0_SHIFT                     12

/* BRPHY2_GPHY_CORE :: EXP35 :: MII_INTERFACE_MODES [11:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP35,0xf00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP35,0xf00,8)
#define BRPHY2_GPHY_CORE_EXP35_MII_INTERFACE_MODES_MASK            0x0f00
#define BRPHY2_GPHY_CORE_EXP35_MII_INTERFACE_MODES_ALIGN           0
#define BRPHY2_GPHY_CORE_EXP35_MII_INTERFACE_MODES_BITS            4
#define BRPHY2_GPHY_CORE_EXP35_MII_INTERFACE_MODES_SHIFT           8

/* BRPHY2_GPHY_CORE :: EXP35 :: LATE_COL_CNTR_THD [07:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP35,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP35,0xff,0)
#define BRPHY2_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_MASK              0x00ff
#define BRPHY2_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_BITS              8
#define BRPHY2_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_SHIFT             0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP36
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP36 :: PPM_DET_PWRDN [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP36,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP36,0x8000,15)
#define BRPHY2_GPHY_CORE_EXP36_PPM_DET_PWRDN_MASK                  0x8000
#define BRPHY2_GPHY_CORE_EXP36_PPM_DET_PWRDN_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP36_PPM_DET_PWRDN_BITS                  1
#define BRPHY2_GPHY_CORE_EXP36_PPM_DET_PWRDN_SHIFT                 15

/* BRPHY2_GPHY_CORE :: EXP36 :: PPM_DET_TEST [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXP36_PPM_DET_TEST(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP36,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXP36_PPM_DET_TEST(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP36,0x4000,14)
#define BRPHY2_GPHY_CORE_EXP36_PPM_DET_TEST_MASK                   0x4000
#define BRPHY2_GPHY_CORE_EXP36_PPM_DET_TEST_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP36_PPM_DET_TEST_BITS                   1
#define BRPHY2_GPHY_CORE_EXP36_PPM_DET_TEST_SHIFT                  14

/* BRPHY2_GPHY_CORE :: EXP36 :: reserved0 [13:10] */
#define BRPHY2_GPHY_CORE_EXP36_RESERVED0_MASK                      0x3c00
#define BRPHY2_GPHY_CORE_EXP36_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP36_RESERVED0_BITS                      4
#define BRPHY2_GPHY_CORE_EXP36_RESERVED0_SHIFT                     10

/* BRPHY2_GPHY_CORE :: EXP36 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP36_PPM_OFFSET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP36,0x3ff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP36_PPM_OFFSET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP36,0x3ff,0)
#define BRPHY2_GPHY_CORE_EXP36_PPM_OFFSET_MASK                     0x03ff
#define BRPHY2_GPHY_CORE_EXP36_PPM_OFFSET_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP36_PPM_OFFSET_BITS                     10
#define BRPHY2_GPHY_CORE_EXP36_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP37
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP37 :: reserved0 [15:10] */
#define BRPHY2_GPHY_CORE_EXP37_RESERVED0_MASK                      0xfc00
#define BRPHY2_GPHY_CORE_EXP37_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP37_RESERVED0_BITS                      6
#define BRPHY2_GPHY_CORE_EXP37_RESERVED0_SHIFT                     10

/* BRPHY2_GPHY_CORE :: EXP37 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP37_PPM_OFFSET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP37,0x3ff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP37_PPM_OFFSET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP37,0x3ff,0)
#define BRPHY2_GPHY_CORE_EXP37_PPM_OFFSET_MASK                     0x03ff
#define BRPHY2_GPHY_CORE_EXP37_PPM_OFFSET_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP37_PPM_OFFSET_BITS                     10
#define BRPHY2_GPHY_CORE_EXP37_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP38
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP38 :: IP_PHONE_DET_CHANGE [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP38,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP38,0x8000,15)
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_MASK            0x8000
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_ALIGN           0
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_BITS            1
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_SHIFT           15

/* BRPHY2_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH_CHANGE [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP38,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP38,0x4000,14)
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_MASK       0x4000
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_ALIGN      0
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_BITS       1
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_SHIFT      14

/* BRPHY2_GPHY_CORE :: EXP38 :: IP_PHONE_FLP_BURST_TX [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP38,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP38,0x2000,13)
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_MASK          0x2000
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_ALIGN         0
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_BITS          1
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_SHIFT         13

/* BRPHY2_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP38,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP38,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_MASK              0x1000
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_BITS              1
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_SHIFT             12

/* BRPHY2_GPHY_CORE :: EXP38 :: IP_PHONE_DET [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP38,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP38,0x800,11)
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_MASK                   0x0800
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_BITS                   1
#define BRPHY2_GPHY_CORE_EXP38_IP_PHONE_DET_SHIFT                  11

/* BRPHY2_GPHY_CORE :: EXP38 :: NO_RESPSONSE [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXP38_NO_RESPSONSE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP38,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXP38_NO_RESPSONSE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP38,0x400,10)
#define BRPHY2_GPHY_CORE_EXP38_NO_RESPSONSE_MASK                   0x0400
#define BRPHY2_GPHY_CORE_EXP38_NO_RESPSONSE_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP38_NO_RESPSONSE_BITS                   1
#define BRPHY2_GPHY_CORE_EXP38_NO_RESPSONSE_SHIFT                  10

/* BRPHY2_GPHY_CORE :: EXP38 :: TOTAL_RT_DLY [09:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP38,0x3ff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP38,0x3ff,0)
#define BRPHY2_GPHY_CORE_EXP38_TOTAL_RT_DLY_MASK                   0x03ff
#define BRPHY2_GPHY_CORE_EXP38_TOTAL_RT_DLY_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP38_TOTAL_RT_DLY_BITS                   10
#define BRPHY2_GPHY_CORE_EXP38_TOTAL_RT_DLY_SHIFT                  0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP42
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP42 :: SERDES_LINK [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_SERDES_LINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_SERDES_LINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x8000,15)
#define BRPHY2_GPHY_CORE_EXP42_SERDES_LINK_MASK                    0x8000
#define BRPHY2_GPHY_CORE_EXP42_SERDES_LINK_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP42_SERDES_LINK_BITS                    1
#define BRPHY2_GPHY_CORE_EXP42_SERDES_LINK_SHIFT                   15

/* BRPHY2_GPHY_CORE :: EXP42 :: SERDES_SPEED [14:13] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_SERDES_SPEED(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x6000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_SERDES_SPEED(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x6000,13)
#define BRPHY2_GPHY_CORE_EXP42_SERDES_SPEED_MASK                   0x6000
#define BRPHY2_GPHY_CORE_EXP42_SERDES_SPEED_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP42_SERDES_SPEED_BITS                   2
#define BRPHY2_GPHY_CORE_EXP42_SERDES_SPEED_SHIFT                  13

/* BRPHY2_GPHY_CORE :: EXP42 :: SERDES_DUPLEX [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_SERDES_DUPLEX(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_SERDES_DUPLEX(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP42_SERDES_DUPLEX_MASK                  0x1000
#define BRPHY2_GPHY_CORE_EXP42_SERDES_DUPLEX_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP42_SERDES_DUPLEX_BITS                  1
#define BRPHY2_GPHY_CORE_EXP42_SERDES_DUPLEX_SHIFT                 12

/* BRPHY2_GPHY_CORE :: EXP42 :: COPPER_LINK [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_COPPER_LINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_COPPER_LINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x800,11)
#define BRPHY2_GPHY_CORE_EXP42_COPPER_LINK_MASK                    0x0800
#define BRPHY2_GPHY_CORE_EXP42_COPPER_LINK_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP42_COPPER_LINK_BITS                    1
#define BRPHY2_GPHY_CORE_EXP42_COPPER_LINK_SHIFT                   11

/* BRPHY2_GPHY_CORE :: EXP42 :: COPPER_SPEED [10:09] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_COPPER_SPEED(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x600,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_COPPER_SPEED(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x600,9)
#define BRPHY2_GPHY_CORE_EXP42_COPPER_SPEED_MASK                   0x0600
#define BRPHY2_GPHY_CORE_EXP42_COPPER_SPEED_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP42_COPPER_SPEED_BITS                   2
#define BRPHY2_GPHY_CORE_EXP42_COPPER_SPEED_SHIFT                  9

/* BRPHY2_GPHY_CORE :: EXP42 :: COPPER_DUPLEX [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_COPPER_DUPLEX(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_COPPER_DUPLEX(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x100,8)
#define BRPHY2_GPHY_CORE_EXP42_COPPER_DUPLEX_MASK                  0x0100
#define BRPHY2_GPHY_CORE_EXP42_COPPER_DUPLEX_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP42_COPPER_DUPLEX_BITS                  1
#define BRPHY2_GPHY_CORE_EXP42_COPPER_DUPLEX_SHIFT                 8

/* BRPHY2_GPHY_CORE :: EXP42 :: COPPER_ENERGY_DETECT [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x80,7)
#define BRPHY2_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_MASK           0x0080
#define BRPHY2_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_ALIGN          0
#define BRPHY2_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_BITS           1
#define BRPHY2_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_SHIFT          7

/* BRPHY2_GPHY_CORE :: EXP42 :: FIBER_SIGNAL_DETECT [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x40,6)
#define BRPHY2_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_MASK            0x0040
#define BRPHY2_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_ALIGN           0
#define BRPHY2_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_BITS            1
#define BRPHY2_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_SHIFT           6

/* BRPHY2_GPHY_CORE :: EXP42 :: SYNC_STATUS [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_SYNC_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_SYNC_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x20,5)
#define BRPHY2_GPHY_CORE_EXP42_SYNC_STATUS_MASK                    0x0020
#define BRPHY2_GPHY_CORE_EXP42_SYNC_STATUS_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP42_SYNC_STATUS_BITS                    1
#define BRPHY2_GPHY_CORE_EXP42_SYNC_STATUS_SHIFT                   5

/* BRPHY2_GPHY_CORE :: EXP42 :: OPERATING_MODE_STATUS [04:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP42,0x1f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP42,0x1f,0)
#define BRPHY2_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_MASK          0x001f
#define BRPHY2_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_ALIGN         0
#define BRPHY2_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_BITS          5
#define BRPHY2_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_SHIFT         0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP5F
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP5F :: PLL_TCLK_OFFSET [15:10] */
#define Wr_BRPHY2_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP5F,0xfc00,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP5F,0xfc00,10)
#define BRPHY2_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_MASK                0xfc00
#define BRPHY2_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_BITS                6
#define BRPHY2_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_SHIFT               10

/* BRPHY2_GPHY_CORE :: EXP5F :: PLL_RCLK_OFFSET [09:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP5F,0x3f0,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP5F,0x3f0,4)
#define BRPHY2_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_MASK                0x03f0
#define BRPHY2_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_BITS                6
#define BRPHY2_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_SHIFT               4

/* BRPHY2_GPHY_CORE :: EXP5F :: PLLTEST_CNT [03:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP5F_PLLTEST_CNT(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP5F,0xc,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP5F_PLLTEST_CNT(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP5F,0xc,2)
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_CNT_MASK                    0x000c
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_CNT_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_CNT_BITS                    2
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_CNT_SHIFT                   2

/* BRPHY2_GPHY_CORE :: EXP5F :: PLLTEST [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP5F_PLLTEST(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP5F,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP5F_PLLTEST(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP5F,0x2,1)
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_MASK                        0x0002
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_BITS                        1
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_SHIFT                       1

/* BRPHY2_GPHY_CORE :: EXP5F :: PLLTEST_EN [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP5F_PLLTEST_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP5F,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP5F_PLLTEST_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP5F,0x1,0)
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_EN_MASK                     0x0001
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_EN_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_EN_BITS                     1
#define BRPHY2_GPHY_CORE_EXP5F_PLLTEST_EN_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP70
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP70 :: reserved0 [15:01] */
#define BRPHY2_GPHY_CORE_EXP70_RESERVED0_MASK                      0xfffe
#define BRPHY2_GPHY_CORE_EXP70_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP70_RESERVED0_BITS                      15
#define BRPHY2_GPHY_CORE_EXP70_RESERVED0_SHIFT                     1

/* BRPHY2_GPHY_CORE :: EXP70 :: SOFT_RESET [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP70_SOFT_RESET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP70,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP70_SOFT_RESET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP70,0x1,0)
#define BRPHY2_GPHY_CORE_EXP70_SOFT_RESET_MASK                     0x0001
#define BRPHY2_GPHY_CORE_EXP70_SOFT_RESET_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP70_SOFT_RESET_BITS                     1
#define BRPHY2_GPHY_CORE_EXP70_SOFT_RESET_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP71
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP71 :: reserved0 [15:14] */
#define BRPHY2_GPHY_CORE_EXP71_RESERVED0_MASK                      0xc000
#define BRPHY2_GPHY_CORE_EXP71_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP71_RESERVED0_BITS                      2
#define BRPHY2_GPHY_CORE_EXP71_RESERVED0_SHIFT                     14

/* BRPHY2_GPHY_CORE :: EXP71 :: SERIAL_LED_EN [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP71,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP71,0x2000,13)
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_EN_MASK                  0x2000
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_EN_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_EN_BITS                  1
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_EN_SHIFT                 13

/* BRPHY2_GPHY_CORE :: EXP71 :: LOW_COST_LED_EN [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP71,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP71,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP71_LOW_COST_LED_EN_MASK                0x1000
#define BRPHY2_GPHY_CORE_EXP71_LOW_COST_LED_EN_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP71_LOW_COST_LED_EN_BITS                1
#define BRPHY2_GPHY_CORE_EXP71_LOW_COST_LED_EN_SHIFT               12

/* BRPHY2_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_6 [11:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP71,0xf00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP71,0xf00,8)
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_MASK               0x0f00
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_BITS               4
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_SHIFT              8

/* BRPHY2_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_5 [07:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP71,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP71,0xf0,4)
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_MASK               0x00f0
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_BITS               4
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_SHIFT              4

/* BRPHY2_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_4 [03:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP71,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP71,0xf,0)
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_MASK               0x000f
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_BITS               4
#define BRPHY2_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP72
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP72 :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_EXP72_RESERVED0_MASK                      0xf000
#define BRPHY2_GPHY_CORE_EXP72_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP72_RESERVED0_BITS                      4
#define BRPHY2_GPHY_CORE_EXP72_RESERVED0_SHIFT                     12

/* BRPHY2_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_3 [11:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP72,0xf00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP72,0xf00,8)
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_MASK               0x0f00
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_BITS               4
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_SHIFT              8

/* BRPHY2_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_2 [07:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP72,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP72,0xf0,4)
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_MASK               0x00f0
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_BITS               4
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_SHIFT              4

/* BRPHY2_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_1 [03:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP72,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP72,0xf,0)
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_MASK               0x000f
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_BITS               4
#define BRPHY2_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP73
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP73 :: reserved0 [15:08] */
#define BRPHY2_GPHY_CORE_EXP73_RESERVED0_MASK                      0xff00
#define BRPHY2_GPHY_CORE_EXP73_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP73_RESERVED0_BITS                      8
#define BRPHY2_GPHY_CORE_EXP73_RESERVED0_SHIFT                     8

/* BRPHY2_GPHY_CORE :: EXP73 :: LED_6_TO_1_COPPER [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP73,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP73,0x80,7)
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_MASK              0x0080
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_BITS              1
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_SHIFT             7

/* BRPHY2_GPHY_CORE :: EXP73 :: LED_5_TO_1_COPPER [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP73,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP73,0x40,6)
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_MASK              0x0040
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_BITS              1
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_SHIFT             6

/* BRPHY2_GPHY_CORE :: EXP73 :: LED_6_TO_0_COPPER [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP73,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP73,0x20,5)
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_MASK              0x0020
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_BITS              1
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_SHIFT             5

/* BRPHY2_GPHY_CORE :: EXP73 :: LED_5_TO_0_COPPER [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP73,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP73,0x10,4)
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_MASK              0x0010
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_ALIGN             0
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_BITS              1
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_SHIFT             4

/* BRPHY2_GPHY_CORE :: EXP73 :: LED_6_TO_1_FIBER [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP73,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP73,0x8,3)
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_MASK               0x0008
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_BITS               1
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_SHIFT              3

/* BRPHY2_GPHY_CORE :: EXP73 :: LED_5_TO_1_FIBER [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP73,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP73,0x4,2)
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_MASK               0x0004
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_BITS               1
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_SHIFT              2

/* BRPHY2_GPHY_CORE :: EXP73 :: LED_6_TO_0_FIBER [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP73,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP73,0x2,1)
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_MASK               0x0002
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_BITS               1
#define BRPHY2_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_SHIFT              1

/* BRPHY2_GPHY_CORE :: EXP73 :: LED_5_TO_0_FIBER [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP73,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP73,0x1,0)
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_MASK               0x0001
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_BITS               1
#define BRPHY2_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP74
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP74 :: LED4_CM_SW_VAL [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP74,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP74,0x8000,15)
#define BRPHY2_GPHY_CORE_EXP74_LED4_CM_SW_VAL_MASK                 0x8000
#define BRPHY2_GPHY_CORE_EXP74_LED4_CM_SW_VAL_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP74_LED4_CM_SW_VAL_BITS                 1
#define BRPHY2_GPHY_CORE_EXP74_LED4_CM_SW_VAL_SHIFT                15

/* BRPHY2_GPHY_CORE :: EXP74 :: LED4_CM_CTRL [14:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP74_LED4_CM_CTRL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP74,0x7000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP74_LED4_CM_CTRL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP74,0x7000,12)
#define BRPHY2_GPHY_CORE_EXP74_LED4_CM_CTRL_MASK                   0x7000
#define BRPHY2_GPHY_CORE_EXP74_LED4_CM_CTRL_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP74_LED4_CM_CTRL_BITS                   3
#define BRPHY2_GPHY_CORE_EXP74_LED4_CM_CTRL_SHIFT                  12

/* BRPHY2_GPHY_CORE :: EXP74 :: LED3_CM_SW_VAL [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP74,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP74,0x800,11)
#define BRPHY2_GPHY_CORE_EXP74_LED3_CM_SW_VAL_MASK                 0x0800
#define BRPHY2_GPHY_CORE_EXP74_LED3_CM_SW_VAL_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP74_LED3_CM_SW_VAL_BITS                 1
#define BRPHY2_GPHY_CORE_EXP74_LED3_CM_SW_VAL_SHIFT                11

/* BRPHY2_GPHY_CORE :: EXP74 :: LED3_CM_CTRL [10:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP74_LED3_CM_CTRL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP74,0x700,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP74_LED3_CM_CTRL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP74,0x700,8)
#define BRPHY2_GPHY_CORE_EXP74_LED3_CM_CTRL_MASK                   0x0700
#define BRPHY2_GPHY_CORE_EXP74_LED3_CM_CTRL_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP74_LED3_CM_CTRL_BITS                   3
#define BRPHY2_GPHY_CORE_EXP74_LED3_CM_CTRL_SHIFT                  8

/* BRPHY2_GPHY_CORE :: EXP74 :: LED2_CM_SW_VAL [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP74,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP74,0x80,7)
#define BRPHY2_GPHY_CORE_EXP74_LED2_CM_SW_VAL_MASK                 0x0080
#define BRPHY2_GPHY_CORE_EXP74_LED2_CM_SW_VAL_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP74_LED2_CM_SW_VAL_BITS                 1
#define BRPHY2_GPHY_CORE_EXP74_LED2_CM_SW_VAL_SHIFT                7

/* BRPHY2_GPHY_CORE :: EXP74 :: LED2_CM_CTRL [06:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP74_LED2_CM_CTRL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP74,0x70,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP74_LED2_CM_CTRL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP74,0x70,4)
#define BRPHY2_GPHY_CORE_EXP74_LED2_CM_CTRL_MASK                   0x0070
#define BRPHY2_GPHY_CORE_EXP74_LED2_CM_CTRL_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP74_LED2_CM_CTRL_BITS                   3
#define BRPHY2_GPHY_CORE_EXP74_LED2_CM_CTRL_SHIFT                  4

/* BRPHY2_GPHY_CORE :: EXP74 :: LED1_CM_SW_VAL [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP74,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP74,0x8,3)
#define BRPHY2_GPHY_CORE_EXP74_LED1_CM_SW_VAL_MASK                 0x0008
#define BRPHY2_GPHY_CORE_EXP74_LED1_CM_SW_VAL_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP74_LED1_CM_SW_VAL_BITS                 1
#define BRPHY2_GPHY_CORE_EXP74_LED1_CM_SW_VAL_SHIFT                3

/* BRPHY2_GPHY_CORE :: EXP74 :: LED1_CM_CTRL [02:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP74_LED1_CM_CTRL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP74,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP74_LED1_CM_CTRL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP74,0x7,0)
#define BRPHY2_GPHY_CORE_EXP74_LED1_CM_CTRL_MASK                   0x0007
#define BRPHY2_GPHY_CORE_EXP74_LED1_CM_CTRL_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXP74_LED1_CM_CTRL_BITS                   3
#define BRPHY2_GPHY_CORE_EXP74_LED1_CM_CTRL_SHIFT                  0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP75
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP75 :: reserved0 [15:10] */
#define BRPHY2_GPHY_CORE_EXP75_RESERVED0_MASK                      0xfc00
#define BRPHY2_GPHY_CORE_EXP75_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP75_RESERVED0_BITS                      6
#define BRPHY2_GPHY_CORE_EXP75_RESERVED0_SHIFT                     10

/* BRPHY2_GPHY_CORE :: EXP75 :: CED_LED_ERR_MASK [09:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP75,0x3ff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP75,0x3ff,0)
#define BRPHY2_GPHY_CORE_EXP75_CED_LED_ERR_MASK_MASK               0x03ff
#define BRPHY2_GPHY_CORE_EXP75_CED_LED_ERR_MASK_ALIGN              0
#define BRPHY2_GPHY_CORE_EXP75_CED_LED_ERR_MASK_BITS               10
#define BRPHY2_GPHY_CORE_EXP75_CED_LED_ERR_MASK_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP78
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP78 :: DAC_ANA_TEST_EN [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP78,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP78,0x8000,15)
#define BRPHY2_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_MASK                0x8000
#define BRPHY2_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_BITS                1
#define BRPHY2_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_SHIFT               15

/* BRPHY2_GPHY_CORE :: EXP78 :: BR_TXPR_EN [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXP78_BR_TXPR_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP78,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXP78_BR_TXPR_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP78,0x4000,14)
#define BRPHY2_GPHY_CORE_EXP78_BR_TXPR_EN_MASK                     0x4000
#define BRPHY2_GPHY_CORE_EXP78_BR_TXPR_EN_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP78_BR_TXPR_EN_BITS                     1
#define BRPHY2_GPHY_CORE_EXP78_BR_TXPR_EN_SHIFT                    14

/* BRPHY2_GPHY_CORE :: EXP78 :: BR_IRP_EN [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXP78_BR_IRP_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP78,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXP78_BR_IRP_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP78,0x2000,13)
#define BRPHY2_GPHY_CORE_EXP78_BR_IRP_EN_MASK                      0x2000
#define BRPHY2_GPHY_CORE_EXP78_BR_IRP_EN_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP78_BR_IRP_EN_BITS                      1
#define BRPHY2_GPHY_CORE_EXP78_BR_IRP_EN_SHIFT                     13

/* BRPHY2_GPHY_CORE :: EXP78 :: PTE_BYPASS_EN [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP78,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP78,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP78_PTE_BYPASS_EN_MASK                  0x1000
#define BRPHY2_GPHY_CORE_EXP78_PTE_BYPASS_EN_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP78_PTE_BYPASS_EN_BITS                  1
#define BRPHY2_GPHY_CORE_EXP78_PTE_BYPASS_EN_SHIFT                 12

/* BRPHY2_GPHY_CORE :: EXP78 :: PTE_DISTORT [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXP78_PTE_DISTORT(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP78,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXP78_PTE_DISTORT(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP78,0x800,11)
#define BRPHY2_GPHY_CORE_EXP78_PTE_DISTORT_MASK                    0x0800
#define BRPHY2_GPHY_CORE_EXP78_PTE_DISTORT_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP78_PTE_DISTORT_BITS                    1
#define BRPHY2_GPHY_CORE_EXP78_PTE_DISTORT_SHIFT                   11

/* BRPHY2_GPHY_CORE :: EXP78 :: LP_SEL [10:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP78_LP_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP78,0x700,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP78_LP_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP78,0x700,8)
#define BRPHY2_GPHY_CORE_EXP78_LP_SEL_MASK                         0x0700
#define BRPHY2_GPHY_CORE_EXP78_LP_SEL_ALIGN                        0
#define BRPHY2_GPHY_CORE_EXP78_LP_SEL_BITS                         3
#define BRPHY2_GPHY_CORE_EXP78_LP_SEL_SHIFT                        8

/* BRPHY2_GPHY_CORE :: EXP78 :: HP_PGA_BYPASS [07:04] */
#define Wr_BRPHY2_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP78,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP78,0xf0,4)
#define BRPHY2_GPHY_CORE_EXP78_HP_PGA_BYPASS_MASK                  0x00f0
#define BRPHY2_GPHY_CORE_EXP78_HP_PGA_BYPASS_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP78_HP_PGA_BYPASS_BITS                  4
#define BRPHY2_GPHY_CORE_EXP78_HP_PGA_BYPASS_SHIFT                 4

/* BRPHY2_GPHY_CORE :: EXP78 :: TDR_GAIN [03:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP78_TDR_GAIN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP78,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP78_TDR_GAIN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP78,0xf,0)
#define BRPHY2_GPHY_CORE_EXP78_TDR_GAIN_MASK                       0x000f
#define BRPHY2_GPHY_CORE_EXP78_TDR_GAIN_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP78_TDR_GAIN_BITS                       4
#define BRPHY2_GPHY_CORE_EXP78_TDR_GAIN_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP7B
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP7B :: I2C_CMD [15:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP7B_I2C_CMD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP7B,0xf000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP7B_I2C_CMD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP7B,0xf000,12)
#define BRPHY2_GPHY_CORE_EXP7B_I2C_CMD_MASK                        0xf000
#define BRPHY2_GPHY_CORE_EXP7B_I2C_CMD_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP7B_I2C_CMD_BITS                        4
#define BRPHY2_GPHY_CORE_EXP7B_I2C_CMD_SHIFT                       12

/* BRPHY2_GPHY_CORE :: EXP7B :: I2C_CTL [11:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP7B_I2C_CTL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP7B,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP7B_I2C_CTL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP7B,0xfff,0)
#define BRPHY2_GPHY_CORE_EXP7B_I2C_CTL_MASK                        0x0fff
#define BRPHY2_GPHY_CORE_EXP7B_I2C_CTL_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP7B_I2C_CTL_BITS                        12
#define BRPHY2_GPHY_CORE_EXP7B_I2C_CTL_SHIFT                       0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP7C
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP7C :: I2C_STATUS [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP7C_I2C_STATUS(x) WriteReg16(BRPHY2_GPHY_CORE_EXP7C,x)
#define Rd_BRPHY2_GPHY_CORE_EXP7C_I2C_STATUS(x) ReadReg16(BRPHY2_GPHY_CORE_EXP7C)
#define BRPHY2_GPHY_CORE_EXP7C_I2C_STATUS_MASK                     0xffff
#define BRPHY2_GPHY_CORE_EXP7C_I2C_STATUS_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP7C_I2C_STATUS_BITS                     16
#define BRPHY2_GPHY_CORE_EXP7C_I2C_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP7F
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP7F :: reserved0 [15:13] */
#define BRPHY2_GPHY_CORE_EXP7F_RESERVED0_MASK                      0xe000
#define BRPHY2_GPHY_CORE_EXP7F_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP7F_RESERVED0_BITS                      3
#define BRPHY2_GPHY_CORE_EXP7F_RESERVED0_SHIFT                     13

/* BRPHY2_GPHY_CORE :: EXP7F :: BR_PSD_PIN_DISABLE [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x1000,12)
#define BRPHY2_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_MASK             0x1000
#define BRPHY2_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_ALIGN            0
#define BRPHY2_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_BITS             1
#define BRPHY2_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_SHIFT            12

/* BRPHY2_GPHY_CORE :: EXP7F :: BR_PSD_OFF [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXP7F_BR_PSD_OFF(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXP7F_BR_PSD_OFF(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x800,11)
#define BRPHY2_GPHY_CORE_EXP7F_BR_PSD_OFF_MASK                     0x0800
#define BRPHY2_GPHY_CORE_EXP7F_BR_PSD_OFF_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP7F_BR_PSD_OFF_BITS                     1
#define BRPHY2_GPHY_CORE_EXP7F_BR_PSD_OFF_SHIFT                    11

/* BRPHY2_GPHY_CORE :: EXP7F :: ECD_DC_OFFSET [10:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x7fc,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x7fc,2)
#define BRPHY2_GPHY_CORE_EXP7F_ECD_DC_OFFSET_MASK                  0x07fc
#define BRPHY2_GPHY_CORE_EXP7F_ECD_DC_OFFSET_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXP7F_ECD_DC_OFFSET_BITS                  9
#define BRPHY2_GPHY_CORE_EXP7F_ECD_DC_OFFSET_SHIFT                 2

/* BRPHY2_GPHY_CORE :: EXP7F :: FIBER_UNIDIR_OV [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x2,1)
#define BRPHY2_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_MASK                0x0002
#define BRPHY2_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_BITS                1
#define BRPHY2_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_SHIFT               1

/* BRPHY2_GPHY_CORE :: EXP7F :: MACSEC_EN [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP7F_MACSEC_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP7F_MACSEC_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP7F,0x1,0)
#define BRPHY2_GPHY_CORE_EXP7F_MACSEC_EN_MASK                      0x0001
#define BRPHY2_GPHY_CORE_EXP7F_MACSEC_EN_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP7F_MACSEC_EN_BITS                      1
#define BRPHY2_GPHY_CORE_EXP7F_MACSEC_EN_SHIFT                     0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: ALIAS_18
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: ALIAS_18 :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_ALIAS_18_RESERVED0_MASK                   0xf000
#define BRPHY2_GPHY_CORE_ALIAS_18_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_ALIAS_18_RESERVED0_BITS                   4
#define BRPHY2_GPHY_CORE_ALIAS_18_RESERVED0_SHIFT                  12

/* BRPHY2_GPHY_CORE :: ALIAS_18 :: ALIAS [11:00] */
#define Wr_BRPHY2_GPHY_CORE_ALIAS_18_ALIAS(x) WriteRegBits16(BRPHY2_GPHY_CORE_ALIAS_18,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_ALIAS_18_ALIAS(x) ReadRegBits16(BRPHY2_GPHY_CORE_ALIAS_18,0xfff,0)
#define BRPHY2_GPHY_CORE_ALIAS_18_ALIAS_MASK                       0x0fff
#define BRPHY2_GPHY_CORE_ALIAS_18_ALIAS_ALIGN                      0
#define BRPHY2_GPHY_CORE_ALIAS_18_ALIAS_BITS                       12
#define BRPHY2_GPHY_CORE_ALIAS_18_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: ALIAS_19
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: ALIAS_19 :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_ALIAS_19_RESERVED0_MASK                   0xf000
#define BRPHY2_GPHY_CORE_ALIAS_19_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_ALIAS_19_RESERVED0_BITS                   4
#define BRPHY2_GPHY_CORE_ALIAS_19_RESERVED0_SHIFT                  12

/* BRPHY2_GPHY_CORE :: ALIAS_19 :: ALIAS [11:00] */
#define Wr_BRPHY2_GPHY_CORE_ALIAS_19_ALIAS(x) WriteRegBits16(BRPHY2_GPHY_CORE_ALIAS_19,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_ALIAS_19_ALIAS(x) ReadRegBits16(BRPHY2_GPHY_CORE_ALIAS_19,0xfff,0)
#define BRPHY2_GPHY_CORE_ALIAS_19_ALIAS_MASK                       0x0fff
#define BRPHY2_GPHY_CORE_ALIAS_19_ALIAS_ALIGN                      0
#define BRPHY2_GPHY_CORE_ALIAS_19_ALIAS_BITS                       12
#define BRPHY2_GPHY_CORE_ALIAS_19_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: ALIAS_1a
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: ALIAS_1a :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_ALIAS_1A_RESERVED0_MASK                   0xf000
#define BRPHY2_GPHY_CORE_ALIAS_1A_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_ALIAS_1A_RESERVED0_BITS                   4
#define BRPHY2_GPHY_CORE_ALIAS_1A_RESERVED0_SHIFT                  12

/* BRPHY2_GPHY_CORE :: ALIAS_1a :: ALIAS [11:00] */
#define Wr_BRPHY2_GPHY_CORE_ALIAS_1a_ALIAS(x) WriteRegBits16(BRPHY2_GPHY_CORE_ALIAS_1A,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_ALIAS_1a_ALIAS(x) ReadRegBits16(BRPHY2_GPHY_CORE_ALIAS_1A,0xfff,0)
#define BRPHY2_GPHY_CORE_ALIAS_1A_ALIAS_MASK                       0x0fff
#define BRPHY2_GPHY_CORE_ALIAS_1A_ALIAS_ALIGN                      0
#define BRPHY2_GPHY_CORE_ALIAS_1A_ALIAS_BITS                       12
#define BRPHY2_GPHY_CORE_ALIAS_1A_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: ALIAS_1b
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: ALIAS_1b :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_ALIAS_1B_RESERVED0_MASK                   0xf000
#define BRPHY2_GPHY_CORE_ALIAS_1B_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_ALIAS_1B_RESERVED0_BITS                   4
#define BRPHY2_GPHY_CORE_ALIAS_1B_RESERVED0_SHIFT                  12

/* BRPHY2_GPHY_CORE :: ALIAS_1b :: ALIAS [11:00] */
#define Wr_BRPHY2_GPHY_CORE_ALIAS_1b_ALIAS(x) WriteRegBits16(BRPHY2_GPHY_CORE_ALIAS_1B,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_ALIAS_1b_ALIAS(x) ReadRegBits16(BRPHY2_GPHY_CORE_ALIAS_1B,0xfff,0)
#define BRPHY2_GPHY_CORE_ALIAS_1B_ALIAS_MASK                       0x0fff
#define BRPHY2_GPHY_CORE_ALIAS_1B_ALIAS_ALIGN                      0
#define BRPHY2_GPHY_CORE_ALIAS_1B_ALIAS_BITS                       12
#define BRPHY2_GPHY_CORE_ALIAS_1B_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: ALIAS_1c
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: ALIAS_1c :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_ALIAS_1C_RESERVED0_MASK                   0xf000
#define BRPHY2_GPHY_CORE_ALIAS_1C_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_ALIAS_1C_RESERVED0_BITS                   4
#define BRPHY2_GPHY_CORE_ALIAS_1C_RESERVED0_SHIFT                  12

/* BRPHY2_GPHY_CORE :: ALIAS_1c :: ALIAS [11:00] */
#define Wr_BRPHY2_GPHY_CORE_ALIAS_1c_ALIAS(x) WriteRegBits16(BRPHY2_GPHY_CORE_ALIAS_1C,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_ALIAS_1c_ALIAS(x) ReadRegBits16(BRPHY2_GPHY_CORE_ALIAS_1C,0xfff,0)
#define BRPHY2_GPHY_CORE_ALIAS_1C_ALIAS_MASK                       0x0fff
#define BRPHY2_GPHY_CORE_ALIAS_1C_ALIAS_ALIGN                      0
#define BRPHY2_GPHY_CORE_ALIAS_1C_ALIAS_BITS                       12
#define BRPHY2_GPHY_CORE_ALIAS_1C_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: ALIAS_1d
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: ALIAS_1d :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_ALIAS_1D_RESERVED0_MASK                   0xf000
#define BRPHY2_GPHY_CORE_ALIAS_1D_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_ALIAS_1D_RESERVED0_BITS                   4
#define BRPHY2_GPHY_CORE_ALIAS_1D_RESERVED0_SHIFT                  12

/* BRPHY2_GPHY_CORE :: ALIAS_1d :: ALIAS [11:00] */
#define Wr_BRPHY2_GPHY_CORE_ALIAS_1d_ALIAS(x) WriteRegBits16(BRPHY2_GPHY_CORE_ALIAS_1D,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_ALIAS_1d_ALIAS(x) ReadRegBits16(BRPHY2_GPHY_CORE_ALIAS_1D,0xfff,0)
#define BRPHY2_GPHY_CORE_ALIAS_1D_ALIAS_MASK                       0x0fff
#define BRPHY2_GPHY_CORE_ALIAS_1D_ALIAS_ALIGN                      0
#define BRPHY2_GPHY_CORE_ALIAS_1D_ALIAS_BITS                       12
#define BRPHY2_GPHY_CORE_ALIAS_1D_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: REG_MAP_CTL
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: REG_MAP_CTL :: REG_LEGACY_EN [15:15] */
#define Wr_BRPHY2_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_REG_MAP_CTL,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_REG_MAP_CTL,0x8000,15)
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_MASK            0x8000
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_BITS            1
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_SHIFT           15

/* BRPHY2_GPHY_CORE :: REG_MAP_CTL :: ALIAS_MODE [14:13] */
#define Wr_BRPHY2_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_REG_MAP_CTL,0x6000,13,x)
#define Rd_BRPHY2_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_REG_MAP_CTL,0x6000,13)
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_MASK               0x6000
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_ALIGN              0
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_BITS               2
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_SHIFT              13

/* BRPHY2_GPHY_CORE :: REG_MAP_CTL :: reserved0 [12:12] */
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_RESERVED0_MASK                0x1000
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_RESERVED0_ALIGN               0
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_RESERVED0_BITS                1
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_RESERVED0_SHIFT               12

/* BRPHY2_GPHY_CORE :: REG_MAP_CTL :: RANGE_OFFSET [11:00] */
#define Wr_BRPHY2_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) WriteRegBits16(BRPHY2_GPHY_CORE_REG_MAP_CTL,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) ReadRegBits16(BRPHY2_GPHY_CORE_REG_MAP_CTL,0xfff,0)
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_MASK             0x0fff
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_ALIGN            0
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_BITS             12
#define BRPHY2_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_SHIFT            0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP98
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP98 :: reserved0 [15:11] */
#define BRPHY2_GPHY_CORE_EXP98_RESERVED0_MASK                      0xf800
#define BRPHY2_GPHY_CORE_EXP98_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXP98_RESERVED0_BITS                      5
#define BRPHY2_GPHY_CORE_EXP98_RESERVED0_SHIFT                     11

/* BRPHY2_GPHY_CORE :: EXP98 :: RC_CAL [10:06] */
#define Wr_BRPHY2_GPHY_CORE_EXP98_RC_CAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP98,0x7c0,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXP98_RC_CAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP98,0x7c0,6)
#define BRPHY2_GPHY_CORE_EXP98_RC_CAL_MASK                         0x07c0
#define BRPHY2_GPHY_CORE_EXP98_RC_CAL_ALIGN                        0
#define BRPHY2_GPHY_CORE_EXP98_RC_CAL_BITS                         5
#define BRPHY2_GPHY_CORE_EXP98_RC_CAL_SHIFT                        6

/* BRPHY2_GPHY_CORE :: EXP98 :: R_CAL [05:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP98_R_CAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP98,0x3e,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP98_R_CAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP98,0x3e,1)
#define BRPHY2_GPHY_CORE_EXP98_R_CAL_MASK                          0x003e
#define BRPHY2_GPHY_CORE_EXP98_R_CAL_ALIGN                         0
#define BRPHY2_GPHY_CORE_EXP98_R_CAL_BITS                          5
#define BRPHY2_GPHY_CORE_EXP98_R_CAL_SHIFT                         1

/* BRPHY2_GPHY_CORE :: EXP98 :: CAL_DONE [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP98_CAL_DONE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP98,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP98_CAL_DONE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP98,0x1,0)
#define BRPHY2_GPHY_CORE_EXP98_CAL_DONE_MASK                       0x0001
#define BRPHY2_GPHY_CORE_EXP98_CAL_DONE_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP98_CAL_DONE_BITS                       1
#define BRPHY2_GPHY_CORE_EXP98_CAL_DONE_SHIFT                      0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXP9C
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXP9C :: MII_REG1C_BNK1 [15:12] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0xf000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0xf000,12)
#define BRPHY2_GPHY_CORE_EXP9C_MII_REG1C_BNK1_MASK                 0xf000
#define BRPHY2_GPHY_CORE_EXP9C_MII_REG1C_BNK1_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP9C_MII_REG1C_BNK1_BITS                 4
#define BRPHY2_GPHY_CORE_EXP9C_MII_REG1C_BNK1_SHIFT                12

/* BRPHY2_GPHY_CORE :: EXP9C :: RSMII_LOAD_XMT [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x800,11)
#define BRPHY2_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_MASK                 0x0800
#define BRPHY2_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_BITS                 1
#define BRPHY2_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_SHIFT                11

/* BRPHY2_GPHY_CORE :: EXP9C :: FIFO_OV_UN [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_FIFO_OV_UN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_FIFO_OV_UN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x400,10)
#define BRPHY2_GPHY_CORE_EXP9C_FIFO_OV_UN_MASK                     0x0400
#define BRPHY2_GPHY_CORE_EXP9C_FIFO_OV_UN_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP9C_FIFO_OV_UN_BITS                     1
#define BRPHY2_GPHY_CORE_EXP9C_FIFO_OV_UN_SHIFT                    10

/* BRPHY2_GPHY_CORE :: EXP9C :: TEST_EN [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_TEST_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_TEST_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x200,9)
#define BRPHY2_GPHY_CORE_EXP9C_TEST_EN_MASK                        0x0200
#define BRPHY2_GPHY_CORE_EXP9C_TEST_EN_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXP9C_TEST_EN_BITS                        1
#define BRPHY2_GPHY_CORE_EXP9C_TEST_EN_SHIFT                       9

/* BRPHY2_GPHY_CORE :: EXP9C :: PTEST [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_PTEST(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_PTEST(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x100,8)
#define BRPHY2_GPHY_CORE_EXP9C_PTEST_MASK                          0x0100
#define BRPHY2_GPHY_CORE_EXP9C_PTEST_ALIGN                         0
#define BRPHY2_GPHY_CORE_EXP9C_PTEST_BITS                          1
#define BRPHY2_GPHY_CORE_EXP9C_PTEST_SHIFT                         8

/* BRPHY2_GPHY_CORE :: EXP9C :: EXRMIIFE [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_EXRMIIFE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_EXRMIIFE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x80,7)
#define BRPHY2_GPHY_CORE_EXP9C_EXRMIIFE_MASK                       0x0080
#define BRPHY2_GPHY_CORE_EXP9C_EXRMIIFE_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXP9C_EXRMIIFE_BITS                       1
#define BRPHY2_GPHY_CORE_EXP9C_EXRMIIFE_SHIFT                      7

/* BRPHY2_GPHY_CORE :: EXP9C :: FIFO_SIZE_CNTL [06:03] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x78,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x78,3)
#define BRPHY2_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_MASK                 0x0078
#define BRPHY2_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_ALIGN                0
#define BRPHY2_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_BITS                 4
#define BRPHY2_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_SHIFT                3

/* BRPHY2_GPHY_CORE :: EXP9C :: BIG_FIFO_EN [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x4,2)
#define BRPHY2_GPHY_CORE_EXP9C_BIG_FIFO_EN_MASK                    0x0004
#define BRPHY2_GPHY_CORE_EXP9C_BIG_FIFO_EN_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXP9C_BIG_FIFO_EN_BITS                    1
#define BRPHY2_GPHY_CORE_EXP9C_BIG_FIFO_EN_SHIFT                   2

/* BRPHY2_GPHY_CORE :: EXP9C :: SMII_S3MII_MODE [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x2,1)
#define BRPHY2_GPHY_CORE_EXP9C_SMII_S3MII_MODE_MASK                0x0002
#define BRPHY2_GPHY_CORE_EXP9C_SMII_S3MII_MODE_ALIGN               0
#define BRPHY2_GPHY_CORE_EXP9C_SMII_S3MII_MODE_BITS                1
#define BRPHY2_GPHY_CORE_EXP9C_SMII_S3MII_MODE_SHIFT               1

/* BRPHY2_GPHY_CORE :: EXP9C :: SSSMII_DIS [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXP9C_SSSMII_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXP9C_SSSMII_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXP9C,0x1,0)
#define BRPHY2_GPHY_CORE_EXP9C_SSSMII_DIS_MASK                     0x0001
#define BRPHY2_GPHY_CORE_EXP9C_SSSMII_DIS_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXP9C_SSSMII_DIS_BITS                     1
#define BRPHY2_GPHY_CORE_EXP9C_SSSMII_DIS_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: BT_LINK_FIX
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: BT_LINK_FIX :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RESERVED0_MASK                0x8000
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RESERVED0_ALIGN               0
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RESERVED0_BITS                1
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RESERVED0_SHIFT               15

/* BRPHY2_GPHY_CORE :: BT_LINK_FIX :: rxc_byp_rclk_dll_div2 [14:14] */
#define Wr_BRPHY2_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) WriteRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) ReadRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0x4000,14)
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_MASK    0x4000
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_ALIGN   0
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_BITS    1
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_SHIFT   14

/* BRPHY2_GPHY_CORE :: BT_LINK_FIX :: rxc_shamoo_tst_en [13:13] */
#define Wr_BRPHY2_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) WriteRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) ReadRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0x2000,13)
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_MASK        0x2000
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_ALIGN       0
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_BITS        1
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_SHIFT       13

/* BRPHY2_GPHY_CORE :: BT_LINK_FIX :: sig_10bt_upp_limit [12:08] */
#define Wr_BRPHY2_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) WriteRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0x1f00,8,x)
#define Rd_BRPHY2_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) ReadRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0x1f00,8)
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_MASK       0x1f00
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_ALIGN      0
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_BITS       5
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_SHIFT      8

/* BRPHY2_GPHY_CORE :: BT_LINK_FIX :: threshold_2mhz [07:01] */
#define Wr_BRPHY2_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) WriteRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0xfe,1,x)
#define Rd_BRPHY2_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) ReadRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0xfe,1)
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_MASK           0x00fe
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_ALIGN          0
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_BITS           7
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_SHIFT          1

/* BRPHY2_GPHY_CORE :: BT_LINK_FIX :: break_link10bt_disable [00:00] */
#define Wr_BRPHY2_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) WriteRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) ReadRegBits16(BRPHY2_GPHY_CORE_BT_LINK_FIX,0x1,0)
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_MASK   0x0001
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_ALIGN  0
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_BITS   1
#define BRPHY2_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_SHIFT  0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SYNCE_PLUS_DBG
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_DBG [15:02] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_MASK             0xfffc
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_ALIGN            0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_BITS             14
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_SHIFT            2

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_BRUTEFORCE_TM [01:01] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_MASK   0x0002
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_ALIGN  0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_BITS   1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_SHIFT  1

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_HSTIMEOUT_CTL [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_MASK   0x0001
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_ALIGN  0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_BITS   1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_SHIFT  0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: SYNCE_PLUS
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: TIMING_CONFIG [15:15] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x8000,15)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_MASK             0x8000
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_ALIGN            0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_BITS             1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_SHIFT            15

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_ONGOING [14:14] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x4000,14)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_MASK     0x4000
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_ALIGN    0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_BITS     1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_SHIFT    14

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: SYNCE_AUTO_ACK [13:13] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x2000,13)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_MASK            0x2000
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_ALIGN           0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_BITS            1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_SHIFT           13

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: SYNCE_WAIT_FOR_IDLE [12:12] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x1000,12)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_MASK       0x1000
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_ALIGN      0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_BITS       1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_SHIFT      12

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_COMPLETE [11:11] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x800,11)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_MASK    0x0800
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_ALIGN   0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_BITS    1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_SHIFT   11

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_PENDING [10:10] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x400,10)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_MASK     0x0400
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_ALIGN    0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_BITS     1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_SHIFT    10

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ERROR_STATUS [09:08] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x300,8,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x300,8)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_MASK        0x0300
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_ALIGN       0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_BITS        2
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_SHIFT       8

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_FAIL [07:07] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x80,7)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_MASK        0x0080
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_ALIGN       0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_BITS        1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_SHIFT       7

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: SYNCE_FTIMEOUT_CTL [06:06] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x40,6)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_MASK        0x0040
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_ALIGN       0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_BITS        1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_SHIFT       6

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: SYNCE_DBG_MUX_CTL [05:04] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x30,4,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x30,4)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_MASK         0x0030
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_ALIGN        0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_BITS         2
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_SHIFT        4

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: SYNCE_INTERRUPT_MASK [03:02] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0xc,2,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0xc,2)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_MASK      0x000c
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_ALIGN     0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_BITS      2
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_SHIFT     2

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: SYNCE_TIMING_SWITCH_START [01:01] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x2,1)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_MASK 0x0002
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_ALIGN 0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_BITS 1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_SHIFT 1

/* BRPHY2_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ENABLE [00:00] */
#define Wr_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_SYNCE_PLUS,0x1,0)
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_MASK              0x0001
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_ALIGN             0
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_BITS              1
#define BRPHY2_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_SHIFT             0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPA8
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPA8 :: ADAPTIVE_BIAS_CTRL [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) WriteReg16(BRPHY2_GPHY_CORE_EXPA8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) ReadReg16(BRPHY2_GPHY_CORE_EXPA8)
#define BRPHY2_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_MASK             0xffff
#define BRPHY2_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_BITS             16
#define BRPHY2_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_SHIFT            0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPA9
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPA9 :: SPARE_REG [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPA9_SPARE_REG(x) WriteReg16(BRPHY2_GPHY_CORE_EXPA9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPA9_SPARE_REG(x) ReadReg16(BRPHY2_GPHY_CORE_EXPA9)
#define BRPHY2_GPHY_CORE_EXPA9_SPARE_REG_MASK                      0xffff
#define BRPHY2_GPHY_CORE_EXPA9_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPA9_SPARE_REG_BITS                      16
#define BRPHY2_GPHY_CORE_EXPA9_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPAA
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPAA :: STATISTIC_TIMER_12HOURS_LPI [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) WriteReg16(BRPHY2_GPHY_CORE_EXPAA,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) ReadReg16(BRPHY2_GPHY_CORE_EXPAA)
#define BRPHY2_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_MASK    0xffff
#define BRPHY2_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_ALIGN   0
#define BRPHY2_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_BITS    16
#define BRPHY2_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_SHIFT   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPAB
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPAB :: STATISTIC_TIMER_12HOURS_LOCAL [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) WriteReg16(BRPHY2_GPHY_CORE_EXPAB,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) ReadReg16(BRPHY2_GPHY_CORE_EXPAB)
#define BRPHY2_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_MASK  0xffff
#define BRPHY2_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_ALIGN 0
#define BRPHY2_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_BITS  16
#define BRPHY2_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_SHIFT 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPAC
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPAC :: STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY2_GPHY_CORE_EXPAC,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY2_GPHY_CORE_EXPAC)
#define BRPHY2_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY2_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY2_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY2_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPAD
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPAD :: STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY2_GPHY_CORE_EXPAD,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY2_GPHY_CORE_EXPAD)
#define BRPHY2_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY2_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY2_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY2_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPAE
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPAE :: SPARE_REG [15:09] */
#define Wr_BRPHY2_GPHY_CORE_EXPAE_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAE,0xfe00,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAE_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAE,0xfe00,9)
#define BRPHY2_GPHY_CORE_EXPAE_SPARE_REG_MASK                      0xfe00
#define BRPHY2_GPHY_CORE_EXPAE_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPAE_SPARE_REG_BITS                      7
#define BRPHY2_GPHY_CORE_EXPAE_SPARE_REG_SHIFT                     9

/* BRPHY2_GPHY_CORE :: EXPAE :: TXBIAS_VAL2 [08:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAE,0x1e0,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAE,0x1e0,5)
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL2_MASK                    0x01e0
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL2_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL2_BITS                    4
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL2_SHIFT                   5

/* BRPHY2_GPHY_CORE :: EXPAE :: TXBIAS_VAL1 [04:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAE,0x1e,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAE,0x1e,1)
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL1_MASK                    0x001e
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL1_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL1_BITS                    4
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_VAL1_SHIFT                   1

/* BRPHY2_GPHY_CORE :: EXPAE :: TXBIAS_PLUS_MODE [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAE,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAE,0x1,0)
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_MASK               0x0001
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_BITS               1
#define BRPHY2_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPAF
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPAF :: STATISTIC_1000BT_MODE [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x8000,15)
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_MASK          0x8000
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_ALIGN         0
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_BITS          1
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_SHIFT         15

/* BRPHY2_GPHY_CORE :: EXPAF :: STATISTIC_UPPER_16BITS_SEL [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x4000,14)
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_MASK     0x4000
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_ALIGN    0
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_BITS     1
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_SHIFT    14

/* BRPHY2_GPHY_CORE :: EXPAF :: STATISTIC_SATURATE_MODE [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x2000,13)
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_MASK        0x2000
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_ALIGN       0
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_BITS        1
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_SHIFT       13

/* BRPHY2_GPHY_CORE :: EXPAF :: STATISTIC_ACCESS_MODE [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_MASK          0x1000
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_ALIGN         0
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_BITS          1
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_SHIFT         12

/* BRPHY2_GPHY_CORE :: EXPAF :: SPARE_REG [11:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0xfe0,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0xfe0,5)
#define BRPHY2_GPHY_CORE_EXPAF_SPARE_REG_MASK                      0x0fe0
#define BRPHY2_GPHY_CORE_EXPAF_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPAF_SPARE_REG_BITS                      7
#define BRPHY2_GPHY_CORE_EXPAF_SPARE_REG_SHIFT                     5

/* BRPHY2_GPHY_CORE :: EXPAF :: EEE_REM_RCVR_STATUS_DIS [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x10,4)
#define BRPHY2_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_MASK        0x0010
#define BRPHY2_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY2_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_BITS        1
#define BRPHY2_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_SHIFT       4

/* BRPHY2_GPHY_CORE :: EXPAF :: EEE_LOC_RCVR_STATUS_DIS [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x8,3)
#define BRPHY2_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_MASK        0x0008
#define BRPHY2_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY2_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_BITS        1
#define BRPHY2_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_SHIFT       3

/* BRPHY2_GPHY_CORE :: EXPAF :: STATISTIC_ADAPTX_EN [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x4,2)
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_MASK            0x0004
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_ALIGN           0
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_BITS            1
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_SHIFT           2

/* BRPHY2_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_RESET [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x2,1)
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_MASK       0x0002
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_ALIGN      0
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_BITS       1
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_SHIFT      1

/* BRPHY2_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_ENABLE [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPAF,0x1,0)
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_MASK      0x0001
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_ALIGN     0
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_BITS      1
#define BRPHY2_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_SHIFT     0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPB0
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPB0 :: BIAS_CTL_0 [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPB0_BIAS_CTL_0(x) WriteReg16(BRPHY2_GPHY_CORE_EXPB0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPB0_BIAS_CTL_0(x) ReadReg16(BRPHY2_GPHY_CORE_EXPB0)
#define BRPHY2_GPHY_CORE_EXPB0_BIAS_CTL_0_MASK                     0xffff
#define BRPHY2_GPHY_CORE_EXPB0_BIAS_CTL_0_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPB0_BIAS_CTL_0_BITS                     16
#define BRPHY2_GPHY_CORE_EXPB0_BIAS_CTL_0_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPB1
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPB1 :: BIAS_CTL_1 [15:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPB1_BIAS_CTL_1(x) WriteReg16(BRPHY2_GPHY_CORE_EXPB1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPB1_BIAS_CTL_1(x) ReadReg16(BRPHY2_GPHY_CORE_EXPB1)
#define BRPHY2_GPHY_CORE_EXPB1_BIAS_CTL_1_MASK                     0xffff
#define BRPHY2_GPHY_CORE_EXPB1_BIAS_CTL_1_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPB1_BIAS_CTL_1_BITS                     16
#define BRPHY2_GPHY_CORE_EXPB1_BIAS_CTL_1_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPB2
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPB2 :: CLK200_SEL_OV [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPB2,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPB2,0x8000,15)
#define BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_OV_MASK                  0x8000
#define BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_OV_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_OV_BITS                  1
#define BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_OV_SHIFT                 15

/* BRPHY2_GPHY_CORE :: EXPB2 :: CLK200_SEL [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPB2,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPB2,0x4000,14)
#define BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_MASK                     0x4000
#define BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_BITS                     1
#define BRPHY2_GPHY_CORE_EXPB2_CLK200_SEL_SHIFT                    14

/* BRPHY2_GPHY_CORE :: EXPB2 :: CK25_SEL [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPB2_CK25_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPB2,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPB2_CK25_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPB2,0x2000,13)
#define BRPHY2_GPHY_CORE_EXPB2_CK25_SEL_MASK                       0x2000
#define BRPHY2_GPHY_CORE_EXPB2_CK25_SEL_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXPB2_CK25_SEL_BITS                       1
#define BRPHY2_GPHY_CORE_EXPB2_CK25_SEL_SHIFT                      13

/* BRPHY2_GPHY_CORE :: EXPB2 :: REG_B2_SPARE [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPB2_REG_B2_SPARE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPB2,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPB2_REG_B2_SPARE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPB2,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPB2_REG_B2_SPARE_MASK                   0x1000
#define BRPHY2_GPHY_CORE_EXPB2_REG_B2_SPARE_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPB2_REG_B2_SPARE_BITS                   1
#define BRPHY2_GPHY_CORE_EXPB2_REG_B2_SPARE_SHIFT                  12

/* BRPHY2_GPHY_CORE :: EXPB2 :: I_RC_OFFSET_PHY [11:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPB2,0xf00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPB2,0xf00,8)
#define BRPHY2_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_MASK                0x0f00
#define BRPHY2_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_BITS                4
#define BRPHY2_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_SHIFT               8

/* BRPHY2_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_1000_100 [07:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPB2,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPB2,0xf0,4)
#define BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_MASK        0x00f0
#define BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_ALIGN       0
#define BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_BITS        4
#define BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_SHIFT       4

/* BRPHY2_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_10 [03:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPB2,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPB2,0xf,0)
#define BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_MASK              0x000f
#define BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_BITS              4
#define BRPHY2_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_SHIFT             0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE3
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE3,0xff00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE3,0xff00,8)
#define BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_100_MASK                 0xff00
#define BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_100_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_100_BITS                 8
#define BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_100_SHIFT                8

/* BRPHY2_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE3,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE3,0xff,0)
#define BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_BITS                8
#define BRPHY2_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE4
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE4 :: TX_PCS_SOP_TSYNC_ERR [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE4,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE4,0x8000,15)
#define BRPHY2_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_MASK           0x8000
#define BRPHY2_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_BITS           1
#define BRPHY2_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_SHIFT          15

/* BRPHY2_GPHY_CORE :: EXPE4 :: reserved0 [14:12] */
#define BRPHY2_GPHY_CORE_EXPE4_RESERVED0_MASK                      0x7000
#define BRPHY2_GPHY_CORE_EXPE4_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPE4_RESERVED0_BITS                      3
#define BRPHY2_GPHY_CORE_EXPE4_RESERVED0_SHIFT                     12

/* BRPHY2_GPHY_CORE :: EXPE4 :: TX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE4,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE4,0xfff,0)
#define BRPHY2_GPHY_CORE_EXPE4_TX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY2_GPHY_CORE_EXPE4_TX_PCS_DLY_10_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXPE4_TX_PCS_DLY_10_BITS                  12
#define BRPHY2_GPHY_CORE_EXPE4_TX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE5
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE5,0xff00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE5,0xff00,8)
#define BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_BITS               8
#define BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_SHIFT              8

/* BRPHY2_GPHY_CORE :: EXPE5 :: reserved0 [07:07] */
#define BRPHY2_GPHY_CORE_EXPE5_RESERVED0_MASK                      0x0080
#define BRPHY2_GPHY_CORE_EXPE5_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPE5_RESERVED0_BITS                      1
#define BRPHY2_GPHY_CORE_EXPE5_RESERVED0_SHIFT                     7

/* BRPHY2_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE5,0x7f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE5,0x7f,0)
#define BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_BITS               7
#define BRPHY2_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE6
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE6,0xff00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE6,0xff00,8)
#define BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_100_MASK                 0xff00
#define BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_100_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_100_BITS                 8
#define BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_100_SHIFT                8

/* BRPHY2_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE6,0xff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE6,0xff,0)
#define BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_BITS                8
#define BRPHY2_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE7
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE7 :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_EXPE7_RESERVED0_MASK                      0xf000
#define BRPHY2_GPHY_CORE_EXPE7_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPE7_RESERVED0_BITS                      4
#define BRPHY2_GPHY_CORE_EXPE7_RESERVED0_SHIFT                     12

/* BRPHY2_GPHY_CORE :: EXPE7 :: RX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE7,0xfff,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE7,0xfff,0)
#define BRPHY2_GPHY_CORE_EXPE7_RX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY2_GPHY_CORE_EXPE7_RX_PCS_DLY_10_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXPE7_RX_PCS_DLY_10_BITS                  12
#define BRPHY2_GPHY_CORE_EXPE7_RX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE8
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE8,0xff00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE8,0xff00,8)
#define BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_BITS               8
#define BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_SHIFT              8

/* BRPHY2_GPHY_CORE :: EXPE8 :: reserved0 [07:07] */
#define BRPHY2_GPHY_CORE_EXPE8_RESERVED0_MASK                      0x0080
#define BRPHY2_GPHY_CORE_EXPE8_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPE8_RESERVED0_BITS                      1
#define BRPHY2_GPHY_CORE_EXPE8_RESERVED0_SHIFT                     7

/* BRPHY2_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE8,0x7f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE8,0x7f,0)
#define BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_BITS               7
#define BRPHY2_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE9
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE9 :: reserved0 [15:14] */
#define BRPHY2_GPHY_CORE_EXPE9_RESERVED0_MASK                      0xc000
#define BRPHY2_GPHY_CORE_EXPE9_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPE9_RESERVED0_BITS                      2
#define BRPHY2_GPHY_CORE_EXPE9_RESERVED0_SHIFT                     14

/* BRPHY2_GPHY_CORE :: EXPE9 :: P1588_TX_DLY_CYCLE [13:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE9,0x3f00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE9,0x3f00,8)
#define BRPHY2_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_MASK             0x3f00
#define BRPHY2_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_BITS             6
#define BRPHY2_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_SHIFT            8

/* BRPHY2_GPHY_CORE :: EXPE9 :: reserved1 [07:06] */
#define BRPHY2_GPHY_CORE_EXPE9_RESERVED1_MASK                      0x00c0
#define BRPHY2_GPHY_CORE_EXPE9_RESERVED1_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPE9_RESERVED1_BITS                      2
#define BRPHY2_GPHY_CORE_EXPE9_RESERVED1_SHIFT                     6

/* BRPHY2_GPHY_CORE :: EXPE9 :: P1588_RX_DLY_CYCLE [05:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE9,0x3f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE9,0x3f,0)
#define BRPHY2_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_MASK             0x003f
#define BRPHY2_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_BITS             6
#define BRPHY2_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_SHIFT            0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE0
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_10 [15:10] */
#define Wr_BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE0,0xfc00,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE0,0xfc00,10)
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_MASK              0xfc00
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_BITS              6
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_SHIFT             10

/* BRPHY2_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_100 [09:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE0,0x3e0,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE0,0x3e0,5)
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_MASK             0x03e0
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_BITS             5
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_SHIFT            5

/* BRPHY2_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_1000 [04:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE0,0x1f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE0,0x1f,0)
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_MASK            0x001f
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_ALIGN           0
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_BITS            5
#define BRPHY2_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_SHIFT           0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE1
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE1 :: reserved0 [15:12] */
#define BRPHY2_GPHY_CORE_EXPE1_RESERVED0_MASK                      0xf000
#define BRPHY2_GPHY_CORE_EXPE1_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPE1_RESERVED0_BITS                      4
#define BRPHY2_GPHY_CORE_EXPE1_RESERVED0_SHIFT                     12

/* BRPHY2_GPHY_CORE :: EXPE1 :: RX_PMA_PMD_DLY_FIBER [11:06] */
#define Wr_BRPHY2_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE1,0xfc0,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE1,0xfc0,6)
#define BRPHY2_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_MASK           0x0fc0
#define BRPHY2_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY2_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_SHIFT          6

/* BRPHY2_GPHY_CORE :: EXPE1 :: TX_PMA_PMD_DLY_FIBER [05:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE1,0x3f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE1,0x3f,0)
#define BRPHY2_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_MASK           0x003f
#define BRPHY2_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY2_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_SHIFT          0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPE2
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPE2 :: reserved0 [15:14] */
#define BRPHY2_GPHY_CORE_EXPE2_RESERVED0_MASK                      0xc000
#define BRPHY2_GPHY_CORE_EXPE2_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPE2_RESERVED0_BITS                      2
#define BRPHY2_GPHY_CORE_EXPE2_RESERVED0_SHIFT                     14

/* BRPHY2_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_10 [13:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE2,0x3f80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE2,0x3f80,7)
#define BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_MASK              0x3f80
#define BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_BITS              7
#define BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_SHIFT             7

/* BRPHY2_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_100_1000 [06:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPE2,0x7f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPE2,0x7f,0)
#define BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_MASK        0x007f
#define BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_ALIGN       0
#define BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_BITS        7
#define BRPHY2_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_SHIFT       0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPEA
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPEA :: reserved0 [15:13] */
#define BRPHY2_GPHY_CORE_EXPEA_RESERVED0_MASK                      0xe000
#define BRPHY2_GPHY_CORE_EXPEA_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPEA_RESERVED0_BITS                      3
#define BRPHY2_GPHY_CORE_EXPEA_RESERVED0_SHIFT                     13

/* BRPHY2_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MAX_DLY_CYCLE [12:10] */
#define Wr_BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPEA,0x1c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPEA,0x1c00,10)
#define BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x1c00
#define BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      10

/* BRPHY2_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MIN_DLY_CYCLE [09:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPEA,0x380,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPEA,0x380,7)
#define BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x0380
#define BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY2_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      7

/* BRPHY2_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MAX_DLY_CYCLE [06:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPEA,0x70,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPEA,0x70,4)
#define BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x0070
#define BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      4

/* BRPHY2_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MIN_DLY_CYCLE [03:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPEA,0xe,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPEA,0xe,1)
#define BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x000e
#define BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY2_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      1

/* BRPHY2_GPHY_CORE :: EXPEA :: FEATURE_802_3BF_ENABLE [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPEA,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPEA,0x1,0)
#define BRPHY2_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_MASK         0x0001
#define BRPHY2_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_ALIGN        0
#define BRPHY2_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_BITS         1
#define BRPHY2_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_SHIFT        0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: LED_PRA_MODE
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: LED_PRA_MODE :: reserved0 [15:04] */
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_RESERVED0_MASK               0xfff0
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_RESERVED0_ALIGN              0
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_RESERVED0_BITS               12
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_RESERVED0_SHIFT              4

/* BRPHY2_GPHY_CORE :: LED_PRA_MODE :: SAT_MODE [03:03] */
#define Wr_BRPHY2_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_LED_PRA_MODE,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_LED_PRA_MODE,0x8,3)
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_SAT_MODE_MASK                0x0008
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_SAT_MODE_ALIGN               0
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_SAT_MODE_BITS                1
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_SAT_MODE_SHIFT               3

/* BRPHY2_GPHY_CORE :: LED_PRA_MODE :: PRA_MODE [02:00] */
#define Wr_BRPHY2_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_LED_PRA_MODE,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_LED_PRA_MODE,0x7,0)
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_PRA_MODE_MASK                0x0007
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_PRA_MODE_ALIGN               0
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_PRA_MODE_BITS                3
#define BRPHY2_GPHY_CORE_LED_PRA_MODE_PRA_MODE_SHIFT               0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: FIFO_CTL
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: FIFO_CTL :: SFT_RST [15:15] */
#define Wr_BRPHY2_GPHY_CORE_FIFO_CTL_SFT_RST(x) WriteRegBits16(BRPHY2_GPHY_CORE_FIFO_CTL,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_FIFO_CTL_SFT_RST(x) ReadRegBits16(BRPHY2_GPHY_CORE_FIFO_CTL,0x8000,15)
#define BRPHY2_GPHY_CORE_FIFO_CTL_SFT_RST_MASK                     0x8000
#define BRPHY2_GPHY_CORE_FIFO_CTL_SFT_RST_ALIGN                    0
#define BRPHY2_GPHY_CORE_FIFO_CTL_SFT_RST_BITS                     1
#define BRPHY2_GPHY_CORE_FIFO_CTL_SFT_RST_SHIFT                    15

/* BRPHY2_GPHY_CORE :: FIFO_CTL :: reserved0 [14:09] */
#define BRPHY2_GPHY_CORE_FIFO_CTL_RESERVED0_MASK                   0x7e00
#define BRPHY2_GPHY_CORE_FIFO_CTL_RESERVED0_ALIGN                  0
#define BRPHY2_GPHY_CORE_FIFO_CTL_RESERVED0_BITS                   6
#define BRPHY2_GPHY_CORE_FIFO_CTL_RESERVED0_SHIFT                  9

/* BRPHY2_GPHY_CORE :: FIFO_CTL :: WRBLOCK_MODE [08:08] */
#define Wr_BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) WriteRegBits16(BRPHY2_GPHY_CORE_FIFO_CTL,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) ReadRegBits16(BRPHY2_GPHY_CORE_FIFO_CTL,0x100,8)
#define BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_MASK                0x0100
#define BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_ALIGN               0
#define BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_BITS                1
#define BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_SHIFT               8

/* BRPHY2_GPHY_CORE :: FIFO_CTL :: WRBLOCK_OVR [07:04] */
#define Wr_BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) WriteRegBits16(BRPHY2_GPHY_CORE_FIFO_CTL,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) ReadRegBits16(BRPHY2_GPHY_CORE_FIFO_CTL,0xf0,4)
#define BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_MASK                 0x00f0
#define BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_ALIGN                0
#define BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_BITS                 4
#define BRPHY2_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_SHIFT                4

/* BRPHY2_GPHY_CORE :: FIFO_CTL :: MIN_IPG [03:00] */
#define Wr_BRPHY2_GPHY_CORE_FIFO_CTL_MIN_IPG(x) WriteRegBits16(BRPHY2_GPHY_CORE_FIFO_CTL,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_FIFO_CTL_MIN_IPG(x) ReadRegBits16(BRPHY2_GPHY_CORE_FIFO_CTL,0xf,0)
#define BRPHY2_GPHY_CORE_FIFO_CTL_MIN_IPG_MASK                     0x000f
#define BRPHY2_GPHY_CORE_FIFO_CTL_MIN_IPG_ALIGN                    0
#define BRPHY2_GPHY_CORE_FIFO_CTL_MIN_IPG_BITS                     4
#define BRPHY2_GPHY_CORE_FIFO_CTL_MIN_IPG_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPD8
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPD8 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_EXPD8_RESERVED0_MASK                      0x8000
#define BRPHY2_GPHY_CORE_EXPD8_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPD8_RESERVED0_BITS                      1
#define BRPHY2_GPHY_CORE_EXPD8_RESERVED0_SHIFT                     15

/* BRPHY2_GPHY_CORE :: EXPD8 :: FORCE_ACD_ON [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x4000,14)
#define BRPHY2_GPHY_CORE_EXPD8_FORCE_ACD_ON_MASK                   0x4000
#define BRPHY2_GPHY_CORE_EXPD8_FORCE_ACD_ON_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPD8_FORCE_ACD_ON_BITS                   1
#define BRPHY2_GPHY_CORE_EXPD8_FORCE_ACD_ON_SHIFT                  14

/* BRPHY2_GPHY_CORE :: EXPD8 :: ACD_PHASE_SEL [13:11] */
#define Wr_BRPHY2_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x3800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x3800,11)
#define BRPHY2_GPHY_CORE_EXPD8_ACD_PHASE_SEL_MASK                  0x3800
#define BRPHY2_GPHY_CORE_EXPD8_ACD_PHASE_SEL_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXPD8_ACD_PHASE_SEL_BITS                  3
#define BRPHY2_GPHY_CORE_EXPD8_ACD_PHASE_SEL_SHIFT                 11

/* BRPHY2_GPHY_CORE :: EXPD8 :: AGC_FSCALE [10:09] */
#define Wr_BRPHY2_GPHY_CORE_EXPD8_AGC_FSCALE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x600,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPD8_AGC_FSCALE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x600,9)
#define BRPHY2_GPHY_CORE_EXPD8_AGC_FSCALE_MASK                     0x0600
#define BRPHY2_GPHY_CORE_EXPD8_AGC_FSCALE_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPD8_AGC_FSCALE_BITS                     2
#define BRPHY2_GPHY_CORE_EXPD8_AGC_FSCALE_SHIFT                    9

/* BRPHY2_GPHY_CORE :: EXPD8 :: STOP_AGC_AFTER_LINK [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x100,8)
#define BRPHY2_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_MASK            0x0100
#define BRPHY2_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_ALIGN           0
#define BRPHY2_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_BITS            1
#define BRPHY2_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_SHIFT           8

/* BRPHY2_GPHY_CORE :: EXPD8 :: UPDATE_FROM_FFE_EN [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x80,7)
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_MASK             0x0080
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_BITS             1
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_SHIFT            7

/* BRPHY2_GPHY_CORE :: EXPD8 :: UPDATE_AGC_WHEN_IDLE [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x40,6)
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_MASK           0x0040
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_BITS           1
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_SHIFT          6

/* BRPHY2_GPHY_CORE :: EXPD8 :: UPDATE_ENC_WHEN_IDLE [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x20,5)
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_MASK           0x0020
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_BITS           1
#define BRPHY2_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_SHIFT          5

/* BRPHY2_GPHY_CORE :: EXPD8 :: FFE_DYN_THD [04:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPD8_FFE_DYN_THD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x1f,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPD8_FFE_DYN_THD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPD8,0x1f,0)
#define BRPHY2_GPHY_CORE_EXPD8_FFE_DYN_THD_MASK                    0x001f
#define BRPHY2_GPHY_CORE_EXPD8_FFE_DYN_THD_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPD8_FFE_DYN_THD_BITS                    5
#define BRPHY2_GPHY_CORE_EXPD8_FFE_DYN_THD_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPF0
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPF0 :: IBS_RX_SEND [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXPF0_IBS_RX_SEND(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF0_IBS_RX_SEND(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x8000,15)
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RX_SEND_MASK                    0x8000
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RX_SEND_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RX_SEND_BITS                    1
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RX_SEND_SHIFT                   15

/* BRPHY2_GPHY_CORE :: EXPF0 :: IBS_TX_EN [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPF0_IBS_TX_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF0_IBS_TX_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x4000,14)
#define BRPHY2_GPHY_CORE_EXPF0_IBS_TX_EN_MASK                      0x4000
#define BRPHY2_GPHY_CORE_EXPF0_IBS_TX_EN_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPF0_IBS_TX_EN_BITS                      1
#define BRPHY2_GPHY_CORE_EXPF0_IBS_TX_EN_SHIFT                     14

/* BRPHY2_GPHY_CORE :: EXPF0 :: IBS_RXCLK_OV_EN [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x2000,13)
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_MASK                0x2000
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_BITS                1
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_SHIFT               13

/* BRPHY2_GPHY_CORE :: EXPF0 :: IBS_RXCLK_SW_OV [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_MASK                0x1000
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_BITS                1
#define BRPHY2_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_SHIFT               12

/* BRPHY2_GPHY_CORE :: EXPF0 :: reserved0 [11:05] */
#define BRPHY2_GPHY_CORE_EXPF0_RESERVED0_MASK                      0x0fe0
#define BRPHY2_GPHY_CORE_EXPF0_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPF0_RESERVED0_BITS                      7
#define BRPHY2_GPHY_CORE_EXPF0_RESERVED0_SHIFT                     5

/* BRPHY2_GPHY_CORE :: EXPF0 :: IBS_PWRDN [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x10,4)
#define BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_MASK                      0x0010
#define BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_BITS                      1
#define BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_SHIFT                     4

/* BRPHY2_GPHY_CORE :: EXPF0 :: IBS_PWRDN_SD [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x8,3)
#define BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_SD_MASK                   0x0008
#define BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_SD_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_SD_BITS                   1
#define BRPHY2_GPHY_CORE_EXPF0_IBS_PWRDN_SD_SHIFT                  3

/* BRPHY2_GPHY_CORE :: EXPF0 :: IBS_AUTO_PWRDN [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x4,2)
#define BRPHY2_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_MASK                 0x0004
#define BRPHY2_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_BITS                 1
#define BRPHY2_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_SHIFT                2

/* BRPHY2_GPHY_CORE :: EXPF0 :: IBS_EARLY_DAC_WAKE [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x2,1)
#define BRPHY2_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_MASK             0x0002
#define BRPHY2_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_BITS             1
#define BRPHY2_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_SHIFT            1

/* BRPHY2_GPHY_CORE :: EXPF0 :: IBS_CK25_DIS [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF0,0x1,0)
#define BRPHY2_GPHY_CORE_EXPF0_IBS_CK25_DIS_MASK                   0x0001
#define BRPHY2_GPHY_CORE_EXPF0_IBS_CK25_DIS_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPF0_IBS_CK25_DIS_BITS                   1
#define BRPHY2_GPHY_CORE_EXPF0_IBS_CK25_DIS_SHIFT                  0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPF5
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_COPPER [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x8000,15)
#define BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_MASK           0x8000
#define BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_BITS           1
#define BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_SHIFT          15

/* BRPHY2_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_FIBER [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x4000,14)
#define BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_MASK            0x4000
#define BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_ALIGN           0
#define BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_BITS            1
#define BRPHY2_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_SHIFT           14

/* BRPHY2_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_COPPER [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x2000,13)
#define BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_MASK           0x2000
#define BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_BITS           1
#define BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_SHIFT          13

/* BRPHY2_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_FIBER [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_MASK            0x1000
#define BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_ALIGN           0
#define BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_BITS            1
#define BRPHY2_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_SHIFT           12

/* BRPHY2_GPHY_CORE :: EXPF5 :: RX_SOP_SEL [11:10] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0xc00,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0xc00,10)
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_MASK                     0x0c00
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_BITS                     2
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_SHIFT                    10

/* BRPHY2_GPHY_CORE :: EXPF5 :: RX_SOP_SEL_OV [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x200,9)
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_MASK                  0x0200
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_BITS                  1
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_SHIFT                 9

/* BRPHY2_GPHY_CORE :: EXPF5 :: TX_SOP_10BT_ENABLE [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x100,8)
#define BRPHY2_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_MASK             0x0100
#define BRPHY2_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_BITS             1
#define BRPHY2_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_SHIFT            8

/* BRPHY2_GPHY_CORE :: EXPF5 :: RX_SOP_10BT_ENABLE [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x80,7)
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_MASK             0x0080
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_BITS             1
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_SHIFT            7

/* BRPHY2_GPHY_CORE :: EXPF5 :: TX_SOP_ERR_STATUS [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x40,6)
#define BRPHY2_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_MASK              0x0040
#define BRPHY2_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_BITS              1
#define BRPHY2_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_SHIFT             6

/* BRPHY2_GPHY_CORE :: EXPF5 :: USE_TXEN_TX_SOP [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x20,5)
#define BRPHY2_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_MASK                0x0020
#define BRPHY2_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_BITS                1
#define BRPHY2_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_SHIFT               5

/* BRPHY2_GPHY_CORE :: EXPF5 :: RX_SOP_ERR_STATUS [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x10,4)
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_MASK              0x0010
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_BITS              1
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_SHIFT             4

/* BRPHY2_GPHY_CORE :: EXPF5 :: RX_SOP_OPTION [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x8,3)
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_OPTION_MASK                  0x0008
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_OPTION_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_OPTION_BITS                  1
#define BRPHY2_GPHY_CORE_EXPF5_RX_SOP_OPTION_SHIFT                 3

/* BRPHY2_GPHY_CORE :: EXPF5 :: USE_RXDV_RX_SOP [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x4,2)
#define BRPHY2_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_MASK                0x0004
#define BRPHY2_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_BITS                1
#define BRPHY2_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_SHIFT               2

/* BRPHY2_GPHY_CORE :: EXPF5 :: RECOVERY_CLK_SEL [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x2,1)
#define BRPHY2_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_MASK               0x0002
#define BRPHY2_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_BITS               1
#define BRPHY2_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_SHIFT              1

/* BRPHY2_GPHY_CORE :: EXPF5 :: TIMESYNC_EN [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPF5_TIMESYNC_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF5_TIMESYNC_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF5,0x1,0)
#define BRPHY2_GPHY_CORE_EXPF5_TIMESYNC_EN_MASK                    0x0001
#define BRPHY2_GPHY_CORE_EXPF5_TIMESYNC_EN_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPF5_TIMESYNC_EN_BITS                    1
#define BRPHY2_GPHY_CORE_EXPF5_TIMESYNC_EN_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPF6
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPF6 :: reserved0 [15:15] */
#define BRPHY2_GPHY_CORE_EXPF6_RESERVED0_MASK                      0x8000
#define BRPHY2_GPHY_CORE_EXPF6_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPF6_RESERVED0_BITS                      1
#define BRPHY2_GPHY_CORE_EXPF6_RESERVED0_SHIFT                     15

/* BRPHY2_GPHY_CORE :: EXPF6 :: PWRDN_DLL [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPF6_PWRDN_DLL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF6,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF6_PWRDN_DLL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF6,0x4000,14)
#define BRPHY2_GPHY_CORE_EXPF6_PWRDN_DLL_MASK                      0x4000
#define BRPHY2_GPHY_CORE_EXPF6_PWRDN_DLL_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPF6_PWRDN_DLL_BITS                      1
#define BRPHY2_GPHY_CORE_EXPF6_PWRDN_DLL_SHIFT                     14

/* BRPHY2_GPHY_CORE :: EXPF6 :: PWRDNBT_DLL [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF6,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF6,0x2000,13)
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNBT_DLL_MASK                    0x2000
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNBT_DLL_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNBT_DLL_BITS                    1
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNBT_DLL_SHIFT                   13

/* BRPHY2_GPHY_CORE :: EXPF6 :: COMMON_PWROFF [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPF6_COMMON_PWROFF(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF6,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF6_COMMON_PWROFF(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF6,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPF6_COMMON_PWROFF_MASK                  0x1000
#define BRPHY2_GPHY_CORE_EXPF6_COMMON_PWROFF_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXPF6_COMMON_PWROFF_BITS                  1
#define BRPHY2_GPHY_CORE_EXPF6_COMMON_PWROFF_SHIFT                 12

/* BRPHY2_GPHY_CORE :: EXPF6 :: PWRDN_SD [11:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPF6_PWRDN_SD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF6,0xf00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF6_PWRDN_SD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF6,0xf00,8)
#define BRPHY2_GPHY_CORE_EXPF6_PWRDN_SD_MASK                       0x0f00
#define BRPHY2_GPHY_CORE_EXPF6_PWRDN_SD_ALIGN                      0
#define BRPHY2_GPHY_CORE_EXPF6_PWRDN_SD_BITS                       4
#define BRPHY2_GPHY_CORE_EXPF6_PWRDN_SD_SHIFT                      8

/* BRPHY2_GPHY_CORE :: EXPF6 :: PWRDNRX [07:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPF6_PWRDNRX(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF6,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF6_PWRDNRX(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF6,0xf0,4)
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNRX_MASK                        0x00f0
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNRX_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNRX_BITS                        4
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNRX_SHIFT                       4

/* BRPHY2_GPHY_CORE :: EXPF6 :: PWRDNTX [03:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPF6_PWRDNTX(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF6,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF6_PWRDNTX(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF6,0xf,0)
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNTX_MASK                        0x000f
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNTX_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNTX_BITS                        4
#define BRPHY2_GPHY_CORE_EXPF6_PWRDNTX_SHIFT                       0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPF7
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPF7 :: reserved0 [15:14] */
#define BRPHY2_GPHY_CORE_EXPF7_RESERVED0_MASK                      0xc000
#define BRPHY2_GPHY_CORE_EXPF7_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPF7_RESERVED0_BITS                      2
#define BRPHY2_GPHY_CORE_EXPF7_RESERVED0_SHIFT                     14

/* BRPHY2_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_DPWR [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x2000,13)
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_MASK              0x2000
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_BITS              1
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_SHIFT             13

/* BRPHY2_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_APWR [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_MASK              0x1000
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_BITS              1
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_SHIFT             12

/* BRPHY2_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_DPWR [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x800,11)
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_MASK              0x0800
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_BITS              1
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_SHIFT             11

/* BRPHY2_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_APWR [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x400,10)
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_MASK              0x0400
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_BITS              1
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_SHIFT             10

/* BRPHY2_GPHY_CORE :: EXPF7 :: R0PWRDN_DPWR [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x200,9)
#define BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_DPWR_MASK                   0x0200
#define BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_DPWR_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_DPWR_BITS                   1
#define BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_DPWR_SHIFT                  9

/* BRPHY2_GPHY_CORE :: EXPF7 :: R0PWRDN_APWR [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x100,8)
#define BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_APWR_MASK                   0x0100
#define BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_APWR_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_APWR_BITS                   1
#define BRPHY2_GPHY_CORE_EXPF7_R0PWRDN_APWR_SHIFT                  8

/* BRPHY2_GPHY_CORE :: EXPF7 :: AUTO_PWRDN_DLL [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x80,7)
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_MASK                 0x0080
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_BITS                 1
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_SHIFT                7

/* BRPHY2_GPHY_CORE :: EXPF7 :: PWRDN_DPWR_EARLY_INT [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x40,6)
#define BRPHY2_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_MASK           0x0040
#define BRPHY2_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_BITS           1
#define BRPHY2_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_SHIFT          6

/* BRPHY2_GPHY_CORE :: EXPF7 :: REAL_ENERGY [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_REAL_ENERGY(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_REAL_ENERGY(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x20,5)
#define BRPHY2_GPHY_CORE_EXPF7_REAL_ENERGY_MASK                    0x0020
#define BRPHY2_GPHY_CORE_EXPF7_REAL_ENERGY_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPF7_REAL_ENERGY_BITS                    1
#define BRPHY2_GPHY_CORE_EXPF7_REAL_ENERGY_SHIFT                   5

/* BRPHY2_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_RAW [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x10,4)
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_MASK               0x0010
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_BITS               1
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_SHIFT              4

/* BRPHY2_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_RAW [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x8,3)
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_MASK               0x0008
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_BITS               1
#define BRPHY2_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_SHIFT              3

/* BRPHY2_GPHY_CORE :: EXPF7 :: CUR_STATE [02:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPF7_CUR_STATE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x7,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF7_CUR_STATE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF7,0x7,0)
#define BRPHY2_GPHY_CORE_EXPF7_CUR_STATE_MASK                      0x0007
#define BRPHY2_GPHY_CORE_EXPF7_CUR_STATE_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPF7_CUR_STATE_BITS                      3
#define BRPHY2_GPHY_CORE_EXPF7_CUR_STATE_SHIFT                     0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPF8
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPF8 :: TRIM_DAC_FROM_FUSE [15:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF8,0xf000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF8,0xf000,12)
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_MASK             0xf000
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_BITS             4
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_SHIFT            12

/* BRPHY2_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_FROM_FUSE [11:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF8,0xf00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF8,0xf00,8)
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_MASK          0x0f00
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_ALIGN         0
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_BITS          4
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_SHIFT         8

/* BRPHY2_GPHY_CORE :: EXPF8 :: TRIM_DAC_TO_BIAS_BLOCK [07:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF8,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF8,0xf0,4)
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_MASK         0x00f0
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_ALIGN        0
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_BITS         4
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_SHIFT        4

/* BRPHY2_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_TO_BIAS_BLOCK [03:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF8,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF8,0xf,0)
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_MASK      0x000f
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_ALIGN     0
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_BITS      4
#define BRPHY2_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_SHIFT     0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPF9
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPF9 :: EXT_CTL [15:11] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_EXT_CTL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0xf800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_EXT_CTL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0xf800,11)
#define BRPHY2_GPHY_CORE_EXPF9_EXT_CTL_MASK                        0xf800
#define BRPHY2_GPHY_CORE_EXPF9_EXT_CTL_ALIGN                       0
#define BRPHY2_GPHY_CORE_EXPF9_EXT_CTL_BITS                        5
#define BRPHY2_GPHY_CORE_EXPF9_EXT_CTL_SHIFT                       11

/* BRPHY2_GPHY_CORE :: EXPF9 :: BT_NIBBLE_VAL [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x400,10)
#define BRPHY2_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_MASK                  0x0400
#define BRPHY2_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_BITS                  1
#define BRPHY2_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_SHIFT                 10

/* BRPHY2_GPHY_CORE :: EXPF9 :: BT_DRIB_RMV [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x200,9)
#define BRPHY2_GPHY_CORE_EXPF9_BT_DRIB_RMV_MASK                    0x0200
#define BRPHY2_GPHY_CORE_EXPF9_BT_DRIB_RMV_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPF9_BT_DRIB_RMV_BITS                    1
#define BRPHY2_GPHY_CORE_EXPF9_BT_DRIB_RMV_SHIFT                   9

/* BRPHY2_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_MDIX_EN [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x100,8)
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_MASK          0x0100
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_ALIGN         0
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_BITS          1
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_SHIFT         8

/* BRPHY2_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SEED_EN [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x80,7)
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_MASK          0x0080
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_ALIGN         0
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_BITS          1
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_SHIFT         7

/* BRPHY2_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_EN [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x40,6)
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_MASK               0x0040
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_BITS               1
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_SHIFT              6

/* BRPHY2_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SIG [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x20,5)
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_MASK              0x0020
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_BITS              1
#define BRPHY2_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_SHIFT             5

/* BRPHY2_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_VAL [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x10,4)
#define BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_MASK          0x0010
#define BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_ALIGN         0
#define BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_BITS          1
#define BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_SHIFT         4

/* BRPHY2_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_EN [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x8,3)
#define BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_MASK           0x0008
#define BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_BITS           1
#define BRPHY2_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_SHIFT          3

/* BRPHY2_GPHY_CORE :: EXPF9 :: ABIST_INF_CONV [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x4,2)
#define BRPHY2_GPHY_CORE_EXPF9_ABIST_INF_CONV_MASK                 0x0004
#define BRPHY2_GPHY_CORE_EXPF9_ABIST_INF_CONV_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPF9_ABIST_INF_CONV_BITS                 1
#define BRPHY2_GPHY_CORE_EXPF9_ABIST_INF_CONV_SHIFT                2

/* BRPHY2_GPHY_CORE :: EXPF9 :: GIGA_ONLY_HALFOUT [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x2,1)
#define BRPHY2_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_MASK              0x0002
#define BRPHY2_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_BITS              1
#define BRPHY2_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_SHIFT             1

/* BRPHY2_GPHY_CORE :: EXPF9 :: SPARE_REG0 [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPF9_SPARE_REG0(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPF9_SPARE_REG0(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPF9,0x1,0)
#define BRPHY2_GPHY_CORE_EXPF9_SPARE_REG0_MASK                     0x0001
#define BRPHY2_GPHY_CORE_EXPF9_SPARE_REG0_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPF9_SPARE_REG0_BITS                     1
#define BRPHY2_GPHY_CORE_EXPF9_SPARE_REG0_SHIFT                    0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPFA
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPFA :: reserved0 [15:04] */
#define BRPHY2_GPHY_CORE_EXPFA_RESERVED0_MASK                      0xfff0
#define BRPHY2_GPHY_CORE_EXPFA_RESERVED0_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPFA_RESERVED0_BITS                      12
#define BRPHY2_GPHY_CORE_EXPFA_RESERVED0_SHIFT                     4

/* BRPHY2_GPHY_CORE :: EXPFA :: HIDDEN_REV_NUM [03:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFA,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFA,0xf,0)
#define BRPHY2_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_MASK                 0x000f
#define BRPHY2_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_BITS                 4
#define BRPHY2_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_SHIFT                0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPFB
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPFB :: TEST_IDDQCLKBIAS [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x8000,15)
#define BRPHY2_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_MASK               0x8000
#define BRPHY2_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_BITS               1
#define BRPHY2_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_SHIFT              15

/* BRPHY2_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x4000,14)
#define BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_MASK                 0x4000
#define BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_BITS                 1
#define BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_SHIFT                14

/* BRPHY2_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV_VAL [13:10] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x3c00,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x3c00,10)
#define BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_MASK             0x3c00
#define BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_BITS             4
#define BRPHY2_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_SHIFT            10

/* BRPHY2_GPHY_CORE :: EXPFB :: TDR_SLAVE_DFE_CONV_VAL [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x200,9)
#define BRPHY2_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_MASK         0x0200
#define BRPHY2_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_ALIGN        0
#define BRPHY2_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_BITS         1
#define BRPHY2_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_SHIFT        9

/* BRPHY2_GPHY_CORE :: EXPFB :: FEXT_INPUTS_OV [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x100,8)
#define BRPHY2_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_MASK                 0x0100
#define BRPHY2_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_BITS                 1
#define BRPHY2_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_SHIFT                8

/* BRPHY2_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_OV [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x80,7)
#define BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_MASK               0x0080
#define BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_BITS               1
#define BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_SHIFT              7

/* BRPHY2_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_VAL [06:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x60,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x60,5)
#define BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_MASK              0x0060
#define BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_BITS              2
#define BRPHY2_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_SHIFT             5

/* BRPHY2_GPHY_CORE :: EXPFB :: LINK_DET_OV [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_LINK_DET_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_LINK_DET_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x10,4)
#define BRPHY2_GPHY_CORE_EXPFB_LINK_DET_OV_MASK                    0x0010
#define BRPHY2_GPHY_CORE_EXPFB_LINK_DET_OV_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPFB_LINK_DET_OV_BITS                    1
#define BRPHY2_GPHY_CORE_EXPFB_LINK_DET_OV_SHIFT                   4

/* BRPHY2_GPHY_CORE :: EXPFB :: LINK_DET_VAL [03:02] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_LINK_DET_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0xc,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_LINK_DET_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0xc,2)
#define BRPHY2_GPHY_CORE_EXPFB_LINK_DET_VAL_MASK                   0x000c
#define BRPHY2_GPHY_CORE_EXPFB_LINK_DET_VAL_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPFB_LINK_DET_VAL_BITS                   2
#define BRPHY2_GPHY_CORE_EXPFB_LINK_DET_VAL_SHIFT                  2

/* BRPHY2_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_OV [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x2,1)
#define BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_MASK               0x0002
#define BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_BITS               1
#define BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_SHIFT              1

/* BRPHY2_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_VAL [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFB,0x1,0)
#define BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_MASK              0x0001
#define BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_BITS              1
#define BRPHY2_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_SHIFT             0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPFC
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPFC :: PASSIVE_TERM_OV [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x8000,15)
#define BRPHY2_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_MASK                0x8000
#define BRPHY2_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_BITS                1
#define BRPHY2_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_SHIFT               15

/* BRPHY2_GPHY_CORE :: EXPFC :: APD_CLKOFF_OV [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x4000,14)
#define BRPHY2_GPHY_CORE_EXPFC_APD_CLKOFF_OV_MASK                  0x4000
#define BRPHY2_GPHY_CORE_EXPFC_APD_CLKOFF_OV_ALIGN                 0
#define BRPHY2_GPHY_CORE_EXPFC_APD_CLKOFF_OV_BITS                  1
#define BRPHY2_GPHY_CORE_EXPFC_APD_CLKOFF_OV_SHIFT                 14

/* BRPHY2_GPHY_CORE :: EXPFC :: TDR_TSD_PTE_OV_VAL_CHD [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x2000,13)
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_MASK         0x2000
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_ALIGN        0
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_BITS         1
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_SHIFT        13

/* BRPHY2_GPHY_CORE :: EXPFC :: TDR_TSC_PTE_OV_VAL_CHC [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_MASK         0x1000
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_ALIGN        0
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_BITS         1
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_SHIFT        12

/* BRPHY2_GPHY_CORE :: EXPFC :: TDR_TSB_PTE_OV_VAL_CHB [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x800,11)
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_MASK         0x0800
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_ALIGN        0
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_BITS         1
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_SHIFT        11

/* BRPHY2_GPHY_CORE :: EXPFC :: TDR_TSA_PTE_OV_VAL_CHA [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x400,10)
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_MASK         0x0400
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_ALIGN        0
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_BITS         1
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_SHIFT        10

/* BRPHY2_GPHY_CORE :: EXPFC :: TDR_TS_EN_OV [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x200,9)
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TS_EN_OV_MASK                   0x0200
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TS_EN_OV_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TS_EN_OV_BITS                   1
#define BRPHY2_GPHY_CORE_EXPFC_TDR_TS_EN_OV_SHIFT                  9

/* BRPHY2_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x100,8)
#define BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_MASK                   0x0100
#define BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_BITS                   1
#define BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_SHIFT                  8

/* BRPHY2_GPHY_CORE :: EXPFC :: BASET_DLL_CLK_OV_VAL [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x80,7)
#define BRPHY2_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_MASK           0x0080
#define BRPHY2_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_ALIGN          0
#define BRPHY2_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_BITS           1
#define BRPHY2_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_SHIFT          7

/* BRPHY2_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV_VAL [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x40,6)
#define BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_MASK               0x0040
#define BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_BITS               1
#define BRPHY2_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_SHIFT              6

/* BRPHY2_GPHY_CORE :: EXPFC :: AUTONEG_1000T_CLK_GATING_DIS [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x20,5)
#define BRPHY2_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_MASK   0x0020
#define BRPHY2_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_ALIGN  0
#define BRPHY2_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_BITS   1
#define BRPHY2_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_SHIFT  5

/* BRPHY2_GPHY_CORE :: EXPFC :: AUTONEG_10BT_LP_DIS [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x10,4)
#define BRPHY2_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_MASK            0x0010
#define BRPHY2_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_ALIGN           0
#define BRPHY2_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_BITS            1
#define BRPHY2_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_SHIFT           4

/* BRPHY2_GPHY_CORE :: EXPFC :: AUTO_PWRDN_CLK_OFF_OV_VAL [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x8,3)
#define BRPHY2_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_MASK      0x0008
#define BRPHY2_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_ALIGN     0
#define BRPHY2_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_BITS      1
#define BRPHY2_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_SHIFT     3

/* BRPHY2_GPHY_CORE :: EXPFC :: LP1000_DIS [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_LP1000_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_LP1000_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x4,2)
#define BRPHY2_GPHY_CORE_EXPFC_LP1000_DIS_MASK                     0x0004
#define BRPHY2_GPHY_CORE_EXPFC_LP1000_DIS_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPFC_LP1000_DIS_BITS                     1
#define BRPHY2_GPHY_CORE_EXPFC_LP1000_DIS_SHIFT                    2

/* BRPHY2_GPHY_CORE :: EXPFC :: LP100_DIS [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_LP100_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_LP100_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x2,1)
#define BRPHY2_GPHY_CORE_EXPFC_LP100_DIS_MASK                      0x0002
#define BRPHY2_GPHY_CORE_EXPFC_LP100_DIS_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPFC_LP100_DIS_BITS                      1
#define BRPHY2_GPHY_CORE_EXPFC_LP100_DIS_SHIFT                     1

/* BRPHY2_GPHY_CORE :: EXPFC :: LP10_DIABLE [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPFC_LP10_DIABLE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFC_LP10_DIABLE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFC,0x1,0)
#define BRPHY2_GPHY_CORE_EXPFC_LP10_DIABLE_MASK                    0x0001
#define BRPHY2_GPHY_CORE_EXPFC_LP10_DIABLE_ALIGN                   0
#define BRPHY2_GPHY_CORE_EXPFC_LP10_DIABLE_BITS                    1
#define BRPHY2_GPHY_CORE_EXPFC_LP10_DIABLE_SHIFT                   0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPFD
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPFD :: SPARE_REG [15:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0xe000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0xe000,13)
#define BRPHY2_GPHY_CORE_EXPFD_SPARE_REG_MASK                      0xe000
#define BRPHY2_GPHY_CORE_EXPFD_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPFD_SPARE_REG_BITS                      3
#define BRPHY2_GPHY_CORE_EXPFD_SPARE_REG_SHIFT                     13

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x800,11)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x400,10)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x200,9)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_BITS               1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x100,8)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_BITS               1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x80,7)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x40,6)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x20,5)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x10,4)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x8,3)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x4,2)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x2,1)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_BITS                1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY2_GPHY_CORE :: EXPFD :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFD,0x1,0)
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_BITS               1
#define BRPHY2_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPFE
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPFE :: SPARE_REG [15:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_SPARE_REG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0xc000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_SPARE_REG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0xc000,14)
#define BRPHY2_GPHY_CORE_EXPFE_SPARE_REG_MASK                      0xc000
#define BRPHY2_GPHY_CORE_EXPFE_SPARE_REG_ALIGN                     0
#define BRPHY2_GPHY_CORE_EXPFE_SPARE_REG_BITS                      2
#define BRPHY2_GPHY_CORE_EXPFE_SPARE_REG_SHIFT                     14

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_DFE_LPI_EN [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x2000,13)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_MASK              0x2000
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_BITS              1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_SHIFT             13

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x800,11,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x800,11)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x400,10,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x400,10)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x200,9,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x200,9)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_BITS               1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x100,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x100,8)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_BITS               1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x80,7,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x80,7)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x40,6,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x40,6)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x20,5,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x20,5)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x10,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x10,4)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x8,3,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x8,3)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x4,2,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x4,2)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x2,1,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x2,1)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_BITS                1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY2_GPHY_CORE :: EXPFE :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x1,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFE,0x1,0)
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_BITS               1
#define BRPHY2_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY2_GPHY_CORE :: EXPFF
 ***************************************************************************/
/* BRPHY2_GPHY_CORE :: EXPFF :: PWRDN_SD_DIS [15:15] */
#define Wr_BRPHY2_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFF,0x8000,15,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFF,0x8000,15)
#define BRPHY2_GPHY_CORE_EXPFF_PWRDN_SD_DIS_MASK                   0x8000
#define BRPHY2_GPHY_CORE_EXPFF_PWRDN_SD_DIS_ALIGN                  0
#define BRPHY2_GPHY_CORE_EXPFF_PWRDN_SD_DIS_BITS                   1
#define BRPHY2_GPHY_CORE_EXPFF_PWRDN_SD_DIS_SHIFT                  15

/* BRPHY2_GPHY_CORE :: EXPFF :: PWRDNSD_OV [14:14] */
#define Wr_BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFF,0x4000,14,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFF,0x4000,14)
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_MASK                     0x4000
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_BITS                     1
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_SHIFT                    14

/* BRPHY2_GPHY_CORE :: EXPFF :: PWRDNTX_OV [13:13] */
#define Wr_BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFF,0x2000,13,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFF,0x2000,13)
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_MASK                     0x2000
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_BITS                     1
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_SHIFT                    13

/* BRPHY2_GPHY_CORE :: EXPFF :: PWRDNRX_OV [12:12] */
#define Wr_BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFF,0x1000,12,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFF,0x1000,12)
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_MASK                     0x1000
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_ALIGN                    0
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_BITS                     1
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_SHIFT                    12

/* BRPHY2_GPHY_CORE :: EXPFF :: PWRDNSD_OV_VAL [11:08] */
#define Wr_BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFF,0xf00,8,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFF,0xf00,8)
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_MASK                 0x0f00
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_BITS                 4
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_SHIFT                8

/* BRPHY2_GPHY_CORE :: EXPFF :: PWRDNTX_OV_VAL [07:04] */
#define Wr_BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFF,0xf0,4,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFF,0xf0,4)
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_MASK                 0x00f0
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_BITS                 4
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_SHIFT                4

/* BRPHY2_GPHY_CORE :: EXPFF :: PWRDNRX_OV_VAL [03:00] */
#define Wr_BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) WriteRegBits16(BRPHY2_GPHY_CORE_EXPFF,0xf,0,x)
#define Rd_BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) ReadRegBits16(BRPHY2_GPHY_CORE_EXPFF,0xf,0)
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_MASK                 0x000f
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_ALIGN                0
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_BITS                 4
#define BRPHY2_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_DSP_TAP
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP0_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP0_C0 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x8000,15)
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY2_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x4000,14)
#define BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY2_DSP_TAP :: TAP0_C0 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x2000,13)
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY2_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x1000,12)
#define BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY2_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY2_DSP_TAP :: TAP0_C0 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x800,11)
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_BITS                1
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY2_DSP_TAP :: TAP0_C0 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x700,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x700,8)
#define BRPHY2_DSP_TAP_TAP0_C0_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY2_DSP_TAP_TAP0_C0_BR_PGA_GAIN_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP0_C0_BR_PGA_GAIN_BITS                    3
#define BRPHY2_DSP_TAP_TAP0_C0_BR_PGA_GAIN_SHIFT                   8

/* BRPHY2_DSP_TAP :: TAP0_C0 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x80,7)
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_OV_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_OV_BITS                    1
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_OV_SHIFT                   7

/* BRPHY2_DSP_TAP :: TAP0_C0 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x7f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C0,0x7f,0)
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_BITS                 7
#define BRPHY2_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP0_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP0_C1 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x8000,15)
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY2_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x4000,14)
#define BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY2_DSP_TAP :: TAP0_C1 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x2000,13)
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY2_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x1000,12)
#define BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY2_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY2_DSP_TAP :: TAP0_C1 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x800,11)
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_BITS                1
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY2_DSP_TAP :: TAP0_C1 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x700,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x700,8)
#define BRPHY2_DSP_TAP_TAP0_C1_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY2_DSP_TAP_TAP0_C1_BR_PGA_GAIN_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP0_C1_BR_PGA_GAIN_BITS                    3
#define BRPHY2_DSP_TAP_TAP0_C1_BR_PGA_GAIN_SHIFT                   8

/* BRPHY2_DSP_TAP :: TAP0_C1 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x80,7)
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_OV_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_OV_BITS                    1
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_OV_SHIFT                   7

/* BRPHY2_DSP_TAP :: TAP0_C1 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x7f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C1,0x7f,0)
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_BITS                 7
#define BRPHY2_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP0_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP0_C2 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x8000,15)
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY2_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x4000,14)
#define BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY2_DSP_TAP :: TAP0_C2 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x2000,13)
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY2_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x1000,12)
#define BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY2_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY2_DSP_TAP :: TAP0_C2 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x800,11)
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_BITS                1
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY2_DSP_TAP :: TAP0_C2 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x700,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x700,8)
#define BRPHY2_DSP_TAP_TAP0_C2_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY2_DSP_TAP_TAP0_C2_BR_PGA_GAIN_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP0_C2_BR_PGA_GAIN_BITS                    3
#define BRPHY2_DSP_TAP_TAP0_C2_BR_PGA_GAIN_SHIFT                   8

/* BRPHY2_DSP_TAP :: TAP0_C2 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x80,7)
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_OV_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_OV_BITS                    1
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_OV_SHIFT                   7

/* BRPHY2_DSP_TAP :: TAP0_C2 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x7f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C2,0x7f,0)
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_BITS                 7
#define BRPHY2_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP0_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP0_C3 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x8000,15)
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY2_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x4000,14)
#define BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY2_DSP_TAP :: TAP0_C3 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x2000,13)
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY2_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x1000,12)
#define BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY2_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY2_DSP_TAP :: TAP0_C3 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x800,11)
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_BITS                1
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY2_DSP_TAP :: TAP0_C3 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x700,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x700,8)
#define BRPHY2_DSP_TAP_TAP0_C3_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY2_DSP_TAP_TAP0_C3_BR_PGA_GAIN_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP0_C3_BR_PGA_GAIN_BITS                    3
#define BRPHY2_DSP_TAP_TAP0_C3_BR_PGA_GAIN_SHIFT                   8

/* BRPHY2_DSP_TAP :: TAP0_C3 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x80,7)
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_OV_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_OV_BITS                    1
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_OV_SHIFT                   7

/* BRPHY2_DSP_TAP :: TAP0_C3 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x7f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP0_C3,0x7f,0)
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_BITS                 7
#define BRPHY2_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP1 :: reserved0 [15:14] */
#define BRPHY2_DSP_TAP_TAP1_RESERVED0_MASK                         0xc000
#define BRPHY2_DSP_TAP_TAP1_RESERVED0_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP1_RESERVED0_BITS                         2
#define BRPHY2_DSP_TAP_TAP1_RESERVED0_SHIFT                        14

/* BRPHY2_DSP_TAP :: TAP1 :: DIG_GAIN_LMS_MODE [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP1,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP1,0x2000,13)
#define BRPHY2_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_MASK                 0x2000
#define BRPHY2_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_BITS                 1
#define BRPHY2_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_SHIFT                13

/* BRPHY2_DSP_TAP :: TAP1 :: IPRF_K_OV_EN [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP1,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP1,0x1000,12)
#define BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_EN_MASK                      0x1000
#define BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_EN_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_EN_BITS                      1
#define BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_EN_SHIFT                     12

/* BRPHY2_DSP_TAP :: TAP1 :: IPRF_K_OV_VALUE [11:07] */
#define Wr_BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP1,0xf80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP1,0xf80,7)
#define BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_VALUE_MASK                   0x0f80
#define BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_VALUE_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_VALUE_BITS                   5
#define BRPHY2_DSP_TAP_TAP1_IPRF_K_OV_VALUE_SHIFT                  7

/* BRPHY2_DSP_TAP :: TAP1 :: GBT_AGC_TARGET_LVL [06:04] */
#define Wr_BRPHY2_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP1,0x70,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP1,0x70,4)
#define BRPHY2_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_MASK                0x0070
#define BRPHY2_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_ALIGN               0
#define BRPHY2_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_BITS                3
#define BRPHY2_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_SHIFT               4

/* BRPHY2_DSP_TAP :: TAP1 :: TX_AGC_TARGET_LVL [03:00] */
#define Wr_BRPHY2_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP1,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP1,0xf,0)
#define BRPHY2_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_MASK                 0x000f
#define BRPHY2_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_ALIGN                0
#define BRPHY2_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_BITS                 4
#define BRPHY2_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP2_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP2_C0 :: MSE [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP2_C0_MSE(x) WriteReg16(BRPHY2_DSP_TAP_TAP2_C0,x)
#define Rd_BRPHY2_DSP_TAP_TAP2_C0_MSE(x) ReadReg16(BRPHY2_DSP_TAP_TAP2_C0)
#define BRPHY2_DSP_TAP_TAP2_C0_MSE_MASK                            0xffff
#define BRPHY2_DSP_TAP_TAP2_C0_MSE_ALIGN                           0
#define BRPHY2_DSP_TAP_TAP2_C0_MSE_BITS                            16
#define BRPHY2_DSP_TAP_TAP2_C0_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP2_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP2_C1 :: MSE [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP2_C1_MSE(x) WriteReg16(BRPHY2_DSP_TAP_TAP2_C1,x)
#define Rd_BRPHY2_DSP_TAP_TAP2_C1_MSE(x) ReadReg16(BRPHY2_DSP_TAP_TAP2_C1)
#define BRPHY2_DSP_TAP_TAP2_C1_MSE_MASK                            0xffff
#define BRPHY2_DSP_TAP_TAP2_C1_MSE_ALIGN                           0
#define BRPHY2_DSP_TAP_TAP2_C1_MSE_BITS                            16
#define BRPHY2_DSP_TAP_TAP2_C1_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP2_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP2_C2 :: MSE [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP2_C2_MSE(x) WriteReg16(BRPHY2_DSP_TAP_TAP2_C2,x)
#define Rd_BRPHY2_DSP_TAP_TAP2_C2_MSE(x) ReadReg16(BRPHY2_DSP_TAP_TAP2_C2)
#define BRPHY2_DSP_TAP_TAP2_C2_MSE_MASK                            0xffff
#define BRPHY2_DSP_TAP_TAP2_C2_MSE_ALIGN                           0
#define BRPHY2_DSP_TAP_TAP2_C2_MSE_BITS                            16
#define BRPHY2_DSP_TAP_TAP2_C2_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP2_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP2_C3 :: MSE [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP2_C3_MSE(x) WriteReg16(BRPHY2_DSP_TAP_TAP2_C3,x)
#define Rd_BRPHY2_DSP_TAP_TAP2_C3_MSE(x) ReadReg16(BRPHY2_DSP_TAP_TAP2_C3)
#define BRPHY2_DSP_TAP_TAP2_C3_MSE_MASK                            0xffff
#define BRPHY2_DSP_TAP_TAP2_C3_MSE_ALIGN                           0
#define BRPHY2_DSP_TAP_TAP2_C3_MSE_BITS                            16
#define BRPHY2_DSP_TAP_TAP2_C3_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP3_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP3_C0 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP3_C0_SOFT_DECISION(x) WriteReg16(BRPHY2_DSP_TAP_TAP3_C0,x)
#define Rd_BRPHY2_DSP_TAP_TAP3_C0_SOFT_DECISION(x) ReadReg16(BRPHY2_DSP_TAP_TAP3_C0)
#define BRPHY2_DSP_TAP_TAP3_C0_SOFT_DECISION_MASK                  0xffff
#define BRPHY2_DSP_TAP_TAP3_C0_SOFT_DECISION_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP3_C0_SOFT_DECISION_BITS                  16
#define BRPHY2_DSP_TAP_TAP3_C0_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP3_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP3_C1 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP3_C1_SOFT_DECISION(x) WriteReg16(BRPHY2_DSP_TAP_TAP3_C1,x)
#define Rd_BRPHY2_DSP_TAP_TAP3_C1_SOFT_DECISION(x) ReadReg16(BRPHY2_DSP_TAP_TAP3_C1)
#define BRPHY2_DSP_TAP_TAP3_C1_SOFT_DECISION_MASK                  0xffff
#define BRPHY2_DSP_TAP_TAP3_C1_SOFT_DECISION_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP3_C1_SOFT_DECISION_BITS                  16
#define BRPHY2_DSP_TAP_TAP3_C1_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP3_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP3_C2 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP3_C2_SOFT_DECISION(x) WriteReg16(BRPHY2_DSP_TAP_TAP3_C2,x)
#define Rd_BRPHY2_DSP_TAP_TAP3_C2_SOFT_DECISION(x) ReadReg16(BRPHY2_DSP_TAP_TAP3_C2)
#define BRPHY2_DSP_TAP_TAP3_C2_SOFT_DECISION_MASK                  0xffff
#define BRPHY2_DSP_TAP_TAP3_C2_SOFT_DECISION_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP3_C2_SOFT_DECISION_BITS                  16
#define BRPHY2_DSP_TAP_TAP3_C2_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP3_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP3_C3 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP3_C3_SOFT_DECISION(x) WriteReg16(BRPHY2_DSP_TAP_TAP3_C3,x)
#define Rd_BRPHY2_DSP_TAP_TAP3_C3_SOFT_DECISION(x) ReadReg16(BRPHY2_DSP_TAP_TAP3_C3)
#define BRPHY2_DSP_TAP_TAP3_C3_SOFT_DECISION_MASK                  0xffff
#define BRPHY2_DSP_TAP_TAP3_C3_SOFT_DECISION_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP3_C3_SOFT_DECISION_BITS                  16
#define BRPHY2_DSP_TAP_TAP3_C3_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP4_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP4_C0 :: reserved0 [15:15] */
#define BRPHY2_DSP_TAP_TAP4_C0_RESERVED0_MASK                      0x8000
#define BRPHY2_DSP_TAP_TAP4_C0_RESERVED0_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C0_RESERVED0_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C0_RESERVED0_SHIFT                     15

/* BRPHY2_DSP_TAP :: TAP4_C0 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x7000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x7000,12)
#define BRPHY2_DSP_TAP_TAP4_C0_PAIR_OFFSET_MASK                    0x7000
#define BRPHY2_DSP_TAP_TAP4_C0_PAIR_OFFSET_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP4_C0_PAIR_OFFSET_BITS                    3
#define BRPHY2_DSP_TAP_TAP4_C0_PAIR_OFFSET_SHIFT                   12

/* BRPHY2_DSP_TAP :: TAP4_C0 :: GAMMA16 [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C0_GAMMA16(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C0_GAMMA16(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x800,11)
#define BRPHY2_DSP_TAP_TAP4_C0_GAMMA16_MASK                        0x0800
#define BRPHY2_DSP_TAP_TAP4_C0_GAMMA16_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP4_C0_GAMMA16_BITS                        1
#define BRPHY2_DSP_TAP_TAP4_C0_GAMMA16_SHIFT                       11

/* BRPHY2_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x400,10)
#define BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY2_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x200,9)
#define BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY2_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY2_DSP_TAP :: TAP4_C0 :: INC_PHASE [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C0_INC_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C0_INC_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x100,8)
#define BRPHY2_DSP_TAP_TAP4_C0_INC_PHASE_MASK                      0x0100
#define BRPHY2_DSP_TAP_TAP4_C0_INC_PHASE_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C0_INC_PHASE_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C0_INC_PHASE_SHIFT                     8

/* BRPHY2_DSP_TAP :: TAP4_C0 :: DEC_PHASE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C0_DEC_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C0_DEC_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x80,7)
#define BRPHY2_DSP_TAP_TAP4_C0_DEC_PHASE_MASK                      0x0080
#define BRPHY2_DSP_TAP_TAP4_C0_DEC_PHASE_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C0_DEC_PHASE_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C0_DEC_PHASE_SHIFT                     7

/* BRPHY2_DSP_TAP :: TAP4_C0 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x40,6)
#define BRPHY2_DSP_TAP_TAP4_C0_PHASE_FREEZE_MASK                   0x0040
#define BRPHY2_DSP_TAP_TAP4_C0_PHASE_FREEZE_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP4_C0_PHASE_FREEZE_BITS                   1
#define BRPHY2_DSP_TAP_TAP4_C0_PHASE_FREEZE_SHIFT                  6

/* BRPHY2_DSP_TAP :: TAP4_C0 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C0,0x3f,0)
#define BRPHY2_DSP_TAP_TAP4_C0_CURRENT_PHASE_MASK                  0x003f
#define BRPHY2_DSP_TAP_TAP4_C0_CURRENT_PHASE_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP4_C0_CURRENT_PHASE_BITS                  6
#define BRPHY2_DSP_TAP_TAP4_C0_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP4_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP4_C1 :: reserved0 [15:15] */
#define BRPHY2_DSP_TAP_TAP4_C1_RESERVED0_MASK                      0x8000
#define BRPHY2_DSP_TAP_TAP4_C1_RESERVED0_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C1_RESERVED0_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C1_RESERVED0_SHIFT                     15

/* BRPHY2_DSP_TAP :: TAP4_C1 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x7000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x7000,12)
#define BRPHY2_DSP_TAP_TAP4_C1_PAIR_OFFSET_MASK                    0x7000
#define BRPHY2_DSP_TAP_TAP4_C1_PAIR_OFFSET_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP4_C1_PAIR_OFFSET_BITS                    3
#define BRPHY2_DSP_TAP_TAP4_C1_PAIR_OFFSET_SHIFT                   12

/* BRPHY2_DSP_TAP :: TAP4_C1 :: GAMMA16 [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C1_GAMMA16(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C1_GAMMA16(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x800,11)
#define BRPHY2_DSP_TAP_TAP4_C1_GAMMA16_MASK                        0x0800
#define BRPHY2_DSP_TAP_TAP4_C1_GAMMA16_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP4_C1_GAMMA16_BITS                        1
#define BRPHY2_DSP_TAP_TAP4_C1_GAMMA16_SHIFT                       11

/* BRPHY2_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x400,10)
#define BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY2_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x200,9)
#define BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY2_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY2_DSP_TAP :: TAP4_C1 :: INC_PHASE [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C1_INC_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C1_INC_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x100,8)
#define BRPHY2_DSP_TAP_TAP4_C1_INC_PHASE_MASK                      0x0100
#define BRPHY2_DSP_TAP_TAP4_C1_INC_PHASE_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C1_INC_PHASE_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C1_INC_PHASE_SHIFT                     8

/* BRPHY2_DSP_TAP :: TAP4_C1 :: DEC_PHASE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C1_DEC_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C1_DEC_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x80,7)
#define BRPHY2_DSP_TAP_TAP4_C1_DEC_PHASE_MASK                      0x0080
#define BRPHY2_DSP_TAP_TAP4_C1_DEC_PHASE_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C1_DEC_PHASE_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C1_DEC_PHASE_SHIFT                     7

/* BRPHY2_DSP_TAP :: TAP4_C1 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x40,6)
#define BRPHY2_DSP_TAP_TAP4_C1_PHASE_FREEZE_MASK                   0x0040
#define BRPHY2_DSP_TAP_TAP4_C1_PHASE_FREEZE_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP4_C1_PHASE_FREEZE_BITS                   1
#define BRPHY2_DSP_TAP_TAP4_C1_PHASE_FREEZE_SHIFT                  6

/* BRPHY2_DSP_TAP :: TAP4_C1 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C1,0x3f,0)
#define BRPHY2_DSP_TAP_TAP4_C1_CURRENT_PHASE_MASK                  0x003f
#define BRPHY2_DSP_TAP_TAP4_C1_CURRENT_PHASE_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP4_C1_CURRENT_PHASE_BITS                  6
#define BRPHY2_DSP_TAP_TAP4_C1_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP4_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP4_C2 :: reserved0 [15:15] */
#define BRPHY2_DSP_TAP_TAP4_C2_RESERVED0_MASK                      0x8000
#define BRPHY2_DSP_TAP_TAP4_C2_RESERVED0_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C2_RESERVED0_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C2_RESERVED0_SHIFT                     15

/* BRPHY2_DSP_TAP :: TAP4_C2 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x7000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x7000,12)
#define BRPHY2_DSP_TAP_TAP4_C2_PAIR_OFFSET_MASK                    0x7000
#define BRPHY2_DSP_TAP_TAP4_C2_PAIR_OFFSET_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP4_C2_PAIR_OFFSET_BITS                    3
#define BRPHY2_DSP_TAP_TAP4_C2_PAIR_OFFSET_SHIFT                   12

/* BRPHY2_DSP_TAP :: TAP4_C2 :: GAMMA16 [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C2_GAMMA16(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C2_GAMMA16(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x800,11)
#define BRPHY2_DSP_TAP_TAP4_C2_GAMMA16_MASK                        0x0800
#define BRPHY2_DSP_TAP_TAP4_C2_GAMMA16_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP4_C2_GAMMA16_BITS                        1
#define BRPHY2_DSP_TAP_TAP4_C2_GAMMA16_SHIFT                       11

/* BRPHY2_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x400,10)
#define BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY2_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x200,9)
#define BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY2_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY2_DSP_TAP :: TAP4_C2 :: INC_PHASE [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C2_INC_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C2_INC_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x100,8)
#define BRPHY2_DSP_TAP_TAP4_C2_INC_PHASE_MASK                      0x0100
#define BRPHY2_DSP_TAP_TAP4_C2_INC_PHASE_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C2_INC_PHASE_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C2_INC_PHASE_SHIFT                     8

/* BRPHY2_DSP_TAP :: TAP4_C2 :: DEC_PHASE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C2_DEC_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C2_DEC_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x80,7)
#define BRPHY2_DSP_TAP_TAP4_C2_DEC_PHASE_MASK                      0x0080
#define BRPHY2_DSP_TAP_TAP4_C2_DEC_PHASE_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C2_DEC_PHASE_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C2_DEC_PHASE_SHIFT                     7

/* BRPHY2_DSP_TAP :: TAP4_C2 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x40,6)
#define BRPHY2_DSP_TAP_TAP4_C2_PHASE_FREEZE_MASK                   0x0040
#define BRPHY2_DSP_TAP_TAP4_C2_PHASE_FREEZE_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP4_C2_PHASE_FREEZE_BITS                   1
#define BRPHY2_DSP_TAP_TAP4_C2_PHASE_FREEZE_SHIFT                  6

/* BRPHY2_DSP_TAP :: TAP4_C2 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C2,0x3f,0)
#define BRPHY2_DSP_TAP_TAP4_C2_CURRENT_PHASE_MASK                  0x003f
#define BRPHY2_DSP_TAP_TAP4_C2_CURRENT_PHASE_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP4_C2_CURRENT_PHASE_BITS                  6
#define BRPHY2_DSP_TAP_TAP4_C2_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP4_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP4_C3 :: reserved0 [15:15] */
#define BRPHY2_DSP_TAP_TAP4_C3_RESERVED0_MASK                      0x8000
#define BRPHY2_DSP_TAP_TAP4_C3_RESERVED0_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C3_RESERVED0_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C3_RESERVED0_SHIFT                     15

/* BRPHY2_DSP_TAP :: TAP4_C3 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x7000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x7000,12)
#define BRPHY2_DSP_TAP_TAP4_C3_PAIR_OFFSET_MASK                    0x7000
#define BRPHY2_DSP_TAP_TAP4_C3_PAIR_OFFSET_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP4_C3_PAIR_OFFSET_BITS                    3
#define BRPHY2_DSP_TAP_TAP4_C3_PAIR_OFFSET_SHIFT                   12

/* BRPHY2_DSP_TAP :: TAP4_C3 :: GAMMA16 [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C3_GAMMA16(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C3_GAMMA16(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x800,11)
#define BRPHY2_DSP_TAP_TAP4_C3_GAMMA16_MASK                        0x0800
#define BRPHY2_DSP_TAP_TAP4_C3_GAMMA16_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP4_C3_GAMMA16_BITS                        1
#define BRPHY2_DSP_TAP_TAP4_C3_GAMMA16_SHIFT                       11

/* BRPHY2_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x400,10)
#define BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY2_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x200,9)
#define BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY2_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY2_DSP_TAP :: TAP4_C3 :: INC_PHASE [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C3_INC_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C3_INC_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x100,8)
#define BRPHY2_DSP_TAP_TAP4_C3_INC_PHASE_MASK                      0x0100
#define BRPHY2_DSP_TAP_TAP4_C3_INC_PHASE_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C3_INC_PHASE_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C3_INC_PHASE_SHIFT                     8

/* BRPHY2_DSP_TAP :: TAP4_C3 :: DEC_PHASE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C3_DEC_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C3_DEC_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x80,7)
#define BRPHY2_DSP_TAP_TAP4_C3_DEC_PHASE_MASK                      0x0080
#define BRPHY2_DSP_TAP_TAP4_C3_DEC_PHASE_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP4_C3_DEC_PHASE_BITS                      1
#define BRPHY2_DSP_TAP_TAP4_C3_DEC_PHASE_SHIFT                     7

/* BRPHY2_DSP_TAP :: TAP4_C3 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x40,6)
#define BRPHY2_DSP_TAP_TAP4_C3_PHASE_FREEZE_MASK                   0x0040
#define BRPHY2_DSP_TAP_TAP4_C3_PHASE_FREEZE_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP4_C3_PHASE_FREEZE_BITS                   1
#define BRPHY2_DSP_TAP_TAP4_C3_PHASE_FREEZE_SHIFT                  6

/* BRPHY2_DSP_TAP :: TAP4_C3 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP4_C3,0x3f,0)
#define BRPHY2_DSP_TAP_TAP4_C3_CURRENT_PHASE_MASK                  0x003f
#define BRPHY2_DSP_TAP_TAP4_C3_CURRENT_PHASE_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP4_C3_CURRENT_PHASE_BITS                  6
#define BRPHY2_DSP_TAP_TAP4_C3_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP5_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP5_C0 :: reserved0 [15:14] */
#define BRPHY2_DSP_TAP_TAP5_C0_RESERVED0_MASK                      0xc000
#define BRPHY2_DSP_TAP_TAP5_C0_RESERVED0_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP5_C0_RESERVED0_BITS                      2
#define BRPHY2_DSP_TAP_TAP5_C0_RESERVED0_SHIFT                     14

/* BRPHY2_DSP_TAP :: TAP5_C0 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_SLICE_ZERO(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_SLICE_ZERO(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x2000,13)
#define BRPHY2_DSP_TAP_TAP5_C0_SLICE_ZERO_MASK                     0x2000
#define BRPHY2_DSP_TAP_TAP5_C0_SLICE_ZERO_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP5_C0_SLICE_ZERO_BITS                     1
#define BRPHY2_DSP_TAP_TAP5_C0_SLICE_ZERO_SHIFT                    13

/* BRPHY2_DSP_TAP :: TAP5_C0 :: DISABLE_TX [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_DISABLE_TX(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_DISABLE_TX(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x1000,12)
#define BRPHY2_DSP_TAP_TAP5_C0_DISABLE_TX_MASK                     0x1000
#define BRPHY2_DSP_TAP_TAP5_C0_DISABLE_TX_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP5_C0_DISABLE_TX_BITS                     1
#define BRPHY2_DSP_TAP_TAP5_C0_DISABLE_TX_SHIFT                    12

/* BRPHY2_DSP_TAP :: TAP5_C0 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x800,11)
#define BRPHY2_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY2_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY2_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY2_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY2_DSP_TAP :: TAP5_C0 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x400,10)
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY2_DSP_TAP :: TAP5_C0 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x3c0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x3c0,6)
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_MASK                      0x03c0
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_BITS                      4
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SKEW_SHIFT                     6

/* BRPHY2_DSP_TAP :: TAP5_C0 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x20,5)
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_BITS              1
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY2_DSP_TAP :: TAP5_C0 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_PAIR_SELECT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x18,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_PAIR_SELECT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x18,3)
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SELECT_MASK                    0x0018
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SELECT_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SELECT_BITS                    2
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_SELECT_SHIFT                   3

/* BRPHY2_DSP_TAP :: TAP5_C0 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x4,2)
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_POLARITY_MASK                  0x0004
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_POLARITY_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_POLARITY_BITS                  1
#define BRPHY2_DSP_TAP_TAP5_C0_PAIR_POLARITY_SHIFT                 2

/* BRPHY2_DSP_TAP :: TAP5_C0 :: SWAPCD [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_SWAPCD(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_SWAPCD(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x2,1)
#define BRPHY2_DSP_TAP_TAP5_C0_SWAPCD_MASK                         0x0002
#define BRPHY2_DSP_TAP_TAP5_C0_SWAPCD_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP5_C0_SWAPCD_BITS                         1
#define BRPHY2_DSP_TAP_TAP5_C0_SWAPCD_SHIFT                        1

/* BRPHY2_DSP_TAP :: TAP5_C0 :: SWAPAB [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C0_SWAPAB(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C0_SWAPAB(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C0,0x1,0)
#define BRPHY2_DSP_TAP_TAP5_C0_SWAPAB_MASK                         0x0001
#define BRPHY2_DSP_TAP_TAP5_C0_SWAPAB_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP5_C0_SWAPAB_BITS                         1
#define BRPHY2_DSP_TAP_TAP5_C0_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP5_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP5_C1 :: reserved0 [15:14] */
#define BRPHY2_DSP_TAP_TAP5_C1_RESERVED0_MASK                      0xc000
#define BRPHY2_DSP_TAP_TAP5_C1_RESERVED0_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP5_C1_RESERVED0_BITS                      2
#define BRPHY2_DSP_TAP_TAP5_C1_RESERVED0_SHIFT                     14

/* BRPHY2_DSP_TAP :: TAP5_C1 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_SLICE_ZERO(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_SLICE_ZERO(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x2000,13)
#define BRPHY2_DSP_TAP_TAP5_C1_SLICE_ZERO_MASK                     0x2000
#define BRPHY2_DSP_TAP_TAP5_C1_SLICE_ZERO_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP5_C1_SLICE_ZERO_BITS                     1
#define BRPHY2_DSP_TAP_TAP5_C1_SLICE_ZERO_SHIFT                    13

/* BRPHY2_DSP_TAP :: TAP5_C1 :: DISABLE_TX [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_DISABLE_TX(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_DISABLE_TX(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x1000,12)
#define BRPHY2_DSP_TAP_TAP5_C1_DISABLE_TX_MASK                     0x1000
#define BRPHY2_DSP_TAP_TAP5_C1_DISABLE_TX_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP5_C1_DISABLE_TX_BITS                     1
#define BRPHY2_DSP_TAP_TAP5_C1_DISABLE_TX_SHIFT                    12

/* BRPHY2_DSP_TAP :: TAP5_C1 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x800,11)
#define BRPHY2_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY2_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY2_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY2_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY2_DSP_TAP :: TAP5_C1 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x400,10)
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY2_DSP_TAP :: TAP5_C1 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x3c0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x3c0,6)
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_MASK                      0x03c0
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_BITS                      4
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SKEW_SHIFT                     6

/* BRPHY2_DSP_TAP :: TAP5_C1 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x20,5)
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_BITS              1
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY2_DSP_TAP :: TAP5_C1 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_PAIR_SELECT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x18,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_PAIR_SELECT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x18,3)
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SELECT_MASK                    0x0018
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SELECT_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SELECT_BITS                    2
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_SELECT_SHIFT                   3

/* BRPHY2_DSP_TAP :: TAP5_C1 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x4,2)
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_POLARITY_MASK                  0x0004
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_POLARITY_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_POLARITY_BITS                  1
#define BRPHY2_DSP_TAP_TAP5_C1_PAIR_POLARITY_SHIFT                 2

/* BRPHY2_DSP_TAP :: TAP5_C1 :: SWAPCD [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_SWAPCD(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_SWAPCD(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x2,1)
#define BRPHY2_DSP_TAP_TAP5_C1_SWAPCD_MASK                         0x0002
#define BRPHY2_DSP_TAP_TAP5_C1_SWAPCD_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP5_C1_SWAPCD_BITS                         1
#define BRPHY2_DSP_TAP_TAP5_C1_SWAPCD_SHIFT                        1

/* BRPHY2_DSP_TAP :: TAP5_C1 :: SWAPAB [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C1_SWAPAB(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C1_SWAPAB(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C1,0x1,0)
#define BRPHY2_DSP_TAP_TAP5_C1_SWAPAB_MASK                         0x0001
#define BRPHY2_DSP_TAP_TAP5_C1_SWAPAB_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP5_C1_SWAPAB_BITS                         1
#define BRPHY2_DSP_TAP_TAP5_C1_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP5_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP5_C2 :: reserved0 [15:14] */
#define BRPHY2_DSP_TAP_TAP5_C2_RESERVED0_MASK                      0xc000
#define BRPHY2_DSP_TAP_TAP5_C2_RESERVED0_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP5_C2_RESERVED0_BITS                      2
#define BRPHY2_DSP_TAP_TAP5_C2_RESERVED0_SHIFT                     14

/* BRPHY2_DSP_TAP :: TAP5_C2 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_SLICE_ZERO(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_SLICE_ZERO(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x2000,13)
#define BRPHY2_DSP_TAP_TAP5_C2_SLICE_ZERO_MASK                     0x2000
#define BRPHY2_DSP_TAP_TAP5_C2_SLICE_ZERO_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP5_C2_SLICE_ZERO_BITS                     1
#define BRPHY2_DSP_TAP_TAP5_C2_SLICE_ZERO_SHIFT                    13

/* BRPHY2_DSP_TAP :: TAP5_C2 :: DISABLE_TX [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_DISABLE_TX(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_DISABLE_TX(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x1000,12)
#define BRPHY2_DSP_TAP_TAP5_C2_DISABLE_TX_MASK                     0x1000
#define BRPHY2_DSP_TAP_TAP5_C2_DISABLE_TX_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP5_C2_DISABLE_TX_BITS                     1
#define BRPHY2_DSP_TAP_TAP5_C2_DISABLE_TX_SHIFT                    12

/* BRPHY2_DSP_TAP :: TAP5_C2 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x800,11)
#define BRPHY2_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY2_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY2_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY2_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY2_DSP_TAP :: TAP5_C2 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x400,10)
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY2_DSP_TAP :: TAP5_C2 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x3c0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x3c0,6)
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_MASK                      0x03c0
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_BITS                      4
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SKEW_SHIFT                     6

/* BRPHY2_DSP_TAP :: TAP5_C2 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x20,5)
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_BITS              1
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY2_DSP_TAP :: TAP5_C2 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_PAIR_SELECT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x18,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_PAIR_SELECT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x18,3)
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SELECT_MASK                    0x0018
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SELECT_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SELECT_BITS                    2
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_SELECT_SHIFT                   3

/* BRPHY2_DSP_TAP :: TAP5_C2 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x4,2)
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_POLARITY_MASK                  0x0004
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_POLARITY_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_POLARITY_BITS                  1
#define BRPHY2_DSP_TAP_TAP5_C2_PAIR_POLARITY_SHIFT                 2

/* BRPHY2_DSP_TAP :: TAP5_C2 :: SWAPCD [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_SWAPCD(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_SWAPCD(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x2,1)
#define BRPHY2_DSP_TAP_TAP5_C2_SWAPCD_MASK                         0x0002
#define BRPHY2_DSP_TAP_TAP5_C2_SWAPCD_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP5_C2_SWAPCD_BITS                         1
#define BRPHY2_DSP_TAP_TAP5_C2_SWAPCD_SHIFT                        1

/* BRPHY2_DSP_TAP :: TAP5_C2 :: SWAPAB [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C2_SWAPAB(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C2_SWAPAB(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C2,0x1,0)
#define BRPHY2_DSP_TAP_TAP5_C2_SWAPAB_MASK                         0x0001
#define BRPHY2_DSP_TAP_TAP5_C2_SWAPAB_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP5_C2_SWAPAB_BITS                         1
#define BRPHY2_DSP_TAP_TAP5_C2_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP5_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP5_C3 :: reserved0 [15:14] */
#define BRPHY2_DSP_TAP_TAP5_C3_RESERVED0_MASK                      0xc000
#define BRPHY2_DSP_TAP_TAP5_C3_RESERVED0_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP5_C3_RESERVED0_BITS                      2
#define BRPHY2_DSP_TAP_TAP5_C3_RESERVED0_SHIFT                     14

/* BRPHY2_DSP_TAP :: TAP5_C3 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_SLICE_ZERO(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_SLICE_ZERO(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x2000,13)
#define BRPHY2_DSP_TAP_TAP5_C3_SLICE_ZERO_MASK                     0x2000
#define BRPHY2_DSP_TAP_TAP5_C3_SLICE_ZERO_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP5_C3_SLICE_ZERO_BITS                     1
#define BRPHY2_DSP_TAP_TAP5_C3_SLICE_ZERO_SHIFT                    13

/* BRPHY2_DSP_TAP :: TAP5_C3 :: DISABLE_TX [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_DISABLE_TX(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_DISABLE_TX(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x1000,12)
#define BRPHY2_DSP_TAP_TAP5_C3_DISABLE_TX_MASK                     0x1000
#define BRPHY2_DSP_TAP_TAP5_C3_DISABLE_TX_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP5_C3_DISABLE_TX_BITS                     1
#define BRPHY2_DSP_TAP_TAP5_C3_DISABLE_TX_SHIFT                    12

/* BRPHY2_DSP_TAP :: TAP5_C3 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x800,11)
#define BRPHY2_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY2_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY2_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY2_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY2_DSP_TAP :: TAP5_C3 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x400,10)
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY2_DSP_TAP :: TAP5_C3 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x3c0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x3c0,6)
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_MASK                      0x03c0
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_BITS                      4
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SKEW_SHIFT                     6

/* BRPHY2_DSP_TAP :: TAP5_C3 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x20,5)
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_BITS              1
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY2_DSP_TAP :: TAP5_C3 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_PAIR_SELECT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x18,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_PAIR_SELECT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x18,3)
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SELECT_MASK                    0x0018
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SELECT_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SELECT_BITS                    2
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_SELECT_SHIFT                   3

/* BRPHY2_DSP_TAP :: TAP5_C3 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x4,2)
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_POLARITY_MASK                  0x0004
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_POLARITY_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_POLARITY_BITS                  1
#define BRPHY2_DSP_TAP_TAP5_C3_PAIR_POLARITY_SHIFT                 2

/* BRPHY2_DSP_TAP :: TAP5_C3 :: SWAPCD [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_SWAPCD(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_SWAPCD(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x2,1)
#define BRPHY2_DSP_TAP_TAP5_C3_SWAPCD_MASK                         0x0002
#define BRPHY2_DSP_TAP_TAP5_C3_SWAPCD_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP5_C3_SWAPCD_BITS                         1
#define BRPHY2_DSP_TAP_TAP5_C3_SWAPCD_SHIFT                        1

/* BRPHY2_DSP_TAP :: TAP5_C3 :: SWAPAB [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP5_C3_SWAPAB(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP5_C3_SWAPAB(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP5_C3,0x1,0)
#define BRPHY2_DSP_TAP_TAP5_C3_SWAPAB_MASK                         0x0001
#define BRPHY2_DSP_TAP_TAP5_C3_SWAPAB_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP5_C3_SWAPAB_BITS                         1
#define BRPHY2_DSP_TAP_TAP5_C3_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP6
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP6 :: CFCDEADMAN_DIS [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP6,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP6,0x8000,15)
#define BRPHY2_DSP_TAP_TAP6_CFCDEADMAN_DIS_MASK                    0x8000
#define BRPHY2_DSP_TAP_TAP6_CFCDEADMAN_DIS_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP6_CFCDEADMAN_DIS_BITS                    1
#define BRPHY2_DSP_TAP_TAP6_CFCDEADMAN_DIS_SHIFT                   15

/* BRPHY2_DSP_TAP :: TAP6 :: AGC_FREEZ_EN [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP6_AGC_FREEZ_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP6,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP6_AGC_FREEZ_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP6,0x4000,14)
#define BRPHY2_DSP_TAP_TAP6_AGC_FREEZ_EN_MASK                      0x4000
#define BRPHY2_DSP_TAP_TAP6_AGC_FREEZ_EN_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP6_AGC_FREEZ_EN_BITS                      1
#define BRPHY2_DSP_TAP_TAP6_AGC_FREEZ_EN_SHIFT                     14

/* BRPHY2_DSP_TAP :: TAP6 :: DAC_GAIN_INV_EN [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP6,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP6,0x2000,13)
#define BRPHY2_DSP_TAP_TAP6_DAC_GAIN_INV_EN_MASK                   0x2000
#define BRPHY2_DSP_TAP_TAP6_DAC_GAIN_INV_EN_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP6_DAC_GAIN_INV_EN_BITS                   1
#define BRPHY2_DSP_TAP_TAP6_DAC_GAIN_INV_EN_SHIFT                  13

/* BRPHY2_DSP_TAP :: TAP6 :: SPARE_REG_B12 [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP6_SPARE_REG_B12(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP6,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP6_SPARE_REG_B12(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP6,0x1000,12)
#define BRPHY2_DSP_TAP_TAP6_SPARE_REG_B12_MASK                     0x1000
#define BRPHY2_DSP_TAP_TAP6_SPARE_REG_B12_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP6_SPARE_REG_B12_BITS                     1
#define BRPHY2_DSP_TAP_TAP6_SPARE_REG_B12_SHIFT                    12

/* BRPHY2_DSP_TAP :: TAP6 :: FORCE_FSM_IDLE [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP6,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP6,0x800,11)
#define BRPHY2_DSP_TAP_TAP6_FORCE_FSM_IDLE_MASK                    0x0800
#define BRPHY2_DSP_TAP_TAP6_FORCE_FSM_IDLE_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP6_FORCE_FSM_IDLE_BITS                    1
#define BRPHY2_DSP_TAP_TAP6_FORCE_FSM_IDLE_SHIFT                   11

/* BRPHY2_DSP_TAP :: TAP6 :: SPARE_REG [10:00] */
#define Wr_BRPHY2_DSP_TAP_TAP6_SPARE_REG(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP6,0x7ff,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP6_SPARE_REG(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP6,0x7ff,0)
#define BRPHY2_DSP_TAP_TAP6_SPARE_REG_MASK                         0x07ff
#define BRPHY2_DSP_TAP_TAP6_SPARE_REG_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP6_SPARE_REG_BITS                         11
#define BRPHY2_DSP_TAP_TAP6_SPARE_REG_SHIFT                        0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP7_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP7_C0 :: TEST_LENGTH [15:09] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_TEST_LENGTH(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0xfe00,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_TEST_LENGTH(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0xfe00,9)
#define BRPHY2_DSP_TAP_TAP7_C0_TEST_LENGTH_MASK                    0xfe00
#define BRPHY2_DSP_TAP_TAP7_C0_TEST_LENGTH_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP7_C0_TEST_LENGTH_BITS                    7
#define BRPHY2_DSP_TAP_TAP7_C0_TEST_LENGTH_SHIFT                   9

/* BRPHY2_DSP_TAP :: TAP7_C0 :: SINGLE_TAP_MODE [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x100,8)
#define BRPHY2_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_MASK                0x0100
#define BRPHY2_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_ALIGN               0
#define BRPHY2_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_BITS                1
#define BRPHY2_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_SHIFT               8

/* BRPHY2_DSP_TAP :: TAP7_C0 :: UPDATE_MODE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x80,7)
#define BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MODE_MASK                    0x0080
#define BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MODE_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MODE_BITS                    1
#define BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MODE_SHIFT                   7

/* BRPHY2_DSP_TAP :: TAP7_C0 :: UPDATE_MAGNITUDE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x40,6)
#define BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_MASK               0x0040
#define BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_BITS               1
#define BRPHY2_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_SHIFT              6

/* BRPHY2_DSP_TAP :: TAP7_C0 :: START_TEST [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_START_TEST(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_START_TEST(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x20,5)
#define BRPHY2_DSP_TAP_TAP7_C0_START_TEST_MASK                     0x0020
#define BRPHY2_DSP_TAP_TAP7_C0_START_TEST_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP7_C0_START_TEST_BITS                     1
#define BRPHY2_DSP_TAP_TAP7_C0_START_TEST_SHIFT                    5

/* BRPHY2_DSP_TAP :: TAP7_C0 :: ZERO_DFE_D [04:04] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x10,4)
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_D_MASK                     0x0010
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_D_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_D_BITS                     1
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_D_SHIFT                    4

/* BRPHY2_DSP_TAP :: TAP7_C0 :: ZERO_DFE_C [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x8,3)
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_C_MASK                     0x0008
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_C_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_C_BITS                     1
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_C_SHIFT                    3

/* BRPHY2_DSP_TAP :: TAP7_C0 :: ZERO_DFE_B [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x4,2)
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_B_MASK                     0x0004
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_B_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_B_BITS                     1
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_B_SHIFT                    2

/* BRPHY2_DSP_TAP :: TAP7_C0 :: ZERO_DFE_A [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x2,1)
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_A_MASK                     0x0002
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_A_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_A_BITS                     1
#define BRPHY2_DSP_TAP_TAP7_C0_ZERO_DFE_A_SHIFT                    1

/* BRPHY2_DSP_TAP :: TAP7_C0 :: ENABLE_BIST_MODE [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C0,0x1,0)
#define BRPHY2_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_MASK               0x0001
#define BRPHY2_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_BITS               1
#define BRPHY2_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_SHIFT              0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP7_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP7_C1 :: TAP_NUMBER [15:08] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C1_TAP_NUMBER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C1,0xff00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C1_TAP_NUMBER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C1,0xff00,8)
#define BRPHY2_DSP_TAP_TAP7_C1_TAP_NUMBER_MASK                     0xff00
#define BRPHY2_DSP_TAP_TAP7_C1_TAP_NUMBER_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP7_C1_TAP_NUMBER_BITS                     8
#define BRPHY2_DSP_TAP_TAP7_C1_TAP_NUMBER_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP7_C1 :: POLARITY_MASK_LSB [07:00] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C1,0xff,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C1,0xff,0)
#define BRPHY2_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_MASK              0x00ff
#define BRPHY2_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_ALIGN             0
#define BRPHY2_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_BITS              8
#define BRPHY2_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_SHIFT             0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP7_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP7_C2 :: SPARE [15:08] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C2_SPARE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0xff00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C2_SPARE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0xff00,8)
#define BRPHY2_DSP_TAP_TAP7_C2_SPARE_MASK                          0xff00
#define BRPHY2_DSP_TAP_TAP7_C2_SPARE_ALIGN                         0
#define BRPHY2_DSP_TAP_TAP7_C2_SPARE_BITS                          8
#define BRPHY2_DSP_TAP_TAP7_C2_SPARE_SHIFT                         8

/* BRPHY2_DSP_TAP :: TAP7_C2 :: BIST_FFE_UPDATE_EN [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x80,7)
#define BRPHY2_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_MASK             0x0080
#define BRPHY2_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_ALIGN            0
#define BRPHY2_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_BITS             1
#define BRPHY2_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_SHIFT            7

/* BRPHY2_DSP_TAP :: TAP7_C2 :: DISABLE_RANDOM_BIST_ADC [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x40,6)
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_MASK        0x0040
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_ALIGN       0
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_BITS        1
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_SHIFT       6

/* BRPHY2_DSP_TAP :: TAP7_C2 :: DISABLE_VITERBI_TO_BIST [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x20,5)
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_MASK        0x0020
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_ALIGN       0
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_BITS        1
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_SHIFT       5

/* BRPHY2_DSP_TAP :: TAP7_C2 :: USE_BIST_FOR_DFE [04:04] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x10,4)
#define BRPHY2_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_MASK               0x0010
#define BRPHY2_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_BITS               1
#define BRPHY2_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_SHIFT              4

/* BRPHY2_DSP_TAP :: TAP7_C2 :: FORCE_VITERBI_MODE [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x8,3)
#define BRPHY2_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_MASK             0x0008
#define BRPHY2_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_ALIGN            0
#define BRPHY2_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_BITS             1
#define BRPHY2_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_SHIFT            3

/* BRPHY2_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_IPRK_OV [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x4,2)
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_MASK           0x0004
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_ALIGN          0
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_BITS           1
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_SHIFT          2

/* BRPHY2_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_GAMMA_OV [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x2,1)
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_MASK          0x0002
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_ALIGN         0
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_BITS          1
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_SHIFT         1

/* BRPHY2_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_ADC_OV [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP7_C2,0x1,0)
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_MASK            0x0001
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_ALIGN           0
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_BITS            1
#define BRPHY2_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_SHIFT           0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP8_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP8_C0 :: PGA_OV [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_PGA_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_PGA_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x8000,15)
#define BRPHY2_DSP_TAP_TAP8_C0_PGA_OV_MASK                         0x8000
#define BRPHY2_DSP_TAP_TAP8_C0_PGA_OV_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP8_C0_PGA_OV_BITS                         1
#define BRPHY2_DSP_TAP_TAP8_C0_PGA_OV_SHIFT                        15

/* BRPHY2_DSP_TAP :: TAP8_C0 :: TIMER_OV [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_TIMER_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_TIMER_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x4000,14)
#define BRPHY2_DSP_TAP_TAP8_C0_TIMER_OV_MASK                       0x4000
#define BRPHY2_DSP_TAP_TAP8_C0_TIMER_OV_ALIGN                      0
#define BRPHY2_DSP_TAP_TAP8_C0_TIMER_OV_BITS                       1
#define BRPHY2_DSP_TAP_TAP8_C0_TIMER_OV_SHIFT                      14

/* BRPHY2_DSP_TAP :: TAP8_C0 :: MONOTONICITY_MODE [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x2000,13)
#define BRPHY2_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_MASK              0x2000
#define BRPHY2_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_ALIGN             0
#define BRPHY2_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_BITS              1
#define BRPHY2_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_SHIFT             13

/* BRPHY2_DSP_TAP :: TAP8_C0 :: FREEZE_ERROR_ON_FAIL [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x1000,12)
#define BRPHY2_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_MASK           0x1000
#define BRPHY2_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_ALIGN          0
#define BRPHY2_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_BITS           1
#define BRPHY2_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_SHIFT          12

/* BRPHY2_DSP_TAP :: TAP8_C0 :: FREEZE_MSE_ON_FAIL [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x800,11)
#define BRPHY2_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_MASK             0x0800
#define BRPHY2_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_ALIGN            0
#define BRPHY2_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_BITS             1
#define BRPHY2_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_SHIFT            11

/* BRPHY2_DSP_TAP :: TAP8_C0 :: FAST_CONV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x400,10)
#define BRPHY2_DSP_TAP_TAP8_C0_FAST_CONV_EN_MASK                   0x0400
#define BRPHY2_DSP_TAP_TAP8_C0_FAST_CONV_EN_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP8_C0_FAST_CONV_EN_BITS                   1
#define BRPHY2_DSP_TAP_TAP8_C0_FAST_CONV_EN_SHIFT                  10

/* BRPHY2_DSP_TAP :: TAP8_C0 :: PGA_TOGGLE_MODE_EN [09:09] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x200,9)
#define BRPHY2_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_MASK             0x0200
#define BRPHY2_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_ALIGN            0
#define BRPHY2_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_BITS             1
#define BRPHY2_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_SHIFT            9

/* BRPHY2_DSP_TAP :: TAP8_C0 :: PAT_GEN_EN [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x100,8)
#define BRPHY2_DSP_TAP_TAP8_C0_PAT_GEN_EN_MASK                     0x0100
#define BRPHY2_DSP_TAP_TAP8_C0_PAT_GEN_EN_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP8_C0_PAT_GEN_EN_BITS                     1
#define BRPHY2_DSP_TAP_TAP8_C0_PAT_GEN_EN_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP8_C0 :: MAX_OFFSET_CHECK_EN [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x80,7)
#define BRPHY2_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_MASK            0x0080
#define BRPHY2_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_ALIGN           0
#define BRPHY2_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_BITS            1
#define BRPHY2_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_SHIFT           7

/* BRPHY2_DSP_TAP :: TAP8_C0 :: SYM_ERR_CHECK_EN [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x40,6)
#define BRPHY2_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_MASK               0x0040
#define BRPHY2_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_ALIGN              0
#define BRPHY2_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_BITS               1
#define BRPHY2_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_SHIFT              6

/* BRPHY2_DSP_TAP :: TAP8_C0 :: PEAK_ERR_CHECK_EN [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x20,5)
#define BRPHY2_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_MASK              0x0020
#define BRPHY2_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_ALIGN             0
#define BRPHY2_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_BITS              1
#define BRPHY2_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_SHIFT             5

/* BRPHY2_DSP_TAP :: TAP8_C0 :: MSE_CHECK_EN [04:04] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x10,4)
#define BRPHY2_DSP_TAP_TAP8_C0_MSE_CHECK_EN_MASK                   0x0010
#define BRPHY2_DSP_TAP_TAP8_C0_MSE_CHECK_EN_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP8_C0_MSE_CHECK_EN_BITS                   1
#define BRPHY2_DSP_TAP_TAP8_C0_MSE_CHECK_EN_SHIFT                  4

/* BRPHY2_DSP_TAP :: TAP8_C0 :: GAIN_AMP_CHECK_EN [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x8,3)
#define BRPHY2_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_MASK              0x0008
#define BRPHY2_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_ALIGN             0
#define BRPHY2_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_BITS              1
#define BRPHY2_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_SHIFT             3

/* BRPHY2_DSP_TAP :: TAP8_C0 :: HALT_ON_ERROR [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x4,2)
#define BRPHY2_DSP_TAP_TAP8_C0_HALT_ON_ERROR_MASK                  0x0004
#define BRPHY2_DSP_TAP_TAP8_C0_HALT_ON_ERROR_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP8_C0_HALT_ON_ERROR_BITS                  1
#define BRPHY2_DSP_TAP_TAP8_C0_HALT_ON_ERROR_SHIFT                 2

/* BRPHY2_DSP_TAP :: TAP8_C0 :: START_ABIST [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_START_ABIST(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_START_ABIST(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x2,1)
#define BRPHY2_DSP_TAP_TAP8_C0_START_ABIST_MASK                    0x0002
#define BRPHY2_DSP_TAP_TAP8_C0_START_ABIST_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP8_C0_START_ABIST_BITS                    1
#define BRPHY2_DSP_TAP_TAP8_C0_START_ABIST_SHIFT                   1

/* BRPHY2_DSP_TAP :: TAP8_C0 :: ABIST_EN [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C0_ABIST_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C0_ABIST_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C0,0x1,0)
#define BRPHY2_DSP_TAP_TAP8_C0_ABIST_EN_MASK                       0x0001
#define BRPHY2_DSP_TAP_TAP8_C0_ABIST_EN_ALIGN                      0
#define BRPHY2_DSP_TAP_TAP8_C0_ABIST_EN_BITS                       1
#define BRPHY2_DSP_TAP_TAP8_C0_ABIST_EN_SHIFT                      0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP8_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP8_C1 :: MAJOR_MODE [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_MAJOR_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_MAJOR_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x8000,15)
#define BRPHY2_DSP_TAP_TAP8_C1_MAJOR_MODE_MASK                     0x8000
#define BRPHY2_DSP_TAP_TAP8_C1_MAJOR_MODE_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP8_C1_MAJOR_MODE_BITS                     1
#define BRPHY2_DSP_TAP_TAP8_C1_MAJOR_MODE_SHIFT                    15

/* BRPHY2_DSP_TAP :: TAP8_C1 :: MULTIPLE_MSE [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x4000,14)
#define BRPHY2_DSP_TAP_TAP8_C1_MULTIPLE_MSE_MASK                   0x4000
#define BRPHY2_DSP_TAP_TAP8_C1_MULTIPLE_MSE_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP8_C1_MULTIPLE_MSE_BITS                   1
#define BRPHY2_DSP_TAP_TAP8_C1_MULTIPLE_MSE_SHIFT                  14

/* BRPHY2_DSP_TAP :: TAP8_C1 :: GAMMA_OV [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_GAMMA_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_GAMMA_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x2000,13)
#define BRPHY2_DSP_TAP_TAP8_C1_GAMMA_OV_MASK                       0x2000
#define BRPHY2_DSP_TAP_TAP8_C1_GAMMA_OV_ALIGN                      0
#define BRPHY2_DSP_TAP_TAP8_C1_GAMMA_OV_BITS                       1
#define BRPHY2_DSP_TAP_TAP8_C1_GAMMA_OV_SHIFT                      13

/* BRPHY2_DSP_TAP :: TAP8_C1 :: FFE_COARSE_OV [12:08] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x1f00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x1f00,8)
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_COARSE_OV_MASK                  0x1f00
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_COARSE_OV_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_COARSE_OV_BITS                  5
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_COARSE_OV_SHIFT                 8

/* BRPHY2_DSP_TAP :: TAP8_C1 :: FFE_PF_OV_INIT [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x80,7)
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_MASK                 0x0080
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_ALIGN                0
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_BITS                 1
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_SHIFT                7

/* BRPHY2_DSP_TAP :: TAP8_C1 :: SINGLE_STEP_MODE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x40,6)
#define BRPHY2_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_MASK               0x0040
#define BRPHY2_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_BITS               1
#define BRPHY2_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_SHIFT              6

/* BRPHY2_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SEL [05:04] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x30,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x30,4)
#define BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_MASK               0x0030
#define BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_ALIGN              0
#define BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_BITS               2
#define BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_SHIFT              4

/* BRPHY2_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SE_EN [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x8,3)
#define BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_MASK             0x0008
#define BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_ALIGN            0
#define BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_BITS             1
#define BRPHY2_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_SHIFT            3

/* BRPHY2_DSP_TAP :: TAP8_C1 :: TX_HALFOUT_OV [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x4,2)
#define BRPHY2_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_MASK                  0x0004
#define BRPHY2_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_BITS                  1
#define BRPHY2_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_SHIFT                 2

/* BRPHY2_DSP_TAP :: TAP8_C1 :: TX_ADJ_EN [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x2,1)
#define BRPHY2_DSP_TAP_TAP8_C1_TX_ADJ_EN_MASK                      0x0002
#define BRPHY2_DSP_TAP_TAP8_C1_TX_ADJ_EN_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP8_C1_TX_ADJ_EN_BITS                      1
#define BRPHY2_DSP_TAP_TAP8_C1_TX_ADJ_EN_SHIFT                     1

/* BRPHY2_DSP_TAP :: TAP8_C1 :: FFE_BUMP_EN [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C1,0x1,0)
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_BUMP_EN_MASK                    0x0001
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_BUMP_EN_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_BUMP_EN_BITS                    1
#define BRPHY2_DSP_TAP_TAP8_C1_FFE_BUMP_EN_SHIFT                   0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP8_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP8_C2 :: LEVELSELECT [15:13] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_LEVELSELECT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0xe000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_LEVELSELECT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0xe000,13)
#define BRPHY2_DSP_TAP_TAP8_C2_LEVELSELECT_MASK                    0xe000
#define BRPHY2_DSP_TAP_TAP8_C2_LEVELSELECT_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP8_C2_LEVELSELECT_BITS                    3
#define BRPHY2_DSP_TAP_TAP8_C2_LEVELSELECT_SHIFT                   13

/* BRPHY2_DSP_TAP :: TAP8_C2 :: FAILING_CHANNEL [12:11] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x1800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x1800,11)
#define BRPHY2_DSP_TAP_TAP8_C2_FAILING_CHANNEL_MASK                0x1800
#define BRPHY2_DSP_TAP_TAP8_C2_FAILING_CHANNEL_ALIGN               0
#define BRPHY2_DSP_TAP_TAP8_C2_FAILING_CHANNEL_BITS                2
#define BRPHY2_DSP_TAP_TAP8_C2_FAILING_CHANNEL_SHIFT               11

/* BRPHY2_DSP_TAP :: TAP8_C2 :: CONV_FAIL_FLAG [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x400,10)
#define BRPHY2_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_MASK                 0x0400
#define BRPHY2_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_ALIGN                0
#define BRPHY2_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_BITS                 1
#define BRPHY2_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_SHIFT                10

/* BRPHY2_DSP_TAP :: TAP8_C2 :: SYM_ERR_FAIL_FLAG [09:09] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x200,9)
#define BRPHY2_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_MASK              0x0200
#define BRPHY2_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_ALIGN             0
#define BRPHY2_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_BITS              1
#define BRPHY2_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_SHIFT             9

/* BRPHY2_DSP_TAP :: TAP8_C2 :: MAX_OFFSET_FAIL_FLAG [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x100,8)
#define BRPHY2_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_MASK           0x0100
#define BRPHY2_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_ALIGN          0
#define BRPHY2_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_BITS           1
#define BRPHY2_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_SHIFT          8

/* BRPHY2_DSP_TAP :: TAP8_C2 :: PEAK_ERR_FAIL_FLAG [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x80,7)
#define BRPHY2_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_MASK             0x0080
#define BRPHY2_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_ALIGN            0
#define BRPHY2_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_BITS             1
#define BRPHY2_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_SHIFT            7

/* BRPHY2_DSP_TAP :: TAP8_C2 :: MSE_FAIL_FLAG [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x40,6)
#define BRPHY2_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_MASK                  0x0040
#define BRPHY2_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_BITS                  1
#define BRPHY2_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_SHIFT                 6

/* BRPHY2_DSP_TAP :: TAP8_C2 :: GAIN_AMP_FAIL_FLAG [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x20,5)
#define BRPHY2_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_MASK             0x0020
#define BRPHY2_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_ALIGN            0
#define BRPHY2_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_BITS             1
#define BRPHY2_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_SHIFT            5

/* BRPHY2_DSP_TAP :: TAP8_C2 :: ABIST_COMPLETE_FLAG [04:04] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0x10,4)
#define BRPHY2_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_MASK            0x0010
#define BRPHY2_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_ALIGN           0
#define BRPHY2_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_BITS            1
#define BRPHY2_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_SHIFT           4

/* BRPHY2_DSP_TAP :: TAP8_C2 :: ADC_OVERFLOW [03:00] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C2,0xf,0)
#define BRPHY2_DSP_TAP_TAP8_C2_ADC_OVERFLOW_MASK                   0x000f
#define BRPHY2_DSP_TAP_TAP8_C2_ADC_OVERFLOW_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP8_C2_ADC_OVERFLOW_BITS                   4
#define BRPHY2_DSP_TAP_TAP8_C2_ADC_OVERFLOW_SHIFT                  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP8_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP8_C3 :: SPARE [15:12] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C3_SPARE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C3,0xf000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C3_SPARE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C3,0xf000,12)
#define BRPHY2_DSP_TAP_TAP8_C3_SPARE_MASK                          0xf000
#define BRPHY2_DSP_TAP_TAP8_C3_SPARE_ALIGN                         0
#define BRPHY2_DSP_TAP_TAP8_C3_SPARE_BITS                          4
#define BRPHY2_DSP_TAP_TAP8_C3_SPARE_SHIFT                         12

/* BRPHY2_DSP_TAP :: TAP8_C3 :: BR_AGC_RST_VAL [11:10] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C3,0xc00,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C3,0xc00,10)
#define BRPHY2_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_MASK                 0x0c00
#define BRPHY2_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_ALIGN                0
#define BRPHY2_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_BITS                 2
#define BRPHY2_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_SHIFT                10

/* BRPHY2_DSP_TAP :: TAP8_C3 :: BR_HPF_CTL [09:00] */
#define Wr_BRPHY2_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP8_C3,0x3ff,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP8_C3,0x3ff,0)
#define BRPHY2_DSP_TAP_TAP8_C3_BR_HPF_CTL_MASK                     0x03ff
#define BRPHY2_DSP_TAP_TAP8_C3_BR_HPF_CTL_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP8_C3_BR_HPF_CTL_BITS                     10
#define BRPHY2_DSP_TAP_TAP8_C3_BR_HPF_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP9
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP9 :: FREQ_REG [15:04] */
#define Wr_BRPHY2_DSP_TAP_TAP9_FREQ_REG(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP9,0xfff0,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP9_FREQ_REG(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP9,0xfff0,4)
#define BRPHY2_DSP_TAP_TAP9_FREQ_REG_MASK                          0xfff0
#define BRPHY2_DSP_TAP_TAP9_FREQ_REG_ALIGN                         0
#define BRPHY2_DSP_TAP_TAP9_FREQ_REG_BITS                          12
#define BRPHY2_DSP_TAP_TAP9_FREQ_REG_SHIFT                         4

/* BRPHY2_DSP_TAP :: TAP9 :: FREQ_REG_OV_EN_ABCD [03:00] */
#define Wr_BRPHY2_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP9,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP9,0xf,0)
#define BRPHY2_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_MASK               0x000f
#define BRPHY2_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_ALIGN              0
#define BRPHY2_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_BITS               4
#define BRPHY2_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_SHIFT              0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP10
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP10 :: SLAVEENCCONVADJUST [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP10,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP10,0x8000,15)
#define BRPHY2_DSP_TAP_TAP10_SLAVEENCCONVADJUST_MASK               0x8000
#define BRPHY2_DSP_TAP_TAP10_SLAVEENCCONVADJUST_ALIGN              0
#define BRPHY2_DSP_TAP_TAP10_SLAVEENCCONVADJUST_BITS               1
#define BRPHY2_DSP_TAP_TAP10_SLAVEENCCONVADJUST_SHIFT              15

/* BRPHY2_DSP_TAP :: TAP10 :: TRIM_HYB [14:11] */
#define Wr_BRPHY2_DSP_TAP_TAP10_TRIM_HYB(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP10,0x7800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP10_TRIM_HYB(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP10,0x7800,11)
#define BRPHY2_DSP_TAP_TAP10_TRIM_HYB_MASK                         0x7800
#define BRPHY2_DSP_TAP_TAP10_TRIM_HYB_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP10_TRIM_HYB_BITS                         4
#define BRPHY2_DSP_TAP_TAP10_TRIM_HYB_SHIFT                        11

/* BRPHY2_DSP_TAP :: TAP10 :: FFE_GAMMA_OV [10:09] */
#define Wr_BRPHY2_DSP_TAP_TAP10_FFE_GAMMA_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP10,0x600,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP10_FFE_GAMMA_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP10,0x600,9)
#define BRPHY2_DSP_TAP_TAP10_FFE_GAMMA_OV_MASK                     0x0600
#define BRPHY2_DSP_TAP_TAP10_FFE_GAMMA_OV_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP10_FFE_GAMMA_OV_BITS                     2
#define BRPHY2_DSP_TAP_TAP10_FFE_GAMMA_OV_SHIFT                    9

/* BRPHY2_DSP_TAP :: TAP10 :: TX_PHASE_CTL_BW_SEL [08:07] */
#define Wr_BRPHY2_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP10,0x180,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP10,0x180,7)
#define BRPHY2_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_MASK              0x0180
#define BRPHY2_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_ALIGN             0
#define BRPHY2_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_BITS              2
#define BRPHY2_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_SHIFT             7

/* BRPHY2_DSP_TAP :: TAP10 :: RESET_PATH_METRICS [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP10_RESET_PATH_METRICS(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP10,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP10_RESET_PATH_METRICS(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP10,0x40,6)
#define BRPHY2_DSP_TAP_TAP10_RESET_PATH_METRICS_MASK               0x0040
#define BRPHY2_DSP_TAP_TAP10_RESET_PATH_METRICS_ALIGN              0
#define BRPHY2_DSP_TAP_TAP10_RESET_PATH_METRICS_BITS               1
#define BRPHY2_DSP_TAP_TAP10_RESET_PATH_METRICS_SHIFT              6

/* BRPHY2_DSP_TAP :: TAP10 :: GBT_PLL_BW_CTL_STARTUP [05:03] */
#define Wr_BRPHY2_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP10,0x38,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP10,0x38,3)
#define BRPHY2_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_MASK           0x0038
#define BRPHY2_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_ALIGN          0
#define BRPHY2_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_BITS           3
#define BRPHY2_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_SHIFT          3

/* BRPHY2_DSP_TAP :: TAP10 :: BGT_PLL_BW_CTL_NORMAL_OP [02:00] */
#define Wr_BRPHY2_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP10,0x7,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP10,0x7,0)
#define BRPHY2_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_MASK         0x0007
#define BRPHY2_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_ALIGN        0
#define BRPHY2_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_BITS         3
#define BRPHY2_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_SHIFT        0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP11
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP11 :: TCLK_OFFSET_STROBE [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP11,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP11,0x8000,15)
#define BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_MASK               0x8000
#define BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_BITS               1
#define BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_SHIFT              15

/* BRPHY2_DSP_TAP :: TAP11 :: RCLK_OFFSET_STROBE [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP11,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP11,0x4000,14)
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_MASK               0x4000
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_BITS               1
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_SHIFT              14

/* BRPHY2_DSP_TAP :: TAP11 :: reserved0 [13:13] */
#define BRPHY2_DSP_TAP_TAP11_RESERVED0_MASK                        0x2000
#define BRPHY2_DSP_TAP_TAP11_RESERVED0_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP11_RESERVED0_BITS                        1
#define BRPHY2_DSP_TAP_TAP11_RESERVED0_SHIFT                       13

/* BRPHY2_DSP_TAP :: TAP11 :: RCLK_OFFSET_FREEZE [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP11,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP11,0x1000,12)
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_MASK               0x1000
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_BITS               1
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_SHIFT              12

/* BRPHY2_DSP_TAP :: TAP11 :: TCLK_OFFSET [11:06] */
#define Wr_BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP11,0xfc0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP11,0xfc0,6)
#define BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_MASK                      0x0fc0
#define BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_BITS                      6
#define BRPHY2_DSP_TAP_TAP11_TCLK_OFFSET_SHIFT                     6

/* BRPHY2_DSP_TAP :: TAP11 :: RCLK_OFFSET [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP11,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP11,0x3f,0)
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_MASK                      0x003f
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_BITS                      6
#define BRPHY2_DSP_TAP_TAP11_RCLK_OFFSET_SHIFT                     0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP12_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP12_C0 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_TAP12_C0_RESERVED0_MASK                     0xff00
#define BRPHY2_DSP_TAP_TAP12_C0_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP12_C0_RESERVED0_BITS                     8
#define BRPHY2_DSP_TAP_TAP12_C0_RESERVED0_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C0,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C0,0x80,7)
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY2_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C0,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C0,0x40,6)
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY2_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C0,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C0,0x3f,0)
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_MASK                   0x003f
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_BITS                   6
#define BRPHY2_DSP_TAP_TAP12_C0_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP12_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP12_C1 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_TAP12_C1_RESERVED0_MASK                     0xff00
#define BRPHY2_DSP_TAP_TAP12_C1_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP12_C1_RESERVED0_BITS                     8
#define BRPHY2_DSP_TAP_TAP12_C1_RESERVED0_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C1,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C1,0x80,7)
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY2_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C1,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C1,0x40,6)
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY2_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C1,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C1,0x3f,0)
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_MASK                   0x003f
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_BITS                   6
#define BRPHY2_DSP_TAP_TAP12_C1_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP12_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP12_C2 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_TAP12_C2_RESERVED0_MASK                     0xff00
#define BRPHY2_DSP_TAP_TAP12_C2_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP12_C2_RESERVED0_BITS                     8
#define BRPHY2_DSP_TAP_TAP12_C2_RESERVED0_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C2,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C2,0x80,7)
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY2_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C2,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C2,0x40,6)
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY2_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C2,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C2,0x3f,0)
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_MASK                   0x003f
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_BITS                   6
#define BRPHY2_DSP_TAP_TAP12_C2_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP12_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP12_C3 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_TAP12_C3_RESERVED0_MASK                     0xff00
#define BRPHY2_DSP_TAP_TAP12_C3_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP12_C3_RESERVED0_BITS                     8
#define BRPHY2_DSP_TAP_TAP12_C3_RESERVED0_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C3,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C3,0x80,7)
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY2_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C3,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C3,0x40,6)
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY2_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP12_C3,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP12_C3,0x3f,0)
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_MASK                   0x003f
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_BITS                   6
#define BRPHY2_DSP_TAP_TAP12_C3_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP13
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP13 :: TMPLATE_EN [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP13_TMPLATE_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_TMPLATE_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0x8000,15)
#define BRPHY2_DSP_TAP_TAP13_TMPLATE_EN_MASK                       0x8000
#define BRPHY2_DSP_TAP_TAP13_TMPLATE_EN_ALIGN                      0
#define BRPHY2_DSP_TAP_TAP13_TMPLATE_EN_BITS                       1
#define BRPHY2_DSP_TAP_TAP13_TMPLATE_EN_SHIFT                      15

/* BRPHY2_DSP_TAP :: TAP13 :: PATTERN_DURATION [14:13] */
#define Wr_BRPHY2_DSP_TAP_TAP13_PATTERN_DURATION(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0x6000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_PATTERN_DURATION(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0x6000,13)
#define BRPHY2_DSP_TAP_TAP13_PATTERN_DURATION_MASK                 0x6000
#define BRPHY2_DSP_TAP_TAP13_PATTERN_DURATION_ALIGN                0
#define BRPHY2_DSP_TAP_TAP13_PATTERN_DURATION_BITS                 2
#define BRPHY2_DSP_TAP_TAP13_PATTERN_DURATION_SHIFT                13

/* BRPHY2_DSP_TAP :: TAP13 :: PATTERN_SEL [12:11] */
#define Wr_BRPHY2_DSP_TAP_TAP13_PATTERN_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0x1800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_PATTERN_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0x1800,11)
#define BRPHY2_DSP_TAP_TAP13_PATTERN_SEL_MASK                      0x1800
#define BRPHY2_DSP_TAP_TAP13_PATTERN_SEL_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP13_PATTERN_SEL_BITS                      2
#define BRPHY2_DSP_TAP_TAP13_PATTERN_SEL_SHIFT                     11

/* BRPHY2_DSP_TAP :: TAP13 :: PATTERN_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP13_PATTERN_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_PATTERN_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0x400,10)
#define BRPHY2_DSP_TAP_TAP13_PATTERN_EN_MASK                       0x0400
#define BRPHY2_DSP_TAP_TAP13_PATTERN_EN_ALIGN                      0
#define BRPHY2_DSP_TAP_TAP13_PATTERN_EN_BITS                       1
#define BRPHY2_DSP_TAP_TAP13_PATTERN_EN_SHIFT                      10

/* BRPHY2_DSP_TAP :: TAP13 :: DISABLETRRRGEN [09:09] */
#define Wr_BRPHY2_DSP_TAP_TAP13_DISABLETRRRGEN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_DISABLETRRRGEN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0x200,9)
#define BRPHY2_DSP_TAP_TAP13_DISABLETRRRGEN_MASK                   0x0200
#define BRPHY2_DSP_TAP_TAP13_DISABLETRRRGEN_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP13_DISABLETRRRGEN_BITS                   1
#define BRPHY2_DSP_TAP_TAP13_DISABLETRRRGEN_SHIFT                  9

/* BRPHY2_DSP_TAP :: TAP13 :: DISABLE10BEXTENSION [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0x100,8)
#define BRPHY2_DSP_TAP_TAP13_DISABLE10BEXTENSION_MASK              0x0100
#define BRPHY2_DSP_TAP_TAP13_DISABLE10BEXTENSION_ALIGN             0
#define BRPHY2_DSP_TAP_TAP13_DISABLE10BEXTENSION_BITS              1
#define BRPHY2_DSP_TAP_TAP13_DISABLE10BEXTENSION_SHIFT             8

/* BRPHY2_DSP_TAP :: TAP13 :: ALIGN_OK1_DISABLE [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0x80,7)
#define BRPHY2_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_MASK                0x0080
#define BRPHY2_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_ALIGN               0
#define BRPHY2_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_BITS                1
#define BRPHY2_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_SHIFT               7

/* BRPHY2_DSP_TAP :: TAP13 :: ALIGN_OK2_DISABLE [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0x40,6)
#define BRPHY2_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_MASK                0x0040
#define BRPHY2_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_ALIGN               0
#define BRPHY2_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_BITS                1
#define BRPHY2_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_SHIFT               6

/* BRPHY2_DSP_TAP :: TAP13 :: DISABLE_ADC_LSBS [05:04] */
#define Wr_BRPHY2_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0x30,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0x30,4)
#define BRPHY2_DSP_TAP_TAP13_DISABLE_ADC_LSBS_MASK                 0x0030
#define BRPHY2_DSP_TAP_TAP13_DISABLE_ADC_LSBS_ALIGN                0
#define BRPHY2_DSP_TAP_TAP13_DISABLE_ADC_LSBS_BITS                 2
#define BRPHY2_DSP_TAP_TAP13_DISABLE_ADC_LSBS_SHIFT                4

/* BRPHY2_DSP_TAP :: TAP13 :: IDLE_EXT_MASK [03:02] */
#define Wr_BRPHY2_DSP_TAP_TAP13_IDLE_EXT_MASK(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP13,0xc,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP13_IDLE_EXT_MASK(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP13,0xc,2)
#define BRPHY2_DSP_TAP_TAP13_IDLE_EXT_MASK_MASK                    0x000c
#define BRPHY2_DSP_TAP_TAP13_IDLE_EXT_MASK_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP13_IDLE_EXT_MASK_BITS                    2
#define BRPHY2_DSP_TAP_TAP13_IDLE_EXT_MASK_SHIFT                   2

/* BRPHY2_DSP_TAP :: TAP13 :: reserved0 [01:00] */
#define BRPHY2_DSP_TAP_TAP13_RESERVED0_MASK                        0x0003
#define BRPHY2_DSP_TAP_TAP13_RESERVED0_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP13_RESERVED0_BITS                        2
#define BRPHY2_DSP_TAP_TAP13_RESERVED0_SHIFT                       0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP14
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP14 :: MSE_THD_1_LSB [15:08] */
#define Wr_BRPHY2_DSP_TAP_TAP14_MSE_THD_1_LSB(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP14,0xff00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP14_MSE_THD_1_LSB(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP14,0xff00,8)
#define BRPHY2_DSP_TAP_TAP14_MSE_THD_1_LSB_MASK                    0xff00
#define BRPHY2_DSP_TAP_TAP14_MSE_THD_1_LSB_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP14_MSE_THD_1_LSB_BITS                    8
#define BRPHY2_DSP_TAP_TAP14_MSE_THD_1_LSB_SHIFT                   8

/* BRPHY2_DSP_TAP :: TAP14 :: ENERGY_DET_THD [07:00] */
#define Wr_BRPHY2_DSP_TAP_TAP14_ENERGY_DET_THD(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP14,0xff,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP14_ENERGY_DET_THD(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP14,0xff,0)
#define BRPHY2_DSP_TAP_TAP14_ENERGY_DET_THD_MASK                   0x00ff
#define BRPHY2_DSP_TAP_TAP14_ENERGY_DET_THD_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP14_ENERGY_DET_THD_BITS                   8
#define BRPHY2_DSP_TAP_TAP14_ENERGY_DET_THD_SHIFT                  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP15
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP15 :: MSE_THD_3_SEL [15:14] */
#define Wr_BRPHY2_DSP_TAP_TAP15_MSE_THD_3_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP15,0xc000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP15_MSE_THD_3_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP15,0xc000,14)
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_3_SEL_MASK                    0xc000
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_3_SEL_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_3_SEL_BITS                    2
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_3_SEL_SHIFT                   14

/* BRPHY2_DSP_TAP :: TAP15 :: MSE_THD_2 [13:02] */
#define Wr_BRPHY2_DSP_TAP_TAP15_MSE_THD_2(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP15,0x3ffc,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP15_MSE_THD_2(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP15,0x3ffc,2)
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_2_MASK                        0x3ffc
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_2_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_2_BITS                        12
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_2_SHIFT                       2

/* BRPHY2_DSP_TAP :: TAP15 :: MSE_THD_1_MSB [01:00] */
#define Wr_BRPHY2_DSP_TAP_TAP15_MSE_THD_1_MSB(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP15,0x3,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP15_MSE_THD_1_MSB(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP15,0x3,0)
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_1_MSB_MASK                    0x0003
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_1_MSB_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_1_MSB_BITS                    2
#define BRPHY2_DSP_TAP_TAP15_MSE_THD_1_MSB_SHIFT                   0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP16_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP16_C0 :: LA_TRIGGER_DELAY [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) WriteReg16(BRPHY2_DSP_TAP_TAP16_C0,x)
#define Rd_BRPHY2_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) ReadReg16(BRPHY2_DSP_TAP_TAP16_C0)
#define BRPHY2_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_MASK              0xffff
#define BRPHY2_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_ALIGN             0
#define BRPHY2_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_BITS              16
#define BRPHY2_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_SHIFT             0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP16_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP16_C1 :: BIST_CRC [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP16_C1_BIST_CRC(x) WriteReg16(BRPHY2_DSP_TAP_TAP16_C1,x)
#define Rd_BRPHY2_DSP_TAP_TAP16_C1_BIST_CRC(x) ReadReg16(BRPHY2_DSP_TAP_TAP16_C1)
#define BRPHY2_DSP_TAP_TAP16_C1_BIST_CRC_MASK                      0xffff
#define BRPHY2_DSP_TAP_TAP16_C1_BIST_CRC_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP16_C1_BIST_CRC_BITS                      16
#define BRPHY2_DSP_TAP_TAP16_C1_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP16_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP16_C2 :: BIST_CRC [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP16_C2_BIST_CRC(x) WriteReg16(BRPHY2_DSP_TAP_TAP16_C2,x)
#define Rd_BRPHY2_DSP_TAP_TAP16_C2_BIST_CRC(x) ReadReg16(BRPHY2_DSP_TAP_TAP16_C2)
#define BRPHY2_DSP_TAP_TAP16_C2_BIST_CRC_MASK                      0xffff
#define BRPHY2_DSP_TAP_TAP16_C2_BIST_CRC_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP16_C2_BIST_CRC_BITS                      16
#define BRPHY2_DSP_TAP_TAP16_C2_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP16_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP16_C3 :: BIST_CRC [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP16_C3_BIST_CRC(x) WriteReg16(BRPHY2_DSP_TAP_TAP16_C3,x)
#define Rd_BRPHY2_DSP_TAP_TAP16_C3_BIST_CRC(x) ReadReg16(BRPHY2_DSP_TAP_TAP16_C3)
#define BRPHY2_DSP_TAP_TAP16_C3_BIST_CRC_MASK                      0xffff
#define BRPHY2_DSP_TAP_TAP16_C3_BIST_CRC_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP16_C3_BIST_CRC_BITS                      16
#define BRPHY2_DSP_TAP_TAP16_C3_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP17_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP17_C0 :: TESTVALUE [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C0_TESTVALUE(x) WriteReg16(BRPHY2_DSP_TAP_TAP17_C0,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C0_TESTVALUE(x) ReadReg16(BRPHY2_DSP_TAP_TAP17_C0)
#define BRPHY2_DSP_TAP_TAP17_C0_TESTVALUE_MASK                     0xffff
#define BRPHY2_DSP_TAP_TAP17_C0_TESTVALUE_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP17_C0_TESTVALUE_BITS                     16
#define BRPHY2_DSP_TAP_TAP17_C0_TESTVALUE_SHIFT                    0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP17_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP17_C1 :: LA_ACQ_DONE [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x8000,15)
#define BRPHY2_DSP_TAP_TAP17_C1_LA_ACQ_DONE_MASK                   0x8000
#define BRPHY2_DSP_TAP_TAP17_C1_LA_ACQ_DONE_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP17_C1_LA_ACQ_DONE_BITS                   1
#define BRPHY2_DSP_TAP_TAP17_C1_LA_ACQ_DONE_SHIFT                  15

/* BRPHY2_DSP_TAP :: TAP17_C1 :: LA_TPOUT_SEL [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x4000,14)
#define BRPHY2_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_MASK                  0x4000
#define BRPHY2_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_BITS                  1
#define BRPHY2_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_SHIFT                 14

/* BRPHY2_DSP_TAP :: TAP17_C1 :: LA_CLK_DIVISOR [13:11] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x3800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x3800,11)
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_MASK                0x3800
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_ALIGN               0
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_BITS                3
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_SHIFT               11

/* BRPHY2_DSP_TAP :: TAP17_C1 :: LA_CLK_DELAY [10:09] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x600,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x600,9)
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DELAY_MASK                  0x0600
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DELAY_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DELAY_BITS                  2
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_DELAY_SHIFT                 9

/* BRPHY2_DSP_TAP :: TAP17_C1 :: LA_CLK_EDGE [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x100,8)
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_EDGE_MASK                   0x0100
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_EDGE_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_EDGE_BITS                   1
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_EDGE_SHIFT                  8

/* BRPHY2_DSP_TAP :: TAP17_C1 :: LA_CLK_SEL [07:03] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0xf8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0xf8,3)
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_SEL_MASK                    0x00f8
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_SEL_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_SEL_BITS                    5
#define BRPHY2_DSP_TAP_TAP17_C1_LA_CLK_SEL_SHIFT                   3

/* BRPHY2_DSP_TAP :: TAP17_C1 :: LA_ENABLE [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C1_LA_ENABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C1_LA_ENABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x4,2)
#define BRPHY2_DSP_TAP_TAP17_C1_LA_ENABLE_MASK                     0x0004
#define BRPHY2_DSP_TAP_TAP17_C1_LA_ENABLE_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP17_C1_LA_ENABLE_BITS                     1
#define BRPHY2_DSP_TAP_TAP17_C1_LA_ENABLE_SHIFT                    2

/* BRPHY2_DSP_TAP :: TAP17_C1 :: TESTMODE_STROBE [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x2,1)
#define BRPHY2_DSP_TAP_TAP17_C1_TESTMODE_STROBE_MASK               0x0002
#define BRPHY2_DSP_TAP_TAP17_C1_TESTMODE_STROBE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP17_C1_TESTMODE_STROBE_BITS               1
#define BRPHY2_DSP_TAP_TAP17_C1_TESTMODE_STROBE_SHIFT              1

/* BRPHY2_DSP_TAP :: TAP17_C1 :: LSITEST_SMDSP [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C1,0x1,0)
#define BRPHY2_DSP_TAP_TAP17_C1_LSITEST_SMDSP_MASK                 0x0001
#define BRPHY2_DSP_TAP_TAP17_C1_LSITEST_SMDSP_ALIGN                0
#define BRPHY2_DSP_TAP_TAP17_C1_LSITEST_SMDSP_BITS                 1
#define BRPHY2_DSP_TAP_TAP17_C1_LSITEST_SMDSP_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP17_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP17_C2 :: TRIGGER2_LAT [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x8000,15)
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_LAT_MASK                  0x8000
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_LAT_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_LAT_BITS                  1
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_LAT_SHIFT                 15

/* BRPHY2_DSP_TAP :: TAP17_C2 :: TRIGGER2_INV [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x4000,14)
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_INV_MASK                  0x4000
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_INV_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_INV_BITS                  1
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_INV_SHIFT                 14

/* BRPHY2_DSP_TAP :: TAP17_C2 :: TRIGGER2_SEL [13:08] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x3f00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x3f00,8)
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_SEL_MASK                  0x3f00
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_SEL_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_SEL_BITS                  6
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER2_SEL_SHIFT                 8

/* BRPHY2_DSP_TAP :: TAP17_C2 :: TRIGGER1_LAT [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x80,7)
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_LAT_MASK                  0x0080
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_LAT_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_LAT_BITS                  1
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_LAT_SHIFT                 7

/* BRPHY2_DSP_TAP :: TAP17_C2 :: TRIGGER1_INV [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x40,6)
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_INV_MASK                  0x0040
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_INV_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_INV_BITS                  1
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_INV_SHIFT                 6

/* BRPHY2_DSP_TAP :: TAP17_C2 :: TRIGGER1_SEL [05:00] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x3f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C2,0x3f,0)
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_SEL_MASK                  0x003f
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_SEL_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_SEL_BITS                  6
#define BRPHY2_DSP_TAP_TAP17_C2_TRIGGER1_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP17_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP17_C3 :: LA_REARM_ACQ [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x8000,15)
#define BRPHY2_DSP_TAP_TAP17_C3_LA_REARM_ACQ_MASK                  0x8000
#define BRPHY2_DSP_TAP_TAP17_C3_LA_REARM_ACQ_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C3_LA_REARM_ACQ_BITS                  1
#define BRPHY2_DSP_TAP_TAP17_C3_LA_REARM_ACQ_SHIFT                 15

/* BRPHY2_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_DELAY_EN [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x4000,14)
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_MASK           0x4000
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_ALIGN          0
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_BITS           1
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_SHIFT          14

/* BRPHY2_DSP_TAP :: TAP17_C3 :: LA_POSTSTORE [13:06] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x3fc0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x3fc0,6)
#define BRPHY2_DSP_TAP_TAP17_C3_LA_POSTSTORE_MASK                  0x3fc0
#define BRPHY2_DSP_TAP_TAP17_C3_LA_POSTSTORE_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C3_LA_POSTSTORE_BITS                  8
#define BRPHY2_DSP_TAP_TAP17_C3_LA_POSTSTORE_SHIFT                 6

/* BRPHY2_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_TYPE [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x20,5)
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_MASK               0x0020
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_BITS               1
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_SHIFT              5

/* BRPHY2_DSP_TAP :: TAP17_C3 :: SPARE [04:04] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C3_SPARE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C3_SPARE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x10,4)
#define BRPHY2_DSP_TAP_TAP17_C3_SPARE_MASK                         0x0010
#define BRPHY2_DSP_TAP_TAP17_C3_SPARE_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP17_C3_SPARE_BITS                         1
#define BRPHY2_DSP_TAP_TAP17_C3_SPARE_SHIFT                        4

/* BRPHY2_DSP_TAP :: TAP17_C3 :: LA_CLKENABLE [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x8,3)
#define BRPHY2_DSP_TAP_TAP17_C3_LA_CLKENABLE_MASK                  0x0008
#define BRPHY2_DSP_TAP_TAP17_C3_LA_CLKENABLE_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP17_C3_LA_CLKENABLE_BITS                  1
#define BRPHY2_DSP_TAP_TAP17_C3_LA_CLKENABLE_SHIFT                 3

/* BRPHY2_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_INV [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x4,2)
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_MASK                0x0004
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_ALIGN               0
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_BITS                1
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_SHIFT               2

/* BRPHY2_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_GATE [01:00] */
#define Wr_BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x3,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP17_C3,0x3,0)
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_MASK               0x0003
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_BITS               2
#define BRPHY2_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_SHIFT              0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP18_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP18_C0 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_TAP18_C0_RESERVED0_MASK                     0xff00
#define BRPHY2_DSP_TAP_TAP18_C0_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP18_C0_RESERVED0_BITS                     8
#define BRPHY2_DSP_TAP_TAP18_C0_RESERVED0_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP18_C0 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY2_DSP_TAP_TAP18_C0_PEAK_NOISE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP18_C0,0xff,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP18_C0_PEAK_NOISE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP18_C0,0xff,0)
#define BRPHY2_DSP_TAP_TAP18_C0_PEAK_NOISE_MASK                    0x00ff
#define BRPHY2_DSP_TAP_TAP18_C0_PEAK_NOISE_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP18_C0_PEAK_NOISE_BITS                    8
#define BRPHY2_DSP_TAP_TAP18_C0_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP18_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP18_C1 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_TAP18_C1_RESERVED0_MASK                     0xff00
#define BRPHY2_DSP_TAP_TAP18_C1_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP18_C1_RESERVED0_BITS                     8
#define BRPHY2_DSP_TAP_TAP18_C1_RESERVED0_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP18_C1 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY2_DSP_TAP_TAP18_C1_PEAK_NOISE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP18_C1,0xff,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP18_C1_PEAK_NOISE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP18_C1,0xff,0)
#define BRPHY2_DSP_TAP_TAP18_C1_PEAK_NOISE_MASK                    0x00ff
#define BRPHY2_DSP_TAP_TAP18_C1_PEAK_NOISE_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP18_C1_PEAK_NOISE_BITS                    8
#define BRPHY2_DSP_TAP_TAP18_C1_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP18_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP18_C2 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_TAP18_C2_RESERVED0_MASK                     0xff00
#define BRPHY2_DSP_TAP_TAP18_C2_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP18_C2_RESERVED0_BITS                     8
#define BRPHY2_DSP_TAP_TAP18_C2_RESERVED0_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP18_C2 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY2_DSP_TAP_TAP18_C2_PEAK_NOISE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP18_C2,0xff,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP18_C2_PEAK_NOISE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP18_C2,0xff,0)
#define BRPHY2_DSP_TAP_TAP18_C2_PEAK_NOISE_MASK                    0x00ff
#define BRPHY2_DSP_TAP_TAP18_C2_PEAK_NOISE_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP18_C2_PEAK_NOISE_BITS                    8
#define BRPHY2_DSP_TAP_TAP18_C2_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP18_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP18_C3 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_TAP18_C3_RESERVED0_MASK                     0xff00
#define BRPHY2_DSP_TAP_TAP18_C3_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP18_C3_RESERVED0_BITS                     8
#define BRPHY2_DSP_TAP_TAP18_C3_RESERVED0_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP18_C3 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY2_DSP_TAP_TAP18_C3_PEAK_NOISE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP18_C3,0xff,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP18_C3_PEAK_NOISE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP18_C3,0xff,0)
#define BRPHY2_DSP_TAP_TAP18_C3_PEAK_NOISE_MASK                    0x00ff
#define BRPHY2_DSP_TAP_TAP18_C3_PEAK_NOISE_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP18_C3_PEAK_NOISE_BITS                    8
#define BRPHY2_DSP_TAP_TAP18_C3_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP20
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP20 :: reserved0 [15:14] */
#define BRPHY2_DSP_TAP_TAP20_RESERVED0_MASK                        0xc000
#define BRPHY2_DSP_TAP_TAP20_RESERVED0_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP20_RESERVED0_BITS                        2
#define BRPHY2_DSP_TAP_TAP20_RESERVED0_SHIFT                       14

/* BRPHY2_DSP_TAP :: TAP20 :: ENC_FIR_PATH_DELAY_ADJ [13:11] */
#define Wr_BRPHY2_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP20,0x3800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP20,0x3800,11)
#define BRPHY2_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_MASK           0x3800
#define BRPHY2_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY2_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_BITS           3
#define BRPHY2_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_SHIFT          11

/* BRPHY2_DSP_TAP :: TAP20 :: ENC_LMS_PATH_DELAY_ADJ [10:08] */
#define Wr_BRPHY2_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP20,0x700,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP20,0x700,8)
#define BRPHY2_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_MASK           0x0700
#define BRPHY2_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY2_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_BITS           3
#define BRPHY2_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_SHIFT          8

/* BRPHY2_DSP_TAP :: TAP20 :: ECHO_LMS_GAIN [07:06] */
#define Wr_BRPHY2_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP20,0xc0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP20,0xc0,6)
#define BRPHY2_DSP_TAP_TAP20_ECHO_LMS_GAIN_MASK                    0x00c0
#define BRPHY2_DSP_TAP_TAP20_ECHO_LMS_GAIN_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP20_ECHO_LMS_GAIN_BITS                    2
#define BRPHY2_DSP_TAP_TAP20_ECHO_LMS_GAIN_SHIFT                   6

/* BRPHY2_DSP_TAP :: TAP20 :: reserved1 [05:04] */
#define BRPHY2_DSP_TAP_TAP20_RESERVED1_MASK                        0x0030
#define BRPHY2_DSP_TAP_TAP20_RESERVED1_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP20_RESERVED1_BITS                        2
#define BRPHY2_DSP_TAP_TAP20_RESERVED1_SHIFT                       4

/* BRPHY2_DSP_TAP :: TAP20 :: TXDIG_PATH_DELAY_CTL [03:00] */
#define Wr_BRPHY2_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP20,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP20,0xf,0)
#define BRPHY2_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_MASK             0x000f
#define BRPHY2_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_ALIGN            0
#define BRPHY2_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_BITS             4
#define BRPHY2_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_SHIFT            0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP21
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP21 :: reserved0 [15:13] */
#define BRPHY2_DSP_TAP_TAP21_RESERVED0_MASK                        0xe000
#define BRPHY2_DSP_TAP_TAP21_RESERVED0_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP21_RESERVED0_BITS                        3
#define BRPHY2_DSP_TAP_TAP21_RESERVED0_SHIFT                       13

/* BRPHY2_DSP_TAP :: TAP21 :: PAUSEPCTPM_ABCD [12:09] */
#define Wr_BRPHY2_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP21,0x1e00,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP21,0x1e00,9)
#define BRPHY2_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_MASK                  0x1e00
#define BRPHY2_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_BITS                  4
#define BRPHY2_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_SHIFT                 9

/* BRPHY2_DSP_TAP :: TAP21 :: TX_EN_MON [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP21_TX_EN_MON(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP21,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP21_TX_EN_MON(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP21,0x100,8)
#define BRPHY2_DSP_TAP_TAP21_TX_EN_MON_MASK                        0x0100
#define BRPHY2_DSP_TAP_TAP21_TX_EN_MON_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP21_TX_EN_MON_BITS                        1
#define BRPHY2_DSP_TAP_TAP21_TX_EN_MON_SHIFT                       8

/* BRPHY2_DSP_TAP :: TAP21 :: LINK_CTL_1000T_MON [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP21,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP21,0x80,7)
#define BRPHY2_DSP_TAP_TAP21_LINK_CTL_1000T_MON_MASK               0x0080
#define BRPHY2_DSP_TAP_TAP21_LINK_CTL_1000T_MON_ALIGN              0
#define BRPHY2_DSP_TAP_TAP21_LINK_CTL_1000T_MON_BITS               1
#define BRPHY2_DSP_TAP_TAP21_LINK_CTL_1000T_MON_SHIFT              7

/* BRPHY2_DSP_TAP :: TAP21 :: REM_RCVR_STATUS_MON [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP21,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP21,0x40,6)
#define BRPHY2_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_MASK              0x0040
#define BRPHY2_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_ALIGN             0
#define BRPHY2_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_BITS              1
#define BRPHY2_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_SHIFT             6

/* BRPHY2_DSP_TAP :: TAP21 :: ALIGN_OK_MON [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP21_ALIGN_OK_MON(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP21,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP21_ALIGN_OK_MON(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP21,0x20,5)
#define BRPHY2_DSP_TAP_TAP21_ALIGN_OK_MON_MASK                     0x0020
#define BRPHY2_DSP_TAP_TAP21_ALIGN_OK_MON_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP21_ALIGN_OK_MON_BITS                     1
#define BRPHY2_DSP_TAP_TAP21_ALIGN_OK_MON_SHIFT                    5

/* BRPHY2_DSP_TAP :: TAP21 :: MAIN_PHYC_STATE [04:00] */
#define Wr_BRPHY2_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP21,0x1f,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP21,0x1f,0)
#define BRPHY2_DSP_TAP_TAP21_MAIN_PHYC_STATE_MASK                  0x001f
#define BRPHY2_DSP_TAP_TAP21_MAIN_PHYC_STATE_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP21_MAIN_PHYC_STATE_BITS                  5
#define BRPHY2_DSP_TAP_TAP21_MAIN_PHYC_STATE_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP22
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP22 :: KRDONE [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP22_KRDONE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP22,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP22_KRDONE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP22,0x8000,15)
#define BRPHY2_DSP_TAP_TAP22_KRDONE_MASK                           0x8000
#define BRPHY2_DSP_TAP_TAP22_KRDONE_ALIGN                          0
#define BRPHY2_DSP_TAP_TAP22_KRDONE_BITS                           1
#define BRPHY2_DSP_TAP_TAP22_KRDONE_SHIFT                          15

/* BRPHY2_DSP_TAP :: TAP22 :: MAXWAIT_TIMER_DONE [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP22,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP22,0x4000,14)
#define BRPHY2_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_MASK               0x4000
#define BRPHY2_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_BITS               1
#define BRPHY2_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_SHIFT              14

/* BRPHY2_DSP_TAP :: TAP22 :: LINK_MONITOR_STATE_MON [13:12] */
#define Wr_BRPHY2_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP22,0x3000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP22,0x3000,12)
#define BRPHY2_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_MASK           0x3000
#define BRPHY2_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_ALIGN          0
#define BRPHY2_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_BITS           2
#define BRPHY2_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_SHIFT          12

/* BRPHY2_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_D [11:09] */
#define Wr_BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP22,0xe00,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP22,0xe00,9)
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_D_MASK                  0x0e00
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_D_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_D_BITS                  3
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_D_SHIFT                 9

/* BRPHY2_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_C [08:06] */
#define Wr_BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP22,0x1c0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP22,0x1c0,6)
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_C_MASK                  0x01c0
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_C_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_C_BITS                  3
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_C_SHIFT                 6

/* BRPHY2_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_B [05:03] */
#define Wr_BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP22,0x38,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP22,0x38,3)
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_B_MASK                  0x0038
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_B_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_B_BITS                  3
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_B_SHIFT                 3

/* BRPHY2_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_A [02:00] */
#define Wr_BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP22,0x7,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP22,0x7,0)
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_A_MASK                  0x0007
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_A_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_A_BITS                  3
#define BRPHY2_DSP_TAP_TAP22_PHYC_SUBSTATE_A_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP23
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP23 :: reserved0 [15:13] */
#define BRPHY2_DSP_TAP_TAP23_RESERVED0_MASK                        0xe000
#define BRPHY2_DSP_TAP_TAP23_RESERVED0_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP23_RESERVED0_BITS                        3
#define BRPHY2_DSP_TAP_TAP23_RESERVED0_SHIFT                       13

/* BRPHY2_DSP_TAP :: TAP23 :: ALIGN_REDO_MON [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP23_ALIGN_REDO_MON(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP23,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP23_ALIGN_REDO_MON(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP23,0x1000,12)
#define BRPHY2_DSP_TAP_TAP23_ALIGN_REDO_MON_MASK                   0x1000
#define BRPHY2_DSP_TAP_TAP23_ALIGN_REDO_MON_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP23_ALIGN_REDO_MON_BITS                   1
#define BRPHY2_DSP_TAP_TAP23_ALIGN_REDO_MON_SHIFT                  12

/* BRPHY2_DSP_TAP :: TAP23 :: MSEOK2_MON [11:08] */
#define Wr_BRPHY2_DSP_TAP_TAP23_MSEOK2_MON(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP23,0xf00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP23_MSEOK2_MON(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP23,0xf00,8)
#define BRPHY2_DSP_TAP_TAP23_MSEOK2_MON_MASK                       0x0f00
#define BRPHY2_DSP_TAP_TAP23_MSEOK2_MON_ALIGN                      0
#define BRPHY2_DSP_TAP_TAP23_MSEOK2_MON_BITS                       4
#define BRPHY2_DSP_TAP_TAP23_MSEOK2_MON_SHIFT                      8

/* BRPHY2_DSP_TAP :: TAP23 :: MSEOK1_MON [07:04] */
#define Wr_BRPHY2_DSP_TAP_TAP23_MSEOK1_MON(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP23,0xf0,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP23_MSEOK1_MON(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP23,0xf0,4)
#define BRPHY2_DSP_TAP_TAP23_MSEOK1_MON_MASK                       0x00f0
#define BRPHY2_DSP_TAP_TAP23_MSEOK1_MON_ALIGN                      0
#define BRPHY2_DSP_TAP_TAP23_MSEOK1_MON_BITS                       4
#define BRPHY2_DSP_TAP_TAP23_MSEOK1_MON_SHIFT                      4

/* BRPHY2_DSP_TAP :: TAP23 :: ENERGY_DETECT [03:00] */
#define Wr_BRPHY2_DSP_TAP_TAP23_ENERGY_DETECT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP23,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP23_ENERGY_DETECT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP23,0xf,0)
#define BRPHY2_DSP_TAP_TAP23_ENERGY_DETECT_MASK                    0x000f
#define BRPHY2_DSP_TAP_TAP23_ENERGY_DETECT_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP23_ENERGY_DETECT_BITS                    4
#define BRPHY2_DSP_TAP_TAP23_ENERGY_DETECT_SHIFT                   0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP24
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP24 :: PHYC_OUTPUT_OV [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x8000,15)
#define BRPHY2_DSP_TAP_TAP24_PHYC_OUTPUT_OV_MASK                   0x8000
#define BRPHY2_DSP_TAP_TAP24_PHYC_OUTPUT_OV_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP24_PHYC_OUTPUT_OV_BITS                   1
#define BRPHY2_DSP_TAP_TAP24_PHYC_OUTPUT_OV_SHIFT                  15

/* BRPHY2_DSP_TAP :: TAP24 :: STABLE_RECENTER_EN [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x4000,14)
#define BRPHY2_DSP_TAP_TAP24_STABLE_RECENTER_EN_MASK               0x4000
#define BRPHY2_DSP_TAP_TAP24_STABLE_RECENTER_EN_ALIGN              0
#define BRPHY2_DSP_TAP_TAP24_STABLE_RECENTER_EN_BITS               1
#define BRPHY2_DSP_TAP_TAP24_STABLE_RECENTER_EN_SHIFT              14

/* BRPHY2_DSP_TAP :: TAP24 :: PHYC_MSE_FIX [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP24_PHYC_MSE_FIX(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_PHYC_MSE_FIX(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x2000,13)
#define BRPHY2_DSP_TAP_TAP24_PHYC_MSE_FIX_MASK                     0x2000
#define BRPHY2_DSP_TAP_TAP24_PHYC_MSE_FIX_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP24_PHYC_MSE_FIX_BITS                     1
#define BRPHY2_DSP_TAP_TAP24_PHYC_MSE_FIX_SHIFT                    13

/* BRPHY2_DSP_TAP :: TAP24 :: DEGATEDFEPC_ABCD_OV [12:09] */
#define Wr_BRPHY2_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x1e00,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x1e00,9)
#define BRPHY2_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_MASK              0x1e00
#define BRPHY2_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_ALIGN             0
#define BRPHY2_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_BITS              4
#define BRPHY2_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_SHIFT             9

/* BRPHY2_DSP_TAP :: TAP24 :: NBRSTWTCH_OV [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP24_NBRSTWTCH_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_NBRSTWTCH_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x100,8)
#define BRPHY2_DSP_TAP_TAP24_NBRSTWTCH_OV_MASK                     0x0100
#define BRPHY2_DSP_TAP_TAP24_NBRSTWTCH_OV_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP24_NBRSTWTCH_OV_BITS                     1
#define BRPHY2_DSP_TAP_TAP24_NBRSTWTCH_OV_SHIFT                    8

/* BRPHY2_DSP_TAP :: TAP24 :: RC_LPBKFIFO_T_OV [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x80,7)
#define BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_MASK                 0x0080
#define BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_ALIGN                0
#define BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_BITS                 1
#define BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_SHIFT                7

/* BRPHY2_DSP_TAP :: TAP24 :: RC_LPBKFIFO_N_OV [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x40,6)
#define BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_MASK                 0x0040
#define BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_ALIGN                0
#define BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_BITS                 1
#define BRPHY2_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_SHIFT                6

/* BRPHY2_DSP_TAP :: TAP24 :: PCS_RESET_OV [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP24_PCS_RESET_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_PCS_RESET_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x20,5)
#define BRPHY2_DSP_TAP_TAP24_PCS_RESET_OV_MASK                     0x0020
#define BRPHY2_DSP_TAP_TAP24_PCS_RESET_OV_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP24_PCS_RESET_OV_BITS                     1
#define BRPHY2_DSP_TAP_TAP24_PCS_RESET_OV_SHIFT                    5

/* BRPHY2_DSP_TAP :: TAP24 :: PHYC_PCS_RSTATE_OV [04:03] */
#define Wr_BRPHY2_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x18,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x18,3)
#define BRPHY2_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_MASK               0x0018
#define BRPHY2_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_ALIGN              0
#define BRPHY2_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_BITS               2
#define BRPHY2_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_SHIFT              3

/* BRPHY2_DSP_TAP :: TAP24 :: LOC_RCVR_STATUS_OV [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x4,2)
#define BRPHY2_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_MASK               0x0004
#define BRPHY2_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_ALIGN              0
#define BRPHY2_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_BITS               1
#define BRPHY2_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_SHIFT              2

/* BRPHY2_DSP_TAP :: TAP24 :: PHYC_TXMODE_OV [01:00] */
#define Wr_BRPHY2_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP24,0x3,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP24,0x3,0)
#define BRPHY2_DSP_TAP_TAP24_PHYC_TXMODE_OV_MASK                   0x0003
#define BRPHY2_DSP_TAP_TAP24_PHYC_TXMODE_OV_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP24_PHYC_TXMODE_OV_BITS                   2
#define BRPHY2_DSP_TAP_TAP24_PHYC_TXMODE_OV_SHIFT                  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP25
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP25 :: reserved0 [15:15] */
#define BRPHY2_DSP_TAP_TAP25_RESERVED0_MASK                        0x8000
#define BRPHY2_DSP_TAP_TAP25_RESERVED0_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP25_RESERVED0_BITS                        1
#define BRPHY2_DSP_TAP_TAP25_RESERVED0_SHIFT                       15

/* BRPHY2_DSP_TAP :: TAP25 :: KRDONE_OV [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP25_KRDONE_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP25,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP25_KRDONE_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP25,0x4000,14)
#define BRPHY2_DSP_TAP_TAP25_KRDONE_OV_MASK                        0x4000
#define BRPHY2_DSP_TAP_TAP25_KRDONE_OV_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP25_KRDONE_OV_BITS                        1
#define BRPHY2_DSP_TAP_TAP25_KRDONE_OV_SHIFT                       14

/* BRPHY2_DSP_TAP :: TAP25 :: ALIGN_REDO_OV [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP25_ALIGN_REDO_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP25,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP25_ALIGN_REDO_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP25,0x2000,13)
#define BRPHY2_DSP_TAP_TAP25_ALIGN_REDO_OV_MASK                    0x2000
#define BRPHY2_DSP_TAP_TAP25_ALIGN_REDO_OV_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP25_ALIGN_REDO_OV_BITS                    1
#define BRPHY2_DSP_TAP_TAP25_ALIGN_REDO_OV_SHIFT                   13

/* BRPHY2_DSP_TAP :: TAP25 :: RC_ADCFIFO_N_OV [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP25,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP25,0x1000,12)
#define BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_MASK                  0x1000
#define BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_BITS                  1
#define BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_SHIFT                 12

/* BRPHY2_DSP_TAP :: TAP25 :: RC_ADCFIFO_T_OV [11:08] */
#define Wr_BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP25,0xf00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP25,0xf00,8)
#define BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_MASK                  0x0f00
#define BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_BITS                  4
#define BRPHY2_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_SHIFT                 8

/* BRPHY2_DSP_TAP :: TAP25 :: reserved1 [07:00] */
#define BRPHY2_DSP_TAP_TAP25_RESERVED1_MASK                        0x00ff
#define BRPHY2_DSP_TAP_TAP25_RESERVED1_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP25_RESERVED1_BITS                        8
#define BRPHY2_DSP_TAP_TAP25_RESERVED1_SHIFT                       0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP26
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP26 :: MSE_INPUT_OV [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP26_MSE_INPUT_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP26,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP26_MSE_INPUT_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP26,0x8000,15)
#define BRPHY2_DSP_TAP_TAP26_MSE_INPUT_OV_MASK                     0x8000
#define BRPHY2_DSP_TAP_TAP26_MSE_INPUT_OV_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP26_MSE_INPUT_OV_BITS                     1
#define BRPHY2_DSP_TAP_TAP26_MSE_INPUT_OV_SHIFT                    15

/* BRPHY2_DSP_TAP :: TAP26 :: MSEOK2_OV [14:11] */
#define Wr_BRPHY2_DSP_TAP_TAP26_MSEOK2_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP26,0x7800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP26_MSEOK2_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP26,0x7800,11)
#define BRPHY2_DSP_TAP_TAP26_MSEOK2_OV_MASK                        0x7800
#define BRPHY2_DSP_TAP_TAP26_MSEOK2_OV_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP26_MSEOK2_OV_BITS                        4
#define BRPHY2_DSP_TAP_TAP26_MSEOK2_OV_SHIFT                       11

/* BRPHY2_DSP_TAP :: TAP26 :: MSEOK1_OV [10:07] */
#define Wr_BRPHY2_DSP_TAP_TAP26_MSEOK1_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP26,0x780,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP26_MSEOK1_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP26,0x780,7)
#define BRPHY2_DSP_TAP_TAP26_MSEOK1_OV_MASK                        0x0780
#define BRPHY2_DSP_TAP_TAP26_MSEOK1_OV_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP26_MSEOK1_OV_BITS                        4
#define BRPHY2_DSP_TAP_TAP26_MSEOK1_OV_SHIFT                       7

/* BRPHY2_DSP_TAP :: TAP26 :: ENERGY_DETECT_OV [06:03] */
#define Wr_BRPHY2_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP26,0x78,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP26,0x78,3)
#define BRPHY2_DSP_TAP_TAP26_ENERGY_DETECT_OV_MASK                 0x0078
#define BRPHY2_DSP_TAP_TAP26_ENERGY_DETECT_OV_ALIGN                0
#define BRPHY2_DSP_TAP_TAP26_ENERGY_DETECT_OV_BITS                 4
#define BRPHY2_DSP_TAP_TAP26_ENERGY_DETECT_OV_SHIFT                3

/* BRPHY2_DSP_TAP :: TAP26 :: PCS_INPUT_OV [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP26_PCS_INPUT_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP26,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP26_PCS_INPUT_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP26,0x4,2)
#define BRPHY2_DSP_TAP_TAP26_PCS_INPUT_OV_MASK                     0x0004
#define BRPHY2_DSP_TAP_TAP26_PCS_INPUT_OV_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP26_PCS_INPUT_OV_BITS                     1
#define BRPHY2_DSP_TAP_TAP26_PCS_INPUT_OV_SHIFT                    2

/* BRPHY2_DSP_TAP :: TAP26 :: REM_RCVR_STATUS_OV [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP26,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP26,0x2,1)
#define BRPHY2_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_MASK               0x0002
#define BRPHY2_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_ALIGN              0
#define BRPHY2_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_BITS               1
#define BRPHY2_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_SHIFT              1

/* BRPHY2_DSP_TAP :: TAP26 :: ALIGN_OK_OV [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP26_ALIGN_OK_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP26,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP26_ALIGN_OK_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP26,0x1,0)
#define BRPHY2_DSP_TAP_TAP26_ALIGN_OK_OV_MASK                      0x0001
#define BRPHY2_DSP_TAP_TAP26_ALIGN_OK_OV_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP26_ALIGN_OK_OV_BITS                      1
#define BRPHY2_DSP_TAP_TAP26_ALIGN_OK_OV_SHIFT                     0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP27
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP27 :: reserved0 [15:09] */
#define BRPHY2_DSP_TAP_TAP27_RESERVED0_MASK                        0xfe00
#define BRPHY2_DSP_TAP_TAP27_RESERVED0_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP27_RESERVED0_BITS                        7
#define BRPHY2_DSP_TAP_TAP27_RESERVED0_SHIFT                       9

/* BRPHY2_DSP_TAP :: TAP27 :: FILTER_CTL_PAUSE_OV [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP27,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP27,0x100,8)
#define BRPHY2_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_MASK              0x0100
#define BRPHY2_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_ALIGN             0
#define BRPHY2_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_BITS              1
#define BRPHY2_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_SHIFT             8

/* BRPHY2_DSP_TAP :: TAP27 :: PAUSEPCTPM_ABCD_OV [07:04] */
#define Wr_BRPHY2_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP27,0xf0,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP27,0xf0,4)
#define BRPHY2_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_MASK               0x00f0
#define BRPHY2_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_ALIGN              0
#define BRPHY2_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_BITS               4
#define BRPHY2_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_SHIFT              4

/* BRPHY2_DSP_TAP :: TAP27 :: AUTONEG_INPUT_OV [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP27,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP27,0x8,3)
#define BRPHY2_DSP_TAP_TAP27_AUTONEG_INPUT_OV_MASK                 0x0008
#define BRPHY2_DSP_TAP_TAP27_AUTONEG_INPUT_OV_ALIGN                0
#define BRPHY2_DSP_TAP_TAP27_AUTONEG_INPUT_OV_BITS                 1
#define BRPHY2_DSP_TAP_TAP27_AUTONEG_INPUT_OV_SHIFT                3

/* BRPHY2_DSP_TAP :: TAP27 :: LINK_SCAN_100TX_OV [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP27,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP27,0x4,2)
#define BRPHY2_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_MASK               0x0004
#define BRPHY2_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_ALIGN              0
#define BRPHY2_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_BITS               1
#define BRPHY2_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_SHIFT              2

/* BRPHY2_DSP_TAP :: TAP27 :: LINK_ENAB_100TX_OV [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP27,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP27,0x2,1)
#define BRPHY2_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_MASK               0x0002
#define BRPHY2_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_ALIGN              0
#define BRPHY2_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_BITS               1
#define BRPHY2_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_SHIFT              1

/* BRPHY2_DSP_TAP :: TAP27 :: LINK_CTL_1000T_OV [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP27,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP27,0x1,0)
#define BRPHY2_DSP_TAP_TAP27_LINK_CTL_1000T_OV_MASK                0x0001
#define BRPHY2_DSP_TAP_TAP27_LINK_CTL_1000T_OV_ALIGN               0
#define BRPHY2_DSP_TAP_TAP27_LINK_CTL_1000T_OV_BITS                1
#define BRPHY2_DSP_TAP_TAP27_LINK_CTL_1000T_OV_SHIFT               0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP28
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP28 :: reserved0 [15:04] */
#define BRPHY2_DSP_TAP_TAP28_RESERVED0_MASK                        0xfff0
#define BRPHY2_DSP_TAP_TAP28_RESERVED0_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP28_RESERVED0_BITS                        12
#define BRPHY2_DSP_TAP_TAP28_RESERVED0_SHIFT                       4

/* BRPHY2_DSP_TAP :: TAP28 :: PLLPRAMP_ABCD_OV [03:00] */
#define Wr_BRPHY2_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP28,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP28,0xf,0)
#define BRPHY2_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_MASK                 0x000f
#define BRPHY2_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_ALIGN                0
#define BRPHY2_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_BITS                 4
#define BRPHY2_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP29
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP29 :: TIMER_MODE_D_FORCE [15:14] */
#define Wr_BRPHY2_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP29,0xc000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP29,0xc000,14)
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_MASK               0xc000
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_BITS               2
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_SHIFT              14

/* BRPHY2_DSP_TAP :: TAP29 :: TIMER_MODE_C_FORCE [13:12] */
#define Wr_BRPHY2_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP29,0x3000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP29,0x3000,12)
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_MASK               0x3000
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_BITS               2
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_SHIFT              12

/* BRPHY2_DSP_TAP :: TAP29 :: TIMER_MODE_B_FORCE [11:10] */
#define Wr_BRPHY2_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP29,0xc00,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP29,0xc00,10)
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_MASK               0x0c00
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_BITS               2
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_SHIFT              10

/* BRPHY2_DSP_TAP :: TAP29 :: TIMER_MODE_A_FORCE [09:08] */
#define Wr_BRPHY2_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP29,0x300,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP29,0x300,8)
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_MASK               0x0300
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_BITS               2
#define BRPHY2_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_SHIFT              8

/* BRPHY2_DSP_TAP :: TAP29 :: MAINSTATE_FORCE [07:04] */
#define Wr_BRPHY2_DSP_TAP_TAP29_MAINSTATE_FORCE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP29,0xf0,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP29_MAINSTATE_FORCE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP29,0xf0,4)
#define BRPHY2_DSP_TAP_TAP29_MAINSTATE_FORCE_MASK                  0x00f0
#define BRPHY2_DSP_TAP_TAP29_MAINSTATE_FORCE_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP29_MAINSTATE_FORCE_BITS                  4
#define BRPHY2_DSP_TAP_TAP29_MAINSTATE_FORCE_SHIFT                 4

/* BRPHY2_DSP_TAP :: TAP29 :: FORCE_PHYC_STATE [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP29,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP29,0x8,3)
#define BRPHY2_DSP_TAP_TAP29_FORCE_PHYC_STATE_MASK                 0x0008
#define BRPHY2_DSP_TAP_TAP29_FORCE_PHYC_STATE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP29_FORCE_PHYC_STATE_BITS                 1
#define BRPHY2_DSP_TAP_TAP29_FORCE_PHYC_STATE_SHIFT                3

/* BRPHY2_DSP_TAP :: TAP29 :: HOLD_IN_ALT [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP29_HOLD_IN_ALT(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP29,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP29_HOLD_IN_ALT(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP29,0x4,2)
#define BRPHY2_DSP_TAP_TAP29_HOLD_IN_ALT_MASK                      0x0004
#define BRPHY2_DSP_TAP_TAP29_HOLD_IN_ALT_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP29_HOLD_IN_ALT_BITS                      1
#define BRPHY2_DSP_TAP_TAP29_HOLD_IN_ALT_SHIFT                     2

/* BRPHY2_DSP_TAP :: TAP29 :: FORCE_ALT_STATE_PATH [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP29,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP29,0x2,1)
#define BRPHY2_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_MASK             0x0002
#define BRPHY2_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_ALIGN            0
#define BRPHY2_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_BITS             1
#define BRPHY2_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_SHIFT            1

/* BRPHY2_DSP_TAP :: TAP29 :: PHYC_FAST_STATE_MODE [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP29,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP29,0x1,0)
#define BRPHY2_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_MASK             0x0001
#define BRPHY2_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_ALIGN            0
#define BRPHY2_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_BITS             1
#define BRPHY2_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_SHIFT            0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP30
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP30 :: reserved0 [15:12] */
#define BRPHY2_DSP_TAP_TAP30_RESERVED0_MASK                        0xf000
#define BRPHY2_DSP_TAP_TAP30_RESERVED0_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP30_RESERVED0_BITS                        4
#define BRPHY2_DSP_TAP_TAP30_RESERVED0_SHIFT                       12

/* BRPHY2_DSP_TAP :: TAP30 :: SUBSTATE_D_FORCE [11:09] */
#define Wr_BRPHY2_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP30,0xe00,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP30,0xe00,9)
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_D_FORCE_MASK                 0x0e00
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_D_FORCE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_D_FORCE_BITS                 3
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_D_FORCE_SHIFT                9

/* BRPHY2_DSP_TAP :: TAP30 :: SUBSTATE_C_FORCE [08:06] */
#define Wr_BRPHY2_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP30,0x1c0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP30,0x1c0,6)
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_C_FORCE_MASK                 0x01c0
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_C_FORCE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_C_FORCE_BITS                 3
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_C_FORCE_SHIFT                6

/* BRPHY2_DSP_TAP :: TAP30 :: SUBSTATE_B_FORCE [05:03] */
#define Wr_BRPHY2_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP30,0x38,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP30,0x38,3)
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_B_FORCE_MASK                 0x0038
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_B_FORCE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_B_FORCE_BITS                 3
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_B_FORCE_SHIFT                3

/* BRPHY2_DSP_TAP :: TAP30 :: SUBSTATE_A_FORCE [02:00] */
#define Wr_BRPHY2_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP30,0x7,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP30,0x7,0)
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_A_FORCE_MASK                 0x0007
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_A_FORCE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_A_FORCE_BITS                 3
#define BRPHY2_DSP_TAP_TAP30_SUBSTATE_A_FORCE_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP31_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP31_C0 :: SDSEL_OV [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x8000,15)
#define BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_MASK                      0x8000
#define BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_ALIGN                     0
#define BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_BITS                      1
#define BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_SHIFT                     15

/* BRPHY2_DSP_TAP :: TAP31_C0 :: SDSEL_OV_EN [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x4000,14)
#define BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_EN_MASK                   0x4000
#define BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_EN_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_EN_BITS                   1
#define BRPHY2_DSP_TAP_TAP31_C0_SDSEL_OV_EN_SHIFT                  14

/* BRPHY2_DSP_TAP :: TAP31_C0 :: ADC_BER_TPOUT_EN [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x2000,13)
#define BRPHY2_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_MASK              0x2000
#define BRPHY2_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_ALIGN             0
#define BRPHY2_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_BITS              1
#define BRPHY2_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_SHIFT             13

/* BRPHY2_DSP_TAP :: TAP31_C0 :: SWAPCD_OV [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP31_C0_SWAPCD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP31_C0_SWAPCD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x1000,12)
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPCD_OV_MASK                     0x1000
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPCD_OV_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPCD_OV_BITS                     1
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPCD_OV_SHIFT                    12

/* BRPHY2_DSP_TAP :: TAP31_C0 :: SWAPAB_OV [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x800,11)
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_OV_MASK                     0x0800
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_OV_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_OV_BITS                     1
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_OV_SHIFT                    11

/* BRPHY2_DSP_TAP :: TAP31_C0 :: SWAPAB_CD_OV_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP31_C0,0x400,10)
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_MASK               0x0400
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_ALIGN              0
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_BITS               1
#define BRPHY2_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_SHIFT              10

/* BRPHY2_DSP_TAP :: TAP31_C0 :: reserved0 [09:00] */
#define BRPHY2_DSP_TAP_TAP31_C0_RESERVED0_MASK                     0x03ff
#define BRPHY2_DSP_TAP_TAP31_C0_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP31_C0_RESERVED0_BITS                     10
#define BRPHY2_DSP_TAP_TAP31_C0_RESERVED0_SHIFT                    0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP32_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP32_C0 :: reserved0 [15:09] */
#define BRPHY2_DSP_TAP_TAP32_C0_RESERVED0_MASK                     0xfe00
#define BRPHY2_DSP_TAP_TAP32_C0_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP32_C0_RESERVED0_BITS                     7
#define BRPHY2_DSP_TAP_TAP32_C0_RESERVED0_SHIFT                    9

/* BRPHY2_DSP_TAP :: TAP32_C0 :: COEFF_RAM_TM_CTRL [08:04] */
#define Wr_BRPHY2_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x1f0,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x1f0,4)
#define BRPHY2_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_MASK             0x01f0
#define BRPHY2_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_ALIGN            0
#define BRPHY2_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_BITS             5
#define BRPHY2_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_SHIFT            4

/* BRPHY2_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_D [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x8,3)
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_MASK         0x0008
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_ALIGN        0
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_BITS         1
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_SHIFT        3

/* BRPHY2_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_C [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x4,2)
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_MASK         0x0004
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_ALIGN        0
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_BITS         1
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_SHIFT        2

/* BRPHY2_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_AB [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x2,1)
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_MASK        0x0002
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_ALIGN       0
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_BITS        1
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_SHIFT       1

/* BRPHY2_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_A [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP32_C0,0x1,0)
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_MASK         0x0001
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_ALIGN        0
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_BITS         1
#define BRPHY2_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_SHIFT        0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FDFE_OV_RD
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_MSB [15:14] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0xc000,14,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0xc000,14)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_MASK             0xc000
#define BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_ALIGN            0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_BITS             2
#define BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_SHIFT            14

/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_LSB [13:13] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x2000,13)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_MASK             0x2000
#define BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_ALIGN            0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_BITS             1
#define BRPHY2_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_SHIFT            13

/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: BETA_OV [12:12] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x1000,12)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_MASK                     0x1000
#define BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_ALIGN                    0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_BITS                     1
#define BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_SHIFT                    12

/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: BETA_OV_VAL [11:09] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0xe00,9,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0xe00,9)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_MASK                 0x0e00
#define BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_ALIGN                0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_BITS                 3
#define BRPHY2_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_SHIFT                9

/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: FDFE_MSE_SEL_OV [08:08] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x100,8)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_MASK             0x0100
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_ALIGN            0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_BITS             1
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_SHIFT            8

/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: FDFE_CLEAR_OV [07:07] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x80,7)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_MASK               0x0080
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_ALIGN              0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_BITS               1
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_SHIFT              7

/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: FDFE_OUTEN_OV [06:06] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x40,6)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_MASK               0x0040
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_ALIGN              0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_BITS               1
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_SHIFT              6

/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: FDFE_UPEN_OV [05:05] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x20,5)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_MASK                0x0020
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_ALIGN               0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_BITS                1
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_SHIFT               5

/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: FDFE_OV_EN [04:04] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0x10,4)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_MASK                  0x0010
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_ALIGN                 0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_BITS                  1
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_SHIFT                 4

/* BRPHY2_DSP_TAP :: FDFE_OV_RD :: FDFE_RD_SEL [03:00] */
#define Wr_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_OV_RD,0xf,0)
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_MASK                 0x000f
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_ALIGN                0
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_BITS                 4
#define BRPHY2_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FDFE_COEFF
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FDFE_COEFF :: FDFE_COEFF [15:00] */
#define Wr_BRPHY2_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) WriteReg16(BRPHY2_DSP_TAP_FDFE_COEFF,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) ReadReg16(BRPHY2_DSP_TAP_FDFE_COEFF)
#define BRPHY2_DSP_TAP_FDFE_COEFF_FDFE_COEFF_MASK                  0xffff
#define BRPHY2_DSP_TAP_FDFE_COEFF_FDFE_COEFF_ALIGN                 0
#define BRPHY2_DSP_TAP_FDFE_COEFF_FDFE_COEFF_BITS                  16
#define BRPHY2_DSP_TAP_FDFE_COEFF_FDFE_COEFF_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FDFE_BETA_THRESHOLD
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_3 [15:12] */
#define Wr_BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12)
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_MASK   0xf000
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_ALIGN  0
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_BITS   4
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_SHIFT  12

/* BRPHY2_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_2 [11:08] */
#define Wr_BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8)
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_MASK   0x0f00
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_ALIGN  0
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_BITS   4
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_SHIFT  8

/* BRPHY2_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_1 [07:04] */
#define Wr_BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4)
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_MASK   0x00f0
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_ALIGN  0
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_BITS   4
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_SHIFT  4

/* BRPHY2_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_0 [03:00] */
#define Wr_BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) WriteRegBits16(BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) ReadRegBits16(BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0)
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_MASK   0x000f
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_ALIGN  0
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_BITS   4
#define BRPHY2_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_SHIFT  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP33_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SD_EN [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x8000,15)
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_MASK               0x8000
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_ALIGN              0
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_BITS               1
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_SHIFT              15

/* BRPHY2_DSP_TAP :: TAP33_C0 :: EEE_MASK_MSE_EN [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x4000,14)
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_MASK               0x4000
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_ALIGN              0
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_BITS               1
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_SHIFT              14

/* BRPHY2_DSP_TAP :: TAP33_C0 :: EEE_PHYC_STATUS_TO_LED [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x2000,13)
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_MASK        0x2000
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_ALIGN       0
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_BITS        1
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_SHIFT       13

/* BRPHY2_DSP_TAP :: TAP33_C0 :: EEE_PLL_TEST_MODE [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x1000,12)
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_MASK             0x1000
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_ALIGN            0
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_BITS             1
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_SHIFT            12

/* BRPHY2_DSP_TAP :: TAP33_C0 :: SPARE11 [11:11] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_SPARE11(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_SPARE11(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x800,11)
#define BRPHY2_DSP_TAP_TAP33_C0_SPARE11_MASK                       0x0800
#define BRPHY2_DSP_TAP_TAP33_C0_SPARE11_ALIGN                      0
#define BRPHY2_DSP_TAP_TAP33_C0_SPARE11_BITS                       1
#define BRPHY2_DSP_TAP_TAP33_C0_SPARE11_SHIFT                      11

/* BRPHY2_DSP_TAP :: TAP33_C0 :: EEE_AFE_STOPPABLE [10:10] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x400,10)
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_MASK             0x0400
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_ALIGN            0
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_BITS             1
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_SHIFT            10

/* BRPHY2_DSP_TAP :: TAP33_C0 :: EEE_CLOCK_STOPPABLE [09:09] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x200,9)
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_MASK           0x0200
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_ALIGN          0
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_BITS           1
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_SHIFT          9

/* BRPHY2_DSP_TAP :: TAP33_C0 :: EEE_SD_SEL [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x100,8)
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_SD_SEL_MASK                    0x0100
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_SD_SEL_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_SD_SEL_BITS                    1
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_SD_SEL_SHIFT                   8

/* BRPHY2_DSP_TAP :: TAP33_C0 :: MAXMSEOK1_CHG_EN [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x80,7)
#define BRPHY2_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_MASK              0x0080
#define BRPHY2_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_ALIGN             0
#define BRPHY2_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_BITS              1
#define BRPHY2_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_SHIFT             7

/* BRPHY2_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SCALE [06:05] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x60,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x60,5)
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_MASK               0x0060
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_BITS               2
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_SHIFT              5

/* BRPHY2_DSP_TAP :: TAP33_C0 :: LPI_TRACK_MODE [04:03] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x18,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x18,3)
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_MASK                0x0018
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_ALIGN               0
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_BITS                2
#define BRPHY2_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_SHIFT               3

/* BRPHY2_DSP_TAP :: TAP33_C0 :: EEE_FREQ_UNLOCK [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x4,2)
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_MASK               0x0004
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_ALIGN              0
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_BITS               1
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_SHIFT              2

/* BRPHY2_DSP_TAP :: TAP33_C0 :: EEE_QUICK_ALIGN [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x2,1)
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_MASK               0x0002
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_ALIGN              0
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_BITS               1
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_SHIFT              1

/* BRPHY2_DSP_TAP :: TAP33_C0 :: EEE_SD300 [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C0_EEE_SD300(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C0_EEE_SD300(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C0,0x1,0)
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_SD300_MASK                     0x0001
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_SD300_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_SD300_BITS                     1
#define BRPHY2_DSP_TAP_TAP33_C0_EEE_SD300_SHIFT                    0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP33_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP33_C1 :: SD_ASSERT_THD [15:08] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C1,0xff00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C1,0xff00,8)
#define BRPHY2_DSP_TAP_TAP33_C1_SD_ASSERT_THD_MASK                 0xff00
#define BRPHY2_DSP_TAP_TAP33_C1_SD_ASSERT_THD_ALIGN                0
#define BRPHY2_DSP_TAP_TAP33_C1_SD_ASSERT_THD_BITS                 8
#define BRPHY2_DSP_TAP_TAP33_C1_SD_ASSERT_THD_SHIFT                8

/* BRPHY2_DSP_TAP :: TAP33_C1 :: SD_DEASSERT_THD [07:00] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C1,0xff,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C1,0xff,0)
#define BRPHY2_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_MASK               0x00ff
#define BRPHY2_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_ALIGN              0
#define BRPHY2_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_BITS               8
#define BRPHY2_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_SHIFT              0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP33_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP33_C2 :: EEE_PHASE_REACQ_TUNE [15:14] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0xc000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0xc000,14)
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_MASK          0xc000
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_ALIGN         0
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_BITS          2
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_SHIFT         14

/* BRPHY2_DSP_TAP :: TAP33_C2 :: EEE_WAIT_SCR_LOCK_N [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0x2000,13)
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_MASK           0x2000
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_ALIGN          0
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_BITS           1
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_SHIFT          13

/* BRPHY2_DSP_TAP :: TAP33_C2 :: LOC_RCVR_WAIT_ALIGNC_N [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0x1000,12)
#define BRPHY2_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_MASK        0x1000
#define BRPHY2_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_ALIGN       0
#define BRPHY2_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_BITS        1
#define BRPHY2_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_SHIFT       12

/* BRPHY2_DSP_TAP :: TAP33_C2 :: EEE_WAKEMZ_TUNE [11:08] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0xf00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0xf00,8)
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_MASK               0x0f00
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_BITS               4
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_SHIFT              8

/* BRPHY2_DSP_TAP :: TAP33_C2 :: EEE_RX_ON_TUNE [07:04] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0xf0,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0xf0,4)
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_MASK                0x00f0
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_ALIGN               0
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_BITS                4
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_SHIFT               4

/* BRPHY2_DSP_TAP :: TAP33_C2 :: EEE_SLAVE_WAIT_TUNE [03:00] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C2,0xf,0)
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_MASK           0x000f
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_ALIGN          0
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_BITS           4
#define BRPHY2_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_SHIFT          0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP33_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP33_C3 :: spare_reg [15:02] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C3_spare_reg(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C3,0xfffc,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C3_spare_reg(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C3,0xfffc,2)
#define BRPHY2_DSP_TAP_TAP33_C3_SPARE_REG_MASK                     0xfffc
#define BRPHY2_DSP_TAP_TAP33_C3_SPARE_REG_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP33_C3_SPARE_REG_BITS                     14
#define BRPHY2_DSP_TAP_TAP33_C3_SPARE_REG_SHIFT                    2

/* BRPHY2_DSP_TAP :: TAP33_C3 :: PWRDNTX_STAGGER_EN [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C3,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C3,0x2,1)
#define BRPHY2_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_MASK            0x0002
#define BRPHY2_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_ALIGN           0
#define BRPHY2_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_BITS            1
#define BRPHY2_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_SHIFT           1

/* BRPHY2_DSP_TAP :: TAP33_C3 :: PWRDNRX_STAGGER_EN [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP33_C3,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP33_C3,0x1,0)
#define BRPHY2_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_MASK            0x0001
#define BRPHY2_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_ALIGN           0
#define BRPHY2_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_BITS            1
#define BRPHY2_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_SHIFT           0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP34_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP34_C0 :: EEE_PLLILPFRZ [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x8000,15)
#define BRPHY2_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_MASK                 0x8000
#define BRPHY2_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_ALIGN                0
#define BRPHY2_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_BITS                 1
#define BRPHY2_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_SHIFT                15

/* BRPHY2_DSP_TAP :: TAP34_C0 :: PLLILPFRZ_OV [14:14] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x4000,14)
#define BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_MASK                  0x4000
#define BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_BITS                  1
#define BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_SHIFT                 14

/* BRPHY2_DSP_TAP :: TAP34_C0 :: PLLILPFRZ [13:13] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x2000,13)
#define BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_MASK                     0x2000
#define BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_BITS                     1
#define BRPHY2_DSP_TAP_TAP34_C0_PLLILPFRZ_SHIFT                    13

/* BRPHY2_DSP_TAP :: TAP34_C0 :: EEE_100TX_UP16_SEL [12:12] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x1000,12)
#define BRPHY2_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_MASK            0x1000
#define BRPHY2_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_ALIGN           0
#define BRPHY2_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_BITS            1
#define BRPHY2_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_SHIFT           12

/* BRPHY2_DSP_TAP :: TAP34_C0 :: PLLFRST_SCALE [11:10] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0xc00,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0xc00,10)
#define BRPHY2_DSP_TAP_TAP34_C0_PLLFRST_SCALE_MASK                 0x0c00
#define BRPHY2_DSP_TAP_TAP34_C0_PLLFRST_SCALE_ALIGN                0
#define BRPHY2_DSP_TAP_TAP34_C0_PLLFRST_SCALE_BITS                 2
#define BRPHY2_DSP_TAP_TAP34_C0_PLLFRST_SCALE_SHIFT                10

/* BRPHY2_DSP_TAP :: TAP34_C0 :: INT_LP_GAIN [09:08] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x300,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x300,8)
#define BRPHY2_DSP_TAP_TAP34_C0_INT_LP_GAIN_MASK                   0x0300
#define BRPHY2_DSP_TAP_TAP34_C0_INT_LP_GAIN_ALIGN                  0
#define BRPHY2_DSP_TAP_TAP34_C0_INT_LP_GAIN_BITS                   2
#define BRPHY2_DSP_TAP_TAP34_C0_INT_LP_GAIN_SHIFT                  8

/* BRPHY2_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_EST_AVERAGE_SEL [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x80,7)
#define BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_MASK    0x0080
#define BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_ALIGN   0
#define BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_BITS    1
#define BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_SHIFT   7

/* BRPHY2_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_SCALE [06:04] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x70,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x70,4)
#define BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_MASK              0x0070
#define BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_ALIGN             0
#define BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_BITS              3
#define BRPHY2_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_SHIFT             4

/* BRPHY2_DSP_TAP :: TAP34_C0 :: KI [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_KI(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_KI(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x8,3)
#define BRPHY2_DSP_TAP_TAP34_C0_KI_MASK                            0x0008
#define BRPHY2_DSP_TAP_TAP34_C0_KI_ALIGN                           0
#define BRPHY2_DSP_TAP_TAP34_C0_KI_BITS                            1
#define BRPHY2_DSP_TAP_TAP34_C0_KI_SHIFT                           3

/* BRPHY2_DSP_TAP :: TAP34_C0 :: KP [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_KP(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_KP(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x4,2)
#define BRPHY2_DSP_TAP_TAP34_C0_KP_MASK                            0x0004
#define BRPHY2_DSP_TAP_TAP34_C0_KP_ALIGN                           0
#define BRPHY2_DSP_TAP_TAP34_C0_KP_BITS                            1
#define BRPHY2_DSP_TAP_TAP34_C0_KP_SHIFT                           2

/* BRPHY2_DSP_TAP :: TAP34_C0 :: KV [01:00] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C0_KV(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x3,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C0_KV(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C0,0x3,0)
#define BRPHY2_DSP_TAP_TAP34_C0_KV_MASK                            0x0003
#define BRPHY2_DSP_TAP_TAP34_C0_KV_ALIGN                           0
#define BRPHY2_DSP_TAP_TAP34_C0_KV_BITS                            2
#define BRPHY2_DSP_TAP_TAP34_C0_KV_SHIFT                           0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP34_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP34_C1 :: SPARE [15:12] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C1_SPARE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C1,0xf000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C1_SPARE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C1,0xf000,12)
#define BRPHY2_DSP_TAP_TAP34_C1_SPARE_MASK                         0xf000
#define BRPHY2_DSP_TAP_TAP34_C1_SPARE_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP34_C1_SPARE_BITS                         4
#define BRPHY2_DSP_TAP_TAP34_C1_SPARE_SHIFT                        12

/* BRPHY2_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_10 [11:08] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C1,0xf00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C1,0xf00,8)
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_MASK             0x0f00
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_ALIGN            0
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_BITS             4
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_SHIFT            8

/* BRPHY2_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_01 [07:04] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C1,0xf0,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C1,0xf0,4)
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_MASK             0x00f0
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_ALIGN            0
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_BITS             4
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_SHIFT            4

/* BRPHY2_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_00 [03:00] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C1,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C1,0xf,0)
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_MASK             0x000f
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_ALIGN            0
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_BITS             4
#define BRPHY2_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_SHIFT            0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP34_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_CH_SEL [15:14] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0xc000,14,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0xc000,14)
#define BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_MASK           0xc000
#define BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_ALIGN          0
#define BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_BITS           2
#define BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_SHIFT          14

/* BRPHY2_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_BUS_SEL [13:11] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0x3800,11,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0x3800,11)
#define BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_MASK          0x3800
#define BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_ALIGN         0
#define BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_BITS          3
#define BRPHY2_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_SHIFT         11

/* BRPHY2_DSP_TAP :: TAP34_C2 :: reserved0 [10:09] */
#define BRPHY2_DSP_TAP_TAP34_C2_RESERVED0_MASK                     0x0600
#define BRPHY2_DSP_TAP_TAP34_C2_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP34_C2_RESERVED0_BITS                     2
#define BRPHY2_DSP_TAP_TAP34_C2_RESERVED0_SHIFT                    9

/* BRPHY2_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_10 [08:06] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0x1c0,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0x1c0,6)
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_MASK               0x01c0
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_ALIGN              0
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_BITS               3
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_SHIFT              6

/* BRPHY2_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_01 [05:03] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0x38,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0x38,3)
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_MASK               0x0038
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_ALIGN              0
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_BITS               3
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_SHIFT              3

/* BRPHY2_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_00 [02:00] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0x7,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP34_C2,0x7,0)
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_MASK               0x0007
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_ALIGN              0
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_BITS               3
#define BRPHY2_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_SHIFT              0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP34_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP34_C3 :: PHASECTL_TPO [15:00] */
#define Wr_BRPHY2_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) WriteReg16(BRPHY2_DSP_TAP_TAP34_C3,x)
#define Rd_BRPHY2_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) ReadReg16(BRPHY2_DSP_TAP_TAP34_C3)
#define BRPHY2_DSP_TAP_TAP34_C3_PHASECTL_TPO_MASK                  0xffff
#define BRPHY2_DSP_TAP_TAP34_C3_PHASECTL_TPO_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP34_C3_PHASECTL_TPO_BITS                  16
#define BRPHY2_DSP_TAP_TAP34_C3_PHASECTL_TPO_SHIFT                 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP35_C0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP35_C0 :: LPI_RX_TW3_TIMER [15:13] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0xe000,13,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0xe000,13)
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_MASK              0xe000
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_ALIGN             0
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_BITS              3
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_SHIFT             13

/* BRPHY2_DSP_TAP :: TAP35_C0 :: LPI_RX_TW2_TIMER [12:10] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0x1c00,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0x1c00,10)
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_MASK              0x1c00
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_ALIGN             0
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_BITS              3
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_SHIFT             10

/* BRPHY2_DSP_TAP :: TAP35_C0 :: LPI_RX_TW1_TIMER [09:07] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0x380,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0x380,7)
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_MASK              0x0380
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_ALIGN             0
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_BITS              3
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_SHIFT             7

/* BRPHY2_DSP_TAP :: TAP35_C0 :: LPI_TX_TQ_TIMER [06:04] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0x70,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0x70,4)
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_MASK               0x0070
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_ALIGN              0
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_BITS               3
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_SHIFT              4

/* BRPHY2_DSP_TAP :: TAP35_C0 :: LPI_TX_TS_TIMER [03:02] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0xc,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0xc,2)
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_MASK               0x000c
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_ALIGN              0
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_BITS               2
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_SHIFT              2

/* BRPHY2_DSP_TAP :: TAP35_C0 :: LPI_TX_TR_TIMER [01:00] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0x3,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C0,0x3,0)
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_MASK               0x0003
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_ALIGN              0
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_BITS               2
#define BRPHY2_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_SHIFT              0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP35_C1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP35_C1 :: LPI_RX_TS3_TIMER [15:10] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C1,0xfc00,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C1,0xfc00,10)
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_MASK              0xfc00
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_ALIGN             0
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_BITS              6
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_SHIFT             10

/* BRPHY2_DSP_TAP :: TAP35_C1 :: LPI_RX_TS2_TIMER [09:04] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C1,0x3f0,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C1,0x3f0,4)
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_MASK              0x03f0
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_ALIGN             0
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_BITS              6
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_SHIFT             4

/* BRPHY2_DSP_TAP :: TAP35_C1 :: LPI_RX_TS1_TIMER [03:00] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C1,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C1,0xf,0)
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_MASK              0x000f
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_ALIGN             0
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_BITS              4
#define BRPHY2_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_SHIFT             0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP35_C2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP35_C2 :: reserved0 [15:14] */
#define BRPHY2_DSP_TAP_TAP35_C2_RESERVED0_MASK                     0xc000
#define BRPHY2_DSP_TAP_TAP35_C2_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP35_C2_RESERVED0_BITS                     2
#define BRPHY2_DSP_TAP_TAP35_C2_RESERVED0_SHIFT                    14

/* BRPHY2_DSP_TAP :: TAP35_C2 :: SPARE [13:10] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C2_SPARE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x3c00,10,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C2_SPARE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x3c00,10)
#define BRPHY2_DSP_TAP_TAP35_C2_SPARE_MASK                         0x3c00
#define BRPHY2_DSP_TAP_TAP35_C2_SPARE_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP35_C2_SPARE_BITS                         4
#define BRPHY2_DSP_TAP_TAP35_C2_SPARE_SHIFT                        10

/* BRPHY2_DSP_TAP :: TAP35_C2 :: LPI_TX_BRCM_MODE [09:09] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x200,9)
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_MASK              0x0200
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_ALIGN             0
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_BITS              1
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_SHIFT             9

/* BRPHY2_DSP_TAP :: TAP35_C2 :: LPI_RX_TI_TIMER [08:08] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x100,8)
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_MASK               0x0100
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_ALIGN              0
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_BITS               1
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_SHIFT              8

/* BRPHY2_DSP_TAP :: TAP35_C2 :: GPCS_ERRTH_SEL [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x80,7)
#define BRPHY2_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_MASK                0x0080
#define BRPHY2_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_ALIGN               0
#define BRPHY2_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_BITS                1
#define BRPHY2_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_SHIFT               7

/* BRPHY2_DSP_TAP :: TAP35_C2 :: PCS_LPI_TEST_CTL [06:04] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x70,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x70,4)
#define BRPHY2_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_MASK              0x0070
#define BRPHY2_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_ALIGN             0
#define BRPHY2_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_BITS              3
#define BRPHY2_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_SHIFT             4

/* BRPHY2_DSP_TAP :: TAP35_C2 :: reserved1 [03:03] */
#define BRPHY2_DSP_TAP_TAP35_C2_RESERVED1_MASK                     0x0008
#define BRPHY2_DSP_TAP_TAP35_C2_RESERVED1_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP35_C2_RESERVED1_BITS                     1
#define BRPHY2_DSP_TAP_TAP35_C2_RESERVED1_SHIFT                    3

/* BRPHY2_DSP_TAP :: TAP35_C2 :: LPI_RX_SQCNTR [02:00] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x7,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C2,0x7,0)
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_MASK                 0x0007
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_ALIGN                0
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_BITS                 3
#define BRPHY2_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: TAP35_C3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: TAP35_C3 :: UNASSIGNED [15:15] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_UNASSIGNED(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_UNASSIGNED(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x8000,15)
#define BRPHY2_DSP_TAP_TAP35_C3_UNASSIGNED_MASK                    0x8000
#define BRPHY2_DSP_TAP_TAP35_C3_UNASSIGNED_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP35_C3_UNASSIGNED_BITS                    1
#define BRPHY2_DSP_TAP_TAP35_C3_UNASSIGNED_SHIFT                   15

/* BRPHY2_DSP_TAP :: TAP35_C3 :: LPI_100TX_STATE [14:12] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x7000,12,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x7000,12)
#define BRPHY2_DSP_TAP_TAP35_C3_LPI_100TX_STATE_MASK               0x7000
#define BRPHY2_DSP_TAP_TAP35_C3_LPI_100TX_STATE_ALIGN              0
#define BRPHY2_DSP_TAP_TAP35_C3_LPI_100TX_STATE_BITS               3
#define BRPHY2_DSP_TAP_TAP35_C3_LPI_100TX_STATE_SHIFT              12

/* BRPHY2_DSP_TAP :: TAP35_C3 :: RXSM_STATE [11:08] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_RXSM_STATE(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0xf00,8,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_RXSM_STATE(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0xf00,8)
#define BRPHY2_DSP_TAP_TAP35_C3_RXSM_STATE_MASK                    0x0f00
#define BRPHY2_DSP_TAP_TAP35_C3_RXSM_STATE_ALIGN                   0
#define BRPHY2_DSP_TAP_TAP35_C3_RXSM_STATE_BITS                    4
#define BRPHY2_DSP_TAP_TAP35_C3_RXSM_STATE_SHIFT                   8

/* BRPHY2_DSP_TAP :: TAP35_C3 :: SEED_INV_CTL [07:07] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x80,7)
#define BRPHY2_DSP_TAP_TAP35_C3_SEED_INV_CTL_MASK                  0x0080
#define BRPHY2_DSP_TAP_TAP35_C3_SEED_INV_CTL_ALIGN                 0
#define BRPHY2_DSP_TAP_TAP35_C3_SEED_INV_CTL_BITS                  1
#define BRPHY2_DSP_TAP_TAP35_C3_SEED_INV_CTL_SHIFT                 7

/* BRPHY2_DSP_TAP :: TAP35_C3 :: LOAD_N [06:06] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_LOAD_N(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_LOAD_N(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x40,6)
#define BRPHY2_DSP_TAP_TAP35_C3_LOAD_N_MASK                        0x0040
#define BRPHY2_DSP_TAP_TAP35_C3_LOAD_N_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP35_C3_LOAD_N_BITS                        1
#define BRPHY2_DSP_TAP_TAP35_C3_LOAD_N_SHIFT                       6

/* BRPHY2_DSP_TAP :: TAP35_C3 :: DET_IDLES [05:05] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_DET_IDLES(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_DET_IDLES(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x20,5)
#define BRPHY2_DSP_TAP_TAP35_C3_DET_IDLES_MASK                     0x0020
#define BRPHY2_DSP_TAP_TAP35_C3_DET_IDLES_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP35_C3_DET_IDLES_BITS                     1
#define BRPHY2_DSP_TAP_TAP35_C3_DET_IDLES_SHIFT                    5

/* BRPHY2_DSP_TAP :: TAP35_C3 :: DET_SLEEP [04:04] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_DET_SLEEP(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_DET_SLEEP(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x10,4)
#define BRPHY2_DSP_TAP_TAP35_C3_DET_SLEEP_MASK                     0x0010
#define BRPHY2_DSP_TAP_TAP35_C3_DET_SLEEP_ALIGN                    0
#define BRPHY2_DSP_TAP_TAP35_C3_DET_SLEEP_BITS                     1
#define BRPHY2_DSP_TAP_TAP35_C3_DET_SLEEP_SHIFT                    4

/* BRPHY2_DSP_TAP :: TAP35_C3 :: FUBAR [03:03] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_FUBAR(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_FUBAR(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x8,3)
#define BRPHY2_DSP_TAP_TAP35_C3_FUBAR_MASK                         0x0008
#define BRPHY2_DSP_TAP_TAP35_C3_FUBAR_ALIGN                        0
#define BRPHY2_DSP_TAP_TAP35_C3_FUBAR_BITS                         1
#define BRPHY2_DSP_TAP_TAP35_C3_FUBAR_SHIFT                        3

/* BRPHY2_DSP_TAP :: TAP35_C3 :: SR_NRZI [02:02] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_SR_NRZI(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_SR_NRZI(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x4,2)
#define BRPHY2_DSP_TAP_TAP35_C3_SR_NRZI_MASK                       0x0004
#define BRPHY2_DSP_TAP_TAP35_C3_SR_NRZI_ALIGN                      0
#define BRPHY2_DSP_TAP_TAP35_C3_SR_NRZI_BITS                       1
#define BRPHY2_DSP_TAP_TAP35_C3_SR_NRZI_SHIFT                      2

/* BRPHY2_DSP_TAP :: TAP35_C3 :: R_USCR [01:01] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_R_USCR(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_R_USCR(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x2,1)
#define BRPHY2_DSP_TAP_TAP35_C3_R_USCR_MASK                        0x0002
#define BRPHY2_DSP_TAP_TAP35_C3_R_USCR_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP35_C3_R_USCR_BITS                        1
#define BRPHY2_DSP_TAP_TAP35_C3_R_USCR_SHIFT                       1

/* BRPHY2_DSP_TAP :: TAP35_C3 :: LOCKED [00:00] */
#define Wr_BRPHY2_DSP_TAP_TAP35_C3_LOCKED(x) WriteRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_TAP35_C3_LOCKED(x) ReadRegBits16(BRPHY2_DSP_TAP_TAP35_C3,0x1,0)
#define BRPHY2_DSP_TAP_TAP35_C3_LOCKED_MASK                        0x0001
#define BRPHY2_DSP_TAP_TAP35_C3_LOCKED_ALIGN                       0
#define BRPHY2_DSP_TAP_TAP35_C3_LOCKED_BITS                        1
#define BRPHY2_DSP_TAP_TAP35_C3_LOCKED_SHIFT                       0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_CTL_CH0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x8000,15)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_MASK              0x8000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_SHIFT             15

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: DC_FREEZE [14:14] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x4000,14)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_MASK               0x4000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_ALIGN              0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_BITS               1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_SHIFT              14

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x2000,13)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_MASK             0x2000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_SHIFT            13

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x1000,12)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_MASK            0x1000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_SHIFT           12

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x800,11)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_MASK            0x0800
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_SHIFT           11

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x400,10)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_MASK            0x0400
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_SHIFT           10

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x200,9)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_MASK            0x0200
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_SHIFT           9

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x100,8)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_MASK              0x0100
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_SHIFT             8

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x80,7)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_MASK             0x0080
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_SHIFT            7

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: DC_DISABLE [06:06] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x40,6)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_MASK              0x0040
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_SHIFT             6

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x20,5)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_MASK            0x0020
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_SHIFT           5

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x10,4)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_MASK           0x0010
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_SHIFT          4

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x8,3)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_MASK           0x0008
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_SHIFT          3

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x4,2)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_MASK           0x0004
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_SHIFT          2

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x2,1)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_MASK           0x0002
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_SHIFT          1

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH0 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH0,0x1,0)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_MASK             0x0001
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_CTL_CH1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x8000,15)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_MASK              0x8000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_SHIFT             15

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: DC_FREEZE [14:14] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x4000,14)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_MASK               0x4000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_ALIGN              0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_BITS               1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_SHIFT              14

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x2000,13)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_MASK             0x2000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_SHIFT            13

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x1000,12)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_MASK            0x1000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_SHIFT           12

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x800,11)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_MASK            0x0800
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_SHIFT           11

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x400,10)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_MASK            0x0400
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_SHIFT           10

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x200,9)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_MASK            0x0200
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_SHIFT           9

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x100,8)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_MASK              0x0100
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_SHIFT             8

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x80,7)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_MASK             0x0080
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_SHIFT            7

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: DC_DISABLE [06:06] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x40,6)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_MASK              0x0040
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_SHIFT             6

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x20,5)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_MASK            0x0020
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_SHIFT           5

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x10,4)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_MASK           0x0010
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_SHIFT          4

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x8,3)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_MASK           0x0008
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_SHIFT          3

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x4,2)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_MASK           0x0004
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_SHIFT          2

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x2,1)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_MASK           0x0002
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_SHIFT          1

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH1 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH1,0x1,0)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_MASK             0x0001
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_CTL_CH2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x8000,15)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_MASK              0x8000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_SHIFT             15

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: DC_FREEZE [14:14] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x4000,14)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_MASK               0x4000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_ALIGN              0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_BITS               1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_SHIFT              14

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x2000,13)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_MASK             0x2000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_SHIFT            13

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x1000,12)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_MASK            0x1000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_SHIFT           12

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x800,11)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_MASK            0x0800
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_SHIFT           11

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x400,10)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_MASK            0x0400
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_SHIFT           10

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x200,9)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_MASK            0x0200
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_SHIFT           9

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x100,8)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_MASK              0x0100
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_SHIFT             8

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x80,7)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_MASK             0x0080
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_SHIFT            7

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: DC_DISABLE [06:06] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x40,6)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_MASK              0x0040
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_SHIFT             6

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x20,5)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_MASK            0x0020
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_SHIFT           5

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x10,4)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_MASK           0x0010
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_SHIFT          4

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x8,3)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_MASK           0x0008
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_SHIFT          3

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x4,2)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_MASK           0x0004
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_SHIFT          2

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x2,1)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_MASK           0x0002
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_SHIFT          1

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH2 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH2,0x1,0)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_MASK             0x0001
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_CTL_CH3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x8000,15)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_MASK              0x8000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_SHIFT             15

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: DC_FREEZE [14:14] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x4000,14)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_MASK               0x4000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_ALIGN              0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_BITS               1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_SHIFT              14

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x2000,13)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_MASK             0x2000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_SHIFT            13

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x1000,12)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_MASK            0x1000
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_SHIFT           12

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x800,11)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_MASK            0x0800
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_SHIFT           11

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x400,10)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_MASK            0x0400
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_SHIFT           10

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x200,9)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_MASK            0x0200
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_SHIFT           9

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x100,8)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_MASK              0x0100
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_SHIFT             8

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x80,7)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_MASK             0x0080
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_SHIFT            7

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: DC_DISABLE [06:06] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x40,6)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_MASK              0x0040
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_SHIFT             6

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x20,5)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_MASK            0x0020
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_SHIFT           5

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x10,4)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_MASK           0x0010
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_SHIFT          4

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x8,3)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_MASK           0x0008
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_SHIFT          3

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x4,2)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_MASK           0x0004
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_SHIFT          2

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x2,1)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_MASK           0x0002
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_ALIGN          0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_BITS           1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_SHIFT          1

/* BRPHY2_DSP_TAP :: FILTER_CTL_CH3 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_CH3,0x1,0)
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_MASK             0x0001
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_ALIGN            0
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_BITS             1
#define BRPHY2_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_MASK          0xff00
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_ALIGN         0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_BITS          8
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_SHIFT         8

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_MASK          0xff00
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_ALIGN         0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_BITS          8
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_SHIFT         8

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_MASK          0xff00
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_ALIGN         0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_BITS          8
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_SHIFT         8

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: reserved0 [15:08] */
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_MASK          0xff00
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_ALIGN         0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_BITS          8
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_SHIFT         8

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY2_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0)
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY2_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: reserved0 [15:15] */
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_MASK             0x8000
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_ALIGN            0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_BITS             1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_SHIFT            15

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT01_PRE1_DIS [14:14] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_MASK  0x4000
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_ALIGN 0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_BITS  1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_SHIFT 14

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: PHYC_SKIP_PHASE_ADJ [13:13] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_MASK   0x2000
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_ALIGN  0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_BITS   1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_SHIFT  13

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: LOCAL_TRAIN_DIS [12:12] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_MASK       0x1000
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_ALIGN      0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_BITS       1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_SHIFT      12

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: SLAVE_FDX_LOCAL_TRAIN_EN [11:11] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x800,11)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_MASK 0x0800
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_ALIGN 0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_BITS 1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_SHIFT 11

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: AUTO_LPF_EN [10:10] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x400,10)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_MASK           0x0400
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_ALIGN          0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_BITS           1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_SHIFT          10

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_PROTECT_EN [09:09] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x200,9)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_MASK        0x0200
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_ALIGN       0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_BITS        1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_SHIFT       9

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT1_DIS [08:08] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x100,8)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_MASK        0x0100
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_ALIGN       0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_BITS        1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_SHIFT       8

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_IDLEDATA_UPD_EN [07:04] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_MASK  0x00f0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_ALIGN 0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_BITS  4
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_SHIFT 4

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_EMI_UPD_EN [03:03] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x8,3)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_MASK       0x0008
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_ALIGN      0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_BITS       1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_SHIFT      3

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_VAL [02:02] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x4,2)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_MASK       0x0004
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_ALIGN      0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_BITS       1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_SHIFT      2

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_OV [01:01] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x2,1)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_MASK        0x0002
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_ALIGN       0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_BITS        1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_SHIFT       1

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_DATAPATH_EN [00:00] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL,0x1,0)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_MASK       0x0001
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_ALIGN      0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_BITS       1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_SHIFT      0


/****************************************************************************
 * BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL2
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL2 :: LPFREQ_SEL_STATUS [15:15] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_MASK    0x8000
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_ALIGN   0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_BITS    1
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_SHIFT   15

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL2 :: reserved0 [14:04] */
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_MASK            0x7ff0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_ALIGN           0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_BITS            11
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_SHIFT           4

/* BRPHY2_DSP_TAP :: EMI_DATAPATH_CTL2 :: GAMMA_LPF_THRESHOLD [03:00] */
#define Wr_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) WriteRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0,x)
#define Rd_BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) ReadRegBits16(BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0)
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_MASK  0x000f
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_ALIGN 0
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_BITS  4
#define BRPHY2_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_SHIFT 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FFEX_CTL
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FFEX_CTL :: reserved0 [15:12] */
#define BRPHY2_DSP_TAP_FFEX_CTL_RESERVED0_MASK                     0xf000
#define BRPHY2_DSP_TAP_FFEX_CTL_RESERVED0_ALIGN                    0
#define BRPHY2_DSP_TAP_FFEX_CTL_RESERVED0_BITS                     4
#define BRPHY2_DSP_TAP_FFEX_CTL_RESERVED0_SHIFT                    12

/* BRPHY2_DSP_TAP :: FFEX_CTL :: ENC_SLOW_LMS_CTL [11:10] */
#define Wr_BRPHY2_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) WriteRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0xc00,10,x)
#define Rd_BRPHY2_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) ReadRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0xc00,10)
#define BRPHY2_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_MASK              0x0c00
#define BRPHY2_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_ALIGN             0
#define BRPHY2_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_BITS              2
#define BRPHY2_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_SHIFT             10

/* BRPHY2_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV_VAL [09:09] */
#define Wr_BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x200,9)
#define BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_MASK               0x0200
#define BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_ALIGN              0
#define BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_BITS               1
#define BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_SHIFT              9

/* BRPHY2_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV [08:08] */
#define Wr_BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x100,8)
#define BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_MASK                   0x0100
#define BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_ALIGN                  0
#define BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_BITS                   1
#define BRPHY2_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_SHIFT                  8

/* BRPHY2_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_VAL [07:07] */
#define Wr_BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) WriteRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) ReadRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x80,7)
#define BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_MASK          0x0080
#define BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_ALIGN         0
#define BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_BITS          1
#define BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_SHIFT         7

/* BRPHY2_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_OV [06:06] */
#define Wr_BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) WriteRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) ReadRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x40,6)
#define BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_MASK           0x0040
#define BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_ALIGN          0
#define BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_BITS           1
#define BRPHY2_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_SHIFT          6

/* BRPHY2_DSP_TAP :: FFEX_CTL :: FFEX_MAINTAP [05:03] */
#define Wr_BRPHY2_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) WriteRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x38,3,x)
#define Rd_BRPHY2_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) ReadRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x38,3)
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_MASK                  0x0038
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_ALIGN                 0
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_BITS                  3
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_SHIFT                 3

/* BRPHY2_DSP_TAP :: FFEX_CTL :: FFEX_LMS_MODE [02:01] */
#define Wr_BRPHY2_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) WriteRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x6,1,x)
#define Rd_BRPHY2_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) ReadRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x6,1)
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_MASK                 0x0006
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_ALIGN                0
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_BITS                 2
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_SHIFT                1

/* BRPHY2_DSP_TAP :: FFEX_CTL :: FFEX_EN [00:00] */
#define Wr_BRPHY2_DSP_TAP_FFEX_CTL_FFEX_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_FFEX_CTL_FFEX_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_FFEX_CTL,0x1,0)
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_EN_MASK                       0x0001
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_EN_ALIGN                      0
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_EN_BITS                       1
#define BRPHY2_DSP_TAP_FFEX_CTL_FFEX_EN_SHIFT                      0


/****************************************************************************
 * BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL0
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_STOP [15:15] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_MASK 0x8000
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_BITS 1
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_SHIFT 15

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: reserved0 [14:07] */
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_MASK         0x7f80
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_ALIGN        0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_BITS         8
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_SHIFT        7

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_MAINSTATE [06:02] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_MASK 0x007c
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_BITS 5
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_SHIFT 2

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_CLR [01:01] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_MASK 0x0002
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_BITS 1
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_SHIFT 1

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_EN [00:00] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_MASK 0x0001
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_BITS 1
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_SHIFT 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL1
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D_EN [15:15] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_MASK 0x8000
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_BITS 1
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_SHIFT 15

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D [14:12] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_MASK 0x7000
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_BITS 3
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_SHIFT 12

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C_EN [11:11] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_MASK 0x0800
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_BITS 1
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_SHIFT 11

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C [10:08] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_MASK 0x0700
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_BITS 3
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_SHIFT 8

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B_EN [07:07] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_MASK 0x0080
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_BITS 1
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_SHIFT 7

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B [06:04] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_MASK 0x0070
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_BITS 3
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_SHIFT 4

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A_EN [03:03] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_MASK 0x0008
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_BITS 1
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_SHIFT 3

/* BRPHY2_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A [02:00] */
#define Wr_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) WriteRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0,x)
#define Rd_BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) ReadRegBits16(BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0)
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_MASK 0x0007
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_ALIGN 0
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_BITS 3
#define BRPHY2_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_SHIFT 0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_ADDR
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_ADDR :: CTL_ALL_CH [15:15] */
#define Wr_BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0x8000,15,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0x8000,15)
#define BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_MASK                 0x8000
#define BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_ALIGN                0
#define BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_BITS                 1
#define BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_SHIFT                15

/* BRPHY2_DSP_TAP :: FILTER_ADDR :: CH_SEL [14:13] */
#define Wr_BRPHY2_DSP_TAP_FILTER_ADDR_CH_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0x6000,13,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_ADDR_CH_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0x6000,13)
#define BRPHY2_DSP_TAP_FILTER_ADDR_CH_SEL_MASK                     0x6000
#define BRPHY2_DSP_TAP_FILTER_ADDR_CH_SEL_ALIGN                    0
#define BRPHY2_DSP_TAP_FILTER_ADDR_CH_SEL_BITS                     2
#define BRPHY2_DSP_TAP_FILTER_ADDR_CH_SEL_SHIFT                    13

/* BRPHY2_DSP_TAP :: FILTER_ADDR :: CTL_ALL_FILTERS [12:12] */
#define Wr_BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0x1000,12)
#define BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_MASK            0x1000
#define BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_BITS            1
#define BRPHY2_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_SHIFT           12

/* BRPHY2_DSP_TAP :: FILTER_ADDR :: FILTER_SEL [11:08] */
#define Wr_BRPHY2_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0xf00,8,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0xf00,8)
#define BRPHY2_DSP_TAP_FILTER_ADDR_FILTER_SEL_MASK                 0x0f00
#define BRPHY2_DSP_TAP_FILTER_ADDR_FILTER_SEL_ALIGN                0
#define BRPHY2_DSP_TAP_FILTER_ADDR_FILTER_SEL_BITS                 4
#define BRPHY2_DSP_TAP_FILTER_ADDR_FILTER_SEL_SHIFT                8

/* BRPHY2_DSP_TAP :: FILTER_ADDR :: TAP_NUMBER [07:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0xff,0,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_ADDR,0xff,0)
#define BRPHY2_DSP_TAP_FILTER_ADDR_TAP_NUMBER_MASK                 0x00ff
#define BRPHY2_DSP_TAP_FILTER_ADDR_TAP_NUMBER_ALIGN                0
#define BRPHY2_DSP_TAP_FILTER_ADDR_TAP_NUMBER_BITS                 8
#define BRPHY2_DSP_TAP_FILTER_ADDR_TAP_NUMBER_SHIFT                0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_CTL
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_CTL :: reserved0 [15:13] */
#define BRPHY2_DSP_TAP_FILTER_CTL_RESERVED0_MASK                   0xe000
#define BRPHY2_DSP_TAP_FILTER_CTL_RESERVED0_ALIGN                  0
#define BRPHY2_DSP_TAP_FILTER_CTL_RESERVED0_BITS                   3
#define BRPHY2_DSP_TAP_FILTER_CTL_RESERVED0_SHIFT                  13

/* BRPHY2_DSP_TAP :: FILTER_CTL :: BUSY [12:12] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_BUSY(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x1000,12,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_BUSY(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x1000,12)
#define BRPHY2_DSP_TAP_FILTER_CTL_BUSY_MASK                        0x1000
#define BRPHY2_DSP_TAP_FILTER_CTL_BUSY_ALIGN                       0
#define BRPHY2_DSP_TAP_FILTER_CTL_BUSY_BITS                        1
#define BRPHY2_DSP_TAP_FILTER_CTL_BUSY_SHIFT                       12

/* BRPHY2_DSP_TAP :: FILTER_CTL :: TAP_PREFETCH [11:11] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x800,11,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x800,11)
#define BRPHY2_DSP_TAP_FILTER_CTL_TAP_PREFETCH_MASK                0x0800
#define BRPHY2_DSP_TAP_FILTER_CTL_TAP_PREFETCH_ALIGN               0
#define BRPHY2_DSP_TAP_FILTER_CTL_TAP_PREFETCH_BITS                1
#define BRPHY2_DSP_TAP_FILTER_CTL_TAP_PREFETCH_SHIFT               11

/* BRPHY2_DSP_TAP :: FILTER_CTL :: UPPER_WORD_SEL [10:10] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x400,10,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x400,10)
#define BRPHY2_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_MASK              0x0400
#define BRPHY2_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_SHIFT             10

/* BRPHY2_DSP_TAP :: FILTER_CTL :: WR_COEFF [09:09] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_WR_COEFF(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x200,9,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_WR_COEFF(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x200,9)
#define BRPHY2_DSP_TAP_FILTER_CTL_WR_COEFF_MASK                    0x0200
#define BRPHY2_DSP_TAP_FILTER_CTL_WR_COEFF_ALIGN                   0
#define BRPHY2_DSP_TAP_FILTER_CTL_WR_COEFF_BITS                    1
#define BRPHY2_DSP_TAP_FILTER_CTL_WR_COEFF_SHIFT                   9

/* BRPHY2_DSP_TAP :: FILTER_CTL :: WR_ALL_NEXT_COEF [08:08] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x100,8,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x100,8)
#define BRPHY2_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_MASK            0x0100
#define BRPHY2_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_ALIGN           0
#define BRPHY2_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_BITS            1
#define BRPHY2_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_SHIFT           8

/* BRPHY2_DSP_TAP :: FILTER_CTL :: RD_COEFF [07:07] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_RD_COEFF(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x80,7,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_RD_COEFF(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x80,7)
#define BRPHY2_DSP_TAP_FILTER_CTL_RD_COEFF_MASK                    0x0080
#define BRPHY2_DSP_TAP_FILTER_CTL_RD_COEFF_ALIGN                   0
#define BRPHY2_DSP_TAP_FILTER_CTL_RD_COEFF_BITS                    1
#define BRPHY2_DSP_TAP_FILTER_CTL_RD_COEFF_SHIFT                   7

/* BRPHY2_DSP_TAP :: FILTER_CTL :: INIT_RAM [06:06] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_INIT_RAM(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x40,6,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_INIT_RAM(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x40,6)
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_RAM_MASK                    0x0040
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_RAM_ALIGN                   0
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_RAM_BITS                    1
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_RAM_SHIFT                   6

/* BRPHY2_DSP_TAP :: FILTER_CTL :: INIT_ENC [05:05] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_INIT_ENC(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x20,5,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_INIT_ENC(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x20,5)
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_ENC_MASK                    0x0020
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_ENC_ALIGN                   0
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_ENC_BITS                    1
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_ENC_SHIFT                   5

/* BRPHY2_DSP_TAP :: FILTER_CTL :: INIT_DFE [04:04] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_INIT_DFE(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x10,4,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_INIT_DFE(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x10,4)
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_DFE_MASK                    0x0010
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_DFE_ALIGN                   0
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_DFE_BITS                    1
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_DFE_SHIFT                   4

/* BRPHY2_DSP_TAP :: FILTER_CTL :: INIT_FFEXTAP [03:03] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x8,3,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x8,3)
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_MASK                0x0008
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_ALIGN               0
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_BITS                1
#define BRPHY2_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_SHIFT               3

/* BRPHY2_DSP_TAP :: FILTER_CTL :: DISABLE_FILTER [02:02] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x4,2,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x4,2)
#define BRPHY2_DSP_TAP_FILTER_CTL_DISABLE_FILTER_MASK              0x0004
#define BRPHY2_DSP_TAP_FILTER_CTL_DISABLE_FILTER_ALIGN             0
#define BRPHY2_DSP_TAP_FILTER_CTL_DISABLE_FILTER_BITS              1
#define BRPHY2_DSP_TAP_FILTER_CTL_DISABLE_FILTER_SHIFT             2

/* BRPHY2_DSP_TAP :: FILTER_CTL :: FREEZE_FILTER [01:01] */
#define Wr_BRPHY2_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) WriteRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x2,1,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) ReadRegBits16(BRPHY2_DSP_TAP_FILTER_CTL,0x2,1)
#define BRPHY2_DSP_TAP_FILTER_CTL_FREEZE_FILTER_MASK               0x0002
#define BRPHY2_DSP_TAP_FILTER_CTL_FREEZE_FILTER_ALIGN              0
#define BRPHY2_DSP_TAP_FILTER_CTL_FREEZE_FILTER_BITS               1
#define BRPHY2_DSP_TAP_FILTER_CTL_FREEZE_FILTER_SHIFT              1

/* BRPHY2_DSP_TAP :: FILTER_CTL :: reserved1 [00:00] */
#define BRPHY2_DSP_TAP_FILTER_CTL_RESERVED1_MASK                   0x0001
#define BRPHY2_DSP_TAP_FILTER_CTL_RESERVED1_ALIGN                  0
#define BRPHY2_DSP_TAP_FILTER_CTL_RESERVED1_BITS                   1
#define BRPHY2_DSP_TAP_FILTER_CTL_RESERVED1_SHIFT                  0


/****************************************************************************
 * BRPHY2_DSP_TAP :: FILTER_DATA
 ***************************************************************************/
/* BRPHY2_DSP_TAP :: FILTER_DATA :: TAP_COEFF [15:00] */
#define Wr_BRPHY2_DSP_TAP_FILTER_DATA_TAP_COEFF(x) WriteReg16(BRPHY2_DSP_TAP_FILTER_DATA,x)
#define Rd_BRPHY2_DSP_TAP_FILTER_DATA_TAP_COEFF(x) ReadReg16(BRPHY2_DSP_TAP_FILTER_DATA)
#define BRPHY2_DSP_TAP_FILTER_DATA_TAP_COEFF_MASK                  0xffff
#define BRPHY2_DSP_TAP_FILTER_DATA_TAP_COEFF_ALIGN                 0
#define BRPHY2_DSP_TAP_FILTER_DATA_TAP_COEFF_BITS                  16
#define BRPHY2_DSP_TAP_FILTER_DATA_TAP_COEFF_SHIFT                 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_PLL_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLLCTRL_0
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLLCTRL_0 :: PLL_CTL [15:00] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) WriteReg16(BRPHY2_PLL_CTRL_PLLCTRL_0,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) ReadReg16(BRPHY2_PLL_CTRL_PLLCTRL_0)
#define BRPHY2_PLL_CTRL_PLLCTRL_0_PLL_CTL_MASK                     0xffff
#define BRPHY2_PLL_CTRL_PLLCTRL_0_PLL_CTL_ALIGN                    0
#define BRPHY2_PLL_CTRL_PLLCTRL_0_PLL_CTL_BITS                     16
#define BRPHY2_PLL_CTRL_PLLCTRL_0_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLLCTRL_1
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLLCTRL_1 :: PLL_CTL [15:00] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) WriteReg16(BRPHY2_PLL_CTRL_PLLCTRL_1,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) ReadReg16(BRPHY2_PLL_CTRL_PLLCTRL_1)
#define BRPHY2_PLL_CTRL_PLLCTRL_1_PLL_CTL_MASK                     0xffff
#define BRPHY2_PLL_CTRL_PLLCTRL_1_PLL_CTL_ALIGN                    0
#define BRPHY2_PLL_CTRL_PLLCTRL_1_PLL_CTL_BITS                     16
#define BRPHY2_PLL_CTRL_PLLCTRL_1_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLLCTRL_2
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2 [15:14] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_2,0xc000,14,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_2,0xc000,14)
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_MASK                  0xc000
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_ALIGN                 0
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_BITS                  2
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_SHIFT                 14

/* BRPHY2_PLL_CTRL :: PLLCTRL_2 :: PLL_PDIV [13:10] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_2,0x3c00,10,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_2,0x3c00,10)
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_PDIV_MASK                    0x3c00
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_PDIV_ALIGN                   0
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_PDIV_BITS                    4
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_PDIV_SHIFT                   10

/* BRPHY2_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2_2 [09:00] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_2,0x3ff,0,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_2,0x3ff,0)
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_MASK                0x03ff
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_ALIGN               0
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_BITS                10
#define BRPHY2_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_SHIFT               0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLLCTRL_3
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLLCTRL_3 :: PLL_SPARE3 [15:10] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_3,0xfc00,10,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_3,0xfc00,10)
#define BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_MASK                  0xfc00
#define BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_ALIGN                 0
#define BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_BITS                  6
#define BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_SHIFT                 10

/* BRPHY2_PLL_CTRL :: PLLCTRL_3 :: PLL_NDIV_INT_MS [09:00] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_3,0x3ff,0,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_3,0x3ff,0)
#define BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_MASK             0x03ff
#define BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_ALIGN            0
#define BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_BITS             10
#define BRPHY2_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_SHIFT            0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLLCTRL_4
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4 [15:15] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x8000,15,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x8000,15)
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_MASK                  0x8000
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_ALIGN                 0
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_BITS                  1
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_SHIFT                 15

/* BRPHY2_PLL_CTRL :: PLLCTRL_4 :: SD_SEL_300mV [14:14] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x4000,14,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x4000,14)
#define BRPHY2_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_MASK                0x4000
#define BRPHY2_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_ALIGN               0
#define BRPHY2_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_BITS                1
#define BRPHY2_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_SHIFT               14

/* BRPHY2_PLL_CTRL :: PLLCTRL_4 :: CML_BUF_TUNE [13:12] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x3000,12,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x3000,12)
#define BRPHY2_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_MASK                0x3000
#define BRPHY2_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_ALIGN               0
#define BRPHY2_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_BITS                2
#define BRPHY2_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_SHIFT               12

/* BRPHY2_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_BANDGAP [11:09] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0xe00,9,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0xe00,9)
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_MASK            0x0e00
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_ALIGN           0
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_BITS            3
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_SHIFT           9

/* BRPHY2_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4a [08:06] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x1c0,6,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x1c0,6)
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_MASK                 0x01c0
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_ALIGN                0
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_BITS                 3
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_SHIFT                6

/* BRPHY2_PLL_CTRL :: PLLCTRL_4 :: ATEST_OR_BIAS_TEST_OUTPUT [05:05] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x20,5,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x20,5)
#define BRPHY2_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_MASK   0x0020
#define BRPHY2_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_ALIGN  0
#define BRPHY2_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_BITS   1
#define BRPHY2_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_SHIFT  5

/* BRPHY2_PLL_CTRL :: PLLCTRL_4 :: PLL_MUX_ATEST [04:03] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x18,3,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x18,3)
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_MASK               0x0018
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_ALIGN              0
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_BITS               2
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_SHIFT              3

/* BRPHY2_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_TEST_MUX [02:00] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x7,0,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_4,0x7,0)
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_MASK           0x0007
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_ALIGN          0
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_BITS           3
#define BRPHY2_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_SHIFT          0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLLCTRL_5
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLLCTRL_5 :: PLL_SPARE5 [15:14] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0xc000,14,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0xc000,14)
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_MASK                  0xc000
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_ALIGN                 0
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_BITS                  2
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_SHIFT                 14

/* BRPHY2_PLL_CTRL :: PLLCTRL_5 :: PLL_CP [13:13] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x2000,13,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x2000,13)
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP_MASK                      0x2000
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP_ALIGN                     0
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP_BITS                      1
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP_SHIFT                     13

/* BRPHY2_PLL_CTRL :: PLLCTRL_5 :: PLL_CP1 [12:12] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x1000,12,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x1000,12)
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP1_MASK                     0x1000
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP1_ALIGN                    0
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP1_BITS                     1
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CP1_SHIFT                    12

/* BRPHY2_PLL_CTRL :: PLLCTRL_5 :: PLL_CZ [11:11] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x800,11,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x800,11)
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CZ_MASK                      0x0800
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CZ_ALIGN                     0
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CZ_BITS                      1
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_CZ_SHIFT                     11

/* BRPHY2_PLL_CTRL :: PLLCTRL_5 :: PLL_RZ [10:07] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x780,7,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x780,7)
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_RZ_MASK                      0x0780
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_RZ_ALIGN                     0
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_RZ_BITS                      4
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_RZ_SHIFT                     7

/* BRPHY2_PLL_CTRL :: PLLCTRL_5 :: PLL_ICP [06:03] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x78,3,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x78,3)
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_ICP_MASK                     0x0078
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_ICP_ALIGN                    0
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_ICP_BITS                     4
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_ICP_SHIFT                    3

/* BRPHY2_PLL_CTRL :: PLLCTRL_5 :: PLL_VCO_GAIN [02:00] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x7,0,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_5,0x7,0)
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_MASK                0x0007
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_ALIGN               0
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_BITS                3
#define BRPHY2_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_SHIFT               0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLLCTRL_6
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLLCTRL_6 :: PLL_SPARE6 [15:09] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0xfe00,9,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0xfe00,9)
#define BRPHY2_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_MASK                  0xfe00
#define BRPHY2_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_ALIGN                 0
#define BRPHY2_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_BITS                  7
#define BRPHY2_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_SHIFT                 9

/* BRPHY2_PLL_CTRL :: PLLCTRL_6 :: POR_CONFIG [08:07] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0x180,7,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0x180,7)
#define BRPHY2_PLL_CTRL_PLLCTRL_6_POR_CONFIG_MASK                  0x0180
#define BRPHY2_PLL_CTRL_PLLCTRL_6_POR_CONFIG_ALIGN                 0
#define BRPHY2_PLL_CTRL_PLLCTRL_6_POR_CONFIG_BITS                  2
#define BRPHY2_PLL_CTRL_PLLCTRL_6_POR_CONFIG_SHIFT                 7

/* BRPHY2_PLL_CTRL :: PLLCTRL_6 :: CLK500_EN [06:06] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0x40,6,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0x40,6)
#define BRPHY2_PLL_CTRL_PLLCTRL_6_CLK500_EN_MASK                   0x0040
#define BRPHY2_PLL_CTRL_PLLCTRL_6_CLK500_EN_ALIGN                  0
#define BRPHY2_PLL_CTRL_PLLCTRL_6_CLK500_EN_BITS                   1
#define BRPHY2_PLL_CTRL_PLLCTRL_6_CLK500_EN_SHIFT                  6

/* BRPHY2_PLL_CTRL :: PLLCTRL_6 :: RCAL_OFFSET [05:03] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0x38,3,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0x38,3)
#define BRPHY2_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_MASK                 0x0038
#define BRPHY2_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_ALIGN                0
#define BRPHY2_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_BITS                 3
#define BRPHY2_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_SHIFT                3

/* BRPHY2_PLL_CTRL :: PLLCTRL_6 :: RCCAL_OFFSET [02:00] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0x7,0,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_6,0x7,0)
#define BRPHY2_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_MASK                0x0007
#define BRPHY2_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_ALIGN               0
#define BRPHY2_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_BITS                3
#define BRPHY2_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_SHIFT               0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLL_STATUS_0
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLL_STATUS_0 :: reserved0 [15:12] */
#define BRPHY2_PLL_CTRL_PLL_STATUS_0_RESERVED0_MASK                0xf000
#define BRPHY2_PLL_CTRL_PLL_STATUS_0_RESERVED0_ALIGN               0
#define BRPHY2_PLL_CTRL_PLL_STATUS_0_RESERVED0_BITS                4
#define BRPHY2_PLL_CTRL_PLL_STATUS_0_RESERVED0_SHIFT               12

/* BRPHY2_PLL_CTRL :: PLL_STATUS_0 :: PLL_STATUS_WORD [11:00] */
#define Wr_BRPHY2_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLL_STATUS_0,0xfff,0,x)
#define Rd_BRPHY2_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLL_STATUS_0,0xfff,0)
#define BRPHY2_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_MASK          0x0fff
#define BRPHY2_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_ALIGN         0
#define BRPHY2_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_BITS          12
#define BRPHY2_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_SHIFT         0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLL_STATUS_1
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLL_STATUS_1 :: reserved0 [15:09] */
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_RESERVED0_MASK                0xfe00
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_RESERVED0_ALIGN               0
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_RESERVED0_BITS                7
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_RESERVED0_SHIFT               9

/* BRPHY2_PLL_CTRL :: PLL_STATUS_1 :: PLL_LOCK [08:08] */
#define Wr_BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLL_STATUS_1,0x100,8,x)
#define Rd_BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLL_STATUS_1,0x100,8)
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_MASK                 0x0100
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_ALIGN                0
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_BITS                 1
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_SHIFT                8

/* BRPHY2_PLL_CTRL :: PLL_STATUS_1 :: reserved1 [07:04] */
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_RESERVED1_MASK                0x00f0
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_RESERVED1_ALIGN               0
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_RESERVED1_BITS                4
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_RESERVED1_SHIFT               4

/* BRPHY2_PLL_CTRL :: PLL_STATUS_1 :: PLL_BER [03:00] */
#define Wr_BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLL_STATUS_1,0xf,0,x)
#define Rd_BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLL_STATUS_1,0xf,0)
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_BER_MASK                  0x000f
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_BER_ALIGN                 0
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_BER_BITS                  4
#define BRPHY2_PLL_CTRL_PLL_STATUS_1_PLL_BER_SHIFT                 0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: AFE_SIGDET_STATUS
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: AFE_SIGDET_STATUS :: reserved0 [15:07] */
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_MASK           0xff80
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_ALIGN          0
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_BITS           9
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_SHIFT          7

/* BRPHY2_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_SIGSTATE [06:01] */
#define Wr_BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) WriteRegBits16(BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1,x)
#define Rd_BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) ReadRegBits16(BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1)
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_MASK    0x007e
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_ALIGN   0
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_BITS    6
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_SHIFT   1

/* BRPHY2_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_Select [00:00] */
#define Wr_BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) WriteRegBits16(BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0,x)
#define Rd_BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) ReadRegBits16(BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0)
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_MASK      0x0001
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_ALIGN     0
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_BITS      1
#define BRPHY2_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_SHIFT     0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLLCTRL_7
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLLCTRL_7 :: TVCO_MUX_EN [15:15] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x8000,15,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x8000,15)
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_MASK                 0x8000
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_ALIGN                0
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_BITS                 1
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_SHIFT                15

/* BRPHY2_PLL_CTRL :: PLLCTRL_7 :: TVCO_PAD [14:12] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x7000,12,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x7000,12)
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_PAD_MASK                    0x7000
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_PAD_ALIGN                   0
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_PAD_BITS                    3
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TVCO_PAD_SHIFT                   12

/* BRPHY2_PLL_CTRL :: PLLCTRL_7 :: ADJUST_AUX_LDO [11:11] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x800,11,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x800,11)
#define BRPHY2_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_MASK              0x0800
#define BRPHY2_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_ALIGN             0
#define BRPHY2_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_BITS              1
#define BRPHY2_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_SHIFT             11

/* BRPHY2_PLL_CTRL :: PLLCTRL_7 :: CLAMP_REFERENCE [10:09] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x600,9,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x600,9)
#define BRPHY2_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_MASK             0x0600
#define BRPHY2_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_ALIGN            0
#define BRPHY2_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_BITS             2
#define BRPHY2_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_SHIFT            9

/* BRPHY2_PLL_CTRL :: PLLCTRL_7 :: CML_BUFFER_PWRDN [08:08] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x100,8,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0x100,8)
#define BRPHY2_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_MASK            0x0100
#define BRPHY2_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_ALIGN           0
#define BRPHY2_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_BITS            1
#define BRPHY2_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_SHIFT           8

/* BRPHY2_PLL_CTRL :: PLLCTRL_7 :: TXCLK_PWRDN [07:04] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0xf0,4,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0xf0,4)
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_MASK                 0x00f0
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_ALIGN                0
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_BITS                 4
#define BRPHY2_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_SHIFT                4

/* BRPHY2_PLL_CTRL :: PLLCTRL_7 :: RXCLK_PWRDN [03:00] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0xf,0,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_7,0xf,0)
#define BRPHY2_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_MASK                 0x000f
#define BRPHY2_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_ALIGN                0
#define BRPHY2_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_BITS                 4
#define BRPHY2_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_SHIFT                0


/****************************************************************************
 * BRPHY2_PLL_CTRL :: PLLCTRL_8
 ***************************************************************************/
/* BRPHY2_PLL_CTRL :: PLLCTRL_8 :: PLL_SPARE5 [15:01] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_8,0xfffe,1,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_8,0xfffe,1)
#define BRPHY2_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_MASK                  0xfffe
#define BRPHY2_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_ALIGN                 0
#define BRPHY2_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_BITS                  15
#define BRPHY2_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_SHIFT                 1

/* BRPHY2_PLL_CTRL :: PLLCTRL_8 :: PC_CLK_1G_PWRDN [00:00] */
#define Wr_BRPHY2_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) WriteRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_8,0x1,0,x)
#define Rd_BRPHY2_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) ReadRegBits16(BRPHY2_PLL_CTRL_PLLCTRL_8,0x1,0)
#define BRPHY2_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_MASK             0x0001
#define BRPHY2_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_ALIGN            0
#define BRPHY2_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_BITS             1
#define BRPHY2_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_SHIFT            0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_AFE_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_AFE_CTRL :: RXCONFIG_0
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: RXCONFIG_0 :: RXCONFIG_15_0 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) WriteReg16(BRPHY2_AFE_CTRL_RXCONFIG_0,x)
#define Rd_BRPHY2_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) ReadReg16(BRPHY2_AFE_CTRL_RXCONFIG_0)
#define BRPHY2_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_MASK              0xffff
#define BRPHY2_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_ALIGN             0
#define BRPHY2_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_BITS              16
#define BRPHY2_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_SHIFT             0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: RXCONFIG_1
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: RXCONFIG_1 :: RXCONFIG_31_23 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) WriteReg16(BRPHY2_AFE_CTRL_RXCONFIG_1,x)
#define Rd_BRPHY2_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) ReadReg16(BRPHY2_AFE_CTRL_RXCONFIG_1)
#define BRPHY2_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_MASK             0xffff
#define BRPHY2_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_ALIGN            0
#define BRPHY2_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_BITS             16
#define BRPHY2_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_SHIFT            0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: RXCONFIG_2
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: RXCONFIG_2 :: RXCONFIG_47_32 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) WriteReg16(BRPHY2_AFE_CTRL_RXCONFIG_2,x)
#define Rd_BRPHY2_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) ReadReg16(BRPHY2_AFE_CTRL_RXCONFIG_2)
#define BRPHY2_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_MASK             0xffff
#define BRPHY2_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_ALIGN            0
#define BRPHY2_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_BITS             16
#define BRPHY2_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_SHIFT            0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: RXCONFIG_3
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: RXCONFIG_3 :: RXCONFIG_63_48 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) WriteReg16(BRPHY2_AFE_CTRL_RXCONFIG_3,x)
#define Rd_BRPHY2_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) ReadReg16(BRPHY2_AFE_CTRL_RXCONFIG_3)
#define BRPHY2_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_MASK             0xffff
#define BRPHY2_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_ALIGN            0
#define BRPHY2_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_BITS             16
#define BRPHY2_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_SHIFT            0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: RXCONFIG_4
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: RXCONFIG_4 :: RXCONFIG_79_64 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) WriteReg16(BRPHY2_AFE_CTRL_RXCONFIG_4,x)
#define Rd_BRPHY2_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) ReadReg16(BRPHY2_AFE_CTRL_RXCONFIG_4)
#define BRPHY2_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_MASK             0xffff
#define BRPHY2_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_ALIGN            0
#define BRPHY2_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_BITS             16
#define BRPHY2_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_SHIFT            0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: RXCONFIG5_LP
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: RXCONFIG5_LP :: RXCONFIG_86_80 [15:09] */
#define Wr_BRPHY2_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) WriteRegBits16(BRPHY2_AFE_CTRL_RXCONFIG5_LP,0xfe00,9,x)
#define Rd_BRPHY2_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) ReadRegBits16(BRPHY2_AFE_CTRL_RXCONFIG5_LP,0xfe00,9)
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_MASK           0xfe00
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_ALIGN          0
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_BITS           7
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_SHIFT          9

/* BRPHY2_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_0 [08:06] */
#define Wr_BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) WriteRegBits16(BRPHY2_AFE_CTRL_RXCONFIG5_LP,0x1c0,6,x)
#define Rd_BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) ReadRegBits16(BRPHY2_AFE_CTRL_RXCONFIG5_LP,0x1c0,6)
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_MASK                  0x01c0
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_ALIGN                 0
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_BITS                  3
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_SHIFT                 6

/* BRPHY2_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_1 [05:03] */
#define Wr_BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) WriteRegBits16(BRPHY2_AFE_CTRL_RXCONFIG5_LP,0x38,3,x)
#define Rd_BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) ReadRegBits16(BRPHY2_AFE_CTRL_RXCONFIG5_LP,0x38,3)
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_MASK                  0x0038
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_ALIGN                 0
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_BITS                  3
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_SHIFT                 3

/* BRPHY2_AFE_CTRL :: RXCONFIG5_LP :: MODE_force [02:00] */
#define Wr_BRPHY2_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) WriteRegBits16(BRPHY2_AFE_CTRL_RXCONFIG5_LP,0x7,0,x)
#define Rd_BRPHY2_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) ReadRegBits16(BRPHY2_AFE_CTRL_RXCONFIG5_LP,0x7,0)
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_MASK               0x0007
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_ALIGN              0
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_BITS               3
#define BRPHY2_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_SHIFT              0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: TX_CONFIG_0
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: TX_CONFIG_0 :: TX_CONFIG_15_0 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) WriteReg16(BRPHY2_AFE_CTRL_TX_CONFIG_0,x)
#define Rd_BRPHY2_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) ReadReg16(BRPHY2_AFE_CTRL_TX_CONFIG_0)
#define BRPHY2_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_MASK            0xffff
#define BRPHY2_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_ALIGN           0
#define BRPHY2_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_BITS            16
#define BRPHY2_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_SHIFT           0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: TX_CONFIG_1
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: TX_CONFIG_1 :: TX_BW_TUNE [15:11] */
#define Wr_BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) WriteRegBits16(BRPHY2_AFE_CTRL_TX_CONFIG_1,0xf800,11,x)
#define Rd_BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) ReadRegBits16(BRPHY2_AFE_CTRL_TX_CONFIG_1,0xf800,11)
#define BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_MASK                0xf800
#define BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_ALIGN               0
#define BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_BITS                5
#define BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_SHIFT               11

/* BRPHY2_AFE_CTRL :: TX_CONFIG_1 :: TX_CONFIG_26_16 [10:00] */
#define Wr_BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) WriteRegBits16(BRPHY2_AFE_CTRL_TX_CONFIG_1,0x7ff,0,x)
#define Rd_BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) ReadRegBits16(BRPHY2_AFE_CTRL_TX_CONFIG_1,0x7ff,0)
#define BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_MASK           0x07ff
#define BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_ALIGN          0
#define BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_BITS           11
#define BRPHY2_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_SHIFT          0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: VDAC_ICTRL_0
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: VDAC_ICTRL_0 :: VDAC_current_ctrl_15_0 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) WriteReg16(BRPHY2_AFE_CTRL_VDAC_ICTRL_0,x)
#define Rd_BRPHY2_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) ReadReg16(BRPHY2_AFE_CTRL_VDAC_ICTRL_0)
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_MASK   0xffff
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_ALIGN  0
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_BITS   16
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_SHIFT  0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: VDAC_ICTRL_1
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: VDAC_ICTRL_1 :: VDAC_current_ctrl_31_16 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) WriteReg16(BRPHY2_AFE_CTRL_VDAC_ICTRL_1,x)
#define Rd_BRPHY2_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) ReadReg16(BRPHY2_AFE_CTRL_VDAC_ICTRL_1)
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_MASK  0xffff
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_ALIGN 0
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_BITS  16
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_SHIFT 0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: VDAC_ICTRL_2
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: VDAC_ICTRL_2 :: VDAC_current_ctrl_51_36 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) WriteReg16(BRPHY2_AFE_CTRL_VDAC_ICTRL_2,x)
#define Rd_BRPHY2_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) ReadReg16(BRPHY2_AFE_CTRL_VDAC_ICTRL_2)
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_MASK  0xffff
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_ALIGN 0
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_BITS  16
#define BRPHY2_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_SHIFT 0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: VDAC_OTHERS_0
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: VDAC_OTHERS_0 :: current_ctrl_35_32_others [15:00] */
#define Wr_BRPHY2_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) WriteReg16(BRPHY2_AFE_CTRL_VDAC_OTHERS_0,x)
#define Rd_BRPHY2_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) ReadReg16(BRPHY2_AFE_CTRL_VDAC_OTHERS_0)
#define BRPHY2_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_MASK 0xffff
#define BRPHY2_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_ALIGN 0
#define BRPHY2_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_BITS 16
#define BRPHY2_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_SHIFT 0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: HPF_TRIM_OTHERS
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: HPF_TRIM_OTHERS :: Reserved [15:10] */
#define Wr_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) WriteRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10,x)
#define Rd_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) ReadRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10)
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_MASK              0xfc00
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_ALIGN             0
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_BITS              6
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_SHIFT             10

/* BRPHY2_AFE_CTRL :: HPF_TRIM_OTHERS :: RX_SAMPLE_WIDTH [09:07] */
#define Wr_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) WriteRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7,x)
#define Rd_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) ReadRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7)
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_MASK       0x0380
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_ALIGN      0
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_BITS       3
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_SHIFT      7

/* BRPHY2_AFE_CTRL :: HPF_TRIM_OTHERS :: IDAC_fine_tune [06:04] */
#define Wr_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) WriteRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4,x)
#define Rd_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) ReadRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4)
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_MASK        0x0070
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_ALIGN       0
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_BITS        3
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_SHIFT       4

/* BRPHY2_AFE_CTRL :: HPF_TRIM_OTHERS :: SOFT_SEL_TRIM_HPF [03:03] */
#define Wr_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) WriteRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3,x)
#define Rd_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) ReadRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3)
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_MASK     0x0008
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_ALIGN    0
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_BITS     1
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_SHIFT    3

/* BRPHY2_AFE_CTRL :: HPF_TRIM_OTHERS :: TRIM_HPF [02:00] */
#define Wr_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) WriteRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0,x)
#define Rd_BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) ReadRegBits16(BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0)
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_MASK              0x0007
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_ALIGN             0
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_BITS              3
#define BRPHY2_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_SHIFT             0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: TX_EXTRA_CONFIG_0
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: TX_EXTRA_CONFIG_0 :: TX_EXTRA_CONFIG_15_0 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) WriteReg16(BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_0,x)
#define Rd_BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) ReadReg16(BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_0)
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_MASK 0xffff
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_ALIGN 0
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_BITS 16
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_SHIFT 0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: TX_EXTRA_CONFIG_1
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: TX_EXTRA_CONFIG_1 :: TX_EXTRA_CONFIG_31_16 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) WriteReg16(BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_1,x)
#define Rd_BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) ReadReg16(BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_1)
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_MASK 0xffff
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_ALIGN 0
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_BITS 16
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_SHIFT 0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: TX_EXTRA_CONFIG_2
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: TX_EXTRA_CONFIG_2 :: TX_EXTRA_CONFIG_47_32 [15:00] */
#define Wr_BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) WriteReg16(BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_2,x)
#define Rd_BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) ReadReg16(BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_2)
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_MASK 0xffff
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_ALIGN 0
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_BITS 16
#define BRPHY2_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_SHIFT 0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: TEMPSEN_OTHERS
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: TEMPSEN_OTHERS :: TEMPSEN [15:02] */
#define Wr_BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) WriteRegBits16(BRPHY2_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2,x)
#define Rd_BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) ReadRegBits16(BRPHY2_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2)
#define BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_MASK                0xfffc
#define BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_ALIGN               0
#define BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_BITS                14
#define BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_SHIFT               2

/* BRPHY2_AFE_CTRL :: TEMPSEN_OTHERS :: EXTRA_10BT [01:00] */
#define Wr_BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) WriteRegBits16(BRPHY2_AFE_CTRL_TEMPSEN_OTHERS,0x3,0,x)
#define Rd_BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) ReadRegBits16(BRPHY2_AFE_CTRL_TEMPSEN_OTHERS,0x3,0)
#define BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_MASK             0x0003
#define BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_ALIGN            0
#define BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_BITS             2
#define BRPHY2_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_SHIFT            0


/****************************************************************************
 * BRPHY2_AFE_CTRL :: FUTURE_RSV
 ***************************************************************************/
/* BRPHY2_AFE_CTRL :: FUTURE_RSV :: FUTURE_RSV [15:00] */
#define Wr_BRPHY2_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) WriteReg16(BRPHY2_AFE_CTRL_FUTURE_RSV,x)
#define Rd_BRPHY2_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) ReadReg16(BRPHY2_AFE_CTRL_FUTURE_RSV)
#define BRPHY2_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_MASK                 0xffff
#define BRPHY2_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_ALIGN                0
#define BRPHY2_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_BITS                 16
#define BRPHY2_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_ECD_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC0
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC0 :: RUN_IMMEDIATE [15:15] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x8000,15,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x8000,15)
#define BRPHY2_ECD_CTRL_EXPC0_RUN_IMMEDIATE_MASK                   0x8000
#define BRPHY2_ECD_CTRL_EXPC0_RUN_IMMEDIATE_ALIGN                  0
#define BRPHY2_ECD_CTRL_EXPC0_RUN_IMMEDIATE_BITS                   1
#define BRPHY2_ECD_CTRL_EXPC0_RUN_IMMEDIATE_SHIFT                  15

/* BRPHY2_ECD_CTRL :: EXPC0 :: RUN_AT_AUTONEG [14:14] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x4000,14,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x4000,14)
#define BRPHY2_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_MASK                  0x4000
#define BRPHY2_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_ALIGN                 0
#define BRPHY2_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_BITS                  1
#define BRPHY2_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_SHIFT                 14

/* BRPHY2_ECD_CTRL :: EXPC0 :: INTER_PAIR_SHORT_DIS [13:13] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x2000,13,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x2000,13)
#define BRPHY2_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_MASK            0x2000
#define BRPHY2_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_ALIGN           0
#define BRPHY2_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_BITS            1
#define BRPHY2_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_SHIFT           13

/* BRPHY2_ECD_CTRL :: EXPC0 :: BREAK_LINK [12:12] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_BREAK_LINK(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x1000,12,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_BREAK_LINK(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x1000,12)
#define BRPHY2_ECD_CTRL_EXPC0_BREAK_LINK_MASK                      0x1000
#define BRPHY2_ECD_CTRL_EXPC0_BREAK_LINK_ALIGN                     0
#define BRPHY2_ECD_CTRL_EXPC0_BREAK_LINK_BITS                      1
#define BRPHY2_ECD_CTRL_EXPC0_BREAK_LINK_SHIFT                     12

/* BRPHY2_ECD_CTRL :: EXPC0 :: CABLE_DIAG_STATUS [11:11] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x800,11,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x800,11)
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_MASK               0x0800
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_ALIGN              0
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_BITS               1
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_SHIFT              11

/* BRPHY2_ECD_CTRL :: EXPC0 :: CABLE_LEN_UNIT [10:10] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x400,10,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x400,10)
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_MASK                  0x0400
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_ALIGN                 0
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_BITS                  1
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_SHIFT                 10

/* BRPHY2_ECD_CTRL :: EXPC0 :: reserved0 [09:09] */
#define BRPHY2_ECD_CTRL_EXPC0_RESERVED0_MASK                       0x0200
#define BRPHY2_ECD_CTRL_EXPC0_RESERVED0_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPC0_RESERVED0_BITS                       1
#define BRPHY2_ECD_CTRL_EXPC0_RESERVED0_SHIFT                      9

/* BRPHY2_ECD_CTRL :: EXPC0 :: FAST_TIMER_ENABLE [08:08] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x100,8,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x100,8)
#define BRPHY2_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_MASK               0x0100
#define BRPHY2_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_ALIGN              0
#define BRPHY2_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_BITS               1
#define BRPHY2_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_SHIFT              8

/* BRPHY2_ECD_CTRL :: EXPC0 :: INTRPT_ENABLE [07:07] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x80,7,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x80,7)
#define BRPHY2_ECD_CTRL_EXPC0_INTRPT_ENABLE_MASK                   0x0080
#define BRPHY2_ECD_CTRL_EXPC0_INTRPT_ENABLE_ALIGN                  0
#define BRPHY2_ECD_CTRL_EXPC0_INTRPT_ENABLE_BITS                   1
#define BRPHY2_ECD_CTRL_EXPC0_INTRPT_ENABLE_SHIFT                  7

/* BRPHY2_ECD_CTRL :: EXPC0 :: STOP_PLL_CLK [06:06] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x40,6,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x40,6)
#define BRPHY2_ECD_CTRL_EXPC0_STOP_PLL_CLK_MASK                    0x0040
#define BRPHY2_ECD_CTRL_EXPC0_STOP_PLL_CLK_ALIGN                   0
#define BRPHY2_ECD_CTRL_EXPC0_STOP_PLL_CLK_BITS                    1
#define BRPHY2_ECD_CTRL_EXPC0_STOP_PLL_CLK_SHIFT                   6

/* BRPHY2_ECD_CTRL :: EXPC0 :: reserved1 [05:04] */
#define BRPHY2_ECD_CTRL_EXPC0_RESERVED1_MASK                       0x0030
#define BRPHY2_ECD_CTRL_EXPC0_RESERVED1_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPC0_RESERVED1_BITS                       2
#define BRPHY2_ECD_CTRL_EXPC0_RESERVED1_SHIFT                      4

/* BRPHY2_ECD_CTRL :: EXPC0 :: INVALID_RESULT [03:03] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_INVALID_RESULT(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x8,3,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_INVALID_RESULT(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x8,3)
#define BRPHY2_ECD_CTRL_EXPC0_INVALID_RESULT_MASK                  0x0008
#define BRPHY2_ECD_CTRL_EXPC0_INVALID_RESULT_ALIGN                 0
#define BRPHY2_ECD_CTRL_EXPC0_INVALID_RESULT_BITS                  1
#define BRPHY2_ECD_CTRL_EXPC0_INVALID_RESULT_SHIFT                 3

/* BRPHY2_ECD_CTRL :: EXPC0 :: CABLE_DIAG_EXE [02:02] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x4,2,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x4,2)
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_MASK                  0x0004
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_ALIGN                 0
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_BITS                  1
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_SHIFT                 2

/* BRPHY2_ECD_CTRL :: EXPC0 :: AUTO_RUN_FOR_BROKEN_ANG [01:01] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x2,1,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x2,1)
#define BRPHY2_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_MASK         0x0002
#define BRPHY2_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_ALIGN        0
#define BRPHY2_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_BITS         1
#define BRPHY2_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_SHIFT        1

/* BRPHY2_ECD_CTRL :: EXPC0 :: CABLE_TYPE [00:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC0_CABLE_TYPE(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x1,0,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC0_CABLE_TYPE(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC0,0x1,0)
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_TYPE_MASK                      0x0001
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_TYPE_ALIGN                     0
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_TYPE_BITS                      1
#define BRPHY2_ECD_CTRL_EXPC0_CABLE_TYPE_SHIFT                     0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC1
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC1 :: PA_CD_CODE [15:12] */
#define Wr_BRPHY2_ECD_CTRL_EXPC1_PA_CD_CODE(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC1,0xf000,12,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC1_PA_CD_CODE(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC1,0xf000,12)
#define BRPHY2_ECD_CTRL_EXPC1_PA_CD_CODE_MASK                      0xf000
#define BRPHY2_ECD_CTRL_EXPC1_PA_CD_CODE_ALIGN                     0
#define BRPHY2_ECD_CTRL_EXPC1_PA_CD_CODE_BITS                      4
#define BRPHY2_ECD_CTRL_EXPC1_PA_CD_CODE_SHIFT                     12

/* BRPHY2_ECD_CTRL :: EXPC1 :: PB_CD_CODE [11:08] */
#define Wr_BRPHY2_ECD_CTRL_EXPC1_PB_CD_CODE(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC1,0xf00,8,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC1_PB_CD_CODE(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC1,0xf00,8)
#define BRPHY2_ECD_CTRL_EXPC1_PB_CD_CODE_MASK                      0x0f00
#define BRPHY2_ECD_CTRL_EXPC1_PB_CD_CODE_ALIGN                     0
#define BRPHY2_ECD_CTRL_EXPC1_PB_CD_CODE_BITS                      4
#define BRPHY2_ECD_CTRL_EXPC1_PB_CD_CODE_SHIFT                     8

/* BRPHY2_ECD_CTRL :: EXPC1 :: PC_CD_CODE [07:04] */
#define Wr_BRPHY2_ECD_CTRL_EXPC1_PC_CD_CODE(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC1,0xf0,4,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC1_PC_CD_CODE(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC1,0xf0,4)
#define BRPHY2_ECD_CTRL_EXPC1_PC_CD_CODE_MASK                      0x00f0
#define BRPHY2_ECD_CTRL_EXPC1_PC_CD_CODE_ALIGN                     0
#define BRPHY2_ECD_CTRL_EXPC1_PC_CD_CODE_BITS                      4
#define BRPHY2_ECD_CTRL_EXPC1_PC_CD_CODE_SHIFT                     4

/* BRPHY2_ECD_CTRL :: EXPC1 :: PD_CD_CODE [03:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC1_PD_CD_CODE(x) WriteRegBits16(BRPHY2_ECD_CTRL_EXPC1,0xf,0,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC1_PD_CD_CODE(x) ReadRegBits16(BRPHY2_ECD_CTRL_EXPC1,0xf,0)
#define BRPHY2_ECD_CTRL_EXPC1_PD_CD_CODE_MASK                      0x000f
#define BRPHY2_ECD_CTRL_EXPC1_PD_CD_CODE_ALIGN                     0
#define BRPHY2_ECD_CTRL_EXPC1_PD_CD_CODE_BITS                      4
#define BRPHY2_ECD_CTRL_EXPC1_PD_CD_CODE_SHIFT                     0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC2
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC2 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) WriteReg16(BRPHY2_ECD_CTRL_EXPC2,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) ReadReg16(BRPHY2_ECD_CTRL_EXPC2)
#define BRPHY2_ECD_CTRL_EXPC2_LENGTH_INDICATION_MASK               0xffff
#define BRPHY2_ECD_CTRL_EXPC2_LENGTH_INDICATION_ALIGN              0
#define BRPHY2_ECD_CTRL_EXPC2_LENGTH_INDICATION_BITS               16
#define BRPHY2_ECD_CTRL_EXPC2_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC3
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC3 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) WriteReg16(BRPHY2_ECD_CTRL_EXPC3,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) ReadReg16(BRPHY2_ECD_CTRL_EXPC3)
#define BRPHY2_ECD_CTRL_EXPC3_LENGTH_INDICATION_MASK               0xffff
#define BRPHY2_ECD_CTRL_EXPC3_LENGTH_INDICATION_ALIGN              0
#define BRPHY2_ECD_CTRL_EXPC3_LENGTH_INDICATION_BITS               16
#define BRPHY2_ECD_CTRL_EXPC3_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC4
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC4 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) WriteReg16(BRPHY2_ECD_CTRL_EXPC4,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) ReadReg16(BRPHY2_ECD_CTRL_EXPC4)
#define BRPHY2_ECD_CTRL_EXPC4_LENGTH_INDICATION_MASK               0xffff
#define BRPHY2_ECD_CTRL_EXPC4_LENGTH_INDICATION_ALIGN              0
#define BRPHY2_ECD_CTRL_EXPC4_LENGTH_INDICATION_BITS               16
#define BRPHY2_ECD_CTRL_EXPC4_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC5
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC5 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) WriteReg16(BRPHY2_ECD_CTRL_EXPC5,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) ReadReg16(BRPHY2_ECD_CTRL_EXPC5)
#define BRPHY2_ECD_CTRL_EXPC5_LENGTH_INDICATION_MASK               0xffff
#define BRPHY2_ECD_CTRL_EXPC5_LENGTH_INDICATION_ALIGN              0
#define BRPHY2_ECD_CTRL_EXPC5_LENGTH_INDICATION_BITS               16
#define BRPHY2_ECD_CTRL_EXPC5_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC6
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC6 :: F_COUNT_0 [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC6_F_COUNT_0(x) WriteReg16(BRPHY2_ECD_CTRL_EXPC6,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC6_F_COUNT_0(x) ReadReg16(BRPHY2_ECD_CTRL_EXPC6)
#define BRPHY2_ECD_CTRL_EXPC6_F_COUNT_0_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPC6_F_COUNT_0_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPC6_F_COUNT_0_BITS                       16
#define BRPHY2_ECD_CTRL_EXPC6_F_COUNT_0_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC7
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC7 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC7_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPC7,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC7_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPC7)
#define BRPHY2_ECD_CTRL_EXPC7_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPC7_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPC7_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPC7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC8
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC8 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC8_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPC8,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC8_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPC8)
#define BRPHY2_ECD_CTRL_EXPC8_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPC8_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPC8_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPC8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPC9
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPC9 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPC9_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPC9,x)
#define Rd_BRPHY2_ECD_CTRL_EXPC9_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPC9)
#define BRPHY2_ECD_CTRL_EXPC9_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPC9_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPC9_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPC9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPCA
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPCA :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPCA_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPCA,x)
#define Rd_BRPHY2_ECD_CTRL_EXPCA_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPCA)
#define BRPHY2_ECD_CTRL_EXPCA_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPCA_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPCA_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPCA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPCB
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPCB :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPCB_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPCB,x)
#define Rd_BRPHY2_ECD_CTRL_EXPCB_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPCB)
#define BRPHY2_ECD_CTRL_EXPCB_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPCB_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPCB_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPCB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPCC
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPCC :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPCC_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPCC,x)
#define Rd_BRPHY2_ECD_CTRL_EXPCC_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPCC)
#define BRPHY2_ECD_CTRL_EXPCC_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPCC_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPCC_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPCC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPCD
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPCD :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPCD_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPCD,x)
#define Rd_BRPHY2_ECD_CTRL_EXPCD_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPCD)
#define BRPHY2_ECD_CTRL_EXPCD_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPCD_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPCD_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPCD_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPCE
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPCE :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPCE_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPCE,x)
#define Rd_BRPHY2_ECD_CTRL_EXPCE_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPCE)
#define BRPHY2_ECD_CTRL_EXPCE_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPCE_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPCE_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPCE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPCF
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPCF :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPCF_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPCF,x)
#define Rd_BRPHY2_ECD_CTRL_EXPCF_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPCF)
#define BRPHY2_ECD_CTRL_EXPCF_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPCF_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPCF_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPCF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE0
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE0 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE0_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE0,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE0_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE0)
#define BRPHY2_ECD_CTRL_EXPE0_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE0_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE0_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE0_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE1
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE1 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE1_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE1,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE1_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE1)
#define BRPHY2_ECD_CTRL_EXPE1_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE1_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE1_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE1_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE2
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE2 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE2_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE2,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE2_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE2)
#define BRPHY2_ECD_CTRL_EXPE2_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE2_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE2_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE2_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE3
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE3 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE3_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE3,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE3_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE3)
#define BRPHY2_ECD_CTRL_EXPE3_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE3_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE3_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE3_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE4
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE4 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE4_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE4,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE4_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE4)
#define BRPHY2_ECD_CTRL_EXPE4_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE4_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE4_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE4_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE5
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE5 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE5_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE5,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE5_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE5)
#define BRPHY2_ECD_CTRL_EXPE5_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE5_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE5_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE5_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE6
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE6 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE6_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE6,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE6_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE6)
#define BRPHY2_ECD_CTRL_EXPE6_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE6_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE6_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE6_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE7
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE7 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE7_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE7,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE7_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE7)
#define BRPHY2_ECD_CTRL_EXPE7_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE7_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE7_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE8
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE8 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE8_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE8,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE8_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE8)
#define BRPHY2_ECD_CTRL_EXPE8_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE8_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE8_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPE9
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPE9 :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPE9_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPE9,x)
#define Rd_BRPHY2_ECD_CTRL_EXPE9_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPE9)
#define BRPHY2_ECD_CTRL_EXPE9_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPE9_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPE9_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPE9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPEA
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPEA :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPEA_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPEA,x)
#define Rd_BRPHY2_ECD_CTRL_EXPEA_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPEA)
#define BRPHY2_ECD_CTRL_EXPEA_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPEA_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPEA_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPEA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPEB
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPEB :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPEB_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPEB,x)
#define Rd_BRPHY2_ECD_CTRL_EXPEB_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPEB)
#define BRPHY2_ECD_CTRL_EXPEB_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPEB_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPEB_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPEB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPEC
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPEC :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPEC_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPEC,x)
#define Rd_BRPHY2_ECD_CTRL_EXPEC_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPEC)
#define BRPHY2_ECD_CTRL_EXPEC_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPEC_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPEC_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPEC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPED
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPED :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPED_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPED,x)
#define Rd_BRPHY2_ECD_CTRL_EXPED_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPED)
#define BRPHY2_ECD_CTRL_EXPED_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPED_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPED_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPED_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPEE
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPEE :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPEE_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPEE,x)
#define Rd_BRPHY2_ECD_CTRL_EXPEE_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPEE)
#define BRPHY2_ECD_CTRL_EXPEE_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPEE_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPEE_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPEE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY2_ECD_CTRL :: EXPEF
 ***************************************************************************/
/* BRPHY2_ECD_CTRL :: EXPEF :: UNDEFINED [15:00] */
#define Wr_BRPHY2_ECD_CTRL_EXPEF_UNDEFINED(x) WriteReg16(BRPHY2_ECD_CTRL_EXPEF,x)
#define Rd_BRPHY2_ECD_CTRL_EXPEF_UNDEFINED(x) ReadReg16(BRPHY2_ECD_CTRL_EXPEF)
#define BRPHY2_ECD_CTRL_EXPEF_UNDEFINED_MASK                       0xffff
#define BRPHY2_ECD_CTRL_EXPEF_UNDEFINED_ALIGN                      0
#define BRPHY2_ECD_CTRL_EXPEF_UNDEFINED_BITS                       16
#define BRPHY2_ECD_CTRL_EXPEF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_BR_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP90
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP90 :: DIG_HPF_EN [15:15] */
#define Wr_BRPHY2_BR_CTRL_EXP90_DIG_HPF_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP90,0x8000,15,x)
#define Rd_BRPHY2_BR_CTRL_EXP90_DIG_HPF_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP90,0x8000,15)
#define BRPHY2_BR_CTRL_EXP90_DIG_HPF_EN_MASK                       0x8000
#define BRPHY2_BR_CTRL_EXP90_DIG_HPF_EN_ALIGN                      0
#define BRPHY2_BR_CTRL_EXP90_DIG_HPF_EN_BITS                       1
#define BRPHY2_BR_CTRL_EXP90_DIG_HPF_EN_SHIFT                      15

/* BRPHY2_BR_CTRL :: EXP90 :: BR_SCR_STATUS [14:13] */
#define Wr_BRPHY2_BR_CTRL_EXP90_BR_SCR_STATUS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP90,0x6000,13,x)
#define Rd_BRPHY2_BR_CTRL_EXP90_BR_SCR_STATUS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP90,0x6000,13)
#define BRPHY2_BR_CTRL_EXP90_BR_SCR_STATUS_MASK                    0x6000
#define BRPHY2_BR_CTRL_EXP90_BR_SCR_STATUS_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP90_BR_SCR_STATUS_BITS                    2
#define BRPHY2_BR_CTRL_EXP90_BR_SCR_STATUS_SHIFT                   13

/* BRPHY2_BR_CTRL :: EXP90 :: BR_ALIGN_STATE [12:10] */
#define Wr_BRPHY2_BR_CTRL_EXP90_BR_ALIGN_STATE(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP90,0x1c00,10,x)
#define Rd_BRPHY2_BR_CTRL_EXP90_BR_ALIGN_STATE(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP90,0x1c00,10)
#define BRPHY2_BR_CTRL_EXP90_BR_ALIGN_STATE_MASK                   0x1c00
#define BRPHY2_BR_CTRL_EXP90_BR_ALIGN_STATE_ALIGN                  0
#define BRPHY2_BR_CTRL_EXP90_BR_ALIGN_STATE_BITS                   3
#define BRPHY2_BR_CTRL_EXP90_BR_ALIGN_STATE_SHIFT                  10

/* BRPHY2_BR_CTRL :: EXP90 :: BR_RX_STATE [09:06] */
#define Wr_BRPHY2_BR_CTRL_EXP90_BR_RX_STATE(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP90,0x3c0,6,x)
#define Rd_BRPHY2_BR_CTRL_EXP90_BR_RX_STATE(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP90,0x3c0,6)
#define BRPHY2_BR_CTRL_EXP90_BR_RX_STATE_MASK                      0x03c0
#define BRPHY2_BR_CTRL_EXP90_BR_RX_STATE_ALIGN                     0
#define BRPHY2_BR_CTRL_EXP90_BR_RX_STATE_BITS                      4
#define BRPHY2_BR_CTRL_EXP90_BR_RX_STATE_SHIFT                     6

/* BRPHY2_BR_CTRL :: EXP90 :: BR_PCS_STATE [05:02] */
#define Wr_BRPHY2_BR_CTRL_EXP90_BR_PCS_STATE(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP90,0x3c,2,x)
#define Rd_BRPHY2_BR_CTRL_EXP90_BR_PCS_STATE(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP90,0x3c,2)
#define BRPHY2_BR_CTRL_EXP90_BR_PCS_STATE_MASK                     0x003c
#define BRPHY2_BR_CTRL_EXP90_BR_PCS_STATE_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP90_BR_PCS_STATE_BITS                     4
#define BRPHY2_BR_CTRL_EXP90_BR_PCS_STATE_SHIFT                    2

/* BRPHY2_BR_CTRL :: EXP90 :: BR_FORCE_LINK_CTL [01:01] */
#define Wr_BRPHY2_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP90,0x2,1,x)
#define Rd_BRPHY2_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP90,0x2,1)
#define BRPHY2_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_MASK                0x0002
#define BRPHY2_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_ALIGN               0
#define BRPHY2_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_BITS                1
#define BRPHY2_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_SHIFT               1

/* BRPHY2_BR_CTRL :: EXP90 :: BR_EN [00:00] */
#define Wr_BRPHY2_BR_CTRL_EXP90_BR_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP90,0x1,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP90_BR_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP90,0x1,0)
#define BRPHY2_BR_CTRL_EXP90_BR_EN_MASK                            0x0001
#define BRPHY2_BR_CTRL_EXP90_BR_EN_ALIGN                           0
#define BRPHY2_BR_CTRL_EXP90_BR_EN_BITS                            1
#define BRPHY2_BR_CTRL_EXP90_BR_EN_SHIFT                           0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP91
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP91 :: DIG_HPF_OV [15:15] */
#define Wr_BRPHY2_BR_CTRL_EXP91_DIG_HPF_OV(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0x8000,15,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_DIG_HPF_OV(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0x8000,15)
#define BRPHY2_BR_CTRL_EXP91_DIG_HPF_OV_MASK                       0x8000
#define BRPHY2_BR_CTRL_EXP91_DIG_HPF_OV_ALIGN                      0
#define BRPHY2_BR_CTRL_EXP91_DIG_HPF_OV_BITS                       1
#define BRPHY2_BR_CTRL_EXP91_DIG_HPF_OV_SHIFT                      15

/* BRPHY2_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV [14:14] */
#define Wr_BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0x4000,14,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0x4000,14)
#define BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_MASK               0x4000
#define BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_ALIGN              0
#define BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_BITS               1
#define BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_SHIFT              14

/* BRPHY2_BR_CTRL :: EXP91 :: INV_LRE_GMII_TXC [13:13] */
#define Wr_BRPHY2_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0x2000,13,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0x2000,13)
#define BRPHY2_BR_CTRL_EXP91_INV_LRE_GMII_TXC_MASK                 0x2000
#define BRPHY2_BR_CTRL_EXP91_INV_LRE_GMII_TXC_ALIGN                0
#define BRPHY2_BR_CTRL_EXP91_INV_LRE_GMII_TXC_BITS                 1
#define BRPHY2_BR_CTRL_EXP91_INV_LRE_GMII_TXC_SHIFT                13

/* BRPHY2_BR_CTRL :: EXP91 :: AGC_AUTOSTAGING_DIS [12:12] */
#define Wr_BRPHY2_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0x1000,12,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0x1000,12)
#define BRPHY2_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_MASK              0x1000
#define BRPHY2_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_ALIGN             0
#define BRPHY2_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_BITS              1
#define BRPHY2_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_SHIFT             12

/* BRPHY2_BR_CTRL :: EXP91 :: BRPGA [11:09] */
#define Wr_BRPHY2_BR_CTRL_EXP91_BRPGA(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0xe00,9,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_BRPGA(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0xe00,9)
#define BRPHY2_BR_CTRL_EXP91_BRPGA_MASK                            0x0e00
#define BRPHY2_BR_CTRL_EXP91_BRPGA_ALIGN                           0
#define BRPHY2_BR_CTRL_EXP91_BRPGA_BITS                            3
#define BRPHY2_BR_CTRL_EXP91_BRPGA_SHIFT                           9

/* BRPHY2_BR_CTRL :: EXP91 :: BRCONFIG [08:04] */
#define Wr_BRPHY2_BR_CTRL_EXP91_BRCONFIG(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0x1f0,4,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_BRCONFIG(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0x1f0,4)
#define BRPHY2_BR_CTRL_EXP91_BRCONFIG_MASK                         0x01f0
#define BRPHY2_BR_CTRL_EXP91_BRCONFIG_ALIGN                        0
#define BRPHY2_BR_CTRL_EXP91_BRCONFIG_BITS                         5
#define BRPHY2_BR_CTRL_EXP91_BRCONFIG_SHIFT                        4

/* BRPHY2_BR_CTRL :: EXP91 :: ACQP_EN_ECO_DIS [03:03] */
#define Wr_BRPHY2_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0x8,3,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0x8,3)
#define BRPHY2_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_MASK                  0x0008
#define BRPHY2_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_ALIGN                 0
#define BRPHY2_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_BITS                  1
#define BRPHY2_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_SHIFT                 3

/* BRPHY2_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV_VAL [02:02] */
#define Wr_BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0x4,2,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0x4,2)
#define BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_MASK           0x0004
#define BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_ALIGN          0
#define BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_BITS           1
#define BRPHY2_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_SHIFT          2

/* BRPHY2_BR_CTRL :: EXP91 :: TXSCR_ZERO_SEED [01:01] */
#define Wr_BRPHY2_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0x2,1,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0x2,1)
#define BRPHY2_BR_CTRL_EXP91_TXSCR_ZERO_SEED_MASK                  0x0002
#define BRPHY2_BR_CTRL_EXP91_TXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY2_BR_CTRL_EXP91_TXSCR_ZERO_SEED_BITS                  1
#define BRPHY2_BR_CTRL_EXP91_TXSCR_ZERO_SEED_SHIFT                 1

/* BRPHY2_BR_CTRL :: EXP91 :: RXSCR_ZERO_SEED [00:00] */
#define Wr_BRPHY2_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP91,0x1,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP91,0x1,0)
#define BRPHY2_BR_CTRL_EXP91_RXSCR_ZERO_SEED_MASK                  0x0001
#define BRPHY2_BR_CTRL_EXP91_RXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY2_BR_CTRL_EXP91_RXSCR_ZERO_SEED_BITS                  1
#define BRPHY2_BR_CTRL_EXP91_RXSCR_ZERO_SEED_SHIFT                 0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP92
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP92 :: DLLCONV_OV_EN [15:15] */
#define Wr_BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x8000,15,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x8000,15)
#define BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_EN_MASK                    0x8000
#define BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_EN_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_EN_BITS                    1
#define BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_EN_SHIFT                   15

/* BRPHY2_BR_CTRL :: EXP92 :: DLLCONV_OV_VAL [14:14] */
#define Wr_BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x4000,14,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x4000,14)
#define BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_VAL_MASK                   0x4000
#define BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_VAL_ALIGN                  0
#define BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_VAL_BITS                   1
#define BRPHY2_BR_CTRL_EXP92_DLLCONV_OV_VAL_SHIFT                  14

/* BRPHY2_BR_CTRL :: EXP92 :: BR_SLAVE_POL_COR_EN [13:13] */
#define Wr_BRPHY2_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x2000,13,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x2000,13)
#define BRPHY2_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_MASK              0x2000
#define BRPHY2_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_ALIGN             0
#define BRPHY2_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_BITS              1
#define BRPHY2_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_SHIFT             13

/* BRPHY2_BR_CTRL :: EXP92 :: BR_EDGE_RATE_SEL [12:11] */
#define Wr_BRPHY2_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x1800,11,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x1800,11)
#define BRPHY2_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_MASK                 0x1800
#define BRPHY2_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_ALIGN                0
#define BRPHY2_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_BITS                 2
#define BRPHY2_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_SHIFT                11

/* BRPHY2_BR_CTRL :: EXP92 :: BR_PCS_RRNOK_POL_EN [10:10] */
#define Wr_BRPHY2_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x400,10,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x400,10)
#define BRPHY2_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_MASK              0x0400
#define BRPHY2_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_ALIGN             0
#define BRPHY2_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_BITS              1
#define BRPHY2_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_SHIFT             10

/* BRPHY2_BR_CTRL :: EXP92 :: LDS_LNK_CHK_ECO_DIS [09:09] */
#define Wr_BRPHY2_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x200,9,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x200,9)
#define BRPHY2_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_MASK              0x0200
#define BRPHY2_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_ALIGN             0
#define BRPHY2_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_BITS              1
#define BRPHY2_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_SHIFT             9

/* BRPHY2_BR_CTRL :: EXP92 :: BR_PCS_POL_EN [08:08] */
#define Wr_BRPHY2_BR_CTRL_EXP92_BR_PCS_POL_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x100,8,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_BR_PCS_POL_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x100,8)
#define BRPHY2_BR_CTRL_EXP92_BR_PCS_POL_EN_MASK                    0x0100
#define BRPHY2_BR_CTRL_EXP92_BR_PCS_POL_EN_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP92_BR_PCS_POL_EN_BITS                    1
#define BRPHY2_BR_CTRL_EXP92_BR_PCS_POL_EN_SHIFT                   8

/* BRPHY2_BR_CTRL :: EXP92 :: JAB_MON_DIS [07:07] */
#define Wr_BRPHY2_BR_CTRL_EXP92_JAB_MON_DIS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x80,7,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_JAB_MON_DIS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x80,7)
#define BRPHY2_BR_CTRL_EXP92_JAB_MON_DIS_MASK                      0x0080
#define BRPHY2_BR_CTRL_EXP92_JAB_MON_DIS_ALIGN                     0
#define BRPHY2_BR_CTRL_EXP92_JAB_MON_DIS_BITS                      1
#define BRPHY2_BR_CTRL_EXP92_JAB_MON_DIS_SHIFT                     7

/* BRPHY2_BR_CTRL :: EXP92 :: BR_AGCSID_TMR_EN [06:06] */
#define Wr_BRPHY2_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x40,6,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x40,6)
#define BRPHY2_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_MASK                 0x0040
#define BRPHY2_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_ALIGN                0
#define BRPHY2_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_BITS                 1
#define BRPHY2_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_SHIFT                6

/* BRPHY2_BR_CTRL :: EXP92 :: BR_SYM_XSCR_EN [05:05] */
#define Wr_BRPHY2_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x20,5,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x20,5)
#define BRPHY2_BR_CTRL_EXP92_BR_SYM_XSCR_EN_MASK                   0x0020
#define BRPHY2_BR_CTRL_EXP92_BR_SYM_XSCR_EN_ALIGN                  0
#define BRPHY2_BR_CTRL_EXP92_BR_SYM_XSCR_EN_BITS                   1
#define BRPHY2_BR_CTRL_EXP92_BR_SYM_XSCR_EN_SHIFT                  5

/* BRPHY2_BR_CTRL :: EXP92 :: CHK_DELIMITER [04:04] */
#define Wr_BRPHY2_BR_CTRL_EXP92_CHK_DELIMITER(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x10,4,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_CHK_DELIMITER(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x10,4)
#define BRPHY2_BR_CTRL_EXP92_CHK_DELIMITER_MASK                    0x0010
#define BRPHY2_BR_CTRL_EXP92_CHK_DELIMITER_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP92_CHK_DELIMITER_BITS                    1
#define BRPHY2_BR_CTRL_EXP92_CHK_DELIMITER_SHIFT                   4

/* BRPHY2_BR_CTRL :: EXP92 :: TX_READ_DLY [03:02] */
#define Wr_BRPHY2_BR_CTRL_EXP92_TX_READ_DLY(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0xc,2,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_TX_READ_DLY(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0xc,2)
#define BRPHY2_BR_CTRL_EXP92_TX_READ_DLY_MASK                      0x000c
#define BRPHY2_BR_CTRL_EXP92_TX_READ_DLY_ALIGN                     0
#define BRPHY2_BR_CTRL_EXP92_TX_READ_DLY_BITS                      2
#define BRPHY2_BR_CTRL_EXP92_TX_READ_DLY_SHIFT                     2

/* BRPHY2_BR_CTRL :: EXP92 :: RX_READ_DLY [01:00] */
#define Wr_BRPHY2_BR_CTRL_EXP92_RX_READ_DLY(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP92,0x3,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP92_RX_READ_DLY(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP92,0x3,0)
#define BRPHY2_BR_CTRL_EXP92_RX_READ_DLY_MASK                      0x0003
#define BRPHY2_BR_CTRL_EXP92_RX_READ_DLY_ALIGN                     0
#define BRPHY2_BR_CTRL_EXP92_RX_READ_DLY_BITS                      2
#define BRPHY2_BR_CTRL_EXP92_RX_READ_DLY_SHIFT                     0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP93
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP93 :: LDS_CAP_DOWNGRADE_DIS [15:15] */
#define Wr_BRPHY2_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP93,0x8000,15,x)
#define Rd_BRPHY2_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP93,0x8000,15)
#define BRPHY2_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_MASK            0x8000
#define BRPHY2_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_ALIGN           0
#define BRPHY2_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_BITS            1
#define BRPHY2_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_SHIFT           15

/* BRPHY2_BR_CTRL :: EXP93 :: LDS_REORDER_DIS [14:14] */
#define Wr_BRPHY2_BR_CTRL_EXP93_LDS_REORDER_DIS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP93,0x4000,14,x)
#define Rd_BRPHY2_BR_CTRL_EXP93_LDS_REORDER_DIS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP93,0x4000,14)
#define BRPHY2_BR_CTRL_EXP93_LDS_REORDER_DIS_MASK                  0x4000
#define BRPHY2_BR_CTRL_EXP93_LDS_REORDER_DIS_ALIGN                 0
#define BRPHY2_BR_CTRL_EXP93_LDS_REORDER_DIS_BITS                  1
#define BRPHY2_BR_CTRL_EXP93_LDS_REORDER_DIS_SHIFT                 14

/* BRPHY2_BR_CTRL :: EXP93 :: LDS_SIM [13:13] */
#define Wr_BRPHY2_BR_CTRL_EXP93_LDS_SIM(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP93,0x2000,13,x)
#define Rd_BRPHY2_BR_CTRL_EXP93_LDS_SIM(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP93,0x2000,13)
#define BRPHY2_BR_CTRL_EXP93_LDS_SIM_MASK                          0x2000
#define BRPHY2_BR_CTRL_EXP93_LDS_SIM_ALIGN                         0
#define BRPHY2_BR_CTRL_EXP93_LDS_SIM_BITS                          1
#define BRPHY2_BR_CTRL_EXP93_LDS_SIM_SHIFT                         13

/* BRPHY2_BR_CTRL :: EXP93 :: LDS_SCR_ON [12:12] */
#define Wr_BRPHY2_BR_CTRL_EXP93_LDS_SCR_ON(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP93,0x1000,12,x)
#define Rd_BRPHY2_BR_CTRL_EXP93_LDS_SCR_ON(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP93,0x1000,12)
#define BRPHY2_BR_CTRL_EXP93_LDS_SCR_ON_MASK                       0x1000
#define BRPHY2_BR_CTRL_EXP93_LDS_SCR_ON_ALIGN                      0
#define BRPHY2_BR_CTRL_EXP93_LDS_SCR_ON_BITS                       1
#define BRPHY2_BR_CTRL_EXP93_LDS_SCR_ON_SHIFT                      12

/* BRPHY2_BR_CTRL :: EXP93 :: LDS_PHASE_BYP [11:11] */
#define Wr_BRPHY2_BR_CTRL_EXP93_LDS_PHASE_BYP(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP93,0x800,11,x)
#define Rd_BRPHY2_BR_CTRL_EXP93_LDS_PHASE_BYP(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP93,0x800,11)
#define BRPHY2_BR_CTRL_EXP93_LDS_PHASE_BYP_MASK                    0x0800
#define BRPHY2_BR_CTRL_EXP93_LDS_PHASE_BYP_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP93_LDS_PHASE_BYP_BITS                    1
#define BRPHY2_BR_CTRL_EXP93_LDS_PHASE_BYP_SHIFT                   11

/* BRPHY2_BR_CTRL :: EXP93 :: LDS_PHASE_INIT [10:08] */
#define Wr_BRPHY2_BR_CTRL_EXP93_LDS_PHASE_INIT(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP93,0x700,8,x)
#define Rd_BRPHY2_BR_CTRL_EXP93_LDS_PHASE_INIT(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP93,0x700,8)
#define BRPHY2_BR_CTRL_EXP93_LDS_PHASE_INIT_MASK                   0x0700
#define BRPHY2_BR_CTRL_EXP93_LDS_PHASE_INIT_ALIGN                  0
#define BRPHY2_BR_CTRL_EXP93_LDS_PHASE_INIT_BITS                   3
#define BRPHY2_BR_CTRL_EXP93_LDS_PHASE_INIT_SHIFT                  8

/* BRPHY2_BR_CTRL :: EXP93 :: LDS_PEAK_THR [07:00] */
#define Wr_BRPHY2_BR_CTRL_EXP93_LDS_PEAK_THR(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP93,0xff,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP93_LDS_PEAK_THR(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP93,0xff,0)
#define BRPHY2_BR_CTRL_EXP93_LDS_PEAK_THR_MASK                     0x00ff
#define BRPHY2_BR_CTRL_EXP93_LDS_PEAK_THR_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP93_LDS_PEAK_THR_BITS                     8
#define BRPHY2_BR_CTRL_EXP93_LDS_PEAK_THR_SHIFT                    0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP94
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP94 :: LDS_LEN_THR1 [15:08] */
#define Wr_BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR1(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP94,0xff00,8,x)
#define Rd_BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR1(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP94,0xff00,8)
#define BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR1_MASK                     0xff00
#define BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR1_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR1_BITS                     8
#define BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR1_SHIFT                    8

/* BRPHY2_BR_CTRL :: EXP94 :: LDS_LEN_THR0 [07:00] */
#define Wr_BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR0(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP94,0xff,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR0(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP94,0xff,0)
#define BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR0_MASK                     0x00ff
#define BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR0_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR0_BITS                     8
#define BRPHY2_BR_CTRL_EXP94_LDS_LEN_THR0_SHIFT                    0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP95
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP95 :: LDS_LEN_THR3 [15:08] */
#define Wr_BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR3(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP95,0xff00,8,x)
#define Rd_BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR3(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP95,0xff00,8)
#define BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR3_MASK                     0xff00
#define BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR3_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR3_BITS                     8
#define BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR3_SHIFT                    8

/* BRPHY2_BR_CTRL :: EXP95 :: LDS_LEN_THR2 [07:00] */
#define Wr_BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR2(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP95,0xff,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR2(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP95,0xff,0)
#define BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR2_MASK                     0x00ff
#define BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR2_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR2_BITS                     8
#define BRPHY2_BR_CTRL_EXP95_LDS_LEN_THR2_SHIFT                    0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP96
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP96 :: LDS_TONE_FREQ [15:15] */
#define Wr_BRPHY2_BR_CTRL_EXP96_LDS_TONE_FREQ(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP96,0x8000,15,x)
#define Rd_BRPHY2_BR_CTRL_EXP96_LDS_TONE_FREQ(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP96,0x8000,15)
#define BRPHY2_BR_CTRL_EXP96_LDS_TONE_FREQ_MASK                    0x8000
#define BRPHY2_BR_CTRL_EXP96_LDS_TONE_FREQ_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP96_LDS_TONE_FREQ_BITS                    1
#define BRPHY2_BR_CTRL_EXP96_LDS_TONE_FREQ_SHIFT                   15

/* BRPHY2_BR_CTRL :: EXP96 :: LDS_EXT_AB_DWNGRD [14:14] */
#define Wr_BRPHY2_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP96,0x4000,14,x)
#define Rd_BRPHY2_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP96,0x4000,14)
#define BRPHY2_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_MASK                0x4000
#define BRPHY2_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_ALIGN               0
#define BRPHY2_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_BITS                1
#define BRPHY2_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_SHIFT               14

/* BRPHY2_BR_CTRL :: EXP96 :: LDS_SCAN_FSM [13:12] */
#define Wr_BRPHY2_BR_CTRL_EXP96_LDS_SCAN_FSM(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP96,0x3000,12,x)
#define Rd_BRPHY2_BR_CTRL_EXP96_LDS_SCAN_FSM(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP96,0x3000,12)
#define BRPHY2_BR_CTRL_EXP96_LDS_SCAN_FSM_MASK                     0x3000
#define BRPHY2_BR_CTRL_EXP96_LDS_SCAN_FSM_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP96_LDS_SCAN_FSM_BITS                     2
#define BRPHY2_BR_CTRL_EXP96_LDS_SCAN_FSM_SHIFT                    12

/* BRPHY2_BR_CTRL :: EXP96 :: CUR_LOC_FNUM [11:04] */
#define Wr_BRPHY2_BR_CTRL_EXP96_CUR_LOC_FNUM(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP96,0xff0,4,x)
#define Rd_BRPHY2_BR_CTRL_EXP96_CUR_LOC_FNUM(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP96,0xff0,4)
#define BRPHY2_BR_CTRL_EXP96_CUR_LOC_FNUM_MASK                     0x0ff0
#define BRPHY2_BR_CTRL_EXP96_CUR_LOC_FNUM_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP96_CUR_LOC_FNUM_BITS                     8
#define BRPHY2_BR_CTRL_EXP96_CUR_LOC_FNUM_SHIFT                    4

/* BRPHY2_BR_CTRL :: EXP96 :: LDS_SPD [03:00] */
#define Wr_BRPHY2_BR_CTRL_EXP96_LDS_SPD(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP96,0xf,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP96_LDS_SPD(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP96,0xf,0)
#define BRPHY2_BR_CTRL_EXP96_LDS_SPD_MASK                          0x000f
#define BRPHY2_BR_CTRL_EXP96_LDS_SPD_ALIGN                         0
#define BRPHY2_BR_CTRL_EXP96_LDS_SPD_BITS                          4
#define BRPHY2_BR_CTRL_EXP96_LDS_SPD_SHIFT                         0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP97
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP97 :: LDS_TX_FSM_H [15:12] */
#define Wr_BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_H(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP97,0xf000,12,x)
#define Rd_BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_H(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP97,0xf000,12)
#define BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_H_MASK                     0xf000
#define BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_H_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_H_BITS                     4
#define BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_H_SHIFT                    12

/* BRPHY2_BR_CTRL :: EXP97 :: LDS_TX_FSM_L [11:08] */
#define Wr_BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_L(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP97,0xf00,8,x)
#define Rd_BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_L(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP97,0xf00,8)
#define BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_L_MASK                     0x0f00
#define BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_L_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_L_BITS                     4
#define BRPHY2_BR_CTRL_EXP97_LDS_TX_FSM_L_SHIFT                    8

/* BRPHY2_BR_CTRL :: EXP97 :: LDS_ARB_FSM_H [07:04] */
#define Wr_BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP97,0xf0,4,x)
#define Rd_BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP97,0xf0,4)
#define BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_H_MASK                    0x00f0
#define BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_H_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_H_BITS                    4
#define BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_H_SHIFT                   4

/* BRPHY2_BR_CTRL :: EXP97 :: LDS_ARB_FSM_L [03:00] */
#define Wr_BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP97,0xf,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP97,0xf,0)
#define BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_L_MASK                    0x000f
#define BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_L_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_L_BITS                    4
#define BRPHY2_BR_CTRL_EXP97_LDS_ARB_FSM_L_SHIFT                   0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP99
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP99 :: LDS_PGACTRL [15:10] */
#define Wr_BRPHY2_BR_CTRL_EXP99_LDS_PGACTRL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP99,0xfc00,10,x)
#define Rd_BRPHY2_BR_CTRL_EXP99_LDS_PGACTRL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP99,0xfc00,10)
#define BRPHY2_BR_CTRL_EXP99_LDS_PGACTRL_MASK                      0xfc00
#define BRPHY2_BR_CTRL_EXP99_LDS_PGACTRL_ALIGN                     0
#define BRPHY2_BR_CTRL_EXP99_LDS_PGACTRL_BITS                      6
#define BRPHY2_BR_CTRL_EXP99_LDS_PGACTRL_SHIFT                     10

/* BRPHY2_BR_CTRL :: EXP99 :: TXDIS_TMR_OPT [09:07] */
#define Wr_BRPHY2_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP99,0x380,7,x)
#define Rd_BRPHY2_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP99,0x380,7)
#define BRPHY2_BR_CTRL_EXP99_TXDIS_TMR_OPT_MASK                    0x0380
#define BRPHY2_BR_CTRL_EXP99_TXDIS_TMR_OPT_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP99_TXDIS_TMR_OPT_BITS                    3
#define BRPHY2_BR_CTRL_EXP99_TXDIS_TMR_OPT_SHIFT                   7

/* BRPHY2_BR_CTRL :: EXP99 :: LNK_TMR_OPT [06:04] */
#define Wr_BRPHY2_BR_CTRL_EXP99_LNK_TMR_OPT(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP99,0x70,4,x)
#define Rd_BRPHY2_BR_CTRL_EXP99_LNK_TMR_OPT(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP99,0x70,4)
#define BRPHY2_BR_CTRL_EXP99_LNK_TMR_OPT_MASK                      0x0070
#define BRPHY2_BR_CTRL_EXP99_LNK_TMR_OPT_ALIGN                     0
#define BRPHY2_BR_CTRL_EXP99_LNK_TMR_OPT_BITS                      3
#define BRPHY2_BR_CTRL_EXP99_LNK_TMR_OPT_SHIFT                     4

/* BRPHY2_BR_CTRL :: EXP99 :: BST_TMR_OPT [03:01] */
#define Wr_BRPHY2_BR_CTRL_EXP99_BST_TMR_OPT(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP99,0xe,1,x)
#define Rd_BRPHY2_BR_CTRL_EXP99_BST_TMR_OPT(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP99,0xe,1)
#define BRPHY2_BR_CTRL_EXP99_BST_TMR_OPT_MASK                      0x000e
#define BRPHY2_BR_CTRL_EXP99_BST_TMR_OPT_ALIGN                     0
#define BRPHY2_BR_CTRL_EXP99_BST_TMR_OPT_BITS                      3
#define BRPHY2_BR_CTRL_EXP99_BST_TMR_OPT_SHIFT                     1

/* BRPHY2_BR_CTRL :: EXP99 :: FASTBST [00:00] */
#define Wr_BRPHY2_BR_CTRL_EXP99_FASTBST(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP99,0x1,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP99_FASTBST(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP99,0x1,0)
#define BRPHY2_BR_CTRL_EXP99_FASTBST_MASK                          0x0001
#define BRPHY2_BR_CTRL_EXP99_FASTBST_ALIGN                         0
#define BRPHY2_BR_CTRL_EXP99_FASTBST_BITS                          1
#define BRPHY2_BR_CTRL_EXP99_FASTBST_SHIFT                         0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP9A
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP9A :: LRE_REG_OV_EN [15:15] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x8000,15,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x8000,15)
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_EN_MASK                    0x8000
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_EN_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_EN_BITS                    1
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_EN_SHIFT                   15

/* BRPHY2_BR_CTRL :: EXP9A :: LRE_REG_OV_VAL [14:14] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x4000,14,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x4000,14)
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_VAL_MASK                   0x4000
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_VAL_ALIGN                  0
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_VAL_BITS                   1
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_OV_VAL_SHIFT                  14

/* BRPHY2_BR_CTRL :: EXP9A :: LRE_REG_ACCESS_STAT [13:13] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x2000,13,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x2000,13)
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_MASK              0x2000
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_ALIGN             0
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_BITS              1
#define BRPHY2_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_SHIFT             13

/* BRPHY2_BR_CTRL :: EXP9A :: LDS_LINK_CHK_EN [12:12] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x1000,12,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x1000,12)
#define BRPHY2_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_MASK                  0x1000
#define BRPHY2_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_ALIGN                 0
#define BRPHY2_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_BITS                  1
#define BRPHY2_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_SHIFT                 12

/* BRPHY2_BR_CTRL :: EXP9A :: BR_AGC_TAR_OV_EN [11:11] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x800,11,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x800,11)
#define BRPHY2_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_MASK                 0x0800
#define BRPHY2_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_ALIGN                0
#define BRPHY2_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_BITS                 1
#define BRPHY2_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_SHIFT                11

/* BRPHY2_BR_CTRL :: EXP9A :: LDS_TIMER_OV_EN [10:10] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x400,10,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x400,10)
#define BRPHY2_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_MASK                  0x0400
#define BRPHY2_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_ALIGN                 0
#define BRPHY2_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_BITS                  1
#define BRPHY2_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_SHIFT                 10

/* BRPHY2_BR_CTRL :: EXP9A :: BR_LOST_TOKEN_FIX [09:09] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x200,9,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x200,9)
#define BRPHY2_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_MASK                0x0200
#define BRPHY2_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_ALIGN               0
#define BRPHY2_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_BITS                1
#define BRPHY2_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_SHIFT               9

/* BRPHY2_BR_CTRL :: EXP9A :: DLLCONV_EN_MSTR [08:08] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x100,8,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x100,8)
#define BRPHY2_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_MASK                  0x0100
#define BRPHY2_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_ALIGN                 0
#define BRPHY2_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_BITS                  1
#define BRPHY2_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_SHIFT                 8

/* BRPHY2_BR_CTRL :: EXP9A :: BR_10M1P_HALFOUT_EN [07:07] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x80,7,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x80,7)
#define BRPHY2_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_MASK              0x0080
#define BRPHY2_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_ALIGN             0
#define BRPHY2_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_BITS              1
#define BRPHY2_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_SHIFT             7

/* BRPHY2_BR_CTRL :: EXP9A :: BR_10M2P_HALFOUT_EN [06:06] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x40,6,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x40,6)
#define BRPHY2_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_MASK              0x0040
#define BRPHY2_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_ALIGN             0
#define BRPHY2_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_BITS              1
#define BRPHY2_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_SHIFT             6

/* BRPHY2_BR_CTRL :: EXP9A :: BR_HALFOUT_EN [05:05] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x20,5,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x20,5)
#define BRPHY2_BR_CTRL_EXP9A_BR_HALFOUT_EN_MASK                    0x0020
#define BRPHY2_BR_CTRL_EXP9A_BR_HALFOUT_EN_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP9A_BR_HALFOUT_EN_BITS                    1
#define BRPHY2_BR_CTRL_EXP9A_BR_HALFOUT_EN_SHIFT                   5

/* BRPHY2_BR_CTRL :: EXP9A :: CLK100T_ECO_DIS [04:04] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0x10,4,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0x10,4)
#define BRPHY2_BR_CTRL_EXP9A_CLK100T_ECO_DIS_MASK                  0x0010
#define BRPHY2_BR_CTRL_EXP9A_CLK100T_ECO_DIS_ALIGN                 0
#define BRPHY2_BR_CTRL_EXP9A_CLK100T_ECO_DIS_BITS                  1
#define BRPHY2_BR_CTRL_EXP9A_CLK100T_ECO_DIS_SHIFT                 4

/* BRPHY2_BR_CTRL :: EXP9A :: CH_STATUS [03:00] */
#define Wr_BRPHY2_BR_CTRL_EXP9A_CH_STATUS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9A,0xf,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP9A_CH_STATUS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9A,0xf,0)
#define BRPHY2_BR_CTRL_EXP9A_CH_STATUS_MASK                        0x000f
#define BRPHY2_BR_CTRL_EXP9A_CH_STATUS_ALIGN                       0
#define BRPHY2_BR_CTRL_EXP9A_CH_STATUS_BITS                        4
#define BRPHY2_BR_CTRL_EXP9A_CH_STATUS_SHIFT                       0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP9B
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP9B :: BR_RATE_OV [15:13] */
#define Wr_BRPHY2_BR_CTRL_EXP9B_BR_RATE_OV(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9B,0xe000,13,x)
#define Rd_BRPHY2_BR_CTRL_EXP9B_BR_RATE_OV(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9B,0xe000,13)
#define BRPHY2_BR_CTRL_EXP9B_BR_RATE_OV_MASK                       0xe000
#define BRPHY2_BR_CTRL_EXP9B_BR_RATE_OV_ALIGN                      0
#define BRPHY2_BR_CTRL_EXP9B_BR_RATE_OV_BITS                       3
#define BRPHY2_BR_CTRL_EXP9B_BR_RATE_OV_SHIFT                      13

/* BRPHY2_BR_CTRL :: EXP9B :: BR_200MBPS_CLK_EN [12:12] */
#define Wr_BRPHY2_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9B,0x1000,12,x)
#define Rd_BRPHY2_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9B,0x1000,12)
#define BRPHY2_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_MASK                0x1000
#define BRPHY2_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_ALIGN               0
#define BRPHY2_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_BITS                1
#define BRPHY2_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_SHIFT               12

/* BRPHY2_BR_CTRL :: EXP9B :: BR_TXCLK_EN [11:11] */
#define Wr_BRPHY2_BR_CTRL_EXP9B_BR_TXCLK_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9B,0x800,11,x)
#define Rd_BRPHY2_BR_CTRL_EXP9B_BR_TXCLK_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9B,0x800,11)
#define BRPHY2_BR_CTRL_EXP9B_BR_TXCLK_EN_MASK                      0x0800
#define BRPHY2_BR_CTRL_EXP9B_BR_TXCLK_EN_ALIGN                     0
#define BRPHY2_BR_CTRL_EXP9B_BR_TXCLK_EN_BITS                      1
#define BRPHY2_BR_CTRL_EXP9B_BR_TXCLK_EN_SHIFT                     11

/* BRPHY2_BR_CTRL :: EXP9B :: BR_TXRXICLK_EN [10:10] */
#define Wr_BRPHY2_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9B,0x400,10,x)
#define Rd_BRPHY2_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9B,0x400,10)
#define BRPHY2_BR_CTRL_EXP9B_BR_TXRXICLK_EN_MASK                   0x0400
#define BRPHY2_BR_CTRL_EXP9B_BR_TXRXICLK_EN_ALIGN                  0
#define BRPHY2_BR_CTRL_EXP9B_BR_TXRXICLK_EN_BITS                   1
#define BRPHY2_BR_CTRL_EXP9B_BR_TXRXICLK_EN_SHIFT                  10

/* BRPHY2_BR_CTRL :: EXP9B :: CLK_1G_DIV20 [09:09] */
#define Wr_BRPHY2_BR_CTRL_EXP9B_CLK_1G_DIV20(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9B,0x200,9,x)
#define Rd_BRPHY2_BR_CTRL_EXP9B_CLK_1G_DIV20(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9B,0x200,9)
#define BRPHY2_BR_CTRL_EXP9B_CLK_1G_DIV20_MASK                     0x0200
#define BRPHY2_BR_CTRL_EXP9B_CLK_1G_DIV20_ALIGN                    0
#define BRPHY2_BR_CTRL_EXP9B_CLK_1G_DIV20_BITS                     1
#define BRPHY2_BR_CTRL_EXP9B_CLK_1G_DIV20_SHIFT                    9

/* BRPHY2_BR_CTRL :: EXP9B :: LVL1_PROG_FREQ_DIV [08:05] */
#define Wr_BRPHY2_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9B,0x1e0,5,x)
#define Rd_BRPHY2_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9B,0x1e0,5)
#define BRPHY2_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_MASK               0x01e0
#define BRPHY2_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_ALIGN              0
#define BRPHY2_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_BITS               4
#define BRPHY2_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_SHIFT              5

/* BRPHY2_BR_CTRL :: EXP9B :: LVL2_PROG_FREQ_DIV [04:01] */
#define Wr_BRPHY2_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9B,0x1e,1,x)
#define Rd_BRPHY2_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9B,0x1e,1)
#define BRPHY2_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_MASK               0x001e
#define BRPHY2_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_ALIGN              0
#define BRPHY2_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_BITS               4
#define BRPHY2_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_SHIFT              1

/* BRPHY2_BR_CTRL :: EXP9B :: BR_PLL_CTL_EN [00:00] */
#define Wr_BRPHY2_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9B,0x1,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9B,0x1,0)
#define BRPHY2_BR_CTRL_EXP9B_BR_PLL_CTL_EN_MASK                    0x0001
#define BRPHY2_BR_CTRL_EXP9B_BR_PLL_CTL_EN_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP9B_BR_PLL_CTL_EN_BITS                    1
#define BRPHY2_BR_CTRL_EXP9B_BR_PLL_CTL_EN_SHIFT                   0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP9D
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP9D :: BR_IPR_BYPASS [15:15] */
#define Wr_BRPHY2_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9D,0x8000,15,x)
#define Rd_BRPHY2_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9D,0x8000,15)
#define BRPHY2_BR_CTRL_EXP9D_BR_IPR_BYPASS_MASK                    0x8000
#define BRPHY2_BR_CTRL_EXP9D_BR_IPR_BYPASS_ALIGN                   0
#define BRPHY2_BR_CTRL_EXP9D_BR_IPR_BYPASS_BITS                    1
#define BRPHY2_BR_CTRL_EXP9D_BR_IPR_BYPASS_SHIFT                   15

/* BRPHY2_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_VAL [14:14] */
#define Wr_BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9D,0x4000,14,x)
#define Rd_BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9D,0x4000,14)
#define BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_MASK               0x4000
#define BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_ALIGN              0
#define BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_BITS               1
#define BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_SHIFT              14

/* BRPHY2_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_EN [13:13] */
#define Wr_BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9D,0x2000,13,x)
#define Rd_BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9D,0x2000,13)
#define BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_MASK                0x2000
#define BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_ALIGN               0
#define BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_BITS                1
#define BRPHY2_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_SHIFT               13

/* BRPHY2_BR_CTRL :: EXP9D :: LDS_SD_THR [12:08] */
#define Wr_BRPHY2_BR_CTRL_EXP9D_LDS_SD_THR(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9D,0x1f00,8,x)
#define Rd_BRPHY2_BR_CTRL_EXP9D_LDS_SD_THR(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9D,0x1f00,8)
#define BRPHY2_BR_CTRL_EXP9D_LDS_SD_THR_MASK                       0x1f00
#define BRPHY2_BR_CTRL_EXP9D_LDS_SD_THR_ALIGN                      0
#define BRPHY2_BR_CTRL_EXP9D_LDS_SD_THR_BITS                       5
#define BRPHY2_BR_CTRL_EXP9D_LDS_SD_THR_SHIFT                      8

/* BRPHY2_BR_CTRL :: EXP9D :: LDS_PEAK_THR_T125 [07:00] */
#define Wr_BRPHY2_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9D,0xff,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9D,0xff,0)
#define BRPHY2_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_MASK                0x00ff
#define BRPHY2_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_ALIGN               0
#define BRPHY2_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_BITS                8
#define BRPHY2_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_SHIFT               0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP9E
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP9E :: LDS_LEN_THR1_T125 [15:08] */
#define Wr_BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9E,0xff00,8,x)
#define Rd_BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9E,0xff00,8)
#define BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_MASK                0xff00
#define BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_ALIGN               0
#define BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_BITS                8
#define BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_SHIFT               8

/* BRPHY2_BR_CTRL :: EXP9E :: LDS_LEN_THR0_T125 [07:00] */
#define Wr_BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9E,0xff,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9E,0xff,0)
#define BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_MASK                0x00ff
#define BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_ALIGN               0
#define BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_BITS                8
#define BRPHY2_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_SHIFT               0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXP9F
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXP9F :: LDS_LEN_THR3_T125 [15:08] */
#define Wr_BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9F,0xff00,8,x)
#define Rd_BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9F,0xff00,8)
#define BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_MASK                0xff00
#define BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_ALIGN               0
#define BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_BITS                8
#define BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_SHIFT               8

/* BRPHY2_BR_CTRL :: EXP9F :: LDS_LEN_THR2_T125 [07:00] */
#define Wr_BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) WriteRegBits16(BRPHY2_BR_CTRL_EXP9F,0xff,0,x)
#define Rd_BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) ReadRegBits16(BRPHY2_BR_CTRL_EXP9F,0xff,0)
#define BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_MASK                0x00ff
#define BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_ALIGN               0
#define BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_BITS                8
#define BRPHY2_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_SHIFT               0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXPA0
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXPA0 :: EPAGE_SPARE [15:02] */
#define Wr_BRPHY2_BR_CTRL_EXPA0_EPAGE_SPARE(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA0,0xfffc,2,x)
#define Rd_BRPHY2_BR_CTRL_EXPA0_EPAGE_SPARE(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA0,0xfffc,2)
#define BRPHY2_BR_CTRL_EXPA0_EPAGE_SPARE_MASK                      0xfffc
#define BRPHY2_BR_CTRL_EXPA0_EPAGE_SPARE_ALIGN                     0
#define BRPHY2_BR_CTRL_EXPA0_EPAGE_SPARE_BITS                      14
#define BRPHY2_BR_CTRL_EXPA0_EPAGE_SPARE_SHIFT                     2

/* BRPHY2_BR_CTRL :: EXPA0 :: PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY2_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA0,0x2,1,x)
#define Rd_BRPHY2_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA0,0x2,1)
#define BRPHY2_BR_CTRL_EXPA0_PAIR_1_250MBPS_MASK                   0x0002
#define BRPHY2_BR_CTRL_EXPA0_PAIR_1_250MBPS_ALIGN                  0
#define BRPHY2_BR_CTRL_EXPA0_PAIR_1_250MBPS_BITS                   1
#define BRPHY2_BR_CTRL_EXPA0_PAIR_1_250MBPS_SHIFT                  1

/* BRPHY2_BR_CTRL :: EXPA0 :: PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY2_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA0,0x1,0,x)
#define Rd_BRPHY2_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA0,0x1,0)
#define BRPHY2_BR_CTRL_EXPA0_PAIR_1_200MBPS_MASK                   0x0001
#define BRPHY2_BR_CTRL_EXPA0_PAIR_1_200MBPS_ALIGN                  0
#define BRPHY2_BR_CTRL_EXPA0_PAIR_1_200MBPS_BITS                   1
#define BRPHY2_BR_CTRL_EXPA0_PAIR_1_200MBPS_SHIFT                  0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXPA1
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXPA1 :: LP_EPAGE_SPARE [15:02] */
#define Wr_BRPHY2_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA1,0xfffc,2,x)
#define Rd_BRPHY2_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA1,0xfffc,2)
#define BRPHY2_BR_CTRL_EXPA1_LP_EPAGE_SPARE_MASK                   0xfffc
#define BRPHY2_BR_CTRL_EXPA1_LP_EPAGE_SPARE_ALIGN                  0
#define BRPHY2_BR_CTRL_EXPA1_LP_EPAGE_SPARE_BITS                   14
#define BRPHY2_BR_CTRL_EXPA1_LP_EPAGE_SPARE_SHIFT                  2

/* BRPHY2_BR_CTRL :: EXPA1 :: LP_PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA1,0x2,1,x)
#define Rd_BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA1,0x2,1)
#define BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_MASK                0x0002
#define BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_ALIGN               0
#define BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_BITS                1
#define BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_SHIFT               1

/* BRPHY2_BR_CTRL :: EXPA1 :: LP_PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA1,0x1,0,x)
#define Rd_BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA1,0x1,0)
#define BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_MASK                0x0001
#define BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_ALIGN               0
#define BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_BITS                1
#define BRPHY2_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_SHIFT               0


/****************************************************************************
 * BRPHY2_BR_CTRL :: EXPA2
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV_EN [15:15] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0x8000,15,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0x8000,15)
#define BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_MASK                  0x8000
#define BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_ALIGN                 0
#define BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_BITS                  1
#define BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_SHIFT                 15

/* BRPHY2_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV [14:14] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0x4000,14,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0x4000,14)
#define BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_MASK                     0x4000
#define BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_ALIGN                    0
#define BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_BITS                     1
#define BRPHY2_BR_CTRL_EXPA2_TFREQ_SEL_OV_SHIFT                    14

/* BRPHY2_BR_CTRL :: EXPA2 :: LOW_FREQ_TONE [13:13] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0x2000,13,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0x2000,13)
#define BRPHY2_BR_CTRL_EXPA2_LOW_FREQ_TONE_MASK                    0x2000
#define BRPHY2_BR_CTRL_EXPA2_LOW_FREQ_TONE_ALIGN                   0
#define BRPHY2_BR_CTRL_EXPA2_LOW_FREQ_TONE_BITS                    1
#define BRPHY2_BR_CTRL_EXPA2_LOW_FREQ_TONE_SHIFT                   13

/* BRPHY2_BR_CTRL :: EXPA2 :: BR_MAXWAIT_CTL [12:11] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0x1800,11,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0x1800,11)
#define BRPHY2_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_MASK                   0x1800
#define BRPHY2_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_ALIGN                  0
#define BRPHY2_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_BITS                   2
#define BRPHY2_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_SHIFT                  11

/* BRPHY2_BR_CTRL :: EXPA2 :: BR_M2S2_TMR_CTL [10:10] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0x400,10,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0x400,10)
#define BRPHY2_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_MASK                  0x0400
#define BRPHY2_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_ALIGN                 0
#define BRPHY2_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_BITS                  1
#define BRPHY2_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_SHIFT                 10

/* BRPHY2_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_FDX_S [09:09] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0x200,9,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0x200,9)
#define BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_MASK               0x0200
#define BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_ALIGN              0
#define BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_BITS               1
#define BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_SHIFT              9

/* BRPHY2_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_HDX [08:08] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0x100,8,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0x100,8)
#define BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_MASK                 0x0100
#define BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_ALIGN                0
#define BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_BITS                 1
#define BRPHY2_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_SHIFT                8

/* BRPHY2_BR_CTRL :: EXPA2 :: BR_PSD_TIMER_CTL [07:06] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0xc0,6,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0xc0,6)
#define BRPHY2_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_MASK                 0x00c0
#define BRPHY2_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_ALIGN                0
#define BRPHY2_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_BITS                 2
#define BRPHY2_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_SHIFT                6

/* BRPHY2_BR_CTRL :: EXPA2 :: MAN_PHASE_CK1X [05:03] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0x38,3,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0x38,3)
#define BRPHY2_BR_CTRL_EXPA2_MAN_PHASE_CK1X_MASK                   0x0038
#define BRPHY2_BR_CTRL_EXPA2_MAN_PHASE_CK1X_ALIGN                  0
#define BRPHY2_BR_CTRL_EXPA2_MAN_PHASE_CK1X_BITS                   3
#define BRPHY2_BR_CTRL_EXPA2_MAN_PHASE_CK1X_SHIFT                  3

/* BRPHY2_BR_CTRL :: EXPA2 :: LDS_PHASE_CK1X [02:00] */
#define Wr_BRPHY2_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) WriteRegBits16(BRPHY2_BR_CTRL_EXPA2,0x7,0,x)
#define Rd_BRPHY2_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) ReadRegBits16(BRPHY2_BR_CTRL_EXPA2,0x7,0)
#define BRPHY2_BR_CTRL_EXPA2_LDS_PHASE_CK1X_MASK                   0x0007
#define BRPHY2_BR_CTRL_EXPA2_LDS_PHASE_CK1X_ALIGN                  0
#define BRPHY2_BR_CTRL_EXPA2_LDS_PHASE_CK1X_BITS                   3
#define BRPHY2_BR_CTRL_EXPA2_LDS_PHASE_CK1X_SHIFT                  0


/****************************************************************************
 * BRPHY2_BR_CTRL :: BR_MISC_CONTROL_STATUS
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_2ND_FILTER [15:15] */
#define Wr_BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) WriteRegBits16(BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15,x)
#define Rd_BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) ReadRegBits16(BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15)
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_MASK 0x8000
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_ALIGN 0
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_BITS 1
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_SHIFT 15

/* BRPHY2_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_PR_DATAPATH [14:14] */
#define Wr_BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) WriteRegBits16(BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14,x)
#define Rd_BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) ReadRegBits16(BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14)
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_MASK 0x4000
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_ALIGN 0
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_BITS 1
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_SHIFT 14

/* BRPHY2_BR_CTRL :: BR_MISC_CONTROL_STATUS :: reserved0 [13:03] */
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_MASK       0x3ff8
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_ALIGN      0
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_BITS       11
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_SHIFT      3

/* BRPHY2_BR_CTRL :: BR_MISC_CONTROL_STATUS :: BR_1P_PCS_SOL [02:00] */
#define Wr_BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) WriteRegBits16(BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0,x)
#define Rd_BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) ReadRegBits16(BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0)
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_MASK   0x0007
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_ALIGN  0
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_BITS   3
#define BRPHY2_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_SHIFT  0


/****************************************************************************
 * BRPHY2_BR_CTRL :: BR250_CTL
 ***************************************************************************/
/* BRPHY2_BR_CTRL :: BR250_CTL :: BR_CURR_RATE [15:12] */
#define Wr_BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) WriteRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0xf000,12,x)
#define Rd_BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) ReadRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0xf000,12)
#define BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_RATE_MASK                 0xf000
#define BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_RATE_ALIGN                0
#define BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_RATE_BITS                 4
#define BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_RATE_SHIFT                12

/* BRPHY2_BR_CTRL :: BR250_CTL :: BR_CURR_PAIR [11:10] */
#define Wr_BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) WriteRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0xc00,10,x)
#define Rd_BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) ReadRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0xc00,10)
#define BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_PAIR_MASK                 0x0c00
#define BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_PAIR_ALIGN                0
#define BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_PAIR_BITS                 2
#define BRPHY2_BR_CTRL_BR250_CTL_BR_CURR_PAIR_SHIFT                10

/* BRPHY2_BR_CTRL :: BR250_CTL :: reserved0 [09:08] */
#define BRPHY2_BR_CTRL_BR250_CTL_RESERVED0_MASK                    0x0300
#define BRPHY2_BR_CTRL_BR250_CTL_RESERVED0_ALIGN                   0
#define BRPHY2_BR_CTRL_BR250_CTL_RESERVED0_BITS                    2
#define BRPHY2_BR_CTRL_BR250_CTL_RESERVED0_SHIFT                   8

/* BRPHY2_BR_CTRL :: BR250_CTL :: BR_PAM5_200_sel [07:07] */
#define Wr_BRPHY2_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) WriteRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0x80,7,x)
#define Rd_BRPHY2_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) ReadRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0x80,7)
#define BRPHY2_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_MASK              0x0080
#define BRPHY2_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_ALIGN             0
#define BRPHY2_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_BITS              1
#define BRPHY2_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_SHIFT             7

/* BRPHY2_BR_CTRL :: BR250_CTL :: LBKTst2 [06:06] */
#define Wr_BRPHY2_BR_CTRL_BR250_CTL_LBKTst2(x) WriteRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0x40,6,x)
#define Rd_BRPHY2_BR_CTRL_BR250_CTL_LBKTst2(x) ReadRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0x40,6)
#define BRPHY2_BR_CTRL_BR250_CTL_LBKTST2_MASK                      0x0040
#define BRPHY2_BR_CTRL_BR250_CTL_LBKTST2_ALIGN                     0
#define BRPHY2_BR_CTRL_BR250_CTL_LBKTST2_BITS                      1
#define BRPHY2_BR_CTRL_BR250_CTL_LBKTST2_SHIFT                     6

/* BRPHY2_BR_CTRL :: BR250_CTL :: CONF_GPLL_125 [05:05] */
#define Wr_BRPHY2_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) WriteRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0x20,5,x)
#define Rd_BRPHY2_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) ReadRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0x20,5)
#define BRPHY2_BR_CTRL_BR250_CTL_CONF_GPLL_125_MASK                0x0020
#define BRPHY2_BR_CTRL_BR250_CTL_CONF_GPLL_125_ALIGN               0
#define BRPHY2_BR_CTRL_BR250_CTL_CONF_GPLL_125_BITS                1
#define BRPHY2_BR_CTRL_BR250_CTL_CONF_GPLL_125_SHIFT               5

/* BRPHY2_BR_CTRL :: BR250_CTL :: reserved1 [04:04] */
#define BRPHY2_BR_CTRL_BR250_CTL_RESERVED1_MASK                    0x0010
#define BRPHY2_BR_CTRL_BR250_CTL_RESERVED1_ALIGN                   0
#define BRPHY2_BR_CTRL_BR250_CTL_RESERVED1_BITS                    1
#define BRPHY2_BR_CTRL_BR250_CTL_RESERVED1_SHIFT                   4

/* BRPHY2_BR_CTRL :: BR250_CTL :: INTRLV_CTL [03:02] */
#define Wr_BRPHY2_BR_CTRL_BR250_CTL_INTRLV_CTL(x) WriteRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0xc,2,x)
#define Rd_BRPHY2_BR_CTRL_BR250_CTL_INTRLV_CTL(x) ReadRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0xc,2)
#define BRPHY2_BR_CTRL_BR250_CTL_INTRLV_CTL_MASK                   0x000c
#define BRPHY2_BR_CTRL_BR250_CTL_INTRLV_CTL_ALIGN                  0
#define BRPHY2_BR_CTRL_BR250_CTL_INTRLV_CTL_BITS                   2
#define BRPHY2_BR_CTRL_BR250_CTL_INTRLV_CTL_SHIFT                  2

/* BRPHY2_BR_CTRL :: BR250_CTL :: PAIR_CFG [01:00] */
#define Wr_BRPHY2_BR_CTRL_BR250_CTL_PAIR_CFG(x) WriteRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0x3,0,x)
#define Rd_BRPHY2_BR_CTRL_BR250_CTL_PAIR_CFG(x) ReadRegBits16(BRPHY2_BR_CTRL_BR250_CTL,0x3,0)
#define BRPHY2_BR_CTRL_BR250_CTL_PAIR_CFG_MASK                     0x0003
#define BRPHY2_BR_CTRL_BR250_CTL_PAIR_CFG_ALIGN                    0
#define BRPHY2_BR_CTRL_BR250_CTL_PAIR_CFG_BITS                     2
#define BRPHY2_BR_CTRL_BR250_CTL_PAIR_CFG_SHIFT                    0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys2_BRPHY2_BR_CL22_IEEE
 ***************************************************************************/
/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: MII_CTRL
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: RESET [15:15] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_RESET(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x8000,15,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_RESET(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x8000,15)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESET_MASK                    0x8000
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESET_ALIGN                   0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESET_BITS                    1
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESET_SHIFT                   15

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: LOOPBACK [14:14] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x4000,14,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x4000,14)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_LOOPBACK_MASK                 0x4000
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_LOOPBACK_ALIGN                0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_LOOPBACK_BITS                 1
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_LOOPBACK_SHIFT                14

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: RESTART_LDS [13:13] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x2000,13,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x2000,13)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_MASK              0x2000
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_ALIGN             0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_BITS              1
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_SHIFT             13

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: LDS_ENABLE [12:12] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x1000,12,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x1000,12)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_MASK               0x1000
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_ALIGN              0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_BITS               1
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_SHIFT              12

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: POWER_DOWN [11:11] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x800,11,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x800,11)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_MASK               0x0800
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_ALIGN              0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_BITS               1
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_SHIFT              11

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: ISOLATE [10:10] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x400,10,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x400,10)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_ISOLATE_MASK                  0x0400
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_ISOLATE_ALIGN                 0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_ISOLATE_BITS                  1
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_ISOLATE_SHIFT                 10

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: manual_speed_select_enable [09:09] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x200,9,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x200,9)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_MASK 0x0200
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_BITS 1
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_SHIFT 9

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: Speed_Selection [08:06] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x1c0,6,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x1c0,6)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_MASK          0x01c0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_ALIGN         0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_BITS          3
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_SHIFT         6

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: Pair_Selection [05:04] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x30,4,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x30,4)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_MASK           0x0030
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_ALIGN          0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_BITS           2
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_SHIFT          4

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: Master_mode [03:03] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_Master_mode(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x8,3,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_Master_mode(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x8,3)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_MASK              0x0008
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_ALIGN             0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_BITS              1
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_SHIFT             3

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: Unidirection_Enable [02:02] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x4,2,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_CTRL,0x4,2)
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_MASK      0x0004
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_ALIGN     0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_BITS      1
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_SHIFT     2

/* BRPHY2_BR_CL22_IEEE :: MII_CTRL :: reserved0 [01:00] */
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESERVED0_MASK                0x0003
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESERVED0_ALIGN               0
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESERVED0_BITS                2
#define BRPHY2_BR_CL22_IEEE_MII_CTRL_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: MII_STAT
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: MII_STAT :: reserved0 [15:15] */
#define BRPHY2_BR_CL22_IEEE_MII_STAT_RESERVED0_MASK                0x8000
#define BRPHY2_BR_CL22_IEEE_MII_STAT_RESERVED0_ALIGN               0
#define BRPHY2_BR_CL22_IEEE_MII_STAT_RESERVED0_BITS                1
#define BRPHY2_BR_CL22_IEEE_MII_STAT_RESERVED0_SHIFT               15

/* BRPHY2_BR_CL22_IEEE :: MII_STAT :: Capability [14:09] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_STAT_Capability(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x7e00,9,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_STAT_Capability(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x7e00,9)
#define BRPHY2_BR_CL22_IEEE_MII_STAT_CAPABILITY_MASK               0x7e00
#define BRPHY2_BR_CL22_IEEE_MII_STAT_CAPABILITY_ALIGN              0
#define BRPHY2_BR_CL22_IEEE_MII_STAT_CAPABILITY_BITS               6
#define BRPHY2_BR_CL22_IEEE_MII_STAT_CAPABILITY_SHIFT              9

/* BRPHY2_BR_CL22_IEEE :: MII_STAT :: EXTENDED_STAT [08:06] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x1c0,6,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x1c0,6)
#define BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_MASK            0x01c0
#define BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_ALIGN           0
#define BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_BITS            3
#define BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_SHIFT           6

/* BRPHY2_BR_CL22_IEEE :: MII_STAT :: LDS_complete [05:05] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_STAT_LDS_complete(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x20,5,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_STAT_LDS_complete(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x20,5)
#define BRPHY2_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_MASK             0x0020
#define BRPHY2_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_ALIGN            0
#define BRPHY2_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_BITS             1
#define BRPHY2_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_SHIFT            5

/* BRPHY2_BR_CL22_IEEE :: MII_STAT :: reserved1 [04:03] */
#define BRPHY2_BR_CL22_IEEE_MII_STAT_RESERVED1_MASK                0x0018
#define BRPHY2_BR_CL22_IEEE_MII_STAT_RESERVED1_ALIGN               0
#define BRPHY2_BR_CL22_IEEE_MII_STAT_RESERVED1_BITS                2
#define BRPHY2_BR_CL22_IEEE_MII_STAT_RESERVED1_SHIFT               3

/* BRPHY2_BR_CL22_IEEE :: MII_STAT :: LNK_STAT [02:02] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x4,2,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x4,2)
#define BRPHY2_BR_CL22_IEEE_MII_STAT_LNK_STAT_MASK                 0x0004
#define BRPHY2_BR_CL22_IEEE_MII_STAT_LNK_STAT_ALIGN                0
#define BRPHY2_BR_CL22_IEEE_MII_STAT_LNK_STAT_BITS                 1
#define BRPHY2_BR_CL22_IEEE_MII_STAT_LNK_STAT_SHIFT                2

/* BRPHY2_BR_CL22_IEEE :: MII_STAT :: JABBER_DETECT [01:01] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x2,1,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x2,1)
#define BRPHY2_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_MASK            0x0002
#define BRPHY2_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_ALIGN           0
#define BRPHY2_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_BITS            1
#define BRPHY2_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_SHIFT           1

/* BRPHY2_BR_CL22_IEEE :: MII_STAT :: EXTENDED_CAPABILITY [00:00] */
#define Wr_BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x1,0,x)
#define Rd_BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_MII_STAT,0x1,0)
#define BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_MASK      0x0001
#define BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_ALIGN     0
#define BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_BITS      1
#define BRPHY2_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_SHIFT     0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: PHY_ID_MSB
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: PHY_ID_MSB :: OUI_MSB [15:00] */
#define Wr_BRPHY2_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) WriteReg16(BRPHY2_BR_CL22_IEEE_PHY_ID_MSB,x)
#define Rd_BRPHY2_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) ReadReg16(BRPHY2_BR_CL22_IEEE_PHY_ID_MSB)
#define BRPHY2_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_MASK                0xffff
#define BRPHY2_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_ALIGN               0
#define BRPHY2_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_BITS                16
#define BRPHY2_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_SHIFT               0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: PHY_ID_LSB
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: PHY_ID_LSB :: OUI_LSB [15:10] */
#define Wr_BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10,x)
#define Rd_BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10)
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_MASK                0xfc00
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_ALIGN               0
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_BITS                6
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_SHIFT               10

/* BRPHY2_BR_CL22_IEEE :: PHY_ID_LSB :: MODEL [09:04] */
#define Wr_BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4,x)
#define Rd_BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4)
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_MODEL_MASK                  0x03f0
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_MODEL_ALIGN                 0
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_MODEL_BITS                  6
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_MODEL_SHIFT                 4

/* BRPHY2_BR_CL22_IEEE :: PHY_ID_LSB :: REVISION [03:00] */
#define Wr_BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_PHY_ID_LSB,0xf,0,x)
#define Rd_BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_PHY_ID_LSB,0xf,0)
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_REVISION_MASK               0x000f
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_REVISION_ALIGN              0
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_REVISION_BITS               4
#define BRPHY2_BR_CL22_IEEE_PHY_ID_LSB_REVISION_SHIFT              0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved0 [13:06] */
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_MASK      0x3fc0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_ALIGN     0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_BITS      8
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_SHIFT     6

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_MASK   0x0020
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_ALIGN  0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_BITS   1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_SHIFT  5

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved1 [00:00] */
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_MASK      0x0001
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_ALIGN     0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_BITS      1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_SHIFT     0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: LDS_Adv_Control
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Control :: Test_Mode [15:13] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_MASK         0xe000
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_ALIGN        0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_BITS         3
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_SHIFT        13

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Control :: reserved0 [12:10] */
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_MASK         0x1c00
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_ALIGN        0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_BITS         3
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_SHIFT        10

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Control :: Port_Type [09:09] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_MASK         0x0200
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_ALIGN        0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_BITS         1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_SHIFT        9

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Control :: Abilities_Field_Update [08:08] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_MASK 0x0100
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_SHIFT 8

/* BRPHY2_BR_CL22_IEEE :: LDS_Adv_Control :: Local_Field_Number [07:00] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0)
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_MASK 0x00ff
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_BITS 8
#define BRPHY2_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: LDS_Ability
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: LDS_Ability :: LDS_Ability [15:00] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) WriteReg16(BRPHY2_BR_CL22_IEEE_LDS_ABILITY,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) ReadReg16(BRPHY2_BR_CL22_IEEE_LDS_ABILITY)
#define BRPHY2_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_MASK           0xffff
#define BRPHY2_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_ALIGN          0
#define BRPHY2_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_BITS           16
#define BRPHY2_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_SHIFT          0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved0 [13:06] */
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_MASK       0x3fc0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_ALIGN      0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_BITS       8
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_SHIFT      6

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_MASK    0x0020
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_ALIGN   0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_BITS    1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_SHIFT   5

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved1 [00:00] */
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_MASK       0x0001
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_ALIGN      0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_BITS       1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_SHIFT      0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: LDS_LP_MSG_NxtP
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: LDS_LP_MSG_NxtP :: Link_Partner_Nxt_Pg_Msg [15:00] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) WriteReg16(BRPHY2_BR_CL22_IEEE_LDS_LP_MSG_NXTP,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) ReadReg16(BRPHY2_BR_CL22_IEEE_LDS_LP_MSG_NXTP)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_MASK 0xffff
#define BRPHY2_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_BITS 16
#define BRPHY2_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_SHIFT 0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_NxtP
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: NextPage_Read_Flag [15:15] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_MASK 0x8000
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_BITS 1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_SHIFT 15

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: reserved0 [14:09] */
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_MASK     0x7e00
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_ALIGN    0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_BITS     6
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_SHIFT    9

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_ACQ [08:08] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_MASK    0x0100
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_ALIGN   0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_BITS    1
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_SHIFT   8

/* BRPHY2_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_Field_Number [07:00] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0)
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_MASK 0x00ff
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_BITS 8
#define BRPHY2_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: LDS_LDS_EXP
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: LDS_LDS_EXP :: Downgrade_Ability [15:15] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15)
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_MASK     0x8000
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_ALIGN    0
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_BITS     1
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_SHIFT    15

/* BRPHY2_BR_CL22_IEEE :: LDS_LDS_EXP :: Master_Slave [14:14] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14)
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_MASK          0x4000
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_ALIGN         0
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_BITS          1
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_SHIFT         14

/* BRPHY2_BR_CL22_IEEE :: LDS_LDS_EXP :: Pair_Number [13:12] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12)
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_MASK           0x3000
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_ALIGN          0
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_BITS           2
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_SHIFT          12

/* BRPHY2_BR_CL22_IEEE :: LDS_LDS_EXP :: Estimated_Wire_Length [11:00] */
#define Wr_BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0)
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_MASK 0x0fff
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_BITS 12
#define BRPHY2_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_SHIFT 0


/****************************************************************************
 * BRPHY2_BR_CL22_IEEE :: LRE_EXTENDED_STAT
 ***************************************************************************/
/* BRPHY2_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: reserved0 [15:10] */
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_MASK       0xfc00
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_ALIGN      0
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_BITS       6
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_SHIFT      10

/* BRPHY2_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: LOCAL_RECEIVE_STATUS [09:09] */
#define Wr_BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9)
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_MASK 0x0200
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_SHIFT 9

/* BRPHY2_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: REMOTE_RECEIVE_STATUS [08:08] */
#define Wr_BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8)
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_MASK 0x0100
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_BITS 1
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_SHIFT 8

/* BRPHY2_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: IDLE_ERROR_CNTR [07:00] */
#define Wr_BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) WriteRegBits16(BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0,x)
#define Rd_BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) ReadRegBits16(BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0)
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_MASK 0x00ff
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_ALIGN 0
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_BITS 8
#define BRPHY2_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_CL45DEV1
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x8000,15)
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESET_BITS                   1
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved0 [14:14] */
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_MASK               0x4000
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_SHIFT              14

/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x2000,13)
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved1 [12:12] */
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_MASK               0x1000
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_BITS               1
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_SHIFT              12

/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x800,11)
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved2 [10:07] */
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_MASK               0x0780
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_BITS               4
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_SHIFT              7

/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x40,6)
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x3c,2)
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved3 [01:01] */
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_MASK               0x0002
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_BITS               1
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_SHIFT              1

/* BRPHY3_CL45DEV1 :: PMD_IEEE_CTL1 :: LPBK [00:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x1,0,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_CTL1,0x1,0)
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LPBK_MASK                    0x0001
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LPBK_ALIGN                   0
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LPBK_BITS                    1
#define BRPHY3_CL45DEV1_PMD_IEEE_CTL1_LPBK_SHIFT                   0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_ST1
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY3_CL45DEV1 :: PMD_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_ST1,0x80,7)
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_FAULT_BITS                    1
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY3_CL45DEV1 :: PMD_IEEE_ST1 :: reserved1 [06:03] */
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED1_MASK                0x0078
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED1_BITS                4
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY3_CL45DEV1 :: PMD_IEEE_ST1 :: RCV_LINK_ST [02:02] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_ST1,0x4,2)
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_MASK              0x0004
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_ALIGN             0
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_BITS              1
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_SHIFT             2

/* BRPHY3_CL45DEV1 :: PMD_IEEE_ST1 :: CAP_LOW_PWR [01:01] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_ST1,0x2,1)
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_MASK              0x0002
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_ALIGN             0
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_BITS              1
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_SHIFT             1

/* BRPHY3_CL45DEV1 :: PMD_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY3_CL45DEV1_PMD_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID0,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID0)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x80,7)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x40,6)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x20,5)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x10,4)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x8,3)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x4,2)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x2,1)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV0,0x1,0)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_DEV1
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV1,0x8000,15)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV1,0x4000,14)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_DEV1,0x2000,13)
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY3_CL45DEV1 :: PMD_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY3_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID0,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID0)
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID1,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID1)
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY3_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY3_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: TX_PMD_TSYNC_EN [01:01] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_MASK    0x0002
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_BITS    1
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_SHIFT   1

/* BRPHY3_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: RX_PMD_TSYNC_EN [00:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_MASK    0x0001
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_BITS    1
#define BRPHY3_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY3_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY3_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY3_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_CL45DEV3
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x8000,15)
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESET_BITS                   1
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1 :: PCS_LPBK [14:14] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x4000,14,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x4000,14)
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_MASK                0x4000
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_ALIGN               0
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_BITS                1
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_SHIFT               14

/* BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x2000,13)
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved0 [12:12] */
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_MASK               0x1000
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_SHIFT              12

/* BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x800,11)
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved1 [10:07] */
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_MASK               0x0780
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_BITS               4
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_SHIFT              7

/* BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x40,6)
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_CTL1,0x3c,2)
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY3_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved2 [01:00] */
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_MASK               0x0003
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_BITS               2
#define BRPHY3_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_SHIFT              0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_ST1
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY3_CL45DEV3 :: PCS_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_ST1,0x80,7)
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_FAULT_BITS                    1
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY3_CL45DEV3 :: PCS_IEEE_ST1 :: CLOCK_STOP_CAPABLE [06:06] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_ST1,0x40,6,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_ST1,0x40,6)
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_MASK       0x0040
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_ALIGN      0
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_BITS       1
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_SHIFT      6

/* BRPHY3_CL45DEV3 :: PCS_IEEE_ST1 :: reserved1 [05:03] */
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED1_MASK                0x0038
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED1_BITS                3
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY3_CL45DEV3 :: PCS_IEEE_ST1 :: PCS_RCV_LINK_ST [02:02] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_ST1,0x4,2)
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_MASK          0x0004
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_ALIGN         0
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_BITS          1
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_SHIFT         2

/* BRPHY3_CL45DEV3 :: PCS_IEEE_ST1 :: LOW_PWR_AB [01:01] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_ST1,0x2,1)
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_MASK               0x0002
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_BITS               1
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_SHIFT              1

/* BRPHY3_CL45DEV3 :: PCS_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY3_CL45DEV3_PCS_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID0,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID0)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x80,7)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x40,6)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x20,5)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x10,4)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x8,3)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x4,2)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x2,1)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV0,0x1,0)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_DEV1
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV1,0x8000,15)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV1,0x4000,14)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_DEV1,0x2000,13)
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY3_CL45DEV3 :: PCS_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY3_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID0,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID0)
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID1,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID1)
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY3_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_EEE_CAP
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_EEE_CAP :: reserved0 [15:07] */
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_RESERVED0_MASK                 0xff80
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_RESERVED0_ALIGN                0
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_RESERVED0_BITS                 9
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_RESERVED0_SHIFT                7

/* BRPHY3_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKR_EEE [06:06] */
#define Wr_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x40,6,x)
#define Rd_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x40,6)
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_MASK         0x0040
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_ALIGN        0
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_BITS         1
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_SHIFT        6

/* BRPHY3_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKX4_EEE [05:05] */
#define Wr_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x20,5,x)
#define Rd_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x20,5)
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_MASK        0x0020
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_ALIGN       0
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_BITS        1
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_SHIFT       5

/* BRPHY3_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASEKX_EEE [04:04] */
#define Wr_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x10,4,x)
#define Rd_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x10,4)
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_MASK        0x0010
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_ALIGN       0
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_BITS        1
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_SHIFT       4

/* BRPHY3_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASET_EEE [03:03] */
#define Wr_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x8,3,x)
#define Rd_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x8,3)
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_MASK          0x0008
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_ALIGN         0
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_BITS          1
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_SHIFT         3

/* BRPHY3_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASET_EEE [02:02] */
#define Wr_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x4,2,x)
#define Rd_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x4,2)
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_MASK         0x0004
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_ALIGN        0
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_BITS         1
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_SHIFT        2

/* BRPHY3_CL45DEV3 :: PCS_EEE_CAP :: PHY_100BASETX_EEE [01:01] */
#define Wr_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x2,1,x)
#define Rd_BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_EEE_CAP,0x2,1)
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_MASK         0x0002
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_ALIGN        0
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_BITS         1
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_SHIFT        1

/* BRPHY3_CL45DEV3 :: PCS_EEE_CAP :: reserved1 [00:00] */
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_RESERVED1_MASK                 0x0001
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_RESERVED1_ALIGN                0
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_RESERVED1_BITS                 1
#define BRPHY3_CL45DEV3_PCS_EEE_CAP_RESERVED1_SHIFT                0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt :: cnt [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) WriteReg16(BRPHY3_CL45DEV3_PCS_EEE_WAKE_ERR_CNT,x)
#define Rd_BRPHY3_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) ReadReg16(BRPHY3_CL45DEV3_PCS_EEE_WAKE_ERR_CNT)
#define BRPHY3_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_MASK              0xffff
#define BRPHY3_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_ALIGN             0
#define BRPHY3_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_BITS              16
#define BRPHY3_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_SHIFT             0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY3_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: TX_PCS_TSYNC_EN [01:01] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_MASK    0x0002
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_BITS    1
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_SHIFT   1

/* BRPHY3_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: RX_PCS_TSYNC_EN [00:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_MASK    0x0001
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_BITS    1
#define BRPHY3_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY3_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY3_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY3_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_CL45DEV7
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_CTRL
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_CTRL :: AN_reset [15:15] */
#define Wr_BRPHY3_CL45DEV7_AN_CTRL_AN_reset(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV7_AN_CTRL_AN_reset(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_CTRL,0x8000,15)
#define BRPHY3_CL45DEV7_AN_CTRL_AN_RESET_MASK                      0x8000
#define BRPHY3_CL45DEV7_AN_CTRL_AN_RESET_ALIGN                     0
#define BRPHY3_CL45DEV7_AN_CTRL_AN_RESET_BITS                      1
#define BRPHY3_CL45DEV7_AN_CTRL_AN_RESET_SHIFT                     15

/* BRPHY3_CL45DEV7 :: AN_CTRL :: reserved0 [14:14] */
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED0_MASK                     0x4000
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED0_ALIGN                    0
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED0_BITS                     1
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED0_SHIFT                    14

/* BRPHY3_CL45DEV7 :: AN_CTRL :: Extended_next_page_control [13:13] */
#define Wr_BRPHY3_CL45DEV7_AN_CTRL_Extended_next_page_control(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV7_AN_CTRL_Extended_next_page_control(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_CTRL,0x2000,13)
#define BRPHY3_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_MASK    0x2000
#define BRPHY3_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_ALIGN   0
#define BRPHY3_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_BITS    1
#define BRPHY3_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_SHIFT   13

/* BRPHY3_CL45DEV7 :: AN_CTRL :: Auto_Negotiation_enable [12:12] */
#define Wr_BRPHY3_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY3_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_CTRL,0x1000,12)
#define BRPHY3_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_MASK       0x1000
#define BRPHY3_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_ALIGN      0
#define BRPHY3_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_BITS       1
#define BRPHY3_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_SHIFT      12

/* BRPHY3_CL45DEV7 :: AN_CTRL :: reserved1 [11:10] */
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED1_MASK                     0x0c00
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED1_ALIGN                    0
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED1_BITS                     2
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED1_SHIFT                    10

/* BRPHY3_CL45DEV7 :: AN_CTRL :: Restart_Auto_Negotiation [09:09] */
#define Wr_BRPHY3_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_CTRL,0x200,9,x)
#define Rd_BRPHY3_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_CTRL,0x200,9)
#define BRPHY3_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_MASK      0x0200
#define BRPHY3_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_ALIGN     0
#define BRPHY3_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_BITS      1
#define BRPHY3_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_SHIFT     9

/* BRPHY3_CL45DEV7 :: AN_CTRL :: reserved2 [08:00] */
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED2_MASK                     0x01ff
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED2_ALIGN                    0
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED2_BITS                     9
#define BRPHY3_CL45DEV7_AN_CTRL_RESERVED2_SHIFT                    0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_STAT
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_STAT :: reserved0 [15:08] */
#define BRPHY3_CL45DEV7_AN_STAT_RESERVED0_MASK                     0xff00
#define BRPHY3_CL45DEV7_AN_STAT_RESERVED0_ALIGN                    0
#define BRPHY3_CL45DEV7_AN_STAT_RESERVED0_BITS                     8
#define BRPHY3_CL45DEV7_AN_STAT_RESERVED0_SHIFT                    8

/* BRPHY3_CL45DEV7 :: AN_STAT :: Extended_next_page_status [07:07] */
#define Wr_BRPHY3_CL45DEV7_AN_STAT_Extended_next_page_status(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x80,7,x)
#define Rd_BRPHY3_CL45DEV7_AN_STAT_Extended_next_page_status(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x80,7)
#define BRPHY3_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_MASK     0x0080
#define BRPHY3_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_ALIGN    0
#define BRPHY3_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_BITS     1
#define BRPHY3_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_SHIFT    7

/* BRPHY3_CL45DEV7 :: AN_STAT :: Page_received [06:06] */
#define Wr_BRPHY3_CL45DEV7_AN_STAT_Page_received(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x40,6,x)
#define Rd_BRPHY3_CL45DEV7_AN_STAT_Page_received(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x40,6)
#define BRPHY3_CL45DEV7_AN_STAT_PAGE_RECEIVED_MASK                 0x0040
#define BRPHY3_CL45DEV7_AN_STAT_PAGE_RECEIVED_ALIGN                0
#define BRPHY3_CL45DEV7_AN_STAT_PAGE_RECEIVED_BITS                 1
#define BRPHY3_CL45DEV7_AN_STAT_PAGE_RECEIVED_SHIFT                6

/* BRPHY3_CL45DEV7 :: AN_STAT :: AN_complete [05:05] */
#define Wr_BRPHY3_CL45DEV7_AN_STAT_AN_complete(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x20,5,x)
#define Rd_BRPHY3_CL45DEV7_AN_STAT_AN_complete(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x20,5)
#define BRPHY3_CL45DEV7_AN_STAT_AN_COMPLETE_MASK                   0x0020
#define BRPHY3_CL45DEV7_AN_STAT_AN_COMPLETE_ALIGN                  0
#define BRPHY3_CL45DEV7_AN_STAT_AN_COMPLETE_BITS                   1
#define BRPHY3_CL45DEV7_AN_STAT_AN_COMPLETE_SHIFT                  5

/* BRPHY3_CL45DEV7 :: AN_STAT :: Remodt_Fault [04:04] */
#define Wr_BRPHY3_CL45DEV7_AN_STAT_Remodt_Fault(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x10,4,x)
#define Rd_BRPHY3_CL45DEV7_AN_STAT_Remodt_Fault(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x10,4)
#define BRPHY3_CL45DEV7_AN_STAT_REMODT_FAULT_MASK                  0x0010
#define BRPHY3_CL45DEV7_AN_STAT_REMODT_FAULT_ALIGN                 0
#define BRPHY3_CL45DEV7_AN_STAT_REMODT_FAULT_BITS                  1
#define BRPHY3_CL45DEV7_AN_STAT_REMODT_FAULT_SHIFT                 4

/* BRPHY3_CL45DEV7 :: AN_STAT :: AN_ability [03:03] */
#define Wr_BRPHY3_CL45DEV7_AN_STAT_AN_ability(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x8,3,x)
#define Rd_BRPHY3_CL45DEV7_AN_STAT_AN_ability(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x8,3)
#define BRPHY3_CL45DEV7_AN_STAT_AN_ABILITY_MASK                    0x0008
#define BRPHY3_CL45DEV7_AN_STAT_AN_ABILITY_ALIGN                   0
#define BRPHY3_CL45DEV7_AN_STAT_AN_ABILITY_BITS                    1
#define BRPHY3_CL45DEV7_AN_STAT_AN_ABILITY_SHIFT                   3

/* BRPHY3_CL45DEV7 :: AN_STAT :: Link_status [02:02] */
#define Wr_BRPHY3_CL45DEV7_AN_STAT_Link_status(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x4,2,x)
#define Rd_BRPHY3_CL45DEV7_AN_STAT_Link_status(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x4,2)
#define BRPHY3_CL45DEV7_AN_STAT_LINK_STATUS_MASK                   0x0004
#define BRPHY3_CL45DEV7_AN_STAT_LINK_STATUS_ALIGN                  0
#define BRPHY3_CL45DEV7_AN_STAT_LINK_STATUS_BITS                   1
#define BRPHY3_CL45DEV7_AN_STAT_LINK_STATUS_SHIFT                  2

/* BRPHY3_CL45DEV7 :: AN_STAT :: reserved1 [01:01] */
#define BRPHY3_CL45DEV7_AN_STAT_RESERVED1_MASK                     0x0002
#define BRPHY3_CL45DEV7_AN_STAT_RESERVED1_ALIGN                    0
#define BRPHY3_CL45DEV7_AN_STAT_RESERVED1_BITS                     1
#define BRPHY3_CL45DEV7_AN_STAT_RESERVED1_SHIFT                    1

/* BRPHY3_CL45DEV7 :: AN_STAT :: Link_partner_AN_ability [00:00] */
#define Wr_BRPHY3_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x1,0,x)
#define Rd_BRPHY3_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_STAT,0x1,0)
#define BRPHY3_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_MASK       0x0001
#define BRPHY3_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY3_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY3_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_SHIFT      0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_DEV_ID_LSB
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_DEV_ID_LSB :: cu_an_device_identifier [15:00] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) WriteReg16(BRPHY3_CL45DEV7_AN_DEV_ID_LSB,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) ReadReg16(BRPHY3_CL45DEV7_AN_DEV_ID_LSB)
#define BRPHY3_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xffff
#define BRPHY3_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY3_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_BITS 16
#define BRPHY3_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_DEV_ID_MSB
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_DEV_ID_MSB :: cu_an_device_identifier [15:10] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10)
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xfc00
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_BITS 6
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 10

/* BRPHY3_CL45DEV7 :: AN_DEV_ID_MSB :: MODEL_NU [09:04] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4)
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_MASK                0x03f0
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_ALIGN               0
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_BITS                6
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_SHIFT               4

/* BRPHY3_CL45DEV7 :: AN_DEV_ID_MSB :: REV_NU [03:00] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_ID_MSB,0xf,0,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_ID_MSB,0xf,0)
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_REV_NU_MASK                  0x000f
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_REV_NU_ALIGN                 0
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_REV_NU_BITS                  4
#define BRPHY3_CL45DEV7_AN_DEV_ID_MSB_REV_NU_SHIFT                 0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: reserved0 [15:08] */
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_MASK           0xff00
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_ALIGN          0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_BITS           8
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_SHIFT          8

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_MASK         0x0080
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_ALIGN        0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_BITS         1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_SHIFT        7

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: TC_PRE [06:06] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_MASK              0x0040
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_ALIGN             0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_BITS              1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_SHIFT             6

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: DTEXS_PRE [05:05] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_MASK           0x0020
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_ALIGN          0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_BITS           1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_SHIFT          5

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PHYXS_PRE [04:04] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_MASK           0x0010
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_ALIGN          0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_BITS           1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_SHIFT          4

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PCS_PRE [03:03] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_MASK             0x0008
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_ALIGN            0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_BITS             1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_SHIFT            3

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: WIS_PRE [02:02] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_MASK             0x0004
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_ALIGN            0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_BITS             1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_SHIFT            2

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PMD_PRE [01:01] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_MASK             0x0002
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_ALIGN            0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_BITS             1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_SHIFT            1

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: CLA22_PRE [00:00] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_MASK           0x0001
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_ALIGN          0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_BITS           1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_SHIFT          0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_MSB
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_MASK      0x8000
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_ALIGN     0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_BITS      1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_SHIFT     15

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_MASK      0x4000
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_ALIGN     0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_BITS      1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_SHIFT     14

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13)
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_MASK       0x2000
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_ALIGN      0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_BITS       1
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_SHIFT      13

/* BRPHY3_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: reserved0 [12:00] */
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_MASK           0x1fff
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_ALIGN          0
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_BITS           13
#define BRPHY3_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_SHIFT          0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_DEV_PKG_ID_LSB
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_DEV_PKG_ID_LSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) WriteReg16(BRPHY3_CL45DEV7_AN_DEV_PKG_ID_LSB,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) ReadReg16(BRPHY3_CL45DEV7_AN_DEV_PKG_ID_LSB)
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_DEV_PKG_ID_MSB
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_DEV_PKG_ID_MSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY3_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) WriteReg16(BRPHY3_CL45DEV7_AN_DEV_PKG_ID_MSB,x)
#define Rd_BRPHY3_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) ReadReg16(BRPHY3_CL45DEV7_AN_DEV_PKG_ID_MSB)
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY3_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_AD
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_AD :: Next_page [15:15] */
#define Wr_BRPHY3_CL45DEV7_AN_AD_Next_page(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_AD,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV7_AN_AD_Next_page(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_AD,0x8000,15)
#define BRPHY3_CL45DEV7_AN_AD_NEXT_PAGE_MASK                       0x8000
#define BRPHY3_CL45DEV7_AN_AD_NEXT_PAGE_ALIGN                      0
#define BRPHY3_CL45DEV7_AN_AD_NEXT_PAGE_BITS                       1
#define BRPHY3_CL45DEV7_AN_AD_NEXT_PAGE_SHIFT                      15

/* BRPHY3_CL45DEV7 :: AN_AD :: Acknowledge [14:14] */
#define Wr_BRPHY3_CL45DEV7_AN_AD_Acknowledge(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_AD,0x4000,14,x)
#define Rd_BRPHY3_CL45DEV7_AN_AD_Acknowledge(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_AD,0x4000,14)
#define BRPHY3_CL45DEV7_AN_AD_ACKNOWLEDGE_MASK                     0x4000
#define BRPHY3_CL45DEV7_AN_AD_ACKNOWLEDGE_ALIGN                    0
#define BRPHY3_CL45DEV7_AN_AD_ACKNOWLEDGE_BITS                     1
#define BRPHY3_CL45DEV7_AN_AD_ACKNOWLEDGE_SHIFT                    14

/* BRPHY3_CL45DEV7 :: AN_AD :: Remote_fault [13:13] */
#define Wr_BRPHY3_CL45DEV7_AN_AD_Remote_fault(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_AD,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV7_AN_AD_Remote_fault(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_AD,0x2000,13)
#define BRPHY3_CL45DEV7_AN_AD_REMOTE_FAULT_MASK                    0x2000
#define BRPHY3_CL45DEV7_AN_AD_REMOTE_FAULT_ALIGN                   0
#define BRPHY3_CL45DEV7_AN_AD_REMOTE_FAULT_BITS                    1
#define BRPHY3_CL45DEV7_AN_AD_REMOTE_FAULT_SHIFT                   13

/* BRPHY3_CL45DEV7 :: AN_AD :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY3_CL45DEV7_AN_AD_Extended_next_page_ability(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_AD,0x1000,12,x)
#define Rd_BRPHY3_CL45DEV7_AN_AD_Extended_next_page_ability(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_AD,0x1000,12)
#define BRPHY3_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_MASK      0x1000
#define BRPHY3_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_ALIGN     0
#define BRPHY3_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_BITS      1
#define BRPHY3_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_SHIFT     12

/* BRPHY3_CL45DEV7 :: AN_AD :: Tech_Field [11:05] */
#define Wr_BRPHY3_CL45DEV7_AN_AD_Tech_Field(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_AD,0xfe0,5,x)
#define Rd_BRPHY3_CL45DEV7_AN_AD_Tech_Field(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_AD,0xfe0,5)
#define BRPHY3_CL45DEV7_AN_AD_TECH_FIELD_MASK                      0x0fe0
#define BRPHY3_CL45DEV7_AN_AD_TECH_FIELD_ALIGN                     0
#define BRPHY3_CL45DEV7_AN_AD_TECH_FIELD_BITS                      7
#define BRPHY3_CL45DEV7_AN_AD_TECH_FIELD_SHIFT                     5

/* BRPHY3_CL45DEV7 :: AN_AD :: Selector_Field [04:00] */
#define Wr_BRPHY3_CL45DEV7_AN_AD_Selector_Field(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_AD,0x1f,0,x)
#define Rd_BRPHY3_CL45DEV7_AN_AD_Selector_Field(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_AD,0x1f,0)
#define BRPHY3_CL45DEV7_AN_AD_SELECTOR_FIELD_MASK                  0x001f
#define BRPHY3_CL45DEV7_AN_AD_SELECTOR_FIELD_ALIGN                 0
#define BRPHY3_CL45DEV7_AN_AD_SELECTOR_FIELD_BITS                  5
#define BRPHY3_CL45DEV7_AN_AD_SELECTOR_FIELD_SHIFT                 0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_LPA
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_LPA :: Next_page [15:15] */
#define Wr_BRPHY3_CL45DEV7_AN_LPA_Next_page(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV7_AN_LPA_Next_page(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x8000,15)
#define BRPHY3_CL45DEV7_AN_LPA_NEXT_PAGE_MASK                      0x8000
#define BRPHY3_CL45DEV7_AN_LPA_NEXT_PAGE_ALIGN                     0
#define BRPHY3_CL45DEV7_AN_LPA_NEXT_PAGE_BITS                      1
#define BRPHY3_CL45DEV7_AN_LPA_NEXT_PAGE_SHIFT                     15

/* BRPHY3_CL45DEV7 :: AN_LPA :: Acknowledge [14:14] */
#define Wr_BRPHY3_CL45DEV7_AN_LPA_Acknowledge(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x4000,14,x)
#define Rd_BRPHY3_CL45DEV7_AN_LPA_Acknowledge(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x4000,14)
#define BRPHY3_CL45DEV7_AN_LPA_ACKNOWLEDGE_MASK                    0x4000
#define BRPHY3_CL45DEV7_AN_LPA_ACKNOWLEDGE_ALIGN                   0
#define BRPHY3_CL45DEV7_AN_LPA_ACKNOWLEDGE_BITS                    1
#define BRPHY3_CL45DEV7_AN_LPA_ACKNOWLEDGE_SHIFT                   14

/* BRPHY3_CL45DEV7 :: AN_LPA :: Remote_fault [13:13] */
#define Wr_BRPHY3_CL45DEV7_AN_LPA_Remote_fault(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV7_AN_LPA_Remote_fault(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x2000,13)
#define BRPHY3_CL45DEV7_AN_LPA_REMOTE_FAULT_MASK                   0x2000
#define BRPHY3_CL45DEV7_AN_LPA_REMOTE_FAULT_ALIGN                  0
#define BRPHY3_CL45DEV7_AN_LPA_REMOTE_FAULT_BITS                   1
#define BRPHY3_CL45DEV7_AN_LPA_REMOTE_FAULT_SHIFT                  13

/* BRPHY3_CL45DEV7 :: AN_LPA :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY3_CL45DEV7_AN_LPA_Extended_next_page_ability(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x1000,12,x)
#define Rd_BRPHY3_CL45DEV7_AN_LPA_Extended_next_page_ability(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x1000,12)
#define BRPHY3_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_MASK     0x1000
#define BRPHY3_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_ALIGN    0
#define BRPHY3_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_BITS     1
#define BRPHY3_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_SHIFT    12

/* BRPHY3_CL45DEV7 :: AN_LPA :: Tech_Field [11:05] */
#define Wr_BRPHY3_CL45DEV7_AN_LPA_Tech_Field(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_LPA,0xfe0,5,x)
#define Rd_BRPHY3_CL45DEV7_AN_LPA_Tech_Field(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_LPA,0xfe0,5)
#define BRPHY3_CL45DEV7_AN_LPA_TECH_FIELD_MASK                     0x0fe0
#define BRPHY3_CL45DEV7_AN_LPA_TECH_FIELD_ALIGN                    0
#define BRPHY3_CL45DEV7_AN_LPA_TECH_FIELD_BITS                     7
#define BRPHY3_CL45DEV7_AN_LPA_TECH_FIELD_SHIFT                    5

/* BRPHY3_CL45DEV7 :: AN_LPA :: Selector_Field [04:00] */
#define Wr_BRPHY3_CL45DEV7_AN_LPA_Selector_Field(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x1f,0,x)
#define Rd_BRPHY3_CL45DEV7_AN_LPA_Selector_Field(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_LPA,0x1f,0)
#define BRPHY3_CL45DEV7_AN_LPA_SELECTOR_FIELD_MASK                 0x001f
#define BRPHY3_CL45DEV7_AN_LPA_SELECTOR_FIELD_ALIGN                0
#define BRPHY3_CL45DEV7_AN_LPA_SELECTOR_FIELD_BITS                 5
#define BRPHY3_CL45DEV7_AN_LPA_SELECTOR_FIELD_SHIFT                0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_XNPA
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_XNPA :: Next_page [15:15] */
#define Wr_BRPHY3_CL45DEV7_AN_XNPA_Next_page(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV7_AN_XNPA_Next_page(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x8000,15)
#define BRPHY3_CL45DEV7_AN_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY3_CL45DEV7_AN_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY3_CL45DEV7_AN_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY3_CL45DEV7_AN_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY3_CL45DEV7 :: AN_XNPA :: reserved0 [14:14] */
#define BRPHY3_CL45DEV7_AN_XNPA_RESERVED0_MASK                     0x4000
#define BRPHY3_CL45DEV7_AN_XNPA_RESERVED0_ALIGN                    0
#define BRPHY3_CL45DEV7_AN_XNPA_RESERVED0_BITS                     1
#define BRPHY3_CL45DEV7_AN_XNPA_RESERVED0_SHIFT                    14

/* BRPHY3_CL45DEV7 :: AN_XNPA :: Message_page [13:13] */
#define Wr_BRPHY3_CL45DEV7_AN_XNPA_Message_page(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV7_AN_XNPA_Message_page(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x2000,13)
#define BRPHY3_CL45DEV7_AN_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY3_CL45DEV7_AN_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY3_CL45DEV7_AN_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY3_CL45DEV7_AN_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY3_CL45DEV7 :: AN_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY3_CL45DEV7_AN_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x1000,12,x)
#define Rd_BRPHY3_CL45DEV7_AN_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x1000,12)
#define BRPHY3_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY3_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY3_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY3_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY3_CL45DEV7 :: AN_XNPA :: Toggle [11:11] */
#define Wr_BRPHY3_CL45DEV7_AN_XNPA_Toggle(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x800,11,x)
#define Rd_BRPHY3_CL45DEV7_AN_XNPA_Toggle(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x800,11)
#define BRPHY3_CL45DEV7_AN_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY3_CL45DEV7_AN_XNPA_TOGGLE_ALIGN                       0
#define BRPHY3_CL45DEV7_AN_XNPA_TOGGLE_BITS                        1
#define BRPHY3_CL45DEV7_AN_XNPA_TOGGLE_SHIFT                       11

/* BRPHY3_CL45DEV7 :: AN_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY3_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x7ff,0,x)
#define Rd_BRPHY3_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY3_CL45DEV7_AN_XNPA,0x7ff,0)
#define BRPHY3_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY3_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY3_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY3_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_XNPB
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY3_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY3_CL45DEV7_AN_XNPB,x)
#define Rd_BRPHY3_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY3_CL45DEV7_AN_XNPB)
#define BRPHY3_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY3_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY3_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY3_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: AN_XNPC
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: AN_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY3_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY3_CL45DEV7_AN_XNPC,x)
#define Rd_BRPHY3_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY3_CL45DEV7_AN_XNPC)
#define BRPHY3_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY3_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY3_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY3_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: LP_XNPA
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: LP_XNPA :: Next_page [15:15] */
#define Wr_BRPHY3_CL45DEV7_LP_XNPA_Next_page(x) WriteRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV7_LP_XNPA_Next_page(x) ReadRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x8000,15)
#define BRPHY3_CL45DEV7_LP_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY3_CL45DEV7_LP_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY3_CL45DEV7_LP_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY3_CL45DEV7_LP_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY3_CL45DEV7 :: LP_XNPA :: Acknowledge [14:14] */
#define Wr_BRPHY3_CL45DEV7_LP_XNPA_Acknowledge(x) WriteRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x4000,14,x)
#define Rd_BRPHY3_CL45DEV7_LP_XNPA_Acknowledge(x) ReadRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x4000,14)
#define BRPHY3_CL45DEV7_LP_XNPA_ACKNOWLEDGE_MASK                   0x4000
#define BRPHY3_CL45DEV7_LP_XNPA_ACKNOWLEDGE_ALIGN                  0
#define BRPHY3_CL45DEV7_LP_XNPA_ACKNOWLEDGE_BITS                   1
#define BRPHY3_CL45DEV7_LP_XNPA_ACKNOWLEDGE_SHIFT                  14

/* BRPHY3_CL45DEV7 :: LP_XNPA :: Message_page [13:13] */
#define Wr_BRPHY3_CL45DEV7_LP_XNPA_Message_page(x) WriteRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV7_LP_XNPA_Message_page(x) ReadRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x2000,13)
#define BRPHY3_CL45DEV7_LP_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY3_CL45DEV7_LP_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY3_CL45DEV7_LP_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY3_CL45DEV7_LP_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY3_CL45DEV7 :: LP_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY3_CL45DEV7_LP_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x1000,12,x)
#define Rd_BRPHY3_CL45DEV7_LP_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x1000,12)
#define BRPHY3_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY3_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY3_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY3_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY3_CL45DEV7 :: LP_XNPA :: Toggle [11:11] */
#define Wr_BRPHY3_CL45DEV7_LP_XNPA_Toggle(x) WriteRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x800,11,x)
#define Rd_BRPHY3_CL45DEV7_LP_XNPA_Toggle(x) ReadRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x800,11)
#define BRPHY3_CL45DEV7_LP_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY3_CL45DEV7_LP_XNPA_TOGGLE_ALIGN                       0
#define BRPHY3_CL45DEV7_LP_XNPA_TOGGLE_BITS                        1
#define BRPHY3_CL45DEV7_LP_XNPA_TOGGLE_SHIFT                       11

/* BRPHY3_CL45DEV7 :: LP_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY3_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x7ff,0,x)
#define Rd_BRPHY3_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY3_CL45DEV7_LP_XNPA,0x7ff,0)
#define BRPHY3_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY3_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY3_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY3_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: LP_XNPB
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: LP_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY3_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY3_CL45DEV7_LP_XNPB,x)
#define Rd_BRPHY3_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY3_CL45DEV7_LP_XNPB)
#define BRPHY3_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY3_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY3_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY3_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: LP_XNPC
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: LP_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY3_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY3_CL45DEV7_LP_XNPC,x)
#define Rd_BRPHY3_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY3_CL45DEV7_LP_XNPC)
#define BRPHY3_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY3_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY3_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY3_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: TENG_AN_CTRL
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_MAN_CONFIG_EN [15:15] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x8000,15)
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_MASK   0x8000
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_ALIGN  0
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_BITS   1
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_SHIFT  15

/* BRPHY3_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_CONFIG_VAL [14:14] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x4000,14,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x4000,14)
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_MASK      0x4000
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_ALIGN     0
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_BITS      1
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_SHIFT     14

/* BRPHY3_CL45DEV7 :: TENG_AN_CTRL :: PORT_TYPE [13:13] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x2000,13)
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_MASK                0x2000
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_ALIGN               0
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_BITS                1
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_SHIFT               13

/* BRPHY3_CL45DEV7 :: TENG_AN_CTRL :: PHY10GBASET_ABLE [12:12] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x1000,12)
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_MASK         0x1000
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_ALIGN        0
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_BITS         1
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_SHIFT        12

/* BRPHY3_CL45DEV7 :: TENG_AN_CTRL :: reserved0 [11:03] */
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_RESERVED0_MASK                0x0ff8
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_RESERVED0_ALIGN               0
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_RESERVED0_BITS                9
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_RESERVED0_SHIFT               3

/* BRPHY3_CL45DEV7 :: TENG_AN_CTRL :: LD_PMA_TRAIN_RST_SEQ [02:02] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x4,2,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x4,2)
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_MASK     0x0004
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_ALIGN    0
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_BITS     1
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_SHIFT    2

/* BRPHY3_CL45DEV7 :: TENG_AN_CTRL :: reserved1 [01:01] */
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_RESERVED1_MASK                0x0002
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_RESERVED1_ALIGN               0
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_RESERVED1_BITS                1
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_RESERVED1_SHIFT               1

/* BRPHY3_CL45DEV7 :: TENG_AN_CTRL :: LD_LOOP_TIMING_ABLE [00:00] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x1,0,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_CTRL,0x1,0)
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_MASK      0x0001
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_BITS      1
#define BRPHY3_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_SHIFT     0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: TENG_AN_STAT
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_FAULT [15:15] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x8000,15,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x8000,15)
#define BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_MASK    0x8000
#define BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_ALIGN   0
#define BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_BITS    1
#define BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_SHIFT   15

/* BRPHY3_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_RES [14:14] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x4000,14,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x4000,14)
#define BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_MASK      0x4000
#define BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_ALIGN     0
#define BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_BITS      1
#define BRPHY3_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_SHIFT     14

/* BRPHY3_CL45DEV7 :: TENG_AN_STAT :: LOCAL_RCVR_STAT [13:13] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x2000,13,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x2000,13)
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_MASK          0x2000
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_ALIGN         0
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_BITS          1
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_SHIFT         13

/* BRPHY3_CL45DEV7 :: TENG_AN_STAT :: REMOTE_RCVR_STAT [12:12] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x1000,12,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x1000,12)
#define BRPHY3_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_MASK         0x1000
#define BRPHY3_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_ALIGN        0
#define BRPHY3_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_BITS         1
#define BRPHY3_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_SHIFT        12

/* BRPHY3_CL45DEV7 :: TENG_AN_STAT :: LNK_PRTNR_10GBASET_CAP [11:11] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x800,11,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x800,11)
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_MASK   0x0800
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_ALIGN  0
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_BITS   1
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_SHIFT  11

/* BRPHY3_CL45DEV7 :: TENG_AN_STAT :: LP_LOOP_TIMING_ABLE [10:10] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x400,10,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x400,10)
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_MASK      0x0400
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_BITS      1
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_SHIFT     10

/* BRPHY3_CL45DEV7 :: TENG_AN_STAT :: LP_PMA_TRAIN_RST_REQ [09:09] */
#define Wr_BRPHY3_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) WriteRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x200,9,x)
#define Rd_BRPHY3_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) ReadRegBits16(BRPHY3_CL45DEV7_TENG_AN_STAT,0x200,9)
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_MASK     0x0200
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_ALIGN    0
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_BITS     1
#define BRPHY3_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_SHIFT    9

/* BRPHY3_CL45DEV7 :: TENG_AN_STAT :: reserved0 [08:00] */
#define BRPHY3_CL45DEV7_TENG_AN_STAT_RESERVED0_MASK                0x01ff
#define BRPHY3_CL45DEV7_TENG_AN_STAT_RESERVED0_ALIGN               0
#define BRPHY3_CL45DEV7_TENG_AN_STAT_RESERVED0_BITS                9
#define BRPHY3_CL45DEV7_TENG_AN_STAT_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: EEE_ADV
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: EEE_ADV :: reserved0 [15:11] */
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED0_MASK                     0xf800
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED0_ALIGN                    0
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED0_BITS                     5
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED0_SHIFT                    11

/* BRPHY3_CL45DEV7 :: EEE_ADV :: Next_page [10:10] */
#define Wr_BRPHY3_CL45DEV7_EEE_ADV_Next_page(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x400,10,x)
#define Rd_BRPHY3_CL45DEV7_EEE_ADV_Next_page(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x400,10)
#define BRPHY3_CL45DEV7_EEE_ADV_NEXT_PAGE_MASK                     0x0400
#define BRPHY3_CL45DEV7_EEE_ADV_NEXT_PAGE_ALIGN                    0
#define BRPHY3_CL45DEV7_EEE_ADV_NEXT_PAGE_BITS                     1
#define BRPHY3_CL45DEV7_EEE_ADV_NEXT_PAGE_SHIFT                    10

/* BRPHY3_CL45DEV7 :: EEE_ADV :: reserved1 [09:07] */
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED1_MASK                     0x0380
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED1_ALIGN                    0
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED1_BITS                     3
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED1_SHIFT                    7

/* BRPHY3_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KR_EEE [06:06] */
#define Wr_BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x40,6,x)
#define Rd_BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x40,6)
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_MASK            0x0040
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_ALIGN           0
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_BITS            1
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_SHIFT           6

/* BRPHY3_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KX4_EEE [05:05] */
#define Wr_BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x20,5,x)
#define Rd_BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x20,5)
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_MASK           0x0020
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_ALIGN          0
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_BITS           1
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_SHIFT          5

/* BRPHY3_CL45DEV7 :: EEE_ADV :: reserved2 [04:04] */
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED2_MASK                     0x0010
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED2_ALIGN                    0
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED2_BITS                     1
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED2_SHIFT                    4

/* BRPHY3_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_T_EEE [03:03] */
#define Wr_BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x8,3,x)
#define Rd_BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x8,3)
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_MASK             0x0008
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_ALIGN            0
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_BITS             1
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_SHIFT            3

/* BRPHY3_CL45DEV7 :: EEE_ADV :: PHY_1000BASE_T_EEE [02:02] */
#define Wr_BRPHY3_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x4,2,x)
#define Rd_BRPHY3_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x4,2)
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_MASK            0x0004
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_ALIGN           0
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_BITS            1
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_SHIFT           2

/* BRPHY3_CL45DEV7 :: EEE_ADV :: PHY_100BASE_T_EEE [01:01] */
#define Wr_BRPHY3_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x2,1,x)
#define Rd_BRPHY3_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_ADV,0x2,1)
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_MASK             0x0002
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_ALIGN            0
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_BITS             1
#define BRPHY3_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_SHIFT            1

/* BRPHY3_CL45DEV7 :: EEE_ADV :: reserved3 [00:00] */
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED3_MASK                     0x0001
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED3_ALIGN                    0
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED3_BITS                     1
#define BRPHY3_CL45DEV7_EEE_ADV_RESERVED3_SHIFT                    0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: EEE_LP_ADV
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: EEE_LP_ADV :: status [15:00] */
#define Wr_BRPHY3_CL45DEV7_EEE_LP_ADV_status(x) WriteReg16(BRPHY3_CL45DEV7_EEE_LP_ADV,x)
#define Rd_BRPHY3_CL45DEV7_EEE_LP_ADV_status(x) ReadReg16(BRPHY3_CL45DEV7_EEE_LP_ADV)
#define BRPHY3_CL45DEV7_EEE_LP_ADV_STATUS_MASK                     0xffff
#define BRPHY3_CL45DEV7_EEE_LP_ADV_STATUS_ALIGN                    0
#define BRPHY3_CL45DEV7_EEE_LP_ADV_STATUS_BITS                     16
#define BRPHY3_CL45DEV7_EEE_LP_ADV_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY3_CL45DEV7 :: EEE_MODE_CTL
 ***************************************************************************/
/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: reserved0 [15:11] */
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED0_MASK                0xf800
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED0_ALIGN               0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED0_BITS                5
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED0_SHIFT               11

/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: Next_page [10:10] */
#define Wr_BRPHY3_CL45DEV7_EEE_MODE_CTL_Next_page(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x400,10,x)
#define Rd_BRPHY3_CL45DEV7_EEE_MODE_CTL_Next_page(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x400,10)
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_MASK                0x0400
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_ALIGN               0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_BITS                1
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_SHIFT               10

/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: reserved1 [09:07] */
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED1_MASK                0x0380
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED1_ALIGN               0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED1_BITS                3
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED1_SHIFT               7

/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KR_reduced_energy [06:06] */
#define Wr_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x40,6,x)
#define Rd_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x40,6)
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_MASK 0x0040
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_ALIGN 0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_BITS 1
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_SHIFT 6

/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KX4_reduced_energy [05:05] */
#define Wr_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x20,5,x)
#define Rd_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x20,5)
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_MASK 0x0020
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_ALIGN 0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_BITS 1
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_SHIFT 5

/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: reserved2 [04:04] */
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED2_MASK                0x0010
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED2_ALIGN               0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED2_BITS                1
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED2_SHIFT               4

/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_T_reduced_energy [03:03] */
#define Wr_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x8,3,x)
#define Rd_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x8,3)
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_MASK 0x0008
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_SHIFT 3

/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: PHY_1000BASE_T_reduced_energy [02:02] */
#define Wr_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x4,2,x)
#define Rd_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x4,2)
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_MASK 0x0004
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_SHIFT 2

/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: PHY_100BASE_T_reduced_energy [01:01] */
#define Wr_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) WriteRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x2,1,x)
#define Rd_BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) ReadRegBits16(BRPHY3_CL45DEV7_EEE_MODE_CTL,0x2,1)
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_MASK 0x0002
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_SHIFT 1

/* BRPHY3_CL45DEV7 :: EEE_MODE_CTL :: reserved3 [00:00] */
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED3_MASK                0x0001
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED3_ALIGN               0
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED3_BITS                1
#define BRPHY3_CL45DEV7_EEE_MODE_CTL_RESERVED3_SHIFT               0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_CL45VEN
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_CL45VEN :: FORCE_LINK
 ***************************************************************************/
/* BRPHY3_CL45VEN :: FORCE_LINK :: FORCE_LINK_MODE [15:15] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x8000,15,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x8000,15)
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_MASK             0x8000
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_ALIGN            0
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_BITS             1
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_SHIFT            15

/* BRPHY3_CL45VEN :: FORCE_LINK :: CHNG_10GBASET_AN_CTRL_BEHAV [14:14] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x4000,14,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x4000,14)
#define BRPHY3_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_MASK 0x4000
#define BRPHY3_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_ALIGN 0
#define BRPHY3_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_BITS 1
#define BRPHY3_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_SHIFT 14

/* BRPHY3_CL45VEN :: FORCE_LINK :: CHNG_BIT13_MCTRL_RD_BEHAV [13:13] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x2000,13,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x2000,13)
#define BRPHY3_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_MASK   0x2000
#define BRPHY3_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_ALIGN  0
#define BRPHY3_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_BITS   1
#define BRPHY3_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_SHIFT  13

/* BRPHY3_CL45VEN :: FORCE_LINK :: AN_FLP_BTB_TMR_MODE [12:12] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x1000,12,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x1000,12)
#define BRPHY3_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_MASK         0x1000
#define BRPHY3_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_ALIGN        0
#define BRPHY3_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_BITS         1
#define BRPHY3_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_SHIFT        12

/* BRPHY3_CL45VEN :: FORCE_LINK :: SWP_UFORMATED_CODE_FLDS [11:11] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x800,11,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x800,11)
#define BRPHY3_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_MASK     0x0800
#define BRPHY3_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_ALIGN    0
#define BRPHY3_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_BITS     1
#define BRPHY3_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_SHIFT    11

/* BRPHY3_CL45VEN :: FORCE_LINK :: BRK_LNK_TMR_MODE [10:10] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x400,10,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x400,10)
#define BRPHY3_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_MASK            0x0400
#define BRPHY3_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_ALIGN           0
#define BRPHY3_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_BITS            1
#define BRPHY3_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_SHIFT           10

/* BRPHY3_CL45VEN :: FORCE_LINK :: PREAMBLE_IGNORE [09:09] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x200,9,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x200,9)
#define BRPHY3_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_MASK             0x0200
#define BRPHY3_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_ALIGN            0
#define BRPHY3_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_BITS             1
#define BRPHY3_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_SHIFT            9

/* BRPHY3_CL45VEN :: FORCE_LINK :: FORCE_LNK_10GBASET_FDX [08:08] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x100,8,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x100,8)
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_MASK      0x0100
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_ALIGN     0
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_BITS      1
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_SHIFT     8

/* BRPHY3_CL45VEN :: FORCE_LINK :: FORCE_LNK_1000BASET_FDX_HDX [07:07] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x80,7,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x80,7)
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_MASK 0x0080
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_ALIGN 0
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_BITS 1
#define BRPHY3_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_SHIFT 7

/* BRPHY3_CL45VEN :: FORCE_LINK :: IGNORE_ACK2 [06:06] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x40,6,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x40,6)
#define BRPHY3_CL45VEN_FORCE_LINK_IGNORE_ACK2_MASK                 0x0040
#define BRPHY3_CL45VEN_FORCE_LINK_IGNORE_ACK2_ALIGN                0
#define BRPHY3_CL45VEN_FORCE_LINK_IGNORE_ACK2_BITS                 1
#define BRPHY3_CL45VEN_FORCE_LINK_IGNORE_ACK2_SHIFT                6

/* BRPHY3_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_OK [05:05] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x20,5,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x20,5)
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_MASK       0x0020
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_ALIGN      0
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_BITS       1
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_SHIFT      5

/* BRPHY3_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_RDY [04:04] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x10,4,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x10,4)
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_MASK      0x0010
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_ALIGN     0
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_BITS      1
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_SHIFT     4

/* BRPHY3_CL45VEN :: FORCE_LINK :: DIS_REG7P0_BIT13_AUTO_UPDATE [03:03] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x8,3,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x8,3)
#define BRPHY3_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_MASK 0x0008
#define BRPHY3_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_ALIGN 0
#define BRPHY3_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_BITS 1
#define BRPHY3_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_SHIFT 3

/* BRPHY3_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_OK [02:02] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x4,2,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x4,2)
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_MASK        0x0004
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_ALIGN       0
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_BITS        1
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_SHIFT       2

/* BRPHY3_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_RDY [01:01] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x2,1,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x2,1)
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_MASK       0x0002
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_ALIGN      0
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_BITS       1
#define BRPHY3_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_SHIFT      1

/* BRPHY3_CL45VEN :: FORCE_LINK :: LAST_PG_TO_EN [00:00] */
#define Wr_BRPHY3_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) WriteRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x1,0,x)
#define Rd_BRPHY3_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) ReadRegBits16(BRPHY3_CL45VEN_FORCE_LINK,0x1,0)
#define BRPHY3_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_MASK               0x0001
#define BRPHY3_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_ALIGN              0
#define BRPHY3_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_BITS               1
#define BRPHY3_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_SHIFT              0


/****************************************************************************
 * BRPHY3_CL45VEN :: SELECTIVE_RESET
 ***************************************************************************/
/* BRPHY3_CL45VEN :: SELECTIVE_RESET :: DSP_RESET [15:15] */
#define Wr_BRPHY3_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) WriteRegBits16(BRPHY3_CL45VEN_SELECTIVE_RESET,0x8000,15,x)
#define Rd_BRPHY3_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) ReadRegBits16(BRPHY3_CL45VEN_SELECTIVE_RESET,0x8000,15)
#define BRPHY3_CL45VEN_SELECTIVE_RESET_DSP_RESET_MASK              0x8000
#define BRPHY3_CL45VEN_SELECTIVE_RESET_DSP_RESET_ALIGN             0
#define BRPHY3_CL45VEN_SELECTIVE_RESET_DSP_RESET_BITS              1
#define BRPHY3_CL45VEN_SELECTIVE_RESET_DSP_RESET_SHIFT             15

/* BRPHY3_CL45VEN :: SELECTIVE_RESET :: SM_DSP_RESET [14:14] */
#define Wr_BRPHY3_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) WriteRegBits16(BRPHY3_CL45VEN_SELECTIVE_RESET,0x4000,14,x)
#define Rd_BRPHY3_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) ReadRegBits16(BRPHY3_CL45VEN_SELECTIVE_RESET,0x4000,14)
#define BRPHY3_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_MASK           0x4000
#define BRPHY3_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_ALIGN          0
#define BRPHY3_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_BITS           1
#define BRPHY3_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_SHIFT          14

/* BRPHY3_CL45VEN :: SELECTIVE_RESET :: reserved0 [13:08] */
#define BRPHY3_CL45VEN_SELECTIVE_RESET_RESERVED0_MASK              0x3f00
#define BRPHY3_CL45VEN_SELECTIVE_RESET_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_SELECTIVE_RESET_RESERVED0_BITS              6
#define BRPHY3_CL45VEN_SELECTIVE_RESET_RESERVED0_SHIFT             8

/* BRPHY3_CL45VEN :: SELECTIVE_RESET :: DIG100_RESET [07:07] */
#define Wr_BRPHY3_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) WriteRegBits16(BRPHY3_CL45VEN_SELECTIVE_RESET,0x80,7,x)
#define Rd_BRPHY3_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) ReadRegBits16(BRPHY3_CL45VEN_SELECTIVE_RESET,0x80,7)
#define BRPHY3_CL45VEN_SELECTIVE_RESET_DIG100_RESET_MASK           0x0080
#define BRPHY3_CL45VEN_SELECTIVE_RESET_DIG100_RESET_ALIGN          0
#define BRPHY3_CL45VEN_SELECTIVE_RESET_DIG100_RESET_BITS           1
#define BRPHY3_CL45VEN_SELECTIVE_RESET_DIG100_RESET_SHIFT          7

/* BRPHY3_CL45VEN :: SELECTIVE_RESET :: reserved1 [06:00] */
#define BRPHY3_CL45VEN_SELECTIVE_RESET_RESERVED1_MASK              0x007f
#define BRPHY3_CL45VEN_SELECTIVE_RESET_RESERVED1_ALIGN             0
#define BRPHY3_CL45VEN_SELECTIVE_RESET_RESERVED1_BITS              7
#define BRPHY3_CL45VEN_SELECTIVE_RESET_RESERVED1_SHIFT             0


/****************************************************************************
 * BRPHY3_CL45VEN :: TEST_FSM_EXT_NXT_PGS
 ***************************************************************************/
/* BRPHY3_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved0 [15:15] */
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_MASK         0x8000
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_ALIGN        0
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_BITS         1
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_SHIFT        15

/* BRPHY3_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_XMTR_STATE [14:12] */
#define Wr_BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) WriteRegBits16(BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12,x)
#define Rd_BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) ReadRegBits16(BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12)
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_MASK    0x7000
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_ALIGN   0
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_BITS    3
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_SHIFT   12

/* BRPHY3_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved1 [11:11] */
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_MASK         0x0800
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_ALIGN        0
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_BITS         1
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_SHIFT        11

/* BRPHY3_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_RCVR_STATE [10:08] */
#define Wr_BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) WriteRegBits16(BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8,x)
#define Rd_BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) ReadRegBits16(BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8)
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_MASK    0x0700
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_ALIGN   0
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_BITS    3
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_SHIFT   8

/* BRPHY3_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: ARB_STATE [07:04] */
#define Wr_BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) WriteRegBits16(BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4,x)
#define Rd_BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) ReadRegBits16(BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4)
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_MASK         0x00f0
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_ALIGN        0
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_BITS         4
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_SHIFT        4

/* BRPHY3_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: HCD_STATE [03:00] */
#define Wr_BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) WriteRegBits16(BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0,x)
#define Rd_BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) ReadRegBits16(BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0)
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_MASK         0x000f
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_ALIGN        0
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_BITS         4
#define BRPHY3_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_SHIFT        0


/****************************************************************************
 * BRPHY3_CL45VEN :: TEST_FSM_NXT_PGS
 ***************************************************************************/
/* BRPHY3_CL45VEN :: TEST_FSM_NXT_PGS :: reserved0 [15:10] */
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_MASK             0xfc00
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_ALIGN            0
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_BITS             6
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_SHIFT            10

/* BRPHY3_CL45VEN :: TEST_FSM_NXT_PGS :: NP_XMTR_STATE [09:05] */
#define Wr_BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) WriteRegBits16(BRPHY3_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5,x)
#define Rd_BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) ReadRegBits16(BRPHY3_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5)
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_MASK         0x03e0
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_ALIGN        0
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_BITS         5
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_SHIFT        5

/* BRPHY3_CL45VEN :: TEST_FSM_NXT_PGS :: reserved1 [04:04] */
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_MASK             0x0010
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_ALIGN            0
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_BITS             1
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_SHIFT            4

/* BRPHY3_CL45VEN :: TEST_FSM_NXT_PGS :: NP_RCVR_STATE [03:00] */
#define Wr_BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) WriteRegBits16(BRPHY3_CL45VEN_TEST_FSM_NXT_PGS,0xf,0,x)
#define Rd_BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) ReadRegBits16(BRPHY3_CL45VEN_TEST_FSM_NXT_PGS,0xf,0)
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_MASK         0x000f
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_ALIGN        0
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_BITS         4
#define BRPHY3_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_SHIFT        0


/****************************************************************************
 * BRPHY3_CL45VEN :: AN_MAN_TEST
 ***************************************************************************/
/* BRPHY3_CL45VEN :: AN_MAN_TEST :: reserved0 [15:12] */
#define BRPHY3_CL45VEN_AN_MAN_TEST_RESERVED0_MASK                  0xf000
#define BRPHY3_CL45VEN_AN_MAN_TEST_RESERVED0_ALIGN                 0
#define BRPHY3_CL45VEN_AN_MAN_TEST_RESERVED0_BITS                  4
#define BRPHY3_CL45VEN_AN_MAN_TEST_RESERVED0_SHIFT                 12

/* BRPHY3_CL45VEN :: AN_MAN_TEST :: LP_PG_TO_CAPTURE [11:08] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_TEST,0xf00,8,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_TEST,0xf00,8)
#define BRPHY3_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_MASK           0x0f00
#define BRPHY3_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_ALIGN          0
#define BRPHY3_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_BITS           4
#define BRPHY3_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_SHIFT          8

/* BRPHY3_CL45VEN :: AN_MAN_TEST :: reserved1 [07:03] */
#define BRPHY3_CL45VEN_AN_MAN_TEST_RESERVED1_MASK                  0x00f8
#define BRPHY3_CL45VEN_AN_MAN_TEST_RESERVED1_ALIGN                 0
#define BRPHY3_CL45VEN_AN_MAN_TEST_RESERVED1_BITS                  5
#define BRPHY3_CL45VEN_AN_MAN_TEST_RESERVED1_SHIFT                 3

/* BRPHY3_CL45VEN :: AN_MAN_TEST :: LNK_PARTNR_NXT_PG_TEST_MODE [02:02] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_TEST,0x4,2,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_TEST,0x4,2)
#define BRPHY3_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_MASK 0x0004
#define BRPHY3_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_SHIFT 2

/* BRPHY3_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN_SEED [01:01] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_TEST,0x2,1,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_TEST,0x2,1)
#define BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_MASK           0x0002
#define BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_ALIGN          0
#define BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_BITS           1
#define BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_SHIFT          1

/* BRPHY3_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN [00:00] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_TEST,0x1,0,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_TEST,0x1,0)
#define BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_MASK                0x0001
#define BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_ALIGN               0
#define BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_BITS                1
#define BRPHY3_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SHIFT               0


/****************************************************************************
 * BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A
 ***************************************************************************/
/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_HDX [15:15] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_MASK 0x8000
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_SHIFT 15

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_FDX [14:14] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_MASK 0x4000
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_SHIFT 14

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_PORT_TYPE [13:13] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_MASK 0x2000
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_SHIFT 13

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_CONFIG_VALUE [12:12] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_MASK 0x1000
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_SHIFT 12

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_MANUAL_CONFIG_EN [11:11] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_MASK 0x0800
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_SHIFT 11

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_SEED [10:00] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_MASK    0x07ff
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_ALIGN   0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_BITS    11
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_SHIFT   0


/****************************************************************************
 * BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B
 ***************************************************************************/
/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved0 [15:05] */
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_MASK      0xffe0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_ALIGN     0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_BITS      11
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_SHIFT     5

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PMA_TRAINING_RESET_REQ [04:04] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_MASK 0x0010
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_SHIFT 4

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved1 [03:03] */
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_MASK      0x0008
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_ALIGN     0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_BITS      1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_SHIFT     3

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PHY_SHORT_REACH_MODE [02:02] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_MASK 0x0004
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_SHIFT 2

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_LOOP_TIMING_ABILITY [01:01] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_MASK 0x0002
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_SHIFT 1

/* BRPHY3_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_10GBASET_CAPABILITY [00:00] */
#define Wr_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) WriteRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0,x)
#define Rd_BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) ReadRegBits16(BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0)
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_MASK 0x0001
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_ALIGN 0
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_BITS 1
#define BRPHY3_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_A
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_A :: LP_NP_A [15:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) WriteReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_A,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) ReadReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_A)
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_MASK            0xffff
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_ALIGN           0
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_BITS            16
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_SHIFT           0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_B
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_B :: LP_NP_B [15:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) WriteReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_B,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) ReadReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_B)
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_MASK            0xffff
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_ALIGN           0
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_BITS            16
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_SHIFT           0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_C
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_C :: LP_NP_C [15:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) WriteReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_C,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) ReadReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_C)
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_MASK            0xffff
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_ALIGN           0
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_BITS            16
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_SHIFT           0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_D
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_D :: LP_NP_D [15:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) WriteReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_D,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) ReadReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_D)
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_MASK            0xffff
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_ALIGN           0
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_BITS            16
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_SHIFT           0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_E
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_E :: LP_NP_E [15:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) WriteReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_E,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) ReadReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_E)
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_MASK            0xffff
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_ALIGN           0
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_BITS            16
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_SHIFT           0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_F
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_NXT_PG_F :: LP_NP_F [15:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) WriteReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_F,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) ReadReg16(BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_F)
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_MASK            0xffff
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_ALIGN           0
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_BITS            16
#define BRPHY3_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_SHIFT           0


/****************************************************************************
 * BRPHY3_CL45VEN :: EPON_CTRL_REG
 ***************************************************************************/
/* BRPHY3_CL45VEN :: EPON_CTRL_REG :: reserved0 [15:10] */
#define BRPHY3_CL45VEN_EPON_CTRL_REG_RESERVED0_MASK                0xfc00
#define BRPHY3_CL45VEN_EPON_CTRL_REG_RESERVED0_ALIGN               0
#define BRPHY3_CL45VEN_EPON_CTRL_REG_RESERVED0_BITS                6
#define BRPHY3_CL45VEN_EPON_CTRL_REG_RESERVED0_SHIFT               10

/* BRPHY3_CL45VEN :: EPON_CTRL_REG :: EPON_MODE [09:09] */
#define Wr_BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) WriteRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x200,9,x)
#define Rd_BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) ReadRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x200,9)
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_MASK                0x0200
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_ALIGN               0
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_BITS                1
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_SHIFT               9

/* BRPHY3_CL45VEN :: EPON_CTRL_REG :: EOC_PACKET_NORM [08:08] */
#define Wr_BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) WriteRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x100,8,x)
#define Rd_BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) ReadRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x100,8)
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_MASK          0x0100
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_ALIGN         0
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_BITS          1
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_SHIFT         8

/* BRPHY3_CL45VEN :: EPON_CTRL_REG :: EPON_MODE_CRCCHECK [07:07] */
#define Wr_BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) WriteRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x80,7,x)
#define Rd_BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) ReadRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x80,7)
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_MASK       0x0080
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_ALIGN      0
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_BITS       1
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_SHIFT      7

/* BRPHY3_CL45VEN :: EPON_CTRL_REG :: TX_EN_EXTEND [06:06] */
#define Wr_BRPHY3_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) WriteRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x40,6,x)
#define Rd_BRPHY3_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) ReadRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x40,6)
#define BRPHY3_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_MASK             0x0040
#define BRPHY3_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_ALIGN            0
#define BRPHY3_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_BITS             1
#define BRPHY3_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_SHIFT            6

/* BRPHY3_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POLARITY [05:05] */
#define Wr_BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) WriteRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x20,5,x)
#define Rd_BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) ReadRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x20,5)
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_MASK        0x0020
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_ALIGN       0
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_BITS        1
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_SHIFT       5

/* BRPHY3_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POL_CORR [04:04] */
#define Wr_BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) WriteRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x10,4,x)
#define Rd_BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) ReadRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0x10,4)
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_MASK        0x0010
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_ALIGN       0
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_BITS        1
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_SHIFT       4

/* BRPHY3_CL45VEN :: EPON_CTRL_REG :: EOC_SPEED_DET_THLD [03:00] */
#define Wr_BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) WriteRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0xf,0,x)
#define Rd_BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) ReadRegBits16(BRPHY3_CL45VEN_EPON_CTRL_REG,0xf,0)
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_MASK       0x000f
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_ALIGN      0
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_BITS       4
#define BRPHY3_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_SHIFT      0


/****************************************************************************
 * BRPHY3_CL45VEN :: EEE_TEST_CTRL_A
 ***************************************************************************/
/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: reserved0 [15:12] */
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_MASK              0xf000
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_BITS              4
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_SHIFT             12

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_RX_EN [11:11] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x800,11,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x800,11)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_MASK        0x0800
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_ALIGN       0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_BITS        1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_SHIFT       11

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_TX_EN [10:10] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x400,10,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x400,10)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_MASK        0x0400
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_ALIGN       0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_BITS        1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_SHIFT       10

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_RX_EN [09:09] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x200,9,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x200,9)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_MASK           0x0200
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_ALIGN          0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_BITS           1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_SHIFT          9

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_TX_EN [08:08] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x100,8,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x100,8)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_MASK           0x0100
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_ALIGN          0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_BITS           1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_SHIFT          8

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: LPI_GPCS_TEST_BUS_EN [07:07] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x80,7,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x80,7)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_MASK   0x0080
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_ALIGN  0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_BITS   1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_SHIFT  7

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: MACSEC_PK_MODE [06:06] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x40,6,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x40,6)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_MASK         0x0040
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_ALIGN        0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_BITS         1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_SHIFT        6

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: MSG_11_VS_10 [05:05] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x20,5,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x20,5)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_MASK           0x0020
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_ALIGN          0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_BITS           1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_SHIFT          5

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE [04:04] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x10,4,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x10,4)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_MASK              0x0010
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_ALIGN             0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_BITS              1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFT             4

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE_SHIFTED [03:03] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x8,3,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x8,3)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_MASK      0x0008
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_ALIGN     0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_BITS      1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_SHIFT     3

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: reserved1 [02:02] */
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_MASK              0x0004
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_ALIGN             0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_BITS              1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_SHIFT             2

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LP_M10 [01:01] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x2,1,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x2,1)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_MASK        0x0002
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_ALIGN       0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_BITS        1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_SHIFT       1

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LD_M10 [00:00] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x1,0,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_A,0x1,0)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_MASK        0x0001
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_ALIGN       0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_BITS        1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_SHIFT       0


/****************************************************************************
 * BRPHY3_CL45VEN :: EEE_TEST_CTRL_B
 ***************************************************************************/
/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x8000,15,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x8000,15)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_MASK         0x8000
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_ALIGN        0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_BITS         1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_SHIFT        15

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x4000,14,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x4000,14)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_MASK 0x4000
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_ALIGN 0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_BITS 1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_SHIFT 14

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_LPI_QUALIFIERS [13:13] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x2000,13,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x2000,13)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_MASK 0x2000
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_ALIGN 0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_BITS 1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_SHIFT 13

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_REG_3_20 [12:12] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x1000,12,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x1000,12)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_MASK 0x1000
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_ALIGN 0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_BITS 1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_SHIFT 12

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_RES [11:11] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x800,11,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x800,11)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_MASK       0x0800
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_ALIGN      0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_BITS       1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_SHIFT      11

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_10BASE_T_RES [10:10] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x400,10,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x400,10)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_MASK 0x0400
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_ALIGN 0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_BITS 1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_SHIFT 10

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: DET_SEND_Z [09:09] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x200,9,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x200,9)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_MASK             0x0200
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_ALIGN            0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_BITS             1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_SHIFT            9

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: EN_DET_SEND_Z_OVERRIDE [08:08] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x100,8,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x100,8)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_MASK 0x0100
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_ALIGN 0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_BITS 1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_SHIFT 8

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: REM_UPD_DONE_TEST [07:07] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x80,7,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x80,7)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_MASK      0x0080
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_ALIGN     0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_BITS      1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_SHIFT     7

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: REM_LPI_REQ_TEST [06:06] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x40,6,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x40,6)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_MASK       0x0040
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_ALIGN      0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_BITS       1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_SHIFT      6

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: LOC_UPD_DONE_TEST [05:05] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x20,5,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x20,5)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_MASK      0x0020
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_ALIGN     0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_BITS      1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_SHIFT     5

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: LOC_LPI_REQ_TEST [04:04] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x10,4,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x10,4)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_MASK       0x0010
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_ALIGN      0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_BITS       1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_SHIFT      4

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_UPD_DONE_OVERRIDE [03:03] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x8,3,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x8,3)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_MASK 0x0008
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_SHIFT 3

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_LPI_REQ_OVERRIDE [02:02] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x4,2,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x4,2)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_MASK 0x0004
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_SHIFT 2

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_UPD_DONE_OVERRIDE [01:01] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x2,1,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x2,1)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_MASK 0x0002
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_SHIFT 1

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_LPI_REQ_OVERRIDE [00:00] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x1,0,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_B,0x1,0)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_MASK 0x0001
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: EEE_TEST_CTRL_C
 ***************************************************************************/
/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_RX_EN [15:15] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x8000,15,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x8000,15)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_MASK        0x8000
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_ALIGN       0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_BITS        1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_SHIFT       15

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_TX_EN [14:14] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x4000,14,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x4000,14)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_MASK        0x4000
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_ALIGN       0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_BITS        1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_SHIFT       14

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_RX_EN [13:13] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x2000,13,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x2000,13)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_MASK            0x2000
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_ALIGN           0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_BITS            1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_SHIFT           13

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_TX_EN [12:12] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x1000,12,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x1000,12)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_MASK            0x1000
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_ALIGN           0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_BITS            1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_SHIFT           12

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_RX_EN [11:11] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x800,11,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x800,11)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_MASK        0x0800
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_ALIGN       0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_BITS        1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_SHIFT       11

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_TX_EN [10:10] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x400,10,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x400,10)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_MASK        0x0400
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_ALIGN       0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_BITS        1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_SHIFT       10

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_RX_EN [09:09] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x200,9,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x200,9)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_MASK            0x0200
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_ALIGN           0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_BITS            1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_SHIFT           9

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_TX_EN [08:08] */
#define Wr_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x100,8,x)
#define Rd_BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_TEST_CTRL_C,0x100,8)
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_MASK            0x0100
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_ALIGN           0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_BITS            1
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_SHIFT           8

/* BRPHY3_CL45VEN :: EEE_TEST_CTRL_C :: reserved0 [07:00] */
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_MASK              0x00ff
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_BITS              8
#define BRPHY3_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_SHIFT             0


/****************************************************************************
 * BRPHY3_CL45VEN :: EEE_SPARE_1
 ***************************************************************************/
/* BRPHY3_CL45VEN :: EEE_SPARE_1 :: SPARE [15:00] */
#define Wr_BRPHY3_CL45VEN_EEE_SPARE_1_SPARE(x) WriteReg16(BRPHY3_CL45VEN_EEE_SPARE_1,x)
#define Rd_BRPHY3_CL45VEN_EEE_SPARE_1_SPARE(x) ReadReg16(BRPHY3_CL45VEN_EEE_SPARE_1)
#define BRPHY3_CL45VEN_EEE_SPARE_1_SPARE_MASK                      0xffff
#define BRPHY3_CL45VEN_EEE_SPARE_1_SPARE_ALIGN                     0
#define BRPHY3_CL45VEN_EEE_SPARE_1_SPARE_BITS                      16
#define BRPHY3_CL45VEN_EEE_SPARE_1_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY3_CL45VEN :: EEE_SPARE_2
 ***************************************************************************/
/* BRPHY3_CL45VEN :: EEE_SPARE_2 :: SPARE [15:00] */
#define Wr_BRPHY3_CL45VEN_EEE_SPARE_2_SPARE(x) WriteReg16(BRPHY3_CL45VEN_EEE_SPARE_2,x)
#define Rd_BRPHY3_CL45VEN_EEE_SPARE_2_SPARE(x) ReadReg16(BRPHY3_CL45VEN_EEE_SPARE_2)
#define BRPHY3_CL45VEN_EEE_SPARE_2_SPARE_MASK                      0xffff
#define BRPHY3_CL45VEN_EEE_SPARE_2_SPARE_ALIGN                     0
#define BRPHY3_CL45VEN_EEE_SPARE_2_SPARE_BITS                      16
#define BRPHY3_CL45VEN_EEE_SPARE_2_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY3_CL45VEN :: EEE_CONTROL
 ***************************************************************************/
/* BRPHY3_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x8000,15,x)
#define Rd_BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x8000,15)
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_MASK             0x8000
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_ALIGN            0
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_BITS             1
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_SHIFT            15

/* BRPHY3_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x4000,14,x)
#define Rd_BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x4000,14)
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_MASK    0x4000
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_ALIGN   0
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_BITS    1
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_SHIFT   14

/* BRPHY3_CL45VEN :: EEE_CONTROL :: LPI_RES_IN_FORCE_MODE_EN [13:13] */
#define Wr_BRPHY3_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x2000,13,x)
#define Rd_BRPHY3_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x2000,13)
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_MASK   0x2000
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_ALIGN  0
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_BITS   1
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_SHIFT  13

/* BRPHY3_CL45VEN :: EEE_CONTROL :: SPARE [12:03] */
#define Wr_BRPHY3_CL45VEN_EEE_CONTROL_SPARE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x1ff8,3,x)
#define Rd_BRPHY3_CL45VEN_EEE_CONTROL_SPARE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x1ff8,3)
#define BRPHY3_CL45VEN_EEE_CONTROL_SPARE_MASK                      0x1ff8
#define BRPHY3_CL45VEN_EEE_CONTROL_SPARE_ALIGN                     0
#define BRPHY3_CL45VEN_EEE_CONTROL_SPARE_BITS                      10
#define BRPHY3_CL45VEN_EEE_CONTROL_SPARE_SHIFT                     3

/* BRPHY3_CL45VEN :: EEE_CONTROL :: LPI_LINKUP_DISABLE [02:02] */
#define Wr_BRPHY3_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x4,2,x)
#define Rd_BRPHY3_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x4,2)
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_MASK         0x0004
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_ALIGN        0
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_BITS         1
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_SHIFT        2

/* BRPHY3_CL45VEN :: EEE_CONTROL :: EEE_DOWNGRADE_ENABLE [01:01] */
#define Wr_BRPHY3_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x2,1,x)
#define Rd_BRPHY3_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x2,1)
#define BRPHY3_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_MASK       0x0002
#define BRPHY3_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_ALIGN      0
#define BRPHY3_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_BITS       1
#define BRPHY3_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_SHIFT      1

/* BRPHY3_CL45VEN :: EEE_CONTROL :: LPI_100TX_BRCM_LINK [00:00] */
#define Wr_BRPHY3_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x1,0,x)
#define Rd_BRPHY3_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_CONTROL,0x1,0)
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_MASK        0x0001
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_ALIGN       0
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_BITS        1
#define BRPHY3_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_SHIFT       0


/****************************************************************************
 * BRPHY3_CL45VEN :: EEE_RES_STAT
 ***************************************************************************/
/* BRPHY3_CL45VEN :: EEE_RES_STAT :: reserved0 [15:07] */
#define BRPHY3_CL45VEN_EEE_RES_STAT_RESERVED0_MASK                 0xff80
#define BRPHY3_CL45VEN_EEE_RES_STAT_RESERVED0_ALIGN                0
#define BRPHY3_CL45VEN_EEE_RES_STAT_RESERVED0_BITS                 9
#define BRPHY3_CL45VEN_EEE_RES_STAT_RESERVED0_SHIFT                7

/* BRPHY3_CL45VEN :: EEE_RES_STAT :: MASK_1000T_EEE [06:06] */
#define Wr_BRPHY3_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x40,6,x)
#define Rd_BRPHY3_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x40,6)
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_MASK            0x0040
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_ALIGN           0
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_BITS            1
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_SHIFT           6

/* BRPHY3_CL45VEN :: EEE_RES_STAT :: MASK_100TX_EEE [05:05] */
#define Wr_BRPHY3_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x20,5,x)
#define Rd_BRPHY3_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x20,5)
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_MASK            0x0020
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_ALIGN           0
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_BITS            1
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_SHIFT           5

/* BRPHY3_CL45VEN :: EEE_RES_STAT :: MASK_10T_EEE [04:04] */
#define Wr_BRPHY3_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x10,4,x)
#define Rd_BRPHY3_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x10,4)
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_MASK              0x0010
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_ALIGN             0
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_BITS              1
#define BRPHY3_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_SHIFT             4

/* BRPHY3_CL45VEN :: EEE_RES_STAT :: reserved1 [03:03] */
#define BRPHY3_CL45VEN_EEE_RES_STAT_RESERVED1_MASK                 0x0008
#define BRPHY3_CL45VEN_EEE_RES_STAT_RESERVED1_ALIGN                0
#define BRPHY3_CL45VEN_EEE_RES_STAT_RESERVED1_BITS                 1
#define BRPHY3_CL45VEN_EEE_RES_STAT_RESERVED1_SHIFT                3

/* BRPHY3_CL45VEN :: EEE_RES_STAT :: EEE_1000T_RES [02:02] */
#define Wr_BRPHY3_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x4,2,x)
#define Rd_BRPHY3_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x4,2)
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_MASK             0x0004
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_ALIGN            0
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_BITS             1
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_SHIFT            2

/* BRPHY3_CL45VEN :: EEE_RES_STAT :: EEE_100TX_RES [01:01] */
#define Wr_BRPHY3_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x2,1,x)
#define Rd_BRPHY3_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x2,1)
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_MASK             0x0002
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_ALIGN            0
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_BITS             1
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_SHIFT            1

/* BRPHY3_CL45VEN :: EEE_RES_STAT :: EEE_10BASE_TE_RES [00:00] */
#define Wr_BRPHY3_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) WriteRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x1,0,x)
#define Rd_BRPHY3_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) ReadRegBits16(BRPHY3_CL45VEN_EEE_RES_STAT,0x1,0)
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_MASK         0x0001
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_ALIGN        0
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_BITS         1
#define BRPHY3_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_SHIFT        0


/****************************************************************************
 * BRPHY3_CL45VEN :: LPI_MODE_CNTR
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LPI_MODE_CNTR :: LPI_MODE_COUNTER [15:00] */
#define Wr_BRPHY3_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) WriteReg16(BRPHY3_CL45VEN_LPI_MODE_CNTR,x)
#define Rd_BRPHY3_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) ReadReg16(BRPHY3_CL45VEN_LPI_MODE_CNTR)
#define BRPHY3_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_MASK         0xffff
#define BRPHY3_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_ALIGN        0
#define BRPHY3_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_BITS         16
#define BRPHY3_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_SHIFT        0


/****************************************************************************
 * BRPHY3_CL45VEN :: LOC_DEV_MSG_5_A
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LOC_DEV_MSG_5_A :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_MASK              0xf800
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_BITS              5
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_SHIFT             11

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_5_A :: BITS_10_0_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LOC_DEV_MSG_5_B
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LOC_DEV_MSG_5_B :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_MASK              0xf800
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_BITS              5
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_SHIFT             11

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_5_B :: BITS_21_11_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LOC_DEV_MSG_5_C
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LOC_DEV_MSG_5_C :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_MASK              0xf800
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_BITS              5
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_SHIFT             11

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_5_C :: BITS_32_22_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LOC_DEV_MSG_5_D
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LOC_DEV_MSG_5_D :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_MASK              0xf800
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_BITS              5
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_SHIFT             11

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_5_D :: BITS_43_33_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY3_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_A
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_A :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_MASK           0xf800
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_ALIGN          0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_BITS           5
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_SHIFT          11

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_A :: BITS_10_0_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_B
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_B :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_MASK           0xf800
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_ALIGN          0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_BITS           5
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_SHIFT          11

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_B :: BITS_21_11_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_C
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_C :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_MASK           0xf800
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_ALIGN          0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_BITS           5
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_SHIFT          11

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_C :: BITS_32_22_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_D
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_D :: MSG_5_OUI_MATCH [15:15] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_MASK     0x8000
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_ALIGN    0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_BITS     1
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_SHIFT    15

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_D :: reserved0 [14:11] */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_MASK           0x7800
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_ALIGN          0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_BITS           4
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_SHIFT          11

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_5_D :: BITS_43_33_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LOC_DEV_MSG_6_A
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_A :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_MASK              0xf800
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_BITS              5
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_SHIFT             11

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_A :: BITS_10_0_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LOC_DEV_MSG_6_B
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_B :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_MASK              0xf800
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_BITS              5
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_SHIFT             11

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_21_17_OF_LOC_DEV_MSG_6 [10:06] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_MASK 0x07c0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_BITS 5
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_SHIFT 6

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_16_11_OF_LOC_DEV_MSG_6 [05:00] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_MASK 0x003f
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_BITS 6
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LOC_DEV_MSG_6_C
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_C :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_MASK              0xf800
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_BITS              5
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_SHIFT             11

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_32_23_OF_LOC_DEV_MSG_6 [10:01] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_MASK 0x07fe
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_BITS 10
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_SHIFT 1

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_22_22_OF_LOC_DEV_MSG_6 [00:00] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_C,0x1,0,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_C,0x1,0)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_MASK 0x0001
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_BITS 1
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LOC_DEV_MSG_6_D
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_D :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_MASK              0xf800
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_ALIGN             0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_BITS              5
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_SHIFT             11

/* BRPHY3_CL45VEN :: LOC_DEV_MSG_6_D :: BITS_43_33_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0)
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY3_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_A
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_A :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_MASK           0xf800
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_ALIGN          0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_BITS           5
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_SHIFT          11

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_A :: BITS_10_0_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_B
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_B :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_MASK           0xf800
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_ALIGN          0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_BITS           5
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_SHIFT          11

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_B :: BITS_21_11_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_C
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_C :: reserved0 [15:11] */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_MASK           0xf800
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_ALIGN          0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_BITS           5
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_SHIFT          11

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_C :: BITS_32_22_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_D
 ***************************************************************************/
/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_OUI_MATCH [15:15] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_MASK     0x8000
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_ALIGN    0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_BITS     1
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_SHIFT    15

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_MODEL_MATCH [14:14] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_MASK   0x4000
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_ALIGN  0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_BITS   1
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_SHIFT  14

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_REV_MATCH [13:13] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_MASK     0x2000
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_ALIGN    0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_BITS     1
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_SHIFT    13

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_D :: reserved0 [12:11] */
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_MASK           0x1800
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_ALIGN          0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_BITS           2
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_SHIFT          11

/* BRPHY3_CL45VEN :: LNK_PARTNR_MSG_6_D :: BITS_43_33_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0)
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY3_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_GPHY_CORE
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE10
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE10 :: MAC_PHY_IF [15:15] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_MAC_PHY_IF(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_MAC_PHY_IF(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x8000,15)
#define BRPHY3_GPHY_CORE_BASE10_MAC_PHY_IF_MASK                    0x8000
#define BRPHY3_GPHY_CORE_BASE10_MAC_PHY_IF_ALIGN                   0
#define BRPHY3_GPHY_CORE_BASE10_MAC_PHY_IF_BITS                    1
#define BRPHY3_GPHY_CORE_BASE10_MAC_PHY_IF_SHIFT                   15

/* BRPHY3_GPHY_CORE :: BASE10 :: AUTO_MDIX_DIS [14:14] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x4000,14)
#define BRPHY3_GPHY_CORE_BASE10_AUTO_MDIX_DIS_MASK                 0x4000
#define BRPHY3_GPHY_CORE_BASE10_AUTO_MDIX_DIS_ALIGN                0
#define BRPHY3_GPHY_CORE_BASE10_AUTO_MDIX_DIS_BITS                 1
#define BRPHY3_GPHY_CORE_BASE10_AUTO_MDIX_DIS_SHIFT                14

/* BRPHY3_GPHY_CORE :: BASE10 :: TX_DIS [13:13] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_TX_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_TX_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x2000,13)
#define BRPHY3_GPHY_CORE_BASE10_TX_DIS_MASK                        0x2000
#define BRPHY3_GPHY_CORE_BASE10_TX_DIS_ALIGN                       0
#define BRPHY3_GPHY_CORE_BASE10_TX_DIS_BITS                        1
#define BRPHY3_GPHY_CORE_BASE10_TX_DIS_SHIFT                       13

/* BRPHY3_GPHY_CORE :: BASE10 :: INT_DIS [12:12] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_INT_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_INT_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x1000,12)
#define BRPHY3_GPHY_CORE_BASE10_INT_DIS_MASK                       0x1000
#define BRPHY3_GPHY_CORE_BASE10_INT_DIS_ALIGN                      0
#define BRPHY3_GPHY_CORE_BASE10_INT_DIS_BITS                       1
#define BRPHY3_GPHY_CORE_BASE10_INT_DIS_SHIFT                      12

/* BRPHY3_GPHY_CORE :: BASE10 :: FORCE_INT [11:11] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_FORCE_INT(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_FORCE_INT(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x800,11)
#define BRPHY3_GPHY_CORE_BASE10_FORCE_INT_MASK                     0x0800
#define BRPHY3_GPHY_CORE_BASE10_FORCE_INT_ALIGN                    0
#define BRPHY3_GPHY_CORE_BASE10_FORCE_INT_BITS                     1
#define BRPHY3_GPHY_CORE_BASE10_FORCE_INT_SHIFT                    11

/* BRPHY3_GPHY_CORE :: BASE10 :: BYPASS_ENCODER [10:10] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_BYPASS_ENCODER(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_BYPASS_ENCODER(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x400,10)
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_ENCODER_MASK                0x0400
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_ENCODER_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_ENCODER_BITS                1
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_ENCODER_SHIFT               10

/* BRPHY3_GPHY_CORE :: BASE10 :: BYPASS_SCRAMBLER [09:09] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x200,9)
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_MASK              0x0200
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_ALIGN             0
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_BITS              1
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_SHIFT             9

/* BRPHY3_GPHY_CORE :: BASE10 :: BYPASS_NRZI_MLT3 [08:08] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x100,8)
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_MASK              0x0100
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_ALIGN             0
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_BITS              1
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_SHIFT             8

/* BRPHY3_GPHY_CORE :: BASE10 :: BYPASS_ALIGNMENT [07:07] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x80,7)
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_MASK              0x0080
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_ALIGN             0
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_BITS              1
#define BRPHY3_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_SHIFT             7

/* BRPHY3_GPHY_CORE :: BASE10 :: RESET_SCRAMBLER [06:06] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x40,6)
#define BRPHY3_GPHY_CORE_BASE10_RESET_SCRAMBLER_MASK               0x0040
#define BRPHY3_GPHY_CORE_BASE10_RESET_SCRAMBLER_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE10_RESET_SCRAMBLER_BITS               1
#define BRPHY3_GPHY_CORE_BASE10_RESET_SCRAMBLER_SHIFT              6

/* BRPHY3_GPHY_CORE :: BASE10 :: LED_TRAFFIC_EN [05:05] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x20,5)
#define BRPHY3_GPHY_CORE_BASE10_LED_TRAFFIC_EN_MASK                0x0020
#define BRPHY3_GPHY_CORE_BASE10_LED_TRAFFIC_EN_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE10_LED_TRAFFIC_EN_BITS                1
#define BRPHY3_GPHY_CORE_BASE10_LED_TRAFFIC_EN_SHIFT               5

/* BRPHY3_GPHY_CORE :: BASE10 :: FORCE_LEDS_ON [04:04] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x10,4)
#define BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_ON_MASK                 0x0010
#define BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_ON_ALIGN                0
#define BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_ON_BITS                 1
#define BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_ON_SHIFT                4

/* BRPHY3_GPHY_CORE :: BASE10 :: FORCE_LEDS_OFF [03:03] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x8,3)
#define BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_OFF_MASK                0x0008
#define BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_OFF_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_OFF_BITS                1
#define BRPHY3_GPHY_CORE_BASE10_FORCE_LEDS_OFF_SHIFT               3

/* BRPHY3_GPHY_CORE :: BASE10 :: BLOCK_TXEN [02:02] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_BLOCK_TXEN(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_BLOCK_TXEN(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x4,2)
#define BRPHY3_GPHY_CORE_BASE10_BLOCK_TXEN_MASK                    0x0004
#define BRPHY3_GPHY_CORE_BASE10_BLOCK_TXEN_ALIGN                   0
#define BRPHY3_GPHY_CORE_BASE10_BLOCK_TXEN_BITS                    1
#define BRPHY3_GPHY_CORE_BASE10_BLOCK_TXEN_SHIFT                   2

/* BRPHY3_GPHY_CORE :: BASE10 :: UNIDIR_EN [01:01] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_UNIDIR_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_UNIDIR_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x2,1)
#define BRPHY3_GPHY_CORE_BASE10_UNIDIR_EN_MASK                     0x0002
#define BRPHY3_GPHY_CORE_BASE10_UNIDIR_EN_ALIGN                    0
#define BRPHY3_GPHY_CORE_BASE10_UNIDIR_EN_BITS                     1
#define BRPHY3_GPHY_CORE_BASE10_UNIDIR_EN_SHIFT                    1

/* BRPHY3_GPHY_CORE :: BASE10 :: GMII_RGMII_FIFO_ELASTICITY [00:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE10,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE10,0x1,0)
#define BRPHY3_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_MASK    0x0001
#define BRPHY3_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_ALIGN   0
#define BRPHY3_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_BITS    1
#define BRPHY3_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_SHIFT   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE11
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE11 :: AUTONEG_FIELD_MISMATCH [15:15] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x8000,15)
#define BRPHY3_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_MASK        0x8000
#define BRPHY3_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_ALIGN       0
#define BRPHY3_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_BITS        1
#define BRPHY3_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_SHIFT       15

/* BRPHY3_GPHY_CORE :: BASE11 :: WIRESPD_DOWNGRADE [14:14] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x4000,14)
#define BRPHY3_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_MASK             0x4000
#define BRPHY3_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_ALIGN            0
#define BRPHY3_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_BITS             1
#define BRPHY3_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_SHIFT            14

/* BRPHY3_GPHY_CORE :: BASE11 :: MDIX_STATE [13:13] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_MDIX_STATE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_MDIX_STATE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x2000,13)
#define BRPHY3_GPHY_CORE_BASE11_MDIX_STATE_MASK                    0x2000
#define BRPHY3_GPHY_CORE_BASE11_MDIX_STATE_ALIGN                   0
#define BRPHY3_GPHY_CORE_BASE11_MDIX_STATE_BITS                    1
#define BRPHY3_GPHY_CORE_BASE11_MDIX_STATE_SHIFT                   13

/* BRPHY3_GPHY_CORE :: BASE11 :: INT_STATUS [12:12] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_INT_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_INT_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x1000,12)
#define BRPHY3_GPHY_CORE_BASE11_INT_STATUS_MASK                    0x1000
#define BRPHY3_GPHY_CORE_BASE11_INT_STATUS_ALIGN                   0
#define BRPHY3_GPHY_CORE_BASE11_INT_STATUS_BITS                    1
#define BRPHY3_GPHY_CORE_BASE11_INT_STATUS_SHIFT                   12

/* BRPHY3_GPHY_CORE :: BASE11 :: RMT_RCVR_STATUS [11:11] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x800,11)
#define BRPHY3_GPHY_CORE_BASE11_RMT_RCVR_STATUS_MASK               0x0800
#define BRPHY3_GPHY_CORE_BASE11_RMT_RCVR_STATUS_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE11_RMT_RCVR_STATUS_BITS               1
#define BRPHY3_GPHY_CORE_BASE11_RMT_RCVR_STATUS_SHIFT              11

/* BRPHY3_GPHY_CORE :: BASE11 :: LOCAL_RCVR_STATUS [10:10] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x400,10)
#define BRPHY3_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_MASK             0x0400
#define BRPHY3_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_ALIGN            0
#define BRPHY3_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_BITS             1
#define BRPHY3_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_SHIFT            10

/* BRPHY3_GPHY_CORE :: BASE11 :: LOCKED [09:09] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_LOCKED(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_LOCKED(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x200,9)
#define BRPHY3_GPHY_CORE_BASE11_LOCKED_MASK                        0x0200
#define BRPHY3_GPHY_CORE_BASE11_LOCKED_ALIGN                       0
#define BRPHY3_GPHY_CORE_BASE11_LOCKED_BITS                        1
#define BRPHY3_GPHY_CORE_BASE11_LOCKED_SHIFT                       9

/* BRPHY3_GPHY_CORE :: BASE11 :: LINK_STATUS [08:08] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_LINK_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_LINK_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x100,8)
#define BRPHY3_GPHY_CORE_BASE11_LINK_STATUS_MASK                   0x0100
#define BRPHY3_GPHY_CORE_BASE11_LINK_STATUS_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE11_LINK_STATUS_BITS                   1
#define BRPHY3_GPHY_CORE_BASE11_LINK_STATUS_SHIFT                  8

/* BRPHY3_GPHY_CORE :: BASE11 :: CRC_ERR_DET [07:07] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_CRC_ERR_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_CRC_ERR_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x80,7)
#define BRPHY3_GPHY_CORE_BASE11_CRC_ERR_DET_MASK                   0x0080
#define BRPHY3_GPHY_CORE_BASE11_CRC_ERR_DET_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE11_CRC_ERR_DET_BITS                   1
#define BRPHY3_GPHY_CORE_BASE11_CRC_ERR_DET_SHIFT                  7

/* BRPHY3_GPHY_CORE :: BASE11 :: CR_EXT_ERR_DET [06:06] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x40,6)
#define BRPHY3_GPHY_CORE_BASE11_CR_EXT_ERR_DET_MASK                0x0040
#define BRPHY3_GPHY_CORE_BASE11_CR_EXT_ERR_DET_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE11_CR_EXT_ERR_DET_BITS                1
#define BRPHY3_GPHY_CORE_BASE11_CR_EXT_ERR_DET_SHIFT               6

/* BRPHY3_GPHY_CORE :: BASE11 :: BAD_SSD_DET_CR [05:05] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x20,5)
#define BRPHY3_GPHY_CORE_BASE11_BAD_SSD_DET_CR_MASK                0x0020
#define BRPHY3_GPHY_CORE_BASE11_BAD_SSD_DET_CR_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE11_BAD_SSD_DET_CR_BITS                1
#define BRPHY3_GPHY_CORE_BASE11_BAD_SSD_DET_CR_SHIFT               5

/* BRPHY3_GPHY_CORE :: BASE11 :: BAD_ESD_DET_END [04:04] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x10,4)
#define BRPHY3_GPHY_CORE_BASE11_BAD_ESD_DET_END_MASK               0x0010
#define BRPHY3_GPHY_CORE_BASE11_BAD_ESD_DET_END_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE11_BAD_ESD_DET_END_BITS               1
#define BRPHY3_GPHY_CORE_BASE11_BAD_ESD_DET_END_SHIFT              4

/* BRPHY3_GPHY_CORE :: BASE11 :: RCV_ERR_DET [03:03] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_RCV_ERR_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_RCV_ERR_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x8,3)
#define BRPHY3_GPHY_CORE_BASE11_RCV_ERR_DET_MASK                   0x0008
#define BRPHY3_GPHY_CORE_BASE11_RCV_ERR_DET_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE11_RCV_ERR_DET_BITS                   1
#define BRPHY3_GPHY_CORE_BASE11_RCV_ERR_DET_SHIFT                  3

/* BRPHY3_GPHY_CORE :: BASE11 :: TX_ERR_DET [02:02] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_TX_ERR_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_TX_ERR_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x4,2)
#define BRPHY3_GPHY_CORE_BASE11_TX_ERR_DET_MASK                    0x0004
#define BRPHY3_GPHY_CORE_BASE11_TX_ERR_DET_ALIGN                   0
#define BRPHY3_GPHY_CORE_BASE11_TX_ERR_DET_BITS                    1
#define BRPHY3_GPHY_CORE_BASE11_TX_ERR_DET_SHIFT                   2

/* BRPHY3_GPHY_CORE :: BASE11 :: LOCK_ERR_DET [01:01] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_LOCK_ERR_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_LOCK_ERR_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x2,1)
#define BRPHY3_GPHY_CORE_BASE11_LOCK_ERR_DET_MASK                  0x0002
#define BRPHY3_GPHY_CORE_BASE11_LOCK_ERR_DET_ALIGN                 0
#define BRPHY3_GPHY_CORE_BASE11_LOCK_ERR_DET_BITS                  1
#define BRPHY3_GPHY_CORE_BASE11_LOCK_ERR_DET_SHIFT                 1

/* BRPHY3_GPHY_CORE :: BASE11 :: MLT3_ERR_DET [00:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE11_MLT3_ERR_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE11,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE11_MLT3_ERR_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE11,0x1,0)
#define BRPHY3_GPHY_CORE_BASE11_MLT3_ERR_DET_MASK                  0x0001
#define BRPHY3_GPHY_CORE_BASE11_MLT3_ERR_DET_ALIGN                 0
#define BRPHY3_GPHY_CORE_BASE11_MLT3_ERR_DET_BITS                  1
#define BRPHY3_GPHY_CORE_BASE11_MLT3_ERR_DET_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE12
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE12 :: RCV_ERR_CNTR [15:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) WriteReg16(BRPHY3_GPHY_CORE_BASE12,x)
#define Rd_BRPHY3_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) ReadReg16(BRPHY3_GPHY_CORE_BASE12)
#define BRPHY3_GPHY_CORE_BASE12_RCV_ERR_CNTR_MASK                  0xffff
#define BRPHY3_GPHY_CORE_BASE12_RCV_ERR_CNTR_ALIGN                 0
#define BRPHY3_GPHY_CORE_BASE12_RCV_ERR_CNTR_BITS                  16
#define BRPHY3_GPHY_CORE_BASE12_RCV_ERR_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE13
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE13 :: SERDES_BER_CNTR [15:08] */
#define Wr_BRPHY3_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE13,0xff00,8,x)
#define Rd_BRPHY3_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE13,0xff00,8)
#define BRPHY3_GPHY_CORE_BASE13_SERDES_BER_CNTR_MASK               0xff00
#define BRPHY3_GPHY_CORE_BASE13_SERDES_BER_CNTR_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE13_SERDES_BER_CNTR_BITS               8
#define BRPHY3_GPHY_CORE_BASE13_SERDES_BER_CNTR_SHIFT              8

/* BRPHY3_GPHY_CORE :: BASE13 :: FALSE_CRS_CNTR [07:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE13,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE13,0xff,0)
#define BRPHY3_GPHY_CORE_BASE13_FALSE_CRS_CNTR_MASK                0x00ff
#define BRPHY3_GPHY_CORE_BASE13_FALSE_CRS_CNTR_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE13_FALSE_CRS_CNTR_BITS                8
#define BRPHY3_GPHY_CORE_BASE13_FALSE_CRS_CNTR_SHIFT               0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE14
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE14 :: LOCAL_RCVR_NOK_CNTR [15:08] */
#define Wr_BRPHY3_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE14,0xff00,8,x)
#define Rd_BRPHY3_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE14,0xff00,8)
#define BRPHY3_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_MASK           0xff00
#define BRPHY3_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_ALIGN          0
#define BRPHY3_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_BITS           8
#define BRPHY3_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_SHIFT          8

/* BRPHY3_GPHY_CORE :: BASE14 :: REMOTE_RCVR_NOK_CNTR [07:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE14,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE14,0xff,0)
#define BRPHY3_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_MASK          0x00ff
#define BRPHY3_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_ALIGN         0
#define BRPHY3_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_BITS          8
#define BRPHY3_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_SHIFT         0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP45
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP45 :: SEL_SERDES_TX [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXP45_SEL_SERDES_TX(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP45,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXP45_SEL_SERDES_TX(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP45,0x8000,15)
#define BRPHY3_GPHY_CORE_EXP45_SEL_SERDES_TX_MASK                  0x8000
#define BRPHY3_GPHY_CORE_EXP45_SEL_SERDES_TX_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP45_SEL_SERDES_TX_BITS                  1
#define BRPHY3_GPHY_CORE_EXP45_SEL_SERDES_TX_SHIFT                 15

/* BRPHY3_GPHY_CORE :: EXP45 :: TX_ERR [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXP45_TX_ERR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP45,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXP45_TX_ERR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP45,0x4000,14)
#define BRPHY3_GPHY_CORE_EXP45_TX_ERR_MASK                         0x4000
#define BRPHY3_GPHY_CORE_EXP45_TX_ERR_ALIGN                        0
#define BRPHY3_GPHY_CORE_EXP45_TX_ERR_BITS                         1
#define BRPHY3_GPHY_CORE_EXP45_TX_ERR_SHIFT                        14

/* BRPHY3_GPHY_CORE :: EXP45 :: SKIP_CRC [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXP45_SKIP_CRC(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP45,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXP45_SKIP_CRC(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP45,0x2000,13)
#define BRPHY3_GPHY_CORE_EXP45_SKIP_CRC_MASK                       0x2000
#define BRPHY3_GPHY_CORE_EXP45_SKIP_CRC_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP45_SKIP_CRC_BITS                       1
#define BRPHY3_GPHY_CORE_EXP45_SKIP_CRC_SHIFT                      13

/* BRPHY3_GPHY_CORE :: EXP45 :: TX_CRC_CHECKER_EN [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP45,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP45,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_MASK              0x1000
#define BRPHY3_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_BITS              1
#define BRPHY3_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_SHIFT             12

/* BRPHY3_GPHY_CORE :: EXP45 :: IPG_SEL [11:09] */
#define Wr_BRPHY3_GPHY_CORE_EXP45_IPG_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP45,0xe00,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXP45_IPG_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP45,0xe00,9)
#define BRPHY3_GPHY_CORE_EXP45_IPG_SEL_MASK                        0x0e00
#define BRPHY3_GPHY_CORE_EXP45_IPG_SEL_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP45_IPG_SEL_BITS                        3
#define BRPHY3_GPHY_CORE_EXP45_IPG_SEL_SHIFT                       9

/* BRPHY3_GPHY_CORE :: EXP45 :: PKT_SIZE [08:03] */
#define Wr_BRPHY3_GPHY_CORE_EXP45_PKT_SIZE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP45,0x1f8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXP45_PKT_SIZE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP45,0x1f8,3)
#define BRPHY3_GPHY_CORE_EXP45_PKT_SIZE_MASK                       0x01f8
#define BRPHY3_GPHY_CORE_EXP45_PKT_SIZE_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP45_PKT_SIZE_BITS                       6
#define BRPHY3_GPHY_CORE_EXP45_PKT_SIZE_SHIFT                      3

/* BRPHY3_GPHY_CORE :: EXP45 :: SINGLE_PASS [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP45_SINGLE_PASS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP45,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP45_SINGLE_PASS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP45,0x4,2)
#define BRPHY3_GPHY_CORE_EXP45_SINGLE_PASS_MASK                    0x0004
#define BRPHY3_GPHY_CORE_EXP45_SINGLE_PASS_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP45_SINGLE_PASS_BITS                    1
#define BRPHY3_GPHY_CORE_EXP45_SINGLE_PASS_SHIFT                   2

/* BRPHY3_GPHY_CORE :: EXP45 :: RUN_PAT_GEN [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP45_RUN_PAT_GEN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP45,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP45_RUN_PAT_GEN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP45,0x2,1)
#define BRPHY3_GPHY_CORE_EXP45_RUN_PAT_GEN_MASK                    0x0002
#define BRPHY3_GPHY_CORE_EXP45_RUN_PAT_GEN_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP45_RUN_PAT_GEN_BITS                    1
#define BRPHY3_GPHY_CORE_EXP45_RUN_PAT_GEN_SHIFT                   1

/* BRPHY3_GPHY_CORE :: EXP45 :: SEL_PAT_GEN_DATA [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP45,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP45,0x1,0)
#define BRPHY3_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_MASK               0x0001
#define BRPHY3_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_BITS               1
#define BRPHY3_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP46
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP46 :: GMII_FIFO_ELASTICITY_1 [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP46,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP46,0x8000,15)
#define BRPHY3_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_MASK         0x8000
#define BRPHY3_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_ALIGN        0
#define BRPHY3_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_BITS         1
#define BRPHY3_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_SHIFT        15

/* BRPHY3_GPHY_CORE :: EXP46 :: GMII_RGMII_FIFO_ELASTICITY_1 [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP46,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP46,0x4000,14)
#define BRPHY3_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_MASK   0x4000
#define BRPHY3_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_ALIGN  0
#define BRPHY3_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_BITS   1
#define BRPHY3_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_SHIFT  14

/* BRPHY3_GPHY_CORE :: EXP46 :: PKT_SIZE_6 [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXP46_PKT_SIZE_6(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP46,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXP46_PKT_SIZE_6(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP46,0x2000,13)
#define BRPHY3_GPHY_CORE_EXP46_PKT_SIZE_6_MASK                     0x2000
#define BRPHY3_GPHY_CORE_EXP46_PKT_SIZE_6_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP46_PKT_SIZE_6_BITS                     1
#define BRPHY3_GPHY_CORE_EXP46_PKT_SIZE_6_SHIFT                    13

/* BRPHY3_GPHY_CORE :: EXP46 :: CR_EXT [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP46_CR_EXT(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP46,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP46_CR_EXT(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP46,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP46_CR_EXT_MASK                         0x1000
#define BRPHY3_GPHY_CORE_EXP46_CR_EXT_ALIGN                        0
#define BRPHY3_GPHY_CORE_EXP46_CR_EXT_BITS                         1
#define BRPHY3_GPHY_CORE_EXP46_CR_EXT_SHIFT                        12

/* BRPHY3_GPHY_CORE :: EXP46 :: reserved0 [11:07] */
#define BRPHY3_GPHY_CORE_EXP46_RESERVED0_MASK                      0x0f80
#define BRPHY3_GPHY_CORE_EXP46_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP46_RESERVED0_BITS                      5
#define BRPHY3_GPHY_CORE_EXP46_RESERVED0_SHIFT                     7

/* BRPHY3_GPHY_CORE :: EXP46 :: RGMII_FIFO_FREQ_LOCK [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP46,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP46,0x40,6)
#define BRPHY3_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_MASK           0x0040
#define BRPHY3_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_ALIGN          0
#define BRPHY3_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_BITS           1
#define BRPHY3_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_SHIFT          6

/* BRPHY3_GPHY_CORE :: EXP46 :: reserved1 [05:05] */
#define BRPHY3_GPHY_CORE_EXP46_RESERVED1_MASK                      0x0020
#define BRPHY3_GPHY_CORE_EXP46_RESERVED1_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP46_RESERVED1_BITS                      1
#define BRPHY3_GPHY_CORE_EXP46_RESERVED1_SHIFT                     5

/* BRPHY3_GPHY_CORE :: EXP46 :: SEL_PATGEN_ON_RXD [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP46,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP46,0x10,4)
#define BRPHY3_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_MASK              0x0010
#define BRPHY3_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_BITS              1
#define BRPHY3_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_SHIFT             4

/* BRPHY3_GPHY_CORE :: EXP46 :: PAT_GEN_ACTIVE [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP46,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP46,0x8,3)
#define BRPHY3_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_MASK                 0x0008
#define BRPHY3_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_BITS                 1
#define BRPHY3_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_SHIFT                3

/* BRPHY3_GPHY_CORE :: EXP46 :: PAT_GEN_FSM [02:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP46_PAT_GEN_FSM(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP46,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP46_PAT_GEN_FSM(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP46,0x7,0)
#define BRPHY3_GPHY_CORE_EXP46_PAT_GEN_FSM_MASK                    0x0007
#define BRPHY3_GPHY_CORE_EXP46_PAT_GEN_FSM_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP46_PAT_GEN_FSM_BITS                    3
#define BRPHY3_GPHY_CORE_EXP46_PAT_GEN_FSM_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE19
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE [15:15] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x8000,15)
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_MASK              0x8000
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ALIGN             0
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_BITS              1
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_SHIFT             15

/* BRPHY3_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE_ACK [14:14] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x4000,14)
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_MASK          0x4000
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_ALIGN         0
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_BITS          1
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_SHIFT         14

/* BRPHY3_GPHY_CORE :: BASE19 :: AUTONEG_ACK_DET [13:13] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x2000,13)
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_ACK_DET_MASK               0x2000
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_ACK_DET_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_ACK_DET_BITS               1
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_ACK_DET_SHIFT              13

/* BRPHY3_GPHY_CORE :: BASE19 :: AUTONEG_ABILITY_DET [12:12] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x1000,12)
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_MASK           0x1000
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_ALIGN          0
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_BITS           1
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_SHIFT          12

/* BRPHY3_GPHY_CORE :: BASE19 :: AUTONEG_NEXT_PAGE_WAIT [11:11] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x800,11)
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_MASK        0x0800
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_ALIGN       0
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_BITS        1
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_SHIFT       11

/* BRPHY3_GPHY_CORE :: BASE19 :: AUTONEG_HCD [10:08] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_AUTONEG_HCD(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x700,8,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_AUTONEG_HCD(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x700,8)
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_HCD_MASK                   0x0700
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_HCD_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_HCD_BITS                   3
#define BRPHY3_GPHY_CORE_BASE19_AUTONEG_HCD_SHIFT                  8

/* BRPHY3_GPHY_CORE :: BASE19 :: PARALLEL_DET_FAULT [07:07] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x80,7)
#define BRPHY3_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_MASK            0x0080
#define BRPHY3_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_ALIGN           0
#define BRPHY3_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_BITS            1
#define BRPHY3_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_SHIFT           7

/* BRPHY3_GPHY_CORE :: BASE19 :: REMOTE_FAULT [06:06] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_REMOTE_FAULT(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_REMOTE_FAULT(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x40,6)
#define BRPHY3_GPHY_CORE_BASE19_REMOTE_FAULT_MASK                  0x0040
#define BRPHY3_GPHY_CORE_BASE19_REMOTE_FAULT_ALIGN                 0
#define BRPHY3_GPHY_CORE_BASE19_REMOTE_FAULT_BITS                  1
#define BRPHY3_GPHY_CORE_BASE19_REMOTE_FAULT_SHIFT                 6

/* BRPHY3_GPHY_CORE :: BASE19 :: PAGE_RECEIVED [05:05] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_PAGE_RECEIVED(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_PAGE_RECEIVED(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x20,5)
#define BRPHY3_GPHY_CORE_BASE19_PAGE_RECEIVED_MASK                 0x0020
#define BRPHY3_GPHY_CORE_BASE19_PAGE_RECEIVED_ALIGN                0
#define BRPHY3_GPHY_CORE_BASE19_PAGE_RECEIVED_BITS                 1
#define BRPHY3_GPHY_CORE_BASE19_PAGE_RECEIVED_SHIFT                5

/* BRPHY3_GPHY_CORE :: BASE19 :: LINK_PARTNER_AN_ABILITY [04:04] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x10,4)
#define BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_MASK       0x0010
#define BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_SHIFT      4

/* BRPHY3_GPHY_CORE :: BASE19 :: LINK_PARTNER_NP_ABILITY [03:03] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x8,3)
#define BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_MASK       0x0008
#define BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_ALIGN      0
#define BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_BITS       1
#define BRPHY3_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_SHIFT      3

/* BRPHY3_GPHY_CORE :: BASE19 :: LINK_STATUS [02:02] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_LINK_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_LINK_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x4,2)
#define BRPHY3_GPHY_CORE_BASE19_LINK_STATUS_MASK                   0x0004
#define BRPHY3_GPHY_CORE_BASE19_LINK_STATUS_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE19_LINK_STATUS_BITS                   1
#define BRPHY3_GPHY_CORE_BASE19_LINK_STATUS_SHIFT                  2

/* BRPHY3_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_RX [01:01] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x2,1)
#define BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_MASK           0x0002
#define BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_ALIGN          0
#define BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_BITS           1
#define BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_SHIFT          1

/* BRPHY3_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_TX [00:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE19,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE19,0x1,0)
#define BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_MASK           0x0001
#define BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_ALIGN          0
#define BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_BITS           1
#define BRPHY3_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_SHIFT          0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE1A
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE1A :: IP_STATUS_CHANGE [15:15] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x8000,15)
#define BRPHY3_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_MASK              0x8000
#define BRPHY3_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_ALIGN             0
#define BRPHY3_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_BITS              1
#define BRPHY3_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_SHIFT             15

/* BRPHY3_GPHY_CORE :: BASE1A :: ILLEGAL_PAIR_SWAP [14:14] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x4000,14)
#define BRPHY3_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_MASK             0x4000
#define BRPHY3_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_ALIGN            0
#define BRPHY3_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_BITS             1
#define BRPHY3_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_SHIFT            14

/* BRPHY3_GPHY_CORE :: BASE1A :: MDIX_STATUS_CHANGE [13:13] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x2000,13)
#define BRPHY3_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_MASK            0x2000
#define BRPHY3_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_ALIGN           0
#define BRPHY3_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_BITS            1
#define BRPHY3_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_SHIFT           13

/* BRPHY3_GPHY_CORE :: BASE1A :: EXCEED_HIGH_CNTR_THD [12:12] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x1000,12)
#define BRPHY3_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_MASK          0x1000
#define BRPHY3_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_ALIGN         0
#define BRPHY3_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_BITS          1
#define BRPHY3_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_SHIFT         12

/* BRPHY3_GPHY_CORE :: BASE1A :: EXCEED_LOW_CNTR_THD [11:11] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x800,11)
#define BRPHY3_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_MASK           0x0800
#define BRPHY3_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_ALIGN          0
#define BRPHY3_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_BITS           1
#define BRPHY3_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_SHIFT          11

/* BRPHY3_GPHY_CORE :: BASE1A :: AUTONEG_PAGE_RX [10:10] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x400,10)
#define BRPHY3_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_MASK               0x0400
#define BRPHY3_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_BITS               1
#define BRPHY3_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_SHIFT              10

/* BRPHY3_GPHY_CORE :: BASE1A :: HCD_NO_LINK [09:09] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_HCD_NO_LINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_HCD_NO_LINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x200,9)
#define BRPHY3_GPHY_CORE_BASE1A_HCD_NO_LINK_MASK                   0x0200
#define BRPHY3_GPHY_CORE_BASE1A_HCD_NO_LINK_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE1A_HCD_NO_LINK_BITS                   1
#define BRPHY3_GPHY_CORE_BASE1A_HCD_NO_LINK_SHIFT                  9

/* BRPHY3_GPHY_CORE :: BASE1A :: NO_HCD [08:08] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_NO_HCD(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_NO_HCD(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x100,8)
#define BRPHY3_GPHY_CORE_BASE1A_NO_HCD_MASK                        0x0100
#define BRPHY3_GPHY_CORE_BASE1A_NO_HCD_ALIGN                       0
#define BRPHY3_GPHY_CORE_BASE1A_NO_HCD_BITS                        1
#define BRPHY3_GPHY_CORE_BASE1A_NO_HCD_SHIFT                       8

/* BRPHY3_GPHY_CORE :: BASE1A :: NEGOTIATED_UNSUPPORTED_HCD [07:07] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x80,7)
#define BRPHY3_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_MASK    0x0080
#define BRPHY3_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_ALIGN   0
#define BRPHY3_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_BITS    1
#define BRPHY3_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_SHIFT   7

/* BRPHY3_GPHY_CORE :: BASE1A :: SCR_SYNC_ERROR [06:06] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x40,6)
#define BRPHY3_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_MASK                0x0040
#define BRPHY3_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_BITS                1
#define BRPHY3_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_SHIFT               6

/* BRPHY3_GPHY_CORE :: BASE1A :: RMT_RCVR_STATUS_CHANGE [05:05] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x20,5)
#define BRPHY3_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_MASK        0x0020
#define BRPHY3_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_ALIGN       0
#define BRPHY3_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_BITS        1
#define BRPHY3_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_SHIFT       5

/* BRPHY3_GPHY_CORE :: BASE1A :: LOCAL_RCVR_STATUS_CHANGE [04:04] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x10,4)
#define BRPHY3_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_MASK      0x0010
#define BRPHY3_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_ALIGN     0
#define BRPHY3_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_BITS      1
#define BRPHY3_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_SHIFT     4

/* BRPHY3_GPHY_CORE :: BASE1A :: DUPLEX_CHANGE [03:03] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x8,3)
#define BRPHY3_GPHY_CORE_BASE1A_DUPLEX_CHANGE_MASK                 0x0008
#define BRPHY3_GPHY_CORE_BASE1A_DUPLEX_CHANGE_ALIGN                0
#define BRPHY3_GPHY_CORE_BASE1A_DUPLEX_CHANGE_BITS                 1
#define BRPHY3_GPHY_CORE_BASE1A_DUPLEX_CHANGE_SHIFT                3

/* BRPHY3_GPHY_CORE :: BASE1A :: LINK_SPEED_CHANGE [02:02] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x4,2)
#define BRPHY3_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_MASK             0x0004
#define BRPHY3_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_ALIGN            0
#define BRPHY3_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_BITS             1
#define BRPHY3_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_SHIFT            2

/* BRPHY3_GPHY_CORE :: BASE1A :: LINK_STATUS_CHANGE [01:01] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x2,1)
#define BRPHY3_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_MASK            0x0002
#define BRPHY3_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_ALIGN           0
#define BRPHY3_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_BITS            1
#define BRPHY3_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_SHIFT           1

/* BRPHY3_GPHY_CORE :: BASE1A :: CRC_ERROR [00:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE1A_CRC_ERROR(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1A_CRC_ERROR(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1A,0x1,0)
#define BRPHY3_GPHY_CORE_BASE1A_CRC_ERROR_MASK                     0x0001
#define BRPHY3_GPHY_CORE_BASE1A_CRC_ERROR_ALIGN                    0
#define BRPHY3_GPHY_CORE_BASE1A_CRC_ERROR_BITS                     1
#define BRPHY3_GPHY_CORE_BASE1A_CRC_ERROR_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE1B
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE1B :: INT_MASK_VECTOR [15:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) WriteReg16(BRPHY3_GPHY_CORE_BASE1B,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) ReadReg16(BRPHY3_GPHY_CORE_BASE1B)
#define BRPHY3_GPHY_CORE_BASE1B_INT_MASK_VECTOR_MASK               0xffff
#define BRPHY3_GPHY_CORE_BASE1B_INT_MASK_VECTOR_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE1B_INT_MASK_VECTOR_BITS               16
#define BRPHY3_GPHY_CORE_BASE1B_INT_MASK_VECTOR_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE1D_SHD
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x8000,15)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_MASK    0x8000
#define BRPHY3_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_ALIGN   0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_BITS    1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_SHIFT   15

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: GB_ADV_DIS [14:14] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x4000,14)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_MASK                0x4000
#define BRPHY3_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_BITS                1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_SHIFT               14

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: TX_ADV_DIS [13:13] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x2000,13)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_MASK                0x2000
#define BRPHY3_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_BITS                1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_SHIFT               13

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: WIRESPEED_DOWNGRADE [12:12] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x1000,12)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_MASK       0x1000
#define BRPHY3_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_ALIGN      0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_BITS       1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_SHIFT      12

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX [11:11] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x800,11)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_MASK             0x0800
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_ALIGN            0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_BITS             1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_SHIFT            11

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_1000T [10:10] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x400,10)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_MASK                 0x0400
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_ALIGN                0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_BITS                 1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_SHIFT                10

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX [09:09] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x200,9)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_MASK              0x0200
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_ALIGN             0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_BITS              1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_SHIFT             9

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_100T [08:08] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x100,8)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_MASK                  0x0100
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_ALIGN                 0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_BITS                  1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_SHIFT                 8

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX [07:07] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x80,7)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_MASK               0x0080
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_BITS               1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_SHIFT              7

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_10T [06:06] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x40,6)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_MASK                   0x0040
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_BITS                   1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_SHIFT                  6

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX_NL [05:05] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x20,5)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_MASK          0x0020
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_ALIGN         0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_BITS          1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_SHIFT         5

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_NL [04:04] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x10,4)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_MASK              0x0010
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_ALIGN             0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_BITS              1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_SHIFT             4

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX_NL [03:03] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x8,3)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_MASK           0x0008
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_ALIGN          0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_BITS           1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_SHIFT          3

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_100T_NL [02:02] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x4,2)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_MASK               0x0004
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_BITS               1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_SHIFT              2

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX_NL [01:01] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x2,1)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_MASK            0x0002
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_ALIGN           0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_BITS            1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_SHIFT           1

/* BRPHY3_GPHY_CORE :: BASE1D_SHD :: HCD_10T_NL [00:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D_SHD,0x1,0)
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_MASK                0x0001
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_BITS                1
#define BRPHY3_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_SHIFT               0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE1D
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE1D :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x8000,15)
#define BRPHY3_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_MASK        0x8000
#define BRPHY3_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_ALIGN       0
#define BRPHY3_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_BITS        1
#define BRPHY3_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_SHIFT       15

/* BRPHY3_GPHY_CORE :: BASE1D :: MASTER_SLAVE_SEED_MATCH [14:14] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x4000,14)
#define BRPHY3_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_MASK       0x4000
#define BRPHY3_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_ALIGN      0
#define BRPHY3_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_BITS       1
#define BRPHY3_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_SHIFT      14

/* BRPHY3_GPHY_CORE :: BASE1D :: LINK_PARTNER_RD_BIT [13:13] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x2000,13)
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_MASK           0x2000
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_ALIGN          0
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_BITS           1
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_SHIFT          13

/* BRPHY3_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_VALUE [12:12] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x1000,12)
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_MASK         0x1000
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_ALIGN        0
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_BITS         1
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_SHIFT        12

/* BRPHY3_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_CFG_EN [11:11] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x800,11)
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_MASK        0x0800
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_ALIGN       0
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_BITS        1
#define BRPHY3_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_SHIFT       11

/* BRPHY3_GPHY_CORE :: BASE1D :: LOCAL_MS_SEED_VALUE [10:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x7ff,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1D,0x7ff,0)
#define BRPHY3_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_MASK           0x07ff
#define BRPHY3_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_ALIGN          0
#define BRPHY3_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_BITS           11
#define BRPHY3_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_SHIFT          0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE1E
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE1E :: CRC_ERR_CNT [15:15] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x8000,15)
#define BRPHY3_GPHY_CORE_BASE1E_CRC_ERR_CNT_MASK                   0x8000
#define BRPHY3_GPHY_CORE_BASE1E_CRC_ERR_CNT_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE1E_CRC_ERR_CNT_BITS                   1
#define BRPHY3_GPHY_CORE_BASE1E_CRC_ERR_CNT_SHIFT                  15

/* BRPHY3_GPHY_CORE :: BASE1E :: TX_ERR_CODE [14:14] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_TX_ERR_CODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_TX_ERR_CODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x4000,14)
#define BRPHY3_GPHY_CORE_BASE1E_TX_ERR_CODE_MASK                   0x4000
#define BRPHY3_GPHY_CORE_BASE1E_TX_ERR_CODE_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE1E_TX_ERR_CODE_BITS                   1
#define BRPHY3_GPHY_CORE_BASE1E_TX_ERR_CODE_SHIFT                  14

/* BRPHY3_GPHY_CORE :: BASE1E :: CNTR_TEST [13:13] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_CNTR_TEST(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_CNTR_TEST(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x2000,13)
#define BRPHY3_GPHY_CORE_BASE1E_CNTR_TEST_MASK                     0x2000
#define BRPHY3_GPHY_CORE_BASE1E_CNTR_TEST_ALIGN                    0
#define BRPHY3_GPHY_CORE_BASE1E_CNTR_TEST_BITS                     1
#define BRPHY3_GPHY_CORE_BASE1E_CNTR_TEST_SHIFT                    13

/* BRPHY3_GPHY_CORE :: BASE1E :: FORCE_LINK [12:12] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_FORCE_LINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_FORCE_LINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x1000,12)
#define BRPHY3_GPHY_CORE_BASE1E_FORCE_LINK_MASK                    0x1000
#define BRPHY3_GPHY_CORE_BASE1E_FORCE_LINK_ALIGN                   0
#define BRPHY3_GPHY_CORE_BASE1E_FORCE_LINK_BITS                    1
#define BRPHY3_GPHY_CORE_BASE1E_FORCE_LINK_SHIFT                   12

/* BRPHY3_GPHY_CORE :: BASE1E :: FORCE_LOCK [11:11] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_FORCE_LOCK(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_FORCE_LOCK(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x800,11)
#define BRPHY3_GPHY_CORE_BASE1E_FORCE_LOCK_MASK                    0x0800
#define BRPHY3_GPHY_CORE_BASE1E_FORCE_LOCK_ALIGN                   0
#define BRPHY3_GPHY_CORE_BASE1E_FORCE_LOCK_BITS                    1
#define BRPHY3_GPHY_CORE_BASE1E_FORCE_LOCK_SHIFT                   11

/* BRPHY3_GPHY_CORE :: BASE1E :: SCR_TEST [10:10] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_SCR_TEST(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_SCR_TEST(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x400,10)
#define BRPHY3_GPHY_CORE_BASE1E_SCR_TEST_MASK                      0x0400
#define BRPHY3_GPHY_CORE_BASE1E_SCR_TEST_ALIGN                     0
#define BRPHY3_GPHY_CORE_BASE1E_SCR_TEST_BITS                      1
#define BRPHY3_GPHY_CORE_BASE1E_SCR_TEST_SHIFT                     10

/* BRPHY3_GPHY_CORE :: BASE1E :: EXT_LINK [09:09] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_EXT_LINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_EXT_LINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x200,9)
#define BRPHY3_GPHY_CORE_BASE1E_EXT_LINK_MASK                      0x0200
#define BRPHY3_GPHY_CORE_BASE1E_EXT_LINK_ALIGN                     0
#define BRPHY3_GPHY_CORE_BASE1E_EXT_LINK_BITS                      1
#define BRPHY3_GPHY_CORE_BASE1E_EXT_LINK_SHIFT                     9

/* BRPHY3_GPHY_CORE :: BASE1E :: FAST_TIMERS [08:08] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_FAST_TIMERS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_FAST_TIMERS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x100,8)
#define BRPHY3_GPHY_CORE_BASE1E_FAST_TIMERS_MASK                   0x0100
#define BRPHY3_GPHY_CORE_BASE1E_FAST_TIMERS_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE1E_FAST_TIMERS_BITS                   1
#define BRPHY3_GPHY_CORE_BASE1E_FAST_TIMERS_SHIFT                  8

/* BRPHY3_GPHY_CORE :: BASE1E :: MANUAL_SWAP_MDI [07:07] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x80,7)
#define BRPHY3_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_MASK               0x0080
#define BRPHY3_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_BITS               1
#define BRPHY3_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_SHIFT              7

/* BRPHY3_GPHY_CORE :: BASE1E :: RX_WATCHDOG_TIMER_DIS [06:06] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x40,6)
#define BRPHY3_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_MASK         0x0040
#define BRPHY3_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_ALIGN        0
#define BRPHY3_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_BITS         1
#define BRPHY3_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_SHIFT        6

/* BRPHY3_GPHY_CORE :: BASE1E :: POLARITY_ENCODE_DIS [05:05] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x20,5)
#define BRPHY3_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_MASK           0x0020
#define BRPHY3_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_ALIGN          0
#define BRPHY3_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_BITS           1
#define BRPHY3_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_SHIFT          5

/* BRPHY3_GPHY_CORE :: BASE1E :: SOFT_TRIM_SETTING_EN [04:04] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0x10,4)
#define BRPHY3_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_MASK          0x0010
#define BRPHY3_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_ALIGN         0
#define BRPHY3_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_BITS          1
#define BRPHY3_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_SHIFT         4

/* BRPHY3_GPHY_CORE :: BASE1E :: TRIM_MAIN_DAC [03:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1E,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1E,0xf,0)
#define BRPHY3_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_MASK                 0x000f
#define BRPHY3_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_ALIGN                0
#define BRPHY3_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_BITS                 4
#define BRPHY3_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_SHIFT                0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BASE1F
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BASE1F :: TEST_SEL_AUTONEG_FSM [15:13] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0xe000,13,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0xe000,13)
#define BRPHY3_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_MASK          0xe000
#define BRPHY3_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_ALIGN         0
#define BRPHY3_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_BITS          3
#define BRPHY3_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_SHIFT         13

/* BRPHY3_GPHY_CORE :: BASE1F :: TEST_AUTONEG_TIMER [12:12] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x1000,12)
#define BRPHY3_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_MASK            0x1000
#define BRPHY3_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_ALIGN           0
#define BRPHY3_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_BITS            1
#define BRPHY3_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_SHIFT           12

/* BRPHY3_GPHY_CORE :: BASE1F :: TEST_MS_SEED [11:11] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_TEST_MS_SEED(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_TEST_MS_SEED(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x800,11)
#define BRPHY3_GPHY_CORE_BASE1F_TEST_MS_SEED_MASK                  0x0800
#define BRPHY3_GPHY_CORE_BASE1F_TEST_MS_SEED_ALIGN                 0
#define BRPHY3_GPHY_CORE_BASE1F_TEST_MS_SEED_BITS                  1
#define BRPHY3_GPHY_CORE_BASE1F_TEST_MS_SEED_SHIFT                 11

/* BRPHY3_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_ABILITY_EN [10:10] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x400,10)
#define BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_MASK    0x0400
#define BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_ALIGN   0
#define BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_BITS    1
#define BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_SHIFT   10

/* BRPHY3_GPHY_CORE :: BASE1F :: FORCE_HCD [09:09] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_FORCE_HCD(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_FORCE_HCD(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x200,9)
#define BRPHY3_GPHY_CORE_BASE1F_FORCE_HCD_MASK                     0x0200
#define BRPHY3_GPHY_CORE_BASE1F_FORCE_HCD_ALIGN                    0
#define BRPHY3_GPHY_CORE_BASE1F_FORCE_HCD_BITS                     1
#define BRPHY3_GPHY_CORE_BASE1F_FORCE_HCD_SHIFT                    9

/* BRPHY3_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_MS_SEED_EN [08:08] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x100,8)
#define BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_MASK    0x0100
#define BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_ALIGN   0
#define BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_BITS    1
#define BRPHY3_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_SHIFT   8

/* BRPHY3_GPHY_CORE :: BASE1F :: TX_10B [07:07] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_TX_10B(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_TX_10B(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x80,7)
#define BRPHY3_GPHY_CORE_BASE1F_TX_10B_MASK                        0x0080
#define BRPHY3_GPHY_CORE_BASE1F_TX_10B_ALIGN                       0
#define BRPHY3_GPHY_CORE_BASE1F_TX_10B_BITS                        1
#define BRPHY3_GPHY_CORE_BASE1F_TX_10B_SHIFT                       7

/* BRPHY3_GPHY_CORE :: BASE1F :: RX_10B [06:06] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_RX_10B(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_RX_10B(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x40,6)
#define BRPHY3_GPHY_CORE_BASE1F_RX_10B_MASK                        0x0040
#define BRPHY3_GPHY_CORE_BASE1F_RX_10B_ALIGN                       0
#define BRPHY3_GPHY_CORE_BASE1F_RX_10B_BITS                        1
#define BRPHY3_GPHY_CORE_BASE1F_RX_10B_SHIFT                       6

/* BRPHY3_GPHY_CORE :: BASE1F :: BYPASS_TXFIFO [05:05] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x20,5)
#define BRPHY3_GPHY_CORE_BASE1F_BYPASS_TXFIFO_MASK                 0x0020
#define BRPHY3_GPHY_CORE_BASE1F_BYPASS_TXFIFO_ALIGN                0
#define BRPHY3_GPHY_CORE_BASE1F_BYPASS_TXFIFO_BITS                 1
#define BRPHY3_GPHY_CORE_BASE1F_BYPASS_TXFIFO_SHIFT                5

/* BRPHY3_GPHY_CORE :: BASE1F :: SAME_SCR_SEEDS [04:04] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x10,4)
#define BRPHY3_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_MASK                0x0010
#define BRPHY3_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_BITS                1
#define BRPHY3_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_SHIFT               4

/* BRPHY3_GPHY_CORE :: BASE1F :: JITTER_TEST [03:03] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_JITTER_TEST(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_JITTER_TEST(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x8,3)
#define BRPHY3_GPHY_CORE_BASE1F_JITTER_TEST_MASK                   0x0008
#define BRPHY3_GPHY_CORE_BASE1F_JITTER_TEST_ALIGN                  0
#define BRPHY3_GPHY_CORE_BASE1F_JITTER_TEST_BITS                   1
#define BRPHY3_GPHY_CORE_BASE1F_JITTER_TEST_SHIFT                  3

/* BRPHY3_GPHY_CORE :: BASE1F :: TEST_ATMP_CNTR [02:02] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x4,2)
#define BRPHY3_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_MASK                0x0004
#define BRPHY3_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_ALIGN               0
#define BRPHY3_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_BITS                1
#define BRPHY3_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_SHIFT               2

/* BRPHY3_GPHY_CORE :: BASE1F :: LATENCY_MEASURE [01:01] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x2,1)
#define BRPHY3_GPHY_CORE_BASE1F_LATENCY_MEASURE_MASK               0x0002
#define BRPHY3_GPHY_CORE_BASE1F_LATENCY_MEASURE_ALIGN              0
#define BRPHY3_GPHY_CORE_BASE1F_LATENCY_MEASURE_BITS               1
#define BRPHY3_GPHY_CORE_BASE1F_LATENCY_MEASURE_SHIFT              1

/* BRPHY3_GPHY_CORE :: BASE1F :: ACTIVE_HYBRID_DIS [00:00] */
#define Wr_BRPHY3_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_BASE1F,0x1,0)
#define BRPHY3_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_MASK             0x0001
#define BRPHY3_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_ALIGN            0
#define BRPHY3_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_BITS             1
#define BRPHY3_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_SHIFT            0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_00
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_00 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_00_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_00_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_00_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_00_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_00 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_00,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_00,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_00_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_00_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_00_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_00_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_00 :: reserved1 [09:08] */
#define BRPHY3_GPHY_CORE_SHD1C_00_RESERVED1_MASK                   0x0300
#define BRPHY3_GPHY_CORE_SHD1C_00_RESERVED1_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_00_RESERVED1_BITS                   2
#define BRPHY3_GPHY_CORE_SHD1C_00_RESERVED1_SHIFT                  8

/* BRPHY3_GPHY_CORE :: SHD1C_00 :: CABLETRON_LED [07:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_00,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_00,0xff,0)
#define BRPHY3_GPHY_CORE_SHD1C_00_CABLETRON_LED_MASK               0x00ff
#define BRPHY3_GPHY_CORE_SHD1C_00_CABLETRON_LED_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD1C_00_CABLETRON_LED_BITS               8
#define BRPHY3_GPHY_CORE_SHD1C_00_CABLETRON_LED_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_01
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_01 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_01_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_01_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_01_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_01_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_01 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_01,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_01,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_01_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_01_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_01_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_01_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_01 :: reserved1 [09:07] */
#define BRPHY3_GPHY_CORE_SHD1C_01_RESERVED1_MASK                   0x0380
#define BRPHY3_GPHY_CORE_SHD1C_01_RESERVED1_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_01_RESERVED1_BITS                   3
#define BRPHY3_GPHY_CORE_SHD1C_01_RESERVED1_SHIFT                  7

/* BRPHY3_GPHY_CORE :: SHD1C_01 :: TVCO_OUTPUT [06:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_01,0x7f,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_01,0x7f,0)
#define BRPHY3_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_MASK                 0x007f
#define BRPHY3_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_BITS                 7
#define BRPHY3_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_SHIFT                0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_02
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_02 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_02_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_02_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_02_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_02_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_02_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_02_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_02_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_02_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: SD_STATUS [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_SD_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_SD_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x200,9)
#define BRPHY3_GPHY_CORE_SHD1C_02_SD_STATUS_MASK                   0x0200
#define BRPHY3_GPHY_CORE_SHD1C_02_SD_STATUS_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_02_SD_STATUS_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_02_SD_STATUS_SHIFT                  9

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: FORCE_SD_ON [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x100,8)
#define BRPHY3_GPHY_CORE_SHD1C_02_FORCE_SD_ON_MASK                 0x0100
#define BRPHY3_GPHY_CORE_SHD1C_02_FORCE_SD_ON_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD1C_02_FORCE_SD_ON_BITS                 1
#define BRPHY3_GPHY_CORE_SHD1C_02_FORCE_SD_ON_SHIFT                8

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: INVERT_SD_PIN [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_MASK               0x0080
#define BRPHY3_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_BITS               1
#define BRPHY3_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_SHIFT              7

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: CFC_INITFILTER_EN [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x40,6)
#define BRPHY3_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_MASK           0x0040
#define BRPHY3_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_ALIGN          0
#define BRPHY3_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_BITS           1
#define BRPHY3_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_SHIFT          6

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: USE_FILTERED_SD [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x20,5)
#define BRPHY3_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_MASK             0x0020
#define BRPHY3_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_BITS             1
#define BRPHY3_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_SHIFT            5

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: FX_COPPER_PATH [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x10,4)
#define BRPHY3_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_MASK              0x0010
#define BRPHY3_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_BITS              1
#define BRPHY3_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_SHIFT             4

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: SPARE_REG [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x8,3)
#define BRPHY3_GPHY_CORE_SHD1C_02_SPARE_REG_MASK                   0x0008
#define BRPHY3_GPHY_CORE_SHD1C_02_SPARE_REG_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_02_SPARE_REG_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_02_SPARE_REG_SHIFT                  3

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: BC_LINK_SPEED_LED [02:02] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x4,2)
#define BRPHY3_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_MASK           0x0004
#define BRPHY3_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_ALIGN          0
#define BRPHY3_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_BITS           1
#define BRPHY3_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_SHIFT          2

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: LOST_TOKEN_FIX_DIS [01:01] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x2,1)
#define BRPHY3_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_MASK          0x0002
#define BRPHY3_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_BITS          1
#define BRPHY3_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_SHIFT         1

/* BRPHY3_GPHY_CORE :: SHD1C_02 :: LINK_LED [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_02_LINK_LED(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_02_LINK_LED(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_02,0x1,0)
#define BRPHY3_GPHY_CORE_SHD1C_02_LINK_LED_MASK                    0x0001
#define BRPHY3_GPHY_CORE_SHD1C_02_LINK_LED_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD1C_02_LINK_LED_BITS                    1
#define BRPHY3_GPHY_CORE_SHD1C_02_LINK_LED_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_03
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_03 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_03_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_03_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_03_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_03_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_03 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_03_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_03_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_03_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_03_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_03 :: GTXCLK_DLY_EN [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x200,9)
#define BRPHY3_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_MASK               0x0200
#define BRPHY3_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_BITS               1
#define BRPHY3_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_SHIFT              9

/* BRPHY3_GPHY_CORE :: SHD1C_03 :: GMII_CLK_ALIGN_STRB [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x100,8)
#define BRPHY3_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_MASK         0x0100
#define BRPHY3_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_BITS         1
#define BRPHY3_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_SHIFT        8

/* BRPHY3_GPHY_CORE :: SHD1C_03 :: RXCLK_ALIGN_STRB [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_MASK            0x0080
#define BRPHY3_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_BITS            1
#define BRPHY3_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_SHIFT           7

/* BRPHY3_GPHY_CORE :: SHD1C_03 :: DLY_VALUE [06:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_03_DLY_VALUE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x70,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_03_DLY_VALUE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0x70,4)
#define BRPHY3_GPHY_CORE_SHD1C_03_DLY_VALUE_MASK                   0x0070
#define BRPHY3_GPHY_CORE_SHD1C_03_DLY_VALUE_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_03_DLY_VALUE_BITS                   3
#define BRPHY3_GPHY_CORE_SHD1C_03_DLY_VALUE_SHIFT                  4

/* BRPHY3_GPHY_CORE :: SHD1C_03 :: DLY_LINE_SEL [03:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_03,0xf,0)
#define BRPHY3_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_MASK                0x000f
#define BRPHY3_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_BITS                4
#define BRPHY3_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_SHIFT               0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_04
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_04 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_04_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_04_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_04_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_04_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_04 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_04_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_04_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_04_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_04_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_04 :: SPARE_REG [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_04_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_04_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x200,9)
#define BRPHY3_GPHY_CORE_SHD1C_04_SPARE_REG_MASK                   0x0200
#define BRPHY3_GPHY_CORE_SHD1C_04_SPARE_REG_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_04_SPARE_REG_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_04_SPARE_REG_SHIFT                  9

/* BRPHY3_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_DIS [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x100,8)
#define BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_MASK         0x0100
#define BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_BITS         1
#define BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_SHIFT        8

/* BRPHY3_GPHY_CORE :: SHD1C_04 :: SELECT_TPOUT_RXD [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_MASK            0x0080
#define BRPHY3_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_BITS            1
#define BRPHY3_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_SHIFT           7

/* BRPHY3_GPHY_CORE :: SHD1C_04 :: DISABLE_PHYA2 [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x40,6)
#define BRPHY3_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_MASK               0x0040
#define BRPHY3_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_BITS               1
#define BRPHY3_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_SHIFT              6

/* BRPHY3_GPHY_CORE :: SHD1C_04 :: RBC_TXC_RXC_TRI [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x20,5)
#define BRPHY3_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_MASK             0x0020
#define BRPHY3_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_BITS             1
#define BRPHY3_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_SHIFT            5

/* BRPHY3_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_LIMIT [04:02] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x1c,2,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x1c,2)
#define BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_MASK       0x001c
#define BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_ALIGN      0
#define BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_BITS       3
#define BRPHY3_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_SHIFT      2

/* BRPHY3_GPHY_CORE :: SHD1C_04 :: ENG_DET_ON_INTR_PIN [01:01] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x2,1)
#define BRPHY3_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_MASK         0x0002
#define BRPHY3_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_BITS         1
#define BRPHY3_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_SHIFT        1

/* BRPHY3_GPHY_CORE :: SHD1C_04 :: TESTONBYTE7_0 [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_04,0x1,0)
#define BRPHY3_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_MASK               0x0001
#define BRPHY3_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_BITS               1
#define BRPHY3_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_05
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_05 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_05_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_05_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_05_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_05_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_05_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_05_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_05_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_05_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: DLL_LOCK_EN [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x200,9)
#define BRPHY3_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_MASK                 0x0200
#define BRPHY3_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_BITS                 1
#define BRPHY3_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_SHIFT                9

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: TXC_RXC_DIS [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x100,8)
#define BRPHY3_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_MASK                 0x0100
#define BRPHY3_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_BITS                 1
#define BRPHY3_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_SHIFT                8

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: BT_R_REJECT_FILTER [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_MASK          0x0080
#define BRPHY3_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_BITS          1
#define BRPHY3_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_SHIFT         7

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: TXC_OFF_EN [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x40,6)
#define BRPHY3_GPHY_CORE_SHD1C_05_TXC_OFF_EN_MASK                  0x0040
#define BRPHY3_GPHY_CORE_SHD1C_05_TXC_OFF_EN_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD1C_05_TXC_OFF_EN_BITS                  1
#define BRPHY3_GPHY_CORE_SHD1C_05_TXC_OFF_EN_SHIFT                 6

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: SD_CHANGE_MUX_SEL [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x20,5)
#define BRPHY3_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_MASK           0x0020
#define BRPHY3_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_ALIGN          0
#define BRPHY3_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_BITS           1
#define BRPHY3_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_SHIFT          5

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: LOW_POWER_ENC_DIS [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x10,4)
#define BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_MASK           0x0010
#define BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_ALIGN          0
#define BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_BITS           1
#define BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_SHIFT          4

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: LOW_POWER_BT_DIS [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x8,3)
#define BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_MASK            0x0008
#define BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_BITS            1
#define BRPHY3_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_SHIFT           3

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: SD_DEASSERT_TIMER_LEN [02:02] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x4,2)
#define BRPHY3_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_MASK       0x0004
#define BRPHY3_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_ALIGN      0
#define BRPHY3_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_BITS       1
#define BRPHY3_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_SHIFT      2

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: AUTO_PWRDN_DLL_DIS [01:01] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x2,1)
#define BRPHY3_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_MASK          0x0002
#define BRPHY3_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_BITS          1
#define BRPHY3_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_SHIFT         1

/* BRPHY3_GPHY_CORE :: SHD1C_05 :: CLK125_OUTPUT_EN [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_05,0x1,0)
#define BRPHY3_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_MASK            0x0001
#define BRPHY3_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_BITS            1
#define BRPHY3_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_SHIFT           0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_06
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_06 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_06_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_06_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_06_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_06_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_06 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_06_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_06_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_06_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_06_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_06 :: SPARE_REG [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_06_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_06_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x200,9)
#define BRPHY3_GPHY_CORE_SHD1C_06_SPARE_REG_MASK                   0x0200
#define BRPHY3_GPHY_CORE_SHD1C_06_SPARE_REG_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_06_SPARE_REG_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_06_SPARE_REG_SHIFT                  9

/* BRPHY3_GPHY_CORE :: SHD1C_06 :: TDR_LINK_TIME_OUT [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x100,8)
#define BRPHY3_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_MASK           0x0100
#define BRPHY3_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_ALIGN          0
#define BRPHY3_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_BITS           1
#define BRPHY3_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_SHIFT          8

/* BRPHY3_GPHY_CORE :: SHD1C_06 :: TEST_PULSE_SIZE [07:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0xe0,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0xe0,5)
#define BRPHY3_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_MASK             0x00e0
#define BRPHY3_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_BITS             3
#define BRPHY3_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_SHIFT            5

/* BRPHY3_GPHY_CORE :: SHD1C_06 :: TX_CHANNEL_SEL [04:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x18,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x18,3)
#define BRPHY3_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_MASK              0x0018
#define BRPHY3_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_BITS              2
#define BRPHY3_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_SHIFT             3

/* BRPHY3_GPHY_CORE :: SHD1C_06 :: RX_CHANNEL_SEL [02:01] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x6,1,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x6,1)
#define BRPHY3_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_MASK              0x0006
#define BRPHY3_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_BITS              2
#define BRPHY3_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_SHIFT             1

/* BRPHY3_GPHY_CORE :: SHD1C_06 :: TDR_START [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_06_TDR_START(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_06_TDR_START(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_06,0x1,0)
#define BRPHY3_GPHY_CORE_SHD1C_06_TDR_START_MASK                   0x0001
#define BRPHY3_GPHY_CORE_SHD1C_06_TDR_START_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_06_TDR_START_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_06_TDR_START_SHIFT                  0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_07
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_07 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_07_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_07_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_07_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_07_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_07_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_07_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_07_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_07_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: SPARE_REG [09:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x300,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x300,8)
#define BRPHY3_GPHY_CORE_SHD1C_07_SPARE_REG_MASK                   0x0300
#define BRPHY3_GPHY_CORE_SHD1C_07_SPARE_REG_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_07_SPARE_REG_BITS                   2
#define BRPHY3_GPHY_CORE_SHD1C_07_SPARE_REG_SHIFT                  8

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_MASK                0x0080
#define BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_BITS                1
#define BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_SHIFT               7

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS_CLEAR [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x40,6)
#define BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_MASK          0x0040
#define BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_BITS          1
#define BRPHY3_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_SHIFT         6

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: FASTTIMERS [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_FASTTIMERS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_FASTTIMERS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x20,5)
#define BRPHY3_GPHY_CORE_SHD1C_07_FASTTIMERS_MASK                  0x0020
#define BRPHY3_GPHY_CORE_SHD1C_07_FASTTIMERS_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD1C_07_FASTTIMERS_BITS                  1
#define BRPHY3_GPHY_CORE_SHD1C_07_FASTTIMERS_SHIFT                 5

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: FEXT [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_FEXT(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_FEXT(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x10,4)
#define BRPHY3_GPHY_CORE_SHD1C_07_FEXT_MASK                        0x0010
#define BRPHY3_GPHY_CORE_SHD1C_07_FEXT_ALIGN                       0
#define BRPHY3_GPHY_CORE_SHD1C_07_FEXT_BITS                        1
#define BRPHY3_GPHY_CORE_SHD1C_07_FEXT_SHIFT                       4

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: MASTER [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_MASTER(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_MASTER(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x8,3)
#define BRPHY3_GPHY_CORE_SHD1C_07_MASTER_MASK                      0x0008
#define BRPHY3_GPHY_CORE_SHD1C_07_MASTER_ALIGN                     0
#define BRPHY3_GPHY_CORE_SHD1C_07_MASTER_BITS                      1
#define BRPHY3_GPHY_CORE_SHD1C_07_MASTER_SHIFT                     3

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: EXT_PHY_NO_AUTONEG [02:02] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x4,2)
#define BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_MASK          0x0004
#define BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_BITS          1
#define BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_SHIFT         2

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: EXT_PHY [01:01] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x2,1)
#define BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_MASK                     0x0002
#define BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_ALIGN                    0
#define BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_BITS                     1
#define BRPHY3_GPHY_CORE_SHD1C_07_EXT_PHY_SHIFT                    1

/* BRPHY3_GPHY_CORE :: SHD1C_07 :: TDR_EN [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_07_TDR_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_07_TDR_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_07,0x1,0)
#define BRPHY3_GPHY_CORE_SHD1C_07_TDR_EN_MASK                      0x0001
#define BRPHY3_GPHY_CORE_SHD1C_07_TDR_EN_ALIGN                     0
#define BRPHY3_GPHY_CORE_SHD1C_07_TDR_EN_BITS                      1
#define BRPHY3_GPHY_CORE_SHD1C_07_TDR_EN_SHIFT                     0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_08
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_08 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_08_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_08_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_08_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_08_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: reserved1 [09:09] */
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED1_MASK                   0x0200
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED1_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED1_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED1_SHIFT                  9

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: SLAVE_N [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_08_SLAVE_N(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_08_SLAVE_N(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x100,8)
#define BRPHY3_GPHY_CORE_SHD1C_08_SLAVE_N_MASK                     0x0100
#define BRPHY3_GPHY_CORE_SHD1C_08_SLAVE_N_ALIGN                    0
#define BRPHY3_GPHY_CORE_SHD1C_08_SLAVE_N_BITS                     1
#define BRPHY3_GPHY_CORE_SHD1C_08_SLAVE_N_SHIFT                    8

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: FDXLED_N [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_08_FDXLED_N(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_08_FDXLED_N(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_08_FDXLED_N_MASK                    0x0080
#define BRPHY3_GPHY_CORE_SHD1C_08_FDXLED_N_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD1C_08_FDXLED_N_BITS                    1
#define BRPHY3_GPHY_CORE_SHD1C_08_FDXLED_N_SHIFT                   7

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: INTR_N [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_08_INTR_N(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_08_INTR_N(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x40,6)
#define BRPHY3_GPHY_CORE_SHD1C_08_INTR_N_MASK                      0x0040
#define BRPHY3_GPHY_CORE_SHD1C_08_INTR_N_ALIGN                     0
#define BRPHY3_GPHY_CORE_SHD1C_08_INTR_N_BITS                      1
#define BRPHY3_GPHY_CORE_SHD1C_08_INTR_N_SHIFT                     6

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: reserved2 [05:05] */
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED2_MASK                   0x0020
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED2_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED2_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_08_RESERVED2_SHIFT                  5

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: LINKSPD_N [04:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_08_LINKSPD_N(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x18,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_08_LINKSPD_N(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x18,3)
#define BRPHY3_GPHY_CORE_SHD1C_08_LINKSPD_N_MASK                   0x0018
#define BRPHY3_GPHY_CORE_SHD1C_08_LINKSPD_N_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_08_LINKSPD_N_BITS                   2
#define BRPHY3_GPHY_CORE_SHD1C_08_LINKSPD_N_SHIFT                  3

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: TRANSMIT_LED [02:02] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x4,2)
#define BRPHY3_GPHY_CORE_SHD1C_08_TRANSMIT_LED_MASK                0x0004
#define BRPHY3_GPHY_CORE_SHD1C_08_TRANSMIT_LED_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD1C_08_TRANSMIT_LED_BITS                1
#define BRPHY3_GPHY_CORE_SHD1C_08_TRANSMIT_LED_SHIFT               2

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: RECEIVE_LED [01:01] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x2,1)
#define BRPHY3_GPHY_CORE_SHD1C_08_RECEIVE_LED_MASK                 0x0002
#define BRPHY3_GPHY_CORE_SHD1C_08_RECEIVE_LED_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD1C_08_RECEIVE_LED_BITS                 1
#define BRPHY3_GPHY_CORE_SHD1C_08_RECEIVE_LED_SHIFT                1

/* BRPHY3_GPHY_CORE :: SHD1C_08 :: QUALITY_LED [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_08_QUALITY_LED(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_08_QUALITY_LED(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_08,0x1,0)
#define BRPHY3_GPHY_CORE_SHD1C_08_QUALITY_LED_MASK                 0x0001
#define BRPHY3_GPHY_CORE_SHD1C_08_QUALITY_LED_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD1C_08_QUALITY_LED_BITS                 1
#define BRPHY3_GPHY_CORE_SHD1C_08_QUALITY_LED_SHIFT                0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_09
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_09 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_09_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_09_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_09_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_09_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_09_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_09_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_09_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_09_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: COL_BLINK [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_COL_BLINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_COL_BLINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x200,9)
#define BRPHY3_GPHY_CORE_SHD1C_09_COL_BLINK_MASK                   0x0200
#define BRPHY3_GPHY_CORE_SHD1C_09_COL_BLINK_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_09_COL_BLINK_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_09_COL_BLINK_SHIFT                  9

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: ACT_LINK_MSB [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x100,8)
#define BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_MASK                0x0100
#define BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_BITS                1
#define BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_SHIFT               8

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: SPARE_REG [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_09_SPARE_REG_MASK                   0x0080
#define BRPHY3_GPHY_CORE_SHD1C_09_SPARE_REG_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_09_SPARE_REG_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_09_SPARE_REG_SHIFT                  7

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: EXT_SERDES_INUSE [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x40,6)
#define BRPHY3_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_MASK            0x0040
#define BRPHY3_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_BITS            1
#define BRPHY3_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_SHIFT           6

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: OV_GBIC_LED [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x20,5)
#define BRPHY3_GPHY_CORE_SHD1C_09_OV_GBIC_LED_MASK                 0x0020
#define BRPHY3_GPHY_CORE_SHD1C_09_OV_GBIC_LED_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD1C_09_OV_GBIC_LED_BITS                 1
#define BRPHY3_GPHY_CORE_SHD1C_09_OV_GBIC_LED_SHIFT                5

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: ACT_LINK_LSB [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x10,4)
#define BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_MASK                0x0010
#define BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_BITS                1
#define BRPHY3_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_SHIFT               4

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: ACTIVITY_LED_EN [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x8,3)
#define BRPHY3_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_MASK             0x0008
#define BRPHY3_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_BITS             1
#define BRPHY3_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_SHIFT            3

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: RMT_FAULT_LED_EN [02:02] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x4,2)
#define BRPHY3_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_MASK            0x0004
#define BRPHY3_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_BITS            1
#define BRPHY3_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_SHIFT           2

/* BRPHY3_GPHY_CORE :: SHD1C_09 :: LINK_UTIL_LED_SEL [01:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x3,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_09,0x3,0)
#define BRPHY3_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_MASK           0x0003
#define BRPHY3_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_ALIGN          0
#define BRPHY3_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_BITS           2
#define BRPHY3_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_SHIFT          0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_0A
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_0A :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_0A_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_0A_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0A_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_0A_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_0A :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_0A_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_0A_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0A_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_0A_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_0A :: reserved1 [09:09] */
#define BRPHY3_GPHY_CORE_SHD1C_0A_RESERVED1_MASK                   0x0200
#define BRPHY3_GPHY_CORE_SHD1C_0A_RESERVED1_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0A_RESERVED1_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_0A_RESERVED1_SHIFT                  9

/* BRPHY3_GPHY_CORE :: SHD1C_0A :: APD_SINGLELP_ENABLE [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x100,8)
#define BRPHY3_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_MASK         0x0100
#define BRPHY3_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_BITS         1
#define BRPHY3_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_SHIFT        8

/* BRPHY3_GPHY_CORE :: SHD1C_0A :: LOWPWR136_ENC_EN [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_MASK            0x0080
#define BRPHY3_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_BITS            1
#define BRPHY3_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_SHIFT           7

/* BRPHY3_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_IGNORE_AUTONEG [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x40,6)
#define BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_MASK   0x0040
#define BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_ALIGN  0
#define BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_BITS   1
#define BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_SHIFT  6

/* BRPHY3_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_EN [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x20,5)
#define BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_MASK               0x0020
#define BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_BITS               1
#define BRPHY3_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_SHIFT              5

/* BRPHY3_GPHY_CORE :: SHD1C_0A :: SLEEP_TIMER_SEL [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0x10,4)
#define BRPHY3_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_MASK             0x0010
#define BRPHY3_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_BITS             1
#define BRPHY3_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_SHIFT            4

/* BRPHY3_GPHY_CORE :: SHD1C_0A :: WAKE_UP_TIMER_SEL [03:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0A,0xf,0)
#define BRPHY3_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_MASK           0x000f
#define BRPHY3_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_ALIGN          0
#define BRPHY3_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_BITS           4
#define BRPHY3_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_SHIFT          0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_0B
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_0B :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_0B_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_0B_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0B_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_0B_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_0B :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0B,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0B,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_0B_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_0B_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0B_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_0B_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_0B :: reserved1 [09:08] */
#define BRPHY3_GPHY_CORE_SHD1C_0B_RESERVED1_MASK                   0x0300
#define BRPHY3_GPHY_CORE_SHD1C_0B_RESERVED1_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0B_RESERVED1_BITS                   2
#define BRPHY3_GPHY_CORE_SHD1C_0B_RESERVED1_SHIFT                  8

/* BRPHY3_GPHY_CORE :: SHD1C_0B :: SPARE_CTL4 [07:01] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0B,0xfe,1,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0B,0xfe,1)
#define BRPHY3_GPHY_CORE_SHD1C_0B_SPARE_CTL4_MASK                  0x00fe
#define BRPHY3_GPHY_CORE_SHD1C_0B_SPARE_CTL4_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD1C_0B_SPARE_CTL4_BITS                  7
#define BRPHY3_GPHY_CORE_SHD1C_0B_SPARE_CTL4_SHIFT                 1

/* BRPHY3_GPHY_CORE :: SHD1C_0B :: dis_cl45 [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0B_dis_cl45(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0B,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0B_dis_cl45(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0B,0x1,0)
#define BRPHY3_GPHY_CORE_SHD1C_0B_DIS_CL45_MASK                    0x0001
#define BRPHY3_GPHY_CORE_SHD1C_0B_DIS_CL45_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD1C_0B_DIS_CL45_BITS                    1
#define BRPHY3_GPHY_CORE_SHD1C_0B_DIS_CL45_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_0D
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_0D :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_0D_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_0D_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0D_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_0D_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_0D :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0D,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0D,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_0D_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_0D_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0D_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_0D_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_0D :: reserved1 [09:08] */
#define BRPHY3_GPHY_CORE_SHD1C_0D_RESERVED1_MASK                   0x0300
#define BRPHY3_GPHY_CORE_SHD1C_0D_RESERVED1_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0D_RESERVED1_BITS                   2
#define BRPHY3_GPHY_CORE_SHD1C_0D_RESERVED1_SHIFT                  8

/* BRPHY3_GPHY_CORE :: SHD1C_0D :: LED2_SEL [07:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0D_LED2_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0D,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0D_LED2_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0D,0xf0,4)
#define BRPHY3_GPHY_CORE_SHD1C_0D_LED2_SEL_MASK                    0x00f0
#define BRPHY3_GPHY_CORE_SHD1C_0D_LED2_SEL_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD1C_0D_LED2_SEL_BITS                    4
#define BRPHY3_GPHY_CORE_SHD1C_0D_LED2_SEL_SHIFT                   4

/* BRPHY3_GPHY_CORE :: SHD1C_0D :: LED1_SEL [03:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0D_LED1_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0D,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0D_LED1_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0D,0xf,0)
#define BRPHY3_GPHY_CORE_SHD1C_0D_LED1_SEL_MASK                    0x000f
#define BRPHY3_GPHY_CORE_SHD1C_0D_LED1_SEL_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD1C_0D_LED1_SEL_BITS                    4
#define BRPHY3_GPHY_CORE_SHD1C_0D_LED1_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_0E
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_0E :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_0E_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_0E_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0E_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_0E_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_0E :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0E,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0E,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_0E_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_0E_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0E_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_0E_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_0E :: reserved1 [09:08] */
#define BRPHY3_GPHY_CORE_SHD1C_0E_RESERVED1_MASK                   0x0300
#define BRPHY3_GPHY_CORE_SHD1C_0E_RESERVED1_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0E_RESERVED1_BITS                   2
#define BRPHY3_GPHY_CORE_SHD1C_0E_RESERVED1_SHIFT                  8

/* BRPHY3_GPHY_CORE :: SHD1C_0E :: LED4_SEL [07:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0E_LED4_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0E,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0E_LED4_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0E,0xf0,4)
#define BRPHY3_GPHY_CORE_SHD1C_0E_LED4_SEL_MASK                    0x00f0
#define BRPHY3_GPHY_CORE_SHD1C_0E_LED4_SEL_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD1C_0E_LED4_SEL_BITS                    4
#define BRPHY3_GPHY_CORE_SHD1C_0E_LED4_SEL_SHIFT                   4

/* BRPHY3_GPHY_CORE :: SHD1C_0E :: LED3_SEL [03:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0E_LED3_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0E,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0E_LED3_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0E,0xf,0)
#define BRPHY3_GPHY_CORE_SHD1C_0E_LED3_SEL_MASK                    0x000f
#define BRPHY3_GPHY_CORE_SHD1C_0E_LED3_SEL_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD1C_0E_LED3_SEL_BITS                    4
#define BRPHY3_GPHY_CORE_SHD1C_0E_LED3_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_0F
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_0F :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_0F_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_0F_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0F_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_0F_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_0F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0F,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0F,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_0F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_0F_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0F_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_0F_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_0F :: reserved1 [09:04] */
#define BRPHY3_GPHY_CORE_SHD1C_0F_RESERVED1_MASK                   0x03f0
#define BRPHY3_GPHY_CORE_SHD1C_0F_RESERVED1_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_0F_RESERVED1_BITS                   6
#define BRPHY3_GPHY_CORE_SHD1C_0F_RESERVED1_SHIFT                  4

/* BRPHY3_GPHY_CORE :: SHD1C_0F :: CURRENT_MODE_LED_EN [03:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_0F,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_0F,0xf,0)
#define BRPHY3_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_MASK         0x000f
#define BRPHY3_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_BITS         4
#define BRPHY3_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_SHIFT        0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_10
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_10 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_10_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_10_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_10_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_10_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_10 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_10_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_10_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_10_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_10_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_10 :: reserved1 [09:08] */
#define BRPHY3_GPHY_CORE_SHD1C_10_RESERVED1_MASK                   0x0300
#define BRPHY3_GPHY_CORE_SHD1C_10_RESERVED1_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_10_RESERVED1_BITS                   2
#define BRPHY3_GPHY_CORE_SHD1C_10_RESERVED1_SHIFT                  8

/* BRPHY3_GPHY_CORE :: SHD1C_10 :: SPARE_REG [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_10_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_10_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_10_SPARE_REG_MASK                   0x0080
#define BRPHY3_GPHY_CORE_SHD1C_10_SPARE_REG_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_10_SPARE_REG_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_10_SPARE_REG_SHIFT                  7

/* BRPHY3_GPHY_CORE :: SHD1C_10 :: USE_ALT_LINKFLT [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x40,6)
#define BRPHY3_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_MASK             0x0040
#define BRPHY3_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_BITS             1
#define BRPHY3_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_SHIFT            6

/* BRPHY3_GPHY_CORE :: SHD1C_10 :: VISIBLE_BLINK [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x20,5)
#define BRPHY3_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_MASK               0x0020
#define BRPHY3_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_BITS               1
#define BRPHY3_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_SHIFT              5

/* BRPHY3_GPHY_CORE :: SHD1C_10 :: ENHANCED_PWR [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0x10,4)
#define BRPHY3_GPHY_CORE_SHD1C_10_ENHANCED_PWR_MASK                0x0010
#define BRPHY3_GPHY_CORE_SHD1C_10_ENHANCED_PWR_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD1C_10_ENHANCED_PWR_BITS                1
#define BRPHY3_GPHY_CORE_SHD1C_10_ENHANCED_PWR_SHIFT               4

/* BRPHY3_GPHY_CORE :: SHD1C_10 :: DISCONNECT_TIMER_VALUE [03:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_10,0xf,0)
#define BRPHY3_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_MASK      0x000f
#define BRPHY3_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_ALIGN     0
#define BRPHY3_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_BITS      4
#define BRPHY3_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_SHIFT     0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD1C_1F
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD1C_1F :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD1C_1F_RESERVED0_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD1C_1F_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_1F_RESERVED0_BITS                   1
#define BRPHY3_GPHY_CORE_SHD1C_1F_RESERVED0_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD1C_1F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY3_GPHY_CORE_SHD1C_1F_SHD1C_SEL_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD1C_1F_SHD1C_SEL_BITS                   5
#define BRPHY3_GPHY_CORE_SHD1C_1F_SHD1C_SEL_SHIFT                  10

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: DUAL_SERDES_CAPABLE [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x200,9)
#define BRPHY3_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_MASK         0x0200
#define BRPHY3_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_BITS         1
#define BRPHY3_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_SHIFT        9

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: MODE_SEL_CHANGE [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x100,8)
#define BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_MASK             0x0100
#define BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_BITS             1
#define BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_SHIFT            8

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: COPPER_LINK [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x80,7)
#define BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_LINK_MASK                 0x0080
#define BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_LINK_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_LINK_BITS                 1
#define BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_LINK_SHIFT                7

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: SERDES_LINK [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x40,6)
#define BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_LINK_MASK                 0x0040
#define BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_LINK_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_LINK_BITS                 1
#define BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_LINK_SHIFT                6

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: COPPER_ENG_DET [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x20,5)
#define BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_MASK              0x0020
#define BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_BITS              1
#define BRPHY3_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_SHIFT             5

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: FIBER_SIGNAL_DET [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x10,4)
#define BRPHY3_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_MASK            0x0010
#define BRPHY3_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_BITS            1
#define BRPHY3_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_SHIFT           4

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: SERDES_CAPABLE [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x8,3)
#define BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_MASK              0x0008
#define BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_BITS              1
#define BRPHY3_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_SHIFT             3

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: MODE_SEL [02:01] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x6,1,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x6,1)
#define BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_MASK                    0x0006
#define BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_BITS                    2
#define BRPHY3_GPHY_CORE_SHD1C_1F_MODE_SEL_SHIFT                   1

/* BRPHY3_GPHY_CORE :: SHD1C_1F :: REG_1000X_EN [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD1C_1F,0x1,0)
#define BRPHY3_GPHY_CORE_SHD1C_1F_REG_1000X_EN_MASK                0x0001
#define BRPHY3_GPHY_CORE_SHD1C_1F_REG_1000X_EN_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD1C_1F_REG_1000X_EN_BITS                1
#define BRPHY3_GPHY_CORE_SHD1C_1F_REG_1000X_EN_SHIFT               0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD18_000
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD18_000 :: EXT_LPBK [15:15] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_EXT_LPBK(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_EXT_LPBK(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x8000,15)
#define BRPHY3_GPHY_CORE_SHD18_000_EXT_LPBK_MASK                   0x8000
#define BRPHY3_GPHY_CORE_SHD18_000_EXT_LPBK_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD18_000_EXT_LPBK_BITS                   1
#define BRPHY3_GPHY_CORE_SHD18_000_EXT_LPBK_SHIFT                  15

/* BRPHY3_GPHY_CORE :: SHD18_000 :: EXT_PKT_LEN [14:14] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x4000,14)
#define BRPHY3_GPHY_CORE_SHD18_000_EXT_PKT_LEN_MASK                0x4000
#define BRPHY3_GPHY_CORE_SHD18_000_EXT_PKT_LEN_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_000_EXT_PKT_LEN_BITS                1
#define BRPHY3_GPHY_CORE_SHD18_000_EXT_PKT_LEN_SHIFT               14

/* BRPHY3_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_1000T [13:12] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x3000,12,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x3000,12)
#define BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_MASK         0x3000
#define BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_BITS         2
#define BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_SHIFT        12

/* BRPHY3_GPHY_CORE :: SHD18_000 :: SM_DSP_CLK_EN [11:11] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x800,11)
#define BRPHY3_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_MASK              0x0800
#define BRPHY3_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_BITS              1
#define BRPHY3_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_SHIFT             11

/* BRPHY3_GPHY_CORE :: SHD18_000 :: TX_6DB_CODING [10:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x400,10)
#define BRPHY3_GPHY_CORE_SHD18_000_TX_6DB_CODING_MASK              0x0400
#define BRPHY3_GPHY_CORE_SHD18_000_TX_6DB_CODING_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD18_000_TX_6DB_CODING_BITS              1
#define BRPHY3_GPHY_CORE_SHD18_000_TX_6DB_CODING_SHIFT             10

/* BRPHY3_GPHY_CORE :: SHD18_000 :: RCV_SLICING [09:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_RCV_SLICING(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x300,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_RCV_SLICING(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x300,8)
#define BRPHY3_GPHY_CORE_SHD18_000_RCV_SLICING_MASK                0x0300
#define BRPHY3_GPHY_CORE_SHD18_000_RCV_SLICING_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_000_RCV_SLICING_BITS                2
#define BRPHY3_GPHY_CORE_SHD18_000_RCV_SLICING_SHIFT               8

/* BRPHY3_GPHY_CORE :: SHD18_000 :: PRF_DIS [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_PRF_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_PRF_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x80,7)
#define BRPHY3_GPHY_CORE_SHD18_000_PRF_DIS_MASK                    0x0080
#define BRPHY3_GPHY_CORE_SHD18_000_PRF_DIS_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD18_000_PRF_DIS_BITS                    1
#define BRPHY3_GPHY_CORE_SHD18_000_PRF_DIS_SHIFT                   7

/* BRPHY3_GPHY_CORE :: SHD18_000 :: INVERSE_PRF_DIS [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x40,6)
#define BRPHY3_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_MASK            0x0040
#define BRPHY3_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_SHIFT           6

/* BRPHY3_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_100TX [05:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x30,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x30,4)
#define BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_MASK         0x0030
#define BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_BITS         2
#define BRPHY3_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_SHIFT        4

/* BRPHY3_GPHY_CORE :: SHD18_000 :: DIAGNOSTIC [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x8,3)
#define BRPHY3_GPHY_CORE_SHD18_000_DIAGNOSTIC_MASK                 0x0008
#define BRPHY3_GPHY_CORE_SHD18_000_DIAGNOSTIC_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD18_000_DIAGNOSTIC_BITS                 1
#define BRPHY3_GPHY_CORE_SHD18_000_DIAGNOSTIC_SHIFT                3

/* BRPHY3_GPHY_CORE :: SHD18_000 :: SHD18_SEL [02:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_000_SHD18_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_000_SHD18_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_000,0x7,0)
#define BRPHY3_GPHY_CORE_SHD18_000_SHD18_SEL_MASK                  0x0007
#define BRPHY3_GPHY_CORE_SHD18_000_SHD18_SEL_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_000_SHD18_SEL_BITS                  3
#define BRPHY3_GPHY_CORE_SHD18_000_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD18_001
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD18_001 :: MANCHESTER_CODE_ERR [15:15] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x8000,15)
#define BRPHY3_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_MASK        0x8000
#define BRPHY3_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_ALIGN       0
#define BRPHY3_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_BITS        1
#define BRPHY3_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_SHIFT       15

/* BRPHY3_GPHY_CORE :: SHD18_001 :: EOF_ERR [14:14] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_EOF_ERR(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_EOF_ERR(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x4000,14)
#define BRPHY3_GPHY_CORE_SHD18_001_EOF_ERR_MASK                    0x4000
#define BRPHY3_GPHY_CORE_SHD18_001_EOF_ERR_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD18_001_EOF_ERR_BITS                    1
#define BRPHY3_GPHY_CORE_SHD18_001_EOF_ERR_SHIFT                   14

/* BRPHY3_GPHY_CORE :: SHD18_001 :: POLARITY_ERR [13:13] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_POLARITY_ERR(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_POLARITY_ERR(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x2000,13)
#define BRPHY3_GPHY_CORE_SHD18_001_POLARITY_ERR_MASK               0x2000
#define BRPHY3_GPHY_CORE_SHD18_001_POLARITY_ERR_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD18_001_POLARITY_ERR_BITS               1
#define BRPHY3_GPHY_CORE_SHD18_001_POLARITY_ERR_SHIFT              13

/* BRPHY3_GPHY_CORE :: SHD18_001 :: BLOCK_RXDV_EXT [12:12] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x1000,12)
#define BRPHY3_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_MASK             0x1000
#define BRPHY3_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_BITS             1
#define BRPHY3_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_SHIFT            12

/* BRPHY3_GPHY_CORE :: SHD18_001 :: BT_TXC_INV [11:11] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_BT_TXC_INV(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_BT_TXC_INV(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x800,11)
#define BRPHY3_GPHY_CORE_SHD18_001_BT_TXC_INV_MASK                 0x0800
#define BRPHY3_GPHY_CORE_SHD18_001_BT_TXC_INV_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD18_001_BT_TXC_INV_BITS                 1
#define BRPHY3_GPHY_CORE_SHD18_001_BT_TXC_INV_SHIFT                11

/* BRPHY3_GPHY_CORE :: SHD18_001 :: CLASS_AB_DRIVER_SEL [10:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x400,10)
#define BRPHY3_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_MASK        0x0400
#define BRPHY3_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_ALIGN       0
#define BRPHY3_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_BITS        1
#define BRPHY3_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_SHIFT       10

/* BRPHY3_GPHY_CORE :: SHD18_001 :: JABBER_DIS [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_JABBER_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_JABBER_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x200,9)
#define BRPHY3_GPHY_CORE_SHD18_001_JABBER_DIS_MASK                 0x0200
#define BRPHY3_GPHY_CORE_SHD18_001_JABBER_DIS_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD18_001_JABBER_DIS_BITS                 1
#define BRPHY3_GPHY_CORE_SHD18_001_JABBER_DIS_SHIFT                9

/* BRPHY3_GPHY_CORE :: SHD18_001 :: BT_SIG_DET_AUTOSWITCH [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x100,8)
#define BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_MASK      0x0100
#define BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_ALIGN     0
#define BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_BITS      1
#define BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_SHIFT     8

/* BRPHY3_GPHY_CORE :: SHD18_001 :: BT_SIG_DETECT_THD [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x80,7)
#define BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_MASK          0x0080
#define BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_BITS          1
#define BRPHY3_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_SHIFT         7

/* BRPHY3_GPHY_CORE :: SHD18_001 :: BT_ECHO [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_BT_ECHO(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_BT_ECHO(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x40,6)
#define BRPHY3_GPHY_CORE_SHD18_001_BT_ECHO_MASK                    0x0040
#define BRPHY3_GPHY_CORE_SHD18_001_BT_ECHO_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD18_001_BT_ECHO_BITS                    1
#define BRPHY3_GPHY_CORE_SHD18_001_BT_ECHO_SHIFT                   6

/* BRPHY3_GPHY_CORE :: SHD18_001 :: SQE_EN [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_SQE_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_SQE_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x20,5)
#define BRPHY3_GPHY_CORE_SHD18_001_SQE_EN_MASK                     0x0020
#define BRPHY3_GPHY_CORE_SHD18_001_SQE_EN_ALIGN                    0
#define BRPHY3_GPHY_CORE_SHD18_001_SQE_EN_BITS                     1
#define BRPHY3_GPHY_CORE_SHD18_001_SQE_EN_SHIFT                    5

/* BRPHY3_GPHY_CORE :: SHD18_001 :: BT_NO_DRIBBLE [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x10,4)
#define BRPHY3_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_MASK              0x0010
#define BRPHY3_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_BITS              1
#define BRPHY3_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_SHIFT             4

/* BRPHY3_GPHY_CORE :: SHD18_001 :: BT_POL_ERR_CNT_MAX [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x8,3)
#define BRPHY3_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_MASK         0x0008
#define BRPHY3_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_BITS         1
#define BRPHY3_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_SHIFT        3

/* BRPHY3_GPHY_CORE :: SHD18_001 :: SHD18_SEL [02:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_001_SHD18_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_001_SHD18_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_001,0x7,0)
#define BRPHY3_GPHY_CORE_SHD18_001_SHD18_SEL_MASK                  0x0007
#define BRPHY3_GPHY_CORE_SHD18_001_SHD18_SEL_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_001_SHD18_SEL_BITS                  3
#define BRPHY3_GPHY_CORE_SHD18_001_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD18_010
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD18_010 :: SPARE_REG_3 [15:11] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_3(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0xf800,11,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_3(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0xf800,11)
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_3_MASK                0xf800
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_3_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_3_BITS                5
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_3_SHIFT               11

/* BRPHY3_GPHY_CORE :: SHD18_010 :: SPARE_REG_2 [10:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_2(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x7c0,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_2(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x7c0,6)
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_2_MASK                0x07c0
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_2_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_2_BITS                5
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_2_SHIFT               6

/* BRPHY3_GPHY_CORE :: SHD18_010 :: SUPER_ISOLATE [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x20,5)
#define BRPHY3_GPHY_CORE_SHD18_010_SUPER_ISOLATE_MASK              0x0020
#define BRPHY3_GPHY_CORE_SHD18_010_SUPER_ISOLATE_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD18_010_SUPER_ISOLATE_BITS              1
#define BRPHY3_GPHY_CORE_SHD18_010_SUPER_ISOLATE_SHIFT             5

/* BRPHY3_GPHY_CORE :: SHD18_010 :: SPARE_REG_1 [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_1(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_1(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x10,4)
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_1_MASK                0x0010
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_1_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_1_BITS                1
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_1_SHIFT               4

/* BRPHY3_GPHY_CORE :: SHD18_010 :: SPARE_REG_0 [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_0(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_0(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x8,3)
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_0_MASK                0x0008
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_0_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_0_BITS                1
#define BRPHY3_GPHY_CORE_SHD18_010_SPARE_REG_0_SHIFT               3

/* BRPHY3_GPHY_CORE :: SHD18_010 :: SHD18_SEL [02:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_010_SHD18_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_010_SHD18_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_010,0x7,0)
#define BRPHY3_GPHY_CORE_SHD18_010_SHD18_SEL_MASK                  0x0007
#define BRPHY3_GPHY_CORE_SHD18_010_SHD18_SEL_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_010_SHD18_SEL_BITS                  3
#define BRPHY3_GPHY_CORE_SHD18_010_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD18_011
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD18_011 :: IP_PHONE_DETECT [15:15] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x8000,15)
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_MASK            0x8000
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_SHIFT           15

/* BRPHY3_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_CNTR [14:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x7c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x7c00,10)
#define BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_MASK          0x7c00
#define BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_BITS          5
#define BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_SHIFT         10

/* BRPHY3_GPHY_CORE :: SHD18_011 :: ALT_RANDOM_SEED [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x200,9)
#define BRPHY3_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_MASK            0x0200
#define BRPHY3_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_SHIFT           9

/* BRPHY3_GPHY_CORE :: SHD18_011 :: RESTART_AUTONEG [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x100,8)
#define BRPHY3_GPHY_CORE_SHD18_011_RESTART_AUTONEG_MASK            0x0100
#define BRPHY3_GPHY_CORE_SHD18_011_RESTART_AUTONEG_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_011_RESTART_AUTONEG_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_011_RESTART_AUTONEG_SHIFT           8

/* BRPHY3_GPHY_CORE :: SHD18_011 :: IP_PHONE_WINDOW [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x80,7)
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_MASK            0x0080
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_SHIFT           7

/* BRPHY3_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_EN [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x40,6)
#define BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_MASK            0x0040
#define BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_SHIFT           6

/* BRPHY3_GPHY_CORE :: SHD18_011 :: IP_PHONE_DET_EN [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x20,5)
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_MASK            0x0020
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_SHIFT           5

/* BRPHY3_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_DIS [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x10,4)
#define BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_MASK      0x0010
#define BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_ALIGN     0
#define BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_BITS      1
#define BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_SHIFT     4

/* BRPHY3_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_SW [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x8,3)
#define BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_MASK       0x0008
#define BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_ALIGN      0
#define BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_BITS       1
#define BRPHY3_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_SHIFT      3

/* BRPHY3_GPHY_CORE :: SHD18_011 :: SHD18_SEL [02:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_011_SHD18_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_011_SHD18_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_011,0x7,0)
#define BRPHY3_GPHY_CORE_SHD18_011_SHD18_SEL_MASK                  0x0007
#define BRPHY3_GPHY_CORE_SHD18_011_SHD18_SEL_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_011_SHD18_SEL_BITS                  3
#define BRPHY3_GPHY_CORE_SHD18_011_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD18_100
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD18_100 :: RMT_LPBK_EN [15:15] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x8000,15)
#define BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_EN_MASK                0x8000
#define BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_EN_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_EN_BITS                1
#define BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_EN_SHIFT               15

/* BRPHY3_GPHY_CORE :: SHD18_100 :: TDK_FIX_EN [14:14] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x4000,14)
#define BRPHY3_GPHY_CORE_SHD18_100_TDK_FIX_EN_MASK                 0x4000
#define BRPHY3_GPHY_CORE_SHD18_100_TDK_FIX_EN_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD18_100_TDK_FIX_EN_BITS                 1
#define BRPHY3_GPHY_CORE_SHD18_100_TDK_FIX_EN_SHIFT                14

/* BRPHY3_GPHY_CORE :: SHD18_100 :: BT_DLL_BYPASS_CLK [13:13] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x2000,13)
#define BRPHY3_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_MASK          0x2000
#define BRPHY3_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_BITS          1
#define BRPHY3_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_SHIFT         13

/* BRPHY3_GPHY_CORE :: SHD18_100 :: BLOCK_10BT_RESTART_AUTONEG [12:12] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x1000,12)
#define BRPHY3_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_MASK 0x1000
#define BRPHY3_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_ALIGN 0
#define BRPHY3_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_BITS 1
#define BRPHY3_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_SHIFT 12

/* BRPHY3_GPHY_CORE :: SHD18_100 :: RMT_LPBK_TRISTATE [11:11] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x800,11)
#define BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_MASK          0x0800
#define BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_BITS          1
#define BRPHY3_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_SHIFT         11

/* BRPHY3_GPHY_CORE :: SHD18_100 :: BT_WAKEUP [10:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_BT_WAKEUP(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_BT_WAKEUP(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x400,10)
#define BRPHY3_GPHY_CORE_SHD18_100_BT_WAKEUP_MASK                  0x0400
#define BRPHY3_GPHY_CORE_SHD18_100_BT_WAKEUP_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_100_BT_WAKEUP_BITS                  1
#define BRPHY3_GPHY_CORE_SHD18_100_BT_WAKEUP_SHIFT                 10

/* BRPHY3_GPHY_CORE :: SHD18_100 :: BT_POLARITY_BYPASS [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x200,9)
#define BRPHY3_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_MASK         0x0200
#define BRPHY3_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_ALIGN        0
#define BRPHY3_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_BITS         1
#define BRPHY3_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_SHIFT        9

/* BRPHY3_GPHY_CORE :: SHD18_100 :: BT_IDLE_BYPASS [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x100,8)
#define BRPHY3_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_MASK             0x0100
#define BRPHY3_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_BITS             1
#define BRPHY3_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_SHIFT            8

/* BRPHY3_GPHY_CORE :: SHD18_100 :: BT_CLK_RESET_EN [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x80,7)
#define BRPHY3_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_MASK            0x0080
#define BRPHY3_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_SHIFT           7

/* BRPHY3_GPHY_CORE :: SHD18_100 :: BT_BYPASS_ADC [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x40,6)
#define BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_MASK              0x0040
#define BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_BITS              1
#define BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_SHIFT             6

/* BRPHY3_GPHY_CORE :: SHD18_100 :: BT_BYPASS_CRS [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x20,5)
#define BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_MASK              0x0020
#define BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_BITS              1
#define BRPHY3_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_SHIFT             5

/* BRPHY3_GPHY_CORE :: SHD18_100 :: SWAP_RXMDIX [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x10,4)
#define BRPHY3_GPHY_CORE_SHD18_100_SWAP_RXMDIX_MASK                0x0010
#define BRPHY3_GPHY_CORE_SHD18_100_SWAP_RXMDIX_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_100_SWAP_RXMDIX_BITS                1
#define BRPHY3_GPHY_CORE_SHD18_100_SWAP_RXMDIX_SHIFT               4

/* BRPHY3_GPHY_CORE :: SHD18_100 :: HALFOUT [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_HALFOUT(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_HALFOUT(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x8,3)
#define BRPHY3_GPHY_CORE_SHD18_100_HALFOUT_MASK                    0x0008
#define BRPHY3_GPHY_CORE_SHD18_100_HALFOUT_ALIGN                   0
#define BRPHY3_GPHY_CORE_SHD18_100_HALFOUT_BITS                    1
#define BRPHY3_GPHY_CORE_SHD18_100_HALFOUT_SHIFT                   3

/* BRPHY3_GPHY_CORE :: SHD18_100 :: SHD18_SEL [02:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_100_SHD18_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_100_SHD18_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_100,0x7,0)
#define BRPHY3_GPHY_CORE_SHD18_100_SHD18_SEL_MASK                  0x0007
#define BRPHY3_GPHY_CORE_SHD18_100_SHD18_SEL_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_100_SHD18_SEL_BITS                  3
#define BRPHY3_GPHY_CORE_SHD18_100_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD18_101
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD18_101 :: COPPER_ENG_DET_OV [15:15] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x8000,15)
#define BRPHY3_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_MASK          0x8000
#define BRPHY3_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_BITS          1
#define BRPHY3_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_SHIFT         15

/* BRPHY3_GPHY_CORE :: SHD18_101 :: ADCFIFO_TX_FIX [14:14] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x4000,14)
#define BRPHY3_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_MASK             0x4000
#define BRPHY3_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_ALIGN            0
#define BRPHY3_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_BITS             1
#define BRPHY3_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_SHIFT            14

/* BRPHY3_GPHY_CORE :: SHD18_101 :: CLASS_AB_DVT_EN [13:13] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x2000,13)
#define BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_MASK            0x2000
#define BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_SHIFT           13

/* BRPHY3_GPHY_CORE :: SHD18_101 :: CLASS_AB_EN [12:12] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x1000,12)
#define BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_EN_MASK                0x1000
#define BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_EN_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_EN_BITS                1
#define BRPHY3_GPHY_CORE_SHD18_101_CLASS_AB_EN_SHIFT               12

/* BRPHY3_GPHY_CORE :: SHD18_101 :: ENC_ERR_SCALE [11:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0xc00,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0xc00,10)
#define BRPHY3_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_MASK              0x0c00
#define BRPHY3_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_ALIGN             0
#define BRPHY3_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_BITS              2
#define BRPHY3_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_SHIFT             10

/* BRPHY3_GPHY_CORE :: SHD18_101 :: SPARE_REG [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x200,9)
#define BRPHY3_GPHY_CORE_SHD18_101_SPARE_REG_MASK                  0x0200
#define BRPHY3_GPHY_CORE_SHD18_101_SPARE_REG_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_101_SPARE_REG_BITS                  1
#define BRPHY3_GPHY_CORE_SHD18_101_SPARE_REG_SHIFT                 9

/* BRPHY3_GPHY_CORE :: SHD18_101 :: AUTO_ENCODING_CORRECTION [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x100,8)
#define BRPHY3_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_MASK   0x0100
#define BRPHY3_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_ALIGN  0
#define BRPHY3_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_BITS   1
#define BRPHY3_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_SHIFT  8

/* BRPHY3_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_RX [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x80,7)
#define BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_MASK        0x0080
#define BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_ALIGN       0
#define BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_BITS        1
#define BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_SHIFT       7

/* BRPHY3_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_TX [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x40,6)
#define BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_MASK        0x0040
#define BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_ALIGN       0
#define BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_BITS        1
#define BRPHY3_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_SHIFT       6

/* BRPHY3_GPHY_CORE :: SHD18_101 :: EC_AS_NEXT [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x20,5)
#define BRPHY3_GPHY_CORE_SHD18_101_EC_AS_NEXT_MASK                 0x0020
#define BRPHY3_GPHY_CORE_SHD18_101_EC_AS_NEXT_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD18_101_EC_AS_NEXT_BITS                 1
#define BRPHY3_GPHY_CORE_SHD18_101_EC_AS_NEXT_SHIFT                5

/* BRPHY3_GPHY_CORE :: SHD18_101 :: FORCE_MDIX [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_FORCE_MDIX(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_FORCE_MDIX(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x10,4)
#define BRPHY3_GPHY_CORE_SHD18_101_FORCE_MDIX_MASK                 0x0010
#define BRPHY3_GPHY_CORE_SHD18_101_FORCE_MDIX_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD18_101_FORCE_MDIX_BITS                 1
#define BRPHY3_GPHY_CORE_SHD18_101_FORCE_MDIX_SHIFT                4

/* BRPHY3_GPHY_CORE :: SHD18_101 :: EN_PWRDNTDAC [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x8,3)
#define BRPHY3_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_MASK               0x0008
#define BRPHY3_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_BITS               1
#define BRPHY3_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_SHIFT              3

/* BRPHY3_GPHY_CORE :: SHD18_101 :: SHD18_SEL [02:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_101_SHD18_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_101_SHD18_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_101,0x7,0)
#define BRPHY3_GPHY_CORE_SHD18_101_SHD18_SEL_MASK                  0x0007
#define BRPHY3_GPHY_CORE_SHD18_101_SHD18_SEL_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_101_SHD18_SEL_BITS                  3
#define BRPHY3_GPHY_CORE_SHD18_101_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD18_110
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD18_110 :: IP_PHONE_SEED_WR_EN [15:15] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_110,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_110,0x8000,15)
#define BRPHY3_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_MASK        0x8000
#define BRPHY3_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_ALIGN       0
#define BRPHY3_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_BITS        1
#define BRPHY3_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_SHIFT       15

/* BRPHY3_GPHY_CORE :: SHD18_110 :: SPARE_REG [14:14] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_110_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_110,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_110_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_110,0x4000,14)
#define BRPHY3_GPHY_CORE_SHD18_110_SPARE_REG_MASK                  0x4000
#define BRPHY3_GPHY_CORE_SHD18_110_SPARE_REG_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_110_SPARE_REG_BITS                  1
#define BRPHY3_GPHY_CORE_SHD18_110_SPARE_REG_SHIFT                 14

/* BRPHY3_GPHY_CORE :: SHD18_110 :: LOC_IP_PHONE_SEED [13:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_110,0x3ff8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_110,0x3ff8,3)
#define BRPHY3_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_MASK          0x3ff8
#define BRPHY3_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_ALIGN         0
#define BRPHY3_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_BITS          11
#define BRPHY3_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_SHIFT         3

/* BRPHY3_GPHY_CORE :: SHD18_110 :: SHD18_SEL [02:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_110_SHD18_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_110,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_110_SHD18_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_110,0x7,0)
#define BRPHY3_GPHY_CORE_SHD18_110_SHD18_SEL_MASK                  0x0007
#define BRPHY3_GPHY_CORE_SHD18_110_SHD18_SEL_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_110_SHD18_SEL_BITS                  3
#define BRPHY3_GPHY_CORE_SHD18_110_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SHD18_111
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SHD18_111 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_SHD18_111_RESERVED0_MASK                  0x8000
#define BRPHY3_GPHY_CORE_SHD18_111_RESERVED0_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_111_RESERVED0_BITS                  1
#define BRPHY3_GPHY_CORE_SHD18_111_RESERVED0_SHIFT                 15

/* BRPHY3_GPHY_CORE :: SHD18_111 :: SHD18_RDSEL [14:12] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x7000,12,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x7000,12)
#define BRPHY3_GPHY_CORE_SHD18_111_SHD18_RDSEL_MASK                0x7000
#define BRPHY3_GPHY_CORE_SHD18_111_SHD18_RDSEL_ALIGN               0
#define BRPHY3_GPHY_CORE_SHD18_111_SHD18_RDSEL_BITS                3
#define BRPHY3_GPHY_CORE_SHD18_111_SHD18_RDSEL_SHIFT               12

/* BRPHY3_GPHY_CORE :: SHD18_111 :: PKT_CNTR [11:11] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_PKT_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_PKT_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x800,11)
#define BRPHY3_GPHY_CORE_SHD18_111_PKT_CNTR_MASK                   0x0800
#define BRPHY3_GPHY_CORE_SHD18_111_PKT_CNTR_ALIGN                  0
#define BRPHY3_GPHY_CORE_SHD18_111_PKT_CNTR_BITS                   1
#define BRPHY3_GPHY_CORE_SHD18_111_PKT_CNTR_SHIFT                  11

/* BRPHY3_GPHY_CORE :: SHD18_111 :: BYPASS_WIRESPEED_TIMER [10:10] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x400,10)
#define BRPHY3_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_MASK     0x0400
#define BRPHY3_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_ALIGN    0
#define BRPHY3_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_BITS     1
#define BRPHY3_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_SHIFT    10

/* BRPHY3_GPHY_CORE :: SHD18_111 :: FORCE_AUTO_MDIX [09:09] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x200,9)
#define BRPHY3_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_MASK            0x0200
#define BRPHY3_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_ALIGN           0
#define BRPHY3_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_BITS            1
#define BRPHY3_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_SHIFT           9

/* BRPHY3_GPHY_CORE :: SHD18_111 :: RGMII_TIMING [08:08] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_RGMII_TIMING(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_RGMII_TIMING(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x100,8)
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_TIMING_MASK               0x0100
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_TIMING_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_TIMING_BITS               1
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_TIMING_SHIFT              8

/* BRPHY3_GPHY_CORE :: SHD18_111 :: RGMII [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_RGMII(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_RGMII(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x80,7)
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_MASK                      0x0080
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_ALIGN                     0
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_BITS                      1
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_SHIFT                     7

/* BRPHY3_GPHY_CORE :: SHD18_111 :: RGMII_RXER [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_RGMII_RXER(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_RGMII_RXER(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x40,6)
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_RXER_MASK                 0x0040
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_RXER_ALIGN                0
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_RXER_BITS                 1
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_RXER_SHIFT                6

/* BRPHY3_GPHY_CORE :: SHD18_111 :: RGMII_OB_STATUS_DIS [05:05] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x20,5)
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_MASK        0x0020
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_ALIGN       0
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_BITS        1
#define BRPHY3_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_SHIFT       5

/* BRPHY3_GPHY_CORE :: SHD18_111 :: WIRESPEED_EN [04:04] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x10,4)
#define BRPHY3_GPHY_CORE_SHD18_111_WIRESPEED_EN_MASK               0x0010
#define BRPHY3_GPHY_CORE_SHD18_111_WIRESPEED_EN_ALIGN              0
#define BRPHY3_GPHY_CORE_SHD18_111_WIRESPEED_EN_BITS               1
#define BRPHY3_GPHY_CORE_SHD18_111_WIRESPEED_EN_SHIFT              4

/* BRPHY3_GPHY_CORE :: SHD18_111 :: MDIO_ALL_PHY_SEL [03:03] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x8,3)
#define BRPHY3_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_MASK           0x0008
#define BRPHY3_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_ALIGN          0
#define BRPHY3_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_BITS           1
#define BRPHY3_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_SHIFT          3

/* BRPHY3_GPHY_CORE :: SHD18_111 :: SHD18_SEL [02:00] */
#define Wr_BRPHY3_GPHY_CORE_SHD18_111_SHD18_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_SHD18_111_SHD18_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SHD18_111,0x7,0)
#define BRPHY3_GPHY_CORE_SHD18_111_SHD18_SEL_MASK                  0x0007
#define BRPHY3_GPHY_CORE_SHD18_111_SHD18_SEL_ALIGN                 0
#define BRPHY3_GPHY_CORE_SHD18_111_SHD18_SEL_BITS                  3
#define BRPHY3_GPHY_CORE_SHD18_111_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP00
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP00 :: PKT_CNTR [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP00_PKT_CNTR(x) WriteReg16(BRPHY3_GPHY_CORE_EXP00,x)
#define Rd_BRPHY3_GPHY_CORE_EXP00_PKT_CNTR(x) ReadReg16(BRPHY3_GPHY_CORE_EXP00)
#define BRPHY3_GPHY_CORE_EXP00_PKT_CNTR_MASK                       0xffff
#define BRPHY3_GPHY_CORE_EXP00_PKT_CNTR_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP00_PKT_CNTR_BITS                       16
#define BRPHY3_GPHY_CORE_EXP00_PKT_CNTR_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP01
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP01 :: LATE_COL_CNTR [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_LATE_COL_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_LATE_COL_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x8000,15)
#define BRPHY3_GPHY_CORE_EXP01_LATE_COL_CNTR_MASK                  0x8000
#define BRPHY3_GPHY_CORE_EXP01_LATE_COL_CNTR_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP01_LATE_COL_CNTR_BITS                  1
#define BRPHY3_GPHY_CORE_EXP01_LATE_COL_CNTR_SHIFT                 15

/* BRPHY3_GPHY_CORE :: EXP01 :: RMT_COPPER_ERR [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x4000,14)
#define BRPHY3_GPHY_CORE_EXP01_RMT_COPPER_ERR_MASK                 0x4000
#define BRPHY3_GPHY_CORE_EXP01_RMT_COPPER_ERR_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP01_RMT_COPPER_ERR_BITS                 1
#define BRPHY3_GPHY_CORE_EXP01_RMT_COPPER_ERR_SHIFT                14

/* BRPHY3_GPHY_CORE :: EXP01 :: SERDES_LINK_PARTNER_RESTARTED [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x2000,13)
#define BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_MASK  0x2000
#define BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_ALIGN 0
#define BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_BITS  1
#define BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_SHIFT 13

/* BRPHY3_GPHY_CORE :: EXP01 :: SERDES_CRC_ERR [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP01_SERDES_CRC_ERR_MASK                 0x1000
#define BRPHY3_GPHY_CORE_EXP01_SERDES_CRC_ERR_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP01_SERDES_CRC_ERR_BITS                 1
#define BRPHY3_GPHY_CORE_EXP01_SERDES_CRC_ERR_SHIFT                12

/* BRPHY3_GPHY_CORE :: EXP01 :: SGMII_SLAVE_CHANGE [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x800,11)
#define BRPHY3_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_MASK             0x0800
#define BRPHY3_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_ALIGN            0
#define BRPHY3_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_BITS             1
#define BRPHY3_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_SHIFT            11

/* BRPHY3_GPHY_CORE :: EXP01 :: FX_SERDES_CHANGE [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x400,10)
#define BRPHY3_GPHY_CORE_EXP01_FX_SERDES_CHANGE_MASK               0x0400
#define BRPHY3_GPHY_CORE_EXP01_FX_SERDES_CHANGE_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP01_FX_SERDES_CHANGE_BITS               1
#define BRPHY3_GPHY_CORE_EXP01_FX_SERDES_CHANGE_SHIFT              10

/* BRPHY3_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_PAGE_RCVD [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x200,9)
#define BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_MASK       0x0200
#define BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_ALIGN      0
#define BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_BITS       1
#define BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_SHIFT      9

/* BRPHY3_GPHY_CORE :: EXP01 :: EXT_SERDES_SEL_CHANGE [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x100,8)
#define BRPHY3_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_MASK          0x0100
#define BRPHY3_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_ALIGN         0
#define BRPHY3_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_BITS          1
#define BRPHY3_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_SHIFT         8

/* BRPHY3_GPHY_CORE :: EXP01 :: MODE_SEL_CHANGE [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x80,7)
#define BRPHY3_GPHY_CORE_EXP01_MODE_SEL_CHANGE_MASK                0x0080
#define BRPHY3_GPHY_CORE_EXP01_MODE_SEL_CHANGE_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP01_MODE_SEL_CHANGE_BITS                1
#define BRPHY3_GPHY_CORE_EXP01_MODE_SEL_CHANGE_SHIFT               7

/* BRPHY3_GPHY_CORE :: EXP01 :: SERDES_LINK_STATUS_CHANGE [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x40,6)
#define BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_MASK      0x0040
#define BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_ALIGN     0
#define BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_BITS      1
#define BRPHY3_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_SHIFT     6

/* BRPHY3_GPHY_CORE :: EXP01 :: RUDI_C_DET [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_RUDI_C_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_RUDI_C_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x20,5)
#define BRPHY3_GPHY_CORE_EXP01_RUDI_C_DET_MASK                     0x0020
#define BRPHY3_GPHY_CORE_EXP01_RUDI_C_DET_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP01_RUDI_C_DET_BITS                     1
#define BRPHY3_GPHY_CORE_EXP01_RUDI_C_DET_SHIFT                    5

/* BRPHY3_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_ERR [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x10,4)
#define BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_MASK             0x0010
#define BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_ALIGN            0
#define BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_BITS             1
#define BRPHY3_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_SHIFT            4

/* BRPHY3_GPHY_CORE :: EXP01 :: RUDI_I_DET [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_RUDI_I_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_RUDI_I_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x8,3)
#define BRPHY3_GPHY_CORE_EXP01_RUDI_I_DET_MASK                     0x0008
#define BRPHY3_GPHY_CORE_EXP01_RUDI_I_DET_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP01_RUDI_I_DET_BITS                     1
#define BRPHY3_GPHY_CORE_EXP01_RUDI_I_DET_SHIFT                    3

/* BRPHY3_GPHY_CORE :: EXP01 :: SERDES_RCVD_BREAK_LINK_CONDITION [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x4,2)
#define BRPHY3_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_MASK 0x0004
#define BRPHY3_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_ALIGN 0
#define BRPHY3_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_BITS 1
#define BRPHY3_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_SHIFT 2

/* BRPHY3_GPHY_CORE :: EXP01 :: ABIST_COMPLETE [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_ABIST_COMPLETE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_ABIST_COMPLETE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x2,1)
#define BRPHY3_GPHY_CORE_EXP01_ABIST_COMPLETE_MASK                 0x0002
#define BRPHY3_GPHY_CORE_EXP01_ABIST_COMPLETE_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP01_ABIST_COMPLETE_BITS                 1
#define BRPHY3_GPHY_CORE_EXP01_ABIST_COMPLETE_SHIFT                1

/* BRPHY3_GPHY_CORE :: EXP01 :: TX_CRC_ERR [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP01_TX_CRC_ERR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP01,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP01_TX_CRC_ERR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP01,0x1,0)
#define BRPHY3_GPHY_CORE_EXP01_TX_CRC_ERR_MASK                     0x0001
#define BRPHY3_GPHY_CORE_EXP01_TX_CRC_ERR_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP01_TX_CRC_ERR_BITS                     1
#define BRPHY3_GPHY_CORE_EXP01_TX_CRC_ERR_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP02
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP02 :: EXP_INT_MASK [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP02_EXP_INT_MASK(x) WriteReg16(BRPHY3_GPHY_CORE_EXP02,x)
#define Rd_BRPHY3_GPHY_CORE_EXP02_EXP_INT_MASK(x) ReadReg16(BRPHY3_GPHY_CORE_EXP02)
#define BRPHY3_GPHY_CORE_EXP02_EXP_INT_MASK_MASK                   0xffff
#define BRPHY3_GPHY_CORE_EXP02_EXP_INT_MASK_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP02_EXP_INT_MASK_BITS                   16
#define BRPHY3_GPHY_CORE_EXP02_EXP_INT_MASK_SHIFT                  0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP03
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP03 :: SPARE_REG [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP03_SPARE_REG(x) WriteReg16(BRPHY3_GPHY_CORE_EXP03,x)
#define Rd_BRPHY3_GPHY_CORE_EXP03_SPARE_REG(x) ReadReg16(BRPHY3_GPHY_CORE_EXP03)
#define BRPHY3_GPHY_CORE_EXP03_SPARE_REG_MASK                      0xffff
#define BRPHY3_GPHY_CORE_EXP03_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP03_SPARE_REG_BITS                      16
#define BRPHY3_GPHY_CORE_EXP03_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP04
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP04 :: reserved0 [15:11] */
#define BRPHY3_GPHY_CORE_EXP04_RESERVED0_MASK                      0xf800
#define BRPHY3_GPHY_CORE_EXP04_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP04_RESERVED0_BITS                      5
#define BRPHY3_GPHY_CORE_EXP04_RESERVED0_SHIFT                     11

/* BRPHY3_GPHY_CORE :: EXP04 :: BC_LED_EN [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXP04_BC_LED_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP04,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXP04_BC_LED_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP04,0x400,10)
#define BRPHY3_GPHY_CORE_EXP04_BC_LED_EN_MASK                      0x0400
#define BRPHY3_GPHY_CORE_EXP04_BC_LED_EN_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP04_BC_LED_EN_BITS                      1
#define BRPHY3_GPHY_CORE_EXP04_BC_LED_EN_SHIFT                     10

/* BRPHY3_GPHY_CORE :: EXP04 :: FLASHNOW [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXP04_FLASHNOW(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP04,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXP04_FLASHNOW(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP04,0x200,9)
#define BRPHY3_GPHY_CORE_EXP04_FLASHNOW_MASK                       0x0200
#define BRPHY3_GPHY_CORE_EXP04_FLASHNOW_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP04_FLASHNOW_BITS                       1
#define BRPHY3_GPHY_CORE_EXP04_FLASHNOW_SHIFT                      9

/* BRPHY3_GPHY_CORE :: EXP04 :: INPHASE [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP04_INPHASE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP04,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP04_INPHASE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP04,0x100,8)
#define BRPHY3_GPHY_CORE_EXP04_INPHASE_MASK                        0x0100
#define BRPHY3_GPHY_CORE_EXP04_INPHASE_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP04_INPHASE_BITS                        1
#define BRPHY3_GPHY_CORE_EXP04_INPHASE_SHIFT                       8

/* BRPHY3_GPHY_CORE :: EXP04 :: BC_SEL_1 [07:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP04_BC_SEL_1(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP04,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP04_BC_SEL_1(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP04,0xf0,4)
#define BRPHY3_GPHY_CORE_EXP04_BC_SEL_1_MASK                       0x00f0
#define BRPHY3_GPHY_CORE_EXP04_BC_SEL_1_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP04_BC_SEL_1_BITS                       4
#define BRPHY3_GPHY_CORE_EXP04_BC_SEL_1_SHIFT                      4

/* BRPHY3_GPHY_CORE :: EXP04 :: BC_SEL_0 [03:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP04_BC_SEL_0(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP04,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP04_BC_SEL_0(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP04,0xf,0)
#define BRPHY3_GPHY_CORE_EXP04_BC_SEL_0_MASK                       0x000f
#define BRPHY3_GPHY_CORE_EXP04_BC_SEL_0_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP04_BC_SEL_0_BITS                       4
#define BRPHY3_GPHY_CORE_EXP04_BC_SEL_0_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP05
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP05 :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_EXP05_RESERVED0_MASK                      0xf000
#define BRPHY3_GPHY_CORE_EXP05_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP05_RESERVED0_BITS                      4
#define BRPHY3_GPHY_CORE_EXP05_RESERVED0_SHIFT                     12

/* BRPHY3_GPHY_CORE :: EXP05 :: ALTERNATION_RATE [11:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP05_ALTERNATION_RATE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP05,0xfc0,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP05_ALTERNATION_RATE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP05,0xfc0,6)
#define BRPHY3_GPHY_CORE_EXP05_ALTERNATION_RATE_MASK               0x0fc0
#define BRPHY3_GPHY_CORE_EXP05_ALTERNATION_RATE_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP05_ALTERNATION_RATE_BITS               6
#define BRPHY3_GPHY_CORE_EXP05_ALTERNATION_RATE_SHIFT              6

/* BRPHY3_GPHY_CORE :: EXP05 :: FLASH_RATE [05:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP05_FLASH_RATE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP05,0x3f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP05_FLASH_RATE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP05,0x3f,0)
#define BRPHY3_GPHY_CORE_EXP05_FLASH_RATE_MASK                     0x003f
#define BRPHY3_GPHY_CORE_EXP05_FLASH_RATE_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP05_FLASH_RATE_BITS                     6
#define BRPHY3_GPHY_CORE_EXP05_FLASH_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP06
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP06 :: reserved0 [15:08] */
#define BRPHY3_GPHY_CORE_EXP06_RESERVED0_MASK                      0xff00
#define BRPHY3_GPHY_CORE_EXP06_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP06_RESERVED0_BITS                      8
#define BRPHY3_GPHY_CORE_EXP06_RESERVED0_SHIFT                     8

/* BRPHY3_GPHY_CORE :: EXP06 :: SPARE_REG [07:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP06_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP06,0xc0,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP06_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP06,0xc0,6)
#define BRPHY3_GPHY_CORE_EXP06_SPARE_REG_MASK                      0x00c0
#define BRPHY3_GPHY_CORE_EXP06_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP06_SPARE_REG_BITS                      2
#define BRPHY3_GPHY_CORE_EXP06_SPARE_REG_SHIFT                     6

/* BRPHY3_GPHY_CORE :: EXP06 :: BLINK_UPDATE_NOW [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP06,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP06,0x20,5)
#define BRPHY3_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_MASK               0x0020
#define BRPHY3_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_BITS               1
#define BRPHY3_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_SHIFT              5

/* BRPHY3_GPHY_CORE :: EXP06 :: BLINK_RATE [04:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP06_BLINK_RATE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP06,0x1f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP06_BLINK_RATE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP06,0x1f,0)
#define BRPHY3_GPHY_CORE_EXP06_BLINK_RATE_MASK                     0x001f
#define BRPHY3_GPHY_CORE_EXP06_BLINK_RATE_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP06_BLINK_RATE_BITS                     5
#define BRPHY3_GPHY_CORE_EXP06_BLINK_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP07
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP07 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_EXP07_RESERVED0_MASK                      0x8000
#define BRPHY3_GPHY_CORE_EXP07_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP07_RESERVED0_BITS                      1
#define BRPHY3_GPHY_CORE_EXP07_RESERVED0_SHIFT                     15

/* BRPHY3_GPHY_CORE :: EXP07 :: EXT_MAX_LP_WIDTH [14:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP07,0x7f00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP07,0x7f00,8)
#define BRPHY3_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_MASK               0x7f00
#define BRPHY3_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_BITS               7
#define BRPHY3_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_SHIFT              8

/* BRPHY3_GPHY_CORE :: EXP07 :: SPARE_REG [07:03] */
#define Wr_BRPHY3_GPHY_CORE_EXP07_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP07,0xf8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXP07_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP07,0xf8,3)
#define BRPHY3_GPHY_CORE_EXP07_SPARE_REG_MASK                      0x00f8
#define BRPHY3_GPHY_CORE_EXP07_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP07_SPARE_REG_BITS                      5
#define BRPHY3_GPHY_CORE_EXP07_SPARE_REG_SHIFT                     3

/* BRPHY3_GPHY_CORE :: EXP07 :: COPPER_FX_SIGSTAT_SEL [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP07,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP07,0x4,2)
#define BRPHY3_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_MASK          0x0004
#define BRPHY3_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_ALIGN         0
#define BRPHY3_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_BITS          1
#define BRPHY3_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_SHIFT         2

/* BRPHY3_GPHY_CORE :: EXP07 :: FAULTING [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP07_FAULTING(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP07,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP07_FAULTING(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP07,0x2,1)
#define BRPHY3_GPHY_CORE_EXP07_FAULTING_MASK                       0x0002
#define BRPHY3_GPHY_CORE_EXP07_FAULTING_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP07_FAULTING_BITS                       1
#define BRPHY3_GPHY_CORE_EXP07_FAULTING_SHIFT                      1

/* BRPHY3_GPHY_CORE :: EXP07 :: FEF_EN [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP07_FEF_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP07,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP07_FEF_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP07,0x1,0)
#define BRPHY3_GPHY_CORE_EXP07_FEF_EN_MASK                         0x0001
#define BRPHY3_GPHY_CORE_EXP07_FEF_EN_ALIGN                        0
#define BRPHY3_GPHY_CORE_EXP07_FEF_EN_BITS                         1
#define BRPHY3_GPHY_CORE_EXP07_FEF_EN_SHIFT                        0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP08
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP08 :: SILENT_LPBK [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_SILENT_LPBK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_SILENT_LPBK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x8000,15)
#define BRPHY3_GPHY_CORE_EXP08_SILENT_LPBK_MASK                    0x8000
#define BRPHY3_GPHY_CORE_EXP08_SILENT_LPBK_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP08_SILENT_LPBK_BITS                    1
#define BRPHY3_GPHY_CORE_EXP08_SILENT_LPBK_SHIFT                   15

/* BRPHY3_GPHY_CORE :: EXP08 :: RX_POLARITY_OV [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x4000,14)
#define BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_MASK                 0x4000
#define BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_BITS                 1
#define BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_SHIFT                14

/* BRPHY3_GPHY_CORE :: EXP08 :: RX_POLARITY_OV_VAL [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x2000,13)
#define BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_MASK             0x2000
#define BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_ALIGN            0
#define BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_BITS             1
#define BRPHY3_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_SHIFT            13

/* BRPHY3_GPHY_CORE :: EXP08 :: BT_BYTE_ALIGN_PREAM [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_MASK            0x1000
#define BRPHY3_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_ALIGN           0
#define BRPHY3_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_BITS            1
#define BRPHY3_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_SHIFT           12

/* BRPHY3_GPHY_CORE :: EXP08 :: BT_PREAM_SUPPRESS [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x800,11)
#define BRPHY3_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_MASK              0x0800
#define BRPHY3_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_BITS              1
#define BRPHY3_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_SHIFT             11

/* BRPHY3_GPHY_CORE :: EXP08 :: EXT_MAX_LP_WIDTH_EN [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x400,10)
#define BRPHY3_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_MASK            0x0400
#define BRPHY3_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_BITS            1
#define BRPHY3_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_SHIFT           10

/* BRPHY3_GPHY_CORE :: EXP08 :: AUTO_EARLY_DAC_WAKE [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x200,9)
#define BRPHY3_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_MASK            0x0200
#define BRPHY3_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_ALIGN           0
#define BRPHY3_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_BITS            1
#define BRPHY3_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_SHIFT           9

/* BRPHY3_GPHY_CORE :: EXP08 :: FORCE_EARLY_DAC_WAKE [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x100,8)
#define BRPHY3_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_MASK           0x0100
#define BRPHY3_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_ALIGN          0
#define BRPHY3_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_BITS           1
#define BRPHY3_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_SHIFT          8

/* BRPHY3_GPHY_CORE :: EXP08 :: SUPPRESS_CRS_HDX [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x80,7)
#define BRPHY3_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_MASK               0x0080
#define BRPHY3_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_BITS               1
#define BRPHY3_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_SHIFT              7

/* BRPHY3_GPHY_CORE :: EXP08 :: REJECT_MORE_15MHZ [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x40,6)
#define BRPHY3_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_MASK              0x0040
#define BRPHY3_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_BITS              1
#define BRPHY3_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_SHIFT             6

/* BRPHY3_GPHY_CORE :: EXP08 :: POLARITY_INVERT [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_POLARITY_INVERT(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_POLARITY_INVERT(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x20,5)
#define BRPHY3_GPHY_CORE_EXP08_POLARITY_INVERT_MASK                0x0020
#define BRPHY3_GPHY_CORE_EXP08_POLARITY_INVERT_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP08_POLARITY_INVERT_BITS                1
#define BRPHY3_GPHY_CORE_EXP08_POLARITY_INVERT_SHIFT               5

/* BRPHY3_GPHY_CORE :: EXP08 :: BLOCK_NARROW_LP [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x10,4)
#define BRPHY3_GPHY_CORE_EXP08_BLOCK_NARROW_LP_MASK                0x0010
#define BRPHY3_GPHY_CORE_EXP08_BLOCK_NARROW_LP_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP08_BLOCK_NARROW_LP_BITS                1
#define BRPHY3_GPHY_CORE_EXP08_BLOCK_NARROW_LP_SHIFT               4

/* BRPHY3_GPHY_CORE :: EXP08 :: USE_OLD_LPDET [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_USE_OLD_LPDET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_USE_OLD_LPDET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x8,3)
#define BRPHY3_GPHY_CORE_EXP08_USE_OLD_LPDET_MASK                  0x0008
#define BRPHY3_GPHY_CORE_EXP08_USE_OLD_LPDET_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP08_USE_OLD_LPDET_BITS                  1
#define BRPHY3_GPHY_CORE_EXP08_USE_OLD_LPDET_SHIFT                 3

/* BRPHY3_GPHY_CORE :: EXP08 :: EDGESTATE_REFINE [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x4,2)
#define BRPHY3_GPHY_CORE_EXP08_EDGESTATE_REFINE_MASK               0x0004
#define BRPHY3_GPHY_CORE_EXP08_EDGESTATE_REFINE_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP08_EDGESTATE_REFINE_BITS               1
#define BRPHY3_GPHY_CORE_EXP08_EDGESTATE_REFINE_SHIFT              2

/* BRPHY3_GPHY_CORE :: EXP08 :: REJECT_15MHZ [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_REJECT_15MHZ(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_REJECT_15MHZ(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x2,1)
#define BRPHY3_GPHY_CORE_EXP08_REJECT_15MHZ_MASK                   0x0002
#define BRPHY3_GPHY_CORE_EXP08_REJECT_15MHZ_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP08_REJECT_15MHZ_BITS                   1
#define BRPHY3_GPHY_CORE_EXP08_REJECT_15MHZ_SHIFT                  1

/* BRPHY3_GPHY_CORE :: EXP08 :: REJECT_2MHZ [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP08_REJECT_2MHZ(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP08,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP08_REJECT_2MHZ(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP08,0x1,0)
#define BRPHY3_GPHY_CORE_EXP08_REJECT_2MHZ_MASK                    0x0001
#define BRPHY3_GPHY_CORE_EXP08_REJECT_2MHZ_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP08_REJECT_2MHZ_BITS                    1
#define BRPHY3_GPHY_CORE_EXP08_REJECT_2MHZ_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP09
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP09 :: GIGABIT_POL_INV [15:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP09,0xf000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP09,0xf000,12)
#define BRPHY3_GPHY_CORE_EXP09_GIGABIT_POL_INV_MASK                0xf000
#define BRPHY3_GPHY_CORE_EXP09_GIGABIT_POL_INV_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP09_GIGABIT_POL_INV_BITS                4
#define BRPHY3_GPHY_CORE_EXP09_GIGABIT_POL_INV_SHIFT               12

/* BRPHY3_GPHY_CORE :: EXP09 :: SPARE_REG [11:09] */
#define Wr_BRPHY3_GPHY_CORE_EXP09_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP09,0xe00,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXP09_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP09,0xe00,9)
#define BRPHY3_GPHY_CORE_EXP09_SPARE_REG_MASK                      0x0e00
#define BRPHY3_GPHY_CORE_EXP09_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP09_SPARE_REG_BITS                      3
#define BRPHY3_GPHY_CORE_EXP09_SPARE_REG_SHIFT                     9

/* BRPHY3_GPHY_CORE :: EXP09 :: ALLOW_SWAP [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP09_ALLOW_SWAP(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP09,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP09_ALLOW_SWAP(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP09,0x100,8)
#define BRPHY3_GPHY_CORE_EXP09_ALLOW_SWAP_MASK                     0x0100
#define BRPHY3_GPHY_CORE_EXP09_ALLOW_SWAP_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP09_ALLOW_SWAP_BITS                     1
#define BRPHY3_GPHY_CORE_EXP09_ALLOW_SWAP_SHIFT                    8

/* BRPHY3_GPHY_CORE :: EXP09 :: CH3_SEL [07:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP09_CH3_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP09,0xc0,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP09_CH3_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP09,0xc0,6)
#define BRPHY3_GPHY_CORE_EXP09_CH3_SEL_MASK                        0x00c0
#define BRPHY3_GPHY_CORE_EXP09_CH3_SEL_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP09_CH3_SEL_BITS                        2
#define BRPHY3_GPHY_CORE_EXP09_CH3_SEL_SHIFT                       6

/* BRPHY3_GPHY_CORE :: EXP09 :: CH2_SEL [05:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP09_CH2_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP09,0x30,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP09_CH2_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP09,0x30,4)
#define BRPHY3_GPHY_CORE_EXP09_CH2_SEL_MASK                        0x0030
#define BRPHY3_GPHY_CORE_EXP09_CH2_SEL_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP09_CH2_SEL_BITS                        2
#define BRPHY3_GPHY_CORE_EXP09_CH2_SEL_SHIFT                       4

/* BRPHY3_GPHY_CORE :: EXP09 :: CH1_SEL [03:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP09_CH1_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP09,0xc,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP09_CH1_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP09,0xc,2)
#define BRPHY3_GPHY_CORE_EXP09_CH1_SEL_MASK                        0x000c
#define BRPHY3_GPHY_CORE_EXP09_CH1_SEL_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP09_CH1_SEL_BITS                        2
#define BRPHY3_GPHY_CORE_EXP09_CH1_SEL_SHIFT                       2

/* BRPHY3_GPHY_CORE :: EXP09 :: CH0_SEL [01:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP09_CH0_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP09,0x3,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP09_CH0_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP09,0x3,0)
#define BRPHY3_GPHY_CORE_EXP09_CH0_SEL_MASK                        0x0003
#define BRPHY3_GPHY_CORE_EXP09_CH0_SEL_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP09_CH0_SEL_BITS                        2
#define BRPHY3_GPHY_CORE_EXP09_CH0_SEL_SHIFT                       0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP0A
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP0A :: reserved0 [15:13] */
#define BRPHY3_GPHY_CORE_EXP0A_RESERVED0_MASK                      0xe000
#define BRPHY3_GPHY_CORE_EXP0A_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP0A_RESERVED0_BITS                      3
#define BRPHY3_GPHY_CORE_EXP0A_RESERVED0_SHIFT                     13

/* BRPHY3_GPHY_CORE :: EXP0A :: SYNC_IN_EN [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP0A_SYNC_IN_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP0A_SYNC_IN_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP0A_SYNC_IN_EN_MASK                     0x1000
#define BRPHY3_GPHY_CORE_EXP0A_SYNC_IN_EN_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP0A_SYNC_IN_EN_BITS                     1
#define BRPHY3_GPHY_CORE_EXP0A_SYNC_IN_EN_SHIFT                    12

/* BRPHY3_GPHY_CORE :: EXP0A :: CHANNEL_KILL [11:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP0A_CHANNEL_KILL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP0A,0xf00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP0A_CHANNEL_KILL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP0A,0xf00,8)
#define BRPHY3_GPHY_CORE_EXP0A_CHANNEL_KILL_MASK                   0x0f00
#define BRPHY3_GPHY_CORE_EXP0A_CHANNEL_KILL_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP0A_CHANNEL_KILL_BITS                   4
#define BRPHY3_GPHY_CORE_EXP0A_CHANNEL_KILL_SHIFT                  8

/* BRPHY3_GPHY_CORE :: EXP0A :: SYNC_KILL [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXP0A_SYNC_KILL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXP0A_SYNC_KILL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x80,7)
#define BRPHY3_GPHY_CORE_EXP0A_SYNC_KILL_MASK                      0x0080
#define BRPHY3_GPHY_CORE_EXP0A_SYNC_KILL_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP0A_SYNC_KILL_BITS                      1
#define BRPHY3_GPHY_CORE_EXP0A_SYNC_KILL_SHIFT                     7

/* BRPHY3_GPHY_CORE :: EXP0A :: BYPASS_ENE [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP0A_BYPASS_ENE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP0A_BYPASS_ENE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x40,6)
#define BRPHY3_GPHY_CORE_EXP0A_BYPASS_ENE_MASK                     0x0040
#define BRPHY3_GPHY_CORE_EXP0A_BYPASS_ENE_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP0A_BYPASS_ENE_BITS                     1
#define BRPHY3_GPHY_CORE_EXP0A_BYPASS_ENE_SHIFT                    6

/* BRPHY3_GPHY_CORE :: EXP0A :: PAT_DURATION [05:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP0A_PAT_DURATION(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x30,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP0A_PAT_DURATION(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x30,4)
#define BRPHY3_GPHY_CORE_EXP0A_PAT_DURATION_MASK                   0x0030
#define BRPHY3_GPHY_CORE_EXP0A_PAT_DURATION_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP0A_PAT_DURATION_BITS                   2
#define BRPHY3_GPHY_CORE_EXP0A_PAT_DURATION_SHIFT                  4

/* BRPHY3_GPHY_CORE :: EXP0A :: PAT_SEL [03:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP0A_PAT_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP0A,0xe,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP0A_PAT_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP0A,0xe,1)
#define BRPHY3_GPHY_CORE_EXP0A_PAT_SEL_MASK                        0x000e
#define BRPHY3_GPHY_CORE_EXP0A_PAT_SEL_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP0A_PAT_SEL_BITS                        3
#define BRPHY3_GPHY_CORE_EXP0A_PAT_SEL_SHIFT                       1

/* BRPHY3_GPHY_CORE :: EXP0A :: TEMPLATE_EN [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP0A_TEMPLATE_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP0A_TEMPLATE_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP0A,0x1,0)
#define BRPHY3_GPHY_CORE_EXP0A_TEMPLATE_EN_MASK                    0x0001
#define BRPHY3_GPHY_CORE_EXP0A_TEMPLATE_EN_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP0A_TEMPLATE_EN_BITS                    1
#define BRPHY3_GPHY_CORE_EXP0A_TEMPLATE_EN_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP0B
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP0B :: EXT_STATUS [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP0B_EXT_STATUS(x) WriteReg16(BRPHY3_GPHY_CORE_EXP0B,x)
#define Rd_BRPHY3_GPHY_CORE_EXP0B_EXT_STATUS(x) ReadReg16(BRPHY3_GPHY_CORE_EXP0B)
#define BRPHY3_GPHY_CORE_EXP0B_EXT_STATUS_MASK                     0xffff
#define BRPHY3_GPHY_CORE_EXP0B_EXT_STATUS_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP0B_EXT_STATUS_BITS                     16
#define BRPHY3_GPHY_CORE_EXP0B_EXT_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP0C
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP0C :: SPARE_REG [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP0C_SPARE_REG(x) WriteReg16(BRPHY3_GPHY_CORE_EXP0C,x)
#define Rd_BRPHY3_GPHY_CORE_EXP0C_SPARE_REG(x) ReadReg16(BRPHY3_GPHY_CORE_EXP0C)
#define BRPHY3_GPHY_CORE_EXP0C_SPARE_REG_MASK                      0xffff
#define BRPHY3_GPHY_CORE_EXP0C_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP0C_SPARE_REG_BITS                      16
#define BRPHY3_GPHY_CORE_EXP0C_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP30
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP30 :: reserved0 [15:05] */
#define BRPHY3_GPHY_CORE_EXP30_RESERVED0_MASK                      0xffe0
#define BRPHY3_GPHY_CORE_EXP30_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP30_RESERVED0_BITS                      11
#define BRPHY3_GPHY_CORE_EXP30_RESERVED0_SHIFT                     5

/* BRPHY3_GPHY_CORE :: EXP30 :: DEADMAN_RESET [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP30_DEADMAN_RESET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP30,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP30_DEADMAN_RESET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP30,0x10,4)
#define BRPHY3_GPHY_CORE_EXP30_DEADMAN_RESET_MASK                  0x0010
#define BRPHY3_GPHY_CORE_EXP30_DEADMAN_RESET_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP30_DEADMAN_RESET_BITS                  1
#define BRPHY3_GPHY_CORE_EXP30_DEADMAN_RESET_SHIFT                 4

/* BRPHY3_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_128_TO_255 [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP30,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP30,0x8,3)
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_MASK       0x0008
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_ALIGN      0
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_BITS       1
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_SHIFT      3

/* BRPHY3_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_64_TO_127 [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP30,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP30,0x4,2)
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_MASK        0x0004
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_ALIGN       0
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_BITS        1
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_SHIFT       2

/* BRPHY3_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_32_TO_63 [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP30,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP30,0x2,1)
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_MASK         0x0002
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_ALIGN        0
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_BITS         1
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_SHIFT        1

/* BRPHY3_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_0_TO_31 [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP30,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP30,0x1,0)
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_MASK          0x0001
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_ALIGN         0
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_BITS          1
#define BRPHY3_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_SHIFT         0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP31
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP31 :: reserved0 [15:08] */
#define BRPHY3_GPHY_CORE_EXP31_RESERVED0_MASK                      0xff00
#define BRPHY3_GPHY_CORE_EXP31_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP31_RESERVED0_BITS                      8
#define BRPHY3_GPHY_CORE_EXP31_RESERVED0_SHIFT                     8

/* BRPHY3_GPHY_CORE :: EXP31 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP31_LATE_COL_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP31,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP31_LATE_COL_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP31,0xff,0)
#define BRPHY3_GPHY_CORE_EXP31_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY3_GPHY_CORE_EXP31_LATE_COL_CNTR_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP31_LATE_COL_CNTR_BITS                  8
#define BRPHY3_GPHY_CORE_EXP31_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP32
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP32 :: reserved0 [15:08] */
#define BRPHY3_GPHY_CORE_EXP32_RESERVED0_MASK                      0xff00
#define BRPHY3_GPHY_CORE_EXP32_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP32_RESERVED0_BITS                      8
#define BRPHY3_GPHY_CORE_EXP32_RESERVED0_SHIFT                     8

/* BRPHY3_GPHY_CORE :: EXP32 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP32_LATE_COL_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP32,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP32_LATE_COL_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP32,0xff,0)
#define BRPHY3_GPHY_CORE_EXP32_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY3_GPHY_CORE_EXP32_LATE_COL_CNTR_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP32_LATE_COL_CNTR_BITS                  8
#define BRPHY3_GPHY_CORE_EXP32_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP33
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP33 :: reserved0 [15:08] */
#define BRPHY3_GPHY_CORE_EXP33_RESERVED0_MASK                      0xff00
#define BRPHY3_GPHY_CORE_EXP33_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP33_RESERVED0_BITS                      8
#define BRPHY3_GPHY_CORE_EXP33_RESERVED0_SHIFT                     8

/* BRPHY3_GPHY_CORE :: EXP33 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP33_LATE_COL_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP33,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP33_LATE_COL_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP33,0xff,0)
#define BRPHY3_GPHY_CORE_EXP33_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY3_GPHY_CORE_EXP33_LATE_COL_CNTR_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP33_LATE_COL_CNTR_BITS                  8
#define BRPHY3_GPHY_CORE_EXP33_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP34
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP34 :: reserved0 [15:08] */
#define BRPHY3_GPHY_CORE_EXP34_RESERVED0_MASK                      0xff00
#define BRPHY3_GPHY_CORE_EXP34_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP34_RESERVED0_BITS                      8
#define BRPHY3_GPHY_CORE_EXP34_RESERVED0_SHIFT                     8

/* BRPHY3_GPHY_CORE :: EXP34 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP34_LATE_COL_CNTR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP34,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP34_LATE_COL_CNTR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP34,0xff,0)
#define BRPHY3_GPHY_CORE_EXP34_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY3_GPHY_CORE_EXP34_LATE_COL_CNTR_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP34_LATE_COL_CNTR_BITS                  8
#define BRPHY3_GPHY_CORE_EXP34_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP35
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP35 :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_EXP35_RESERVED0_MASK                      0xf000
#define BRPHY3_GPHY_CORE_EXP35_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP35_RESERVED0_BITS                      4
#define BRPHY3_GPHY_CORE_EXP35_RESERVED0_SHIFT                     12

/* BRPHY3_GPHY_CORE :: EXP35 :: MII_INTERFACE_MODES [11:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP35,0xf00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP35,0xf00,8)
#define BRPHY3_GPHY_CORE_EXP35_MII_INTERFACE_MODES_MASK            0x0f00
#define BRPHY3_GPHY_CORE_EXP35_MII_INTERFACE_MODES_ALIGN           0
#define BRPHY3_GPHY_CORE_EXP35_MII_INTERFACE_MODES_BITS            4
#define BRPHY3_GPHY_CORE_EXP35_MII_INTERFACE_MODES_SHIFT           8

/* BRPHY3_GPHY_CORE :: EXP35 :: LATE_COL_CNTR_THD [07:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP35,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP35,0xff,0)
#define BRPHY3_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_MASK              0x00ff
#define BRPHY3_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_BITS              8
#define BRPHY3_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_SHIFT             0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP36
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP36 :: PPM_DET_PWRDN [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP36,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP36,0x8000,15)
#define BRPHY3_GPHY_CORE_EXP36_PPM_DET_PWRDN_MASK                  0x8000
#define BRPHY3_GPHY_CORE_EXP36_PPM_DET_PWRDN_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP36_PPM_DET_PWRDN_BITS                  1
#define BRPHY3_GPHY_CORE_EXP36_PPM_DET_PWRDN_SHIFT                 15

/* BRPHY3_GPHY_CORE :: EXP36 :: PPM_DET_TEST [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXP36_PPM_DET_TEST(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP36,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXP36_PPM_DET_TEST(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP36,0x4000,14)
#define BRPHY3_GPHY_CORE_EXP36_PPM_DET_TEST_MASK                   0x4000
#define BRPHY3_GPHY_CORE_EXP36_PPM_DET_TEST_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP36_PPM_DET_TEST_BITS                   1
#define BRPHY3_GPHY_CORE_EXP36_PPM_DET_TEST_SHIFT                  14

/* BRPHY3_GPHY_CORE :: EXP36 :: reserved0 [13:10] */
#define BRPHY3_GPHY_CORE_EXP36_RESERVED0_MASK                      0x3c00
#define BRPHY3_GPHY_CORE_EXP36_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP36_RESERVED0_BITS                      4
#define BRPHY3_GPHY_CORE_EXP36_RESERVED0_SHIFT                     10

/* BRPHY3_GPHY_CORE :: EXP36 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP36_PPM_OFFSET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP36,0x3ff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP36_PPM_OFFSET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP36,0x3ff,0)
#define BRPHY3_GPHY_CORE_EXP36_PPM_OFFSET_MASK                     0x03ff
#define BRPHY3_GPHY_CORE_EXP36_PPM_OFFSET_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP36_PPM_OFFSET_BITS                     10
#define BRPHY3_GPHY_CORE_EXP36_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP37
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP37 :: reserved0 [15:10] */
#define BRPHY3_GPHY_CORE_EXP37_RESERVED0_MASK                      0xfc00
#define BRPHY3_GPHY_CORE_EXP37_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP37_RESERVED0_BITS                      6
#define BRPHY3_GPHY_CORE_EXP37_RESERVED0_SHIFT                     10

/* BRPHY3_GPHY_CORE :: EXP37 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP37_PPM_OFFSET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP37,0x3ff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP37_PPM_OFFSET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP37,0x3ff,0)
#define BRPHY3_GPHY_CORE_EXP37_PPM_OFFSET_MASK                     0x03ff
#define BRPHY3_GPHY_CORE_EXP37_PPM_OFFSET_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP37_PPM_OFFSET_BITS                     10
#define BRPHY3_GPHY_CORE_EXP37_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP38
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP38 :: IP_PHONE_DET_CHANGE [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP38,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP38,0x8000,15)
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_MASK            0x8000
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_ALIGN           0
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_BITS            1
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_SHIFT           15

/* BRPHY3_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH_CHANGE [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP38,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP38,0x4000,14)
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_MASK       0x4000
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_ALIGN      0
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_BITS       1
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_SHIFT      14

/* BRPHY3_GPHY_CORE :: EXP38 :: IP_PHONE_FLP_BURST_TX [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP38,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP38,0x2000,13)
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_MASK          0x2000
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_ALIGN         0
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_BITS          1
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_SHIFT         13

/* BRPHY3_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP38,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP38,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_MASK              0x1000
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_BITS              1
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_SHIFT             12

/* BRPHY3_GPHY_CORE :: EXP38 :: IP_PHONE_DET [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP38,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP38,0x800,11)
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_MASK                   0x0800
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_BITS                   1
#define BRPHY3_GPHY_CORE_EXP38_IP_PHONE_DET_SHIFT                  11

/* BRPHY3_GPHY_CORE :: EXP38 :: NO_RESPSONSE [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXP38_NO_RESPSONSE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP38,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXP38_NO_RESPSONSE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP38,0x400,10)
#define BRPHY3_GPHY_CORE_EXP38_NO_RESPSONSE_MASK                   0x0400
#define BRPHY3_GPHY_CORE_EXP38_NO_RESPSONSE_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP38_NO_RESPSONSE_BITS                   1
#define BRPHY3_GPHY_CORE_EXP38_NO_RESPSONSE_SHIFT                  10

/* BRPHY3_GPHY_CORE :: EXP38 :: TOTAL_RT_DLY [09:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP38,0x3ff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP38,0x3ff,0)
#define BRPHY3_GPHY_CORE_EXP38_TOTAL_RT_DLY_MASK                   0x03ff
#define BRPHY3_GPHY_CORE_EXP38_TOTAL_RT_DLY_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP38_TOTAL_RT_DLY_BITS                   10
#define BRPHY3_GPHY_CORE_EXP38_TOTAL_RT_DLY_SHIFT                  0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP42
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP42 :: SERDES_LINK [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_SERDES_LINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_SERDES_LINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x8000,15)
#define BRPHY3_GPHY_CORE_EXP42_SERDES_LINK_MASK                    0x8000
#define BRPHY3_GPHY_CORE_EXP42_SERDES_LINK_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP42_SERDES_LINK_BITS                    1
#define BRPHY3_GPHY_CORE_EXP42_SERDES_LINK_SHIFT                   15

/* BRPHY3_GPHY_CORE :: EXP42 :: SERDES_SPEED [14:13] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_SERDES_SPEED(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x6000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_SERDES_SPEED(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x6000,13)
#define BRPHY3_GPHY_CORE_EXP42_SERDES_SPEED_MASK                   0x6000
#define BRPHY3_GPHY_CORE_EXP42_SERDES_SPEED_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP42_SERDES_SPEED_BITS                   2
#define BRPHY3_GPHY_CORE_EXP42_SERDES_SPEED_SHIFT                  13

/* BRPHY3_GPHY_CORE :: EXP42 :: SERDES_DUPLEX [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_SERDES_DUPLEX(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_SERDES_DUPLEX(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP42_SERDES_DUPLEX_MASK                  0x1000
#define BRPHY3_GPHY_CORE_EXP42_SERDES_DUPLEX_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP42_SERDES_DUPLEX_BITS                  1
#define BRPHY3_GPHY_CORE_EXP42_SERDES_DUPLEX_SHIFT                 12

/* BRPHY3_GPHY_CORE :: EXP42 :: COPPER_LINK [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_COPPER_LINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_COPPER_LINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x800,11)
#define BRPHY3_GPHY_CORE_EXP42_COPPER_LINK_MASK                    0x0800
#define BRPHY3_GPHY_CORE_EXP42_COPPER_LINK_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP42_COPPER_LINK_BITS                    1
#define BRPHY3_GPHY_CORE_EXP42_COPPER_LINK_SHIFT                   11

/* BRPHY3_GPHY_CORE :: EXP42 :: COPPER_SPEED [10:09] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_COPPER_SPEED(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x600,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_COPPER_SPEED(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x600,9)
#define BRPHY3_GPHY_CORE_EXP42_COPPER_SPEED_MASK                   0x0600
#define BRPHY3_GPHY_CORE_EXP42_COPPER_SPEED_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP42_COPPER_SPEED_BITS                   2
#define BRPHY3_GPHY_CORE_EXP42_COPPER_SPEED_SHIFT                  9

/* BRPHY3_GPHY_CORE :: EXP42 :: COPPER_DUPLEX [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_COPPER_DUPLEX(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_COPPER_DUPLEX(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x100,8)
#define BRPHY3_GPHY_CORE_EXP42_COPPER_DUPLEX_MASK                  0x0100
#define BRPHY3_GPHY_CORE_EXP42_COPPER_DUPLEX_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP42_COPPER_DUPLEX_BITS                  1
#define BRPHY3_GPHY_CORE_EXP42_COPPER_DUPLEX_SHIFT                 8

/* BRPHY3_GPHY_CORE :: EXP42 :: COPPER_ENERGY_DETECT [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x80,7)
#define BRPHY3_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_MASK           0x0080
#define BRPHY3_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_ALIGN          0
#define BRPHY3_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_BITS           1
#define BRPHY3_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_SHIFT          7

/* BRPHY3_GPHY_CORE :: EXP42 :: FIBER_SIGNAL_DETECT [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x40,6)
#define BRPHY3_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_MASK            0x0040
#define BRPHY3_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_ALIGN           0
#define BRPHY3_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_BITS            1
#define BRPHY3_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_SHIFT           6

/* BRPHY3_GPHY_CORE :: EXP42 :: SYNC_STATUS [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_SYNC_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_SYNC_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x20,5)
#define BRPHY3_GPHY_CORE_EXP42_SYNC_STATUS_MASK                    0x0020
#define BRPHY3_GPHY_CORE_EXP42_SYNC_STATUS_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP42_SYNC_STATUS_BITS                    1
#define BRPHY3_GPHY_CORE_EXP42_SYNC_STATUS_SHIFT                   5

/* BRPHY3_GPHY_CORE :: EXP42 :: OPERATING_MODE_STATUS [04:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP42,0x1f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP42,0x1f,0)
#define BRPHY3_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_MASK          0x001f
#define BRPHY3_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_ALIGN         0
#define BRPHY3_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_BITS          5
#define BRPHY3_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_SHIFT         0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP5F
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP5F :: PLL_TCLK_OFFSET [15:10] */
#define Wr_BRPHY3_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP5F,0xfc00,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP5F,0xfc00,10)
#define BRPHY3_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_MASK                0xfc00
#define BRPHY3_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_BITS                6
#define BRPHY3_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_SHIFT               10

/* BRPHY3_GPHY_CORE :: EXP5F :: PLL_RCLK_OFFSET [09:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP5F,0x3f0,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP5F,0x3f0,4)
#define BRPHY3_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_MASK                0x03f0
#define BRPHY3_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_BITS                6
#define BRPHY3_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_SHIFT               4

/* BRPHY3_GPHY_CORE :: EXP5F :: PLLTEST_CNT [03:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP5F_PLLTEST_CNT(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP5F,0xc,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP5F_PLLTEST_CNT(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP5F,0xc,2)
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_CNT_MASK                    0x000c
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_CNT_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_CNT_BITS                    2
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_CNT_SHIFT                   2

/* BRPHY3_GPHY_CORE :: EXP5F :: PLLTEST [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP5F_PLLTEST(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP5F,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP5F_PLLTEST(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP5F,0x2,1)
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_MASK                        0x0002
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_BITS                        1
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_SHIFT                       1

/* BRPHY3_GPHY_CORE :: EXP5F :: PLLTEST_EN [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP5F_PLLTEST_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP5F,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP5F_PLLTEST_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP5F,0x1,0)
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_EN_MASK                     0x0001
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_EN_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_EN_BITS                     1
#define BRPHY3_GPHY_CORE_EXP5F_PLLTEST_EN_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP70
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP70 :: reserved0 [15:01] */
#define BRPHY3_GPHY_CORE_EXP70_RESERVED0_MASK                      0xfffe
#define BRPHY3_GPHY_CORE_EXP70_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP70_RESERVED0_BITS                      15
#define BRPHY3_GPHY_CORE_EXP70_RESERVED0_SHIFT                     1

/* BRPHY3_GPHY_CORE :: EXP70 :: SOFT_RESET [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP70_SOFT_RESET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP70,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP70_SOFT_RESET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP70,0x1,0)
#define BRPHY3_GPHY_CORE_EXP70_SOFT_RESET_MASK                     0x0001
#define BRPHY3_GPHY_CORE_EXP70_SOFT_RESET_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP70_SOFT_RESET_BITS                     1
#define BRPHY3_GPHY_CORE_EXP70_SOFT_RESET_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP71
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP71 :: reserved0 [15:14] */
#define BRPHY3_GPHY_CORE_EXP71_RESERVED0_MASK                      0xc000
#define BRPHY3_GPHY_CORE_EXP71_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP71_RESERVED0_BITS                      2
#define BRPHY3_GPHY_CORE_EXP71_RESERVED0_SHIFT                     14

/* BRPHY3_GPHY_CORE :: EXP71 :: SERIAL_LED_EN [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP71,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP71,0x2000,13)
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_EN_MASK                  0x2000
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_EN_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_EN_BITS                  1
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_EN_SHIFT                 13

/* BRPHY3_GPHY_CORE :: EXP71 :: LOW_COST_LED_EN [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP71,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP71,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP71_LOW_COST_LED_EN_MASK                0x1000
#define BRPHY3_GPHY_CORE_EXP71_LOW_COST_LED_EN_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP71_LOW_COST_LED_EN_BITS                1
#define BRPHY3_GPHY_CORE_EXP71_LOW_COST_LED_EN_SHIFT               12

/* BRPHY3_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_6 [11:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP71,0xf00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP71,0xf00,8)
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_MASK               0x0f00
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_BITS               4
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_SHIFT              8

/* BRPHY3_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_5 [07:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP71,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP71,0xf0,4)
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_MASK               0x00f0
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_BITS               4
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_SHIFT              4

/* BRPHY3_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_4 [03:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP71,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP71,0xf,0)
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_MASK               0x000f
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_BITS               4
#define BRPHY3_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP72
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP72 :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_EXP72_RESERVED0_MASK                      0xf000
#define BRPHY3_GPHY_CORE_EXP72_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP72_RESERVED0_BITS                      4
#define BRPHY3_GPHY_CORE_EXP72_RESERVED0_SHIFT                     12

/* BRPHY3_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_3 [11:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP72,0xf00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP72,0xf00,8)
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_MASK               0x0f00
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_BITS               4
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_SHIFT              8

/* BRPHY3_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_2 [07:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP72,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP72,0xf0,4)
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_MASK               0x00f0
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_BITS               4
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_SHIFT              4

/* BRPHY3_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_1 [03:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP72,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP72,0xf,0)
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_MASK               0x000f
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_BITS               4
#define BRPHY3_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP73
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP73 :: reserved0 [15:08] */
#define BRPHY3_GPHY_CORE_EXP73_RESERVED0_MASK                      0xff00
#define BRPHY3_GPHY_CORE_EXP73_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP73_RESERVED0_BITS                      8
#define BRPHY3_GPHY_CORE_EXP73_RESERVED0_SHIFT                     8

/* BRPHY3_GPHY_CORE :: EXP73 :: LED_6_TO_1_COPPER [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP73,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP73,0x80,7)
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_MASK              0x0080
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_BITS              1
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_SHIFT             7

/* BRPHY3_GPHY_CORE :: EXP73 :: LED_5_TO_1_COPPER [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP73,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP73,0x40,6)
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_MASK              0x0040
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_BITS              1
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_SHIFT             6

/* BRPHY3_GPHY_CORE :: EXP73 :: LED_6_TO_0_COPPER [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP73,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP73,0x20,5)
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_MASK              0x0020
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_BITS              1
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_SHIFT             5

/* BRPHY3_GPHY_CORE :: EXP73 :: LED_5_TO_0_COPPER [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP73,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP73,0x10,4)
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_MASK              0x0010
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_ALIGN             0
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_BITS              1
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_SHIFT             4

/* BRPHY3_GPHY_CORE :: EXP73 :: LED_6_TO_1_FIBER [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP73,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP73,0x8,3)
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_MASK               0x0008
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_BITS               1
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_SHIFT              3

/* BRPHY3_GPHY_CORE :: EXP73 :: LED_5_TO_1_FIBER [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP73,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP73,0x4,2)
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_MASK               0x0004
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_BITS               1
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_SHIFT              2

/* BRPHY3_GPHY_CORE :: EXP73 :: LED_6_TO_0_FIBER [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP73,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP73,0x2,1)
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_MASK               0x0002
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_BITS               1
#define BRPHY3_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_SHIFT              1

/* BRPHY3_GPHY_CORE :: EXP73 :: LED_5_TO_0_FIBER [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP73,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP73,0x1,0)
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_MASK               0x0001
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_BITS               1
#define BRPHY3_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP74
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP74 :: LED4_CM_SW_VAL [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP74,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP74,0x8000,15)
#define BRPHY3_GPHY_CORE_EXP74_LED4_CM_SW_VAL_MASK                 0x8000
#define BRPHY3_GPHY_CORE_EXP74_LED4_CM_SW_VAL_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP74_LED4_CM_SW_VAL_BITS                 1
#define BRPHY3_GPHY_CORE_EXP74_LED4_CM_SW_VAL_SHIFT                15

/* BRPHY3_GPHY_CORE :: EXP74 :: LED4_CM_CTRL [14:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP74_LED4_CM_CTRL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP74,0x7000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP74_LED4_CM_CTRL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP74,0x7000,12)
#define BRPHY3_GPHY_CORE_EXP74_LED4_CM_CTRL_MASK                   0x7000
#define BRPHY3_GPHY_CORE_EXP74_LED4_CM_CTRL_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP74_LED4_CM_CTRL_BITS                   3
#define BRPHY3_GPHY_CORE_EXP74_LED4_CM_CTRL_SHIFT                  12

/* BRPHY3_GPHY_CORE :: EXP74 :: LED3_CM_SW_VAL [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP74,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP74,0x800,11)
#define BRPHY3_GPHY_CORE_EXP74_LED3_CM_SW_VAL_MASK                 0x0800
#define BRPHY3_GPHY_CORE_EXP74_LED3_CM_SW_VAL_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP74_LED3_CM_SW_VAL_BITS                 1
#define BRPHY3_GPHY_CORE_EXP74_LED3_CM_SW_VAL_SHIFT                11

/* BRPHY3_GPHY_CORE :: EXP74 :: LED3_CM_CTRL [10:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP74_LED3_CM_CTRL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP74,0x700,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP74_LED3_CM_CTRL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP74,0x700,8)
#define BRPHY3_GPHY_CORE_EXP74_LED3_CM_CTRL_MASK                   0x0700
#define BRPHY3_GPHY_CORE_EXP74_LED3_CM_CTRL_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP74_LED3_CM_CTRL_BITS                   3
#define BRPHY3_GPHY_CORE_EXP74_LED3_CM_CTRL_SHIFT                  8

/* BRPHY3_GPHY_CORE :: EXP74 :: LED2_CM_SW_VAL [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP74,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP74,0x80,7)
#define BRPHY3_GPHY_CORE_EXP74_LED2_CM_SW_VAL_MASK                 0x0080
#define BRPHY3_GPHY_CORE_EXP74_LED2_CM_SW_VAL_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP74_LED2_CM_SW_VAL_BITS                 1
#define BRPHY3_GPHY_CORE_EXP74_LED2_CM_SW_VAL_SHIFT                7

/* BRPHY3_GPHY_CORE :: EXP74 :: LED2_CM_CTRL [06:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP74_LED2_CM_CTRL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP74,0x70,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP74_LED2_CM_CTRL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP74,0x70,4)
#define BRPHY3_GPHY_CORE_EXP74_LED2_CM_CTRL_MASK                   0x0070
#define BRPHY3_GPHY_CORE_EXP74_LED2_CM_CTRL_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP74_LED2_CM_CTRL_BITS                   3
#define BRPHY3_GPHY_CORE_EXP74_LED2_CM_CTRL_SHIFT                  4

/* BRPHY3_GPHY_CORE :: EXP74 :: LED1_CM_SW_VAL [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP74,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP74,0x8,3)
#define BRPHY3_GPHY_CORE_EXP74_LED1_CM_SW_VAL_MASK                 0x0008
#define BRPHY3_GPHY_CORE_EXP74_LED1_CM_SW_VAL_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP74_LED1_CM_SW_VAL_BITS                 1
#define BRPHY3_GPHY_CORE_EXP74_LED1_CM_SW_VAL_SHIFT                3

/* BRPHY3_GPHY_CORE :: EXP74 :: LED1_CM_CTRL [02:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP74_LED1_CM_CTRL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP74,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP74_LED1_CM_CTRL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP74,0x7,0)
#define BRPHY3_GPHY_CORE_EXP74_LED1_CM_CTRL_MASK                   0x0007
#define BRPHY3_GPHY_CORE_EXP74_LED1_CM_CTRL_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXP74_LED1_CM_CTRL_BITS                   3
#define BRPHY3_GPHY_CORE_EXP74_LED1_CM_CTRL_SHIFT                  0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP75
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP75 :: reserved0 [15:10] */
#define BRPHY3_GPHY_CORE_EXP75_RESERVED0_MASK                      0xfc00
#define BRPHY3_GPHY_CORE_EXP75_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP75_RESERVED0_BITS                      6
#define BRPHY3_GPHY_CORE_EXP75_RESERVED0_SHIFT                     10

/* BRPHY3_GPHY_CORE :: EXP75 :: CED_LED_ERR_MASK [09:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP75,0x3ff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP75,0x3ff,0)
#define BRPHY3_GPHY_CORE_EXP75_CED_LED_ERR_MASK_MASK               0x03ff
#define BRPHY3_GPHY_CORE_EXP75_CED_LED_ERR_MASK_ALIGN              0
#define BRPHY3_GPHY_CORE_EXP75_CED_LED_ERR_MASK_BITS               10
#define BRPHY3_GPHY_CORE_EXP75_CED_LED_ERR_MASK_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP78
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP78 :: DAC_ANA_TEST_EN [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP78,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP78,0x8000,15)
#define BRPHY3_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_MASK                0x8000
#define BRPHY3_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_BITS                1
#define BRPHY3_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_SHIFT               15

/* BRPHY3_GPHY_CORE :: EXP78 :: BR_TXPR_EN [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXP78_BR_TXPR_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP78,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXP78_BR_TXPR_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP78,0x4000,14)
#define BRPHY3_GPHY_CORE_EXP78_BR_TXPR_EN_MASK                     0x4000
#define BRPHY3_GPHY_CORE_EXP78_BR_TXPR_EN_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP78_BR_TXPR_EN_BITS                     1
#define BRPHY3_GPHY_CORE_EXP78_BR_TXPR_EN_SHIFT                    14

/* BRPHY3_GPHY_CORE :: EXP78 :: BR_IRP_EN [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXP78_BR_IRP_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP78,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXP78_BR_IRP_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP78,0x2000,13)
#define BRPHY3_GPHY_CORE_EXP78_BR_IRP_EN_MASK                      0x2000
#define BRPHY3_GPHY_CORE_EXP78_BR_IRP_EN_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP78_BR_IRP_EN_BITS                      1
#define BRPHY3_GPHY_CORE_EXP78_BR_IRP_EN_SHIFT                     13

/* BRPHY3_GPHY_CORE :: EXP78 :: PTE_BYPASS_EN [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP78,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP78,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP78_PTE_BYPASS_EN_MASK                  0x1000
#define BRPHY3_GPHY_CORE_EXP78_PTE_BYPASS_EN_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP78_PTE_BYPASS_EN_BITS                  1
#define BRPHY3_GPHY_CORE_EXP78_PTE_BYPASS_EN_SHIFT                 12

/* BRPHY3_GPHY_CORE :: EXP78 :: PTE_DISTORT [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXP78_PTE_DISTORT(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP78,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXP78_PTE_DISTORT(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP78,0x800,11)
#define BRPHY3_GPHY_CORE_EXP78_PTE_DISTORT_MASK                    0x0800
#define BRPHY3_GPHY_CORE_EXP78_PTE_DISTORT_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP78_PTE_DISTORT_BITS                    1
#define BRPHY3_GPHY_CORE_EXP78_PTE_DISTORT_SHIFT                   11

/* BRPHY3_GPHY_CORE :: EXP78 :: LP_SEL [10:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP78_LP_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP78,0x700,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP78_LP_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP78,0x700,8)
#define BRPHY3_GPHY_CORE_EXP78_LP_SEL_MASK                         0x0700
#define BRPHY3_GPHY_CORE_EXP78_LP_SEL_ALIGN                        0
#define BRPHY3_GPHY_CORE_EXP78_LP_SEL_BITS                         3
#define BRPHY3_GPHY_CORE_EXP78_LP_SEL_SHIFT                        8

/* BRPHY3_GPHY_CORE :: EXP78 :: HP_PGA_BYPASS [07:04] */
#define Wr_BRPHY3_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP78,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP78,0xf0,4)
#define BRPHY3_GPHY_CORE_EXP78_HP_PGA_BYPASS_MASK                  0x00f0
#define BRPHY3_GPHY_CORE_EXP78_HP_PGA_BYPASS_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP78_HP_PGA_BYPASS_BITS                  4
#define BRPHY3_GPHY_CORE_EXP78_HP_PGA_BYPASS_SHIFT                 4

/* BRPHY3_GPHY_CORE :: EXP78 :: TDR_GAIN [03:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP78_TDR_GAIN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP78,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP78_TDR_GAIN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP78,0xf,0)
#define BRPHY3_GPHY_CORE_EXP78_TDR_GAIN_MASK                       0x000f
#define BRPHY3_GPHY_CORE_EXP78_TDR_GAIN_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP78_TDR_GAIN_BITS                       4
#define BRPHY3_GPHY_CORE_EXP78_TDR_GAIN_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP7B
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP7B :: I2C_CMD [15:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP7B_I2C_CMD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP7B,0xf000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP7B_I2C_CMD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP7B,0xf000,12)
#define BRPHY3_GPHY_CORE_EXP7B_I2C_CMD_MASK                        0xf000
#define BRPHY3_GPHY_CORE_EXP7B_I2C_CMD_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP7B_I2C_CMD_BITS                        4
#define BRPHY3_GPHY_CORE_EXP7B_I2C_CMD_SHIFT                       12

/* BRPHY3_GPHY_CORE :: EXP7B :: I2C_CTL [11:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP7B_I2C_CTL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP7B,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP7B_I2C_CTL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP7B,0xfff,0)
#define BRPHY3_GPHY_CORE_EXP7B_I2C_CTL_MASK                        0x0fff
#define BRPHY3_GPHY_CORE_EXP7B_I2C_CTL_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP7B_I2C_CTL_BITS                        12
#define BRPHY3_GPHY_CORE_EXP7B_I2C_CTL_SHIFT                       0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP7C
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP7C :: I2C_STATUS [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP7C_I2C_STATUS(x) WriteReg16(BRPHY3_GPHY_CORE_EXP7C,x)
#define Rd_BRPHY3_GPHY_CORE_EXP7C_I2C_STATUS(x) ReadReg16(BRPHY3_GPHY_CORE_EXP7C)
#define BRPHY3_GPHY_CORE_EXP7C_I2C_STATUS_MASK                     0xffff
#define BRPHY3_GPHY_CORE_EXP7C_I2C_STATUS_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP7C_I2C_STATUS_BITS                     16
#define BRPHY3_GPHY_CORE_EXP7C_I2C_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP7F
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP7F :: reserved0 [15:13] */
#define BRPHY3_GPHY_CORE_EXP7F_RESERVED0_MASK                      0xe000
#define BRPHY3_GPHY_CORE_EXP7F_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP7F_RESERVED0_BITS                      3
#define BRPHY3_GPHY_CORE_EXP7F_RESERVED0_SHIFT                     13

/* BRPHY3_GPHY_CORE :: EXP7F :: BR_PSD_PIN_DISABLE [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x1000,12)
#define BRPHY3_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_MASK             0x1000
#define BRPHY3_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_ALIGN            0
#define BRPHY3_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_BITS             1
#define BRPHY3_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_SHIFT            12

/* BRPHY3_GPHY_CORE :: EXP7F :: BR_PSD_OFF [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXP7F_BR_PSD_OFF(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXP7F_BR_PSD_OFF(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x800,11)
#define BRPHY3_GPHY_CORE_EXP7F_BR_PSD_OFF_MASK                     0x0800
#define BRPHY3_GPHY_CORE_EXP7F_BR_PSD_OFF_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP7F_BR_PSD_OFF_BITS                     1
#define BRPHY3_GPHY_CORE_EXP7F_BR_PSD_OFF_SHIFT                    11

/* BRPHY3_GPHY_CORE :: EXP7F :: ECD_DC_OFFSET [10:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x7fc,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x7fc,2)
#define BRPHY3_GPHY_CORE_EXP7F_ECD_DC_OFFSET_MASK                  0x07fc
#define BRPHY3_GPHY_CORE_EXP7F_ECD_DC_OFFSET_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXP7F_ECD_DC_OFFSET_BITS                  9
#define BRPHY3_GPHY_CORE_EXP7F_ECD_DC_OFFSET_SHIFT                 2

/* BRPHY3_GPHY_CORE :: EXP7F :: FIBER_UNIDIR_OV [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x2,1)
#define BRPHY3_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_MASK                0x0002
#define BRPHY3_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_BITS                1
#define BRPHY3_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_SHIFT               1

/* BRPHY3_GPHY_CORE :: EXP7F :: MACSEC_EN [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP7F_MACSEC_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP7F_MACSEC_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP7F,0x1,0)
#define BRPHY3_GPHY_CORE_EXP7F_MACSEC_EN_MASK                      0x0001
#define BRPHY3_GPHY_CORE_EXP7F_MACSEC_EN_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP7F_MACSEC_EN_BITS                      1
#define BRPHY3_GPHY_CORE_EXP7F_MACSEC_EN_SHIFT                     0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: ALIAS_18
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: ALIAS_18 :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_ALIAS_18_RESERVED0_MASK                   0xf000
#define BRPHY3_GPHY_CORE_ALIAS_18_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_ALIAS_18_RESERVED0_BITS                   4
#define BRPHY3_GPHY_CORE_ALIAS_18_RESERVED0_SHIFT                  12

/* BRPHY3_GPHY_CORE :: ALIAS_18 :: ALIAS [11:00] */
#define Wr_BRPHY3_GPHY_CORE_ALIAS_18_ALIAS(x) WriteRegBits16(BRPHY3_GPHY_CORE_ALIAS_18,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_ALIAS_18_ALIAS(x) ReadRegBits16(BRPHY3_GPHY_CORE_ALIAS_18,0xfff,0)
#define BRPHY3_GPHY_CORE_ALIAS_18_ALIAS_MASK                       0x0fff
#define BRPHY3_GPHY_CORE_ALIAS_18_ALIAS_ALIGN                      0
#define BRPHY3_GPHY_CORE_ALIAS_18_ALIAS_BITS                       12
#define BRPHY3_GPHY_CORE_ALIAS_18_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: ALIAS_19
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: ALIAS_19 :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_ALIAS_19_RESERVED0_MASK                   0xf000
#define BRPHY3_GPHY_CORE_ALIAS_19_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_ALIAS_19_RESERVED0_BITS                   4
#define BRPHY3_GPHY_CORE_ALIAS_19_RESERVED0_SHIFT                  12

/* BRPHY3_GPHY_CORE :: ALIAS_19 :: ALIAS [11:00] */
#define Wr_BRPHY3_GPHY_CORE_ALIAS_19_ALIAS(x) WriteRegBits16(BRPHY3_GPHY_CORE_ALIAS_19,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_ALIAS_19_ALIAS(x) ReadRegBits16(BRPHY3_GPHY_CORE_ALIAS_19,0xfff,0)
#define BRPHY3_GPHY_CORE_ALIAS_19_ALIAS_MASK                       0x0fff
#define BRPHY3_GPHY_CORE_ALIAS_19_ALIAS_ALIGN                      0
#define BRPHY3_GPHY_CORE_ALIAS_19_ALIAS_BITS                       12
#define BRPHY3_GPHY_CORE_ALIAS_19_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: ALIAS_1a
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: ALIAS_1a :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_ALIAS_1A_RESERVED0_MASK                   0xf000
#define BRPHY3_GPHY_CORE_ALIAS_1A_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_ALIAS_1A_RESERVED0_BITS                   4
#define BRPHY3_GPHY_CORE_ALIAS_1A_RESERVED0_SHIFT                  12

/* BRPHY3_GPHY_CORE :: ALIAS_1a :: ALIAS [11:00] */
#define Wr_BRPHY3_GPHY_CORE_ALIAS_1a_ALIAS(x) WriteRegBits16(BRPHY3_GPHY_CORE_ALIAS_1A,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_ALIAS_1a_ALIAS(x) ReadRegBits16(BRPHY3_GPHY_CORE_ALIAS_1A,0xfff,0)
#define BRPHY3_GPHY_CORE_ALIAS_1A_ALIAS_MASK                       0x0fff
#define BRPHY3_GPHY_CORE_ALIAS_1A_ALIAS_ALIGN                      0
#define BRPHY3_GPHY_CORE_ALIAS_1A_ALIAS_BITS                       12
#define BRPHY3_GPHY_CORE_ALIAS_1A_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: ALIAS_1b
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: ALIAS_1b :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_ALIAS_1B_RESERVED0_MASK                   0xf000
#define BRPHY3_GPHY_CORE_ALIAS_1B_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_ALIAS_1B_RESERVED0_BITS                   4
#define BRPHY3_GPHY_CORE_ALIAS_1B_RESERVED0_SHIFT                  12

/* BRPHY3_GPHY_CORE :: ALIAS_1b :: ALIAS [11:00] */
#define Wr_BRPHY3_GPHY_CORE_ALIAS_1b_ALIAS(x) WriteRegBits16(BRPHY3_GPHY_CORE_ALIAS_1B,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_ALIAS_1b_ALIAS(x) ReadRegBits16(BRPHY3_GPHY_CORE_ALIAS_1B,0xfff,0)
#define BRPHY3_GPHY_CORE_ALIAS_1B_ALIAS_MASK                       0x0fff
#define BRPHY3_GPHY_CORE_ALIAS_1B_ALIAS_ALIGN                      0
#define BRPHY3_GPHY_CORE_ALIAS_1B_ALIAS_BITS                       12
#define BRPHY3_GPHY_CORE_ALIAS_1B_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: ALIAS_1c
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: ALIAS_1c :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_ALIAS_1C_RESERVED0_MASK                   0xf000
#define BRPHY3_GPHY_CORE_ALIAS_1C_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_ALIAS_1C_RESERVED0_BITS                   4
#define BRPHY3_GPHY_CORE_ALIAS_1C_RESERVED0_SHIFT                  12

/* BRPHY3_GPHY_CORE :: ALIAS_1c :: ALIAS [11:00] */
#define Wr_BRPHY3_GPHY_CORE_ALIAS_1c_ALIAS(x) WriteRegBits16(BRPHY3_GPHY_CORE_ALIAS_1C,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_ALIAS_1c_ALIAS(x) ReadRegBits16(BRPHY3_GPHY_CORE_ALIAS_1C,0xfff,0)
#define BRPHY3_GPHY_CORE_ALIAS_1C_ALIAS_MASK                       0x0fff
#define BRPHY3_GPHY_CORE_ALIAS_1C_ALIAS_ALIGN                      0
#define BRPHY3_GPHY_CORE_ALIAS_1C_ALIAS_BITS                       12
#define BRPHY3_GPHY_CORE_ALIAS_1C_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: ALIAS_1d
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: ALIAS_1d :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_ALIAS_1D_RESERVED0_MASK                   0xf000
#define BRPHY3_GPHY_CORE_ALIAS_1D_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_ALIAS_1D_RESERVED0_BITS                   4
#define BRPHY3_GPHY_CORE_ALIAS_1D_RESERVED0_SHIFT                  12

/* BRPHY3_GPHY_CORE :: ALIAS_1d :: ALIAS [11:00] */
#define Wr_BRPHY3_GPHY_CORE_ALIAS_1d_ALIAS(x) WriteRegBits16(BRPHY3_GPHY_CORE_ALIAS_1D,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_ALIAS_1d_ALIAS(x) ReadRegBits16(BRPHY3_GPHY_CORE_ALIAS_1D,0xfff,0)
#define BRPHY3_GPHY_CORE_ALIAS_1D_ALIAS_MASK                       0x0fff
#define BRPHY3_GPHY_CORE_ALIAS_1D_ALIAS_ALIGN                      0
#define BRPHY3_GPHY_CORE_ALIAS_1D_ALIAS_BITS                       12
#define BRPHY3_GPHY_CORE_ALIAS_1D_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: REG_MAP_CTL
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: REG_MAP_CTL :: REG_LEGACY_EN [15:15] */
#define Wr_BRPHY3_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_REG_MAP_CTL,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_REG_MAP_CTL,0x8000,15)
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_MASK            0x8000
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_BITS            1
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_SHIFT           15

/* BRPHY3_GPHY_CORE :: REG_MAP_CTL :: ALIAS_MODE [14:13] */
#define Wr_BRPHY3_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_REG_MAP_CTL,0x6000,13,x)
#define Rd_BRPHY3_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_REG_MAP_CTL,0x6000,13)
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_MASK               0x6000
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_ALIGN              0
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_BITS               2
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_SHIFT              13

/* BRPHY3_GPHY_CORE :: REG_MAP_CTL :: reserved0 [12:12] */
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_RESERVED0_MASK                0x1000
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_RESERVED0_ALIGN               0
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_RESERVED0_BITS                1
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_RESERVED0_SHIFT               12

/* BRPHY3_GPHY_CORE :: REG_MAP_CTL :: RANGE_OFFSET [11:00] */
#define Wr_BRPHY3_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) WriteRegBits16(BRPHY3_GPHY_CORE_REG_MAP_CTL,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) ReadRegBits16(BRPHY3_GPHY_CORE_REG_MAP_CTL,0xfff,0)
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_MASK             0x0fff
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_ALIGN            0
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_BITS             12
#define BRPHY3_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_SHIFT            0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP98
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP98 :: reserved0 [15:11] */
#define BRPHY3_GPHY_CORE_EXP98_RESERVED0_MASK                      0xf800
#define BRPHY3_GPHY_CORE_EXP98_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXP98_RESERVED0_BITS                      5
#define BRPHY3_GPHY_CORE_EXP98_RESERVED0_SHIFT                     11

/* BRPHY3_GPHY_CORE :: EXP98 :: RC_CAL [10:06] */
#define Wr_BRPHY3_GPHY_CORE_EXP98_RC_CAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP98,0x7c0,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXP98_RC_CAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP98,0x7c0,6)
#define BRPHY3_GPHY_CORE_EXP98_RC_CAL_MASK                         0x07c0
#define BRPHY3_GPHY_CORE_EXP98_RC_CAL_ALIGN                        0
#define BRPHY3_GPHY_CORE_EXP98_RC_CAL_BITS                         5
#define BRPHY3_GPHY_CORE_EXP98_RC_CAL_SHIFT                        6

/* BRPHY3_GPHY_CORE :: EXP98 :: R_CAL [05:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP98_R_CAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP98,0x3e,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP98_R_CAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP98,0x3e,1)
#define BRPHY3_GPHY_CORE_EXP98_R_CAL_MASK                          0x003e
#define BRPHY3_GPHY_CORE_EXP98_R_CAL_ALIGN                         0
#define BRPHY3_GPHY_CORE_EXP98_R_CAL_BITS                          5
#define BRPHY3_GPHY_CORE_EXP98_R_CAL_SHIFT                         1

/* BRPHY3_GPHY_CORE :: EXP98 :: CAL_DONE [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP98_CAL_DONE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP98,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP98_CAL_DONE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP98,0x1,0)
#define BRPHY3_GPHY_CORE_EXP98_CAL_DONE_MASK                       0x0001
#define BRPHY3_GPHY_CORE_EXP98_CAL_DONE_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP98_CAL_DONE_BITS                       1
#define BRPHY3_GPHY_CORE_EXP98_CAL_DONE_SHIFT                      0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXP9C
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXP9C :: MII_REG1C_BNK1 [15:12] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0xf000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0xf000,12)
#define BRPHY3_GPHY_CORE_EXP9C_MII_REG1C_BNK1_MASK                 0xf000
#define BRPHY3_GPHY_CORE_EXP9C_MII_REG1C_BNK1_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP9C_MII_REG1C_BNK1_BITS                 4
#define BRPHY3_GPHY_CORE_EXP9C_MII_REG1C_BNK1_SHIFT                12

/* BRPHY3_GPHY_CORE :: EXP9C :: RSMII_LOAD_XMT [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x800,11)
#define BRPHY3_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_MASK                 0x0800
#define BRPHY3_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_BITS                 1
#define BRPHY3_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_SHIFT                11

/* BRPHY3_GPHY_CORE :: EXP9C :: FIFO_OV_UN [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_FIFO_OV_UN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_FIFO_OV_UN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x400,10)
#define BRPHY3_GPHY_CORE_EXP9C_FIFO_OV_UN_MASK                     0x0400
#define BRPHY3_GPHY_CORE_EXP9C_FIFO_OV_UN_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP9C_FIFO_OV_UN_BITS                     1
#define BRPHY3_GPHY_CORE_EXP9C_FIFO_OV_UN_SHIFT                    10

/* BRPHY3_GPHY_CORE :: EXP9C :: TEST_EN [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_TEST_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_TEST_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x200,9)
#define BRPHY3_GPHY_CORE_EXP9C_TEST_EN_MASK                        0x0200
#define BRPHY3_GPHY_CORE_EXP9C_TEST_EN_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXP9C_TEST_EN_BITS                        1
#define BRPHY3_GPHY_CORE_EXP9C_TEST_EN_SHIFT                       9

/* BRPHY3_GPHY_CORE :: EXP9C :: PTEST [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_PTEST(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_PTEST(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x100,8)
#define BRPHY3_GPHY_CORE_EXP9C_PTEST_MASK                          0x0100
#define BRPHY3_GPHY_CORE_EXP9C_PTEST_ALIGN                         0
#define BRPHY3_GPHY_CORE_EXP9C_PTEST_BITS                          1
#define BRPHY3_GPHY_CORE_EXP9C_PTEST_SHIFT                         8

/* BRPHY3_GPHY_CORE :: EXP9C :: EXRMIIFE [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_EXRMIIFE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_EXRMIIFE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x80,7)
#define BRPHY3_GPHY_CORE_EXP9C_EXRMIIFE_MASK                       0x0080
#define BRPHY3_GPHY_CORE_EXP9C_EXRMIIFE_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXP9C_EXRMIIFE_BITS                       1
#define BRPHY3_GPHY_CORE_EXP9C_EXRMIIFE_SHIFT                      7

/* BRPHY3_GPHY_CORE :: EXP9C :: FIFO_SIZE_CNTL [06:03] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x78,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x78,3)
#define BRPHY3_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_MASK                 0x0078
#define BRPHY3_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_ALIGN                0
#define BRPHY3_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_BITS                 4
#define BRPHY3_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_SHIFT                3

/* BRPHY3_GPHY_CORE :: EXP9C :: BIG_FIFO_EN [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x4,2)
#define BRPHY3_GPHY_CORE_EXP9C_BIG_FIFO_EN_MASK                    0x0004
#define BRPHY3_GPHY_CORE_EXP9C_BIG_FIFO_EN_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXP9C_BIG_FIFO_EN_BITS                    1
#define BRPHY3_GPHY_CORE_EXP9C_BIG_FIFO_EN_SHIFT                   2

/* BRPHY3_GPHY_CORE :: EXP9C :: SMII_S3MII_MODE [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x2,1)
#define BRPHY3_GPHY_CORE_EXP9C_SMII_S3MII_MODE_MASK                0x0002
#define BRPHY3_GPHY_CORE_EXP9C_SMII_S3MII_MODE_ALIGN               0
#define BRPHY3_GPHY_CORE_EXP9C_SMII_S3MII_MODE_BITS                1
#define BRPHY3_GPHY_CORE_EXP9C_SMII_S3MII_MODE_SHIFT               1

/* BRPHY3_GPHY_CORE :: EXP9C :: SSSMII_DIS [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXP9C_SSSMII_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXP9C_SSSMII_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXP9C,0x1,0)
#define BRPHY3_GPHY_CORE_EXP9C_SSSMII_DIS_MASK                     0x0001
#define BRPHY3_GPHY_CORE_EXP9C_SSSMII_DIS_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXP9C_SSSMII_DIS_BITS                     1
#define BRPHY3_GPHY_CORE_EXP9C_SSSMII_DIS_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: BT_LINK_FIX
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: BT_LINK_FIX :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RESERVED0_MASK                0x8000
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RESERVED0_ALIGN               0
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RESERVED0_BITS                1
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RESERVED0_SHIFT               15

/* BRPHY3_GPHY_CORE :: BT_LINK_FIX :: rxc_byp_rclk_dll_div2 [14:14] */
#define Wr_BRPHY3_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) WriteRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) ReadRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0x4000,14)
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_MASK    0x4000
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_ALIGN   0
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_BITS    1
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_SHIFT   14

/* BRPHY3_GPHY_CORE :: BT_LINK_FIX :: rxc_shamoo_tst_en [13:13] */
#define Wr_BRPHY3_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) WriteRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) ReadRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0x2000,13)
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_MASK        0x2000
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_ALIGN       0
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_BITS        1
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_SHIFT       13

/* BRPHY3_GPHY_CORE :: BT_LINK_FIX :: sig_10bt_upp_limit [12:08] */
#define Wr_BRPHY3_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) WriteRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0x1f00,8,x)
#define Rd_BRPHY3_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) ReadRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0x1f00,8)
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_MASK       0x1f00
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_ALIGN      0
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_BITS       5
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_SHIFT      8

/* BRPHY3_GPHY_CORE :: BT_LINK_FIX :: threshold_2mhz [07:01] */
#define Wr_BRPHY3_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) WriteRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0xfe,1,x)
#define Rd_BRPHY3_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) ReadRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0xfe,1)
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_MASK           0x00fe
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_ALIGN          0
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_BITS           7
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_SHIFT          1

/* BRPHY3_GPHY_CORE :: BT_LINK_FIX :: break_link10bt_disable [00:00] */
#define Wr_BRPHY3_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) WriteRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) ReadRegBits16(BRPHY3_GPHY_CORE_BT_LINK_FIX,0x1,0)
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_MASK   0x0001
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_ALIGN  0
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_BITS   1
#define BRPHY3_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_SHIFT  0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SYNCE_PLUS_DBG
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_DBG [15:02] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_MASK             0xfffc
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_ALIGN            0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_BITS             14
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_SHIFT            2

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_BRUTEFORCE_TM [01:01] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_MASK   0x0002
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_ALIGN  0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_BITS   1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_SHIFT  1

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_HSTIMEOUT_CTL [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_MASK   0x0001
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_ALIGN  0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_BITS   1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_SHIFT  0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: SYNCE_PLUS
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: TIMING_CONFIG [15:15] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x8000,15)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_MASK             0x8000
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_ALIGN            0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_BITS             1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_SHIFT            15

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_ONGOING [14:14] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x4000,14)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_MASK     0x4000
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_ALIGN    0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_BITS     1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_SHIFT    14

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: SYNCE_AUTO_ACK [13:13] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x2000,13)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_MASK            0x2000
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_ALIGN           0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_BITS            1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_SHIFT           13

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: SYNCE_WAIT_FOR_IDLE [12:12] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x1000,12)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_MASK       0x1000
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_ALIGN      0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_BITS       1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_SHIFT      12

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_COMPLETE [11:11] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x800,11)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_MASK    0x0800
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_ALIGN   0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_BITS    1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_SHIFT   11

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_PENDING [10:10] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x400,10)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_MASK     0x0400
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_ALIGN    0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_BITS     1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_SHIFT    10

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ERROR_STATUS [09:08] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x300,8,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x300,8)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_MASK        0x0300
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_ALIGN       0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_BITS        2
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_SHIFT       8

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_FAIL [07:07] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x80,7)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_MASK        0x0080
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_ALIGN       0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_BITS        1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_SHIFT       7

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: SYNCE_FTIMEOUT_CTL [06:06] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x40,6)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_MASK        0x0040
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_ALIGN       0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_BITS        1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_SHIFT       6

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: SYNCE_DBG_MUX_CTL [05:04] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x30,4,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x30,4)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_MASK         0x0030
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_ALIGN        0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_BITS         2
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_SHIFT        4

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: SYNCE_INTERRUPT_MASK [03:02] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0xc,2,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0xc,2)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_MASK      0x000c
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_ALIGN     0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_BITS      2
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_SHIFT     2

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: SYNCE_TIMING_SWITCH_START [01:01] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x2,1)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_MASK 0x0002
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_ALIGN 0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_BITS 1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_SHIFT 1

/* BRPHY3_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ENABLE [00:00] */
#define Wr_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_SYNCE_PLUS,0x1,0)
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_MASK              0x0001
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_ALIGN             0
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_BITS              1
#define BRPHY3_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_SHIFT             0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPA8
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPA8 :: ADAPTIVE_BIAS_CTRL [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) WriteReg16(BRPHY3_GPHY_CORE_EXPA8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) ReadReg16(BRPHY3_GPHY_CORE_EXPA8)
#define BRPHY3_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_MASK             0xffff
#define BRPHY3_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_BITS             16
#define BRPHY3_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_SHIFT            0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPA9
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPA9 :: SPARE_REG [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPA9_SPARE_REG(x) WriteReg16(BRPHY3_GPHY_CORE_EXPA9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPA9_SPARE_REG(x) ReadReg16(BRPHY3_GPHY_CORE_EXPA9)
#define BRPHY3_GPHY_CORE_EXPA9_SPARE_REG_MASK                      0xffff
#define BRPHY3_GPHY_CORE_EXPA9_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPA9_SPARE_REG_BITS                      16
#define BRPHY3_GPHY_CORE_EXPA9_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPAA
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPAA :: STATISTIC_TIMER_12HOURS_LPI [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) WriteReg16(BRPHY3_GPHY_CORE_EXPAA,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) ReadReg16(BRPHY3_GPHY_CORE_EXPAA)
#define BRPHY3_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_MASK    0xffff
#define BRPHY3_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_ALIGN   0
#define BRPHY3_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_BITS    16
#define BRPHY3_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_SHIFT   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPAB
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPAB :: STATISTIC_TIMER_12HOURS_LOCAL [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) WriteReg16(BRPHY3_GPHY_CORE_EXPAB,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) ReadReg16(BRPHY3_GPHY_CORE_EXPAB)
#define BRPHY3_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_MASK  0xffff
#define BRPHY3_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_ALIGN 0
#define BRPHY3_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_BITS  16
#define BRPHY3_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_SHIFT 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPAC
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPAC :: STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY3_GPHY_CORE_EXPAC,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY3_GPHY_CORE_EXPAC)
#define BRPHY3_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY3_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY3_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY3_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPAD
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPAD :: STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY3_GPHY_CORE_EXPAD,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY3_GPHY_CORE_EXPAD)
#define BRPHY3_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY3_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY3_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY3_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPAE
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPAE :: SPARE_REG [15:09] */
#define Wr_BRPHY3_GPHY_CORE_EXPAE_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAE,0xfe00,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAE_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAE,0xfe00,9)
#define BRPHY3_GPHY_CORE_EXPAE_SPARE_REG_MASK                      0xfe00
#define BRPHY3_GPHY_CORE_EXPAE_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPAE_SPARE_REG_BITS                      7
#define BRPHY3_GPHY_CORE_EXPAE_SPARE_REG_SHIFT                     9

/* BRPHY3_GPHY_CORE :: EXPAE :: TXBIAS_VAL2 [08:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAE,0x1e0,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAE,0x1e0,5)
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL2_MASK                    0x01e0
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL2_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL2_BITS                    4
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL2_SHIFT                   5

/* BRPHY3_GPHY_CORE :: EXPAE :: TXBIAS_VAL1 [04:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAE,0x1e,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAE,0x1e,1)
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL1_MASK                    0x001e
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL1_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL1_BITS                    4
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_VAL1_SHIFT                   1

/* BRPHY3_GPHY_CORE :: EXPAE :: TXBIAS_PLUS_MODE [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAE,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAE,0x1,0)
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_MASK               0x0001
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_BITS               1
#define BRPHY3_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPAF
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPAF :: STATISTIC_1000BT_MODE [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x8000,15)
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_MASK          0x8000
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_ALIGN         0
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_BITS          1
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_SHIFT         15

/* BRPHY3_GPHY_CORE :: EXPAF :: STATISTIC_UPPER_16BITS_SEL [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x4000,14)
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_MASK     0x4000
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_ALIGN    0
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_BITS     1
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_SHIFT    14

/* BRPHY3_GPHY_CORE :: EXPAF :: STATISTIC_SATURATE_MODE [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x2000,13)
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_MASK        0x2000
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_ALIGN       0
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_BITS        1
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_SHIFT       13

/* BRPHY3_GPHY_CORE :: EXPAF :: STATISTIC_ACCESS_MODE [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_MASK          0x1000
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_ALIGN         0
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_BITS          1
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_SHIFT         12

/* BRPHY3_GPHY_CORE :: EXPAF :: SPARE_REG [11:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0xfe0,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0xfe0,5)
#define BRPHY3_GPHY_CORE_EXPAF_SPARE_REG_MASK                      0x0fe0
#define BRPHY3_GPHY_CORE_EXPAF_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPAF_SPARE_REG_BITS                      7
#define BRPHY3_GPHY_CORE_EXPAF_SPARE_REG_SHIFT                     5

/* BRPHY3_GPHY_CORE :: EXPAF :: EEE_REM_RCVR_STATUS_DIS [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x10,4)
#define BRPHY3_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_MASK        0x0010
#define BRPHY3_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY3_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_BITS        1
#define BRPHY3_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_SHIFT       4

/* BRPHY3_GPHY_CORE :: EXPAF :: EEE_LOC_RCVR_STATUS_DIS [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x8,3)
#define BRPHY3_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_MASK        0x0008
#define BRPHY3_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY3_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_BITS        1
#define BRPHY3_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_SHIFT       3

/* BRPHY3_GPHY_CORE :: EXPAF :: STATISTIC_ADAPTX_EN [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x4,2)
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_MASK            0x0004
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_ALIGN           0
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_BITS            1
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_SHIFT           2

/* BRPHY3_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_RESET [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x2,1)
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_MASK       0x0002
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_ALIGN      0
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_BITS       1
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_SHIFT      1

/* BRPHY3_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_ENABLE [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPAF,0x1,0)
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_MASK      0x0001
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_ALIGN     0
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_BITS      1
#define BRPHY3_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_SHIFT     0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPB0
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPB0 :: BIAS_CTL_0 [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPB0_BIAS_CTL_0(x) WriteReg16(BRPHY3_GPHY_CORE_EXPB0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPB0_BIAS_CTL_0(x) ReadReg16(BRPHY3_GPHY_CORE_EXPB0)
#define BRPHY3_GPHY_CORE_EXPB0_BIAS_CTL_0_MASK                     0xffff
#define BRPHY3_GPHY_CORE_EXPB0_BIAS_CTL_0_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPB0_BIAS_CTL_0_BITS                     16
#define BRPHY3_GPHY_CORE_EXPB0_BIAS_CTL_0_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPB1
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPB1 :: BIAS_CTL_1 [15:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPB1_BIAS_CTL_1(x) WriteReg16(BRPHY3_GPHY_CORE_EXPB1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPB1_BIAS_CTL_1(x) ReadReg16(BRPHY3_GPHY_CORE_EXPB1)
#define BRPHY3_GPHY_CORE_EXPB1_BIAS_CTL_1_MASK                     0xffff
#define BRPHY3_GPHY_CORE_EXPB1_BIAS_CTL_1_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPB1_BIAS_CTL_1_BITS                     16
#define BRPHY3_GPHY_CORE_EXPB1_BIAS_CTL_1_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPB2
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPB2 :: CLK200_SEL_OV [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPB2,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPB2,0x8000,15)
#define BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_OV_MASK                  0x8000
#define BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_OV_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_OV_BITS                  1
#define BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_OV_SHIFT                 15

/* BRPHY3_GPHY_CORE :: EXPB2 :: CLK200_SEL [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPB2,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPB2,0x4000,14)
#define BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_MASK                     0x4000
#define BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_BITS                     1
#define BRPHY3_GPHY_CORE_EXPB2_CLK200_SEL_SHIFT                    14

/* BRPHY3_GPHY_CORE :: EXPB2 :: CK25_SEL [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPB2_CK25_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPB2,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPB2_CK25_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPB2,0x2000,13)
#define BRPHY3_GPHY_CORE_EXPB2_CK25_SEL_MASK                       0x2000
#define BRPHY3_GPHY_CORE_EXPB2_CK25_SEL_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXPB2_CK25_SEL_BITS                       1
#define BRPHY3_GPHY_CORE_EXPB2_CK25_SEL_SHIFT                      13

/* BRPHY3_GPHY_CORE :: EXPB2 :: REG_B2_SPARE [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPB2_REG_B2_SPARE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPB2,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPB2_REG_B2_SPARE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPB2,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPB2_REG_B2_SPARE_MASK                   0x1000
#define BRPHY3_GPHY_CORE_EXPB2_REG_B2_SPARE_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPB2_REG_B2_SPARE_BITS                   1
#define BRPHY3_GPHY_CORE_EXPB2_REG_B2_SPARE_SHIFT                  12

/* BRPHY3_GPHY_CORE :: EXPB2 :: I_RC_OFFSET_PHY [11:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPB2,0xf00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPB2,0xf00,8)
#define BRPHY3_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_MASK                0x0f00
#define BRPHY3_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_BITS                4
#define BRPHY3_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_SHIFT               8

/* BRPHY3_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_1000_100 [07:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPB2,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPB2,0xf0,4)
#define BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_MASK        0x00f0
#define BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_ALIGN       0
#define BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_BITS        4
#define BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_SHIFT       4

/* BRPHY3_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_10 [03:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPB2,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPB2,0xf,0)
#define BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_MASK              0x000f
#define BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_BITS              4
#define BRPHY3_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_SHIFT             0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE3
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE3,0xff00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE3,0xff00,8)
#define BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_100_MASK                 0xff00
#define BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_100_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_100_BITS                 8
#define BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_100_SHIFT                8

/* BRPHY3_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE3,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE3,0xff,0)
#define BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_BITS                8
#define BRPHY3_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE4
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE4 :: TX_PCS_SOP_TSYNC_ERR [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE4,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE4,0x8000,15)
#define BRPHY3_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_MASK           0x8000
#define BRPHY3_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_BITS           1
#define BRPHY3_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_SHIFT          15

/* BRPHY3_GPHY_CORE :: EXPE4 :: reserved0 [14:12] */
#define BRPHY3_GPHY_CORE_EXPE4_RESERVED0_MASK                      0x7000
#define BRPHY3_GPHY_CORE_EXPE4_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPE4_RESERVED0_BITS                      3
#define BRPHY3_GPHY_CORE_EXPE4_RESERVED0_SHIFT                     12

/* BRPHY3_GPHY_CORE :: EXPE4 :: TX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE4,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE4,0xfff,0)
#define BRPHY3_GPHY_CORE_EXPE4_TX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY3_GPHY_CORE_EXPE4_TX_PCS_DLY_10_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXPE4_TX_PCS_DLY_10_BITS                  12
#define BRPHY3_GPHY_CORE_EXPE4_TX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE5
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE5,0xff00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE5,0xff00,8)
#define BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_BITS               8
#define BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_SHIFT              8

/* BRPHY3_GPHY_CORE :: EXPE5 :: reserved0 [07:07] */
#define BRPHY3_GPHY_CORE_EXPE5_RESERVED0_MASK                      0x0080
#define BRPHY3_GPHY_CORE_EXPE5_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPE5_RESERVED0_BITS                      1
#define BRPHY3_GPHY_CORE_EXPE5_RESERVED0_SHIFT                     7

/* BRPHY3_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE5,0x7f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE5,0x7f,0)
#define BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_BITS               7
#define BRPHY3_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE6
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE6,0xff00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE6,0xff00,8)
#define BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_100_MASK                 0xff00
#define BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_100_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_100_BITS                 8
#define BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_100_SHIFT                8

/* BRPHY3_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE6,0xff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE6,0xff,0)
#define BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_BITS                8
#define BRPHY3_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE7
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE7 :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_EXPE7_RESERVED0_MASK                      0xf000
#define BRPHY3_GPHY_CORE_EXPE7_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPE7_RESERVED0_BITS                      4
#define BRPHY3_GPHY_CORE_EXPE7_RESERVED0_SHIFT                     12

/* BRPHY3_GPHY_CORE :: EXPE7 :: RX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE7,0xfff,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE7,0xfff,0)
#define BRPHY3_GPHY_CORE_EXPE7_RX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY3_GPHY_CORE_EXPE7_RX_PCS_DLY_10_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXPE7_RX_PCS_DLY_10_BITS                  12
#define BRPHY3_GPHY_CORE_EXPE7_RX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE8
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE8,0xff00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE8,0xff00,8)
#define BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_BITS               8
#define BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_SHIFT              8

/* BRPHY3_GPHY_CORE :: EXPE8 :: reserved0 [07:07] */
#define BRPHY3_GPHY_CORE_EXPE8_RESERVED0_MASK                      0x0080
#define BRPHY3_GPHY_CORE_EXPE8_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPE8_RESERVED0_BITS                      1
#define BRPHY3_GPHY_CORE_EXPE8_RESERVED0_SHIFT                     7

/* BRPHY3_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE8,0x7f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE8,0x7f,0)
#define BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_BITS               7
#define BRPHY3_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE9
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE9 :: reserved0 [15:14] */
#define BRPHY3_GPHY_CORE_EXPE9_RESERVED0_MASK                      0xc000
#define BRPHY3_GPHY_CORE_EXPE9_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPE9_RESERVED0_BITS                      2
#define BRPHY3_GPHY_CORE_EXPE9_RESERVED0_SHIFT                     14

/* BRPHY3_GPHY_CORE :: EXPE9 :: P1588_TX_DLY_CYCLE [13:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE9,0x3f00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE9,0x3f00,8)
#define BRPHY3_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_MASK             0x3f00
#define BRPHY3_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_BITS             6
#define BRPHY3_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_SHIFT            8

/* BRPHY3_GPHY_CORE :: EXPE9 :: reserved1 [07:06] */
#define BRPHY3_GPHY_CORE_EXPE9_RESERVED1_MASK                      0x00c0
#define BRPHY3_GPHY_CORE_EXPE9_RESERVED1_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPE9_RESERVED1_BITS                      2
#define BRPHY3_GPHY_CORE_EXPE9_RESERVED1_SHIFT                     6

/* BRPHY3_GPHY_CORE :: EXPE9 :: P1588_RX_DLY_CYCLE [05:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE9,0x3f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE9,0x3f,0)
#define BRPHY3_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_MASK             0x003f
#define BRPHY3_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_BITS             6
#define BRPHY3_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_SHIFT            0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE0
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_10 [15:10] */
#define Wr_BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE0,0xfc00,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE0,0xfc00,10)
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_MASK              0xfc00
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_BITS              6
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_SHIFT             10

/* BRPHY3_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_100 [09:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE0,0x3e0,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE0,0x3e0,5)
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_MASK             0x03e0
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_BITS             5
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_SHIFT            5

/* BRPHY3_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_1000 [04:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE0,0x1f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE0,0x1f,0)
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_MASK            0x001f
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_ALIGN           0
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_BITS            5
#define BRPHY3_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_SHIFT           0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE1
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE1 :: reserved0 [15:12] */
#define BRPHY3_GPHY_CORE_EXPE1_RESERVED0_MASK                      0xf000
#define BRPHY3_GPHY_CORE_EXPE1_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPE1_RESERVED0_BITS                      4
#define BRPHY3_GPHY_CORE_EXPE1_RESERVED0_SHIFT                     12

/* BRPHY3_GPHY_CORE :: EXPE1 :: RX_PMA_PMD_DLY_FIBER [11:06] */
#define Wr_BRPHY3_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE1,0xfc0,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE1,0xfc0,6)
#define BRPHY3_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_MASK           0x0fc0
#define BRPHY3_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY3_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_SHIFT          6

/* BRPHY3_GPHY_CORE :: EXPE1 :: TX_PMA_PMD_DLY_FIBER [05:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE1,0x3f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE1,0x3f,0)
#define BRPHY3_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_MASK           0x003f
#define BRPHY3_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY3_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_SHIFT          0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPE2
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPE2 :: reserved0 [15:14] */
#define BRPHY3_GPHY_CORE_EXPE2_RESERVED0_MASK                      0xc000
#define BRPHY3_GPHY_CORE_EXPE2_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPE2_RESERVED0_BITS                      2
#define BRPHY3_GPHY_CORE_EXPE2_RESERVED0_SHIFT                     14

/* BRPHY3_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_10 [13:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE2,0x3f80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE2,0x3f80,7)
#define BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_MASK              0x3f80
#define BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_BITS              7
#define BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_SHIFT             7

/* BRPHY3_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_100_1000 [06:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPE2,0x7f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPE2,0x7f,0)
#define BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_MASK        0x007f
#define BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_ALIGN       0
#define BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_BITS        7
#define BRPHY3_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_SHIFT       0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPEA
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPEA :: reserved0 [15:13] */
#define BRPHY3_GPHY_CORE_EXPEA_RESERVED0_MASK                      0xe000
#define BRPHY3_GPHY_CORE_EXPEA_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPEA_RESERVED0_BITS                      3
#define BRPHY3_GPHY_CORE_EXPEA_RESERVED0_SHIFT                     13

/* BRPHY3_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MAX_DLY_CYCLE [12:10] */
#define Wr_BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPEA,0x1c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPEA,0x1c00,10)
#define BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x1c00
#define BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      10

/* BRPHY3_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MIN_DLY_CYCLE [09:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPEA,0x380,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPEA,0x380,7)
#define BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x0380
#define BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY3_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      7

/* BRPHY3_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MAX_DLY_CYCLE [06:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPEA,0x70,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPEA,0x70,4)
#define BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x0070
#define BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      4

/* BRPHY3_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MIN_DLY_CYCLE [03:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPEA,0xe,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPEA,0xe,1)
#define BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x000e
#define BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY3_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      1

/* BRPHY3_GPHY_CORE :: EXPEA :: FEATURE_802_3BF_ENABLE [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPEA,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPEA,0x1,0)
#define BRPHY3_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_MASK         0x0001
#define BRPHY3_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_ALIGN        0
#define BRPHY3_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_BITS         1
#define BRPHY3_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_SHIFT        0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: LED_PRA_MODE
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: LED_PRA_MODE :: reserved0 [15:04] */
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_RESERVED0_MASK               0xfff0
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_RESERVED0_ALIGN              0
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_RESERVED0_BITS               12
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_RESERVED0_SHIFT              4

/* BRPHY3_GPHY_CORE :: LED_PRA_MODE :: SAT_MODE [03:03] */
#define Wr_BRPHY3_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_LED_PRA_MODE,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_LED_PRA_MODE,0x8,3)
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_SAT_MODE_MASK                0x0008
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_SAT_MODE_ALIGN               0
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_SAT_MODE_BITS                1
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_SAT_MODE_SHIFT               3

/* BRPHY3_GPHY_CORE :: LED_PRA_MODE :: PRA_MODE [02:00] */
#define Wr_BRPHY3_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_LED_PRA_MODE,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_LED_PRA_MODE,0x7,0)
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_PRA_MODE_MASK                0x0007
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_PRA_MODE_ALIGN               0
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_PRA_MODE_BITS                3
#define BRPHY3_GPHY_CORE_LED_PRA_MODE_PRA_MODE_SHIFT               0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: FIFO_CTL
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: FIFO_CTL :: SFT_RST [15:15] */
#define Wr_BRPHY3_GPHY_CORE_FIFO_CTL_SFT_RST(x) WriteRegBits16(BRPHY3_GPHY_CORE_FIFO_CTL,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_FIFO_CTL_SFT_RST(x) ReadRegBits16(BRPHY3_GPHY_CORE_FIFO_CTL,0x8000,15)
#define BRPHY3_GPHY_CORE_FIFO_CTL_SFT_RST_MASK                     0x8000
#define BRPHY3_GPHY_CORE_FIFO_CTL_SFT_RST_ALIGN                    0
#define BRPHY3_GPHY_CORE_FIFO_CTL_SFT_RST_BITS                     1
#define BRPHY3_GPHY_CORE_FIFO_CTL_SFT_RST_SHIFT                    15

/* BRPHY3_GPHY_CORE :: FIFO_CTL :: reserved0 [14:09] */
#define BRPHY3_GPHY_CORE_FIFO_CTL_RESERVED0_MASK                   0x7e00
#define BRPHY3_GPHY_CORE_FIFO_CTL_RESERVED0_ALIGN                  0
#define BRPHY3_GPHY_CORE_FIFO_CTL_RESERVED0_BITS                   6
#define BRPHY3_GPHY_CORE_FIFO_CTL_RESERVED0_SHIFT                  9

/* BRPHY3_GPHY_CORE :: FIFO_CTL :: WRBLOCK_MODE [08:08] */
#define Wr_BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) WriteRegBits16(BRPHY3_GPHY_CORE_FIFO_CTL,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) ReadRegBits16(BRPHY3_GPHY_CORE_FIFO_CTL,0x100,8)
#define BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_MASK                0x0100
#define BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_ALIGN               0
#define BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_BITS                1
#define BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_SHIFT               8

/* BRPHY3_GPHY_CORE :: FIFO_CTL :: WRBLOCK_OVR [07:04] */
#define Wr_BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) WriteRegBits16(BRPHY3_GPHY_CORE_FIFO_CTL,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) ReadRegBits16(BRPHY3_GPHY_CORE_FIFO_CTL,0xf0,4)
#define BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_MASK                 0x00f0
#define BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_ALIGN                0
#define BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_BITS                 4
#define BRPHY3_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_SHIFT                4

/* BRPHY3_GPHY_CORE :: FIFO_CTL :: MIN_IPG [03:00] */
#define Wr_BRPHY3_GPHY_CORE_FIFO_CTL_MIN_IPG(x) WriteRegBits16(BRPHY3_GPHY_CORE_FIFO_CTL,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_FIFO_CTL_MIN_IPG(x) ReadRegBits16(BRPHY3_GPHY_CORE_FIFO_CTL,0xf,0)
#define BRPHY3_GPHY_CORE_FIFO_CTL_MIN_IPG_MASK                     0x000f
#define BRPHY3_GPHY_CORE_FIFO_CTL_MIN_IPG_ALIGN                    0
#define BRPHY3_GPHY_CORE_FIFO_CTL_MIN_IPG_BITS                     4
#define BRPHY3_GPHY_CORE_FIFO_CTL_MIN_IPG_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPD8
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPD8 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_EXPD8_RESERVED0_MASK                      0x8000
#define BRPHY3_GPHY_CORE_EXPD8_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPD8_RESERVED0_BITS                      1
#define BRPHY3_GPHY_CORE_EXPD8_RESERVED0_SHIFT                     15

/* BRPHY3_GPHY_CORE :: EXPD8 :: FORCE_ACD_ON [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x4000,14)
#define BRPHY3_GPHY_CORE_EXPD8_FORCE_ACD_ON_MASK                   0x4000
#define BRPHY3_GPHY_CORE_EXPD8_FORCE_ACD_ON_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPD8_FORCE_ACD_ON_BITS                   1
#define BRPHY3_GPHY_CORE_EXPD8_FORCE_ACD_ON_SHIFT                  14

/* BRPHY3_GPHY_CORE :: EXPD8 :: ACD_PHASE_SEL [13:11] */
#define Wr_BRPHY3_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x3800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x3800,11)
#define BRPHY3_GPHY_CORE_EXPD8_ACD_PHASE_SEL_MASK                  0x3800
#define BRPHY3_GPHY_CORE_EXPD8_ACD_PHASE_SEL_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXPD8_ACD_PHASE_SEL_BITS                  3
#define BRPHY3_GPHY_CORE_EXPD8_ACD_PHASE_SEL_SHIFT                 11

/* BRPHY3_GPHY_CORE :: EXPD8 :: AGC_FSCALE [10:09] */
#define Wr_BRPHY3_GPHY_CORE_EXPD8_AGC_FSCALE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x600,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPD8_AGC_FSCALE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x600,9)
#define BRPHY3_GPHY_CORE_EXPD8_AGC_FSCALE_MASK                     0x0600
#define BRPHY3_GPHY_CORE_EXPD8_AGC_FSCALE_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPD8_AGC_FSCALE_BITS                     2
#define BRPHY3_GPHY_CORE_EXPD8_AGC_FSCALE_SHIFT                    9

/* BRPHY3_GPHY_CORE :: EXPD8 :: STOP_AGC_AFTER_LINK [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x100,8)
#define BRPHY3_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_MASK            0x0100
#define BRPHY3_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_ALIGN           0
#define BRPHY3_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_BITS            1
#define BRPHY3_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_SHIFT           8

/* BRPHY3_GPHY_CORE :: EXPD8 :: UPDATE_FROM_FFE_EN [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x80,7)
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_MASK             0x0080
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_BITS             1
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_SHIFT            7

/* BRPHY3_GPHY_CORE :: EXPD8 :: UPDATE_AGC_WHEN_IDLE [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x40,6)
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_MASK           0x0040
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_BITS           1
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_SHIFT          6

/* BRPHY3_GPHY_CORE :: EXPD8 :: UPDATE_ENC_WHEN_IDLE [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x20,5)
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_MASK           0x0020
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_BITS           1
#define BRPHY3_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_SHIFT          5

/* BRPHY3_GPHY_CORE :: EXPD8 :: FFE_DYN_THD [04:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPD8_FFE_DYN_THD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x1f,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPD8_FFE_DYN_THD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPD8,0x1f,0)
#define BRPHY3_GPHY_CORE_EXPD8_FFE_DYN_THD_MASK                    0x001f
#define BRPHY3_GPHY_CORE_EXPD8_FFE_DYN_THD_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPD8_FFE_DYN_THD_BITS                    5
#define BRPHY3_GPHY_CORE_EXPD8_FFE_DYN_THD_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPF0
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPF0 :: IBS_RX_SEND [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXPF0_IBS_RX_SEND(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF0_IBS_RX_SEND(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x8000,15)
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RX_SEND_MASK                    0x8000
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RX_SEND_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RX_SEND_BITS                    1
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RX_SEND_SHIFT                   15

/* BRPHY3_GPHY_CORE :: EXPF0 :: IBS_TX_EN [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPF0_IBS_TX_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF0_IBS_TX_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x4000,14)
#define BRPHY3_GPHY_CORE_EXPF0_IBS_TX_EN_MASK                      0x4000
#define BRPHY3_GPHY_CORE_EXPF0_IBS_TX_EN_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPF0_IBS_TX_EN_BITS                      1
#define BRPHY3_GPHY_CORE_EXPF0_IBS_TX_EN_SHIFT                     14

/* BRPHY3_GPHY_CORE :: EXPF0 :: IBS_RXCLK_OV_EN [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x2000,13)
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_MASK                0x2000
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_BITS                1
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_SHIFT               13

/* BRPHY3_GPHY_CORE :: EXPF0 :: IBS_RXCLK_SW_OV [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_MASK                0x1000
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_BITS                1
#define BRPHY3_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_SHIFT               12

/* BRPHY3_GPHY_CORE :: EXPF0 :: reserved0 [11:05] */
#define BRPHY3_GPHY_CORE_EXPF0_RESERVED0_MASK                      0x0fe0
#define BRPHY3_GPHY_CORE_EXPF0_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPF0_RESERVED0_BITS                      7
#define BRPHY3_GPHY_CORE_EXPF0_RESERVED0_SHIFT                     5

/* BRPHY3_GPHY_CORE :: EXPF0 :: IBS_PWRDN [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x10,4)
#define BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_MASK                      0x0010
#define BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_BITS                      1
#define BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_SHIFT                     4

/* BRPHY3_GPHY_CORE :: EXPF0 :: IBS_PWRDN_SD [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x8,3)
#define BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_SD_MASK                   0x0008
#define BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_SD_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_SD_BITS                   1
#define BRPHY3_GPHY_CORE_EXPF0_IBS_PWRDN_SD_SHIFT                  3

/* BRPHY3_GPHY_CORE :: EXPF0 :: IBS_AUTO_PWRDN [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x4,2)
#define BRPHY3_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_MASK                 0x0004
#define BRPHY3_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_BITS                 1
#define BRPHY3_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_SHIFT                2

/* BRPHY3_GPHY_CORE :: EXPF0 :: IBS_EARLY_DAC_WAKE [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x2,1)
#define BRPHY3_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_MASK             0x0002
#define BRPHY3_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_BITS             1
#define BRPHY3_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_SHIFT            1

/* BRPHY3_GPHY_CORE :: EXPF0 :: IBS_CK25_DIS [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF0,0x1,0)
#define BRPHY3_GPHY_CORE_EXPF0_IBS_CK25_DIS_MASK                   0x0001
#define BRPHY3_GPHY_CORE_EXPF0_IBS_CK25_DIS_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPF0_IBS_CK25_DIS_BITS                   1
#define BRPHY3_GPHY_CORE_EXPF0_IBS_CK25_DIS_SHIFT                  0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPF5
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_COPPER [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x8000,15)
#define BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_MASK           0x8000
#define BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_BITS           1
#define BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_SHIFT          15

/* BRPHY3_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_FIBER [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x4000,14)
#define BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_MASK            0x4000
#define BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_ALIGN           0
#define BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_BITS            1
#define BRPHY3_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_SHIFT           14

/* BRPHY3_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_COPPER [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x2000,13)
#define BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_MASK           0x2000
#define BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_BITS           1
#define BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_SHIFT          13

/* BRPHY3_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_FIBER [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_MASK            0x1000
#define BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_ALIGN           0
#define BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_BITS            1
#define BRPHY3_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_SHIFT           12

/* BRPHY3_GPHY_CORE :: EXPF5 :: RX_SOP_SEL [11:10] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0xc00,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0xc00,10)
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_MASK                     0x0c00
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_BITS                     2
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_SHIFT                    10

/* BRPHY3_GPHY_CORE :: EXPF5 :: RX_SOP_SEL_OV [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x200,9)
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_MASK                  0x0200
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_BITS                  1
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_SHIFT                 9

/* BRPHY3_GPHY_CORE :: EXPF5 :: TX_SOP_10BT_ENABLE [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x100,8)
#define BRPHY3_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_MASK             0x0100
#define BRPHY3_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_BITS             1
#define BRPHY3_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_SHIFT            8

/* BRPHY3_GPHY_CORE :: EXPF5 :: RX_SOP_10BT_ENABLE [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x80,7)
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_MASK             0x0080
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_BITS             1
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_SHIFT            7

/* BRPHY3_GPHY_CORE :: EXPF5 :: TX_SOP_ERR_STATUS [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x40,6)
#define BRPHY3_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_MASK              0x0040
#define BRPHY3_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_BITS              1
#define BRPHY3_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_SHIFT             6

/* BRPHY3_GPHY_CORE :: EXPF5 :: USE_TXEN_TX_SOP [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x20,5)
#define BRPHY3_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_MASK                0x0020
#define BRPHY3_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_BITS                1
#define BRPHY3_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_SHIFT               5

/* BRPHY3_GPHY_CORE :: EXPF5 :: RX_SOP_ERR_STATUS [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x10,4)
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_MASK              0x0010
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_BITS              1
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_SHIFT             4

/* BRPHY3_GPHY_CORE :: EXPF5 :: RX_SOP_OPTION [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x8,3)
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_OPTION_MASK                  0x0008
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_OPTION_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_OPTION_BITS                  1
#define BRPHY3_GPHY_CORE_EXPF5_RX_SOP_OPTION_SHIFT                 3

/* BRPHY3_GPHY_CORE :: EXPF5 :: USE_RXDV_RX_SOP [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x4,2)
#define BRPHY3_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_MASK                0x0004
#define BRPHY3_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_BITS                1
#define BRPHY3_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_SHIFT               2

/* BRPHY3_GPHY_CORE :: EXPF5 :: RECOVERY_CLK_SEL [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x2,1)
#define BRPHY3_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_MASK               0x0002
#define BRPHY3_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_BITS               1
#define BRPHY3_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_SHIFT              1

/* BRPHY3_GPHY_CORE :: EXPF5 :: TIMESYNC_EN [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPF5_TIMESYNC_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF5_TIMESYNC_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF5,0x1,0)
#define BRPHY3_GPHY_CORE_EXPF5_TIMESYNC_EN_MASK                    0x0001
#define BRPHY3_GPHY_CORE_EXPF5_TIMESYNC_EN_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPF5_TIMESYNC_EN_BITS                    1
#define BRPHY3_GPHY_CORE_EXPF5_TIMESYNC_EN_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPF6
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPF6 :: reserved0 [15:15] */
#define BRPHY3_GPHY_CORE_EXPF6_RESERVED0_MASK                      0x8000
#define BRPHY3_GPHY_CORE_EXPF6_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPF6_RESERVED0_BITS                      1
#define BRPHY3_GPHY_CORE_EXPF6_RESERVED0_SHIFT                     15

/* BRPHY3_GPHY_CORE :: EXPF6 :: PWRDN_DLL [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPF6_PWRDN_DLL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF6,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF6_PWRDN_DLL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF6,0x4000,14)
#define BRPHY3_GPHY_CORE_EXPF6_PWRDN_DLL_MASK                      0x4000
#define BRPHY3_GPHY_CORE_EXPF6_PWRDN_DLL_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPF6_PWRDN_DLL_BITS                      1
#define BRPHY3_GPHY_CORE_EXPF6_PWRDN_DLL_SHIFT                     14

/* BRPHY3_GPHY_CORE :: EXPF6 :: PWRDNBT_DLL [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF6,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF6,0x2000,13)
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNBT_DLL_MASK                    0x2000
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNBT_DLL_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNBT_DLL_BITS                    1
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNBT_DLL_SHIFT                   13

/* BRPHY3_GPHY_CORE :: EXPF6 :: COMMON_PWROFF [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPF6_COMMON_PWROFF(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF6,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF6_COMMON_PWROFF(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF6,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPF6_COMMON_PWROFF_MASK                  0x1000
#define BRPHY3_GPHY_CORE_EXPF6_COMMON_PWROFF_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXPF6_COMMON_PWROFF_BITS                  1
#define BRPHY3_GPHY_CORE_EXPF6_COMMON_PWROFF_SHIFT                 12

/* BRPHY3_GPHY_CORE :: EXPF6 :: PWRDN_SD [11:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPF6_PWRDN_SD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF6,0xf00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF6_PWRDN_SD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF6,0xf00,8)
#define BRPHY3_GPHY_CORE_EXPF6_PWRDN_SD_MASK                       0x0f00
#define BRPHY3_GPHY_CORE_EXPF6_PWRDN_SD_ALIGN                      0
#define BRPHY3_GPHY_CORE_EXPF6_PWRDN_SD_BITS                       4
#define BRPHY3_GPHY_CORE_EXPF6_PWRDN_SD_SHIFT                      8

/* BRPHY3_GPHY_CORE :: EXPF6 :: PWRDNRX [07:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPF6_PWRDNRX(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF6,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF6_PWRDNRX(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF6,0xf0,4)
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNRX_MASK                        0x00f0
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNRX_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNRX_BITS                        4
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNRX_SHIFT                       4

/* BRPHY3_GPHY_CORE :: EXPF6 :: PWRDNTX [03:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPF6_PWRDNTX(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF6,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF6_PWRDNTX(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF6,0xf,0)
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNTX_MASK                        0x000f
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNTX_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNTX_BITS                        4
#define BRPHY3_GPHY_CORE_EXPF6_PWRDNTX_SHIFT                       0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPF7
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPF7 :: reserved0 [15:14] */
#define BRPHY3_GPHY_CORE_EXPF7_RESERVED0_MASK                      0xc000
#define BRPHY3_GPHY_CORE_EXPF7_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPF7_RESERVED0_BITS                      2
#define BRPHY3_GPHY_CORE_EXPF7_RESERVED0_SHIFT                     14

/* BRPHY3_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_DPWR [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x2000,13)
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_MASK              0x2000
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_BITS              1
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_SHIFT             13

/* BRPHY3_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_APWR [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_MASK              0x1000
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_BITS              1
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_SHIFT             12

/* BRPHY3_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_DPWR [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x800,11)
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_MASK              0x0800
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_BITS              1
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_SHIFT             11

/* BRPHY3_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_APWR [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x400,10)
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_MASK              0x0400
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_BITS              1
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_SHIFT             10

/* BRPHY3_GPHY_CORE :: EXPF7 :: R0PWRDN_DPWR [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x200,9)
#define BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_DPWR_MASK                   0x0200
#define BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_DPWR_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_DPWR_BITS                   1
#define BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_DPWR_SHIFT                  9

/* BRPHY3_GPHY_CORE :: EXPF7 :: R0PWRDN_APWR [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x100,8)
#define BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_APWR_MASK                   0x0100
#define BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_APWR_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_APWR_BITS                   1
#define BRPHY3_GPHY_CORE_EXPF7_R0PWRDN_APWR_SHIFT                  8

/* BRPHY3_GPHY_CORE :: EXPF7 :: AUTO_PWRDN_DLL [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x80,7)
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_MASK                 0x0080
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_BITS                 1
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_SHIFT                7

/* BRPHY3_GPHY_CORE :: EXPF7 :: PWRDN_DPWR_EARLY_INT [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x40,6)
#define BRPHY3_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_MASK           0x0040
#define BRPHY3_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_BITS           1
#define BRPHY3_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_SHIFT          6

/* BRPHY3_GPHY_CORE :: EXPF7 :: REAL_ENERGY [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_REAL_ENERGY(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_REAL_ENERGY(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x20,5)
#define BRPHY3_GPHY_CORE_EXPF7_REAL_ENERGY_MASK                    0x0020
#define BRPHY3_GPHY_CORE_EXPF7_REAL_ENERGY_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPF7_REAL_ENERGY_BITS                    1
#define BRPHY3_GPHY_CORE_EXPF7_REAL_ENERGY_SHIFT                   5

/* BRPHY3_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_RAW [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x10,4)
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_MASK               0x0010
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_BITS               1
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_SHIFT              4

/* BRPHY3_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_RAW [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x8,3)
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_MASK               0x0008
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_BITS               1
#define BRPHY3_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_SHIFT              3

/* BRPHY3_GPHY_CORE :: EXPF7 :: CUR_STATE [02:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPF7_CUR_STATE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x7,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF7_CUR_STATE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF7,0x7,0)
#define BRPHY3_GPHY_CORE_EXPF7_CUR_STATE_MASK                      0x0007
#define BRPHY3_GPHY_CORE_EXPF7_CUR_STATE_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPF7_CUR_STATE_BITS                      3
#define BRPHY3_GPHY_CORE_EXPF7_CUR_STATE_SHIFT                     0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPF8
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPF8 :: TRIM_DAC_FROM_FUSE [15:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF8,0xf000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF8,0xf000,12)
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_MASK             0xf000
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_BITS             4
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_SHIFT            12

/* BRPHY3_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_FROM_FUSE [11:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF8,0xf00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF8,0xf00,8)
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_MASK          0x0f00
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_ALIGN         0
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_BITS          4
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_SHIFT         8

/* BRPHY3_GPHY_CORE :: EXPF8 :: TRIM_DAC_TO_BIAS_BLOCK [07:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF8,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF8,0xf0,4)
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_MASK         0x00f0
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_ALIGN        0
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_BITS         4
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_SHIFT        4

/* BRPHY3_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_TO_BIAS_BLOCK [03:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF8,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF8,0xf,0)
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_MASK      0x000f
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_ALIGN     0
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_BITS      4
#define BRPHY3_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_SHIFT     0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPF9
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPF9 :: EXT_CTL [15:11] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_EXT_CTL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0xf800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_EXT_CTL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0xf800,11)
#define BRPHY3_GPHY_CORE_EXPF9_EXT_CTL_MASK                        0xf800
#define BRPHY3_GPHY_CORE_EXPF9_EXT_CTL_ALIGN                       0
#define BRPHY3_GPHY_CORE_EXPF9_EXT_CTL_BITS                        5
#define BRPHY3_GPHY_CORE_EXPF9_EXT_CTL_SHIFT                       11

/* BRPHY3_GPHY_CORE :: EXPF9 :: BT_NIBBLE_VAL [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x400,10)
#define BRPHY3_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_MASK                  0x0400
#define BRPHY3_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_BITS                  1
#define BRPHY3_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_SHIFT                 10

/* BRPHY3_GPHY_CORE :: EXPF9 :: BT_DRIB_RMV [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x200,9)
#define BRPHY3_GPHY_CORE_EXPF9_BT_DRIB_RMV_MASK                    0x0200
#define BRPHY3_GPHY_CORE_EXPF9_BT_DRIB_RMV_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPF9_BT_DRIB_RMV_BITS                    1
#define BRPHY3_GPHY_CORE_EXPF9_BT_DRIB_RMV_SHIFT                   9

/* BRPHY3_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_MDIX_EN [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x100,8)
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_MASK          0x0100
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_ALIGN         0
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_BITS          1
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_SHIFT         8

/* BRPHY3_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SEED_EN [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x80,7)
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_MASK          0x0080
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_ALIGN         0
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_BITS          1
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_SHIFT         7

/* BRPHY3_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_EN [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x40,6)
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_MASK               0x0040
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_BITS               1
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_SHIFT              6

/* BRPHY3_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SIG [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x20,5)
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_MASK              0x0020
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_BITS              1
#define BRPHY3_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_SHIFT             5

/* BRPHY3_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_VAL [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x10,4)
#define BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_MASK          0x0010
#define BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_ALIGN         0
#define BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_BITS          1
#define BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_SHIFT         4

/* BRPHY3_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_EN [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x8,3)
#define BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_MASK           0x0008
#define BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_BITS           1
#define BRPHY3_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_SHIFT          3

/* BRPHY3_GPHY_CORE :: EXPF9 :: ABIST_INF_CONV [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x4,2)
#define BRPHY3_GPHY_CORE_EXPF9_ABIST_INF_CONV_MASK                 0x0004
#define BRPHY3_GPHY_CORE_EXPF9_ABIST_INF_CONV_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPF9_ABIST_INF_CONV_BITS                 1
#define BRPHY3_GPHY_CORE_EXPF9_ABIST_INF_CONV_SHIFT                2

/* BRPHY3_GPHY_CORE :: EXPF9 :: GIGA_ONLY_HALFOUT [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x2,1)
#define BRPHY3_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_MASK              0x0002
#define BRPHY3_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_BITS              1
#define BRPHY3_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_SHIFT             1

/* BRPHY3_GPHY_CORE :: EXPF9 :: SPARE_REG0 [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPF9_SPARE_REG0(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPF9_SPARE_REG0(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPF9,0x1,0)
#define BRPHY3_GPHY_CORE_EXPF9_SPARE_REG0_MASK                     0x0001
#define BRPHY3_GPHY_CORE_EXPF9_SPARE_REG0_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPF9_SPARE_REG0_BITS                     1
#define BRPHY3_GPHY_CORE_EXPF9_SPARE_REG0_SHIFT                    0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPFA
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPFA :: reserved0 [15:04] */
#define BRPHY3_GPHY_CORE_EXPFA_RESERVED0_MASK                      0xfff0
#define BRPHY3_GPHY_CORE_EXPFA_RESERVED0_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPFA_RESERVED0_BITS                      12
#define BRPHY3_GPHY_CORE_EXPFA_RESERVED0_SHIFT                     4

/* BRPHY3_GPHY_CORE :: EXPFA :: HIDDEN_REV_NUM [03:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFA,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFA,0xf,0)
#define BRPHY3_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_MASK                 0x000f
#define BRPHY3_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_BITS                 4
#define BRPHY3_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_SHIFT                0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPFB
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPFB :: TEST_IDDQCLKBIAS [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x8000,15)
#define BRPHY3_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_MASK               0x8000
#define BRPHY3_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_BITS               1
#define BRPHY3_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_SHIFT              15

/* BRPHY3_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x4000,14)
#define BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_MASK                 0x4000
#define BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_BITS                 1
#define BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_SHIFT                14

/* BRPHY3_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV_VAL [13:10] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x3c00,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x3c00,10)
#define BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_MASK             0x3c00
#define BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_BITS             4
#define BRPHY3_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_SHIFT            10

/* BRPHY3_GPHY_CORE :: EXPFB :: TDR_SLAVE_DFE_CONV_VAL [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x200,9)
#define BRPHY3_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_MASK         0x0200
#define BRPHY3_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_ALIGN        0
#define BRPHY3_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_BITS         1
#define BRPHY3_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_SHIFT        9

/* BRPHY3_GPHY_CORE :: EXPFB :: FEXT_INPUTS_OV [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x100,8)
#define BRPHY3_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_MASK                 0x0100
#define BRPHY3_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_BITS                 1
#define BRPHY3_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_SHIFT                8

/* BRPHY3_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_OV [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x80,7)
#define BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_MASK               0x0080
#define BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_BITS               1
#define BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_SHIFT              7

/* BRPHY3_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_VAL [06:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x60,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x60,5)
#define BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_MASK              0x0060
#define BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_BITS              2
#define BRPHY3_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_SHIFT             5

/* BRPHY3_GPHY_CORE :: EXPFB :: LINK_DET_OV [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_LINK_DET_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_LINK_DET_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x10,4)
#define BRPHY3_GPHY_CORE_EXPFB_LINK_DET_OV_MASK                    0x0010
#define BRPHY3_GPHY_CORE_EXPFB_LINK_DET_OV_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPFB_LINK_DET_OV_BITS                    1
#define BRPHY3_GPHY_CORE_EXPFB_LINK_DET_OV_SHIFT                   4

/* BRPHY3_GPHY_CORE :: EXPFB :: LINK_DET_VAL [03:02] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_LINK_DET_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0xc,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_LINK_DET_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0xc,2)
#define BRPHY3_GPHY_CORE_EXPFB_LINK_DET_VAL_MASK                   0x000c
#define BRPHY3_GPHY_CORE_EXPFB_LINK_DET_VAL_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPFB_LINK_DET_VAL_BITS                   2
#define BRPHY3_GPHY_CORE_EXPFB_LINK_DET_VAL_SHIFT                  2

/* BRPHY3_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_OV [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x2,1)
#define BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_MASK               0x0002
#define BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_BITS               1
#define BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_SHIFT              1

/* BRPHY3_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_VAL [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFB,0x1,0)
#define BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_MASK              0x0001
#define BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_BITS              1
#define BRPHY3_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_SHIFT             0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPFC
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPFC :: PASSIVE_TERM_OV [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x8000,15)
#define BRPHY3_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_MASK                0x8000
#define BRPHY3_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_BITS                1
#define BRPHY3_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_SHIFT               15

/* BRPHY3_GPHY_CORE :: EXPFC :: APD_CLKOFF_OV [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x4000,14)
#define BRPHY3_GPHY_CORE_EXPFC_APD_CLKOFF_OV_MASK                  0x4000
#define BRPHY3_GPHY_CORE_EXPFC_APD_CLKOFF_OV_ALIGN                 0
#define BRPHY3_GPHY_CORE_EXPFC_APD_CLKOFF_OV_BITS                  1
#define BRPHY3_GPHY_CORE_EXPFC_APD_CLKOFF_OV_SHIFT                 14

/* BRPHY3_GPHY_CORE :: EXPFC :: TDR_TSD_PTE_OV_VAL_CHD [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x2000,13)
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_MASK         0x2000
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_ALIGN        0
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_BITS         1
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_SHIFT        13

/* BRPHY3_GPHY_CORE :: EXPFC :: TDR_TSC_PTE_OV_VAL_CHC [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_MASK         0x1000
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_ALIGN        0
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_BITS         1
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_SHIFT        12

/* BRPHY3_GPHY_CORE :: EXPFC :: TDR_TSB_PTE_OV_VAL_CHB [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x800,11)
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_MASK         0x0800
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_ALIGN        0
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_BITS         1
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_SHIFT        11

/* BRPHY3_GPHY_CORE :: EXPFC :: TDR_TSA_PTE_OV_VAL_CHA [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x400,10)
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_MASK         0x0400
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_ALIGN        0
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_BITS         1
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_SHIFT        10

/* BRPHY3_GPHY_CORE :: EXPFC :: TDR_TS_EN_OV [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x200,9)
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TS_EN_OV_MASK                   0x0200
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TS_EN_OV_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TS_EN_OV_BITS                   1
#define BRPHY3_GPHY_CORE_EXPFC_TDR_TS_EN_OV_SHIFT                  9

/* BRPHY3_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x100,8)
#define BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_MASK                   0x0100
#define BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_BITS                   1
#define BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_SHIFT                  8

/* BRPHY3_GPHY_CORE :: EXPFC :: BASET_DLL_CLK_OV_VAL [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x80,7)
#define BRPHY3_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_MASK           0x0080
#define BRPHY3_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_ALIGN          0
#define BRPHY3_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_BITS           1
#define BRPHY3_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_SHIFT          7

/* BRPHY3_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV_VAL [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x40,6)
#define BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_MASK               0x0040
#define BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_BITS               1
#define BRPHY3_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_SHIFT              6

/* BRPHY3_GPHY_CORE :: EXPFC :: AUTONEG_1000T_CLK_GATING_DIS [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x20,5)
#define BRPHY3_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_MASK   0x0020
#define BRPHY3_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_ALIGN  0
#define BRPHY3_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_BITS   1
#define BRPHY3_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_SHIFT  5

/* BRPHY3_GPHY_CORE :: EXPFC :: AUTONEG_10BT_LP_DIS [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x10,4)
#define BRPHY3_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_MASK            0x0010
#define BRPHY3_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_ALIGN           0
#define BRPHY3_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_BITS            1
#define BRPHY3_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_SHIFT           4

/* BRPHY3_GPHY_CORE :: EXPFC :: AUTO_PWRDN_CLK_OFF_OV_VAL [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x8,3)
#define BRPHY3_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_MASK      0x0008
#define BRPHY3_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_ALIGN     0
#define BRPHY3_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_BITS      1
#define BRPHY3_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_SHIFT     3

/* BRPHY3_GPHY_CORE :: EXPFC :: LP1000_DIS [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_LP1000_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_LP1000_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x4,2)
#define BRPHY3_GPHY_CORE_EXPFC_LP1000_DIS_MASK                     0x0004
#define BRPHY3_GPHY_CORE_EXPFC_LP1000_DIS_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPFC_LP1000_DIS_BITS                     1
#define BRPHY3_GPHY_CORE_EXPFC_LP1000_DIS_SHIFT                    2

/* BRPHY3_GPHY_CORE :: EXPFC :: LP100_DIS [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_LP100_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_LP100_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x2,1)
#define BRPHY3_GPHY_CORE_EXPFC_LP100_DIS_MASK                      0x0002
#define BRPHY3_GPHY_CORE_EXPFC_LP100_DIS_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPFC_LP100_DIS_BITS                      1
#define BRPHY3_GPHY_CORE_EXPFC_LP100_DIS_SHIFT                     1

/* BRPHY3_GPHY_CORE :: EXPFC :: LP10_DIABLE [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPFC_LP10_DIABLE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFC_LP10_DIABLE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFC,0x1,0)
#define BRPHY3_GPHY_CORE_EXPFC_LP10_DIABLE_MASK                    0x0001
#define BRPHY3_GPHY_CORE_EXPFC_LP10_DIABLE_ALIGN                   0
#define BRPHY3_GPHY_CORE_EXPFC_LP10_DIABLE_BITS                    1
#define BRPHY3_GPHY_CORE_EXPFC_LP10_DIABLE_SHIFT                   0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPFD
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPFD :: SPARE_REG [15:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0xe000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0xe000,13)
#define BRPHY3_GPHY_CORE_EXPFD_SPARE_REG_MASK                      0xe000
#define BRPHY3_GPHY_CORE_EXPFD_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPFD_SPARE_REG_BITS                      3
#define BRPHY3_GPHY_CORE_EXPFD_SPARE_REG_SHIFT                     13

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x800,11)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x400,10)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x200,9)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_BITS               1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x100,8)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_BITS               1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x80,7)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x40,6)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x20,5)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x10,4)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x8,3)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x4,2)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x2,1)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_BITS                1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY3_GPHY_CORE :: EXPFD :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFD,0x1,0)
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_BITS               1
#define BRPHY3_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPFE
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPFE :: SPARE_REG [15:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_SPARE_REG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0xc000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_SPARE_REG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0xc000,14)
#define BRPHY3_GPHY_CORE_EXPFE_SPARE_REG_MASK                      0xc000
#define BRPHY3_GPHY_CORE_EXPFE_SPARE_REG_ALIGN                     0
#define BRPHY3_GPHY_CORE_EXPFE_SPARE_REG_BITS                      2
#define BRPHY3_GPHY_CORE_EXPFE_SPARE_REG_SHIFT                     14

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_DFE_LPI_EN [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x2000,13)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_MASK              0x2000
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_BITS              1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_SHIFT             13

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x800,11,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x800,11)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x400,10,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x400,10)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x200,9,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x200,9)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_BITS               1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x100,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x100,8)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_BITS               1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x80,7,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x80,7)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x40,6,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x40,6)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x20,5,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x20,5)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x10,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x10,4)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x8,3,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x8,3)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x4,2,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x4,2)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x2,1,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x2,1)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_BITS                1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY3_GPHY_CORE :: EXPFE :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x1,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFE,0x1,0)
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_BITS               1
#define BRPHY3_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY3_GPHY_CORE :: EXPFF
 ***************************************************************************/
/* BRPHY3_GPHY_CORE :: EXPFF :: PWRDN_SD_DIS [15:15] */
#define Wr_BRPHY3_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFF,0x8000,15,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFF,0x8000,15)
#define BRPHY3_GPHY_CORE_EXPFF_PWRDN_SD_DIS_MASK                   0x8000
#define BRPHY3_GPHY_CORE_EXPFF_PWRDN_SD_DIS_ALIGN                  0
#define BRPHY3_GPHY_CORE_EXPFF_PWRDN_SD_DIS_BITS                   1
#define BRPHY3_GPHY_CORE_EXPFF_PWRDN_SD_DIS_SHIFT                  15

/* BRPHY3_GPHY_CORE :: EXPFF :: PWRDNSD_OV [14:14] */
#define Wr_BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFF,0x4000,14,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFF,0x4000,14)
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_MASK                     0x4000
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_BITS                     1
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_SHIFT                    14

/* BRPHY3_GPHY_CORE :: EXPFF :: PWRDNTX_OV [13:13] */
#define Wr_BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFF,0x2000,13,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFF,0x2000,13)
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_MASK                     0x2000
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_BITS                     1
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_SHIFT                    13

/* BRPHY3_GPHY_CORE :: EXPFF :: PWRDNRX_OV [12:12] */
#define Wr_BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFF,0x1000,12,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFF,0x1000,12)
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_MASK                     0x1000
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_ALIGN                    0
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_BITS                     1
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_SHIFT                    12

/* BRPHY3_GPHY_CORE :: EXPFF :: PWRDNSD_OV_VAL [11:08] */
#define Wr_BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFF,0xf00,8,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFF,0xf00,8)
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_MASK                 0x0f00
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_BITS                 4
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_SHIFT                8

/* BRPHY3_GPHY_CORE :: EXPFF :: PWRDNTX_OV_VAL [07:04] */
#define Wr_BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFF,0xf0,4,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFF,0xf0,4)
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_MASK                 0x00f0
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_BITS                 4
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_SHIFT                4

/* BRPHY3_GPHY_CORE :: EXPFF :: PWRDNRX_OV_VAL [03:00] */
#define Wr_BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) WriteRegBits16(BRPHY3_GPHY_CORE_EXPFF,0xf,0,x)
#define Rd_BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) ReadRegBits16(BRPHY3_GPHY_CORE_EXPFF,0xf,0)
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_MASK                 0x000f
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_ALIGN                0
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_BITS                 4
#define BRPHY3_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_DSP_TAP
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP0_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP0_C0 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x8000,15)
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY3_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x4000,14)
#define BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY3_DSP_TAP :: TAP0_C0 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x2000,13)
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY3_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x1000,12)
#define BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY3_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY3_DSP_TAP :: TAP0_C0 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x800,11)
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_BITS                1
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY3_DSP_TAP :: TAP0_C0 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x700,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x700,8)
#define BRPHY3_DSP_TAP_TAP0_C0_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY3_DSP_TAP_TAP0_C0_BR_PGA_GAIN_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP0_C0_BR_PGA_GAIN_BITS                    3
#define BRPHY3_DSP_TAP_TAP0_C0_BR_PGA_GAIN_SHIFT                   8

/* BRPHY3_DSP_TAP :: TAP0_C0 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x80,7)
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_OV_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_OV_BITS                    1
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_OV_SHIFT                   7

/* BRPHY3_DSP_TAP :: TAP0_C0 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x7f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C0,0x7f,0)
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_BITS                 7
#define BRPHY3_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP0_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP0_C1 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x8000,15)
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY3_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x4000,14)
#define BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY3_DSP_TAP :: TAP0_C1 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x2000,13)
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY3_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x1000,12)
#define BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY3_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY3_DSP_TAP :: TAP0_C1 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x800,11)
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_BITS                1
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY3_DSP_TAP :: TAP0_C1 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x700,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x700,8)
#define BRPHY3_DSP_TAP_TAP0_C1_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY3_DSP_TAP_TAP0_C1_BR_PGA_GAIN_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP0_C1_BR_PGA_GAIN_BITS                    3
#define BRPHY3_DSP_TAP_TAP0_C1_BR_PGA_GAIN_SHIFT                   8

/* BRPHY3_DSP_TAP :: TAP0_C1 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x80,7)
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_OV_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_OV_BITS                    1
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_OV_SHIFT                   7

/* BRPHY3_DSP_TAP :: TAP0_C1 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x7f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C1,0x7f,0)
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_BITS                 7
#define BRPHY3_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP0_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP0_C2 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x8000,15)
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY3_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x4000,14)
#define BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY3_DSP_TAP :: TAP0_C2 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x2000,13)
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY3_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x1000,12)
#define BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY3_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY3_DSP_TAP :: TAP0_C2 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x800,11)
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_BITS                1
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY3_DSP_TAP :: TAP0_C2 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x700,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x700,8)
#define BRPHY3_DSP_TAP_TAP0_C2_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY3_DSP_TAP_TAP0_C2_BR_PGA_GAIN_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP0_C2_BR_PGA_GAIN_BITS                    3
#define BRPHY3_DSP_TAP_TAP0_C2_BR_PGA_GAIN_SHIFT                   8

/* BRPHY3_DSP_TAP :: TAP0_C2 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x80,7)
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_OV_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_OV_BITS                    1
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_OV_SHIFT                   7

/* BRPHY3_DSP_TAP :: TAP0_C2 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x7f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C2,0x7f,0)
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_BITS                 7
#define BRPHY3_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP0_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP0_C3 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x8000,15)
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY3_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x4000,14)
#define BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY3_DSP_TAP :: TAP0_C3 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x2000,13)
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY3_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x1000,12)
#define BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY3_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY3_DSP_TAP :: TAP0_C3 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x800,11)
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_BITS                1
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY3_DSP_TAP :: TAP0_C3 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x700,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x700,8)
#define BRPHY3_DSP_TAP_TAP0_C3_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY3_DSP_TAP_TAP0_C3_BR_PGA_GAIN_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP0_C3_BR_PGA_GAIN_BITS                    3
#define BRPHY3_DSP_TAP_TAP0_C3_BR_PGA_GAIN_SHIFT                   8

/* BRPHY3_DSP_TAP :: TAP0_C3 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x80,7)
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_OV_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_OV_BITS                    1
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_OV_SHIFT                   7

/* BRPHY3_DSP_TAP :: TAP0_C3 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x7f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP0_C3,0x7f,0)
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_BITS                 7
#define BRPHY3_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP1 :: reserved0 [15:14] */
#define BRPHY3_DSP_TAP_TAP1_RESERVED0_MASK                         0xc000
#define BRPHY3_DSP_TAP_TAP1_RESERVED0_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP1_RESERVED0_BITS                         2
#define BRPHY3_DSP_TAP_TAP1_RESERVED0_SHIFT                        14

/* BRPHY3_DSP_TAP :: TAP1 :: DIG_GAIN_LMS_MODE [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP1,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP1,0x2000,13)
#define BRPHY3_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_MASK                 0x2000
#define BRPHY3_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_BITS                 1
#define BRPHY3_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_SHIFT                13

/* BRPHY3_DSP_TAP :: TAP1 :: IPRF_K_OV_EN [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP1,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP1,0x1000,12)
#define BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_EN_MASK                      0x1000
#define BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_EN_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_EN_BITS                      1
#define BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_EN_SHIFT                     12

/* BRPHY3_DSP_TAP :: TAP1 :: IPRF_K_OV_VALUE [11:07] */
#define Wr_BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP1,0xf80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP1,0xf80,7)
#define BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_VALUE_MASK                   0x0f80
#define BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_VALUE_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_VALUE_BITS                   5
#define BRPHY3_DSP_TAP_TAP1_IPRF_K_OV_VALUE_SHIFT                  7

/* BRPHY3_DSP_TAP :: TAP1 :: GBT_AGC_TARGET_LVL [06:04] */
#define Wr_BRPHY3_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP1,0x70,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP1,0x70,4)
#define BRPHY3_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_MASK                0x0070
#define BRPHY3_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_ALIGN               0
#define BRPHY3_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_BITS                3
#define BRPHY3_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_SHIFT               4

/* BRPHY3_DSP_TAP :: TAP1 :: TX_AGC_TARGET_LVL [03:00] */
#define Wr_BRPHY3_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP1,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP1,0xf,0)
#define BRPHY3_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_MASK                 0x000f
#define BRPHY3_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_ALIGN                0
#define BRPHY3_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_BITS                 4
#define BRPHY3_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP2_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP2_C0 :: MSE [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP2_C0_MSE(x) WriteReg16(BRPHY3_DSP_TAP_TAP2_C0,x)
#define Rd_BRPHY3_DSP_TAP_TAP2_C0_MSE(x) ReadReg16(BRPHY3_DSP_TAP_TAP2_C0)
#define BRPHY3_DSP_TAP_TAP2_C0_MSE_MASK                            0xffff
#define BRPHY3_DSP_TAP_TAP2_C0_MSE_ALIGN                           0
#define BRPHY3_DSP_TAP_TAP2_C0_MSE_BITS                            16
#define BRPHY3_DSP_TAP_TAP2_C0_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP2_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP2_C1 :: MSE [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP2_C1_MSE(x) WriteReg16(BRPHY3_DSP_TAP_TAP2_C1,x)
#define Rd_BRPHY3_DSP_TAP_TAP2_C1_MSE(x) ReadReg16(BRPHY3_DSP_TAP_TAP2_C1)
#define BRPHY3_DSP_TAP_TAP2_C1_MSE_MASK                            0xffff
#define BRPHY3_DSP_TAP_TAP2_C1_MSE_ALIGN                           0
#define BRPHY3_DSP_TAP_TAP2_C1_MSE_BITS                            16
#define BRPHY3_DSP_TAP_TAP2_C1_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP2_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP2_C2 :: MSE [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP2_C2_MSE(x) WriteReg16(BRPHY3_DSP_TAP_TAP2_C2,x)
#define Rd_BRPHY3_DSP_TAP_TAP2_C2_MSE(x) ReadReg16(BRPHY3_DSP_TAP_TAP2_C2)
#define BRPHY3_DSP_TAP_TAP2_C2_MSE_MASK                            0xffff
#define BRPHY3_DSP_TAP_TAP2_C2_MSE_ALIGN                           0
#define BRPHY3_DSP_TAP_TAP2_C2_MSE_BITS                            16
#define BRPHY3_DSP_TAP_TAP2_C2_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP2_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP2_C3 :: MSE [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP2_C3_MSE(x) WriteReg16(BRPHY3_DSP_TAP_TAP2_C3,x)
#define Rd_BRPHY3_DSP_TAP_TAP2_C3_MSE(x) ReadReg16(BRPHY3_DSP_TAP_TAP2_C3)
#define BRPHY3_DSP_TAP_TAP2_C3_MSE_MASK                            0xffff
#define BRPHY3_DSP_TAP_TAP2_C3_MSE_ALIGN                           0
#define BRPHY3_DSP_TAP_TAP2_C3_MSE_BITS                            16
#define BRPHY3_DSP_TAP_TAP2_C3_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP3_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP3_C0 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP3_C0_SOFT_DECISION(x) WriteReg16(BRPHY3_DSP_TAP_TAP3_C0,x)
#define Rd_BRPHY3_DSP_TAP_TAP3_C0_SOFT_DECISION(x) ReadReg16(BRPHY3_DSP_TAP_TAP3_C0)
#define BRPHY3_DSP_TAP_TAP3_C0_SOFT_DECISION_MASK                  0xffff
#define BRPHY3_DSP_TAP_TAP3_C0_SOFT_DECISION_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP3_C0_SOFT_DECISION_BITS                  16
#define BRPHY3_DSP_TAP_TAP3_C0_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP3_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP3_C1 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP3_C1_SOFT_DECISION(x) WriteReg16(BRPHY3_DSP_TAP_TAP3_C1,x)
#define Rd_BRPHY3_DSP_TAP_TAP3_C1_SOFT_DECISION(x) ReadReg16(BRPHY3_DSP_TAP_TAP3_C1)
#define BRPHY3_DSP_TAP_TAP3_C1_SOFT_DECISION_MASK                  0xffff
#define BRPHY3_DSP_TAP_TAP3_C1_SOFT_DECISION_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP3_C1_SOFT_DECISION_BITS                  16
#define BRPHY3_DSP_TAP_TAP3_C1_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP3_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP3_C2 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP3_C2_SOFT_DECISION(x) WriteReg16(BRPHY3_DSP_TAP_TAP3_C2,x)
#define Rd_BRPHY3_DSP_TAP_TAP3_C2_SOFT_DECISION(x) ReadReg16(BRPHY3_DSP_TAP_TAP3_C2)
#define BRPHY3_DSP_TAP_TAP3_C2_SOFT_DECISION_MASK                  0xffff
#define BRPHY3_DSP_TAP_TAP3_C2_SOFT_DECISION_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP3_C2_SOFT_DECISION_BITS                  16
#define BRPHY3_DSP_TAP_TAP3_C2_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP3_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP3_C3 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP3_C3_SOFT_DECISION(x) WriteReg16(BRPHY3_DSP_TAP_TAP3_C3,x)
#define Rd_BRPHY3_DSP_TAP_TAP3_C3_SOFT_DECISION(x) ReadReg16(BRPHY3_DSP_TAP_TAP3_C3)
#define BRPHY3_DSP_TAP_TAP3_C3_SOFT_DECISION_MASK                  0xffff
#define BRPHY3_DSP_TAP_TAP3_C3_SOFT_DECISION_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP3_C3_SOFT_DECISION_BITS                  16
#define BRPHY3_DSP_TAP_TAP3_C3_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP4_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP4_C0 :: reserved0 [15:15] */
#define BRPHY3_DSP_TAP_TAP4_C0_RESERVED0_MASK                      0x8000
#define BRPHY3_DSP_TAP_TAP4_C0_RESERVED0_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C0_RESERVED0_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C0_RESERVED0_SHIFT                     15

/* BRPHY3_DSP_TAP :: TAP4_C0 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x7000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x7000,12)
#define BRPHY3_DSP_TAP_TAP4_C0_PAIR_OFFSET_MASK                    0x7000
#define BRPHY3_DSP_TAP_TAP4_C0_PAIR_OFFSET_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP4_C0_PAIR_OFFSET_BITS                    3
#define BRPHY3_DSP_TAP_TAP4_C0_PAIR_OFFSET_SHIFT                   12

/* BRPHY3_DSP_TAP :: TAP4_C0 :: GAMMA16 [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C0_GAMMA16(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C0_GAMMA16(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x800,11)
#define BRPHY3_DSP_TAP_TAP4_C0_GAMMA16_MASK                        0x0800
#define BRPHY3_DSP_TAP_TAP4_C0_GAMMA16_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP4_C0_GAMMA16_BITS                        1
#define BRPHY3_DSP_TAP_TAP4_C0_GAMMA16_SHIFT                       11

/* BRPHY3_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x400,10)
#define BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY3_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x200,9)
#define BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY3_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY3_DSP_TAP :: TAP4_C0 :: INC_PHASE [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C0_INC_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C0_INC_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x100,8)
#define BRPHY3_DSP_TAP_TAP4_C0_INC_PHASE_MASK                      0x0100
#define BRPHY3_DSP_TAP_TAP4_C0_INC_PHASE_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C0_INC_PHASE_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C0_INC_PHASE_SHIFT                     8

/* BRPHY3_DSP_TAP :: TAP4_C0 :: DEC_PHASE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C0_DEC_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C0_DEC_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x80,7)
#define BRPHY3_DSP_TAP_TAP4_C0_DEC_PHASE_MASK                      0x0080
#define BRPHY3_DSP_TAP_TAP4_C0_DEC_PHASE_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C0_DEC_PHASE_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C0_DEC_PHASE_SHIFT                     7

/* BRPHY3_DSP_TAP :: TAP4_C0 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x40,6)
#define BRPHY3_DSP_TAP_TAP4_C0_PHASE_FREEZE_MASK                   0x0040
#define BRPHY3_DSP_TAP_TAP4_C0_PHASE_FREEZE_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP4_C0_PHASE_FREEZE_BITS                   1
#define BRPHY3_DSP_TAP_TAP4_C0_PHASE_FREEZE_SHIFT                  6

/* BRPHY3_DSP_TAP :: TAP4_C0 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C0,0x3f,0)
#define BRPHY3_DSP_TAP_TAP4_C0_CURRENT_PHASE_MASK                  0x003f
#define BRPHY3_DSP_TAP_TAP4_C0_CURRENT_PHASE_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP4_C0_CURRENT_PHASE_BITS                  6
#define BRPHY3_DSP_TAP_TAP4_C0_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP4_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP4_C1 :: reserved0 [15:15] */
#define BRPHY3_DSP_TAP_TAP4_C1_RESERVED0_MASK                      0x8000
#define BRPHY3_DSP_TAP_TAP4_C1_RESERVED0_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C1_RESERVED0_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C1_RESERVED0_SHIFT                     15

/* BRPHY3_DSP_TAP :: TAP4_C1 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x7000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x7000,12)
#define BRPHY3_DSP_TAP_TAP4_C1_PAIR_OFFSET_MASK                    0x7000
#define BRPHY3_DSP_TAP_TAP4_C1_PAIR_OFFSET_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP4_C1_PAIR_OFFSET_BITS                    3
#define BRPHY3_DSP_TAP_TAP4_C1_PAIR_OFFSET_SHIFT                   12

/* BRPHY3_DSP_TAP :: TAP4_C1 :: GAMMA16 [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C1_GAMMA16(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C1_GAMMA16(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x800,11)
#define BRPHY3_DSP_TAP_TAP4_C1_GAMMA16_MASK                        0x0800
#define BRPHY3_DSP_TAP_TAP4_C1_GAMMA16_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP4_C1_GAMMA16_BITS                        1
#define BRPHY3_DSP_TAP_TAP4_C1_GAMMA16_SHIFT                       11

/* BRPHY3_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x400,10)
#define BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY3_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x200,9)
#define BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY3_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY3_DSP_TAP :: TAP4_C1 :: INC_PHASE [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C1_INC_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C1_INC_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x100,8)
#define BRPHY3_DSP_TAP_TAP4_C1_INC_PHASE_MASK                      0x0100
#define BRPHY3_DSP_TAP_TAP4_C1_INC_PHASE_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C1_INC_PHASE_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C1_INC_PHASE_SHIFT                     8

/* BRPHY3_DSP_TAP :: TAP4_C1 :: DEC_PHASE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C1_DEC_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C1_DEC_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x80,7)
#define BRPHY3_DSP_TAP_TAP4_C1_DEC_PHASE_MASK                      0x0080
#define BRPHY3_DSP_TAP_TAP4_C1_DEC_PHASE_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C1_DEC_PHASE_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C1_DEC_PHASE_SHIFT                     7

/* BRPHY3_DSP_TAP :: TAP4_C1 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x40,6)
#define BRPHY3_DSP_TAP_TAP4_C1_PHASE_FREEZE_MASK                   0x0040
#define BRPHY3_DSP_TAP_TAP4_C1_PHASE_FREEZE_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP4_C1_PHASE_FREEZE_BITS                   1
#define BRPHY3_DSP_TAP_TAP4_C1_PHASE_FREEZE_SHIFT                  6

/* BRPHY3_DSP_TAP :: TAP4_C1 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C1,0x3f,0)
#define BRPHY3_DSP_TAP_TAP4_C1_CURRENT_PHASE_MASK                  0x003f
#define BRPHY3_DSP_TAP_TAP4_C1_CURRENT_PHASE_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP4_C1_CURRENT_PHASE_BITS                  6
#define BRPHY3_DSP_TAP_TAP4_C1_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP4_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP4_C2 :: reserved0 [15:15] */
#define BRPHY3_DSP_TAP_TAP4_C2_RESERVED0_MASK                      0x8000
#define BRPHY3_DSP_TAP_TAP4_C2_RESERVED0_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C2_RESERVED0_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C2_RESERVED0_SHIFT                     15

/* BRPHY3_DSP_TAP :: TAP4_C2 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x7000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x7000,12)
#define BRPHY3_DSP_TAP_TAP4_C2_PAIR_OFFSET_MASK                    0x7000
#define BRPHY3_DSP_TAP_TAP4_C2_PAIR_OFFSET_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP4_C2_PAIR_OFFSET_BITS                    3
#define BRPHY3_DSP_TAP_TAP4_C2_PAIR_OFFSET_SHIFT                   12

/* BRPHY3_DSP_TAP :: TAP4_C2 :: GAMMA16 [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C2_GAMMA16(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C2_GAMMA16(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x800,11)
#define BRPHY3_DSP_TAP_TAP4_C2_GAMMA16_MASK                        0x0800
#define BRPHY3_DSP_TAP_TAP4_C2_GAMMA16_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP4_C2_GAMMA16_BITS                        1
#define BRPHY3_DSP_TAP_TAP4_C2_GAMMA16_SHIFT                       11

/* BRPHY3_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x400,10)
#define BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY3_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x200,9)
#define BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY3_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY3_DSP_TAP :: TAP4_C2 :: INC_PHASE [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C2_INC_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C2_INC_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x100,8)
#define BRPHY3_DSP_TAP_TAP4_C2_INC_PHASE_MASK                      0x0100
#define BRPHY3_DSP_TAP_TAP4_C2_INC_PHASE_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C2_INC_PHASE_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C2_INC_PHASE_SHIFT                     8

/* BRPHY3_DSP_TAP :: TAP4_C2 :: DEC_PHASE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C2_DEC_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C2_DEC_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x80,7)
#define BRPHY3_DSP_TAP_TAP4_C2_DEC_PHASE_MASK                      0x0080
#define BRPHY3_DSP_TAP_TAP4_C2_DEC_PHASE_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C2_DEC_PHASE_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C2_DEC_PHASE_SHIFT                     7

/* BRPHY3_DSP_TAP :: TAP4_C2 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x40,6)
#define BRPHY3_DSP_TAP_TAP4_C2_PHASE_FREEZE_MASK                   0x0040
#define BRPHY3_DSP_TAP_TAP4_C2_PHASE_FREEZE_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP4_C2_PHASE_FREEZE_BITS                   1
#define BRPHY3_DSP_TAP_TAP4_C2_PHASE_FREEZE_SHIFT                  6

/* BRPHY3_DSP_TAP :: TAP4_C2 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C2,0x3f,0)
#define BRPHY3_DSP_TAP_TAP4_C2_CURRENT_PHASE_MASK                  0x003f
#define BRPHY3_DSP_TAP_TAP4_C2_CURRENT_PHASE_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP4_C2_CURRENT_PHASE_BITS                  6
#define BRPHY3_DSP_TAP_TAP4_C2_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP4_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP4_C3 :: reserved0 [15:15] */
#define BRPHY3_DSP_TAP_TAP4_C3_RESERVED0_MASK                      0x8000
#define BRPHY3_DSP_TAP_TAP4_C3_RESERVED0_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C3_RESERVED0_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C3_RESERVED0_SHIFT                     15

/* BRPHY3_DSP_TAP :: TAP4_C3 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x7000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x7000,12)
#define BRPHY3_DSP_TAP_TAP4_C3_PAIR_OFFSET_MASK                    0x7000
#define BRPHY3_DSP_TAP_TAP4_C3_PAIR_OFFSET_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP4_C3_PAIR_OFFSET_BITS                    3
#define BRPHY3_DSP_TAP_TAP4_C3_PAIR_OFFSET_SHIFT                   12

/* BRPHY3_DSP_TAP :: TAP4_C3 :: GAMMA16 [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C3_GAMMA16(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C3_GAMMA16(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x800,11)
#define BRPHY3_DSP_TAP_TAP4_C3_GAMMA16_MASK                        0x0800
#define BRPHY3_DSP_TAP_TAP4_C3_GAMMA16_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP4_C3_GAMMA16_BITS                        1
#define BRPHY3_DSP_TAP_TAP4_C3_GAMMA16_SHIFT                       11

/* BRPHY3_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x400,10)
#define BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY3_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x200,9)
#define BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY3_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY3_DSP_TAP :: TAP4_C3 :: INC_PHASE [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C3_INC_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C3_INC_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x100,8)
#define BRPHY3_DSP_TAP_TAP4_C3_INC_PHASE_MASK                      0x0100
#define BRPHY3_DSP_TAP_TAP4_C3_INC_PHASE_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C3_INC_PHASE_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C3_INC_PHASE_SHIFT                     8

/* BRPHY3_DSP_TAP :: TAP4_C3 :: DEC_PHASE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C3_DEC_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C3_DEC_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x80,7)
#define BRPHY3_DSP_TAP_TAP4_C3_DEC_PHASE_MASK                      0x0080
#define BRPHY3_DSP_TAP_TAP4_C3_DEC_PHASE_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP4_C3_DEC_PHASE_BITS                      1
#define BRPHY3_DSP_TAP_TAP4_C3_DEC_PHASE_SHIFT                     7

/* BRPHY3_DSP_TAP :: TAP4_C3 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x40,6)
#define BRPHY3_DSP_TAP_TAP4_C3_PHASE_FREEZE_MASK                   0x0040
#define BRPHY3_DSP_TAP_TAP4_C3_PHASE_FREEZE_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP4_C3_PHASE_FREEZE_BITS                   1
#define BRPHY3_DSP_TAP_TAP4_C3_PHASE_FREEZE_SHIFT                  6

/* BRPHY3_DSP_TAP :: TAP4_C3 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP4_C3,0x3f,0)
#define BRPHY3_DSP_TAP_TAP4_C3_CURRENT_PHASE_MASK                  0x003f
#define BRPHY3_DSP_TAP_TAP4_C3_CURRENT_PHASE_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP4_C3_CURRENT_PHASE_BITS                  6
#define BRPHY3_DSP_TAP_TAP4_C3_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP5_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP5_C0 :: reserved0 [15:14] */
#define BRPHY3_DSP_TAP_TAP5_C0_RESERVED0_MASK                      0xc000
#define BRPHY3_DSP_TAP_TAP5_C0_RESERVED0_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP5_C0_RESERVED0_BITS                      2
#define BRPHY3_DSP_TAP_TAP5_C0_RESERVED0_SHIFT                     14

/* BRPHY3_DSP_TAP :: TAP5_C0 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_SLICE_ZERO(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_SLICE_ZERO(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x2000,13)
#define BRPHY3_DSP_TAP_TAP5_C0_SLICE_ZERO_MASK                     0x2000
#define BRPHY3_DSP_TAP_TAP5_C0_SLICE_ZERO_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP5_C0_SLICE_ZERO_BITS                     1
#define BRPHY3_DSP_TAP_TAP5_C0_SLICE_ZERO_SHIFT                    13

/* BRPHY3_DSP_TAP :: TAP5_C0 :: DISABLE_TX [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_DISABLE_TX(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_DISABLE_TX(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x1000,12)
#define BRPHY3_DSP_TAP_TAP5_C0_DISABLE_TX_MASK                     0x1000
#define BRPHY3_DSP_TAP_TAP5_C0_DISABLE_TX_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP5_C0_DISABLE_TX_BITS                     1
#define BRPHY3_DSP_TAP_TAP5_C0_DISABLE_TX_SHIFT                    12

/* BRPHY3_DSP_TAP :: TAP5_C0 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x800,11)
#define BRPHY3_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY3_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY3_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY3_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY3_DSP_TAP :: TAP5_C0 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x400,10)
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY3_DSP_TAP :: TAP5_C0 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x3c0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x3c0,6)
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_MASK                      0x03c0
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_BITS                      4
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SKEW_SHIFT                     6

/* BRPHY3_DSP_TAP :: TAP5_C0 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x20,5)
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_BITS              1
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY3_DSP_TAP :: TAP5_C0 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_PAIR_SELECT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x18,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_PAIR_SELECT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x18,3)
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SELECT_MASK                    0x0018
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SELECT_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SELECT_BITS                    2
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_SELECT_SHIFT                   3

/* BRPHY3_DSP_TAP :: TAP5_C0 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x4,2)
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_POLARITY_MASK                  0x0004
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_POLARITY_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_POLARITY_BITS                  1
#define BRPHY3_DSP_TAP_TAP5_C0_PAIR_POLARITY_SHIFT                 2

/* BRPHY3_DSP_TAP :: TAP5_C0 :: SWAPCD [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_SWAPCD(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_SWAPCD(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x2,1)
#define BRPHY3_DSP_TAP_TAP5_C0_SWAPCD_MASK                         0x0002
#define BRPHY3_DSP_TAP_TAP5_C0_SWAPCD_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP5_C0_SWAPCD_BITS                         1
#define BRPHY3_DSP_TAP_TAP5_C0_SWAPCD_SHIFT                        1

/* BRPHY3_DSP_TAP :: TAP5_C0 :: SWAPAB [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C0_SWAPAB(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C0_SWAPAB(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C0,0x1,0)
#define BRPHY3_DSP_TAP_TAP5_C0_SWAPAB_MASK                         0x0001
#define BRPHY3_DSP_TAP_TAP5_C0_SWAPAB_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP5_C0_SWAPAB_BITS                         1
#define BRPHY3_DSP_TAP_TAP5_C0_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP5_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP5_C1 :: reserved0 [15:14] */
#define BRPHY3_DSP_TAP_TAP5_C1_RESERVED0_MASK                      0xc000
#define BRPHY3_DSP_TAP_TAP5_C1_RESERVED0_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP5_C1_RESERVED0_BITS                      2
#define BRPHY3_DSP_TAP_TAP5_C1_RESERVED0_SHIFT                     14

/* BRPHY3_DSP_TAP :: TAP5_C1 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_SLICE_ZERO(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_SLICE_ZERO(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x2000,13)
#define BRPHY3_DSP_TAP_TAP5_C1_SLICE_ZERO_MASK                     0x2000
#define BRPHY3_DSP_TAP_TAP5_C1_SLICE_ZERO_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP5_C1_SLICE_ZERO_BITS                     1
#define BRPHY3_DSP_TAP_TAP5_C1_SLICE_ZERO_SHIFT                    13

/* BRPHY3_DSP_TAP :: TAP5_C1 :: DISABLE_TX [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_DISABLE_TX(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_DISABLE_TX(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x1000,12)
#define BRPHY3_DSP_TAP_TAP5_C1_DISABLE_TX_MASK                     0x1000
#define BRPHY3_DSP_TAP_TAP5_C1_DISABLE_TX_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP5_C1_DISABLE_TX_BITS                     1
#define BRPHY3_DSP_TAP_TAP5_C1_DISABLE_TX_SHIFT                    12

/* BRPHY3_DSP_TAP :: TAP5_C1 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x800,11)
#define BRPHY3_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY3_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY3_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY3_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY3_DSP_TAP :: TAP5_C1 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x400,10)
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY3_DSP_TAP :: TAP5_C1 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x3c0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x3c0,6)
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_MASK                      0x03c0
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_BITS                      4
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SKEW_SHIFT                     6

/* BRPHY3_DSP_TAP :: TAP5_C1 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x20,5)
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_BITS              1
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY3_DSP_TAP :: TAP5_C1 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_PAIR_SELECT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x18,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_PAIR_SELECT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x18,3)
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SELECT_MASK                    0x0018
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SELECT_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SELECT_BITS                    2
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_SELECT_SHIFT                   3

/* BRPHY3_DSP_TAP :: TAP5_C1 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x4,2)
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_POLARITY_MASK                  0x0004
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_POLARITY_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_POLARITY_BITS                  1
#define BRPHY3_DSP_TAP_TAP5_C1_PAIR_POLARITY_SHIFT                 2

/* BRPHY3_DSP_TAP :: TAP5_C1 :: SWAPCD [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_SWAPCD(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_SWAPCD(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x2,1)
#define BRPHY3_DSP_TAP_TAP5_C1_SWAPCD_MASK                         0x0002
#define BRPHY3_DSP_TAP_TAP5_C1_SWAPCD_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP5_C1_SWAPCD_BITS                         1
#define BRPHY3_DSP_TAP_TAP5_C1_SWAPCD_SHIFT                        1

/* BRPHY3_DSP_TAP :: TAP5_C1 :: SWAPAB [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C1_SWAPAB(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C1_SWAPAB(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C1,0x1,0)
#define BRPHY3_DSP_TAP_TAP5_C1_SWAPAB_MASK                         0x0001
#define BRPHY3_DSP_TAP_TAP5_C1_SWAPAB_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP5_C1_SWAPAB_BITS                         1
#define BRPHY3_DSP_TAP_TAP5_C1_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP5_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP5_C2 :: reserved0 [15:14] */
#define BRPHY3_DSP_TAP_TAP5_C2_RESERVED0_MASK                      0xc000
#define BRPHY3_DSP_TAP_TAP5_C2_RESERVED0_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP5_C2_RESERVED0_BITS                      2
#define BRPHY3_DSP_TAP_TAP5_C2_RESERVED0_SHIFT                     14

/* BRPHY3_DSP_TAP :: TAP5_C2 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_SLICE_ZERO(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_SLICE_ZERO(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x2000,13)
#define BRPHY3_DSP_TAP_TAP5_C2_SLICE_ZERO_MASK                     0x2000
#define BRPHY3_DSP_TAP_TAP5_C2_SLICE_ZERO_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP5_C2_SLICE_ZERO_BITS                     1
#define BRPHY3_DSP_TAP_TAP5_C2_SLICE_ZERO_SHIFT                    13

/* BRPHY3_DSP_TAP :: TAP5_C2 :: DISABLE_TX [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_DISABLE_TX(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_DISABLE_TX(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x1000,12)
#define BRPHY3_DSP_TAP_TAP5_C2_DISABLE_TX_MASK                     0x1000
#define BRPHY3_DSP_TAP_TAP5_C2_DISABLE_TX_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP5_C2_DISABLE_TX_BITS                     1
#define BRPHY3_DSP_TAP_TAP5_C2_DISABLE_TX_SHIFT                    12

/* BRPHY3_DSP_TAP :: TAP5_C2 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x800,11)
#define BRPHY3_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY3_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY3_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY3_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY3_DSP_TAP :: TAP5_C2 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x400,10)
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY3_DSP_TAP :: TAP5_C2 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x3c0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x3c0,6)
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_MASK                      0x03c0
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_BITS                      4
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SKEW_SHIFT                     6

/* BRPHY3_DSP_TAP :: TAP5_C2 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x20,5)
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_BITS              1
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY3_DSP_TAP :: TAP5_C2 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_PAIR_SELECT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x18,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_PAIR_SELECT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x18,3)
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SELECT_MASK                    0x0018
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SELECT_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SELECT_BITS                    2
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_SELECT_SHIFT                   3

/* BRPHY3_DSP_TAP :: TAP5_C2 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x4,2)
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_POLARITY_MASK                  0x0004
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_POLARITY_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_POLARITY_BITS                  1
#define BRPHY3_DSP_TAP_TAP5_C2_PAIR_POLARITY_SHIFT                 2

/* BRPHY3_DSP_TAP :: TAP5_C2 :: SWAPCD [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_SWAPCD(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_SWAPCD(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x2,1)
#define BRPHY3_DSP_TAP_TAP5_C2_SWAPCD_MASK                         0x0002
#define BRPHY3_DSP_TAP_TAP5_C2_SWAPCD_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP5_C2_SWAPCD_BITS                         1
#define BRPHY3_DSP_TAP_TAP5_C2_SWAPCD_SHIFT                        1

/* BRPHY3_DSP_TAP :: TAP5_C2 :: SWAPAB [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C2_SWAPAB(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C2_SWAPAB(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C2,0x1,0)
#define BRPHY3_DSP_TAP_TAP5_C2_SWAPAB_MASK                         0x0001
#define BRPHY3_DSP_TAP_TAP5_C2_SWAPAB_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP5_C2_SWAPAB_BITS                         1
#define BRPHY3_DSP_TAP_TAP5_C2_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP5_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP5_C3 :: reserved0 [15:14] */
#define BRPHY3_DSP_TAP_TAP5_C3_RESERVED0_MASK                      0xc000
#define BRPHY3_DSP_TAP_TAP5_C3_RESERVED0_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP5_C3_RESERVED0_BITS                      2
#define BRPHY3_DSP_TAP_TAP5_C3_RESERVED0_SHIFT                     14

/* BRPHY3_DSP_TAP :: TAP5_C3 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_SLICE_ZERO(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_SLICE_ZERO(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x2000,13)
#define BRPHY3_DSP_TAP_TAP5_C3_SLICE_ZERO_MASK                     0x2000
#define BRPHY3_DSP_TAP_TAP5_C3_SLICE_ZERO_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP5_C3_SLICE_ZERO_BITS                     1
#define BRPHY3_DSP_TAP_TAP5_C3_SLICE_ZERO_SHIFT                    13

/* BRPHY3_DSP_TAP :: TAP5_C3 :: DISABLE_TX [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_DISABLE_TX(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_DISABLE_TX(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x1000,12)
#define BRPHY3_DSP_TAP_TAP5_C3_DISABLE_TX_MASK                     0x1000
#define BRPHY3_DSP_TAP_TAP5_C3_DISABLE_TX_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP5_C3_DISABLE_TX_BITS                     1
#define BRPHY3_DSP_TAP_TAP5_C3_DISABLE_TX_SHIFT                    12

/* BRPHY3_DSP_TAP :: TAP5_C3 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x800,11)
#define BRPHY3_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY3_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY3_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY3_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY3_DSP_TAP :: TAP5_C3 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x400,10)
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY3_DSP_TAP :: TAP5_C3 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x3c0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x3c0,6)
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_MASK                      0x03c0
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_BITS                      4
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SKEW_SHIFT                     6

/* BRPHY3_DSP_TAP :: TAP5_C3 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x20,5)
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_BITS              1
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY3_DSP_TAP :: TAP5_C3 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_PAIR_SELECT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x18,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_PAIR_SELECT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x18,3)
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SELECT_MASK                    0x0018
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SELECT_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SELECT_BITS                    2
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_SELECT_SHIFT                   3

/* BRPHY3_DSP_TAP :: TAP5_C3 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x4,2)
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_POLARITY_MASK                  0x0004
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_POLARITY_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_POLARITY_BITS                  1
#define BRPHY3_DSP_TAP_TAP5_C3_PAIR_POLARITY_SHIFT                 2

/* BRPHY3_DSP_TAP :: TAP5_C3 :: SWAPCD [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_SWAPCD(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_SWAPCD(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x2,1)
#define BRPHY3_DSP_TAP_TAP5_C3_SWAPCD_MASK                         0x0002
#define BRPHY3_DSP_TAP_TAP5_C3_SWAPCD_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP5_C3_SWAPCD_BITS                         1
#define BRPHY3_DSP_TAP_TAP5_C3_SWAPCD_SHIFT                        1

/* BRPHY3_DSP_TAP :: TAP5_C3 :: SWAPAB [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP5_C3_SWAPAB(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP5_C3_SWAPAB(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP5_C3,0x1,0)
#define BRPHY3_DSP_TAP_TAP5_C3_SWAPAB_MASK                         0x0001
#define BRPHY3_DSP_TAP_TAP5_C3_SWAPAB_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP5_C3_SWAPAB_BITS                         1
#define BRPHY3_DSP_TAP_TAP5_C3_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP6
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP6 :: CFCDEADMAN_DIS [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP6,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP6,0x8000,15)
#define BRPHY3_DSP_TAP_TAP6_CFCDEADMAN_DIS_MASK                    0x8000
#define BRPHY3_DSP_TAP_TAP6_CFCDEADMAN_DIS_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP6_CFCDEADMAN_DIS_BITS                    1
#define BRPHY3_DSP_TAP_TAP6_CFCDEADMAN_DIS_SHIFT                   15

/* BRPHY3_DSP_TAP :: TAP6 :: AGC_FREEZ_EN [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP6_AGC_FREEZ_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP6,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP6_AGC_FREEZ_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP6,0x4000,14)
#define BRPHY3_DSP_TAP_TAP6_AGC_FREEZ_EN_MASK                      0x4000
#define BRPHY3_DSP_TAP_TAP6_AGC_FREEZ_EN_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP6_AGC_FREEZ_EN_BITS                      1
#define BRPHY3_DSP_TAP_TAP6_AGC_FREEZ_EN_SHIFT                     14

/* BRPHY3_DSP_TAP :: TAP6 :: DAC_GAIN_INV_EN [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP6,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP6,0x2000,13)
#define BRPHY3_DSP_TAP_TAP6_DAC_GAIN_INV_EN_MASK                   0x2000
#define BRPHY3_DSP_TAP_TAP6_DAC_GAIN_INV_EN_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP6_DAC_GAIN_INV_EN_BITS                   1
#define BRPHY3_DSP_TAP_TAP6_DAC_GAIN_INV_EN_SHIFT                  13

/* BRPHY3_DSP_TAP :: TAP6 :: SPARE_REG_B12 [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP6_SPARE_REG_B12(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP6,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP6_SPARE_REG_B12(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP6,0x1000,12)
#define BRPHY3_DSP_TAP_TAP6_SPARE_REG_B12_MASK                     0x1000
#define BRPHY3_DSP_TAP_TAP6_SPARE_REG_B12_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP6_SPARE_REG_B12_BITS                     1
#define BRPHY3_DSP_TAP_TAP6_SPARE_REG_B12_SHIFT                    12

/* BRPHY3_DSP_TAP :: TAP6 :: FORCE_FSM_IDLE [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP6,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP6,0x800,11)
#define BRPHY3_DSP_TAP_TAP6_FORCE_FSM_IDLE_MASK                    0x0800
#define BRPHY3_DSP_TAP_TAP6_FORCE_FSM_IDLE_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP6_FORCE_FSM_IDLE_BITS                    1
#define BRPHY3_DSP_TAP_TAP6_FORCE_FSM_IDLE_SHIFT                   11

/* BRPHY3_DSP_TAP :: TAP6 :: SPARE_REG [10:00] */
#define Wr_BRPHY3_DSP_TAP_TAP6_SPARE_REG(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP6,0x7ff,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP6_SPARE_REG(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP6,0x7ff,0)
#define BRPHY3_DSP_TAP_TAP6_SPARE_REG_MASK                         0x07ff
#define BRPHY3_DSP_TAP_TAP6_SPARE_REG_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP6_SPARE_REG_BITS                         11
#define BRPHY3_DSP_TAP_TAP6_SPARE_REG_SHIFT                        0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP7_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP7_C0 :: TEST_LENGTH [15:09] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_TEST_LENGTH(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0xfe00,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_TEST_LENGTH(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0xfe00,9)
#define BRPHY3_DSP_TAP_TAP7_C0_TEST_LENGTH_MASK                    0xfe00
#define BRPHY3_DSP_TAP_TAP7_C0_TEST_LENGTH_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP7_C0_TEST_LENGTH_BITS                    7
#define BRPHY3_DSP_TAP_TAP7_C0_TEST_LENGTH_SHIFT                   9

/* BRPHY3_DSP_TAP :: TAP7_C0 :: SINGLE_TAP_MODE [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x100,8)
#define BRPHY3_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_MASK                0x0100
#define BRPHY3_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_ALIGN               0
#define BRPHY3_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_BITS                1
#define BRPHY3_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_SHIFT               8

/* BRPHY3_DSP_TAP :: TAP7_C0 :: UPDATE_MODE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x80,7)
#define BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MODE_MASK                    0x0080
#define BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MODE_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MODE_BITS                    1
#define BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MODE_SHIFT                   7

/* BRPHY3_DSP_TAP :: TAP7_C0 :: UPDATE_MAGNITUDE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x40,6)
#define BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_MASK               0x0040
#define BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_BITS               1
#define BRPHY3_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_SHIFT              6

/* BRPHY3_DSP_TAP :: TAP7_C0 :: START_TEST [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_START_TEST(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_START_TEST(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x20,5)
#define BRPHY3_DSP_TAP_TAP7_C0_START_TEST_MASK                     0x0020
#define BRPHY3_DSP_TAP_TAP7_C0_START_TEST_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP7_C0_START_TEST_BITS                     1
#define BRPHY3_DSP_TAP_TAP7_C0_START_TEST_SHIFT                    5

/* BRPHY3_DSP_TAP :: TAP7_C0 :: ZERO_DFE_D [04:04] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x10,4)
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_D_MASK                     0x0010
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_D_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_D_BITS                     1
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_D_SHIFT                    4

/* BRPHY3_DSP_TAP :: TAP7_C0 :: ZERO_DFE_C [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x8,3)
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_C_MASK                     0x0008
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_C_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_C_BITS                     1
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_C_SHIFT                    3

/* BRPHY3_DSP_TAP :: TAP7_C0 :: ZERO_DFE_B [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x4,2)
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_B_MASK                     0x0004
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_B_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_B_BITS                     1
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_B_SHIFT                    2

/* BRPHY3_DSP_TAP :: TAP7_C0 :: ZERO_DFE_A [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x2,1)
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_A_MASK                     0x0002
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_A_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_A_BITS                     1
#define BRPHY3_DSP_TAP_TAP7_C0_ZERO_DFE_A_SHIFT                    1

/* BRPHY3_DSP_TAP :: TAP7_C0 :: ENABLE_BIST_MODE [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C0,0x1,0)
#define BRPHY3_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_MASK               0x0001
#define BRPHY3_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_BITS               1
#define BRPHY3_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_SHIFT              0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP7_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP7_C1 :: TAP_NUMBER [15:08] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C1_TAP_NUMBER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C1,0xff00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C1_TAP_NUMBER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C1,0xff00,8)
#define BRPHY3_DSP_TAP_TAP7_C1_TAP_NUMBER_MASK                     0xff00
#define BRPHY3_DSP_TAP_TAP7_C1_TAP_NUMBER_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP7_C1_TAP_NUMBER_BITS                     8
#define BRPHY3_DSP_TAP_TAP7_C1_TAP_NUMBER_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP7_C1 :: POLARITY_MASK_LSB [07:00] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C1,0xff,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C1,0xff,0)
#define BRPHY3_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_MASK              0x00ff
#define BRPHY3_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_ALIGN             0
#define BRPHY3_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_BITS              8
#define BRPHY3_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_SHIFT             0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP7_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP7_C2 :: SPARE [15:08] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C2_SPARE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0xff00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C2_SPARE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0xff00,8)
#define BRPHY3_DSP_TAP_TAP7_C2_SPARE_MASK                          0xff00
#define BRPHY3_DSP_TAP_TAP7_C2_SPARE_ALIGN                         0
#define BRPHY3_DSP_TAP_TAP7_C2_SPARE_BITS                          8
#define BRPHY3_DSP_TAP_TAP7_C2_SPARE_SHIFT                         8

/* BRPHY3_DSP_TAP :: TAP7_C2 :: BIST_FFE_UPDATE_EN [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x80,7)
#define BRPHY3_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_MASK             0x0080
#define BRPHY3_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_ALIGN            0
#define BRPHY3_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_BITS             1
#define BRPHY3_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_SHIFT            7

/* BRPHY3_DSP_TAP :: TAP7_C2 :: DISABLE_RANDOM_BIST_ADC [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x40,6)
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_MASK        0x0040
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_ALIGN       0
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_BITS        1
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_SHIFT       6

/* BRPHY3_DSP_TAP :: TAP7_C2 :: DISABLE_VITERBI_TO_BIST [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x20,5)
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_MASK        0x0020
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_ALIGN       0
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_BITS        1
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_SHIFT       5

/* BRPHY3_DSP_TAP :: TAP7_C2 :: USE_BIST_FOR_DFE [04:04] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x10,4)
#define BRPHY3_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_MASK               0x0010
#define BRPHY3_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_BITS               1
#define BRPHY3_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_SHIFT              4

/* BRPHY3_DSP_TAP :: TAP7_C2 :: FORCE_VITERBI_MODE [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x8,3)
#define BRPHY3_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_MASK             0x0008
#define BRPHY3_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_ALIGN            0
#define BRPHY3_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_BITS             1
#define BRPHY3_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_SHIFT            3

/* BRPHY3_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_IPRK_OV [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x4,2)
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_MASK           0x0004
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_ALIGN          0
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_BITS           1
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_SHIFT          2

/* BRPHY3_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_GAMMA_OV [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x2,1)
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_MASK          0x0002
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_ALIGN         0
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_BITS          1
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_SHIFT         1

/* BRPHY3_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_ADC_OV [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP7_C2,0x1,0)
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_MASK            0x0001
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_ALIGN           0
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_BITS            1
#define BRPHY3_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_SHIFT           0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP8_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP8_C0 :: PGA_OV [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_PGA_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_PGA_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x8000,15)
#define BRPHY3_DSP_TAP_TAP8_C0_PGA_OV_MASK                         0x8000
#define BRPHY3_DSP_TAP_TAP8_C0_PGA_OV_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP8_C0_PGA_OV_BITS                         1
#define BRPHY3_DSP_TAP_TAP8_C0_PGA_OV_SHIFT                        15

/* BRPHY3_DSP_TAP :: TAP8_C0 :: TIMER_OV [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_TIMER_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_TIMER_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x4000,14)
#define BRPHY3_DSP_TAP_TAP8_C0_TIMER_OV_MASK                       0x4000
#define BRPHY3_DSP_TAP_TAP8_C0_TIMER_OV_ALIGN                      0
#define BRPHY3_DSP_TAP_TAP8_C0_TIMER_OV_BITS                       1
#define BRPHY3_DSP_TAP_TAP8_C0_TIMER_OV_SHIFT                      14

/* BRPHY3_DSP_TAP :: TAP8_C0 :: MONOTONICITY_MODE [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x2000,13)
#define BRPHY3_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_MASK              0x2000
#define BRPHY3_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_ALIGN             0
#define BRPHY3_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_BITS              1
#define BRPHY3_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_SHIFT             13

/* BRPHY3_DSP_TAP :: TAP8_C0 :: FREEZE_ERROR_ON_FAIL [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x1000,12)
#define BRPHY3_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_MASK           0x1000
#define BRPHY3_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_ALIGN          0
#define BRPHY3_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_BITS           1
#define BRPHY3_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_SHIFT          12

/* BRPHY3_DSP_TAP :: TAP8_C0 :: FREEZE_MSE_ON_FAIL [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x800,11)
#define BRPHY3_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_MASK             0x0800
#define BRPHY3_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_ALIGN            0
#define BRPHY3_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_BITS             1
#define BRPHY3_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_SHIFT            11

/* BRPHY3_DSP_TAP :: TAP8_C0 :: FAST_CONV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x400,10)
#define BRPHY3_DSP_TAP_TAP8_C0_FAST_CONV_EN_MASK                   0x0400
#define BRPHY3_DSP_TAP_TAP8_C0_FAST_CONV_EN_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP8_C0_FAST_CONV_EN_BITS                   1
#define BRPHY3_DSP_TAP_TAP8_C0_FAST_CONV_EN_SHIFT                  10

/* BRPHY3_DSP_TAP :: TAP8_C0 :: PGA_TOGGLE_MODE_EN [09:09] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x200,9)
#define BRPHY3_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_MASK             0x0200
#define BRPHY3_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_ALIGN            0
#define BRPHY3_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_BITS             1
#define BRPHY3_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_SHIFT            9

/* BRPHY3_DSP_TAP :: TAP8_C0 :: PAT_GEN_EN [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x100,8)
#define BRPHY3_DSP_TAP_TAP8_C0_PAT_GEN_EN_MASK                     0x0100
#define BRPHY3_DSP_TAP_TAP8_C0_PAT_GEN_EN_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP8_C0_PAT_GEN_EN_BITS                     1
#define BRPHY3_DSP_TAP_TAP8_C0_PAT_GEN_EN_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP8_C0 :: MAX_OFFSET_CHECK_EN [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x80,7)
#define BRPHY3_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_MASK            0x0080
#define BRPHY3_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_ALIGN           0
#define BRPHY3_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_BITS            1
#define BRPHY3_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_SHIFT           7

/* BRPHY3_DSP_TAP :: TAP8_C0 :: SYM_ERR_CHECK_EN [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x40,6)
#define BRPHY3_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_MASK               0x0040
#define BRPHY3_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_ALIGN              0
#define BRPHY3_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_BITS               1
#define BRPHY3_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_SHIFT              6

/* BRPHY3_DSP_TAP :: TAP8_C0 :: PEAK_ERR_CHECK_EN [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x20,5)
#define BRPHY3_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_MASK              0x0020
#define BRPHY3_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_ALIGN             0
#define BRPHY3_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_BITS              1
#define BRPHY3_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_SHIFT             5

/* BRPHY3_DSP_TAP :: TAP8_C0 :: MSE_CHECK_EN [04:04] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x10,4)
#define BRPHY3_DSP_TAP_TAP8_C0_MSE_CHECK_EN_MASK                   0x0010
#define BRPHY3_DSP_TAP_TAP8_C0_MSE_CHECK_EN_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP8_C0_MSE_CHECK_EN_BITS                   1
#define BRPHY3_DSP_TAP_TAP8_C0_MSE_CHECK_EN_SHIFT                  4

/* BRPHY3_DSP_TAP :: TAP8_C0 :: GAIN_AMP_CHECK_EN [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x8,3)
#define BRPHY3_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_MASK              0x0008
#define BRPHY3_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_ALIGN             0
#define BRPHY3_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_BITS              1
#define BRPHY3_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_SHIFT             3

/* BRPHY3_DSP_TAP :: TAP8_C0 :: HALT_ON_ERROR [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x4,2)
#define BRPHY3_DSP_TAP_TAP8_C0_HALT_ON_ERROR_MASK                  0x0004
#define BRPHY3_DSP_TAP_TAP8_C0_HALT_ON_ERROR_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP8_C0_HALT_ON_ERROR_BITS                  1
#define BRPHY3_DSP_TAP_TAP8_C0_HALT_ON_ERROR_SHIFT                 2

/* BRPHY3_DSP_TAP :: TAP8_C0 :: START_ABIST [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_START_ABIST(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_START_ABIST(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x2,1)
#define BRPHY3_DSP_TAP_TAP8_C0_START_ABIST_MASK                    0x0002
#define BRPHY3_DSP_TAP_TAP8_C0_START_ABIST_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP8_C0_START_ABIST_BITS                    1
#define BRPHY3_DSP_TAP_TAP8_C0_START_ABIST_SHIFT                   1

/* BRPHY3_DSP_TAP :: TAP8_C0 :: ABIST_EN [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C0_ABIST_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C0_ABIST_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C0,0x1,0)
#define BRPHY3_DSP_TAP_TAP8_C0_ABIST_EN_MASK                       0x0001
#define BRPHY3_DSP_TAP_TAP8_C0_ABIST_EN_ALIGN                      0
#define BRPHY3_DSP_TAP_TAP8_C0_ABIST_EN_BITS                       1
#define BRPHY3_DSP_TAP_TAP8_C0_ABIST_EN_SHIFT                      0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP8_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP8_C1 :: MAJOR_MODE [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_MAJOR_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_MAJOR_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x8000,15)
#define BRPHY3_DSP_TAP_TAP8_C1_MAJOR_MODE_MASK                     0x8000
#define BRPHY3_DSP_TAP_TAP8_C1_MAJOR_MODE_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP8_C1_MAJOR_MODE_BITS                     1
#define BRPHY3_DSP_TAP_TAP8_C1_MAJOR_MODE_SHIFT                    15

/* BRPHY3_DSP_TAP :: TAP8_C1 :: MULTIPLE_MSE [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x4000,14)
#define BRPHY3_DSP_TAP_TAP8_C1_MULTIPLE_MSE_MASK                   0x4000
#define BRPHY3_DSP_TAP_TAP8_C1_MULTIPLE_MSE_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP8_C1_MULTIPLE_MSE_BITS                   1
#define BRPHY3_DSP_TAP_TAP8_C1_MULTIPLE_MSE_SHIFT                  14

/* BRPHY3_DSP_TAP :: TAP8_C1 :: GAMMA_OV [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_GAMMA_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_GAMMA_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x2000,13)
#define BRPHY3_DSP_TAP_TAP8_C1_GAMMA_OV_MASK                       0x2000
#define BRPHY3_DSP_TAP_TAP8_C1_GAMMA_OV_ALIGN                      0
#define BRPHY3_DSP_TAP_TAP8_C1_GAMMA_OV_BITS                       1
#define BRPHY3_DSP_TAP_TAP8_C1_GAMMA_OV_SHIFT                      13

/* BRPHY3_DSP_TAP :: TAP8_C1 :: FFE_COARSE_OV [12:08] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x1f00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x1f00,8)
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_COARSE_OV_MASK                  0x1f00
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_COARSE_OV_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_COARSE_OV_BITS                  5
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_COARSE_OV_SHIFT                 8

/* BRPHY3_DSP_TAP :: TAP8_C1 :: FFE_PF_OV_INIT [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x80,7)
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_MASK                 0x0080
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_ALIGN                0
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_BITS                 1
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_SHIFT                7

/* BRPHY3_DSP_TAP :: TAP8_C1 :: SINGLE_STEP_MODE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x40,6)
#define BRPHY3_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_MASK               0x0040
#define BRPHY3_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_BITS               1
#define BRPHY3_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_SHIFT              6

/* BRPHY3_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SEL [05:04] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x30,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x30,4)
#define BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_MASK               0x0030
#define BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_ALIGN              0
#define BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_BITS               2
#define BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_SHIFT              4

/* BRPHY3_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SE_EN [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x8,3)
#define BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_MASK             0x0008
#define BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_ALIGN            0
#define BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_BITS             1
#define BRPHY3_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_SHIFT            3

/* BRPHY3_DSP_TAP :: TAP8_C1 :: TX_HALFOUT_OV [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x4,2)
#define BRPHY3_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_MASK                  0x0004
#define BRPHY3_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_BITS                  1
#define BRPHY3_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_SHIFT                 2

/* BRPHY3_DSP_TAP :: TAP8_C1 :: TX_ADJ_EN [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x2,1)
#define BRPHY3_DSP_TAP_TAP8_C1_TX_ADJ_EN_MASK                      0x0002
#define BRPHY3_DSP_TAP_TAP8_C1_TX_ADJ_EN_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP8_C1_TX_ADJ_EN_BITS                      1
#define BRPHY3_DSP_TAP_TAP8_C1_TX_ADJ_EN_SHIFT                     1

/* BRPHY3_DSP_TAP :: TAP8_C1 :: FFE_BUMP_EN [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C1,0x1,0)
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_BUMP_EN_MASK                    0x0001
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_BUMP_EN_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_BUMP_EN_BITS                    1
#define BRPHY3_DSP_TAP_TAP8_C1_FFE_BUMP_EN_SHIFT                   0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP8_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP8_C2 :: LEVELSELECT [15:13] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_LEVELSELECT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0xe000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_LEVELSELECT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0xe000,13)
#define BRPHY3_DSP_TAP_TAP8_C2_LEVELSELECT_MASK                    0xe000
#define BRPHY3_DSP_TAP_TAP8_C2_LEVELSELECT_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP8_C2_LEVELSELECT_BITS                    3
#define BRPHY3_DSP_TAP_TAP8_C2_LEVELSELECT_SHIFT                   13

/* BRPHY3_DSP_TAP :: TAP8_C2 :: FAILING_CHANNEL [12:11] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x1800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x1800,11)
#define BRPHY3_DSP_TAP_TAP8_C2_FAILING_CHANNEL_MASK                0x1800
#define BRPHY3_DSP_TAP_TAP8_C2_FAILING_CHANNEL_ALIGN               0
#define BRPHY3_DSP_TAP_TAP8_C2_FAILING_CHANNEL_BITS                2
#define BRPHY3_DSP_TAP_TAP8_C2_FAILING_CHANNEL_SHIFT               11

/* BRPHY3_DSP_TAP :: TAP8_C2 :: CONV_FAIL_FLAG [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x400,10)
#define BRPHY3_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_MASK                 0x0400
#define BRPHY3_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_ALIGN                0
#define BRPHY3_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_BITS                 1
#define BRPHY3_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_SHIFT                10

/* BRPHY3_DSP_TAP :: TAP8_C2 :: SYM_ERR_FAIL_FLAG [09:09] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x200,9)
#define BRPHY3_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_MASK              0x0200
#define BRPHY3_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_ALIGN             0
#define BRPHY3_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_BITS              1
#define BRPHY3_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_SHIFT             9

/* BRPHY3_DSP_TAP :: TAP8_C2 :: MAX_OFFSET_FAIL_FLAG [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x100,8)
#define BRPHY3_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_MASK           0x0100
#define BRPHY3_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_ALIGN          0
#define BRPHY3_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_BITS           1
#define BRPHY3_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_SHIFT          8

/* BRPHY3_DSP_TAP :: TAP8_C2 :: PEAK_ERR_FAIL_FLAG [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x80,7)
#define BRPHY3_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_MASK             0x0080
#define BRPHY3_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_ALIGN            0
#define BRPHY3_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_BITS             1
#define BRPHY3_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_SHIFT            7

/* BRPHY3_DSP_TAP :: TAP8_C2 :: MSE_FAIL_FLAG [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x40,6)
#define BRPHY3_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_MASK                  0x0040
#define BRPHY3_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_BITS                  1
#define BRPHY3_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_SHIFT                 6

/* BRPHY3_DSP_TAP :: TAP8_C2 :: GAIN_AMP_FAIL_FLAG [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x20,5)
#define BRPHY3_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_MASK             0x0020
#define BRPHY3_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_ALIGN            0
#define BRPHY3_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_BITS             1
#define BRPHY3_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_SHIFT            5

/* BRPHY3_DSP_TAP :: TAP8_C2 :: ABIST_COMPLETE_FLAG [04:04] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0x10,4)
#define BRPHY3_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_MASK            0x0010
#define BRPHY3_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_ALIGN           0
#define BRPHY3_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_BITS            1
#define BRPHY3_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_SHIFT           4

/* BRPHY3_DSP_TAP :: TAP8_C2 :: ADC_OVERFLOW [03:00] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C2,0xf,0)
#define BRPHY3_DSP_TAP_TAP8_C2_ADC_OVERFLOW_MASK                   0x000f
#define BRPHY3_DSP_TAP_TAP8_C2_ADC_OVERFLOW_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP8_C2_ADC_OVERFLOW_BITS                   4
#define BRPHY3_DSP_TAP_TAP8_C2_ADC_OVERFLOW_SHIFT                  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP8_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP8_C3 :: SPARE [15:12] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C3_SPARE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C3,0xf000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C3_SPARE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C3,0xf000,12)
#define BRPHY3_DSP_TAP_TAP8_C3_SPARE_MASK                          0xf000
#define BRPHY3_DSP_TAP_TAP8_C3_SPARE_ALIGN                         0
#define BRPHY3_DSP_TAP_TAP8_C3_SPARE_BITS                          4
#define BRPHY3_DSP_TAP_TAP8_C3_SPARE_SHIFT                         12

/* BRPHY3_DSP_TAP :: TAP8_C3 :: BR_AGC_RST_VAL [11:10] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C3,0xc00,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C3,0xc00,10)
#define BRPHY3_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_MASK                 0x0c00
#define BRPHY3_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_ALIGN                0
#define BRPHY3_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_BITS                 2
#define BRPHY3_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_SHIFT                10

/* BRPHY3_DSP_TAP :: TAP8_C3 :: BR_HPF_CTL [09:00] */
#define Wr_BRPHY3_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP8_C3,0x3ff,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP8_C3,0x3ff,0)
#define BRPHY3_DSP_TAP_TAP8_C3_BR_HPF_CTL_MASK                     0x03ff
#define BRPHY3_DSP_TAP_TAP8_C3_BR_HPF_CTL_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP8_C3_BR_HPF_CTL_BITS                     10
#define BRPHY3_DSP_TAP_TAP8_C3_BR_HPF_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP9
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP9 :: FREQ_REG [15:04] */
#define Wr_BRPHY3_DSP_TAP_TAP9_FREQ_REG(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP9,0xfff0,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP9_FREQ_REG(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP9,0xfff0,4)
#define BRPHY3_DSP_TAP_TAP9_FREQ_REG_MASK                          0xfff0
#define BRPHY3_DSP_TAP_TAP9_FREQ_REG_ALIGN                         0
#define BRPHY3_DSP_TAP_TAP9_FREQ_REG_BITS                          12
#define BRPHY3_DSP_TAP_TAP9_FREQ_REG_SHIFT                         4

/* BRPHY3_DSP_TAP :: TAP9 :: FREQ_REG_OV_EN_ABCD [03:00] */
#define Wr_BRPHY3_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP9,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP9,0xf,0)
#define BRPHY3_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_MASK               0x000f
#define BRPHY3_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_ALIGN              0
#define BRPHY3_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_BITS               4
#define BRPHY3_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_SHIFT              0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP10
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP10 :: SLAVEENCCONVADJUST [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP10,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP10,0x8000,15)
#define BRPHY3_DSP_TAP_TAP10_SLAVEENCCONVADJUST_MASK               0x8000
#define BRPHY3_DSP_TAP_TAP10_SLAVEENCCONVADJUST_ALIGN              0
#define BRPHY3_DSP_TAP_TAP10_SLAVEENCCONVADJUST_BITS               1
#define BRPHY3_DSP_TAP_TAP10_SLAVEENCCONVADJUST_SHIFT              15

/* BRPHY3_DSP_TAP :: TAP10 :: TRIM_HYB [14:11] */
#define Wr_BRPHY3_DSP_TAP_TAP10_TRIM_HYB(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP10,0x7800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP10_TRIM_HYB(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP10,0x7800,11)
#define BRPHY3_DSP_TAP_TAP10_TRIM_HYB_MASK                         0x7800
#define BRPHY3_DSP_TAP_TAP10_TRIM_HYB_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP10_TRIM_HYB_BITS                         4
#define BRPHY3_DSP_TAP_TAP10_TRIM_HYB_SHIFT                        11

/* BRPHY3_DSP_TAP :: TAP10 :: FFE_GAMMA_OV [10:09] */
#define Wr_BRPHY3_DSP_TAP_TAP10_FFE_GAMMA_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP10,0x600,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP10_FFE_GAMMA_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP10,0x600,9)
#define BRPHY3_DSP_TAP_TAP10_FFE_GAMMA_OV_MASK                     0x0600
#define BRPHY3_DSP_TAP_TAP10_FFE_GAMMA_OV_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP10_FFE_GAMMA_OV_BITS                     2
#define BRPHY3_DSP_TAP_TAP10_FFE_GAMMA_OV_SHIFT                    9

/* BRPHY3_DSP_TAP :: TAP10 :: TX_PHASE_CTL_BW_SEL [08:07] */
#define Wr_BRPHY3_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP10,0x180,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP10,0x180,7)
#define BRPHY3_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_MASK              0x0180
#define BRPHY3_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_ALIGN             0
#define BRPHY3_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_BITS              2
#define BRPHY3_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_SHIFT             7

/* BRPHY3_DSP_TAP :: TAP10 :: RESET_PATH_METRICS [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP10_RESET_PATH_METRICS(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP10,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP10_RESET_PATH_METRICS(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP10,0x40,6)
#define BRPHY3_DSP_TAP_TAP10_RESET_PATH_METRICS_MASK               0x0040
#define BRPHY3_DSP_TAP_TAP10_RESET_PATH_METRICS_ALIGN              0
#define BRPHY3_DSP_TAP_TAP10_RESET_PATH_METRICS_BITS               1
#define BRPHY3_DSP_TAP_TAP10_RESET_PATH_METRICS_SHIFT              6

/* BRPHY3_DSP_TAP :: TAP10 :: GBT_PLL_BW_CTL_STARTUP [05:03] */
#define Wr_BRPHY3_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP10,0x38,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP10,0x38,3)
#define BRPHY3_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_MASK           0x0038
#define BRPHY3_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_ALIGN          0
#define BRPHY3_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_BITS           3
#define BRPHY3_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_SHIFT          3

/* BRPHY3_DSP_TAP :: TAP10 :: BGT_PLL_BW_CTL_NORMAL_OP [02:00] */
#define Wr_BRPHY3_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP10,0x7,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP10,0x7,0)
#define BRPHY3_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_MASK         0x0007
#define BRPHY3_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_ALIGN        0
#define BRPHY3_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_BITS         3
#define BRPHY3_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_SHIFT        0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP11
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP11 :: TCLK_OFFSET_STROBE [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP11,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP11,0x8000,15)
#define BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_MASK               0x8000
#define BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_BITS               1
#define BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_SHIFT              15

/* BRPHY3_DSP_TAP :: TAP11 :: RCLK_OFFSET_STROBE [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP11,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP11,0x4000,14)
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_MASK               0x4000
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_BITS               1
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_SHIFT              14

/* BRPHY3_DSP_TAP :: TAP11 :: reserved0 [13:13] */
#define BRPHY3_DSP_TAP_TAP11_RESERVED0_MASK                        0x2000
#define BRPHY3_DSP_TAP_TAP11_RESERVED0_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP11_RESERVED0_BITS                        1
#define BRPHY3_DSP_TAP_TAP11_RESERVED0_SHIFT                       13

/* BRPHY3_DSP_TAP :: TAP11 :: RCLK_OFFSET_FREEZE [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP11,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP11,0x1000,12)
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_MASK               0x1000
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_BITS               1
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_SHIFT              12

/* BRPHY3_DSP_TAP :: TAP11 :: TCLK_OFFSET [11:06] */
#define Wr_BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP11,0xfc0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP11,0xfc0,6)
#define BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_MASK                      0x0fc0
#define BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_BITS                      6
#define BRPHY3_DSP_TAP_TAP11_TCLK_OFFSET_SHIFT                     6

/* BRPHY3_DSP_TAP :: TAP11 :: RCLK_OFFSET [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP11,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP11,0x3f,0)
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_MASK                      0x003f
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_BITS                      6
#define BRPHY3_DSP_TAP_TAP11_RCLK_OFFSET_SHIFT                     0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP12_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP12_C0 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_TAP12_C0_RESERVED0_MASK                     0xff00
#define BRPHY3_DSP_TAP_TAP12_C0_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP12_C0_RESERVED0_BITS                     8
#define BRPHY3_DSP_TAP_TAP12_C0_RESERVED0_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C0,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C0,0x80,7)
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY3_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C0,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C0,0x40,6)
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY3_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C0,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C0,0x3f,0)
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_MASK                   0x003f
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_BITS                   6
#define BRPHY3_DSP_TAP_TAP12_C0_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP12_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP12_C1 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_TAP12_C1_RESERVED0_MASK                     0xff00
#define BRPHY3_DSP_TAP_TAP12_C1_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP12_C1_RESERVED0_BITS                     8
#define BRPHY3_DSP_TAP_TAP12_C1_RESERVED0_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C1,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C1,0x80,7)
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY3_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C1,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C1,0x40,6)
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY3_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C1,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C1,0x3f,0)
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_MASK                   0x003f
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_BITS                   6
#define BRPHY3_DSP_TAP_TAP12_C1_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP12_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP12_C2 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_TAP12_C2_RESERVED0_MASK                     0xff00
#define BRPHY3_DSP_TAP_TAP12_C2_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP12_C2_RESERVED0_BITS                     8
#define BRPHY3_DSP_TAP_TAP12_C2_RESERVED0_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C2,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C2,0x80,7)
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY3_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C2,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C2,0x40,6)
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY3_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C2,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C2,0x3f,0)
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_MASK                   0x003f
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_BITS                   6
#define BRPHY3_DSP_TAP_TAP12_C2_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP12_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP12_C3 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_TAP12_C3_RESERVED0_MASK                     0xff00
#define BRPHY3_DSP_TAP_TAP12_C3_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP12_C3_RESERVED0_BITS                     8
#define BRPHY3_DSP_TAP_TAP12_C3_RESERVED0_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C3,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C3,0x80,7)
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY3_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C3,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C3,0x40,6)
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY3_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP12_C3,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP12_C3,0x3f,0)
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_MASK                   0x003f
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_BITS                   6
#define BRPHY3_DSP_TAP_TAP12_C3_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP13
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP13 :: TMPLATE_EN [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP13_TMPLATE_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_TMPLATE_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0x8000,15)
#define BRPHY3_DSP_TAP_TAP13_TMPLATE_EN_MASK                       0x8000
#define BRPHY3_DSP_TAP_TAP13_TMPLATE_EN_ALIGN                      0
#define BRPHY3_DSP_TAP_TAP13_TMPLATE_EN_BITS                       1
#define BRPHY3_DSP_TAP_TAP13_TMPLATE_EN_SHIFT                      15

/* BRPHY3_DSP_TAP :: TAP13 :: PATTERN_DURATION [14:13] */
#define Wr_BRPHY3_DSP_TAP_TAP13_PATTERN_DURATION(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0x6000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_PATTERN_DURATION(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0x6000,13)
#define BRPHY3_DSP_TAP_TAP13_PATTERN_DURATION_MASK                 0x6000
#define BRPHY3_DSP_TAP_TAP13_PATTERN_DURATION_ALIGN                0
#define BRPHY3_DSP_TAP_TAP13_PATTERN_DURATION_BITS                 2
#define BRPHY3_DSP_TAP_TAP13_PATTERN_DURATION_SHIFT                13

/* BRPHY3_DSP_TAP :: TAP13 :: PATTERN_SEL [12:11] */
#define Wr_BRPHY3_DSP_TAP_TAP13_PATTERN_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0x1800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_PATTERN_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0x1800,11)
#define BRPHY3_DSP_TAP_TAP13_PATTERN_SEL_MASK                      0x1800
#define BRPHY3_DSP_TAP_TAP13_PATTERN_SEL_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP13_PATTERN_SEL_BITS                      2
#define BRPHY3_DSP_TAP_TAP13_PATTERN_SEL_SHIFT                     11

/* BRPHY3_DSP_TAP :: TAP13 :: PATTERN_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP13_PATTERN_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_PATTERN_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0x400,10)
#define BRPHY3_DSP_TAP_TAP13_PATTERN_EN_MASK                       0x0400
#define BRPHY3_DSP_TAP_TAP13_PATTERN_EN_ALIGN                      0
#define BRPHY3_DSP_TAP_TAP13_PATTERN_EN_BITS                       1
#define BRPHY3_DSP_TAP_TAP13_PATTERN_EN_SHIFT                      10

/* BRPHY3_DSP_TAP :: TAP13 :: DISABLETRRRGEN [09:09] */
#define Wr_BRPHY3_DSP_TAP_TAP13_DISABLETRRRGEN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_DISABLETRRRGEN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0x200,9)
#define BRPHY3_DSP_TAP_TAP13_DISABLETRRRGEN_MASK                   0x0200
#define BRPHY3_DSP_TAP_TAP13_DISABLETRRRGEN_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP13_DISABLETRRRGEN_BITS                   1
#define BRPHY3_DSP_TAP_TAP13_DISABLETRRRGEN_SHIFT                  9

/* BRPHY3_DSP_TAP :: TAP13 :: DISABLE10BEXTENSION [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0x100,8)
#define BRPHY3_DSP_TAP_TAP13_DISABLE10BEXTENSION_MASK              0x0100
#define BRPHY3_DSP_TAP_TAP13_DISABLE10BEXTENSION_ALIGN             0
#define BRPHY3_DSP_TAP_TAP13_DISABLE10BEXTENSION_BITS              1
#define BRPHY3_DSP_TAP_TAP13_DISABLE10BEXTENSION_SHIFT             8

/* BRPHY3_DSP_TAP :: TAP13 :: ALIGN_OK1_DISABLE [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0x80,7)
#define BRPHY3_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_MASK                0x0080
#define BRPHY3_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_ALIGN               0
#define BRPHY3_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_BITS                1
#define BRPHY3_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_SHIFT               7

/* BRPHY3_DSP_TAP :: TAP13 :: ALIGN_OK2_DISABLE [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0x40,6)
#define BRPHY3_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_MASK                0x0040
#define BRPHY3_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_ALIGN               0
#define BRPHY3_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_BITS                1
#define BRPHY3_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_SHIFT               6

/* BRPHY3_DSP_TAP :: TAP13 :: DISABLE_ADC_LSBS [05:04] */
#define Wr_BRPHY3_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0x30,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0x30,4)
#define BRPHY3_DSP_TAP_TAP13_DISABLE_ADC_LSBS_MASK                 0x0030
#define BRPHY3_DSP_TAP_TAP13_DISABLE_ADC_LSBS_ALIGN                0
#define BRPHY3_DSP_TAP_TAP13_DISABLE_ADC_LSBS_BITS                 2
#define BRPHY3_DSP_TAP_TAP13_DISABLE_ADC_LSBS_SHIFT                4

/* BRPHY3_DSP_TAP :: TAP13 :: IDLE_EXT_MASK [03:02] */
#define Wr_BRPHY3_DSP_TAP_TAP13_IDLE_EXT_MASK(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP13,0xc,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP13_IDLE_EXT_MASK(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP13,0xc,2)
#define BRPHY3_DSP_TAP_TAP13_IDLE_EXT_MASK_MASK                    0x000c
#define BRPHY3_DSP_TAP_TAP13_IDLE_EXT_MASK_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP13_IDLE_EXT_MASK_BITS                    2
#define BRPHY3_DSP_TAP_TAP13_IDLE_EXT_MASK_SHIFT                   2

/* BRPHY3_DSP_TAP :: TAP13 :: reserved0 [01:00] */
#define BRPHY3_DSP_TAP_TAP13_RESERVED0_MASK                        0x0003
#define BRPHY3_DSP_TAP_TAP13_RESERVED0_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP13_RESERVED0_BITS                        2
#define BRPHY3_DSP_TAP_TAP13_RESERVED0_SHIFT                       0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP14
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP14 :: MSE_THD_1_LSB [15:08] */
#define Wr_BRPHY3_DSP_TAP_TAP14_MSE_THD_1_LSB(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP14,0xff00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP14_MSE_THD_1_LSB(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP14,0xff00,8)
#define BRPHY3_DSP_TAP_TAP14_MSE_THD_1_LSB_MASK                    0xff00
#define BRPHY3_DSP_TAP_TAP14_MSE_THD_1_LSB_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP14_MSE_THD_1_LSB_BITS                    8
#define BRPHY3_DSP_TAP_TAP14_MSE_THD_1_LSB_SHIFT                   8

/* BRPHY3_DSP_TAP :: TAP14 :: ENERGY_DET_THD [07:00] */
#define Wr_BRPHY3_DSP_TAP_TAP14_ENERGY_DET_THD(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP14,0xff,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP14_ENERGY_DET_THD(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP14,0xff,0)
#define BRPHY3_DSP_TAP_TAP14_ENERGY_DET_THD_MASK                   0x00ff
#define BRPHY3_DSP_TAP_TAP14_ENERGY_DET_THD_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP14_ENERGY_DET_THD_BITS                   8
#define BRPHY3_DSP_TAP_TAP14_ENERGY_DET_THD_SHIFT                  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP15
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP15 :: MSE_THD_3_SEL [15:14] */
#define Wr_BRPHY3_DSP_TAP_TAP15_MSE_THD_3_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP15,0xc000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP15_MSE_THD_3_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP15,0xc000,14)
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_3_SEL_MASK                    0xc000
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_3_SEL_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_3_SEL_BITS                    2
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_3_SEL_SHIFT                   14

/* BRPHY3_DSP_TAP :: TAP15 :: MSE_THD_2 [13:02] */
#define Wr_BRPHY3_DSP_TAP_TAP15_MSE_THD_2(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP15,0x3ffc,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP15_MSE_THD_2(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP15,0x3ffc,2)
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_2_MASK                        0x3ffc
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_2_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_2_BITS                        12
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_2_SHIFT                       2

/* BRPHY3_DSP_TAP :: TAP15 :: MSE_THD_1_MSB [01:00] */
#define Wr_BRPHY3_DSP_TAP_TAP15_MSE_THD_1_MSB(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP15,0x3,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP15_MSE_THD_1_MSB(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP15,0x3,0)
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_1_MSB_MASK                    0x0003
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_1_MSB_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_1_MSB_BITS                    2
#define BRPHY3_DSP_TAP_TAP15_MSE_THD_1_MSB_SHIFT                   0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP16_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP16_C0 :: LA_TRIGGER_DELAY [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) WriteReg16(BRPHY3_DSP_TAP_TAP16_C0,x)
#define Rd_BRPHY3_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) ReadReg16(BRPHY3_DSP_TAP_TAP16_C0)
#define BRPHY3_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_MASK              0xffff
#define BRPHY3_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_ALIGN             0
#define BRPHY3_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_BITS              16
#define BRPHY3_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_SHIFT             0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP16_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP16_C1 :: BIST_CRC [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP16_C1_BIST_CRC(x) WriteReg16(BRPHY3_DSP_TAP_TAP16_C1,x)
#define Rd_BRPHY3_DSP_TAP_TAP16_C1_BIST_CRC(x) ReadReg16(BRPHY3_DSP_TAP_TAP16_C1)
#define BRPHY3_DSP_TAP_TAP16_C1_BIST_CRC_MASK                      0xffff
#define BRPHY3_DSP_TAP_TAP16_C1_BIST_CRC_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP16_C1_BIST_CRC_BITS                      16
#define BRPHY3_DSP_TAP_TAP16_C1_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP16_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP16_C2 :: BIST_CRC [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP16_C2_BIST_CRC(x) WriteReg16(BRPHY3_DSP_TAP_TAP16_C2,x)
#define Rd_BRPHY3_DSP_TAP_TAP16_C2_BIST_CRC(x) ReadReg16(BRPHY3_DSP_TAP_TAP16_C2)
#define BRPHY3_DSP_TAP_TAP16_C2_BIST_CRC_MASK                      0xffff
#define BRPHY3_DSP_TAP_TAP16_C2_BIST_CRC_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP16_C2_BIST_CRC_BITS                      16
#define BRPHY3_DSP_TAP_TAP16_C2_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP16_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP16_C3 :: BIST_CRC [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP16_C3_BIST_CRC(x) WriteReg16(BRPHY3_DSP_TAP_TAP16_C3,x)
#define Rd_BRPHY3_DSP_TAP_TAP16_C3_BIST_CRC(x) ReadReg16(BRPHY3_DSP_TAP_TAP16_C3)
#define BRPHY3_DSP_TAP_TAP16_C3_BIST_CRC_MASK                      0xffff
#define BRPHY3_DSP_TAP_TAP16_C3_BIST_CRC_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP16_C3_BIST_CRC_BITS                      16
#define BRPHY3_DSP_TAP_TAP16_C3_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP17_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP17_C0 :: TESTVALUE [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C0_TESTVALUE(x) WriteReg16(BRPHY3_DSP_TAP_TAP17_C0,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C0_TESTVALUE(x) ReadReg16(BRPHY3_DSP_TAP_TAP17_C0)
#define BRPHY3_DSP_TAP_TAP17_C0_TESTVALUE_MASK                     0xffff
#define BRPHY3_DSP_TAP_TAP17_C0_TESTVALUE_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP17_C0_TESTVALUE_BITS                     16
#define BRPHY3_DSP_TAP_TAP17_C0_TESTVALUE_SHIFT                    0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP17_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP17_C1 :: LA_ACQ_DONE [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x8000,15)
#define BRPHY3_DSP_TAP_TAP17_C1_LA_ACQ_DONE_MASK                   0x8000
#define BRPHY3_DSP_TAP_TAP17_C1_LA_ACQ_DONE_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP17_C1_LA_ACQ_DONE_BITS                   1
#define BRPHY3_DSP_TAP_TAP17_C1_LA_ACQ_DONE_SHIFT                  15

/* BRPHY3_DSP_TAP :: TAP17_C1 :: LA_TPOUT_SEL [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x4000,14)
#define BRPHY3_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_MASK                  0x4000
#define BRPHY3_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_BITS                  1
#define BRPHY3_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_SHIFT                 14

/* BRPHY3_DSP_TAP :: TAP17_C1 :: LA_CLK_DIVISOR [13:11] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x3800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x3800,11)
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_MASK                0x3800
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_ALIGN               0
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_BITS                3
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_SHIFT               11

/* BRPHY3_DSP_TAP :: TAP17_C1 :: LA_CLK_DELAY [10:09] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x600,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x600,9)
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DELAY_MASK                  0x0600
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DELAY_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DELAY_BITS                  2
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_DELAY_SHIFT                 9

/* BRPHY3_DSP_TAP :: TAP17_C1 :: LA_CLK_EDGE [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x100,8)
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_EDGE_MASK                   0x0100
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_EDGE_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_EDGE_BITS                   1
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_EDGE_SHIFT                  8

/* BRPHY3_DSP_TAP :: TAP17_C1 :: LA_CLK_SEL [07:03] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0xf8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0xf8,3)
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_SEL_MASK                    0x00f8
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_SEL_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_SEL_BITS                    5
#define BRPHY3_DSP_TAP_TAP17_C1_LA_CLK_SEL_SHIFT                   3

/* BRPHY3_DSP_TAP :: TAP17_C1 :: LA_ENABLE [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C1_LA_ENABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C1_LA_ENABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x4,2)
#define BRPHY3_DSP_TAP_TAP17_C1_LA_ENABLE_MASK                     0x0004
#define BRPHY3_DSP_TAP_TAP17_C1_LA_ENABLE_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP17_C1_LA_ENABLE_BITS                     1
#define BRPHY3_DSP_TAP_TAP17_C1_LA_ENABLE_SHIFT                    2

/* BRPHY3_DSP_TAP :: TAP17_C1 :: TESTMODE_STROBE [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x2,1)
#define BRPHY3_DSP_TAP_TAP17_C1_TESTMODE_STROBE_MASK               0x0002
#define BRPHY3_DSP_TAP_TAP17_C1_TESTMODE_STROBE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP17_C1_TESTMODE_STROBE_BITS               1
#define BRPHY3_DSP_TAP_TAP17_C1_TESTMODE_STROBE_SHIFT              1

/* BRPHY3_DSP_TAP :: TAP17_C1 :: LSITEST_SMDSP [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C1,0x1,0)
#define BRPHY3_DSP_TAP_TAP17_C1_LSITEST_SMDSP_MASK                 0x0001
#define BRPHY3_DSP_TAP_TAP17_C1_LSITEST_SMDSP_ALIGN                0
#define BRPHY3_DSP_TAP_TAP17_C1_LSITEST_SMDSP_BITS                 1
#define BRPHY3_DSP_TAP_TAP17_C1_LSITEST_SMDSP_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP17_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP17_C2 :: TRIGGER2_LAT [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x8000,15)
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_LAT_MASK                  0x8000
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_LAT_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_LAT_BITS                  1
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_LAT_SHIFT                 15

/* BRPHY3_DSP_TAP :: TAP17_C2 :: TRIGGER2_INV [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x4000,14)
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_INV_MASK                  0x4000
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_INV_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_INV_BITS                  1
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_INV_SHIFT                 14

/* BRPHY3_DSP_TAP :: TAP17_C2 :: TRIGGER2_SEL [13:08] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x3f00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x3f00,8)
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_SEL_MASK                  0x3f00
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_SEL_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_SEL_BITS                  6
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER2_SEL_SHIFT                 8

/* BRPHY3_DSP_TAP :: TAP17_C2 :: TRIGGER1_LAT [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x80,7)
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_LAT_MASK                  0x0080
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_LAT_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_LAT_BITS                  1
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_LAT_SHIFT                 7

/* BRPHY3_DSP_TAP :: TAP17_C2 :: TRIGGER1_INV [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x40,6)
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_INV_MASK                  0x0040
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_INV_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_INV_BITS                  1
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_INV_SHIFT                 6

/* BRPHY3_DSP_TAP :: TAP17_C2 :: TRIGGER1_SEL [05:00] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x3f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C2,0x3f,0)
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_SEL_MASK                  0x003f
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_SEL_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_SEL_BITS                  6
#define BRPHY3_DSP_TAP_TAP17_C2_TRIGGER1_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP17_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP17_C3 :: LA_REARM_ACQ [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x8000,15)
#define BRPHY3_DSP_TAP_TAP17_C3_LA_REARM_ACQ_MASK                  0x8000
#define BRPHY3_DSP_TAP_TAP17_C3_LA_REARM_ACQ_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C3_LA_REARM_ACQ_BITS                  1
#define BRPHY3_DSP_TAP_TAP17_C3_LA_REARM_ACQ_SHIFT                 15

/* BRPHY3_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_DELAY_EN [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x4000,14)
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_MASK           0x4000
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_ALIGN          0
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_BITS           1
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_SHIFT          14

/* BRPHY3_DSP_TAP :: TAP17_C3 :: LA_POSTSTORE [13:06] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x3fc0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x3fc0,6)
#define BRPHY3_DSP_TAP_TAP17_C3_LA_POSTSTORE_MASK                  0x3fc0
#define BRPHY3_DSP_TAP_TAP17_C3_LA_POSTSTORE_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C3_LA_POSTSTORE_BITS                  8
#define BRPHY3_DSP_TAP_TAP17_C3_LA_POSTSTORE_SHIFT                 6

/* BRPHY3_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_TYPE [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x20,5)
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_MASK               0x0020
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_BITS               1
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_SHIFT              5

/* BRPHY3_DSP_TAP :: TAP17_C3 :: SPARE [04:04] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C3_SPARE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C3_SPARE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x10,4)
#define BRPHY3_DSP_TAP_TAP17_C3_SPARE_MASK                         0x0010
#define BRPHY3_DSP_TAP_TAP17_C3_SPARE_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP17_C3_SPARE_BITS                         1
#define BRPHY3_DSP_TAP_TAP17_C3_SPARE_SHIFT                        4

/* BRPHY3_DSP_TAP :: TAP17_C3 :: LA_CLKENABLE [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x8,3)
#define BRPHY3_DSP_TAP_TAP17_C3_LA_CLKENABLE_MASK                  0x0008
#define BRPHY3_DSP_TAP_TAP17_C3_LA_CLKENABLE_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP17_C3_LA_CLKENABLE_BITS                  1
#define BRPHY3_DSP_TAP_TAP17_C3_LA_CLKENABLE_SHIFT                 3

/* BRPHY3_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_INV [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x4,2)
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_MASK                0x0004
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_ALIGN               0
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_BITS                1
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_SHIFT               2

/* BRPHY3_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_GATE [01:00] */
#define Wr_BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x3,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP17_C3,0x3,0)
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_MASK               0x0003
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_BITS               2
#define BRPHY3_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_SHIFT              0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP18_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP18_C0 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_TAP18_C0_RESERVED0_MASK                     0xff00
#define BRPHY3_DSP_TAP_TAP18_C0_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP18_C0_RESERVED0_BITS                     8
#define BRPHY3_DSP_TAP_TAP18_C0_RESERVED0_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP18_C0 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY3_DSP_TAP_TAP18_C0_PEAK_NOISE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP18_C0,0xff,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP18_C0_PEAK_NOISE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP18_C0,0xff,0)
#define BRPHY3_DSP_TAP_TAP18_C0_PEAK_NOISE_MASK                    0x00ff
#define BRPHY3_DSP_TAP_TAP18_C0_PEAK_NOISE_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP18_C0_PEAK_NOISE_BITS                    8
#define BRPHY3_DSP_TAP_TAP18_C0_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP18_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP18_C1 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_TAP18_C1_RESERVED0_MASK                     0xff00
#define BRPHY3_DSP_TAP_TAP18_C1_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP18_C1_RESERVED0_BITS                     8
#define BRPHY3_DSP_TAP_TAP18_C1_RESERVED0_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP18_C1 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY3_DSP_TAP_TAP18_C1_PEAK_NOISE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP18_C1,0xff,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP18_C1_PEAK_NOISE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP18_C1,0xff,0)
#define BRPHY3_DSP_TAP_TAP18_C1_PEAK_NOISE_MASK                    0x00ff
#define BRPHY3_DSP_TAP_TAP18_C1_PEAK_NOISE_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP18_C1_PEAK_NOISE_BITS                    8
#define BRPHY3_DSP_TAP_TAP18_C1_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP18_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP18_C2 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_TAP18_C2_RESERVED0_MASK                     0xff00
#define BRPHY3_DSP_TAP_TAP18_C2_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP18_C2_RESERVED0_BITS                     8
#define BRPHY3_DSP_TAP_TAP18_C2_RESERVED0_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP18_C2 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY3_DSP_TAP_TAP18_C2_PEAK_NOISE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP18_C2,0xff,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP18_C2_PEAK_NOISE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP18_C2,0xff,0)
#define BRPHY3_DSP_TAP_TAP18_C2_PEAK_NOISE_MASK                    0x00ff
#define BRPHY3_DSP_TAP_TAP18_C2_PEAK_NOISE_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP18_C2_PEAK_NOISE_BITS                    8
#define BRPHY3_DSP_TAP_TAP18_C2_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP18_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP18_C3 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_TAP18_C3_RESERVED0_MASK                     0xff00
#define BRPHY3_DSP_TAP_TAP18_C3_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP18_C3_RESERVED0_BITS                     8
#define BRPHY3_DSP_TAP_TAP18_C3_RESERVED0_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP18_C3 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY3_DSP_TAP_TAP18_C3_PEAK_NOISE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP18_C3,0xff,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP18_C3_PEAK_NOISE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP18_C3,0xff,0)
#define BRPHY3_DSP_TAP_TAP18_C3_PEAK_NOISE_MASK                    0x00ff
#define BRPHY3_DSP_TAP_TAP18_C3_PEAK_NOISE_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP18_C3_PEAK_NOISE_BITS                    8
#define BRPHY3_DSP_TAP_TAP18_C3_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP20
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP20 :: reserved0 [15:14] */
#define BRPHY3_DSP_TAP_TAP20_RESERVED0_MASK                        0xc000
#define BRPHY3_DSP_TAP_TAP20_RESERVED0_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP20_RESERVED0_BITS                        2
#define BRPHY3_DSP_TAP_TAP20_RESERVED0_SHIFT                       14

/* BRPHY3_DSP_TAP :: TAP20 :: ENC_FIR_PATH_DELAY_ADJ [13:11] */
#define Wr_BRPHY3_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP20,0x3800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP20,0x3800,11)
#define BRPHY3_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_MASK           0x3800
#define BRPHY3_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY3_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_BITS           3
#define BRPHY3_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_SHIFT          11

/* BRPHY3_DSP_TAP :: TAP20 :: ENC_LMS_PATH_DELAY_ADJ [10:08] */
#define Wr_BRPHY3_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP20,0x700,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP20,0x700,8)
#define BRPHY3_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_MASK           0x0700
#define BRPHY3_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY3_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_BITS           3
#define BRPHY3_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_SHIFT          8

/* BRPHY3_DSP_TAP :: TAP20 :: ECHO_LMS_GAIN [07:06] */
#define Wr_BRPHY3_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP20,0xc0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP20,0xc0,6)
#define BRPHY3_DSP_TAP_TAP20_ECHO_LMS_GAIN_MASK                    0x00c0
#define BRPHY3_DSP_TAP_TAP20_ECHO_LMS_GAIN_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP20_ECHO_LMS_GAIN_BITS                    2
#define BRPHY3_DSP_TAP_TAP20_ECHO_LMS_GAIN_SHIFT                   6

/* BRPHY3_DSP_TAP :: TAP20 :: reserved1 [05:04] */
#define BRPHY3_DSP_TAP_TAP20_RESERVED1_MASK                        0x0030
#define BRPHY3_DSP_TAP_TAP20_RESERVED1_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP20_RESERVED1_BITS                        2
#define BRPHY3_DSP_TAP_TAP20_RESERVED1_SHIFT                       4

/* BRPHY3_DSP_TAP :: TAP20 :: TXDIG_PATH_DELAY_CTL [03:00] */
#define Wr_BRPHY3_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP20,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP20,0xf,0)
#define BRPHY3_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_MASK             0x000f
#define BRPHY3_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_ALIGN            0
#define BRPHY3_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_BITS             4
#define BRPHY3_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_SHIFT            0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP21
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP21 :: reserved0 [15:13] */
#define BRPHY3_DSP_TAP_TAP21_RESERVED0_MASK                        0xe000
#define BRPHY3_DSP_TAP_TAP21_RESERVED0_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP21_RESERVED0_BITS                        3
#define BRPHY3_DSP_TAP_TAP21_RESERVED0_SHIFT                       13

/* BRPHY3_DSP_TAP :: TAP21 :: PAUSEPCTPM_ABCD [12:09] */
#define Wr_BRPHY3_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP21,0x1e00,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP21,0x1e00,9)
#define BRPHY3_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_MASK                  0x1e00
#define BRPHY3_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_BITS                  4
#define BRPHY3_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_SHIFT                 9

/* BRPHY3_DSP_TAP :: TAP21 :: TX_EN_MON [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP21_TX_EN_MON(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP21,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP21_TX_EN_MON(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP21,0x100,8)
#define BRPHY3_DSP_TAP_TAP21_TX_EN_MON_MASK                        0x0100
#define BRPHY3_DSP_TAP_TAP21_TX_EN_MON_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP21_TX_EN_MON_BITS                        1
#define BRPHY3_DSP_TAP_TAP21_TX_EN_MON_SHIFT                       8

/* BRPHY3_DSP_TAP :: TAP21 :: LINK_CTL_1000T_MON [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP21,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP21,0x80,7)
#define BRPHY3_DSP_TAP_TAP21_LINK_CTL_1000T_MON_MASK               0x0080
#define BRPHY3_DSP_TAP_TAP21_LINK_CTL_1000T_MON_ALIGN              0
#define BRPHY3_DSP_TAP_TAP21_LINK_CTL_1000T_MON_BITS               1
#define BRPHY3_DSP_TAP_TAP21_LINK_CTL_1000T_MON_SHIFT              7

/* BRPHY3_DSP_TAP :: TAP21 :: REM_RCVR_STATUS_MON [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP21,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP21,0x40,6)
#define BRPHY3_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_MASK              0x0040
#define BRPHY3_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_ALIGN             0
#define BRPHY3_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_BITS              1
#define BRPHY3_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_SHIFT             6

/* BRPHY3_DSP_TAP :: TAP21 :: ALIGN_OK_MON [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP21_ALIGN_OK_MON(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP21,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP21_ALIGN_OK_MON(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP21,0x20,5)
#define BRPHY3_DSP_TAP_TAP21_ALIGN_OK_MON_MASK                     0x0020
#define BRPHY3_DSP_TAP_TAP21_ALIGN_OK_MON_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP21_ALIGN_OK_MON_BITS                     1
#define BRPHY3_DSP_TAP_TAP21_ALIGN_OK_MON_SHIFT                    5

/* BRPHY3_DSP_TAP :: TAP21 :: MAIN_PHYC_STATE [04:00] */
#define Wr_BRPHY3_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP21,0x1f,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP21,0x1f,0)
#define BRPHY3_DSP_TAP_TAP21_MAIN_PHYC_STATE_MASK                  0x001f
#define BRPHY3_DSP_TAP_TAP21_MAIN_PHYC_STATE_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP21_MAIN_PHYC_STATE_BITS                  5
#define BRPHY3_DSP_TAP_TAP21_MAIN_PHYC_STATE_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP22
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP22 :: KRDONE [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP22_KRDONE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP22,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP22_KRDONE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP22,0x8000,15)
#define BRPHY3_DSP_TAP_TAP22_KRDONE_MASK                           0x8000
#define BRPHY3_DSP_TAP_TAP22_KRDONE_ALIGN                          0
#define BRPHY3_DSP_TAP_TAP22_KRDONE_BITS                           1
#define BRPHY3_DSP_TAP_TAP22_KRDONE_SHIFT                          15

/* BRPHY3_DSP_TAP :: TAP22 :: MAXWAIT_TIMER_DONE [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP22,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP22,0x4000,14)
#define BRPHY3_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_MASK               0x4000
#define BRPHY3_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_BITS               1
#define BRPHY3_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_SHIFT              14

/* BRPHY3_DSP_TAP :: TAP22 :: LINK_MONITOR_STATE_MON [13:12] */
#define Wr_BRPHY3_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP22,0x3000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP22,0x3000,12)
#define BRPHY3_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_MASK           0x3000
#define BRPHY3_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_ALIGN          0
#define BRPHY3_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_BITS           2
#define BRPHY3_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_SHIFT          12

/* BRPHY3_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_D [11:09] */
#define Wr_BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP22,0xe00,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP22,0xe00,9)
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_D_MASK                  0x0e00
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_D_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_D_BITS                  3
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_D_SHIFT                 9

/* BRPHY3_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_C [08:06] */
#define Wr_BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP22,0x1c0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP22,0x1c0,6)
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_C_MASK                  0x01c0
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_C_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_C_BITS                  3
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_C_SHIFT                 6

/* BRPHY3_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_B [05:03] */
#define Wr_BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP22,0x38,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP22,0x38,3)
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_B_MASK                  0x0038
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_B_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_B_BITS                  3
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_B_SHIFT                 3

/* BRPHY3_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_A [02:00] */
#define Wr_BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP22,0x7,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP22,0x7,0)
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_A_MASK                  0x0007
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_A_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_A_BITS                  3
#define BRPHY3_DSP_TAP_TAP22_PHYC_SUBSTATE_A_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP23
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP23 :: reserved0 [15:13] */
#define BRPHY3_DSP_TAP_TAP23_RESERVED0_MASK                        0xe000
#define BRPHY3_DSP_TAP_TAP23_RESERVED0_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP23_RESERVED0_BITS                        3
#define BRPHY3_DSP_TAP_TAP23_RESERVED0_SHIFT                       13

/* BRPHY3_DSP_TAP :: TAP23 :: ALIGN_REDO_MON [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP23_ALIGN_REDO_MON(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP23,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP23_ALIGN_REDO_MON(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP23,0x1000,12)
#define BRPHY3_DSP_TAP_TAP23_ALIGN_REDO_MON_MASK                   0x1000
#define BRPHY3_DSP_TAP_TAP23_ALIGN_REDO_MON_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP23_ALIGN_REDO_MON_BITS                   1
#define BRPHY3_DSP_TAP_TAP23_ALIGN_REDO_MON_SHIFT                  12

/* BRPHY3_DSP_TAP :: TAP23 :: MSEOK2_MON [11:08] */
#define Wr_BRPHY3_DSP_TAP_TAP23_MSEOK2_MON(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP23,0xf00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP23_MSEOK2_MON(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP23,0xf00,8)
#define BRPHY3_DSP_TAP_TAP23_MSEOK2_MON_MASK                       0x0f00
#define BRPHY3_DSP_TAP_TAP23_MSEOK2_MON_ALIGN                      0
#define BRPHY3_DSP_TAP_TAP23_MSEOK2_MON_BITS                       4
#define BRPHY3_DSP_TAP_TAP23_MSEOK2_MON_SHIFT                      8

/* BRPHY3_DSP_TAP :: TAP23 :: MSEOK1_MON [07:04] */
#define Wr_BRPHY3_DSP_TAP_TAP23_MSEOK1_MON(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP23,0xf0,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP23_MSEOK1_MON(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP23,0xf0,4)
#define BRPHY3_DSP_TAP_TAP23_MSEOK1_MON_MASK                       0x00f0
#define BRPHY3_DSP_TAP_TAP23_MSEOK1_MON_ALIGN                      0
#define BRPHY3_DSP_TAP_TAP23_MSEOK1_MON_BITS                       4
#define BRPHY3_DSP_TAP_TAP23_MSEOK1_MON_SHIFT                      4

/* BRPHY3_DSP_TAP :: TAP23 :: ENERGY_DETECT [03:00] */
#define Wr_BRPHY3_DSP_TAP_TAP23_ENERGY_DETECT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP23,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP23_ENERGY_DETECT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP23,0xf,0)
#define BRPHY3_DSP_TAP_TAP23_ENERGY_DETECT_MASK                    0x000f
#define BRPHY3_DSP_TAP_TAP23_ENERGY_DETECT_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP23_ENERGY_DETECT_BITS                    4
#define BRPHY3_DSP_TAP_TAP23_ENERGY_DETECT_SHIFT                   0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP24
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP24 :: PHYC_OUTPUT_OV [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x8000,15)
#define BRPHY3_DSP_TAP_TAP24_PHYC_OUTPUT_OV_MASK                   0x8000
#define BRPHY3_DSP_TAP_TAP24_PHYC_OUTPUT_OV_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP24_PHYC_OUTPUT_OV_BITS                   1
#define BRPHY3_DSP_TAP_TAP24_PHYC_OUTPUT_OV_SHIFT                  15

/* BRPHY3_DSP_TAP :: TAP24 :: STABLE_RECENTER_EN [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x4000,14)
#define BRPHY3_DSP_TAP_TAP24_STABLE_RECENTER_EN_MASK               0x4000
#define BRPHY3_DSP_TAP_TAP24_STABLE_RECENTER_EN_ALIGN              0
#define BRPHY3_DSP_TAP_TAP24_STABLE_RECENTER_EN_BITS               1
#define BRPHY3_DSP_TAP_TAP24_STABLE_RECENTER_EN_SHIFT              14

/* BRPHY3_DSP_TAP :: TAP24 :: PHYC_MSE_FIX [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP24_PHYC_MSE_FIX(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_PHYC_MSE_FIX(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x2000,13)
#define BRPHY3_DSP_TAP_TAP24_PHYC_MSE_FIX_MASK                     0x2000
#define BRPHY3_DSP_TAP_TAP24_PHYC_MSE_FIX_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP24_PHYC_MSE_FIX_BITS                     1
#define BRPHY3_DSP_TAP_TAP24_PHYC_MSE_FIX_SHIFT                    13

/* BRPHY3_DSP_TAP :: TAP24 :: DEGATEDFEPC_ABCD_OV [12:09] */
#define Wr_BRPHY3_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x1e00,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x1e00,9)
#define BRPHY3_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_MASK              0x1e00
#define BRPHY3_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_ALIGN             0
#define BRPHY3_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_BITS              4
#define BRPHY3_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_SHIFT             9

/* BRPHY3_DSP_TAP :: TAP24 :: NBRSTWTCH_OV [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP24_NBRSTWTCH_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_NBRSTWTCH_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x100,8)
#define BRPHY3_DSP_TAP_TAP24_NBRSTWTCH_OV_MASK                     0x0100
#define BRPHY3_DSP_TAP_TAP24_NBRSTWTCH_OV_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP24_NBRSTWTCH_OV_BITS                     1
#define BRPHY3_DSP_TAP_TAP24_NBRSTWTCH_OV_SHIFT                    8

/* BRPHY3_DSP_TAP :: TAP24 :: RC_LPBKFIFO_T_OV [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x80,7)
#define BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_MASK                 0x0080
#define BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_ALIGN                0
#define BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_BITS                 1
#define BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_SHIFT                7

/* BRPHY3_DSP_TAP :: TAP24 :: RC_LPBKFIFO_N_OV [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x40,6)
#define BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_MASK                 0x0040
#define BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_ALIGN                0
#define BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_BITS                 1
#define BRPHY3_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_SHIFT                6

/* BRPHY3_DSP_TAP :: TAP24 :: PCS_RESET_OV [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP24_PCS_RESET_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_PCS_RESET_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x20,5)
#define BRPHY3_DSP_TAP_TAP24_PCS_RESET_OV_MASK                     0x0020
#define BRPHY3_DSP_TAP_TAP24_PCS_RESET_OV_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP24_PCS_RESET_OV_BITS                     1
#define BRPHY3_DSP_TAP_TAP24_PCS_RESET_OV_SHIFT                    5

/* BRPHY3_DSP_TAP :: TAP24 :: PHYC_PCS_RSTATE_OV [04:03] */
#define Wr_BRPHY3_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x18,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x18,3)
#define BRPHY3_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_MASK               0x0018
#define BRPHY3_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_ALIGN              0
#define BRPHY3_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_BITS               2
#define BRPHY3_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_SHIFT              3

/* BRPHY3_DSP_TAP :: TAP24 :: LOC_RCVR_STATUS_OV [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x4,2)
#define BRPHY3_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_MASK               0x0004
#define BRPHY3_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_ALIGN              0
#define BRPHY3_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_BITS               1
#define BRPHY3_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_SHIFT              2

/* BRPHY3_DSP_TAP :: TAP24 :: PHYC_TXMODE_OV [01:00] */
#define Wr_BRPHY3_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP24,0x3,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP24,0x3,0)
#define BRPHY3_DSP_TAP_TAP24_PHYC_TXMODE_OV_MASK                   0x0003
#define BRPHY3_DSP_TAP_TAP24_PHYC_TXMODE_OV_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP24_PHYC_TXMODE_OV_BITS                   2
#define BRPHY3_DSP_TAP_TAP24_PHYC_TXMODE_OV_SHIFT                  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP25
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP25 :: reserved0 [15:15] */
#define BRPHY3_DSP_TAP_TAP25_RESERVED0_MASK                        0x8000
#define BRPHY3_DSP_TAP_TAP25_RESERVED0_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP25_RESERVED0_BITS                        1
#define BRPHY3_DSP_TAP_TAP25_RESERVED0_SHIFT                       15

/* BRPHY3_DSP_TAP :: TAP25 :: KRDONE_OV [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP25_KRDONE_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP25,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP25_KRDONE_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP25,0x4000,14)
#define BRPHY3_DSP_TAP_TAP25_KRDONE_OV_MASK                        0x4000
#define BRPHY3_DSP_TAP_TAP25_KRDONE_OV_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP25_KRDONE_OV_BITS                        1
#define BRPHY3_DSP_TAP_TAP25_KRDONE_OV_SHIFT                       14

/* BRPHY3_DSP_TAP :: TAP25 :: ALIGN_REDO_OV [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP25_ALIGN_REDO_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP25,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP25_ALIGN_REDO_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP25,0x2000,13)
#define BRPHY3_DSP_TAP_TAP25_ALIGN_REDO_OV_MASK                    0x2000
#define BRPHY3_DSP_TAP_TAP25_ALIGN_REDO_OV_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP25_ALIGN_REDO_OV_BITS                    1
#define BRPHY3_DSP_TAP_TAP25_ALIGN_REDO_OV_SHIFT                   13

/* BRPHY3_DSP_TAP :: TAP25 :: RC_ADCFIFO_N_OV [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP25,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP25,0x1000,12)
#define BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_MASK                  0x1000
#define BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_BITS                  1
#define BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_SHIFT                 12

/* BRPHY3_DSP_TAP :: TAP25 :: RC_ADCFIFO_T_OV [11:08] */
#define Wr_BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP25,0xf00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP25,0xf00,8)
#define BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_MASK                  0x0f00
#define BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_BITS                  4
#define BRPHY3_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_SHIFT                 8

/* BRPHY3_DSP_TAP :: TAP25 :: reserved1 [07:00] */
#define BRPHY3_DSP_TAP_TAP25_RESERVED1_MASK                        0x00ff
#define BRPHY3_DSP_TAP_TAP25_RESERVED1_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP25_RESERVED1_BITS                        8
#define BRPHY3_DSP_TAP_TAP25_RESERVED1_SHIFT                       0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP26
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP26 :: MSE_INPUT_OV [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP26_MSE_INPUT_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP26,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP26_MSE_INPUT_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP26,0x8000,15)
#define BRPHY3_DSP_TAP_TAP26_MSE_INPUT_OV_MASK                     0x8000
#define BRPHY3_DSP_TAP_TAP26_MSE_INPUT_OV_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP26_MSE_INPUT_OV_BITS                     1
#define BRPHY3_DSP_TAP_TAP26_MSE_INPUT_OV_SHIFT                    15

/* BRPHY3_DSP_TAP :: TAP26 :: MSEOK2_OV [14:11] */
#define Wr_BRPHY3_DSP_TAP_TAP26_MSEOK2_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP26,0x7800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP26_MSEOK2_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP26,0x7800,11)
#define BRPHY3_DSP_TAP_TAP26_MSEOK2_OV_MASK                        0x7800
#define BRPHY3_DSP_TAP_TAP26_MSEOK2_OV_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP26_MSEOK2_OV_BITS                        4
#define BRPHY3_DSP_TAP_TAP26_MSEOK2_OV_SHIFT                       11

/* BRPHY3_DSP_TAP :: TAP26 :: MSEOK1_OV [10:07] */
#define Wr_BRPHY3_DSP_TAP_TAP26_MSEOK1_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP26,0x780,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP26_MSEOK1_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP26,0x780,7)
#define BRPHY3_DSP_TAP_TAP26_MSEOK1_OV_MASK                        0x0780
#define BRPHY3_DSP_TAP_TAP26_MSEOK1_OV_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP26_MSEOK1_OV_BITS                        4
#define BRPHY3_DSP_TAP_TAP26_MSEOK1_OV_SHIFT                       7

/* BRPHY3_DSP_TAP :: TAP26 :: ENERGY_DETECT_OV [06:03] */
#define Wr_BRPHY3_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP26,0x78,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP26,0x78,3)
#define BRPHY3_DSP_TAP_TAP26_ENERGY_DETECT_OV_MASK                 0x0078
#define BRPHY3_DSP_TAP_TAP26_ENERGY_DETECT_OV_ALIGN                0
#define BRPHY3_DSP_TAP_TAP26_ENERGY_DETECT_OV_BITS                 4
#define BRPHY3_DSP_TAP_TAP26_ENERGY_DETECT_OV_SHIFT                3

/* BRPHY3_DSP_TAP :: TAP26 :: PCS_INPUT_OV [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP26_PCS_INPUT_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP26,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP26_PCS_INPUT_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP26,0x4,2)
#define BRPHY3_DSP_TAP_TAP26_PCS_INPUT_OV_MASK                     0x0004
#define BRPHY3_DSP_TAP_TAP26_PCS_INPUT_OV_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP26_PCS_INPUT_OV_BITS                     1
#define BRPHY3_DSP_TAP_TAP26_PCS_INPUT_OV_SHIFT                    2

/* BRPHY3_DSP_TAP :: TAP26 :: REM_RCVR_STATUS_OV [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP26,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP26,0x2,1)
#define BRPHY3_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_MASK               0x0002
#define BRPHY3_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_ALIGN              0
#define BRPHY3_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_BITS               1
#define BRPHY3_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_SHIFT              1

/* BRPHY3_DSP_TAP :: TAP26 :: ALIGN_OK_OV [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP26_ALIGN_OK_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP26,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP26_ALIGN_OK_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP26,0x1,0)
#define BRPHY3_DSP_TAP_TAP26_ALIGN_OK_OV_MASK                      0x0001
#define BRPHY3_DSP_TAP_TAP26_ALIGN_OK_OV_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP26_ALIGN_OK_OV_BITS                      1
#define BRPHY3_DSP_TAP_TAP26_ALIGN_OK_OV_SHIFT                     0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP27
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP27 :: reserved0 [15:09] */
#define BRPHY3_DSP_TAP_TAP27_RESERVED0_MASK                        0xfe00
#define BRPHY3_DSP_TAP_TAP27_RESERVED0_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP27_RESERVED0_BITS                        7
#define BRPHY3_DSP_TAP_TAP27_RESERVED0_SHIFT                       9

/* BRPHY3_DSP_TAP :: TAP27 :: FILTER_CTL_PAUSE_OV [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP27,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP27,0x100,8)
#define BRPHY3_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_MASK              0x0100
#define BRPHY3_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_ALIGN             0
#define BRPHY3_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_BITS              1
#define BRPHY3_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_SHIFT             8

/* BRPHY3_DSP_TAP :: TAP27 :: PAUSEPCTPM_ABCD_OV [07:04] */
#define Wr_BRPHY3_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP27,0xf0,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP27,0xf0,4)
#define BRPHY3_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_MASK               0x00f0
#define BRPHY3_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_ALIGN              0
#define BRPHY3_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_BITS               4
#define BRPHY3_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_SHIFT              4

/* BRPHY3_DSP_TAP :: TAP27 :: AUTONEG_INPUT_OV [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP27,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP27,0x8,3)
#define BRPHY3_DSP_TAP_TAP27_AUTONEG_INPUT_OV_MASK                 0x0008
#define BRPHY3_DSP_TAP_TAP27_AUTONEG_INPUT_OV_ALIGN                0
#define BRPHY3_DSP_TAP_TAP27_AUTONEG_INPUT_OV_BITS                 1
#define BRPHY3_DSP_TAP_TAP27_AUTONEG_INPUT_OV_SHIFT                3

/* BRPHY3_DSP_TAP :: TAP27 :: LINK_SCAN_100TX_OV [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP27,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP27,0x4,2)
#define BRPHY3_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_MASK               0x0004
#define BRPHY3_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_ALIGN              0
#define BRPHY3_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_BITS               1
#define BRPHY3_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_SHIFT              2

/* BRPHY3_DSP_TAP :: TAP27 :: LINK_ENAB_100TX_OV [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP27,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP27,0x2,1)
#define BRPHY3_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_MASK               0x0002
#define BRPHY3_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_ALIGN              0
#define BRPHY3_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_BITS               1
#define BRPHY3_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_SHIFT              1

/* BRPHY3_DSP_TAP :: TAP27 :: LINK_CTL_1000T_OV [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP27,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP27,0x1,0)
#define BRPHY3_DSP_TAP_TAP27_LINK_CTL_1000T_OV_MASK                0x0001
#define BRPHY3_DSP_TAP_TAP27_LINK_CTL_1000T_OV_ALIGN               0
#define BRPHY3_DSP_TAP_TAP27_LINK_CTL_1000T_OV_BITS                1
#define BRPHY3_DSP_TAP_TAP27_LINK_CTL_1000T_OV_SHIFT               0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP28
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP28 :: reserved0 [15:04] */
#define BRPHY3_DSP_TAP_TAP28_RESERVED0_MASK                        0xfff0
#define BRPHY3_DSP_TAP_TAP28_RESERVED0_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP28_RESERVED0_BITS                        12
#define BRPHY3_DSP_TAP_TAP28_RESERVED0_SHIFT                       4

/* BRPHY3_DSP_TAP :: TAP28 :: PLLPRAMP_ABCD_OV [03:00] */
#define Wr_BRPHY3_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP28,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP28,0xf,0)
#define BRPHY3_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_MASK                 0x000f
#define BRPHY3_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_ALIGN                0
#define BRPHY3_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_BITS                 4
#define BRPHY3_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP29
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP29 :: TIMER_MODE_D_FORCE [15:14] */
#define Wr_BRPHY3_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP29,0xc000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP29,0xc000,14)
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_MASK               0xc000
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_BITS               2
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_SHIFT              14

/* BRPHY3_DSP_TAP :: TAP29 :: TIMER_MODE_C_FORCE [13:12] */
#define Wr_BRPHY3_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP29,0x3000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP29,0x3000,12)
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_MASK               0x3000
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_BITS               2
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_SHIFT              12

/* BRPHY3_DSP_TAP :: TAP29 :: TIMER_MODE_B_FORCE [11:10] */
#define Wr_BRPHY3_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP29,0xc00,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP29,0xc00,10)
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_MASK               0x0c00
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_BITS               2
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_SHIFT              10

/* BRPHY3_DSP_TAP :: TAP29 :: TIMER_MODE_A_FORCE [09:08] */
#define Wr_BRPHY3_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP29,0x300,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP29,0x300,8)
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_MASK               0x0300
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_BITS               2
#define BRPHY3_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_SHIFT              8

/* BRPHY3_DSP_TAP :: TAP29 :: MAINSTATE_FORCE [07:04] */
#define Wr_BRPHY3_DSP_TAP_TAP29_MAINSTATE_FORCE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP29,0xf0,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP29_MAINSTATE_FORCE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP29,0xf0,4)
#define BRPHY3_DSP_TAP_TAP29_MAINSTATE_FORCE_MASK                  0x00f0
#define BRPHY3_DSP_TAP_TAP29_MAINSTATE_FORCE_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP29_MAINSTATE_FORCE_BITS                  4
#define BRPHY3_DSP_TAP_TAP29_MAINSTATE_FORCE_SHIFT                 4

/* BRPHY3_DSP_TAP :: TAP29 :: FORCE_PHYC_STATE [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP29,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP29,0x8,3)
#define BRPHY3_DSP_TAP_TAP29_FORCE_PHYC_STATE_MASK                 0x0008
#define BRPHY3_DSP_TAP_TAP29_FORCE_PHYC_STATE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP29_FORCE_PHYC_STATE_BITS                 1
#define BRPHY3_DSP_TAP_TAP29_FORCE_PHYC_STATE_SHIFT                3

/* BRPHY3_DSP_TAP :: TAP29 :: HOLD_IN_ALT [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP29_HOLD_IN_ALT(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP29,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP29_HOLD_IN_ALT(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP29,0x4,2)
#define BRPHY3_DSP_TAP_TAP29_HOLD_IN_ALT_MASK                      0x0004
#define BRPHY3_DSP_TAP_TAP29_HOLD_IN_ALT_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP29_HOLD_IN_ALT_BITS                      1
#define BRPHY3_DSP_TAP_TAP29_HOLD_IN_ALT_SHIFT                     2

/* BRPHY3_DSP_TAP :: TAP29 :: FORCE_ALT_STATE_PATH [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP29,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP29,0x2,1)
#define BRPHY3_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_MASK             0x0002
#define BRPHY3_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_ALIGN            0
#define BRPHY3_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_BITS             1
#define BRPHY3_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_SHIFT            1

/* BRPHY3_DSP_TAP :: TAP29 :: PHYC_FAST_STATE_MODE [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP29,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP29,0x1,0)
#define BRPHY3_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_MASK             0x0001
#define BRPHY3_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_ALIGN            0
#define BRPHY3_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_BITS             1
#define BRPHY3_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_SHIFT            0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP30
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP30 :: reserved0 [15:12] */
#define BRPHY3_DSP_TAP_TAP30_RESERVED0_MASK                        0xf000
#define BRPHY3_DSP_TAP_TAP30_RESERVED0_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP30_RESERVED0_BITS                        4
#define BRPHY3_DSP_TAP_TAP30_RESERVED0_SHIFT                       12

/* BRPHY3_DSP_TAP :: TAP30 :: SUBSTATE_D_FORCE [11:09] */
#define Wr_BRPHY3_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP30,0xe00,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP30,0xe00,9)
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_D_FORCE_MASK                 0x0e00
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_D_FORCE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_D_FORCE_BITS                 3
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_D_FORCE_SHIFT                9

/* BRPHY3_DSP_TAP :: TAP30 :: SUBSTATE_C_FORCE [08:06] */
#define Wr_BRPHY3_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP30,0x1c0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP30,0x1c0,6)
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_C_FORCE_MASK                 0x01c0
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_C_FORCE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_C_FORCE_BITS                 3
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_C_FORCE_SHIFT                6

/* BRPHY3_DSP_TAP :: TAP30 :: SUBSTATE_B_FORCE [05:03] */
#define Wr_BRPHY3_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP30,0x38,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP30,0x38,3)
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_B_FORCE_MASK                 0x0038
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_B_FORCE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_B_FORCE_BITS                 3
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_B_FORCE_SHIFT                3

/* BRPHY3_DSP_TAP :: TAP30 :: SUBSTATE_A_FORCE [02:00] */
#define Wr_BRPHY3_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP30,0x7,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP30,0x7,0)
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_A_FORCE_MASK                 0x0007
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_A_FORCE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_A_FORCE_BITS                 3
#define BRPHY3_DSP_TAP_TAP30_SUBSTATE_A_FORCE_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP31_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP31_C0 :: SDSEL_OV [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x8000,15)
#define BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_MASK                      0x8000
#define BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_ALIGN                     0
#define BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_BITS                      1
#define BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_SHIFT                     15

/* BRPHY3_DSP_TAP :: TAP31_C0 :: SDSEL_OV_EN [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x4000,14)
#define BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_EN_MASK                   0x4000
#define BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_EN_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_EN_BITS                   1
#define BRPHY3_DSP_TAP_TAP31_C0_SDSEL_OV_EN_SHIFT                  14

/* BRPHY3_DSP_TAP :: TAP31_C0 :: ADC_BER_TPOUT_EN [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x2000,13)
#define BRPHY3_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_MASK              0x2000
#define BRPHY3_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_ALIGN             0
#define BRPHY3_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_BITS              1
#define BRPHY3_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_SHIFT             13

/* BRPHY3_DSP_TAP :: TAP31_C0 :: SWAPCD_OV [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP31_C0_SWAPCD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP31_C0_SWAPCD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x1000,12)
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPCD_OV_MASK                     0x1000
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPCD_OV_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPCD_OV_BITS                     1
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPCD_OV_SHIFT                    12

/* BRPHY3_DSP_TAP :: TAP31_C0 :: SWAPAB_OV [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x800,11)
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_OV_MASK                     0x0800
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_OV_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_OV_BITS                     1
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_OV_SHIFT                    11

/* BRPHY3_DSP_TAP :: TAP31_C0 :: SWAPAB_CD_OV_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP31_C0,0x400,10)
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_MASK               0x0400
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_ALIGN              0
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_BITS               1
#define BRPHY3_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_SHIFT              10

/* BRPHY3_DSP_TAP :: TAP31_C0 :: reserved0 [09:00] */
#define BRPHY3_DSP_TAP_TAP31_C0_RESERVED0_MASK                     0x03ff
#define BRPHY3_DSP_TAP_TAP31_C0_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP31_C0_RESERVED0_BITS                     10
#define BRPHY3_DSP_TAP_TAP31_C0_RESERVED0_SHIFT                    0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP32_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP32_C0 :: reserved0 [15:09] */
#define BRPHY3_DSP_TAP_TAP32_C0_RESERVED0_MASK                     0xfe00
#define BRPHY3_DSP_TAP_TAP32_C0_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP32_C0_RESERVED0_BITS                     7
#define BRPHY3_DSP_TAP_TAP32_C0_RESERVED0_SHIFT                    9

/* BRPHY3_DSP_TAP :: TAP32_C0 :: COEFF_RAM_TM_CTRL [08:04] */
#define Wr_BRPHY3_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x1f0,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x1f0,4)
#define BRPHY3_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_MASK             0x01f0
#define BRPHY3_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_ALIGN            0
#define BRPHY3_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_BITS             5
#define BRPHY3_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_SHIFT            4

/* BRPHY3_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_D [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x8,3)
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_MASK         0x0008
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_ALIGN        0
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_BITS         1
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_SHIFT        3

/* BRPHY3_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_C [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x4,2)
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_MASK         0x0004
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_ALIGN        0
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_BITS         1
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_SHIFT        2

/* BRPHY3_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_AB [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x2,1)
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_MASK        0x0002
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_ALIGN       0
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_BITS        1
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_SHIFT       1

/* BRPHY3_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_A [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP32_C0,0x1,0)
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_MASK         0x0001
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_ALIGN        0
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_BITS         1
#define BRPHY3_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_SHIFT        0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FDFE_OV_RD
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_MSB [15:14] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0xc000,14,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0xc000,14)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_MASK             0xc000
#define BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_ALIGN            0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_BITS             2
#define BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_SHIFT            14

/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_LSB [13:13] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x2000,13)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_MASK             0x2000
#define BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_ALIGN            0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_BITS             1
#define BRPHY3_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_SHIFT            13

/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: BETA_OV [12:12] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x1000,12)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_MASK                     0x1000
#define BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_ALIGN                    0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_BITS                     1
#define BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_SHIFT                    12

/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: BETA_OV_VAL [11:09] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0xe00,9,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0xe00,9)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_MASK                 0x0e00
#define BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_ALIGN                0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_BITS                 3
#define BRPHY3_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_SHIFT                9

/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: FDFE_MSE_SEL_OV [08:08] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x100,8)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_MASK             0x0100
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_ALIGN            0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_BITS             1
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_SHIFT            8

/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: FDFE_CLEAR_OV [07:07] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x80,7)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_MASK               0x0080
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_ALIGN              0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_BITS               1
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_SHIFT              7

/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: FDFE_OUTEN_OV [06:06] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x40,6)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_MASK               0x0040
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_ALIGN              0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_BITS               1
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_SHIFT              6

/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: FDFE_UPEN_OV [05:05] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x20,5)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_MASK                0x0020
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_ALIGN               0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_BITS                1
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_SHIFT               5

/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: FDFE_OV_EN [04:04] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0x10,4)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_MASK                  0x0010
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_ALIGN                 0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_BITS                  1
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_SHIFT                 4

/* BRPHY3_DSP_TAP :: FDFE_OV_RD :: FDFE_RD_SEL [03:00] */
#define Wr_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_OV_RD,0xf,0)
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_MASK                 0x000f
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_ALIGN                0
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_BITS                 4
#define BRPHY3_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FDFE_COEFF
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FDFE_COEFF :: FDFE_COEFF [15:00] */
#define Wr_BRPHY3_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) WriteReg16(BRPHY3_DSP_TAP_FDFE_COEFF,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) ReadReg16(BRPHY3_DSP_TAP_FDFE_COEFF)
#define BRPHY3_DSP_TAP_FDFE_COEFF_FDFE_COEFF_MASK                  0xffff
#define BRPHY3_DSP_TAP_FDFE_COEFF_FDFE_COEFF_ALIGN                 0
#define BRPHY3_DSP_TAP_FDFE_COEFF_FDFE_COEFF_BITS                  16
#define BRPHY3_DSP_TAP_FDFE_COEFF_FDFE_COEFF_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FDFE_BETA_THRESHOLD
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_3 [15:12] */
#define Wr_BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12)
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_MASK   0xf000
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_ALIGN  0
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_BITS   4
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_SHIFT  12

/* BRPHY3_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_2 [11:08] */
#define Wr_BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8)
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_MASK   0x0f00
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_ALIGN  0
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_BITS   4
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_SHIFT  8

/* BRPHY3_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_1 [07:04] */
#define Wr_BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4)
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_MASK   0x00f0
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_ALIGN  0
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_BITS   4
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_SHIFT  4

/* BRPHY3_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_0 [03:00] */
#define Wr_BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) WriteRegBits16(BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) ReadRegBits16(BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0)
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_MASK   0x000f
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_ALIGN  0
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_BITS   4
#define BRPHY3_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_SHIFT  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP33_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SD_EN [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x8000,15)
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_MASK               0x8000
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_ALIGN              0
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_BITS               1
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_SHIFT              15

/* BRPHY3_DSP_TAP :: TAP33_C0 :: EEE_MASK_MSE_EN [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x4000,14)
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_MASK               0x4000
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_ALIGN              0
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_BITS               1
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_SHIFT              14

/* BRPHY3_DSP_TAP :: TAP33_C0 :: EEE_PHYC_STATUS_TO_LED [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x2000,13)
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_MASK        0x2000
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_ALIGN       0
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_BITS        1
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_SHIFT       13

/* BRPHY3_DSP_TAP :: TAP33_C0 :: EEE_PLL_TEST_MODE [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x1000,12)
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_MASK             0x1000
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_ALIGN            0
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_BITS             1
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_SHIFT            12

/* BRPHY3_DSP_TAP :: TAP33_C0 :: SPARE11 [11:11] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_SPARE11(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_SPARE11(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x800,11)
#define BRPHY3_DSP_TAP_TAP33_C0_SPARE11_MASK                       0x0800
#define BRPHY3_DSP_TAP_TAP33_C0_SPARE11_ALIGN                      0
#define BRPHY3_DSP_TAP_TAP33_C0_SPARE11_BITS                       1
#define BRPHY3_DSP_TAP_TAP33_C0_SPARE11_SHIFT                      11

/* BRPHY3_DSP_TAP :: TAP33_C0 :: EEE_AFE_STOPPABLE [10:10] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x400,10)
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_MASK             0x0400
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_ALIGN            0
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_BITS             1
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_SHIFT            10

/* BRPHY3_DSP_TAP :: TAP33_C0 :: EEE_CLOCK_STOPPABLE [09:09] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x200,9)
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_MASK           0x0200
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_ALIGN          0
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_BITS           1
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_SHIFT          9

/* BRPHY3_DSP_TAP :: TAP33_C0 :: EEE_SD_SEL [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x100,8)
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_SD_SEL_MASK                    0x0100
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_SD_SEL_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_SD_SEL_BITS                    1
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_SD_SEL_SHIFT                   8

/* BRPHY3_DSP_TAP :: TAP33_C0 :: MAXMSEOK1_CHG_EN [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x80,7)
#define BRPHY3_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_MASK              0x0080
#define BRPHY3_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_ALIGN             0
#define BRPHY3_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_BITS              1
#define BRPHY3_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_SHIFT             7

/* BRPHY3_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SCALE [06:05] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x60,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x60,5)
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_MASK               0x0060
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_BITS               2
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_SHIFT              5

/* BRPHY3_DSP_TAP :: TAP33_C0 :: LPI_TRACK_MODE [04:03] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x18,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x18,3)
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_MASK                0x0018
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_ALIGN               0
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_BITS                2
#define BRPHY3_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_SHIFT               3

/* BRPHY3_DSP_TAP :: TAP33_C0 :: EEE_FREQ_UNLOCK [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x4,2)
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_MASK               0x0004
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_ALIGN              0
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_BITS               1
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_SHIFT              2

/* BRPHY3_DSP_TAP :: TAP33_C0 :: EEE_QUICK_ALIGN [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x2,1)
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_MASK               0x0002
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_ALIGN              0
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_BITS               1
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_SHIFT              1

/* BRPHY3_DSP_TAP :: TAP33_C0 :: EEE_SD300 [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C0_EEE_SD300(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C0_EEE_SD300(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C0,0x1,0)
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_SD300_MASK                     0x0001
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_SD300_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_SD300_BITS                     1
#define BRPHY3_DSP_TAP_TAP33_C0_EEE_SD300_SHIFT                    0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP33_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP33_C1 :: SD_ASSERT_THD [15:08] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C1,0xff00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C1,0xff00,8)
#define BRPHY3_DSP_TAP_TAP33_C1_SD_ASSERT_THD_MASK                 0xff00
#define BRPHY3_DSP_TAP_TAP33_C1_SD_ASSERT_THD_ALIGN                0
#define BRPHY3_DSP_TAP_TAP33_C1_SD_ASSERT_THD_BITS                 8
#define BRPHY3_DSP_TAP_TAP33_C1_SD_ASSERT_THD_SHIFT                8

/* BRPHY3_DSP_TAP :: TAP33_C1 :: SD_DEASSERT_THD [07:00] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C1,0xff,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C1,0xff,0)
#define BRPHY3_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_MASK               0x00ff
#define BRPHY3_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_ALIGN              0
#define BRPHY3_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_BITS               8
#define BRPHY3_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_SHIFT              0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP33_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP33_C2 :: EEE_PHASE_REACQ_TUNE [15:14] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0xc000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0xc000,14)
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_MASK          0xc000
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_ALIGN         0
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_BITS          2
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_SHIFT         14

/* BRPHY3_DSP_TAP :: TAP33_C2 :: EEE_WAIT_SCR_LOCK_N [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0x2000,13)
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_MASK           0x2000
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_ALIGN          0
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_BITS           1
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_SHIFT          13

/* BRPHY3_DSP_TAP :: TAP33_C2 :: LOC_RCVR_WAIT_ALIGNC_N [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0x1000,12)
#define BRPHY3_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_MASK        0x1000
#define BRPHY3_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_ALIGN       0
#define BRPHY3_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_BITS        1
#define BRPHY3_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_SHIFT       12

/* BRPHY3_DSP_TAP :: TAP33_C2 :: EEE_WAKEMZ_TUNE [11:08] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0xf00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0xf00,8)
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_MASK               0x0f00
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_BITS               4
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_SHIFT              8

/* BRPHY3_DSP_TAP :: TAP33_C2 :: EEE_RX_ON_TUNE [07:04] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0xf0,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0xf0,4)
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_MASK                0x00f0
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_ALIGN               0
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_BITS                4
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_SHIFT               4

/* BRPHY3_DSP_TAP :: TAP33_C2 :: EEE_SLAVE_WAIT_TUNE [03:00] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C2,0xf,0)
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_MASK           0x000f
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_ALIGN          0
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_BITS           4
#define BRPHY3_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_SHIFT          0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP33_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP33_C3 :: spare_reg [15:02] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C3_spare_reg(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C3,0xfffc,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C3_spare_reg(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C3,0xfffc,2)
#define BRPHY3_DSP_TAP_TAP33_C3_SPARE_REG_MASK                     0xfffc
#define BRPHY3_DSP_TAP_TAP33_C3_SPARE_REG_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP33_C3_SPARE_REG_BITS                     14
#define BRPHY3_DSP_TAP_TAP33_C3_SPARE_REG_SHIFT                    2

/* BRPHY3_DSP_TAP :: TAP33_C3 :: PWRDNTX_STAGGER_EN [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C3,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C3,0x2,1)
#define BRPHY3_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_MASK            0x0002
#define BRPHY3_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_ALIGN           0
#define BRPHY3_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_BITS            1
#define BRPHY3_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_SHIFT           1

/* BRPHY3_DSP_TAP :: TAP33_C3 :: PWRDNRX_STAGGER_EN [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP33_C3,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP33_C3,0x1,0)
#define BRPHY3_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_MASK            0x0001
#define BRPHY3_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_ALIGN           0
#define BRPHY3_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_BITS            1
#define BRPHY3_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_SHIFT           0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP34_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP34_C0 :: EEE_PLLILPFRZ [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x8000,15)
#define BRPHY3_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_MASK                 0x8000
#define BRPHY3_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_ALIGN                0
#define BRPHY3_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_BITS                 1
#define BRPHY3_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_SHIFT                15

/* BRPHY3_DSP_TAP :: TAP34_C0 :: PLLILPFRZ_OV [14:14] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x4000,14)
#define BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_MASK                  0x4000
#define BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_BITS                  1
#define BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_SHIFT                 14

/* BRPHY3_DSP_TAP :: TAP34_C0 :: PLLILPFRZ [13:13] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x2000,13)
#define BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_MASK                     0x2000
#define BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_BITS                     1
#define BRPHY3_DSP_TAP_TAP34_C0_PLLILPFRZ_SHIFT                    13

/* BRPHY3_DSP_TAP :: TAP34_C0 :: EEE_100TX_UP16_SEL [12:12] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x1000,12)
#define BRPHY3_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_MASK            0x1000
#define BRPHY3_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_ALIGN           0
#define BRPHY3_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_BITS            1
#define BRPHY3_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_SHIFT           12

/* BRPHY3_DSP_TAP :: TAP34_C0 :: PLLFRST_SCALE [11:10] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0xc00,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0xc00,10)
#define BRPHY3_DSP_TAP_TAP34_C0_PLLFRST_SCALE_MASK                 0x0c00
#define BRPHY3_DSP_TAP_TAP34_C0_PLLFRST_SCALE_ALIGN                0
#define BRPHY3_DSP_TAP_TAP34_C0_PLLFRST_SCALE_BITS                 2
#define BRPHY3_DSP_TAP_TAP34_C0_PLLFRST_SCALE_SHIFT                10

/* BRPHY3_DSP_TAP :: TAP34_C0 :: INT_LP_GAIN [09:08] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x300,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x300,8)
#define BRPHY3_DSP_TAP_TAP34_C0_INT_LP_GAIN_MASK                   0x0300
#define BRPHY3_DSP_TAP_TAP34_C0_INT_LP_GAIN_ALIGN                  0
#define BRPHY3_DSP_TAP_TAP34_C0_INT_LP_GAIN_BITS                   2
#define BRPHY3_DSP_TAP_TAP34_C0_INT_LP_GAIN_SHIFT                  8

/* BRPHY3_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_EST_AVERAGE_SEL [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x80,7)
#define BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_MASK    0x0080
#define BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_ALIGN   0
#define BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_BITS    1
#define BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_SHIFT   7

/* BRPHY3_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_SCALE [06:04] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x70,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x70,4)
#define BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_MASK              0x0070
#define BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_ALIGN             0
#define BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_BITS              3
#define BRPHY3_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_SHIFT             4

/* BRPHY3_DSP_TAP :: TAP34_C0 :: KI [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_KI(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_KI(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x8,3)
#define BRPHY3_DSP_TAP_TAP34_C0_KI_MASK                            0x0008
#define BRPHY3_DSP_TAP_TAP34_C0_KI_ALIGN                           0
#define BRPHY3_DSP_TAP_TAP34_C0_KI_BITS                            1
#define BRPHY3_DSP_TAP_TAP34_C0_KI_SHIFT                           3

/* BRPHY3_DSP_TAP :: TAP34_C0 :: KP [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_KP(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_KP(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x4,2)
#define BRPHY3_DSP_TAP_TAP34_C0_KP_MASK                            0x0004
#define BRPHY3_DSP_TAP_TAP34_C0_KP_ALIGN                           0
#define BRPHY3_DSP_TAP_TAP34_C0_KP_BITS                            1
#define BRPHY3_DSP_TAP_TAP34_C0_KP_SHIFT                           2

/* BRPHY3_DSP_TAP :: TAP34_C0 :: KV [01:00] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C0_KV(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x3,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C0_KV(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C0,0x3,0)
#define BRPHY3_DSP_TAP_TAP34_C0_KV_MASK                            0x0003
#define BRPHY3_DSP_TAP_TAP34_C0_KV_ALIGN                           0
#define BRPHY3_DSP_TAP_TAP34_C0_KV_BITS                            2
#define BRPHY3_DSP_TAP_TAP34_C0_KV_SHIFT                           0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP34_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP34_C1 :: SPARE [15:12] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C1_SPARE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C1,0xf000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C1_SPARE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C1,0xf000,12)
#define BRPHY3_DSP_TAP_TAP34_C1_SPARE_MASK                         0xf000
#define BRPHY3_DSP_TAP_TAP34_C1_SPARE_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP34_C1_SPARE_BITS                         4
#define BRPHY3_DSP_TAP_TAP34_C1_SPARE_SHIFT                        12

/* BRPHY3_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_10 [11:08] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C1,0xf00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C1,0xf00,8)
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_MASK             0x0f00
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_ALIGN            0
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_BITS             4
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_SHIFT            8

/* BRPHY3_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_01 [07:04] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C1,0xf0,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C1,0xf0,4)
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_MASK             0x00f0
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_ALIGN            0
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_BITS             4
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_SHIFT            4

/* BRPHY3_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_00 [03:00] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C1,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C1,0xf,0)
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_MASK             0x000f
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_ALIGN            0
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_BITS             4
#define BRPHY3_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_SHIFT            0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP34_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_CH_SEL [15:14] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0xc000,14,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0xc000,14)
#define BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_MASK           0xc000
#define BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_ALIGN          0
#define BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_BITS           2
#define BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_SHIFT          14

/* BRPHY3_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_BUS_SEL [13:11] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0x3800,11,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0x3800,11)
#define BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_MASK          0x3800
#define BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_ALIGN         0
#define BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_BITS          3
#define BRPHY3_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_SHIFT         11

/* BRPHY3_DSP_TAP :: TAP34_C2 :: reserved0 [10:09] */
#define BRPHY3_DSP_TAP_TAP34_C2_RESERVED0_MASK                     0x0600
#define BRPHY3_DSP_TAP_TAP34_C2_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP34_C2_RESERVED0_BITS                     2
#define BRPHY3_DSP_TAP_TAP34_C2_RESERVED0_SHIFT                    9

/* BRPHY3_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_10 [08:06] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0x1c0,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0x1c0,6)
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_MASK               0x01c0
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_ALIGN              0
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_BITS               3
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_SHIFT              6

/* BRPHY3_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_01 [05:03] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0x38,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0x38,3)
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_MASK               0x0038
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_ALIGN              0
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_BITS               3
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_SHIFT              3

/* BRPHY3_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_00 [02:00] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0x7,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP34_C2,0x7,0)
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_MASK               0x0007
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_ALIGN              0
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_BITS               3
#define BRPHY3_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_SHIFT              0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP34_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP34_C3 :: PHASECTL_TPO [15:00] */
#define Wr_BRPHY3_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) WriteReg16(BRPHY3_DSP_TAP_TAP34_C3,x)
#define Rd_BRPHY3_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) ReadReg16(BRPHY3_DSP_TAP_TAP34_C3)
#define BRPHY3_DSP_TAP_TAP34_C3_PHASECTL_TPO_MASK                  0xffff
#define BRPHY3_DSP_TAP_TAP34_C3_PHASECTL_TPO_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP34_C3_PHASECTL_TPO_BITS                  16
#define BRPHY3_DSP_TAP_TAP34_C3_PHASECTL_TPO_SHIFT                 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP35_C0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP35_C0 :: LPI_RX_TW3_TIMER [15:13] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0xe000,13,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0xe000,13)
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_MASK              0xe000
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_ALIGN             0
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_BITS              3
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_SHIFT             13

/* BRPHY3_DSP_TAP :: TAP35_C0 :: LPI_RX_TW2_TIMER [12:10] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0x1c00,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0x1c00,10)
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_MASK              0x1c00
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_ALIGN             0
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_BITS              3
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_SHIFT             10

/* BRPHY3_DSP_TAP :: TAP35_C0 :: LPI_RX_TW1_TIMER [09:07] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0x380,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0x380,7)
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_MASK              0x0380
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_ALIGN             0
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_BITS              3
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_SHIFT             7

/* BRPHY3_DSP_TAP :: TAP35_C0 :: LPI_TX_TQ_TIMER [06:04] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0x70,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0x70,4)
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_MASK               0x0070
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_ALIGN              0
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_BITS               3
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_SHIFT              4

/* BRPHY3_DSP_TAP :: TAP35_C0 :: LPI_TX_TS_TIMER [03:02] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0xc,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0xc,2)
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_MASK               0x000c
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_ALIGN              0
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_BITS               2
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_SHIFT              2

/* BRPHY3_DSP_TAP :: TAP35_C0 :: LPI_TX_TR_TIMER [01:00] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0x3,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C0,0x3,0)
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_MASK               0x0003
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_ALIGN              0
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_BITS               2
#define BRPHY3_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_SHIFT              0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP35_C1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP35_C1 :: LPI_RX_TS3_TIMER [15:10] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C1,0xfc00,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C1,0xfc00,10)
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_MASK              0xfc00
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_ALIGN             0
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_BITS              6
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_SHIFT             10

/* BRPHY3_DSP_TAP :: TAP35_C1 :: LPI_RX_TS2_TIMER [09:04] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C1,0x3f0,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C1,0x3f0,4)
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_MASK              0x03f0
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_ALIGN             0
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_BITS              6
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_SHIFT             4

/* BRPHY3_DSP_TAP :: TAP35_C1 :: LPI_RX_TS1_TIMER [03:00] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C1,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C1,0xf,0)
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_MASK              0x000f
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_ALIGN             0
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_BITS              4
#define BRPHY3_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_SHIFT             0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP35_C2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP35_C2 :: reserved0 [15:14] */
#define BRPHY3_DSP_TAP_TAP35_C2_RESERVED0_MASK                     0xc000
#define BRPHY3_DSP_TAP_TAP35_C2_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP35_C2_RESERVED0_BITS                     2
#define BRPHY3_DSP_TAP_TAP35_C2_RESERVED0_SHIFT                    14

/* BRPHY3_DSP_TAP :: TAP35_C2 :: SPARE [13:10] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C2_SPARE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x3c00,10,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C2_SPARE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x3c00,10)
#define BRPHY3_DSP_TAP_TAP35_C2_SPARE_MASK                         0x3c00
#define BRPHY3_DSP_TAP_TAP35_C2_SPARE_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP35_C2_SPARE_BITS                         4
#define BRPHY3_DSP_TAP_TAP35_C2_SPARE_SHIFT                        10

/* BRPHY3_DSP_TAP :: TAP35_C2 :: LPI_TX_BRCM_MODE [09:09] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x200,9)
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_MASK              0x0200
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_ALIGN             0
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_BITS              1
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_SHIFT             9

/* BRPHY3_DSP_TAP :: TAP35_C2 :: LPI_RX_TI_TIMER [08:08] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x100,8)
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_MASK               0x0100
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_ALIGN              0
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_BITS               1
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_SHIFT              8

/* BRPHY3_DSP_TAP :: TAP35_C2 :: GPCS_ERRTH_SEL [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x80,7)
#define BRPHY3_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_MASK                0x0080
#define BRPHY3_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_ALIGN               0
#define BRPHY3_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_BITS                1
#define BRPHY3_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_SHIFT               7

/* BRPHY3_DSP_TAP :: TAP35_C2 :: PCS_LPI_TEST_CTL [06:04] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x70,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x70,4)
#define BRPHY3_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_MASK              0x0070
#define BRPHY3_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_ALIGN             0
#define BRPHY3_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_BITS              3
#define BRPHY3_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_SHIFT             4

/* BRPHY3_DSP_TAP :: TAP35_C2 :: reserved1 [03:03] */
#define BRPHY3_DSP_TAP_TAP35_C2_RESERVED1_MASK                     0x0008
#define BRPHY3_DSP_TAP_TAP35_C2_RESERVED1_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP35_C2_RESERVED1_BITS                     1
#define BRPHY3_DSP_TAP_TAP35_C2_RESERVED1_SHIFT                    3

/* BRPHY3_DSP_TAP :: TAP35_C2 :: LPI_RX_SQCNTR [02:00] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x7,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C2,0x7,0)
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_MASK                 0x0007
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_ALIGN                0
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_BITS                 3
#define BRPHY3_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: TAP35_C3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: TAP35_C3 :: UNASSIGNED [15:15] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_UNASSIGNED(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_UNASSIGNED(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x8000,15)
#define BRPHY3_DSP_TAP_TAP35_C3_UNASSIGNED_MASK                    0x8000
#define BRPHY3_DSP_TAP_TAP35_C3_UNASSIGNED_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP35_C3_UNASSIGNED_BITS                    1
#define BRPHY3_DSP_TAP_TAP35_C3_UNASSIGNED_SHIFT                   15

/* BRPHY3_DSP_TAP :: TAP35_C3 :: LPI_100TX_STATE [14:12] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x7000,12,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x7000,12)
#define BRPHY3_DSP_TAP_TAP35_C3_LPI_100TX_STATE_MASK               0x7000
#define BRPHY3_DSP_TAP_TAP35_C3_LPI_100TX_STATE_ALIGN              0
#define BRPHY3_DSP_TAP_TAP35_C3_LPI_100TX_STATE_BITS               3
#define BRPHY3_DSP_TAP_TAP35_C3_LPI_100TX_STATE_SHIFT              12

/* BRPHY3_DSP_TAP :: TAP35_C3 :: RXSM_STATE [11:08] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_RXSM_STATE(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0xf00,8,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_RXSM_STATE(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0xf00,8)
#define BRPHY3_DSP_TAP_TAP35_C3_RXSM_STATE_MASK                    0x0f00
#define BRPHY3_DSP_TAP_TAP35_C3_RXSM_STATE_ALIGN                   0
#define BRPHY3_DSP_TAP_TAP35_C3_RXSM_STATE_BITS                    4
#define BRPHY3_DSP_TAP_TAP35_C3_RXSM_STATE_SHIFT                   8

/* BRPHY3_DSP_TAP :: TAP35_C3 :: SEED_INV_CTL [07:07] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x80,7)
#define BRPHY3_DSP_TAP_TAP35_C3_SEED_INV_CTL_MASK                  0x0080
#define BRPHY3_DSP_TAP_TAP35_C3_SEED_INV_CTL_ALIGN                 0
#define BRPHY3_DSP_TAP_TAP35_C3_SEED_INV_CTL_BITS                  1
#define BRPHY3_DSP_TAP_TAP35_C3_SEED_INV_CTL_SHIFT                 7

/* BRPHY3_DSP_TAP :: TAP35_C3 :: LOAD_N [06:06] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_LOAD_N(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_LOAD_N(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x40,6)
#define BRPHY3_DSP_TAP_TAP35_C3_LOAD_N_MASK                        0x0040
#define BRPHY3_DSP_TAP_TAP35_C3_LOAD_N_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP35_C3_LOAD_N_BITS                        1
#define BRPHY3_DSP_TAP_TAP35_C3_LOAD_N_SHIFT                       6

/* BRPHY3_DSP_TAP :: TAP35_C3 :: DET_IDLES [05:05] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_DET_IDLES(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_DET_IDLES(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x20,5)
#define BRPHY3_DSP_TAP_TAP35_C3_DET_IDLES_MASK                     0x0020
#define BRPHY3_DSP_TAP_TAP35_C3_DET_IDLES_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP35_C3_DET_IDLES_BITS                     1
#define BRPHY3_DSP_TAP_TAP35_C3_DET_IDLES_SHIFT                    5

/* BRPHY3_DSP_TAP :: TAP35_C3 :: DET_SLEEP [04:04] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_DET_SLEEP(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_DET_SLEEP(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x10,4)
#define BRPHY3_DSP_TAP_TAP35_C3_DET_SLEEP_MASK                     0x0010
#define BRPHY3_DSP_TAP_TAP35_C3_DET_SLEEP_ALIGN                    0
#define BRPHY3_DSP_TAP_TAP35_C3_DET_SLEEP_BITS                     1
#define BRPHY3_DSP_TAP_TAP35_C3_DET_SLEEP_SHIFT                    4

/* BRPHY3_DSP_TAP :: TAP35_C3 :: FUBAR [03:03] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_FUBAR(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_FUBAR(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x8,3)
#define BRPHY3_DSP_TAP_TAP35_C3_FUBAR_MASK                         0x0008
#define BRPHY3_DSP_TAP_TAP35_C3_FUBAR_ALIGN                        0
#define BRPHY3_DSP_TAP_TAP35_C3_FUBAR_BITS                         1
#define BRPHY3_DSP_TAP_TAP35_C3_FUBAR_SHIFT                        3

/* BRPHY3_DSP_TAP :: TAP35_C3 :: SR_NRZI [02:02] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_SR_NRZI(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_SR_NRZI(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x4,2)
#define BRPHY3_DSP_TAP_TAP35_C3_SR_NRZI_MASK                       0x0004
#define BRPHY3_DSP_TAP_TAP35_C3_SR_NRZI_ALIGN                      0
#define BRPHY3_DSP_TAP_TAP35_C3_SR_NRZI_BITS                       1
#define BRPHY3_DSP_TAP_TAP35_C3_SR_NRZI_SHIFT                      2

/* BRPHY3_DSP_TAP :: TAP35_C3 :: R_USCR [01:01] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_R_USCR(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_R_USCR(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x2,1)
#define BRPHY3_DSP_TAP_TAP35_C3_R_USCR_MASK                        0x0002
#define BRPHY3_DSP_TAP_TAP35_C3_R_USCR_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP35_C3_R_USCR_BITS                        1
#define BRPHY3_DSP_TAP_TAP35_C3_R_USCR_SHIFT                       1

/* BRPHY3_DSP_TAP :: TAP35_C3 :: LOCKED [00:00] */
#define Wr_BRPHY3_DSP_TAP_TAP35_C3_LOCKED(x) WriteRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_TAP35_C3_LOCKED(x) ReadRegBits16(BRPHY3_DSP_TAP_TAP35_C3,0x1,0)
#define BRPHY3_DSP_TAP_TAP35_C3_LOCKED_MASK                        0x0001
#define BRPHY3_DSP_TAP_TAP35_C3_LOCKED_ALIGN                       0
#define BRPHY3_DSP_TAP_TAP35_C3_LOCKED_BITS                        1
#define BRPHY3_DSP_TAP_TAP35_C3_LOCKED_SHIFT                       0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_CTL_CH0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x8000,15)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_MASK              0x8000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_SHIFT             15

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: DC_FREEZE [14:14] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x4000,14)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_MASK               0x4000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_ALIGN              0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_BITS               1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_SHIFT              14

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x2000,13)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_MASK             0x2000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_SHIFT            13

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x1000,12)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_MASK            0x1000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_SHIFT           12

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x800,11)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_MASK            0x0800
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_SHIFT           11

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x400,10)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_MASK            0x0400
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_SHIFT           10

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x200,9)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_MASK            0x0200
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_SHIFT           9

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x100,8)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_MASK              0x0100
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_SHIFT             8

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x80,7)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_MASK             0x0080
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_SHIFT            7

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: DC_DISABLE [06:06] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x40,6)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_MASK              0x0040
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_SHIFT             6

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x20,5)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_MASK            0x0020
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_SHIFT           5

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x10,4)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_MASK           0x0010
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_SHIFT          4

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x8,3)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_MASK           0x0008
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_SHIFT          3

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x4,2)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_MASK           0x0004
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_SHIFT          2

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x2,1)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_MASK           0x0002
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_SHIFT          1

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH0 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH0,0x1,0)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_MASK             0x0001
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_CTL_CH1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x8000,15)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_MASK              0x8000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_SHIFT             15

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: DC_FREEZE [14:14] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x4000,14)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_MASK               0x4000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_ALIGN              0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_BITS               1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_SHIFT              14

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x2000,13)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_MASK             0x2000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_SHIFT            13

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x1000,12)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_MASK            0x1000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_SHIFT           12

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x800,11)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_MASK            0x0800
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_SHIFT           11

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x400,10)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_MASK            0x0400
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_SHIFT           10

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x200,9)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_MASK            0x0200
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_SHIFT           9

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x100,8)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_MASK              0x0100
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_SHIFT             8

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x80,7)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_MASK             0x0080
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_SHIFT            7

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: DC_DISABLE [06:06] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x40,6)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_MASK              0x0040
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_SHIFT             6

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x20,5)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_MASK            0x0020
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_SHIFT           5

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x10,4)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_MASK           0x0010
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_SHIFT          4

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x8,3)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_MASK           0x0008
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_SHIFT          3

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x4,2)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_MASK           0x0004
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_SHIFT          2

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x2,1)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_MASK           0x0002
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_SHIFT          1

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH1 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH1,0x1,0)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_MASK             0x0001
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_CTL_CH2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x8000,15)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_MASK              0x8000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_SHIFT             15

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: DC_FREEZE [14:14] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x4000,14)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_MASK               0x4000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_ALIGN              0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_BITS               1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_SHIFT              14

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x2000,13)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_MASK             0x2000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_SHIFT            13

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x1000,12)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_MASK            0x1000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_SHIFT           12

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x800,11)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_MASK            0x0800
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_SHIFT           11

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x400,10)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_MASK            0x0400
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_SHIFT           10

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x200,9)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_MASK            0x0200
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_SHIFT           9

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x100,8)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_MASK              0x0100
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_SHIFT             8

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x80,7)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_MASK             0x0080
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_SHIFT            7

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: DC_DISABLE [06:06] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x40,6)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_MASK              0x0040
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_SHIFT             6

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x20,5)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_MASK            0x0020
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_SHIFT           5

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x10,4)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_MASK           0x0010
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_SHIFT          4

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x8,3)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_MASK           0x0008
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_SHIFT          3

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x4,2)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_MASK           0x0004
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_SHIFT          2

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x2,1)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_MASK           0x0002
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_SHIFT          1

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH2 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH2,0x1,0)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_MASK             0x0001
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_CTL_CH3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x8000,15)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_MASK              0x8000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_SHIFT             15

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: DC_FREEZE [14:14] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x4000,14)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_MASK               0x4000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_ALIGN              0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_BITS               1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_SHIFT              14

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x2000,13)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_MASK             0x2000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_SHIFT            13

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x1000,12)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_MASK            0x1000
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_SHIFT           12

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x800,11)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_MASK            0x0800
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_SHIFT           11

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x400,10)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_MASK            0x0400
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_SHIFT           10

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x200,9)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_MASK            0x0200
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_SHIFT           9

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x100,8)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_MASK              0x0100
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_SHIFT             8

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x80,7)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_MASK             0x0080
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_SHIFT            7

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: DC_DISABLE [06:06] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x40,6)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_MASK              0x0040
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_SHIFT             6

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x20,5)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_MASK            0x0020
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_SHIFT           5

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x10,4)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_MASK           0x0010
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_SHIFT          4

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x8,3)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_MASK           0x0008
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_SHIFT          3

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x4,2)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_MASK           0x0004
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_SHIFT          2

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x2,1)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_MASK           0x0002
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_ALIGN          0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_BITS           1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_SHIFT          1

/* BRPHY3_DSP_TAP :: FILTER_CTL_CH3 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_CH3,0x1,0)
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_MASK             0x0001
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_ALIGN            0
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_BITS             1
#define BRPHY3_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_MASK          0xff00
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_ALIGN         0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_BITS          8
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_SHIFT         8

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_MASK          0xff00
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_ALIGN         0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_BITS          8
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_SHIFT         8

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_MASK          0xff00
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_ALIGN         0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_BITS          8
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_SHIFT         8

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: reserved0 [15:08] */
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_MASK          0xff00
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_ALIGN         0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_BITS          8
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_SHIFT         8

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY3_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0)
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY3_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: reserved0 [15:15] */
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_MASK             0x8000
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_ALIGN            0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_BITS             1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_SHIFT            15

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT01_PRE1_DIS [14:14] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_MASK  0x4000
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_ALIGN 0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_BITS  1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_SHIFT 14

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: PHYC_SKIP_PHASE_ADJ [13:13] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_MASK   0x2000
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_ALIGN  0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_BITS   1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_SHIFT  13

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: LOCAL_TRAIN_DIS [12:12] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_MASK       0x1000
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_ALIGN      0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_BITS       1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_SHIFT      12

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: SLAVE_FDX_LOCAL_TRAIN_EN [11:11] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x800,11)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_MASK 0x0800
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_ALIGN 0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_BITS 1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_SHIFT 11

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: AUTO_LPF_EN [10:10] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x400,10)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_MASK           0x0400
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_ALIGN          0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_BITS           1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_SHIFT          10

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_PROTECT_EN [09:09] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x200,9)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_MASK        0x0200
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_ALIGN       0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_BITS        1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_SHIFT       9

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT1_DIS [08:08] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x100,8)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_MASK        0x0100
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_ALIGN       0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_BITS        1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_SHIFT       8

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_IDLEDATA_UPD_EN [07:04] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_MASK  0x00f0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_ALIGN 0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_BITS  4
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_SHIFT 4

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_EMI_UPD_EN [03:03] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x8,3)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_MASK       0x0008
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_ALIGN      0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_BITS       1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_SHIFT      3

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_VAL [02:02] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x4,2)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_MASK       0x0004
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_ALIGN      0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_BITS       1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_SHIFT      2

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_OV [01:01] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x2,1)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_MASK        0x0002
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_ALIGN       0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_BITS        1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_SHIFT       1

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_DATAPATH_EN [00:00] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL,0x1,0)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_MASK       0x0001
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_ALIGN      0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_BITS       1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_SHIFT      0


/****************************************************************************
 * BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL2
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL2 :: LPFREQ_SEL_STATUS [15:15] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_MASK    0x8000
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_ALIGN   0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_BITS    1
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_SHIFT   15

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL2 :: reserved0 [14:04] */
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_MASK            0x7ff0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_ALIGN           0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_BITS            11
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_SHIFT           4

/* BRPHY3_DSP_TAP :: EMI_DATAPATH_CTL2 :: GAMMA_LPF_THRESHOLD [03:00] */
#define Wr_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) WriteRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0,x)
#define Rd_BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) ReadRegBits16(BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0)
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_MASK  0x000f
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_ALIGN 0
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_BITS  4
#define BRPHY3_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_SHIFT 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FFEX_CTL
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FFEX_CTL :: reserved0 [15:12] */
#define BRPHY3_DSP_TAP_FFEX_CTL_RESERVED0_MASK                     0xf000
#define BRPHY3_DSP_TAP_FFEX_CTL_RESERVED0_ALIGN                    0
#define BRPHY3_DSP_TAP_FFEX_CTL_RESERVED0_BITS                     4
#define BRPHY3_DSP_TAP_FFEX_CTL_RESERVED0_SHIFT                    12

/* BRPHY3_DSP_TAP :: FFEX_CTL :: ENC_SLOW_LMS_CTL [11:10] */
#define Wr_BRPHY3_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) WriteRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0xc00,10,x)
#define Rd_BRPHY3_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) ReadRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0xc00,10)
#define BRPHY3_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_MASK              0x0c00
#define BRPHY3_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_ALIGN             0
#define BRPHY3_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_BITS              2
#define BRPHY3_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_SHIFT             10

/* BRPHY3_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV_VAL [09:09] */
#define Wr_BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x200,9)
#define BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_MASK               0x0200
#define BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_ALIGN              0
#define BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_BITS               1
#define BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_SHIFT              9

/* BRPHY3_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV [08:08] */
#define Wr_BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x100,8)
#define BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_MASK                   0x0100
#define BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_ALIGN                  0
#define BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_BITS                   1
#define BRPHY3_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_SHIFT                  8

/* BRPHY3_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_VAL [07:07] */
#define Wr_BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) WriteRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) ReadRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x80,7)
#define BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_MASK          0x0080
#define BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_ALIGN         0
#define BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_BITS          1
#define BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_SHIFT         7

/* BRPHY3_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_OV [06:06] */
#define Wr_BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) WriteRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) ReadRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x40,6)
#define BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_MASK           0x0040
#define BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_ALIGN          0
#define BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_BITS           1
#define BRPHY3_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_SHIFT          6

/* BRPHY3_DSP_TAP :: FFEX_CTL :: FFEX_MAINTAP [05:03] */
#define Wr_BRPHY3_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) WriteRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x38,3,x)
#define Rd_BRPHY3_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) ReadRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x38,3)
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_MASK                  0x0038
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_ALIGN                 0
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_BITS                  3
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_SHIFT                 3

/* BRPHY3_DSP_TAP :: FFEX_CTL :: FFEX_LMS_MODE [02:01] */
#define Wr_BRPHY3_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) WriteRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x6,1,x)
#define Rd_BRPHY3_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) ReadRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x6,1)
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_MASK                 0x0006
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_ALIGN                0
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_BITS                 2
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_SHIFT                1

/* BRPHY3_DSP_TAP :: FFEX_CTL :: FFEX_EN [00:00] */
#define Wr_BRPHY3_DSP_TAP_FFEX_CTL_FFEX_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_FFEX_CTL_FFEX_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_FFEX_CTL,0x1,0)
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_EN_MASK                       0x0001
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_EN_ALIGN                      0
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_EN_BITS                       1
#define BRPHY3_DSP_TAP_FFEX_CTL_FFEX_EN_SHIFT                      0


/****************************************************************************
 * BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL0
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_STOP [15:15] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_MASK 0x8000
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_BITS 1
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_SHIFT 15

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: reserved0 [14:07] */
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_MASK         0x7f80
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_ALIGN        0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_BITS         8
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_SHIFT        7

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_MAINSTATE [06:02] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_MASK 0x007c
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_BITS 5
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_SHIFT 2

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_CLR [01:01] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_MASK 0x0002
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_BITS 1
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_SHIFT 1

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_EN [00:00] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_MASK 0x0001
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_BITS 1
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_SHIFT 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL1
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D_EN [15:15] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_MASK 0x8000
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_BITS 1
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_SHIFT 15

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D [14:12] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_MASK 0x7000
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_BITS 3
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_SHIFT 12

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C_EN [11:11] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_MASK 0x0800
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_BITS 1
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_SHIFT 11

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C [10:08] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_MASK 0x0700
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_BITS 3
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_SHIFT 8

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B_EN [07:07] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_MASK 0x0080
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_BITS 1
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_SHIFT 7

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B [06:04] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_MASK 0x0070
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_BITS 3
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_SHIFT 4

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A_EN [03:03] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_MASK 0x0008
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_BITS 1
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_SHIFT 3

/* BRPHY3_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A [02:00] */
#define Wr_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) WriteRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0,x)
#define Rd_BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) ReadRegBits16(BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0)
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_MASK 0x0007
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_ALIGN 0
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_BITS 3
#define BRPHY3_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_SHIFT 0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_ADDR
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_ADDR :: CTL_ALL_CH [15:15] */
#define Wr_BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0x8000,15,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0x8000,15)
#define BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_MASK                 0x8000
#define BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_ALIGN                0
#define BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_BITS                 1
#define BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_SHIFT                15

/* BRPHY3_DSP_TAP :: FILTER_ADDR :: CH_SEL [14:13] */
#define Wr_BRPHY3_DSP_TAP_FILTER_ADDR_CH_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0x6000,13,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_ADDR_CH_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0x6000,13)
#define BRPHY3_DSP_TAP_FILTER_ADDR_CH_SEL_MASK                     0x6000
#define BRPHY3_DSP_TAP_FILTER_ADDR_CH_SEL_ALIGN                    0
#define BRPHY3_DSP_TAP_FILTER_ADDR_CH_SEL_BITS                     2
#define BRPHY3_DSP_TAP_FILTER_ADDR_CH_SEL_SHIFT                    13

/* BRPHY3_DSP_TAP :: FILTER_ADDR :: CTL_ALL_FILTERS [12:12] */
#define Wr_BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0x1000,12)
#define BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_MASK            0x1000
#define BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_BITS            1
#define BRPHY3_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_SHIFT           12

/* BRPHY3_DSP_TAP :: FILTER_ADDR :: FILTER_SEL [11:08] */
#define Wr_BRPHY3_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0xf00,8,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0xf00,8)
#define BRPHY3_DSP_TAP_FILTER_ADDR_FILTER_SEL_MASK                 0x0f00
#define BRPHY3_DSP_TAP_FILTER_ADDR_FILTER_SEL_ALIGN                0
#define BRPHY3_DSP_TAP_FILTER_ADDR_FILTER_SEL_BITS                 4
#define BRPHY3_DSP_TAP_FILTER_ADDR_FILTER_SEL_SHIFT                8

/* BRPHY3_DSP_TAP :: FILTER_ADDR :: TAP_NUMBER [07:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0xff,0,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_ADDR,0xff,0)
#define BRPHY3_DSP_TAP_FILTER_ADDR_TAP_NUMBER_MASK                 0x00ff
#define BRPHY3_DSP_TAP_FILTER_ADDR_TAP_NUMBER_ALIGN                0
#define BRPHY3_DSP_TAP_FILTER_ADDR_TAP_NUMBER_BITS                 8
#define BRPHY3_DSP_TAP_FILTER_ADDR_TAP_NUMBER_SHIFT                0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_CTL
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_CTL :: reserved0 [15:13] */
#define BRPHY3_DSP_TAP_FILTER_CTL_RESERVED0_MASK                   0xe000
#define BRPHY3_DSP_TAP_FILTER_CTL_RESERVED0_ALIGN                  0
#define BRPHY3_DSP_TAP_FILTER_CTL_RESERVED0_BITS                   3
#define BRPHY3_DSP_TAP_FILTER_CTL_RESERVED0_SHIFT                  13

/* BRPHY3_DSP_TAP :: FILTER_CTL :: BUSY [12:12] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_BUSY(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x1000,12,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_BUSY(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x1000,12)
#define BRPHY3_DSP_TAP_FILTER_CTL_BUSY_MASK                        0x1000
#define BRPHY3_DSP_TAP_FILTER_CTL_BUSY_ALIGN                       0
#define BRPHY3_DSP_TAP_FILTER_CTL_BUSY_BITS                        1
#define BRPHY3_DSP_TAP_FILTER_CTL_BUSY_SHIFT                       12

/* BRPHY3_DSP_TAP :: FILTER_CTL :: TAP_PREFETCH [11:11] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x800,11,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x800,11)
#define BRPHY3_DSP_TAP_FILTER_CTL_TAP_PREFETCH_MASK                0x0800
#define BRPHY3_DSP_TAP_FILTER_CTL_TAP_PREFETCH_ALIGN               0
#define BRPHY3_DSP_TAP_FILTER_CTL_TAP_PREFETCH_BITS                1
#define BRPHY3_DSP_TAP_FILTER_CTL_TAP_PREFETCH_SHIFT               11

/* BRPHY3_DSP_TAP :: FILTER_CTL :: UPPER_WORD_SEL [10:10] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x400,10,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x400,10)
#define BRPHY3_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_MASK              0x0400
#define BRPHY3_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_SHIFT             10

/* BRPHY3_DSP_TAP :: FILTER_CTL :: WR_COEFF [09:09] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_WR_COEFF(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x200,9,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_WR_COEFF(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x200,9)
#define BRPHY3_DSP_TAP_FILTER_CTL_WR_COEFF_MASK                    0x0200
#define BRPHY3_DSP_TAP_FILTER_CTL_WR_COEFF_ALIGN                   0
#define BRPHY3_DSP_TAP_FILTER_CTL_WR_COEFF_BITS                    1
#define BRPHY3_DSP_TAP_FILTER_CTL_WR_COEFF_SHIFT                   9

/* BRPHY3_DSP_TAP :: FILTER_CTL :: WR_ALL_NEXT_COEF [08:08] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x100,8,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x100,8)
#define BRPHY3_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_MASK            0x0100
#define BRPHY3_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_ALIGN           0
#define BRPHY3_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_BITS            1
#define BRPHY3_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_SHIFT           8

/* BRPHY3_DSP_TAP :: FILTER_CTL :: RD_COEFF [07:07] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_RD_COEFF(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x80,7,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_RD_COEFF(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x80,7)
#define BRPHY3_DSP_TAP_FILTER_CTL_RD_COEFF_MASK                    0x0080
#define BRPHY3_DSP_TAP_FILTER_CTL_RD_COEFF_ALIGN                   0
#define BRPHY3_DSP_TAP_FILTER_CTL_RD_COEFF_BITS                    1
#define BRPHY3_DSP_TAP_FILTER_CTL_RD_COEFF_SHIFT                   7

/* BRPHY3_DSP_TAP :: FILTER_CTL :: INIT_RAM [06:06] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_INIT_RAM(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x40,6,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_INIT_RAM(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x40,6)
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_RAM_MASK                    0x0040
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_RAM_ALIGN                   0
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_RAM_BITS                    1
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_RAM_SHIFT                   6

/* BRPHY3_DSP_TAP :: FILTER_CTL :: INIT_ENC [05:05] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_INIT_ENC(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x20,5,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_INIT_ENC(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x20,5)
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_ENC_MASK                    0x0020
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_ENC_ALIGN                   0
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_ENC_BITS                    1
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_ENC_SHIFT                   5

/* BRPHY3_DSP_TAP :: FILTER_CTL :: INIT_DFE [04:04] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_INIT_DFE(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x10,4,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_INIT_DFE(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x10,4)
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_DFE_MASK                    0x0010
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_DFE_ALIGN                   0
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_DFE_BITS                    1
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_DFE_SHIFT                   4

/* BRPHY3_DSP_TAP :: FILTER_CTL :: INIT_FFEXTAP [03:03] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x8,3,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x8,3)
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_MASK                0x0008
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_ALIGN               0
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_BITS                1
#define BRPHY3_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_SHIFT               3

/* BRPHY3_DSP_TAP :: FILTER_CTL :: DISABLE_FILTER [02:02] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x4,2,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x4,2)
#define BRPHY3_DSP_TAP_FILTER_CTL_DISABLE_FILTER_MASK              0x0004
#define BRPHY3_DSP_TAP_FILTER_CTL_DISABLE_FILTER_ALIGN             0
#define BRPHY3_DSP_TAP_FILTER_CTL_DISABLE_FILTER_BITS              1
#define BRPHY3_DSP_TAP_FILTER_CTL_DISABLE_FILTER_SHIFT             2

/* BRPHY3_DSP_TAP :: FILTER_CTL :: FREEZE_FILTER [01:01] */
#define Wr_BRPHY3_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) WriteRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x2,1,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) ReadRegBits16(BRPHY3_DSP_TAP_FILTER_CTL,0x2,1)
#define BRPHY3_DSP_TAP_FILTER_CTL_FREEZE_FILTER_MASK               0x0002
#define BRPHY3_DSP_TAP_FILTER_CTL_FREEZE_FILTER_ALIGN              0
#define BRPHY3_DSP_TAP_FILTER_CTL_FREEZE_FILTER_BITS               1
#define BRPHY3_DSP_TAP_FILTER_CTL_FREEZE_FILTER_SHIFT              1

/* BRPHY3_DSP_TAP :: FILTER_CTL :: reserved1 [00:00] */
#define BRPHY3_DSP_TAP_FILTER_CTL_RESERVED1_MASK                   0x0001
#define BRPHY3_DSP_TAP_FILTER_CTL_RESERVED1_ALIGN                  0
#define BRPHY3_DSP_TAP_FILTER_CTL_RESERVED1_BITS                   1
#define BRPHY3_DSP_TAP_FILTER_CTL_RESERVED1_SHIFT                  0


/****************************************************************************
 * BRPHY3_DSP_TAP :: FILTER_DATA
 ***************************************************************************/
/* BRPHY3_DSP_TAP :: FILTER_DATA :: TAP_COEFF [15:00] */
#define Wr_BRPHY3_DSP_TAP_FILTER_DATA_TAP_COEFF(x) WriteReg16(BRPHY3_DSP_TAP_FILTER_DATA,x)
#define Rd_BRPHY3_DSP_TAP_FILTER_DATA_TAP_COEFF(x) ReadReg16(BRPHY3_DSP_TAP_FILTER_DATA)
#define BRPHY3_DSP_TAP_FILTER_DATA_TAP_COEFF_MASK                  0xffff
#define BRPHY3_DSP_TAP_FILTER_DATA_TAP_COEFF_ALIGN                 0
#define BRPHY3_DSP_TAP_FILTER_DATA_TAP_COEFF_BITS                  16
#define BRPHY3_DSP_TAP_FILTER_DATA_TAP_COEFF_SHIFT                 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_PLL_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLLCTRL_0
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLLCTRL_0 :: PLL_CTL [15:00] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) WriteReg16(BRPHY3_PLL_CTRL_PLLCTRL_0,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) ReadReg16(BRPHY3_PLL_CTRL_PLLCTRL_0)
#define BRPHY3_PLL_CTRL_PLLCTRL_0_PLL_CTL_MASK                     0xffff
#define BRPHY3_PLL_CTRL_PLLCTRL_0_PLL_CTL_ALIGN                    0
#define BRPHY3_PLL_CTRL_PLLCTRL_0_PLL_CTL_BITS                     16
#define BRPHY3_PLL_CTRL_PLLCTRL_0_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLLCTRL_1
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLLCTRL_1 :: PLL_CTL [15:00] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) WriteReg16(BRPHY3_PLL_CTRL_PLLCTRL_1,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) ReadReg16(BRPHY3_PLL_CTRL_PLLCTRL_1)
#define BRPHY3_PLL_CTRL_PLLCTRL_1_PLL_CTL_MASK                     0xffff
#define BRPHY3_PLL_CTRL_PLLCTRL_1_PLL_CTL_ALIGN                    0
#define BRPHY3_PLL_CTRL_PLLCTRL_1_PLL_CTL_BITS                     16
#define BRPHY3_PLL_CTRL_PLLCTRL_1_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLLCTRL_2
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2 [15:14] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_2,0xc000,14,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_2,0xc000,14)
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_MASK                  0xc000
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_ALIGN                 0
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_BITS                  2
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_SHIFT                 14

/* BRPHY3_PLL_CTRL :: PLLCTRL_2 :: PLL_PDIV [13:10] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_2,0x3c00,10,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_2,0x3c00,10)
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_PDIV_MASK                    0x3c00
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_PDIV_ALIGN                   0
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_PDIV_BITS                    4
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_PDIV_SHIFT                   10

/* BRPHY3_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2_2 [09:00] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_2,0x3ff,0,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_2,0x3ff,0)
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_MASK                0x03ff
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_ALIGN               0
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_BITS                10
#define BRPHY3_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_SHIFT               0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLLCTRL_3
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLLCTRL_3 :: PLL_SPARE3 [15:10] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_3,0xfc00,10,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_3,0xfc00,10)
#define BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_MASK                  0xfc00
#define BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_ALIGN                 0
#define BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_BITS                  6
#define BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_SHIFT                 10

/* BRPHY3_PLL_CTRL :: PLLCTRL_3 :: PLL_NDIV_INT_MS [09:00] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_3,0x3ff,0,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_3,0x3ff,0)
#define BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_MASK             0x03ff
#define BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_ALIGN            0
#define BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_BITS             10
#define BRPHY3_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_SHIFT            0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLLCTRL_4
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4 [15:15] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x8000,15,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x8000,15)
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_MASK                  0x8000
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_ALIGN                 0
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_BITS                  1
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_SHIFT                 15

/* BRPHY3_PLL_CTRL :: PLLCTRL_4 :: SD_SEL_300mV [14:14] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x4000,14,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x4000,14)
#define BRPHY3_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_MASK                0x4000
#define BRPHY3_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_ALIGN               0
#define BRPHY3_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_BITS                1
#define BRPHY3_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_SHIFT               14

/* BRPHY3_PLL_CTRL :: PLLCTRL_4 :: CML_BUF_TUNE [13:12] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x3000,12,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x3000,12)
#define BRPHY3_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_MASK                0x3000
#define BRPHY3_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_ALIGN               0
#define BRPHY3_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_BITS                2
#define BRPHY3_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_SHIFT               12

/* BRPHY3_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_BANDGAP [11:09] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0xe00,9,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0xe00,9)
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_MASK            0x0e00
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_ALIGN           0
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_BITS            3
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_SHIFT           9

/* BRPHY3_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4a [08:06] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x1c0,6,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x1c0,6)
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_MASK                 0x01c0
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_ALIGN                0
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_BITS                 3
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_SHIFT                6

/* BRPHY3_PLL_CTRL :: PLLCTRL_4 :: ATEST_OR_BIAS_TEST_OUTPUT [05:05] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x20,5,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x20,5)
#define BRPHY3_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_MASK   0x0020
#define BRPHY3_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_ALIGN  0
#define BRPHY3_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_BITS   1
#define BRPHY3_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_SHIFT  5

/* BRPHY3_PLL_CTRL :: PLLCTRL_4 :: PLL_MUX_ATEST [04:03] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x18,3,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x18,3)
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_MASK               0x0018
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_ALIGN              0
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_BITS               2
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_SHIFT              3

/* BRPHY3_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_TEST_MUX [02:00] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x7,0,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_4,0x7,0)
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_MASK           0x0007
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_ALIGN          0
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_BITS           3
#define BRPHY3_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_SHIFT          0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLLCTRL_5
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLLCTRL_5 :: PLL_SPARE5 [15:14] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0xc000,14,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0xc000,14)
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_MASK                  0xc000
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_ALIGN                 0
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_BITS                  2
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_SHIFT                 14

/* BRPHY3_PLL_CTRL :: PLLCTRL_5 :: PLL_CP [13:13] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x2000,13,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x2000,13)
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP_MASK                      0x2000
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP_ALIGN                     0
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP_BITS                      1
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP_SHIFT                     13

/* BRPHY3_PLL_CTRL :: PLLCTRL_5 :: PLL_CP1 [12:12] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x1000,12,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x1000,12)
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP1_MASK                     0x1000
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP1_ALIGN                    0
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP1_BITS                     1
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CP1_SHIFT                    12

/* BRPHY3_PLL_CTRL :: PLLCTRL_5 :: PLL_CZ [11:11] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x800,11,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x800,11)
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CZ_MASK                      0x0800
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CZ_ALIGN                     0
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CZ_BITS                      1
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_CZ_SHIFT                     11

/* BRPHY3_PLL_CTRL :: PLLCTRL_5 :: PLL_RZ [10:07] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x780,7,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x780,7)
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_RZ_MASK                      0x0780
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_RZ_ALIGN                     0
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_RZ_BITS                      4
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_RZ_SHIFT                     7

/* BRPHY3_PLL_CTRL :: PLLCTRL_5 :: PLL_ICP [06:03] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x78,3,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x78,3)
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_ICP_MASK                     0x0078
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_ICP_ALIGN                    0
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_ICP_BITS                     4
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_ICP_SHIFT                    3

/* BRPHY3_PLL_CTRL :: PLLCTRL_5 :: PLL_VCO_GAIN [02:00] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x7,0,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_5,0x7,0)
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_MASK                0x0007
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_ALIGN               0
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_BITS                3
#define BRPHY3_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_SHIFT               0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLLCTRL_6
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLLCTRL_6 :: PLL_SPARE6 [15:09] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0xfe00,9,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0xfe00,9)
#define BRPHY3_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_MASK                  0xfe00
#define BRPHY3_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_ALIGN                 0
#define BRPHY3_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_BITS                  7
#define BRPHY3_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_SHIFT                 9

/* BRPHY3_PLL_CTRL :: PLLCTRL_6 :: POR_CONFIG [08:07] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0x180,7,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0x180,7)
#define BRPHY3_PLL_CTRL_PLLCTRL_6_POR_CONFIG_MASK                  0x0180
#define BRPHY3_PLL_CTRL_PLLCTRL_6_POR_CONFIG_ALIGN                 0
#define BRPHY3_PLL_CTRL_PLLCTRL_6_POR_CONFIG_BITS                  2
#define BRPHY3_PLL_CTRL_PLLCTRL_6_POR_CONFIG_SHIFT                 7

/* BRPHY3_PLL_CTRL :: PLLCTRL_6 :: CLK500_EN [06:06] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0x40,6,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0x40,6)
#define BRPHY3_PLL_CTRL_PLLCTRL_6_CLK500_EN_MASK                   0x0040
#define BRPHY3_PLL_CTRL_PLLCTRL_6_CLK500_EN_ALIGN                  0
#define BRPHY3_PLL_CTRL_PLLCTRL_6_CLK500_EN_BITS                   1
#define BRPHY3_PLL_CTRL_PLLCTRL_6_CLK500_EN_SHIFT                  6

/* BRPHY3_PLL_CTRL :: PLLCTRL_6 :: RCAL_OFFSET [05:03] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0x38,3,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0x38,3)
#define BRPHY3_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_MASK                 0x0038
#define BRPHY3_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_ALIGN                0
#define BRPHY3_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_BITS                 3
#define BRPHY3_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_SHIFT                3

/* BRPHY3_PLL_CTRL :: PLLCTRL_6 :: RCCAL_OFFSET [02:00] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0x7,0,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_6,0x7,0)
#define BRPHY3_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_MASK                0x0007
#define BRPHY3_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_ALIGN               0
#define BRPHY3_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_BITS                3
#define BRPHY3_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_SHIFT               0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLL_STATUS_0
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLL_STATUS_0 :: reserved0 [15:12] */
#define BRPHY3_PLL_CTRL_PLL_STATUS_0_RESERVED0_MASK                0xf000
#define BRPHY3_PLL_CTRL_PLL_STATUS_0_RESERVED0_ALIGN               0
#define BRPHY3_PLL_CTRL_PLL_STATUS_0_RESERVED0_BITS                4
#define BRPHY3_PLL_CTRL_PLL_STATUS_0_RESERVED0_SHIFT               12

/* BRPHY3_PLL_CTRL :: PLL_STATUS_0 :: PLL_STATUS_WORD [11:00] */
#define Wr_BRPHY3_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLL_STATUS_0,0xfff,0,x)
#define Rd_BRPHY3_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLL_STATUS_0,0xfff,0)
#define BRPHY3_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_MASK          0x0fff
#define BRPHY3_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_ALIGN         0
#define BRPHY3_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_BITS          12
#define BRPHY3_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_SHIFT         0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLL_STATUS_1
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLL_STATUS_1 :: reserved0 [15:09] */
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_RESERVED0_MASK                0xfe00
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_RESERVED0_ALIGN               0
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_RESERVED0_BITS                7
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_RESERVED0_SHIFT               9

/* BRPHY3_PLL_CTRL :: PLL_STATUS_1 :: PLL_LOCK [08:08] */
#define Wr_BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLL_STATUS_1,0x100,8,x)
#define Rd_BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLL_STATUS_1,0x100,8)
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_MASK                 0x0100
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_ALIGN                0
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_BITS                 1
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_SHIFT                8

/* BRPHY3_PLL_CTRL :: PLL_STATUS_1 :: reserved1 [07:04] */
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_RESERVED1_MASK                0x00f0
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_RESERVED1_ALIGN               0
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_RESERVED1_BITS                4
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_RESERVED1_SHIFT               4

/* BRPHY3_PLL_CTRL :: PLL_STATUS_1 :: PLL_BER [03:00] */
#define Wr_BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLL_STATUS_1,0xf,0,x)
#define Rd_BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLL_STATUS_1,0xf,0)
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_BER_MASK                  0x000f
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_BER_ALIGN                 0
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_BER_BITS                  4
#define BRPHY3_PLL_CTRL_PLL_STATUS_1_PLL_BER_SHIFT                 0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: AFE_SIGDET_STATUS
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: AFE_SIGDET_STATUS :: reserved0 [15:07] */
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_MASK           0xff80
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_ALIGN          0
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_BITS           9
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_SHIFT          7

/* BRPHY3_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_SIGSTATE [06:01] */
#define Wr_BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) WriteRegBits16(BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1,x)
#define Rd_BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) ReadRegBits16(BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1)
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_MASK    0x007e
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_ALIGN   0
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_BITS    6
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_SHIFT   1

/* BRPHY3_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_Select [00:00] */
#define Wr_BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) WriteRegBits16(BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0,x)
#define Rd_BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) ReadRegBits16(BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0)
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_MASK      0x0001
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_ALIGN     0
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_BITS      1
#define BRPHY3_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_SHIFT     0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLLCTRL_7
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLLCTRL_7 :: TVCO_MUX_EN [15:15] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x8000,15,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x8000,15)
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_MASK                 0x8000
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_ALIGN                0
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_BITS                 1
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_SHIFT                15

/* BRPHY3_PLL_CTRL :: PLLCTRL_7 :: TVCO_PAD [14:12] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x7000,12,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x7000,12)
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_PAD_MASK                    0x7000
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_PAD_ALIGN                   0
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_PAD_BITS                    3
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TVCO_PAD_SHIFT                   12

/* BRPHY3_PLL_CTRL :: PLLCTRL_7 :: ADJUST_AUX_LDO [11:11] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x800,11,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x800,11)
#define BRPHY3_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_MASK              0x0800
#define BRPHY3_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_ALIGN             0
#define BRPHY3_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_BITS              1
#define BRPHY3_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_SHIFT             11

/* BRPHY3_PLL_CTRL :: PLLCTRL_7 :: CLAMP_REFERENCE [10:09] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x600,9,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x600,9)
#define BRPHY3_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_MASK             0x0600
#define BRPHY3_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_ALIGN            0
#define BRPHY3_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_BITS             2
#define BRPHY3_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_SHIFT            9

/* BRPHY3_PLL_CTRL :: PLLCTRL_7 :: CML_BUFFER_PWRDN [08:08] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x100,8,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0x100,8)
#define BRPHY3_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_MASK            0x0100
#define BRPHY3_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_ALIGN           0
#define BRPHY3_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_BITS            1
#define BRPHY3_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_SHIFT           8

/* BRPHY3_PLL_CTRL :: PLLCTRL_7 :: TXCLK_PWRDN [07:04] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0xf0,4,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0xf0,4)
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_MASK                 0x00f0
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_ALIGN                0
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_BITS                 4
#define BRPHY3_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_SHIFT                4

/* BRPHY3_PLL_CTRL :: PLLCTRL_7 :: RXCLK_PWRDN [03:00] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0xf,0,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_7,0xf,0)
#define BRPHY3_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_MASK                 0x000f
#define BRPHY3_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_ALIGN                0
#define BRPHY3_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_BITS                 4
#define BRPHY3_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_SHIFT                0


/****************************************************************************
 * BRPHY3_PLL_CTRL :: PLLCTRL_8
 ***************************************************************************/
/* BRPHY3_PLL_CTRL :: PLLCTRL_8 :: PLL_SPARE5 [15:01] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_8,0xfffe,1,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_8,0xfffe,1)
#define BRPHY3_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_MASK                  0xfffe
#define BRPHY3_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_ALIGN                 0
#define BRPHY3_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_BITS                  15
#define BRPHY3_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_SHIFT                 1

/* BRPHY3_PLL_CTRL :: PLLCTRL_8 :: PC_CLK_1G_PWRDN [00:00] */
#define Wr_BRPHY3_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) WriteRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_8,0x1,0,x)
#define Rd_BRPHY3_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) ReadRegBits16(BRPHY3_PLL_CTRL_PLLCTRL_8,0x1,0)
#define BRPHY3_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_MASK             0x0001
#define BRPHY3_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_ALIGN            0
#define BRPHY3_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_BITS             1
#define BRPHY3_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_SHIFT            0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_AFE_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_AFE_CTRL :: RXCONFIG_0
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: RXCONFIG_0 :: RXCONFIG_15_0 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) WriteReg16(BRPHY3_AFE_CTRL_RXCONFIG_0,x)
#define Rd_BRPHY3_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) ReadReg16(BRPHY3_AFE_CTRL_RXCONFIG_0)
#define BRPHY3_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_MASK              0xffff
#define BRPHY3_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_ALIGN             0
#define BRPHY3_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_BITS              16
#define BRPHY3_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_SHIFT             0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: RXCONFIG_1
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: RXCONFIG_1 :: RXCONFIG_31_23 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) WriteReg16(BRPHY3_AFE_CTRL_RXCONFIG_1,x)
#define Rd_BRPHY3_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) ReadReg16(BRPHY3_AFE_CTRL_RXCONFIG_1)
#define BRPHY3_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_MASK             0xffff
#define BRPHY3_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_ALIGN            0
#define BRPHY3_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_BITS             16
#define BRPHY3_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_SHIFT            0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: RXCONFIG_2
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: RXCONFIG_2 :: RXCONFIG_47_32 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) WriteReg16(BRPHY3_AFE_CTRL_RXCONFIG_2,x)
#define Rd_BRPHY3_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) ReadReg16(BRPHY3_AFE_CTRL_RXCONFIG_2)
#define BRPHY3_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_MASK             0xffff
#define BRPHY3_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_ALIGN            0
#define BRPHY3_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_BITS             16
#define BRPHY3_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_SHIFT            0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: RXCONFIG_3
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: RXCONFIG_3 :: RXCONFIG_63_48 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) WriteReg16(BRPHY3_AFE_CTRL_RXCONFIG_3,x)
#define Rd_BRPHY3_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) ReadReg16(BRPHY3_AFE_CTRL_RXCONFIG_3)
#define BRPHY3_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_MASK             0xffff
#define BRPHY3_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_ALIGN            0
#define BRPHY3_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_BITS             16
#define BRPHY3_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_SHIFT            0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: RXCONFIG_4
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: RXCONFIG_4 :: RXCONFIG_79_64 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) WriteReg16(BRPHY3_AFE_CTRL_RXCONFIG_4,x)
#define Rd_BRPHY3_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) ReadReg16(BRPHY3_AFE_CTRL_RXCONFIG_4)
#define BRPHY3_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_MASK             0xffff
#define BRPHY3_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_ALIGN            0
#define BRPHY3_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_BITS             16
#define BRPHY3_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_SHIFT            0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: RXCONFIG5_LP
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: RXCONFIG5_LP :: RXCONFIG_86_80 [15:09] */
#define Wr_BRPHY3_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) WriteRegBits16(BRPHY3_AFE_CTRL_RXCONFIG5_LP,0xfe00,9,x)
#define Rd_BRPHY3_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) ReadRegBits16(BRPHY3_AFE_CTRL_RXCONFIG5_LP,0xfe00,9)
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_MASK           0xfe00
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_ALIGN          0
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_BITS           7
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_SHIFT          9

/* BRPHY3_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_0 [08:06] */
#define Wr_BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) WriteRegBits16(BRPHY3_AFE_CTRL_RXCONFIG5_LP,0x1c0,6,x)
#define Rd_BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) ReadRegBits16(BRPHY3_AFE_CTRL_RXCONFIG5_LP,0x1c0,6)
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_MASK                  0x01c0
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_ALIGN                 0
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_BITS                  3
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_SHIFT                 6

/* BRPHY3_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_1 [05:03] */
#define Wr_BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) WriteRegBits16(BRPHY3_AFE_CTRL_RXCONFIG5_LP,0x38,3,x)
#define Rd_BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) ReadRegBits16(BRPHY3_AFE_CTRL_RXCONFIG5_LP,0x38,3)
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_MASK                  0x0038
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_ALIGN                 0
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_BITS                  3
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_SHIFT                 3

/* BRPHY3_AFE_CTRL :: RXCONFIG5_LP :: MODE_force [02:00] */
#define Wr_BRPHY3_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) WriteRegBits16(BRPHY3_AFE_CTRL_RXCONFIG5_LP,0x7,0,x)
#define Rd_BRPHY3_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) ReadRegBits16(BRPHY3_AFE_CTRL_RXCONFIG5_LP,0x7,0)
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_MASK               0x0007
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_ALIGN              0
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_BITS               3
#define BRPHY3_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_SHIFT              0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: TX_CONFIG_0
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: TX_CONFIG_0 :: TX_CONFIG_15_0 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) WriteReg16(BRPHY3_AFE_CTRL_TX_CONFIG_0,x)
#define Rd_BRPHY3_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) ReadReg16(BRPHY3_AFE_CTRL_TX_CONFIG_0)
#define BRPHY3_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_MASK            0xffff
#define BRPHY3_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_ALIGN           0
#define BRPHY3_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_BITS            16
#define BRPHY3_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_SHIFT           0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: TX_CONFIG_1
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: TX_CONFIG_1 :: TX_BW_TUNE [15:11] */
#define Wr_BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) WriteRegBits16(BRPHY3_AFE_CTRL_TX_CONFIG_1,0xf800,11,x)
#define Rd_BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) ReadRegBits16(BRPHY3_AFE_CTRL_TX_CONFIG_1,0xf800,11)
#define BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_MASK                0xf800
#define BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_ALIGN               0
#define BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_BITS                5
#define BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_SHIFT               11

/* BRPHY3_AFE_CTRL :: TX_CONFIG_1 :: TX_CONFIG_26_16 [10:00] */
#define Wr_BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) WriteRegBits16(BRPHY3_AFE_CTRL_TX_CONFIG_1,0x7ff,0,x)
#define Rd_BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) ReadRegBits16(BRPHY3_AFE_CTRL_TX_CONFIG_1,0x7ff,0)
#define BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_MASK           0x07ff
#define BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_ALIGN          0
#define BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_BITS           11
#define BRPHY3_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_SHIFT          0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: VDAC_ICTRL_0
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: VDAC_ICTRL_0 :: VDAC_current_ctrl_15_0 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) WriteReg16(BRPHY3_AFE_CTRL_VDAC_ICTRL_0,x)
#define Rd_BRPHY3_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) ReadReg16(BRPHY3_AFE_CTRL_VDAC_ICTRL_0)
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_MASK   0xffff
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_ALIGN  0
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_BITS   16
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_SHIFT  0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: VDAC_ICTRL_1
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: VDAC_ICTRL_1 :: VDAC_current_ctrl_31_16 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) WriteReg16(BRPHY3_AFE_CTRL_VDAC_ICTRL_1,x)
#define Rd_BRPHY3_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) ReadReg16(BRPHY3_AFE_CTRL_VDAC_ICTRL_1)
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_MASK  0xffff
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_ALIGN 0
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_BITS  16
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_SHIFT 0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: VDAC_ICTRL_2
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: VDAC_ICTRL_2 :: VDAC_current_ctrl_51_36 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) WriteReg16(BRPHY3_AFE_CTRL_VDAC_ICTRL_2,x)
#define Rd_BRPHY3_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) ReadReg16(BRPHY3_AFE_CTRL_VDAC_ICTRL_2)
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_MASK  0xffff
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_ALIGN 0
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_BITS  16
#define BRPHY3_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_SHIFT 0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: VDAC_OTHERS_0
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: VDAC_OTHERS_0 :: current_ctrl_35_32_others [15:00] */
#define Wr_BRPHY3_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) WriteReg16(BRPHY3_AFE_CTRL_VDAC_OTHERS_0,x)
#define Rd_BRPHY3_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) ReadReg16(BRPHY3_AFE_CTRL_VDAC_OTHERS_0)
#define BRPHY3_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_MASK 0xffff
#define BRPHY3_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_ALIGN 0
#define BRPHY3_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_BITS 16
#define BRPHY3_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_SHIFT 0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: HPF_TRIM_OTHERS
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: HPF_TRIM_OTHERS :: Reserved [15:10] */
#define Wr_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) WriteRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10,x)
#define Rd_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) ReadRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10)
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_MASK              0xfc00
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_ALIGN             0
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_BITS              6
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_SHIFT             10

/* BRPHY3_AFE_CTRL :: HPF_TRIM_OTHERS :: RX_SAMPLE_WIDTH [09:07] */
#define Wr_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) WriteRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7,x)
#define Rd_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) ReadRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7)
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_MASK       0x0380
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_ALIGN      0
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_BITS       3
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_SHIFT      7

/* BRPHY3_AFE_CTRL :: HPF_TRIM_OTHERS :: IDAC_fine_tune [06:04] */
#define Wr_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) WriteRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4,x)
#define Rd_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) ReadRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4)
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_MASK        0x0070
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_ALIGN       0
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_BITS        3
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_SHIFT       4

/* BRPHY3_AFE_CTRL :: HPF_TRIM_OTHERS :: SOFT_SEL_TRIM_HPF [03:03] */
#define Wr_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) WriteRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3,x)
#define Rd_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) ReadRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3)
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_MASK     0x0008
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_ALIGN    0
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_BITS     1
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_SHIFT    3

/* BRPHY3_AFE_CTRL :: HPF_TRIM_OTHERS :: TRIM_HPF [02:00] */
#define Wr_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) WriteRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0,x)
#define Rd_BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) ReadRegBits16(BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0)
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_MASK              0x0007
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_ALIGN             0
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_BITS              3
#define BRPHY3_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_SHIFT             0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: TX_EXTRA_CONFIG_0
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: TX_EXTRA_CONFIG_0 :: TX_EXTRA_CONFIG_15_0 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) WriteReg16(BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_0,x)
#define Rd_BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) ReadReg16(BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_0)
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_MASK 0xffff
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_ALIGN 0
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_BITS 16
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_SHIFT 0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: TX_EXTRA_CONFIG_1
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: TX_EXTRA_CONFIG_1 :: TX_EXTRA_CONFIG_31_16 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) WriteReg16(BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_1,x)
#define Rd_BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) ReadReg16(BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_1)
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_MASK 0xffff
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_ALIGN 0
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_BITS 16
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_SHIFT 0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: TX_EXTRA_CONFIG_2
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: TX_EXTRA_CONFIG_2 :: TX_EXTRA_CONFIG_47_32 [15:00] */
#define Wr_BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) WriteReg16(BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_2,x)
#define Rd_BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) ReadReg16(BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_2)
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_MASK 0xffff
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_ALIGN 0
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_BITS 16
#define BRPHY3_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_SHIFT 0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: TEMPSEN_OTHERS
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: TEMPSEN_OTHERS :: TEMPSEN [15:02] */
#define Wr_BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) WriteRegBits16(BRPHY3_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2,x)
#define Rd_BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) ReadRegBits16(BRPHY3_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2)
#define BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_MASK                0xfffc
#define BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_ALIGN               0
#define BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_BITS                14
#define BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_SHIFT               2

/* BRPHY3_AFE_CTRL :: TEMPSEN_OTHERS :: EXTRA_10BT [01:00] */
#define Wr_BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) WriteRegBits16(BRPHY3_AFE_CTRL_TEMPSEN_OTHERS,0x3,0,x)
#define Rd_BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) ReadRegBits16(BRPHY3_AFE_CTRL_TEMPSEN_OTHERS,0x3,0)
#define BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_MASK             0x0003
#define BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_ALIGN            0
#define BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_BITS             2
#define BRPHY3_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_SHIFT            0


/****************************************************************************
 * BRPHY3_AFE_CTRL :: FUTURE_RSV
 ***************************************************************************/
/* BRPHY3_AFE_CTRL :: FUTURE_RSV :: FUTURE_RSV [15:00] */
#define Wr_BRPHY3_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) WriteReg16(BRPHY3_AFE_CTRL_FUTURE_RSV,x)
#define Rd_BRPHY3_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) ReadReg16(BRPHY3_AFE_CTRL_FUTURE_RSV)
#define BRPHY3_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_MASK                 0xffff
#define BRPHY3_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_ALIGN                0
#define BRPHY3_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_BITS                 16
#define BRPHY3_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_ECD_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC0
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC0 :: RUN_IMMEDIATE [15:15] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x8000,15,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x8000,15)
#define BRPHY3_ECD_CTRL_EXPC0_RUN_IMMEDIATE_MASK                   0x8000
#define BRPHY3_ECD_CTRL_EXPC0_RUN_IMMEDIATE_ALIGN                  0
#define BRPHY3_ECD_CTRL_EXPC0_RUN_IMMEDIATE_BITS                   1
#define BRPHY3_ECD_CTRL_EXPC0_RUN_IMMEDIATE_SHIFT                  15

/* BRPHY3_ECD_CTRL :: EXPC0 :: RUN_AT_AUTONEG [14:14] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x4000,14,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x4000,14)
#define BRPHY3_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_MASK                  0x4000
#define BRPHY3_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_ALIGN                 0
#define BRPHY3_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_BITS                  1
#define BRPHY3_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_SHIFT                 14

/* BRPHY3_ECD_CTRL :: EXPC0 :: INTER_PAIR_SHORT_DIS [13:13] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x2000,13,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x2000,13)
#define BRPHY3_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_MASK            0x2000
#define BRPHY3_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_ALIGN           0
#define BRPHY3_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_BITS            1
#define BRPHY3_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_SHIFT           13

/* BRPHY3_ECD_CTRL :: EXPC0 :: BREAK_LINK [12:12] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_BREAK_LINK(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x1000,12,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_BREAK_LINK(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x1000,12)
#define BRPHY3_ECD_CTRL_EXPC0_BREAK_LINK_MASK                      0x1000
#define BRPHY3_ECD_CTRL_EXPC0_BREAK_LINK_ALIGN                     0
#define BRPHY3_ECD_CTRL_EXPC0_BREAK_LINK_BITS                      1
#define BRPHY3_ECD_CTRL_EXPC0_BREAK_LINK_SHIFT                     12

/* BRPHY3_ECD_CTRL :: EXPC0 :: CABLE_DIAG_STATUS [11:11] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x800,11,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x800,11)
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_MASK               0x0800
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_ALIGN              0
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_BITS               1
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_SHIFT              11

/* BRPHY3_ECD_CTRL :: EXPC0 :: CABLE_LEN_UNIT [10:10] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x400,10,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x400,10)
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_MASK                  0x0400
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_ALIGN                 0
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_BITS                  1
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_SHIFT                 10

/* BRPHY3_ECD_CTRL :: EXPC0 :: reserved0 [09:09] */
#define BRPHY3_ECD_CTRL_EXPC0_RESERVED0_MASK                       0x0200
#define BRPHY3_ECD_CTRL_EXPC0_RESERVED0_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPC0_RESERVED0_BITS                       1
#define BRPHY3_ECD_CTRL_EXPC0_RESERVED0_SHIFT                      9

/* BRPHY3_ECD_CTRL :: EXPC0 :: FAST_TIMER_ENABLE [08:08] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x100,8,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x100,8)
#define BRPHY3_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_MASK               0x0100
#define BRPHY3_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_ALIGN              0
#define BRPHY3_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_BITS               1
#define BRPHY3_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_SHIFT              8

/* BRPHY3_ECD_CTRL :: EXPC0 :: INTRPT_ENABLE [07:07] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x80,7,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x80,7)
#define BRPHY3_ECD_CTRL_EXPC0_INTRPT_ENABLE_MASK                   0x0080
#define BRPHY3_ECD_CTRL_EXPC0_INTRPT_ENABLE_ALIGN                  0
#define BRPHY3_ECD_CTRL_EXPC0_INTRPT_ENABLE_BITS                   1
#define BRPHY3_ECD_CTRL_EXPC0_INTRPT_ENABLE_SHIFT                  7

/* BRPHY3_ECD_CTRL :: EXPC0 :: STOP_PLL_CLK [06:06] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x40,6,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x40,6)
#define BRPHY3_ECD_CTRL_EXPC0_STOP_PLL_CLK_MASK                    0x0040
#define BRPHY3_ECD_CTRL_EXPC0_STOP_PLL_CLK_ALIGN                   0
#define BRPHY3_ECD_CTRL_EXPC0_STOP_PLL_CLK_BITS                    1
#define BRPHY3_ECD_CTRL_EXPC0_STOP_PLL_CLK_SHIFT                   6

/* BRPHY3_ECD_CTRL :: EXPC0 :: reserved1 [05:04] */
#define BRPHY3_ECD_CTRL_EXPC0_RESERVED1_MASK                       0x0030
#define BRPHY3_ECD_CTRL_EXPC0_RESERVED1_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPC0_RESERVED1_BITS                       2
#define BRPHY3_ECD_CTRL_EXPC0_RESERVED1_SHIFT                      4

/* BRPHY3_ECD_CTRL :: EXPC0 :: INVALID_RESULT [03:03] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_INVALID_RESULT(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x8,3,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_INVALID_RESULT(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x8,3)
#define BRPHY3_ECD_CTRL_EXPC0_INVALID_RESULT_MASK                  0x0008
#define BRPHY3_ECD_CTRL_EXPC0_INVALID_RESULT_ALIGN                 0
#define BRPHY3_ECD_CTRL_EXPC0_INVALID_RESULT_BITS                  1
#define BRPHY3_ECD_CTRL_EXPC0_INVALID_RESULT_SHIFT                 3

/* BRPHY3_ECD_CTRL :: EXPC0 :: CABLE_DIAG_EXE [02:02] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x4,2,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x4,2)
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_MASK                  0x0004
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_ALIGN                 0
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_BITS                  1
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_SHIFT                 2

/* BRPHY3_ECD_CTRL :: EXPC0 :: AUTO_RUN_FOR_BROKEN_ANG [01:01] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x2,1,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x2,1)
#define BRPHY3_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_MASK         0x0002
#define BRPHY3_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_ALIGN        0
#define BRPHY3_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_BITS         1
#define BRPHY3_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_SHIFT        1

/* BRPHY3_ECD_CTRL :: EXPC0 :: CABLE_TYPE [00:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC0_CABLE_TYPE(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x1,0,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC0_CABLE_TYPE(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC0,0x1,0)
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_TYPE_MASK                      0x0001
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_TYPE_ALIGN                     0
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_TYPE_BITS                      1
#define BRPHY3_ECD_CTRL_EXPC0_CABLE_TYPE_SHIFT                     0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC1
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC1 :: PA_CD_CODE [15:12] */
#define Wr_BRPHY3_ECD_CTRL_EXPC1_PA_CD_CODE(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC1,0xf000,12,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC1_PA_CD_CODE(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC1,0xf000,12)
#define BRPHY3_ECD_CTRL_EXPC1_PA_CD_CODE_MASK                      0xf000
#define BRPHY3_ECD_CTRL_EXPC1_PA_CD_CODE_ALIGN                     0
#define BRPHY3_ECD_CTRL_EXPC1_PA_CD_CODE_BITS                      4
#define BRPHY3_ECD_CTRL_EXPC1_PA_CD_CODE_SHIFT                     12

/* BRPHY3_ECD_CTRL :: EXPC1 :: PB_CD_CODE [11:08] */
#define Wr_BRPHY3_ECD_CTRL_EXPC1_PB_CD_CODE(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC1,0xf00,8,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC1_PB_CD_CODE(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC1,0xf00,8)
#define BRPHY3_ECD_CTRL_EXPC1_PB_CD_CODE_MASK                      0x0f00
#define BRPHY3_ECD_CTRL_EXPC1_PB_CD_CODE_ALIGN                     0
#define BRPHY3_ECD_CTRL_EXPC1_PB_CD_CODE_BITS                      4
#define BRPHY3_ECD_CTRL_EXPC1_PB_CD_CODE_SHIFT                     8

/* BRPHY3_ECD_CTRL :: EXPC1 :: PC_CD_CODE [07:04] */
#define Wr_BRPHY3_ECD_CTRL_EXPC1_PC_CD_CODE(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC1,0xf0,4,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC1_PC_CD_CODE(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC1,0xf0,4)
#define BRPHY3_ECD_CTRL_EXPC1_PC_CD_CODE_MASK                      0x00f0
#define BRPHY3_ECD_CTRL_EXPC1_PC_CD_CODE_ALIGN                     0
#define BRPHY3_ECD_CTRL_EXPC1_PC_CD_CODE_BITS                      4
#define BRPHY3_ECD_CTRL_EXPC1_PC_CD_CODE_SHIFT                     4

/* BRPHY3_ECD_CTRL :: EXPC1 :: PD_CD_CODE [03:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC1_PD_CD_CODE(x) WriteRegBits16(BRPHY3_ECD_CTRL_EXPC1,0xf,0,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC1_PD_CD_CODE(x) ReadRegBits16(BRPHY3_ECD_CTRL_EXPC1,0xf,0)
#define BRPHY3_ECD_CTRL_EXPC1_PD_CD_CODE_MASK                      0x000f
#define BRPHY3_ECD_CTRL_EXPC1_PD_CD_CODE_ALIGN                     0
#define BRPHY3_ECD_CTRL_EXPC1_PD_CD_CODE_BITS                      4
#define BRPHY3_ECD_CTRL_EXPC1_PD_CD_CODE_SHIFT                     0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC2
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC2 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) WriteReg16(BRPHY3_ECD_CTRL_EXPC2,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) ReadReg16(BRPHY3_ECD_CTRL_EXPC2)
#define BRPHY3_ECD_CTRL_EXPC2_LENGTH_INDICATION_MASK               0xffff
#define BRPHY3_ECD_CTRL_EXPC2_LENGTH_INDICATION_ALIGN              0
#define BRPHY3_ECD_CTRL_EXPC2_LENGTH_INDICATION_BITS               16
#define BRPHY3_ECD_CTRL_EXPC2_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC3
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC3 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) WriteReg16(BRPHY3_ECD_CTRL_EXPC3,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) ReadReg16(BRPHY3_ECD_CTRL_EXPC3)
#define BRPHY3_ECD_CTRL_EXPC3_LENGTH_INDICATION_MASK               0xffff
#define BRPHY3_ECD_CTRL_EXPC3_LENGTH_INDICATION_ALIGN              0
#define BRPHY3_ECD_CTRL_EXPC3_LENGTH_INDICATION_BITS               16
#define BRPHY3_ECD_CTRL_EXPC3_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC4
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC4 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) WriteReg16(BRPHY3_ECD_CTRL_EXPC4,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) ReadReg16(BRPHY3_ECD_CTRL_EXPC4)
#define BRPHY3_ECD_CTRL_EXPC4_LENGTH_INDICATION_MASK               0xffff
#define BRPHY3_ECD_CTRL_EXPC4_LENGTH_INDICATION_ALIGN              0
#define BRPHY3_ECD_CTRL_EXPC4_LENGTH_INDICATION_BITS               16
#define BRPHY3_ECD_CTRL_EXPC4_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC5
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC5 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) WriteReg16(BRPHY3_ECD_CTRL_EXPC5,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) ReadReg16(BRPHY3_ECD_CTRL_EXPC5)
#define BRPHY3_ECD_CTRL_EXPC5_LENGTH_INDICATION_MASK               0xffff
#define BRPHY3_ECD_CTRL_EXPC5_LENGTH_INDICATION_ALIGN              0
#define BRPHY3_ECD_CTRL_EXPC5_LENGTH_INDICATION_BITS               16
#define BRPHY3_ECD_CTRL_EXPC5_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC6
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC6 :: F_COUNT_0 [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC6_F_COUNT_0(x) WriteReg16(BRPHY3_ECD_CTRL_EXPC6,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC6_F_COUNT_0(x) ReadReg16(BRPHY3_ECD_CTRL_EXPC6)
#define BRPHY3_ECD_CTRL_EXPC6_F_COUNT_0_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPC6_F_COUNT_0_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPC6_F_COUNT_0_BITS                       16
#define BRPHY3_ECD_CTRL_EXPC6_F_COUNT_0_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC7
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC7 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC7_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPC7,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC7_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPC7)
#define BRPHY3_ECD_CTRL_EXPC7_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPC7_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPC7_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPC7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC8
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC8 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC8_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPC8,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC8_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPC8)
#define BRPHY3_ECD_CTRL_EXPC8_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPC8_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPC8_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPC8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPC9
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPC9 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPC9_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPC9,x)
#define Rd_BRPHY3_ECD_CTRL_EXPC9_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPC9)
#define BRPHY3_ECD_CTRL_EXPC9_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPC9_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPC9_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPC9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPCA
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPCA :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPCA_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPCA,x)
#define Rd_BRPHY3_ECD_CTRL_EXPCA_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPCA)
#define BRPHY3_ECD_CTRL_EXPCA_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPCA_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPCA_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPCA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPCB
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPCB :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPCB_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPCB,x)
#define Rd_BRPHY3_ECD_CTRL_EXPCB_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPCB)
#define BRPHY3_ECD_CTRL_EXPCB_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPCB_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPCB_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPCB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPCC
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPCC :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPCC_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPCC,x)
#define Rd_BRPHY3_ECD_CTRL_EXPCC_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPCC)
#define BRPHY3_ECD_CTRL_EXPCC_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPCC_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPCC_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPCC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPCD
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPCD :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPCD_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPCD,x)
#define Rd_BRPHY3_ECD_CTRL_EXPCD_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPCD)
#define BRPHY3_ECD_CTRL_EXPCD_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPCD_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPCD_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPCD_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPCE
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPCE :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPCE_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPCE,x)
#define Rd_BRPHY3_ECD_CTRL_EXPCE_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPCE)
#define BRPHY3_ECD_CTRL_EXPCE_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPCE_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPCE_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPCE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPCF
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPCF :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPCF_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPCF,x)
#define Rd_BRPHY3_ECD_CTRL_EXPCF_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPCF)
#define BRPHY3_ECD_CTRL_EXPCF_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPCF_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPCF_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPCF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE0
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE0 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE0_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE0,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE0_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE0)
#define BRPHY3_ECD_CTRL_EXPE0_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE0_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE0_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE0_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE1
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE1 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE1_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE1,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE1_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE1)
#define BRPHY3_ECD_CTRL_EXPE1_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE1_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE1_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE1_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE2
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE2 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE2_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE2,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE2_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE2)
#define BRPHY3_ECD_CTRL_EXPE2_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE2_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE2_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE2_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE3
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE3 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE3_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE3,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE3_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE3)
#define BRPHY3_ECD_CTRL_EXPE3_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE3_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE3_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE3_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE4
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE4 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE4_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE4,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE4_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE4)
#define BRPHY3_ECD_CTRL_EXPE4_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE4_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE4_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE4_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE5
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE5 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE5_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE5,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE5_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE5)
#define BRPHY3_ECD_CTRL_EXPE5_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE5_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE5_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE5_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE6
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE6 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE6_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE6,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE6_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE6)
#define BRPHY3_ECD_CTRL_EXPE6_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE6_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE6_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE6_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE7
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE7 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE7_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE7,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE7_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE7)
#define BRPHY3_ECD_CTRL_EXPE7_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE7_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE7_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE8
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE8 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE8_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE8,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE8_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE8)
#define BRPHY3_ECD_CTRL_EXPE8_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE8_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE8_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPE9
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPE9 :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPE9_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPE9,x)
#define Rd_BRPHY3_ECD_CTRL_EXPE9_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPE9)
#define BRPHY3_ECD_CTRL_EXPE9_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPE9_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPE9_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPE9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPEA
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPEA :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPEA_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPEA,x)
#define Rd_BRPHY3_ECD_CTRL_EXPEA_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPEA)
#define BRPHY3_ECD_CTRL_EXPEA_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPEA_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPEA_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPEA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPEB
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPEB :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPEB_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPEB,x)
#define Rd_BRPHY3_ECD_CTRL_EXPEB_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPEB)
#define BRPHY3_ECD_CTRL_EXPEB_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPEB_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPEB_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPEB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPEC
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPEC :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPEC_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPEC,x)
#define Rd_BRPHY3_ECD_CTRL_EXPEC_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPEC)
#define BRPHY3_ECD_CTRL_EXPEC_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPEC_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPEC_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPEC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPED
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPED :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPED_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPED,x)
#define Rd_BRPHY3_ECD_CTRL_EXPED_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPED)
#define BRPHY3_ECD_CTRL_EXPED_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPED_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPED_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPED_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPEE
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPEE :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPEE_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPEE,x)
#define Rd_BRPHY3_ECD_CTRL_EXPEE_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPEE)
#define BRPHY3_ECD_CTRL_EXPEE_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPEE_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPEE_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPEE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY3_ECD_CTRL :: EXPEF
 ***************************************************************************/
/* BRPHY3_ECD_CTRL :: EXPEF :: UNDEFINED [15:00] */
#define Wr_BRPHY3_ECD_CTRL_EXPEF_UNDEFINED(x) WriteReg16(BRPHY3_ECD_CTRL_EXPEF,x)
#define Rd_BRPHY3_ECD_CTRL_EXPEF_UNDEFINED(x) ReadReg16(BRPHY3_ECD_CTRL_EXPEF)
#define BRPHY3_ECD_CTRL_EXPEF_UNDEFINED_MASK                       0xffff
#define BRPHY3_ECD_CTRL_EXPEF_UNDEFINED_ALIGN                      0
#define BRPHY3_ECD_CTRL_EXPEF_UNDEFINED_BITS                       16
#define BRPHY3_ECD_CTRL_EXPEF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_BR_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP90
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP90 :: DIG_HPF_EN [15:15] */
#define Wr_BRPHY3_BR_CTRL_EXP90_DIG_HPF_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP90,0x8000,15,x)
#define Rd_BRPHY3_BR_CTRL_EXP90_DIG_HPF_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP90,0x8000,15)
#define BRPHY3_BR_CTRL_EXP90_DIG_HPF_EN_MASK                       0x8000
#define BRPHY3_BR_CTRL_EXP90_DIG_HPF_EN_ALIGN                      0
#define BRPHY3_BR_CTRL_EXP90_DIG_HPF_EN_BITS                       1
#define BRPHY3_BR_CTRL_EXP90_DIG_HPF_EN_SHIFT                      15

/* BRPHY3_BR_CTRL :: EXP90 :: BR_SCR_STATUS [14:13] */
#define Wr_BRPHY3_BR_CTRL_EXP90_BR_SCR_STATUS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP90,0x6000,13,x)
#define Rd_BRPHY3_BR_CTRL_EXP90_BR_SCR_STATUS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP90,0x6000,13)
#define BRPHY3_BR_CTRL_EXP90_BR_SCR_STATUS_MASK                    0x6000
#define BRPHY3_BR_CTRL_EXP90_BR_SCR_STATUS_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP90_BR_SCR_STATUS_BITS                    2
#define BRPHY3_BR_CTRL_EXP90_BR_SCR_STATUS_SHIFT                   13

/* BRPHY3_BR_CTRL :: EXP90 :: BR_ALIGN_STATE [12:10] */
#define Wr_BRPHY3_BR_CTRL_EXP90_BR_ALIGN_STATE(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP90,0x1c00,10,x)
#define Rd_BRPHY3_BR_CTRL_EXP90_BR_ALIGN_STATE(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP90,0x1c00,10)
#define BRPHY3_BR_CTRL_EXP90_BR_ALIGN_STATE_MASK                   0x1c00
#define BRPHY3_BR_CTRL_EXP90_BR_ALIGN_STATE_ALIGN                  0
#define BRPHY3_BR_CTRL_EXP90_BR_ALIGN_STATE_BITS                   3
#define BRPHY3_BR_CTRL_EXP90_BR_ALIGN_STATE_SHIFT                  10

/* BRPHY3_BR_CTRL :: EXP90 :: BR_RX_STATE [09:06] */
#define Wr_BRPHY3_BR_CTRL_EXP90_BR_RX_STATE(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP90,0x3c0,6,x)
#define Rd_BRPHY3_BR_CTRL_EXP90_BR_RX_STATE(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP90,0x3c0,6)
#define BRPHY3_BR_CTRL_EXP90_BR_RX_STATE_MASK                      0x03c0
#define BRPHY3_BR_CTRL_EXP90_BR_RX_STATE_ALIGN                     0
#define BRPHY3_BR_CTRL_EXP90_BR_RX_STATE_BITS                      4
#define BRPHY3_BR_CTRL_EXP90_BR_RX_STATE_SHIFT                     6

/* BRPHY3_BR_CTRL :: EXP90 :: BR_PCS_STATE [05:02] */
#define Wr_BRPHY3_BR_CTRL_EXP90_BR_PCS_STATE(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP90,0x3c,2,x)
#define Rd_BRPHY3_BR_CTRL_EXP90_BR_PCS_STATE(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP90,0x3c,2)
#define BRPHY3_BR_CTRL_EXP90_BR_PCS_STATE_MASK                     0x003c
#define BRPHY3_BR_CTRL_EXP90_BR_PCS_STATE_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP90_BR_PCS_STATE_BITS                     4
#define BRPHY3_BR_CTRL_EXP90_BR_PCS_STATE_SHIFT                    2

/* BRPHY3_BR_CTRL :: EXP90 :: BR_FORCE_LINK_CTL [01:01] */
#define Wr_BRPHY3_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP90,0x2,1,x)
#define Rd_BRPHY3_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP90,0x2,1)
#define BRPHY3_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_MASK                0x0002
#define BRPHY3_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_ALIGN               0
#define BRPHY3_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_BITS                1
#define BRPHY3_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_SHIFT               1

/* BRPHY3_BR_CTRL :: EXP90 :: BR_EN [00:00] */
#define Wr_BRPHY3_BR_CTRL_EXP90_BR_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP90,0x1,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP90_BR_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP90,0x1,0)
#define BRPHY3_BR_CTRL_EXP90_BR_EN_MASK                            0x0001
#define BRPHY3_BR_CTRL_EXP90_BR_EN_ALIGN                           0
#define BRPHY3_BR_CTRL_EXP90_BR_EN_BITS                            1
#define BRPHY3_BR_CTRL_EXP90_BR_EN_SHIFT                           0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP91
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP91 :: DIG_HPF_OV [15:15] */
#define Wr_BRPHY3_BR_CTRL_EXP91_DIG_HPF_OV(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0x8000,15,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_DIG_HPF_OV(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0x8000,15)
#define BRPHY3_BR_CTRL_EXP91_DIG_HPF_OV_MASK                       0x8000
#define BRPHY3_BR_CTRL_EXP91_DIG_HPF_OV_ALIGN                      0
#define BRPHY3_BR_CTRL_EXP91_DIG_HPF_OV_BITS                       1
#define BRPHY3_BR_CTRL_EXP91_DIG_HPF_OV_SHIFT                      15

/* BRPHY3_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV [14:14] */
#define Wr_BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0x4000,14,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0x4000,14)
#define BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_MASK               0x4000
#define BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_ALIGN              0
#define BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_BITS               1
#define BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_SHIFT              14

/* BRPHY3_BR_CTRL :: EXP91 :: INV_LRE_GMII_TXC [13:13] */
#define Wr_BRPHY3_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0x2000,13,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0x2000,13)
#define BRPHY3_BR_CTRL_EXP91_INV_LRE_GMII_TXC_MASK                 0x2000
#define BRPHY3_BR_CTRL_EXP91_INV_LRE_GMII_TXC_ALIGN                0
#define BRPHY3_BR_CTRL_EXP91_INV_LRE_GMII_TXC_BITS                 1
#define BRPHY3_BR_CTRL_EXP91_INV_LRE_GMII_TXC_SHIFT                13

/* BRPHY3_BR_CTRL :: EXP91 :: AGC_AUTOSTAGING_DIS [12:12] */
#define Wr_BRPHY3_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0x1000,12,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0x1000,12)
#define BRPHY3_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_MASK              0x1000
#define BRPHY3_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_ALIGN             0
#define BRPHY3_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_BITS              1
#define BRPHY3_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_SHIFT             12

/* BRPHY3_BR_CTRL :: EXP91 :: BRPGA [11:09] */
#define Wr_BRPHY3_BR_CTRL_EXP91_BRPGA(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0xe00,9,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_BRPGA(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0xe00,9)
#define BRPHY3_BR_CTRL_EXP91_BRPGA_MASK                            0x0e00
#define BRPHY3_BR_CTRL_EXP91_BRPGA_ALIGN                           0
#define BRPHY3_BR_CTRL_EXP91_BRPGA_BITS                            3
#define BRPHY3_BR_CTRL_EXP91_BRPGA_SHIFT                           9

/* BRPHY3_BR_CTRL :: EXP91 :: BRCONFIG [08:04] */
#define Wr_BRPHY3_BR_CTRL_EXP91_BRCONFIG(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0x1f0,4,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_BRCONFIG(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0x1f0,4)
#define BRPHY3_BR_CTRL_EXP91_BRCONFIG_MASK                         0x01f0
#define BRPHY3_BR_CTRL_EXP91_BRCONFIG_ALIGN                        0
#define BRPHY3_BR_CTRL_EXP91_BRCONFIG_BITS                         5
#define BRPHY3_BR_CTRL_EXP91_BRCONFIG_SHIFT                        4

/* BRPHY3_BR_CTRL :: EXP91 :: ACQP_EN_ECO_DIS [03:03] */
#define Wr_BRPHY3_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0x8,3,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0x8,3)
#define BRPHY3_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_MASK                  0x0008
#define BRPHY3_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_ALIGN                 0
#define BRPHY3_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_BITS                  1
#define BRPHY3_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_SHIFT                 3

/* BRPHY3_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV_VAL [02:02] */
#define Wr_BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0x4,2,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0x4,2)
#define BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_MASK           0x0004
#define BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_ALIGN          0
#define BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_BITS           1
#define BRPHY3_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_SHIFT          2

/* BRPHY3_BR_CTRL :: EXP91 :: TXSCR_ZERO_SEED [01:01] */
#define Wr_BRPHY3_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0x2,1,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0x2,1)
#define BRPHY3_BR_CTRL_EXP91_TXSCR_ZERO_SEED_MASK                  0x0002
#define BRPHY3_BR_CTRL_EXP91_TXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY3_BR_CTRL_EXP91_TXSCR_ZERO_SEED_BITS                  1
#define BRPHY3_BR_CTRL_EXP91_TXSCR_ZERO_SEED_SHIFT                 1

/* BRPHY3_BR_CTRL :: EXP91 :: RXSCR_ZERO_SEED [00:00] */
#define Wr_BRPHY3_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP91,0x1,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP91,0x1,0)
#define BRPHY3_BR_CTRL_EXP91_RXSCR_ZERO_SEED_MASK                  0x0001
#define BRPHY3_BR_CTRL_EXP91_RXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY3_BR_CTRL_EXP91_RXSCR_ZERO_SEED_BITS                  1
#define BRPHY3_BR_CTRL_EXP91_RXSCR_ZERO_SEED_SHIFT                 0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP92
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP92 :: DLLCONV_OV_EN [15:15] */
#define Wr_BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x8000,15,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x8000,15)
#define BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_EN_MASK                    0x8000
#define BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_EN_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_EN_BITS                    1
#define BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_EN_SHIFT                   15

/* BRPHY3_BR_CTRL :: EXP92 :: DLLCONV_OV_VAL [14:14] */
#define Wr_BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x4000,14,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x4000,14)
#define BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_VAL_MASK                   0x4000
#define BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_VAL_ALIGN                  0
#define BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_VAL_BITS                   1
#define BRPHY3_BR_CTRL_EXP92_DLLCONV_OV_VAL_SHIFT                  14

/* BRPHY3_BR_CTRL :: EXP92 :: BR_SLAVE_POL_COR_EN [13:13] */
#define Wr_BRPHY3_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x2000,13,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x2000,13)
#define BRPHY3_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_MASK              0x2000
#define BRPHY3_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_ALIGN             0
#define BRPHY3_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_BITS              1
#define BRPHY3_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_SHIFT             13

/* BRPHY3_BR_CTRL :: EXP92 :: BR_EDGE_RATE_SEL [12:11] */
#define Wr_BRPHY3_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x1800,11,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x1800,11)
#define BRPHY3_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_MASK                 0x1800
#define BRPHY3_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_ALIGN                0
#define BRPHY3_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_BITS                 2
#define BRPHY3_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_SHIFT                11

/* BRPHY3_BR_CTRL :: EXP92 :: BR_PCS_RRNOK_POL_EN [10:10] */
#define Wr_BRPHY3_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x400,10,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x400,10)
#define BRPHY3_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_MASK              0x0400
#define BRPHY3_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_ALIGN             0
#define BRPHY3_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_BITS              1
#define BRPHY3_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_SHIFT             10

/* BRPHY3_BR_CTRL :: EXP92 :: LDS_LNK_CHK_ECO_DIS [09:09] */
#define Wr_BRPHY3_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x200,9,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x200,9)
#define BRPHY3_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_MASK              0x0200
#define BRPHY3_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_ALIGN             0
#define BRPHY3_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_BITS              1
#define BRPHY3_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_SHIFT             9

/* BRPHY3_BR_CTRL :: EXP92 :: BR_PCS_POL_EN [08:08] */
#define Wr_BRPHY3_BR_CTRL_EXP92_BR_PCS_POL_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x100,8,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_BR_PCS_POL_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x100,8)
#define BRPHY3_BR_CTRL_EXP92_BR_PCS_POL_EN_MASK                    0x0100
#define BRPHY3_BR_CTRL_EXP92_BR_PCS_POL_EN_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP92_BR_PCS_POL_EN_BITS                    1
#define BRPHY3_BR_CTRL_EXP92_BR_PCS_POL_EN_SHIFT                   8

/* BRPHY3_BR_CTRL :: EXP92 :: JAB_MON_DIS [07:07] */
#define Wr_BRPHY3_BR_CTRL_EXP92_JAB_MON_DIS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x80,7,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_JAB_MON_DIS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x80,7)
#define BRPHY3_BR_CTRL_EXP92_JAB_MON_DIS_MASK                      0x0080
#define BRPHY3_BR_CTRL_EXP92_JAB_MON_DIS_ALIGN                     0
#define BRPHY3_BR_CTRL_EXP92_JAB_MON_DIS_BITS                      1
#define BRPHY3_BR_CTRL_EXP92_JAB_MON_DIS_SHIFT                     7

/* BRPHY3_BR_CTRL :: EXP92 :: BR_AGCSID_TMR_EN [06:06] */
#define Wr_BRPHY3_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x40,6,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x40,6)
#define BRPHY3_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_MASK                 0x0040
#define BRPHY3_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_ALIGN                0
#define BRPHY3_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_BITS                 1
#define BRPHY3_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_SHIFT                6

/* BRPHY3_BR_CTRL :: EXP92 :: BR_SYM_XSCR_EN [05:05] */
#define Wr_BRPHY3_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x20,5,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x20,5)
#define BRPHY3_BR_CTRL_EXP92_BR_SYM_XSCR_EN_MASK                   0x0020
#define BRPHY3_BR_CTRL_EXP92_BR_SYM_XSCR_EN_ALIGN                  0
#define BRPHY3_BR_CTRL_EXP92_BR_SYM_XSCR_EN_BITS                   1
#define BRPHY3_BR_CTRL_EXP92_BR_SYM_XSCR_EN_SHIFT                  5

/* BRPHY3_BR_CTRL :: EXP92 :: CHK_DELIMITER [04:04] */
#define Wr_BRPHY3_BR_CTRL_EXP92_CHK_DELIMITER(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x10,4,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_CHK_DELIMITER(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x10,4)
#define BRPHY3_BR_CTRL_EXP92_CHK_DELIMITER_MASK                    0x0010
#define BRPHY3_BR_CTRL_EXP92_CHK_DELIMITER_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP92_CHK_DELIMITER_BITS                    1
#define BRPHY3_BR_CTRL_EXP92_CHK_DELIMITER_SHIFT                   4

/* BRPHY3_BR_CTRL :: EXP92 :: TX_READ_DLY [03:02] */
#define Wr_BRPHY3_BR_CTRL_EXP92_TX_READ_DLY(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0xc,2,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_TX_READ_DLY(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0xc,2)
#define BRPHY3_BR_CTRL_EXP92_TX_READ_DLY_MASK                      0x000c
#define BRPHY3_BR_CTRL_EXP92_TX_READ_DLY_ALIGN                     0
#define BRPHY3_BR_CTRL_EXP92_TX_READ_DLY_BITS                      2
#define BRPHY3_BR_CTRL_EXP92_TX_READ_DLY_SHIFT                     2

/* BRPHY3_BR_CTRL :: EXP92 :: RX_READ_DLY [01:00] */
#define Wr_BRPHY3_BR_CTRL_EXP92_RX_READ_DLY(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP92,0x3,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP92_RX_READ_DLY(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP92,0x3,0)
#define BRPHY3_BR_CTRL_EXP92_RX_READ_DLY_MASK                      0x0003
#define BRPHY3_BR_CTRL_EXP92_RX_READ_DLY_ALIGN                     0
#define BRPHY3_BR_CTRL_EXP92_RX_READ_DLY_BITS                      2
#define BRPHY3_BR_CTRL_EXP92_RX_READ_DLY_SHIFT                     0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP93
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP93 :: LDS_CAP_DOWNGRADE_DIS [15:15] */
#define Wr_BRPHY3_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP93,0x8000,15,x)
#define Rd_BRPHY3_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP93,0x8000,15)
#define BRPHY3_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_MASK            0x8000
#define BRPHY3_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_ALIGN           0
#define BRPHY3_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_BITS            1
#define BRPHY3_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_SHIFT           15

/* BRPHY3_BR_CTRL :: EXP93 :: LDS_REORDER_DIS [14:14] */
#define Wr_BRPHY3_BR_CTRL_EXP93_LDS_REORDER_DIS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP93,0x4000,14,x)
#define Rd_BRPHY3_BR_CTRL_EXP93_LDS_REORDER_DIS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP93,0x4000,14)
#define BRPHY3_BR_CTRL_EXP93_LDS_REORDER_DIS_MASK                  0x4000
#define BRPHY3_BR_CTRL_EXP93_LDS_REORDER_DIS_ALIGN                 0
#define BRPHY3_BR_CTRL_EXP93_LDS_REORDER_DIS_BITS                  1
#define BRPHY3_BR_CTRL_EXP93_LDS_REORDER_DIS_SHIFT                 14

/* BRPHY3_BR_CTRL :: EXP93 :: LDS_SIM [13:13] */
#define Wr_BRPHY3_BR_CTRL_EXP93_LDS_SIM(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP93,0x2000,13,x)
#define Rd_BRPHY3_BR_CTRL_EXP93_LDS_SIM(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP93,0x2000,13)
#define BRPHY3_BR_CTRL_EXP93_LDS_SIM_MASK                          0x2000
#define BRPHY3_BR_CTRL_EXP93_LDS_SIM_ALIGN                         0
#define BRPHY3_BR_CTRL_EXP93_LDS_SIM_BITS                          1
#define BRPHY3_BR_CTRL_EXP93_LDS_SIM_SHIFT                         13

/* BRPHY3_BR_CTRL :: EXP93 :: LDS_SCR_ON [12:12] */
#define Wr_BRPHY3_BR_CTRL_EXP93_LDS_SCR_ON(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP93,0x1000,12,x)
#define Rd_BRPHY3_BR_CTRL_EXP93_LDS_SCR_ON(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP93,0x1000,12)
#define BRPHY3_BR_CTRL_EXP93_LDS_SCR_ON_MASK                       0x1000
#define BRPHY3_BR_CTRL_EXP93_LDS_SCR_ON_ALIGN                      0
#define BRPHY3_BR_CTRL_EXP93_LDS_SCR_ON_BITS                       1
#define BRPHY3_BR_CTRL_EXP93_LDS_SCR_ON_SHIFT                      12

/* BRPHY3_BR_CTRL :: EXP93 :: LDS_PHASE_BYP [11:11] */
#define Wr_BRPHY3_BR_CTRL_EXP93_LDS_PHASE_BYP(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP93,0x800,11,x)
#define Rd_BRPHY3_BR_CTRL_EXP93_LDS_PHASE_BYP(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP93,0x800,11)
#define BRPHY3_BR_CTRL_EXP93_LDS_PHASE_BYP_MASK                    0x0800
#define BRPHY3_BR_CTRL_EXP93_LDS_PHASE_BYP_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP93_LDS_PHASE_BYP_BITS                    1
#define BRPHY3_BR_CTRL_EXP93_LDS_PHASE_BYP_SHIFT                   11

/* BRPHY3_BR_CTRL :: EXP93 :: LDS_PHASE_INIT [10:08] */
#define Wr_BRPHY3_BR_CTRL_EXP93_LDS_PHASE_INIT(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP93,0x700,8,x)
#define Rd_BRPHY3_BR_CTRL_EXP93_LDS_PHASE_INIT(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP93,0x700,8)
#define BRPHY3_BR_CTRL_EXP93_LDS_PHASE_INIT_MASK                   0x0700
#define BRPHY3_BR_CTRL_EXP93_LDS_PHASE_INIT_ALIGN                  0
#define BRPHY3_BR_CTRL_EXP93_LDS_PHASE_INIT_BITS                   3
#define BRPHY3_BR_CTRL_EXP93_LDS_PHASE_INIT_SHIFT                  8

/* BRPHY3_BR_CTRL :: EXP93 :: LDS_PEAK_THR [07:00] */
#define Wr_BRPHY3_BR_CTRL_EXP93_LDS_PEAK_THR(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP93,0xff,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP93_LDS_PEAK_THR(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP93,0xff,0)
#define BRPHY3_BR_CTRL_EXP93_LDS_PEAK_THR_MASK                     0x00ff
#define BRPHY3_BR_CTRL_EXP93_LDS_PEAK_THR_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP93_LDS_PEAK_THR_BITS                     8
#define BRPHY3_BR_CTRL_EXP93_LDS_PEAK_THR_SHIFT                    0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP94
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP94 :: LDS_LEN_THR1 [15:08] */
#define Wr_BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR1(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP94,0xff00,8,x)
#define Rd_BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR1(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP94,0xff00,8)
#define BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR1_MASK                     0xff00
#define BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR1_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR1_BITS                     8
#define BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR1_SHIFT                    8

/* BRPHY3_BR_CTRL :: EXP94 :: LDS_LEN_THR0 [07:00] */
#define Wr_BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR0(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP94,0xff,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR0(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP94,0xff,0)
#define BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR0_MASK                     0x00ff
#define BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR0_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR0_BITS                     8
#define BRPHY3_BR_CTRL_EXP94_LDS_LEN_THR0_SHIFT                    0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP95
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP95 :: LDS_LEN_THR3 [15:08] */
#define Wr_BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR3(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP95,0xff00,8,x)
#define Rd_BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR3(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP95,0xff00,8)
#define BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR3_MASK                     0xff00
#define BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR3_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR3_BITS                     8
#define BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR3_SHIFT                    8

/* BRPHY3_BR_CTRL :: EXP95 :: LDS_LEN_THR2 [07:00] */
#define Wr_BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR2(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP95,0xff,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR2(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP95,0xff,0)
#define BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR2_MASK                     0x00ff
#define BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR2_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR2_BITS                     8
#define BRPHY3_BR_CTRL_EXP95_LDS_LEN_THR2_SHIFT                    0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP96
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP96 :: LDS_TONE_FREQ [15:15] */
#define Wr_BRPHY3_BR_CTRL_EXP96_LDS_TONE_FREQ(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP96,0x8000,15,x)
#define Rd_BRPHY3_BR_CTRL_EXP96_LDS_TONE_FREQ(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP96,0x8000,15)
#define BRPHY3_BR_CTRL_EXP96_LDS_TONE_FREQ_MASK                    0x8000
#define BRPHY3_BR_CTRL_EXP96_LDS_TONE_FREQ_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP96_LDS_TONE_FREQ_BITS                    1
#define BRPHY3_BR_CTRL_EXP96_LDS_TONE_FREQ_SHIFT                   15

/* BRPHY3_BR_CTRL :: EXP96 :: LDS_EXT_AB_DWNGRD [14:14] */
#define Wr_BRPHY3_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP96,0x4000,14,x)
#define Rd_BRPHY3_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP96,0x4000,14)
#define BRPHY3_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_MASK                0x4000
#define BRPHY3_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_ALIGN               0
#define BRPHY3_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_BITS                1
#define BRPHY3_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_SHIFT               14

/* BRPHY3_BR_CTRL :: EXP96 :: LDS_SCAN_FSM [13:12] */
#define Wr_BRPHY3_BR_CTRL_EXP96_LDS_SCAN_FSM(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP96,0x3000,12,x)
#define Rd_BRPHY3_BR_CTRL_EXP96_LDS_SCAN_FSM(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP96,0x3000,12)
#define BRPHY3_BR_CTRL_EXP96_LDS_SCAN_FSM_MASK                     0x3000
#define BRPHY3_BR_CTRL_EXP96_LDS_SCAN_FSM_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP96_LDS_SCAN_FSM_BITS                     2
#define BRPHY3_BR_CTRL_EXP96_LDS_SCAN_FSM_SHIFT                    12

/* BRPHY3_BR_CTRL :: EXP96 :: CUR_LOC_FNUM [11:04] */
#define Wr_BRPHY3_BR_CTRL_EXP96_CUR_LOC_FNUM(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP96,0xff0,4,x)
#define Rd_BRPHY3_BR_CTRL_EXP96_CUR_LOC_FNUM(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP96,0xff0,4)
#define BRPHY3_BR_CTRL_EXP96_CUR_LOC_FNUM_MASK                     0x0ff0
#define BRPHY3_BR_CTRL_EXP96_CUR_LOC_FNUM_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP96_CUR_LOC_FNUM_BITS                     8
#define BRPHY3_BR_CTRL_EXP96_CUR_LOC_FNUM_SHIFT                    4

/* BRPHY3_BR_CTRL :: EXP96 :: LDS_SPD [03:00] */
#define Wr_BRPHY3_BR_CTRL_EXP96_LDS_SPD(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP96,0xf,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP96_LDS_SPD(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP96,0xf,0)
#define BRPHY3_BR_CTRL_EXP96_LDS_SPD_MASK                          0x000f
#define BRPHY3_BR_CTRL_EXP96_LDS_SPD_ALIGN                         0
#define BRPHY3_BR_CTRL_EXP96_LDS_SPD_BITS                          4
#define BRPHY3_BR_CTRL_EXP96_LDS_SPD_SHIFT                         0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP97
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP97 :: LDS_TX_FSM_H [15:12] */
#define Wr_BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_H(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP97,0xf000,12,x)
#define Rd_BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_H(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP97,0xf000,12)
#define BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_H_MASK                     0xf000
#define BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_H_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_H_BITS                     4
#define BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_H_SHIFT                    12

/* BRPHY3_BR_CTRL :: EXP97 :: LDS_TX_FSM_L [11:08] */
#define Wr_BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_L(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP97,0xf00,8,x)
#define Rd_BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_L(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP97,0xf00,8)
#define BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_L_MASK                     0x0f00
#define BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_L_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_L_BITS                     4
#define BRPHY3_BR_CTRL_EXP97_LDS_TX_FSM_L_SHIFT                    8

/* BRPHY3_BR_CTRL :: EXP97 :: LDS_ARB_FSM_H [07:04] */
#define Wr_BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP97,0xf0,4,x)
#define Rd_BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP97,0xf0,4)
#define BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_H_MASK                    0x00f0
#define BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_H_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_H_BITS                    4
#define BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_H_SHIFT                   4

/* BRPHY3_BR_CTRL :: EXP97 :: LDS_ARB_FSM_L [03:00] */
#define Wr_BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP97,0xf,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP97,0xf,0)
#define BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_L_MASK                    0x000f
#define BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_L_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_L_BITS                    4
#define BRPHY3_BR_CTRL_EXP97_LDS_ARB_FSM_L_SHIFT                   0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP99
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP99 :: LDS_PGACTRL [15:10] */
#define Wr_BRPHY3_BR_CTRL_EXP99_LDS_PGACTRL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP99,0xfc00,10,x)
#define Rd_BRPHY3_BR_CTRL_EXP99_LDS_PGACTRL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP99,0xfc00,10)
#define BRPHY3_BR_CTRL_EXP99_LDS_PGACTRL_MASK                      0xfc00
#define BRPHY3_BR_CTRL_EXP99_LDS_PGACTRL_ALIGN                     0
#define BRPHY3_BR_CTRL_EXP99_LDS_PGACTRL_BITS                      6
#define BRPHY3_BR_CTRL_EXP99_LDS_PGACTRL_SHIFT                     10

/* BRPHY3_BR_CTRL :: EXP99 :: TXDIS_TMR_OPT [09:07] */
#define Wr_BRPHY3_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP99,0x380,7,x)
#define Rd_BRPHY3_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP99,0x380,7)
#define BRPHY3_BR_CTRL_EXP99_TXDIS_TMR_OPT_MASK                    0x0380
#define BRPHY3_BR_CTRL_EXP99_TXDIS_TMR_OPT_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP99_TXDIS_TMR_OPT_BITS                    3
#define BRPHY3_BR_CTRL_EXP99_TXDIS_TMR_OPT_SHIFT                   7

/* BRPHY3_BR_CTRL :: EXP99 :: LNK_TMR_OPT [06:04] */
#define Wr_BRPHY3_BR_CTRL_EXP99_LNK_TMR_OPT(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP99,0x70,4,x)
#define Rd_BRPHY3_BR_CTRL_EXP99_LNK_TMR_OPT(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP99,0x70,4)
#define BRPHY3_BR_CTRL_EXP99_LNK_TMR_OPT_MASK                      0x0070
#define BRPHY3_BR_CTRL_EXP99_LNK_TMR_OPT_ALIGN                     0
#define BRPHY3_BR_CTRL_EXP99_LNK_TMR_OPT_BITS                      3
#define BRPHY3_BR_CTRL_EXP99_LNK_TMR_OPT_SHIFT                     4

/* BRPHY3_BR_CTRL :: EXP99 :: BST_TMR_OPT [03:01] */
#define Wr_BRPHY3_BR_CTRL_EXP99_BST_TMR_OPT(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP99,0xe,1,x)
#define Rd_BRPHY3_BR_CTRL_EXP99_BST_TMR_OPT(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP99,0xe,1)
#define BRPHY3_BR_CTRL_EXP99_BST_TMR_OPT_MASK                      0x000e
#define BRPHY3_BR_CTRL_EXP99_BST_TMR_OPT_ALIGN                     0
#define BRPHY3_BR_CTRL_EXP99_BST_TMR_OPT_BITS                      3
#define BRPHY3_BR_CTRL_EXP99_BST_TMR_OPT_SHIFT                     1

/* BRPHY3_BR_CTRL :: EXP99 :: FASTBST [00:00] */
#define Wr_BRPHY3_BR_CTRL_EXP99_FASTBST(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP99,0x1,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP99_FASTBST(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP99,0x1,0)
#define BRPHY3_BR_CTRL_EXP99_FASTBST_MASK                          0x0001
#define BRPHY3_BR_CTRL_EXP99_FASTBST_ALIGN                         0
#define BRPHY3_BR_CTRL_EXP99_FASTBST_BITS                          1
#define BRPHY3_BR_CTRL_EXP99_FASTBST_SHIFT                         0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP9A
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP9A :: LRE_REG_OV_EN [15:15] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x8000,15,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x8000,15)
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_EN_MASK                    0x8000
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_EN_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_EN_BITS                    1
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_EN_SHIFT                   15

/* BRPHY3_BR_CTRL :: EXP9A :: LRE_REG_OV_VAL [14:14] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x4000,14,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x4000,14)
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_VAL_MASK                   0x4000
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_VAL_ALIGN                  0
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_VAL_BITS                   1
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_OV_VAL_SHIFT                  14

/* BRPHY3_BR_CTRL :: EXP9A :: LRE_REG_ACCESS_STAT [13:13] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x2000,13,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x2000,13)
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_MASK              0x2000
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_ALIGN             0
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_BITS              1
#define BRPHY3_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_SHIFT             13

/* BRPHY3_BR_CTRL :: EXP9A :: LDS_LINK_CHK_EN [12:12] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x1000,12,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x1000,12)
#define BRPHY3_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_MASK                  0x1000
#define BRPHY3_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_ALIGN                 0
#define BRPHY3_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_BITS                  1
#define BRPHY3_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_SHIFT                 12

/* BRPHY3_BR_CTRL :: EXP9A :: BR_AGC_TAR_OV_EN [11:11] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x800,11,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x800,11)
#define BRPHY3_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_MASK                 0x0800
#define BRPHY3_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_ALIGN                0
#define BRPHY3_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_BITS                 1
#define BRPHY3_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_SHIFT                11

/* BRPHY3_BR_CTRL :: EXP9A :: LDS_TIMER_OV_EN [10:10] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x400,10,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x400,10)
#define BRPHY3_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_MASK                  0x0400
#define BRPHY3_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_ALIGN                 0
#define BRPHY3_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_BITS                  1
#define BRPHY3_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_SHIFT                 10

/* BRPHY3_BR_CTRL :: EXP9A :: BR_LOST_TOKEN_FIX [09:09] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x200,9,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x200,9)
#define BRPHY3_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_MASK                0x0200
#define BRPHY3_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_ALIGN               0
#define BRPHY3_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_BITS                1
#define BRPHY3_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_SHIFT               9

/* BRPHY3_BR_CTRL :: EXP9A :: DLLCONV_EN_MSTR [08:08] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x100,8,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x100,8)
#define BRPHY3_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_MASK                  0x0100
#define BRPHY3_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_ALIGN                 0
#define BRPHY3_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_BITS                  1
#define BRPHY3_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_SHIFT                 8

/* BRPHY3_BR_CTRL :: EXP9A :: BR_10M1P_HALFOUT_EN [07:07] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x80,7,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x80,7)
#define BRPHY3_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_MASK              0x0080
#define BRPHY3_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_ALIGN             0
#define BRPHY3_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_BITS              1
#define BRPHY3_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_SHIFT             7

/* BRPHY3_BR_CTRL :: EXP9A :: BR_10M2P_HALFOUT_EN [06:06] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x40,6,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x40,6)
#define BRPHY3_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_MASK              0x0040
#define BRPHY3_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_ALIGN             0
#define BRPHY3_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_BITS              1
#define BRPHY3_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_SHIFT             6

/* BRPHY3_BR_CTRL :: EXP9A :: BR_HALFOUT_EN [05:05] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x20,5,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x20,5)
#define BRPHY3_BR_CTRL_EXP9A_BR_HALFOUT_EN_MASK                    0x0020
#define BRPHY3_BR_CTRL_EXP9A_BR_HALFOUT_EN_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP9A_BR_HALFOUT_EN_BITS                    1
#define BRPHY3_BR_CTRL_EXP9A_BR_HALFOUT_EN_SHIFT                   5

/* BRPHY3_BR_CTRL :: EXP9A :: CLK100T_ECO_DIS [04:04] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0x10,4,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0x10,4)
#define BRPHY3_BR_CTRL_EXP9A_CLK100T_ECO_DIS_MASK                  0x0010
#define BRPHY3_BR_CTRL_EXP9A_CLK100T_ECO_DIS_ALIGN                 0
#define BRPHY3_BR_CTRL_EXP9A_CLK100T_ECO_DIS_BITS                  1
#define BRPHY3_BR_CTRL_EXP9A_CLK100T_ECO_DIS_SHIFT                 4

/* BRPHY3_BR_CTRL :: EXP9A :: CH_STATUS [03:00] */
#define Wr_BRPHY3_BR_CTRL_EXP9A_CH_STATUS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9A,0xf,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP9A_CH_STATUS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9A,0xf,0)
#define BRPHY3_BR_CTRL_EXP9A_CH_STATUS_MASK                        0x000f
#define BRPHY3_BR_CTRL_EXP9A_CH_STATUS_ALIGN                       0
#define BRPHY3_BR_CTRL_EXP9A_CH_STATUS_BITS                        4
#define BRPHY3_BR_CTRL_EXP9A_CH_STATUS_SHIFT                       0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP9B
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP9B :: BR_RATE_OV [15:13] */
#define Wr_BRPHY3_BR_CTRL_EXP9B_BR_RATE_OV(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9B,0xe000,13,x)
#define Rd_BRPHY3_BR_CTRL_EXP9B_BR_RATE_OV(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9B,0xe000,13)
#define BRPHY3_BR_CTRL_EXP9B_BR_RATE_OV_MASK                       0xe000
#define BRPHY3_BR_CTRL_EXP9B_BR_RATE_OV_ALIGN                      0
#define BRPHY3_BR_CTRL_EXP9B_BR_RATE_OV_BITS                       3
#define BRPHY3_BR_CTRL_EXP9B_BR_RATE_OV_SHIFT                      13

/* BRPHY3_BR_CTRL :: EXP9B :: BR_200MBPS_CLK_EN [12:12] */
#define Wr_BRPHY3_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9B,0x1000,12,x)
#define Rd_BRPHY3_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9B,0x1000,12)
#define BRPHY3_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_MASK                0x1000
#define BRPHY3_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_ALIGN               0
#define BRPHY3_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_BITS                1
#define BRPHY3_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_SHIFT               12

/* BRPHY3_BR_CTRL :: EXP9B :: BR_TXCLK_EN [11:11] */
#define Wr_BRPHY3_BR_CTRL_EXP9B_BR_TXCLK_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9B,0x800,11,x)
#define Rd_BRPHY3_BR_CTRL_EXP9B_BR_TXCLK_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9B,0x800,11)
#define BRPHY3_BR_CTRL_EXP9B_BR_TXCLK_EN_MASK                      0x0800
#define BRPHY3_BR_CTRL_EXP9B_BR_TXCLK_EN_ALIGN                     0
#define BRPHY3_BR_CTRL_EXP9B_BR_TXCLK_EN_BITS                      1
#define BRPHY3_BR_CTRL_EXP9B_BR_TXCLK_EN_SHIFT                     11

/* BRPHY3_BR_CTRL :: EXP9B :: BR_TXRXICLK_EN [10:10] */
#define Wr_BRPHY3_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9B,0x400,10,x)
#define Rd_BRPHY3_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9B,0x400,10)
#define BRPHY3_BR_CTRL_EXP9B_BR_TXRXICLK_EN_MASK                   0x0400
#define BRPHY3_BR_CTRL_EXP9B_BR_TXRXICLK_EN_ALIGN                  0
#define BRPHY3_BR_CTRL_EXP9B_BR_TXRXICLK_EN_BITS                   1
#define BRPHY3_BR_CTRL_EXP9B_BR_TXRXICLK_EN_SHIFT                  10

/* BRPHY3_BR_CTRL :: EXP9B :: CLK_1G_DIV20 [09:09] */
#define Wr_BRPHY3_BR_CTRL_EXP9B_CLK_1G_DIV20(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9B,0x200,9,x)
#define Rd_BRPHY3_BR_CTRL_EXP9B_CLK_1G_DIV20(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9B,0x200,9)
#define BRPHY3_BR_CTRL_EXP9B_CLK_1G_DIV20_MASK                     0x0200
#define BRPHY3_BR_CTRL_EXP9B_CLK_1G_DIV20_ALIGN                    0
#define BRPHY3_BR_CTRL_EXP9B_CLK_1G_DIV20_BITS                     1
#define BRPHY3_BR_CTRL_EXP9B_CLK_1G_DIV20_SHIFT                    9

/* BRPHY3_BR_CTRL :: EXP9B :: LVL1_PROG_FREQ_DIV [08:05] */
#define Wr_BRPHY3_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9B,0x1e0,5,x)
#define Rd_BRPHY3_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9B,0x1e0,5)
#define BRPHY3_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_MASK               0x01e0
#define BRPHY3_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_ALIGN              0
#define BRPHY3_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_BITS               4
#define BRPHY3_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_SHIFT              5

/* BRPHY3_BR_CTRL :: EXP9B :: LVL2_PROG_FREQ_DIV [04:01] */
#define Wr_BRPHY3_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9B,0x1e,1,x)
#define Rd_BRPHY3_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9B,0x1e,1)
#define BRPHY3_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_MASK               0x001e
#define BRPHY3_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_ALIGN              0
#define BRPHY3_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_BITS               4
#define BRPHY3_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_SHIFT              1

/* BRPHY3_BR_CTRL :: EXP9B :: BR_PLL_CTL_EN [00:00] */
#define Wr_BRPHY3_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9B,0x1,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9B,0x1,0)
#define BRPHY3_BR_CTRL_EXP9B_BR_PLL_CTL_EN_MASK                    0x0001
#define BRPHY3_BR_CTRL_EXP9B_BR_PLL_CTL_EN_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP9B_BR_PLL_CTL_EN_BITS                    1
#define BRPHY3_BR_CTRL_EXP9B_BR_PLL_CTL_EN_SHIFT                   0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP9D
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP9D :: BR_IPR_BYPASS [15:15] */
#define Wr_BRPHY3_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9D,0x8000,15,x)
#define Rd_BRPHY3_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9D,0x8000,15)
#define BRPHY3_BR_CTRL_EXP9D_BR_IPR_BYPASS_MASK                    0x8000
#define BRPHY3_BR_CTRL_EXP9D_BR_IPR_BYPASS_ALIGN                   0
#define BRPHY3_BR_CTRL_EXP9D_BR_IPR_BYPASS_BITS                    1
#define BRPHY3_BR_CTRL_EXP9D_BR_IPR_BYPASS_SHIFT                   15

/* BRPHY3_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_VAL [14:14] */
#define Wr_BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9D,0x4000,14,x)
#define Rd_BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9D,0x4000,14)
#define BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_MASK               0x4000
#define BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_ALIGN              0
#define BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_BITS               1
#define BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_SHIFT              14

/* BRPHY3_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_EN [13:13] */
#define Wr_BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9D,0x2000,13,x)
#define Rd_BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9D,0x2000,13)
#define BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_MASK                0x2000
#define BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_ALIGN               0
#define BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_BITS                1
#define BRPHY3_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_SHIFT               13

/* BRPHY3_BR_CTRL :: EXP9D :: LDS_SD_THR [12:08] */
#define Wr_BRPHY3_BR_CTRL_EXP9D_LDS_SD_THR(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9D,0x1f00,8,x)
#define Rd_BRPHY3_BR_CTRL_EXP9D_LDS_SD_THR(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9D,0x1f00,8)
#define BRPHY3_BR_CTRL_EXP9D_LDS_SD_THR_MASK                       0x1f00
#define BRPHY3_BR_CTRL_EXP9D_LDS_SD_THR_ALIGN                      0
#define BRPHY3_BR_CTRL_EXP9D_LDS_SD_THR_BITS                       5
#define BRPHY3_BR_CTRL_EXP9D_LDS_SD_THR_SHIFT                      8

/* BRPHY3_BR_CTRL :: EXP9D :: LDS_PEAK_THR_T125 [07:00] */
#define Wr_BRPHY3_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9D,0xff,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9D,0xff,0)
#define BRPHY3_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_MASK                0x00ff
#define BRPHY3_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_ALIGN               0
#define BRPHY3_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_BITS                8
#define BRPHY3_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_SHIFT               0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP9E
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP9E :: LDS_LEN_THR1_T125 [15:08] */
#define Wr_BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9E,0xff00,8,x)
#define Rd_BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9E,0xff00,8)
#define BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_MASK                0xff00
#define BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_ALIGN               0
#define BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_BITS                8
#define BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_SHIFT               8

/* BRPHY3_BR_CTRL :: EXP9E :: LDS_LEN_THR0_T125 [07:00] */
#define Wr_BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9E,0xff,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9E,0xff,0)
#define BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_MASK                0x00ff
#define BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_ALIGN               0
#define BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_BITS                8
#define BRPHY3_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_SHIFT               0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXP9F
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXP9F :: LDS_LEN_THR3_T125 [15:08] */
#define Wr_BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9F,0xff00,8,x)
#define Rd_BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9F,0xff00,8)
#define BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_MASK                0xff00
#define BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_ALIGN               0
#define BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_BITS                8
#define BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_SHIFT               8

/* BRPHY3_BR_CTRL :: EXP9F :: LDS_LEN_THR2_T125 [07:00] */
#define Wr_BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) WriteRegBits16(BRPHY3_BR_CTRL_EXP9F,0xff,0,x)
#define Rd_BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) ReadRegBits16(BRPHY3_BR_CTRL_EXP9F,0xff,0)
#define BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_MASK                0x00ff
#define BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_ALIGN               0
#define BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_BITS                8
#define BRPHY3_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_SHIFT               0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXPA0
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXPA0 :: EPAGE_SPARE [15:02] */
#define Wr_BRPHY3_BR_CTRL_EXPA0_EPAGE_SPARE(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA0,0xfffc,2,x)
#define Rd_BRPHY3_BR_CTRL_EXPA0_EPAGE_SPARE(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA0,0xfffc,2)
#define BRPHY3_BR_CTRL_EXPA0_EPAGE_SPARE_MASK                      0xfffc
#define BRPHY3_BR_CTRL_EXPA0_EPAGE_SPARE_ALIGN                     0
#define BRPHY3_BR_CTRL_EXPA0_EPAGE_SPARE_BITS                      14
#define BRPHY3_BR_CTRL_EXPA0_EPAGE_SPARE_SHIFT                     2

/* BRPHY3_BR_CTRL :: EXPA0 :: PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY3_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA0,0x2,1,x)
#define Rd_BRPHY3_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA0,0x2,1)
#define BRPHY3_BR_CTRL_EXPA0_PAIR_1_250MBPS_MASK                   0x0002
#define BRPHY3_BR_CTRL_EXPA0_PAIR_1_250MBPS_ALIGN                  0
#define BRPHY3_BR_CTRL_EXPA0_PAIR_1_250MBPS_BITS                   1
#define BRPHY3_BR_CTRL_EXPA0_PAIR_1_250MBPS_SHIFT                  1

/* BRPHY3_BR_CTRL :: EXPA0 :: PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY3_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA0,0x1,0,x)
#define Rd_BRPHY3_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA0,0x1,0)
#define BRPHY3_BR_CTRL_EXPA0_PAIR_1_200MBPS_MASK                   0x0001
#define BRPHY3_BR_CTRL_EXPA0_PAIR_1_200MBPS_ALIGN                  0
#define BRPHY3_BR_CTRL_EXPA0_PAIR_1_200MBPS_BITS                   1
#define BRPHY3_BR_CTRL_EXPA0_PAIR_1_200MBPS_SHIFT                  0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXPA1
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXPA1 :: LP_EPAGE_SPARE [15:02] */
#define Wr_BRPHY3_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA1,0xfffc,2,x)
#define Rd_BRPHY3_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA1,0xfffc,2)
#define BRPHY3_BR_CTRL_EXPA1_LP_EPAGE_SPARE_MASK                   0xfffc
#define BRPHY3_BR_CTRL_EXPA1_LP_EPAGE_SPARE_ALIGN                  0
#define BRPHY3_BR_CTRL_EXPA1_LP_EPAGE_SPARE_BITS                   14
#define BRPHY3_BR_CTRL_EXPA1_LP_EPAGE_SPARE_SHIFT                  2

/* BRPHY3_BR_CTRL :: EXPA1 :: LP_PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA1,0x2,1,x)
#define Rd_BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA1,0x2,1)
#define BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_MASK                0x0002
#define BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_ALIGN               0
#define BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_BITS                1
#define BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_SHIFT               1

/* BRPHY3_BR_CTRL :: EXPA1 :: LP_PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA1,0x1,0,x)
#define Rd_BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA1,0x1,0)
#define BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_MASK                0x0001
#define BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_ALIGN               0
#define BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_BITS                1
#define BRPHY3_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_SHIFT               0


/****************************************************************************
 * BRPHY3_BR_CTRL :: EXPA2
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV_EN [15:15] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0x8000,15,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0x8000,15)
#define BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_MASK                  0x8000
#define BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_ALIGN                 0
#define BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_BITS                  1
#define BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_SHIFT                 15

/* BRPHY3_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV [14:14] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0x4000,14,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0x4000,14)
#define BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_MASK                     0x4000
#define BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_ALIGN                    0
#define BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_BITS                     1
#define BRPHY3_BR_CTRL_EXPA2_TFREQ_SEL_OV_SHIFT                    14

/* BRPHY3_BR_CTRL :: EXPA2 :: LOW_FREQ_TONE [13:13] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0x2000,13,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0x2000,13)
#define BRPHY3_BR_CTRL_EXPA2_LOW_FREQ_TONE_MASK                    0x2000
#define BRPHY3_BR_CTRL_EXPA2_LOW_FREQ_TONE_ALIGN                   0
#define BRPHY3_BR_CTRL_EXPA2_LOW_FREQ_TONE_BITS                    1
#define BRPHY3_BR_CTRL_EXPA2_LOW_FREQ_TONE_SHIFT                   13

/* BRPHY3_BR_CTRL :: EXPA2 :: BR_MAXWAIT_CTL [12:11] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0x1800,11,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0x1800,11)
#define BRPHY3_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_MASK                   0x1800
#define BRPHY3_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_ALIGN                  0
#define BRPHY3_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_BITS                   2
#define BRPHY3_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_SHIFT                  11

/* BRPHY3_BR_CTRL :: EXPA2 :: BR_M2S2_TMR_CTL [10:10] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0x400,10,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0x400,10)
#define BRPHY3_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_MASK                  0x0400
#define BRPHY3_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_ALIGN                 0
#define BRPHY3_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_BITS                  1
#define BRPHY3_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_SHIFT                 10

/* BRPHY3_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_FDX_S [09:09] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0x200,9,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0x200,9)
#define BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_MASK               0x0200
#define BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_ALIGN              0
#define BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_BITS               1
#define BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_SHIFT              9

/* BRPHY3_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_HDX [08:08] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0x100,8,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0x100,8)
#define BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_MASK                 0x0100
#define BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_ALIGN                0
#define BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_BITS                 1
#define BRPHY3_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_SHIFT                8

/* BRPHY3_BR_CTRL :: EXPA2 :: BR_PSD_TIMER_CTL [07:06] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0xc0,6,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0xc0,6)
#define BRPHY3_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_MASK                 0x00c0
#define BRPHY3_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_ALIGN                0
#define BRPHY3_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_BITS                 2
#define BRPHY3_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_SHIFT                6

/* BRPHY3_BR_CTRL :: EXPA2 :: MAN_PHASE_CK1X [05:03] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0x38,3,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0x38,3)
#define BRPHY3_BR_CTRL_EXPA2_MAN_PHASE_CK1X_MASK                   0x0038
#define BRPHY3_BR_CTRL_EXPA2_MAN_PHASE_CK1X_ALIGN                  0
#define BRPHY3_BR_CTRL_EXPA2_MAN_PHASE_CK1X_BITS                   3
#define BRPHY3_BR_CTRL_EXPA2_MAN_PHASE_CK1X_SHIFT                  3

/* BRPHY3_BR_CTRL :: EXPA2 :: LDS_PHASE_CK1X [02:00] */
#define Wr_BRPHY3_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) WriteRegBits16(BRPHY3_BR_CTRL_EXPA2,0x7,0,x)
#define Rd_BRPHY3_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) ReadRegBits16(BRPHY3_BR_CTRL_EXPA2,0x7,0)
#define BRPHY3_BR_CTRL_EXPA2_LDS_PHASE_CK1X_MASK                   0x0007
#define BRPHY3_BR_CTRL_EXPA2_LDS_PHASE_CK1X_ALIGN                  0
#define BRPHY3_BR_CTRL_EXPA2_LDS_PHASE_CK1X_BITS                   3
#define BRPHY3_BR_CTRL_EXPA2_LDS_PHASE_CK1X_SHIFT                  0


/****************************************************************************
 * BRPHY3_BR_CTRL :: BR_MISC_CONTROL_STATUS
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_2ND_FILTER [15:15] */
#define Wr_BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) WriteRegBits16(BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15,x)
#define Rd_BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) ReadRegBits16(BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15)
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_MASK 0x8000
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_ALIGN 0
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_BITS 1
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_SHIFT 15

/* BRPHY3_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_PR_DATAPATH [14:14] */
#define Wr_BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) WriteRegBits16(BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14,x)
#define Rd_BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) ReadRegBits16(BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14)
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_MASK 0x4000
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_ALIGN 0
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_BITS 1
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_SHIFT 14

/* BRPHY3_BR_CTRL :: BR_MISC_CONTROL_STATUS :: reserved0 [13:03] */
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_MASK       0x3ff8
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_ALIGN      0
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_BITS       11
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_SHIFT      3

/* BRPHY3_BR_CTRL :: BR_MISC_CONTROL_STATUS :: BR_1P_PCS_SOL [02:00] */
#define Wr_BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) WriteRegBits16(BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0,x)
#define Rd_BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) ReadRegBits16(BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0)
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_MASK   0x0007
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_ALIGN  0
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_BITS   3
#define BRPHY3_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_SHIFT  0


/****************************************************************************
 * BRPHY3_BR_CTRL :: BR250_CTL
 ***************************************************************************/
/* BRPHY3_BR_CTRL :: BR250_CTL :: BR_CURR_RATE [15:12] */
#define Wr_BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) WriteRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0xf000,12,x)
#define Rd_BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) ReadRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0xf000,12)
#define BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_RATE_MASK                 0xf000
#define BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_RATE_ALIGN                0
#define BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_RATE_BITS                 4
#define BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_RATE_SHIFT                12

/* BRPHY3_BR_CTRL :: BR250_CTL :: BR_CURR_PAIR [11:10] */
#define Wr_BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) WriteRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0xc00,10,x)
#define Rd_BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) ReadRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0xc00,10)
#define BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_PAIR_MASK                 0x0c00
#define BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_PAIR_ALIGN                0
#define BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_PAIR_BITS                 2
#define BRPHY3_BR_CTRL_BR250_CTL_BR_CURR_PAIR_SHIFT                10

/* BRPHY3_BR_CTRL :: BR250_CTL :: reserved0 [09:08] */
#define BRPHY3_BR_CTRL_BR250_CTL_RESERVED0_MASK                    0x0300
#define BRPHY3_BR_CTRL_BR250_CTL_RESERVED0_ALIGN                   0
#define BRPHY3_BR_CTRL_BR250_CTL_RESERVED0_BITS                    2
#define BRPHY3_BR_CTRL_BR250_CTL_RESERVED0_SHIFT                   8

/* BRPHY3_BR_CTRL :: BR250_CTL :: BR_PAM5_200_sel [07:07] */
#define Wr_BRPHY3_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) WriteRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0x80,7,x)
#define Rd_BRPHY3_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) ReadRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0x80,7)
#define BRPHY3_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_MASK              0x0080
#define BRPHY3_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_ALIGN             0
#define BRPHY3_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_BITS              1
#define BRPHY3_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_SHIFT             7

/* BRPHY3_BR_CTRL :: BR250_CTL :: LBKTst2 [06:06] */
#define Wr_BRPHY3_BR_CTRL_BR250_CTL_LBKTst2(x) WriteRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0x40,6,x)
#define Rd_BRPHY3_BR_CTRL_BR250_CTL_LBKTst2(x) ReadRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0x40,6)
#define BRPHY3_BR_CTRL_BR250_CTL_LBKTST2_MASK                      0x0040
#define BRPHY3_BR_CTRL_BR250_CTL_LBKTST2_ALIGN                     0
#define BRPHY3_BR_CTRL_BR250_CTL_LBKTST2_BITS                      1
#define BRPHY3_BR_CTRL_BR250_CTL_LBKTST2_SHIFT                     6

/* BRPHY3_BR_CTRL :: BR250_CTL :: CONF_GPLL_125 [05:05] */
#define Wr_BRPHY3_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) WriteRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0x20,5,x)
#define Rd_BRPHY3_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) ReadRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0x20,5)
#define BRPHY3_BR_CTRL_BR250_CTL_CONF_GPLL_125_MASK                0x0020
#define BRPHY3_BR_CTRL_BR250_CTL_CONF_GPLL_125_ALIGN               0
#define BRPHY3_BR_CTRL_BR250_CTL_CONF_GPLL_125_BITS                1
#define BRPHY3_BR_CTRL_BR250_CTL_CONF_GPLL_125_SHIFT               5

/* BRPHY3_BR_CTRL :: BR250_CTL :: reserved1 [04:04] */
#define BRPHY3_BR_CTRL_BR250_CTL_RESERVED1_MASK                    0x0010
#define BRPHY3_BR_CTRL_BR250_CTL_RESERVED1_ALIGN                   0
#define BRPHY3_BR_CTRL_BR250_CTL_RESERVED1_BITS                    1
#define BRPHY3_BR_CTRL_BR250_CTL_RESERVED1_SHIFT                   4

/* BRPHY3_BR_CTRL :: BR250_CTL :: INTRLV_CTL [03:02] */
#define Wr_BRPHY3_BR_CTRL_BR250_CTL_INTRLV_CTL(x) WriteRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0xc,2,x)
#define Rd_BRPHY3_BR_CTRL_BR250_CTL_INTRLV_CTL(x) ReadRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0xc,2)
#define BRPHY3_BR_CTRL_BR250_CTL_INTRLV_CTL_MASK                   0x000c
#define BRPHY3_BR_CTRL_BR250_CTL_INTRLV_CTL_ALIGN                  0
#define BRPHY3_BR_CTRL_BR250_CTL_INTRLV_CTL_BITS                   2
#define BRPHY3_BR_CTRL_BR250_CTL_INTRLV_CTL_SHIFT                  2

/* BRPHY3_BR_CTRL :: BR250_CTL :: PAIR_CFG [01:00] */
#define Wr_BRPHY3_BR_CTRL_BR250_CTL_PAIR_CFG(x) WriteRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0x3,0,x)
#define Rd_BRPHY3_BR_CTRL_BR250_CTL_PAIR_CFG(x) ReadRegBits16(BRPHY3_BR_CTRL_BR250_CTL,0x3,0)
#define BRPHY3_BR_CTRL_BR250_CTL_PAIR_CFG_MASK                     0x0003
#define BRPHY3_BR_CTRL_BR250_CTL_PAIR_CFG_ALIGN                    0
#define BRPHY3_BR_CTRL_BR250_CTL_PAIR_CFG_BITS                     2
#define BRPHY3_BR_CTRL_BR250_CTL_PAIR_CFG_SHIFT                    0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys3_BRPHY3_BR_CL22_IEEE
 ***************************************************************************/
/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: MII_CTRL
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: RESET [15:15] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_RESET(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x8000,15,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_RESET(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x8000,15)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESET_MASK                    0x8000
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESET_ALIGN                   0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESET_BITS                    1
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESET_SHIFT                   15

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: LOOPBACK [14:14] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x4000,14,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x4000,14)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_LOOPBACK_MASK                 0x4000
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_LOOPBACK_ALIGN                0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_LOOPBACK_BITS                 1
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_LOOPBACK_SHIFT                14

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: RESTART_LDS [13:13] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x2000,13,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x2000,13)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_MASK              0x2000
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_ALIGN             0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_BITS              1
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_SHIFT             13

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: LDS_ENABLE [12:12] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x1000,12,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x1000,12)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_MASK               0x1000
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_ALIGN              0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_BITS               1
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_SHIFT              12

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: POWER_DOWN [11:11] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x800,11,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x800,11)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_MASK               0x0800
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_ALIGN              0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_BITS               1
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_SHIFT              11

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: ISOLATE [10:10] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x400,10,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x400,10)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_ISOLATE_MASK                  0x0400
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_ISOLATE_ALIGN                 0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_ISOLATE_BITS                  1
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_ISOLATE_SHIFT                 10

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: manual_speed_select_enable [09:09] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x200,9,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x200,9)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_MASK 0x0200
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_BITS 1
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_SHIFT 9

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: Speed_Selection [08:06] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x1c0,6,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x1c0,6)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_MASK          0x01c0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_ALIGN         0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_BITS          3
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_SHIFT         6

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: Pair_Selection [05:04] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x30,4,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x30,4)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_MASK           0x0030
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_ALIGN          0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_BITS           2
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_SHIFT          4

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: Master_mode [03:03] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_Master_mode(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x8,3,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_Master_mode(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x8,3)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_MASK              0x0008
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_ALIGN             0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_BITS              1
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_SHIFT             3

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: Unidirection_Enable [02:02] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x4,2,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_CTRL,0x4,2)
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_MASK      0x0004
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_ALIGN     0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_BITS      1
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_SHIFT     2

/* BRPHY3_BR_CL22_IEEE :: MII_CTRL :: reserved0 [01:00] */
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESERVED0_MASK                0x0003
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESERVED0_ALIGN               0
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESERVED0_BITS                2
#define BRPHY3_BR_CL22_IEEE_MII_CTRL_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: MII_STAT
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: MII_STAT :: reserved0 [15:15] */
#define BRPHY3_BR_CL22_IEEE_MII_STAT_RESERVED0_MASK                0x8000
#define BRPHY3_BR_CL22_IEEE_MII_STAT_RESERVED0_ALIGN               0
#define BRPHY3_BR_CL22_IEEE_MII_STAT_RESERVED0_BITS                1
#define BRPHY3_BR_CL22_IEEE_MII_STAT_RESERVED0_SHIFT               15

/* BRPHY3_BR_CL22_IEEE :: MII_STAT :: Capability [14:09] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_STAT_Capability(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x7e00,9,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_STAT_Capability(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x7e00,9)
#define BRPHY3_BR_CL22_IEEE_MII_STAT_CAPABILITY_MASK               0x7e00
#define BRPHY3_BR_CL22_IEEE_MII_STAT_CAPABILITY_ALIGN              0
#define BRPHY3_BR_CL22_IEEE_MII_STAT_CAPABILITY_BITS               6
#define BRPHY3_BR_CL22_IEEE_MII_STAT_CAPABILITY_SHIFT              9

/* BRPHY3_BR_CL22_IEEE :: MII_STAT :: EXTENDED_STAT [08:06] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x1c0,6,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x1c0,6)
#define BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_MASK            0x01c0
#define BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_ALIGN           0
#define BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_BITS            3
#define BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_SHIFT           6

/* BRPHY3_BR_CL22_IEEE :: MII_STAT :: LDS_complete [05:05] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_STAT_LDS_complete(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x20,5,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_STAT_LDS_complete(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x20,5)
#define BRPHY3_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_MASK             0x0020
#define BRPHY3_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_ALIGN            0
#define BRPHY3_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_BITS             1
#define BRPHY3_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_SHIFT            5

/* BRPHY3_BR_CL22_IEEE :: MII_STAT :: reserved1 [04:03] */
#define BRPHY3_BR_CL22_IEEE_MII_STAT_RESERVED1_MASK                0x0018
#define BRPHY3_BR_CL22_IEEE_MII_STAT_RESERVED1_ALIGN               0
#define BRPHY3_BR_CL22_IEEE_MII_STAT_RESERVED1_BITS                2
#define BRPHY3_BR_CL22_IEEE_MII_STAT_RESERVED1_SHIFT               3

/* BRPHY3_BR_CL22_IEEE :: MII_STAT :: LNK_STAT [02:02] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x4,2,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x4,2)
#define BRPHY3_BR_CL22_IEEE_MII_STAT_LNK_STAT_MASK                 0x0004
#define BRPHY3_BR_CL22_IEEE_MII_STAT_LNK_STAT_ALIGN                0
#define BRPHY3_BR_CL22_IEEE_MII_STAT_LNK_STAT_BITS                 1
#define BRPHY3_BR_CL22_IEEE_MII_STAT_LNK_STAT_SHIFT                2

/* BRPHY3_BR_CL22_IEEE :: MII_STAT :: JABBER_DETECT [01:01] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x2,1,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x2,1)
#define BRPHY3_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_MASK            0x0002
#define BRPHY3_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_ALIGN           0
#define BRPHY3_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_BITS            1
#define BRPHY3_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_SHIFT           1

/* BRPHY3_BR_CL22_IEEE :: MII_STAT :: EXTENDED_CAPABILITY [00:00] */
#define Wr_BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x1,0,x)
#define Rd_BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_MII_STAT,0x1,0)
#define BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_MASK      0x0001
#define BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_ALIGN     0
#define BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_BITS      1
#define BRPHY3_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_SHIFT     0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: PHY_ID_MSB
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: PHY_ID_MSB :: OUI_MSB [15:00] */
#define Wr_BRPHY3_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) WriteReg16(BRPHY3_BR_CL22_IEEE_PHY_ID_MSB,x)
#define Rd_BRPHY3_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) ReadReg16(BRPHY3_BR_CL22_IEEE_PHY_ID_MSB)
#define BRPHY3_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_MASK                0xffff
#define BRPHY3_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_ALIGN               0
#define BRPHY3_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_BITS                16
#define BRPHY3_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_SHIFT               0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: PHY_ID_LSB
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: PHY_ID_LSB :: OUI_LSB [15:10] */
#define Wr_BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10,x)
#define Rd_BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10)
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_MASK                0xfc00
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_ALIGN               0
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_BITS                6
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_SHIFT               10

/* BRPHY3_BR_CL22_IEEE :: PHY_ID_LSB :: MODEL [09:04] */
#define Wr_BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4,x)
#define Rd_BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4)
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_MODEL_MASK                  0x03f0
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_MODEL_ALIGN                 0
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_MODEL_BITS                  6
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_MODEL_SHIFT                 4

/* BRPHY3_BR_CL22_IEEE :: PHY_ID_LSB :: REVISION [03:00] */
#define Wr_BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_PHY_ID_LSB,0xf,0,x)
#define Rd_BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_PHY_ID_LSB,0xf,0)
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_REVISION_MASK               0x000f
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_REVISION_ALIGN              0
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_REVISION_BITS               4
#define BRPHY3_BR_CL22_IEEE_PHY_ID_LSB_REVISION_SHIFT              0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved0 [13:06] */
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_MASK      0x3fc0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_ALIGN     0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_BITS      8
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_SHIFT     6

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_MASK   0x0020
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_ALIGN  0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_BITS   1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_SHIFT  5

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved1 [00:00] */
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_MASK      0x0001
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_ALIGN     0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_BITS      1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_SHIFT     0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: LDS_Adv_Control
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Control :: Test_Mode [15:13] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_MASK         0xe000
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_ALIGN        0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_BITS         3
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_SHIFT        13

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Control :: reserved0 [12:10] */
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_MASK         0x1c00
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_ALIGN        0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_BITS         3
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_SHIFT        10

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Control :: Port_Type [09:09] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_MASK         0x0200
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_ALIGN        0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_BITS         1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_SHIFT        9

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Control :: Abilities_Field_Update [08:08] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_MASK 0x0100
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_SHIFT 8

/* BRPHY3_BR_CL22_IEEE :: LDS_Adv_Control :: Local_Field_Number [07:00] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0)
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_MASK 0x00ff
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_BITS 8
#define BRPHY3_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: LDS_Ability
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: LDS_Ability :: LDS_Ability [15:00] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) WriteReg16(BRPHY3_BR_CL22_IEEE_LDS_ABILITY,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) ReadReg16(BRPHY3_BR_CL22_IEEE_LDS_ABILITY)
#define BRPHY3_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_MASK           0xffff
#define BRPHY3_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_ALIGN          0
#define BRPHY3_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_BITS           16
#define BRPHY3_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_SHIFT          0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved0 [13:06] */
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_MASK       0x3fc0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_ALIGN      0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_BITS       8
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_SHIFT      6

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_MASK    0x0020
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_ALIGN   0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_BITS    1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_SHIFT   5

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved1 [00:00] */
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_MASK       0x0001
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_ALIGN      0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_BITS       1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_SHIFT      0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: LDS_LP_MSG_NxtP
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: LDS_LP_MSG_NxtP :: Link_Partner_Nxt_Pg_Msg [15:00] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) WriteReg16(BRPHY3_BR_CL22_IEEE_LDS_LP_MSG_NXTP,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) ReadReg16(BRPHY3_BR_CL22_IEEE_LDS_LP_MSG_NXTP)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_MASK 0xffff
#define BRPHY3_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_BITS 16
#define BRPHY3_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_SHIFT 0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_NxtP
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: NextPage_Read_Flag [15:15] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_MASK 0x8000
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_BITS 1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_SHIFT 15

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: reserved0 [14:09] */
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_MASK     0x7e00
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_ALIGN    0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_BITS     6
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_SHIFT    9

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_ACQ [08:08] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_MASK    0x0100
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_ALIGN   0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_BITS    1
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_SHIFT   8

/* BRPHY3_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_Field_Number [07:00] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0)
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_MASK 0x00ff
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_BITS 8
#define BRPHY3_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: LDS_LDS_EXP
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: LDS_LDS_EXP :: Downgrade_Ability [15:15] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15)
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_MASK     0x8000
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_ALIGN    0
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_BITS     1
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_SHIFT    15

/* BRPHY3_BR_CL22_IEEE :: LDS_LDS_EXP :: Master_Slave [14:14] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14)
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_MASK          0x4000
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_ALIGN         0
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_BITS          1
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_SHIFT         14

/* BRPHY3_BR_CL22_IEEE :: LDS_LDS_EXP :: Pair_Number [13:12] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12)
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_MASK           0x3000
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_ALIGN          0
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_BITS           2
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_SHIFT          12

/* BRPHY3_BR_CL22_IEEE :: LDS_LDS_EXP :: Estimated_Wire_Length [11:00] */
#define Wr_BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0)
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_MASK 0x0fff
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_BITS 12
#define BRPHY3_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_SHIFT 0


/****************************************************************************
 * BRPHY3_BR_CL22_IEEE :: LRE_EXTENDED_STAT
 ***************************************************************************/
/* BRPHY3_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: reserved0 [15:10] */
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_MASK       0xfc00
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_ALIGN      0
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_BITS       6
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_SHIFT      10

/* BRPHY3_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: LOCAL_RECEIVE_STATUS [09:09] */
#define Wr_BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9)
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_MASK 0x0200
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_SHIFT 9

/* BRPHY3_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: REMOTE_RECEIVE_STATUS [08:08] */
#define Wr_BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8)
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_MASK 0x0100
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_BITS 1
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_SHIFT 8

/* BRPHY3_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: IDLE_ERROR_CNTR [07:00] */
#define Wr_BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) WriteRegBits16(BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0,x)
#define Rd_BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) ReadRegBits16(BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0)
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_MASK 0x00ff
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_ALIGN 0
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_BITS 8
#define BRPHY3_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_CL45DEV1
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x8000,15)
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESET_BITS                   1
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved0 [14:14] */
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_MASK               0x4000
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED0_SHIFT              14

/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x2000,13)
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved1 [12:12] */
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_MASK               0x1000
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_BITS               1
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED1_SHIFT              12

/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x800,11)
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved2 [10:07] */
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_MASK               0x0780
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_BITS               4
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED2_SHIFT              7

/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x40,6)
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x3c,2)
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: reserved3 [01:01] */
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_MASK               0x0002
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_BITS               1
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_RESERVED3_SHIFT              1

/* BRPHY4_CL45DEV1 :: PMD_IEEE_CTL1 :: LPBK [00:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x1,0,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LPBK(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_CTL1,0x1,0)
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LPBK_MASK                    0x0001
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LPBK_ALIGN                   0
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LPBK_BITS                    1
#define BRPHY4_CL45DEV1_PMD_IEEE_CTL1_LPBK_SHIFT                   0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_ST1
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY4_CL45DEV1 :: PMD_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_ST1,0x80,7)
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_FAULT_BITS                    1
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY4_CL45DEV1 :: PMD_IEEE_ST1 :: reserved1 [06:03] */
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED1_MASK                0x0078
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED1_BITS                4
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY4_CL45DEV1 :: PMD_IEEE_ST1 :: RCV_LINK_ST [02:02] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_ST1,0x4,2)
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_MASK              0x0004
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_ALIGN             0
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_BITS              1
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RCV_LINK_ST_SHIFT             2

/* BRPHY4_CL45DEV1 :: PMD_IEEE_ST1 :: CAP_LOW_PWR [01:01] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_ST1,0x2,1)
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_MASK              0x0002
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_ALIGN             0
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_BITS              1
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_CAP_LOW_PWR_SHIFT             1

/* BRPHY4_CL45DEV1 :: PMD_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY4_CL45DEV1_PMD_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID0,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID0)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1,0xf,0)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x80,7)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x40,6)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x20,5)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x10,4)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x8,3)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x4,2)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x2,1)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV0,0x1,0)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_DEV1
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV1,0x8000,15)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV1,0x4000,14)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_DEV1,0x2000,13)
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY4_CL45DEV1 :: PMD_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY4_CL45DEV1_PMD_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID0,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID0)
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID1,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID1)
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY4_CL45DEV1_PMD_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY4_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: TX_PMD_TSYNC_EN [01:01] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_MASK    0x0002
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_BITS    1
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_TX_PMD_TSYNC_EN_SHIFT   1

/* BRPHY4_CL45DEV1 :: PMD_IEEE_TSYNC_CAP :: RX_PMD_TSYNC_EN [00:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) WriteRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN(x) ReadRegBits16(BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_MASK    0x0001
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_ALIGN   0
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_BITS    1
#define BRPHY4_CL45DEV1_PMD_IEEE_TSYNC_CAP_RX_PMD_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY4_CL45DEV1_PMD_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PMD_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_MASK 0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_ALIGN 0
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_BITS 16
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PMD_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PMD_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_MASK 0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_ALIGN 0
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_BITS 16
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PMD_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PMD_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_MASK 0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_ALIGN 0
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_BITS 16
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PMD_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY4_CL45DEV1 :: PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PMD_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) WriteReg16(BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16(x) ReadReg16(BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_MASK 0xffff
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_ALIGN 0
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_BITS 16
#define BRPHY4_CL45DEV1_PMD_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PMD_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_CL45DEV3
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1 :: RESET [15:15] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESET(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESET(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x8000,15)
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESET_MASK                   0x8000
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESET_ALIGN                  0
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESET_BITS                   1
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESET_SHIFT                  15

/* BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1 :: PCS_LPBK [14:14] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x4000,14,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x4000,14)
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_MASK                0x4000
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_ALIGN               0
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_BITS                1
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_PCS_LPBK_SHIFT               14

/* BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_1 [13:13] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x2000,13)
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_MASK             0x2000
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_ALIGN            0
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_BITS             1
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_1_SHIFT            13

/* BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved0 [12:12] */
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_MASK               0x1000
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_BITS               1
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED0_SHIFT              12

/* BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1 :: LOW_PWR [11:11] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x800,11,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x800,11)
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_MASK                 0x0800
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_ALIGN                0
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_BITS                 1
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_LOW_PWR_SHIFT                11

/* BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved1 [10:07] */
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_MASK               0x0780
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_BITS               4
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED1_SHIFT              7

/* BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_0 [06:06] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x40,6,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x40,6)
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_MASK             0x0040
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_ALIGN            0
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_BITS             1
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_0_SHIFT            6

/* BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1 :: SPEED_SEL_10G [05:02] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x3c,2,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_CTL1,0x3c,2)
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_MASK           0x003c
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_ALIGN          0
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_BITS           4
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_SPEED_SEL_10G_SHIFT          2

/* BRPHY4_CL45DEV3 :: PCS_IEEE_CTL1 :: reserved2 [01:00] */
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_MASK               0x0003
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_BITS               2
#define BRPHY4_CL45DEV3_PCS_IEEE_CTL1_RESERVED2_SHIFT              0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_ST1
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_ST1 :: reserved0 [15:08] */
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED0_MASK                0xff00
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED0_ALIGN               0
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED0_BITS                8
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED0_SHIFT               8

/* BRPHY4_CL45DEV3 :: PCS_IEEE_ST1 :: FAULT [07:07] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_ST1_FAULT(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_ST1,0x80,7,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_ST1_FAULT(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_ST1,0x80,7)
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_FAULT_MASK                    0x0080
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_FAULT_ALIGN                   0
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_FAULT_BITS                    1
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_FAULT_SHIFT                   7

/* BRPHY4_CL45DEV3 :: PCS_IEEE_ST1 :: CLOCK_STOP_CAPABLE [06:06] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_ST1,0x40,6,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_ST1,0x40,6)
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_MASK       0x0040
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_ALIGN      0
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_BITS       1
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_CLOCK_STOP_CAPABLE_SHIFT      6

/* BRPHY4_CL45DEV3 :: PCS_IEEE_ST1 :: reserved1 [05:03] */
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED1_MASK                0x0038
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED1_ALIGN               0
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED1_BITS                3
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED1_SHIFT               3

/* BRPHY4_CL45DEV3 :: PCS_IEEE_ST1 :: PCS_RCV_LINK_ST [02:02] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_ST1,0x4,2,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_ST1,0x4,2)
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_MASK          0x0004
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_ALIGN         0
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_BITS          1
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_PCS_RCV_LINK_ST_SHIFT         2

/* BRPHY4_CL45DEV3 :: PCS_IEEE_ST1 :: LOW_PWR_AB [01:01] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_ST1,0x2,1,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_ST1,0x2,1)
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_MASK               0x0002
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_BITS               1
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_LOW_PWR_AB_SHIFT              1

/* BRPHY4_CL45DEV3 :: PCS_IEEE_ST1 :: reserved2 [00:00] */
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED2_MASK                0x0001
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED2_ALIGN               0
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED2_BITS                1
#define BRPHY4_CL45DEV3_PCS_IEEE_ST1_RESERVED2_SHIFT               0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_DEV_ID0
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV_ID0 :: DEV_ID0 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID0,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID0)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_MASK              0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_ALIGN             0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_BITS              16
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID0_DEV_ID0_SHIFT             0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_DEV_ID1
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: DEV_ID1 [15:10] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1,0xfc00,10)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_MASK              0xfc00
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_ALIGN             0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_BITS              6
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_DEV_ID1_SHIFT             10

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: MODEL_NU [09:04] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1,0x3f0,4)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_MASK             0x03f0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_ALIGN            0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_BITS             6
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_MODEL_NU_SHIFT            4

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV_ID1 :: REV_NU [03:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1,0xf,0)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_MASK               0x000f
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_BITS               4
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV_ID1_REV_NU_SHIFT              0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0 :: reserved0 [15:08] */
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_MASK               0xff00
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_BITS               8
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_RESERVED0_SHIFT              8

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0 :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x80,7,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x80,7)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_MASK             0x0080
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_ALIGN            0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_BITS             1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_AUTONEG_PRE_SHIFT            7

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0 :: TC_PRE [06:06] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x40,6,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_TC_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x40,6)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_MASK                  0x0040
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_ALIGN                 0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_BITS                  1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_TC_PRE_SHIFT                 6

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0 :: DTEXS_PRE [05:05] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x20,5,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x20,5)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_MASK               0x0020
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_BITS               1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_DTEXS_PRE_SHIFT              5

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0 :: PHYXS_PRE [04:04] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x10,4,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x10,4)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_MASK               0x0010
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_BITS               1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PHYXS_PRE_SHIFT              4

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0 :: PCS_PRE [03:03] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x8,3,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x8,3)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_MASK                 0x0008
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_ALIGN                0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_BITS                 1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PCS_PRE_SHIFT                3

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0 :: WIS_PRE [02:02] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x4,2,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x4,2)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_MASK                 0x0004
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_ALIGN                0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_BITS                 1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_WIS_PRE_SHIFT                2

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0 :: PMD_PRE [01:01] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x2,1,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x2,1)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_MASK                 0x0002
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_ALIGN                0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_BITS                 1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_PMD_PRE_SHIFT                1

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV0 :: CLA22_PRE [00:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x1,0,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV0,0x1,0)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_MASK               0x0001
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_BITS               1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV0_CLA22_PRE_SHIFT              0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_DEV1
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV1,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV1,0x8000,15)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_MASK          0x8000
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_ALIGN         0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_BITS          1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV2_PRE_SHIFT         15

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV1 :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV1,0x4000,14,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV1,0x4000,14)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_MASK          0x4000
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_ALIGN         0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_BITS          1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_VENSP_DEV1_PRE_SHIFT         14

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV1 :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV1,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_DEV1,0x2000,13)
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_MASK           0x2000
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_ALIGN          0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_BITS           1
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_CLA22_EXT_PRE_SHIFT          13

/* BRPHY4_CL45DEV3 :: PCS_IEEE_DEV1 :: reserved0 [12:00] */
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_MASK               0x1fff
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_ALIGN              0
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_BITS               13
#define BRPHY4_CL45DEV3_PCS_IEEE_DEV1_RESERVED0_SHIFT              0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_PKG_ID0
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_PKG_ID0 :: PKG_ID_0 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID0,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID0)
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_MASK             0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_ALIGN            0
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_BITS             16
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID0_PKG_ID_0_SHIFT            0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_PKG_ID1
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_PKG_ID1 :: PKG_ID_1 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID1,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID1)
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_MASK             0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_ALIGN            0
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_BITS             16
#define BRPHY4_CL45DEV3_PCS_IEEE_PKG_ID1_PKG_ID_1_SHIFT            0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_EEE_CAP
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_EEE_CAP :: reserved0 [15:07] */
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_RESERVED0_MASK                 0xff80
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_RESERVED0_ALIGN                0
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_RESERVED0_BITS                 9
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_RESERVED0_SHIFT                7

/* BRPHY4_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKR_EEE [06:06] */
#define Wr_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x40,6,x)
#define Rd_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x40,6)
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_MASK         0x0040
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_ALIGN        0
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_BITS         1
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKR_EEE_SHIFT        6

/* BRPHY4_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASEKX4_EEE [05:05] */
#define Wr_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x20,5,x)
#define Rd_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x20,5)
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_MASK        0x0020
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_ALIGN       0
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_BITS        1
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASEKX4_EEE_SHIFT       5

/* BRPHY4_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASEKX_EEE [04:04] */
#define Wr_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x10,4,x)
#define Rd_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x10,4)
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_MASK        0x0010
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_ALIGN       0
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_BITS        1
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASEKX_EEE_SHIFT       4

/* BRPHY4_CL45DEV3 :: PCS_EEE_CAP :: PHY_10GBASET_EEE [03:03] */
#define Wr_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x8,3,x)
#define Rd_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x8,3)
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_MASK          0x0008
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_ALIGN         0
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_BITS          1
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_10GBASET_EEE_SHIFT         3

/* BRPHY4_CL45DEV3 :: PCS_EEE_CAP :: PHY_1000BASET_EEE [02:02] */
#define Wr_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x4,2,x)
#define Rd_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x4,2)
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_MASK         0x0004
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_ALIGN        0
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_BITS         1
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_1000BASET_EEE_SHIFT        2

/* BRPHY4_CL45DEV3 :: PCS_EEE_CAP :: PHY_100BASETX_EEE [01:01] */
#define Wr_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x2,1,x)
#define Rd_BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_EEE_CAP,0x2,1)
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_MASK         0x0002
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_ALIGN        0
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_BITS         1
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_PHY_100BASETX_EEE_SHIFT        1

/* BRPHY4_CL45DEV3 :: PCS_EEE_CAP :: reserved1 [00:00] */
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_RESERVED1_MASK                 0x0001
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_RESERVED1_ALIGN                0
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_RESERVED1_BITS                 1
#define BRPHY4_CL45DEV3_PCS_EEE_CAP_RESERVED1_SHIFT                0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_EEE_Wake_Err_Cnt :: cnt [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) WriteReg16(BRPHY4_CL45DEV3_PCS_EEE_WAKE_ERR_CNT,x)
#define Rd_BRPHY4_CL45DEV3_PCS_EEE_Wake_Err_Cnt_cnt(x) ReadReg16(BRPHY4_CL45DEV3_PCS_EEE_WAKE_ERR_CNT)
#define BRPHY4_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_MASK              0xffff
#define BRPHY4_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_ALIGN             0
#define BRPHY4_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_BITS              16
#define BRPHY4_CL45DEV3_PCS_EEE_WAKE_ERR_CNT_CNT_SHIFT             0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_TSYNC_CAP
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: reserved0 [15:02] */
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_MASK          0xfffc
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_ALIGN         0
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_BITS          14
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RESERVED0_SHIFT         2

/* BRPHY4_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: TX_PCS_TSYNC_EN [01:01] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x2,1)
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_MASK    0x0002
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_BITS    1
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_TX_PCS_TSYNC_EN_SHIFT   1

/* BRPHY4_CL45DEV3 :: PCS_IEEE_TSYNC_CAP :: RX_PCS_TSYNC_EN [00:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) WriteRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN(x) ReadRegBits16(BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP,0x1,0)
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_MASK    0x0001
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_ALIGN   0
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_BITS    1
#define BRPHY4_CL45DEV3_PCS_IEEE_TSYNC_CAP_RX_PCS_TSYNC_EN_SHIFT   0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER :: TX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_LOWER_TX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER :: TX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MAX_DELAY_UPPER_TX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER :: TX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_LOWER_TX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER :: TX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY4_CL45DEV3_PCS_IEEE_TX_TSYNC_MIN_DELAY_UPPER_TX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER :: RX_PCS_MAX_DLY_15_0 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER)
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_MASK 0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_ALIGN 0
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_BITS 16
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_LOWER_RX_PCS_MAX_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER :: RX_PCS_MAX_DLY_31_16 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER)
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_MASK 0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_ALIGN 0
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_BITS 16
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MAX_DELAY_UPPER_RX_PCS_MAX_DLY_31_16_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER :: RX_PCS_MIN_DLY_15_0 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER)
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_MASK 0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_ALIGN 0
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_BITS 16
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_LOWER_RX_PCS_MIN_DLY_15_0_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER
 ***************************************************************************/
/* BRPHY4_CL45DEV3 :: PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER :: RX_PCS_MIN_DLY_31_16 [15:00] */
#define Wr_BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) WriteReg16(BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER,x)
#define Rd_BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16(x) ReadReg16(BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER)
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_MASK 0xffff
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_ALIGN 0
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_BITS 16
#define BRPHY4_CL45DEV3_PCS_IEEE_RX_TSYNC_MIN_DELAY_UPPER_RX_PCS_MIN_DLY_31_16_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_CL45DEV7
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_CTRL
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_CTRL :: AN_reset [15:15] */
#define Wr_BRPHY4_CL45DEV7_AN_CTRL_AN_reset(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV7_AN_CTRL_AN_reset(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_CTRL,0x8000,15)
#define BRPHY4_CL45DEV7_AN_CTRL_AN_RESET_MASK                      0x8000
#define BRPHY4_CL45DEV7_AN_CTRL_AN_RESET_ALIGN                     0
#define BRPHY4_CL45DEV7_AN_CTRL_AN_RESET_BITS                      1
#define BRPHY4_CL45DEV7_AN_CTRL_AN_RESET_SHIFT                     15

/* BRPHY4_CL45DEV7 :: AN_CTRL :: reserved0 [14:14] */
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED0_MASK                     0x4000
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED0_ALIGN                    0
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED0_BITS                     1
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED0_SHIFT                    14

/* BRPHY4_CL45DEV7 :: AN_CTRL :: Extended_next_page_control [13:13] */
#define Wr_BRPHY4_CL45DEV7_AN_CTRL_Extended_next_page_control(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV7_AN_CTRL_Extended_next_page_control(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_CTRL,0x2000,13)
#define BRPHY4_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_MASK    0x2000
#define BRPHY4_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_ALIGN   0
#define BRPHY4_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_BITS    1
#define BRPHY4_CL45DEV7_AN_CTRL_EXTENDED_NEXT_PAGE_CONTROL_SHIFT   13

/* BRPHY4_CL45DEV7 :: AN_CTRL :: Auto_Negotiation_enable [12:12] */
#define Wr_BRPHY4_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY4_CL45DEV7_AN_CTRL_Auto_Negotiation_enable(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_CTRL,0x1000,12)
#define BRPHY4_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_MASK       0x1000
#define BRPHY4_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_ALIGN      0
#define BRPHY4_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_BITS       1
#define BRPHY4_CL45DEV7_AN_CTRL_AUTO_NEGOTIATION_ENABLE_SHIFT      12

/* BRPHY4_CL45DEV7 :: AN_CTRL :: reserved1 [11:10] */
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED1_MASK                     0x0c00
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED1_ALIGN                    0
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED1_BITS                     2
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED1_SHIFT                    10

/* BRPHY4_CL45DEV7 :: AN_CTRL :: Restart_Auto_Negotiation [09:09] */
#define Wr_BRPHY4_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_CTRL,0x200,9,x)
#define Rd_BRPHY4_CL45DEV7_AN_CTRL_Restart_Auto_Negotiation(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_CTRL,0x200,9)
#define BRPHY4_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_MASK      0x0200
#define BRPHY4_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_ALIGN     0
#define BRPHY4_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_BITS      1
#define BRPHY4_CL45DEV7_AN_CTRL_RESTART_AUTO_NEGOTIATION_SHIFT     9

/* BRPHY4_CL45DEV7 :: AN_CTRL :: reserved2 [08:00] */
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED2_MASK                     0x01ff
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED2_ALIGN                    0
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED2_BITS                     9
#define BRPHY4_CL45DEV7_AN_CTRL_RESERVED2_SHIFT                    0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_STAT
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_STAT :: reserved0 [15:08] */
#define BRPHY4_CL45DEV7_AN_STAT_RESERVED0_MASK                     0xff00
#define BRPHY4_CL45DEV7_AN_STAT_RESERVED0_ALIGN                    0
#define BRPHY4_CL45DEV7_AN_STAT_RESERVED0_BITS                     8
#define BRPHY4_CL45DEV7_AN_STAT_RESERVED0_SHIFT                    8

/* BRPHY4_CL45DEV7 :: AN_STAT :: Extended_next_page_status [07:07] */
#define Wr_BRPHY4_CL45DEV7_AN_STAT_Extended_next_page_status(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x80,7,x)
#define Rd_BRPHY4_CL45DEV7_AN_STAT_Extended_next_page_status(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x80,7)
#define BRPHY4_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_MASK     0x0080
#define BRPHY4_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_ALIGN    0
#define BRPHY4_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_BITS     1
#define BRPHY4_CL45DEV7_AN_STAT_EXTENDED_NEXT_PAGE_STATUS_SHIFT    7

/* BRPHY4_CL45DEV7 :: AN_STAT :: Page_received [06:06] */
#define Wr_BRPHY4_CL45DEV7_AN_STAT_Page_received(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x40,6,x)
#define Rd_BRPHY4_CL45DEV7_AN_STAT_Page_received(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x40,6)
#define BRPHY4_CL45DEV7_AN_STAT_PAGE_RECEIVED_MASK                 0x0040
#define BRPHY4_CL45DEV7_AN_STAT_PAGE_RECEIVED_ALIGN                0
#define BRPHY4_CL45DEV7_AN_STAT_PAGE_RECEIVED_BITS                 1
#define BRPHY4_CL45DEV7_AN_STAT_PAGE_RECEIVED_SHIFT                6

/* BRPHY4_CL45DEV7 :: AN_STAT :: AN_complete [05:05] */
#define Wr_BRPHY4_CL45DEV7_AN_STAT_AN_complete(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x20,5,x)
#define Rd_BRPHY4_CL45DEV7_AN_STAT_AN_complete(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x20,5)
#define BRPHY4_CL45DEV7_AN_STAT_AN_COMPLETE_MASK                   0x0020
#define BRPHY4_CL45DEV7_AN_STAT_AN_COMPLETE_ALIGN                  0
#define BRPHY4_CL45DEV7_AN_STAT_AN_COMPLETE_BITS                   1
#define BRPHY4_CL45DEV7_AN_STAT_AN_COMPLETE_SHIFT                  5

/* BRPHY4_CL45DEV7 :: AN_STAT :: Remodt_Fault [04:04] */
#define Wr_BRPHY4_CL45DEV7_AN_STAT_Remodt_Fault(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x10,4,x)
#define Rd_BRPHY4_CL45DEV7_AN_STAT_Remodt_Fault(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x10,4)
#define BRPHY4_CL45DEV7_AN_STAT_REMODT_FAULT_MASK                  0x0010
#define BRPHY4_CL45DEV7_AN_STAT_REMODT_FAULT_ALIGN                 0
#define BRPHY4_CL45DEV7_AN_STAT_REMODT_FAULT_BITS                  1
#define BRPHY4_CL45DEV7_AN_STAT_REMODT_FAULT_SHIFT                 4

/* BRPHY4_CL45DEV7 :: AN_STAT :: AN_ability [03:03] */
#define Wr_BRPHY4_CL45DEV7_AN_STAT_AN_ability(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x8,3,x)
#define Rd_BRPHY4_CL45DEV7_AN_STAT_AN_ability(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x8,3)
#define BRPHY4_CL45DEV7_AN_STAT_AN_ABILITY_MASK                    0x0008
#define BRPHY4_CL45DEV7_AN_STAT_AN_ABILITY_ALIGN                   0
#define BRPHY4_CL45DEV7_AN_STAT_AN_ABILITY_BITS                    1
#define BRPHY4_CL45DEV7_AN_STAT_AN_ABILITY_SHIFT                   3

/* BRPHY4_CL45DEV7 :: AN_STAT :: Link_status [02:02] */
#define Wr_BRPHY4_CL45DEV7_AN_STAT_Link_status(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x4,2,x)
#define Rd_BRPHY4_CL45DEV7_AN_STAT_Link_status(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x4,2)
#define BRPHY4_CL45DEV7_AN_STAT_LINK_STATUS_MASK                   0x0004
#define BRPHY4_CL45DEV7_AN_STAT_LINK_STATUS_ALIGN                  0
#define BRPHY4_CL45DEV7_AN_STAT_LINK_STATUS_BITS                   1
#define BRPHY4_CL45DEV7_AN_STAT_LINK_STATUS_SHIFT                  2

/* BRPHY4_CL45DEV7 :: AN_STAT :: reserved1 [01:01] */
#define BRPHY4_CL45DEV7_AN_STAT_RESERVED1_MASK                     0x0002
#define BRPHY4_CL45DEV7_AN_STAT_RESERVED1_ALIGN                    0
#define BRPHY4_CL45DEV7_AN_STAT_RESERVED1_BITS                     1
#define BRPHY4_CL45DEV7_AN_STAT_RESERVED1_SHIFT                    1

/* BRPHY4_CL45DEV7 :: AN_STAT :: Link_partner_AN_ability [00:00] */
#define Wr_BRPHY4_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x1,0,x)
#define Rd_BRPHY4_CL45DEV7_AN_STAT_Link_partner_AN_ability(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_STAT,0x1,0)
#define BRPHY4_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_MASK       0x0001
#define BRPHY4_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY4_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY4_CL45DEV7_AN_STAT_LINK_PARTNER_AN_ABILITY_SHIFT      0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_DEV_ID_LSB
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_DEV_ID_LSB :: cu_an_device_identifier [15:00] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) WriteReg16(BRPHY4_CL45DEV7_AN_DEV_ID_LSB,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_ID_LSB_cu_an_device_identifier(x) ReadReg16(BRPHY4_CL45DEV7_AN_DEV_ID_LSB)
#define BRPHY4_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xffff
#define BRPHY4_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY4_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_BITS 16
#define BRPHY4_CL45DEV7_AN_DEV_ID_LSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_DEV_ID_MSB
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_DEV_ID_MSB :: cu_an_device_identifier [15:10] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_ID_MSB_cu_an_device_identifier(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_ID_MSB,0xfc00,10)
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_MASK 0xfc00
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_ALIGN 0
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_BITS 6
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_CU_AN_DEVICE_IDENTIFIER_SHIFT 10

/* BRPHY4_CL45DEV7 :: AN_DEV_ID_MSB :: MODEL_NU [09:04] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_ID_MSB,0x3f0,4)
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_MASK                0x03f0
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_ALIGN               0
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_BITS                6
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_MODEL_NU_SHIFT               4

/* BRPHY4_CL45DEV7 :: AN_DEV_ID_MSB :: REV_NU [03:00] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_ID_MSB,0xf,0,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_ID_MSB_REV_NU(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_ID_MSB,0xf,0)
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_REV_NU_MASK                  0x000f
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_REV_NU_ALIGN                 0
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_REV_NU_BITS                  4
#define BRPHY4_CL45DEV7_AN_DEV_ID_MSB_REV_NU_SHIFT                 0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: reserved0 [15:08] */
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_MASK           0xff00
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_ALIGN          0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_BITS           8
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_RESERVED0_SHIFT          8

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: AUTONEG_PRE [07:07] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x80,7)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_MASK         0x0080
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_ALIGN        0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_BITS         1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_AUTONEG_PRE_SHIFT        7

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: TC_PRE [06:06] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x40,6)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_MASK              0x0040
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_ALIGN             0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_BITS              1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_TC_PRE_SHIFT             6

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: DTEXS_PRE [05:05] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x20,5)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_MASK           0x0020
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_ALIGN          0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_BITS           1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_DTEXS_PRE_SHIFT          5

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PHYXS_PRE [04:04] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x10,4)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_MASK           0x0010
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_ALIGN          0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_BITS           1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PHYXS_PRE_SHIFT          4

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PCS_PRE [03:03] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x8,3)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_MASK             0x0008
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_ALIGN            0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_BITS             1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PCS_PRE_SHIFT            3

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: WIS_PRE [02:02] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x4,2)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_MASK             0x0004
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_ALIGN            0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_BITS             1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_WIS_PRE_SHIFT            2

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: PMD_PRE [01:01] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x2,1)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_MASK             0x0002
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_ALIGN            0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_BITS             1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_PMD_PRE_SHIFT            1

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_LSB :: CLA22_PRE [00:00] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB,0x1,0)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_MASK           0x0001
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_ALIGN          0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_BITS           1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_LSB_CLA22_PRE_SHIFT          0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_MSB
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV2_PRE [15:15] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB,0x8000,15)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_MASK      0x8000
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_ALIGN     0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_BITS      1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV2_PRE_SHIFT     15

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: VENSP_DEV1_PRE [14:14] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB,0x4000,14)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_MASK      0x4000
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_ALIGN     0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_BITS      1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_VENSP_DEV1_PRE_SHIFT     14

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: CLA22_EXT_PRE [13:13] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB,0x2000,13)
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_MASK       0x2000
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_ALIGN      0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_BITS       1
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_CLA22_EXT_PRE_SHIFT      13

/* BRPHY4_CL45DEV7 :: AN_DEV_IN_PKG_MSB :: reserved0 [12:00] */
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_MASK           0x1fff
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_ALIGN          0
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_BITS           13
#define BRPHY4_CL45DEV7_AN_DEV_IN_PKG_MSB_RESERVED0_SHIFT          0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_DEV_PKG_ID_LSB
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_DEV_PKG_ID_LSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) WriteReg16(BRPHY4_CL45DEV7_AN_DEV_PKG_ID_LSB,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_PKG_ID_LSB_cu_an_device_package_id(x) ReadReg16(BRPHY4_CL45DEV7_AN_DEV_PKG_ID_LSB)
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_LSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_DEV_PKG_ID_MSB
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_DEV_PKG_ID_MSB :: cu_an_device_package_id [15:00] */
#define Wr_BRPHY4_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) WriteReg16(BRPHY4_CL45DEV7_AN_DEV_PKG_ID_MSB,x)
#define Rd_BRPHY4_CL45DEV7_AN_DEV_PKG_ID_MSB_cu_an_device_package_id(x) ReadReg16(BRPHY4_CL45DEV7_AN_DEV_PKG_ID_MSB)
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_MASK 0xffff
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_ALIGN 0
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_BITS 16
#define BRPHY4_CL45DEV7_AN_DEV_PKG_ID_MSB_CU_AN_DEVICE_PACKAGE_ID_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_AD
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_AD :: Next_page [15:15] */
#define Wr_BRPHY4_CL45DEV7_AN_AD_Next_page(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_AD,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV7_AN_AD_Next_page(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_AD,0x8000,15)
#define BRPHY4_CL45DEV7_AN_AD_NEXT_PAGE_MASK                       0x8000
#define BRPHY4_CL45DEV7_AN_AD_NEXT_PAGE_ALIGN                      0
#define BRPHY4_CL45DEV7_AN_AD_NEXT_PAGE_BITS                       1
#define BRPHY4_CL45DEV7_AN_AD_NEXT_PAGE_SHIFT                      15

/* BRPHY4_CL45DEV7 :: AN_AD :: Acknowledge [14:14] */
#define Wr_BRPHY4_CL45DEV7_AN_AD_Acknowledge(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_AD,0x4000,14,x)
#define Rd_BRPHY4_CL45DEV7_AN_AD_Acknowledge(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_AD,0x4000,14)
#define BRPHY4_CL45DEV7_AN_AD_ACKNOWLEDGE_MASK                     0x4000
#define BRPHY4_CL45DEV7_AN_AD_ACKNOWLEDGE_ALIGN                    0
#define BRPHY4_CL45DEV7_AN_AD_ACKNOWLEDGE_BITS                     1
#define BRPHY4_CL45DEV7_AN_AD_ACKNOWLEDGE_SHIFT                    14

/* BRPHY4_CL45DEV7 :: AN_AD :: Remote_fault [13:13] */
#define Wr_BRPHY4_CL45DEV7_AN_AD_Remote_fault(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_AD,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV7_AN_AD_Remote_fault(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_AD,0x2000,13)
#define BRPHY4_CL45DEV7_AN_AD_REMOTE_FAULT_MASK                    0x2000
#define BRPHY4_CL45DEV7_AN_AD_REMOTE_FAULT_ALIGN                   0
#define BRPHY4_CL45DEV7_AN_AD_REMOTE_FAULT_BITS                    1
#define BRPHY4_CL45DEV7_AN_AD_REMOTE_FAULT_SHIFT                   13

/* BRPHY4_CL45DEV7 :: AN_AD :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY4_CL45DEV7_AN_AD_Extended_next_page_ability(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_AD,0x1000,12,x)
#define Rd_BRPHY4_CL45DEV7_AN_AD_Extended_next_page_ability(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_AD,0x1000,12)
#define BRPHY4_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_MASK      0x1000
#define BRPHY4_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_ALIGN     0
#define BRPHY4_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_BITS      1
#define BRPHY4_CL45DEV7_AN_AD_EXTENDED_NEXT_PAGE_ABILITY_SHIFT     12

/* BRPHY4_CL45DEV7 :: AN_AD :: Tech_Field [11:05] */
#define Wr_BRPHY4_CL45DEV7_AN_AD_Tech_Field(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_AD,0xfe0,5,x)
#define Rd_BRPHY4_CL45DEV7_AN_AD_Tech_Field(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_AD,0xfe0,5)
#define BRPHY4_CL45DEV7_AN_AD_TECH_FIELD_MASK                      0x0fe0
#define BRPHY4_CL45DEV7_AN_AD_TECH_FIELD_ALIGN                     0
#define BRPHY4_CL45DEV7_AN_AD_TECH_FIELD_BITS                      7
#define BRPHY4_CL45DEV7_AN_AD_TECH_FIELD_SHIFT                     5

/* BRPHY4_CL45DEV7 :: AN_AD :: Selector_Field [04:00] */
#define Wr_BRPHY4_CL45DEV7_AN_AD_Selector_Field(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_AD,0x1f,0,x)
#define Rd_BRPHY4_CL45DEV7_AN_AD_Selector_Field(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_AD,0x1f,0)
#define BRPHY4_CL45DEV7_AN_AD_SELECTOR_FIELD_MASK                  0x001f
#define BRPHY4_CL45DEV7_AN_AD_SELECTOR_FIELD_ALIGN                 0
#define BRPHY4_CL45DEV7_AN_AD_SELECTOR_FIELD_BITS                  5
#define BRPHY4_CL45DEV7_AN_AD_SELECTOR_FIELD_SHIFT                 0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_LPA
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_LPA :: Next_page [15:15] */
#define Wr_BRPHY4_CL45DEV7_AN_LPA_Next_page(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV7_AN_LPA_Next_page(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x8000,15)
#define BRPHY4_CL45DEV7_AN_LPA_NEXT_PAGE_MASK                      0x8000
#define BRPHY4_CL45DEV7_AN_LPA_NEXT_PAGE_ALIGN                     0
#define BRPHY4_CL45DEV7_AN_LPA_NEXT_PAGE_BITS                      1
#define BRPHY4_CL45DEV7_AN_LPA_NEXT_PAGE_SHIFT                     15

/* BRPHY4_CL45DEV7 :: AN_LPA :: Acknowledge [14:14] */
#define Wr_BRPHY4_CL45DEV7_AN_LPA_Acknowledge(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x4000,14,x)
#define Rd_BRPHY4_CL45DEV7_AN_LPA_Acknowledge(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x4000,14)
#define BRPHY4_CL45DEV7_AN_LPA_ACKNOWLEDGE_MASK                    0x4000
#define BRPHY4_CL45DEV7_AN_LPA_ACKNOWLEDGE_ALIGN                   0
#define BRPHY4_CL45DEV7_AN_LPA_ACKNOWLEDGE_BITS                    1
#define BRPHY4_CL45DEV7_AN_LPA_ACKNOWLEDGE_SHIFT                   14

/* BRPHY4_CL45DEV7 :: AN_LPA :: Remote_fault [13:13] */
#define Wr_BRPHY4_CL45DEV7_AN_LPA_Remote_fault(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV7_AN_LPA_Remote_fault(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x2000,13)
#define BRPHY4_CL45DEV7_AN_LPA_REMOTE_FAULT_MASK                   0x2000
#define BRPHY4_CL45DEV7_AN_LPA_REMOTE_FAULT_ALIGN                  0
#define BRPHY4_CL45DEV7_AN_LPA_REMOTE_FAULT_BITS                   1
#define BRPHY4_CL45DEV7_AN_LPA_REMOTE_FAULT_SHIFT                  13

/* BRPHY4_CL45DEV7 :: AN_LPA :: Extended_next_page_ability [12:12] */
#define Wr_BRPHY4_CL45DEV7_AN_LPA_Extended_next_page_ability(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x1000,12,x)
#define Rd_BRPHY4_CL45DEV7_AN_LPA_Extended_next_page_ability(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x1000,12)
#define BRPHY4_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_MASK     0x1000
#define BRPHY4_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_ALIGN    0
#define BRPHY4_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_BITS     1
#define BRPHY4_CL45DEV7_AN_LPA_EXTENDED_NEXT_PAGE_ABILITY_SHIFT    12

/* BRPHY4_CL45DEV7 :: AN_LPA :: Tech_Field [11:05] */
#define Wr_BRPHY4_CL45DEV7_AN_LPA_Tech_Field(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_LPA,0xfe0,5,x)
#define Rd_BRPHY4_CL45DEV7_AN_LPA_Tech_Field(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_LPA,0xfe0,5)
#define BRPHY4_CL45DEV7_AN_LPA_TECH_FIELD_MASK                     0x0fe0
#define BRPHY4_CL45DEV7_AN_LPA_TECH_FIELD_ALIGN                    0
#define BRPHY4_CL45DEV7_AN_LPA_TECH_FIELD_BITS                     7
#define BRPHY4_CL45DEV7_AN_LPA_TECH_FIELD_SHIFT                    5

/* BRPHY4_CL45DEV7 :: AN_LPA :: Selector_Field [04:00] */
#define Wr_BRPHY4_CL45DEV7_AN_LPA_Selector_Field(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x1f,0,x)
#define Rd_BRPHY4_CL45DEV7_AN_LPA_Selector_Field(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_LPA,0x1f,0)
#define BRPHY4_CL45DEV7_AN_LPA_SELECTOR_FIELD_MASK                 0x001f
#define BRPHY4_CL45DEV7_AN_LPA_SELECTOR_FIELD_ALIGN                0
#define BRPHY4_CL45DEV7_AN_LPA_SELECTOR_FIELD_BITS                 5
#define BRPHY4_CL45DEV7_AN_LPA_SELECTOR_FIELD_SHIFT                0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_XNPA
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_XNPA :: Next_page [15:15] */
#define Wr_BRPHY4_CL45DEV7_AN_XNPA_Next_page(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV7_AN_XNPA_Next_page(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x8000,15)
#define BRPHY4_CL45DEV7_AN_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY4_CL45DEV7_AN_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY4_CL45DEV7_AN_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY4_CL45DEV7_AN_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY4_CL45DEV7 :: AN_XNPA :: reserved0 [14:14] */
#define BRPHY4_CL45DEV7_AN_XNPA_RESERVED0_MASK                     0x4000
#define BRPHY4_CL45DEV7_AN_XNPA_RESERVED0_ALIGN                    0
#define BRPHY4_CL45DEV7_AN_XNPA_RESERVED0_BITS                     1
#define BRPHY4_CL45DEV7_AN_XNPA_RESERVED0_SHIFT                    14

/* BRPHY4_CL45DEV7 :: AN_XNPA :: Message_page [13:13] */
#define Wr_BRPHY4_CL45DEV7_AN_XNPA_Message_page(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV7_AN_XNPA_Message_page(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x2000,13)
#define BRPHY4_CL45DEV7_AN_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY4_CL45DEV7_AN_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY4_CL45DEV7_AN_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY4_CL45DEV7_AN_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY4_CL45DEV7 :: AN_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY4_CL45DEV7_AN_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x1000,12,x)
#define Rd_BRPHY4_CL45DEV7_AN_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x1000,12)
#define BRPHY4_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY4_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY4_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY4_CL45DEV7_AN_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY4_CL45DEV7 :: AN_XNPA :: Toggle [11:11] */
#define Wr_BRPHY4_CL45DEV7_AN_XNPA_Toggle(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x800,11,x)
#define Rd_BRPHY4_CL45DEV7_AN_XNPA_Toggle(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x800,11)
#define BRPHY4_CL45DEV7_AN_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY4_CL45DEV7_AN_XNPA_TOGGLE_ALIGN                       0
#define BRPHY4_CL45DEV7_AN_XNPA_TOGGLE_BITS                        1
#define BRPHY4_CL45DEV7_AN_XNPA_TOGGLE_SHIFT                       11

/* BRPHY4_CL45DEV7 :: AN_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY4_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x7ff,0,x)
#define Rd_BRPHY4_CL45DEV7_AN_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY4_CL45DEV7_AN_XNPA,0x7ff,0)
#define BRPHY4_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY4_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY4_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY4_CL45DEV7_AN_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_XNPB
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY4_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY4_CL45DEV7_AN_XNPB,x)
#define Rd_BRPHY4_CL45DEV7_AN_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY4_CL45DEV7_AN_XNPB)
#define BRPHY4_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY4_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY4_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY4_CL45DEV7_AN_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: AN_XNPC
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: AN_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY4_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY4_CL45DEV7_AN_XNPC,x)
#define Rd_BRPHY4_CL45DEV7_AN_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY4_CL45DEV7_AN_XNPC)
#define BRPHY4_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY4_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY4_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY4_CL45DEV7_AN_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: LP_XNPA
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: LP_XNPA :: Next_page [15:15] */
#define Wr_BRPHY4_CL45DEV7_LP_XNPA_Next_page(x) WriteRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV7_LP_XNPA_Next_page(x) ReadRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x8000,15)
#define BRPHY4_CL45DEV7_LP_XNPA_NEXT_PAGE_MASK                     0x8000
#define BRPHY4_CL45DEV7_LP_XNPA_NEXT_PAGE_ALIGN                    0
#define BRPHY4_CL45DEV7_LP_XNPA_NEXT_PAGE_BITS                     1
#define BRPHY4_CL45DEV7_LP_XNPA_NEXT_PAGE_SHIFT                    15

/* BRPHY4_CL45DEV7 :: LP_XNPA :: Acknowledge [14:14] */
#define Wr_BRPHY4_CL45DEV7_LP_XNPA_Acknowledge(x) WriteRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x4000,14,x)
#define Rd_BRPHY4_CL45DEV7_LP_XNPA_Acknowledge(x) ReadRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x4000,14)
#define BRPHY4_CL45DEV7_LP_XNPA_ACKNOWLEDGE_MASK                   0x4000
#define BRPHY4_CL45DEV7_LP_XNPA_ACKNOWLEDGE_ALIGN                  0
#define BRPHY4_CL45DEV7_LP_XNPA_ACKNOWLEDGE_BITS                   1
#define BRPHY4_CL45DEV7_LP_XNPA_ACKNOWLEDGE_SHIFT                  14

/* BRPHY4_CL45DEV7 :: LP_XNPA :: Message_page [13:13] */
#define Wr_BRPHY4_CL45DEV7_LP_XNPA_Message_page(x) WriteRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV7_LP_XNPA_Message_page(x) ReadRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x2000,13)
#define BRPHY4_CL45DEV7_LP_XNPA_MESSAGE_PAGE_MASK                  0x2000
#define BRPHY4_CL45DEV7_LP_XNPA_MESSAGE_PAGE_ALIGN                 0
#define BRPHY4_CL45DEV7_LP_XNPA_MESSAGE_PAGE_BITS                  1
#define BRPHY4_CL45DEV7_LP_XNPA_MESSAGE_PAGE_SHIFT                 13

/* BRPHY4_CL45DEV7 :: LP_XNPA :: Acknowledge_2 [12:12] */
#define Wr_BRPHY4_CL45DEV7_LP_XNPA_Acknowledge_2(x) WriteRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x1000,12,x)
#define Rd_BRPHY4_CL45DEV7_LP_XNPA_Acknowledge_2(x) ReadRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x1000,12)
#define BRPHY4_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_MASK                 0x1000
#define BRPHY4_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_ALIGN                0
#define BRPHY4_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_BITS                 1
#define BRPHY4_CL45DEV7_LP_XNPA_ACKNOWLEDGE_2_SHIFT                12

/* BRPHY4_CL45DEV7 :: LP_XNPA :: Toggle [11:11] */
#define Wr_BRPHY4_CL45DEV7_LP_XNPA_Toggle(x) WriteRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x800,11,x)
#define Rd_BRPHY4_CL45DEV7_LP_XNPA_Toggle(x) ReadRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x800,11)
#define BRPHY4_CL45DEV7_LP_XNPA_TOGGLE_MASK                        0x0800
#define BRPHY4_CL45DEV7_LP_XNPA_TOGGLE_ALIGN                       0
#define BRPHY4_CL45DEV7_LP_XNPA_TOGGLE_BITS                        1
#define BRPHY4_CL45DEV7_LP_XNPA_TOGGLE_SHIFT                       11

/* BRPHY4_CL45DEV7 :: LP_XNPA :: Unformatted_Code_Field [10:00] */
#define Wr_BRPHY4_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) WriteRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x7ff,0,x)
#define Rd_BRPHY4_CL45DEV7_LP_XNPA_Unformatted_Code_Field(x) ReadRegBits16(BRPHY4_CL45DEV7_LP_XNPA,0x7ff,0)
#define BRPHY4_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_MASK        0x07ff
#define BRPHY4_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_ALIGN       0
#define BRPHY4_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_BITS        11
#define BRPHY4_CL45DEV7_LP_XNPA_UNFORMATTED_CODE_FIELD_SHIFT       0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: LP_XNPB
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: LP_XNPB :: Unformatted_Code_Field1 [15:00] */
#define Wr_BRPHY4_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) WriteReg16(BRPHY4_CL45DEV7_LP_XNPB,x)
#define Rd_BRPHY4_CL45DEV7_LP_XNPB_Unformatted_Code_Field1(x) ReadReg16(BRPHY4_CL45DEV7_LP_XNPB)
#define BRPHY4_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_MASK       0xffff
#define BRPHY4_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_ALIGN      0
#define BRPHY4_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_BITS       16
#define BRPHY4_CL45DEV7_LP_XNPB_UNFORMATTED_CODE_FIELD1_SHIFT      0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: LP_XNPC
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: LP_XNPC :: Unformatted_Code_Field2 [15:00] */
#define Wr_BRPHY4_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) WriteReg16(BRPHY4_CL45DEV7_LP_XNPC,x)
#define Rd_BRPHY4_CL45DEV7_LP_XNPC_Unformatted_Code_Field2(x) ReadReg16(BRPHY4_CL45DEV7_LP_XNPC)
#define BRPHY4_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_MASK       0xffff
#define BRPHY4_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_ALIGN      0
#define BRPHY4_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_BITS       16
#define BRPHY4_CL45DEV7_LP_XNPC_UNFORMATTED_CODE_FIELD2_SHIFT      0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: TENG_AN_CTRL
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_MAN_CONFIG_EN [15:15] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x8000,15)
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_MASK   0x8000
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_ALIGN  0
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_BITS   1
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_MAN_CONFIG_EN_SHIFT  15

/* BRPHY4_CL45DEV7 :: TENG_AN_CTRL :: MSTR_SLV_CONFIG_VAL [14:14] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x4000,14,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x4000,14)
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_MASK      0x4000
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_ALIGN     0
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_BITS      1
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_MSTR_SLV_CONFIG_VAL_SHIFT     14

/* BRPHY4_CL45DEV7 :: TENG_AN_CTRL :: PORT_TYPE [13:13] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_CTRL_PORT_TYPE(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x2000,13)
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_MASK                0x2000
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_ALIGN               0
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_BITS                1
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_PORT_TYPE_SHIFT               13

/* BRPHY4_CL45DEV7 :: TENG_AN_CTRL :: PHY10GBASET_ABLE [12:12] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x1000,12,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x1000,12)
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_MASK         0x1000
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_ALIGN        0
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_BITS         1
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_PHY10GBASET_ABLE_SHIFT        12

/* BRPHY4_CL45DEV7 :: TENG_AN_CTRL :: reserved0 [11:03] */
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_RESERVED0_MASK                0x0ff8
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_RESERVED0_ALIGN               0
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_RESERVED0_BITS                9
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_RESERVED0_SHIFT               3

/* BRPHY4_CL45DEV7 :: TENG_AN_CTRL :: LD_PMA_TRAIN_RST_SEQ [02:02] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x4,2,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x4,2)
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_MASK     0x0004
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_ALIGN    0
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_BITS     1
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_PMA_TRAIN_RST_SEQ_SHIFT    2

/* BRPHY4_CL45DEV7 :: TENG_AN_CTRL :: reserved1 [01:01] */
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_RESERVED1_MASK                0x0002
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_RESERVED1_ALIGN               0
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_RESERVED1_BITS                1
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_RESERVED1_SHIFT               1

/* BRPHY4_CL45DEV7 :: TENG_AN_CTRL :: LD_LOOP_TIMING_ABLE [00:00] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x1,0,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_CTRL,0x1,0)
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_MASK      0x0001
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_BITS      1
#define BRPHY4_CL45DEV7_TENG_AN_CTRL_LD_LOOP_TIMING_ABLE_SHIFT     0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: TENG_AN_STAT
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_FAULT [15:15] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x8000,15,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x8000,15)
#define BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_MASK    0x8000
#define BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_ALIGN   0
#define BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_BITS    1
#define BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_FAULT_SHIFT   15

/* BRPHY4_CL45DEV7 :: TENG_AN_STAT :: MSTR_SLV_CONFIG_RES [14:14] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x4000,14,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x4000,14)
#define BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_MASK      0x4000
#define BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_ALIGN     0
#define BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_BITS      1
#define BRPHY4_CL45DEV7_TENG_AN_STAT_MSTR_SLV_CONFIG_RES_SHIFT     14

/* BRPHY4_CL45DEV7 :: TENG_AN_STAT :: LOCAL_RCVR_STAT [13:13] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x2000,13,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x2000,13)
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_MASK          0x2000
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_ALIGN         0
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_BITS          1
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LOCAL_RCVR_STAT_SHIFT         13

/* BRPHY4_CL45DEV7 :: TENG_AN_STAT :: REMOTE_RCVR_STAT [12:12] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x1000,12,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x1000,12)
#define BRPHY4_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_MASK         0x1000
#define BRPHY4_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_ALIGN        0
#define BRPHY4_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_BITS         1
#define BRPHY4_CL45DEV7_TENG_AN_STAT_REMOTE_RCVR_STAT_SHIFT        12

/* BRPHY4_CL45DEV7 :: TENG_AN_STAT :: LNK_PRTNR_10GBASET_CAP [11:11] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x800,11,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x800,11)
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_MASK   0x0800
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_ALIGN  0
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_BITS   1
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LNK_PRTNR_10GBASET_CAP_SHIFT  11

/* BRPHY4_CL45DEV7 :: TENG_AN_STAT :: LP_LOOP_TIMING_ABLE [10:10] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x400,10,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x400,10)
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_MASK      0x0400
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_ALIGN     0
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_BITS      1
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LP_LOOP_TIMING_ABLE_SHIFT     10

/* BRPHY4_CL45DEV7 :: TENG_AN_STAT :: LP_PMA_TRAIN_RST_REQ [09:09] */
#define Wr_BRPHY4_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) WriteRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x200,9,x)
#define Rd_BRPHY4_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ(x) ReadRegBits16(BRPHY4_CL45DEV7_TENG_AN_STAT,0x200,9)
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_MASK     0x0200
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_ALIGN    0
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_BITS     1
#define BRPHY4_CL45DEV7_TENG_AN_STAT_LP_PMA_TRAIN_RST_REQ_SHIFT    9

/* BRPHY4_CL45DEV7 :: TENG_AN_STAT :: reserved0 [08:00] */
#define BRPHY4_CL45DEV7_TENG_AN_STAT_RESERVED0_MASK                0x01ff
#define BRPHY4_CL45DEV7_TENG_AN_STAT_RESERVED0_ALIGN               0
#define BRPHY4_CL45DEV7_TENG_AN_STAT_RESERVED0_BITS                9
#define BRPHY4_CL45DEV7_TENG_AN_STAT_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: EEE_ADV
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: EEE_ADV :: reserved0 [15:11] */
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED0_MASK                     0xf800
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED0_ALIGN                    0
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED0_BITS                     5
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED0_SHIFT                    11

/* BRPHY4_CL45DEV7 :: EEE_ADV :: Next_page [10:10] */
#define Wr_BRPHY4_CL45DEV7_EEE_ADV_Next_page(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x400,10,x)
#define Rd_BRPHY4_CL45DEV7_EEE_ADV_Next_page(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x400,10)
#define BRPHY4_CL45DEV7_EEE_ADV_NEXT_PAGE_MASK                     0x0400
#define BRPHY4_CL45DEV7_EEE_ADV_NEXT_PAGE_ALIGN                    0
#define BRPHY4_CL45DEV7_EEE_ADV_NEXT_PAGE_BITS                     1
#define BRPHY4_CL45DEV7_EEE_ADV_NEXT_PAGE_SHIFT                    10

/* BRPHY4_CL45DEV7 :: EEE_ADV :: reserved1 [09:07] */
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED1_MASK                     0x0380
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED1_ALIGN                    0
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED1_BITS                     3
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED1_SHIFT                    7

/* BRPHY4_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KR_EEE [06:06] */
#define Wr_BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x40,6,x)
#define Rd_BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x40,6)
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_MASK            0x0040
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_ALIGN           0
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_BITS            1
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KR_EEE_SHIFT           6

/* BRPHY4_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_KX4_EEE [05:05] */
#define Wr_BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x20,5,x)
#define Rd_BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x20,5)
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_MASK           0x0020
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_ALIGN          0
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_BITS           1
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_KX4_EEE_SHIFT          5

/* BRPHY4_CL45DEV7 :: EEE_ADV :: reserved2 [04:04] */
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED2_MASK                     0x0010
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED2_ALIGN                    0
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED2_BITS                     1
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED2_SHIFT                    4

/* BRPHY4_CL45DEV7 :: EEE_ADV :: PHY_10GBASE_T_EEE [03:03] */
#define Wr_BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x8,3,x)
#define Rd_BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x8,3)
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_MASK             0x0008
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_ALIGN            0
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_BITS             1
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_10GBASE_T_EEE_SHIFT            3

/* BRPHY4_CL45DEV7 :: EEE_ADV :: PHY_1000BASE_T_EEE [02:02] */
#define Wr_BRPHY4_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x4,2,x)
#define Rd_BRPHY4_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x4,2)
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_MASK            0x0004
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_ALIGN           0
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_BITS            1
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_1000BASE_T_EEE_SHIFT           2

/* BRPHY4_CL45DEV7 :: EEE_ADV :: PHY_100BASE_T_EEE [01:01] */
#define Wr_BRPHY4_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x2,1,x)
#define Rd_BRPHY4_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_ADV,0x2,1)
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_MASK             0x0002
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_ALIGN            0
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_BITS             1
#define BRPHY4_CL45DEV7_EEE_ADV_PHY_100BASE_T_EEE_SHIFT            1

/* BRPHY4_CL45DEV7 :: EEE_ADV :: reserved3 [00:00] */
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED3_MASK                     0x0001
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED3_ALIGN                    0
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED3_BITS                     1
#define BRPHY4_CL45DEV7_EEE_ADV_RESERVED3_SHIFT                    0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: EEE_LP_ADV
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: EEE_LP_ADV :: status [15:00] */
#define Wr_BRPHY4_CL45DEV7_EEE_LP_ADV_status(x) WriteReg16(BRPHY4_CL45DEV7_EEE_LP_ADV,x)
#define Rd_BRPHY4_CL45DEV7_EEE_LP_ADV_status(x) ReadReg16(BRPHY4_CL45DEV7_EEE_LP_ADV)
#define BRPHY4_CL45DEV7_EEE_LP_ADV_STATUS_MASK                     0xffff
#define BRPHY4_CL45DEV7_EEE_LP_ADV_STATUS_ALIGN                    0
#define BRPHY4_CL45DEV7_EEE_LP_ADV_STATUS_BITS                     16
#define BRPHY4_CL45DEV7_EEE_LP_ADV_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY4_CL45DEV7 :: EEE_MODE_CTL
 ***************************************************************************/
/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: reserved0 [15:11] */
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED0_MASK                0xf800
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED0_ALIGN               0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED0_BITS                5
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED0_SHIFT               11

/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: Next_page [10:10] */
#define Wr_BRPHY4_CL45DEV7_EEE_MODE_CTL_Next_page(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x400,10,x)
#define Rd_BRPHY4_CL45DEV7_EEE_MODE_CTL_Next_page(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x400,10)
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_MASK                0x0400
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_ALIGN               0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_BITS                1
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_NEXT_PAGE_SHIFT               10

/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: reserved1 [09:07] */
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED1_MASK                0x0380
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED1_ALIGN               0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED1_BITS                3
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED1_SHIFT               7

/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KR_reduced_energy [06:06] */
#define Wr_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x40,6,x)
#define Rd_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_reduced_energy(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x40,6)
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_MASK 0x0040
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_ALIGN 0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_BITS 1
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KR_REDUCED_ENERGY_SHIFT 6

/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_KX4_reduced_energy [05:05] */
#define Wr_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x20,5,x)
#define Rd_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_reduced_energy(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x20,5)
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_MASK 0x0020
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_ALIGN 0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_BITS 1
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_KX4_REDUCED_ENERGY_SHIFT 5

/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: reserved2 [04:04] */
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED2_MASK                0x0010
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED2_ALIGN               0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED2_BITS                1
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED2_SHIFT               4

/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: PHY_10GBASE_T_reduced_energy [03:03] */
#define Wr_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x8,3,x)
#define Rd_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_reduced_energy(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x8,3)
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_MASK 0x0008
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_10GBASE_T_REDUCED_ENERGY_SHIFT 3

/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: PHY_1000BASE_T_reduced_energy [02:02] */
#define Wr_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x4,2,x)
#define Rd_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_reduced_energy(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x4,2)
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_MASK 0x0004
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_1000BASE_T_REDUCED_ENERGY_SHIFT 2

/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: PHY_100BASE_T_reduced_energy [01:01] */
#define Wr_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) WriteRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x2,1,x)
#define Rd_BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_reduced_energy(x) ReadRegBits16(BRPHY4_CL45DEV7_EEE_MODE_CTL,0x2,1)
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_MASK 0x0002
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_ALIGN 0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_BITS 1
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_PHY_100BASE_T_REDUCED_ENERGY_SHIFT 1

/* BRPHY4_CL45DEV7 :: EEE_MODE_CTL :: reserved3 [00:00] */
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED3_MASK                0x0001
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED3_ALIGN               0
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED3_BITS                1
#define BRPHY4_CL45DEV7_EEE_MODE_CTL_RESERVED3_SHIFT               0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_CL45VEN
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_CL45VEN :: FORCE_LINK
 ***************************************************************************/
/* BRPHY4_CL45VEN :: FORCE_LINK :: FORCE_LINK_MODE [15:15] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x8000,15,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_FORCE_LINK_MODE(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x8000,15)
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_MASK             0x8000
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_ALIGN            0
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_BITS             1
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LINK_MODE_SHIFT            15

/* BRPHY4_CL45VEN :: FORCE_LINK :: CHNG_10GBASET_AN_CTRL_BEHAV [14:14] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x4000,14,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x4000,14)
#define BRPHY4_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_MASK 0x4000
#define BRPHY4_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_ALIGN 0
#define BRPHY4_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_BITS 1
#define BRPHY4_CL45VEN_FORCE_LINK_CHNG_10GBASET_AN_CTRL_BEHAV_SHIFT 14

/* BRPHY4_CL45VEN :: FORCE_LINK :: CHNG_BIT13_MCTRL_RD_BEHAV [13:13] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x2000,13,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x2000,13)
#define BRPHY4_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_MASK   0x2000
#define BRPHY4_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_ALIGN  0
#define BRPHY4_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_BITS   1
#define BRPHY4_CL45VEN_FORCE_LINK_CHNG_BIT13_MCTRL_RD_BEHAV_SHIFT  13

/* BRPHY4_CL45VEN :: FORCE_LINK :: AN_FLP_BTB_TMR_MODE [12:12] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x1000,12,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x1000,12)
#define BRPHY4_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_MASK         0x1000
#define BRPHY4_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_ALIGN        0
#define BRPHY4_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_BITS         1
#define BRPHY4_CL45VEN_FORCE_LINK_AN_FLP_BTB_TMR_MODE_SHIFT        12

/* BRPHY4_CL45VEN :: FORCE_LINK :: SWP_UFORMATED_CODE_FLDS [11:11] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x800,11,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x800,11)
#define BRPHY4_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_MASK     0x0800
#define BRPHY4_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_ALIGN    0
#define BRPHY4_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_BITS     1
#define BRPHY4_CL45VEN_FORCE_LINK_SWP_UFORMATED_CODE_FLDS_SHIFT    11

/* BRPHY4_CL45VEN :: FORCE_LINK :: BRK_LNK_TMR_MODE [10:10] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x400,10,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x400,10)
#define BRPHY4_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_MASK            0x0400
#define BRPHY4_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_ALIGN           0
#define BRPHY4_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_BITS            1
#define BRPHY4_CL45VEN_FORCE_LINK_BRK_LNK_TMR_MODE_SHIFT           10

/* BRPHY4_CL45VEN :: FORCE_LINK :: PREAMBLE_IGNORE [09:09] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x200,9,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x200,9)
#define BRPHY4_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_MASK             0x0200
#define BRPHY4_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_ALIGN            0
#define BRPHY4_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_BITS             1
#define BRPHY4_CL45VEN_FORCE_LINK_PREAMBLE_IGNORE_SHIFT            9

/* BRPHY4_CL45VEN :: FORCE_LINK :: FORCE_LNK_10GBASET_FDX [08:08] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x100,8,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x100,8)
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_MASK      0x0100
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_ALIGN     0
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_BITS      1
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_10GBASET_FDX_SHIFT     8

/* BRPHY4_CL45VEN :: FORCE_LINK :: FORCE_LNK_1000BASET_FDX_HDX [07:07] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x80,7,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x80,7)
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_MASK 0x0080
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_ALIGN 0
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_BITS 1
#define BRPHY4_CL45VEN_FORCE_LINK_FORCE_LNK_1000BASET_FDX_HDX_SHIFT 7

/* BRPHY4_CL45VEN :: FORCE_LINK :: IGNORE_ACK2 [06:06] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x40,6,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_IGNORE_ACK2(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x40,6)
#define BRPHY4_CL45VEN_FORCE_LINK_IGNORE_ACK2_MASK                 0x0040
#define BRPHY4_CL45VEN_FORCE_LINK_IGNORE_ACK2_ALIGN                0
#define BRPHY4_CL45VEN_FORCE_LINK_IGNORE_ACK2_BITS                 1
#define BRPHY4_CL45VEN_FORCE_LINK_IGNORE_ACK2_SHIFT                6

/* BRPHY4_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_OK [05:05] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x20,5,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x20,5)
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_MASK       0x0020
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_ALIGN      0
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_BITS       1
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_OK_SHIFT      5

/* BRPHY4_CL45VEN :: FORCE_LINK :: LNK_FORCE_100BASET_RDY [04:04] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x10,4,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x10,4)
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_MASK      0x0010
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_ALIGN     0
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_BITS      1
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_100BASET_RDY_SHIFT     4

/* BRPHY4_CL45VEN :: FORCE_LINK :: DIS_REG7P0_BIT13_AUTO_UPDATE [03:03] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x8,3,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x8,3)
#define BRPHY4_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_MASK 0x0008
#define BRPHY4_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_ALIGN 0
#define BRPHY4_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_BITS 1
#define BRPHY4_CL45VEN_FORCE_LINK_DIS_REG7P0_BIT13_AUTO_UPDATE_SHIFT 3

/* BRPHY4_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_OK [02:02] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x4,2,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x4,2)
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_MASK        0x0004
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_ALIGN       0
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_BITS        1
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_OK_SHIFT       2

/* BRPHY4_CL45VEN :: FORCE_LINK :: LNK_FORCE_10BASET_RDY [01:01] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x2,1,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x2,1)
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_MASK       0x0002
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_ALIGN      0
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_BITS       1
#define BRPHY4_CL45VEN_FORCE_LINK_LNK_FORCE_10BASET_RDY_SHIFT      1

/* BRPHY4_CL45VEN :: FORCE_LINK :: LAST_PG_TO_EN [00:00] */
#define Wr_BRPHY4_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) WriteRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x1,0,x)
#define Rd_BRPHY4_CL45VEN_FORCE_LINK_LAST_PG_TO_EN(x) ReadRegBits16(BRPHY4_CL45VEN_FORCE_LINK,0x1,0)
#define BRPHY4_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_MASK               0x0001
#define BRPHY4_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_ALIGN              0
#define BRPHY4_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_BITS               1
#define BRPHY4_CL45VEN_FORCE_LINK_LAST_PG_TO_EN_SHIFT              0


/****************************************************************************
 * BRPHY4_CL45VEN :: SELECTIVE_RESET
 ***************************************************************************/
/* BRPHY4_CL45VEN :: SELECTIVE_RESET :: DSP_RESET [15:15] */
#define Wr_BRPHY4_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) WriteRegBits16(BRPHY4_CL45VEN_SELECTIVE_RESET,0x8000,15,x)
#define Rd_BRPHY4_CL45VEN_SELECTIVE_RESET_DSP_RESET(x) ReadRegBits16(BRPHY4_CL45VEN_SELECTIVE_RESET,0x8000,15)
#define BRPHY4_CL45VEN_SELECTIVE_RESET_DSP_RESET_MASK              0x8000
#define BRPHY4_CL45VEN_SELECTIVE_RESET_DSP_RESET_ALIGN             0
#define BRPHY4_CL45VEN_SELECTIVE_RESET_DSP_RESET_BITS              1
#define BRPHY4_CL45VEN_SELECTIVE_RESET_DSP_RESET_SHIFT             15

/* BRPHY4_CL45VEN :: SELECTIVE_RESET :: SM_DSP_RESET [14:14] */
#define Wr_BRPHY4_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) WriteRegBits16(BRPHY4_CL45VEN_SELECTIVE_RESET,0x4000,14,x)
#define Rd_BRPHY4_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET(x) ReadRegBits16(BRPHY4_CL45VEN_SELECTIVE_RESET,0x4000,14)
#define BRPHY4_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_MASK           0x4000
#define BRPHY4_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_ALIGN          0
#define BRPHY4_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_BITS           1
#define BRPHY4_CL45VEN_SELECTIVE_RESET_SM_DSP_RESET_SHIFT          14

/* BRPHY4_CL45VEN :: SELECTIVE_RESET :: reserved0 [13:08] */
#define BRPHY4_CL45VEN_SELECTIVE_RESET_RESERVED0_MASK              0x3f00
#define BRPHY4_CL45VEN_SELECTIVE_RESET_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_SELECTIVE_RESET_RESERVED0_BITS              6
#define BRPHY4_CL45VEN_SELECTIVE_RESET_RESERVED0_SHIFT             8

/* BRPHY4_CL45VEN :: SELECTIVE_RESET :: DIG100_RESET [07:07] */
#define Wr_BRPHY4_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) WriteRegBits16(BRPHY4_CL45VEN_SELECTIVE_RESET,0x80,7,x)
#define Rd_BRPHY4_CL45VEN_SELECTIVE_RESET_DIG100_RESET(x) ReadRegBits16(BRPHY4_CL45VEN_SELECTIVE_RESET,0x80,7)
#define BRPHY4_CL45VEN_SELECTIVE_RESET_DIG100_RESET_MASK           0x0080
#define BRPHY4_CL45VEN_SELECTIVE_RESET_DIG100_RESET_ALIGN          0
#define BRPHY4_CL45VEN_SELECTIVE_RESET_DIG100_RESET_BITS           1
#define BRPHY4_CL45VEN_SELECTIVE_RESET_DIG100_RESET_SHIFT          7

/* BRPHY4_CL45VEN :: SELECTIVE_RESET :: reserved1 [06:00] */
#define BRPHY4_CL45VEN_SELECTIVE_RESET_RESERVED1_MASK              0x007f
#define BRPHY4_CL45VEN_SELECTIVE_RESET_RESERVED1_ALIGN             0
#define BRPHY4_CL45VEN_SELECTIVE_RESET_RESERVED1_BITS              7
#define BRPHY4_CL45VEN_SELECTIVE_RESET_RESERVED1_SHIFT             0


/****************************************************************************
 * BRPHY4_CL45VEN :: TEST_FSM_EXT_NXT_PGS
 ***************************************************************************/
/* BRPHY4_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved0 [15:15] */
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_MASK         0x8000
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_ALIGN        0
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_BITS         1
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED0_SHIFT        15

/* BRPHY4_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_XMTR_STATE [14:12] */
#define Wr_BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) WriteRegBits16(BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12,x)
#define Rd_BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE(x) ReadRegBits16(BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x7000,12)
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_MASK    0x7000
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_ALIGN   0
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_BITS    3
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_XMTR_STATE_SHIFT   12

/* BRPHY4_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: reserved1 [11:11] */
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_MASK         0x0800
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_ALIGN        0
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_BITS         1
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_RESERVED1_SHIFT        11

/* BRPHY4_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: XNP_RCVR_STATE [10:08] */
#define Wr_BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) WriteRegBits16(BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8,x)
#define Rd_BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE(x) ReadRegBits16(BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS,0x700,8)
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_MASK    0x0700
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_ALIGN   0
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_BITS    3
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_XNP_RCVR_STATE_SHIFT   8

/* BRPHY4_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: ARB_STATE [07:04] */
#define Wr_BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) WriteRegBits16(BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4,x)
#define Rd_BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE(x) ReadRegBits16(BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf0,4)
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_MASK         0x00f0
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_ALIGN        0
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_BITS         4
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_ARB_STATE_SHIFT        4

/* BRPHY4_CL45VEN :: TEST_FSM_EXT_NXT_PGS :: HCD_STATE [03:00] */
#define Wr_BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) WriteRegBits16(BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0,x)
#define Rd_BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE(x) ReadRegBits16(BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS,0xf,0)
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_MASK         0x000f
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_ALIGN        0
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_BITS         4
#define BRPHY4_CL45VEN_TEST_FSM_EXT_NXT_PGS_HCD_STATE_SHIFT        0


/****************************************************************************
 * BRPHY4_CL45VEN :: TEST_FSM_NXT_PGS
 ***************************************************************************/
/* BRPHY4_CL45VEN :: TEST_FSM_NXT_PGS :: reserved0 [15:10] */
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_MASK             0xfc00
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_ALIGN            0
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_BITS             6
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_RESERVED0_SHIFT            10

/* BRPHY4_CL45VEN :: TEST_FSM_NXT_PGS :: NP_XMTR_STATE [09:05] */
#define Wr_BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) WriteRegBits16(BRPHY4_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5,x)
#define Rd_BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE(x) ReadRegBits16(BRPHY4_CL45VEN_TEST_FSM_NXT_PGS,0x3e0,5)
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_MASK         0x03e0
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_ALIGN        0
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_BITS         5
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_XMTR_STATE_SHIFT        5

/* BRPHY4_CL45VEN :: TEST_FSM_NXT_PGS :: reserved1 [04:04] */
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_MASK             0x0010
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_ALIGN            0
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_BITS             1
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_RESERVED1_SHIFT            4

/* BRPHY4_CL45VEN :: TEST_FSM_NXT_PGS :: NP_RCVR_STATE [03:00] */
#define Wr_BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) WriteRegBits16(BRPHY4_CL45VEN_TEST_FSM_NXT_PGS,0xf,0,x)
#define Rd_BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE(x) ReadRegBits16(BRPHY4_CL45VEN_TEST_FSM_NXT_PGS,0xf,0)
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_MASK         0x000f
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_ALIGN        0
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_BITS         4
#define BRPHY4_CL45VEN_TEST_FSM_NXT_PGS_NP_RCVR_STATE_SHIFT        0


/****************************************************************************
 * BRPHY4_CL45VEN :: AN_MAN_TEST
 ***************************************************************************/
/* BRPHY4_CL45VEN :: AN_MAN_TEST :: reserved0 [15:12] */
#define BRPHY4_CL45VEN_AN_MAN_TEST_RESERVED0_MASK                  0xf000
#define BRPHY4_CL45VEN_AN_MAN_TEST_RESERVED0_ALIGN                 0
#define BRPHY4_CL45VEN_AN_MAN_TEST_RESERVED0_BITS                  4
#define BRPHY4_CL45VEN_AN_MAN_TEST_RESERVED0_SHIFT                 12

/* BRPHY4_CL45VEN :: AN_MAN_TEST :: LP_PG_TO_CAPTURE [11:08] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_TEST,0xf00,8,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_TEST,0xf00,8)
#define BRPHY4_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_MASK           0x0f00
#define BRPHY4_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_ALIGN          0
#define BRPHY4_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_BITS           4
#define BRPHY4_CL45VEN_AN_MAN_TEST_LP_PG_TO_CAPTURE_SHIFT          8

/* BRPHY4_CL45VEN :: AN_MAN_TEST :: reserved1 [07:03] */
#define BRPHY4_CL45VEN_AN_MAN_TEST_RESERVED1_MASK                  0x00f8
#define BRPHY4_CL45VEN_AN_MAN_TEST_RESERVED1_ALIGN                 0
#define BRPHY4_CL45VEN_AN_MAN_TEST_RESERVED1_BITS                  5
#define BRPHY4_CL45VEN_AN_MAN_TEST_RESERVED1_SHIFT                 3

/* BRPHY4_CL45VEN :: AN_MAN_TEST :: LNK_PARTNR_NXT_PG_TEST_MODE [02:02] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_TEST,0x4,2,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_TEST,0x4,2)
#define BRPHY4_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_MASK 0x0004
#define BRPHY4_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_TEST_LNK_PARTNR_NXT_PG_TEST_MODE_SHIFT 2

/* BRPHY4_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN_SEED [01:01] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_TEST,0x2,1,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_TEST,0x2,1)
#define BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_MASK           0x0002
#define BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_ALIGN          0
#define BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_BITS           1
#define BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SEED_SHIFT          1

/* BRPHY4_CL45VEN :: AN_MAN_TEST :: MAN_TEST_EN [00:00] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_TEST,0x1,0,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_TEST,0x1,0)
#define BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_MASK                0x0001
#define BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_ALIGN               0
#define BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_BITS                1
#define BRPHY4_CL45VEN_AN_MAN_TEST_MAN_TEST_EN_SHIFT               0


/****************************************************************************
 * BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A
 ***************************************************************************/
/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_HDX [15:15] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x8000,15)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_MASK 0x8000
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_HDX_SHIFT 15

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_1000TX_FDX [14:14] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x4000,14)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_MASK 0x4000
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_1000TX_FDX_SHIFT 14

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_PORT_TYPE [13:13] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x2000,13)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_MASK 0x2000
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_PORT_TYPE_SHIFT 13

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_CONFIG_VALUE [12:12] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x1000,12)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_MASK 0x1000
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_CONFIG_VALUE_SHIFT 12

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_MS_MANUAL_CONFIG_EN [11:11] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x800,11)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_MASK 0x0800
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_MS_MANUAL_CONFIG_EN_SHIFT 11

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_A :: MAN_LP_SEED [10:00] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A,0x7ff,0)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_MASK    0x07ff
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_ALIGN   0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_BITS    11
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_A_MAN_LP_SEED_SHIFT   0


/****************************************************************************
 * BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B
 ***************************************************************************/
/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved0 [15:05] */
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_MASK      0xffe0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_ALIGN     0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_BITS      11
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED0_SHIFT     5

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PMA_TRAINING_RESET_REQ [04:04] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x10,4)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_MASK 0x0010
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PMA_TRAINING_RESET_REQ_SHIFT 4

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: reserved1 [03:03] */
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_MASK      0x0008
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_ALIGN     0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_BITS      1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_RESERVED1_SHIFT     3

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_PHY_SHORT_REACH_MODE [02:02] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x4,2)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_MASK 0x0004
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_PHY_SHORT_REACH_MODE_SHIFT 2

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_LOOP_TIMING_ABILITY [01:01] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x2,1)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_MASK 0x0002
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_LOOP_TIMING_ABILITY_SHIFT 1

/* BRPHY4_CL45VEN :: AN_MAN_LNK_PARTNR_ABI_B :: MAN_LP_10GBASET_CAPABILITY [00:00] */
#define Wr_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) WriteRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0,x)
#define Rd_BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY(x) ReadRegBits16(BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B,0x1,0)
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_MASK 0x0001
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_ALIGN 0
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_BITS 1
#define BRPHY4_CL45VEN_AN_MAN_LNK_PARTNR_ABI_B_MAN_LP_10GBASET_CAPABILITY_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_A
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_A :: LP_NP_A [15:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) WriteReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_A,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A(x) ReadReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_A)
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_MASK            0xffff
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_ALIGN           0
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_BITS            16
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_A_LP_NP_A_SHIFT           0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_B
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_B :: LP_NP_B [15:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) WriteReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_B,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B(x) ReadReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_B)
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_MASK            0xffff
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_ALIGN           0
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_BITS            16
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_B_LP_NP_B_SHIFT           0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_C
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_C :: LP_NP_C [15:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) WriteReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_C,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C(x) ReadReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_C)
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_MASK            0xffff
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_ALIGN           0
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_BITS            16
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_C_LP_NP_C_SHIFT           0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_D
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_D :: LP_NP_D [15:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) WriteReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_D,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D(x) ReadReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_D)
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_MASK            0xffff
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_ALIGN           0
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_BITS            16
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_D_LP_NP_D_SHIFT           0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_E
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_E :: LP_NP_E [15:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) WriteReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_E,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E(x) ReadReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_E)
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_MASK            0xffff
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_ALIGN           0
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_BITS            16
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_E_LP_NP_E_SHIFT           0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_F
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_NXT_PG_F :: LP_NP_F [15:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) WriteReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_F,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F(x) ReadReg16(BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_F)
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_MASK            0xffff
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_ALIGN           0
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_BITS            16
#define BRPHY4_CL45VEN_LNK_PARTNR_NXT_PG_F_LP_NP_F_SHIFT           0


/****************************************************************************
 * BRPHY4_CL45VEN :: EPON_CTRL_REG
 ***************************************************************************/
/* BRPHY4_CL45VEN :: EPON_CTRL_REG :: reserved0 [15:10] */
#define BRPHY4_CL45VEN_EPON_CTRL_REG_RESERVED0_MASK                0xfc00
#define BRPHY4_CL45VEN_EPON_CTRL_REG_RESERVED0_ALIGN               0
#define BRPHY4_CL45VEN_EPON_CTRL_REG_RESERVED0_BITS                6
#define BRPHY4_CL45VEN_EPON_CTRL_REG_RESERVED0_SHIFT               10

/* BRPHY4_CL45VEN :: EPON_CTRL_REG :: EPON_MODE [09:09] */
#define Wr_BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) WriteRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x200,9,x)
#define Rd_BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE(x) ReadRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x200,9)
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_MASK                0x0200
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_ALIGN               0
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_BITS                1
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_SHIFT               9

/* BRPHY4_CL45VEN :: EPON_CTRL_REG :: EOC_PACKET_NORM [08:08] */
#define Wr_BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) WriteRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x100,8,x)
#define Rd_BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM(x) ReadRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x100,8)
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_MASK          0x0100
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_ALIGN         0
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_BITS          1
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_PACKET_NORM_SHIFT         8

/* BRPHY4_CL45VEN :: EPON_CTRL_REG :: EPON_MODE_CRCCHECK [07:07] */
#define Wr_BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) WriteRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x80,7,x)
#define Rd_BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK(x) ReadRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x80,7)
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_MASK       0x0080
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_ALIGN      0
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_BITS       1
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EPON_MODE_CRCCHECK_SHIFT      7

/* BRPHY4_CL45VEN :: EPON_CTRL_REG :: TX_EN_EXTEND [06:06] */
#define Wr_BRPHY4_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) WriteRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x40,6,x)
#define Rd_BRPHY4_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND(x) ReadRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x40,6)
#define BRPHY4_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_MASK             0x0040
#define BRPHY4_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_ALIGN            0
#define BRPHY4_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_BITS             1
#define BRPHY4_CL45VEN_EPON_CTRL_REG_TX_EN_EXTEND_SHIFT            6

/* BRPHY4_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POLARITY [05:05] */
#define Wr_BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) WriteRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x20,5,x)
#define Rd_BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY(x) ReadRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x20,5)
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_MASK        0x0020
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_ALIGN       0
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_BITS        1
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POLARITY_SHIFT       5

/* BRPHY4_CL45VEN :: EPON_CTRL_REG :: EOC_MODE_POL_CORR [04:04] */
#define Wr_BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) WriteRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x10,4,x)
#define Rd_BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR(x) ReadRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0x10,4)
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_MASK        0x0010
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_ALIGN       0
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_BITS        1
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_MODE_POL_CORR_SHIFT       4

/* BRPHY4_CL45VEN :: EPON_CTRL_REG :: EOC_SPEED_DET_THLD [03:00] */
#define Wr_BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) WriteRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0xf,0,x)
#define Rd_BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD(x) ReadRegBits16(BRPHY4_CL45VEN_EPON_CTRL_REG,0xf,0)
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_MASK       0x000f
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_ALIGN      0
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_BITS       4
#define BRPHY4_CL45VEN_EPON_CTRL_REG_EOC_SPEED_DET_THLD_SHIFT      0


/****************************************************************************
 * BRPHY4_CL45VEN :: EEE_TEST_CTRL_A
 ***************************************************************************/
/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: reserved0 [15:12] */
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_MASK              0xf000
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_BITS              4
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_RESERVED0_SHIFT             12

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_RX_EN [11:11] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x800,11,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x800,11)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_MASK        0x0800
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_ALIGN       0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_BITS        1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_RX_EN_SHIFT       11

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10XNP_TX_EN [10:10] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x400,10,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x400,10)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_MASK        0x0400
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_ALIGN       0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_BITS        1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10XNP_TX_EN_SHIFT       10

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_RX_EN [09:09] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x200,9,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x200,9)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_MASK           0x0200
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_ALIGN          0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_BITS           1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_RX_EN_SHIFT          9

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: MSG_10_TX_EN [08:08] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x100,8,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x100,8)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_MASK           0x0100
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_ALIGN          0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_BITS           1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_10_TX_EN_SHIFT          8

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: LPI_GPCS_TEST_BUS_EN [07:07] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x80,7,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x80,7)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_MASK   0x0080
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_ALIGN  0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_BITS   1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_LPI_GPCS_TEST_BUS_EN_SHIFT  7

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: MACSEC_PK_MODE [06:06] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x40,6,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x40,6)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_MASK         0x0040
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_ALIGN        0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_BITS         1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MACSEC_PK_MODE_SHIFT        6

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: MSG_11_VS_10 [05:05] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x20,5,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x20,5)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_MASK           0x0020
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_ALIGN          0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_BITS           1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_11_VS_10_SHIFT          5

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE [04:04] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x10,4,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x10,4)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_MASK              0x0010
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_ALIGN             0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_BITS              1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFT             4

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: MSG_9_EEE_SHIFTED [03:03] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x8,3,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x8,3)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_MASK      0x0008
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_ALIGN     0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_BITS      1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_MSG_9_EEE_SHIFTED_SHIFT     3

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: reserved1 [02:02] */
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_MASK              0x0004
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_ALIGN             0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_BITS              1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_RESERVED1_SHIFT             2

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LP_M10 [01:01] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x2,1,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x2,1)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_MASK        0x0002
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_ALIGN       0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_BITS        1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LP_M10_SHIFT       1

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_A :: OVERRIDE_LD_M10 [00:00] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x1,0,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_A,0x1,0)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_MASK        0x0001
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_ALIGN       0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_BITS        1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_A_OVERRIDE_LD_M10_SHIFT       0


/****************************************************************************
 * BRPHY4_CL45VEN :: EEE_TEST_CTRL_B
 ***************************************************************************/
/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x8000,15,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x8000,15)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_MASK         0x8000
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_ALIGN        0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_BITS         1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_SHIFT        15

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x4000,14,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x4000,14)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_MASK 0x4000
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_ALIGN 0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_BITS 1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LPI_FEATURE_EN_DIG1000X_SHIFT 14

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_LPI_QUALIFIERS [13:13] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x2000,13,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x2000,13)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_MASK 0x2000
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_ALIGN 0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_BITS 1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_LPI_QUALIFIERS_SHIFT 13

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: EN_TEST_MODE_FOR_REG_3_20 [12:12] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x1000,12,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x1000,12)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_MASK 0x1000
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_ALIGN 0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_BITS 1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_TEST_MODE_FOR_REG_3_20_SHIFT 12

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_RES [11:11] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x800,11,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x800,11)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_MASK       0x0800
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_ALIGN      0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_BITS       1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_RES_SHIFT      11

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: EN_10BASE_TE_10BASE_T_RES [10:10] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x400,10,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x400,10)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_MASK 0x0400
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_ALIGN 0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_BITS 1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_10BASE_TE_10BASE_T_RES_SHIFT 10

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: DET_SEND_Z [09:09] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x200,9,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x200,9)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_MASK             0x0200
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_ALIGN            0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_BITS             1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_DET_SEND_Z_SHIFT            9

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: EN_DET_SEND_Z_OVERRIDE [08:08] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x100,8,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x100,8)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_MASK 0x0100
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_ALIGN 0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_BITS 1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_DET_SEND_Z_OVERRIDE_SHIFT 8

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: REM_UPD_DONE_TEST [07:07] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x80,7,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x80,7)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_MASK      0x0080
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_ALIGN     0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_BITS      1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_UPD_DONE_TEST_SHIFT     7

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: REM_LPI_REQ_TEST [06:06] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x40,6,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x40,6)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_MASK       0x0040
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_ALIGN      0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_BITS       1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_REM_LPI_REQ_TEST_SHIFT      6

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: LOC_UPD_DONE_TEST [05:05] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x20,5,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x20,5)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_MASK      0x0020
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_ALIGN     0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_BITS      1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_UPD_DONE_TEST_SHIFT     5

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: LOC_LPI_REQ_TEST [04:04] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x10,4,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x10,4)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_MASK       0x0010
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_ALIGN      0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_BITS       1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_LOC_LPI_REQ_TEST_SHIFT      4

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_UPD_DONE_OVERRIDE [03:03] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x8,3,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x8,3)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_MASK 0x0008
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_UPD_DONE_OVERRIDE_SHIFT 3

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: EN_REM_LPI_REQ_OVERRIDE [02:02] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x4,2,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x4,2)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_MASK 0x0004
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_REM_LPI_REQ_OVERRIDE_SHIFT 2

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_UPD_DONE_OVERRIDE [01:01] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x2,1,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x2,1)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_MASK 0x0002
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_ALIGN 0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_BITS 1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_UPD_DONE_OVERRIDE_SHIFT 1

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_B :: EN_LOC_LPI_REQ_OVERRIDE [00:00] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x1,0,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_B,0x1,0)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_MASK 0x0001
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_ALIGN 0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_BITS 1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_B_EN_LOC_LPI_REQ_OVERRIDE_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: EEE_TEST_CTRL_C
 ***************************************************************************/
/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_RX_EN [15:15] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x8000,15,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x8000,15)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_MASK        0x8000
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_ALIGN       0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_BITS        1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_RX_EN_SHIFT       15

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_XNP_TX_EN [14:14] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x4000,14,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x4000,14)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_MASK        0x4000
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_ALIGN       0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_BITS        1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_XNP_TX_EN_SHIFT       14

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_RX_EN [13:13] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x2000,13,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x2000,13)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_MASK            0x2000
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_ALIGN           0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_BITS            1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_RX_EN_SHIFT           13

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_C :: MSG_6_TX_EN [12:12] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x1000,12,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x1000,12)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_MASK            0x1000
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_ALIGN           0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_BITS            1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_6_TX_EN_SHIFT           12

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_RX_EN [11:11] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x800,11,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x800,11)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_MASK        0x0800
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_ALIGN       0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_BITS        1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_RX_EN_SHIFT       11

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_XNP_TX_EN [10:10] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x400,10,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x400,10)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_MASK        0x0400
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_ALIGN       0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_BITS        1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_XNP_TX_EN_SHIFT       10

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_RX_EN [09:09] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x200,9,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x200,9)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_MASK            0x0200
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_ALIGN           0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_BITS            1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_RX_EN_SHIFT           9

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_C :: MSG_5_TX_EN [08:08] */
#define Wr_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x100,8,x)
#define Rd_BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_TEST_CTRL_C,0x100,8)
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_MASK            0x0100
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_ALIGN           0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_BITS            1
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_MSG_5_TX_EN_SHIFT           8

/* BRPHY4_CL45VEN :: EEE_TEST_CTRL_C :: reserved0 [07:00] */
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_MASK              0x00ff
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_BITS              8
#define BRPHY4_CL45VEN_EEE_TEST_CTRL_C_RESERVED0_SHIFT             0


/****************************************************************************
 * BRPHY4_CL45VEN :: EEE_SPARE_1
 ***************************************************************************/
/* BRPHY4_CL45VEN :: EEE_SPARE_1 :: SPARE [15:00] */
#define Wr_BRPHY4_CL45VEN_EEE_SPARE_1_SPARE(x) WriteReg16(BRPHY4_CL45VEN_EEE_SPARE_1,x)
#define Rd_BRPHY4_CL45VEN_EEE_SPARE_1_SPARE(x) ReadReg16(BRPHY4_CL45VEN_EEE_SPARE_1)
#define BRPHY4_CL45VEN_EEE_SPARE_1_SPARE_MASK                      0xffff
#define BRPHY4_CL45VEN_EEE_SPARE_1_SPARE_ALIGN                     0
#define BRPHY4_CL45VEN_EEE_SPARE_1_SPARE_BITS                      16
#define BRPHY4_CL45VEN_EEE_SPARE_1_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY4_CL45VEN :: EEE_SPARE_2
 ***************************************************************************/
/* BRPHY4_CL45VEN :: EEE_SPARE_2 :: SPARE [15:00] */
#define Wr_BRPHY4_CL45VEN_EEE_SPARE_2_SPARE(x) WriteReg16(BRPHY4_CL45VEN_EEE_SPARE_2,x)
#define Rd_BRPHY4_CL45VEN_EEE_SPARE_2_SPARE(x) ReadReg16(BRPHY4_CL45VEN_EEE_SPARE_2)
#define BRPHY4_CL45VEN_EEE_SPARE_2_SPARE_MASK                      0xffff
#define BRPHY4_CL45VEN_EEE_SPARE_2_SPARE_ALIGN                     0
#define BRPHY4_CL45VEN_EEE_SPARE_2_SPARE_BITS                      16
#define BRPHY4_CL45VEN_EEE_SPARE_2_SPARE_SHIFT                     0


/****************************************************************************
 * BRPHY4_CL45VEN :: EEE_CONTROL
 ***************************************************************************/
/* BRPHY4_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN [15:15] */
#define Wr_BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x8000,15,x)
#define Rd_BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x8000,15)
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_MASK             0x8000
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_ALIGN            0
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_BITS             1
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_SHIFT            15

/* BRPHY4_CL45VEN :: EEE_CONTROL :: LPI_FEATURE_EN_DIG1000X [14:14] */
#define Wr_BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x4000,14,x)
#define Rd_BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x4000,14)
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_MASK    0x4000
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_ALIGN   0
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_BITS    1
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_FEATURE_EN_DIG1000X_SHIFT   14

/* BRPHY4_CL45VEN :: EEE_CONTROL :: LPI_RES_IN_FORCE_MODE_EN [13:13] */
#define Wr_BRPHY4_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x2000,13,x)
#define Rd_BRPHY4_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x2000,13)
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_MASK   0x2000
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_ALIGN  0
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_BITS   1
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_RES_IN_FORCE_MODE_EN_SHIFT  13

/* BRPHY4_CL45VEN :: EEE_CONTROL :: SPARE [12:03] */
#define Wr_BRPHY4_CL45VEN_EEE_CONTROL_SPARE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x1ff8,3,x)
#define Rd_BRPHY4_CL45VEN_EEE_CONTROL_SPARE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x1ff8,3)
#define BRPHY4_CL45VEN_EEE_CONTROL_SPARE_MASK                      0x1ff8
#define BRPHY4_CL45VEN_EEE_CONTROL_SPARE_ALIGN                     0
#define BRPHY4_CL45VEN_EEE_CONTROL_SPARE_BITS                      10
#define BRPHY4_CL45VEN_EEE_CONTROL_SPARE_SHIFT                     3

/* BRPHY4_CL45VEN :: EEE_CONTROL :: LPI_LINKUP_DISABLE [02:02] */
#define Wr_BRPHY4_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x4,2,x)
#define Rd_BRPHY4_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x4,2)
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_MASK         0x0004
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_ALIGN        0
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_BITS         1
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_LINKUP_DISABLE_SHIFT        2

/* BRPHY4_CL45VEN :: EEE_CONTROL :: EEE_DOWNGRADE_ENABLE [01:01] */
#define Wr_BRPHY4_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x2,1,x)
#define Rd_BRPHY4_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x2,1)
#define BRPHY4_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_MASK       0x0002
#define BRPHY4_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_ALIGN      0
#define BRPHY4_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_BITS       1
#define BRPHY4_CL45VEN_EEE_CONTROL_EEE_DOWNGRADE_ENABLE_SHIFT      1

/* BRPHY4_CL45VEN :: EEE_CONTROL :: LPI_100TX_BRCM_LINK [00:00] */
#define Wr_BRPHY4_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x1,0,x)
#define Rd_BRPHY4_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_CONTROL,0x1,0)
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_MASK        0x0001
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_ALIGN       0
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_BITS        1
#define BRPHY4_CL45VEN_EEE_CONTROL_LPI_100TX_BRCM_LINK_SHIFT       0


/****************************************************************************
 * BRPHY4_CL45VEN :: EEE_RES_STAT
 ***************************************************************************/
/* BRPHY4_CL45VEN :: EEE_RES_STAT :: reserved0 [15:07] */
#define BRPHY4_CL45VEN_EEE_RES_STAT_RESERVED0_MASK                 0xff80
#define BRPHY4_CL45VEN_EEE_RES_STAT_RESERVED0_ALIGN                0
#define BRPHY4_CL45VEN_EEE_RES_STAT_RESERVED0_BITS                 9
#define BRPHY4_CL45VEN_EEE_RES_STAT_RESERVED0_SHIFT                7

/* BRPHY4_CL45VEN :: EEE_RES_STAT :: MASK_1000T_EEE [06:06] */
#define Wr_BRPHY4_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x40,6,x)
#define Rd_BRPHY4_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x40,6)
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_MASK            0x0040
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_ALIGN           0
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_BITS            1
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_1000T_EEE_SHIFT           6

/* BRPHY4_CL45VEN :: EEE_RES_STAT :: MASK_100TX_EEE [05:05] */
#define Wr_BRPHY4_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x20,5,x)
#define Rd_BRPHY4_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x20,5)
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_MASK            0x0020
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_ALIGN           0
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_BITS            1
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_100TX_EEE_SHIFT           5

/* BRPHY4_CL45VEN :: EEE_RES_STAT :: MASK_10T_EEE [04:04] */
#define Wr_BRPHY4_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x10,4,x)
#define Rd_BRPHY4_CL45VEN_EEE_RES_STAT_MASK_10T_EEE(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x10,4)
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_MASK              0x0010
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_ALIGN             0
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_BITS              1
#define BRPHY4_CL45VEN_EEE_RES_STAT_MASK_10T_EEE_SHIFT             4

/* BRPHY4_CL45VEN :: EEE_RES_STAT :: reserved1 [03:03] */
#define BRPHY4_CL45VEN_EEE_RES_STAT_RESERVED1_MASK                 0x0008
#define BRPHY4_CL45VEN_EEE_RES_STAT_RESERVED1_ALIGN                0
#define BRPHY4_CL45VEN_EEE_RES_STAT_RESERVED1_BITS                 1
#define BRPHY4_CL45VEN_EEE_RES_STAT_RESERVED1_SHIFT                3

/* BRPHY4_CL45VEN :: EEE_RES_STAT :: EEE_1000T_RES [02:02] */
#define Wr_BRPHY4_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x4,2,x)
#define Rd_BRPHY4_CL45VEN_EEE_RES_STAT_EEE_1000T_RES(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x4,2)
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_MASK             0x0004
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_ALIGN            0
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_BITS             1
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_1000T_RES_SHIFT            2

/* BRPHY4_CL45VEN :: EEE_RES_STAT :: EEE_100TX_RES [01:01] */
#define Wr_BRPHY4_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x2,1,x)
#define Rd_BRPHY4_CL45VEN_EEE_RES_STAT_EEE_100TX_RES(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x2,1)
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_MASK             0x0002
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_ALIGN            0
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_BITS             1
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_100TX_RES_SHIFT            1

/* BRPHY4_CL45VEN :: EEE_RES_STAT :: EEE_10BASE_TE_RES [00:00] */
#define Wr_BRPHY4_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) WriteRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x1,0,x)
#define Rd_BRPHY4_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES(x) ReadRegBits16(BRPHY4_CL45VEN_EEE_RES_STAT,0x1,0)
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_MASK         0x0001
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_ALIGN        0
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_BITS         1
#define BRPHY4_CL45VEN_EEE_RES_STAT_EEE_10BASE_TE_RES_SHIFT        0


/****************************************************************************
 * BRPHY4_CL45VEN :: LPI_MODE_CNTR
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LPI_MODE_CNTR :: LPI_MODE_COUNTER [15:00] */
#define Wr_BRPHY4_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) WriteReg16(BRPHY4_CL45VEN_LPI_MODE_CNTR,x)
#define Rd_BRPHY4_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER(x) ReadReg16(BRPHY4_CL45VEN_LPI_MODE_CNTR)
#define BRPHY4_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_MASK         0xffff
#define BRPHY4_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_ALIGN        0
#define BRPHY4_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_BITS         16
#define BRPHY4_CL45VEN_LPI_MODE_CNTR_LPI_MODE_COUNTER_SHIFT        0


/****************************************************************************
 * BRPHY4_CL45VEN :: LOC_DEV_MSG_5_A
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LOC_DEV_MSG_5_A :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_MASK              0xf800
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_BITS              5
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_RESERVED0_SHIFT             11

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_5_A :: BITS_10_0_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_5_A,0x7ff,0)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_A_BITS_10_0_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LOC_DEV_MSG_5_B
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LOC_DEV_MSG_5_B :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_MASK              0xf800
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_BITS              5
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_RESERVED0_SHIFT             11

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_5_B :: BITS_21_11_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_5_B,0x7ff,0)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_B_BITS_21_11_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LOC_DEV_MSG_5_C
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LOC_DEV_MSG_5_C :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_MASK              0xf800
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_BITS              5
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_RESERVED0_SHIFT             11

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_5_C :: BITS_32_22_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_5_C,0x7ff,0)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_C_BITS_32_22_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LOC_DEV_MSG_5_D
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LOC_DEV_MSG_5_D :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_MASK              0xf800
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_BITS              5
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_RESERVED0_SHIFT             11

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_5_D :: BITS_43_33_OF_LOC_DEV_MSG_5 [10:00] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_5_D,0x7ff,0)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_MASK 0x07ff
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_BITS 11
#define BRPHY4_CL45VEN_LOC_DEV_MSG_5_D_BITS_43_33_OF_LOC_DEV_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_A
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_A :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_MASK           0xf800
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_ALIGN          0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_BITS           5
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_RESERVED0_SHIFT          11

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_A :: BITS_10_0_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A,0x7ff,0)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_A_BITS_10_0_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_B
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_B :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_MASK           0xf800
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_ALIGN          0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_BITS           5
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_RESERVED0_SHIFT          11

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_B :: BITS_21_11_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B,0x7ff,0)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_B_BITS_21_11_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_C
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_C :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_MASK           0xf800
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_ALIGN          0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_BITS           5
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_RESERVED0_SHIFT          11

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_C :: BITS_32_22_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C,0x7ff,0)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_C_BITS_32_22_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_D
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_D :: MSG_5_OUI_MATCH [15:15] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D,0x8000,15)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_MASK     0x8000
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_ALIGN    0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_BITS     1
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_MSG_5_OUI_MATCH_SHIFT    15

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_D :: reserved0 [14:11] */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_MASK           0x7800
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_ALIGN          0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_BITS           4
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_RESERVED0_SHIFT          11

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_5_D :: BITS_43_33_OF_LNK_PARTNR_MSG_5 [10:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D,0x7ff,0)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_MASK 0x07ff
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_ALIGN 0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_BITS 11
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_5_D_BITS_43_33_OF_LNK_PARTNR_MSG_5_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LOC_DEV_MSG_6_A
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_A :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_MASK              0xf800
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_BITS              5
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_RESERVED0_SHIFT             11

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_A :: BITS_10_0_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_A,0x7ff,0)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_A_BITS_10_0_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LOC_DEV_MSG_6_B
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_B :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_MASK              0xf800
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_BITS              5
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_RESERVED0_SHIFT             11

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_21_17_OF_LOC_DEV_MSG_6 [10:06] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_B,0x7c0,6)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_MASK 0x07c0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_BITS 5
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_21_17_OF_LOC_DEV_MSG_6_SHIFT 6

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_B :: BITS_16_11_OF_LOC_DEV_MSG_6 [05:00] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_B,0x3f,0)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_MASK 0x003f
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_BITS 6
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_B_BITS_16_11_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LOC_DEV_MSG_6_C
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_C :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_MASK              0xf800
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_BITS              5
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_RESERVED0_SHIFT             11

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_32_23_OF_LOC_DEV_MSG_6 [10:01] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_C,0x7fe,1)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_MASK 0x07fe
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_BITS 10
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_32_23_OF_LOC_DEV_MSG_6_SHIFT 1

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_C :: BITS_22_22_OF_LOC_DEV_MSG_6 [00:00] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_C,0x1,0,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_C,0x1,0)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_MASK 0x0001
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_BITS 1
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_C_BITS_22_22_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LOC_DEV_MSG_6_D
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_D :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_MASK              0xf800
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_ALIGN             0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_BITS              5
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_RESERVED0_SHIFT             11

/* BRPHY4_CL45VEN :: LOC_DEV_MSG_6_D :: BITS_43_33_OF_LOC_DEV_MSG_6 [10:00] */
#define Wr_BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LOC_DEV_MSG_6_D,0x7ff,0)
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_MASK 0x07ff
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_BITS 11
#define BRPHY4_CL45VEN_LOC_DEV_MSG_6_D_BITS_43_33_OF_LOC_DEV_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_A
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_A :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_MASK           0xf800
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_ALIGN          0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_BITS           5
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_RESERVED0_SHIFT          11

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_A :: BITS_10_0_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A,0x7ff,0)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_A_BITS_10_0_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_B
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_B :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_MASK           0xf800
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_ALIGN          0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_BITS           5
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_RESERVED0_SHIFT          11

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_B :: BITS_21_11_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B,0x7ff,0)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_B_BITS_21_11_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_C
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_C :: reserved0 [15:11] */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_MASK           0xf800
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_ALIGN          0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_BITS           5
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_RESERVED0_SHIFT          11

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_C :: BITS_32_22_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C,0x7ff,0)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_C_BITS_32_22_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_D
 ***************************************************************************/
/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_OUI_MATCH [15:15] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D,0x8000,15)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_MASK     0x8000
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_ALIGN    0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_BITS     1
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_OUI_MATCH_SHIFT    15

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_MODEL_MATCH [14:14] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D,0x4000,14)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_MASK   0x4000
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_ALIGN  0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_BITS   1
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_MODEL_MATCH_SHIFT  14

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_D :: MSG_6_REV_MATCH [13:13] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D,0x2000,13)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_MASK     0x2000
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_ALIGN    0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_BITS     1
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_MSG_6_REV_MATCH_SHIFT    13

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_D :: reserved0 [12:11] */
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_MASK           0x1800
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_ALIGN          0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_BITS           2
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_RESERVED0_SHIFT          11

/* BRPHY4_CL45VEN :: LNK_PARTNR_MSG_6_D :: BITS_43_33_OF_LNK_PARTNR_MSG_6 [10:00] */
#define Wr_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) WriteRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0,x)
#define Rd_BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6(x) ReadRegBits16(BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D,0x7ff,0)
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_MASK 0x07ff
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_ALIGN 0
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_BITS 11
#define BRPHY4_CL45VEN_LNK_PARTNR_MSG_6_D_BITS_43_33_OF_LNK_PARTNR_MSG_6_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_GPHY_CORE
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE10
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE10 :: MAC_PHY_IF [15:15] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_MAC_PHY_IF(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_MAC_PHY_IF(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x8000,15)
#define BRPHY4_GPHY_CORE_BASE10_MAC_PHY_IF_MASK                    0x8000
#define BRPHY4_GPHY_CORE_BASE10_MAC_PHY_IF_ALIGN                   0
#define BRPHY4_GPHY_CORE_BASE10_MAC_PHY_IF_BITS                    1
#define BRPHY4_GPHY_CORE_BASE10_MAC_PHY_IF_SHIFT                   15

/* BRPHY4_GPHY_CORE :: BASE10 :: AUTO_MDIX_DIS [14:14] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_AUTO_MDIX_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x4000,14)
#define BRPHY4_GPHY_CORE_BASE10_AUTO_MDIX_DIS_MASK                 0x4000
#define BRPHY4_GPHY_CORE_BASE10_AUTO_MDIX_DIS_ALIGN                0
#define BRPHY4_GPHY_CORE_BASE10_AUTO_MDIX_DIS_BITS                 1
#define BRPHY4_GPHY_CORE_BASE10_AUTO_MDIX_DIS_SHIFT                14

/* BRPHY4_GPHY_CORE :: BASE10 :: TX_DIS [13:13] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_TX_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_TX_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x2000,13)
#define BRPHY4_GPHY_CORE_BASE10_TX_DIS_MASK                        0x2000
#define BRPHY4_GPHY_CORE_BASE10_TX_DIS_ALIGN                       0
#define BRPHY4_GPHY_CORE_BASE10_TX_DIS_BITS                        1
#define BRPHY4_GPHY_CORE_BASE10_TX_DIS_SHIFT                       13

/* BRPHY4_GPHY_CORE :: BASE10 :: INT_DIS [12:12] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_INT_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_INT_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x1000,12)
#define BRPHY4_GPHY_CORE_BASE10_INT_DIS_MASK                       0x1000
#define BRPHY4_GPHY_CORE_BASE10_INT_DIS_ALIGN                      0
#define BRPHY4_GPHY_CORE_BASE10_INT_DIS_BITS                       1
#define BRPHY4_GPHY_CORE_BASE10_INT_DIS_SHIFT                      12

/* BRPHY4_GPHY_CORE :: BASE10 :: FORCE_INT [11:11] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_FORCE_INT(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_FORCE_INT(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x800,11)
#define BRPHY4_GPHY_CORE_BASE10_FORCE_INT_MASK                     0x0800
#define BRPHY4_GPHY_CORE_BASE10_FORCE_INT_ALIGN                    0
#define BRPHY4_GPHY_CORE_BASE10_FORCE_INT_BITS                     1
#define BRPHY4_GPHY_CORE_BASE10_FORCE_INT_SHIFT                    11

/* BRPHY4_GPHY_CORE :: BASE10 :: BYPASS_ENCODER [10:10] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_BYPASS_ENCODER(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_BYPASS_ENCODER(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x400,10)
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_ENCODER_MASK                0x0400
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_ENCODER_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_ENCODER_BITS                1
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_ENCODER_SHIFT               10

/* BRPHY4_GPHY_CORE :: BASE10 :: BYPASS_SCRAMBLER [09:09] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_BYPASS_SCRAMBLER(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x200,9)
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_MASK              0x0200
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_ALIGN             0
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_BITS              1
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_SCRAMBLER_SHIFT             9

/* BRPHY4_GPHY_CORE :: BASE10 :: BYPASS_NRZI_MLT3 [08:08] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x100,8)
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_MASK              0x0100
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_ALIGN             0
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_BITS              1
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_NRZI_MLT3_SHIFT             8

/* BRPHY4_GPHY_CORE :: BASE10 :: BYPASS_ALIGNMENT [07:07] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_BYPASS_ALIGNMENT(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x80,7)
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_MASK              0x0080
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_ALIGN             0
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_BITS              1
#define BRPHY4_GPHY_CORE_BASE10_BYPASS_ALIGNMENT_SHIFT             7

/* BRPHY4_GPHY_CORE :: BASE10 :: RESET_SCRAMBLER [06:06] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_RESET_SCRAMBLER(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x40,6)
#define BRPHY4_GPHY_CORE_BASE10_RESET_SCRAMBLER_MASK               0x0040
#define BRPHY4_GPHY_CORE_BASE10_RESET_SCRAMBLER_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE10_RESET_SCRAMBLER_BITS               1
#define BRPHY4_GPHY_CORE_BASE10_RESET_SCRAMBLER_SHIFT              6

/* BRPHY4_GPHY_CORE :: BASE10 :: LED_TRAFFIC_EN [05:05] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_LED_TRAFFIC_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x20,5)
#define BRPHY4_GPHY_CORE_BASE10_LED_TRAFFIC_EN_MASK                0x0020
#define BRPHY4_GPHY_CORE_BASE10_LED_TRAFFIC_EN_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE10_LED_TRAFFIC_EN_BITS                1
#define BRPHY4_GPHY_CORE_BASE10_LED_TRAFFIC_EN_SHIFT               5

/* BRPHY4_GPHY_CORE :: BASE10 :: FORCE_LEDS_ON [04:04] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_ON(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x10,4)
#define BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_ON_MASK                 0x0010
#define BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_ON_ALIGN                0
#define BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_ON_BITS                 1
#define BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_ON_SHIFT                4

/* BRPHY4_GPHY_CORE :: BASE10 :: FORCE_LEDS_OFF [03:03] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_OFF(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x8,3)
#define BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_OFF_MASK                0x0008
#define BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_OFF_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_OFF_BITS                1
#define BRPHY4_GPHY_CORE_BASE10_FORCE_LEDS_OFF_SHIFT               3

/* BRPHY4_GPHY_CORE :: BASE10 :: BLOCK_TXEN [02:02] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_BLOCK_TXEN(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_BLOCK_TXEN(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x4,2)
#define BRPHY4_GPHY_CORE_BASE10_BLOCK_TXEN_MASK                    0x0004
#define BRPHY4_GPHY_CORE_BASE10_BLOCK_TXEN_ALIGN                   0
#define BRPHY4_GPHY_CORE_BASE10_BLOCK_TXEN_BITS                    1
#define BRPHY4_GPHY_CORE_BASE10_BLOCK_TXEN_SHIFT                   2

/* BRPHY4_GPHY_CORE :: BASE10 :: UNIDIR_EN [01:01] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_UNIDIR_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_UNIDIR_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x2,1)
#define BRPHY4_GPHY_CORE_BASE10_UNIDIR_EN_MASK                     0x0002
#define BRPHY4_GPHY_CORE_BASE10_UNIDIR_EN_ALIGN                    0
#define BRPHY4_GPHY_CORE_BASE10_UNIDIR_EN_BITS                     1
#define BRPHY4_GPHY_CORE_BASE10_UNIDIR_EN_SHIFT                    1

/* BRPHY4_GPHY_CORE :: BASE10 :: GMII_RGMII_FIFO_ELASTICITY [00:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE10,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE10,0x1,0)
#define BRPHY4_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_MASK    0x0001
#define BRPHY4_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_ALIGN   0
#define BRPHY4_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_BITS    1
#define BRPHY4_GPHY_CORE_BASE10_GMII_RGMII_FIFO_ELASTICITY_SHIFT   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE11
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE11 :: AUTONEG_FIELD_MISMATCH [15:15] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x8000,15)
#define BRPHY4_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_MASK        0x8000
#define BRPHY4_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_ALIGN       0
#define BRPHY4_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_BITS        1
#define BRPHY4_GPHY_CORE_BASE11_AUTONEG_FIELD_MISMATCH_SHIFT       15

/* BRPHY4_GPHY_CORE :: BASE11 :: WIRESPD_DOWNGRADE [14:14] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x4000,14)
#define BRPHY4_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_MASK             0x4000
#define BRPHY4_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_ALIGN            0
#define BRPHY4_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_BITS             1
#define BRPHY4_GPHY_CORE_BASE11_WIRESPD_DOWNGRADE_SHIFT            14

/* BRPHY4_GPHY_CORE :: BASE11 :: MDIX_STATE [13:13] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_MDIX_STATE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_MDIX_STATE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x2000,13)
#define BRPHY4_GPHY_CORE_BASE11_MDIX_STATE_MASK                    0x2000
#define BRPHY4_GPHY_CORE_BASE11_MDIX_STATE_ALIGN                   0
#define BRPHY4_GPHY_CORE_BASE11_MDIX_STATE_BITS                    1
#define BRPHY4_GPHY_CORE_BASE11_MDIX_STATE_SHIFT                   13

/* BRPHY4_GPHY_CORE :: BASE11 :: INT_STATUS [12:12] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_INT_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_INT_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x1000,12)
#define BRPHY4_GPHY_CORE_BASE11_INT_STATUS_MASK                    0x1000
#define BRPHY4_GPHY_CORE_BASE11_INT_STATUS_ALIGN                   0
#define BRPHY4_GPHY_CORE_BASE11_INT_STATUS_BITS                    1
#define BRPHY4_GPHY_CORE_BASE11_INT_STATUS_SHIFT                   12

/* BRPHY4_GPHY_CORE :: BASE11 :: RMT_RCVR_STATUS [11:11] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_RMT_RCVR_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x800,11)
#define BRPHY4_GPHY_CORE_BASE11_RMT_RCVR_STATUS_MASK               0x0800
#define BRPHY4_GPHY_CORE_BASE11_RMT_RCVR_STATUS_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE11_RMT_RCVR_STATUS_BITS               1
#define BRPHY4_GPHY_CORE_BASE11_RMT_RCVR_STATUS_SHIFT              11

/* BRPHY4_GPHY_CORE :: BASE11 :: LOCAL_RCVR_STATUS [10:10] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x400,10)
#define BRPHY4_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_MASK             0x0400
#define BRPHY4_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_ALIGN            0
#define BRPHY4_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_BITS             1
#define BRPHY4_GPHY_CORE_BASE11_LOCAL_RCVR_STATUS_SHIFT            10

/* BRPHY4_GPHY_CORE :: BASE11 :: LOCKED [09:09] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_LOCKED(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_LOCKED(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x200,9)
#define BRPHY4_GPHY_CORE_BASE11_LOCKED_MASK                        0x0200
#define BRPHY4_GPHY_CORE_BASE11_LOCKED_ALIGN                       0
#define BRPHY4_GPHY_CORE_BASE11_LOCKED_BITS                        1
#define BRPHY4_GPHY_CORE_BASE11_LOCKED_SHIFT                       9

/* BRPHY4_GPHY_CORE :: BASE11 :: LINK_STATUS [08:08] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_LINK_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_LINK_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x100,8)
#define BRPHY4_GPHY_CORE_BASE11_LINK_STATUS_MASK                   0x0100
#define BRPHY4_GPHY_CORE_BASE11_LINK_STATUS_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE11_LINK_STATUS_BITS                   1
#define BRPHY4_GPHY_CORE_BASE11_LINK_STATUS_SHIFT                  8

/* BRPHY4_GPHY_CORE :: BASE11 :: CRC_ERR_DET [07:07] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_CRC_ERR_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_CRC_ERR_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x80,7)
#define BRPHY4_GPHY_CORE_BASE11_CRC_ERR_DET_MASK                   0x0080
#define BRPHY4_GPHY_CORE_BASE11_CRC_ERR_DET_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE11_CRC_ERR_DET_BITS                   1
#define BRPHY4_GPHY_CORE_BASE11_CRC_ERR_DET_SHIFT                  7

/* BRPHY4_GPHY_CORE :: BASE11 :: CR_EXT_ERR_DET [06:06] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_CR_EXT_ERR_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x40,6)
#define BRPHY4_GPHY_CORE_BASE11_CR_EXT_ERR_DET_MASK                0x0040
#define BRPHY4_GPHY_CORE_BASE11_CR_EXT_ERR_DET_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE11_CR_EXT_ERR_DET_BITS                1
#define BRPHY4_GPHY_CORE_BASE11_CR_EXT_ERR_DET_SHIFT               6

/* BRPHY4_GPHY_CORE :: BASE11 :: BAD_SSD_DET_CR [05:05] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_BAD_SSD_DET_CR(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x20,5)
#define BRPHY4_GPHY_CORE_BASE11_BAD_SSD_DET_CR_MASK                0x0020
#define BRPHY4_GPHY_CORE_BASE11_BAD_SSD_DET_CR_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE11_BAD_SSD_DET_CR_BITS                1
#define BRPHY4_GPHY_CORE_BASE11_BAD_SSD_DET_CR_SHIFT               5

/* BRPHY4_GPHY_CORE :: BASE11 :: BAD_ESD_DET_END [04:04] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_BAD_ESD_DET_END(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x10,4)
#define BRPHY4_GPHY_CORE_BASE11_BAD_ESD_DET_END_MASK               0x0010
#define BRPHY4_GPHY_CORE_BASE11_BAD_ESD_DET_END_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE11_BAD_ESD_DET_END_BITS               1
#define BRPHY4_GPHY_CORE_BASE11_BAD_ESD_DET_END_SHIFT              4

/* BRPHY4_GPHY_CORE :: BASE11 :: RCV_ERR_DET [03:03] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_RCV_ERR_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_RCV_ERR_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x8,3)
#define BRPHY4_GPHY_CORE_BASE11_RCV_ERR_DET_MASK                   0x0008
#define BRPHY4_GPHY_CORE_BASE11_RCV_ERR_DET_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE11_RCV_ERR_DET_BITS                   1
#define BRPHY4_GPHY_CORE_BASE11_RCV_ERR_DET_SHIFT                  3

/* BRPHY4_GPHY_CORE :: BASE11 :: TX_ERR_DET [02:02] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_TX_ERR_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_TX_ERR_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x4,2)
#define BRPHY4_GPHY_CORE_BASE11_TX_ERR_DET_MASK                    0x0004
#define BRPHY4_GPHY_CORE_BASE11_TX_ERR_DET_ALIGN                   0
#define BRPHY4_GPHY_CORE_BASE11_TX_ERR_DET_BITS                    1
#define BRPHY4_GPHY_CORE_BASE11_TX_ERR_DET_SHIFT                   2

/* BRPHY4_GPHY_CORE :: BASE11 :: LOCK_ERR_DET [01:01] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_LOCK_ERR_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_LOCK_ERR_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x2,1)
#define BRPHY4_GPHY_CORE_BASE11_LOCK_ERR_DET_MASK                  0x0002
#define BRPHY4_GPHY_CORE_BASE11_LOCK_ERR_DET_ALIGN                 0
#define BRPHY4_GPHY_CORE_BASE11_LOCK_ERR_DET_BITS                  1
#define BRPHY4_GPHY_CORE_BASE11_LOCK_ERR_DET_SHIFT                 1

/* BRPHY4_GPHY_CORE :: BASE11 :: MLT3_ERR_DET [00:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE11_MLT3_ERR_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE11,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE11_MLT3_ERR_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE11,0x1,0)
#define BRPHY4_GPHY_CORE_BASE11_MLT3_ERR_DET_MASK                  0x0001
#define BRPHY4_GPHY_CORE_BASE11_MLT3_ERR_DET_ALIGN                 0
#define BRPHY4_GPHY_CORE_BASE11_MLT3_ERR_DET_BITS                  1
#define BRPHY4_GPHY_CORE_BASE11_MLT3_ERR_DET_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE12
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE12 :: RCV_ERR_CNTR [15:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) WriteReg16(BRPHY4_GPHY_CORE_BASE12,x)
#define Rd_BRPHY4_GPHY_CORE_BASE12_RCV_ERR_CNTR(x) ReadReg16(BRPHY4_GPHY_CORE_BASE12)
#define BRPHY4_GPHY_CORE_BASE12_RCV_ERR_CNTR_MASK                  0xffff
#define BRPHY4_GPHY_CORE_BASE12_RCV_ERR_CNTR_ALIGN                 0
#define BRPHY4_GPHY_CORE_BASE12_RCV_ERR_CNTR_BITS                  16
#define BRPHY4_GPHY_CORE_BASE12_RCV_ERR_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE13
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE13 :: SERDES_BER_CNTR [15:08] */
#define Wr_BRPHY4_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE13,0xff00,8,x)
#define Rd_BRPHY4_GPHY_CORE_BASE13_SERDES_BER_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE13,0xff00,8)
#define BRPHY4_GPHY_CORE_BASE13_SERDES_BER_CNTR_MASK               0xff00
#define BRPHY4_GPHY_CORE_BASE13_SERDES_BER_CNTR_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE13_SERDES_BER_CNTR_BITS               8
#define BRPHY4_GPHY_CORE_BASE13_SERDES_BER_CNTR_SHIFT              8

/* BRPHY4_GPHY_CORE :: BASE13 :: FALSE_CRS_CNTR [07:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE13,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE13_FALSE_CRS_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE13,0xff,0)
#define BRPHY4_GPHY_CORE_BASE13_FALSE_CRS_CNTR_MASK                0x00ff
#define BRPHY4_GPHY_CORE_BASE13_FALSE_CRS_CNTR_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE13_FALSE_CRS_CNTR_BITS                8
#define BRPHY4_GPHY_CORE_BASE13_FALSE_CRS_CNTR_SHIFT               0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE14
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE14 :: LOCAL_RCVR_NOK_CNTR [15:08] */
#define Wr_BRPHY4_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE14,0xff00,8,x)
#define Rd_BRPHY4_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE14,0xff00,8)
#define BRPHY4_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_MASK           0xff00
#define BRPHY4_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_ALIGN          0
#define BRPHY4_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_BITS           8
#define BRPHY4_GPHY_CORE_BASE14_LOCAL_RCVR_NOK_CNTR_SHIFT          8

/* BRPHY4_GPHY_CORE :: BASE14 :: REMOTE_RCVR_NOK_CNTR [07:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE14,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE14,0xff,0)
#define BRPHY4_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_MASK          0x00ff
#define BRPHY4_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_ALIGN         0
#define BRPHY4_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_BITS          8
#define BRPHY4_GPHY_CORE_BASE14_REMOTE_RCVR_NOK_CNTR_SHIFT         0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP45
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP45 :: SEL_SERDES_TX [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXP45_SEL_SERDES_TX(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP45,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXP45_SEL_SERDES_TX(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP45,0x8000,15)
#define BRPHY4_GPHY_CORE_EXP45_SEL_SERDES_TX_MASK                  0x8000
#define BRPHY4_GPHY_CORE_EXP45_SEL_SERDES_TX_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP45_SEL_SERDES_TX_BITS                  1
#define BRPHY4_GPHY_CORE_EXP45_SEL_SERDES_TX_SHIFT                 15

/* BRPHY4_GPHY_CORE :: EXP45 :: TX_ERR [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXP45_TX_ERR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP45,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXP45_TX_ERR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP45,0x4000,14)
#define BRPHY4_GPHY_CORE_EXP45_TX_ERR_MASK                         0x4000
#define BRPHY4_GPHY_CORE_EXP45_TX_ERR_ALIGN                        0
#define BRPHY4_GPHY_CORE_EXP45_TX_ERR_BITS                         1
#define BRPHY4_GPHY_CORE_EXP45_TX_ERR_SHIFT                        14

/* BRPHY4_GPHY_CORE :: EXP45 :: SKIP_CRC [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXP45_SKIP_CRC(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP45,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXP45_SKIP_CRC(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP45,0x2000,13)
#define BRPHY4_GPHY_CORE_EXP45_SKIP_CRC_MASK                       0x2000
#define BRPHY4_GPHY_CORE_EXP45_SKIP_CRC_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP45_SKIP_CRC_BITS                       1
#define BRPHY4_GPHY_CORE_EXP45_SKIP_CRC_SHIFT                      13

/* BRPHY4_GPHY_CORE :: EXP45 :: TX_CRC_CHECKER_EN [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP45,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP45,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_MASK              0x1000
#define BRPHY4_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_BITS              1
#define BRPHY4_GPHY_CORE_EXP45_TX_CRC_CHECKER_EN_SHIFT             12

/* BRPHY4_GPHY_CORE :: EXP45 :: IPG_SEL [11:09] */
#define Wr_BRPHY4_GPHY_CORE_EXP45_IPG_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP45,0xe00,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXP45_IPG_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP45,0xe00,9)
#define BRPHY4_GPHY_CORE_EXP45_IPG_SEL_MASK                        0x0e00
#define BRPHY4_GPHY_CORE_EXP45_IPG_SEL_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP45_IPG_SEL_BITS                        3
#define BRPHY4_GPHY_CORE_EXP45_IPG_SEL_SHIFT                       9

/* BRPHY4_GPHY_CORE :: EXP45 :: PKT_SIZE [08:03] */
#define Wr_BRPHY4_GPHY_CORE_EXP45_PKT_SIZE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP45,0x1f8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXP45_PKT_SIZE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP45,0x1f8,3)
#define BRPHY4_GPHY_CORE_EXP45_PKT_SIZE_MASK                       0x01f8
#define BRPHY4_GPHY_CORE_EXP45_PKT_SIZE_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP45_PKT_SIZE_BITS                       6
#define BRPHY4_GPHY_CORE_EXP45_PKT_SIZE_SHIFT                      3

/* BRPHY4_GPHY_CORE :: EXP45 :: SINGLE_PASS [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP45_SINGLE_PASS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP45,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP45_SINGLE_PASS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP45,0x4,2)
#define BRPHY4_GPHY_CORE_EXP45_SINGLE_PASS_MASK                    0x0004
#define BRPHY4_GPHY_CORE_EXP45_SINGLE_PASS_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP45_SINGLE_PASS_BITS                    1
#define BRPHY4_GPHY_CORE_EXP45_SINGLE_PASS_SHIFT                   2

/* BRPHY4_GPHY_CORE :: EXP45 :: RUN_PAT_GEN [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP45_RUN_PAT_GEN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP45,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP45_RUN_PAT_GEN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP45,0x2,1)
#define BRPHY4_GPHY_CORE_EXP45_RUN_PAT_GEN_MASK                    0x0002
#define BRPHY4_GPHY_CORE_EXP45_RUN_PAT_GEN_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP45_RUN_PAT_GEN_BITS                    1
#define BRPHY4_GPHY_CORE_EXP45_RUN_PAT_GEN_SHIFT                   1

/* BRPHY4_GPHY_CORE :: EXP45 :: SEL_PAT_GEN_DATA [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP45,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP45,0x1,0)
#define BRPHY4_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_MASK               0x0001
#define BRPHY4_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_BITS               1
#define BRPHY4_GPHY_CORE_EXP45_SEL_PAT_GEN_DATA_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP46
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP46 :: GMII_FIFO_ELASTICITY_1 [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP46,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP46,0x8000,15)
#define BRPHY4_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_MASK         0x8000
#define BRPHY4_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_ALIGN        0
#define BRPHY4_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_BITS         1
#define BRPHY4_GPHY_CORE_EXP46_GMII_FIFO_ELASTICITY_1_SHIFT        15

/* BRPHY4_GPHY_CORE :: EXP46 :: GMII_RGMII_FIFO_ELASTICITY_1 [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP46,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP46,0x4000,14)
#define BRPHY4_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_MASK   0x4000
#define BRPHY4_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_ALIGN  0
#define BRPHY4_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_BITS   1
#define BRPHY4_GPHY_CORE_EXP46_GMII_RGMII_FIFO_ELASTICITY_1_SHIFT  14

/* BRPHY4_GPHY_CORE :: EXP46 :: PKT_SIZE_6 [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXP46_PKT_SIZE_6(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP46,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXP46_PKT_SIZE_6(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP46,0x2000,13)
#define BRPHY4_GPHY_CORE_EXP46_PKT_SIZE_6_MASK                     0x2000
#define BRPHY4_GPHY_CORE_EXP46_PKT_SIZE_6_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP46_PKT_SIZE_6_BITS                     1
#define BRPHY4_GPHY_CORE_EXP46_PKT_SIZE_6_SHIFT                    13

/* BRPHY4_GPHY_CORE :: EXP46 :: CR_EXT [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP46_CR_EXT(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP46,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP46_CR_EXT(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP46,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP46_CR_EXT_MASK                         0x1000
#define BRPHY4_GPHY_CORE_EXP46_CR_EXT_ALIGN                        0
#define BRPHY4_GPHY_CORE_EXP46_CR_EXT_BITS                         1
#define BRPHY4_GPHY_CORE_EXP46_CR_EXT_SHIFT                        12

/* BRPHY4_GPHY_CORE :: EXP46 :: reserved0 [11:07] */
#define BRPHY4_GPHY_CORE_EXP46_RESERVED0_MASK                      0x0f80
#define BRPHY4_GPHY_CORE_EXP46_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP46_RESERVED0_BITS                      5
#define BRPHY4_GPHY_CORE_EXP46_RESERVED0_SHIFT                     7

/* BRPHY4_GPHY_CORE :: EXP46 :: RGMII_FIFO_FREQ_LOCK [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP46,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP46,0x40,6)
#define BRPHY4_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_MASK           0x0040
#define BRPHY4_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_ALIGN          0
#define BRPHY4_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_BITS           1
#define BRPHY4_GPHY_CORE_EXP46_RGMII_FIFO_FREQ_LOCK_SHIFT          6

/* BRPHY4_GPHY_CORE :: EXP46 :: reserved1 [05:05] */
#define BRPHY4_GPHY_CORE_EXP46_RESERVED1_MASK                      0x0020
#define BRPHY4_GPHY_CORE_EXP46_RESERVED1_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP46_RESERVED1_BITS                      1
#define BRPHY4_GPHY_CORE_EXP46_RESERVED1_SHIFT                     5

/* BRPHY4_GPHY_CORE :: EXP46 :: SEL_PATGEN_ON_RXD [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP46,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP46,0x10,4)
#define BRPHY4_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_MASK              0x0010
#define BRPHY4_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_BITS              1
#define BRPHY4_GPHY_CORE_EXP46_SEL_PATGEN_ON_RXD_SHIFT             4

/* BRPHY4_GPHY_CORE :: EXP46 :: PAT_GEN_ACTIVE [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP46,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXP46_PAT_GEN_ACTIVE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP46,0x8,3)
#define BRPHY4_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_MASK                 0x0008
#define BRPHY4_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_BITS                 1
#define BRPHY4_GPHY_CORE_EXP46_PAT_GEN_ACTIVE_SHIFT                3

/* BRPHY4_GPHY_CORE :: EXP46 :: PAT_GEN_FSM [02:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP46_PAT_GEN_FSM(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP46,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP46_PAT_GEN_FSM(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP46,0x7,0)
#define BRPHY4_GPHY_CORE_EXP46_PAT_GEN_FSM_MASK                    0x0007
#define BRPHY4_GPHY_CORE_EXP46_PAT_GEN_FSM_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP46_PAT_GEN_FSM_BITS                    3
#define BRPHY4_GPHY_CORE_EXP46_PAT_GEN_FSM_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE19
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE [15:15] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x8000,15)
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_MASK              0x8000
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ALIGN             0
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_BITS              1
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_SHIFT             15

/* BRPHY4_GPHY_CORE :: BASE19 :: AUTONEG_COMPLETE_ACK [14:14] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x4000,14)
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_MASK          0x4000
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_ALIGN         0
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_BITS          1
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_COMPLETE_ACK_SHIFT         14

/* BRPHY4_GPHY_CORE :: BASE19 :: AUTONEG_ACK_DET [13:13] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_AUTONEG_ACK_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x2000,13)
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_ACK_DET_MASK               0x2000
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_ACK_DET_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_ACK_DET_BITS               1
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_ACK_DET_SHIFT              13

/* BRPHY4_GPHY_CORE :: BASE19 :: AUTONEG_ABILITY_DET [12:12] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x1000,12)
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_MASK           0x1000
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_ALIGN          0
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_BITS           1
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_ABILITY_DET_SHIFT          12

/* BRPHY4_GPHY_CORE :: BASE19 :: AUTONEG_NEXT_PAGE_WAIT [11:11] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x800,11)
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_MASK        0x0800
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_ALIGN       0
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_BITS        1
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_NEXT_PAGE_WAIT_SHIFT       11

/* BRPHY4_GPHY_CORE :: BASE19 :: AUTONEG_HCD [10:08] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_AUTONEG_HCD(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x700,8,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_AUTONEG_HCD(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x700,8)
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_HCD_MASK                   0x0700
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_HCD_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_HCD_BITS                   3
#define BRPHY4_GPHY_CORE_BASE19_AUTONEG_HCD_SHIFT                  8

/* BRPHY4_GPHY_CORE :: BASE19 :: PARALLEL_DET_FAULT [07:07] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_PARALLEL_DET_FAULT(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x80,7)
#define BRPHY4_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_MASK            0x0080
#define BRPHY4_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_ALIGN           0
#define BRPHY4_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_BITS            1
#define BRPHY4_GPHY_CORE_BASE19_PARALLEL_DET_FAULT_SHIFT           7

/* BRPHY4_GPHY_CORE :: BASE19 :: REMOTE_FAULT [06:06] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_REMOTE_FAULT(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_REMOTE_FAULT(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x40,6)
#define BRPHY4_GPHY_CORE_BASE19_REMOTE_FAULT_MASK                  0x0040
#define BRPHY4_GPHY_CORE_BASE19_REMOTE_FAULT_ALIGN                 0
#define BRPHY4_GPHY_CORE_BASE19_REMOTE_FAULT_BITS                  1
#define BRPHY4_GPHY_CORE_BASE19_REMOTE_FAULT_SHIFT                 6

/* BRPHY4_GPHY_CORE :: BASE19 :: PAGE_RECEIVED [05:05] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_PAGE_RECEIVED(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_PAGE_RECEIVED(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x20,5)
#define BRPHY4_GPHY_CORE_BASE19_PAGE_RECEIVED_MASK                 0x0020
#define BRPHY4_GPHY_CORE_BASE19_PAGE_RECEIVED_ALIGN                0
#define BRPHY4_GPHY_CORE_BASE19_PAGE_RECEIVED_BITS                 1
#define BRPHY4_GPHY_CORE_BASE19_PAGE_RECEIVED_SHIFT                5

/* BRPHY4_GPHY_CORE :: BASE19 :: LINK_PARTNER_AN_ABILITY [04:04] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x10,4)
#define BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_MASK       0x0010
#define BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_ALIGN      0
#define BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_BITS       1
#define BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_AN_ABILITY_SHIFT      4

/* BRPHY4_GPHY_CORE :: BASE19 :: LINK_PARTNER_NP_ABILITY [03:03] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x8,3)
#define BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_MASK       0x0008
#define BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_ALIGN      0
#define BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_BITS       1
#define BRPHY4_GPHY_CORE_BASE19_LINK_PARTNER_NP_ABILITY_SHIFT      3

/* BRPHY4_GPHY_CORE :: BASE19 :: LINK_STATUS [02:02] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_LINK_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_LINK_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x4,2)
#define BRPHY4_GPHY_CORE_BASE19_LINK_STATUS_MASK                   0x0004
#define BRPHY4_GPHY_CORE_BASE19_LINK_STATUS_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE19_LINK_STATUS_BITS                   1
#define BRPHY4_GPHY_CORE_BASE19_LINK_STATUS_SHIFT                  2

/* BRPHY4_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_RX [01:01] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x2,1)
#define BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_MASK           0x0002
#define BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_ALIGN          0
#define BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_BITS           1
#define BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_RX_SHIFT          1

/* BRPHY4_GPHY_CORE :: BASE19 :: PAUSE_RESOLUTION_TX [00:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE19,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE19,0x1,0)
#define BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_MASK           0x0001
#define BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_ALIGN          0
#define BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_BITS           1
#define BRPHY4_GPHY_CORE_BASE19_PAUSE_RESOLUTION_TX_SHIFT          0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE1A
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE1A :: IP_STATUS_CHANGE [15:15] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_IP_STATUS_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x8000,15)
#define BRPHY4_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_MASK              0x8000
#define BRPHY4_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_ALIGN             0
#define BRPHY4_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_BITS              1
#define BRPHY4_GPHY_CORE_BASE1A_IP_STATUS_CHANGE_SHIFT             15

/* BRPHY4_GPHY_CORE :: BASE1A :: ILLEGAL_PAIR_SWAP [14:14] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x4000,14)
#define BRPHY4_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_MASK             0x4000
#define BRPHY4_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_ALIGN            0
#define BRPHY4_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_BITS             1
#define BRPHY4_GPHY_CORE_BASE1A_ILLEGAL_PAIR_SWAP_SHIFT            14

/* BRPHY4_GPHY_CORE :: BASE1A :: MDIX_STATUS_CHANGE [13:13] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x2000,13)
#define BRPHY4_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_MASK            0x2000
#define BRPHY4_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_ALIGN           0
#define BRPHY4_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_BITS            1
#define BRPHY4_GPHY_CORE_BASE1A_MDIX_STATUS_CHANGE_SHIFT           13

/* BRPHY4_GPHY_CORE :: BASE1A :: EXCEED_HIGH_CNTR_THD [12:12] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x1000,12)
#define BRPHY4_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_MASK          0x1000
#define BRPHY4_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_ALIGN         0
#define BRPHY4_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_BITS          1
#define BRPHY4_GPHY_CORE_BASE1A_EXCEED_HIGH_CNTR_THD_SHIFT         12

/* BRPHY4_GPHY_CORE :: BASE1A :: EXCEED_LOW_CNTR_THD [11:11] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x800,11)
#define BRPHY4_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_MASK           0x0800
#define BRPHY4_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_ALIGN          0
#define BRPHY4_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_BITS           1
#define BRPHY4_GPHY_CORE_BASE1A_EXCEED_LOW_CNTR_THD_SHIFT          11

/* BRPHY4_GPHY_CORE :: BASE1A :: AUTONEG_PAGE_RX [10:10] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x400,10)
#define BRPHY4_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_MASK               0x0400
#define BRPHY4_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_BITS               1
#define BRPHY4_GPHY_CORE_BASE1A_AUTONEG_PAGE_RX_SHIFT              10

/* BRPHY4_GPHY_CORE :: BASE1A :: HCD_NO_LINK [09:09] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_HCD_NO_LINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_HCD_NO_LINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x200,9)
#define BRPHY4_GPHY_CORE_BASE1A_HCD_NO_LINK_MASK                   0x0200
#define BRPHY4_GPHY_CORE_BASE1A_HCD_NO_LINK_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE1A_HCD_NO_LINK_BITS                   1
#define BRPHY4_GPHY_CORE_BASE1A_HCD_NO_LINK_SHIFT                  9

/* BRPHY4_GPHY_CORE :: BASE1A :: NO_HCD [08:08] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_NO_HCD(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_NO_HCD(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x100,8)
#define BRPHY4_GPHY_CORE_BASE1A_NO_HCD_MASK                        0x0100
#define BRPHY4_GPHY_CORE_BASE1A_NO_HCD_ALIGN                       0
#define BRPHY4_GPHY_CORE_BASE1A_NO_HCD_BITS                        1
#define BRPHY4_GPHY_CORE_BASE1A_NO_HCD_SHIFT                       8

/* BRPHY4_GPHY_CORE :: BASE1A :: NEGOTIATED_UNSUPPORTED_HCD [07:07] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x80,7)
#define BRPHY4_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_MASK    0x0080
#define BRPHY4_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_ALIGN   0
#define BRPHY4_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_BITS    1
#define BRPHY4_GPHY_CORE_BASE1A_NEGOTIATED_UNSUPPORTED_HCD_SHIFT   7

/* BRPHY4_GPHY_CORE :: BASE1A :: SCR_SYNC_ERROR [06:06] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_SCR_SYNC_ERROR(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x40,6)
#define BRPHY4_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_MASK                0x0040
#define BRPHY4_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_BITS                1
#define BRPHY4_GPHY_CORE_BASE1A_SCR_SYNC_ERROR_SHIFT               6

/* BRPHY4_GPHY_CORE :: BASE1A :: RMT_RCVR_STATUS_CHANGE [05:05] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x20,5)
#define BRPHY4_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_MASK        0x0020
#define BRPHY4_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_ALIGN       0
#define BRPHY4_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_BITS        1
#define BRPHY4_GPHY_CORE_BASE1A_RMT_RCVR_STATUS_CHANGE_SHIFT       5

/* BRPHY4_GPHY_CORE :: BASE1A :: LOCAL_RCVR_STATUS_CHANGE [04:04] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x10,4)
#define BRPHY4_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_MASK      0x0010
#define BRPHY4_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_ALIGN     0
#define BRPHY4_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_BITS      1
#define BRPHY4_GPHY_CORE_BASE1A_LOCAL_RCVR_STATUS_CHANGE_SHIFT     4

/* BRPHY4_GPHY_CORE :: BASE1A :: DUPLEX_CHANGE [03:03] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_DUPLEX_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x8,3)
#define BRPHY4_GPHY_CORE_BASE1A_DUPLEX_CHANGE_MASK                 0x0008
#define BRPHY4_GPHY_CORE_BASE1A_DUPLEX_CHANGE_ALIGN                0
#define BRPHY4_GPHY_CORE_BASE1A_DUPLEX_CHANGE_BITS                 1
#define BRPHY4_GPHY_CORE_BASE1A_DUPLEX_CHANGE_SHIFT                3

/* BRPHY4_GPHY_CORE :: BASE1A :: LINK_SPEED_CHANGE [02:02] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x4,2)
#define BRPHY4_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_MASK             0x0004
#define BRPHY4_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_ALIGN            0
#define BRPHY4_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_BITS             1
#define BRPHY4_GPHY_CORE_BASE1A_LINK_SPEED_CHANGE_SHIFT            2

/* BRPHY4_GPHY_CORE :: BASE1A :: LINK_STATUS_CHANGE [01:01] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x2,1)
#define BRPHY4_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_MASK            0x0002
#define BRPHY4_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_ALIGN           0
#define BRPHY4_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_BITS            1
#define BRPHY4_GPHY_CORE_BASE1A_LINK_STATUS_CHANGE_SHIFT           1

/* BRPHY4_GPHY_CORE :: BASE1A :: CRC_ERROR [00:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE1A_CRC_ERROR(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1A_CRC_ERROR(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1A,0x1,0)
#define BRPHY4_GPHY_CORE_BASE1A_CRC_ERROR_MASK                     0x0001
#define BRPHY4_GPHY_CORE_BASE1A_CRC_ERROR_ALIGN                    0
#define BRPHY4_GPHY_CORE_BASE1A_CRC_ERROR_BITS                     1
#define BRPHY4_GPHY_CORE_BASE1A_CRC_ERROR_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE1B
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE1B :: INT_MASK_VECTOR [15:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) WriteReg16(BRPHY4_GPHY_CORE_BASE1B,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1B_INT_MASK_VECTOR(x) ReadReg16(BRPHY4_GPHY_CORE_BASE1B)
#define BRPHY4_GPHY_CORE_BASE1B_INT_MASK_VECTOR_MASK               0xffff
#define BRPHY4_GPHY_CORE_BASE1B_INT_MASK_VECTOR_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE1B_INT_MASK_VECTOR_BITS               16
#define BRPHY4_GPHY_CORE_BASE1B_INT_MASK_VECTOR_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE1D_SHD
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x8000,15)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_MASK    0x8000
#define BRPHY4_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_ALIGN   0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_BITS    1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_ENABLE_SHADOW_REGISTER_SHIFT   15

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: GB_ADV_DIS [14:14] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x4000,14)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_MASK                0x4000
#define BRPHY4_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_BITS                1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_GB_ADV_DIS_SHIFT               14

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: TX_ADV_DIS [13:13] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x2000,13)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_MASK                0x2000
#define BRPHY4_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_BITS                1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_TX_ADV_DIS_SHIFT               13

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: WIRESPEED_DOWNGRADE [12:12] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x1000,12)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_MASK       0x1000
#define BRPHY4_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_ALIGN      0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_BITS       1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_WIRESPEED_DOWNGRADE_SHIFT      12

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX [11:11] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x800,11)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_MASK             0x0800
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_ALIGN            0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_BITS             1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_SHIFT            11

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_1000T [10:10] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x400,10)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_MASK                 0x0400
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_ALIGN                0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_BITS                 1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_SHIFT                10

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX [09:09] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x200,9)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_MASK              0x0200
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_ALIGN             0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_BITS              1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_SHIFT             9

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_100T [08:08] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x100,8)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_MASK                  0x0100
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_ALIGN                 0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_BITS                  1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_SHIFT                 8

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX [07:07] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x80,7)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_MASK               0x0080
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_BITS               1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_SHIFT              7

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_10T [06:06] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x40,6)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_MASK                   0x0040
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_BITS                   1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_SHIFT                  6

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_FDX_NL [05:05] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x20,5)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_MASK          0x0020
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_ALIGN         0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_BITS          1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_FDX_NL_SHIFT         5

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_1000T_NL [04:04] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x10,4)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_MASK              0x0010
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_ALIGN             0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_BITS              1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_1000T_NL_SHIFT             4

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_100T_FDX_NL [03:03] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x8,3)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_MASK           0x0008
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_ALIGN          0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_BITS           1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_FDX_NL_SHIFT          3

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_100T_NL [02:02] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_NL(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x4,2)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_MASK               0x0004
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_BITS               1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_100T_NL_SHIFT              2

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_10T_FDX_NL [01:01] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x2,1)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_MASK            0x0002
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_ALIGN           0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_BITS            1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_FDX_NL_SHIFT           1

/* BRPHY4_GPHY_CORE :: BASE1D_SHD :: HCD_10T_NL [00:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_NL(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D_SHD,0x1,0)
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_MASK                0x0001
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_BITS                1
#define BRPHY4_GPHY_CORE_BASE1D_SHD_HCD_10T_NL_SHIFT               0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE1D
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE1D :: ENABLE_SHADOW_REGISTER [15:15] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x8000,15)
#define BRPHY4_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_MASK        0x8000
#define BRPHY4_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_ALIGN       0
#define BRPHY4_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_BITS        1
#define BRPHY4_GPHY_CORE_BASE1D_ENABLE_SHADOW_REGISTER_SHIFT       15

/* BRPHY4_GPHY_CORE :: BASE1D :: MASTER_SLAVE_SEED_MATCH [14:14] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x4000,14)
#define BRPHY4_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_MASK       0x4000
#define BRPHY4_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_ALIGN      0
#define BRPHY4_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_BITS       1
#define BRPHY4_GPHY_CORE_BASE1D_MASTER_SLAVE_SEED_MATCH_SHIFT      14

/* BRPHY4_GPHY_CORE :: BASE1D :: LINK_PARTNER_RD_BIT [13:13] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x2000,13)
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_MASK           0x2000
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_ALIGN          0
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_BITS           1
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_RD_BIT_SHIFT          13

/* BRPHY4_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_VALUE [12:12] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x1000,12)
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_MASK         0x1000
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_ALIGN        0
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_BITS         1
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_VALUE_SHIFT        12

/* BRPHY4_GPHY_CORE :: BASE1D :: LINK_PARTNER_MS_CFG_EN [11:11] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x800,11)
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_MASK        0x0800
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_ALIGN       0
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_BITS        1
#define BRPHY4_GPHY_CORE_BASE1D_LINK_PARTNER_MS_CFG_EN_SHIFT       11

/* BRPHY4_GPHY_CORE :: BASE1D :: LOCAL_MS_SEED_VALUE [10:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x7ff,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1D,0x7ff,0)
#define BRPHY4_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_MASK           0x07ff
#define BRPHY4_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_ALIGN          0
#define BRPHY4_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_BITS           11
#define BRPHY4_GPHY_CORE_BASE1D_LOCAL_MS_SEED_VALUE_SHIFT          0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE1E
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE1E :: CRC_ERR_CNT [15:15] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_CRC_ERR_CNT(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x8000,15)
#define BRPHY4_GPHY_CORE_BASE1E_CRC_ERR_CNT_MASK                   0x8000
#define BRPHY4_GPHY_CORE_BASE1E_CRC_ERR_CNT_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE1E_CRC_ERR_CNT_BITS                   1
#define BRPHY4_GPHY_CORE_BASE1E_CRC_ERR_CNT_SHIFT                  15

/* BRPHY4_GPHY_CORE :: BASE1E :: TX_ERR_CODE [14:14] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_TX_ERR_CODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_TX_ERR_CODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x4000,14)
#define BRPHY4_GPHY_CORE_BASE1E_TX_ERR_CODE_MASK                   0x4000
#define BRPHY4_GPHY_CORE_BASE1E_TX_ERR_CODE_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE1E_TX_ERR_CODE_BITS                   1
#define BRPHY4_GPHY_CORE_BASE1E_TX_ERR_CODE_SHIFT                  14

/* BRPHY4_GPHY_CORE :: BASE1E :: CNTR_TEST [13:13] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_CNTR_TEST(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_CNTR_TEST(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x2000,13)
#define BRPHY4_GPHY_CORE_BASE1E_CNTR_TEST_MASK                     0x2000
#define BRPHY4_GPHY_CORE_BASE1E_CNTR_TEST_ALIGN                    0
#define BRPHY4_GPHY_CORE_BASE1E_CNTR_TEST_BITS                     1
#define BRPHY4_GPHY_CORE_BASE1E_CNTR_TEST_SHIFT                    13

/* BRPHY4_GPHY_CORE :: BASE1E :: FORCE_LINK [12:12] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_FORCE_LINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_FORCE_LINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x1000,12)
#define BRPHY4_GPHY_CORE_BASE1E_FORCE_LINK_MASK                    0x1000
#define BRPHY4_GPHY_CORE_BASE1E_FORCE_LINK_ALIGN                   0
#define BRPHY4_GPHY_CORE_BASE1E_FORCE_LINK_BITS                    1
#define BRPHY4_GPHY_CORE_BASE1E_FORCE_LINK_SHIFT                   12

/* BRPHY4_GPHY_CORE :: BASE1E :: FORCE_LOCK [11:11] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_FORCE_LOCK(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_FORCE_LOCK(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x800,11)
#define BRPHY4_GPHY_CORE_BASE1E_FORCE_LOCK_MASK                    0x0800
#define BRPHY4_GPHY_CORE_BASE1E_FORCE_LOCK_ALIGN                   0
#define BRPHY4_GPHY_CORE_BASE1E_FORCE_LOCK_BITS                    1
#define BRPHY4_GPHY_CORE_BASE1E_FORCE_LOCK_SHIFT                   11

/* BRPHY4_GPHY_CORE :: BASE1E :: SCR_TEST [10:10] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_SCR_TEST(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_SCR_TEST(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x400,10)
#define BRPHY4_GPHY_CORE_BASE1E_SCR_TEST_MASK                      0x0400
#define BRPHY4_GPHY_CORE_BASE1E_SCR_TEST_ALIGN                     0
#define BRPHY4_GPHY_CORE_BASE1E_SCR_TEST_BITS                      1
#define BRPHY4_GPHY_CORE_BASE1E_SCR_TEST_SHIFT                     10

/* BRPHY4_GPHY_CORE :: BASE1E :: EXT_LINK [09:09] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_EXT_LINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_EXT_LINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x200,9)
#define BRPHY4_GPHY_CORE_BASE1E_EXT_LINK_MASK                      0x0200
#define BRPHY4_GPHY_CORE_BASE1E_EXT_LINK_ALIGN                     0
#define BRPHY4_GPHY_CORE_BASE1E_EXT_LINK_BITS                      1
#define BRPHY4_GPHY_CORE_BASE1E_EXT_LINK_SHIFT                     9

/* BRPHY4_GPHY_CORE :: BASE1E :: FAST_TIMERS [08:08] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_FAST_TIMERS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_FAST_TIMERS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x100,8)
#define BRPHY4_GPHY_CORE_BASE1E_FAST_TIMERS_MASK                   0x0100
#define BRPHY4_GPHY_CORE_BASE1E_FAST_TIMERS_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE1E_FAST_TIMERS_BITS                   1
#define BRPHY4_GPHY_CORE_BASE1E_FAST_TIMERS_SHIFT                  8

/* BRPHY4_GPHY_CORE :: BASE1E :: MANUAL_SWAP_MDI [07:07] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x80,7)
#define BRPHY4_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_MASK               0x0080
#define BRPHY4_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_BITS               1
#define BRPHY4_GPHY_CORE_BASE1E_MANUAL_SWAP_MDI_SHIFT              7

/* BRPHY4_GPHY_CORE :: BASE1E :: RX_WATCHDOG_TIMER_DIS [06:06] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x40,6)
#define BRPHY4_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_MASK         0x0040
#define BRPHY4_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_ALIGN        0
#define BRPHY4_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_BITS         1
#define BRPHY4_GPHY_CORE_BASE1E_RX_WATCHDOG_TIMER_DIS_SHIFT        6

/* BRPHY4_GPHY_CORE :: BASE1E :: POLARITY_ENCODE_DIS [05:05] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x20,5)
#define BRPHY4_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_MASK           0x0020
#define BRPHY4_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_ALIGN          0
#define BRPHY4_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_BITS           1
#define BRPHY4_GPHY_CORE_BASE1E_POLARITY_ENCODE_DIS_SHIFT          5

/* BRPHY4_GPHY_CORE :: BASE1E :: SOFT_TRIM_SETTING_EN [04:04] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0x10,4)
#define BRPHY4_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_MASK          0x0010
#define BRPHY4_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_ALIGN         0
#define BRPHY4_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_BITS          1
#define BRPHY4_GPHY_CORE_BASE1E_SOFT_TRIM_SETTING_EN_SHIFT         4

/* BRPHY4_GPHY_CORE :: BASE1E :: TRIM_MAIN_DAC [03:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1E,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1E_TRIM_MAIN_DAC(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1E,0xf,0)
#define BRPHY4_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_MASK                 0x000f
#define BRPHY4_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_ALIGN                0
#define BRPHY4_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_BITS                 4
#define BRPHY4_GPHY_CORE_BASE1E_TRIM_MAIN_DAC_SHIFT                0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BASE1F
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BASE1F :: TEST_SEL_AUTONEG_FSM [15:13] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0xe000,13,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0xe000,13)
#define BRPHY4_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_MASK          0xe000
#define BRPHY4_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_ALIGN         0
#define BRPHY4_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_BITS          3
#define BRPHY4_GPHY_CORE_BASE1F_TEST_SEL_AUTONEG_FSM_SHIFT         13

/* BRPHY4_GPHY_CORE :: BASE1F :: TEST_AUTONEG_TIMER [12:12] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x1000,12)
#define BRPHY4_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_MASK            0x1000
#define BRPHY4_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_ALIGN           0
#define BRPHY4_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_BITS            1
#define BRPHY4_GPHY_CORE_BASE1F_TEST_AUTONEG_TIMER_SHIFT           12

/* BRPHY4_GPHY_CORE :: BASE1F :: TEST_MS_SEED [11:11] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_TEST_MS_SEED(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_TEST_MS_SEED(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x800,11)
#define BRPHY4_GPHY_CORE_BASE1F_TEST_MS_SEED_MASK                  0x0800
#define BRPHY4_GPHY_CORE_BASE1F_TEST_MS_SEED_ALIGN                 0
#define BRPHY4_GPHY_CORE_BASE1F_TEST_MS_SEED_BITS                  1
#define BRPHY4_GPHY_CORE_BASE1F_TEST_MS_SEED_SHIFT                 11

/* BRPHY4_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_ABILITY_EN [10:10] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x400,10)
#define BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_MASK    0x0400
#define BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_ALIGN   0
#define BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_BITS    1
#define BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_ABILITY_EN_SHIFT   10

/* BRPHY4_GPHY_CORE :: BASE1F :: FORCE_HCD [09:09] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_FORCE_HCD(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_FORCE_HCD(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x200,9)
#define BRPHY4_GPHY_CORE_BASE1F_FORCE_HCD_MASK                     0x0200
#define BRPHY4_GPHY_CORE_BASE1F_FORCE_HCD_ALIGN                    0
#define BRPHY4_GPHY_CORE_BASE1F_FORCE_HCD_BITS                     1
#define BRPHY4_GPHY_CORE_BASE1F_FORCE_HCD_SHIFT                    9

/* BRPHY4_GPHY_CORE :: BASE1F :: WR_LINK_PARTNER_MS_SEED_EN [08:08] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x100,8)
#define BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_MASK    0x0100
#define BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_ALIGN   0
#define BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_BITS    1
#define BRPHY4_GPHY_CORE_BASE1F_WR_LINK_PARTNER_MS_SEED_EN_SHIFT   8

/* BRPHY4_GPHY_CORE :: BASE1F :: TX_10B [07:07] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_TX_10B(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_TX_10B(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x80,7)
#define BRPHY4_GPHY_CORE_BASE1F_TX_10B_MASK                        0x0080
#define BRPHY4_GPHY_CORE_BASE1F_TX_10B_ALIGN                       0
#define BRPHY4_GPHY_CORE_BASE1F_TX_10B_BITS                        1
#define BRPHY4_GPHY_CORE_BASE1F_TX_10B_SHIFT                       7

/* BRPHY4_GPHY_CORE :: BASE1F :: RX_10B [06:06] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_RX_10B(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_RX_10B(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x40,6)
#define BRPHY4_GPHY_CORE_BASE1F_RX_10B_MASK                        0x0040
#define BRPHY4_GPHY_CORE_BASE1F_RX_10B_ALIGN                       0
#define BRPHY4_GPHY_CORE_BASE1F_RX_10B_BITS                        1
#define BRPHY4_GPHY_CORE_BASE1F_RX_10B_SHIFT                       6

/* BRPHY4_GPHY_CORE :: BASE1F :: BYPASS_TXFIFO [05:05] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_BYPASS_TXFIFO(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x20,5)
#define BRPHY4_GPHY_CORE_BASE1F_BYPASS_TXFIFO_MASK                 0x0020
#define BRPHY4_GPHY_CORE_BASE1F_BYPASS_TXFIFO_ALIGN                0
#define BRPHY4_GPHY_CORE_BASE1F_BYPASS_TXFIFO_BITS                 1
#define BRPHY4_GPHY_CORE_BASE1F_BYPASS_TXFIFO_SHIFT                5

/* BRPHY4_GPHY_CORE :: BASE1F :: SAME_SCR_SEEDS [04:04] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_SAME_SCR_SEEDS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x10,4)
#define BRPHY4_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_MASK                0x0010
#define BRPHY4_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_BITS                1
#define BRPHY4_GPHY_CORE_BASE1F_SAME_SCR_SEEDS_SHIFT               4

/* BRPHY4_GPHY_CORE :: BASE1F :: JITTER_TEST [03:03] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_JITTER_TEST(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_JITTER_TEST(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x8,3)
#define BRPHY4_GPHY_CORE_BASE1F_JITTER_TEST_MASK                   0x0008
#define BRPHY4_GPHY_CORE_BASE1F_JITTER_TEST_ALIGN                  0
#define BRPHY4_GPHY_CORE_BASE1F_JITTER_TEST_BITS                   1
#define BRPHY4_GPHY_CORE_BASE1F_JITTER_TEST_SHIFT                  3

/* BRPHY4_GPHY_CORE :: BASE1F :: TEST_ATMP_CNTR [02:02] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_TEST_ATMP_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x4,2)
#define BRPHY4_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_MASK                0x0004
#define BRPHY4_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_ALIGN               0
#define BRPHY4_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_BITS                1
#define BRPHY4_GPHY_CORE_BASE1F_TEST_ATMP_CNTR_SHIFT               2

/* BRPHY4_GPHY_CORE :: BASE1F :: LATENCY_MEASURE [01:01] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_LATENCY_MEASURE(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x2,1)
#define BRPHY4_GPHY_CORE_BASE1F_LATENCY_MEASURE_MASK               0x0002
#define BRPHY4_GPHY_CORE_BASE1F_LATENCY_MEASURE_ALIGN              0
#define BRPHY4_GPHY_CORE_BASE1F_LATENCY_MEASURE_BITS               1
#define BRPHY4_GPHY_CORE_BASE1F_LATENCY_MEASURE_SHIFT              1

/* BRPHY4_GPHY_CORE :: BASE1F :: ACTIVE_HYBRID_DIS [00:00] */
#define Wr_BRPHY4_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_BASE1F,0x1,0)
#define BRPHY4_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_MASK             0x0001
#define BRPHY4_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_ALIGN            0
#define BRPHY4_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_BITS             1
#define BRPHY4_GPHY_CORE_BASE1F_ACTIVE_HYBRID_DIS_SHIFT            0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_00
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_00 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_00_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_00_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_00_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_00_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_00 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_00,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_00_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_00,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_00_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_00_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_00_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_00_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_00 :: reserved1 [09:08] */
#define BRPHY4_GPHY_CORE_SHD1C_00_RESERVED1_MASK                   0x0300
#define BRPHY4_GPHY_CORE_SHD1C_00_RESERVED1_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_00_RESERVED1_BITS                   2
#define BRPHY4_GPHY_CORE_SHD1C_00_RESERVED1_SHIFT                  8

/* BRPHY4_GPHY_CORE :: SHD1C_00 :: CABLETRON_LED [07:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_00,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_00_CABLETRON_LED(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_00,0xff,0)
#define BRPHY4_GPHY_CORE_SHD1C_00_CABLETRON_LED_MASK               0x00ff
#define BRPHY4_GPHY_CORE_SHD1C_00_CABLETRON_LED_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD1C_00_CABLETRON_LED_BITS               8
#define BRPHY4_GPHY_CORE_SHD1C_00_CABLETRON_LED_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_01
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_01 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_01_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_01_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_01_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_01_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_01 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_01,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_01_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_01,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_01_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_01_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_01_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_01_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_01 :: reserved1 [09:07] */
#define BRPHY4_GPHY_CORE_SHD1C_01_RESERVED1_MASK                   0x0380
#define BRPHY4_GPHY_CORE_SHD1C_01_RESERVED1_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_01_RESERVED1_BITS                   3
#define BRPHY4_GPHY_CORE_SHD1C_01_RESERVED1_SHIFT                  7

/* BRPHY4_GPHY_CORE :: SHD1C_01 :: TVCO_OUTPUT [06:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_01,0x7f,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_01_TVCO_OUTPUT(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_01,0x7f,0)
#define BRPHY4_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_MASK                 0x007f
#define BRPHY4_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_BITS                 7
#define BRPHY4_GPHY_CORE_SHD1C_01_TVCO_OUTPUT_SHIFT                0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_02
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_02 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_02_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_02_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_02_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_02_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_02_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_02_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_02_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_02_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: SD_STATUS [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_SD_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_SD_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x200,9)
#define BRPHY4_GPHY_CORE_SHD1C_02_SD_STATUS_MASK                   0x0200
#define BRPHY4_GPHY_CORE_SHD1C_02_SD_STATUS_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_02_SD_STATUS_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_02_SD_STATUS_SHIFT                  9

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: FORCE_SD_ON [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_FORCE_SD_ON(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x100,8)
#define BRPHY4_GPHY_CORE_SHD1C_02_FORCE_SD_ON_MASK                 0x0100
#define BRPHY4_GPHY_CORE_SHD1C_02_FORCE_SD_ON_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD1C_02_FORCE_SD_ON_BITS                 1
#define BRPHY4_GPHY_CORE_SHD1C_02_FORCE_SD_ON_SHIFT                8

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: INVERT_SD_PIN [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_INVERT_SD_PIN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_MASK               0x0080
#define BRPHY4_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_BITS               1
#define BRPHY4_GPHY_CORE_SHD1C_02_INVERT_SD_PIN_SHIFT              7

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: CFC_INITFILTER_EN [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x40,6)
#define BRPHY4_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_MASK           0x0040
#define BRPHY4_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_ALIGN          0
#define BRPHY4_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_BITS           1
#define BRPHY4_GPHY_CORE_SHD1C_02_CFC_INITFILTER_EN_SHIFT          6

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: USE_FILTERED_SD [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_USE_FILTERED_SD(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x20,5)
#define BRPHY4_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_MASK             0x0020
#define BRPHY4_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_BITS             1
#define BRPHY4_GPHY_CORE_SHD1C_02_USE_FILTERED_SD_SHIFT            5

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: FX_COPPER_PATH [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_FX_COPPER_PATH(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x10,4)
#define BRPHY4_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_MASK              0x0010
#define BRPHY4_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_BITS              1
#define BRPHY4_GPHY_CORE_SHD1C_02_FX_COPPER_PATH_SHIFT             4

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: SPARE_REG [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x8,3)
#define BRPHY4_GPHY_CORE_SHD1C_02_SPARE_REG_MASK                   0x0008
#define BRPHY4_GPHY_CORE_SHD1C_02_SPARE_REG_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_02_SPARE_REG_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_02_SPARE_REG_SHIFT                  3

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: BC_LINK_SPEED_LED [02:02] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x4,2)
#define BRPHY4_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_MASK           0x0004
#define BRPHY4_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_ALIGN          0
#define BRPHY4_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_BITS           1
#define BRPHY4_GPHY_CORE_SHD1C_02_BC_LINK_SPEED_LED_SHIFT          2

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: LOST_TOKEN_FIX_DIS [01:01] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x2,1)
#define BRPHY4_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_MASK          0x0002
#define BRPHY4_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_BITS          1
#define BRPHY4_GPHY_CORE_SHD1C_02_LOST_TOKEN_FIX_DIS_SHIFT         1

/* BRPHY4_GPHY_CORE :: SHD1C_02 :: LINK_LED [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_02_LINK_LED(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_02_LINK_LED(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_02,0x1,0)
#define BRPHY4_GPHY_CORE_SHD1C_02_LINK_LED_MASK                    0x0001
#define BRPHY4_GPHY_CORE_SHD1C_02_LINK_LED_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD1C_02_LINK_LED_BITS                    1
#define BRPHY4_GPHY_CORE_SHD1C_02_LINK_LED_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_03
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_03 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_03_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_03_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_03_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_03_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_03 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_03_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_03_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_03_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_03_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_03_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_03 :: GTXCLK_DLY_EN [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x200,9)
#define BRPHY4_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_MASK               0x0200
#define BRPHY4_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_BITS               1
#define BRPHY4_GPHY_CORE_SHD1C_03_GTXCLK_DLY_EN_SHIFT              9

/* BRPHY4_GPHY_CORE :: SHD1C_03 :: GMII_CLK_ALIGN_STRB [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x100,8)
#define BRPHY4_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_MASK         0x0100
#define BRPHY4_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_BITS         1
#define BRPHY4_GPHY_CORE_SHD1C_03_GMII_CLK_ALIGN_STRB_SHIFT        8

/* BRPHY4_GPHY_CORE :: SHD1C_03 :: RXCLK_ALIGN_STRB [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_MASK            0x0080
#define BRPHY4_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_BITS            1
#define BRPHY4_GPHY_CORE_SHD1C_03_RXCLK_ALIGN_STRB_SHIFT           7

/* BRPHY4_GPHY_CORE :: SHD1C_03 :: DLY_VALUE [06:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_03_DLY_VALUE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x70,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_03_DLY_VALUE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0x70,4)
#define BRPHY4_GPHY_CORE_SHD1C_03_DLY_VALUE_MASK                   0x0070
#define BRPHY4_GPHY_CORE_SHD1C_03_DLY_VALUE_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_03_DLY_VALUE_BITS                   3
#define BRPHY4_GPHY_CORE_SHD1C_03_DLY_VALUE_SHIFT                  4

/* BRPHY4_GPHY_CORE :: SHD1C_03 :: DLY_LINE_SEL [03:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_03_DLY_LINE_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_03,0xf,0)
#define BRPHY4_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_MASK                0x000f
#define BRPHY4_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_BITS                4
#define BRPHY4_GPHY_CORE_SHD1C_03_DLY_LINE_SEL_SHIFT               0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_04
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_04 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_04_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_04_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_04_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_04_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_04 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_04_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_04_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_04_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_04_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_04_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_04 :: SPARE_REG [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_04_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_04_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x200,9)
#define BRPHY4_GPHY_CORE_SHD1C_04_SPARE_REG_MASK                   0x0200
#define BRPHY4_GPHY_CORE_SHD1C_04_SPARE_REG_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_04_SPARE_REG_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_04_SPARE_REG_SHIFT                  9

/* BRPHY4_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_DIS [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x100,8)
#define BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_MASK         0x0100
#define BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_BITS         1
#define BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_DIS_SHIFT        8

/* BRPHY4_GPHY_CORE :: SHD1C_04 :: SELECT_TPOUT_RXD [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_MASK            0x0080
#define BRPHY4_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_BITS            1
#define BRPHY4_GPHY_CORE_SHD1C_04_SELECT_TPOUT_RXD_SHIFT           7

/* BRPHY4_GPHY_CORE :: SHD1C_04 :: DISABLE_PHYA2 [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_04_DISABLE_PHYA2(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x40,6)
#define BRPHY4_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_MASK               0x0040
#define BRPHY4_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_BITS               1
#define BRPHY4_GPHY_CORE_SHD1C_04_DISABLE_PHYA2_SHIFT              6

/* BRPHY4_GPHY_CORE :: SHD1C_04 :: RBC_TXC_RXC_TRI [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x20,5)
#define BRPHY4_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_MASK             0x0020
#define BRPHY4_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_BITS             1
#define BRPHY4_GPHY_CORE_SHD1C_04_RBC_TXC_RXC_TRI_SHIFT            5

/* BRPHY4_GPHY_CORE :: SHD1C_04 :: WIRESPEED_RETRY_LIMIT [04:02] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x1c,2,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x1c,2)
#define BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_MASK       0x001c
#define BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_ALIGN      0
#define BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_BITS       3
#define BRPHY4_GPHY_CORE_SHD1C_04_WIRESPEED_RETRY_LIMIT_SHIFT      2

/* BRPHY4_GPHY_CORE :: SHD1C_04 :: ENG_DET_ON_INTR_PIN [01:01] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x2,1)
#define BRPHY4_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_MASK         0x0002
#define BRPHY4_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_BITS         1
#define BRPHY4_GPHY_CORE_SHD1C_04_ENG_DET_ON_INTR_PIN_SHIFT        1

/* BRPHY4_GPHY_CORE :: SHD1C_04 :: TESTONBYTE7_0 [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_04_TESTONBYTE7_0(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_04,0x1,0)
#define BRPHY4_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_MASK               0x0001
#define BRPHY4_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_BITS               1
#define BRPHY4_GPHY_CORE_SHD1C_04_TESTONBYTE7_0_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_05
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_05 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_05_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_05_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_05_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_05_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_05_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_05_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_05_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_05_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: DLL_LOCK_EN [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_DLL_LOCK_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x200,9)
#define BRPHY4_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_MASK                 0x0200
#define BRPHY4_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_BITS                 1
#define BRPHY4_GPHY_CORE_SHD1C_05_DLL_LOCK_EN_SHIFT                9

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: TXC_RXC_DIS [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_TXC_RXC_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x100,8)
#define BRPHY4_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_MASK                 0x0100
#define BRPHY4_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_BITS                 1
#define BRPHY4_GPHY_CORE_SHD1C_05_TXC_RXC_DIS_SHIFT                8

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: BT_R_REJECT_FILTER [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_MASK          0x0080
#define BRPHY4_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_BITS          1
#define BRPHY4_GPHY_CORE_SHD1C_05_BT_R_REJECT_FILTER_SHIFT         7

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: TXC_OFF_EN [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_TXC_OFF_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x40,6)
#define BRPHY4_GPHY_CORE_SHD1C_05_TXC_OFF_EN_MASK                  0x0040
#define BRPHY4_GPHY_CORE_SHD1C_05_TXC_OFF_EN_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD1C_05_TXC_OFF_EN_BITS                  1
#define BRPHY4_GPHY_CORE_SHD1C_05_TXC_OFF_EN_SHIFT                 6

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: SD_CHANGE_MUX_SEL [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x20,5)
#define BRPHY4_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_MASK           0x0020
#define BRPHY4_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_ALIGN          0
#define BRPHY4_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_BITS           1
#define BRPHY4_GPHY_CORE_SHD1C_05_SD_CHANGE_MUX_SEL_SHIFT          5

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: LOW_POWER_ENC_DIS [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x10,4)
#define BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_MASK           0x0010
#define BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_ALIGN          0
#define BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_BITS           1
#define BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_ENC_DIS_SHIFT          4

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: LOW_POWER_BT_DIS [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x8,3)
#define BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_MASK            0x0008
#define BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_BITS            1
#define BRPHY4_GPHY_CORE_SHD1C_05_LOW_POWER_BT_DIS_SHIFT           3

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: SD_DEASSERT_TIMER_LEN [02:02] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x4,2)
#define BRPHY4_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_MASK       0x0004
#define BRPHY4_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_ALIGN      0
#define BRPHY4_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_BITS       1
#define BRPHY4_GPHY_CORE_SHD1C_05_SD_DEASSERT_TIMER_LEN_SHIFT      2

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: AUTO_PWRDN_DLL_DIS [01:01] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x2,1)
#define BRPHY4_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_MASK          0x0002
#define BRPHY4_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_BITS          1
#define BRPHY4_GPHY_CORE_SHD1C_05_AUTO_PWRDN_DLL_DIS_SHIFT         1

/* BRPHY4_GPHY_CORE :: SHD1C_05 :: CLK125_OUTPUT_EN [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_05,0x1,0)
#define BRPHY4_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_MASK            0x0001
#define BRPHY4_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_BITS            1
#define BRPHY4_GPHY_CORE_SHD1C_05_CLK125_OUTPUT_EN_SHIFT           0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_06
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_06 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_06_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_06_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_06_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_06_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_06 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_06_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_06_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_06_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_06_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_06_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_06 :: SPARE_REG [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_06_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_06_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x200,9)
#define BRPHY4_GPHY_CORE_SHD1C_06_SPARE_REG_MASK                   0x0200
#define BRPHY4_GPHY_CORE_SHD1C_06_SPARE_REG_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_06_SPARE_REG_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_06_SPARE_REG_SHIFT                  9

/* BRPHY4_GPHY_CORE :: SHD1C_06 :: TDR_LINK_TIME_OUT [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x100,8)
#define BRPHY4_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_MASK           0x0100
#define BRPHY4_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_ALIGN          0
#define BRPHY4_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_BITS           1
#define BRPHY4_GPHY_CORE_SHD1C_06_TDR_LINK_TIME_OUT_SHIFT          8

/* BRPHY4_GPHY_CORE :: SHD1C_06 :: TEST_PULSE_SIZE [07:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0xe0,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0xe0,5)
#define BRPHY4_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_MASK             0x00e0
#define BRPHY4_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_BITS             3
#define BRPHY4_GPHY_CORE_SHD1C_06_TEST_PULSE_SIZE_SHIFT            5

/* BRPHY4_GPHY_CORE :: SHD1C_06 :: TX_CHANNEL_SEL [04:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x18,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x18,3)
#define BRPHY4_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_MASK              0x0018
#define BRPHY4_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_BITS              2
#define BRPHY4_GPHY_CORE_SHD1C_06_TX_CHANNEL_SEL_SHIFT             3

/* BRPHY4_GPHY_CORE :: SHD1C_06 :: RX_CHANNEL_SEL [02:01] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x6,1,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x6,1)
#define BRPHY4_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_MASK              0x0006
#define BRPHY4_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_BITS              2
#define BRPHY4_GPHY_CORE_SHD1C_06_RX_CHANNEL_SEL_SHIFT             1

/* BRPHY4_GPHY_CORE :: SHD1C_06 :: TDR_START [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_06_TDR_START(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_06_TDR_START(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_06,0x1,0)
#define BRPHY4_GPHY_CORE_SHD1C_06_TDR_START_MASK                   0x0001
#define BRPHY4_GPHY_CORE_SHD1C_06_TDR_START_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_06_TDR_START_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_06_TDR_START_SHIFT                  0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_07
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_07 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_07_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_07_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_07_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_07_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_07_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_07_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_07_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_07_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: SPARE_REG [09:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x300,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x300,8)
#define BRPHY4_GPHY_CORE_SHD1C_07_SPARE_REG_MASK                   0x0300
#define BRPHY4_GPHY_CORE_SHD1C_07_SPARE_REG_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_07_SPARE_REG_BITS                   2
#define BRPHY4_GPHY_CORE_SHD1C_07_SPARE_REG_SHIFT                  8

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_MASK                0x0080
#define BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_BITS                1
#define BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_SHIFT               7

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: PHASE_STATUS_CLEAR [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x40,6)
#define BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_MASK          0x0040
#define BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_BITS          1
#define BRPHY4_GPHY_CORE_SHD1C_07_PHASE_STATUS_CLEAR_SHIFT         6

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: FASTTIMERS [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_FASTTIMERS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_FASTTIMERS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x20,5)
#define BRPHY4_GPHY_CORE_SHD1C_07_FASTTIMERS_MASK                  0x0020
#define BRPHY4_GPHY_CORE_SHD1C_07_FASTTIMERS_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD1C_07_FASTTIMERS_BITS                  1
#define BRPHY4_GPHY_CORE_SHD1C_07_FASTTIMERS_SHIFT                 5

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: FEXT [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_FEXT(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_FEXT(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x10,4)
#define BRPHY4_GPHY_CORE_SHD1C_07_FEXT_MASK                        0x0010
#define BRPHY4_GPHY_CORE_SHD1C_07_FEXT_ALIGN                       0
#define BRPHY4_GPHY_CORE_SHD1C_07_FEXT_BITS                        1
#define BRPHY4_GPHY_CORE_SHD1C_07_FEXT_SHIFT                       4

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: MASTER [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_MASTER(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_MASTER(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x8,3)
#define BRPHY4_GPHY_CORE_SHD1C_07_MASTER_MASK                      0x0008
#define BRPHY4_GPHY_CORE_SHD1C_07_MASTER_ALIGN                     0
#define BRPHY4_GPHY_CORE_SHD1C_07_MASTER_BITS                      1
#define BRPHY4_GPHY_CORE_SHD1C_07_MASTER_SHIFT                     3

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: EXT_PHY_NO_AUTONEG [02:02] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x4,2)
#define BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_MASK          0x0004
#define BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_BITS          1
#define BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_NO_AUTONEG_SHIFT         2

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: EXT_PHY [01:01] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x2,1)
#define BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_MASK                     0x0002
#define BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_ALIGN                    0
#define BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_BITS                     1
#define BRPHY4_GPHY_CORE_SHD1C_07_EXT_PHY_SHIFT                    1

/* BRPHY4_GPHY_CORE :: SHD1C_07 :: TDR_EN [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_07_TDR_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_07_TDR_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_07,0x1,0)
#define BRPHY4_GPHY_CORE_SHD1C_07_TDR_EN_MASK                      0x0001
#define BRPHY4_GPHY_CORE_SHD1C_07_TDR_EN_ALIGN                     0
#define BRPHY4_GPHY_CORE_SHD1C_07_TDR_EN_BITS                      1
#define BRPHY4_GPHY_CORE_SHD1C_07_TDR_EN_SHIFT                     0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_08
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_08 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_08_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_08_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_08_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_08_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_08_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: reserved1 [09:09] */
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED1_MASK                   0x0200
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED1_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED1_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED1_SHIFT                  9

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: SLAVE_N [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_08_SLAVE_N(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_08_SLAVE_N(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x100,8)
#define BRPHY4_GPHY_CORE_SHD1C_08_SLAVE_N_MASK                     0x0100
#define BRPHY4_GPHY_CORE_SHD1C_08_SLAVE_N_ALIGN                    0
#define BRPHY4_GPHY_CORE_SHD1C_08_SLAVE_N_BITS                     1
#define BRPHY4_GPHY_CORE_SHD1C_08_SLAVE_N_SHIFT                    8

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: FDXLED_N [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_08_FDXLED_N(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_08_FDXLED_N(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_08_FDXLED_N_MASK                    0x0080
#define BRPHY4_GPHY_CORE_SHD1C_08_FDXLED_N_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD1C_08_FDXLED_N_BITS                    1
#define BRPHY4_GPHY_CORE_SHD1C_08_FDXLED_N_SHIFT                   7

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: INTR_N [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_08_INTR_N(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_08_INTR_N(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x40,6)
#define BRPHY4_GPHY_CORE_SHD1C_08_INTR_N_MASK                      0x0040
#define BRPHY4_GPHY_CORE_SHD1C_08_INTR_N_ALIGN                     0
#define BRPHY4_GPHY_CORE_SHD1C_08_INTR_N_BITS                      1
#define BRPHY4_GPHY_CORE_SHD1C_08_INTR_N_SHIFT                     6

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: reserved2 [05:05] */
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED2_MASK                   0x0020
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED2_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED2_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_08_RESERVED2_SHIFT                  5

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: LINKSPD_N [04:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_08_LINKSPD_N(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x18,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_08_LINKSPD_N(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x18,3)
#define BRPHY4_GPHY_CORE_SHD1C_08_LINKSPD_N_MASK                   0x0018
#define BRPHY4_GPHY_CORE_SHD1C_08_LINKSPD_N_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_08_LINKSPD_N_BITS                   2
#define BRPHY4_GPHY_CORE_SHD1C_08_LINKSPD_N_SHIFT                  3

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: TRANSMIT_LED [02:02] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_08_TRANSMIT_LED(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x4,2)
#define BRPHY4_GPHY_CORE_SHD1C_08_TRANSMIT_LED_MASK                0x0004
#define BRPHY4_GPHY_CORE_SHD1C_08_TRANSMIT_LED_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD1C_08_TRANSMIT_LED_BITS                1
#define BRPHY4_GPHY_CORE_SHD1C_08_TRANSMIT_LED_SHIFT               2

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: RECEIVE_LED [01:01] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_08_RECEIVE_LED(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x2,1)
#define BRPHY4_GPHY_CORE_SHD1C_08_RECEIVE_LED_MASK                 0x0002
#define BRPHY4_GPHY_CORE_SHD1C_08_RECEIVE_LED_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD1C_08_RECEIVE_LED_BITS                 1
#define BRPHY4_GPHY_CORE_SHD1C_08_RECEIVE_LED_SHIFT                1

/* BRPHY4_GPHY_CORE :: SHD1C_08 :: QUALITY_LED [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_08_QUALITY_LED(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_08_QUALITY_LED(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_08,0x1,0)
#define BRPHY4_GPHY_CORE_SHD1C_08_QUALITY_LED_MASK                 0x0001
#define BRPHY4_GPHY_CORE_SHD1C_08_QUALITY_LED_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD1C_08_QUALITY_LED_BITS                 1
#define BRPHY4_GPHY_CORE_SHD1C_08_QUALITY_LED_SHIFT                0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_09
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_09 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_09_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_09_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_09_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_09_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_09_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_09_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_09_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_09_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: COL_BLINK [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_COL_BLINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_COL_BLINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x200,9)
#define BRPHY4_GPHY_CORE_SHD1C_09_COL_BLINK_MASK                   0x0200
#define BRPHY4_GPHY_CORE_SHD1C_09_COL_BLINK_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_09_COL_BLINK_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_09_COL_BLINK_SHIFT                  9

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: ACT_LINK_MSB [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_MSB(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x100,8)
#define BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_MASK                0x0100
#define BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_BITS                1
#define BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_MSB_SHIFT               8

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: SPARE_REG [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_09_SPARE_REG_MASK                   0x0080
#define BRPHY4_GPHY_CORE_SHD1C_09_SPARE_REG_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_09_SPARE_REG_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_09_SPARE_REG_SHIFT                  7

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: EXT_SERDES_INUSE [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x40,6)
#define BRPHY4_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_MASK            0x0040
#define BRPHY4_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_BITS            1
#define BRPHY4_GPHY_CORE_SHD1C_09_EXT_SERDES_INUSE_SHIFT           6

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: OV_GBIC_LED [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_OV_GBIC_LED(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x20,5)
#define BRPHY4_GPHY_CORE_SHD1C_09_OV_GBIC_LED_MASK                 0x0020
#define BRPHY4_GPHY_CORE_SHD1C_09_OV_GBIC_LED_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD1C_09_OV_GBIC_LED_BITS                 1
#define BRPHY4_GPHY_CORE_SHD1C_09_OV_GBIC_LED_SHIFT                5

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: ACT_LINK_LSB [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_LSB(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x10,4)
#define BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_MASK                0x0010
#define BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_BITS                1
#define BRPHY4_GPHY_CORE_SHD1C_09_ACT_LINK_LSB_SHIFT               4

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: ACTIVITY_LED_EN [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x8,3)
#define BRPHY4_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_MASK             0x0008
#define BRPHY4_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_BITS             1
#define BRPHY4_GPHY_CORE_SHD1C_09_ACTIVITY_LED_EN_SHIFT            3

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: RMT_FAULT_LED_EN [02:02] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x4,2)
#define BRPHY4_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_MASK            0x0004
#define BRPHY4_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_BITS            1
#define BRPHY4_GPHY_CORE_SHD1C_09_RMT_FAULT_LED_EN_SHIFT           2

/* BRPHY4_GPHY_CORE :: SHD1C_09 :: LINK_UTIL_LED_SEL [01:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x3,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_09,0x3,0)
#define BRPHY4_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_MASK           0x0003
#define BRPHY4_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_ALIGN          0
#define BRPHY4_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_BITS           2
#define BRPHY4_GPHY_CORE_SHD1C_09_LINK_UTIL_LED_SEL_SHIFT          0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_0A
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_0A :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_0A_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_0A_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0A_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_0A_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_0A :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0A_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_0A_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_0A_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0A_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_0A_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_0A :: reserved1 [09:09] */
#define BRPHY4_GPHY_CORE_SHD1C_0A_RESERVED1_MASK                   0x0200
#define BRPHY4_GPHY_CORE_SHD1C_0A_RESERVED1_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0A_RESERVED1_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_0A_RESERVED1_SHIFT                  9

/* BRPHY4_GPHY_CORE :: SHD1C_0A :: APD_SINGLELP_ENABLE [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x100,8)
#define BRPHY4_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_MASK         0x0100
#define BRPHY4_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_BITS         1
#define BRPHY4_GPHY_CORE_SHD1C_0A_APD_SINGLELP_ENABLE_SHIFT        8

/* BRPHY4_GPHY_CORE :: SHD1C_0A :: LOWPWR136_ENC_EN [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_MASK            0x0080
#define BRPHY4_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_BITS            1
#define BRPHY4_GPHY_CORE_SHD1C_0A_LOWPWR136_ENC_EN_SHIFT           7

/* BRPHY4_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_IGNORE_AUTONEG [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x40,6)
#define BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_MASK   0x0040
#define BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_ALIGN  0
#define BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_BITS   1
#define BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_IGNORE_AUTONEG_SHIFT  6

/* BRPHY4_GPHY_CORE :: SHD1C_0A :: AUTO_PWRDN_EN [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x20,5)
#define BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_MASK               0x0020
#define BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_BITS               1
#define BRPHY4_GPHY_CORE_SHD1C_0A_AUTO_PWRDN_EN_SHIFT              5

/* BRPHY4_GPHY_CORE :: SHD1C_0A :: SLEEP_TIMER_SEL [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0x10,4)
#define BRPHY4_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_MASK             0x0010
#define BRPHY4_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_BITS             1
#define BRPHY4_GPHY_CORE_SHD1C_0A_SLEEP_TIMER_SEL_SHIFT            4

/* BRPHY4_GPHY_CORE :: SHD1C_0A :: WAKE_UP_TIMER_SEL [03:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0A,0xf,0)
#define BRPHY4_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_MASK           0x000f
#define BRPHY4_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_ALIGN          0
#define BRPHY4_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_BITS           4
#define BRPHY4_GPHY_CORE_SHD1C_0A_WAKE_UP_TIMER_SEL_SHIFT          0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_0B
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_0B :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_0B_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_0B_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0B_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_0B_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_0B :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0B,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0B_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0B,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_0B_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_0B_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0B_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_0B_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_0B :: reserved1 [09:08] */
#define BRPHY4_GPHY_CORE_SHD1C_0B_RESERVED1_MASK                   0x0300
#define BRPHY4_GPHY_CORE_SHD1C_0B_RESERVED1_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0B_RESERVED1_BITS                   2
#define BRPHY4_GPHY_CORE_SHD1C_0B_RESERVED1_SHIFT                  8

/* BRPHY4_GPHY_CORE :: SHD1C_0B :: SPARE_CTL4 [07:01] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0B,0xfe,1,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0B_SPARE_CTL4(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0B,0xfe,1)
#define BRPHY4_GPHY_CORE_SHD1C_0B_SPARE_CTL4_MASK                  0x00fe
#define BRPHY4_GPHY_CORE_SHD1C_0B_SPARE_CTL4_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD1C_0B_SPARE_CTL4_BITS                  7
#define BRPHY4_GPHY_CORE_SHD1C_0B_SPARE_CTL4_SHIFT                 1

/* BRPHY4_GPHY_CORE :: SHD1C_0B :: dis_cl45 [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0B_dis_cl45(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0B,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0B_dis_cl45(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0B,0x1,0)
#define BRPHY4_GPHY_CORE_SHD1C_0B_DIS_CL45_MASK                    0x0001
#define BRPHY4_GPHY_CORE_SHD1C_0B_DIS_CL45_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD1C_0B_DIS_CL45_BITS                    1
#define BRPHY4_GPHY_CORE_SHD1C_0B_DIS_CL45_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_0D
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_0D :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_0D_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_0D_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0D_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_0D_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_0D :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0D,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0D_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0D,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_0D_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_0D_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0D_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_0D_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_0D :: reserved1 [09:08] */
#define BRPHY4_GPHY_CORE_SHD1C_0D_RESERVED1_MASK                   0x0300
#define BRPHY4_GPHY_CORE_SHD1C_0D_RESERVED1_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0D_RESERVED1_BITS                   2
#define BRPHY4_GPHY_CORE_SHD1C_0D_RESERVED1_SHIFT                  8

/* BRPHY4_GPHY_CORE :: SHD1C_0D :: LED2_SEL [07:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0D_LED2_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0D,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0D_LED2_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0D,0xf0,4)
#define BRPHY4_GPHY_CORE_SHD1C_0D_LED2_SEL_MASK                    0x00f0
#define BRPHY4_GPHY_CORE_SHD1C_0D_LED2_SEL_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD1C_0D_LED2_SEL_BITS                    4
#define BRPHY4_GPHY_CORE_SHD1C_0D_LED2_SEL_SHIFT                   4

/* BRPHY4_GPHY_CORE :: SHD1C_0D :: LED1_SEL [03:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0D_LED1_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0D,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0D_LED1_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0D,0xf,0)
#define BRPHY4_GPHY_CORE_SHD1C_0D_LED1_SEL_MASK                    0x000f
#define BRPHY4_GPHY_CORE_SHD1C_0D_LED1_SEL_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD1C_0D_LED1_SEL_BITS                    4
#define BRPHY4_GPHY_CORE_SHD1C_0D_LED1_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_0E
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_0E :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_0E_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_0E_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0E_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_0E_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_0E :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0E,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0E_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0E,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_0E_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_0E_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0E_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_0E_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_0E :: reserved1 [09:08] */
#define BRPHY4_GPHY_CORE_SHD1C_0E_RESERVED1_MASK                   0x0300
#define BRPHY4_GPHY_CORE_SHD1C_0E_RESERVED1_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0E_RESERVED1_BITS                   2
#define BRPHY4_GPHY_CORE_SHD1C_0E_RESERVED1_SHIFT                  8

/* BRPHY4_GPHY_CORE :: SHD1C_0E :: LED4_SEL [07:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0E_LED4_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0E,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0E_LED4_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0E,0xf0,4)
#define BRPHY4_GPHY_CORE_SHD1C_0E_LED4_SEL_MASK                    0x00f0
#define BRPHY4_GPHY_CORE_SHD1C_0E_LED4_SEL_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD1C_0E_LED4_SEL_BITS                    4
#define BRPHY4_GPHY_CORE_SHD1C_0E_LED4_SEL_SHIFT                   4

/* BRPHY4_GPHY_CORE :: SHD1C_0E :: LED3_SEL [03:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0E_LED3_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0E,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0E_LED3_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0E,0xf,0)
#define BRPHY4_GPHY_CORE_SHD1C_0E_LED3_SEL_MASK                    0x000f
#define BRPHY4_GPHY_CORE_SHD1C_0E_LED3_SEL_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD1C_0E_LED3_SEL_BITS                    4
#define BRPHY4_GPHY_CORE_SHD1C_0E_LED3_SEL_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_0F
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_0F :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_0F_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_0F_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0F_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_0F_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_0F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0F,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0F_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0F,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_0F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_0F_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0F_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_0F_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_0F :: reserved1 [09:04] */
#define BRPHY4_GPHY_CORE_SHD1C_0F_RESERVED1_MASK                   0x03f0
#define BRPHY4_GPHY_CORE_SHD1C_0F_RESERVED1_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_0F_RESERVED1_BITS                   6
#define BRPHY4_GPHY_CORE_SHD1C_0F_RESERVED1_SHIFT                  4

/* BRPHY4_GPHY_CORE :: SHD1C_0F :: CURRENT_MODE_LED_EN [03:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_0F,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_0F,0xf,0)
#define BRPHY4_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_MASK         0x000f
#define BRPHY4_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_BITS         4
#define BRPHY4_GPHY_CORE_SHD1C_0F_CURRENT_MODE_LED_EN_SHIFT        0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_10
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_10 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_10_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_10_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_10_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_10_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_10 :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_10_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_10_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_10_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_10_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_10_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_10 :: reserved1 [09:08] */
#define BRPHY4_GPHY_CORE_SHD1C_10_RESERVED1_MASK                   0x0300
#define BRPHY4_GPHY_CORE_SHD1C_10_RESERVED1_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_10_RESERVED1_BITS                   2
#define BRPHY4_GPHY_CORE_SHD1C_10_RESERVED1_SHIFT                  8

/* BRPHY4_GPHY_CORE :: SHD1C_10 :: SPARE_REG [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_10_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_10_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_10_SPARE_REG_MASK                   0x0080
#define BRPHY4_GPHY_CORE_SHD1C_10_SPARE_REG_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_10_SPARE_REG_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_10_SPARE_REG_SHIFT                  7

/* BRPHY4_GPHY_CORE :: SHD1C_10 :: USE_ALT_LINKFLT [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x40,6)
#define BRPHY4_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_MASK             0x0040
#define BRPHY4_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_BITS             1
#define BRPHY4_GPHY_CORE_SHD1C_10_USE_ALT_LINKFLT_SHIFT            6

/* BRPHY4_GPHY_CORE :: SHD1C_10 :: VISIBLE_BLINK [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_10_VISIBLE_BLINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x20,5)
#define BRPHY4_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_MASK               0x0020
#define BRPHY4_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_BITS               1
#define BRPHY4_GPHY_CORE_SHD1C_10_VISIBLE_BLINK_SHIFT              5

/* BRPHY4_GPHY_CORE :: SHD1C_10 :: ENHANCED_PWR [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_10_ENHANCED_PWR(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0x10,4)
#define BRPHY4_GPHY_CORE_SHD1C_10_ENHANCED_PWR_MASK                0x0010
#define BRPHY4_GPHY_CORE_SHD1C_10_ENHANCED_PWR_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD1C_10_ENHANCED_PWR_BITS                1
#define BRPHY4_GPHY_CORE_SHD1C_10_ENHANCED_PWR_SHIFT               4

/* BRPHY4_GPHY_CORE :: SHD1C_10 :: DISCONNECT_TIMER_VALUE [03:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_10,0xf,0)
#define BRPHY4_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_MASK      0x000f
#define BRPHY4_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_ALIGN     0
#define BRPHY4_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_BITS      4
#define BRPHY4_GPHY_CORE_SHD1C_10_DISCONNECT_TIMER_VALUE_SHIFT     0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD1C_1F
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD1C_1F :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD1C_1F_RESERVED0_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD1C_1F_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_1F_RESERVED0_BITS                   1
#define BRPHY4_GPHY_CORE_SHD1C_1F_RESERVED0_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: SHD1C_SEL [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_SHD1C_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD1C_1F_SHD1C_SEL_MASK                   0x7c00
#define BRPHY4_GPHY_CORE_SHD1C_1F_SHD1C_SEL_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD1C_1F_SHD1C_SEL_BITS                   5
#define BRPHY4_GPHY_CORE_SHD1C_1F_SHD1C_SEL_SHIFT                  10

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: DUAL_SERDES_CAPABLE [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x200,9)
#define BRPHY4_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_MASK         0x0200
#define BRPHY4_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_BITS         1
#define BRPHY4_GPHY_CORE_SHD1C_1F_DUAL_SERDES_CAPABLE_SHIFT        9

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: MODE_SEL_CHANGE [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x100,8)
#define BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_MASK             0x0100
#define BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_BITS             1
#define BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_CHANGE_SHIFT            8

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: COPPER_LINK [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_LINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x80,7)
#define BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_LINK_MASK                 0x0080
#define BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_LINK_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_LINK_BITS                 1
#define BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_LINK_SHIFT                7

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: SERDES_LINK [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_LINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x40,6)
#define BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_LINK_MASK                 0x0040
#define BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_LINK_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_LINK_BITS                 1
#define BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_LINK_SHIFT                6

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: COPPER_ENG_DET [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x20,5)
#define BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_MASK              0x0020
#define BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_BITS              1
#define BRPHY4_GPHY_CORE_SHD1C_1F_COPPER_ENG_DET_SHIFT             5

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: FIBER_SIGNAL_DET [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x10,4)
#define BRPHY4_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_MASK            0x0010
#define BRPHY4_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_BITS            1
#define BRPHY4_GPHY_CORE_SHD1C_1F_FIBER_SIGNAL_DET_SHIFT           4

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: SERDES_CAPABLE [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x8,3)
#define BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_MASK              0x0008
#define BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_BITS              1
#define BRPHY4_GPHY_CORE_SHD1C_1F_SERDES_CAPABLE_SHIFT             3

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: MODE_SEL [02:01] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x6,1,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x6,1)
#define BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_MASK                    0x0006
#define BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_BITS                    2
#define BRPHY4_GPHY_CORE_SHD1C_1F_MODE_SEL_SHIFT                   1

/* BRPHY4_GPHY_CORE :: SHD1C_1F :: REG_1000X_EN [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD1C_1F_REG_1000X_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD1C_1F,0x1,0)
#define BRPHY4_GPHY_CORE_SHD1C_1F_REG_1000X_EN_MASK                0x0001
#define BRPHY4_GPHY_CORE_SHD1C_1F_REG_1000X_EN_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD1C_1F_REG_1000X_EN_BITS                1
#define BRPHY4_GPHY_CORE_SHD1C_1F_REG_1000X_EN_SHIFT               0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD18_000
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD18_000 :: EXT_LPBK [15:15] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_EXT_LPBK(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_EXT_LPBK(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x8000,15)
#define BRPHY4_GPHY_CORE_SHD18_000_EXT_LPBK_MASK                   0x8000
#define BRPHY4_GPHY_CORE_SHD18_000_EXT_LPBK_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD18_000_EXT_LPBK_BITS                   1
#define BRPHY4_GPHY_CORE_SHD18_000_EXT_LPBK_SHIFT                  15

/* BRPHY4_GPHY_CORE :: SHD18_000 :: EXT_PKT_LEN [14:14] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_EXT_PKT_LEN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x4000,14)
#define BRPHY4_GPHY_CORE_SHD18_000_EXT_PKT_LEN_MASK                0x4000
#define BRPHY4_GPHY_CORE_SHD18_000_EXT_PKT_LEN_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_000_EXT_PKT_LEN_BITS                1
#define BRPHY4_GPHY_CORE_SHD18_000_EXT_PKT_LEN_SHIFT               14

/* BRPHY4_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_1000T [13:12] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x3000,12,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x3000,12)
#define BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_MASK         0x3000
#define BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_BITS         2
#define BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_1000T_SHIFT        12

/* BRPHY4_GPHY_CORE :: SHD18_000 :: SM_DSP_CLK_EN [11:11] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x800,11)
#define BRPHY4_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_MASK              0x0800
#define BRPHY4_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_BITS              1
#define BRPHY4_GPHY_CORE_SHD18_000_SM_DSP_CLK_EN_SHIFT             11

/* BRPHY4_GPHY_CORE :: SHD18_000 :: TX_6DB_CODING [10:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_TX_6DB_CODING(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x400,10)
#define BRPHY4_GPHY_CORE_SHD18_000_TX_6DB_CODING_MASK              0x0400
#define BRPHY4_GPHY_CORE_SHD18_000_TX_6DB_CODING_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD18_000_TX_6DB_CODING_BITS              1
#define BRPHY4_GPHY_CORE_SHD18_000_TX_6DB_CODING_SHIFT             10

/* BRPHY4_GPHY_CORE :: SHD18_000 :: RCV_SLICING [09:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_RCV_SLICING(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x300,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_RCV_SLICING(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x300,8)
#define BRPHY4_GPHY_CORE_SHD18_000_RCV_SLICING_MASK                0x0300
#define BRPHY4_GPHY_CORE_SHD18_000_RCV_SLICING_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_000_RCV_SLICING_BITS                2
#define BRPHY4_GPHY_CORE_SHD18_000_RCV_SLICING_SHIFT               8

/* BRPHY4_GPHY_CORE :: SHD18_000 :: PRF_DIS [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_PRF_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_PRF_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x80,7)
#define BRPHY4_GPHY_CORE_SHD18_000_PRF_DIS_MASK                    0x0080
#define BRPHY4_GPHY_CORE_SHD18_000_PRF_DIS_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD18_000_PRF_DIS_BITS                    1
#define BRPHY4_GPHY_CORE_SHD18_000_PRF_DIS_SHIFT                   7

/* BRPHY4_GPHY_CORE :: SHD18_000 :: INVERSE_PRF_DIS [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x40,6)
#define BRPHY4_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_MASK            0x0040
#define BRPHY4_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_000_INVERSE_PRF_DIS_SHIFT           6

/* BRPHY4_GPHY_CORE :: SHD18_000 :: EDGERATE_CTL_100TX [05:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x30,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x30,4)
#define BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_MASK         0x0030
#define BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_BITS         2
#define BRPHY4_GPHY_CORE_SHD18_000_EDGERATE_CTL_100TX_SHIFT        4

/* BRPHY4_GPHY_CORE :: SHD18_000 :: DIAGNOSTIC [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_DIAGNOSTIC(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x8,3)
#define BRPHY4_GPHY_CORE_SHD18_000_DIAGNOSTIC_MASK                 0x0008
#define BRPHY4_GPHY_CORE_SHD18_000_DIAGNOSTIC_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD18_000_DIAGNOSTIC_BITS                 1
#define BRPHY4_GPHY_CORE_SHD18_000_DIAGNOSTIC_SHIFT                3

/* BRPHY4_GPHY_CORE :: SHD18_000 :: SHD18_SEL [02:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_000_SHD18_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_000_SHD18_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_000,0x7,0)
#define BRPHY4_GPHY_CORE_SHD18_000_SHD18_SEL_MASK                  0x0007
#define BRPHY4_GPHY_CORE_SHD18_000_SHD18_SEL_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_000_SHD18_SEL_BITS                  3
#define BRPHY4_GPHY_CORE_SHD18_000_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD18_001
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD18_001 :: MANCHESTER_CODE_ERR [15:15] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x8000,15)
#define BRPHY4_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_MASK        0x8000
#define BRPHY4_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_ALIGN       0
#define BRPHY4_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_BITS        1
#define BRPHY4_GPHY_CORE_SHD18_001_MANCHESTER_CODE_ERR_SHIFT       15

/* BRPHY4_GPHY_CORE :: SHD18_001 :: EOF_ERR [14:14] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_EOF_ERR(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_EOF_ERR(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x4000,14)
#define BRPHY4_GPHY_CORE_SHD18_001_EOF_ERR_MASK                    0x4000
#define BRPHY4_GPHY_CORE_SHD18_001_EOF_ERR_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD18_001_EOF_ERR_BITS                    1
#define BRPHY4_GPHY_CORE_SHD18_001_EOF_ERR_SHIFT                   14

/* BRPHY4_GPHY_CORE :: SHD18_001 :: POLARITY_ERR [13:13] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_POLARITY_ERR(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_POLARITY_ERR(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x2000,13)
#define BRPHY4_GPHY_CORE_SHD18_001_POLARITY_ERR_MASK               0x2000
#define BRPHY4_GPHY_CORE_SHD18_001_POLARITY_ERR_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD18_001_POLARITY_ERR_BITS               1
#define BRPHY4_GPHY_CORE_SHD18_001_POLARITY_ERR_SHIFT              13

/* BRPHY4_GPHY_CORE :: SHD18_001 :: BLOCK_RXDV_EXT [12:12] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x1000,12)
#define BRPHY4_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_MASK             0x1000
#define BRPHY4_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_BITS             1
#define BRPHY4_GPHY_CORE_SHD18_001_BLOCK_RXDV_EXT_SHIFT            12

/* BRPHY4_GPHY_CORE :: SHD18_001 :: BT_TXC_INV [11:11] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_BT_TXC_INV(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_BT_TXC_INV(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x800,11)
#define BRPHY4_GPHY_CORE_SHD18_001_BT_TXC_INV_MASK                 0x0800
#define BRPHY4_GPHY_CORE_SHD18_001_BT_TXC_INV_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD18_001_BT_TXC_INV_BITS                 1
#define BRPHY4_GPHY_CORE_SHD18_001_BT_TXC_INV_SHIFT                11

/* BRPHY4_GPHY_CORE :: SHD18_001 :: CLASS_AB_DRIVER_SEL [10:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x400,10)
#define BRPHY4_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_MASK        0x0400
#define BRPHY4_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_ALIGN       0
#define BRPHY4_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_BITS        1
#define BRPHY4_GPHY_CORE_SHD18_001_CLASS_AB_DRIVER_SEL_SHIFT       10

/* BRPHY4_GPHY_CORE :: SHD18_001 :: JABBER_DIS [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_JABBER_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_JABBER_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x200,9)
#define BRPHY4_GPHY_CORE_SHD18_001_JABBER_DIS_MASK                 0x0200
#define BRPHY4_GPHY_CORE_SHD18_001_JABBER_DIS_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD18_001_JABBER_DIS_BITS                 1
#define BRPHY4_GPHY_CORE_SHD18_001_JABBER_DIS_SHIFT                9

/* BRPHY4_GPHY_CORE :: SHD18_001 :: BT_SIG_DET_AUTOSWITCH [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x100,8)
#define BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_MASK      0x0100
#define BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_ALIGN     0
#define BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_BITS      1
#define BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DET_AUTOSWITCH_SHIFT     8

/* BRPHY4_GPHY_CORE :: SHD18_001 :: BT_SIG_DETECT_THD [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x80,7)
#define BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_MASK          0x0080
#define BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_BITS          1
#define BRPHY4_GPHY_CORE_SHD18_001_BT_SIG_DETECT_THD_SHIFT         7

/* BRPHY4_GPHY_CORE :: SHD18_001 :: BT_ECHO [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_BT_ECHO(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_BT_ECHO(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x40,6)
#define BRPHY4_GPHY_CORE_SHD18_001_BT_ECHO_MASK                    0x0040
#define BRPHY4_GPHY_CORE_SHD18_001_BT_ECHO_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD18_001_BT_ECHO_BITS                    1
#define BRPHY4_GPHY_CORE_SHD18_001_BT_ECHO_SHIFT                   6

/* BRPHY4_GPHY_CORE :: SHD18_001 :: SQE_EN [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_SQE_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_SQE_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x20,5)
#define BRPHY4_GPHY_CORE_SHD18_001_SQE_EN_MASK                     0x0020
#define BRPHY4_GPHY_CORE_SHD18_001_SQE_EN_ALIGN                    0
#define BRPHY4_GPHY_CORE_SHD18_001_SQE_EN_BITS                     1
#define BRPHY4_GPHY_CORE_SHD18_001_SQE_EN_SHIFT                    5

/* BRPHY4_GPHY_CORE :: SHD18_001 :: BT_NO_DRIBBLE [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x10,4)
#define BRPHY4_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_MASK              0x0010
#define BRPHY4_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_BITS              1
#define BRPHY4_GPHY_CORE_SHD18_001_BT_NO_DRIBBLE_SHIFT             4

/* BRPHY4_GPHY_CORE :: SHD18_001 :: BT_POL_ERR_CNT_MAX [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x8,3)
#define BRPHY4_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_MASK         0x0008
#define BRPHY4_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_BITS         1
#define BRPHY4_GPHY_CORE_SHD18_001_BT_POL_ERR_CNT_MAX_SHIFT        3

/* BRPHY4_GPHY_CORE :: SHD18_001 :: SHD18_SEL [02:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_001_SHD18_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_001_SHD18_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_001,0x7,0)
#define BRPHY4_GPHY_CORE_SHD18_001_SHD18_SEL_MASK                  0x0007
#define BRPHY4_GPHY_CORE_SHD18_001_SHD18_SEL_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_001_SHD18_SEL_BITS                  3
#define BRPHY4_GPHY_CORE_SHD18_001_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD18_010
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD18_010 :: SPARE_REG_3 [15:11] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_3(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0xf800,11,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_3(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0xf800,11)
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_3_MASK                0xf800
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_3_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_3_BITS                5
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_3_SHIFT               11

/* BRPHY4_GPHY_CORE :: SHD18_010 :: SPARE_REG_2 [10:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_2(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x7c0,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_2(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x7c0,6)
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_2_MASK                0x07c0
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_2_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_2_BITS                5
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_2_SHIFT               6

/* BRPHY4_GPHY_CORE :: SHD18_010 :: SUPER_ISOLATE [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_010_SUPER_ISOLATE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x20,5)
#define BRPHY4_GPHY_CORE_SHD18_010_SUPER_ISOLATE_MASK              0x0020
#define BRPHY4_GPHY_CORE_SHD18_010_SUPER_ISOLATE_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD18_010_SUPER_ISOLATE_BITS              1
#define BRPHY4_GPHY_CORE_SHD18_010_SUPER_ISOLATE_SHIFT             5

/* BRPHY4_GPHY_CORE :: SHD18_010 :: SPARE_REG_1 [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_1(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_1(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x10,4)
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_1_MASK                0x0010
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_1_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_1_BITS                1
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_1_SHIFT               4

/* BRPHY4_GPHY_CORE :: SHD18_010 :: SPARE_REG_0 [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_0(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_0(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x8,3)
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_0_MASK                0x0008
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_0_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_0_BITS                1
#define BRPHY4_GPHY_CORE_SHD18_010_SPARE_REG_0_SHIFT               3

/* BRPHY4_GPHY_CORE :: SHD18_010 :: SHD18_SEL [02:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_010_SHD18_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_010_SHD18_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_010,0x7,0)
#define BRPHY4_GPHY_CORE_SHD18_010_SHD18_SEL_MASK                  0x0007
#define BRPHY4_GPHY_CORE_SHD18_010_SHD18_SEL_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_010_SHD18_SEL_BITS                  3
#define BRPHY4_GPHY_CORE_SHD18_010_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD18_011
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD18_011 :: IP_PHONE_DETECT [15:15] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DETECT(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x8000,15)
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_MASK            0x8000
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DETECT_SHIFT           15

/* BRPHY4_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_CNTR [14:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x7c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x7c00,10)
#define BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_MASK          0x7c00
#define BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_BITS          5
#define BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_CNTR_SHIFT         10

/* BRPHY4_GPHY_CORE :: SHD18_011 :: ALT_RANDOM_SEED [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x200,9)
#define BRPHY4_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_MASK            0x0200
#define BRPHY4_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_011_ALT_RANDOM_SEED_SHIFT           9

/* BRPHY4_GPHY_CORE :: SHD18_011 :: RESTART_AUTONEG [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_RESTART_AUTONEG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x100,8)
#define BRPHY4_GPHY_CORE_SHD18_011_RESTART_AUTONEG_MASK            0x0100
#define BRPHY4_GPHY_CORE_SHD18_011_RESTART_AUTONEG_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_011_RESTART_AUTONEG_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_011_RESTART_AUTONEG_SHIFT           8

/* BRPHY4_GPHY_CORE :: SHD18_011 :: IP_PHONE_WINDOW [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x80,7)
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_MASK            0x0080
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_WINDOW_SHIFT           7

/* BRPHY4_GPHY_CORE :: SHD18_011 :: EXT_LP_WIDTH_EN [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x40,6)
#define BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_MASK            0x0040
#define BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_011_EXT_LP_WIDTH_EN_SHIFT           6

/* BRPHY4_GPHY_CORE :: SHD18_011 :: IP_PHONE_DET_EN [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x20,5)
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_MASK            0x0020
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_011_IP_PHONE_DET_EN_SHIFT           5

/* BRPHY4_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_DIS [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x10,4)
#define BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_MASK      0x0010
#define BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_ALIGN     0
#define BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_BITS      1
#define BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_DIS_SHIFT     4

/* BRPHY4_GPHY_CORE :: SHD18_011 :: BLK_LINK10_WINDOW_SW [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x8,3)
#define BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_MASK       0x0008
#define BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_ALIGN      0
#define BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_BITS       1
#define BRPHY4_GPHY_CORE_SHD18_011_BLK_LINK10_WINDOW_SW_SHIFT      3

/* BRPHY4_GPHY_CORE :: SHD18_011 :: SHD18_SEL [02:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_011_SHD18_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_011_SHD18_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_011,0x7,0)
#define BRPHY4_GPHY_CORE_SHD18_011_SHD18_SEL_MASK                  0x0007
#define BRPHY4_GPHY_CORE_SHD18_011_SHD18_SEL_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_011_SHD18_SEL_BITS                  3
#define BRPHY4_GPHY_CORE_SHD18_011_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD18_100
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD18_100 :: RMT_LPBK_EN [15:15] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x8000,15)
#define BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_EN_MASK                0x8000
#define BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_EN_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_EN_BITS                1
#define BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_EN_SHIFT               15

/* BRPHY4_GPHY_CORE :: SHD18_100 :: TDK_FIX_EN [14:14] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_TDK_FIX_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x4000,14)
#define BRPHY4_GPHY_CORE_SHD18_100_TDK_FIX_EN_MASK                 0x4000
#define BRPHY4_GPHY_CORE_SHD18_100_TDK_FIX_EN_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD18_100_TDK_FIX_EN_BITS                 1
#define BRPHY4_GPHY_CORE_SHD18_100_TDK_FIX_EN_SHIFT                14

/* BRPHY4_GPHY_CORE :: SHD18_100 :: BT_DLL_BYPASS_CLK [13:13] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x2000,13)
#define BRPHY4_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_MASK          0x2000
#define BRPHY4_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_BITS          1
#define BRPHY4_GPHY_CORE_SHD18_100_BT_DLL_BYPASS_CLK_SHIFT         13

/* BRPHY4_GPHY_CORE :: SHD18_100 :: BLOCK_10BT_RESTART_AUTONEG [12:12] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x1000,12)
#define BRPHY4_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_MASK 0x1000
#define BRPHY4_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_ALIGN 0
#define BRPHY4_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_BITS 1
#define BRPHY4_GPHY_CORE_SHD18_100_BLOCK_10BT_RESTART_AUTONEG_SHIFT 12

/* BRPHY4_GPHY_CORE :: SHD18_100 :: RMT_LPBK_TRISTATE [11:11] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x800,11)
#define BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_MASK          0x0800
#define BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_BITS          1
#define BRPHY4_GPHY_CORE_SHD18_100_RMT_LPBK_TRISTATE_SHIFT         11

/* BRPHY4_GPHY_CORE :: SHD18_100 :: BT_WAKEUP [10:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_BT_WAKEUP(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_BT_WAKEUP(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x400,10)
#define BRPHY4_GPHY_CORE_SHD18_100_BT_WAKEUP_MASK                  0x0400
#define BRPHY4_GPHY_CORE_SHD18_100_BT_WAKEUP_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_100_BT_WAKEUP_BITS                  1
#define BRPHY4_GPHY_CORE_SHD18_100_BT_WAKEUP_SHIFT                 10

/* BRPHY4_GPHY_CORE :: SHD18_100 :: BT_POLARITY_BYPASS [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x200,9)
#define BRPHY4_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_MASK         0x0200
#define BRPHY4_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_ALIGN        0
#define BRPHY4_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_BITS         1
#define BRPHY4_GPHY_CORE_SHD18_100_BT_POLARITY_BYPASS_SHIFT        9

/* BRPHY4_GPHY_CORE :: SHD18_100 :: BT_IDLE_BYPASS [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x100,8)
#define BRPHY4_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_MASK             0x0100
#define BRPHY4_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_BITS             1
#define BRPHY4_GPHY_CORE_SHD18_100_BT_IDLE_BYPASS_SHIFT            8

/* BRPHY4_GPHY_CORE :: SHD18_100 :: BT_CLK_RESET_EN [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x80,7)
#define BRPHY4_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_MASK            0x0080
#define BRPHY4_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_100_BT_CLK_RESET_EN_SHIFT           7

/* BRPHY4_GPHY_CORE :: SHD18_100 :: BT_BYPASS_ADC [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_ADC(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x40,6)
#define BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_MASK              0x0040
#define BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_BITS              1
#define BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_ADC_SHIFT             6

/* BRPHY4_GPHY_CORE :: SHD18_100 :: BT_BYPASS_CRS [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_CRS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x20,5)
#define BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_MASK              0x0020
#define BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_BITS              1
#define BRPHY4_GPHY_CORE_SHD18_100_BT_BYPASS_CRS_SHIFT             5

/* BRPHY4_GPHY_CORE :: SHD18_100 :: SWAP_RXMDIX [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_SWAP_RXMDIX(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x10,4)
#define BRPHY4_GPHY_CORE_SHD18_100_SWAP_RXMDIX_MASK                0x0010
#define BRPHY4_GPHY_CORE_SHD18_100_SWAP_RXMDIX_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_100_SWAP_RXMDIX_BITS                1
#define BRPHY4_GPHY_CORE_SHD18_100_SWAP_RXMDIX_SHIFT               4

/* BRPHY4_GPHY_CORE :: SHD18_100 :: HALFOUT [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_HALFOUT(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_HALFOUT(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x8,3)
#define BRPHY4_GPHY_CORE_SHD18_100_HALFOUT_MASK                    0x0008
#define BRPHY4_GPHY_CORE_SHD18_100_HALFOUT_ALIGN                   0
#define BRPHY4_GPHY_CORE_SHD18_100_HALFOUT_BITS                    1
#define BRPHY4_GPHY_CORE_SHD18_100_HALFOUT_SHIFT                   3

/* BRPHY4_GPHY_CORE :: SHD18_100 :: SHD18_SEL [02:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_100_SHD18_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_100_SHD18_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_100,0x7,0)
#define BRPHY4_GPHY_CORE_SHD18_100_SHD18_SEL_MASK                  0x0007
#define BRPHY4_GPHY_CORE_SHD18_100_SHD18_SEL_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_100_SHD18_SEL_BITS                  3
#define BRPHY4_GPHY_CORE_SHD18_100_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD18_101
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD18_101 :: COPPER_ENG_DET_OV [15:15] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x8000,15)
#define BRPHY4_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_MASK          0x8000
#define BRPHY4_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_BITS          1
#define BRPHY4_GPHY_CORE_SHD18_101_COPPER_ENG_DET_OV_SHIFT         15

/* BRPHY4_GPHY_CORE :: SHD18_101 :: ADCFIFO_TX_FIX [14:14] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x4000,14)
#define BRPHY4_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_MASK             0x4000
#define BRPHY4_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_ALIGN            0
#define BRPHY4_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_BITS             1
#define BRPHY4_GPHY_CORE_SHD18_101_ADCFIFO_TX_FIX_SHIFT            14

/* BRPHY4_GPHY_CORE :: SHD18_101 :: CLASS_AB_DVT_EN [13:13] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x2000,13)
#define BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_MASK            0x2000
#define BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_DVT_EN_SHIFT           13

/* BRPHY4_GPHY_CORE :: SHD18_101 :: CLASS_AB_EN [12:12] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x1000,12)
#define BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_EN_MASK                0x1000
#define BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_EN_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_EN_BITS                1
#define BRPHY4_GPHY_CORE_SHD18_101_CLASS_AB_EN_SHIFT               12

/* BRPHY4_GPHY_CORE :: SHD18_101 :: ENC_ERR_SCALE [11:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0xc00,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_ENC_ERR_SCALE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0xc00,10)
#define BRPHY4_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_MASK              0x0c00
#define BRPHY4_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_ALIGN             0
#define BRPHY4_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_BITS              2
#define BRPHY4_GPHY_CORE_SHD18_101_ENC_ERR_SCALE_SHIFT             10

/* BRPHY4_GPHY_CORE :: SHD18_101 :: SPARE_REG [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x200,9)
#define BRPHY4_GPHY_CORE_SHD18_101_SPARE_REG_MASK                  0x0200
#define BRPHY4_GPHY_CORE_SHD18_101_SPARE_REG_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_101_SPARE_REG_BITS                  1
#define BRPHY4_GPHY_CORE_SHD18_101_SPARE_REG_SHIFT                 9

/* BRPHY4_GPHY_CORE :: SHD18_101 :: AUTO_ENCODING_CORRECTION [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x100,8)
#define BRPHY4_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_MASK   0x0100
#define BRPHY4_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_ALIGN  0
#define BRPHY4_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_BITS   1
#define BRPHY4_GPHY_CORE_SHD18_101_AUTO_ENCODING_CORRECTION_SHIFT  8

/* BRPHY4_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_RX [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x80,7)
#define BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_MASK        0x0080
#define BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_ALIGN       0
#define BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_BITS        1
#define BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_RX_SHIFT       7

/* BRPHY4_GPHY_CORE :: SHD18_101 :: OLD_PCS_ENCODING_TX [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x40,6)
#define BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_MASK        0x0040
#define BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_ALIGN       0
#define BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_BITS        1
#define BRPHY4_GPHY_CORE_SHD18_101_OLD_PCS_ENCODING_TX_SHIFT       6

/* BRPHY4_GPHY_CORE :: SHD18_101 :: EC_AS_NEXT [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_EC_AS_NEXT(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x20,5)
#define BRPHY4_GPHY_CORE_SHD18_101_EC_AS_NEXT_MASK                 0x0020
#define BRPHY4_GPHY_CORE_SHD18_101_EC_AS_NEXT_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD18_101_EC_AS_NEXT_BITS                 1
#define BRPHY4_GPHY_CORE_SHD18_101_EC_AS_NEXT_SHIFT                5

/* BRPHY4_GPHY_CORE :: SHD18_101 :: FORCE_MDIX [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_FORCE_MDIX(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_FORCE_MDIX(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x10,4)
#define BRPHY4_GPHY_CORE_SHD18_101_FORCE_MDIX_MASK                 0x0010
#define BRPHY4_GPHY_CORE_SHD18_101_FORCE_MDIX_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD18_101_FORCE_MDIX_BITS                 1
#define BRPHY4_GPHY_CORE_SHD18_101_FORCE_MDIX_SHIFT                4

/* BRPHY4_GPHY_CORE :: SHD18_101 :: EN_PWRDNTDAC [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_EN_PWRDNTDAC(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x8,3)
#define BRPHY4_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_MASK               0x0008
#define BRPHY4_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_BITS               1
#define BRPHY4_GPHY_CORE_SHD18_101_EN_PWRDNTDAC_SHIFT              3

/* BRPHY4_GPHY_CORE :: SHD18_101 :: SHD18_SEL [02:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_101_SHD18_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_101_SHD18_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_101,0x7,0)
#define BRPHY4_GPHY_CORE_SHD18_101_SHD18_SEL_MASK                  0x0007
#define BRPHY4_GPHY_CORE_SHD18_101_SHD18_SEL_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_101_SHD18_SEL_BITS                  3
#define BRPHY4_GPHY_CORE_SHD18_101_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD18_110
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD18_110 :: IP_PHONE_SEED_WR_EN [15:15] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_110,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_110,0x8000,15)
#define BRPHY4_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_MASK        0x8000
#define BRPHY4_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_ALIGN       0
#define BRPHY4_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_BITS        1
#define BRPHY4_GPHY_CORE_SHD18_110_IP_PHONE_SEED_WR_EN_SHIFT       15

/* BRPHY4_GPHY_CORE :: SHD18_110 :: SPARE_REG [14:14] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_110_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_110,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_110_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_110,0x4000,14)
#define BRPHY4_GPHY_CORE_SHD18_110_SPARE_REG_MASK                  0x4000
#define BRPHY4_GPHY_CORE_SHD18_110_SPARE_REG_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_110_SPARE_REG_BITS                  1
#define BRPHY4_GPHY_CORE_SHD18_110_SPARE_REG_SHIFT                 14

/* BRPHY4_GPHY_CORE :: SHD18_110 :: LOC_IP_PHONE_SEED [13:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_110,0x3ff8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_110,0x3ff8,3)
#define BRPHY4_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_MASK          0x3ff8
#define BRPHY4_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_ALIGN         0
#define BRPHY4_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_BITS          11
#define BRPHY4_GPHY_CORE_SHD18_110_LOC_IP_PHONE_SEED_SHIFT         3

/* BRPHY4_GPHY_CORE :: SHD18_110 :: SHD18_SEL [02:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_110_SHD18_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_110,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_110_SHD18_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_110,0x7,0)
#define BRPHY4_GPHY_CORE_SHD18_110_SHD18_SEL_MASK                  0x0007
#define BRPHY4_GPHY_CORE_SHD18_110_SHD18_SEL_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_110_SHD18_SEL_BITS                  3
#define BRPHY4_GPHY_CORE_SHD18_110_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SHD18_111
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SHD18_111 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_SHD18_111_RESERVED0_MASK                  0x8000
#define BRPHY4_GPHY_CORE_SHD18_111_RESERVED0_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_111_RESERVED0_BITS                  1
#define BRPHY4_GPHY_CORE_SHD18_111_RESERVED0_SHIFT                 15

/* BRPHY4_GPHY_CORE :: SHD18_111 :: SHD18_RDSEL [14:12] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x7000,12,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_SHD18_RDSEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x7000,12)
#define BRPHY4_GPHY_CORE_SHD18_111_SHD18_RDSEL_MASK                0x7000
#define BRPHY4_GPHY_CORE_SHD18_111_SHD18_RDSEL_ALIGN               0
#define BRPHY4_GPHY_CORE_SHD18_111_SHD18_RDSEL_BITS                3
#define BRPHY4_GPHY_CORE_SHD18_111_SHD18_RDSEL_SHIFT               12

/* BRPHY4_GPHY_CORE :: SHD18_111 :: PKT_CNTR [11:11] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_PKT_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_PKT_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x800,11)
#define BRPHY4_GPHY_CORE_SHD18_111_PKT_CNTR_MASK                   0x0800
#define BRPHY4_GPHY_CORE_SHD18_111_PKT_CNTR_ALIGN                  0
#define BRPHY4_GPHY_CORE_SHD18_111_PKT_CNTR_BITS                   1
#define BRPHY4_GPHY_CORE_SHD18_111_PKT_CNTR_SHIFT                  11

/* BRPHY4_GPHY_CORE :: SHD18_111 :: BYPASS_WIRESPEED_TIMER [10:10] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x400,10)
#define BRPHY4_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_MASK     0x0400
#define BRPHY4_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_ALIGN    0
#define BRPHY4_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_BITS     1
#define BRPHY4_GPHY_CORE_SHD18_111_BYPASS_WIRESPEED_TIMER_SHIFT    10

/* BRPHY4_GPHY_CORE :: SHD18_111 :: FORCE_AUTO_MDIX [09:09] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x200,9)
#define BRPHY4_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_MASK            0x0200
#define BRPHY4_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_ALIGN           0
#define BRPHY4_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_BITS            1
#define BRPHY4_GPHY_CORE_SHD18_111_FORCE_AUTO_MDIX_SHIFT           9

/* BRPHY4_GPHY_CORE :: SHD18_111 :: RGMII_TIMING [08:08] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_RGMII_TIMING(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_RGMII_TIMING(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x100,8)
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_TIMING_MASK               0x0100
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_TIMING_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_TIMING_BITS               1
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_TIMING_SHIFT              8

/* BRPHY4_GPHY_CORE :: SHD18_111 :: RGMII [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_RGMII(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_RGMII(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x80,7)
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_MASK                      0x0080
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_ALIGN                     0
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_BITS                      1
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_SHIFT                     7

/* BRPHY4_GPHY_CORE :: SHD18_111 :: RGMII_RXER [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_RGMII_RXER(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_RGMII_RXER(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x40,6)
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_RXER_MASK                 0x0040
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_RXER_ALIGN                0
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_RXER_BITS                 1
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_RXER_SHIFT                6

/* BRPHY4_GPHY_CORE :: SHD18_111 :: RGMII_OB_STATUS_DIS [05:05] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x20,5)
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_MASK        0x0020
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_ALIGN       0
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_BITS        1
#define BRPHY4_GPHY_CORE_SHD18_111_RGMII_OB_STATUS_DIS_SHIFT       5

/* BRPHY4_GPHY_CORE :: SHD18_111 :: WIRESPEED_EN [04:04] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_WIRESPEED_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x10,4)
#define BRPHY4_GPHY_CORE_SHD18_111_WIRESPEED_EN_MASK               0x0010
#define BRPHY4_GPHY_CORE_SHD18_111_WIRESPEED_EN_ALIGN              0
#define BRPHY4_GPHY_CORE_SHD18_111_WIRESPEED_EN_BITS               1
#define BRPHY4_GPHY_CORE_SHD18_111_WIRESPEED_EN_SHIFT              4

/* BRPHY4_GPHY_CORE :: SHD18_111 :: MDIO_ALL_PHY_SEL [03:03] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x8,3)
#define BRPHY4_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_MASK           0x0008
#define BRPHY4_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_ALIGN          0
#define BRPHY4_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_BITS           1
#define BRPHY4_GPHY_CORE_SHD18_111_MDIO_ALL_PHY_SEL_SHIFT          3

/* BRPHY4_GPHY_CORE :: SHD18_111 :: SHD18_SEL [02:00] */
#define Wr_BRPHY4_GPHY_CORE_SHD18_111_SHD18_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_SHD18_111_SHD18_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SHD18_111,0x7,0)
#define BRPHY4_GPHY_CORE_SHD18_111_SHD18_SEL_MASK                  0x0007
#define BRPHY4_GPHY_CORE_SHD18_111_SHD18_SEL_ALIGN                 0
#define BRPHY4_GPHY_CORE_SHD18_111_SHD18_SEL_BITS                  3
#define BRPHY4_GPHY_CORE_SHD18_111_SHD18_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP00
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP00 :: PKT_CNTR [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP00_PKT_CNTR(x) WriteReg16(BRPHY4_GPHY_CORE_EXP00,x)
#define Rd_BRPHY4_GPHY_CORE_EXP00_PKT_CNTR(x) ReadReg16(BRPHY4_GPHY_CORE_EXP00)
#define BRPHY4_GPHY_CORE_EXP00_PKT_CNTR_MASK                       0xffff
#define BRPHY4_GPHY_CORE_EXP00_PKT_CNTR_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP00_PKT_CNTR_BITS                       16
#define BRPHY4_GPHY_CORE_EXP00_PKT_CNTR_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP01
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP01 :: LATE_COL_CNTR [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_LATE_COL_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_LATE_COL_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x8000,15)
#define BRPHY4_GPHY_CORE_EXP01_LATE_COL_CNTR_MASK                  0x8000
#define BRPHY4_GPHY_CORE_EXP01_LATE_COL_CNTR_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP01_LATE_COL_CNTR_BITS                  1
#define BRPHY4_GPHY_CORE_EXP01_LATE_COL_CNTR_SHIFT                 15

/* BRPHY4_GPHY_CORE :: EXP01 :: RMT_COPPER_ERR [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_RMT_COPPER_ERR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x4000,14)
#define BRPHY4_GPHY_CORE_EXP01_RMT_COPPER_ERR_MASK                 0x4000
#define BRPHY4_GPHY_CORE_EXP01_RMT_COPPER_ERR_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP01_RMT_COPPER_ERR_BITS                 1
#define BRPHY4_GPHY_CORE_EXP01_RMT_COPPER_ERR_SHIFT                14

/* BRPHY4_GPHY_CORE :: EXP01 :: SERDES_LINK_PARTNER_RESTARTED [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x2000,13)
#define BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_MASK  0x2000
#define BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_ALIGN 0
#define BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_BITS  1
#define BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_PARTNER_RESTARTED_SHIFT 13

/* BRPHY4_GPHY_CORE :: EXP01 :: SERDES_CRC_ERR [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_SERDES_CRC_ERR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP01_SERDES_CRC_ERR_MASK                 0x1000
#define BRPHY4_GPHY_CORE_EXP01_SERDES_CRC_ERR_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP01_SERDES_CRC_ERR_BITS                 1
#define BRPHY4_GPHY_CORE_EXP01_SERDES_CRC_ERR_SHIFT                12

/* BRPHY4_GPHY_CORE :: EXP01 :: SGMII_SLAVE_CHANGE [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x800,11)
#define BRPHY4_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_MASK             0x0800
#define BRPHY4_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_ALIGN            0
#define BRPHY4_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_BITS             1
#define BRPHY4_GPHY_CORE_EXP01_SGMII_SLAVE_CHANGE_SHIFT            11

/* BRPHY4_GPHY_CORE :: EXP01 :: FX_SERDES_CHANGE [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_FX_SERDES_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x400,10)
#define BRPHY4_GPHY_CORE_EXP01_FX_SERDES_CHANGE_MASK               0x0400
#define BRPHY4_GPHY_CORE_EXP01_FX_SERDES_CHANGE_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP01_FX_SERDES_CHANGE_BITS               1
#define BRPHY4_GPHY_CORE_EXP01_FX_SERDES_CHANGE_SHIFT              10

/* BRPHY4_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_PAGE_RCVD [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x200,9)
#define BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_MASK       0x0200
#define BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_ALIGN      0
#define BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_BITS       1
#define BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_PAGE_RCVD_SHIFT      9

/* BRPHY4_GPHY_CORE :: EXP01 :: EXT_SERDES_SEL_CHANGE [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x100,8)
#define BRPHY4_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_MASK          0x0100
#define BRPHY4_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_ALIGN         0
#define BRPHY4_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_BITS          1
#define BRPHY4_GPHY_CORE_EXP01_EXT_SERDES_SEL_CHANGE_SHIFT         8

/* BRPHY4_GPHY_CORE :: EXP01 :: MODE_SEL_CHANGE [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_MODE_SEL_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x80,7)
#define BRPHY4_GPHY_CORE_EXP01_MODE_SEL_CHANGE_MASK                0x0080
#define BRPHY4_GPHY_CORE_EXP01_MODE_SEL_CHANGE_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP01_MODE_SEL_CHANGE_BITS                1
#define BRPHY4_GPHY_CORE_EXP01_MODE_SEL_CHANGE_SHIFT               7

/* BRPHY4_GPHY_CORE :: EXP01 :: SERDES_LINK_STATUS_CHANGE [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x40,6)
#define BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_MASK      0x0040
#define BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_ALIGN     0
#define BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_BITS      1
#define BRPHY4_GPHY_CORE_EXP01_SERDES_LINK_STATUS_CHANGE_SHIFT     6

/* BRPHY4_GPHY_CORE :: EXP01 :: RUDI_C_DET [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_RUDI_C_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_RUDI_C_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x20,5)
#define BRPHY4_GPHY_CORE_EXP01_RUDI_C_DET_MASK                     0x0020
#define BRPHY4_GPHY_CORE_EXP01_RUDI_C_DET_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP01_RUDI_C_DET_BITS                     1
#define BRPHY4_GPHY_CORE_EXP01_RUDI_C_DET_SHIFT                    5

/* BRPHY4_GPHY_CORE :: EXP01 :: SERDES_AUTONEG_ERR [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x10,4)
#define BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_MASK             0x0010
#define BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_ALIGN            0
#define BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_BITS             1
#define BRPHY4_GPHY_CORE_EXP01_SERDES_AUTONEG_ERR_SHIFT            4

/* BRPHY4_GPHY_CORE :: EXP01 :: RUDI_I_DET [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_RUDI_I_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_RUDI_I_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x8,3)
#define BRPHY4_GPHY_CORE_EXP01_RUDI_I_DET_MASK                     0x0008
#define BRPHY4_GPHY_CORE_EXP01_RUDI_I_DET_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP01_RUDI_I_DET_BITS                     1
#define BRPHY4_GPHY_CORE_EXP01_RUDI_I_DET_SHIFT                    3

/* BRPHY4_GPHY_CORE :: EXP01 :: SERDES_RCVD_BREAK_LINK_CONDITION [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x4,2)
#define BRPHY4_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_MASK 0x0004
#define BRPHY4_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_ALIGN 0
#define BRPHY4_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_BITS 1
#define BRPHY4_GPHY_CORE_EXP01_SERDES_RCVD_BREAK_LINK_CONDITION_SHIFT 2

/* BRPHY4_GPHY_CORE :: EXP01 :: ABIST_COMPLETE [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_ABIST_COMPLETE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_ABIST_COMPLETE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x2,1)
#define BRPHY4_GPHY_CORE_EXP01_ABIST_COMPLETE_MASK                 0x0002
#define BRPHY4_GPHY_CORE_EXP01_ABIST_COMPLETE_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP01_ABIST_COMPLETE_BITS                 1
#define BRPHY4_GPHY_CORE_EXP01_ABIST_COMPLETE_SHIFT                1

/* BRPHY4_GPHY_CORE :: EXP01 :: TX_CRC_ERR [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP01_TX_CRC_ERR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP01,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP01_TX_CRC_ERR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP01,0x1,0)
#define BRPHY4_GPHY_CORE_EXP01_TX_CRC_ERR_MASK                     0x0001
#define BRPHY4_GPHY_CORE_EXP01_TX_CRC_ERR_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP01_TX_CRC_ERR_BITS                     1
#define BRPHY4_GPHY_CORE_EXP01_TX_CRC_ERR_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP02
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP02 :: EXP_INT_MASK [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP02_EXP_INT_MASK(x) WriteReg16(BRPHY4_GPHY_CORE_EXP02,x)
#define Rd_BRPHY4_GPHY_CORE_EXP02_EXP_INT_MASK(x) ReadReg16(BRPHY4_GPHY_CORE_EXP02)
#define BRPHY4_GPHY_CORE_EXP02_EXP_INT_MASK_MASK                   0xffff
#define BRPHY4_GPHY_CORE_EXP02_EXP_INT_MASK_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP02_EXP_INT_MASK_BITS                   16
#define BRPHY4_GPHY_CORE_EXP02_EXP_INT_MASK_SHIFT                  0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP03
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP03 :: SPARE_REG [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP03_SPARE_REG(x) WriteReg16(BRPHY4_GPHY_CORE_EXP03,x)
#define Rd_BRPHY4_GPHY_CORE_EXP03_SPARE_REG(x) ReadReg16(BRPHY4_GPHY_CORE_EXP03)
#define BRPHY4_GPHY_CORE_EXP03_SPARE_REG_MASK                      0xffff
#define BRPHY4_GPHY_CORE_EXP03_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP03_SPARE_REG_BITS                      16
#define BRPHY4_GPHY_CORE_EXP03_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP04
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP04 :: reserved0 [15:11] */
#define BRPHY4_GPHY_CORE_EXP04_RESERVED0_MASK                      0xf800
#define BRPHY4_GPHY_CORE_EXP04_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP04_RESERVED0_BITS                      5
#define BRPHY4_GPHY_CORE_EXP04_RESERVED0_SHIFT                     11

/* BRPHY4_GPHY_CORE :: EXP04 :: BC_LED_EN [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXP04_BC_LED_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP04,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXP04_BC_LED_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP04,0x400,10)
#define BRPHY4_GPHY_CORE_EXP04_BC_LED_EN_MASK                      0x0400
#define BRPHY4_GPHY_CORE_EXP04_BC_LED_EN_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP04_BC_LED_EN_BITS                      1
#define BRPHY4_GPHY_CORE_EXP04_BC_LED_EN_SHIFT                     10

/* BRPHY4_GPHY_CORE :: EXP04 :: FLASHNOW [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXP04_FLASHNOW(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP04,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXP04_FLASHNOW(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP04,0x200,9)
#define BRPHY4_GPHY_CORE_EXP04_FLASHNOW_MASK                       0x0200
#define BRPHY4_GPHY_CORE_EXP04_FLASHNOW_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP04_FLASHNOW_BITS                       1
#define BRPHY4_GPHY_CORE_EXP04_FLASHNOW_SHIFT                      9

/* BRPHY4_GPHY_CORE :: EXP04 :: INPHASE [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP04_INPHASE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP04,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP04_INPHASE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP04,0x100,8)
#define BRPHY4_GPHY_CORE_EXP04_INPHASE_MASK                        0x0100
#define BRPHY4_GPHY_CORE_EXP04_INPHASE_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP04_INPHASE_BITS                        1
#define BRPHY4_GPHY_CORE_EXP04_INPHASE_SHIFT                       8

/* BRPHY4_GPHY_CORE :: EXP04 :: BC_SEL_1 [07:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP04_BC_SEL_1(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP04,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP04_BC_SEL_1(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP04,0xf0,4)
#define BRPHY4_GPHY_CORE_EXP04_BC_SEL_1_MASK                       0x00f0
#define BRPHY4_GPHY_CORE_EXP04_BC_SEL_1_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP04_BC_SEL_1_BITS                       4
#define BRPHY4_GPHY_CORE_EXP04_BC_SEL_1_SHIFT                      4

/* BRPHY4_GPHY_CORE :: EXP04 :: BC_SEL_0 [03:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP04_BC_SEL_0(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP04,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP04_BC_SEL_0(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP04,0xf,0)
#define BRPHY4_GPHY_CORE_EXP04_BC_SEL_0_MASK                       0x000f
#define BRPHY4_GPHY_CORE_EXP04_BC_SEL_0_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP04_BC_SEL_0_BITS                       4
#define BRPHY4_GPHY_CORE_EXP04_BC_SEL_0_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP05
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP05 :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_EXP05_RESERVED0_MASK                      0xf000
#define BRPHY4_GPHY_CORE_EXP05_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP05_RESERVED0_BITS                      4
#define BRPHY4_GPHY_CORE_EXP05_RESERVED0_SHIFT                     12

/* BRPHY4_GPHY_CORE :: EXP05 :: ALTERNATION_RATE [11:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP05_ALTERNATION_RATE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP05,0xfc0,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP05_ALTERNATION_RATE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP05,0xfc0,6)
#define BRPHY4_GPHY_CORE_EXP05_ALTERNATION_RATE_MASK               0x0fc0
#define BRPHY4_GPHY_CORE_EXP05_ALTERNATION_RATE_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP05_ALTERNATION_RATE_BITS               6
#define BRPHY4_GPHY_CORE_EXP05_ALTERNATION_RATE_SHIFT              6

/* BRPHY4_GPHY_CORE :: EXP05 :: FLASH_RATE [05:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP05_FLASH_RATE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP05,0x3f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP05_FLASH_RATE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP05,0x3f,0)
#define BRPHY4_GPHY_CORE_EXP05_FLASH_RATE_MASK                     0x003f
#define BRPHY4_GPHY_CORE_EXP05_FLASH_RATE_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP05_FLASH_RATE_BITS                     6
#define BRPHY4_GPHY_CORE_EXP05_FLASH_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP06
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP06 :: reserved0 [15:08] */
#define BRPHY4_GPHY_CORE_EXP06_RESERVED0_MASK                      0xff00
#define BRPHY4_GPHY_CORE_EXP06_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP06_RESERVED0_BITS                      8
#define BRPHY4_GPHY_CORE_EXP06_RESERVED0_SHIFT                     8

/* BRPHY4_GPHY_CORE :: EXP06 :: SPARE_REG [07:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP06_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP06,0xc0,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP06_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP06,0xc0,6)
#define BRPHY4_GPHY_CORE_EXP06_SPARE_REG_MASK                      0x00c0
#define BRPHY4_GPHY_CORE_EXP06_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP06_SPARE_REG_BITS                      2
#define BRPHY4_GPHY_CORE_EXP06_SPARE_REG_SHIFT                     6

/* BRPHY4_GPHY_CORE :: EXP06 :: BLINK_UPDATE_NOW [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP06,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXP06_BLINK_UPDATE_NOW(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP06,0x20,5)
#define BRPHY4_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_MASK               0x0020
#define BRPHY4_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_BITS               1
#define BRPHY4_GPHY_CORE_EXP06_BLINK_UPDATE_NOW_SHIFT              5

/* BRPHY4_GPHY_CORE :: EXP06 :: BLINK_RATE [04:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP06_BLINK_RATE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP06,0x1f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP06_BLINK_RATE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP06,0x1f,0)
#define BRPHY4_GPHY_CORE_EXP06_BLINK_RATE_MASK                     0x001f
#define BRPHY4_GPHY_CORE_EXP06_BLINK_RATE_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP06_BLINK_RATE_BITS                     5
#define BRPHY4_GPHY_CORE_EXP06_BLINK_RATE_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP07
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP07 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_EXP07_RESERVED0_MASK                      0x8000
#define BRPHY4_GPHY_CORE_EXP07_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP07_RESERVED0_BITS                      1
#define BRPHY4_GPHY_CORE_EXP07_RESERVED0_SHIFT                     15

/* BRPHY4_GPHY_CORE :: EXP07 :: EXT_MAX_LP_WIDTH [14:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP07,0x7f00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP07,0x7f00,8)
#define BRPHY4_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_MASK               0x7f00
#define BRPHY4_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_BITS               7
#define BRPHY4_GPHY_CORE_EXP07_EXT_MAX_LP_WIDTH_SHIFT              8

/* BRPHY4_GPHY_CORE :: EXP07 :: SPARE_REG [07:03] */
#define Wr_BRPHY4_GPHY_CORE_EXP07_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP07,0xf8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXP07_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP07,0xf8,3)
#define BRPHY4_GPHY_CORE_EXP07_SPARE_REG_MASK                      0x00f8
#define BRPHY4_GPHY_CORE_EXP07_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP07_SPARE_REG_BITS                      5
#define BRPHY4_GPHY_CORE_EXP07_SPARE_REG_SHIFT                     3

/* BRPHY4_GPHY_CORE :: EXP07 :: COPPER_FX_SIGSTAT_SEL [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP07,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP07,0x4,2)
#define BRPHY4_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_MASK          0x0004
#define BRPHY4_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_ALIGN         0
#define BRPHY4_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_BITS          1
#define BRPHY4_GPHY_CORE_EXP07_COPPER_FX_SIGSTAT_SEL_SHIFT         2

/* BRPHY4_GPHY_CORE :: EXP07 :: FAULTING [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP07_FAULTING(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP07,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP07_FAULTING(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP07,0x2,1)
#define BRPHY4_GPHY_CORE_EXP07_FAULTING_MASK                       0x0002
#define BRPHY4_GPHY_CORE_EXP07_FAULTING_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP07_FAULTING_BITS                       1
#define BRPHY4_GPHY_CORE_EXP07_FAULTING_SHIFT                      1

/* BRPHY4_GPHY_CORE :: EXP07 :: FEF_EN [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP07_FEF_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP07,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP07_FEF_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP07,0x1,0)
#define BRPHY4_GPHY_CORE_EXP07_FEF_EN_MASK                         0x0001
#define BRPHY4_GPHY_CORE_EXP07_FEF_EN_ALIGN                        0
#define BRPHY4_GPHY_CORE_EXP07_FEF_EN_BITS                         1
#define BRPHY4_GPHY_CORE_EXP07_FEF_EN_SHIFT                        0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP08
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP08 :: SILENT_LPBK [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_SILENT_LPBK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_SILENT_LPBK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x8000,15)
#define BRPHY4_GPHY_CORE_EXP08_SILENT_LPBK_MASK                    0x8000
#define BRPHY4_GPHY_CORE_EXP08_SILENT_LPBK_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP08_SILENT_LPBK_BITS                    1
#define BRPHY4_GPHY_CORE_EXP08_SILENT_LPBK_SHIFT                   15

/* BRPHY4_GPHY_CORE :: EXP08 :: RX_POLARITY_OV [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x4000,14)
#define BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_MASK                 0x4000
#define BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_BITS                 1
#define BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_SHIFT                14

/* BRPHY4_GPHY_CORE :: EXP08 :: RX_POLARITY_OV_VAL [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x2000,13)
#define BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_MASK             0x2000
#define BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_ALIGN            0
#define BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_BITS             1
#define BRPHY4_GPHY_CORE_EXP08_RX_POLARITY_OV_VAL_SHIFT            13

/* BRPHY4_GPHY_CORE :: EXP08 :: BT_BYTE_ALIGN_PREAM [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_MASK            0x1000
#define BRPHY4_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_ALIGN           0
#define BRPHY4_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_BITS            1
#define BRPHY4_GPHY_CORE_EXP08_BT_BYTE_ALIGN_PREAM_SHIFT           12

/* BRPHY4_GPHY_CORE :: EXP08 :: BT_PREAM_SUPPRESS [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x800,11)
#define BRPHY4_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_MASK              0x0800
#define BRPHY4_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_BITS              1
#define BRPHY4_GPHY_CORE_EXP08_BT_PREAM_SUPPRESS_SHIFT             11

/* BRPHY4_GPHY_CORE :: EXP08 :: EXT_MAX_LP_WIDTH_EN [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x400,10)
#define BRPHY4_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_MASK            0x0400
#define BRPHY4_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_BITS            1
#define BRPHY4_GPHY_CORE_EXP08_EXT_MAX_LP_WIDTH_EN_SHIFT           10

/* BRPHY4_GPHY_CORE :: EXP08 :: AUTO_EARLY_DAC_WAKE [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x200,9)
#define BRPHY4_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_MASK            0x0200
#define BRPHY4_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_ALIGN           0
#define BRPHY4_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_BITS            1
#define BRPHY4_GPHY_CORE_EXP08_AUTO_EARLY_DAC_WAKE_SHIFT           9

/* BRPHY4_GPHY_CORE :: EXP08 :: FORCE_EARLY_DAC_WAKE [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x100,8)
#define BRPHY4_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_MASK           0x0100
#define BRPHY4_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_ALIGN          0
#define BRPHY4_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_BITS           1
#define BRPHY4_GPHY_CORE_EXP08_FORCE_EARLY_DAC_WAKE_SHIFT          8

/* BRPHY4_GPHY_CORE :: EXP08 :: SUPPRESS_CRS_HDX [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x80,7)
#define BRPHY4_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_MASK               0x0080
#define BRPHY4_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_BITS               1
#define BRPHY4_GPHY_CORE_EXP08_SUPPRESS_CRS_HDX_SHIFT              7

/* BRPHY4_GPHY_CORE :: EXP08 :: REJECT_MORE_15MHZ [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_REJECT_MORE_15MHZ(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x40,6)
#define BRPHY4_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_MASK              0x0040
#define BRPHY4_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_BITS              1
#define BRPHY4_GPHY_CORE_EXP08_REJECT_MORE_15MHZ_SHIFT             6

/* BRPHY4_GPHY_CORE :: EXP08 :: POLARITY_INVERT [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_POLARITY_INVERT(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_POLARITY_INVERT(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x20,5)
#define BRPHY4_GPHY_CORE_EXP08_POLARITY_INVERT_MASK                0x0020
#define BRPHY4_GPHY_CORE_EXP08_POLARITY_INVERT_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP08_POLARITY_INVERT_BITS                1
#define BRPHY4_GPHY_CORE_EXP08_POLARITY_INVERT_SHIFT               5

/* BRPHY4_GPHY_CORE :: EXP08 :: BLOCK_NARROW_LP [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_BLOCK_NARROW_LP(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x10,4)
#define BRPHY4_GPHY_CORE_EXP08_BLOCK_NARROW_LP_MASK                0x0010
#define BRPHY4_GPHY_CORE_EXP08_BLOCK_NARROW_LP_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP08_BLOCK_NARROW_LP_BITS                1
#define BRPHY4_GPHY_CORE_EXP08_BLOCK_NARROW_LP_SHIFT               4

/* BRPHY4_GPHY_CORE :: EXP08 :: USE_OLD_LPDET [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_USE_OLD_LPDET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_USE_OLD_LPDET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x8,3)
#define BRPHY4_GPHY_CORE_EXP08_USE_OLD_LPDET_MASK                  0x0008
#define BRPHY4_GPHY_CORE_EXP08_USE_OLD_LPDET_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP08_USE_OLD_LPDET_BITS                  1
#define BRPHY4_GPHY_CORE_EXP08_USE_OLD_LPDET_SHIFT                 3

/* BRPHY4_GPHY_CORE :: EXP08 :: EDGESTATE_REFINE [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_EDGESTATE_REFINE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x4,2)
#define BRPHY4_GPHY_CORE_EXP08_EDGESTATE_REFINE_MASK               0x0004
#define BRPHY4_GPHY_CORE_EXP08_EDGESTATE_REFINE_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP08_EDGESTATE_REFINE_BITS               1
#define BRPHY4_GPHY_CORE_EXP08_EDGESTATE_REFINE_SHIFT              2

/* BRPHY4_GPHY_CORE :: EXP08 :: REJECT_15MHZ [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_REJECT_15MHZ(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_REJECT_15MHZ(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x2,1)
#define BRPHY4_GPHY_CORE_EXP08_REJECT_15MHZ_MASK                   0x0002
#define BRPHY4_GPHY_CORE_EXP08_REJECT_15MHZ_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP08_REJECT_15MHZ_BITS                   1
#define BRPHY4_GPHY_CORE_EXP08_REJECT_15MHZ_SHIFT                  1

/* BRPHY4_GPHY_CORE :: EXP08 :: REJECT_2MHZ [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP08_REJECT_2MHZ(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP08,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP08_REJECT_2MHZ(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP08,0x1,0)
#define BRPHY4_GPHY_CORE_EXP08_REJECT_2MHZ_MASK                    0x0001
#define BRPHY4_GPHY_CORE_EXP08_REJECT_2MHZ_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP08_REJECT_2MHZ_BITS                    1
#define BRPHY4_GPHY_CORE_EXP08_REJECT_2MHZ_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP09
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP09 :: GIGABIT_POL_INV [15:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP09,0xf000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP09_GIGABIT_POL_INV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP09,0xf000,12)
#define BRPHY4_GPHY_CORE_EXP09_GIGABIT_POL_INV_MASK                0xf000
#define BRPHY4_GPHY_CORE_EXP09_GIGABIT_POL_INV_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP09_GIGABIT_POL_INV_BITS                4
#define BRPHY4_GPHY_CORE_EXP09_GIGABIT_POL_INV_SHIFT               12

/* BRPHY4_GPHY_CORE :: EXP09 :: SPARE_REG [11:09] */
#define Wr_BRPHY4_GPHY_CORE_EXP09_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP09,0xe00,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXP09_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP09,0xe00,9)
#define BRPHY4_GPHY_CORE_EXP09_SPARE_REG_MASK                      0x0e00
#define BRPHY4_GPHY_CORE_EXP09_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP09_SPARE_REG_BITS                      3
#define BRPHY4_GPHY_CORE_EXP09_SPARE_REG_SHIFT                     9

/* BRPHY4_GPHY_CORE :: EXP09 :: ALLOW_SWAP [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP09_ALLOW_SWAP(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP09,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP09_ALLOW_SWAP(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP09,0x100,8)
#define BRPHY4_GPHY_CORE_EXP09_ALLOW_SWAP_MASK                     0x0100
#define BRPHY4_GPHY_CORE_EXP09_ALLOW_SWAP_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP09_ALLOW_SWAP_BITS                     1
#define BRPHY4_GPHY_CORE_EXP09_ALLOW_SWAP_SHIFT                    8

/* BRPHY4_GPHY_CORE :: EXP09 :: CH3_SEL [07:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP09_CH3_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP09,0xc0,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP09_CH3_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP09,0xc0,6)
#define BRPHY4_GPHY_CORE_EXP09_CH3_SEL_MASK                        0x00c0
#define BRPHY4_GPHY_CORE_EXP09_CH3_SEL_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP09_CH3_SEL_BITS                        2
#define BRPHY4_GPHY_CORE_EXP09_CH3_SEL_SHIFT                       6

/* BRPHY4_GPHY_CORE :: EXP09 :: CH2_SEL [05:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP09_CH2_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP09,0x30,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP09_CH2_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP09,0x30,4)
#define BRPHY4_GPHY_CORE_EXP09_CH2_SEL_MASK                        0x0030
#define BRPHY4_GPHY_CORE_EXP09_CH2_SEL_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP09_CH2_SEL_BITS                        2
#define BRPHY4_GPHY_CORE_EXP09_CH2_SEL_SHIFT                       4

/* BRPHY4_GPHY_CORE :: EXP09 :: CH1_SEL [03:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP09_CH1_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP09,0xc,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP09_CH1_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP09,0xc,2)
#define BRPHY4_GPHY_CORE_EXP09_CH1_SEL_MASK                        0x000c
#define BRPHY4_GPHY_CORE_EXP09_CH1_SEL_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP09_CH1_SEL_BITS                        2
#define BRPHY4_GPHY_CORE_EXP09_CH1_SEL_SHIFT                       2

/* BRPHY4_GPHY_CORE :: EXP09 :: CH0_SEL [01:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP09_CH0_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP09,0x3,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP09_CH0_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP09,0x3,0)
#define BRPHY4_GPHY_CORE_EXP09_CH0_SEL_MASK                        0x0003
#define BRPHY4_GPHY_CORE_EXP09_CH0_SEL_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP09_CH0_SEL_BITS                        2
#define BRPHY4_GPHY_CORE_EXP09_CH0_SEL_SHIFT                       0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP0A
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP0A :: reserved0 [15:13] */
#define BRPHY4_GPHY_CORE_EXP0A_RESERVED0_MASK                      0xe000
#define BRPHY4_GPHY_CORE_EXP0A_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP0A_RESERVED0_BITS                      3
#define BRPHY4_GPHY_CORE_EXP0A_RESERVED0_SHIFT                     13

/* BRPHY4_GPHY_CORE :: EXP0A :: SYNC_IN_EN [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP0A_SYNC_IN_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP0A_SYNC_IN_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP0A_SYNC_IN_EN_MASK                     0x1000
#define BRPHY4_GPHY_CORE_EXP0A_SYNC_IN_EN_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP0A_SYNC_IN_EN_BITS                     1
#define BRPHY4_GPHY_CORE_EXP0A_SYNC_IN_EN_SHIFT                    12

/* BRPHY4_GPHY_CORE :: EXP0A :: CHANNEL_KILL [11:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP0A_CHANNEL_KILL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP0A,0xf00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP0A_CHANNEL_KILL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP0A,0xf00,8)
#define BRPHY4_GPHY_CORE_EXP0A_CHANNEL_KILL_MASK                   0x0f00
#define BRPHY4_GPHY_CORE_EXP0A_CHANNEL_KILL_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP0A_CHANNEL_KILL_BITS                   4
#define BRPHY4_GPHY_CORE_EXP0A_CHANNEL_KILL_SHIFT                  8

/* BRPHY4_GPHY_CORE :: EXP0A :: SYNC_KILL [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXP0A_SYNC_KILL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXP0A_SYNC_KILL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x80,7)
#define BRPHY4_GPHY_CORE_EXP0A_SYNC_KILL_MASK                      0x0080
#define BRPHY4_GPHY_CORE_EXP0A_SYNC_KILL_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP0A_SYNC_KILL_BITS                      1
#define BRPHY4_GPHY_CORE_EXP0A_SYNC_KILL_SHIFT                     7

/* BRPHY4_GPHY_CORE :: EXP0A :: BYPASS_ENE [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP0A_BYPASS_ENE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP0A_BYPASS_ENE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x40,6)
#define BRPHY4_GPHY_CORE_EXP0A_BYPASS_ENE_MASK                     0x0040
#define BRPHY4_GPHY_CORE_EXP0A_BYPASS_ENE_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP0A_BYPASS_ENE_BITS                     1
#define BRPHY4_GPHY_CORE_EXP0A_BYPASS_ENE_SHIFT                    6

/* BRPHY4_GPHY_CORE :: EXP0A :: PAT_DURATION [05:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP0A_PAT_DURATION(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x30,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP0A_PAT_DURATION(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x30,4)
#define BRPHY4_GPHY_CORE_EXP0A_PAT_DURATION_MASK                   0x0030
#define BRPHY4_GPHY_CORE_EXP0A_PAT_DURATION_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP0A_PAT_DURATION_BITS                   2
#define BRPHY4_GPHY_CORE_EXP0A_PAT_DURATION_SHIFT                  4

/* BRPHY4_GPHY_CORE :: EXP0A :: PAT_SEL [03:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP0A_PAT_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP0A,0xe,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP0A_PAT_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP0A,0xe,1)
#define BRPHY4_GPHY_CORE_EXP0A_PAT_SEL_MASK                        0x000e
#define BRPHY4_GPHY_CORE_EXP0A_PAT_SEL_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP0A_PAT_SEL_BITS                        3
#define BRPHY4_GPHY_CORE_EXP0A_PAT_SEL_SHIFT                       1

/* BRPHY4_GPHY_CORE :: EXP0A :: TEMPLATE_EN [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP0A_TEMPLATE_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP0A_TEMPLATE_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP0A,0x1,0)
#define BRPHY4_GPHY_CORE_EXP0A_TEMPLATE_EN_MASK                    0x0001
#define BRPHY4_GPHY_CORE_EXP0A_TEMPLATE_EN_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP0A_TEMPLATE_EN_BITS                    1
#define BRPHY4_GPHY_CORE_EXP0A_TEMPLATE_EN_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP0B
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP0B :: EXT_STATUS [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP0B_EXT_STATUS(x) WriteReg16(BRPHY4_GPHY_CORE_EXP0B,x)
#define Rd_BRPHY4_GPHY_CORE_EXP0B_EXT_STATUS(x) ReadReg16(BRPHY4_GPHY_CORE_EXP0B)
#define BRPHY4_GPHY_CORE_EXP0B_EXT_STATUS_MASK                     0xffff
#define BRPHY4_GPHY_CORE_EXP0B_EXT_STATUS_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP0B_EXT_STATUS_BITS                     16
#define BRPHY4_GPHY_CORE_EXP0B_EXT_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP0C
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP0C :: SPARE_REG [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP0C_SPARE_REG(x) WriteReg16(BRPHY4_GPHY_CORE_EXP0C,x)
#define Rd_BRPHY4_GPHY_CORE_EXP0C_SPARE_REG(x) ReadReg16(BRPHY4_GPHY_CORE_EXP0C)
#define BRPHY4_GPHY_CORE_EXP0C_SPARE_REG_MASK                      0xffff
#define BRPHY4_GPHY_CORE_EXP0C_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP0C_SPARE_REG_BITS                      16
#define BRPHY4_GPHY_CORE_EXP0C_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP30
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP30 :: reserved0 [15:05] */
#define BRPHY4_GPHY_CORE_EXP30_RESERVED0_MASK                      0xffe0
#define BRPHY4_GPHY_CORE_EXP30_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP30_RESERVED0_BITS                      11
#define BRPHY4_GPHY_CORE_EXP30_RESERVED0_SHIFT                     5

/* BRPHY4_GPHY_CORE :: EXP30 :: DEADMAN_RESET [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP30_DEADMAN_RESET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP30,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP30_DEADMAN_RESET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP30,0x10,4)
#define BRPHY4_GPHY_CORE_EXP30_DEADMAN_RESET_MASK                  0x0010
#define BRPHY4_GPHY_CORE_EXP30_DEADMAN_RESET_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP30_DEADMAN_RESET_BITS                  1
#define BRPHY4_GPHY_CORE_EXP30_DEADMAN_RESET_SHIFT                 4

/* BRPHY4_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_128_TO_255 [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP30,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP30,0x8,3)
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_MASK       0x0008
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_ALIGN      0
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_BITS       1
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_128_TO_255_SHIFT      3

/* BRPHY4_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_64_TO_127 [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP30,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP30,0x4,2)
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_MASK        0x0004
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_ALIGN       0
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_BITS        1
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_64_TO_127_SHIFT       2

/* BRPHY4_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_32_TO_63 [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP30,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP30,0x2,1)
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_MASK         0x0002
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_ALIGN        0
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_BITS         1
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_32_TO_63_SHIFT        1

/* BRPHY4_GPHY_CORE :: EXP30 :: LATE_COL_CNTR_0_TO_31 [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP30,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP30,0x1,0)
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_MASK          0x0001
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_ALIGN         0
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_BITS          1
#define BRPHY4_GPHY_CORE_EXP30_LATE_COL_CNTR_0_TO_31_SHIFT         0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP31
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP31 :: reserved0 [15:08] */
#define BRPHY4_GPHY_CORE_EXP31_RESERVED0_MASK                      0xff00
#define BRPHY4_GPHY_CORE_EXP31_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP31_RESERVED0_BITS                      8
#define BRPHY4_GPHY_CORE_EXP31_RESERVED0_SHIFT                     8

/* BRPHY4_GPHY_CORE :: EXP31 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP31_LATE_COL_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP31,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP31_LATE_COL_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP31,0xff,0)
#define BRPHY4_GPHY_CORE_EXP31_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY4_GPHY_CORE_EXP31_LATE_COL_CNTR_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP31_LATE_COL_CNTR_BITS                  8
#define BRPHY4_GPHY_CORE_EXP31_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP32
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP32 :: reserved0 [15:08] */
#define BRPHY4_GPHY_CORE_EXP32_RESERVED0_MASK                      0xff00
#define BRPHY4_GPHY_CORE_EXP32_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP32_RESERVED0_BITS                      8
#define BRPHY4_GPHY_CORE_EXP32_RESERVED0_SHIFT                     8

/* BRPHY4_GPHY_CORE :: EXP32 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP32_LATE_COL_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP32,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP32_LATE_COL_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP32,0xff,0)
#define BRPHY4_GPHY_CORE_EXP32_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY4_GPHY_CORE_EXP32_LATE_COL_CNTR_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP32_LATE_COL_CNTR_BITS                  8
#define BRPHY4_GPHY_CORE_EXP32_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP33
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP33 :: reserved0 [15:08] */
#define BRPHY4_GPHY_CORE_EXP33_RESERVED0_MASK                      0xff00
#define BRPHY4_GPHY_CORE_EXP33_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP33_RESERVED0_BITS                      8
#define BRPHY4_GPHY_CORE_EXP33_RESERVED0_SHIFT                     8

/* BRPHY4_GPHY_CORE :: EXP33 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP33_LATE_COL_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP33,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP33_LATE_COL_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP33,0xff,0)
#define BRPHY4_GPHY_CORE_EXP33_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY4_GPHY_CORE_EXP33_LATE_COL_CNTR_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP33_LATE_COL_CNTR_BITS                  8
#define BRPHY4_GPHY_CORE_EXP33_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP34
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP34 :: reserved0 [15:08] */
#define BRPHY4_GPHY_CORE_EXP34_RESERVED0_MASK                      0xff00
#define BRPHY4_GPHY_CORE_EXP34_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP34_RESERVED0_BITS                      8
#define BRPHY4_GPHY_CORE_EXP34_RESERVED0_SHIFT                     8

/* BRPHY4_GPHY_CORE :: EXP34 :: LATE_COL_CNTR [07:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP34_LATE_COL_CNTR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP34,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP34_LATE_COL_CNTR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP34,0xff,0)
#define BRPHY4_GPHY_CORE_EXP34_LATE_COL_CNTR_MASK                  0x00ff
#define BRPHY4_GPHY_CORE_EXP34_LATE_COL_CNTR_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP34_LATE_COL_CNTR_BITS                  8
#define BRPHY4_GPHY_CORE_EXP34_LATE_COL_CNTR_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP35
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP35 :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_EXP35_RESERVED0_MASK                      0xf000
#define BRPHY4_GPHY_CORE_EXP35_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP35_RESERVED0_BITS                      4
#define BRPHY4_GPHY_CORE_EXP35_RESERVED0_SHIFT                     12

/* BRPHY4_GPHY_CORE :: EXP35 :: MII_INTERFACE_MODES [11:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP35,0xf00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP35_MII_INTERFACE_MODES(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP35,0xf00,8)
#define BRPHY4_GPHY_CORE_EXP35_MII_INTERFACE_MODES_MASK            0x0f00
#define BRPHY4_GPHY_CORE_EXP35_MII_INTERFACE_MODES_ALIGN           0
#define BRPHY4_GPHY_CORE_EXP35_MII_INTERFACE_MODES_BITS            4
#define BRPHY4_GPHY_CORE_EXP35_MII_INTERFACE_MODES_SHIFT           8

/* BRPHY4_GPHY_CORE :: EXP35 :: LATE_COL_CNTR_THD [07:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP35,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP35_LATE_COL_CNTR_THD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP35,0xff,0)
#define BRPHY4_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_MASK              0x00ff
#define BRPHY4_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_BITS              8
#define BRPHY4_GPHY_CORE_EXP35_LATE_COL_CNTR_THD_SHIFT             0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP36
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP36 :: PPM_DET_PWRDN [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP36,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXP36_PPM_DET_PWRDN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP36,0x8000,15)
#define BRPHY4_GPHY_CORE_EXP36_PPM_DET_PWRDN_MASK                  0x8000
#define BRPHY4_GPHY_CORE_EXP36_PPM_DET_PWRDN_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP36_PPM_DET_PWRDN_BITS                  1
#define BRPHY4_GPHY_CORE_EXP36_PPM_DET_PWRDN_SHIFT                 15

/* BRPHY4_GPHY_CORE :: EXP36 :: PPM_DET_TEST [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXP36_PPM_DET_TEST(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP36,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXP36_PPM_DET_TEST(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP36,0x4000,14)
#define BRPHY4_GPHY_CORE_EXP36_PPM_DET_TEST_MASK                   0x4000
#define BRPHY4_GPHY_CORE_EXP36_PPM_DET_TEST_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP36_PPM_DET_TEST_BITS                   1
#define BRPHY4_GPHY_CORE_EXP36_PPM_DET_TEST_SHIFT                  14

/* BRPHY4_GPHY_CORE :: EXP36 :: reserved0 [13:10] */
#define BRPHY4_GPHY_CORE_EXP36_RESERVED0_MASK                      0x3c00
#define BRPHY4_GPHY_CORE_EXP36_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP36_RESERVED0_BITS                      4
#define BRPHY4_GPHY_CORE_EXP36_RESERVED0_SHIFT                     10

/* BRPHY4_GPHY_CORE :: EXP36 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP36_PPM_OFFSET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP36,0x3ff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP36_PPM_OFFSET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP36,0x3ff,0)
#define BRPHY4_GPHY_CORE_EXP36_PPM_OFFSET_MASK                     0x03ff
#define BRPHY4_GPHY_CORE_EXP36_PPM_OFFSET_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP36_PPM_OFFSET_BITS                     10
#define BRPHY4_GPHY_CORE_EXP36_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP37
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP37 :: reserved0 [15:10] */
#define BRPHY4_GPHY_CORE_EXP37_RESERVED0_MASK                      0xfc00
#define BRPHY4_GPHY_CORE_EXP37_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP37_RESERVED0_BITS                      6
#define BRPHY4_GPHY_CORE_EXP37_RESERVED0_SHIFT                     10

/* BRPHY4_GPHY_CORE :: EXP37 :: PPM_OFFSET [09:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP37_PPM_OFFSET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP37,0x3ff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP37_PPM_OFFSET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP37,0x3ff,0)
#define BRPHY4_GPHY_CORE_EXP37_PPM_OFFSET_MASK                     0x03ff
#define BRPHY4_GPHY_CORE_EXP37_PPM_OFFSET_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP37_PPM_OFFSET_BITS                     10
#define BRPHY4_GPHY_CORE_EXP37_PPM_OFFSET_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP38
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP38 :: IP_PHONE_DET_CHANGE [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP38,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP38,0x8000,15)
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_MASK            0x8000
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_ALIGN           0
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_BITS            1
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_CHANGE_SHIFT           15

/* BRPHY4_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH_CHANGE [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP38,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP38,0x4000,14)
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_MASK       0x4000
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_ALIGN      0
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_BITS       1
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_CHANGE_SHIFT      14

/* BRPHY4_GPHY_CORE :: EXP38 :: IP_PHONE_FLP_BURST_TX [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP38,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP38,0x2000,13)
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_MASK          0x2000
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_ALIGN         0
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_BITS          1
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_FLP_BURST_TX_SHIFT         13

/* BRPHY4_GPHY_CORE :: EXP38 :: IP_PHONE_MISMATCH [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP38,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP38,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_MASK              0x1000
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_BITS              1
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_MISMATCH_SHIFT             12

/* BRPHY4_GPHY_CORE :: EXP38 :: IP_PHONE_DET [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP38,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP38,0x800,11)
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_MASK                   0x0800
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_BITS                   1
#define BRPHY4_GPHY_CORE_EXP38_IP_PHONE_DET_SHIFT                  11

/* BRPHY4_GPHY_CORE :: EXP38 :: NO_RESPSONSE [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXP38_NO_RESPSONSE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP38,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXP38_NO_RESPSONSE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP38,0x400,10)
#define BRPHY4_GPHY_CORE_EXP38_NO_RESPSONSE_MASK                   0x0400
#define BRPHY4_GPHY_CORE_EXP38_NO_RESPSONSE_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP38_NO_RESPSONSE_BITS                   1
#define BRPHY4_GPHY_CORE_EXP38_NO_RESPSONSE_SHIFT                  10

/* BRPHY4_GPHY_CORE :: EXP38 :: TOTAL_RT_DLY [09:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP38,0x3ff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP38_TOTAL_RT_DLY(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP38,0x3ff,0)
#define BRPHY4_GPHY_CORE_EXP38_TOTAL_RT_DLY_MASK                   0x03ff
#define BRPHY4_GPHY_CORE_EXP38_TOTAL_RT_DLY_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP38_TOTAL_RT_DLY_BITS                   10
#define BRPHY4_GPHY_CORE_EXP38_TOTAL_RT_DLY_SHIFT                  0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP42
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP42 :: SERDES_LINK [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_SERDES_LINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_SERDES_LINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x8000,15)
#define BRPHY4_GPHY_CORE_EXP42_SERDES_LINK_MASK                    0x8000
#define BRPHY4_GPHY_CORE_EXP42_SERDES_LINK_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP42_SERDES_LINK_BITS                    1
#define BRPHY4_GPHY_CORE_EXP42_SERDES_LINK_SHIFT                   15

/* BRPHY4_GPHY_CORE :: EXP42 :: SERDES_SPEED [14:13] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_SERDES_SPEED(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x6000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_SERDES_SPEED(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x6000,13)
#define BRPHY4_GPHY_CORE_EXP42_SERDES_SPEED_MASK                   0x6000
#define BRPHY4_GPHY_CORE_EXP42_SERDES_SPEED_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP42_SERDES_SPEED_BITS                   2
#define BRPHY4_GPHY_CORE_EXP42_SERDES_SPEED_SHIFT                  13

/* BRPHY4_GPHY_CORE :: EXP42 :: SERDES_DUPLEX [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_SERDES_DUPLEX(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_SERDES_DUPLEX(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP42_SERDES_DUPLEX_MASK                  0x1000
#define BRPHY4_GPHY_CORE_EXP42_SERDES_DUPLEX_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP42_SERDES_DUPLEX_BITS                  1
#define BRPHY4_GPHY_CORE_EXP42_SERDES_DUPLEX_SHIFT                 12

/* BRPHY4_GPHY_CORE :: EXP42 :: COPPER_LINK [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_COPPER_LINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_COPPER_LINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x800,11)
#define BRPHY4_GPHY_CORE_EXP42_COPPER_LINK_MASK                    0x0800
#define BRPHY4_GPHY_CORE_EXP42_COPPER_LINK_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP42_COPPER_LINK_BITS                    1
#define BRPHY4_GPHY_CORE_EXP42_COPPER_LINK_SHIFT                   11

/* BRPHY4_GPHY_CORE :: EXP42 :: COPPER_SPEED [10:09] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_COPPER_SPEED(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x600,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_COPPER_SPEED(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x600,9)
#define BRPHY4_GPHY_CORE_EXP42_COPPER_SPEED_MASK                   0x0600
#define BRPHY4_GPHY_CORE_EXP42_COPPER_SPEED_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP42_COPPER_SPEED_BITS                   2
#define BRPHY4_GPHY_CORE_EXP42_COPPER_SPEED_SHIFT                  9

/* BRPHY4_GPHY_CORE :: EXP42 :: COPPER_DUPLEX [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_COPPER_DUPLEX(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_COPPER_DUPLEX(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x100,8)
#define BRPHY4_GPHY_CORE_EXP42_COPPER_DUPLEX_MASK                  0x0100
#define BRPHY4_GPHY_CORE_EXP42_COPPER_DUPLEX_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP42_COPPER_DUPLEX_BITS                  1
#define BRPHY4_GPHY_CORE_EXP42_COPPER_DUPLEX_SHIFT                 8

/* BRPHY4_GPHY_CORE :: EXP42 :: COPPER_ENERGY_DETECT [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x80,7)
#define BRPHY4_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_MASK           0x0080
#define BRPHY4_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_ALIGN          0
#define BRPHY4_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_BITS           1
#define BRPHY4_GPHY_CORE_EXP42_COPPER_ENERGY_DETECT_SHIFT          7

/* BRPHY4_GPHY_CORE :: EXP42 :: FIBER_SIGNAL_DETECT [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x40,6)
#define BRPHY4_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_MASK            0x0040
#define BRPHY4_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_ALIGN           0
#define BRPHY4_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_BITS            1
#define BRPHY4_GPHY_CORE_EXP42_FIBER_SIGNAL_DETECT_SHIFT           6

/* BRPHY4_GPHY_CORE :: EXP42 :: SYNC_STATUS [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_SYNC_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_SYNC_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x20,5)
#define BRPHY4_GPHY_CORE_EXP42_SYNC_STATUS_MASK                    0x0020
#define BRPHY4_GPHY_CORE_EXP42_SYNC_STATUS_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP42_SYNC_STATUS_BITS                    1
#define BRPHY4_GPHY_CORE_EXP42_SYNC_STATUS_SHIFT                   5

/* BRPHY4_GPHY_CORE :: EXP42 :: OPERATING_MODE_STATUS [04:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP42,0x1f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP42_OPERATING_MODE_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP42,0x1f,0)
#define BRPHY4_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_MASK          0x001f
#define BRPHY4_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_ALIGN         0
#define BRPHY4_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_BITS          5
#define BRPHY4_GPHY_CORE_EXP42_OPERATING_MODE_STATUS_SHIFT         0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP5F
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP5F :: PLL_TCLK_OFFSET [15:10] */
#define Wr_BRPHY4_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP5F,0xfc00,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP5F,0xfc00,10)
#define BRPHY4_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_MASK                0xfc00
#define BRPHY4_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_BITS                6
#define BRPHY4_GPHY_CORE_EXP5F_PLL_TCLK_OFFSET_SHIFT               10

/* BRPHY4_GPHY_CORE :: EXP5F :: PLL_RCLK_OFFSET [09:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP5F,0x3f0,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP5F,0x3f0,4)
#define BRPHY4_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_MASK                0x03f0
#define BRPHY4_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_BITS                6
#define BRPHY4_GPHY_CORE_EXP5F_PLL_RCLK_OFFSET_SHIFT               4

/* BRPHY4_GPHY_CORE :: EXP5F :: PLLTEST_CNT [03:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP5F_PLLTEST_CNT(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP5F,0xc,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP5F_PLLTEST_CNT(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP5F,0xc,2)
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_CNT_MASK                    0x000c
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_CNT_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_CNT_BITS                    2
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_CNT_SHIFT                   2

/* BRPHY4_GPHY_CORE :: EXP5F :: PLLTEST [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP5F_PLLTEST(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP5F,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP5F_PLLTEST(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP5F,0x2,1)
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_MASK                        0x0002
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_BITS                        1
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_SHIFT                       1

/* BRPHY4_GPHY_CORE :: EXP5F :: PLLTEST_EN [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP5F_PLLTEST_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP5F,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP5F_PLLTEST_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP5F,0x1,0)
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_EN_MASK                     0x0001
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_EN_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_EN_BITS                     1
#define BRPHY4_GPHY_CORE_EXP5F_PLLTEST_EN_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP70
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP70 :: reserved0 [15:01] */
#define BRPHY4_GPHY_CORE_EXP70_RESERVED0_MASK                      0xfffe
#define BRPHY4_GPHY_CORE_EXP70_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP70_RESERVED0_BITS                      15
#define BRPHY4_GPHY_CORE_EXP70_RESERVED0_SHIFT                     1

/* BRPHY4_GPHY_CORE :: EXP70 :: SOFT_RESET [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP70_SOFT_RESET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP70,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP70_SOFT_RESET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP70,0x1,0)
#define BRPHY4_GPHY_CORE_EXP70_SOFT_RESET_MASK                     0x0001
#define BRPHY4_GPHY_CORE_EXP70_SOFT_RESET_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP70_SOFT_RESET_BITS                     1
#define BRPHY4_GPHY_CORE_EXP70_SOFT_RESET_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP71
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP71 :: reserved0 [15:14] */
#define BRPHY4_GPHY_CORE_EXP71_RESERVED0_MASK                      0xc000
#define BRPHY4_GPHY_CORE_EXP71_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP71_RESERVED0_BITS                      2
#define BRPHY4_GPHY_CORE_EXP71_RESERVED0_SHIFT                     14

/* BRPHY4_GPHY_CORE :: EXP71 :: SERIAL_LED_EN [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP71,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP71,0x2000,13)
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_EN_MASK                  0x2000
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_EN_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_EN_BITS                  1
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_EN_SHIFT                 13

/* BRPHY4_GPHY_CORE :: EXP71 :: LOW_COST_LED_EN [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP71,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP71_LOW_COST_LED_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP71,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP71_LOW_COST_LED_EN_MASK                0x1000
#define BRPHY4_GPHY_CORE_EXP71_LOW_COST_LED_EN_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP71_LOW_COST_LED_EN_BITS                1
#define BRPHY4_GPHY_CORE_EXP71_LOW_COST_LED_EN_SHIFT               12

/* BRPHY4_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_6 [11:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP71,0xf00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_6(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP71,0xf00,8)
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_MASK               0x0f00
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_BITS               4
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_6_SHIFT              8

/* BRPHY4_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_5 [07:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP71,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_5(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP71,0xf0,4)
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_MASK               0x00f0
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_BITS               4
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_5_SHIFT              4

/* BRPHY4_GPHY_CORE :: EXP71 :: SERIAL_LED_SEL_4 [03:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP71,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_4(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP71,0xf,0)
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_MASK               0x000f
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_BITS               4
#define BRPHY4_GPHY_CORE_EXP71_SERIAL_LED_SEL_4_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP72
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP72 :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_EXP72_RESERVED0_MASK                      0xf000
#define BRPHY4_GPHY_CORE_EXP72_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP72_RESERVED0_BITS                      4
#define BRPHY4_GPHY_CORE_EXP72_RESERVED0_SHIFT                     12

/* BRPHY4_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_3 [11:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP72,0xf00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_3(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP72,0xf00,8)
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_MASK               0x0f00
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_BITS               4
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_3_SHIFT              8

/* BRPHY4_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_2 [07:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP72,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_2(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP72,0xf0,4)
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_MASK               0x00f0
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_BITS               4
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_2_SHIFT              4

/* BRPHY4_GPHY_CORE :: EXP72 :: SERIAL_LED_SEL_1 [03:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP72,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_1(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP72,0xf,0)
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_MASK               0x000f
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_BITS               4
#define BRPHY4_GPHY_CORE_EXP72_SERIAL_LED_SEL_1_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP73
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP73 :: reserved0 [15:08] */
#define BRPHY4_GPHY_CORE_EXP73_RESERVED0_MASK                      0xff00
#define BRPHY4_GPHY_CORE_EXP73_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP73_RESERVED0_BITS                      8
#define BRPHY4_GPHY_CORE_EXP73_RESERVED0_SHIFT                     8

/* BRPHY4_GPHY_CORE :: EXP73 :: LED_6_TO_1_COPPER [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP73,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_COPPER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP73,0x80,7)
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_MASK              0x0080
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_BITS              1
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_COPPER_SHIFT             7

/* BRPHY4_GPHY_CORE :: EXP73 :: LED_5_TO_1_COPPER [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP73,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_COPPER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP73,0x40,6)
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_MASK              0x0040
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_BITS              1
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_COPPER_SHIFT             6

/* BRPHY4_GPHY_CORE :: EXP73 :: LED_6_TO_0_COPPER [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP73,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_COPPER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP73,0x20,5)
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_MASK              0x0020
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_BITS              1
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_COPPER_SHIFT             5

/* BRPHY4_GPHY_CORE :: EXP73 :: LED_5_TO_0_COPPER [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP73,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_COPPER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP73,0x10,4)
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_MASK              0x0010
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_ALIGN             0
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_BITS              1
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_COPPER_SHIFT             4

/* BRPHY4_GPHY_CORE :: EXP73 :: LED_6_TO_1_FIBER [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP73,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_FIBER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP73,0x8,3)
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_MASK               0x0008
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_BITS               1
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_1_FIBER_SHIFT              3

/* BRPHY4_GPHY_CORE :: EXP73 :: LED_5_TO_1_FIBER [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP73,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_FIBER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP73,0x4,2)
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_MASK               0x0004
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_BITS               1
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_1_FIBER_SHIFT              2

/* BRPHY4_GPHY_CORE :: EXP73 :: LED_6_TO_0_FIBER [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP73,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_FIBER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP73,0x2,1)
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_MASK               0x0002
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_BITS               1
#define BRPHY4_GPHY_CORE_EXP73_LED_6_TO_0_FIBER_SHIFT              1

/* BRPHY4_GPHY_CORE :: EXP73 :: LED_5_TO_0_FIBER [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP73,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_FIBER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP73,0x1,0)
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_MASK               0x0001
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_BITS               1
#define BRPHY4_GPHY_CORE_EXP73_LED_5_TO_0_FIBER_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP74
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP74 :: LED4_CM_SW_VAL [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP74,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXP74_LED4_CM_SW_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP74,0x8000,15)
#define BRPHY4_GPHY_CORE_EXP74_LED4_CM_SW_VAL_MASK                 0x8000
#define BRPHY4_GPHY_CORE_EXP74_LED4_CM_SW_VAL_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP74_LED4_CM_SW_VAL_BITS                 1
#define BRPHY4_GPHY_CORE_EXP74_LED4_CM_SW_VAL_SHIFT                15

/* BRPHY4_GPHY_CORE :: EXP74 :: LED4_CM_CTRL [14:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP74_LED4_CM_CTRL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP74,0x7000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP74_LED4_CM_CTRL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP74,0x7000,12)
#define BRPHY4_GPHY_CORE_EXP74_LED4_CM_CTRL_MASK                   0x7000
#define BRPHY4_GPHY_CORE_EXP74_LED4_CM_CTRL_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP74_LED4_CM_CTRL_BITS                   3
#define BRPHY4_GPHY_CORE_EXP74_LED4_CM_CTRL_SHIFT                  12

/* BRPHY4_GPHY_CORE :: EXP74 :: LED3_CM_SW_VAL [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP74,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXP74_LED3_CM_SW_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP74,0x800,11)
#define BRPHY4_GPHY_CORE_EXP74_LED3_CM_SW_VAL_MASK                 0x0800
#define BRPHY4_GPHY_CORE_EXP74_LED3_CM_SW_VAL_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP74_LED3_CM_SW_VAL_BITS                 1
#define BRPHY4_GPHY_CORE_EXP74_LED3_CM_SW_VAL_SHIFT                11

/* BRPHY4_GPHY_CORE :: EXP74 :: LED3_CM_CTRL [10:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP74_LED3_CM_CTRL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP74,0x700,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP74_LED3_CM_CTRL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP74,0x700,8)
#define BRPHY4_GPHY_CORE_EXP74_LED3_CM_CTRL_MASK                   0x0700
#define BRPHY4_GPHY_CORE_EXP74_LED3_CM_CTRL_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP74_LED3_CM_CTRL_BITS                   3
#define BRPHY4_GPHY_CORE_EXP74_LED3_CM_CTRL_SHIFT                  8

/* BRPHY4_GPHY_CORE :: EXP74 :: LED2_CM_SW_VAL [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP74,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXP74_LED2_CM_SW_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP74,0x80,7)
#define BRPHY4_GPHY_CORE_EXP74_LED2_CM_SW_VAL_MASK                 0x0080
#define BRPHY4_GPHY_CORE_EXP74_LED2_CM_SW_VAL_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP74_LED2_CM_SW_VAL_BITS                 1
#define BRPHY4_GPHY_CORE_EXP74_LED2_CM_SW_VAL_SHIFT                7

/* BRPHY4_GPHY_CORE :: EXP74 :: LED2_CM_CTRL [06:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP74_LED2_CM_CTRL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP74,0x70,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP74_LED2_CM_CTRL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP74,0x70,4)
#define BRPHY4_GPHY_CORE_EXP74_LED2_CM_CTRL_MASK                   0x0070
#define BRPHY4_GPHY_CORE_EXP74_LED2_CM_CTRL_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP74_LED2_CM_CTRL_BITS                   3
#define BRPHY4_GPHY_CORE_EXP74_LED2_CM_CTRL_SHIFT                  4

/* BRPHY4_GPHY_CORE :: EXP74 :: LED1_CM_SW_VAL [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP74,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXP74_LED1_CM_SW_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP74,0x8,3)
#define BRPHY4_GPHY_CORE_EXP74_LED1_CM_SW_VAL_MASK                 0x0008
#define BRPHY4_GPHY_CORE_EXP74_LED1_CM_SW_VAL_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP74_LED1_CM_SW_VAL_BITS                 1
#define BRPHY4_GPHY_CORE_EXP74_LED1_CM_SW_VAL_SHIFT                3

/* BRPHY4_GPHY_CORE :: EXP74 :: LED1_CM_CTRL [02:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP74_LED1_CM_CTRL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP74,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP74_LED1_CM_CTRL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP74,0x7,0)
#define BRPHY4_GPHY_CORE_EXP74_LED1_CM_CTRL_MASK                   0x0007
#define BRPHY4_GPHY_CORE_EXP74_LED1_CM_CTRL_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXP74_LED1_CM_CTRL_BITS                   3
#define BRPHY4_GPHY_CORE_EXP74_LED1_CM_CTRL_SHIFT                  0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP75
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP75 :: reserved0 [15:10] */
#define BRPHY4_GPHY_CORE_EXP75_RESERVED0_MASK                      0xfc00
#define BRPHY4_GPHY_CORE_EXP75_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP75_RESERVED0_BITS                      6
#define BRPHY4_GPHY_CORE_EXP75_RESERVED0_SHIFT                     10

/* BRPHY4_GPHY_CORE :: EXP75 :: CED_LED_ERR_MASK [09:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP75,0x3ff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP75_CED_LED_ERR_MASK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP75,0x3ff,0)
#define BRPHY4_GPHY_CORE_EXP75_CED_LED_ERR_MASK_MASK               0x03ff
#define BRPHY4_GPHY_CORE_EXP75_CED_LED_ERR_MASK_ALIGN              0
#define BRPHY4_GPHY_CORE_EXP75_CED_LED_ERR_MASK_BITS               10
#define BRPHY4_GPHY_CORE_EXP75_CED_LED_ERR_MASK_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP78
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP78 :: DAC_ANA_TEST_EN [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP78,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXP78_DAC_ANA_TEST_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP78,0x8000,15)
#define BRPHY4_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_MASK                0x8000
#define BRPHY4_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_BITS                1
#define BRPHY4_GPHY_CORE_EXP78_DAC_ANA_TEST_EN_SHIFT               15

/* BRPHY4_GPHY_CORE :: EXP78 :: BR_TXPR_EN [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXP78_BR_TXPR_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP78,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXP78_BR_TXPR_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP78,0x4000,14)
#define BRPHY4_GPHY_CORE_EXP78_BR_TXPR_EN_MASK                     0x4000
#define BRPHY4_GPHY_CORE_EXP78_BR_TXPR_EN_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP78_BR_TXPR_EN_BITS                     1
#define BRPHY4_GPHY_CORE_EXP78_BR_TXPR_EN_SHIFT                    14

/* BRPHY4_GPHY_CORE :: EXP78 :: BR_IRP_EN [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXP78_BR_IRP_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP78,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXP78_BR_IRP_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP78,0x2000,13)
#define BRPHY4_GPHY_CORE_EXP78_BR_IRP_EN_MASK                      0x2000
#define BRPHY4_GPHY_CORE_EXP78_BR_IRP_EN_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP78_BR_IRP_EN_BITS                      1
#define BRPHY4_GPHY_CORE_EXP78_BR_IRP_EN_SHIFT                     13

/* BRPHY4_GPHY_CORE :: EXP78 :: PTE_BYPASS_EN [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP78,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP78_PTE_BYPASS_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP78,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP78_PTE_BYPASS_EN_MASK                  0x1000
#define BRPHY4_GPHY_CORE_EXP78_PTE_BYPASS_EN_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP78_PTE_BYPASS_EN_BITS                  1
#define BRPHY4_GPHY_CORE_EXP78_PTE_BYPASS_EN_SHIFT                 12

/* BRPHY4_GPHY_CORE :: EXP78 :: PTE_DISTORT [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXP78_PTE_DISTORT(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP78,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXP78_PTE_DISTORT(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP78,0x800,11)
#define BRPHY4_GPHY_CORE_EXP78_PTE_DISTORT_MASK                    0x0800
#define BRPHY4_GPHY_CORE_EXP78_PTE_DISTORT_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP78_PTE_DISTORT_BITS                    1
#define BRPHY4_GPHY_CORE_EXP78_PTE_DISTORT_SHIFT                   11

/* BRPHY4_GPHY_CORE :: EXP78 :: LP_SEL [10:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP78_LP_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP78,0x700,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP78_LP_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP78,0x700,8)
#define BRPHY4_GPHY_CORE_EXP78_LP_SEL_MASK                         0x0700
#define BRPHY4_GPHY_CORE_EXP78_LP_SEL_ALIGN                        0
#define BRPHY4_GPHY_CORE_EXP78_LP_SEL_BITS                         3
#define BRPHY4_GPHY_CORE_EXP78_LP_SEL_SHIFT                        8

/* BRPHY4_GPHY_CORE :: EXP78 :: HP_PGA_BYPASS [07:04] */
#define Wr_BRPHY4_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP78,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXP78_HP_PGA_BYPASS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP78,0xf0,4)
#define BRPHY4_GPHY_CORE_EXP78_HP_PGA_BYPASS_MASK                  0x00f0
#define BRPHY4_GPHY_CORE_EXP78_HP_PGA_BYPASS_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP78_HP_PGA_BYPASS_BITS                  4
#define BRPHY4_GPHY_CORE_EXP78_HP_PGA_BYPASS_SHIFT                 4

/* BRPHY4_GPHY_CORE :: EXP78 :: TDR_GAIN [03:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP78_TDR_GAIN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP78,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP78_TDR_GAIN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP78,0xf,0)
#define BRPHY4_GPHY_CORE_EXP78_TDR_GAIN_MASK                       0x000f
#define BRPHY4_GPHY_CORE_EXP78_TDR_GAIN_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP78_TDR_GAIN_BITS                       4
#define BRPHY4_GPHY_CORE_EXP78_TDR_GAIN_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP7B
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP7B :: I2C_CMD [15:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP7B_I2C_CMD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP7B,0xf000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP7B_I2C_CMD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP7B,0xf000,12)
#define BRPHY4_GPHY_CORE_EXP7B_I2C_CMD_MASK                        0xf000
#define BRPHY4_GPHY_CORE_EXP7B_I2C_CMD_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP7B_I2C_CMD_BITS                        4
#define BRPHY4_GPHY_CORE_EXP7B_I2C_CMD_SHIFT                       12

/* BRPHY4_GPHY_CORE :: EXP7B :: I2C_CTL [11:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP7B_I2C_CTL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP7B,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP7B_I2C_CTL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP7B,0xfff,0)
#define BRPHY4_GPHY_CORE_EXP7B_I2C_CTL_MASK                        0x0fff
#define BRPHY4_GPHY_CORE_EXP7B_I2C_CTL_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP7B_I2C_CTL_BITS                        12
#define BRPHY4_GPHY_CORE_EXP7B_I2C_CTL_SHIFT                       0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP7C
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP7C :: I2C_STATUS [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP7C_I2C_STATUS(x) WriteReg16(BRPHY4_GPHY_CORE_EXP7C,x)
#define Rd_BRPHY4_GPHY_CORE_EXP7C_I2C_STATUS(x) ReadReg16(BRPHY4_GPHY_CORE_EXP7C)
#define BRPHY4_GPHY_CORE_EXP7C_I2C_STATUS_MASK                     0xffff
#define BRPHY4_GPHY_CORE_EXP7C_I2C_STATUS_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP7C_I2C_STATUS_BITS                     16
#define BRPHY4_GPHY_CORE_EXP7C_I2C_STATUS_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP7F
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP7F :: reserved0 [15:13] */
#define BRPHY4_GPHY_CORE_EXP7F_RESERVED0_MASK                      0xe000
#define BRPHY4_GPHY_CORE_EXP7F_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP7F_RESERVED0_BITS                      3
#define BRPHY4_GPHY_CORE_EXP7F_RESERVED0_SHIFT                     13

/* BRPHY4_GPHY_CORE :: EXP7F :: BR_PSD_PIN_DISABLE [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x1000,12)
#define BRPHY4_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_MASK             0x1000
#define BRPHY4_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_ALIGN            0
#define BRPHY4_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_BITS             1
#define BRPHY4_GPHY_CORE_EXP7F_BR_PSD_PIN_DISABLE_SHIFT            12

/* BRPHY4_GPHY_CORE :: EXP7F :: BR_PSD_OFF [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXP7F_BR_PSD_OFF(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXP7F_BR_PSD_OFF(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x800,11)
#define BRPHY4_GPHY_CORE_EXP7F_BR_PSD_OFF_MASK                     0x0800
#define BRPHY4_GPHY_CORE_EXP7F_BR_PSD_OFF_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP7F_BR_PSD_OFF_BITS                     1
#define BRPHY4_GPHY_CORE_EXP7F_BR_PSD_OFF_SHIFT                    11

/* BRPHY4_GPHY_CORE :: EXP7F :: ECD_DC_OFFSET [10:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x7fc,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP7F_ECD_DC_OFFSET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x7fc,2)
#define BRPHY4_GPHY_CORE_EXP7F_ECD_DC_OFFSET_MASK                  0x07fc
#define BRPHY4_GPHY_CORE_EXP7F_ECD_DC_OFFSET_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXP7F_ECD_DC_OFFSET_BITS                  9
#define BRPHY4_GPHY_CORE_EXP7F_ECD_DC_OFFSET_SHIFT                 2

/* BRPHY4_GPHY_CORE :: EXP7F :: FIBER_UNIDIR_OV [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x2,1)
#define BRPHY4_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_MASK                0x0002
#define BRPHY4_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_BITS                1
#define BRPHY4_GPHY_CORE_EXP7F_FIBER_UNIDIR_OV_SHIFT               1

/* BRPHY4_GPHY_CORE :: EXP7F :: MACSEC_EN [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP7F_MACSEC_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP7F_MACSEC_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP7F,0x1,0)
#define BRPHY4_GPHY_CORE_EXP7F_MACSEC_EN_MASK                      0x0001
#define BRPHY4_GPHY_CORE_EXP7F_MACSEC_EN_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP7F_MACSEC_EN_BITS                      1
#define BRPHY4_GPHY_CORE_EXP7F_MACSEC_EN_SHIFT                     0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: ALIAS_18
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: ALIAS_18 :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_ALIAS_18_RESERVED0_MASK                   0xf000
#define BRPHY4_GPHY_CORE_ALIAS_18_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_ALIAS_18_RESERVED0_BITS                   4
#define BRPHY4_GPHY_CORE_ALIAS_18_RESERVED0_SHIFT                  12

/* BRPHY4_GPHY_CORE :: ALIAS_18 :: ALIAS [11:00] */
#define Wr_BRPHY4_GPHY_CORE_ALIAS_18_ALIAS(x) WriteRegBits16(BRPHY4_GPHY_CORE_ALIAS_18,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_ALIAS_18_ALIAS(x) ReadRegBits16(BRPHY4_GPHY_CORE_ALIAS_18,0xfff,0)
#define BRPHY4_GPHY_CORE_ALIAS_18_ALIAS_MASK                       0x0fff
#define BRPHY4_GPHY_CORE_ALIAS_18_ALIAS_ALIGN                      0
#define BRPHY4_GPHY_CORE_ALIAS_18_ALIAS_BITS                       12
#define BRPHY4_GPHY_CORE_ALIAS_18_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: ALIAS_19
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: ALIAS_19 :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_ALIAS_19_RESERVED0_MASK                   0xf000
#define BRPHY4_GPHY_CORE_ALIAS_19_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_ALIAS_19_RESERVED0_BITS                   4
#define BRPHY4_GPHY_CORE_ALIAS_19_RESERVED0_SHIFT                  12

/* BRPHY4_GPHY_CORE :: ALIAS_19 :: ALIAS [11:00] */
#define Wr_BRPHY4_GPHY_CORE_ALIAS_19_ALIAS(x) WriteRegBits16(BRPHY4_GPHY_CORE_ALIAS_19,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_ALIAS_19_ALIAS(x) ReadRegBits16(BRPHY4_GPHY_CORE_ALIAS_19,0xfff,0)
#define BRPHY4_GPHY_CORE_ALIAS_19_ALIAS_MASK                       0x0fff
#define BRPHY4_GPHY_CORE_ALIAS_19_ALIAS_ALIGN                      0
#define BRPHY4_GPHY_CORE_ALIAS_19_ALIAS_BITS                       12
#define BRPHY4_GPHY_CORE_ALIAS_19_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: ALIAS_1a
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: ALIAS_1a :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_ALIAS_1A_RESERVED0_MASK                   0xf000
#define BRPHY4_GPHY_CORE_ALIAS_1A_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_ALIAS_1A_RESERVED0_BITS                   4
#define BRPHY4_GPHY_CORE_ALIAS_1A_RESERVED0_SHIFT                  12

/* BRPHY4_GPHY_CORE :: ALIAS_1a :: ALIAS [11:00] */
#define Wr_BRPHY4_GPHY_CORE_ALIAS_1a_ALIAS(x) WriteRegBits16(BRPHY4_GPHY_CORE_ALIAS_1A,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_ALIAS_1a_ALIAS(x) ReadRegBits16(BRPHY4_GPHY_CORE_ALIAS_1A,0xfff,0)
#define BRPHY4_GPHY_CORE_ALIAS_1A_ALIAS_MASK                       0x0fff
#define BRPHY4_GPHY_CORE_ALIAS_1A_ALIAS_ALIGN                      0
#define BRPHY4_GPHY_CORE_ALIAS_1A_ALIAS_BITS                       12
#define BRPHY4_GPHY_CORE_ALIAS_1A_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: ALIAS_1b
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: ALIAS_1b :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_ALIAS_1B_RESERVED0_MASK                   0xf000
#define BRPHY4_GPHY_CORE_ALIAS_1B_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_ALIAS_1B_RESERVED0_BITS                   4
#define BRPHY4_GPHY_CORE_ALIAS_1B_RESERVED0_SHIFT                  12

/* BRPHY4_GPHY_CORE :: ALIAS_1b :: ALIAS [11:00] */
#define Wr_BRPHY4_GPHY_CORE_ALIAS_1b_ALIAS(x) WriteRegBits16(BRPHY4_GPHY_CORE_ALIAS_1B,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_ALIAS_1b_ALIAS(x) ReadRegBits16(BRPHY4_GPHY_CORE_ALIAS_1B,0xfff,0)
#define BRPHY4_GPHY_CORE_ALIAS_1B_ALIAS_MASK                       0x0fff
#define BRPHY4_GPHY_CORE_ALIAS_1B_ALIAS_ALIGN                      0
#define BRPHY4_GPHY_CORE_ALIAS_1B_ALIAS_BITS                       12
#define BRPHY4_GPHY_CORE_ALIAS_1B_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: ALIAS_1c
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: ALIAS_1c :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_ALIAS_1C_RESERVED0_MASK                   0xf000
#define BRPHY4_GPHY_CORE_ALIAS_1C_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_ALIAS_1C_RESERVED0_BITS                   4
#define BRPHY4_GPHY_CORE_ALIAS_1C_RESERVED0_SHIFT                  12

/* BRPHY4_GPHY_CORE :: ALIAS_1c :: ALIAS [11:00] */
#define Wr_BRPHY4_GPHY_CORE_ALIAS_1c_ALIAS(x) WriteRegBits16(BRPHY4_GPHY_CORE_ALIAS_1C,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_ALIAS_1c_ALIAS(x) ReadRegBits16(BRPHY4_GPHY_CORE_ALIAS_1C,0xfff,0)
#define BRPHY4_GPHY_CORE_ALIAS_1C_ALIAS_MASK                       0x0fff
#define BRPHY4_GPHY_CORE_ALIAS_1C_ALIAS_ALIGN                      0
#define BRPHY4_GPHY_CORE_ALIAS_1C_ALIAS_BITS                       12
#define BRPHY4_GPHY_CORE_ALIAS_1C_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: ALIAS_1d
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: ALIAS_1d :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_ALIAS_1D_RESERVED0_MASK                   0xf000
#define BRPHY4_GPHY_CORE_ALIAS_1D_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_ALIAS_1D_RESERVED0_BITS                   4
#define BRPHY4_GPHY_CORE_ALIAS_1D_RESERVED0_SHIFT                  12

/* BRPHY4_GPHY_CORE :: ALIAS_1d :: ALIAS [11:00] */
#define Wr_BRPHY4_GPHY_CORE_ALIAS_1d_ALIAS(x) WriteRegBits16(BRPHY4_GPHY_CORE_ALIAS_1D,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_ALIAS_1d_ALIAS(x) ReadRegBits16(BRPHY4_GPHY_CORE_ALIAS_1D,0xfff,0)
#define BRPHY4_GPHY_CORE_ALIAS_1D_ALIAS_MASK                       0x0fff
#define BRPHY4_GPHY_CORE_ALIAS_1D_ALIAS_ALIGN                      0
#define BRPHY4_GPHY_CORE_ALIAS_1D_ALIAS_BITS                       12
#define BRPHY4_GPHY_CORE_ALIAS_1D_ALIAS_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: REG_MAP_CTL
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: REG_MAP_CTL :: REG_LEGACY_EN [15:15] */
#define Wr_BRPHY4_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_REG_MAP_CTL,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_REG_MAP_CTL,0x8000,15)
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_MASK            0x8000
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_BITS            1
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_REG_LEGACY_EN_SHIFT           15

/* BRPHY4_GPHY_CORE :: REG_MAP_CTL :: ALIAS_MODE [14:13] */
#define Wr_BRPHY4_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_REG_MAP_CTL,0x6000,13,x)
#define Rd_BRPHY4_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_REG_MAP_CTL,0x6000,13)
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_MASK               0x6000
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_ALIGN              0
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_BITS               2
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_ALIAS_MODE_SHIFT              13

/* BRPHY4_GPHY_CORE :: REG_MAP_CTL :: reserved0 [12:12] */
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_RESERVED0_MASK                0x1000
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_RESERVED0_ALIGN               0
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_RESERVED0_BITS                1
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_RESERVED0_SHIFT               12

/* BRPHY4_GPHY_CORE :: REG_MAP_CTL :: RANGE_OFFSET [11:00] */
#define Wr_BRPHY4_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) WriteRegBits16(BRPHY4_GPHY_CORE_REG_MAP_CTL,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET(x) ReadRegBits16(BRPHY4_GPHY_CORE_REG_MAP_CTL,0xfff,0)
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_MASK             0x0fff
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_ALIGN            0
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_BITS             12
#define BRPHY4_GPHY_CORE_REG_MAP_CTL_RANGE_OFFSET_SHIFT            0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP98
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP98 :: reserved0 [15:11] */
#define BRPHY4_GPHY_CORE_EXP98_RESERVED0_MASK                      0xf800
#define BRPHY4_GPHY_CORE_EXP98_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXP98_RESERVED0_BITS                      5
#define BRPHY4_GPHY_CORE_EXP98_RESERVED0_SHIFT                     11

/* BRPHY4_GPHY_CORE :: EXP98 :: RC_CAL [10:06] */
#define Wr_BRPHY4_GPHY_CORE_EXP98_RC_CAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP98,0x7c0,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXP98_RC_CAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP98,0x7c0,6)
#define BRPHY4_GPHY_CORE_EXP98_RC_CAL_MASK                         0x07c0
#define BRPHY4_GPHY_CORE_EXP98_RC_CAL_ALIGN                        0
#define BRPHY4_GPHY_CORE_EXP98_RC_CAL_BITS                         5
#define BRPHY4_GPHY_CORE_EXP98_RC_CAL_SHIFT                        6

/* BRPHY4_GPHY_CORE :: EXP98 :: R_CAL [05:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP98_R_CAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP98,0x3e,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP98_R_CAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP98,0x3e,1)
#define BRPHY4_GPHY_CORE_EXP98_R_CAL_MASK                          0x003e
#define BRPHY4_GPHY_CORE_EXP98_R_CAL_ALIGN                         0
#define BRPHY4_GPHY_CORE_EXP98_R_CAL_BITS                          5
#define BRPHY4_GPHY_CORE_EXP98_R_CAL_SHIFT                         1

/* BRPHY4_GPHY_CORE :: EXP98 :: CAL_DONE [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP98_CAL_DONE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP98,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP98_CAL_DONE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP98,0x1,0)
#define BRPHY4_GPHY_CORE_EXP98_CAL_DONE_MASK                       0x0001
#define BRPHY4_GPHY_CORE_EXP98_CAL_DONE_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP98_CAL_DONE_BITS                       1
#define BRPHY4_GPHY_CORE_EXP98_CAL_DONE_SHIFT                      0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXP9C
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXP9C :: MII_REG1C_BNK1 [15:12] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0xf000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_MII_REG1C_BNK1(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0xf000,12)
#define BRPHY4_GPHY_CORE_EXP9C_MII_REG1C_BNK1_MASK                 0xf000
#define BRPHY4_GPHY_CORE_EXP9C_MII_REG1C_BNK1_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP9C_MII_REG1C_BNK1_BITS                 4
#define BRPHY4_GPHY_CORE_EXP9C_MII_REG1C_BNK1_SHIFT                12

/* BRPHY4_GPHY_CORE :: EXP9C :: RSMII_LOAD_XMT [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_RSMII_LOAD_XMT(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x800,11)
#define BRPHY4_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_MASK                 0x0800
#define BRPHY4_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_BITS                 1
#define BRPHY4_GPHY_CORE_EXP9C_RSMII_LOAD_XMT_SHIFT                11

/* BRPHY4_GPHY_CORE :: EXP9C :: FIFO_OV_UN [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_FIFO_OV_UN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_FIFO_OV_UN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x400,10)
#define BRPHY4_GPHY_CORE_EXP9C_FIFO_OV_UN_MASK                     0x0400
#define BRPHY4_GPHY_CORE_EXP9C_FIFO_OV_UN_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP9C_FIFO_OV_UN_BITS                     1
#define BRPHY4_GPHY_CORE_EXP9C_FIFO_OV_UN_SHIFT                    10

/* BRPHY4_GPHY_CORE :: EXP9C :: TEST_EN [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_TEST_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_TEST_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x200,9)
#define BRPHY4_GPHY_CORE_EXP9C_TEST_EN_MASK                        0x0200
#define BRPHY4_GPHY_CORE_EXP9C_TEST_EN_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXP9C_TEST_EN_BITS                        1
#define BRPHY4_GPHY_CORE_EXP9C_TEST_EN_SHIFT                       9

/* BRPHY4_GPHY_CORE :: EXP9C :: PTEST [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_PTEST(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_PTEST(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x100,8)
#define BRPHY4_GPHY_CORE_EXP9C_PTEST_MASK                          0x0100
#define BRPHY4_GPHY_CORE_EXP9C_PTEST_ALIGN                         0
#define BRPHY4_GPHY_CORE_EXP9C_PTEST_BITS                          1
#define BRPHY4_GPHY_CORE_EXP9C_PTEST_SHIFT                         8

/* BRPHY4_GPHY_CORE :: EXP9C :: EXRMIIFE [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_EXRMIIFE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_EXRMIIFE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x80,7)
#define BRPHY4_GPHY_CORE_EXP9C_EXRMIIFE_MASK                       0x0080
#define BRPHY4_GPHY_CORE_EXP9C_EXRMIIFE_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXP9C_EXRMIIFE_BITS                       1
#define BRPHY4_GPHY_CORE_EXP9C_EXRMIIFE_SHIFT                      7

/* BRPHY4_GPHY_CORE :: EXP9C :: FIFO_SIZE_CNTL [06:03] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x78,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x78,3)
#define BRPHY4_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_MASK                 0x0078
#define BRPHY4_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_ALIGN                0
#define BRPHY4_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_BITS                 4
#define BRPHY4_GPHY_CORE_EXP9C_FIFO_SIZE_CNTL_SHIFT                3

/* BRPHY4_GPHY_CORE :: EXP9C :: BIG_FIFO_EN [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_BIG_FIFO_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x4,2)
#define BRPHY4_GPHY_CORE_EXP9C_BIG_FIFO_EN_MASK                    0x0004
#define BRPHY4_GPHY_CORE_EXP9C_BIG_FIFO_EN_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXP9C_BIG_FIFO_EN_BITS                    1
#define BRPHY4_GPHY_CORE_EXP9C_BIG_FIFO_EN_SHIFT                   2

/* BRPHY4_GPHY_CORE :: EXP9C :: SMII_S3MII_MODE [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_SMII_S3MII_MODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x2,1)
#define BRPHY4_GPHY_CORE_EXP9C_SMII_S3MII_MODE_MASK                0x0002
#define BRPHY4_GPHY_CORE_EXP9C_SMII_S3MII_MODE_ALIGN               0
#define BRPHY4_GPHY_CORE_EXP9C_SMII_S3MII_MODE_BITS                1
#define BRPHY4_GPHY_CORE_EXP9C_SMII_S3MII_MODE_SHIFT               1

/* BRPHY4_GPHY_CORE :: EXP9C :: SSSMII_DIS [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXP9C_SSSMII_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXP9C_SSSMII_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXP9C,0x1,0)
#define BRPHY4_GPHY_CORE_EXP9C_SSSMII_DIS_MASK                     0x0001
#define BRPHY4_GPHY_CORE_EXP9C_SSSMII_DIS_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXP9C_SSSMII_DIS_BITS                     1
#define BRPHY4_GPHY_CORE_EXP9C_SSSMII_DIS_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: BT_LINK_FIX
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: BT_LINK_FIX :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RESERVED0_MASK                0x8000
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RESERVED0_ALIGN               0
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RESERVED0_BITS                1
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RESERVED0_SHIFT               15

/* BRPHY4_GPHY_CORE :: BT_LINK_FIX :: rxc_byp_rclk_dll_div2 [14:14] */
#define Wr_BRPHY4_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) WriteRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_BT_LINK_FIX_rxc_byp_rclk_dll_div2(x) ReadRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0x4000,14)
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_MASK    0x4000
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_ALIGN   0
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_BITS    1
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RXC_BYP_RCLK_DLL_DIV2_SHIFT   14

/* BRPHY4_GPHY_CORE :: BT_LINK_FIX :: rxc_shamoo_tst_en [13:13] */
#define Wr_BRPHY4_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) WriteRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_BT_LINK_FIX_rxc_shamoo_tst_en(x) ReadRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0x2000,13)
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_MASK        0x2000
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_ALIGN       0
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_BITS        1
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_RXC_SHAMOO_TST_EN_SHIFT       13

/* BRPHY4_GPHY_CORE :: BT_LINK_FIX :: sig_10bt_upp_limit [12:08] */
#define Wr_BRPHY4_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) WriteRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0x1f00,8,x)
#define Rd_BRPHY4_GPHY_CORE_BT_LINK_FIX_sig_10bt_upp_limit(x) ReadRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0x1f00,8)
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_MASK       0x1f00
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_ALIGN      0
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_BITS       5
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_SIG_10BT_UPP_LIMIT_SHIFT      8

/* BRPHY4_GPHY_CORE :: BT_LINK_FIX :: threshold_2mhz [07:01] */
#define Wr_BRPHY4_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) WriteRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0xfe,1,x)
#define Rd_BRPHY4_GPHY_CORE_BT_LINK_FIX_threshold_2mhz(x) ReadRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0xfe,1)
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_MASK           0x00fe
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_ALIGN          0
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_BITS           7
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_THRESHOLD_2MHZ_SHIFT          1

/* BRPHY4_GPHY_CORE :: BT_LINK_FIX :: break_link10bt_disable [00:00] */
#define Wr_BRPHY4_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) WriteRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_BT_LINK_FIX_break_link10bt_disable(x) ReadRegBits16(BRPHY4_GPHY_CORE_BT_LINK_FIX,0x1,0)
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_MASK   0x0001
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_ALIGN  0
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_BITS   1
#define BRPHY4_GPHY_CORE_BT_LINK_FIX_BREAK_LINK10BT_DISABLE_SHIFT  0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SYNCE_PLUS_DBG
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_DBG [15:02] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG,0xfffc,2)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_MASK             0xfffc
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_ALIGN            0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_BITS             14
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_DBG_SHIFT            2

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_BRUTEFORCE_TM [01:01] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG,0x2,1)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_MASK   0x0002
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_ALIGN  0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_BITS   1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_BRUTEFORCE_TM_SHIFT  1

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS_DBG :: SYNCE_HSTIMEOUT_CTL [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG,0x1,0)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_MASK   0x0001
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_ALIGN  0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_BITS   1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_DBG_SYNCE_HSTIMEOUT_CTL_SHIFT  0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: SYNCE_PLUS
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: TIMING_CONFIG [15:15] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x8000,15)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_MASK             0x8000
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_ALIGN            0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_BITS             1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_CONFIG_SHIFT            15

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_ONGOING [14:14] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x4000,14)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_MASK     0x4000
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_ALIGN    0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_BITS     1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_ONGOING_SHIFT    14

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: SYNCE_AUTO_ACK [13:13] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x2000,13)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_MASK            0x2000
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_ALIGN           0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_BITS            1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_AUTO_ACK_SHIFT           13

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: SYNCE_WAIT_FOR_IDLE [12:12] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x1000,12)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_MASK       0x1000
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_ALIGN      0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_BITS       1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_WAIT_FOR_IDLE_SHIFT      12

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_COMPLETE [11:11] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x800,11)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_MASK    0x0800
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_ALIGN   0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_BITS    1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_COMPLETE_SHIFT   11

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_PENDING [10:10] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x400,10)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_MASK     0x0400
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_ALIGN    0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_BITS     1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_PENDING_SHIFT    10

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ERROR_STATUS [09:08] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x300,8,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x300,8)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_MASK        0x0300
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_ALIGN       0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_BITS        2
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ERROR_STATUS_SHIFT       8

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: TIMING_SWITCH_FAIL [07:07] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x80,7)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_MASK        0x0080
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_ALIGN       0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_BITS        1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_TIMING_SWITCH_FAIL_SHIFT       7

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: SYNCE_FTIMEOUT_CTL [06:06] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x40,6)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_MASK        0x0040
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_ALIGN       0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_BITS        1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_FTIMEOUT_CTL_SHIFT       6

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: SYNCE_DBG_MUX_CTL [05:04] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x30,4,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x30,4)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_MASK         0x0030
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_ALIGN        0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_BITS         2
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_DBG_MUX_CTL_SHIFT        4

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: SYNCE_INTERRUPT_MASK [03:02] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0xc,2,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0xc,2)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_MASK      0x000c
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_ALIGN     0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_BITS      2
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_INTERRUPT_MASK_SHIFT     2

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: SYNCE_TIMING_SWITCH_START [01:01] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x2,1)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_MASK 0x0002
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_ALIGN 0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_BITS 1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_TIMING_SWITCH_START_SHIFT 1

/* BRPHY4_GPHY_CORE :: SYNCE_PLUS :: SYNCE_ENABLE [00:00] */
#define Wr_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_SYNCE_PLUS,0x1,0)
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_MASK              0x0001
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_ALIGN             0
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_BITS              1
#define BRPHY4_GPHY_CORE_SYNCE_PLUS_SYNCE_ENABLE_SHIFT             0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPA8
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPA8 :: ADAPTIVE_BIAS_CTRL [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) WriteReg16(BRPHY4_GPHY_CORE_EXPA8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL(x) ReadReg16(BRPHY4_GPHY_CORE_EXPA8)
#define BRPHY4_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_MASK             0xffff
#define BRPHY4_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_BITS             16
#define BRPHY4_GPHY_CORE_EXPA8_ADAPTIVE_BIAS_CTRL_SHIFT            0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPA9
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPA9 :: SPARE_REG [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPA9_SPARE_REG(x) WriteReg16(BRPHY4_GPHY_CORE_EXPA9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPA9_SPARE_REG(x) ReadReg16(BRPHY4_GPHY_CORE_EXPA9)
#define BRPHY4_GPHY_CORE_EXPA9_SPARE_REG_MASK                      0xffff
#define BRPHY4_GPHY_CORE_EXPA9_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPA9_SPARE_REG_BITS                      16
#define BRPHY4_GPHY_CORE_EXPA9_SPARE_REG_SHIFT                     0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPAA
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPAA :: STATISTIC_TIMER_12HOURS_LPI [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) WriteReg16(BRPHY4_GPHY_CORE_EXPAA,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI(x) ReadReg16(BRPHY4_GPHY_CORE_EXPAA)
#define BRPHY4_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_MASK    0xffff
#define BRPHY4_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_ALIGN   0
#define BRPHY4_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_BITS    16
#define BRPHY4_GPHY_CORE_EXPAA_STATISTIC_TIMER_12HOURS_LPI_SHIFT   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPAB
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPAB :: STATISTIC_TIMER_12HOURS_LOCAL [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) WriteReg16(BRPHY4_GPHY_CORE_EXPAB,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL(x) ReadReg16(BRPHY4_GPHY_CORE_EXPAB)
#define BRPHY4_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_MASK  0xffff
#define BRPHY4_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_ALIGN 0
#define BRPHY4_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_BITS  16
#define BRPHY4_GPHY_CORE_EXPAB_STATISTIC_TIMER_12HOURS_LOCAL_SHIFT 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPAC
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPAC :: STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY4_GPHY_CORE_EXPAC,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY4_GPHY_CORE_EXPAC)
#define BRPHY4_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY4_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY4_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY4_GPHY_CORE_EXPAC_STATISTIC_LOC_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPAD
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPAD :: STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) WriteReg16(BRPHY4_GPHY_CORE_EXPAD,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER(x) ReadReg16(BRPHY4_GPHY_CORE_EXPAD)
#define BRPHY4_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_MASK 0xffff
#define BRPHY4_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_ALIGN 0
#define BRPHY4_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_BITS 16
#define BRPHY4_GPHY_CORE_EXPAD_STATISTIC_REM_LPI_REQ_0_TO_1_COUNTER_SHIFT 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPAE
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPAE :: SPARE_REG [15:09] */
#define Wr_BRPHY4_GPHY_CORE_EXPAE_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAE,0xfe00,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAE_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAE,0xfe00,9)
#define BRPHY4_GPHY_CORE_EXPAE_SPARE_REG_MASK                      0xfe00
#define BRPHY4_GPHY_CORE_EXPAE_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPAE_SPARE_REG_BITS                      7
#define BRPHY4_GPHY_CORE_EXPAE_SPARE_REG_SHIFT                     9

/* BRPHY4_GPHY_CORE :: EXPAE :: TXBIAS_VAL2 [08:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAE,0x1e0,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL2(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAE,0x1e0,5)
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL2_MASK                    0x01e0
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL2_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL2_BITS                    4
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL2_SHIFT                   5

/* BRPHY4_GPHY_CORE :: EXPAE :: TXBIAS_VAL1 [04:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAE,0x1e,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL1(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAE,0x1e,1)
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL1_MASK                    0x001e
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL1_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL1_BITS                    4
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_VAL1_SHIFT                   1

/* BRPHY4_GPHY_CORE :: EXPAE :: TXBIAS_PLUS_MODE [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAE,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAE,0x1,0)
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_MASK               0x0001
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_BITS               1
#define BRPHY4_GPHY_CORE_EXPAE_TXBIAS_PLUS_MODE_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPAF
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPAF :: STATISTIC_1000BT_MODE [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x8000,15)
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_MASK          0x8000
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_ALIGN         0
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_BITS          1
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_1000BT_MODE_SHIFT         15

/* BRPHY4_GPHY_CORE :: EXPAF :: STATISTIC_UPPER_16BITS_SEL [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x4000,14)
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_MASK     0x4000
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_ALIGN    0
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_BITS     1
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_UPPER_16BITS_SEL_SHIFT    14

/* BRPHY4_GPHY_CORE :: EXPAF :: STATISTIC_SATURATE_MODE [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x2000,13)
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_MASK        0x2000
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_ALIGN       0
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_BITS        1
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_SATURATE_MODE_SHIFT       13

/* BRPHY4_GPHY_CORE :: EXPAF :: STATISTIC_ACCESS_MODE [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_MASK          0x1000
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_ALIGN         0
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_BITS          1
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ACCESS_MODE_SHIFT         12

/* BRPHY4_GPHY_CORE :: EXPAF :: SPARE_REG [11:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0xfe0,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0xfe0,5)
#define BRPHY4_GPHY_CORE_EXPAF_SPARE_REG_MASK                      0x0fe0
#define BRPHY4_GPHY_CORE_EXPAF_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPAF_SPARE_REG_BITS                      7
#define BRPHY4_GPHY_CORE_EXPAF_SPARE_REG_SHIFT                     5

/* BRPHY4_GPHY_CORE :: EXPAF :: EEE_REM_RCVR_STATUS_DIS [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x10,4)
#define BRPHY4_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_MASK        0x0010
#define BRPHY4_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY4_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_BITS        1
#define BRPHY4_GPHY_CORE_EXPAF_EEE_REM_RCVR_STATUS_DIS_SHIFT       4

/* BRPHY4_GPHY_CORE :: EXPAF :: EEE_LOC_RCVR_STATUS_DIS [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x8,3)
#define BRPHY4_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_MASK        0x0008
#define BRPHY4_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_ALIGN       0
#define BRPHY4_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_BITS        1
#define BRPHY4_GPHY_CORE_EXPAF_EEE_LOC_RCVR_STATUS_DIS_SHIFT       3

/* BRPHY4_GPHY_CORE :: EXPAF :: STATISTIC_ADAPTX_EN [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x4,2)
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_MASK            0x0004
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_ALIGN           0
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_BITS            1
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_ADAPTX_EN_SHIFT           2

/* BRPHY4_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_RESET [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x2,1)
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_MASK       0x0002
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_ALIGN      0
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_BITS       1
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_RESET_SHIFT      1

/* BRPHY4_GPHY_CORE :: EXPAF :: STATISTIC_COUNTERS_ENABLE [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPAF,0x1,0)
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_MASK      0x0001
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_ALIGN     0
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_BITS      1
#define BRPHY4_GPHY_CORE_EXPAF_STATISTIC_COUNTERS_ENABLE_SHIFT     0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPB0
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPB0 :: BIAS_CTL_0 [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPB0_BIAS_CTL_0(x) WriteReg16(BRPHY4_GPHY_CORE_EXPB0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPB0_BIAS_CTL_0(x) ReadReg16(BRPHY4_GPHY_CORE_EXPB0)
#define BRPHY4_GPHY_CORE_EXPB0_BIAS_CTL_0_MASK                     0xffff
#define BRPHY4_GPHY_CORE_EXPB0_BIAS_CTL_0_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPB0_BIAS_CTL_0_BITS                     16
#define BRPHY4_GPHY_CORE_EXPB0_BIAS_CTL_0_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPB1
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPB1 :: BIAS_CTL_1 [15:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPB1_BIAS_CTL_1(x) WriteReg16(BRPHY4_GPHY_CORE_EXPB1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPB1_BIAS_CTL_1(x) ReadReg16(BRPHY4_GPHY_CORE_EXPB1)
#define BRPHY4_GPHY_CORE_EXPB1_BIAS_CTL_1_MASK                     0xffff
#define BRPHY4_GPHY_CORE_EXPB1_BIAS_CTL_1_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPB1_BIAS_CTL_1_BITS                     16
#define BRPHY4_GPHY_CORE_EXPB1_BIAS_CTL_1_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPB2
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPB2 :: CLK200_SEL_OV [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPB2,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPB2,0x8000,15)
#define BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_OV_MASK                  0x8000
#define BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_OV_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_OV_BITS                  1
#define BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_OV_SHIFT                 15

/* BRPHY4_GPHY_CORE :: EXPB2 :: CLK200_SEL [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPB2,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPB2,0x4000,14)
#define BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_MASK                     0x4000
#define BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_BITS                     1
#define BRPHY4_GPHY_CORE_EXPB2_CLK200_SEL_SHIFT                    14

/* BRPHY4_GPHY_CORE :: EXPB2 :: CK25_SEL [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPB2_CK25_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPB2,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPB2_CK25_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPB2,0x2000,13)
#define BRPHY4_GPHY_CORE_EXPB2_CK25_SEL_MASK                       0x2000
#define BRPHY4_GPHY_CORE_EXPB2_CK25_SEL_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXPB2_CK25_SEL_BITS                       1
#define BRPHY4_GPHY_CORE_EXPB2_CK25_SEL_SHIFT                      13

/* BRPHY4_GPHY_CORE :: EXPB2 :: REG_B2_SPARE [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPB2_REG_B2_SPARE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPB2,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPB2_REG_B2_SPARE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPB2,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPB2_REG_B2_SPARE_MASK                   0x1000
#define BRPHY4_GPHY_CORE_EXPB2_REG_B2_SPARE_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPB2_REG_B2_SPARE_BITS                   1
#define BRPHY4_GPHY_CORE_EXPB2_REG_B2_SPARE_SHIFT                  12

/* BRPHY4_GPHY_CORE :: EXPB2 :: I_RC_OFFSET_PHY [11:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPB2,0xf00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPB2,0xf00,8)
#define BRPHY4_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_MASK                0x0f00
#define BRPHY4_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_BITS                4
#define BRPHY4_GPHY_CORE_EXPB2_I_RC_OFFSET_PHY_SHIFT               8

/* BRPHY4_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_1000_100 [07:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPB2,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPB2,0xf0,4)
#define BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_MASK        0x00f0
#define BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_ALIGN       0
#define BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_BITS        4
#define BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_1000_100_SHIFT       4

/* BRPHY4_GPHY_CORE :: EXPB2 :: I_R_OFFSET_PHY_10 [03:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPB2,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPB2,0xf,0)
#define BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_MASK              0x000f
#define BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_BITS              4
#define BRPHY4_GPHY_CORE_EXPB2_I_R_OFFSET_PHY_10_SHIFT             0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE3
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE3,0xff00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_100(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE3,0xff00,8)
#define BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_100_MASK                 0xff00
#define BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_100_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_100_BITS                 8
#define BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_100_SHIFT                8

/* BRPHY4_GPHY_CORE :: EXPE3 :: TX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE3,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_1000(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE3,0xff,0)
#define BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_BITS                8
#define BRPHY4_GPHY_CORE_EXPE3_TX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE4
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE4 :: TX_PCS_SOP_TSYNC_ERR [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE4,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE4,0x8000,15)
#define BRPHY4_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_MASK           0x8000
#define BRPHY4_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_BITS           1
#define BRPHY4_GPHY_CORE_EXPE4_TX_PCS_SOP_TSYNC_ERR_SHIFT          15

/* BRPHY4_GPHY_CORE :: EXPE4 :: reserved0 [14:12] */
#define BRPHY4_GPHY_CORE_EXPE4_RESERVED0_MASK                      0x7000
#define BRPHY4_GPHY_CORE_EXPE4_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPE4_RESERVED0_BITS                      3
#define BRPHY4_GPHY_CORE_EXPE4_RESERVED0_SHIFT                     12

/* BRPHY4_GPHY_CORE :: EXPE4 :: TX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE4,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE4_TX_PCS_DLY_10(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE4,0xfff,0)
#define BRPHY4_GPHY_CORE_EXPE4_TX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY4_GPHY_CORE_EXPE4_TX_PCS_DLY_10_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXPE4_TX_PCS_DLY_10_BITS                  12
#define BRPHY4_GPHY_CORE_EXPE4_TX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE5
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE5,0xff00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE5,0xff00,8)
#define BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_BITS               8
#define BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_100FX_SHIFT              8

/* BRPHY4_GPHY_CORE :: EXPE5 :: reserved0 [07:07] */
#define BRPHY4_GPHY_CORE_EXPE5_RESERVED0_MASK                      0x0080
#define BRPHY4_GPHY_CORE_EXPE5_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPE5_RESERVED0_BITS                      1
#define BRPHY4_GPHY_CORE_EXPE5_RESERVED0_SHIFT                     7

/* BRPHY4_GPHY_CORE :: EXPE5 :: TX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE5,0x7f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE5,0x7f,0)
#define BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_BITS               7
#define BRPHY4_GPHY_CORE_EXPE5_TX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE6
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_100 [15:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE6,0xff00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_100(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE6,0xff00,8)
#define BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_100_MASK                 0xff00
#define BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_100_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_100_BITS                 8
#define BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_100_SHIFT                8

/* BRPHY4_GPHY_CORE :: EXPE6 :: RX_PCS_DLY_1000 [07:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE6,0xff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_1000(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE6,0xff,0)
#define BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_MASK                0x00ff
#define BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_BITS                8
#define BRPHY4_GPHY_CORE_EXPE6_RX_PCS_DLY_1000_SHIFT               0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE7
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE7 :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_EXPE7_RESERVED0_MASK                      0xf000
#define BRPHY4_GPHY_CORE_EXPE7_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPE7_RESERVED0_BITS                      4
#define BRPHY4_GPHY_CORE_EXPE7_RESERVED0_SHIFT                     12

/* BRPHY4_GPHY_CORE :: EXPE7 :: RX_PCS_DLY_10 [11:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE7,0xfff,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE7_RX_PCS_DLY_10(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE7,0xfff,0)
#define BRPHY4_GPHY_CORE_EXPE7_RX_PCS_DLY_10_MASK                  0x0fff
#define BRPHY4_GPHY_CORE_EXPE7_RX_PCS_DLY_10_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXPE7_RX_PCS_DLY_10_BITS                  12
#define BRPHY4_GPHY_CORE_EXPE7_RX_PCS_DLY_10_SHIFT                 0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE8
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_100FX [15:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE8,0xff00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE8,0xff00,8)
#define BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_MASK               0xff00
#define BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_BITS               8
#define BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_100FX_SHIFT              8

/* BRPHY4_GPHY_CORE :: EXPE8 :: reserved0 [07:07] */
#define BRPHY4_GPHY_CORE_EXPE8_RESERVED0_MASK                      0x0080
#define BRPHY4_GPHY_CORE_EXPE8_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPE8_RESERVED0_BITS                      1
#define BRPHY4_GPHY_CORE_EXPE8_RESERVED0_SHIFT                     7

/* BRPHY4_GPHY_CORE :: EXPE8 :: RX_PCS_DLY_1000X [06:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE8,0x7f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE8,0x7f,0)
#define BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_MASK               0x007f
#define BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_BITS               7
#define BRPHY4_GPHY_CORE_EXPE8_RX_PCS_DLY_1000X_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE9
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE9 :: reserved0 [15:14] */
#define BRPHY4_GPHY_CORE_EXPE9_RESERVED0_MASK                      0xc000
#define BRPHY4_GPHY_CORE_EXPE9_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPE9_RESERVED0_BITS                      2
#define BRPHY4_GPHY_CORE_EXPE9_RESERVED0_SHIFT                     14

/* BRPHY4_GPHY_CORE :: EXPE9 :: P1588_TX_DLY_CYCLE [13:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE9,0x3f00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE9,0x3f00,8)
#define BRPHY4_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_MASK             0x3f00
#define BRPHY4_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_BITS             6
#define BRPHY4_GPHY_CORE_EXPE9_P1588_TX_DLY_CYCLE_SHIFT            8

/* BRPHY4_GPHY_CORE :: EXPE9 :: reserved1 [07:06] */
#define BRPHY4_GPHY_CORE_EXPE9_RESERVED1_MASK                      0x00c0
#define BRPHY4_GPHY_CORE_EXPE9_RESERVED1_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPE9_RESERVED1_BITS                      2
#define BRPHY4_GPHY_CORE_EXPE9_RESERVED1_SHIFT                     6

/* BRPHY4_GPHY_CORE :: EXPE9 :: P1588_RX_DLY_CYCLE [05:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE9,0x3f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE9,0x3f,0)
#define BRPHY4_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_MASK             0x003f
#define BRPHY4_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_BITS             6
#define BRPHY4_GPHY_CORE_EXPE9_P1588_RX_DLY_CYCLE_SHIFT            0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE0
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_10 [15:10] */
#define Wr_BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE0,0xfc00,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE0,0xfc00,10)
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_MASK              0xfc00
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_BITS              6
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_10_SHIFT             10

/* BRPHY4_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_100 [09:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE0,0x3e0,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE0,0x3e0,5)
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_MASK             0x03e0
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_BITS             5
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_100_SHIFT            5

/* BRPHY4_GPHY_CORE :: EXPE0 :: TX_PMA_PMD_DLY_1000 [04:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE0,0x1f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE0,0x1f,0)
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_MASK            0x001f
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_ALIGN           0
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_BITS            5
#define BRPHY4_GPHY_CORE_EXPE0_TX_PMA_PMD_DLY_1000_SHIFT           0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE1
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE1 :: reserved0 [15:12] */
#define BRPHY4_GPHY_CORE_EXPE1_RESERVED0_MASK                      0xf000
#define BRPHY4_GPHY_CORE_EXPE1_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPE1_RESERVED0_BITS                      4
#define BRPHY4_GPHY_CORE_EXPE1_RESERVED0_SHIFT                     12

/* BRPHY4_GPHY_CORE :: EXPE1 :: RX_PMA_PMD_DLY_FIBER [11:06] */
#define Wr_BRPHY4_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE1,0xfc0,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE1,0xfc0,6)
#define BRPHY4_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_MASK           0x0fc0
#define BRPHY4_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY4_GPHY_CORE_EXPE1_RX_PMA_PMD_DLY_FIBER_SHIFT          6

/* BRPHY4_GPHY_CORE :: EXPE1 :: TX_PMA_PMD_DLY_FIBER [05:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE1,0x3f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE1,0x3f,0)
#define BRPHY4_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_MASK           0x003f
#define BRPHY4_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_BITS           6
#define BRPHY4_GPHY_CORE_EXPE1_TX_PMA_PMD_DLY_FIBER_SHIFT          0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPE2
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPE2 :: reserved0 [15:14] */
#define BRPHY4_GPHY_CORE_EXPE2_RESERVED0_MASK                      0xc000
#define BRPHY4_GPHY_CORE_EXPE2_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPE2_RESERVED0_BITS                      2
#define BRPHY4_GPHY_CORE_EXPE2_RESERVED0_SHIFT                     14

/* BRPHY4_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_10 [13:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE2,0x3f80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE2,0x3f80,7)
#define BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_MASK              0x3f80
#define BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_BITS              7
#define BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_10_SHIFT             7

/* BRPHY4_GPHY_CORE :: EXPE2 :: RX_PMA_PMD_DLY_100_1000 [06:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPE2,0x7f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPE2,0x7f,0)
#define BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_MASK        0x007f
#define BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_ALIGN       0
#define BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_BITS        7
#define BRPHY4_GPHY_CORE_EXPE2_RX_PMA_PMD_DLY_100_1000_SHIFT       0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPEA
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPEA :: reserved0 [15:13] */
#define BRPHY4_GPHY_CORE_EXPEA_RESERVED0_MASK                      0xe000
#define BRPHY4_GPHY_CORE_EXPEA_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPEA_RESERVED0_BITS                      3
#define BRPHY4_GPHY_CORE_EXPEA_RESERVED0_SHIFT                     13

/* BRPHY4_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MAX_DLY_CYCLE [12:10] */
#define Wr_BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPEA,0x1c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPEA,0x1c00,10)
#define BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x1c00
#define BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      10

/* BRPHY4_GPHY_CORE :: EXPEA :: TX_PCS_ADJ_MIN_DLY_CYCLE [09:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPEA,0x380,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPEA,0x380,7)
#define BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x0380
#define BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY4_GPHY_CORE_EXPEA_TX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      7

/* BRPHY4_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MAX_DLY_CYCLE [06:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPEA,0x70,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPEA,0x70,4)
#define BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_MASK       0x0070
#define BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_ALIGN      0
#define BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_BITS       3
#define BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MAX_DLY_CYCLE_SHIFT      4

/* BRPHY4_GPHY_CORE :: EXPEA :: RX_PCS_ADJ_MIN_DLY_CYCLE [03:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPEA,0xe,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPEA,0xe,1)
#define BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_MASK       0x000e
#define BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_ALIGN      0
#define BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_BITS       3
#define BRPHY4_GPHY_CORE_EXPEA_RX_PCS_ADJ_MIN_DLY_CYCLE_SHIFT      1

/* BRPHY4_GPHY_CORE :: EXPEA :: FEATURE_802_3BF_ENABLE [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPEA,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPEA,0x1,0)
#define BRPHY4_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_MASK         0x0001
#define BRPHY4_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_ALIGN        0
#define BRPHY4_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_BITS         1
#define BRPHY4_GPHY_CORE_EXPEA_FEATURE_802_3BF_ENABLE_SHIFT        0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: LED_PRA_MODE
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: LED_PRA_MODE :: reserved0 [15:04] */
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_RESERVED0_MASK               0xfff0
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_RESERVED0_ALIGN              0
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_RESERVED0_BITS               12
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_RESERVED0_SHIFT              4

/* BRPHY4_GPHY_CORE :: LED_PRA_MODE :: SAT_MODE [03:03] */
#define Wr_BRPHY4_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_LED_PRA_MODE,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_LED_PRA_MODE_SAT_MODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_LED_PRA_MODE,0x8,3)
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_SAT_MODE_MASK                0x0008
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_SAT_MODE_ALIGN               0
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_SAT_MODE_BITS                1
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_SAT_MODE_SHIFT               3

/* BRPHY4_GPHY_CORE :: LED_PRA_MODE :: PRA_MODE [02:00] */
#define Wr_BRPHY4_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_LED_PRA_MODE,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_LED_PRA_MODE_PRA_MODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_LED_PRA_MODE,0x7,0)
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_PRA_MODE_MASK                0x0007
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_PRA_MODE_ALIGN               0
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_PRA_MODE_BITS                3
#define BRPHY4_GPHY_CORE_LED_PRA_MODE_PRA_MODE_SHIFT               0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: FIFO_CTL
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: FIFO_CTL :: SFT_RST [15:15] */
#define Wr_BRPHY4_GPHY_CORE_FIFO_CTL_SFT_RST(x) WriteRegBits16(BRPHY4_GPHY_CORE_FIFO_CTL,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_FIFO_CTL_SFT_RST(x) ReadRegBits16(BRPHY4_GPHY_CORE_FIFO_CTL,0x8000,15)
#define BRPHY4_GPHY_CORE_FIFO_CTL_SFT_RST_MASK                     0x8000
#define BRPHY4_GPHY_CORE_FIFO_CTL_SFT_RST_ALIGN                    0
#define BRPHY4_GPHY_CORE_FIFO_CTL_SFT_RST_BITS                     1
#define BRPHY4_GPHY_CORE_FIFO_CTL_SFT_RST_SHIFT                    15

/* BRPHY4_GPHY_CORE :: FIFO_CTL :: reserved0 [14:09] */
#define BRPHY4_GPHY_CORE_FIFO_CTL_RESERVED0_MASK                   0x7e00
#define BRPHY4_GPHY_CORE_FIFO_CTL_RESERVED0_ALIGN                  0
#define BRPHY4_GPHY_CORE_FIFO_CTL_RESERVED0_BITS                   6
#define BRPHY4_GPHY_CORE_FIFO_CTL_RESERVED0_SHIFT                  9

/* BRPHY4_GPHY_CORE :: FIFO_CTL :: WRBLOCK_MODE [08:08] */
#define Wr_BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) WriteRegBits16(BRPHY4_GPHY_CORE_FIFO_CTL,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE(x) ReadRegBits16(BRPHY4_GPHY_CORE_FIFO_CTL,0x100,8)
#define BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_MASK                0x0100
#define BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_ALIGN               0
#define BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_BITS                1
#define BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_MODE_SHIFT               8

/* BRPHY4_GPHY_CORE :: FIFO_CTL :: WRBLOCK_OVR [07:04] */
#define Wr_BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) WriteRegBits16(BRPHY4_GPHY_CORE_FIFO_CTL,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR(x) ReadRegBits16(BRPHY4_GPHY_CORE_FIFO_CTL,0xf0,4)
#define BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_MASK                 0x00f0
#define BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_ALIGN                0
#define BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_BITS                 4
#define BRPHY4_GPHY_CORE_FIFO_CTL_WRBLOCK_OVR_SHIFT                4

/* BRPHY4_GPHY_CORE :: FIFO_CTL :: MIN_IPG [03:00] */
#define Wr_BRPHY4_GPHY_CORE_FIFO_CTL_MIN_IPG(x) WriteRegBits16(BRPHY4_GPHY_CORE_FIFO_CTL,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_FIFO_CTL_MIN_IPG(x) ReadRegBits16(BRPHY4_GPHY_CORE_FIFO_CTL,0xf,0)
#define BRPHY4_GPHY_CORE_FIFO_CTL_MIN_IPG_MASK                     0x000f
#define BRPHY4_GPHY_CORE_FIFO_CTL_MIN_IPG_ALIGN                    0
#define BRPHY4_GPHY_CORE_FIFO_CTL_MIN_IPG_BITS                     4
#define BRPHY4_GPHY_CORE_FIFO_CTL_MIN_IPG_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPD8
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPD8 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_EXPD8_RESERVED0_MASK                      0x8000
#define BRPHY4_GPHY_CORE_EXPD8_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPD8_RESERVED0_BITS                      1
#define BRPHY4_GPHY_CORE_EXPD8_RESERVED0_SHIFT                     15

/* BRPHY4_GPHY_CORE :: EXPD8 :: FORCE_ACD_ON [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPD8_FORCE_ACD_ON(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x4000,14)
#define BRPHY4_GPHY_CORE_EXPD8_FORCE_ACD_ON_MASK                   0x4000
#define BRPHY4_GPHY_CORE_EXPD8_FORCE_ACD_ON_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPD8_FORCE_ACD_ON_BITS                   1
#define BRPHY4_GPHY_CORE_EXPD8_FORCE_ACD_ON_SHIFT                  14

/* BRPHY4_GPHY_CORE :: EXPD8 :: ACD_PHASE_SEL [13:11] */
#define Wr_BRPHY4_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x3800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXPD8_ACD_PHASE_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x3800,11)
#define BRPHY4_GPHY_CORE_EXPD8_ACD_PHASE_SEL_MASK                  0x3800
#define BRPHY4_GPHY_CORE_EXPD8_ACD_PHASE_SEL_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXPD8_ACD_PHASE_SEL_BITS                  3
#define BRPHY4_GPHY_CORE_EXPD8_ACD_PHASE_SEL_SHIFT                 11

/* BRPHY4_GPHY_CORE :: EXPD8 :: AGC_FSCALE [10:09] */
#define Wr_BRPHY4_GPHY_CORE_EXPD8_AGC_FSCALE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x600,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPD8_AGC_FSCALE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x600,9)
#define BRPHY4_GPHY_CORE_EXPD8_AGC_FSCALE_MASK                     0x0600
#define BRPHY4_GPHY_CORE_EXPD8_AGC_FSCALE_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPD8_AGC_FSCALE_BITS                     2
#define BRPHY4_GPHY_CORE_EXPD8_AGC_FSCALE_SHIFT                    9

/* BRPHY4_GPHY_CORE :: EXPD8 :: STOP_AGC_AFTER_LINK [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x100,8)
#define BRPHY4_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_MASK            0x0100
#define BRPHY4_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_ALIGN           0
#define BRPHY4_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_BITS            1
#define BRPHY4_GPHY_CORE_EXPD8_STOP_AGC_AFTER_LINK_SHIFT           8

/* BRPHY4_GPHY_CORE :: EXPD8 :: UPDATE_FROM_FFE_EN [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x80,7)
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_MASK             0x0080
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_BITS             1
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_FROM_FFE_EN_SHIFT            7

/* BRPHY4_GPHY_CORE :: EXPD8 :: UPDATE_AGC_WHEN_IDLE [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x40,6)
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_MASK           0x0040
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_BITS           1
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_AGC_WHEN_IDLE_SHIFT          6

/* BRPHY4_GPHY_CORE :: EXPD8 :: UPDATE_ENC_WHEN_IDLE [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x20,5)
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_MASK           0x0020
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_BITS           1
#define BRPHY4_GPHY_CORE_EXPD8_UPDATE_ENC_WHEN_IDLE_SHIFT          5

/* BRPHY4_GPHY_CORE :: EXPD8 :: FFE_DYN_THD [04:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPD8_FFE_DYN_THD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x1f,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPD8_FFE_DYN_THD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPD8,0x1f,0)
#define BRPHY4_GPHY_CORE_EXPD8_FFE_DYN_THD_MASK                    0x001f
#define BRPHY4_GPHY_CORE_EXPD8_FFE_DYN_THD_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPD8_FFE_DYN_THD_BITS                    5
#define BRPHY4_GPHY_CORE_EXPD8_FFE_DYN_THD_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPF0
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPF0 :: IBS_RX_SEND [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXPF0_IBS_RX_SEND(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF0_IBS_RX_SEND(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x8000,15)
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RX_SEND_MASK                    0x8000
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RX_SEND_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RX_SEND_BITS                    1
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RX_SEND_SHIFT                   15

/* BRPHY4_GPHY_CORE :: EXPF0 :: IBS_TX_EN [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPF0_IBS_TX_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF0_IBS_TX_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x4000,14)
#define BRPHY4_GPHY_CORE_EXPF0_IBS_TX_EN_MASK                      0x4000
#define BRPHY4_GPHY_CORE_EXPF0_IBS_TX_EN_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPF0_IBS_TX_EN_BITS                      1
#define BRPHY4_GPHY_CORE_EXPF0_IBS_TX_EN_SHIFT                     14

/* BRPHY4_GPHY_CORE :: EXPF0 :: IBS_RXCLK_OV_EN [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x2000,13)
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_MASK                0x2000
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_BITS                1
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_OV_EN_SHIFT               13

/* BRPHY4_GPHY_CORE :: EXPF0 :: IBS_RXCLK_SW_OV [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_MASK                0x1000
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_BITS                1
#define BRPHY4_GPHY_CORE_EXPF0_IBS_RXCLK_SW_OV_SHIFT               12

/* BRPHY4_GPHY_CORE :: EXPF0 :: reserved0 [11:05] */
#define BRPHY4_GPHY_CORE_EXPF0_RESERVED0_MASK                      0x0fe0
#define BRPHY4_GPHY_CORE_EXPF0_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPF0_RESERVED0_BITS                      7
#define BRPHY4_GPHY_CORE_EXPF0_RESERVED0_SHIFT                     5

/* BRPHY4_GPHY_CORE :: EXPF0 :: IBS_PWRDN [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x10,4)
#define BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_MASK                      0x0010
#define BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_BITS                      1
#define BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_SHIFT                     4

/* BRPHY4_GPHY_CORE :: EXPF0 :: IBS_PWRDN_SD [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_SD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x8,3)
#define BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_SD_MASK                   0x0008
#define BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_SD_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_SD_BITS                   1
#define BRPHY4_GPHY_CORE_EXPF0_IBS_PWRDN_SD_SHIFT                  3

/* BRPHY4_GPHY_CORE :: EXPF0 :: IBS_AUTO_PWRDN [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x4,2)
#define BRPHY4_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_MASK                 0x0004
#define BRPHY4_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_BITS                 1
#define BRPHY4_GPHY_CORE_EXPF0_IBS_AUTO_PWRDN_SHIFT                2

/* BRPHY4_GPHY_CORE :: EXPF0 :: IBS_EARLY_DAC_WAKE [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x2,1)
#define BRPHY4_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_MASK             0x0002
#define BRPHY4_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_BITS             1
#define BRPHY4_GPHY_CORE_EXPF0_IBS_EARLY_DAC_WAKE_SHIFT            1

/* BRPHY4_GPHY_CORE :: EXPF0 :: IBS_CK25_DIS [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF0_IBS_CK25_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF0,0x1,0)
#define BRPHY4_GPHY_CORE_EXPF0_IBS_CK25_DIS_MASK                   0x0001
#define BRPHY4_GPHY_CORE_EXPF0_IBS_CK25_DIS_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPF0_IBS_CK25_DIS_BITS                   1
#define BRPHY4_GPHY_CORE_EXPF0_IBS_CK25_DIS_SHIFT                  0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPF5
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_COPPER [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x8000,15)
#define BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_MASK           0x8000
#define BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_BITS           1
#define BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_COPPER_SHIFT          15

/* BRPHY4_GPHY_CORE :: EXPF5 :: BLK_TX_AT_CRC_FIBER [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x4000,14)
#define BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_MASK            0x4000
#define BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_ALIGN           0
#define BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_BITS            1
#define BRPHY4_GPHY_CORE_EXPF5_BLK_TX_AT_CRC_FIBER_SHIFT           14

/* BRPHY4_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_COPPER [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x2000,13)
#define BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_MASK           0x2000
#define BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_BITS           1
#define BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_COPPER_SHIFT          13

/* BRPHY4_GPHY_CORE :: EXPF5 :: BLK_RX_AT_CRC_FIBER [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_MASK            0x1000
#define BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_ALIGN           0
#define BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_BITS            1
#define BRPHY4_GPHY_CORE_EXPF5_BLK_RX_AT_CRC_FIBER_SHIFT           12

/* BRPHY4_GPHY_CORE :: EXPF5 :: RX_SOP_SEL [11:10] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0xc00,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0xc00,10)
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_MASK                     0x0c00
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_BITS                     2
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_SHIFT                    10

/* BRPHY4_GPHY_CORE :: EXPF5 :: RX_SOP_SEL_OV [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x200,9)
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_MASK                  0x0200
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_BITS                  1
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_SEL_OV_SHIFT                 9

/* BRPHY4_GPHY_CORE :: EXPF5 :: TX_SOP_10BT_ENABLE [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x100,8)
#define BRPHY4_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_MASK             0x0100
#define BRPHY4_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_BITS             1
#define BRPHY4_GPHY_CORE_EXPF5_TX_SOP_10BT_ENABLE_SHIFT            8

/* BRPHY4_GPHY_CORE :: EXPF5 :: RX_SOP_10BT_ENABLE [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x80,7)
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_MASK             0x0080
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_BITS             1
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_10BT_ENABLE_SHIFT            7

/* BRPHY4_GPHY_CORE :: EXPF5 :: TX_SOP_ERR_STATUS [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x40,6)
#define BRPHY4_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_MASK              0x0040
#define BRPHY4_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_BITS              1
#define BRPHY4_GPHY_CORE_EXPF5_TX_SOP_ERR_STATUS_SHIFT             6

/* BRPHY4_GPHY_CORE :: EXPF5 :: USE_TXEN_TX_SOP [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x20,5)
#define BRPHY4_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_MASK                0x0020
#define BRPHY4_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_BITS                1
#define BRPHY4_GPHY_CORE_EXPF5_USE_TXEN_TX_SOP_SHIFT               5

/* BRPHY4_GPHY_CORE :: EXPF5 :: RX_SOP_ERR_STATUS [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x10,4)
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_MASK              0x0010
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_BITS              1
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_ERR_STATUS_SHIFT             4

/* BRPHY4_GPHY_CORE :: EXPF5 :: RX_SOP_OPTION [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_RX_SOP_OPTION(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x8,3)
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_OPTION_MASK                  0x0008
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_OPTION_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_OPTION_BITS                  1
#define BRPHY4_GPHY_CORE_EXPF5_RX_SOP_OPTION_SHIFT                 3

/* BRPHY4_GPHY_CORE :: EXPF5 :: USE_RXDV_RX_SOP [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x4,2)
#define BRPHY4_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_MASK                0x0004
#define BRPHY4_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_BITS                1
#define BRPHY4_GPHY_CORE_EXPF5_USE_RXDV_RX_SOP_SHIFT               2

/* BRPHY4_GPHY_CORE :: EXPF5 :: RECOVERY_CLK_SEL [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x2,1)
#define BRPHY4_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_MASK               0x0002
#define BRPHY4_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_BITS               1
#define BRPHY4_GPHY_CORE_EXPF5_RECOVERY_CLK_SEL_SHIFT              1

/* BRPHY4_GPHY_CORE :: EXPF5 :: TIMESYNC_EN [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPF5_TIMESYNC_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF5_TIMESYNC_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF5,0x1,0)
#define BRPHY4_GPHY_CORE_EXPF5_TIMESYNC_EN_MASK                    0x0001
#define BRPHY4_GPHY_CORE_EXPF5_TIMESYNC_EN_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPF5_TIMESYNC_EN_BITS                    1
#define BRPHY4_GPHY_CORE_EXPF5_TIMESYNC_EN_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPF6
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPF6 :: reserved0 [15:15] */
#define BRPHY4_GPHY_CORE_EXPF6_RESERVED0_MASK                      0x8000
#define BRPHY4_GPHY_CORE_EXPF6_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPF6_RESERVED0_BITS                      1
#define BRPHY4_GPHY_CORE_EXPF6_RESERVED0_SHIFT                     15

/* BRPHY4_GPHY_CORE :: EXPF6 :: PWRDN_DLL [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPF6_PWRDN_DLL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF6,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF6_PWRDN_DLL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF6,0x4000,14)
#define BRPHY4_GPHY_CORE_EXPF6_PWRDN_DLL_MASK                      0x4000
#define BRPHY4_GPHY_CORE_EXPF6_PWRDN_DLL_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPF6_PWRDN_DLL_BITS                      1
#define BRPHY4_GPHY_CORE_EXPF6_PWRDN_DLL_SHIFT                     14

/* BRPHY4_GPHY_CORE :: EXPF6 :: PWRDNBT_DLL [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF6,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF6_PWRDNBT_DLL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF6,0x2000,13)
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNBT_DLL_MASK                    0x2000
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNBT_DLL_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNBT_DLL_BITS                    1
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNBT_DLL_SHIFT                   13

/* BRPHY4_GPHY_CORE :: EXPF6 :: COMMON_PWROFF [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPF6_COMMON_PWROFF(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF6,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF6_COMMON_PWROFF(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF6,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPF6_COMMON_PWROFF_MASK                  0x1000
#define BRPHY4_GPHY_CORE_EXPF6_COMMON_PWROFF_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXPF6_COMMON_PWROFF_BITS                  1
#define BRPHY4_GPHY_CORE_EXPF6_COMMON_PWROFF_SHIFT                 12

/* BRPHY4_GPHY_CORE :: EXPF6 :: PWRDN_SD [11:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPF6_PWRDN_SD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF6,0xf00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF6_PWRDN_SD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF6,0xf00,8)
#define BRPHY4_GPHY_CORE_EXPF6_PWRDN_SD_MASK                       0x0f00
#define BRPHY4_GPHY_CORE_EXPF6_PWRDN_SD_ALIGN                      0
#define BRPHY4_GPHY_CORE_EXPF6_PWRDN_SD_BITS                       4
#define BRPHY4_GPHY_CORE_EXPF6_PWRDN_SD_SHIFT                      8

/* BRPHY4_GPHY_CORE :: EXPF6 :: PWRDNRX [07:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPF6_PWRDNRX(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF6,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF6_PWRDNRX(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF6,0xf0,4)
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNRX_MASK                        0x00f0
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNRX_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNRX_BITS                        4
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNRX_SHIFT                       4

/* BRPHY4_GPHY_CORE :: EXPF6 :: PWRDNTX [03:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPF6_PWRDNTX(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF6,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF6_PWRDNTX(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF6,0xf,0)
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNTX_MASK                        0x000f
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNTX_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNTX_BITS                        4
#define BRPHY4_GPHY_CORE_EXPF6_PWRDNTX_SHIFT                       0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPF7
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPF7 :: reserved0 [15:14] */
#define BRPHY4_GPHY_CORE_EXPF7_RESERVED0_MASK                      0xc000
#define BRPHY4_GPHY_CORE_EXPF7_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPF7_RESERVED0_BITS                      2
#define BRPHY4_GPHY_CORE_EXPF7_RESERVED0_SHIFT                     14

/* BRPHY4_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_DPWR [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x2000,13)
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_MASK              0x2000
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_BITS              1
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_DPWR_SHIFT             13

/* BRPHY4_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_APWR [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_MASK              0x1000
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_BITS              1
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_APWR_SHIFT             12

/* BRPHY4_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_DPWR [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x800,11)
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_MASK              0x0800
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_BITS              1
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_DPWR_SHIFT             11

/* BRPHY4_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_APWR [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x400,10)
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_MASK              0x0400
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_BITS              1
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_APWR_SHIFT             10

/* BRPHY4_GPHY_CORE :: EXPF7 :: R0PWRDN_DPWR [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_DPWR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x200,9)
#define BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_DPWR_MASK                   0x0200
#define BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_DPWR_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_DPWR_BITS                   1
#define BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_DPWR_SHIFT                  9

/* BRPHY4_GPHY_CORE :: EXPF7 :: R0PWRDN_APWR [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_APWR(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x100,8)
#define BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_APWR_MASK                   0x0100
#define BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_APWR_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_APWR_BITS                   1
#define BRPHY4_GPHY_CORE_EXPF7_R0PWRDN_APWR_SHIFT                  8

/* BRPHY4_GPHY_CORE :: EXPF7 :: AUTO_PWRDN_DLL [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x80,7)
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_MASK                 0x0080
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_BITS                 1
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDN_DLL_SHIFT                7

/* BRPHY4_GPHY_CORE :: EXPF7 :: PWRDN_DPWR_EARLY_INT [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x40,6)
#define BRPHY4_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_MASK           0x0040
#define BRPHY4_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_BITS           1
#define BRPHY4_GPHY_CORE_EXPF7_PWRDN_DPWR_EARLY_INT_SHIFT          6

/* BRPHY4_GPHY_CORE :: EXPF7 :: REAL_ENERGY [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_REAL_ENERGY(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_REAL_ENERGY(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x20,5)
#define BRPHY4_GPHY_CORE_EXPF7_REAL_ENERGY_MASK                    0x0020
#define BRPHY4_GPHY_CORE_EXPF7_REAL_ENERGY_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPF7_REAL_ENERGY_BITS                    1
#define BRPHY4_GPHY_CORE_EXPF7_REAL_ENERGY_SHIFT                   5

/* BRPHY4_GPHY_CORE :: EXPF7 :: AUTO_PWRDNRX_RAW [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x10,4)
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_MASK               0x0010
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_BITS               1
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNRX_RAW_SHIFT              4

/* BRPHY4_GPHY_CORE :: EXPF7 :: AUTO_PWRDNTX_RAW [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x8,3)
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_MASK               0x0008
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_BITS               1
#define BRPHY4_GPHY_CORE_EXPF7_AUTO_PWRDNTX_RAW_SHIFT              3

/* BRPHY4_GPHY_CORE :: EXPF7 :: CUR_STATE [02:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPF7_CUR_STATE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x7,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF7_CUR_STATE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF7,0x7,0)
#define BRPHY4_GPHY_CORE_EXPF7_CUR_STATE_MASK                      0x0007
#define BRPHY4_GPHY_CORE_EXPF7_CUR_STATE_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPF7_CUR_STATE_BITS                      3
#define BRPHY4_GPHY_CORE_EXPF7_CUR_STATE_SHIFT                     0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPF8
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPF8 :: TRIM_DAC_FROM_FUSE [15:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF8,0xf000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF8,0xf000,12)
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_MASK             0xf000
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_BITS             4
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_FROM_FUSE_SHIFT            12

/* BRPHY4_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_FROM_FUSE [11:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF8,0xf00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF8,0xf00,8)
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_MASK          0x0f00
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_ALIGN         0
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_BITS          4
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_FROM_FUSE_SHIFT         8

/* BRPHY4_GPHY_CORE :: EXPF8 :: TRIM_DAC_TO_BIAS_BLOCK [07:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF8,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF8,0xf0,4)
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_MASK         0x00f0
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_ALIGN        0
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_BITS         4
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_DAC_TO_BIAS_BLOCK_SHIFT        4

/* BRPHY4_GPHY_CORE :: EXPF8 :: TRIM_HYBRID_TO_BIAS_BLOCK [03:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF8,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF8,0xf,0)
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_MASK      0x000f
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_ALIGN     0
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_BITS      4
#define BRPHY4_GPHY_CORE_EXPF8_TRIM_HYBRID_TO_BIAS_BLOCK_SHIFT     0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPF9
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPF9 :: EXT_CTL [15:11] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_EXT_CTL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0xf800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_EXT_CTL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0xf800,11)
#define BRPHY4_GPHY_CORE_EXPF9_EXT_CTL_MASK                        0xf800
#define BRPHY4_GPHY_CORE_EXPF9_EXT_CTL_ALIGN                       0
#define BRPHY4_GPHY_CORE_EXPF9_EXT_CTL_BITS                        5
#define BRPHY4_GPHY_CORE_EXPF9_EXT_CTL_SHIFT                       11

/* BRPHY4_GPHY_CORE :: EXPF9 :: BT_NIBBLE_VAL [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_BT_NIBBLE_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x400,10)
#define BRPHY4_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_MASK                  0x0400
#define BRPHY4_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_BITS                  1
#define BRPHY4_GPHY_CORE_EXPF9_BT_NIBBLE_VAL_SHIFT                 10

/* BRPHY4_GPHY_CORE :: EXPF9 :: BT_DRIB_RMV [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_BT_DRIB_RMV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x200,9)
#define BRPHY4_GPHY_CORE_EXPF9_BT_DRIB_RMV_MASK                    0x0200
#define BRPHY4_GPHY_CORE_EXPF9_BT_DRIB_RMV_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPF9_BT_DRIB_RMV_BITS                    1
#define BRPHY4_GPHY_CORE_EXPF9_BT_DRIB_RMV_SHIFT                   9

/* BRPHY4_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_MDIX_EN [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x100,8)
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_MASK          0x0100
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_ALIGN         0
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_BITS          1
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_MDIX_EN_SHIFT         8

/* BRPHY4_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SEED_EN [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x80,7)
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_MASK          0x0080
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_ALIGN         0
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_BITS          1
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SEED_EN_SHIFT         7

/* BRPHY4_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_EN [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x40,6)
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_MASK               0x0040
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_BITS               1
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_EN_SHIFT              6

/* BRPHY4_GPHY_CORE :: EXPF9 :: CORE_RING_OSC_SIG [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x20,5)
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_MASK              0x0020
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_BITS              1
#define BRPHY4_GPHY_CORE_EXPF9_CORE_RING_OSC_SIG_SHIFT             5

/* BRPHY4_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_VAL [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x10,4)
#define BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_MASK          0x0010
#define BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_ALIGN         0
#define BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_BITS          1
#define BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_VAL_SHIFT         4

/* BRPHY4_GPHY_CORE :: EXPF9 :: HALFOUT_HYBRID_OV_EN [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x8,3)
#define BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_MASK           0x0008
#define BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_BITS           1
#define BRPHY4_GPHY_CORE_EXPF9_HALFOUT_HYBRID_OV_EN_SHIFT          3

/* BRPHY4_GPHY_CORE :: EXPF9 :: ABIST_INF_CONV [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_ABIST_INF_CONV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x4,2)
#define BRPHY4_GPHY_CORE_EXPF9_ABIST_INF_CONV_MASK                 0x0004
#define BRPHY4_GPHY_CORE_EXPF9_ABIST_INF_CONV_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPF9_ABIST_INF_CONV_BITS                 1
#define BRPHY4_GPHY_CORE_EXPF9_ABIST_INF_CONV_SHIFT                2

/* BRPHY4_GPHY_CORE :: EXPF9 :: GIGA_ONLY_HALFOUT [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x2,1)
#define BRPHY4_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_MASK              0x0002
#define BRPHY4_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_BITS              1
#define BRPHY4_GPHY_CORE_EXPF9_GIGA_ONLY_HALFOUT_SHIFT             1

/* BRPHY4_GPHY_CORE :: EXPF9 :: SPARE_REG0 [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPF9_SPARE_REG0(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPF9_SPARE_REG0(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPF9,0x1,0)
#define BRPHY4_GPHY_CORE_EXPF9_SPARE_REG0_MASK                     0x0001
#define BRPHY4_GPHY_CORE_EXPF9_SPARE_REG0_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPF9_SPARE_REG0_BITS                     1
#define BRPHY4_GPHY_CORE_EXPF9_SPARE_REG0_SHIFT                    0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPFA
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPFA :: reserved0 [15:04] */
#define BRPHY4_GPHY_CORE_EXPFA_RESERVED0_MASK                      0xfff0
#define BRPHY4_GPHY_CORE_EXPFA_RESERVED0_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPFA_RESERVED0_BITS                      12
#define BRPHY4_GPHY_CORE_EXPFA_RESERVED0_SHIFT                     4

/* BRPHY4_GPHY_CORE :: EXPFA :: HIDDEN_REV_NUM [03:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFA,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFA_HIDDEN_REV_NUM(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFA,0xf,0)
#define BRPHY4_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_MASK                 0x000f
#define BRPHY4_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_BITS                 4
#define BRPHY4_GPHY_CORE_EXPFA_HIDDEN_REV_NUM_SHIFT                0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPFB
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPFB :: TEST_IDDQCLKBIAS [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x8000,15)
#define BRPHY4_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_MASK               0x8000
#define BRPHY4_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_BITS               1
#define BRPHY4_GPHY_CORE_EXPFB_TEST_IDDQCLKBIAS_SHIFT              15

/* BRPHY4_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x4000,14)
#define BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_MASK                 0x4000
#define BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_BITS                 1
#define BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_SHIFT                14

/* BRPHY4_GPHY_CORE :: EXPFB :: IDDQCLKBIAS_OV_VAL [13:10] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x3c00,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x3c00,10)
#define BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_MASK             0x3c00
#define BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_BITS             4
#define BRPHY4_GPHY_CORE_EXPFB_IDDQCLKBIAS_OV_VAL_SHIFT            10

/* BRPHY4_GPHY_CORE :: EXPFB :: TDR_SLAVE_DFE_CONV_VAL [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x200,9)
#define BRPHY4_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_MASK         0x0200
#define BRPHY4_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_ALIGN        0
#define BRPHY4_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_BITS         1
#define BRPHY4_GPHY_CORE_EXPFB_TDR_SLAVE_DFE_CONV_VAL_SHIFT        9

/* BRPHY4_GPHY_CORE :: EXPFB :: FEXT_INPUTS_OV [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_FEXT_INPUTS_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x100,8)
#define BRPHY4_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_MASK                 0x0100
#define BRPHY4_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_BITS                 1
#define BRPHY4_GPHY_CORE_EXPFB_FEXT_INPUTS_OV_SHIFT                8

/* BRPHY4_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_OV [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x80,7)
#define BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_MASK               0x0080
#define BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_BITS               1
#define BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_OV_SHIFT              7

/* BRPHY4_GPHY_CORE :: EXPFB :: RX_LP_TIMEOUT_VAL [06:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x60,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x60,5)
#define BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_MASK              0x0060
#define BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_BITS              2
#define BRPHY4_GPHY_CORE_EXPFB_RX_LP_TIMEOUT_VAL_SHIFT             5

/* BRPHY4_GPHY_CORE :: EXPFB :: LINK_DET_OV [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_LINK_DET_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_LINK_DET_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x10,4)
#define BRPHY4_GPHY_CORE_EXPFB_LINK_DET_OV_MASK                    0x0010
#define BRPHY4_GPHY_CORE_EXPFB_LINK_DET_OV_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPFB_LINK_DET_OV_BITS                    1
#define BRPHY4_GPHY_CORE_EXPFB_LINK_DET_OV_SHIFT                   4

/* BRPHY4_GPHY_CORE :: EXPFB :: LINK_DET_VAL [03:02] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_LINK_DET_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0xc,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_LINK_DET_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0xc,2)
#define BRPHY4_GPHY_CORE_EXPFB_LINK_DET_VAL_MASK                   0x000c
#define BRPHY4_GPHY_CORE_EXPFB_LINK_DET_VAL_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPFB_LINK_DET_VAL_BITS                   2
#define BRPHY4_GPHY_CORE_EXPFB_LINK_DET_VAL_SHIFT                  2

/* BRPHY4_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_OV [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x2,1)
#define BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_MASK               0x0002
#define BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_BITS               1
#define BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_OV_SHIFT              1

/* BRPHY4_GPHY_CORE :: EXPFB :: SLAVE_CMD_DET_VAL [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFB,0x1,0)
#define BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_MASK              0x0001
#define BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_BITS              1
#define BRPHY4_GPHY_CORE_EXPFB_SLAVE_CMD_DET_VAL_SHIFT             0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPFC
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPFC :: PASSIVE_TERM_OV [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_PASSIVE_TERM_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x8000,15)
#define BRPHY4_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_MASK                0x8000
#define BRPHY4_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_BITS                1
#define BRPHY4_GPHY_CORE_EXPFC_PASSIVE_TERM_OV_SHIFT               15

/* BRPHY4_GPHY_CORE :: EXPFC :: APD_CLKOFF_OV [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_APD_CLKOFF_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x4000,14)
#define BRPHY4_GPHY_CORE_EXPFC_APD_CLKOFF_OV_MASK                  0x4000
#define BRPHY4_GPHY_CORE_EXPFC_APD_CLKOFF_OV_ALIGN                 0
#define BRPHY4_GPHY_CORE_EXPFC_APD_CLKOFF_OV_BITS                  1
#define BRPHY4_GPHY_CORE_EXPFC_APD_CLKOFF_OV_SHIFT                 14

/* BRPHY4_GPHY_CORE :: EXPFC :: TDR_TSD_PTE_OV_VAL_CHD [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x2000,13)
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_MASK         0x2000
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_ALIGN        0
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_BITS         1
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSD_PTE_OV_VAL_CHD_SHIFT        13

/* BRPHY4_GPHY_CORE :: EXPFC :: TDR_TSC_PTE_OV_VAL_CHC [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_MASK         0x1000
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_ALIGN        0
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_BITS         1
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSC_PTE_OV_VAL_CHC_SHIFT        12

/* BRPHY4_GPHY_CORE :: EXPFC :: TDR_TSB_PTE_OV_VAL_CHB [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x800,11)
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_MASK         0x0800
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_ALIGN        0
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_BITS         1
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSB_PTE_OV_VAL_CHB_SHIFT        11

/* BRPHY4_GPHY_CORE :: EXPFC :: TDR_TSA_PTE_OV_VAL_CHA [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x400,10)
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_MASK         0x0400
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_ALIGN        0
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_BITS         1
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TSA_PTE_OV_VAL_CHA_SHIFT        10

/* BRPHY4_GPHY_CORE :: EXPFC :: TDR_TS_EN_OV [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_TDR_TS_EN_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x200,9)
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TS_EN_OV_MASK                   0x0200
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TS_EN_OV_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TS_EN_OV_BITS                   1
#define BRPHY4_GPHY_CORE_EXPFC_TDR_TS_EN_OV_SHIFT                  9

/* BRPHY4_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x100,8)
#define BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_MASK                   0x0100
#define BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_BITS                   1
#define BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_SHIFT                  8

/* BRPHY4_GPHY_CORE :: EXPFC :: BASET_DLL_CLK_OV_VAL [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x80,7)
#define BRPHY4_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_MASK           0x0080
#define BRPHY4_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_ALIGN          0
#define BRPHY4_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_BITS           1
#define BRPHY4_GPHY_CORE_EXPFC_BASET_DLL_CLK_OV_VAL_SHIFT          7

/* BRPHY4_GPHY_CORE :: EXPFC :: DLL_PWRDN_OV_VAL [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x40,6)
#define BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_MASK               0x0040
#define BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_BITS               1
#define BRPHY4_GPHY_CORE_EXPFC_DLL_PWRDN_OV_VAL_SHIFT              6

/* BRPHY4_GPHY_CORE :: EXPFC :: AUTONEG_1000T_CLK_GATING_DIS [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x20,5)
#define BRPHY4_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_MASK   0x0020
#define BRPHY4_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_ALIGN  0
#define BRPHY4_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_BITS   1
#define BRPHY4_GPHY_CORE_EXPFC_AUTONEG_1000T_CLK_GATING_DIS_SHIFT  5

/* BRPHY4_GPHY_CORE :: EXPFC :: AUTONEG_10BT_LP_DIS [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x10,4)
#define BRPHY4_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_MASK            0x0010
#define BRPHY4_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_ALIGN           0
#define BRPHY4_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_BITS            1
#define BRPHY4_GPHY_CORE_EXPFC_AUTONEG_10BT_LP_DIS_SHIFT           4

/* BRPHY4_GPHY_CORE :: EXPFC :: AUTO_PWRDN_CLK_OFF_OV_VAL [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x8,3)
#define BRPHY4_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_MASK      0x0008
#define BRPHY4_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_ALIGN     0
#define BRPHY4_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_BITS      1
#define BRPHY4_GPHY_CORE_EXPFC_AUTO_PWRDN_CLK_OFF_OV_VAL_SHIFT     3

/* BRPHY4_GPHY_CORE :: EXPFC :: LP1000_DIS [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_LP1000_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_LP1000_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x4,2)
#define BRPHY4_GPHY_CORE_EXPFC_LP1000_DIS_MASK                     0x0004
#define BRPHY4_GPHY_CORE_EXPFC_LP1000_DIS_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPFC_LP1000_DIS_BITS                     1
#define BRPHY4_GPHY_CORE_EXPFC_LP1000_DIS_SHIFT                    2

/* BRPHY4_GPHY_CORE :: EXPFC :: LP100_DIS [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_LP100_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_LP100_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x2,1)
#define BRPHY4_GPHY_CORE_EXPFC_LP100_DIS_MASK                      0x0002
#define BRPHY4_GPHY_CORE_EXPFC_LP100_DIS_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPFC_LP100_DIS_BITS                      1
#define BRPHY4_GPHY_CORE_EXPFC_LP100_DIS_SHIFT                     1

/* BRPHY4_GPHY_CORE :: EXPFC :: LP10_DIABLE [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPFC_LP10_DIABLE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFC_LP10_DIABLE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFC,0x1,0)
#define BRPHY4_GPHY_CORE_EXPFC_LP10_DIABLE_MASK                    0x0001
#define BRPHY4_GPHY_CORE_EXPFC_LP10_DIABLE_ALIGN                   0
#define BRPHY4_GPHY_CORE_EXPFC_LP10_DIABLE_BITS                    1
#define BRPHY4_GPHY_CORE_EXPFC_LP10_DIABLE_SHIFT                   0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPFD
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPFD :: SPARE_REG [15:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0xe000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0xe000,13)
#define BRPHY4_GPHY_CORE_EXPFD_SPARE_REG_MASK                      0xe000
#define BRPHY4_GPHY_CORE_EXPFD_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPFD_SPARE_REG_BITS                      3
#define BRPHY4_GPHY_CORE_EXPFD_SPARE_REG_SHIFT                     13

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x800,11)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x400,10)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x200,9)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_BITS               1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x100,8)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_BITS               1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x80,7)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x40,6)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x20,5)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x10,4)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x8,3)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x4,2)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x2,1)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_BITS                1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY4_GPHY_CORE :: EXPFD :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFD,0x1,0)
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_BITS               1
#define BRPHY4_GPHY_CORE_EXPFD_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPFE
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPFE :: SPARE_REG [15:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_SPARE_REG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0xc000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_SPARE_REG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0xc000,14)
#define BRPHY4_GPHY_CORE_EXPFE_SPARE_REG_MASK                      0xc000
#define BRPHY4_GPHY_CORE_EXPFE_SPARE_REG_ALIGN                     0
#define BRPHY4_GPHY_CORE_EXPFE_SPARE_REG_BITS                      2
#define BRPHY4_GPHY_CORE_EXPFE_SPARE_REG_SHIFT                     14

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_DFE_LPI_EN [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x2000,13)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_MASK              0x2000
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_BITS              1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_DFE_LPI_EN_SHIFT             13

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK_BCD [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_MASK         0x1000
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_ALIGN        0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_BITS         1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BCD_SHIFT        12

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GTXCLK [11:11] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x800,11,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x800,11)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_MASK            0x0800
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_ALIGN           0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_BITS            1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GTXCLK_SHIFT           11

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_1000T_GPCS_TXCLKG [10:10] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x400,10,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x400,10)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_MASK       0x0400
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_ALIGN      0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_BITS       1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_GPCS_TXCLKG_SHIFT      10

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_1000T_ENC [09:09] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x200,9,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x200,9)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_MASK               0x0200
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_BITS               1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_ENC_SHIFT              9

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFE [08:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x100,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x100,8)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_MASK               0x0100
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_BITS               1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFE_SHIFT              8

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_1000T_DFSE [07:07] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x80,7,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x80,7)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_MASK              0x0080
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_ALIGN             0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_BITS              1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_DFSE_SHIFT             7

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_1000T_RXCLK [06:06] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x40,6,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x40,6)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_MASK             0x0040
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_BITS             1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_1000T_RXCLK_SHIFT            6

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_100TX_TXCLK [05:05] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x20,5,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x20,5)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_MASK             0x0020
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_BITS             1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_TXCLK_SHIFT            5

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_100TX_RXCLK [04:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x10,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x10,4)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_MASK             0x0010
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_BITS             1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_RXCLK_SHIFT            4

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_100TX_CLK25 [03:03] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x8,3,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x8,3)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_MASK             0x0008
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_ALIGN            0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_BITS             1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_100TX_CLK25_SHIFT            3

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_10T_TXCLK [02:02] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x4,2,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x4,2)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_MASK               0x0004
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_BITS               1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TXCLK_SHIFT              2

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_10T_CK20 [01:01] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x2,1,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_CK20(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x2,1)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_MASK                0x0002
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_ALIGN               0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_BITS                1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_CK20_SHIFT               1

/* BRPHY4_GPHY_CORE :: EXPFE :: CLKOFF_10T_TCK20 [00:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x1,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFE,0x1,0)
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_MASK               0x0001
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_ALIGN              0
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_BITS               1
#define BRPHY4_GPHY_CORE_EXPFE_CLKOFF_10T_TCK20_SHIFT              0


/****************************************************************************
 * BRPHY4_GPHY_CORE :: EXPFF
 ***************************************************************************/
/* BRPHY4_GPHY_CORE :: EXPFF :: PWRDN_SD_DIS [15:15] */
#define Wr_BRPHY4_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFF,0x8000,15,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFF_PWRDN_SD_DIS(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFF,0x8000,15)
#define BRPHY4_GPHY_CORE_EXPFF_PWRDN_SD_DIS_MASK                   0x8000
#define BRPHY4_GPHY_CORE_EXPFF_PWRDN_SD_DIS_ALIGN                  0
#define BRPHY4_GPHY_CORE_EXPFF_PWRDN_SD_DIS_BITS                   1
#define BRPHY4_GPHY_CORE_EXPFF_PWRDN_SD_DIS_SHIFT                  15

/* BRPHY4_GPHY_CORE :: EXPFF :: PWRDNSD_OV [14:14] */
#define Wr_BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFF,0x4000,14,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFF,0x4000,14)
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_MASK                     0x4000
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_BITS                     1
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_SHIFT                    14

/* BRPHY4_GPHY_CORE :: EXPFF :: PWRDNTX_OV [13:13] */
#define Wr_BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFF,0x2000,13,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFF,0x2000,13)
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_MASK                     0x2000
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_BITS                     1
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_SHIFT                    13

/* BRPHY4_GPHY_CORE :: EXPFF :: PWRDNRX_OV [12:12] */
#define Wr_BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFF,0x1000,12,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFF,0x1000,12)
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_MASK                     0x1000
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_ALIGN                    0
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_BITS                     1
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_SHIFT                    12

/* BRPHY4_GPHY_CORE :: EXPFF :: PWRDNSD_OV_VAL [11:08] */
#define Wr_BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFF,0xf00,8,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFF,0xf00,8)
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_MASK                 0x0f00
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_BITS                 4
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNSD_OV_VAL_SHIFT                8

/* BRPHY4_GPHY_CORE :: EXPFF :: PWRDNTX_OV_VAL [07:04] */
#define Wr_BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFF,0xf0,4,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFF,0xf0,4)
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_MASK                 0x00f0
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_BITS                 4
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNTX_OV_VAL_SHIFT                4

/* BRPHY4_GPHY_CORE :: EXPFF :: PWRDNRX_OV_VAL [03:00] */
#define Wr_BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) WriteRegBits16(BRPHY4_GPHY_CORE_EXPFF,0xf,0,x)
#define Rd_BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL(x) ReadRegBits16(BRPHY4_GPHY_CORE_EXPFF,0xf,0)
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_MASK                 0x000f
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_ALIGN                0
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_BITS                 4
#define BRPHY4_GPHY_CORE_EXPFF_PWRDNRX_OV_VAL_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_DSP_TAP
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP0_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP0_C0 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x8000,15)
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY4_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x4000,14)
#define BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY4_DSP_TAP :: TAP0_C0 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x2000,13)
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY4_DSP_TAP :: TAP0_C0 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x1000,12)
#define BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY4_DSP_TAP_TAP0_C0_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY4_DSP_TAP :: TAP0_C0 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x800,11)
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_BITS                1
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY4_DSP_TAP :: TAP0_C0 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x700,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C0_BR_PGA_GAIN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x700,8)
#define BRPHY4_DSP_TAP_TAP0_C0_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY4_DSP_TAP_TAP0_C0_BR_PGA_GAIN_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP0_C0_BR_PGA_GAIN_BITS                    3
#define BRPHY4_DSP_TAP_TAP0_C0_BR_PGA_GAIN_SHIFT                   8

/* BRPHY4_DSP_TAP :: TAP0_C0 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x80,7)
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_OV_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_OV_BITS                    1
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_OV_SHIFT                   7

/* BRPHY4_DSP_TAP :: TAP0_C0 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x7f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C0,0x7f,0)
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_BITS                 7
#define BRPHY4_DSP_TAP_TAP0_C0_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP0_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP0_C1 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x8000,15)
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY4_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x4000,14)
#define BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY4_DSP_TAP :: TAP0_C1 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x2000,13)
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY4_DSP_TAP :: TAP0_C1 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x1000,12)
#define BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY4_DSP_TAP_TAP0_C1_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY4_DSP_TAP :: TAP0_C1 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x800,11)
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_BITS                1
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY4_DSP_TAP :: TAP0_C1 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x700,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C1_BR_PGA_GAIN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x700,8)
#define BRPHY4_DSP_TAP_TAP0_C1_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY4_DSP_TAP_TAP0_C1_BR_PGA_GAIN_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP0_C1_BR_PGA_GAIN_BITS                    3
#define BRPHY4_DSP_TAP_TAP0_C1_BR_PGA_GAIN_SHIFT                   8

/* BRPHY4_DSP_TAP :: TAP0_C1 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x80,7)
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_OV_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_OV_BITS                    1
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_OV_SHIFT                   7

/* BRPHY4_DSP_TAP :: TAP0_C1 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x7f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C1,0x7f,0)
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_BITS                 7
#define BRPHY4_DSP_TAP_TAP0_C1_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP0_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP0_C2 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x8000,15)
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY4_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x4000,14)
#define BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY4_DSP_TAP :: TAP0_C2 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x2000,13)
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY4_DSP_TAP :: TAP0_C2 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x1000,12)
#define BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY4_DSP_TAP_TAP0_C2_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY4_DSP_TAP :: TAP0_C2 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x800,11)
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_BITS                1
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY4_DSP_TAP :: TAP0_C2 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x700,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C2_BR_PGA_GAIN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x700,8)
#define BRPHY4_DSP_TAP_TAP0_C2_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY4_DSP_TAP_TAP0_C2_BR_PGA_GAIN_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP0_C2_BR_PGA_GAIN_BITS                    3
#define BRPHY4_DSP_TAP_TAP0_C2_BR_PGA_GAIN_SHIFT                   8

/* BRPHY4_DSP_TAP :: TAP0_C2 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x80,7)
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_OV_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_OV_BITS                    1
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_OV_SHIFT                   7

/* BRPHY4_DSP_TAP :: TAP0_C2 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x7f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C2,0x7f,0)
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_BITS                 7
#define BRPHY4_DSP_TAP_TAP0_C2_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP0_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP0_C3 :: AGC_FFE_JAM_DISABLE [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x8000,15)
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_MASK            0x8000
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_BITS            1
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_FFE_JAM_DISABLE_SHIFT           15

/* BRPHY4_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_COARSE_FREEZE [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x4000,14)
#define BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_MASK       0x4000
#define BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_ALIGN      0
#define BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_BITS       1
#define BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_COARSE_FREEZE_SHIFT      14

/* BRPHY4_DSP_TAP :: TAP0_C3 :: AGC_COARSE_FREEZE [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x2000,13)
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_MASK              0x2000
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_COARSE_FREEZE_SHIFT             13

/* BRPHY4_DSP_TAP :: TAP0_C3 :: ENABLE_AGC_FINE_FREEZE [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x1000,12)
#define BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_MASK         0x1000
#define BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_ALIGN        0
#define BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_BITS         1
#define BRPHY4_DSP_TAP_TAP0_C3_ENABLE_AGC_FINE_FREEZE_SHIFT        12

/* BRPHY4_DSP_TAP :: TAP0_C3 :: AGC_FINE_FREEZE [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x800,11)
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_MASK                0x0800
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_ALIGN               0
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_BITS                1
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_FINE_FREEZE_SHIFT               11

/* BRPHY4_DSP_TAP :: TAP0_C3 :: BR_PGA_GAIN [10:08] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x700,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C3_BR_PGA_GAIN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x700,8)
#define BRPHY4_DSP_TAP_TAP0_C3_BR_PGA_GAIN_MASK                    0x0700
#define BRPHY4_DSP_TAP_TAP0_C3_BR_PGA_GAIN_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP0_C3_BR_PGA_GAIN_BITS                    3
#define BRPHY4_DSP_TAP_TAP0_C3_BR_PGA_GAIN_SHIFT                   8

/* BRPHY4_DSP_TAP :: TAP0_C3 :: AGC_GAIN_OV [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x80,7)
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_OV_MASK                    0x0080
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_OV_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_OV_BITS                    1
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_OV_SHIFT                   7

/* BRPHY4_DSP_TAP :: TAP0_C3 :: AGC_GAIN_VALUE [06:00] */
#define Wr_BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x7f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP0_C3,0x7f,0)
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_MASK                 0x007f
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_BITS                 7
#define BRPHY4_DSP_TAP_TAP0_C3_AGC_GAIN_VALUE_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP1 :: reserved0 [15:14] */
#define BRPHY4_DSP_TAP_TAP1_RESERVED0_MASK                         0xc000
#define BRPHY4_DSP_TAP_TAP1_RESERVED0_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP1_RESERVED0_BITS                         2
#define BRPHY4_DSP_TAP_TAP1_RESERVED0_SHIFT                        14

/* BRPHY4_DSP_TAP :: TAP1 :: DIG_GAIN_LMS_MODE [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP1,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP1,0x2000,13)
#define BRPHY4_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_MASK                 0x2000
#define BRPHY4_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_BITS                 1
#define BRPHY4_DSP_TAP_TAP1_DIG_GAIN_LMS_MODE_SHIFT                13

/* BRPHY4_DSP_TAP :: TAP1 :: IPRF_K_OV_EN [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP1,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP1,0x1000,12)
#define BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_EN_MASK                      0x1000
#define BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_EN_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_EN_BITS                      1
#define BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_EN_SHIFT                     12

/* BRPHY4_DSP_TAP :: TAP1 :: IPRF_K_OV_VALUE [11:07] */
#define Wr_BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP1,0xf80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_VALUE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP1,0xf80,7)
#define BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_VALUE_MASK                   0x0f80
#define BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_VALUE_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_VALUE_BITS                   5
#define BRPHY4_DSP_TAP_TAP1_IPRF_K_OV_VALUE_SHIFT                  7

/* BRPHY4_DSP_TAP :: TAP1 :: GBT_AGC_TARGET_LVL [06:04] */
#define Wr_BRPHY4_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP1,0x70,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP1,0x70,4)
#define BRPHY4_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_MASK                0x0070
#define BRPHY4_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_ALIGN               0
#define BRPHY4_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_BITS                3
#define BRPHY4_DSP_TAP_TAP1_GBT_AGC_TARGET_LVL_SHIFT               4

/* BRPHY4_DSP_TAP :: TAP1 :: TX_AGC_TARGET_LVL [03:00] */
#define Wr_BRPHY4_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP1,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP1_TX_AGC_TARGET_LVL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP1,0xf,0)
#define BRPHY4_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_MASK                 0x000f
#define BRPHY4_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_ALIGN                0
#define BRPHY4_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_BITS                 4
#define BRPHY4_DSP_TAP_TAP1_TX_AGC_TARGET_LVL_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP2_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP2_C0 :: MSE [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP2_C0_MSE(x) WriteReg16(BRPHY4_DSP_TAP_TAP2_C0,x)
#define Rd_BRPHY4_DSP_TAP_TAP2_C0_MSE(x) ReadReg16(BRPHY4_DSP_TAP_TAP2_C0)
#define BRPHY4_DSP_TAP_TAP2_C0_MSE_MASK                            0xffff
#define BRPHY4_DSP_TAP_TAP2_C0_MSE_ALIGN                           0
#define BRPHY4_DSP_TAP_TAP2_C0_MSE_BITS                            16
#define BRPHY4_DSP_TAP_TAP2_C0_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP2_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP2_C1 :: MSE [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP2_C1_MSE(x) WriteReg16(BRPHY4_DSP_TAP_TAP2_C1,x)
#define Rd_BRPHY4_DSP_TAP_TAP2_C1_MSE(x) ReadReg16(BRPHY4_DSP_TAP_TAP2_C1)
#define BRPHY4_DSP_TAP_TAP2_C1_MSE_MASK                            0xffff
#define BRPHY4_DSP_TAP_TAP2_C1_MSE_ALIGN                           0
#define BRPHY4_DSP_TAP_TAP2_C1_MSE_BITS                            16
#define BRPHY4_DSP_TAP_TAP2_C1_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP2_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP2_C2 :: MSE [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP2_C2_MSE(x) WriteReg16(BRPHY4_DSP_TAP_TAP2_C2,x)
#define Rd_BRPHY4_DSP_TAP_TAP2_C2_MSE(x) ReadReg16(BRPHY4_DSP_TAP_TAP2_C2)
#define BRPHY4_DSP_TAP_TAP2_C2_MSE_MASK                            0xffff
#define BRPHY4_DSP_TAP_TAP2_C2_MSE_ALIGN                           0
#define BRPHY4_DSP_TAP_TAP2_C2_MSE_BITS                            16
#define BRPHY4_DSP_TAP_TAP2_C2_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP2_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP2_C3 :: MSE [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP2_C3_MSE(x) WriteReg16(BRPHY4_DSP_TAP_TAP2_C3,x)
#define Rd_BRPHY4_DSP_TAP_TAP2_C3_MSE(x) ReadReg16(BRPHY4_DSP_TAP_TAP2_C3)
#define BRPHY4_DSP_TAP_TAP2_C3_MSE_MASK                            0xffff
#define BRPHY4_DSP_TAP_TAP2_C3_MSE_ALIGN                           0
#define BRPHY4_DSP_TAP_TAP2_C3_MSE_BITS                            16
#define BRPHY4_DSP_TAP_TAP2_C3_MSE_SHIFT                           0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP3_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP3_C0 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP3_C0_SOFT_DECISION(x) WriteReg16(BRPHY4_DSP_TAP_TAP3_C0,x)
#define Rd_BRPHY4_DSP_TAP_TAP3_C0_SOFT_DECISION(x) ReadReg16(BRPHY4_DSP_TAP_TAP3_C0)
#define BRPHY4_DSP_TAP_TAP3_C0_SOFT_DECISION_MASK                  0xffff
#define BRPHY4_DSP_TAP_TAP3_C0_SOFT_DECISION_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP3_C0_SOFT_DECISION_BITS                  16
#define BRPHY4_DSP_TAP_TAP3_C0_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP3_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP3_C1 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP3_C1_SOFT_DECISION(x) WriteReg16(BRPHY4_DSP_TAP_TAP3_C1,x)
#define Rd_BRPHY4_DSP_TAP_TAP3_C1_SOFT_DECISION(x) ReadReg16(BRPHY4_DSP_TAP_TAP3_C1)
#define BRPHY4_DSP_TAP_TAP3_C1_SOFT_DECISION_MASK                  0xffff
#define BRPHY4_DSP_TAP_TAP3_C1_SOFT_DECISION_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP3_C1_SOFT_DECISION_BITS                  16
#define BRPHY4_DSP_TAP_TAP3_C1_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP3_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP3_C2 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP3_C2_SOFT_DECISION(x) WriteReg16(BRPHY4_DSP_TAP_TAP3_C2,x)
#define Rd_BRPHY4_DSP_TAP_TAP3_C2_SOFT_DECISION(x) ReadReg16(BRPHY4_DSP_TAP_TAP3_C2)
#define BRPHY4_DSP_TAP_TAP3_C2_SOFT_DECISION_MASK                  0xffff
#define BRPHY4_DSP_TAP_TAP3_C2_SOFT_DECISION_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP3_C2_SOFT_DECISION_BITS                  16
#define BRPHY4_DSP_TAP_TAP3_C2_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP3_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP3_C3 :: SOFT_DECISION [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP3_C3_SOFT_DECISION(x) WriteReg16(BRPHY4_DSP_TAP_TAP3_C3,x)
#define Rd_BRPHY4_DSP_TAP_TAP3_C3_SOFT_DECISION(x) ReadReg16(BRPHY4_DSP_TAP_TAP3_C3)
#define BRPHY4_DSP_TAP_TAP3_C3_SOFT_DECISION_MASK                  0xffff
#define BRPHY4_DSP_TAP_TAP3_C3_SOFT_DECISION_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP3_C3_SOFT_DECISION_BITS                  16
#define BRPHY4_DSP_TAP_TAP3_C3_SOFT_DECISION_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP4_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP4_C0 :: reserved0 [15:15] */
#define BRPHY4_DSP_TAP_TAP4_C0_RESERVED0_MASK                      0x8000
#define BRPHY4_DSP_TAP_TAP4_C0_RESERVED0_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C0_RESERVED0_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C0_RESERVED0_SHIFT                     15

/* BRPHY4_DSP_TAP :: TAP4_C0 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x7000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C0_PAIR_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x7000,12)
#define BRPHY4_DSP_TAP_TAP4_C0_PAIR_OFFSET_MASK                    0x7000
#define BRPHY4_DSP_TAP_TAP4_C0_PAIR_OFFSET_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP4_C0_PAIR_OFFSET_BITS                    3
#define BRPHY4_DSP_TAP_TAP4_C0_PAIR_OFFSET_SHIFT                   12

/* BRPHY4_DSP_TAP :: TAP4_C0 :: GAMMA16 [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C0_GAMMA16(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C0_GAMMA16(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x800,11)
#define BRPHY4_DSP_TAP_TAP4_C0_GAMMA16_MASK                        0x0800
#define BRPHY4_DSP_TAP_TAP4_C0_GAMMA16_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP4_C0_GAMMA16_BITS                        1
#define BRPHY4_DSP_TAP_TAP4_C0_GAMMA16_SHIFT                       11

/* BRPHY4_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x400,10)
#define BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY4_DSP_TAP :: TAP4_C0 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x200,9)
#define BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY4_DSP_TAP_TAP4_C0_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY4_DSP_TAP :: TAP4_C0 :: INC_PHASE [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C0_INC_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C0_INC_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x100,8)
#define BRPHY4_DSP_TAP_TAP4_C0_INC_PHASE_MASK                      0x0100
#define BRPHY4_DSP_TAP_TAP4_C0_INC_PHASE_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C0_INC_PHASE_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C0_INC_PHASE_SHIFT                     8

/* BRPHY4_DSP_TAP :: TAP4_C0 :: DEC_PHASE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C0_DEC_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C0_DEC_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x80,7)
#define BRPHY4_DSP_TAP_TAP4_C0_DEC_PHASE_MASK                      0x0080
#define BRPHY4_DSP_TAP_TAP4_C0_DEC_PHASE_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C0_DEC_PHASE_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C0_DEC_PHASE_SHIFT                     7

/* BRPHY4_DSP_TAP :: TAP4_C0 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C0_PHASE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x40,6)
#define BRPHY4_DSP_TAP_TAP4_C0_PHASE_FREEZE_MASK                   0x0040
#define BRPHY4_DSP_TAP_TAP4_C0_PHASE_FREEZE_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP4_C0_PHASE_FREEZE_BITS                   1
#define BRPHY4_DSP_TAP_TAP4_C0_PHASE_FREEZE_SHIFT                  6

/* BRPHY4_DSP_TAP :: TAP4_C0 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C0_CURRENT_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C0,0x3f,0)
#define BRPHY4_DSP_TAP_TAP4_C0_CURRENT_PHASE_MASK                  0x003f
#define BRPHY4_DSP_TAP_TAP4_C0_CURRENT_PHASE_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP4_C0_CURRENT_PHASE_BITS                  6
#define BRPHY4_DSP_TAP_TAP4_C0_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP4_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP4_C1 :: reserved0 [15:15] */
#define BRPHY4_DSP_TAP_TAP4_C1_RESERVED0_MASK                      0x8000
#define BRPHY4_DSP_TAP_TAP4_C1_RESERVED0_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C1_RESERVED0_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C1_RESERVED0_SHIFT                     15

/* BRPHY4_DSP_TAP :: TAP4_C1 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x7000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C1_PAIR_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x7000,12)
#define BRPHY4_DSP_TAP_TAP4_C1_PAIR_OFFSET_MASK                    0x7000
#define BRPHY4_DSP_TAP_TAP4_C1_PAIR_OFFSET_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP4_C1_PAIR_OFFSET_BITS                    3
#define BRPHY4_DSP_TAP_TAP4_C1_PAIR_OFFSET_SHIFT                   12

/* BRPHY4_DSP_TAP :: TAP4_C1 :: GAMMA16 [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C1_GAMMA16(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C1_GAMMA16(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x800,11)
#define BRPHY4_DSP_TAP_TAP4_C1_GAMMA16_MASK                        0x0800
#define BRPHY4_DSP_TAP_TAP4_C1_GAMMA16_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP4_C1_GAMMA16_BITS                        1
#define BRPHY4_DSP_TAP_TAP4_C1_GAMMA16_SHIFT                       11

/* BRPHY4_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x400,10)
#define BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY4_DSP_TAP :: TAP4_C1 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x200,9)
#define BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY4_DSP_TAP_TAP4_C1_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY4_DSP_TAP :: TAP4_C1 :: INC_PHASE [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C1_INC_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C1_INC_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x100,8)
#define BRPHY4_DSP_TAP_TAP4_C1_INC_PHASE_MASK                      0x0100
#define BRPHY4_DSP_TAP_TAP4_C1_INC_PHASE_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C1_INC_PHASE_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C1_INC_PHASE_SHIFT                     8

/* BRPHY4_DSP_TAP :: TAP4_C1 :: DEC_PHASE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C1_DEC_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C1_DEC_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x80,7)
#define BRPHY4_DSP_TAP_TAP4_C1_DEC_PHASE_MASK                      0x0080
#define BRPHY4_DSP_TAP_TAP4_C1_DEC_PHASE_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C1_DEC_PHASE_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C1_DEC_PHASE_SHIFT                     7

/* BRPHY4_DSP_TAP :: TAP4_C1 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C1_PHASE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x40,6)
#define BRPHY4_DSP_TAP_TAP4_C1_PHASE_FREEZE_MASK                   0x0040
#define BRPHY4_DSP_TAP_TAP4_C1_PHASE_FREEZE_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP4_C1_PHASE_FREEZE_BITS                   1
#define BRPHY4_DSP_TAP_TAP4_C1_PHASE_FREEZE_SHIFT                  6

/* BRPHY4_DSP_TAP :: TAP4_C1 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C1_CURRENT_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C1,0x3f,0)
#define BRPHY4_DSP_TAP_TAP4_C1_CURRENT_PHASE_MASK                  0x003f
#define BRPHY4_DSP_TAP_TAP4_C1_CURRENT_PHASE_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP4_C1_CURRENT_PHASE_BITS                  6
#define BRPHY4_DSP_TAP_TAP4_C1_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP4_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP4_C2 :: reserved0 [15:15] */
#define BRPHY4_DSP_TAP_TAP4_C2_RESERVED0_MASK                      0x8000
#define BRPHY4_DSP_TAP_TAP4_C2_RESERVED0_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C2_RESERVED0_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C2_RESERVED0_SHIFT                     15

/* BRPHY4_DSP_TAP :: TAP4_C2 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x7000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C2_PAIR_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x7000,12)
#define BRPHY4_DSP_TAP_TAP4_C2_PAIR_OFFSET_MASK                    0x7000
#define BRPHY4_DSP_TAP_TAP4_C2_PAIR_OFFSET_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP4_C2_PAIR_OFFSET_BITS                    3
#define BRPHY4_DSP_TAP_TAP4_C2_PAIR_OFFSET_SHIFT                   12

/* BRPHY4_DSP_TAP :: TAP4_C2 :: GAMMA16 [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C2_GAMMA16(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C2_GAMMA16(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x800,11)
#define BRPHY4_DSP_TAP_TAP4_C2_GAMMA16_MASK                        0x0800
#define BRPHY4_DSP_TAP_TAP4_C2_GAMMA16_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP4_C2_GAMMA16_BITS                        1
#define BRPHY4_DSP_TAP_TAP4_C2_GAMMA16_SHIFT                       11

/* BRPHY4_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x400,10)
#define BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY4_DSP_TAP :: TAP4_C2 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x200,9)
#define BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY4_DSP_TAP_TAP4_C2_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY4_DSP_TAP :: TAP4_C2 :: INC_PHASE [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C2_INC_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C2_INC_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x100,8)
#define BRPHY4_DSP_TAP_TAP4_C2_INC_PHASE_MASK                      0x0100
#define BRPHY4_DSP_TAP_TAP4_C2_INC_PHASE_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C2_INC_PHASE_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C2_INC_PHASE_SHIFT                     8

/* BRPHY4_DSP_TAP :: TAP4_C2 :: DEC_PHASE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C2_DEC_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C2_DEC_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x80,7)
#define BRPHY4_DSP_TAP_TAP4_C2_DEC_PHASE_MASK                      0x0080
#define BRPHY4_DSP_TAP_TAP4_C2_DEC_PHASE_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C2_DEC_PHASE_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C2_DEC_PHASE_SHIFT                     7

/* BRPHY4_DSP_TAP :: TAP4_C2 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C2_PHASE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x40,6)
#define BRPHY4_DSP_TAP_TAP4_C2_PHASE_FREEZE_MASK                   0x0040
#define BRPHY4_DSP_TAP_TAP4_C2_PHASE_FREEZE_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP4_C2_PHASE_FREEZE_BITS                   1
#define BRPHY4_DSP_TAP_TAP4_C2_PHASE_FREEZE_SHIFT                  6

/* BRPHY4_DSP_TAP :: TAP4_C2 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C2_CURRENT_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C2,0x3f,0)
#define BRPHY4_DSP_TAP_TAP4_C2_CURRENT_PHASE_MASK                  0x003f
#define BRPHY4_DSP_TAP_TAP4_C2_CURRENT_PHASE_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP4_C2_CURRENT_PHASE_BITS                  6
#define BRPHY4_DSP_TAP_TAP4_C2_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP4_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP4_C3 :: reserved0 [15:15] */
#define BRPHY4_DSP_TAP_TAP4_C3_RESERVED0_MASK                      0x8000
#define BRPHY4_DSP_TAP_TAP4_C3_RESERVED0_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C3_RESERVED0_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C3_RESERVED0_SHIFT                     15

/* BRPHY4_DSP_TAP :: TAP4_C3 :: PAIR_OFFSET [14:12] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x7000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C3_PAIR_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x7000,12)
#define BRPHY4_DSP_TAP_TAP4_C3_PAIR_OFFSET_MASK                    0x7000
#define BRPHY4_DSP_TAP_TAP4_C3_PAIR_OFFSET_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP4_C3_PAIR_OFFSET_BITS                    3
#define BRPHY4_DSP_TAP_TAP4_C3_PAIR_OFFSET_SHIFT                   12

/* BRPHY4_DSP_TAP :: TAP4_C3 :: GAMMA16 [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C3_GAMMA16(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C3_GAMMA16(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x800,11)
#define BRPHY4_DSP_TAP_TAP4_C3_GAMMA16_MASK                        0x0800
#define BRPHY4_DSP_TAP_TAP4_C3_GAMMA16_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP4_C3_GAMMA16_BITS                        1
#define BRPHY4_DSP_TAP_TAP4_C3_GAMMA16_SHIFT                       11

/* BRPHY4_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x400,10)
#define BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_MASK           0x0400
#define BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_ALIGN          0
#define BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_BITS           1
#define BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_EN_SHIFT          10

/* BRPHY4_DSP_TAP :: TAP4_C3 :: CAGC_HIGH_GEAR_OV [09:09] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x200,9)
#define BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_MASK              0x0200
#define BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_ALIGN             0
#define BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_BITS              1
#define BRPHY4_DSP_TAP_TAP4_C3_CAGC_HIGH_GEAR_OV_SHIFT             9

/* BRPHY4_DSP_TAP :: TAP4_C3 :: INC_PHASE [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C3_INC_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C3_INC_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x100,8)
#define BRPHY4_DSP_TAP_TAP4_C3_INC_PHASE_MASK                      0x0100
#define BRPHY4_DSP_TAP_TAP4_C3_INC_PHASE_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C3_INC_PHASE_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C3_INC_PHASE_SHIFT                     8

/* BRPHY4_DSP_TAP :: TAP4_C3 :: DEC_PHASE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C3_DEC_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C3_DEC_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x80,7)
#define BRPHY4_DSP_TAP_TAP4_C3_DEC_PHASE_MASK                      0x0080
#define BRPHY4_DSP_TAP_TAP4_C3_DEC_PHASE_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP4_C3_DEC_PHASE_BITS                      1
#define BRPHY4_DSP_TAP_TAP4_C3_DEC_PHASE_SHIFT                     7

/* BRPHY4_DSP_TAP :: TAP4_C3 :: PHASE_FREEZE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C3_PHASE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x40,6)
#define BRPHY4_DSP_TAP_TAP4_C3_PHASE_FREEZE_MASK                   0x0040
#define BRPHY4_DSP_TAP_TAP4_C3_PHASE_FREEZE_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP4_C3_PHASE_FREEZE_BITS                   1
#define BRPHY4_DSP_TAP_TAP4_C3_PHASE_FREEZE_SHIFT                  6

/* BRPHY4_DSP_TAP :: TAP4_C3 :: CURRENT_PHASE [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP4_C3_CURRENT_PHASE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP4_C3,0x3f,0)
#define BRPHY4_DSP_TAP_TAP4_C3_CURRENT_PHASE_MASK                  0x003f
#define BRPHY4_DSP_TAP_TAP4_C3_CURRENT_PHASE_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP4_C3_CURRENT_PHASE_BITS                  6
#define BRPHY4_DSP_TAP_TAP4_C3_CURRENT_PHASE_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP5_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP5_C0 :: reserved0 [15:14] */
#define BRPHY4_DSP_TAP_TAP5_C0_RESERVED0_MASK                      0xc000
#define BRPHY4_DSP_TAP_TAP5_C0_RESERVED0_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP5_C0_RESERVED0_BITS                      2
#define BRPHY4_DSP_TAP_TAP5_C0_RESERVED0_SHIFT                     14

/* BRPHY4_DSP_TAP :: TAP5_C0 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_SLICE_ZERO(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_SLICE_ZERO(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x2000,13)
#define BRPHY4_DSP_TAP_TAP5_C0_SLICE_ZERO_MASK                     0x2000
#define BRPHY4_DSP_TAP_TAP5_C0_SLICE_ZERO_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP5_C0_SLICE_ZERO_BITS                     1
#define BRPHY4_DSP_TAP_TAP5_C0_SLICE_ZERO_SHIFT                    13

/* BRPHY4_DSP_TAP :: TAP5_C0 :: DISABLE_TX [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_DISABLE_TX(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_DISABLE_TX(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x1000,12)
#define BRPHY4_DSP_TAP_TAP5_C0_DISABLE_TX_MASK                     0x1000
#define BRPHY4_DSP_TAP_TAP5_C0_DISABLE_TX_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP5_C0_DISABLE_TX_BITS                     1
#define BRPHY4_DSP_TAP_TAP5_C0_DISABLE_TX_SHIFT                    12

/* BRPHY4_DSP_TAP :: TAP5_C0 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x800,11)
#define BRPHY4_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY4_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY4_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY4_DSP_TAP_TAP5_C0_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY4_DSP_TAP :: TAP5_C0 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x400,10)
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY4_DSP_TAP :: TAP5_C0 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x3c0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x3c0,6)
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_MASK                      0x03c0
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_BITS                      4
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SKEW_SHIFT                     6

/* BRPHY4_DSP_TAP :: TAP5_C0 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x20,5)
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_BITS              1
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY4_DSP_TAP :: TAP5_C0 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_PAIR_SELECT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x18,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_PAIR_SELECT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x18,3)
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SELECT_MASK                    0x0018
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SELECT_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SELECT_BITS                    2
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_SELECT_SHIFT                   3

/* BRPHY4_DSP_TAP :: TAP5_C0 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_PAIR_POLARITY(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x4,2)
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_POLARITY_MASK                  0x0004
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_POLARITY_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_POLARITY_BITS                  1
#define BRPHY4_DSP_TAP_TAP5_C0_PAIR_POLARITY_SHIFT                 2

/* BRPHY4_DSP_TAP :: TAP5_C0 :: SWAPCD [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_SWAPCD(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_SWAPCD(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x2,1)
#define BRPHY4_DSP_TAP_TAP5_C0_SWAPCD_MASK                         0x0002
#define BRPHY4_DSP_TAP_TAP5_C0_SWAPCD_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP5_C0_SWAPCD_BITS                         1
#define BRPHY4_DSP_TAP_TAP5_C0_SWAPCD_SHIFT                        1

/* BRPHY4_DSP_TAP :: TAP5_C0 :: SWAPAB [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C0_SWAPAB(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C0_SWAPAB(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C0,0x1,0)
#define BRPHY4_DSP_TAP_TAP5_C0_SWAPAB_MASK                         0x0001
#define BRPHY4_DSP_TAP_TAP5_C0_SWAPAB_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP5_C0_SWAPAB_BITS                         1
#define BRPHY4_DSP_TAP_TAP5_C0_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP5_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP5_C1 :: reserved0 [15:14] */
#define BRPHY4_DSP_TAP_TAP5_C1_RESERVED0_MASK                      0xc000
#define BRPHY4_DSP_TAP_TAP5_C1_RESERVED0_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP5_C1_RESERVED0_BITS                      2
#define BRPHY4_DSP_TAP_TAP5_C1_RESERVED0_SHIFT                     14

/* BRPHY4_DSP_TAP :: TAP5_C1 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_SLICE_ZERO(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_SLICE_ZERO(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x2000,13)
#define BRPHY4_DSP_TAP_TAP5_C1_SLICE_ZERO_MASK                     0x2000
#define BRPHY4_DSP_TAP_TAP5_C1_SLICE_ZERO_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP5_C1_SLICE_ZERO_BITS                     1
#define BRPHY4_DSP_TAP_TAP5_C1_SLICE_ZERO_SHIFT                    13

/* BRPHY4_DSP_TAP :: TAP5_C1 :: DISABLE_TX [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_DISABLE_TX(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_DISABLE_TX(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x1000,12)
#define BRPHY4_DSP_TAP_TAP5_C1_DISABLE_TX_MASK                     0x1000
#define BRPHY4_DSP_TAP_TAP5_C1_DISABLE_TX_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP5_C1_DISABLE_TX_BITS                     1
#define BRPHY4_DSP_TAP_TAP5_C1_DISABLE_TX_SHIFT                    12

/* BRPHY4_DSP_TAP :: TAP5_C1 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x800,11)
#define BRPHY4_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY4_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY4_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY4_DSP_TAP_TAP5_C1_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY4_DSP_TAP :: TAP5_C1 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x400,10)
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY4_DSP_TAP :: TAP5_C1 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x3c0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x3c0,6)
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_MASK                      0x03c0
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_BITS                      4
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SKEW_SHIFT                     6

/* BRPHY4_DSP_TAP :: TAP5_C1 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x20,5)
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_BITS              1
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY4_DSP_TAP :: TAP5_C1 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_PAIR_SELECT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x18,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_PAIR_SELECT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x18,3)
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SELECT_MASK                    0x0018
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SELECT_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SELECT_BITS                    2
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_SELECT_SHIFT                   3

/* BRPHY4_DSP_TAP :: TAP5_C1 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_PAIR_POLARITY(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x4,2)
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_POLARITY_MASK                  0x0004
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_POLARITY_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_POLARITY_BITS                  1
#define BRPHY4_DSP_TAP_TAP5_C1_PAIR_POLARITY_SHIFT                 2

/* BRPHY4_DSP_TAP :: TAP5_C1 :: SWAPCD [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_SWAPCD(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_SWAPCD(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x2,1)
#define BRPHY4_DSP_TAP_TAP5_C1_SWAPCD_MASK                         0x0002
#define BRPHY4_DSP_TAP_TAP5_C1_SWAPCD_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP5_C1_SWAPCD_BITS                         1
#define BRPHY4_DSP_TAP_TAP5_C1_SWAPCD_SHIFT                        1

/* BRPHY4_DSP_TAP :: TAP5_C1 :: SWAPAB [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C1_SWAPAB(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C1_SWAPAB(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C1,0x1,0)
#define BRPHY4_DSP_TAP_TAP5_C1_SWAPAB_MASK                         0x0001
#define BRPHY4_DSP_TAP_TAP5_C1_SWAPAB_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP5_C1_SWAPAB_BITS                         1
#define BRPHY4_DSP_TAP_TAP5_C1_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP5_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP5_C2 :: reserved0 [15:14] */
#define BRPHY4_DSP_TAP_TAP5_C2_RESERVED0_MASK                      0xc000
#define BRPHY4_DSP_TAP_TAP5_C2_RESERVED0_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP5_C2_RESERVED0_BITS                      2
#define BRPHY4_DSP_TAP_TAP5_C2_RESERVED0_SHIFT                     14

/* BRPHY4_DSP_TAP :: TAP5_C2 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_SLICE_ZERO(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_SLICE_ZERO(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x2000,13)
#define BRPHY4_DSP_TAP_TAP5_C2_SLICE_ZERO_MASK                     0x2000
#define BRPHY4_DSP_TAP_TAP5_C2_SLICE_ZERO_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP5_C2_SLICE_ZERO_BITS                     1
#define BRPHY4_DSP_TAP_TAP5_C2_SLICE_ZERO_SHIFT                    13

/* BRPHY4_DSP_TAP :: TAP5_C2 :: DISABLE_TX [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_DISABLE_TX(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_DISABLE_TX(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x1000,12)
#define BRPHY4_DSP_TAP_TAP5_C2_DISABLE_TX_MASK                     0x1000
#define BRPHY4_DSP_TAP_TAP5_C2_DISABLE_TX_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP5_C2_DISABLE_TX_BITS                     1
#define BRPHY4_DSP_TAP_TAP5_C2_DISABLE_TX_SHIFT                    12

/* BRPHY4_DSP_TAP :: TAP5_C2 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x800,11)
#define BRPHY4_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY4_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY4_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY4_DSP_TAP_TAP5_C2_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY4_DSP_TAP :: TAP5_C2 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x400,10)
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY4_DSP_TAP :: TAP5_C2 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x3c0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x3c0,6)
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_MASK                      0x03c0
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_BITS                      4
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SKEW_SHIFT                     6

/* BRPHY4_DSP_TAP :: TAP5_C2 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x20,5)
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_BITS              1
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY4_DSP_TAP :: TAP5_C2 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_PAIR_SELECT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x18,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_PAIR_SELECT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x18,3)
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SELECT_MASK                    0x0018
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SELECT_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SELECT_BITS                    2
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_SELECT_SHIFT                   3

/* BRPHY4_DSP_TAP :: TAP5_C2 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_PAIR_POLARITY(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x4,2)
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_POLARITY_MASK                  0x0004
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_POLARITY_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_POLARITY_BITS                  1
#define BRPHY4_DSP_TAP_TAP5_C2_PAIR_POLARITY_SHIFT                 2

/* BRPHY4_DSP_TAP :: TAP5_C2 :: SWAPCD [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_SWAPCD(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_SWAPCD(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x2,1)
#define BRPHY4_DSP_TAP_TAP5_C2_SWAPCD_MASK                         0x0002
#define BRPHY4_DSP_TAP_TAP5_C2_SWAPCD_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP5_C2_SWAPCD_BITS                         1
#define BRPHY4_DSP_TAP_TAP5_C2_SWAPCD_SHIFT                        1

/* BRPHY4_DSP_TAP :: TAP5_C2 :: SWAPAB [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C2_SWAPAB(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C2_SWAPAB(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C2,0x1,0)
#define BRPHY4_DSP_TAP_TAP5_C2_SWAPAB_MASK                         0x0001
#define BRPHY4_DSP_TAP_TAP5_C2_SWAPAB_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP5_C2_SWAPAB_BITS                         1
#define BRPHY4_DSP_TAP_TAP5_C2_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP5_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP5_C3 :: reserved0 [15:14] */
#define BRPHY4_DSP_TAP_TAP5_C3_RESERVED0_MASK                      0xc000
#define BRPHY4_DSP_TAP_TAP5_C3_RESERVED0_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP5_C3_RESERVED0_BITS                      2
#define BRPHY4_DSP_TAP_TAP5_C3_RESERVED0_SHIFT                     14

/* BRPHY4_DSP_TAP :: TAP5_C3 :: SLICE_ZERO [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_SLICE_ZERO(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_SLICE_ZERO(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x2000,13)
#define BRPHY4_DSP_TAP_TAP5_C3_SLICE_ZERO_MASK                     0x2000
#define BRPHY4_DSP_TAP_TAP5_C3_SLICE_ZERO_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP5_C3_SLICE_ZERO_BITS                     1
#define BRPHY4_DSP_TAP_TAP5_C3_SLICE_ZERO_SHIFT                    13

/* BRPHY4_DSP_TAP :: TAP5_C3 :: DISABLE_TX [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_DISABLE_TX(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_DISABLE_TX(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x1000,12)
#define BRPHY4_DSP_TAP_TAP5_C3_DISABLE_TX_MASK                     0x1000
#define BRPHY4_DSP_TAP_TAP5_C3_DISABLE_TX_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP5_C3_DISABLE_TX_BITS                     1
#define BRPHY4_DSP_TAP_TAP5_C3_DISABLE_TX_SHIFT                    12

/* BRPHY4_DSP_TAP :: TAP5_C3 :: BLOCK_PHYC_ENC_CTL [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x800,11)
#define BRPHY4_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_MASK             0x0800
#define BRPHY4_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_ALIGN            0
#define BRPHY4_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_BITS             1
#define BRPHY4_DSP_TAP_TAP5_C3_BLOCK_PHYC_ENC_CTL_SHIFT            11

/* BRPHY4_DSP_TAP :: TAP5_C3 :: PAIR_SKEW_SET_OV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x400,10)
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_MASK            0x0400
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_ALIGN           0
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_BITS            1
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_SET_OV_EN_SHIFT           10

/* BRPHY4_DSP_TAP :: TAP5_C3 :: PAIR_SKEW [09:06] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x3c0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x3c0,6)
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_MASK                      0x03c0
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_BITS                      4
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SKEW_SHIFT                     6

/* BRPHY4_DSP_TAP :: TAP5_C3 :: PAIR_STATUS_VALID [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x20,5)
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_MASK              0x0020
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_ALIGN             0
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_BITS              1
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_STATUS_VALID_SHIFT             5

/* BRPHY4_DSP_TAP :: TAP5_C3 :: PAIR_SELECT [04:03] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_PAIR_SELECT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x18,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_PAIR_SELECT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x18,3)
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SELECT_MASK                    0x0018
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SELECT_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SELECT_BITS                    2
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_SELECT_SHIFT                   3

/* BRPHY4_DSP_TAP :: TAP5_C3 :: PAIR_POLARITY [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_PAIR_POLARITY(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x4,2)
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_POLARITY_MASK                  0x0004
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_POLARITY_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_POLARITY_BITS                  1
#define BRPHY4_DSP_TAP_TAP5_C3_PAIR_POLARITY_SHIFT                 2

/* BRPHY4_DSP_TAP :: TAP5_C3 :: SWAPCD [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_SWAPCD(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_SWAPCD(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x2,1)
#define BRPHY4_DSP_TAP_TAP5_C3_SWAPCD_MASK                         0x0002
#define BRPHY4_DSP_TAP_TAP5_C3_SWAPCD_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP5_C3_SWAPCD_BITS                         1
#define BRPHY4_DSP_TAP_TAP5_C3_SWAPCD_SHIFT                        1

/* BRPHY4_DSP_TAP :: TAP5_C3 :: SWAPAB [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP5_C3_SWAPAB(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP5_C3_SWAPAB(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP5_C3,0x1,0)
#define BRPHY4_DSP_TAP_TAP5_C3_SWAPAB_MASK                         0x0001
#define BRPHY4_DSP_TAP_TAP5_C3_SWAPAB_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP5_C3_SWAPAB_BITS                         1
#define BRPHY4_DSP_TAP_TAP5_C3_SWAPAB_SHIFT                        0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP6
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP6 :: CFCDEADMAN_DIS [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP6,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP6_CFCDEADMAN_DIS(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP6,0x8000,15)
#define BRPHY4_DSP_TAP_TAP6_CFCDEADMAN_DIS_MASK                    0x8000
#define BRPHY4_DSP_TAP_TAP6_CFCDEADMAN_DIS_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP6_CFCDEADMAN_DIS_BITS                    1
#define BRPHY4_DSP_TAP_TAP6_CFCDEADMAN_DIS_SHIFT                   15

/* BRPHY4_DSP_TAP :: TAP6 :: AGC_FREEZ_EN [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP6_AGC_FREEZ_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP6,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP6_AGC_FREEZ_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP6,0x4000,14)
#define BRPHY4_DSP_TAP_TAP6_AGC_FREEZ_EN_MASK                      0x4000
#define BRPHY4_DSP_TAP_TAP6_AGC_FREEZ_EN_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP6_AGC_FREEZ_EN_BITS                      1
#define BRPHY4_DSP_TAP_TAP6_AGC_FREEZ_EN_SHIFT                     14

/* BRPHY4_DSP_TAP :: TAP6 :: DAC_GAIN_INV_EN [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP6,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP6_DAC_GAIN_INV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP6,0x2000,13)
#define BRPHY4_DSP_TAP_TAP6_DAC_GAIN_INV_EN_MASK                   0x2000
#define BRPHY4_DSP_TAP_TAP6_DAC_GAIN_INV_EN_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP6_DAC_GAIN_INV_EN_BITS                   1
#define BRPHY4_DSP_TAP_TAP6_DAC_GAIN_INV_EN_SHIFT                  13

/* BRPHY4_DSP_TAP :: TAP6 :: SPARE_REG_B12 [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP6_SPARE_REG_B12(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP6,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP6_SPARE_REG_B12(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP6,0x1000,12)
#define BRPHY4_DSP_TAP_TAP6_SPARE_REG_B12_MASK                     0x1000
#define BRPHY4_DSP_TAP_TAP6_SPARE_REG_B12_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP6_SPARE_REG_B12_BITS                     1
#define BRPHY4_DSP_TAP_TAP6_SPARE_REG_B12_SHIFT                    12

/* BRPHY4_DSP_TAP :: TAP6 :: FORCE_FSM_IDLE [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP6,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP6_FORCE_FSM_IDLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP6,0x800,11)
#define BRPHY4_DSP_TAP_TAP6_FORCE_FSM_IDLE_MASK                    0x0800
#define BRPHY4_DSP_TAP_TAP6_FORCE_FSM_IDLE_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP6_FORCE_FSM_IDLE_BITS                    1
#define BRPHY4_DSP_TAP_TAP6_FORCE_FSM_IDLE_SHIFT                   11

/* BRPHY4_DSP_TAP :: TAP6 :: SPARE_REG [10:00] */
#define Wr_BRPHY4_DSP_TAP_TAP6_SPARE_REG(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP6,0x7ff,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP6_SPARE_REG(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP6,0x7ff,0)
#define BRPHY4_DSP_TAP_TAP6_SPARE_REG_MASK                         0x07ff
#define BRPHY4_DSP_TAP_TAP6_SPARE_REG_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP6_SPARE_REG_BITS                         11
#define BRPHY4_DSP_TAP_TAP6_SPARE_REG_SHIFT                        0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP7_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP7_C0 :: TEST_LENGTH [15:09] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_TEST_LENGTH(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0xfe00,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_TEST_LENGTH(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0xfe00,9)
#define BRPHY4_DSP_TAP_TAP7_C0_TEST_LENGTH_MASK                    0xfe00
#define BRPHY4_DSP_TAP_TAP7_C0_TEST_LENGTH_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP7_C0_TEST_LENGTH_BITS                    7
#define BRPHY4_DSP_TAP_TAP7_C0_TEST_LENGTH_SHIFT                   9

/* BRPHY4_DSP_TAP :: TAP7_C0 :: SINGLE_TAP_MODE [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x100,8)
#define BRPHY4_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_MASK                0x0100
#define BRPHY4_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_ALIGN               0
#define BRPHY4_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_BITS                1
#define BRPHY4_DSP_TAP_TAP7_C0_SINGLE_TAP_MODE_SHIFT               8

/* BRPHY4_DSP_TAP :: TAP7_C0 :: UPDATE_MODE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x80,7)
#define BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MODE_MASK                    0x0080
#define BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MODE_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MODE_BITS                    1
#define BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MODE_SHIFT                   7

/* BRPHY4_DSP_TAP :: TAP7_C0 :: UPDATE_MAGNITUDE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x40,6)
#define BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_MASK               0x0040
#define BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_BITS               1
#define BRPHY4_DSP_TAP_TAP7_C0_UPDATE_MAGNITUDE_SHIFT              6

/* BRPHY4_DSP_TAP :: TAP7_C0 :: START_TEST [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_START_TEST(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_START_TEST(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x20,5)
#define BRPHY4_DSP_TAP_TAP7_C0_START_TEST_MASK                     0x0020
#define BRPHY4_DSP_TAP_TAP7_C0_START_TEST_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP7_C0_START_TEST_BITS                     1
#define BRPHY4_DSP_TAP_TAP7_C0_START_TEST_SHIFT                    5

/* BRPHY4_DSP_TAP :: TAP7_C0 :: ZERO_DFE_D [04:04] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_D(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x10,4)
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_D_MASK                     0x0010
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_D_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_D_BITS                     1
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_D_SHIFT                    4

/* BRPHY4_DSP_TAP :: TAP7_C0 :: ZERO_DFE_C [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_C(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x8,3)
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_C_MASK                     0x0008
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_C_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_C_BITS                     1
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_C_SHIFT                    3

/* BRPHY4_DSP_TAP :: TAP7_C0 :: ZERO_DFE_B [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_B(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x4,2)
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_B_MASK                     0x0004
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_B_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_B_BITS                     1
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_B_SHIFT                    2

/* BRPHY4_DSP_TAP :: TAP7_C0 :: ZERO_DFE_A [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_A(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x2,1)
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_A_MASK                     0x0002
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_A_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_A_BITS                     1
#define BRPHY4_DSP_TAP_TAP7_C0_ZERO_DFE_A_SHIFT                    1

/* BRPHY4_DSP_TAP :: TAP7_C0 :: ENABLE_BIST_MODE [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C0,0x1,0)
#define BRPHY4_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_MASK               0x0001
#define BRPHY4_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_BITS               1
#define BRPHY4_DSP_TAP_TAP7_C0_ENABLE_BIST_MODE_SHIFT              0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP7_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP7_C1 :: TAP_NUMBER [15:08] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C1_TAP_NUMBER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C1,0xff00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C1_TAP_NUMBER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C1,0xff00,8)
#define BRPHY4_DSP_TAP_TAP7_C1_TAP_NUMBER_MASK                     0xff00
#define BRPHY4_DSP_TAP_TAP7_C1_TAP_NUMBER_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP7_C1_TAP_NUMBER_BITS                     8
#define BRPHY4_DSP_TAP_TAP7_C1_TAP_NUMBER_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP7_C1 :: POLARITY_MASK_LSB [07:00] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C1,0xff,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C1,0xff,0)
#define BRPHY4_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_MASK              0x00ff
#define BRPHY4_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_ALIGN             0
#define BRPHY4_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_BITS              8
#define BRPHY4_DSP_TAP_TAP7_C1_POLARITY_MASK_LSB_SHIFT             0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP7_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP7_C2 :: SPARE [15:08] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C2_SPARE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0xff00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C2_SPARE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0xff00,8)
#define BRPHY4_DSP_TAP_TAP7_C2_SPARE_MASK                          0xff00
#define BRPHY4_DSP_TAP_TAP7_C2_SPARE_ALIGN                         0
#define BRPHY4_DSP_TAP_TAP7_C2_SPARE_BITS                          8
#define BRPHY4_DSP_TAP_TAP7_C2_SPARE_SHIFT                         8

/* BRPHY4_DSP_TAP :: TAP7_C2 :: BIST_FFE_UPDATE_EN [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x80,7)
#define BRPHY4_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_MASK             0x0080
#define BRPHY4_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_ALIGN            0
#define BRPHY4_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_BITS             1
#define BRPHY4_DSP_TAP_TAP7_C2_BIST_FFE_UPDATE_EN_SHIFT            7

/* BRPHY4_DSP_TAP :: TAP7_C2 :: DISABLE_RANDOM_BIST_ADC [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x40,6)
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_MASK        0x0040
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_ALIGN       0
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_BITS        1
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_RANDOM_BIST_ADC_SHIFT       6

/* BRPHY4_DSP_TAP :: TAP7_C2 :: DISABLE_VITERBI_TO_BIST [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x20,5)
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_MASK        0x0020
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_ALIGN       0
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_BITS        1
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_VITERBI_TO_BIST_SHIFT       5

/* BRPHY4_DSP_TAP :: TAP7_C2 :: USE_BIST_FOR_DFE [04:04] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x10,4)
#define BRPHY4_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_MASK               0x0010
#define BRPHY4_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_BITS               1
#define BRPHY4_DSP_TAP_TAP7_C2_USE_BIST_FOR_DFE_SHIFT              4

/* BRPHY4_DSP_TAP :: TAP7_C2 :: FORCE_VITERBI_MODE [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x8,3)
#define BRPHY4_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_MASK             0x0008
#define BRPHY4_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_ALIGN            0
#define BRPHY4_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_BITS             1
#define BRPHY4_DSP_TAP_TAP7_C2_FORCE_VITERBI_MODE_SHIFT            3

/* BRPHY4_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_IPRK_OV [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x4,2)
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_MASK           0x0004
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_ALIGN          0
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_BITS           1
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_IPRK_OV_SHIFT          2

/* BRPHY4_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_GAMMA_OV [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x2,1)
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_MASK          0x0002
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_ALIGN         0
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_BITS          1
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_GAMMA_OV_SHIFT         1

/* BRPHY4_DSP_TAP :: TAP7_C2 :: DISABLE_BIST_ADC_OV [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP7_C2,0x1,0)
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_MASK            0x0001
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_ALIGN           0
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_BITS            1
#define BRPHY4_DSP_TAP_TAP7_C2_DISABLE_BIST_ADC_OV_SHIFT           0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP8_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP8_C0 :: PGA_OV [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_PGA_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_PGA_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x8000,15)
#define BRPHY4_DSP_TAP_TAP8_C0_PGA_OV_MASK                         0x8000
#define BRPHY4_DSP_TAP_TAP8_C0_PGA_OV_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP8_C0_PGA_OV_BITS                         1
#define BRPHY4_DSP_TAP_TAP8_C0_PGA_OV_SHIFT                        15

/* BRPHY4_DSP_TAP :: TAP8_C0 :: TIMER_OV [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_TIMER_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_TIMER_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x4000,14)
#define BRPHY4_DSP_TAP_TAP8_C0_TIMER_OV_MASK                       0x4000
#define BRPHY4_DSP_TAP_TAP8_C0_TIMER_OV_ALIGN                      0
#define BRPHY4_DSP_TAP_TAP8_C0_TIMER_OV_BITS                       1
#define BRPHY4_DSP_TAP_TAP8_C0_TIMER_OV_SHIFT                      14

/* BRPHY4_DSP_TAP :: TAP8_C0 :: MONOTONICITY_MODE [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_MONOTONICITY_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x2000,13)
#define BRPHY4_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_MASK              0x2000
#define BRPHY4_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_ALIGN             0
#define BRPHY4_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_BITS              1
#define BRPHY4_DSP_TAP_TAP8_C0_MONOTONICITY_MODE_SHIFT             13

/* BRPHY4_DSP_TAP :: TAP8_C0 :: FREEZE_ERROR_ON_FAIL [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x1000,12)
#define BRPHY4_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_MASK           0x1000
#define BRPHY4_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_ALIGN          0
#define BRPHY4_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_BITS           1
#define BRPHY4_DSP_TAP_TAP8_C0_FREEZE_ERROR_ON_FAIL_SHIFT          12

/* BRPHY4_DSP_TAP :: TAP8_C0 :: FREEZE_MSE_ON_FAIL [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x800,11)
#define BRPHY4_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_MASK             0x0800
#define BRPHY4_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_ALIGN            0
#define BRPHY4_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_BITS             1
#define BRPHY4_DSP_TAP_TAP8_C0_FREEZE_MSE_ON_FAIL_SHIFT            11

/* BRPHY4_DSP_TAP :: TAP8_C0 :: FAST_CONV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_FAST_CONV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x400,10)
#define BRPHY4_DSP_TAP_TAP8_C0_FAST_CONV_EN_MASK                   0x0400
#define BRPHY4_DSP_TAP_TAP8_C0_FAST_CONV_EN_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP8_C0_FAST_CONV_EN_BITS                   1
#define BRPHY4_DSP_TAP_TAP8_C0_FAST_CONV_EN_SHIFT                  10

/* BRPHY4_DSP_TAP :: TAP8_C0 :: PGA_TOGGLE_MODE_EN [09:09] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x200,9)
#define BRPHY4_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_MASK             0x0200
#define BRPHY4_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_ALIGN            0
#define BRPHY4_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_BITS             1
#define BRPHY4_DSP_TAP_TAP8_C0_PGA_TOGGLE_MODE_EN_SHIFT            9

/* BRPHY4_DSP_TAP :: TAP8_C0 :: PAT_GEN_EN [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_PAT_GEN_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x100,8)
#define BRPHY4_DSP_TAP_TAP8_C0_PAT_GEN_EN_MASK                     0x0100
#define BRPHY4_DSP_TAP_TAP8_C0_PAT_GEN_EN_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP8_C0_PAT_GEN_EN_BITS                     1
#define BRPHY4_DSP_TAP_TAP8_C0_PAT_GEN_EN_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP8_C0 :: MAX_OFFSET_CHECK_EN [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x80,7)
#define BRPHY4_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_MASK            0x0080
#define BRPHY4_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_ALIGN           0
#define BRPHY4_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_BITS            1
#define BRPHY4_DSP_TAP_TAP8_C0_MAX_OFFSET_CHECK_EN_SHIFT           7

/* BRPHY4_DSP_TAP :: TAP8_C0 :: SYM_ERR_CHECK_EN [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x40,6)
#define BRPHY4_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_MASK               0x0040
#define BRPHY4_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_ALIGN              0
#define BRPHY4_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_BITS               1
#define BRPHY4_DSP_TAP_TAP8_C0_SYM_ERR_CHECK_EN_SHIFT              6

/* BRPHY4_DSP_TAP :: TAP8_C0 :: PEAK_ERR_CHECK_EN [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x20,5)
#define BRPHY4_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_MASK              0x0020
#define BRPHY4_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_ALIGN             0
#define BRPHY4_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_BITS              1
#define BRPHY4_DSP_TAP_TAP8_C0_PEAK_ERR_CHECK_EN_SHIFT             5

/* BRPHY4_DSP_TAP :: TAP8_C0 :: MSE_CHECK_EN [04:04] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_MSE_CHECK_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x10,4)
#define BRPHY4_DSP_TAP_TAP8_C0_MSE_CHECK_EN_MASK                   0x0010
#define BRPHY4_DSP_TAP_TAP8_C0_MSE_CHECK_EN_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP8_C0_MSE_CHECK_EN_BITS                   1
#define BRPHY4_DSP_TAP_TAP8_C0_MSE_CHECK_EN_SHIFT                  4

/* BRPHY4_DSP_TAP :: TAP8_C0 :: GAIN_AMP_CHECK_EN [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x8,3)
#define BRPHY4_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_MASK              0x0008
#define BRPHY4_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_ALIGN             0
#define BRPHY4_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_BITS              1
#define BRPHY4_DSP_TAP_TAP8_C0_GAIN_AMP_CHECK_EN_SHIFT             3

/* BRPHY4_DSP_TAP :: TAP8_C0 :: HALT_ON_ERROR [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_HALT_ON_ERROR(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x4,2)
#define BRPHY4_DSP_TAP_TAP8_C0_HALT_ON_ERROR_MASK                  0x0004
#define BRPHY4_DSP_TAP_TAP8_C0_HALT_ON_ERROR_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP8_C0_HALT_ON_ERROR_BITS                  1
#define BRPHY4_DSP_TAP_TAP8_C0_HALT_ON_ERROR_SHIFT                 2

/* BRPHY4_DSP_TAP :: TAP8_C0 :: START_ABIST [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_START_ABIST(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_START_ABIST(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x2,1)
#define BRPHY4_DSP_TAP_TAP8_C0_START_ABIST_MASK                    0x0002
#define BRPHY4_DSP_TAP_TAP8_C0_START_ABIST_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP8_C0_START_ABIST_BITS                    1
#define BRPHY4_DSP_TAP_TAP8_C0_START_ABIST_SHIFT                   1

/* BRPHY4_DSP_TAP :: TAP8_C0 :: ABIST_EN [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C0_ABIST_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C0_ABIST_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C0,0x1,0)
#define BRPHY4_DSP_TAP_TAP8_C0_ABIST_EN_MASK                       0x0001
#define BRPHY4_DSP_TAP_TAP8_C0_ABIST_EN_ALIGN                      0
#define BRPHY4_DSP_TAP_TAP8_C0_ABIST_EN_BITS                       1
#define BRPHY4_DSP_TAP_TAP8_C0_ABIST_EN_SHIFT                      0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP8_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP8_C1 :: MAJOR_MODE [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_MAJOR_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_MAJOR_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x8000,15)
#define BRPHY4_DSP_TAP_TAP8_C1_MAJOR_MODE_MASK                     0x8000
#define BRPHY4_DSP_TAP_TAP8_C1_MAJOR_MODE_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP8_C1_MAJOR_MODE_BITS                     1
#define BRPHY4_DSP_TAP_TAP8_C1_MAJOR_MODE_SHIFT                    15

/* BRPHY4_DSP_TAP :: TAP8_C1 :: MULTIPLE_MSE [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_MULTIPLE_MSE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x4000,14)
#define BRPHY4_DSP_TAP_TAP8_C1_MULTIPLE_MSE_MASK                   0x4000
#define BRPHY4_DSP_TAP_TAP8_C1_MULTIPLE_MSE_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP8_C1_MULTIPLE_MSE_BITS                   1
#define BRPHY4_DSP_TAP_TAP8_C1_MULTIPLE_MSE_SHIFT                  14

/* BRPHY4_DSP_TAP :: TAP8_C1 :: GAMMA_OV [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_GAMMA_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_GAMMA_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x2000,13)
#define BRPHY4_DSP_TAP_TAP8_C1_GAMMA_OV_MASK                       0x2000
#define BRPHY4_DSP_TAP_TAP8_C1_GAMMA_OV_ALIGN                      0
#define BRPHY4_DSP_TAP_TAP8_C1_GAMMA_OV_BITS                       1
#define BRPHY4_DSP_TAP_TAP8_C1_GAMMA_OV_SHIFT                      13

/* BRPHY4_DSP_TAP :: TAP8_C1 :: FFE_COARSE_OV [12:08] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x1f00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_FFE_COARSE_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x1f00,8)
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_COARSE_OV_MASK                  0x1f00
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_COARSE_OV_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_COARSE_OV_BITS                  5
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_COARSE_OV_SHIFT                 8

/* BRPHY4_DSP_TAP :: TAP8_C1 :: FFE_PF_OV_INIT [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x80,7)
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_MASK                 0x0080
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_ALIGN                0
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_BITS                 1
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_PF_OV_INIT_SHIFT                7

/* BRPHY4_DSP_TAP :: TAP8_C1 :: SINGLE_STEP_MODE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x40,6)
#define BRPHY4_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_MASK               0x0040
#define BRPHY4_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_BITS               1
#define BRPHY4_DSP_TAP_TAP8_C1_SINGLE_STEP_MODE_SHIFT              6

/* BRPHY4_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SEL [05:04] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x30,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x30,4)
#define BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_MASK               0x0030
#define BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_ALIGN              0
#define BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_BITS               2
#define BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SEL_SHIFT              4

/* BRPHY4_DSP_TAP :: TAP8_C1 :: TX_AMPLITUDE_SE_EN [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x8,3)
#define BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_MASK             0x0008
#define BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_ALIGN            0
#define BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_BITS             1
#define BRPHY4_DSP_TAP_TAP8_C1_TX_AMPLITUDE_SE_EN_SHIFT            3

/* BRPHY4_DSP_TAP :: TAP8_C1 :: TX_HALFOUT_OV [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_TX_HALFOUT_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x4,2)
#define BRPHY4_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_MASK                  0x0004
#define BRPHY4_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_BITS                  1
#define BRPHY4_DSP_TAP_TAP8_C1_TX_HALFOUT_OV_SHIFT                 2

/* BRPHY4_DSP_TAP :: TAP8_C1 :: TX_ADJ_EN [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_TX_ADJ_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x2,1)
#define BRPHY4_DSP_TAP_TAP8_C1_TX_ADJ_EN_MASK                      0x0002
#define BRPHY4_DSP_TAP_TAP8_C1_TX_ADJ_EN_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP8_C1_TX_ADJ_EN_BITS                      1
#define BRPHY4_DSP_TAP_TAP8_C1_TX_ADJ_EN_SHIFT                     1

/* BRPHY4_DSP_TAP :: TAP8_C1 :: FFE_BUMP_EN [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C1_FFE_BUMP_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C1,0x1,0)
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_BUMP_EN_MASK                    0x0001
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_BUMP_EN_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_BUMP_EN_BITS                    1
#define BRPHY4_DSP_TAP_TAP8_C1_FFE_BUMP_EN_SHIFT                   0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP8_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP8_C2 :: LEVELSELECT [15:13] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_LEVELSELECT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0xe000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_LEVELSELECT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0xe000,13)
#define BRPHY4_DSP_TAP_TAP8_C2_LEVELSELECT_MASK                    0xe000
#define BRPHY4_DSP_TAP_TAP8_C2_LEVELSELECT_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP8_C2_LEVELSELECT_BITS                    3
#define BRPHY4_DSP_TAP_TAP8_C2_LEVELSELECT_SHIFT                   13

/* BRPHY4_DSP_TAP :: TAP8_C2 :: FAILING_CHANNEL [12:11] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x1800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_FAILING_CHANNEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x1800,11)
#define BRPHY4_DSP_TAP_TAP8_C2_FAILING_CHANNEL_MASK                0x1800
#define BRPHY4_DSP_TAP_TAP8_C2_FAILING_CHANNEL_ALIGN               0
#define BRPHY4_DSP_TAP_TAP8_C2_FAILING_CHANNEL_BITS                2
#define BRPHY4_DSP_TAP_TAP8_C2_FAILING_CHANNEL_SHIFT               11

/* BRPHY4_DSP_TAP :: TAP8_C2 :: CONV_FAIL_FLAG [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x400,10)
#define BRPHY4_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_MASK                 0x0400
#define BRPHY4_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_ALIGN                0
#define BRPHY4_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_BITS                 1
#define BRPHY4_DSP_TAP_TAP8_C2_CONV_FAIL_FLAG_SHIFT                10

/* BRPHY4_DSP_TAP :: TAP8_C2 :: SYM_ERR_FAIL_FLAG [09:09] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x200,9)
#define BRPHY4_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_MASK              0x0200
#define BRPHY4_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_ALIGN             0
#define BRPHY4_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_BITS              1
#define BRPHY4_DSP_TAP_TAP8_C2_SYM_ERR_FAIL_FLAG_SHIFT             9

/* BRPHY4_DSP_TAP :: TAP8_C2 :: MAX_OFFSET_FAIL_FLAG [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x100,8)
#define BRPHY4_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_MASK           0x0100
#define BRPHY4_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_ALIGN          0
#define BRPHY4_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_BITS           1
#define BRPHY4_DSP_TAP_TAP8_C2_MAX_OFFSET_FAIL_FLAG_SHIFT          8

/* BRPHY4_DSP_TAP :: TAP8_C2 :: PEAK_ERR_FAIL_FLAG [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x80,7)
#define BRPHY4_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_MASK             0x0080
#define BRPHY4_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_ALIGN            0
#define BRPHY4_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_BITS             1
#define BRPHY4_DSP_TAP_TAP8_C2_PEAK_ERR_FAIL_FLAG_SHIFT            7

/* BRPHY4_DSP_TAP :: TAP8_C2 :: MSE_FAIL_FLAG [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x40,6)
#define BRPHY4_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_MASK                  0x0040
#define BRPHY4_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_BITS                  1
#define BRPHY4_DSP_TAP_TAP8_C2_MSE_FAIL_FLAG_SHIFT                 6

/* BRPHY4_DSP_TAP :: TAP8_C2 :: GAIN_AMP_FAIL_FLAG [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x20,5)
#define BRPHY4_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_MASK             0x0020
#define BRPHY4_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_ALIGN            0
#define BRPHY4_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_BITS             1
#define BRPHY4_DSP_TAP_TAP8_C2_GAIN_AMP_FAIL_FLAG_SHIFT            5

/* BRPHY4_DSP_TAP :: TAP8_C2 :: ABIST_COMPLETE_FLAG [04:04] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0x10,4)
#define BRPHY4_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_MASK            0x0010
#define BRPHY4_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_ALIGN           0
#define BRPHY4_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_BITS            1
#define BRPHY4_DSP_TAP_TAP8_C2_ABIST_COMPLETE_FLAG_SHIFT           4

/* BRPHY4_DSP_TAP :: TAP8_C2 :: ADC_OVERFLOW [03:00] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C2_ADC_OVERFLOW(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C2,0xf,0)
#define BRPHY4_DSP_TAP_TAP8_C2_ADC_OVERFLOW_MASK                   0x000f
#define BRPHY4_DSP_TAP_TAP8_C2_ADC_OVERFLOW_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP8_C2_ADC_OVERFLOW_BITS                   4
#define BRPHY4_DSP_TAP_TAP8_C2_ADC_OVERFLOW_SHIFT                  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP8_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP8_C3 :: SPARE [15:12] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C3_SPARE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C3,0xf000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C3_SPARE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C3,0xf000,12)
#define BRPHY4_DSP_TAP_TAP8_C3_SPARE_MASK                          0xf000
#define BRPHY4_DSP_TAP_TAP8_C3_SPARE_ALIGN                         0
#define BRPHY4_DSP_TAP_TAP8_C3_SPARE_BITS                          4
#define BRPHY4_DSP_TAP_TAP8_C3_SPARE_SHIFT                         12

/* BRPHY4_DSP_TAP :: TAP8_C3 :: BR_AGC_RST_VAL [11:10] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C3,0xc00,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C3,0xc00,10)
#define BRPHY4_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_MASK                 0x0c00
#define BRPHY4_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_ALIGN                0
#define BRPHY4_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_BITS                 2
#define BRPHY4_DSP_TAP_TAP8_C3_BR_AGC_RST_VAL_SHIFT                10

/* BRPHY4_DSP_TAP :: TAP8_C3 :: BR_HPF_CTL [09:00] */
#define Wr_BRPHY4_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP8_C3,0x3ff,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP8_C3_BR_HPF_CTL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP8_C3,0x3ff,0)
#define BRPHY4_DSP_TAP_TAP8_C3_BR_HPF_CTL_MASK                     0x03ff
#define BRPHY4_DSP_TAP_TAP8_C3_BR_HPF_CTL_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP8_C3_BR_HPF_CTL_BITS                     10
#define BRPHY4_DSP_TAP_TAP8_C3_BR_HPF_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP9
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP9 :: FREQ_REG [15:04] */
#define Wr_BRPHY4_DSP_TAP_TAP9_FREQ_REG(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP9,0xfff0,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP9_FREQ_REG(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP9,0xfff0,4)
#define BRPHY4_DSP_TAP_TAP9_FREQ_REG_MASK                          0xfff0
#define BRPHY4_DSP_TAP_TAP9_FREQ_REG_ALIGN                         0
#define BRPHY4_DSP_TAP_TAP9_FREQ_REG_BITS                          12
#define BRPHY4_DSP_TAP_TAP9_FREQ_REG_SHIFT                         4

/* BRPHY4_DSP_TAP :: TAP9 :: FREQ_REG_OV_EN_ABCD [03:00] */
#define Wr_BRPHY4_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP9,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP9,0xf,0)
#define BRPHY4_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_MASK               0x000f
#define BRPHY4_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_ALIGN              0
#define BRPHY4_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_BITS               4
#define BRPHY4_DSP_TAP_TAP9_FREQ_REG_OV_EN_ABCD_SHIFT              0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP10
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP10 :: SLAVEENCCONVADJUST [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP10,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP10_SLAVEENCCONVADJUST(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP10,0x8000,15)
#define BRPHY4_DSP_TAP_TAP10_SLAVEENCCONVADJUST_MASK               0x8000
#define BRPHY4_DSP_TAP_TAP10_SLAVEENCCONVADJUST_ALIGN              0
#define BRPHY4_DSP_TAP_TAP10_SLAVEENCCONVADJUST_BITS               1
#define BRPHY4_DSP_TAP_TAP10_SLAVEENCCONVADJUST_SHIFT              15

/* BRPHY4_DSP_TAP :: TAP10 :: TRIM_HYB [14:11] */
#define Wr_BRPHY4_DSP_TAP_TAP10_TRIM_HYB(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP10,0x7800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP10_TRIM_HYB(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP10,0x7800,11)
#define BRPHY4_DSP_TAP_TAP10_TRIM_HYB_MASK                         0x7800
#define BRPHY4_DSP_TAP_TAP10_TRIM_HYB_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP10_TRIM_HYB_BITS                         4
#define BRPHY4_DSP_TAP_TAP10_TRIM_HYB_SHIFT                        11

/* BRPHY4_DSP_TAP :: TAP10 :: FFE_GAMMA_OV [10:09] */
#define Wr_BRPHY4_DSP_TAP_TAP10_FFE_GAMMA_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP10,0x600,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP10_FFE_GAMMA_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP10,0x600,9)
#define BRPHY4_DSP_TAP_TAP10_FFE_GAMMA_OV_MASK                     0x0600
#define BRPHY4_DSP_TAP_TAP10_FFE_GAMMA_OV_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP10_FFE_GAMMA_OV_BITS                     2
#define BRPHY4_DSP_TAP_TAP10_FFE_GAMMA_OV_SHIFT                    9

/* BRPHY4_DSP_TAP :: TAP10 :: TX_PHASE_CTL_BW_SEL [08:07] */
#define Wr_BRPHY4_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP10,0x180,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP10,0x180,7)
#define BRPHY4_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_MASK              0x0180
#define BRPHY4_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_ALIGN             0
#define BRPHY4_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_BITS              2
#define BRPHY4_DSP_TAP_TAP10_TX_PHASE_CTL_BW_SEL_SHIFT             7

/* BRPHY4_DSP_TAP :: TAP10 :: RESET_PATH_METRICS [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP10_RESET_PATH_METRICS(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP10,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP10_RESET_PATH_METRICS(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP10,0x40,6)
#define BRPHY4_DSP_TAP_TAP10_RESET_PATH_METRICS_MASK               0x0040
#define BRPHY4_DSP_TAP_TAP10_RESET_PATH_METRICS_ALIGN              0
#define BRPHY4_DSP_TAP_TAP10_RESET_PATH_METRICS_BITS               1
#define BRPHY4_DSP_TAP_TAP10_RESET_PATH_METRICS_SHIFT              6

/* BRPHY4_DSP_TAP :: TAP10 :: GBT_PLL_BW_CTL_STARTUP [05:03] */
#define Wr_BRPHY4_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP10,0x38,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP10,0x38,3)
#define BRPHY4_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_MASK           0x0038
#define BRPHY4_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_ALIGN          0
#define BRPHY4_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_BITS           3
#define BRPHY4_DSP_TAP_TAP10_GBT_PLL_BW_CTL_STARTUP_SHIFT          3

/* BRPHY4_DSP_TAP :: TAP10 :: BGT_PLL_BW_CTL_NORMAL_OP [02:00] */
#define Wr_BRPHY4_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP10,0x7,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP10,0x7,0)
#define BRPHY4_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_MASK         0x0007
#define BRPHY4_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_ALIGN        0
#define BRPHY4_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_BITS         3
#define BRPHY4_DSP_TAP_TAP10_BGT_PLL_BW_CTL_NORMAL_OP_SHIFT        0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP11
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP11 :: TCLK_OFFSET_STROBE [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP11,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP11,0x8000,15)
#define BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_MASK               0x8000
#define BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_BITS               1
#define BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_STROBE_SHIFT              15

/* BRPHY4_DSP_TAP :: TAP11 :: RCLK_OFFSET_STROBE [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP11,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP11,0x4000,14)
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_MASK               0x4000
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_BITS               1
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_STROBE_SHIFT              14

/* BRPHY4_DSP_TAP :: TAP11 :: reserved0 [13:13] */
#define BRPHY4_DSP_TAP_TAP11_RESERVED0_MASK                        0x2000
#define BRPHY4_DSP_TAP_TAP11_RESERVED0_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP11_RESERVED0_BITS                        1
#define BRPHY4_DSP_TAP_TAP11_RESERVED0_SHIFT                       13

/* BRPHY4_DSP_TAP :: TAP11 :: RCLK_OFFSET_FREEZE [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP11,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP11,0x1000,12)
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_MASK               0x1000
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_BITS               1
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_FREEZE_SHIFT              12

/* BRPHY4_DSP_TAP :: TAP11 :: TCLK_OFFSET [11:06] */
#define Wr_BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP11,0xfc0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP11,0xfc0,6)
#define BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_MASK                      0x0fc0
#define BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_BITS                      6
#define BRPHY4_DSP_TAP_TAP11_TCLK_OFFSET_SHIFT                     6

/* BRPHY4_DSP_TAP :: TAP11 :: RCLK_OFFSET [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP11,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP11,0x3f,0)
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_MASK                      0x003f
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_BITS                      6
#define BRPHY4_DSP_TAP_TAP11_RCLK_OFFSET_SHIFT                     0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP12_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP12_C0 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_TAP12_C0_RESERVED0_MASK                     0xff00
#define BRPHY4_DSP_TAP_TAP12_C0_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP12_C0_RESERVED0_BITS                     8
#define BRPHY4_DSP_TAP_TAP12_C0_RESERVED0_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C0,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C0,0x80,7)
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY4_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C0,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C0,0x40,6)
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY4_DSP_TAP :: TAP12_C0 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C0,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C0,0x3f,0)
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_MASK                   0x003f
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_BITS                   6
#define BRPHY4_DSP_TAP_TAP12_C0_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP12_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP12_C1 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_TAP12_C1_RESERVED0_MASK                     0xff00
#define BRPHY4_DSP_TAP_TAP12_C1_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP12_C1_RESERVED0_BITS                     8
#define BRPHY4_DSP_TAP_TAP12_C1_RESERVED0_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C1,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C1,0x80,7)
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY4_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C1,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C1,0x40,6)
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY4_DSP_TAP :: TAP12_C1 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C1,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C1,0x3f,0)
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_MASK                   0x003f
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_BITS                   6
#define BRPHY4_DSP_TAP_TAP12_C1_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP12_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP12_C2 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_TAP12_C2_RESERVED0_MASK                     0xff00
#define BRPHY4_DSP_TAP_TAP12_C2_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP12_C2_RESERVED0_BITS                     8
#define BRPHY4_DSP_TAP_TAP12_C2_RESERVED0_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C2,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C2,0x80,7)
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY4_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C2,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C2,0x40,6)
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY4_DSP_TAP :: TAP12_C2 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C2,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C2,0x3f,0)
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_MASK                   0x003f
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_BITS                   6
#define BRPHY4_DSP_TAP_TAP12_C2_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP12_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP12_C3 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_TAP12_C3_RESERVED0_MASK                     0xff00
#define BRPHY4_DSP_TAP_TAP12_C3_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP12_C3_RESERVED0_BITS                     8
#define BRPHY4_DSP_TAP_TAP12_C3_RESERVED0_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_STROBE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C3,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C3,0x80,7)
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_MASK            0x0080
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_BITS            1
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_STROBE_SHIFT           7

/* BRPHY4_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET_FREEZE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C3,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C3,0x40,6)
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_MASK            0x0040
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_FREEZE_SHIFT           6

/* BRPHY4_DSP_TAP :: TAP12_C3 :: ACLK_OFFSET [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP12_C3,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP12_C3,0x3f,0)
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_MASK                   0x003f
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_BITS                   6
#define BRPHY4_DSP_TAP_TAP12_C3_ACLK_OFFSET_SHIFT                  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP13
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP13 :: TMPLATE_EN [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP13_TMPLATE_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_TMPLATE_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0x8000,15)
#define BRPHY4_DSP_TAP_TAP13_TMPLATE_EN_MASK                       0x8000
#define BRPHY4_DSP_TAP_TAP13_TMPLATE_EN_ALIGN                      0
#define BRPHY4_DSP_TAP_TAP13_TMPLATE_EN_BITS                       1
#define BRPHY4_DSP_TAP_TAP13_TMPLATE_EN_SHIFT                      15

/* BRPHY4_DSP_TAP :: TAP13 :: PATTERN_DURATION [14:13] */
#define Wr_BRPHY4_DSP_TAP_TAP13_PATTERN_DURATION(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0x6000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_PATTERN_DURATION(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0x6000,13)
#define BRPHY4_DSP_TAP_TAP13_PATTERN_DURATION_MASK                 0x6000
#define BRPHY4_DSP_TAP_TAP13_PATTERN_DURATION_ALIGN                0
#define BRPHY4_DSP_TAP_TAP13_PATTERN_DURATION_BITS                 2
#define BRPHY4_DSP_TAP_TAP13_PATTERN_DURATION_SHIFT                13

/* BRPHY4_DSP_TAP :: TAP13 :: PATTERN_SEL [12:11] */
#define Wr_BRPHY4_DSP_TAP_TAP13_PATTERN_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0x1800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_PATTERN_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0x1800,11)
#define BRPHY4_DSP_TAP_TAP13_PATTERN_SEL_MASK                      0x1800
#define BRPHY4_DSP_TAP_TAP13_PATTERN_SEL_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP13_PATTERN_SEL_BITS                      2
#define BRPHY4_DSP_TAP_TAP13_PATTERN_SEL_SHIFT                     11

/* BRPHY4_DSP_TAP :: TAP13 :: PATTERN_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP13_PATTERN_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_PATTERN_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0x400,10)
#define BRPHY4_DSP_TAP_TAP13_PATTERN_EN_MASK                       0x0400
#define BRPHY4_DSP_TAP_TAP13_PATTERN_EN_ALIGN                      0
#define BRPHY4_DSP_TAP_TAP13_PATTERN_EN_BITS                       1
#define BRPHY4_DSP_TAP_TAP13_PATTERN_EN_SHIFT                      10

/* BRPHY4_DSP_TAP :: TAP13 :: DISABLETRRRGEN [09:09] */
#define Wr_BRPHY4_DSP_TAP_TAP13_DISABLETRRRGEN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_DISABLETRRRGEN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0x200,9)
#define BRPHY4_DSP_TAP_TAP13_DISABLETRRRGEN_MASK                   0x0200
#define BRPHY4_DSP_TAP_TAP13_DISABLETRRRGEN_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP13_DISABLETRRRGEN_BITS                   1
#define BRPHY4_DSP_TAP_TAP13_DISABLETRRRGEN_SHIFT                  9

/* BRPHY4_DSP_TAP :: TAP13 :: DISABLE10BEXTENSION [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_DISABLE10BEXTENSION(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0x100,8)
#define BRPHY4_DSP_TAP_TAP13_DISABLE10BEXTENSION_MASK              0x0100
#define BRPHY4_DSP_TAP_TAP13_DISABLE10BEXTENSION_ALIGN             0
#define BRPHY4_DSP_TAP_TAP13_DISABLE10BEXTENSION_BITS              1
#define BRPHY4_DSP_TAP_TAP13_DISABLE10BEXTENSION_SHIFT             8

/* BRPHY4_DSP_TAP :: TAP13 :: ALIGN_OK1_DISABLE [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_ALIGN_OK1_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0x80,7)
#define BRPHY4_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_MASK                0x0080
#define BRPHY4_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_ALIGN               0
#define BRPHY4_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_BITS                1
#define BRPHY4_DSP_TAP_TAP13_ALIGN_OK1_DISABLE_SHIFT               7

/* BRPHY4_DSP_TAP :: TAP13 :: ALIGN_OK2_DISABLE [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_ALIGN_OK2_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0x40,6)
#define BRPHY4_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_MASK                0x0040
#define BRPHY4_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_ALIGN               0
#define BRPHY4_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_BITS                1
#define BRPHY4_DSP_TAP_TAP13_ALIGN_OK2_DISABLE_SHIFT               6

/* BRPHY4_DSP_TAP :: TAP13 :: DISABLE_ADC_LSBS [05:04] */
#define Wr_BRPHY4_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0x30,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_DISABLE_ADC_LSBS(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0x30,4)
#define BRPHY4_DSP_TAP_TAP13_DISABLE_ADC_LSBS_MASK                 0x0030
#define BRPHY4_DSP_TAP_TAP13_DISABLE_ADC_LSBS_ALIGN                0
#define BRPHY4_DSP_TAP_TAP13_DISABLE_ADC_LSBS_BITS                 2
#define BRPHY4_DSP_TAP_TAP13_DISABLE_ADC_LSBS_SHIFT                4

/* BRPHY4_DSP_TAP :: TAP13 :: IDLE_EXT_MASK [03:02] */
#define Wr_BRPHY4_DSP_TAP_TAP13_IDLE_EXT_MASK(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP13,0xc,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP13_IDLE_EXT_MASK(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP13,0xc,2)
#define BRPHY4_DSP_TAP_TAP13_IDLE_EXT_MASK_MASK                    0x000c
#define BRPHY4_DSP_TAP_TAP13_IDLE_EXT_MASK_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP13_IDLE_EXT_MASK_BITS                    2
#define BRPHY4_DSP_TAP_TAP13_IDLE_EXT_MASK_SHIFT                   2

/* BRPHY4_DSP_TAP :: TAP13 :: reserved0 [01:00] */
#define BRPHY4_DSP_TAP_TAP13_RESERVED0_MASK                        0x0003
#define BRPHY4_DSP_TAP_TAP13_RESERVED0_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP13_RESERVED0_BITS                        2
#define BRPHY4_DSP_TAP_TAP13_RESERVED0_SHIFT                       0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP14
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP14 :: MSE_THD_1_LSB [15:08] */
#define Wr_BRPHY4_DSP_TAP_TAP14_MSE_THD_1_LSB(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP14,0xff00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP14_MSE_THD_1_LSB(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP14,0xff00,8)
#define BRPHY4_DSP_TAP_TAP14_MSE_THD_1_LSB_MASK                    0xff00
#define BRPHY4_DSP_TAP_TAP14_MSE_THD_1_LSB_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP14_MSE_THD_1_LSB_BITS                    8
#define BRPHY4_DSP_TAP_TAP14_MSE_THD_1_LSB_SHIFT                   8

/* BRPHY4_DSP_TAP :: TAP14 :: ENERGY_DET_THD [07:00] */
#define Wr_BRPHY4_DSP_TAP_TAP14_ENERGY_DET_THD(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP14,0xff,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP14_ENERGY_DET_THD(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP14,0xff,0)
#define BRPHY4_DSP_TAP_TAP14_ENERGY_DET_THD_MASK                   0x00ff
#define BRPHY4_DSP_TAP_TAP14_ENERGY_DET_THD_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP14_ENERGY_DET_THD_BITS                   8
#define BRPHY4_DSP_TAP_TAP14_ENERGY_DET_THD_SHIFT                  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP15
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP15 :: MSE_THD_3_SEL [15:14] */
#define Wr_BRPHY4_DSP_TAP_TAP15_MSE_THD_3_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP15,0xc000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP15_MSE_THD_3_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP15,0xc000,14)
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_3_SEL_MASK                    0xc000
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_3_SEL_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_3_SEL_BITS                    2
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_3_SEL_SHIFT                   14

/* BRPHY4_DSP_TAP :: TAP15 :: MSE_THD_2 [13:02] */
#define Wr_BRPHY4_DSP_TAP_TAP15_MSE_THD_2(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP15,0x3ffc,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP15_MSE_THD_2(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP15,0x3ffc,2)
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_2_MASK                        0x3ffc
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_2_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_2_BITS                        12
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_2_SHIFT                       2

/* BRPHY4_DSP_TAP :: TAP15 :: MSE_THD_1_MSB [01:00] */
#define Wr_BRPHY4_DSP_TAP_TAP15_MSE_THD_1_MSB(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP15,0x3,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP15_MSE_THD_1_MSB(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP15,0x3,0)
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_1_MSB_MASK                    0x0003
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_1_MSB_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_1_MSB_BITS                    2
#define BRPHY4_DSP_TAP_TAP15_MSE_THD_1_MSB_SHIFT                   0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP16_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP16_C0 :: LA_TRIGGER_DELAY [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) WriteReg16(BRPHY4_DSP_TAP_TAP16_C0,x)
#define Rd_BRPHY4_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY(x) ReadReg16(BRPHY4_DSP_TAP_TAP16_C0)
#define BRPHY4_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_MASK              0xffff
#define BRPHY4_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_ALIGN             0
#define BRPHY4_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_BITS              16
#define BRPHY4_DSP_TAP_TAP16_C0_LA_TRIGGER_DELAY_SHIFT             0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP16_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP16_C1 :: BIST_CRC [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP16_C1_BIST_CRC(x) WriteReg16(BRPHY4_DSP_TAP_TAP16_C1,x)
#define Rd_BRPHY4_DSP_TAP_TAP16_C1_BIST_CRC(x) ReadReg16(BRPHY4_DSP_TAP_TAP16_C1)
#define BRPHY4_DSP_TAP_TAP16_C1_BIST_CRC_MASK                      0xffff
#define BRPHY4_DSP_TAP_TAP16_C1_BIST_CRC_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP16_C1_BIST_CRC_BITS                      16
#define BRPHY4_DSP_TAP_TAP16_C1_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP16_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP16_C2 :: BIST_CRC [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP16_C2_BIST_CRC(x) WriteReg16(BRPHY4_DSP_TAP_TAP16_C2,x)
#define Rd_BRPHY4_DSP_TAP_TAP16_C2_BIST_CRC(x) ReadReg16(BRPHY4_DSP_TAP_TAP16_C2)
#define BRPHY4_DSP_TAP_TAP16_C2_BIST_CRC_MASK                      0xffff
#define BRPHY4_DSP_TAP_TAP16_C2_BIST_CRC_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP16_C2_BIST_CRC_BITS                      16
#define BRPHY4_DSP_TAP_TAP16_C2_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP16_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP16_C3 :: BIST_CRC [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP16_C3_BIST_CRC(x) WriteReg16(BRPHY4_DSP_TAP_TAP16_C3,x)
#define Rd_BRPHY4_DSP_TAP_TAP16_C3_BIST_CRC(x) ReadReg16(BRPHY4_DSP_TAP_TAP16_C3)
#define BRPHY4_DSP_TAP_TAP16_C3_BIST_CRC_MASK                      0xffff
#define BRPHY4_DSP_TAP_TAP16_C3_BIST_CRC_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP16_C3_BIST_CRC_BITS                      16
#define BRPHY4_DSP_TAP_TAP16_C3_BIST_CRC_SHIFT                     0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP17_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP17_C0 :: TESTVALUE [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C0_TESTVALUE(x) WriteReg16(BRPHY4_DSP_TAP_TAP17_C0,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C0_TESTVALUE(x) ReadReg16(BRPHY4_DSP_TAP_TAP17_C0)
#define BRPHY4_DSP_TAP_TAP17_C0_TESTVALUE_MASK                     0xffff
#define BRPHY4_DSP_TAP_TAP17_C0_TESTVALUE_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP17_C0_TESTVALUE_BITS                     16
#define BRPHY4_DSP_TAP_TAP17_C0_TESTVALUE_SHIFT                    0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP17_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP17_C1 :: LA_ACQ_DONE [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C1_LA_ACQ_DONE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x8000,15)
#define BRPHY4_DSP_TAP_TAP17_C1_LA_ACQ_DONE_MASK                   0x8000
#define BRPHY4_DSP_TAP_TAP17_C1_LA_ACQ_DONE_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP17_C1_LA_ACQ_DONE_BITS                   1
#define BRPHY4_DSP_TAP_TAP17_C1_LA_ACQ_DONE_SHIFT                  15

/* BRPHY4_DSP_TAP :: TAP17_C1 :: LA_TPOUT_SEL [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C1_LA_TPOUT_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x4000,14)
#define BRPHY4_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_MASK                  0x4000
#define BRPHY4_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_BITS                  1
#define BRPHY4_DSP_TAP_TAP17_C1_LA_TPOUT_SEL_SHIFT                 14

/* BRPHY4_DSP_TAP :: TAP17_C1 :: LA_CLK_DIVISOR [13:11] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x3800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x3800,11)
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_MASK                0x3800
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_ALIGN               0
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_BITS                3
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DIVISOR_SHIFT               11

/* BRPHY4_DSP_TAP :: TAP17_C1 :: LA_CLK_DELAY [10:09] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x600,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DELAY(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x600,9)
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DELAY_MASK                  0x0600
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DELAY_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DELAY_BITS                  2
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_DELAY_SHIFT                 9

/* BRPHY4_DSP_TAP :: TAP17_C1 :: LA_CLK_EDGE [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_EDGE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x100,8)
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_EDGE_MASK                   0x0100
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_EDGE_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_EDGE_BITS                   1
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_EDGE_SHIFT                  8

/* BRPHY4_DSP_TAP :: TAP17_C1 :: LA_CLK_SEL [07:03] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0xf8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0xf8,3)
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_SEL_MASK                    0x00f8
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_SEL_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_SEL_BITS                    5
#define BRPHY4_DSP_TAP_TAP17_C1_LA_CLK_SEL_SHIFT                   3

/* BRPHY4_DSP_TAP :: TAP17_C1 :: LA_ENABLE [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C1_LA_ENABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C1_LA_ENABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x4,2)
#define BRPHY4_DSP_TAP_TAP17_C1_LA_ENABLE_MASK                     0x0004
#define BRPHY4_DSP_TAP_TAP17_C1_LA_ENABLE_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP17_C1_LA_ENABLE_BITS                     1
#define BRPHY4_DSP_TAP_TAP17_C1_LA_ENABLE_SHIFT                    2

/* BRPHY4_DSP_TAP :: TAP17_C1 :: TESTMODE_STROBE [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C1_TESTMODE_STROBE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x2,1)
#define BRPHY4_DSP_TAP_TAP17_C1_TESTMODE_STROBE_MASK               0x0002
#define BRPHY4_DSP_TAP_TAP17_C1_TESTMODE_STROBE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP17_C1_TESTMODE_STROBE_BITS               1
#define BRPHY4_DSP_TAP_TAP17_C1_TESTMODE_STROBE_SHIFT              1

/* BRPHY4_DSP_TAP :: TAP17_C1 :: LSITEST_SMDSP [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C1_LSITEST_SMDSP(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C1,0x1,0)
#define BRPHY4_DSP_TAP_TAP17_C1_LSITEST_SMDSP_MASK                 0x0001
#define BRPHY4_DSP_TAP_TAP17_C1_LSITEST_SMDSP_ALIGN                0
#define BRPHY4_DSP_TAP_TAP17_C1_LSITEST_SMDSP_BITS                 1
#define BRPHY4_DSP_TAP_TAP17_C1_LSITEST_SMDSP_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP17_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP17_C2 :: TRIGGER2_LAT [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_LAT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x8000,15)
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_LAT_MASK                  0x8000
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_LAT_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_LAT_BITS                  1
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_LAT_SHIFT                 15

/* BRPHY4_DSP_TAP :: TAP17_C2 :: TRIGGER2_INV [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_INV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x4000,14)
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_INV_MASK                  0x4000
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_INV_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_INV_BITS                  1
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_INV_SHIFT                 14

/* BRPHY4_DSP_TAP :: TAP17_C2 :: TRIGGER2_SEL [13:08] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x3f00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x3f00,8)
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_SEL_MASK                  0x3f00
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_SEL_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_SEL_BITS                  6
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER2_SEL_SHIFT                 8

/* BRPHY4_DSP_TAP :: TAP17_C2 :: TRIGGER1_LAT [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_LAT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x80,7)
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_LAT_MASK                  0x0080
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_LAT_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_LAT_BITS                  1
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_LAT_SHIFT                 7

/* BRPHY4_DSP_TAP :: TAP17_C2 :: TRIGGER1_INV [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_INV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x40,6)
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_INV_MASK                  0x0040
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_INV_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_INV_BITS                  1
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_INV_SHIFT                 6

/* BRPHY4_DSP_TAP :: TAP17_C2 :: TRIGGER1_SEL [05:00] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x3f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C2,0x3f,0)
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_SEL_MASK                  0x003f
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_SEL_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_SEL_BITS                  6
#define BRPHY4_DSP_TAP_TAP17_C2_TRIGGER1_SEL_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP17_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP17_C3 :: LA_REARM_ACQ [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C3_LA_REARM_ACQ(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x8000,15)
#define BRPHY4_DSP_TAP_TAP17_C3_LA_REARM_ACQ_MASK                  0x8000
#define BRPHY4_DSP_TAP_TAP17_C3_LA_REARM_ACQ_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C3_LA_REARM_ACQ_BITS                  1
#define BRPHY4_DSP_TAP_TAP17_C3_LA_REARM_ACQ_SHIFT                 15

/* BRPHY4_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_DELAY_EN [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x4000,14)
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_MASK           0x4000
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_ALIGN          0
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_BITS           1
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_DELAY_EN_SHIFT          14

/* BRPHY4_DSP_TAP :: TAP17_C3 :: LA_POSTSTORE [13:06] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x3fc0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C3_LA_POSTSTORE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x3fc0,6)
#define BRPHY4_DSP_TAP_TAP17_C3_LA_POSTSTORE_MASK                  0x3fc0
#define BRPHY4_DSP_TAP_TAP17_C3_LA_POSTSTORE_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C3_LA_POSTSTORE_BITS                  8
#define BRPHY4_DSP_TAP_TAP17_C3_LA_POSTSTORE_SHIFT                 6

/* BRPHY4_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_TYPE [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x20,5)
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_MASK               0x0020
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_BITS               1
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_TYPE_SHIFT              5

/* BRPHY4_DSP_TAP :: TAP17_C3 :: SPARE [04:04] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C3_SPARE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C3_SPARE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x10,4)
#define BRPHY4_DSP_TAP_TAP17_C3_SPARE_MASK                         0x0010
#define BRPHY4_DSP_TAP_TAP17_C3_SPARE_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP17_C3_SPARE_BITS                         1
#define BRPHY4_DSP_TAP_TAP17_C3_SPARE_SHIFT                        4

/* BRPHY4_DSP_TAP :: TAP17_C3 :: LA_CLKENABLE [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C3_LA_CLKENABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x8,3)
#define BRPHY4_DSP_TAP_TAP17_C3_LA_CLKENABLE_MASK                  0x0008
#define BRPHY4_DSP_TAP_TAP17_C3_LA_CLKENABLE_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP17_C3_LA_CLKENABLE_BITS                  1
#define BRPHY4_DSP_TAP_TAP17_C3_LA_CLKENABLE_SHIFT                 3

/* BRPHY4_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_INV [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_INV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x4,2)
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_MASK                0x0004
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_ALIGN               0
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_BITS                1
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_INV_SHIFT               2

/* BRPHY4_DSP_TAP :: TAP17_C3 :: LA_TRIGGER_GATE [01:00] */
#define Wr_BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x3,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP17_C3,0x3,0)
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_MASK               0x0003
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_BITS               2
#define BRPHY4_DSP_TAP_TAP17_C3_LA_TRIGGER_GATE_SHIFT              0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP18_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP18_C0 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_TAP18_C0_RESERVED0_MASK                     0xff00
#define BRPHY4_DSP_TAP_TAP18_C0_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP18_C0_RESERVED0_BITS                     8
#define BRPHY4_DSP_TAP_TAP18_C0_RESERVED0_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP18_C0 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY4_DSP_TAP_TAP18_C0_PEAK_NOISE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP18_C0,0xff,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP18_C0_PEAK_NOISE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP18_C0,0xff,0)
#define BRPHY4_DSP_TAP_TAP18_C0_PEAK_NOISE_MASK                    0x00ff
#define BRPHY4_DSP_TAP_TAP18_C0_PEAK_NOISE_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP18_C0_PEAK_NOISE_BITS                    8
#define BRPHY4_DSP_TAP_TAP18_C0_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP18_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP18_C1 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_TAP18_C1_RESERVED0_MASK                     0xff00
#define BRPHY4_DSP_TAP_TAP18_C1_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP18_C1_RESERVED0_BITS                     8
#define BRPHY4_DSP_TAP_TAP18_C1_RESERVED0_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP18_C1 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY4_DSP_TAP_TAP18_C1_PEAK_NOISE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP18_C1,0xff,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP18_C1_PEAK_NOISE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP18_C1,0xff,0)
#define BRPHY4_DSP_TAP_TAP18_C1_PEAK_NOISE_MASK                    0x00ff
#define BRPHY4_DSP_TAP_TAP18_C1_PEAK_NOISE_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP18_C1_PEAK_NOISE_BITS                    8
#define BRPHY4_DSP_TAP_TAP18_C1_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP18_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP18_C2 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_TAP18_C2_RESERVED0_MASK                     0xff00
#define BRPHY4_DSP_TAP_TAP18_C2_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP18_C2_RESERVED0_BITS                     8
#define BRPHY4_DSP_TAP_TAP18_C2_RESERVED0_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP18_C2 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY4_DSP_TAP_TAP18_C2_PEAK_NOISE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP18_C2,0xff,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP18_C2_PEAK_NOISE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP18_C2,0xff,0)
#define BRPHY4_DSP_TAP_TAP18_C2_PEAK_NOISE_MASK                    0x00ff
#define BRPHY4_DSP_TAP_TAP18_C2_PEAK_NOISE_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP18_C2_PEAK_NOISE_BITS                    8
#define BRPHY4_DSP_TAP_TAP18_C2_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP18_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP18_C3 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_TAP18_C3_RESERVED0_MASK                     0xff00
#define BRPHY4_DSP_TAP_TAP18_C3_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP18_C3_RESERVED0_BITS                     8
#define BRPHY4_DSP_TAP_TAP18_C3_RESERVED0_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP18_C3 :: PEAK_NOISE [07:00] */
#define Wr_BRPHY4_DSP_TAP_TAP18_C3_PEAK_NOISE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP18_C3,0xff,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP18_C3_PEAK_NOISE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP18_C3,0xff,0)
#define BRPHY4_DSP_TAP_TAP18_C3_PEAK_NOISE_MASK                    0x00ff
#define BRPHY4_DSP_TAP_TAP18_C3_PEAK_NOISE_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP18_C3_PEAK_NOISE_BITS                    8
#define BRPHY4_DSP_TAP_TAP18_C3_PEAK_NOISE_SHIFT                   0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP20
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP20 :: reserved0 [15:14] */
#define BRPHY4_DSP_TAP_TAP20_RESERVED0_MASK                        0xc000
#define BRPHY4_DSP_TAP_TAP20_RESERVED0_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP20_RESERVED0_BITS                        2
#define BRPHY4_DSP_TAP_TAP20_RESERVED0_SHIFT                       14

/* BRPHY4_DSP_TAP :: TAP20 :: ENC_FIR_PATH_DELAY_ADJ [13:11] */
#define Wr_BRPHY4_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP20,0x3800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP20,0x3800,11)
#define BRPHY4_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_MASK           0x3800
#define BRPHY4_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY4_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_BITS           3
#define BRPHY4_DSP_TAP_TAP20_ENC_FIR_PATH_DELAY_ADJ_SHIFT          11

/* BRPHY4_DSP_TAP :: TAP20 :: ENC_LMS_PATH_DELAY_ADJ [10:08] */
#define Wr_BRPHY4_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP20,0x700,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP20,0x700,8)
#define BRPHY4_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_MASK           0x0700
#define BRPHY4_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_ALIGN          0
#define BRPHY4_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_BITS           3
#define BRPHY4_DSP_TAP_TAP20_ENC_LMS_PATH_DELAY_ADJ_SHIFT          8

/* BRPHY4_DSP_TAP :: TAP20 :: ECHO_LMS_GAIN [07:06] */
#define Wr_BRPHY4_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP20,0xc0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP20_ECHO_LMS_GAIN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP20,0xc0,6)
#define BRPHY4_DSP_TAP_TAP20_ECHO_LMS_GAIN_MASK                    0x00c0
#define BRPHY4_DSP_TAP_TAP20_ECHO_LMS_GAIN_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP20_ECHO_LMS_GAIN_BITS                    2
#define BRPHY4_DSP_TAP_TAP20_ECHO_LMS_GAIN_SHIFT                   6

/* BRPHY4_DSP_TAP :: TAP20 :: reserved1 [05:04] */
#define BRPHY4_DSP_TAP_TAP20_RESERVED1_MASK                        0x0030
#define BRPHY4_DSP_TAP_TAP20_RESERVED1_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP20_RESERVED1_BITS                        2
#define BRPHY4_DSP_TAP_TAP20_RESERVED1_SHIFT                       4

/* BRPHY4_DSP_TAP :: TAP20 :: TXDIG_PATH_DELAY_CTL [03:00] */
#define Wr_BRPHY4_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP20,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP20,0xf,0)
#define BRPHY4_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_MASK             0x000f
#define BRPHY4_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_ALIGN            0
#define BRPHY4_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_BITS             4
#define BRPHY4_DSP_TAP_TAP20_TXDIG_PATH_DELAY_CTL_SHIFT            0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP21
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP21 :: reserved0 [15:13] */
#define BRPHY4_DSP_TAP_TAP21_RESERVED0_MASK                        0xe000
#define BRPHY4_DSP_TAP_TAP21_RESERVED0_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP21_RESERVED0_BITS                        3
#define BRPHY4_DSP_TAP_TAP21_RESERVED0_SHIFT                       13

/* BRPHY4_DSP_TAP :: TAP21 :: PAUSEPCTPM_ABCD [12:09] */
#define Wr_BRPHY4_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP21,0x1e00,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP21_PAUSEPCTPM_ABCD(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP21,0x1e00,9)
#define BRPHY4_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_MASK                  0x1e00
#define BRPHY4_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_BITS                  4
#define BRPHY4_DSP_TAP_TAP21_PAUSEPCTPM_ABCD_SHIFT                 9

/* BRPHY4_DSP_TAP :: TAP21 :: TX_EN_MON [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP21_TX_EN_MON(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP21,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP21_TX_EN_MON(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP21,0x100,8)
#define BRPHY4_DSP_TAP_TAP21_TX_EN_MON_MASK                        0x0100
#define BRPHY4_DSP_TAP_TAP21_TX_EN_MON_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP21_TX_EN_MON_BITS                        1
#define BRPHY4_DSP_TAP_TAP21_TX_EN_MON_SHIFT                       8

/* BRPHY4_DSP_TAP :: TAP21 :: LINK_CTL_1000T_MON [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP21,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP21_LINK_CTL_1000T_MON(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP21,0x80,7)
#define BRPHY4_DSP_TAP_TAP21_LINK_CTL_1000T_MON_MASK               0x0080
#define BRPHY4_DSP_TAP_TAP21_LINK_CTL_1000T_MON_ALIGN              0
#define BRPHY4_DSP_TAP_TAP21_LINK_CTL_1000T_MON_BITS               1
#define BRPHY4_DSP_TAP_TAP21_LINK_CTL_1000T_MON_SHIFT              7

/* BRPHY4_DSP_TAP :: TAP21 :: REM_RCVR_STATUS_MON [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP21,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP21_REM_RCVR_STATUS_MON(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP21,0x40,6)
#define BRPHY4_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_MASK              0x0040
#define BRPHY4_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_ALIGN             0
#define BRPHY4_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_BITS              1
#define BRPHY4_DSP_TAP_TAP21_REM_RCVR_STATUS_MON_SHIFT             6

/* BRPHY4_DSP_TAP :: TAP21 :: ALIGN_OK_MON [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP21_ALIGN_OK_MON(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP21,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP21_ALIGN_OK_MON(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP21,0x20,5)
#define BRPHY4_DSP_TAP_TAP21_ALIGN_OK_MON_MASK                     0x0020
#define BRPHY4_DSP_TAP_TAP21_ALIGN_OK_MON_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP21_ALIGN_OK_MON_BITS                     1
#define BRPHY4_DSP_TAP_TAP21_ALIGN_OK_MON_SHIFT                    5

/* BRPHY4_DSP_TAP :: TAP21 :: MAIN_PHYC_STATE [04:00] */
#define Wr_BRPHY4_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP21,0x1f,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP21_MAIN_PHYC_STATE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP21,0x1f,0)
#define BRPHY4_DSP_TAP_TAP21_MAIN_PHYC_STATE_MASK                  0x001f
#define BRPHY4_DSP_TAP_TAP21_MAIN_PHYC_STATE_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP21_MAIN_PHYC_STATE_BITS                  5
#define BRPHY4_DSP_TAP_TAP21_MAIN_PHYC_STATE_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP22
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP22 :: KRDONE [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP22_KRDONE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP22,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP22_KRDONE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP22,0x8000,15)
#define BRPHY4_DSP_TAP_TAP22_KRDONE_MASK                           0x8000
#define BRPHY4_DSP_TAP_TAP22_KRDONE_ALIGN                          0
#define BRPHY4_DSP_TAP_TAP22_KRDONE_BITS                           1
#define BRPHY4_DSP_TAP_TAP22_KRDONE_SHIFT                          15

/* BRPHY4_DSP_TAP :: TAP22 :: MAXWAIT_TIMER_DONE [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP22,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP22,0x4000,14)
#define BRPHY4_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_MASK               0x4000
#define BRPHY4_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_BITS               1
#define BRPHY4_DSP_TAP_TAP22_MAXWAIT_TIMER_DONE_SHIFT              14

/* BRPHY4_DSP_TAP :: TAP22 :: LINK_MONITOR_STATE_MON [13:12] */
#define Wr_BRPHY4_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP22,0x3000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP22,0x3000,12)
#define BRPHY4_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_MASK           0x3000
#define BRPHY4_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_ALIGN          0
#define BRPHY4_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_BITS           2
#define BRPHY4_DSP_TAP_TAP22_LINK_MONITOR_STATE_MON_SHIFT          12

/* BRPHY4_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_D [11:09] */
#define Wr_BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP22,0xe00,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_D(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP22,0xe00,9)
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_D_MASK                  0x0e00
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_D_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_D_BITS                  3
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_D_SHIFT                 9

/* BRPHY4_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_C [08:06] */
#define Wr_BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP22,0x1c0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_C(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP22,0x1c0,6)
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_C_MASK                  0x01c0
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_C_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_C_BITS                  3
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_C_SHIFT                 6

/* BRPHY4_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_B [05:03] */
#define Wr_BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP22,0x38,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_B(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP22,0x38,3)
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_B_MASK                  0x0038
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_B_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_B_BITS                  3
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_B_SHIFT                 3

/* BRPHY4_DSP_TAP :: TAP22 :: PHYC_SUBSTATE_A [02:00] */
#define Wr_BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP22,0x7,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_A(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP22,0x7,0)
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_A_MASK                  0x0007
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_A_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_A_BITS                  3
#define BRPHY4_DSP_TAP_TAP22_PHYC_SUBSTATE_A_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP23
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP23 :: reserved0 [15:13] */
#define BRPHY4_DSP_TAP_TAP23_RESERVED0_MASK                        0xe000
#define BRPHY4_DSP_TAP_TAP23_RESERVED0_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP23_RESERVED0_BITS                        3
#define BRPHY4_DSP_TAP_TAP23_RESERVED0_SHIFT                       13

/* BRPHY4_DSP_TAP :: TAP23 :: ALIGN_REDO_MON [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP23_ALIGN_REDO_MON(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP23,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP23_ALIGN_REDO_MON(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP23,0x1000,12)
#define BRPHY4_DSP_TAP_TAP23_ALIGN_REDO_MON_MASK                   0x1000
#define BRPHY4_DSP_TAP_TAP23_ALIGN_REDO_MON_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP23_ALIGN_REDO_MON_BITS                   1
#define BRPHY4_DSP_TAP_TAP23_ALIGN_REDO_MON_SHIFT                  12

/* BRPHY4_DSP_TAP :: TAP23 :: MSEOK2_MON [11:08] */
#define Wr_BRPHY4_DSP_TAP_TAP23_MSEOK2_MON(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP23,0xf00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP23_MSEOK2_MON(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP23,0xf00,8)
#define BRPHY4_DSP_TAP_TAP23_MSEOK2_MON_MASK                       0x0f00
#define BRPHY4_DSP_TAP_TAP23_MSEOK2_MON_ALIGN                      0
#define BRPHY4_DSP_TAP_TAP23_MSEOK2_MON_BITS                       4
#define BRPHY4_DSP_TAP_TAP23_MSEOK2_MON_SHIFT                      8

/* BRPHY4_DSP_TAP :: TAP23 :: MSEOK1_MON [07:04] */
#define Wr_BRPHY4_DSP_TAP_TAP23_MSEOK1_MON(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP23,0xf0,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP23_MSEOK1_MON(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP23,0xf0,4)
#define BRPHY4_DSP_TAP_TAP23_MSEOK1_MON_MASK                       0x00f0
#define BRPHY4_DSP_TAP_TAP23_MSEOK1_MON_ALIGN                      0
#define BRPHY4_DSP_TAP_TAP23_MSEOK1_MON_BITS                       4
#define BRPHY4_DSP_TAP_TAP23_MSEOK1_MON_SHIFT                      4

/* BRPHY4_DSP_TAP :: TAP23 :: ENERGY_DETECT [03:00] */
#define Wr_BRPHY4_DSP_TAP_TAP23_ENERGY_DETECT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP23,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP23_ENERGY_DETECT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP23,0xf,0)
#define BRPHY4_DSP_TAP_TAP23_ENERGY_DETECT_MASK                    0x000f
#define BRPHY4_DSP_TAP_TAP23_ENERGY_DETECT_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP23_ENERGY_DETECT_BITS                    4
#define BRPHY4_DSP_TAP_TAP23_ENERGY_DETECT_SHIFT                   0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP24
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP24 :: PHYC_OUTPUT_OV [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_PHYC_OUTPUT_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x8000,15)
#define BRPHY4_DSP_TAP_TAP24_PHYC_OUTPUT_OV_MASK                   0x8000
#define BRPHY4_DSP_TAP_TAP24_PHYC_OUTPUT_OV_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP24_PHYC_OUTPUT_OV_BITS                   1
#define BRPHY4_DSP_TAP_TAP24_PHYC_OUTPUT_OV_SHIFT                  15

/* BRPHY4_DSP_TAP :: TAP24 :: STABLE_RECENTER_EN [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_STABLE_RECENTER_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x4000,14)
#define BRPHY4_DSP_TAP_TAP24_STABLE_RECENTER_EN_MASK               0x4000
#define BRPHY4_DSP_TAP_TAP24_STABLE_RECENTER_EN_ALIGN              0
#define BRPHY4_DSP_TAP_TAP24_STABLE_RECENTER_EN_BITS               1
#define BRPHY4_DSP_TAP_TAP24_STABLE_RECENTER_EN_SHIFT              14

/* BRPHY4_DSP_TAP :: TAP24 :: PHYC_MSE_FIX [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP24_PHYC_MSE_FIX(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_PHYC_MSE_FIX(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x2000,13)
#define BRPHY4_DSP_TAP_TAP24_PHYC_MSE_FIX_MASK                     0x2000
#define BRPHY4_DSP_TAP_TAP24_PHYC_MSE_FIX_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP24_PHYC_MSE_FIX_BITS                     1
#define BRPHY4_DSP_TAP_TAP24_PHYC_MSE_FIX_SHIFT                    13

/* BRPHY4_DSP_TAP :: TAP24 :: DEGATEDFEPC_ABCD_OV [12:09] */
#define Wr_BRPHY4_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x1e00,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x1e00,9)
#define BRPHY4_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_MASK              0x1e00
#define BRPHY4_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_ALIGN             0
#define BRPHY4_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_BITS              4
#define BRPHY4_DSP_TAP_TAP24_DEGATEDFEPC_ABCD_OV_SHIFT             9

/* BRPHY4_DSP_TAP :: TAP24 :: NBRSTWTCH_OV [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP24_NBRSTWTCH_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_NBRSTWTCH_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x100,8)
#define BRPHY4_DSP_TAP_TAP24_NBRSTWTCH_OV_MASK                     0x0100
#define BRPHY4_DSP_TAP_TAP24_NBRSTWTCH_OV_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP24_NBRSTWTCH_OV_BITS                     1
#define BRPHY4_DSP_TAP_TAP24_NBRSTWTCH_OV_SHIFT                    8

/* BRPHY4_DSP_TAP :: TAP24 :: RC_LPBKFIFO_T_OV [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x80,7)
#define BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_MASK                 0x0080
#define BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_ALIGN                0
#define BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_BITS                 1
#define BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_T_OV_SHIFT                7

/* BRPHY4_DSP_TAP :: TAP24 :: RC_LPBKFIFO_N_OV [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x40,6)
#define BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_MASK                 0x0040
#define BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_ALIGN                0
#define BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_BITS                 1
#define BRPHY4_DSP_TAP_TAP24_RC_LPBKFIFO_N_OV_SHIFT                6

/* BRPHY4_DSP_TAP :: TAP24 :: PCS_RESET_OV [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP24_PCS_RESET_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_PCS_RESET_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x20,5)
#define BRPHY4_DSP_TAP_TAP24_PCS_RESET_OV_MASK                     0x0020
#define BRPHY4_DSP_TAP_TAP24_PCS_RESET_OV_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP24_PCS_RESET_OV_BITS                     1
#define BRPHY4_DSP_TAP_TAP24_PCS_RESET_OV_SHIFT                    5

/* BRPHY4_DSP_TAP :: TAP24 :: PHYC_PCS_RSTATE_OV [04:03] */
#define Wr_BRPHY4_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x18,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x18,3)
#define BRPHY4_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_MASK               0x0018
#define BRPHY4_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_ALIGN              0
#define BRPHY4_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_BITS               2
#define BRPHY4_DSP_TAP_TAP24_PHYC_PCS_RSTATE_OV_SHIFT              3

/* BRPHY4_DSP_TAP :: TAP24 :: LOC_RCVR_STATUS_OV [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x4,2)
#define BRPHY4_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_MASK               0x0004
#define BRPHY4_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_ALIGN              0
#define BRPHY4_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_BITS               1
#define BRPHY4_DSP_TAP_TAP24_LOC_RCVR_STATUS_OV_SHIFT              2

/* BRPHY4_DSP_TAP :: TAP24 :: PHYC_TXMODE_OV [01:00] */
#define Wr_BRPHY4_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP24,0x3,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP24_PHYC_TXMODE_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP24,0x3,0)
#define BRPHY4_DSP_TAP_TAP24_PHYC_TXMODE_OV_MASK                   0x0003
#define BRPHY4_DSP_TAP_TAP24_PHYC_TXMODE_OV_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP24_PHYC_TXMODE_OV_BITS                   2
#define BRPHY4_DSP_TAP_TAP24_PHYC_TXMODE_OV_SHIFT                  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP25
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP25 :: reserved0 [15:15] */
#define BRPHY4_DSP_TAP_TAP25_RESERVED0_MASK                        0x8000
#define BRPHY4_DSP_TAP_TAP25_RESERVED0_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP25_RESERVED0_BITS                        1
#define BRPHY4_DSP_TAP_TAP25_RESERVED0_SHIFT                       15

/* BRPHY4_DSP_TAP :: TAP25 :: KRDONE_OV [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP25_KRDONE_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP25,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP25_KRDONE_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP25,0x4000,14)
#define BRPHY4_DSP_TAP_TAP25_KRDONE_OV_MASK                        0x4000
#define BRPHY4_DSP_TAP_TAP25_KRDONE_OV_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP25_KRDONE_OV_BITS                        1
#define BRPHY4_DSP_TAP_TAP25_KRDONE_OV_SHIFT                       14

/* BRPHY4_DSP_TAP :: TAP25 :: ALIGN_REDO_OV [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP25_ALIGN_REDO_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP25,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP25_ALIGN_REDO_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP25,0x2000,13)
#define BRPHY4_DSP_TAP_TAP25_ALIGN_REDO_OV_MASK                    0x2000
#define BRPHY4_DSP_TAP_TAP25_ALIGN_REDO_OV_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP25_ALIGN_REDO_OV_BITS                    1
#define BRPHY4_DSP_TAP_TAP25_ALIGN_REDO_OV_SHIFT                   13

/* BRPHY4_DSP_TAP :: TAP25 :: RC_ADCFIFO_N_OV [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP25,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_N_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP25,0x1000,12)
#define BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_MASK                  0x1000
#define BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_BITS                  1
#define BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_N_OV_SHIFT                 12

/* BRPHY4_DSP_TAP :: TAP25 :: RC_ADCFIFO_T_OV [11:08] */
#define Wr_BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP25,0xf00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_T_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP25,0xf00,8)
#define BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_MASK                  0x0f00
#define BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_BITS                  4
#define BRPHY4_DSP_TAP_TAP25_RC_ADCFIFO_T_OV_SHIFT                 8

/* BRPHY4_DSP_TAP :: TAP25 :: reserved1 [07:00] */
#define BRPHY4_DSP_TAP_TAP25_RESERVED1_MASK                        0x00ff
#define BRPHY4_DSP_TAP_TAP25_RESERVED1_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP25_RESERVED1_BITS                        8
#define BRPHY4_DSP_TAP_TAP25_RESERVED1_SHIFT                       0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP26
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP26 :: MSE_INPUT_OV [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP26_MSE_INPUT_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP26,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP26_MSE_INPUT_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP26,0x8000,15)
#define BRPHY4_DSP_TAP_TAP26_MSE_INPUT_OV_MASK                     0x8000
#define BRPHY4_DSP_TAP_TAP26_MSE_INPUT_OV_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP26_MSE_INPUT_OV_BITS                     1
#define BRPHY4_DSP_TAP_TAP26_MSE_INPUT_OV_SHIFT                    15

/* BRPHY4_DSP_TAP :: TAP26 :: MSEOK2_OV [14:11] */
#define Wr_BRPHY4_DSP_TAP_TAP26_MSEOK2_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP26,0x7800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP26_MSEOK2_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP26,0x7800,11)
#define BRPHY4_DSP_TAP_TAP26_MSEOK2_OV_MASK                        0x7800
#define BRPHY4_DSP_TAP_TAP26_MSEOK2_OV_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP26_MSEOK2_OV_BITS                        4
#define BRPHY4_DSP_TAP_TAP26_MSEOK2_OV_SHIFT                       11

/* BRPHY4_DSP_TAP :: TAP26 :: MSEOK1_OV [10:07] */
#define Wr_BRPHY4_DSP_TAP_TAP26_MSEOK1_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP26,0x780,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP26_MSEOK1_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP26,0x780,7)
#define BRPHY4_DSP_TAP_TAP26_MSEOK1_OV_MASK                        0x0780
#define BRPHY4_DSP_TAP_TAP26_MSEOK1_OV_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP26_MSEOK1_OV_BITS                        4
#define BRPHY4_DSP_TAP_TAP26_MSEOK1_OV_SHIFT                       7

/* BRPHY4_DSP_TAP :: TAP26 :: ENERGY_DETECT_OV [06:03] */
#define Wr_BRPHY4_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP26,0x78,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP26_ENERGY_DETECT_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP26,0x78,3)
#define BRPHY4_DSP_TAP_TAP26_ENERGY_DETECT_OV_MASK                 0x0078
#define BRPHY4_DSP_TAP_TAP26_ENERGY_DETECT_OV_ALIGN                0
#define BRPHY4_DSP_TAP_TAP26_ENERGY_DETECT_OV_BITS                 4
#define BRPHY4_DSP_TAP_TAP26_ENERGY_DETECT_OV_SHIFT                3

/* BRPHY4_DSP_TAP :: TAP26 :: PCS_INPUT_OV [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP26_PCS_INPUT_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP26,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP26_PCS_INPUT_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP26,0x4,2)
#define BRPHY4_DSP_TAP_TAP26_PCS_INPUT_OV_MASK                     0x0004
#define BRPHY4_DSP_TAP_TAP26_PCS_INPUT_OV_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP26_PCS_INPUT_OV_BITS                     1
#define BRPHY4_DSP_TAP_TAP26_PCS_INPUT_OV_SHIFT                    2

/* BRPHY4_DSP_TAP :: TAP26 :: REM_RCVR_STATUS_OV [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP26,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP26_REM_RCVR_STATUS_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP26,0x2,1)
#define BRPHY4_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_MASK               0x0002
#define BRPHY4_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_ALIGN              0
#define BRPHY4_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_BITS               1
#define BRPHY4_DSP_TAP_TAP26_REM_RCVR_STATUS_OV_SHIFT              1

/* BRPHY4_DSP_TAP :: TAP26 :: ALIGN_OK_OV [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP26_ALIGN_OK_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP26,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP26_ALIGN_OK_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP26,0x1,0)
#define BRPHY4_DSP_TAP_TAP26_ALIGN_OK_OV_MASK                      0x0001
#define BRPHY4_DSP_TAP_TAP26_ALIGN_OK_OV_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP26_ALIGN_OK_OV_BITS                      1
#define BRPHY4_DSP_TAP_TAP26_ALIGN_OK_OV_SHIFT                     0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP27
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP27 :: reserved0 [15:09] */
#define BRPHY4_DSP_TAP_TAP27_RESERVED0_MASK                        0xfe00
#define BRPHY4_DSP_TAP_TAP27_RESERVED0_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP27_RESERVED0_BITS                        7
#define BRPHY4_DSP_TAP_TAP27_RESERVED0_SHIFT                       9

/* BRPHY4_DSP_TAP :: TAP27 :: FILTER_CTL_PAUSE_OV [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP27,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP27,0x100,8)
#define BRPHY4_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_MASK              0x0100
#define BRPHY4_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_ALIGN             0
#define BRPHY4_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_BITS              1
#define BRPHY4_DSP_TAP_TAP27_FILTER_CTL_PAUSE_OV_SHIFT             8

/* BRPHY4_DSP_TAP :: TAP27 :: PAUSEPCTPM_ABCD_OV [07:04] */
#define Wr_BRPHY4_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP27,0xf0,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP27,0xf0,4)
#define BRPHY4_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_MASK               0x00f0
#define BRPHY4_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_ALIGN              0
#define BRPHY4_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_BITS               4
#define BRPHY4_DSP_TAP_TAP27_PAUSEPCTPM_ABCD_OV_SHIFT              4

/* BRPHY4_DSP_TAP :: TAP27 :: AUTONEG_INPUT_OV [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP27,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP27_AUTONEG_INPUT_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP27,0x8,3)
#define BRPHY4_DSP_TAP_TAP27_AUTONEG_INPUT_OV_MASK                 0x0008
#define BRPHY4_DSP_TAP_TAP27_AUTONEG_INPUT_OV_ALIGN                0
#define BRPHY4_DSP_TAP_TAP27_AUTONEG_INPUT_OV_BITS                 1
#define BRPHY4_DSP_TAP_TAP27_AUTONEG_INPUT_OV_SHIFT                3

/* BRPHY4_DSP_TAP :: TAP27 :: LINK_SCAN_100TX_OV [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP27,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP27_LINK_SCAN_100TX_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP27,0x4,2)
#define BRPHY4_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_MASK               0x0004
#define BRPHY4_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_ALIGN              0
#define BRPHY4_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_BITS               1
#define BRPHY4_DSP_TAP_TAP27_LINK_SCAN_100TX_OV_SHIFT              2

/* BRPHY4_DSP_TAP :: TAP27 :: LINK_ENAB_100TX_OV [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP27,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP27_LINK_ENAB_100TX_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP27,0x2,1)
#define BRPHY4_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_MASK               0x0002
#define BRPHY4_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_ALIGN              0
#define BRPHY4_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_BITS               1
#define BRPHY4_DSP_TAP_TAP27_LINK_ENAB_100TX_OV_SHIFT              1

/* BRPHY4_DSP_TAP :: TAP27 :: LINK_CTL_1000T_OV [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP27,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP27_LINK_CTL_1000T_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP27,0x1,0)
#define BRPHY4_DSP_TAP_TAP27_LINK_CTL_1000T_OV_MASK                0x0001
#define BRPHY4_DSP_TAP_TAP27_LINK_CTL_1000T_OV_ALIGN               0
#define BRPHY4_DSP_TAP_TAP27_LINK_CTL_1000T_OV_BITS                1
#define BRPHY4_DSP_TAP_TAP27_LINK_CTL_1000T_OV_SHIFT               0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP28
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP28 :: reserved0 [15:04] */
#define BRPHY4_DSP_TAP_TAP28_RESERVED0_MASK                        0xfff0
#define BRPHY4_DSP_TAP_TAP28_RESERVED0_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP28_RESERVED0_BITS                        12
#define BRPHY4_DSP_TAP_TAP28_RESERVED0_SHIFT                       4

/* BRPHY4_DSP_TAP :: TAP28 :: PLLPRAMP_ABCD_OV [03:00] */
#define Wr_BRPHY4_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP28,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP28,0xf,0)
#define BRPHY4_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_MASK                 0x000f
#define BRPHY4_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_ALIGN                0
#define BRPHY4_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_BITS                 4
#define BRPHY4_DSP_TAP_TAP28_PLLPRAMP_ABCD_OV_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP29
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP29 :: TIMER_MODE_D_FORCE [15:14] */
#define Wr_BRPHY4_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP29,0xc000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP29_TIMER_MODE_D_FORCE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP29,0xc000,14)
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_MASK               0xc000
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_BITS               2
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_D_FORCE_SHIFT              14

/* BRPHY4_DSP_TAP :: TAP29 :: TIMER_MODE_C_FORCE [13:12] */
#define Wr_BRPHY4_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP29,0x3000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP29_TIMER_MODE_C_FORCE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP29,0x3000,12)
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_MASK               0x3000
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_BITS               2
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_C_FORCE_SHIFT              12

/* BRPHY4_DSP_TAP :: TAP29 :: TIMER_MODE_B_FORCE [11:10] */
#define Wr_BRPHY4_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP29,0xc00,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP29_TIMER_MODE_B_FORCE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP29,0xc00,10)
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_MASK               0x0c00
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_BITS               2
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_B_FORCE_SHIFT              10

/* BRPHY4_DSP_TAP :: TAP29 :: TIMER_MODE_A_FORCE [09:08] */
#define Wr_BRPHY4_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP29,0x300,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP29_TIMER_MODE_A_FORCE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP29,0x300,8)
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_MASK               0x0300
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_BITS               2
#define BRPHY4_DSP_TAP_TAP29_TIMER_MODE_A_FORCE_SHIFT              8

/* BRPHY4_DSP_TAP :: TAP29 :: MAINSTATE_FORCE [07:04] */
#define Wr_BRPHY4_DSP_TAP_TAP29_MAINSTATE_FORCE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP29,0xf0,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP29_MAINSTATE_FORCE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP29,0xf0,4)
#define BRPHY4_DSP_TAP_TAP29_MAINSTATE_FORCE_MASK                  0x00f0
#define BRPHY4_DSP_TAP_TAP29_MAINSTATE_FORCE_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP29_MAINSTATE_FORCE_BITS                  4
#define BRPHY4_DSP_TAP_TAP29_MAINSTATE_FORCE_SHIFT                 4

/* BRPHY4_DSP_TAP :: TAP29 :: FORCE_PHYC_STATE [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP29,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP29_FORCE_PHYC_STATE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP29,0x8,3)
#define BRPHY4_DSP_TAP_TAP29_FORCE_PHYC_STATE_MASK                 0x0008
#define BRPHY4_DSP_TAP_TAP29_FORCE_PHYC_STATE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP29_FORCE_PHYC_STATE_BITS                 1
#define BRPHY4_DSP_TAP_TAP29_FORCE_PHYC_STATE_SHIFT                3

/* BRPHY4_DSP_TAP :: TAP29 :: HOLD_IN_ALT [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP29_HOLD_IN_ALT(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP29,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP29_HOLD_IN_ALT(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP29,0x4,2)
#define BRPHY4_DSP_TAP_TAP29_HOLD_IN_ALT_MASK                      0x0004
#define BRPHY4_DSP_TAP_TAP29_HOLD_IN_ALT_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP29_HOLD_IN_ALT_BITS                      1
#define BRPHY4_DSP_TAP_TAP29_HOLD_IN_ALT_SHIFT                     2

/* BRPHY4_DSP_TAP :: TAP29 :: FORCE_ALT_STATE_PATH [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP29,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP29,0x2,1)
#define BRPHY4_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_MASK             0x0002
#define BRPHY4_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_ALIGN            0
#define BRPHY4_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_BITS             1
#define BRPHY4_DSP_TAP_TAP29_FORCE_ALT_STATE_PATH_SHIFT            1

/* BRPHY4_DSP_TAP :: TAP29 :: PHYC_FAST_STATE_MODE [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP29,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP29,0x1,0)
#define BRPHY4_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_MASK             0x0001
#define BRPHY4_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_ALIGN            0
#define BRPHY4_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_BITS             1
#define BRPHY4_DSP_TAP_TAP29_PHYC_FAST_STATE_MODE_SHIFT            0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP30
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP30 :: reserved0 [15:12] */
#define BRPHY4_DSP_TAP_TAP30_RESERVED0_MASK                        0xf000
#define BRPHY4_DSP_TAP_TAP30_RESERVED0_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP30_RESERVED0_BITS                        4
#define BRPHY4_DSP_TAP_TAP30_RESERVED0_SHIFT                       12

/* BRPHY4_DSP_TAP :: TAP30 :: SUBSTATE_D_FORCE [11:09] */
#define Wr_BRPHY4_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP30,0xe00,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP30_SUBSTATE_D_FORCE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP30,0xe00,9)
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_D_FORCE_MASK                 0x0e00
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_D_FORCE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_D_FORCE_BITS                 3
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_D_FORCE_SHIFT                9

/* BRPHY4_DSP_TAP :: TAP30 :: SUBSTATE_C_FORCE [08:06] */
#define Wr_BRPHY4_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP30,0x1c0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP30_SUBSTATE_C_FORCE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP30,0x1c0,6)
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_C_FORCE_MASK                 0x01c0
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_C_FORCE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_C_FORCE_BITS                 3
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_C_FORCE_SHIFT                6

/* BRPHY4_DSP_TAP :: TAP30 :: SUBSTATE_B_FORCE [05:03] */
#define Wr_BRPHY4_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP30,0x38,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP30_SUBSTATE_B_FORCE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP30,0x38,3)
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_B_FORCE_MASK                 0x0038
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_B_FORCE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_B_FORCE_BITS                 3
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_B_FORCE_SHIFT                3

/* BRPHY4_DSP_TAP :: TAP30 :: SUBSTATE_A_FORCE [02:00] */
#define Wr_BRPHY4_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP30,0x7,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP30_SUBSTATE_A_FORCE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP30,0x7,0)
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_A_FORCE_MASK                 0x0007
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_A_FORCE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_A_FORCE_BITS                 3
#define BRPHY4_DSP_TAP_TAP30_SUBSTATE_A_FORCE_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP31_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP31_C0 :: SDSEL_OV [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x8000,15)
#define BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_MASK                      0x8000
#define BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_ALIGN                     0
#define BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_BITS                      1
#define BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_SHIFT                     15

/* BRPHY4_DSP_TAP :: TAP31_C0 :: SDSEL_OV_EN [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x4000,14)
#define BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_EN_MASK                   0x4000
#define BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_EN_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_EN_BITS                   1
#define BRPHY4_DSP_TAP_TAP31_C0_SDSEL_OV_EN_SHIFT                  14

/* BRPHY4_DSP_TAP :: TAP31_C0 :: ADC_BER_TPOUT_EN [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x2000,13)
#define BRPHY4_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_MASK              0x2000
#define BRPHY4_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_ALIGN             0
#define BRPHY4_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_BITS              1
#define BRPHY4_DSP_TAP_TAP31_C0_ADC_BER_TPOUT_EN_SHIFT             13

/* BRPHY4_DSP_TAP :: TAP31_C0 :: SWAPCD_OV [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP31_C0_SWAPCD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP31_C0_SWAPCD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x1000,12)
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPCD_OV_MASK                     0x1000
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPCD_OV_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPCD_OV_BITS                     1
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPCD_OV_SHIFT                    12

/* BRPHY4_DSP_TAP :: TAP31_C0 :: SWAPAB_OV [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x800,11)
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_OV_MASK                     0x0800
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_OV_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_OV_BITS                     1
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_OV_SHIFT                    11

/* BRPHY4_DSP_TAP :: TAP31_C0 :: SWAPAB_CD_OV_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP31_C0,0x400,10)
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_MASK               0x0400
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_ALIGN              0
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_BITS               1
#define BRPHY4_DSP_TAP_TAP31_C0_SWAPAB_CD_OV_EN_SHIFT              10

/* BRPHY4_DSP_TAP :: TAP31_C0 :: reserved0 [09:00] */
#define BRPHY4_DSP_TAP_TAP31_C0_RESERVED0_MASK                     0x03ff
#define BRPHY4_DSP_TAP_TAP31_C0_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP31_C0_RESERVED0_BITS                     10
#define BRPHY4_DSP_TAP_TAP31_C0_RESERVED0_SHIFT                    0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP32_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP32_C0 :: reserved0 [15:09] */
#define BRPHY4_DSP_TAP_TAP32_C0_RESERVED0_MASK                     0xfe00
#define BRPHY4_DSP_TAP_TAP32_C0_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP32_C0_RESERVED0_BITS                     7
#define BRPHY4_DSP_TAP_TAP32_C0_RESERVED0_SHIFT                    9

/* BRPHY4_DSP_TAP :: TAP32_C0 :: COEFF_RAM_TM_CTRL [08:04] */
#define Wr_BRPHY4_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x1f0,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x1f0,4)
#define BRPHY4_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_MASK             0x01f0
#define BRPHY4_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_ALIGN            0
#define BRPHY4_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_BITS             5
#define BRPHY4_DSP_TAP_TAP32_C0_COEFF_RAM_TM_CTRL_SHIFT            4

/* BRPHY4_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_D [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x8,3)
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_MASK         0x0008
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_ALIGN        0
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_BITS         1
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_D_SHIFT        3

/* BRPHY4_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_C [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x4,2)
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_MASK         0x0004
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_ALIGN        0
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_BITS         1
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_C_SHIFT        2

/* BRPHY4_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_AB [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x2,1)
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_MASK        0x0002
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_ALIGN       0
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_BITS        1
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_AB_SHIFT       1

/* BRPHY4_DSP_TAP :: TAP32_C0 :: TESTMODE_SYNC_PULSE_A [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP32_C0,0x1,0)
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_MASK         0x0001
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_ALIGN        0
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_BITS         1
#define BRPHY4_DSP_TAP_TAP32_C0_TESTMODE_SYNC_PULSE_A_SHIFT        0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FDFE_OV_RD
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_MSB [15:14] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0xc000,14,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0xc000,14)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_MASK             0xc000
#define BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_ALIGN            0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_BITS             2
#define BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_MSB_SHIFT            14

/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: MSE_THRESH4_LSB [13:13] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x2000,13)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_MASK             0x2000
#define BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_ALIGN            0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_BITS             1
#define BRPHY4_DSP_TAP_FDFE_OV_RD_MSE_THRESH4_LSB_SHIFT            13

/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: BETA_OV [12:12] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x1000,12)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_MASK                     0x1000
#define BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_ALIGN                    0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_BITS                     1
#define BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_SHIFT                    12

/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: BETA_OV_VAL [11:09] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0xe00,9,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0xe00,9)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_MASK                 0x0e00
#define BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_ALIGN                0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_BITS                 3
#define BRPHY4_DSP_TAP_FDFE_OV_RD_BETA_OV_VAL_SHIFT                9

/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: FDFE_MSE_SEL_OV [08:08] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x100,8)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_MASK             0x0100
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_ALIGN            0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_BITS             1
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_MSE_SEL_OV_SHIFT            8

/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: FDFE_CLEAR_OV [07:07] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x80,7)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_MASK               0x0080
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_ALIGN              0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_BITS               1
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_CLEAR_OV_SHIFT              7

/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: FDFE_OUTEN_OV [06:06] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x40,6)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_MASK               0x0040
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_ALIGN              0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_BITS               1
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OUTEN_OV_SHIFT              6

/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: FDFE_UPEN_OV [05:05] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x20,5)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_MASK                0x0020
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_ALIGN               0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_BITS                1
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_UPEN_OV_SHIFT               5

/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: FDFE_OV_EN [04:04] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0x10,4)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_MASK                  0x0010
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_ALIGN                 0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_BITS                  1
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_OV_EN_SHIFT                 4

/* BRPHY4_DSP_TAP :: FDFE_OV_RD :: FDFE_RD_SEL [03:00] */
#define Wr_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_OV_RD,0xf,0)
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_MASK                 0x000f
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_ALIGN                0
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_BITS                 4
#define BRPHY4_DSP_TAP_FDFE_OV_RD_FDFE_RD_SEL_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FDFE_COEFF
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FDFE_COEFF :: FDFE_COEFF [15:00] */
#define Wr_BRPHY4_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) WriteReg16(BRPHY4_DSP_TAP_FDFE_COEFF,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_COEFF_FDFE_COEFF(x) ReadReg16(BRPHY4_DSP_TAP_FDFE_COEFF)
#define BRPHY4_DSP_TAP_FDFE_COEFF_FDFE_COEFF_MASK                  0xffff
#define BRPHY4_DSP_TAP_FDFE_COEFF_FDFE_COEFF_ALIGN                 0
#define BRPHY4_DSP_TAP_FDFE_COEFF_FDFE_COEFF_BITS                  16
#define BRPHY4_DSP_TAP_FDFE_COEFF_FDFE_COEFF_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FDFE_BETA_THRESHOLD
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_3 [15:12] */
#define Wr_BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD,0xf000,12)
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_MASK   0xf000
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_ALIGN  0
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_BITS   4
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_3_SHIFT  12

/* BRPHY4_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_2 [11:08] */
#define Wr_BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD,0xf00,8)
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_MASK   0x0f00
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_ALIGN  0
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_BITS   4
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_2_SHIFT  8

/* BRPHY4_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_1 [07:04] */
#define Wr_BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD,0xf0,4)
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_MASK   0x00f0
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_ALIGN  0
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_BITS   4
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_1_SHIFT  4

/* BRPHY4_DSP_TAP :: FDFE_BETA_THRESHOLD :: BETA_THRESHOLD_0 [03:00] */
#define Wr_BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) WriteRegBits16(BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0(x) ReadRegBits16(BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD,0xf,0)
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_MASK   0x000f
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_ALIGN  0
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_BITS   4
#define BRPHY4_DSP_TAP_FDFE_BETA_THRESHOLD_BETA_THRESHOLD_0_SHIFT  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP33_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SD_EN [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x8000,15)
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_MASK               0x8000
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_ALIGN              0
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_BITS               1
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SD_EN_SHIFT              15

/* BRPHY4_DSP_TAP :: TAP33_C0 :: EEE_MASK_MSE_EN [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x4000,14)
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_MASK               0x4000
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_ALIGN              0
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_BITS               1
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_MASK_MSE_EN_SHIFT              14

/* BRPHY4_DSP_TAP :: TAP33_C0 :: EEE_PHYC_STATUS_TO_LED [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x2000,13)
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_MASK        0x2000
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_ALIGN       0
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_BITS        1
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_PHYC_STATUS_TO_LED_SHIFT       13

/* BRPHY4_DSP_TAP :: TAP33_C0 :: EEE_PLL_TEST_MODE [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x1000,12)
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_MASK             0x1000
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_ALIGN            0
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_BITS             1
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_PLL_TEST_MODE_SHIFT            12

/* BRPHY4_DSP_TAP :: TAP33_C0 :: SPARE11 [11:11] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_SPARE11(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_SPARE11(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x800,11)
#define BRPHY4_DSP_TAP_TAP33_C0_SPARE11_MASK                       0x0800
#define BRPHY4_DSP_TAP_TAP33_C0_SPARE11_ALIGN                      0
#define BRPHY4_DSP_TAP_TAP33_C0_SPARE11_BITS                       1
#define BRPHY4_DSP_TAP_TAP33_C0_SPARE11_SHIFT                      11

/* BRPHY4_DSP_TAP :: TAP33_C0 :: EEE_AFE_STOPPABLE [10:10] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x400,10)
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_MASK             0x0400
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_ALIGN            0
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_BITS             1
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_AFE_STOPPABLE_SHIFT            10

/* BRPHY4_DSP_TAP :: TAP33_C0 :: EEE_CLOCK_STOPPABLE [09:09] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x200,9)
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_MASK           0x0200
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_ALIGN          0
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_BITS           1
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_CLOCK_STOPPABLE_SHIFT          9

/* BRPHY4_DSP_TAP :: TAP33_C0 :: EEE_SD_SEL [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_EEE_SD_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x100,8)
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_SD_SEL_MASK                    0x0100
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_SD_SEL_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_SD_SEL_BITS                    1
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_SD_SEL_SHIFT                   8

/* BRPHY4_DSP_TAP :: TAP33_C0 :: MAXMSEOK1_CHG_EN [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x80,7)
#define BRPHY4_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_MASK              0x0080
#define BRPHY4_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_ALIGN             0
#define BRPHY4_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_BITS              1
#define BRPHY4_DSP_TAP_TAP33_C0_MAXMSEOK1_CHG_EN_SHIFT             7

/* BRPHY4_DSP_TAP :: TAP33_C0 :: LPI_QUIET_SCALE [06:05] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x60,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x60,5)
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_MASK               0x0060
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_BITS               2
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_QUIET_SCALE_SHIFT              5

/* BRPHY4_DSP_TAP :: TAP33_C0 :: LPI_TRACK_MODE [04:03] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x18,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_LPI_TRACK_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x18,3)
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_MASK                0x0018
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_ALIGN               0
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_BITS                2
#define BRPHY4_DSP_TAP_TAP33_C0_LPI_TRACK_MODE_SHIFT               3

/* BRPHY4_DSP_TAP :: TAP33_C0 :: EEE_FREQ_UNLOCK [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x4,2)
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_MASK               0x0004
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_ALIGN              0
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_BITS               1
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_FREQ_UNLOCK_SHIFT              2

/* BRPHY4_DSP_TAP :: TAP33_C0 :: EEE_QUICK_ALIGN [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x2,1)
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_MASK               0x0002
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_ALIGN              0
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_BITS               1
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_QUICK_ALIGN_SHIFT              1

/* BRPHY4_DSP_TAP :: TAP33_C0 :: EEE_SD300 [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C0_EEE_SD300(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C0_EEE_SD300(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C0,0x1,0)
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_SD300_MASK                     0x0001
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_SD300_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_SD300_BITS                     1
#define BRPHY4_DSP_TAP_TAP33_C0_EEE_SD300_SHIFT                    0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP33_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP33_C1 :: SD_ASSERT_THD [15:08] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C1,0xff00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C1_SD_ASSERT_THD(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C1,0xff00,8)
#define BRPHY4_DSP_TAP_TAP33_C1_SD_ASSERT_THD_MASK                 0xff00
#define BRPHY4_DSP_TAP_TAP33_C1_SD_ASSERT_THD_ALIGN                0
#define BRPHY4_DSP_TAP_TAP33_C1_SD_ASSERT_THD_BITS                 8
#define BRPHY4_DSP_TAP_TAP33_C1_SD_ASSERT_THD_SHIFT                8

/* BRPHY4_DSP_TAP :: TAP33_C1 :: SD_DEASSERT_THD [07:00] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C1,0xff,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C1_SD_DEASSERT_THD(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C1,0xff,0)
#define BRPHY4_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_MASK               0x00ff
#define BRPHY4_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_ALIGN              0
#define BRPHY4_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_BITS               8
#define BRPHY4_DSP_TAP_TAP33_C1_SD_DEASSERT_THD_SHIFT              0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP33_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP33_C2 :: EEE_PHASE_REACQ_TUNE [15:14] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0xc000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0xc000,14)
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_MASK          0xc000
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_ALIGN         0
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_BITS          2
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_PHASE_REACQ_TUNE_SHIFT         14

/* BRPHY4_DSP_TAP :: TAP33_C2 :: EEE_WAIT_SCR_LOCK_N [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0x2000,13)
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_MASK           0x2000
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_ALIGN          0
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_BITS           1
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_WAIT_SCR_LOCK_N_SHIFT          13

/* BRPHY4_DSP_TAP :: TAP33_C2 :: LOC_RCVR_WAIT_ALIGNC_N [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0x1000,12)
#define BRPHY4_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_MASK        0x1000
#define BRPHY4_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_ALIGN       0
#define BRPHY4_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_BITS        1
#define BRPHY4_DSP_TAP_TAP33_C2_LOC_RCVR_WAIT_ALIGNC_N_SHIFT       12

/* BRPHY4_DSP_TAP :: TAP33_C2 :: EEE_WAKEMZ_TUNE [11:08] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0xf00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0xf00,8)
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_MASK               0x0f00
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_BITS               4
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_WAKEMZ_TUNE_SHIFT              8

/* BRPHY4_DSP_TAP :: TAP33_C2 :: EEE_RX_ON_TUNE [07:04] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0xf0,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0xf0,4)
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_MASK                0x00f0
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_ALIGN               0
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_BITS                4
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_RX_ON_TUNE_SHIFT               4

/* BRPHY4_DSP_TAP :: TAP33_C2 :: EEE_SLAVE_WAIT_TUNE [03:00] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C2,0xf,0)
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_MASK           0x000f
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_ALIGN          0
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_BITS           4
#define BRPHY4_DSP_TAP_TAP33_C2_EEE_SLAVE_WAIT_TUNE_SHIFT          0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP33_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP33_C3 :: spare_reg [15:02] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C3_spare_reg(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C3,0xfffc,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C3_spare_reg(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C3,0xfffc,2)
#define BRPHY4_DSP_TAP_TAP33_C3_SPARE_REG_MASK                     0xfffc
#define BRPHY4_DSP_TAP_TAP33_C3_SPARE_REG_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP33_C3_SPARE_REG_BITS                     14
#define BRPHY4_DSP_TAP_TAP33_C3_SPARE_REG_SHIFT                    2

/* BRPHY4_DSP_TAP :: TAP33_C3 :: PWRDNTX_STAGGER_EN [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C3,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C3,0x2,1)
#define BRPHY4_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_MASK            0x0002
#define BRPHY4_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_ALIGN           0
#define BRPHY4_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_BITS            1
#define BRPHY4_DSP_TAP_TAP33_C3_PWRDNTX_STAGGER_EN_SHIFT           1

/* BRPHY4_DSP_TAP :: TAP33_C3 :: PWRDNRX_STAGGER_EN [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP33_C3,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP33_C3,0x1,0)
#define BRPHY4_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_MASK            0x0001
#define BRPHY4_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_ALIGN           0
#define BRPHY4_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_BITS            1
#define BRPHY4_DSP_TAP_TAP33_C3_PWRDNRX_STAGGER_EN_SHIFT           0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP34_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP34_C0 :: EEE_PLLILPFRZ [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x8000,15)
#define BRPHY4_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_MASK                 0x8000
#define BRPHY4_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_ALIGN                0
#define BRPHY4_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_BITS                 1
#define BRPHY4_DSP_TAP_TAP34_C0_EEE_PLLILPFRZ_SHIFT                15

/* BRPHY4_DSP_TAP :: TAP34_C0 :: PLLILPFRZ_OV [14:14] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x4000,14)
#define BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_MASK                  0x4000
#define BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_BITS                  1
#define BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_OV_SHIFT                 14

/* BRPHY4_DSP_TAP :: TAP34_C0 :: PLLILPFRZ [13:13] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x2000,13)
#define BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_MASK                     0x2000
#define BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_BITS                     1
#define BRPHY4_DSP_TAP_TAP34_C0_PLLILPFRZ_SHIFT                    13

/* BRPHY4_DSP_TAP :: TAP34_C0 :: EEE_100TX_UP16_SEL [12:12] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x1000,12)
#define BRPHY4_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_MASK            0x1000
#define BRPHY4_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_ALIGN           0
#define BRPHY4_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_BITS            1
#define BRPHY4_DSP_TAP_TAP34_C0_EEE_100TX_UP16_SEL_SHIFT           12

/* BRPHY4_DSP_TAP :: TAP34_C0 :: PLLFRST_SCALE [11:10] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0xc00,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_PLLFRST_SCALE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0xc00,10)
#define BRPHY4_DSP_TAP_TAP34_C0_PLLFRST_SCALE_MASK                 0x0c00
#define BRPHY4_DSP_TAP_TAP34_C0_PLLFRST_SCALE_ALIGN                0
#define BRPHY4_DSP_TAP_TAP34_C0_PLLFRST_SCALE_BITS                 2
#define BRPHY4_DSP_TAP_TAP34_C0_PLLFRST_SCALE_SHIFT                10

/* BRPHY4_DSP_TAP :: TAP34_C0 :: INT_LP_GAIN [09:08] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x300,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_INT_LP_GAIN(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x300,8)
#define BRPHY4_DSP_TAP_TAP34_C0_INT_LP_GAIN_MASK                   0x0300
#define BRPHY4_DSP_TAP_TAP34_C0_INT_LP_GAIN_ALIGN                  0
#define BRPHY4_DSP_TAP_TAP34_C0_INT_LP_GAIN_BITS                   2
#define BRPHY4_DSP_TAP_TAP34_C0_INT_LP_GAIN_SHIFT                  8

/* BRPHY4_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_EST_AVERAGE_SEL [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x80,7)
#define BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_MASK    0x0080
#define BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_ALIGN   0
#define BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_BITS    1
#define BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_EST_AVERAGE_SEL_SHIFT   7

/* BRPHY4_DSP_TAP :: TAP34_C0 :: FREQ_DRIFT_SCALE [06:04] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x70,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x70,4)
#define BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_MASK              0x0070
#define BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_ALIGN             0
#define BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_BITS              3
#define BRPHY4_DSP_TAP_TAP34_C0_FREQ_DRIFT_SCALE_SHIFT             4

/* BRPHY4_DSP_TAP :: TAP34_C0 :: KI [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_KI(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_KI(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x8,3)
#define BRPHY4_DSP_TAP_TAP34_C0_KI_MASK                            0x0008
#define BRPHY4_DSP_TAP_TAP34_C0_KI_ALIGN                           0
#define BRPHY4_DSP_TAP_TAP34_C0_KI_BITS                            1
#define BRPHY4_DSP_TAP_TAP34_C0_KI_SHIFT                           3

/* BRPHY4_DSP_TAP :: TAP34_C0 :: KP [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_KP(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_KP(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x4,2)
#define BRPHY4_DSP_TAP_TAP34_C0_KP_MASK                            0x0004
#define BRPHY4_DSP_TAP_TAP34_C0_KP_ALIGN                           0
#define BRPHY4_DSP_TAP_TAP34_C0_KP_BITS                            1
#define BRPHY4_DSP_TAP_TAP34_C0_KP_SHIFT                           2

/* BRPHY4_DSP_TAP :: TAP34_C0 :: KV [01:00] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C0_KV(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x3,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C0_KV(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C0,0x3,0)
#define BRPHY4_DSP_TAP_TAP34_C0_KV_MASK                            0x0003
#define BRPHY4_DSP_TAP_TAP34_C0_KV_ALIGN                           0
#define BRPHY4_DSP_TAP_TAP34_C0_KV_BITS                            2
#define BRPHY4_DSP_TAP_TAP34_C0_KV_SHIFT                           0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP34_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP34_C1 :: SPARE [15:12] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C1_SPARE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C1,0xf000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C1_SPARE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C1,0xf000,12)
#define BRPHY4_DSP_TAP_TAP34_C1_SPARE_MASK                         0xf000
#define BRPHY4_DSP_TAP_TAP34_C1_SPARE_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP34_C1_SPARE_BITS                         4
#define BRPHY4_DSP_TAP_TAP34_C1_SPARE_SHIFT                        12

/* BRPHY4_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_10 [11:08] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C1,0xf00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C1,0xf00,8)
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_MASK             0x0f00
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_ALIGN            0
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_BITS             4
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_10_SHIFT            8

/* BRPHY4_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_01 [07:04] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C1,0xf0,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C1,0xf0,4)
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_MASK             0x00f0
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_ALIGN            0
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_BITS             4
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_01_SHIFT            4

/* BRPHY4_DSP_TAP :: TAP34_C1 :: PLL_BW_CTL_EEE_00 [03:00] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C1,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C1,0xf,0)
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_MASK             0x000f
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_ALIGN            0
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_BITS             4
#define BRPHY4_DSP_TAP_TAP34_C1_PLL_BW_CTL_EEE_00_SHIFT            0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP34_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_CH_SEL [15:14] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0xc000,14,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0xc000,14)
#define BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_MASK           0xc000
#define BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_ALIGN          0
#define BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_BITS           2
#define BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_CH_SEL_SHIFT          14

/* BRPHY4_DSP_TAP :: TAP34_C2 :: PHASECTL_TPO_BUS_SEL [13:11] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0x3800,11,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0x3800,11)
#define BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_MASK          0x3800
#define BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_ALIGN         0
#define BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_BITS          3
#define BRPHY4_DSP_TAP_TAP34_C2_PHASECTL_TPO_BUS_SEL_SHIFT         11

/* BRPHY4_DSP_TAP :: TAP34_C2 :: reserved0 [10:09] */
#define BRPHY4_DSP_TAP_TAP34_C2_RESERVED0_MASK                     0x0600
#define BRPHY4_DSP_TAP_TAP34_C2_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP34_C2_RESERVED0_BITS                     2
#define BRPHY4_DSP_TAP_TAP34_C2_RESERVED0_SHIFT                    9

/* BRPHY4_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_10 [08:06] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0x1c0,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0x1c0,6)
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_MASK               0x01c0
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_ALIGN              0
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_BITS               3
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_10_SHIFT              6

/* BRPHY4_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_01 [05:03] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0x38,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0x38,3)
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_MASK               0x0038
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_ALIGN              0
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_BITS               3
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_01_SHIFT              3

/* BRPHY4_DSP_TAP :: TAP34_C2 :: TX_BWSEL_EEE_00 [02:00] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0x7,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP34_C2,0x7,0)
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_MASK               0x0007
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_ALIGN              0
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_BITS               3
#define BRPHY4_DSP_TAP_TAP34_C2_TX_BWSEL_EEE_00_SHIFT              0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP34_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP34_C3 :: PHASECTL_TPO [15:00] */
#define Wr_BRPHY4_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) WriteReg16(BRPHY4_DSP_TAP_TAP34_C3,x)
#define Rd_BRPHY4_DSP_TAP_TAP34_C3_PHASECTL_TPO(x) ReadReg16(BRPHY4_DSP_TAP_TAP34_C3)
#define BRPHY4_DSP_TAP_TAP34_C3_PHASECTL_TPO_MASK                  0xffff
#define BRPHY4_DSP_TAP_TAP34_C3_PHASECTL_TPO_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP34_C3_PHASECTL_TPO_BITS                  16
#define BRPHY4_DSP_TAP_TAP34_C3_PHASECTL_TPO_SHIFT                 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP35_C0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP35_C0 :: LPI_RX_TW3_TIMER [15:13] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0xe000,13,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0xe000,13)
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_MASK              0xe000
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_ALIGN             0
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_BITS              3
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW3_TIMER_SHIFT             13

/* BRPHY4_DSP_TAP :: TAP35_C0 :: LPI_RX_TW2_TIMER [12:10] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0x1c00,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0x1c00,10)
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_MASK              0x1c00
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_ALIGN             0
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_BITS              3
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW2_TIMER_SHIFT             10

/* BRPHY4_DSP_TAP :: TAP35_C0 :: LPI_RX_TW1_TIMER [09:07] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0x380,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0x380,7)
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_MASK              0x0380
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_ALIGN             0
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_BITS              3
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_RX_TW1_TIMER_SHIFT             7

/* BRPHY4_DSP_TAP :: TAP35_C0 :: LPI_TX_TQ_TIMER [06:04] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0x70,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0x70,4)
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_MASK               0x0070
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_ALIGN              0
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_BITS               3
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TQ_TIMER_SHIFT              4

/* BRPHY4_DSP_TAP :: TAP35_C0 :: LPI_TX_TS_TIMER [03:02] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0xc,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0xc,2)
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_MASK               0x000c
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_ALIGN              0
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_BITS               2
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TS_TIMER_SHIFT              2

/* BRPHY4_DSP_TAP :: TAP35_C0 :: LPI_TX_TR_TIMER [01:00] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0x3,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C0,0x3,0)
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_MASK               0x0003
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_ALIGN              0
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_BITS               2
#define BRPHY4_DSP_TAP_TAP35_C0_LPI_TX_TR_TIMER_SHIFT              0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP35_C1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP35_C1 :: LPI_RX_TS3_TIMER [15:10] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C1,0xfc00,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C1,0xfc00,10)
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_MASK              0xfc00
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_ALIGN             0
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_BITS              6
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS3_TIMER_SHIFT             10

/* BRPHY4_DSP_TAP :: TAP35_C1 :: LPI_RX_TS2_TIMER [09:04] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C1,0x3f0,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C1,0x3f0,4)
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_MASK              0x03f0
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_ALIGN             0
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_BITS              6
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS2_TIMER_SHIFT             4

/* BRPHY4_DSP_TAP :: TAP35_C1 :: LPI_RX_TS1_TIMER [03:00] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C1,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C1,0xf,0)
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_MASK              0x000f
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_ALIGN             0
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_BITS              4
#define BRPHY4_DSP_TAP_TAP35_C1_LPI_RX_TS1_TIMER_SHIFT             0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP35_C2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP35_C2 :: reserved0 [15:14] */
#define BRPHY4_DSP_TAP_TAP35_C2_RESERVED0_MASK                     0xc000
#define BRPHY4_DSP_TAP_TAP35_C2_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP35_C2_RESERVED0_BITS                     2
#define BRPHY4_DSP_TAP_TAP35_C2_RESERVED0_SHIFT                    14

/* BRPHY4_DSP_TAP :: TAP35_C2 :: SPARE [13:10] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C2_SPARE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x3c00,10,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C2_SPARE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x3c00,10)
#define BRPHY4_DSP_TAP_TAP35_C2_SPARE_MASK                         0x3c00
#define BRPHY4_DSP_TAP_TAP35_C2_SPARE_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP35_C2_SPARE_BITS                         4
#define BRPHY4_DSP_TAP_TAP35_C2_SPARE_SHIFT                        10

/* BRPHY4_DSP_TAP :: TAP35_C2 :: LPI_TX_BRCM_MODE [09:09] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x200,9)
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_MASK              0x0200
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_ALIGN             0
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_BITS              1
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_TX_BRCM_MODE_SHIFT             9

/* BRPHY4_DSP_TAP :: TAP35_C2 :: LPI_RX_TI_TIMER [08:08] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x100,8)
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_MASK               0x0100
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_ALIGN              0
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_BITS               1
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_TI_TIMER_SHIFT              8

/* BRPHY4_DSP_TAP :: TAP35_C2 :: GPCS_ERRTH_SEL [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x80,7)
#define BRPHY4_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_MASK                0x0080
#define BRPHY4_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_ALIGN               0
#define BRPHY4_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_BITS                1
#define BRPHY4_DSP_TAP_TAP35_C2_GPCS_ERRTH_SEL_SHIFT               7

/* BRPHY4_DSP_TAP :: TAP35_C2 :: PCS_LPI_TEST_CTL [06:04] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x70,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x70,4)
#define BRPHY4_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_MASK              0x0070
#define BRPHY4_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_ALIGN             0
#define BRPHY4_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_BITS              3
#define BRPHY4_DSP_TAP_TAP35_C2_PCS_LPI_TEST_CTL_SHIFT             4

/* BRPHY4_DSP_TAP :: TAP35_C2 :: reserved1 [03:03] */
#define BRPHY4_DSP_TAP_TAP35_C2_RESERVED1_MASK                     0x0008
#define BRPHY4_DSP_TAP_TAP35_C2_RESERVED1_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP35_C2_RESERVED1_BITS                     1
#define BRPHY4_DSP_TAP_TAP35_C2_RESERVED1_SHIFT                    3

/* BRPHY4_DSP_TAP :: TAP35_C2 :: LPI_RX_SQCNTR [02:00] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x7,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C2,0x7,0)
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_MASK                 0x0007
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_ALIGN                0
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_BITS                 3
#define BRPHY4_DSP_TAP_TAP35_C2_LPI_RX_SQCNTR_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: TAP35_C3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: TAP35_C3 :: UNASSIGNED [15:15] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_UNASSIGNED(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_UNASSIGNED(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x8000,15)
#define BRPHY4_DSP_TAP_TAP35_C3_UNASSIGNED_MASK                    0x8000
#define BRPHY4_DSP_TAP_TAP35_C3_UNASSIGNED_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP35_C3_UNASSIGNED_BITS                    1
#define BRPHY4_DSP_TAP_TAP35_C3_UNASSIGNED_SHIFT                   15

/* BRPHY4_DSP_TAP :: TAP35_C3 :: LPI_100TX_STATE [14:12] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x7000,12,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_LPI_100TX_STATE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x7000,12)
#define BRPHY4_DSP_TAP_TAP35_C3_LPI_100TX_STATE_MASK               0x7000
#define BRPHY4_DSP_TAP_TAP35_C3_LPI_100TX_STATE_ALIGN              0
#define BRPHY4_DSP_TAP_TAP35_C3_LPI_100TX_STATE_BITS               3
#define BRPHY4_DSP_TAP_TAP35_C3_LPI_100TX_STATE_SHIFT              12

/* BRPHY4_DSP_TAP :: TAP35_C3 :: RXSM_STATE [11:08] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_RXSM_STATE(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0xf00,8,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_RXSM_STATE(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0xf00,8)
#define BRPHY4_DSP_TAP_TAP35_C3_RXSM_STATE_MASK                    0x0f00
#define BRPHY4_DSP_TAP_TAP35_C3_RXSM_STATE_ALIGN                   0
#define BRPHY4_DSP_TAP_TAP35_C3_RXSM_STATE_BITS                    4
#define BRPHY4_DSP_TAP_TAP35_C3_RXSM_STATE_SHIFT                   8

/* BRPHY4_DSP_TAP :: TAP35_C3 :: SEED_INV_CTL [07:07] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_SEED_INV_CTL(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x80,7)
#define BRPHY4_DSP_TAP_TAP35_C3_SEED_INV_CTL_MASK                  0x0080
#define BRPHY4_DSP_TAP_TAP35_C3_SEED_INV_CTL_ALIGN                 0
#define BRPHY4_DSP_TAP_TAP35_C3_SEED_INV_CTL_BITS                  1
#define BRPHY4_DSP_TAP_TAP35_C3_SEED_INV_CTL_SHIFT                 7

/* BRPHY4_DSP_TAP :: TAP35_C3 :: LOAD_N [06:06] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_LOAD_N(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_LOAD_N(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x40,6)
#define BRPHY4_DSP_TAP_TAP35_C3_LOAD_N_MASK                        0x0040
#define BRPHY4_DSP_TAP_TAP35_C3_LOAD_N_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP35_C3_LOAD_N_BITS                        1
#define BRPHY4_DSP_TAP_TAP35_C3_LOAD_N_SHIFT                       6

/* BRPHY4_DSP_TAP :: TAP35_C3 :: DET_IDLES [05:05] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_DET_IDLES(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_DET_IDLES(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x20,5)
#define BRPHY4_DSP_TAP_TAP35_C3_DET_IDLES_MASK                     0x0020
#define BRPHY4_DSP_TAP_TAP35_C3_DET_IDLES_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP35_C3_DET_IDLES_BITS                     1
#define BRPHY4_DSP_TAP_TAP35_C3_DET_IDLES_SHIFT                    5

/* BRPHY4_DSP_TAP :: TAP35_C3 :: DET_SLEEP [04:04] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_DET_SLEEP(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_DET_SLEEP(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x10,4)
#define BRPHY4_DSP_TAP_TAP35_C3_DET_SLEEP_MASK                     0x0010
#define BRPHY4_DSP_TAP_TAP35_C3_DET_SLEEP_ALIGN                    0
#define BRPHY4_DSP_TAP_TAP35_C3_DET_SLEEP_BITS                     1
#define BRPHY4_DSP_TAP_TAP35_C3_DET_SLEEP_SHIFT                    4

/* BRPHY4_DSP_TAP :: TAP35_C3 :: FUBAR [03:03] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_FUBAR(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_FUBAR(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x8,3)
#define BRPHY4_DSP_TAP_TAP35_C3_FUBAR_MASK                         0x0008
#define BRPHY4_DSP_TAP_TAP35_C3_FUBAR_ALIGN                        0
#define BRPHY4_DSP_TAP_TAP35_C3_FUBAR_BITS                         1
#define BRPHY4_DSP_TAP_TAP35_C3_FUBAR_SHIFT                        3

/* BRPHY4_DSP_TAP :: TAP35_C3 :: SR_NRZI [02:02] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_SR_NRZI(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_SR_NRZI(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x4,2)
#define BRPHY4_DSP_TAP_TAP35_C3_SR_NRZI_MASK                       0x0004
#define BRPHY4_DSP_TAP_TAP35_C3_SR_NRZI_ALIGN                      0
#define BRPHY4_DSP_TAP_TAP35_C3_SR_NRZI_BITS                       1
#define BRPHY4_DSP_TAP_TAP35_C3_SR_NRZI_SHIFT                      2

/* BRPHY4_DSP_TAP :: TAP35_C3 :: R_USCR [01:01] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_R_USCR(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_R_USCR(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x2,1)
#define BRPHY4_DSP_TAP_TAP35_C3_R_USCR_MASK                        0x0002
#define BRPHY4_DSP_TAP_TAP35_C3_R_USCR_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP35_C3_R_USCR_BITS                        1
#define BRPHY4_DSP_TAP_TAP35_C3_R_USCR_SHIFT                       1

/* BRPHY4_DSP_TAP :: TAP35_C3 :: LOCKED [00:00] */
#define Wr_BRPHY4_DSP_TAP_TAP35_C3_LOCKED(x) WriteRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_TAP35_C3_LOCKED(x) ReadRegBits16(BRPHY4_DSP_TAP_TAP35_C3,0x1,0)
#define BRPHY4_DSP_TAP_TAP35_C3_LOCKED_MASK                        0x0001
#define BRPHY4_DSP_TAP_TAP35_C3_LOCKED_ALIGN                       0
#define BRPHY4_DSP_TAP_TAP35_C3_LOCKED_BITS                        1
#define BRPHY4_DSP_TAP_TAP35_C3_LOCKED_SHIFT                       0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_CTL_CH0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x8000,15)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_MASK              0x8000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_FREEZE_SHIFT             15

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: DC_FREEZE [14:14] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x4000,14)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_MASK               0x4000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_ALIGN              0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_BITS               1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_FREEZE_SHIFT              14

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x2000,13)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_MASK             0x2000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_FREEZE_SHIFT            13

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x1000,12)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_MASK            0x1000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_FREEZE_SHIFT           12

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x800,11)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_MASK            0x0800
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_FREEZE_SHIFT           11

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x400,10)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_MASK            0x0400
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_FREEZE_SHIFT           10

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x200,9)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_MASK            0x0200
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_FREEZE_SHIFT           9

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x100,8)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_MASK              0x0100
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_FREEZE_SHIFT             8

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x80,7)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_MASK             0x0080
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_FFE_DISABLE_SHIFT            7

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: DC_DISABLE [06:06] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x40,6)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_MASK              0x0040
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DC_DISABLE_SHIFT             6

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x20,5)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_MASK            0x0020
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_ECHO_DISABLE_SHIFT           5

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x10,4)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_MASK           0x0010
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT3_DISABLE_SHIFT          4

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x8,3)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_MASK           0x0008
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT2_DISABLE_SHIFT          3

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x4,2)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_MASK           0x0004
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT1_DISABLE_SHIFT          2

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x2,1)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_MASK           0x0002
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_NEXT0_DISABLE_SHIFT          1

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH0 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH0,0x1,0)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_MASK             0x0001
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH0_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_CTL_CH1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x8000,15)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_MASK              0x8000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_FREEZE_SHIFT             15

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: DC_FREEZE [14:14] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x4000,14)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_MASK               0x4000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_ALIGN              0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_BITS               1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_FREEZE_SHIFT              14

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x2000,13)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_MASK             0x2000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_FREEZE_SHIFT            13

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x1000,12)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_MASK            0x1000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_FREEZE_SHIFT           12

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x800,11)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_MASK            0x0800
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_FREEZE_SHIFT           11

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x400,10)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_MASK            0x0400
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_FREEZE_SHIFT           10

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x200,9)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_MASK            0x0200
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_FREEZE_SHIFT           9

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x100,8)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_MASK              0x0100
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_FREEZE_SHIFT             8

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x80,7)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_MASK             0x0080
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_FFE_DISABLE_SHIFT            7

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: DC_DISABLE [06:06] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x40,6)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_MASK              0x0040
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DC_DISABLE_SHIFT             6

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x20,5)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_MASK            0x0020
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_ECHO_DISABLE_SHIFT           5

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x10,4)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_MASK           0x0010
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT3_DISABLE_SHIFT          4

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x8,3)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_MASK           0x0008
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT2_DISABLE_SHIFT          3

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x4,2)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_MASK           0x0004
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT1_DISABLE_SHIFT          2

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x2,1)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_MASK           0x0002
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_NEXT0_DISABLE_SHIFT          1

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH1 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH1,0x1,0)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_MASK             0x0001
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH1_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_CTL_CH2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x8000,15)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_MASK              0x8000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_FREEZE_SHIFT             15

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: DC_FREEZE [14:14] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x4000,14)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_MASK               0x4000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_ALIGN              0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_BITS               1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_FREEZE_SHIFT              14

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x2000,13)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_MASK             0x2000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_FREEZE_SHIFT            13

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x1000,12)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_MASK            0x1000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_FREEZE_SHIFT           12

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x800,11)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_MASK            0x0800
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_FREEZE_SHIFT           11

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x400,10)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_MASK            0x0400
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_FREEZE_SHIFT           10

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x200,9)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_MASK            0x0200
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_FREEZE_SHIFT           9

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x100,8)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_MASK              0x0100
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_FREEZE_SHIFT             8

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x80,7)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_MASK             0x0080
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_FFE_DISABLE_SHIFT            7

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: DC_DISABLE [06:06] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x40,6)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_MASK              0x0040
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DC_DISABLE_SHIFT             6

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x20,5)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_MASK            0x0020
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_ECHO_DISABLE_SHIFT           5

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x10,4)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_MASK           0x0010
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT3_DISABLE_SHIFT          4

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x8,3)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_MASK           0x0008
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT2_DISABLE_SHIFT          3

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x4,2)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_MASK           0x0004
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT1_DISABLE_SHIFT          2

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x2,1)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_MASK           0x0002
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_NEXT0_DISABLE_SHIFT          1

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH2 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH2,0x1,0)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_MASK             0x0001
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH2_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_CTL_CH3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: FFE_FREEZE [15:15] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x8000,15)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_MASK              0x8000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_FREEZE_SHIFT             15

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: DC_FREEZE [14:14] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x4000,14)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_MASK               0x4000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_ALIGN              0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_BITS               1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_FREEZE_SHIFT              14

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_FREEZE [13:13] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x2000,13)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_MASK             0x2000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_FREEZE_SHIFT            13

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_FREEZE [12:12] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x1000,12)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_MASK            0x1000
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_FREEZE_SHIFT           12

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_FREEZE [11:11] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x800,11)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_MASK            0x0800
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_FREEZE_SHIFT           11

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_FREEZE [10:10] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x400,10)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_MASK            0x0400
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_FREEZE_SHIFT           10

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_FREEZE [09:09] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x200,9)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_MASK            0x0200
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_FREEZE_SHIFT           9

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: DFE_FREEZE [08:08] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x100,8)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_MASK              0x0100
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_FREEZE_SHIFT             8

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: FFE_DISABLE [07:07] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x80,7)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_MASK             0x0080
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_FFE_DISABLE_SHIFT            7

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: DC_DISABLE [06:06] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x40,6)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_MASK              0x0040
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DC_DISABLE_SHIFT             6

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: ECHO_DISABLE [05:05] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x20,5)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_MASK            0x0020
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_ECHO_DISABLE_SHIFT           5

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: NEXT3_DISABLE [04:04] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x10,4)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_MASK           0x0010
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT3_DISABLE_SHIFT          4

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: NEXT2_DISABLE [03:03] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x8,3)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_MASK           0x0008
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT2_DISABLE_SHIFT          3

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: NEXT1_DISABLE [02:02] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x4,2)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_MASK           0x0004
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT1_DISABLE_SHIFT          2

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: NEXT0_DISABLE [01:01] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x2,1)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_MASK           0x0002
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_ALIGN          0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_BITS           1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_NEXT0_DISABLE_SHIFT          1

/* BRPHY4_DSP_TAP :: FILTER_CTL_CH3 :: DFE_DISABLE [00:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_CH3,0x1,0)
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_MASK             0x0001
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_ALIGN            0
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_BITS             1
#define BRPHY4_DSP_TAP_FILTER_CTL_CH3_DFE_DISABLE_SHIFT            0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_MASK          0xff00
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_ALIGN         0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_BITS          8
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_RESERVED0_SHIFT         8

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x80,7)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x40,6)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x20,5)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x10,4)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x8,3)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x4,2)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x2,1)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH0 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0,0x1,0)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH0_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_MASK          0xff00
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_ALIGN         0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_BITS          8
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_RESERVED0_SHIFT         8

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x80,7)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x40,6)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x20,5)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x10,4)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x8,3)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x4,2)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x2,1)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH1 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1,0x1,0)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH1_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_MASK          0xff00
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_ALIGN         0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_BITS          8
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_RESERVED0_SHIFT         8

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x80,7)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x40,6)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x20,5)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x10,4)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x8,3)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x4,2)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x2,1)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH2 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2,0x1,0)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH2_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: reserved0 [15:08] */
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_MASK          0xff00
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_ALIGN         0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_BITS          8
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_RESERVED0_SHIFT         8

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV_VAL [07:07] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x80,7)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_MASK 0x0080
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_VAL_SHIFT 7

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV_VAL [06:06] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x40,6)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_MASK 0x0040
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_VAL_SHIFT 6

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV_VAL [05:05] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x20,5)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_MASK 0x0020
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_VAL_SHIFT 5

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV_VAL [04:04] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x10,4)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_MASK 0x0010
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_ALIGN 0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_BITS 1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_VAL_SHIFT 4

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_OTHR_UPD_OV [03:03] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x8,3)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_MASK   0x0008
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_OTHR_UPD_OV_SHIFT  3

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PRE1_UPD_OV [02:02] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x4,2)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_MASK   0x0004
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PRE1_UPD_OV_SHIFT  2

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_PST1_UPD_OV [01:01] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x2,1)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_MASK   0x0002
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_PST1_UPD_OV_SHIFT  1

/* BRPHY4_DSP_TAP :: FILTER_CTL_FFEX_CH3 :: FFEX_MAIN_UPD_OV [00:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3,0x1,0)
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_MASK   0x0001
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_ALIGN  0
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_BITS   1
#define BRPHY4_DSP_TAP_FILTER_CTL_FFEX_CH3_FFEX_MAIN_UPD_OV_SHIFT  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: reserved0 [15:15] */
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_MASK             0x8000
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_ALIGN            0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_BITS             1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_RESERVED0_SHIFT            15

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT01_PRE1_DIS [14:14] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x4000,14)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_MASK  0x4000
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_ALIGN 0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_BITS  1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT01_PRE1_DIS_SHIFT 14

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: PHYC_SKIP_PHASE_ADJ [13:13] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x2000,13)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_MASK   0x2000
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_ALIGN  0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_BITS   1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_PHYC_SKIP_PHASE_ADJ_SHIFT  13

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: LOCAL_TRAIN_DIS [12:12] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x1000,12)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_MASK       0x1000
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_ALIGN      0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_BITS       1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_LOCAL_TRAIN_DIS_SHIFT      12

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: SLAVE_FDX_LOCAL_TRAIN_EN [11:11] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x800,11)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_MASK 0x0800
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_ALIGN 0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_BITS 1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_SLAVE_FDX_LOCAL_TRAIN_EN_SHIFT 11

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: AUTO_LPF_EN [10:10] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x400,10)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_MASK           0x0400
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_ALIGN          0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_BITS           1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_AUTO_LPF_EN_SHIFT          10

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_PROTECT_EN [09:09] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x200,9)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_MASK        0x0200
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_ALIGN       0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_BITS        1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_PROTECT_EN_SHIFT       9

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_INIT1_DIS [08:08] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x100,8)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_MASK        0x0100
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_ALIGN       0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_BITS        1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_INIT1_DIS_SHIFT       8

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_IDLEDATA_UPD_EN [07:04] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0xf0,4)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_MASK  0x00f0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_ALIGN 0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_BITS  4
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_IDLEDATA_UPD_EN_SHIFT 4

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_EMI_UPD_EN [03:03] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x8,3)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_MASK       0x0008
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_ALIGN      0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_BITS       1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_EMI_UPD_EN_SHIFT      3

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_VAL [02:02] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x4,2)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_MASK       0x0004
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_ALIGN      0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_BITS       1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_VAL_SHIFT      2

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: FFEX_BYPASS_OV [01:01] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x2,1)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_MASK        0x0002
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_ALIGN       0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_BITS        1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_FFEX_BYPASS_OV_SHIFT       1

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL :: EMI_DATAPATH_EN [00:00] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL,0x1,0)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_MASK       0x0001
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_ALIGN      0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_BITS       1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL_EMI_DATAPATH_EN_SHIFT      0


/****************************************************************************
 * BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL2
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL2 :: LPFREQ_SEL_STATUS [15:15] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2,0x8000,15)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_MASK    0x8000
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_ALIGN   0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_BITS    1
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_LPFREQ_SEL_STATUS_SHIFT   15

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL2 :: reserved0 [14:04] */
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_MASK            0x7ff0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_ALIGN           0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_BITS            11
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_RESERVED0_SHIFT           4

/* BRPHY4_DSP_TAP :: EMI_DATAPATH_CTL2 :: GAMMA_LPF_THRESHOLD [03:00] */
#define Wr_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) WriteRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0,x)
#define Rd_BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD(x) ReadRegBits16(BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2,0xf,0)
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_MASK  0x000f
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_ALIGN 0
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_BITS  4
#define BRPHY4_DSP_TAP_EMI_DATAPATH_CTL2_GAMMA_LPF_THRESHOLD_SHIFT 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FFEX_CTL
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FFEX_CTL :: reserved0 [15:12] */
#define BRPHY4_DSP_TAP_FFEX_CTL_RESERVED0_MASK                     0xf000
#define BRPHY4_DSP_TAP_FFEX_CTL_RESERVED0_ALIGN                    0
#define BRPHY4_DSP_TAP_FFEX_CTL_RESERVED0_BITS                     4
#define BRPHY4_DSP_TAP_FFEX_CTL_RESERVED0_SHIFT                    12

/* BRPHY4_DSP_TAP :: FFEX_CTL :: ENC_SLOW_LMS_CTL [11:10] */
#define Wr_BRPHY4_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) WriteRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0xc00,10,x)
#define Rd_BRPHY4_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL(x) ReadRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0xc00,10)
#define BRPHY4_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_MASK              0x0c00
#define BRPHY4_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_ALIGN             0
#define BRPHY4_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_BITS              2
#define BRPHY4_DSP_TAP_FFEX_CTL_ENC_SLOW_LMS_CTL_SHIFT             10

/* BRPHY4_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV_VAL [09:09] */
#define Wr_BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x200,9)
#define BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_MASK               0x0200
#define BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_ALIGN              0
#define BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_BITS               1
#define BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_VAL_SHIFT              9

/* BRPHY4_DSP_TAP :: FFEX_CTL :: ENCHGEAR_OV [08:08] */
#define Wr_BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x100,8)
#define BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_MASK                   0x0100
#define BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_ALIGN                  0
#define BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_BITS                   1
#define BRPHY4_DSP_TAP_FFEX_CTL_ENCHGEAR_OV_SHIFT                  8

/* BRPHY4_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_VAL [07:07] */
#define Wr_BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) WriteRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL(x) ReadRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x80,7)
#define BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_MASK          0x0080
#define BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_ALIGN         0
#define BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_BITS          1
#define BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_VAL_SHIFT         7

/* BRPHY4_DSP_TAP :: FFEX_CTL :: PREFILTER_BYPASS_OV [06:06] */
#define Wr_BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) WriteRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV(x) ReadRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x40,6)
#define BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_MASK           0x0040
#define BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_ALIGN          0
#define BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_BITS           1
#define BRPHY4_DSP_TAP_FFEX_CTL_PREFILTER_BYPASS_OV_SHIFT          6

/* BRPHY4_DSP_TAP :: FFEX_CTL :: FFEX_MAINTAP [05:03] */
#define Wr_BRPHY4_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) WriteRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x38,3,x)
#define Rd_BRPHY4_DSP_TAP_FFEX_CTL_FFEX_MAINTAP(x) ReadRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x38,3)
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_MASK                  0x0038
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_ALIGN                 0
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_BITS                  3
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_MAINTAP_SHIFT                 3

/* BRPHY4_DSP_TAP :: FFEX_CTL :: FFEX_LMS_MODE [02:01] */
#define Wr_BRPHY4_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) WriteRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x6,1,x)
#define Rd_BRPHY4_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE(x) ReadRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x6,1)
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_MASK                 0x0006
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_ALIGN                0
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_BITS                 2
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_LMS_MODE_SHIFT                1

/* BRPHY4_DSP_TAP :: FFEX_CTL :: FFEX_EN [00:00] */
#define Wr_BRPHY4_DSP_TAP_FFEX_CTL_FFEX_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_FFEX_CTL_FFEX_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_FFEX_CTL,0x1,0)
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_EN_MASK                       0x0001
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_EN_ALIGN                      0
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_EN_BITS                       1
#define BRPHY4_DSP_TAP_FFEX_CTL_FFEX_EN_SHIFT                      0


/****************************************************************************
 * BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL0
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_STOP [15:15] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x8000,15)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_MASK 0x8000
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_BITS 1
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_STOP_SHIFT 15

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: reserved0 [14:07] */
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_MASK         0x7f80
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_ALIGN        0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_BITS         8
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_RESERVED0_SHIFT        7

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_MAINSTATE [06:02] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x7c,2)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_MASK 0x007c
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_BITS 5
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_MAINSTATE_SHIFT 2

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_CLR [01:01] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x2,1)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_MASK 0x0002
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_BITS 1
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_CLR_SHIFT 1

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL0 :: PHYC_BREAKPOINT_EN [00:00] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0,0x1,0)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_MASK 0x0001
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_BITS 1
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL0_PHYC_BREAKPOINT_EN_SHIFT 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL1
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D_EN [15:15] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8000,15)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_MASK 0x8000
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_BITS 1
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_EN_SHIFT 15

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_D [14:12] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7000,12)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_MASK 0x7000
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_BITS 3
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_D_SHIFT 12

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C_EN [11:11] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x800,11)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_MASK 0x0800
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_BITS 1
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_EN_SHIFT 11

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_C [10:08] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x700,8)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_MASK 0x0700
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_BITS 3
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_C_SHIFT 8

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B_EN [07:07] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x80,7)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_MASK 0x0080
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_BITS 1
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_EN_SHIFT 7

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_B [06:04] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x70,4)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_MASK 0x0070
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_BITS 3
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_B_SHIFT 4

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A_EN [03:03] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x8,3)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_MASK 0x0008
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_BITS 1
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_EN_SHIFT 3

/* BRPHY4_DSP_TAP :: PHYC_BREAKPOINT_CTL1 :: PHYC_BREAKPOINT_SUB_A [02:00] */
#define Wr_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) WriteRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0,x)
#define Rd_BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A(x) ReadRegBits16(BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1,0x7,0)
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_MASK 0x0007
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_ALIGN 0
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_BITS 3
#define BRPHY4_DSP_TAP_PHYC_BREAKPOINT_CTL1_PHYC_BREAKPOINT_SUB_A_SHIFT 0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_ADDR
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_ADDR :: CTL_ALL_CH [15:15] */
#define Wr_BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0x8000,15,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_CH(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0x8000,15)
#define BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_MASK                 0x8000
#define BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_ALIGN                0
#define BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_BITS                 1
#define BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_CH_SHIFT                15

/* BRPHY4_DSP_TAP :: FILTER_ADDR :: CH_SEL [14:13] */
#define Wr_BRPHY4_DSP_TAP_FILTER_ADDR_CH_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0x6000,13,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_ADDR_CH_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0x6000,13)
#define BRPHY4_DSP_TAP_FILTER_ADDR_CH_SEL_MASK                     0x6000
#define BRPHY4_DSP_TAP_FILTER_ADDR_CH_SEL_ALIGN                    0
#define BRPHY4_DSP_TAP_FILTER_ADDR_CH_SEL_BITS                     2
#define BRPHY4_DSP_TAP_FILTER_ADDR_CH_SEL_SHIFT                    13

/* BRPHY4_DSP_TAP :: FILTER_ADDR :: CTL_ALL_FILTERS [12:12] */
#define Wr_BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0x1000,12)
#define BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_MASK            0x1000
#define BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_BITS            1
#define BRPHY4_DSP_TAP_FILTER_ADDR_CTL_ALL_FILTERS_SHIFT           12

/* BRPHY4_DSP_TAP :: FILTER_ADDR :: FILTER_SEL [11:08] */
#define Wr_BRPHY4_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0xf00,8,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_ADDR_FILTER_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0xf00,8)
#define BRPHY4_DSP_TAP_FILTER_ADDR_FILTER_SEL_MASK                 0x0f00
#define BRPHY4_DSP_TAP_FILTER_ADDR_FILTER_SEL_ALIGN                0
#define BRPHY4_DSP_TAP_FILTER_ADDR_FILTER_SEL_BITS                 4
#define BRPHY4_DSP_TAP_FILTER_ADDR_FILTER_SEL_SHIFT                8

/* BRPHY4_DSP_TAP :: FILTER_ADDR :: TAP_NUMBER [07:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0xff,0,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_ADDR_TAP_NUMBER(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_ADDR,0xff,0)
#define BRPHY4_DSP_TAP_FILTER_ADDR_TAP_NUMBER_MASK                 0x00ff
#define BRPHY4_DSP_TAP_FILTER_ADDR_TAP_NUMBER_ALIGN                0
#define BRPHY4_DSP_TAP_FILTER_ADDR_TAP_NUMBER_BITS                 8
#define BRPHY4_DSP_TAP_FILTER_ADDR_TAP_NUMBER_SHIFT                0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_CTL
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_CTL :: reserved0 [15:13] */
#define BRPHY4_DSP_TAP_FILTER_CTL_RESERVED0_MASK                   0xe000
#define BRPHY4_DSP_TAP_FILTER_CTL_RESERVED0_ALIGN                  0
#define BRPHY4_DSP_TAP_FILTER_CTL_RESERVED0_BITS                   3
#define BRPHY4_DSP_TAP_FILTER_CTL_RESERVED0_SHIFT                  13

/* BRPHY4_DSP_TAP :: FILTER_CTL :: BUSY [12:12] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_BUSY(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x1000,12,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_BUSY(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x1000,12)
#define BRPHY4_DSP_TAP_FILTER_CTL_BUSY_MASK                        0x1000
#define BRPHY4_DSP_TAP_FILTER_CTL_BUSY_ALIGN                       0
#define BRPHY4_DSP_TAP_FILTER_CTL_BUSY_BITS                        1
#define BRPHY4_DSP_TAP_FILTER_CTL_BUSY_SHIFT                       12

/* BRPHY4_DSP_TAP :: FILTER_CTL :: TAP_PREFETCH [11:11] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x800,11,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_TAP_PREFETCH(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x800,11)
#define BRPHY4_DSP_TAP_FILTER_CTL_TAP_PREFETCH_MASK                0x0800
#define BRPHY4_DSP_TAP_FILTER_CTL_TAP_PREFETCH_ALIGN               0
#define BRPHY4_DSP_TAP_FILTER_CTL_TAP_PREFETCH_BITS                1
#define BRPHY4_DSP_TAP_FILTER_CTL_TAP_PREFETCH_SHIFT               11

/* BRPHY4_DSP_TAP :: FILTER_CTL :: UPPER_WORD_SEL [10:10] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x400,10,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x400,10)
#define BRPHY4_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_MASK              0x0400
#define BRPHY4_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_UPPER_WORD_SEL_SHIFT             10

/* BRPHY4_DSP_TAP :: FILTER_CTL :: WR_COEFF [09:09] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_WR_COEFF(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x200,9,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_WR_COEFF(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x200,9)
#define BRPHY4_DSP_TAP_FILTER_CTL_WR_COEFF_MASK                    0x0200
#define BRPHY4_DSP_TAP_FILTER_CTL_WR_COEFF_ALIGN                   0
#define BRPHY4_DSP_TAP_FILTER_CTL_WR_COEFF_BITS                    1
#define BRPHY4_DSP_TAP_FILTER_CTL_WR_COEFF_SHIFT                   9

/* BRPHY4_DSP_TAP :: FILTER_CTL :: WR_ALL_NEXT_COEF [08:08] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x100,8,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x100,8)
#define BRPHY4_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_MASK            0x0100
#define BRPHY4_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_ALIGN           0
#define BRPHY4_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_BITS            1
#define BRPHY4_DSP_TAP_FILTER_CTL_WR_ALL_NEXT_COEF_SHIFT           8

/* BRPHY4_DSP_TAP :: FILTER_CTL :: RD_COEFF [07:07] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_RD_COEFF(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x80,7,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_RD_COEFF(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x80,7)
#define BRPHY4_DSP_TAP_FILTER_CTL_RD_COEFF_MASK                    0x0080
#define BRPHY4_DSP_TAP_FILTER_CTL_RD_COEFF_ALIGN                   0
#define BRPHY4_DSP_TAP_FILTER_CTL_RD_COEFF_BITS                    1
#define BRPHY4_DSP_TAP_FILTER_CTL_RD_COEFF_SHIFT                   7

/* BRPHY4_DSP_TAP :: FILTER_CTL :: INIT_RAM [06:06] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_INIT_RAM(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x40,6,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_INIT_RAM(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x40,6)
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_RAM_MASK                    0x0040
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_RAM_ALIGN                   0
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_RAM_BITS                    1
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_RAM_SHIFT                   6

/* BRPHY4_DSP_TAP :: FILTER_CTL :: INIT_ENC [05:05] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_INIT_ENC(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x20,5,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_INIT_ENC(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x20,5)
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_ENC_MASK                    0x0020
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_ENC_ALIGN                   0
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_ENC_BITS                    1
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_ENC_SHIFT                   5

/* BRPHY4_DSP_TAP :: FILTER_CTL :: INIT_DFE [04:04] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_INIT_DFE(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x10,4,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_INIT_DFE(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x10,4)
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_DFE_MASK                    0x0010
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_DFE_ALIGN                   0
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_DFE_BITS                    1
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_DFE_SHIFT                   4

/* BRPHY4_DSP_TAP :: FILTER_CTL :: INIT_FFEXTAP [03:03] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x8,3,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_INIT_FFEXTAP(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x8,3)
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_MASK                0x0008
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_ALIGN               0
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_BITS                1
#define BRPHY4_DSP_TAP_FILTER_CTL_INIT_FFEXTAP_SHIFT               3

/* BRPHY4_DSP_TAP :: FILTER_CTL :: DISABLE_FILTER [02:02] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x4,2,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_DISABLE_FILTER(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x4,2)
#define BRPHY4_DSP_TAP_FILTER_CTL_DISABLE_FILTER_MASK              0x0004
#define BRPHY4_DSP_TAP_FILTER_CTL_DISABLE_FILTER_ALIGN             0
#define BRPHY4_DSP_TAP_FILTER_CTL_DISABLE_FILTER_BITS              1
#define BRPHY4_DSP_TAP_FILTER_CTL_DISABLE_FILTER_SHIFT             2

/* BRPHY4_DSP_TAP :: FILTER_CTL :: FREEZE_FILTER [01:01] */
#define Wr_BRPHY4_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) WriteRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x2,1,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_CTL_FREEZE_FILTER(x) ReadRegBits16(BRPHY4_DSP_TAP_FILTER_CTL,0x2,1)
#define BRPHY4_DSP_TAP_FILTER_CTL_FREEZE_FILTER_MASK               0x0002
#define BRPHY4_DSP_TAP_FILTER_CTL_FREEZE_FILTER_ALIGN              0
#define BRPHY4_DSP_TAP_FILTER_CTL_FREEZE_FILTER_BITS               1
#define BRPHY4_DSP_TAP_FILTER_CTL_FREEZE_FILTER_SHIFT              1

/* BRPHY4_DSP_TAP :: FILTER_CTL :: reserved1 [00:00] */
#define BRPHY4_DSP_TAP_FILTER_CTL_RESERVED1_MASK                   0x0001
#define BRPHY4_DSP_TAP_FILTER_CTL_RESERVED1_ALIGN                  0
#define BRPHY4_DSP_TAP_FILTER_CTL_RESERVED1_BITS                   1
#define BRPHY4_DSP_TAP_FILTER_CTL_RESERVED1_SHIFT                  0


/****************************************************************************
 * BRPHY4_DSP_TAP :: FILTER_DATA
 ***************************************************************************/
/* BRPHY4_DSP_TAP :: FILTER_DATA :: TAP_COEFF [15:00] */
#define Wr_BRPHY4_DSP_TAP_FILTER_DATA_TAP_COEFF(x) WriteReg16(BRPHY4_DSP_TAP_FILTER_DATA,x)
#define Rd_BRPHY4_DSP_TAP_FILTER_DATA_TAP_COEFF(x) ReadReg16(BRPHY4_DSP_TAP_FILTER_DATA)
#define BRPHY4_DSP_TAP_FILTER_DATA_TAP_COEFF_MASK                  0xffff
#define BRPHY4_DSP_TAP_FILTER_DATA_TAP_COEFF_ALIGN                 0
#define BRPHY4_DSP_TAP_FILTER_DATA_TAP_COEFF_BITS                  16
#define BRPHY4_DSP_TAP_FILTER_DATA_TAP_COEFF_SHIFT                 0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_PLL_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLLCTRL_0
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLLCTRL_0 :: PLL_CTL [15:00] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) WriteReg16(BRPHY4_PLL_CTRL_PLLCTRL_0,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_0_PLL_CTL(x) ReadReg16(BRPHY4_PLL_CTRL_PLLCTRL_0)
#define BRPHY4_PLL_CTRL_PLLCTRL_0_PLL_CTL_MASK                     0xffff
#define BRPHY4_PLL_CTRL_PLLCTRL_0_PLL_CTL_ALIGN                    0
#define BRPHY4_PLL_CTRL_PLLCTRL_0_PLL_CTL_BITS                     16
#define BRPHY4_PLL_CTRL_PLLCTRL_0_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLLCTRL_1
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLLCTRL_1 :: PLL_CTL [15:00] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) WriteReg16(BRPHY4_PLL_CTRL_PLLCTRL_1,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_1_PLL_CTL(x) ReadReg16(BRPHY4_PLL_CTRL_PLLCTRL_1)
#define BRPHY4_PLL_CTRL_PLLCTRL_1_PLL_CTL_MASK                     0xffff
#define BRPHY4_PLL_CTRL_PLLCTRL_1_PLL_CTL_ALIGN                    0
#define BRPHY4_PLL_CTRL_PLLCTRL_1_PLL_CTL_BITS                     16
#define BRPHY4_PLL_CTRL_PLLCTRL_1_PLL_CTL_SHIFT                    0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLLCTRL_2
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2 [15:14] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_2,0xc000,14,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_2,0xc000,14)
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_MASK                  0xc000
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_ALIGN                 0
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_BITS                  2
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_SHIFT                 14

/* BRPHY4_PLL_CTRL :: PLLCTRL_2 :: PLL_PDIV [13:10] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_2,0x3c00,10,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_PDIV(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_2,0x3c00,10)
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_PDIV_MASK                    0x3c00
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_PDIV_ALIGN                   0
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_PDIV_BITS                    4
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_PDIV_SHIFT                   10

/* BRPHY4_PLL_CTRL :: PLLCTRL_2 :: PLL_SPARE2_2 [09:00] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_2,0x3ff,0,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_2,0x3ff,0)
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_MASK                0x03ff
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_ALIGN               0
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_BITS                10
#define BRPHY4_PLL_CTRL_PLLCTRL_2_PLL_SPARE2_2_SHIFT               0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLLCTRL_3
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLLCTRL_3 :: PLL_SPARE3 [15:10] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_3,0xfc00,10,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_SPARE3(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_3,0xfc00,10)
#define BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_MASK                  0xfc00
#define BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_ALIGN                 0
#define BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_BITS                  6
#define BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_SPARE3_SHIFT                 10

/* BRPHY4_PLL_CTRL :: PLLCTRL_3 :: PLL_NDIV_INT_MS [09:00] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_3,0x3ff,0,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_3,0x3ff,0)
#define BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_MASK             0x03ff
#define BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_ALIGN            0
#define BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_BITS             10
#define BRPHY4_PLL_CTRL_PLLCTRL_3_PLL_NDIV_INT_MS_SHIFT            0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLLCTRL_4
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4 [15:15] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x8000,15,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x8000,15)
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_MASK                  0x8000
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_ALIGN                 0
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_BITS                  1
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4_SHIFT                 15

/* BRPHY4_PLL_CTRL :: PLLCTRL_4 :: SD_SEL_300mV [14:14] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x4000,14,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_4_SD_SEL_300mV(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x4000,14)
#define BRPHY4_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_MASK                0x4000
#define BRPHY4_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_ALIGN               0
#define BRPHY4_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_BITS                1
#define BRPHY4_PLL_CTRL_PLLCTRL_4_SD_SEL_300MV_SHIFT               14

/* BRPHY4_PLL_CTRL :: PLLCTRL_4 :: CML_BUF_TUNE [13:12] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x3000,12,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x3000,12)
#define BRPHY4_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_MASK                0x3000
#define BRPHY4_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_ALIGN               0
#define BRPHY4_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_BITS                2
#define BRPHY4_PLL_CTRL_PLLCTRL_4_CML_BUF_TUNE_SHIFT               12

/* BRPHY4_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_BANDGAP [11:09] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0xe00,9,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0xe00,9)
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_MASK            0x0e00
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_ALIGN           0
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_BITS            3
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_BANDGAP_SHIFT           9

/* BRPHY4_PLL_CTRL :: PLLCTRL_4 :: PLL_SPARE4a [08:06] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x1c0,6,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4a(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x1c0,6)
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_MASK                 0x01c0
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_ALIGN                0
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_BITS                 3
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_SPARE4A_SHIFT                6

/* BRPHY4_PLL_CTRL :: PLLCTRL_4 :: ATEST_OR_BIAS_TEST_OUTPUT [05:05] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x20,5,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x20,5)
#define BRPHY4_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_MASK   0x0020
#define BRPHY4_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_ALIGN  0
#define BRPHY4_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_BITS   1
#define BRPHY4_PLL_CTRL_PLLCTRL_4_ATEST_OR_BIAS_TEST_OUTPUT_SHIFT  5

/* BRPHY4_PLL_CTRL :: PLLCTRL_4 :: PLL_MUX_ATEST [04:03] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x18,3,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x18,3)
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_MASK               0x0018
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_ALIGN              0
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_BITS               2
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_MUX_ATEST_SHIFT              3

/* BRPHY4_PLL_CTRL :: PLLCTRL_4 :: PLL_BIAS_TEST_MUX [02:00] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x7,0,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_4,0x7,0)
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_MASK           0x0007
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_ALIGN          0
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_BITS           3
#define BRPHY4_PLL_CTRL_PLLCTRL_4_PLL_BIAS_TEST_MUX_SHIFT          0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLLCTRL_5
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLLCTRL_5 :: PLL_SPARE5 [15:14] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0xc000,14,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_SPARE5(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0xc000,14)
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_MASK                  0xc000
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_ALIGN                 0
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_BITS                  2
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_SPARE5_SHIFT                 14

/* BRPHY4_PLL_CTRL :: PLLCTRL_5 :: PLL_CP [13:13] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x2000,13,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x2000,13)
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP_MASK                      0x2000
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP_ALIGN                     0
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP_BITS                      1
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP_SHIFT                     13

/* BRPHY4_PLL_CTRL :: PLLCTRL_5 :: PLL_CP1 [12:12] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x1000,12,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP1(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x1000,12)
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP1_MASK                     0x1000
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP1_ALIGN                    0
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP1_BITS                     1
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CP1_SHIFT                    12

/* BRPHY4_PLL_CTRL :: PLLCTRL_5 :: PLL_CZ [11:11] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x800,11,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CZ(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x800,11)
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CZ_MASK                      0x0800
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CZ_ALIGN                     0
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CZ_BITS                      1
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_CZ_SHIFT                     11

/* BRPHY4_PLL_CTRL :: PLLCTRL_5 :: PLL_RZ [10:07] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x780,7,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_RZ(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x780,7)
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_RZ_MASK                      0x0780
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_RZ_ALIGN                     0
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_RZ_BITS                      4
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_RZ_SHIFT                     7

/* BRPHY4_PLL_CTRL :: PLLCTRL_5 :: PLL_ICP [06:03] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x78,3,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_ICP(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x78,3)
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_ICP_MASK                     0x0078
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_ICP_ALIGN                    0
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_ICP_BITS                     4
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_ICP_SHIFT                    3

/* BRPHY4_PLL_CTRL :: PLLCTRL_5 :: PLL_VCO_GAIN [02:00] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x7,0,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_5,0x7,0)
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_MASK                0x0007
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_ALIGN               0
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_BITS                3
#define BRPHY4_PLL_CTRL_PLLCTRL_5_PLL_VCO_GAIN_SHIFT               0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLLCTRL_6
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLLCTRL_6 :: PLL_SPARE6 [15:09] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0xfe00,9,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_6_PLL_SPARE6(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0xfe00,9)
#define BRPHY4_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_MASK                  0xfe00
#define BRPHY4_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_ALIGN                 0
#define BRPHY4_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_BITS                  7
#define BRPHY4_PLL_CTRL_PLLCTRL_6_PLL_SPARE6_SHIFT                 9

/* BRPHY4_PLL_CTRL :: PLLCTRL_6 :: POR_CONFIG [08:07] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0x180,7,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_6_POR_CONFIG(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0x180,7)
#define BRPHY4_PLL_CTRL_PLLCTRL_6_POR_CONFIG_MASK                  0x0180
#define BRPHY4_PLL_CTRL_PLLCTRL_6_POR_CONFIG_ALIGN                 0
#define BRPHY4_PLL_CTRL_PLLCTRL_6_POR_CONFIG_BITS                  2
#define BRPHY4_PLL_CTRL_PLLCTRL_6_POR_CONFIG_SHIFT                 7

/* BRPHY4_PLL_CTRL :: PLLCTRL_6 :: CLK500_EN [06:06] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0x40,6,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_6_CLK500_EN(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0x40,6)
#define BRPHY4_PLL_CTRL_PLLCTRL_6_CLK500_EN_MASK                   0x0040
#define BRPHY4_PLL_CTRL_PLLCTRL_6_CLK500_EN_ALIGN                  0
#define BRPHY4_PLL_CTRL_PLLCTRL_6_CLK500_EN_BITS                   1
#define BRPHY4_PLL_CTRL_PLLCTRL_6_CLK500_EN_SHIFT                  6

/* BRPHY4_PLL_CTRL :: PLLCTRL_6 :: RCAL_OFFSET [05:03] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0x38,3,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0x38,3)
#define BRPHY4_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_MASK                 0x0038
#define BRPHY4_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_ALIGN                0
#define BRPHY4_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_BITS                 3
#define BRPHY4_PLL_CTRL_PLLCTRL_6_RCAL_OFFSET_SHIFT                3

/* BRPHY4_PLL_CTRL :: PLLCTRL_6 :: RCCAL_OFFSET [02:00] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0x7,0,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_6,0x7,0)
#define BRPHY4_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_MASK                0x0007
#define BRPHY4_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_ALIGN               0
#define BRPHY4_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_BITS                3
#define BRPHY4_PLL_CTRL_PLLCTRL_6_RCCAL_OFFSET_SHIFT               0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLL_STATUS_0
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLL_STATUS_0 :: reserved0 [15:12] */
#define BRPHY4_PLL_CTRL_PLL_STATUS_0_RESERVED0_MASK                0xf000
#define BRPHY4_PLL_CTRL_PLL_STATUS_0_RESERVED0_ALIGN               0
#define BRPHY4_PLL_CTRL_PLL_STATUS_0_RESERVED0_BITS                4
#define BRPHY4_PLL_CTRL_PLL_STATUS_0_RESERVED0_SHIFT               12

/* BRPHY4_PLL_CTRL :: PLL_STATUS_0 :: PLL_STATUS_WORD [11:00] */
#define Wr_BRPHY4_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLL_STATUS_0,0xfff,0,x)
#define Rd_BRPHY4_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLL_STATUS_0,0xfff,0)
#define BRPHY4_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_MASK          0x0fff
#define BRPHY4_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_ALIGN         0
#define BRPHY4_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_BITS          12
#define BRPHY4_PLL_CTRL_PLL_STATUS_0_PLL_STATUS_WORD_SHIFT         0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLL_STATUS_1
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLL_STATUS_1 :: reserved0 [15:09] */
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_RESERVED0_MASK                0xfe00
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_RESERVED0_ALIGN               0
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_RESERVED0_BITS                7
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_RESERVED0_SHIFT               9

/* BRPHY4_PLL_CTRL :: PLL_STATUS_1 :: PLL_LOCK [08:08] */
#define Wr_BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLL_STATUS_1,0x100,8,x)
#define Rd_BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_LOCK(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLL_STATUS_1,0x100,8)
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_MASK                 0x0100
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_ALIGN                0
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_BITS                 1
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_LOCK_SHIFT                8

/* BRPHY4_PLL_CTRL :: PLL_STATUS_1 :: reserved1 [07:04] */
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_RESERVED1_MASK                0x00f0
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_RESERVED1_ALIGN               0
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_RESERVED1_BITS                4
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_RESERVED1_SHIFT               4

/* BRPHY4_PLL_CTRL :: PLL_STATUS_1 :: PLL_BER [03:00] */
#define Wr_BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLL_STATUS_1,0xf,0,x)
#define Rd_BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_BER(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLL_STATUS_1,0xf,0)
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_BER_MASK                  0x000f
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_BER_ALIGN                 0
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_BER_BITS                  4
#define BRPHY4_PLL_CTRL_PLL_STATUS_1_PLL_BER_SHIFT                 0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: AFE_SIGDET_STATUS
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: AFE_SIGDET_STATUS :: reserved0 [15:07] */
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_MASK           0xff80
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_ALIGN          0
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_BITS           9
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_RESERVED0_SHIFT          7

/* BRPHY4_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_SIGSTATE [06:01] */
#define Wr_BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) WriteRegBits16(BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1,x)
#define Rd_BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE(x) ReadRegBits16(BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS,0x7e,1)
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_MASK    0x007e
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_ALIGN   0
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_BITS    6
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SIGSTATE_SHIFT   1

/* BRPHY4_PLL_CTRL :: AFE_SIGDET_STATUS :: CHANNEL_Select [00:00] */
#define Wr_BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) WriteRegBits16(BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0,x)
#define Rd_BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_Select(x) ReadRegBits16(BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS,0x1,0)
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_MASK      0x0001
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_ALIGN     0
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_BITS      1
#define BRPHY4_PLL_CTRL_AFE_SIGDET_STATUS_CHANNEL_SELECT_SHIFT     0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLLCTRL_7
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLLCTRL_7 :: TVCO_MUX_EN [15:15] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x8000,15,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x8000,15)
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_MASK                 0x8000
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_ALIGN                0
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_BITS                 1
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_MUX_EN_SHIFT                15

/* BRPHY4_PLL_CTRL :: PLLCTRL_7 :: TVCO_PAD [14:12] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x7000,12,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_PAD(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x7000,12)
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_PAD_MASK                    0x7000
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_PAD_ALIGN                   0
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_PAD_BITS                    3
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TVCO_PAD_SHIFT                   12

/* BRPHY4_PLL_CTRL :: PLLCTRL_7 :: ADJUST_AUX_LDO [11:11] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x800,11,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x800,11)
#define BRPHY4_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_MASK              0x0800
#define BRPHY4_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_ALIGN             0
#define BRPHY4_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_BITS              1
#define BRPHY4_PLL_CTRL_PLLCTRL_7_ADJUST_AUX_LDO_SHIFT             11

/* BRPHY4_PLL_CTRL :: PLLCTRL_7 :: CLAMP_REFERENCE [10:09] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x600,9,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x600,9)
#define BRPHY4_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_MASK             0x0600
#define BRPHY4_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_ALIGN            0
#define BRPHY4_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_BITS             2
#define BRPHY4_PLL_CTRL_PLLCTRL_7_CLAMP_REFERENCE_SHIFT            9

/* BRPHY4_PLL_CTRL :: PLLCTRL_7 :: CML_BUFFER_PWRDN [08:08] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x100,8,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0x100,8)
#define BRPHY4_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_MASK            0x0100
#define BRPHY4_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_ALIGN           0
#define BRPHY4_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_BITS            1
#define BRPHY4_PLL_CTRL_PLLCTRL_7_CML_BUFFER_PWRDN_SHIFT           8

/* BRPHY4_PLL_CTRL :: PLLCTRL_7 :: TXCLK_PWRDN [07:04] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0xf0,4,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0xf0,4)
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_MASK                 0x00f0
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_ALIGN                0
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_BITS                 4
#define BRPHY4_PLL_CTRL_PLLCTRL_7_TXCLK_PWRDN_SHIFT                4

/* BRPHY4_PLL_CTRL :: PLLCTRL_7 :: RXCLK_PWRDN [03:00] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0xf,0,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_7,0xf,0)
#define BRPHY4_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_MASK                 0x000f
#define BRPHY4_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_ALIGN                0
#define BRPHY4_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_BITS                 4
#define BRPHY4_PLL_CTRL_PLLCTRL_7_RXCLK_PWRDN_SHIFT                0


/****************************************************************************
 * BRPHY4_PLL_CTRL :: PLLCTRL_8
 ***************************************************************************/
/* BRPHY4_PLL_CTRL :: PLLCTRL_8 :: PLL_SPARE5 [15:01] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_8,0xfffe,1,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_8_PLL_SPARE5(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_8,0xfffe,1)
#define BRPHY4_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_MASK                  0xfffe
#define BRPHY4_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_ALIGN                 0
#define BRPHY4_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_BITS                  15
#define BRPHY4_PLL_CTRL_PLLCTRL_8_PLL_SPARE5_SHIFT                 1

/* BRPHY4_PLL_CTRL :: PLLCTRL_8 :: PC_CLK_1G_PWRDN [00:00] */
#define Wr_BRPHY4_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) WriteRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_8,0x1,0,x)
#define Rd_BRPHY4_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN(x) ReadRegBits16(BRPHY4_PLL_CTRL_PLLCTRL_8,0x1,0)
#define BRPHY4_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_MASK             0x0001
#define BRPHY4_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_ALIGN            0
#define BRPHY4_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_BITS             1
#define BRPHY4_PLL_CTRL_PLLCTRL_8_PC_CLK_1G_PWRDN_SHIFT            0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_AFE_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_AFE_CTRL :: RXCONFIG_0
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: RXCONFIG_0 :: RXCONFIG_15_0 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) WriteReg16(BRPHY4_AFE_CTRL_RXCONFIG_0,x)
#define Rd_BRPHY4_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0(x) ReadReg16(BRPHY4_AFE_CTRL_RXCONFIG_0)
#define BRPHY4_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_MASK              0xffff
#define BRPHY4_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_ALIGN             0
#define BRPHY4_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_BITS              16
#define BRPHY4_AFE_CTRL_RXCONFIG_0_RXCONFIG_15_0_SHIFT             0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: RXCONFIG_1
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: RXCONFIG_1 :: RXCONFIG_31_23 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) WriteReg16(BRPHY4_AFE_CTRL_RXCONFIG_1,x)
#define Rd_BRPHY4_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23(x) ReadReg16(BRPHY4_AFE_CTRL_RXCONFIG_1)
#define BRPHY4_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_MASK             0xffff
#define BRPHY4_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_ALIGN            0
#define BRPHY4_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_BITS             16
#define BRPHY4_AFE_CTRL_RXCONFIG_1_RXCONFIG_31_23_SHIFT            0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: RXCONFIG_2
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: RXCONFIG_2 :: RXCONFIG_47_32 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) WriteReg16(BRPHY4_AFE_CTRL_RXCONFIG_2,x)
#define Rd_BRPHY4_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32(x) ReadReg16(BRPHY4_AFE_CTRL_RXCONFIG_2)
#define BRPHY4_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_MASK             0xffff
#define BRPHY4_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_ALIGN            0
#define BRPHY4_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_BITS             16
#define BRPHY4_AFE_CTRL_RXCONFIG_2_RXCONFIG_47_32_SHIFT            0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: RXCONFIG_3
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: RXCONFIG_3 :: RXCONFIG_63_48 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) WriteReg16(BRPHY4_AFE_CTRL_RXCONFIG_3,x)
#define Rd_BRPHY4_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48(x) ReadReg16(BRPHY4_AFE_CTRL_RXCONFIG_3)
#define BRPHY4_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_MASK             0xffff
#define BRPHY4_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_ALIGN            0
#define BRPHY4_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_BITS             16
#define BRPHY4_AFE_CTRL_RXCONFIG_3_RXCONFIG_63_48_SHIFT            0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: RXCONFIG_4
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: RXCONFIG_4 :: RXCONFIG_79_64 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) WriteReg16(BRPHY4_AFE_CTRL_RXCONFIG_4,x)
#define Rd_BRPHY4_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64(x) ReadReg16(BRPHY4_AFE_CTRL_RXCONFIG_4)
#define BRPHY4_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_MASK             0xffff
#define BRPHY4_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_ALIGN            0
#define BRPHY4_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_BITS             16
#define BRPHY4_AFE_CTRL_RXCONFIG_4_RXCONFIG_79_64_SHIFT            0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: RXCONFIG5_LP
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: RXCONFIG5_LP :: RXCONFIG_86_80 [15:09] */
#define Wr_BRPHY4_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) WriteRegBits16(BRPHY4_AFE_CTRL_RXCONFIG5_LP,0xfe00,9,x)
#define Rd_BRPHY4_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80(x) ReadRegBits16(BRPHY4_AFE_CTRL_RXCONFIG5_LP,0xfe00,9)
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_MASK           0xfe00
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_ALIGN          0
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_BITS           7
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RXCONFIG_86_80_SHIFT          9

/* BRPHY4_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_0 [08:06] */
#define Wr_BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) WriteRegBits16(BRPHY4_AFE_CTRL_RXCONFIG5_LP,0x1c0,6,x)
#define Rd_BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_0(x) ReadRegBits16(BRPHY4_AFE_CTRL_RXCONFIG5_LP,0x1c0,6)
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_MASK                  0x01c0
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_ALIGN                 0
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_BITS                  3
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_0_SHIFT                 6

/* BRPHY4_AFE_CTRL :: RXCONFIG5_LP :: RX_LP_1 [05:03] */
#define Wr_BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) WriteRegBits16(BRPHY4_AFE_CTRL_RXCONFIG5_LP,0x38,3,x)
#define Rd_BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_1(x) ReadRegBits16(BRPHY4_AFE_CTRL_RXCONFIG5_LP,0x38,3)
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_MASK                  0x0038
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_ALIGN                 0
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_BITS                  3
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_RX_LP_1_SHIFT                 3

/* BRPHY4_AFE_CTRL :: RXCONFIG5_LP :: MODE_force [02:00] */
#define Wr_BRPHY4_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) WriteRegBits16(BRPHY4_AFE_CTRL_RXCONFIG5_LP,0x7,0,x)
#define Rd_BRPHY4_AFE_CTRL_RXCONFIG5_LP_MODE_force(x) ReadRegBits16(BRPHY4_AFE_CTRL_RXCONFIG5_LP,0x7,0)
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_MASK               0x0007
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_ALIGN              0
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_BITS               3
#define BRPHY4_AFE_CTRL_RXCONFIG5_LP_MODE_FORCE_SHIFT              0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: TX_CONFIG_0
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: TX_CONFIG_0 :: TX_CONFIG_15_0 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) WriteReg16(BRPHY4_AFE_CTRL_TX_CONFIG_0,x)
#define Rd_BRPHY4_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0(x) ReadReg16(BRPHY4_AFE_CTRL_TX_CONFIG_0)
#define BRPHY4_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_MASK            0xffff
#define BRPHY4_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_ALIGN           0
#define BRPHY4_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_BITS            16
#define BRPHY4_AFE_CTRL_TX_CONFIG_0_TX_CONFIG_15_0_SHIFT           0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: TX_CONFIG_1
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: TX_CONFIG_1 :: TX_BW_TUNE [15:11] */
#define Wr_BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) WriteRegBits16(BRPHY4_AFE_CTRL_TX_CONFIG_1,0xf800,11,x)
#define Rd_BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE(x) ReadRegBits16(BRPHY4_AFE_CTRL_TX_CONFIG_1,0xf800,11)
#define BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_MASK                0xf800
#define BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_ALIGN               0
#define BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_BITS                5
#define BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_BW_TUNE_SHIFT               11

/* BRPHY4_AFE_CTRL :: TX_CONFIG_1 :: TX_CONFIG_26_16 [10:00] */
#define Wr_BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) WriteRegBits16(BRPHY4_AFE_CTRL_TX_CONFIG_1,0x7ff,0,x)
#define Rd_BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16(x) ReadRegBits16(BRPHY4_AFE_CTRL_TX_CONFIG_1,0x7ff,0)
#define BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_MASK           0x07ff
#define BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_ALIGN          0
#define BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_BITS           11
#define BRPHY4_AFE_CTRL_TX_CONFIG_1_TX_CONFIG_26_16_SHIFT          0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: VDAC_ICTRL_0
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: VDAC_ICTRL_0 :: VDAC_current_ctrl_15_0 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) WriteReg16(BRPHY4_AFE_CTRL_VDAC_ICTRL_0,x)
#define Rd_BRPHY4_AFE_CTRL_VDAC_ICTRL_0_VDAC_current_ctrl_15_0(x) ReadReg16(BRPHY4_AFE_CTRL_VDAC_ICTRL_0)
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_MASK   0xffff
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_ALIGN  0
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_BITS   16
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_0_VDAC_CURRENT_CTRL_15_0_SHIFT  0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: VDAC_ICTRL_1
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: VDAC_ICTRL_1 :: VDAC_current_ctrl_31_16 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) WriteReg16(BRPHY4_AFE_CTRL_VDAC_ICTRL_1,x)
#define Rd_BRPHY4_AFE_CTRL_VDAC_ICTRL_1_VDAC_current_ctrl_31_16(x) ReadReg16(BRPHY4_AFE_CTRL_VDAC_ICTRL_1)
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_MASK  0xffff
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_ALIGN 0
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_BITS  16
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_1_VDAC_CURRENT_CTRL_31_16_SHIFT 0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: VDAC_ICTRL_2
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: VDAC_ICTRL_2 :: VDAC_current_ctrl_51_36 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) WriteReg16(BRPHY4_AFE_CTRL_VDAC_ICTRL_2,x)
#define Rd_BRPHY4_AFE_CTRL_VDAC_ICTRL_2_VDAC_current_ctrl_51_36(x) ReadReg16(BRPHY4_AFE_CTRL_VDAC_ICTRL_2)
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_MASK  0xffff
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_ALIGN 0
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_BITS  16
#define BRPHY4_AFE_CTRL_VDAC_ICTRL_2_VDAC_CURRENT_CTRL_51_36_SHIFT 0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: VDAC_OTHERS_0
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: VDAC_OTHERS_0 :: current_ctrl_35_32_others [15:00] */
#define Wr_BRPHY4_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) WriteReg16(BRPHY4_AFE_CTRL_VDAC_OTHERS_0,x)
#define Rd_BRPHY4_AFE_CTRL_VDAC_OTHERS_0_current_ctrl_35_32_others(x) ReadReg16(BRPHY4_AFE_CTRL_VDAC_OTHERS_0)
#define BRPHY4_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_MASK 0xffff
#define BRPHY4_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_ALIGN 0
#define BRPHY4_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_BITS 16
#define BRPHY4_AFE_CTRL_VDAC_OTHERS_0_CURRENT_CTRL_35_32_OTHERS_SHIFT 0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: HPF_TRIM_OTHERS
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: HPF_TRIM_OTHERS :: Reserved [15:10] */
#define Wr_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) WriteRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10,x)
#define Rd_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_Reserved(x) ReadRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0xfc00,10)
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_MASK              0xfc00
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_ALIGN             0
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_BITS              6
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RESERVED_SHIFT             10

/* BRPHY4_AFE_CTRL :: HPF_TRIM_OTHERS :: RX_SAMPLE_WIDTH [09:07] */
#define Wr_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) WriteRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7,x)
#define Rd_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH(x) ReadRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0x380,7)
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_MASK       0x0380
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_ALIGN      0
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_BITS       3
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_RX_SAMPLE_WIDTH_SHIFT      7

/* BRPHY4_AFE_CTRL :: HPF_TRIM_OTHERS :: IDAC_fine_tune [06:04] */
#define Wr_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) WriteRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4,x)
#define Rd_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_fine_tune(x) ReadRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0x70,4)
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_MASK        0x0070
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_ALIGN       0
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_BITS        3
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_IDAC_FINE_TUNE_SHIFT       4

/* BRPHY4_AFE_CTRL :: HPF_TRIM_OTHERS :: SOFT_SEL_TRIM_HPF [03:03] */
#define Wr_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) WriteRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3,x)
#define Rd_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF(x) ReadRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0x8,3)
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_MASK     0x0008
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_ALIGN    0
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_BITS     1
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_SOFT_SEL_TRIM_HPF_SHIFT    3

/* BRPHY4_AFE_CTRL :: HPF_TRIM_OTHERS :: TRIM_HPF [02:00] */
#define Wr_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) WriteRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0,x)
#define Rd_BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF(x) ReadRegBits16(BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS,0x7,0)
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_MASK              0x0007
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_ALIGN             0
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_BITS              3
#define BRPHY4_AFE_CTRL_HPF_TRIM_OTHERS_TRIM_HPF_SHIFT             0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: TX_EXTRA_CONFIG_0
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: TX_EXTRA_CONFIG_0 :: TX_EXTRA_CONFIG_15_0 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) WriteReg16(BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_0,x)
#define Rd_BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0(x) ReadReg16(BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_0)
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_MASK 0xffff
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_ALIGN 0
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_BITS 16
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_0_TX_EXTRA_CONFIG_15_0_SHIFT 0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: TX_EXTRA_CONFIG_1
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: TX_EXTRA_CONFIG_1 :: TX_EXTRA_CONFIG_31_16 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) WriteReg16(BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_1,x)
#define Rd_BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16(x) ReadReg16(BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_1)
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_MASK 0xffff
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_ALIGN 0
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_BITS 16
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_1_TX_EXTRA_CONFIG_31_16_SHIFT 0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: TX_EXTRA_CONFIG_2
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: TX_EXTRA_CONFIG_2 :: TX_EXTRA_CONFIG_47_32 [15:00] */
#define Wr_BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) WriteReg16(BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_2,x)
#define Rd_BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32(x) ReadReg16(BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_2)
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_MASK 0xffff
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_ALIGN 0
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_BITS 16
#define BRPHY4_AFE_CTRL_TX_EXTRA_CONFIG_2_TX_EXTRA_CONFIG_47_32_SHIFT 0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: TEMPSEN_OTHERS
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: TEMPSEN_OTHERS :: TEMPSEN [15:02] */
#define Wr_BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) WriteRegBits16(BRPHY4_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2,x)
#define Rd_BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN(x) ReadRegBits16(BRPHY4_AFE_CTRL_TEMPSEN_OTHERS,0xfffc,2)
#define BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_MASK                0xfffc
#define BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_ALIGN               0
#define BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_BITS                14
#define BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_TEMPSEN_SHIFT               2

/* BRPHY4_AFE_CTRL :: TEMPSEN_OTHERS :: EXTRA_10BT [01:00] */
#define Wr_BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) WriteRegBits16(BRPHY4_AFE_CTRL_TEMPSEN_OTHERS,0x3,0,x)
#define Rd_BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT(x) ReadRegBits16(BRPHY4_AFE_CTRL_TEMPSEN_OTHERS,0x3,0)
#define BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_MASK             0x0003
#define BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_ALIGN            0
#define BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_BITS             2
#define BRPHY4_AFE_CTRL_TEMPSEN_OTHERS_EXTRA_10BT_SHIFT            0


/****************************************************************************
 * BRPHY4_AFE_CTRL :: FUTURE_RSV
 ***************************************************************************/
/* BRPHY4_AFE_CTRL :: FUTURE_RSV :: FUTURE_RSV [15:00] */
#define Wr_BRPHY4_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) WriteReg16(BRPHY4_AFE_CTRL_FUTURE_RSV,x)
#define Rd_BRPHY4_AFE_CTRL_FUTURE_RSV_FUTURE_RSV(x) ReadReg16(BRPHY4_AFE_CTRL_FUTURE_RSV)
#define BRPHY4_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_MASK                 0xffff
#define BRPHY4_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_ALIGN                0
#define BRPHY4_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_BITS                 16
#define BRPHY4_AFE_CTRL_FUTURE_RSV_FUTURE_RSV_SHIFT                0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_ECD_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC0
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC0 :: RUN_IMMEDIATE [15:15] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x8000,15,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_RUN_IMMEDIATE(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x8000,15)
#define BRPHY4_ECD_CTRL_EXPC0_RUN_IMMEDIATE_MASK                   0x8000
#define BRPHY4_ECD_CTRL_EXPC0_RUN_IMMEDIATE_ALIGN                  0
#define BRPHY4_ECD_CTRL_EXPC0_RUN_IMMEDIATE_BITS                   1
#define BRPHY4_ECD_CTRL_EXPC0_RUN_IMMEDIATE_SHIFT                  15

/* BRPHY4_ECD_CTRL :: EXPC0 :: RUN_AT_AUTONEG [14:14] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x4000,14,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_RUN_AT_AUTONEG(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x4000,14)
#define BRPHY4_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_MASK                  0x4000
#define BRPHY4_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_ALIGN                 0
#define BRPHY4_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_BITS                  1
#define BRPHY4_ECD_CTRL_EXPC0_RUN_AT_AUTONEG_SHIFT                 14

/* BRPHY4_ECD_CTRL :: EXPC0 :: INTER_PAIR_SHORT_DIS [13:13] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x2000,13,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x2000,13)
#define BRPHY4_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_MASK            0x2000
#define BRPHY4_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_ALIGN           0
#define BRPHY4_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_BITS            1
#define BRPHY4_ECD_CTRL_EXPC0_INTER_PAIR_SHORT_DIS_SHIFT           13

/* BRPHY4_ECD_CTRL :: EXPC0 :: BREAK_LINK [12:12] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_BREAK_LINK(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x1000,12,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_BREAK_LINK(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x1000,12)
#define BRPHY4_ECD_CTRL_EXPC0_BREAK_LINK_MASK                      0x1000
#define BRPHY4_ECD_CTRL_EXPC0_BREAK_LINK_ALIGN                     0
#define BRPHY4_ECD_CTRL_EXPC0_BREAK_LINK_BITS                      1
#define BRPHY4_ECD_CTRL_EXPC0_BREAK_LINK_SHIFT                     12

/* BRPHY4_ECD_CTRL :: EXPC0 :: CABLE_DIAG_STATUS [11:11] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x800,11,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x800,11)
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_MASK               0x0800
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_ALIGN              0
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_BITS               1
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_STATUS_SHIFT              11

/* BRPHY4_ECD_CTRL :: EXPC0 :: CABLE_LEN_UNIT [10:10] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x400,10,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_CABLE_LEN_UNIT(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x400,10)
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_MASK                  0x0400
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_ALIGN                 0
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_BITS                  1
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_LEN_UNIT_SHIFT                 10

/* BRPHY4_ECD_CTRL :: EXPC0 :: reserved0 [09:09] */
#define BRPHY4_ECD_CTRL_EXPC0_RESERVED0_MASK                       0x0200
#define BRPHY4_ECD_CTRL_EXPC0_RESERVED0_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPC0_RESERVED0_BITS                       1
#define BRPHY4_ECD_CTRL_EXPC0_RESERVED0_SHIFT                      9

/* BRPHY4_ECD_CTRL :: EXPC0 :: FAST_TIMER_ENABLE [08:08] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x100,8,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x100,8)
#define BRPHY4_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_MASK               0x0100
#define BRPHY4_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_ALIGN              0
#define BRPHY4_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_BITS               1
#define BRPHY4_ECD_CTRL_EXPC0_FAST_TIMER_ENABLE_SHIFT              8

/* BRPHY4_ECD_CTRL :: EXPC0 :: INTRPT_ENABLE [07:07] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x80,7,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_INTRPT_ENABLE(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x80,7)
#define BRPHY4_ECD_CTRL_EXPC0_INTRPT_ENABLE_MASK                   0x0080
#define BRPHY4_ECD_CTRL_EXPC0_INTRPT_ENABLE_ALIGN                  0
#define BRPHY4_ECD_CTRL_EXPC0_INTRPT_ENABLE_BITS                   1
#define BRPHY4_ECD_CTRL_EXPC0_INTRPT_ENABLE_SHIFT                  7

/* BRPHY4_ECD_CTRL :: EXPC0 :: STOP_PLL_CLK [06:06] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x40,6,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_STOP_PLL_CLK(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x40,6)
#define BRPHY4_ECD_CTRL_EXPC0_STOP_PLL_CLK_MASK                    0x0040
#define BRPHY4_ECD_CTRL_EXPC0_STOP_PLL_CLK_ALIGN                   0
#define BRPHY4_ECD_CTRL_EXPC0_STOP_PLL_CLK_BITS                    1
#define BRPHY4_ECD_CTRL_EXPC0_STOP_PLL_CLK_SHIFT                   6

/* BRPHY4_ECD_CTRL :: EXPC0 :: reserved1 [05:04] */
#define BRPHY4_ECD_CTRL_EXPC0_RESERVED1_MASK                       0x0030
#define BRPHY4_ECD_CTRL_EXPC0_RESERVED1_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPC0_RESERVED1_BITS                       2
#define BRPHY4_ECD_CTRL_EXPC0_RESERVED1_SHIFT                      4

/* BRPHY4_ECD_CTRL :: EXPC0 :: INVALID_RESULT [03:03] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_INVALID_RESULT(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x8,3,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_INVALID_RESULT(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x8,3)
#define BRPHY4_ECD_CTRL_EXPC0_INVALID_RESULT_MASK                  0x0008
#define BRPHY4_ECD_CTRL_EXPC0_INVALID_RESULT_ALIGN                 0
#define BRPHY4_ECD_CTRL_EXPC0_INVALID_RESULT_BITS                  1
#define BRPHY4_ECD_CTRL_EXPC0_INVALID_RESULT_SHIFT                 3

/* BRPHY4_ECD_CTRL :: EXPC0 :: CABLE_DIAG_EXE [02:02] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x4,2,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_EXE(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x4,2)
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_MASK                  0x0004
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_ALIGN                 0
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_BITS                  1
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_DIAG_EXE_SHIFT                 2

/* BRPHY4_ECD_CTRL :: EXPC0 :: AUTO_RUN_FOR_BROKEN_ANG [01:01] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x2,1,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x2,1)
#define BRPHY4_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_MASK         0x0002
#define BRPHY4_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_ALIGN        0
#define BRPHY4_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_BITS         1
#define BRPHY4_ECD_CTRL_EXPC0_AUTO_RUN_FOR_BROKEN_ANG_SHIFT        1

/* BRPHY4_ECD_CTRL :: EXPC0 :: CABLE_TYPE [00:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC0_CABLE_TYPE(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x1,0,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC0_CABLE_TYPE(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC0,0x1,0)
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_TYPE_MASK                      0x0001
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_TYPE_ALIGN                     0
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_TYPE_BITS                      1
#define BRPHY4_ECD_CTRL_EXPC0_CABLE_TYPE_SHIFT                     0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC1
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC1 :: PA_CD_CODE [15:12] */
#define Wr_BRPHY4_ECD_CTRL_EXPC1_PA_CD_CODE(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC1,0xf000,12,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC1_PA_CD_CODE(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC1,0xf000,12)
#define BRPHY4_ECD_CTRL_EXPC1_PA_CD_CODE_MASK                      0xf000
#define BRPHY4_ECD_CTRL_EXPC1_PA_CD_CODE_ALIGN                     0
#define BRPHY4_ECD_CTRL_EXPC1_PA_CD_CODE_BITS                      4
#define BRPHY4_ECD_CTRL_EXPC1_PA_CD_CODE_SHIFT                     12

/* BRPHY4_ECD_CTRL :: EXPC1 :: PB_CD_CODE [11:08] */
#define Wr_BRPHY4_ECD_CTRL_EXPC1_PB_CD_CODE(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC1,0xf00,8,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC1_PB_CD_CODE(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC1,0xf00,8)
#define BRPHY4_ECD_CTRL_EXPC1_PB_CD_CODE_MASK                      0x0f00
#define BRPHY4_ECD_CTRL_EXPC1_PB_CD_CODE_ALIGN                     0
#define BRPHY4_ECD_CTRL_EXPC1_PB_CD_CODE_BITS                      4
#define BRPHY4_ECD_CTRL_EXPC1_PB_CD_CODE_SHIFT                     8

/* BRPHY4_ECD_CTRL :: EXPC1 :: PC_CD_CODE [07:04] */
#define Wr_BRPHY4_ECD_CTRL_EXPC1_PC_CD_CODE(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC1,0xf0,4,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC1_PC_CD_CODE(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC1,0xf0,4)
#define BRPHY4_ECD_CTRL_EXPC1_PC_CD_CODE_MASK                      0x00f0
#define BRPHY4_ECD_CTRL_EXPC1_PC_CD_CODE_ALIGN                     0
#define BRPHY4_ECD_CTRL_EXPC1_PC_CD_CODE_BITS                      4
#define BRPHY4_ECD_CTRL_EXPC1_PC_CD_CODE_SHIFT                     4

/* BRPHY4_ECD_CTRL :: EXPC1 :: PD_CD_CODE [03:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC1_PD_CD_CODE(x) WriteRegBits16(BRPHY4_ECD_CTRL_EXPC1,0xf,0,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC1_PD_CD_CODE(x) ReadRegBits16(BRPHY4_ECD_CTRL_EXPC1,0xf,0)
#define BRPHY4_ECD_CTRL_EXPC1_PD_CD_CODE_MASK                      0x000f
#define BRPHY4_ECD_CTRL_EXPC1_PD_CD_CODE_ALIGN                     0
#define BRPHY4_ECD_CTRL_EXPC1_PD_CD_CODE_BITS                      4
#define BRPHY4_ECD_CTRL_EXPC1_PD_CD_CODE_SHIFT                     0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC2
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC2 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) WriteReg16(BRPHY4_ECD_CTRL_EXPC2,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC2_LENGTH_INDICATION(x) ReadReg16(BRPHY4_ECD_CTRL_EXPC2)
#define BRPHY4_ECD_CTRL_EXPC2_LENGTH_INDICATION_MASK               0xffff
#define BRPHY4_ECD_CTRL_EXPC2_LENGTH_INDICATION_ALIGN              0
#define BRPHY4_ECD_CTRL_EXPC2_LENGTH_INDICATION_BITS               16
#define BRPHY4_ECD_CTRL_EXPC2_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC3
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC3 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) WriteReg16(BRPHY4_ECD_CTRL_EXPC3,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC3_LENGTH_INDICATION(x) ReadReg16(BRPHY4_ECD_CTRL_EXPC3)
#define BRPHY4_ECD_CTRL_EXPC3_LENGTH_INDICATION_MASK               0xffff
#define BRPHY4_ECD_CTRL_EXPC3_LENGTH_INDICATION_ALIGN              0
#define BRPHY4_ECD_CTRL_EXPC3_LENGTH_INDICATION_BITS               16
#define BRPHY4_ECD_CTRL_EXPC3_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC4
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC4 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) WriteReg16(BRPHY4_ECD_CTRL_EXPC4,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC4_LENGTH_INDICATION(x) ReadReg16(BRPHY4_ECD_CTRL_EXPC4)
#define BRPHY4_ECD_CTRL_EXPC4_LENGTH_INDICATION_MASK               0xffff
#define BRPHY4_ECD_CTRL_EXPC4_LENGTH_INDICATION_ALIGN              0
#define BRPHY4_ECD_CTRL_EXPC4_LENGTH_INDICATION_BITS               16
#define BRPHY4_ECD_CTRL_EXPC4_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC5
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC5 :: LENGTH_INDICATION [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) WriteReg16(BRPHY4_ECD_CTRL_EXPC5,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC5_LENGTH_INDICATION(x) ReadReg16(BRPHY4_ECD_CTRL_EXPC5)
#define BRPHY4_ECD_CTRL_EXPC5_LENGTH_INDICATION_MASK               0xffff
#define BRPHY4_ECD_CTRL_EXPC5_LENGTH_INDICATION_ALIGN              0
#define BRPHY4_ECD_CTRL_EXPC5_LENGTH_INDICATION_BITS               16
#define BRPHY4_ECD_CTRL_EXPC5_LENGTH_INDICATION_SHIFT              0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC6
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC6 :: F_COUNT_0 [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC6_F_COUNT_0(x) WriteReg16(BRPHY4_ECD_CTRL_EXPC6,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC6_F_COUNT_0(x) ReadReg16(BRPHY4_ECD_CTRL_EXPC6)
#define BRPHY4_ECD_CTRL_EXPC6_F_COUNT_0_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPC6_F_COUNT_0_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPC6_F_COUNT_0_BITS                       16
#define BRPHY4_ECD_CTRL_EXPC6_F_COUNT_0_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC7
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC7 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC7_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPC7,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC7_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPC7)
#define BRPHY4_ECD_CTRL_EXPC7_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPC7_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPC7_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPC7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC8
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC8 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC8_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPC8,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC8_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPC8)
#define BRPHY4_ECD_CTRL_EXPC8_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPC8_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPC8_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPC8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPC9
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPC9 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPC9_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPC9,x)
#define Rd_BRPHY4_ECD_CTRL_EXPC9_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPC9)
#define BRPHY4_ECD_CTRL_EXPC9_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPC9_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPC9_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPC9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPCA
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPCA :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPCA_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPCA,x)
#define Rd_BRPHY4_ECD_CTRL_EXPCA_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPCA)
#define BRPHY4_ECD_CTRL_EXPCA_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPCA_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPCA_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPCA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPCB
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPCB :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPCB_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPCB,x)
#define Rd_BRPHY4_ECD_CTRL_EXPCB_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPCB)
#define BRPHY4_ECD_CTRL_EXPCB_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPCB_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPCB_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPCB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPCC
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPCC :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPCC_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPCC,x)
#define Rd_BRPHY4_ECD_CTRL_EXPCC_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPCC)
#define BRPHY4_ECD_CTRL_EXPCC_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPCC_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPCC_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPCC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPCD
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPCD :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPCD_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPCD,x)
#define Rd_BRPHY4_ECD_CTRL_EXPCD_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPCD)
#define BRPHY4_ECD_CTRL_EXPCD_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPCD_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPCD_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPCD_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPCE
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPCE :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPCE_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPCE,x)
#define Rd_BRPHY4_ECD_CTRL_EXPCE_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPCE)
#define BRPHY4_ECD_CTRL_EXPCE_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPCE_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPCE_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPCE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPCF
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPCF :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPCF_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPCF,x)
#define Rd_BRPHY4_ECD_CTRL_EXPCF_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPCF)
#define BRPHY4_ECD_CTRL_EXPCF_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPCF_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPCF_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPCF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE0
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE0 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE0_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE0,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE0_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE0)
#define BRPHY4_ECD_CTRL_EXPE0_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE0_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE0_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE0_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE1
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE1 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE1_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE1,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE1_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE1)
#define BRPHY4_ECD_CTRL_EXPE1_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE1_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE1_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE1_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE2
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE2 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE2_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE2,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE2_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE2)
#define BRPHY4_ECD_CTRL_EXPE2_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE2_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE2_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE2_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE3
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE3 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE3_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE3,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE3_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE3)
#define BRPHY4_ECD_CTRL_EXPE3_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE3_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE3_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE3_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE4
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE4 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE4_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE4,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE4_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE4)
#define BRPHY4_ECD_CTRL_EXPE4_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE4_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE4_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE4_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE5
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE5 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE5_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE5,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE5_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE5)
#define BRPHY4_ECD_CTRL_EXPE5_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE5_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE5_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE5_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE6
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE6 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE6_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE6,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE6_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE6)
#define BRPHY4_ECD_CTRL_EXPE6_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE6_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE6_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE6_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE7
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE7 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE7_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE7,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE7_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE7)
#define BRPHY4_ECD_CTRL_EXPE7_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE7_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE7_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE7_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE8
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE8 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE8_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE8,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE8_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE8)
#define BRPHY4_ECD_CTRL_EXPE8_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE8_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE8_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE8_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPE9
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPE9 :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPE9_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPE9,x)
#define Rd_BRPHY4_ECD_CTRL_EXPE9_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPE9)
#define BRPHY4_ECD_CTRL_EXPE9_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPE9_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPE9_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPE9_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPEA
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPEA :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPEA_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPEA,x)
#define Rd_BRPHY4_ECD_CTRL_EXPEA_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPEA)
#define BRPHY4_ECD_CTRL_EXPEA_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPEA_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPEA_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPEA_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPEB
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPEB :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPEB_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPEB,x)
#define Rd_BRPHY4_ECD_CTRL_EXPEB_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPEB)
#define BRPHY4_ECD_CTRL_EXPEB_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPEB_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPEB_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPEB_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPEC
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPEC :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPEC_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPEC,x)
#define Rd_BRPHY4_ECD_CTRL_EXPEC_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPEC)
#define BRPHY4_ECD_CTRL_EXPEC_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPEC_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPEC_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPEC_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPED
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPED :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPED_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPED,x)
#define Rd_BRPHY4_ECD_CTRL_EXPED_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPED)
#define BRPHY4_ECD_CTRL_EXPED_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPED_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPED_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPED_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPEE
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPEE :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPEE_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPEE,x)
#define Rd_BRPHY4_ECD_CTRL_EXPEE_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPEE)
#define BRPHY4_ECD_CTRL_EXPEE_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPEE_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPEE_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPEE_UNDEFINED_SHIFT                      0


/****************************************************************************
 * BRPHY4_ECD_CTRL :: EXPEF
 ***************************************************************************/
/* BRPHY4_ECD_CTRL :: EXPEF :: UNDEFINED [15:00] */
#define Wr_BRPHY4_ECD_CTRL_EXPEF_UNDEFINED(x) WriteReg16(BRPHY4_ECD_CTRL_EXPEF,x)
#define Rd_BRPHY4_ECD_CTRL_EXPEF_UNDEFINED(x) ReadReg16(BRPHY4_ECD_CTRL_EXPEF)
#define BRPHY4_ECD_CTRL_EXPEF_UNDEFINED_MASK                       0xffff
#define BRPHY4_ECD_CTRL_EXPEF_UNDEFINED_ALIGN                      0
#define BRPHY4_ECD_CTRL_EXPEF_UNDEFINED_BITS                       16
#define BRPHY4_ECD_CTRL_EXPEF_UNDEFINED_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_BR_CTRL
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP90
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP90 :: DIG_HPF_EN [15:15] */
#define Wr_BRPHY4_BR_CTRL_EXP90_DIG_HPF_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP90,0x8000,15,x)
#define Rd_BRPHY4_BR_CTRL_EXP90_DIG_HPF_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP90,0x8000,15)
#define BRPHY4_BR_CTRL_EXP90_DIG_HPF_EN_MASK                       0x8000
#define BRPHY4_BR_CTRL_EXP90_DIG_HPF_EN_ALIGN                      0
#define BRPHY4_BR_CTRL_EXP90_DIG_HPF_EN_BITS                       1
#define BRPHY4_BR_CTRL_EXP90_DIG_HPF_EN_SHIFT                      15

/* BRPHY4_BR_CTRL :: EXP90 :: BR_SCR_STATUS [14:13] */
#define Wr_BRPHY4_BR_CTRL_EXP90_BR_SCR_STATUS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP90,0x6000,13,x)
#define Rd_BRPHY4_BR_CTRL_EXP90_BR_SCR_STATUS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP90,0x6000,13)
#define BRPHY4_BR_CTRL_EXP90_BR_SCR_STATUS_MASK                    0x6000
#define BRPHY4_BR_CTRL_EXP90_BR_SCR_STATUS_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP90_BR_SCR_STATUS_BITS                    2
#define BRPHY4_BR_CTRL_EXP90_BR_SCR_STATUS_SHIFT                   13

/* BRPHY4_BR_CTRL :: EXP90 :: BR_ALIGN_STATE [12:10] */
#define Wr_BRPHY4_BR_CTRL_EXP90_BR_ALIGN_STATE(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP90,0x1c00,10,x)
#define Rd_BRPHY4_BR_CTRL_EXP90_BR_ALIGN_STATE(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP90,0x1c00,10)
#define BRPHY4_BR_CTRL_EXP90_BR_ALIGN_STATE_MASK                   0x1c00
#define BRPHY4_BR_CTRL_EXP90_BR_ALIGN_STATE_ALIGN                  0
#define BRPHY4_BR_CTRL_EXP90_BR_ALIGN_STATE_BITS                   3
#define BRPHY4_BR_CTRL_EXP90_BR_ALIGN_STATE_SHIFT                  10

/* BRPHY4_BR_CTRL :: EXP90 :: BR_RX_STATE [09:06] */
#define Wr_BRPHY4_BR_CTRL_EXP90_BR_RX_STATE(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP90,0x3c0,6,x)
#define Rd_BRPHY4_BR_CTRL_EXP90_BR_RX_STATE(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP90,0x3c0,6)
#define BRPHY4_BR_CTRL_EXP90_BR_RX_STATE_MASK                      0x03c0
#define BRPHY4_BR_CTRL_EXP90_BR_RX_STATE_ALIGN                     0
#define BRPHY4_BR_CTRL_EXP90_BR_RX_STATE_BITS                      4
#define BRPHY4_BR_CTRL_EXP90_BR_RX_STATE_SHIFT                     6

/* BRPHY4_BR_CTRL :: EXP90 :: BR_PCS_STATE [05:02] */
#define Wr_BRPHY4_BR_CTRL_EXP90_BR_PCS_STATE(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP90,0x3c,2,x)
#define Rd_BRPHY4_BR_CTRL_EXP90_BR_PCS_STATE(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP90,0x3c,2)
#define BRPHY4_BR_CTRL_EXP90_BR_PCS_STATE_MASK                     0x003c
#define BRPHY4_BR_CTRL_EXP90_BR_PCS_STATE_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP90_BR_PCS_STATE_BITS                     4
#define BRPHY4_BR_CTRL_EXP90_BR_PCS_STATE_SHIFT                    2

/* BRPHY4_BR_CTRL :: EXP90 :: BR_FORCE_LINK_CTL [01:01] */
#define Wr_BRPHY4_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP90,0x2,1,x)
#define Rd_BRPHY4_BR_CTRL_EXP90_BR_FORCE_LINK_CTL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP90,0x2,1)
#define BRPHY4_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_MASK                0x0002
#define BRPHY4_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_ALIGN               0
#define BRPHY4_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_BITS                1
#define BRPHY4_BR_CTRL_EXP90_BR_FORCE_LINK_CTL_SHIFT               1

/* BRPHY4_BR_CTRL :: EXP90 :: BR_EN [00:00] */
#define Wr_BRPHY4_BR_CTRL_EXP90_BR_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP90,0x1,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP90_BR_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP90,0x1,0)
#define BRPHY4_BR_CTRL_EXP90_BR_EN_MASK                            0x0001
#define BRPHY4_BR_CTRL_EXP90_BR_EN_ALIGN                           0
#define BRPHY4_BR_CTRL_EXP90_BR_EN_BITS                            1
#define BRPHY4_BR_CTRL_EXP90_BR_EN_SHIFT                           0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP91
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP91 :: DIG_HPF_OV [15:15] */
#define Wr_BRPHY4_BR_CTRL_EXP91_DIG_HPF_OV(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0x8000,15,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_DIG_HPF_OV(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0x8000,15)
#define BRPHY4_BR_CTRL_EXP91_DIG_HPF_OV_MASK                       0x8000
#define BRPHY4_BR_CTRL_EXP91_DIG_HPF_OV_ALIGN                      0
#define BRPHY4_BR_CTRL_EXP91_DIG_HPF_OV_BITS                       1
#define BRPHY4_BR_CTRL_EXP91_DIG_HPF_OV_SHIFT                      15

/* BRPHY4_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV [14:14] */
#define Wr_BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0x4000,14,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0x4000,14)
#define BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_MASK               0x4000
#define BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_ALIGN              0
#define BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_BITS               1
#define BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_SHIFT              14

/* BRPHY4_BR_CTRL :: EXP91 :: INV_LRE_GMII_TXC [13:13] */
#define Wr_BRPHY4_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0x2000,13,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_INV_LRE_GMII_TXC(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0x2000,13)
#define BRPHY4_BR_CTRL_EXP91_INV_LRE_GMII_TXC_MASK                 0x2000
#define BRPHY4_BR_CTRL_EXP91_INV_LRE_GMII_TXC_ALIGN                0
#define BRPHY4_BR_CTRL_EXP91_INV_LRE_GMII_TXC_BITS                 1
#define BRPHY4_BR_CTRL_EXP91_INV_LRE_GMII_TXC_SHIFT                13

/* BRPHY4_BR_CTRL :: EXP91 :: AGC_AUTOSTAGING_DIS [12:12] */
#define Wr_BRPHY4_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0x1000,12,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0x1000,12)
#define BRPHY4_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_MASK              0x1000
#define BRPHY4_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_ALIGN             0
#define BRPHY4_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_BITS              1
#define BRPHY4_BR_CTRL_EXP91_AGC_AUTOSTAGING_DIS_SHIFT             12

/* BRPHY4_BR_CTRL :: EXP91 :: BRPGA [11:09] */
#define Wr_BRPHY4_BR_CTRL_EXP91_BRPGA(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0xe00,9,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_BRPGA(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0xe00,9)
#define BRPHY4_BR_CTRL_EXP91_BRPGA_MASK                            0x0e00
#define BRPHY4_BR_CTRL_EXP91_BRPGA_ALIGN                           0
#define BRPHY4_BR_CTRL_EXP91_BRPGA_BITS                            3
#define BRPHY4_BR_CTRL_EXP91_BRPGA_SHIFT                           9

/* BRPHY4_BR_CTRL :: EXP91 :: BRCONFIG [08:04] */
#define Wr_BRPHY4_BR_CTRL_EXP91_BRCONFIG(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0x1f0,4,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_BRCONFIG(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0x1f0,4)
#define BRPHY4_BR_CTRL_EXP91_BRCONFIG_MASK                         0x01f0
#define BRPHY4_BR_CTRL_EXP91_BRCONFIG_ALIGN                        0
#define BRPHY4_BR_CTRL_EXP91_BRCONFIG_BITS                         5
#define BRPHY4_BR_CTRL_EXP91_BRCONFIG_SHIFT                        4

/* BRPHY4_BR_CTRL :: EXP91 :: ACQP_EN_ECO_DIS [03:03] */
#define Wr_BRPHY4_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0x8,3,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_ACQP_EN_ECO_DIS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0x8,3)
#define BRPHY4_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_MASK                  0x0008
#define BRPHY4_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_ALIGN                 0
#define BRPHY4_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_BITS                  1
#define BRPHY4_BR_CTRL_EXP91_ACQP_EN_ECO_DIS_SHIFT                 3

/* BRPHY4_BR_CTRL :: EXP91 :: BR_N_TOGGLE_DIS_OV_VAL [02:02] */
#define Wr_BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0x4,2,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0x4,2)
#define BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_MASK           0x0004
#define BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_ALIGN          0
#define BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_BITS           1
#define BRPHY4_BR_CTRL_EXP91_BR_N_TOGGLE_DIS_OV_VAL_SHIFT          2

/* BRPHY4_BR_CTRL :: EXP91 :: TXSCR_ZERO_SEED [01:01] */
#define Wr_BRPHY4_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0x2,1,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_TXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0x2,1)
#define BRPHY4_BR_CTRL_EXP91_TXSCR_ZERO_SEED_MASK                  0x0002
#define BRPHY4_BR_CTRL_EXP91_TXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY4_BR_CTRL_EXP91_TXSCR_ZERO_SEED_BITS                  1
#define BRPHY4_BR_CTRL_EXP91_TXSCR_ZERO_SEED_SHIFT                 1

/* BRPHY4_BR_CTRL :: EXP91 :: RXSCR_ZERO_SEED [00:00] */
#define Wr_BRPHY4_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP91,0x1,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP91_RXSCR_ZERO_SEED(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP91,0x1,0)
#define BRPHY4_BR_CTRL_EXP91_RXSCR_ZERO_SEED_MASK                  0x0001
#define BRPHY4_BR_CTRL_EXP91_RXSCR_ZERO_SEED_ALIGN                 0
#define BRPHY4_BR_CTRL_EXP91_RXSCR_ZERO_SEED_BITS                  1
#define BRPHY4_BR_CTRL_EXP91_RXSCR_ZERO_SEED_SHIFT                 0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP92
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP92 :: DLLCONV_OV_EN [15:15] */
#define Wr_BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x8000,15,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x8000,15)
#define BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_EN_MASK                    0x8000
#define BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_EN_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_EN_BITS                    1
#define BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_EN_SHIFT                   15

/* BRPHY4_BR_CTRL :: EXP92 :: DLLCONV_OV_VAL [14:14] */
#define Wr_BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x4000,14,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_VAL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x4000,14)
#define BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_VAL_MASK                   0x4000
#define BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_VAL_ALIGN                  0
#define BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_VAL_BITS                   1
#define BRPHY4_BR_CTRL_EXP92_DLLCONV_OV_VAL_SHIFT                  14

/* BRPHY4_BR_CTRL :: EXP92 :: BR_SLAVE_POL_COR_EN [13:13] */
#define Wr_BRPHY4_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x2000,13,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x2000,13)
#define BRPHY4_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_MASK              0x2000
#define BRPHY4_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_ALIGN             0
#define BRPHY4_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_BITS              1
#define BRPHY4_BR_CTRL_EXP92_BR_SLAVE_POL_COR_EN_SHIFT             13

/* BRPHY4_BR_CTRL :: EXP92 :: BR_EDGE_RATE_SEL [12:11] */
#define Wr_BRPHY4_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x1800,11,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_BR_EDGE_RATE_SEL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x1800,11)
#define BRPHY4_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_MASK                 0x1800
#define BRPHY4_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_ALIGN                0
#define BRPHY4_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_BITS                 2
#define BRPHY4_BR_CTRL_EXP92_BR_EDGE_RATE_SEL_SHIFT                11

/* BRPHY4_BR_CTRL :: EXP92 :: BR_PCS_RRNOK_POL_EN [10:10] */
#define Wr_BRPHY4_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x400,10,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x400,10)
#define BRPHY4_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_MASK              0x0400
#define BRPHY4_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_ALIGN             0
#define BRPHY4_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_BITS              1
#define BRPHY4_BR_CTRL_EXP92_BR_PCS_RRNOK_POL_EN_SHIFT             10

/* BRPHY4_BR_CTRL :: EXP92 :: LDS_LNK_CHK_ECO_DIS [09:09] */
#define Wr_BRPHY4_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x200,9,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x200,9)
#define BRPHY4_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_MASK              0x0200
#define BRPHY4_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_ALIGN             0
#define BRPHY4_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_BITS              1
#define BRPHY4_BR_CTRL_EXP92_LDS_LNK_CHK_ECO_DIS_SHIFT             9

/* BRPHY4_BR_CTRL :: EXP92 :: BR_PCS_POL_EN [08:08] */
#define Wr_BRPHY4_BR_CTRL_EXP92_BR_PCS_POL_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x100,8,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_BR_PCS_POL_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x100,8)
#define BRPHY4_BR_CTRL_EXP92_BR_PCS_POL_EN_MASK                    0x0100
#define BRPHY4_BR_CTRL_EXP92_BR_PCS_POL_EN_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP92_BR_PCS_POL_EN_BITS                    1
#define BRPHY4_BR_CTRL_EXP92_BR_PCS_POL_EN_SHIFT                   8

/* BRPHY4_BR_CTRL :: EXP92 :: JAB_MON_DIS [07:07] */
#define Wr_BRPHY4_BR_CTRL_EXP92_JAB_MON_DIS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x80,7,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_JAB_MON_DIS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x80,7)
#define BRPHY4_BR_CTRL_EXP92_JAB_MON_DIS_MASK                      0x0080
#define BRPHY4_BR_CTRL_EXP92_JAB_MON_DIS_ALIGN                     0
#define BRPHY4_BR_CTRL_EXP92_JAB_MON_DIS_BITS                      1
#define BRPHY4_BR_CTRL_EXP92_JAB_MON_DIS_SHIFT                     7

/* BRPHY4_BR_CTRL :: EXP92 :: BR_AGCSID_TMR_EN [06:06] */
#define Wr_BRPHY4_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x40,6,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_BR_AGCSID_TMR_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x40,6)
#define BRPHY4_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_MASK                 0x0040
#define BRPHY4_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_ALIGN                0
#define BRPHY4_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_BITS                 1
#define BRPHY4_BR_CTRL_EXP92_BR_AGCSID_TMR_EN_SHIFT                6

/* BRPHY4_BR_CTRL :: EXP92 :: BR_SYM_XSCR_EN [05:05] */
#define Wr_BRPHY4_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x20,5,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_BR_SYM_XSCR_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x20,5)
#define BRPHY4_BR_CTRL_EXP92_BR_SYM_XSCR_EN_MASK                   0x0020
#define BRPHY4_BR_CTRL_EXP92_BR_SYM_XSCR_EN_ALIGN                  0
#define BRPHY4_BR_CTRL_EXP92_BR_SYM_XSCR_EN_BITS                   1
#define BRPHY4_BR_CTRL_EXP92_BR_SYM_XSCR_EN_SHIFT                  5

/* BRPHY4_BR_CTRL :: EXP92 :: CHK_DELIMITER [04:04] */
#define Wr_BRPHY4_BR_CTRL_EXP92_CHK_DELIMITER(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x10,4,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_CHK_DELIMITER(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x10,4)
#define BRPHY4_BR_CTRL_EXP92_CHK_DELIMITER_MASK                    0x0010
#define BRPHY4_BR_CTRL_EXP92_CHK_DELIMITER_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP92_CHK_DELIMITER_BITS                    1
#define BRPHY4_BR_CTRL_EXP92_CHK_DELIMITER_SHIFT                   4

/* BRPHY4_BR_CTRL :: EXP92 :: TX_READ_DLY [03:02] */
#define Wr_BRPHY4_BR_CTRL_EXP92_TX_READ_DLY(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0xc,2,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_TX_READ_DLY(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0xc,2)
#define BRPHY4_BR_CTRL_EXP92_TX_READ_DLY_MASK                      0x000c
#define BRPHY4_BR_CTRL_EXP92_TX_READ_DLY_ALIGN                     0
#define BRPHY4_BR_CTRL_EXP92_TX_READ_DLY_BITS                      2
#define BRPHY4_BR_CTRL_EXP92_TX_READ_DLY_SHIFT                     2

/* BRPHY4_BR_CTRL :: EXP92 :: RX_READ_DLY [01:00] */
#define Wr_BRPHY4_BR_CTRL_EXP92_RX_READ_DLY(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP92,0x3,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP92_RX_READ_DLY(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP92,0x3,0)
#define BRPHY4_BR_CTRL_EXP92_RX_READ_DLY_MASK                      0x0003
#define BRPHY4_BR_CTRL_EXP92_RX_READ_DLY_ALIGN                     0
#define BRPHY4_BR_CTRL_EXP92_RX_READ_DLY_BITS                      2
#define BRPHY4_BR_CTRL_EXP92_RX_READ_DLY_SHIFT                     0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP93
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP93 :: LDS_CAP_DOWNGRADE_DIS [15:15] */
#define Wr_BRPHY4_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP93,0x8000,15,x)
#define Rd_BRPHY4_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP93,0x8000,15)
#define BRPHY4_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_MASK            0x8000
#define BRPHY4_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_ALIGN           0
#define BRPHY4_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_BITS            1
#define BRPHY4_BR_CTRL_EXP93_LDS_CAP_DOWNGRADE_DIS_SHIFT           15

/* BRPHY4_BR_CTRL :: EXP93 :: LDS_REORDER_DIS [14:14] */
#define Wr_BRPHY4_BR_CTRL_EXP93_LDS_REORDER_DIS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP93,0x4000,14,x)
#define Rd_BRPHY4_BR_CTRL_EXP93_LDS_REORDER_DIS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP93,0x4000,14)
#define BRPHY4_BR_CTRL_EXP93_LDS_REORDER_DIS_MASK                  0x4000
#define BRPHY4_BR_CTRL_EXP93_LDS_REORDER_DIS_ALIGN                 0
#define BRPHY4_BR_CTRL_EXP93_LDS_REORDER_DIS_BITS                  1
#define BRPHY4_BR_CTRL_EXP93_LDS_REORDER_DIS_SHIFT                 14

/* BRPHY4_BR_CTRL :: EXP93 :: LDS_SIM [13:13] */
#define Wr_BRPHY4_BR_CTRL_EXP93_LDS_SIM(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP93,0x2000,13,x)
#define Rd_BRPHY4_BR_CTRL_EXP93_LDS_SIM(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP93,0x2000,13)
#define BRPHY4_BR_CTRL_EXP93_LDS_SIM_MASK                          0x2000
#define BRPHY4_BR_CTRL_EXP93_LDS_SIM_ALIGN                         0
#define BRPHY4_BR_CTRL_EXP93_LDS_SIM_BITS                          1
#define BRPHY4_BR_CTRL_EXP93_LDS_SIM_SHIFT                         13

/* BRPHY4_BR_CTRL :: EXP93 :: LDS_SCR_ON [12:12] */
#define Wr_BRPHY4_BR_CTRL_EXP93_LDS_SCR_ON(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP93,0x1000,12,x)
#define Rd_BRPHY4_BR_CTRL_EXP93_LDS_SCR_ON(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP93,0x1000,12)
#define BRPHY4_BR_CTRL_EXP93_LDS_SCR_ON_MASK                       0x1000
#define BRPHY4_BR_CTRL_EXP93_LDS_SCR_ON_ALIGN                      0
#define BRPHY4_BR_CTRL_EXP93_LDS_SCR_ON_BITS                       1
#define BRPHY4_BR_CTRL_EXP93_LDS_SCR_ON_SHIFT                      12

/* BRPHY4_BR_CTRL :: EXP93 :: LDS_PHASE_BYP [11:11] */
#define Wr_BRPHY4_BR_CTRL_EXP93_LDS_PHASE_BYP(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP93,0x800,11,x)
#define Rd_BRPHY4_BR_CTRL_EXP93_LDS_PHASE_BYP(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP93,0x800,11)
#define BRPHY4_BR_CTRL_EXP93_LDS_PHASE_BYP_MASK                    0x0800
#define BRPHY4_BR_CTRL_EXP93_LDS_PHASE_BYP_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP93_LDS_PHASE_BYP_BITS                    1
#define BRPHY4_BR_CTRL_EXP93_LDS_PHASE_BYP_SHIFT                   11

/* BRPHY4_BR_CTRL :: EXP93 :: LDS_PHASE_INIT [10:08] */
#define Wr_BRPHY4_BR_CTRL_EXP93_LDS_PHASE_INIT(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP93,0x700,8,x)
#define Rd_BRPHY4_BR_CTRL_EXP93_LDS_PHASE_INIT(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP93,0x700,8)
#define BRPHY4_BR_CTRL_EXP93_LDS_PHASE_INIT_MASK                   0x0700
#define BRPHY4_BR_CTRL_EXP93_LDS_PHASE_INIT_ALIGN                  0
#define BRPHY4_BR_CTRL_EXP93_LDS_PHASE_INIT_BITS                   3
#define BRPHY4_BR_CTRL_EXP93_LDS_PHASE_INIT_SHIFT                  8

/* BRPHY4_BR_CTRL :: EXP93 :: LDS_PEAK_THR [07:00] */
#define Wr_BRPHY4_BR_CTRL_EXP93_LDS_PEAK_THR(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP93,0xff,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP93_LDS_PEAK_THR(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP93,0xff,0)
#define BRPHY4_BR_CTRL_EXP93_LDS_PEAK_THR_MASK                     0x00ff
#define BRPHY4_BR_CTRL_EXP93_LDS_PEAK_THR_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP93_LDS_PEAK_THR_BITS                     8
#define BRPHY4_BR_CTRL_EXP93_LDS_PEAK_THR_SHIFT                    0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP94
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP94 :: LDS_LEN_THR1 [15:08] */
#define Wr_BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR1(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP94,0xff00,8,x)
#define Rd_BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR1(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP94,0xff00,8)
#define BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR1_MASK                     0xff00
#define BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR1_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR1_BITS                     8
#define BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR1_SHIFT                    8

/* BRPHY4_BR_CTRL :: EXP94 :: LDS_LEN_THR0 [07:00] */
#define Wr_BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR0(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP94,0xff,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR0(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP94,0xff,0)
#define BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR0_MASK                     0x00ff
#define BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR0_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR0_BITS                     8
#define BRPHY4_BR_CTRL_EXP94_LDS_LEN_THR0_SHIFT                    0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP95
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP95 :: LDS_LEN_THR3 [15:08] */
#define Wr_BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR3(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP95,0xff00,8,x)
#define Rd_BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR3(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP95,0xff00,8)
#define BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR3_MASK                     0xff00
#define BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR3_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR3_BITS                     8
#define BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR3_SHIFT                    8

/* BRPHY4_BR_CTRL :: EXP95 :: LDS_LEN_THR2 [07:00] */
#define Wr_BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR2(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP95,0xff,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR2(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP95,0xff,0)
#define BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR2_MASK                     0x00ff
#define BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR2_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR2_BITS                     8
#define BRPHY4_BR_CTRL_EXP95_LDS_LEN_THR2_SHIFT                    0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP96
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP96 :: LDS_TONE_FREQ [15:15] */
#define Wr_BRPHY4_BR_CTRL_EXP96_LDS_TONE_FREQ(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP96,0x8000,15,x)
#define Rd_BRPHY4_BR_CTRL_EXP96_LDS_TONE_FREQ(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP96,0x8000,15)
#define BRPHY4_BR_CTRL_EXP96_LDS_TONE_FREQ_MASK                    0x8000
#define BRPHY4_BR_CTRL_EXP96_LDS_TONE_FREQ_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP96_LDS_TONE_FREQ_BITS                    1
#define BRPHY4_BR_CTRL_EXP96_LDS_TONE_FREQ_SHIFT                   15

/* BRPHY4_BR_CTRL :: EXP96 :: LDS_EXT_AB_DWNGRD [14:14] */
#define Wr_BRPHY4_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP96,0x4000,14,x)
#define Rd_BRPHY4_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP96,0x4000,14)
#define BRPHY4_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_MASK                0x4000
#define BRPHY4_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_ALIGN               0
#define BRPHY4_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_BITS                1
#define BRPHY4_BR_CTRL_EXP96_LDS_EXT_AB_DWNGRD_SHIFT               14

/* BRPHY4_BR_CTRL :: EXP96 :: LDS_SCAN_FSM [13:12] */
#define Wr_BRPHY4_BR_CTRL_EXP96_LDS_SCAN_FSM(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP96,0x3000,12,x)
#define Rd_BRPHY4_BR_CTRL_EXP96_LDS_SCAN_FSM(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP96,0x3000,12)
#define BRPHY4_BR_CTRL_EXP96_LDS_SCAN_FSM_MASK                     0x3000
#define BRPHY4_BR_CTRL_EXP96_LDS_SCAN_FSM_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP96_LDS_SCAN_FSM_BITS                     2
#define BRPHY4_BR_CTRL_EXP96_LDS_SCAN_FSM_SHIFT                    12

/* BRPHY4_BR_CTRL :: EXP96 :: CUR_LOC_FNUM [11:04] */
#define Wr_BRPHY4_BR_CTRL_EXP96_CUR_LOC_FNUM(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP96,0xff0,4,x)
#define Rd_BRPHY4_BR_CTRL_EXP96_CUR_LOC_FNUM(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP96,0xff0,4)
#define BRPHY4_BR_CTRL_EXP96_CUR_LOC_FNUM_MASK                     0x0ff0
#define BRPHY4_BR_CTRL_EXP96_CUR_LOC_FNUM_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP96_CUR_LOC_FNUM_BITS                     8
#define BRPHY4_BR_CTRL_EXP96_CUR_LOC_FNUM_SHIFT                    4

/* BRPHY4_BR_CTRL :: EXP96 :: LDS_SPD [03:00] */
#define Wr_BRPHY4_BR_CTRL_EXP96_LDS_SPD(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP96,0xf,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP96_LDS_SPD(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP96,0xf,0)
#define BRPHY4_BR_CTRL_EXP96_LDS_SPD_MASK                          0x000f
#define BRPHY4_BR_CTRL_EXP96_LDS_SPD_ALIGN                         0
#define BRPHY4_BR_CTRL_EXP96_LDS_SPD_BITS                          4
#define BRPHY4_BR_CTRL_EXP96_LDS_SPD_SHIFT                         0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP97
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP97 :: LDS_TX_FSM_H [15:12] */
#define Wr_BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_H(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP97,0xf000,12,x)
#define Rd_BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_H(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP97,0xf000,12)
#define BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_H_MASK                     0xf000
#define BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_H_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_H_BITS                     4
#define BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_H_SHIFT                    12

/* BRPHY4_BR_CTRL :: EXP97 :: LDS_TX_FSM_L [11:08] */
#define Wr_BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_L(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP97,0xf00,8,x)
#define Rd_BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_L(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP97,0xf00,8)
#define BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_L_MASK                     0x0f00
#define BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_L_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_L_BITS                     4
#define BRPHY4_BR_CTRL_EXP97_LDS_TX_FSM_L_SHIFT                    8

/* BRPHY4_BR_CTRL :: EXP97 :: LDS_ARB_FSM_H [07:04] */
#define Wr_BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP97,0xf0,4,x)
#define Rd_BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_H(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP97,0xf0,4)
#define BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_H_MASK                    0x00f0
#define BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_H_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_H_BITS                    4
#define BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_H_SHIFT                   4

/* BRPHY4_BR_CTRL :: EXP97 :: LDS_ARB_FSM_L [03:00] */
#define Wr_BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP97,0xf,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_L(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP97,0xf,0)
#define BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_L_MASK                    0x000f
#define BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_L_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_L_BITS                    4
#define BRPHY4_BR_CTRL_EXP97_LDS_ARB_FSM_L_SHIFT                   0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP99
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP99 :: LDS_PGACTRL [15:10] */
#define Wr_BRPHY4_BR_CTRL_EXP99_LDS_PGACTRL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP99,0xfc00,10,x)
#define Rd_BRPHY4_BR_CTRL_EXP99_LDS_PGACTRL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP99,0xfc00,10)
#define BRPHY4_BR_CTRL_EXP99_LDS_PGACTRL_MASK                      0xfc00
#define BRPHY4_BR_CTRL_EXP99_LDS_PGACTRL_ALIGN                     0
#define BRPHY4_BR_CTRL_EXP99_LDS_PGACTRL_BITS                      6
#define BRPHY4_BR_CTRL_EXP99_LDS_PGACTRL_SHIFT                     10

/* BRPHY4_BR_CTRL :: EXP99 :: TXDIS_TMR_OPT [09:07] */
#define Wr_BRPHY4_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP99,0x380,7,x)
#define Rd_BRPHY4_BR_CTRL_EXP99_TXDIS_TMR_OPT(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP99,0x380,7)
#define BRPHY4_BR_CTRL_EXP99_TXDIS_TMR_OPT_MASK                    0x0380
#define BRPHY4_BR_CTRL_EXP99_TXDIS_TMR_OPT_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP99_TXDIS_TMR_OPT_BITS                    3
#define BRPHY4_BR_CTRL_EXP99_TXDIS_TMR_OPT_SHIFT                   7

/* BRPHY4_BR_CTRL :: EXP99 :: LNK_TMR_OPT [06:04] */
#define Wr_BRPHY4_BR_CTRL_EXP99_LNK_TMR_OPT(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP99,0x70,4,x)
#define Rd_BRPHY4_BR_CTRL_EXP99_LNK_TMR_OPT(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP99,0x70,4)
#define BRPHY4_BR_CTRL_EXP99_LNK_TMR_OPT_MASK                      0x0070
#define BRPHY4_BR_CTRL_EXP99_LNK_TMR_OPT_ALIGN                     0
#define BRPHY4_BR_CTRL_EXP99_LNK_TMR_OPT_BITS                      3
#define BRPHY4_BR_CTRL_EXP99_LNK_TMR_OPT_SHIFT                     4

/* BRPHY4_BR_CTRL :: EXP99 :: BST_TMR_OPT [03:01] */
#define Wr_BRPHY4_BR_CTRL_EXP99_BST_TMR_OPT(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP99,0xe,1,x)
#define Rd_BRPHY4_BR_CTRL_EXP99_BST_TMR_OPT(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP99,0xe,1)
#define BRPHY4_BR_CTRL_EXP99_BST_TMR_OPT_MASK                      0x000e
#define BRPHY4_BR_CTRL_EXP99_BST_TMR_OPT_ALIGN                     0
#define BRPHY4_BR_CTRL_EXP99_BST_TMR_OPT_BITS                      3
#define BRPHY4_BR_CTRL_EXP99_BST_TMR_OPT_SHIFT                     1

/* BRPHY4_BR_CTRL :: EXP99 :: FASTBST [00:00] */
#define Wr_BRPHY4_BR_CTRL_EXP99_FASTBST(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP99,0x1,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP99_FASTBST(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP99,0x1,0)
#define BRPHY4_BR_CTRL_EXP99_FASTBST_MASK                          0x0001
#define BRPHY4_BR_CTRL_EXP99_FASTBST_ALIGN                         0
#define BRPHY4_BR_CTRL_EXP99_FASTBST_BITS                          1
#define BRPHY4_BR_CTRL_EXP99_FASTBST_SHIFT                         0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP9A
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP9A :: LRE_REG_OV_EN [15:15] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x8000,15,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x8000,15)
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_EN_MASK                    0x8000
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_EN_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_EN_BITS                    1
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_EN_SHIFT                   15

/* BRPHY4_BR_CTRL :: EXP9A :: LRE_REG_OV_VAL [14:14] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x4000,14,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_VAL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x4000,14)
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_VAL_MASK                   0x4000
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_VAL_ALIGN                  0
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_VAL_BITS                   1
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_OV_VAL_SHIFT                  14

/* BRPHY4_BR_CTRL :: EXP9A :: LRE_REG_ACCESS_STAT [13:13] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x2000,13,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x2000,13)
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_MASK              0x2000
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_ALIGN             0
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_BITS              1
#define BRPHY4_BR_CTRL_EXP9A_LRE_REG_ACCESS_STAT_SHIFT             13

/* BRPHY4_BR_CTRL :: EXP9A :: LDS_LINK_CHK_EN [12:12] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x1000,12,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_LDS_LINK_CHK_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x1000,12)
#define BRPHY4_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_MASK                  0x1000
#define BRPHY4_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_ALIGN                 0
#define BRPHY4_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_BITS                  1
#define BRPHY4_BR_CTRL_EXP9A_LDS_LINK_CHK_EN_SHIFT                 12

/* BRPHY4_BR_CTRL :: EXP9A :: BR_AGC_TAR_OV_EN [11:11] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x800,11,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x800,11)
#define BRPHY4_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_MASK                 0x0800
#define BRPHY4_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_ALIGN                0
#define BRPHY4_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_BITS                 1
#define BRPHY4_BR_CTRL_EXP9A_BR_AGC_TAR_OV_EN_SHIFT                11

/* BRPHY4_BR_CTRL :: EXP9A :: LDS_TIMER_OV_EN [10:10] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x400,10,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_LDS_TIMER_OV_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x400,10)
#define BRPHY4_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_MASK                  0x0400
#define BRPHY4_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_ALIGN                 0
#define BRPHY4_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_BITS                  1
#define BRPHY4_BR_CTRL_EXP9A_LDS_TIMER_OV_EN_SHIFT                 10

/* BRPHY4_BR_CTRL :: EXP9A :: BR_LOST_TOKEN_FIX [09:09] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x200,9,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x200,9)
#define BRPHY4_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_MASK                0x0200
#define BRPHY4_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_ALIGN               0
#define BRPHY4_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_BITS                1
#define BRPHY4_BR_CTRL_EXP9A_BR_LOST_TOKEN_FIX_SHIFT               9

/* BRPHY4_BR_CTRL :: EXP9A :: DLLCONV_EN_MSTR [08:08] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x100,8,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_DLLCONV_EN_MSTR(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x100,8)
#define BRPHY4_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_MASK                  0x0100
#define BRPHY4_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_ALIGN                 0
#define BRPHY4_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_BITS                  1
#define BRPHY4_BR_CTRL_EXP9A_DLLCONV_EN_MSTR_SHIFT                 8

/* BRPHY4_BR_CTRL :: EXP9A :: BR_10M1P_HALFOUT_EN [07:07] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x80,7,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x80,7)
#define BRPHY4_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_MASK              0x0080
#define BRPHY4_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_ALIGN             0
#define BRPHY4_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_BITS              1
#define BRPHY4_BR_CTRL_EXP9A_BR_10M1P_HALFOUT_EN_SHIFT             7

/* BRPHY4_BR_CTRL :: EXP9A :: BR_10M2P_HALFOUT_EN [06:06] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x40,6,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x40,6)
#define BRPHY4_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_MASK              0x0040
#define BRPHY4_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_ALIGN             0
#define BRPHY4_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_BITS              1
#define BRPHY4_BR_CTRL_EXP9A_BR_10M2P_HALFOUT_EN_SHIFT             6

/* BRPHY4_BR_CTRL :: EXP9A :: BR_HALFOUT_EN [05:05] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x20,5,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_BR_HALFOUT_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x20,5)
#define BRPHY4_BR_CTRL_EXP9A_BR_HALFOUT_EN_MASK                    0x0020
#define BRPHY4_BR_CTRL_EXP9A_BR_HALFOUT_EN_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP9A_BR_HALFOUT_EN_BITS                    1
#define BRPHY4_BR_CTRL_EXP9A_BR_HALFOUT_EN_SHIFT                   5

/* BRPHY4_BR_CTRL :: EXP9A :: CLK100T_ECO_DIS [04:04] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0x10,4,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_CLK100T_ECO_DIS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0x10,4)
#define BRPHY4_BR_CTRL_EXP9A_CLK100T_ECO_DIS_MASK                  0x0010
#define BRPHY4_BR_CTRL_EXP9A_CLK100T_ECO_DIS_ALIGN                 0
#define BRPHY4_BR_CTRL_EXP9A_CLK100T_ECO_DIS_BITS                  1
#define BRPHY4_BR_CTRL_EXP9A_CLK100T_ECO_DIS_SHIFT                 4

/* BRPHY4_BR_CTRL :: EXP9A :: CH_STATUS [03:00] */
#define Wr_BRPHY4_BR_CTRL_EXP9A_CH_STATUS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9A,0xf,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP9A_CH_STATUS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9A,0xf,0)
#define BRPHY4_BR_CTRL_EXP9A_CH_STATUS_MASK                        0x000f
#define BRPHY4_BR_CTRL_EXP9A_CH_STATUS_ALIGN                       0
#define BRPHY4_BR_CTRL_EXP9A_CH_STATUS_BITS                        4
#define BRPHY4_BR_CTRL_EXP9A_CH_STATUS_SHIFT                       0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP9B
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP9B :: BR_RATE_OV [15:13] */
#define Wr_BRPHY4_BR_CTRL_EXP9B_BR_RATE_OV(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9B,0xe000,13,x)
#define Rd_BRPHY4_BR_CTRL_EXP9B_BR_RATE_OV(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9B,0xe000,13)
#define BRPHY4_BR_CTRL_EXP9B_BR_RATE_OV_MASK                       0xe000
#define BRPHY4_BR_CTRL_EXP9B_BR_RATE_OV_ALIGN                      0
#define BRPHY4_BR_CTRL_EXP9B_BR_RATE_OV_BITS                       3
#define BRPHY4_BR_CTRL_EXP9B_BR_RATE_OV_SHIFT                      13

/* BRPHY4_BR_CTRL :: EXP9B :: BR_200MBPS_CLK_EN [12:12] */
#define Wr_BRPHY4_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9B,0x1000,12,x)
#define Rd_BRPHY4_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9B,0x1000,12)
#define BRPHY4_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_MASK                0x1000
#define BRPHY4_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_ALIGN               0
#define BRPHY4_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_BITS                1
#define BRPHY4_BR_CTRL_EXP9B_BR_200MBPS_CLK_EN_SHIFT               12

/* BRPHY4_BR_CTRL :: EXP9B :: BR_TXCLK_EN [11:11] */
#define Wr_BRPHY4_BR_CTRL_EXP9B_BR_TXCLK_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9B,0x800,11,x)
#define Rd_BRPHY4_BR_CTRL_EXP9B_BR_TXCLK_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9B,0x800,11)
#define BRPHY4_BR_CTRL_EXP9B_BR_TXCLK_EN_MASK                      0x0800
#define BRPHY4_BR_CTRL_EXP9B_BR_TXCLK_EN_ALIGN                     0
#define BRPHY4_BR_CTRL_EXP9B_BR_TXCLK_EN_BITS                      1
#define BRPHY4_BR_CTRL_EXP9B_BR_TXCLK_EN_SHIFT                     11

/* BRPHY4_BR_CTRL :: EXP9B :: BR_TXRXICLK_EN [10:10] */
#define Wr_BRPHY4_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9B,0x400,10,x)
#define Rd_BRPHY4_BR_CTRL_EXP9B_BR_TXRXICLK_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9B,0x400,10)
#define BRPHY4_BR_CTRL_EXP9B_BR_TXRXICLK_EN_MASK                   0x0400
#define BRPHY4_BR_CTRL_EXP9B_BR_TXRXICLK_EN_ALIGN                  0
#define BRPHY4_BR_CTRL_EXP9B_BR_TXRXICLK_EN_BITS                   1
#define BRPHY4_BR_CTRL_EXP9B_BR_TXRXICLK_EN_SHIFT                  10

/* BRPHY4_BR_CTRL :: EXP9B :: CLK_1G_DIV20 [09:09] */
#define Wr_BRPHY4_BR_CTRL_EXP9B_CLK_1G_DIV20(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9B,0x200,9,x)
#define Rd_BRPHY4_BR_CTRL_EXP9B_CLK_1G_DIV20(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9B,0x200,9)
#define BRPHY4_BR_CTRL_EXP9B_CLK_1G_DIV20_MASK                     0x0200
#define BRPHY4_BR_CTRL_EXP9B_CLK_1G_DIV20_ALIGN                    0
#define BRPHY4_BR_CTRL_EXP9B_CLK_1G_DIV20_BITS                     1
#define BRPHY4_BR_CTRL_EXP9B_CLK_1G_DIV20_SHIFT                    9

/* BRPHY4_BR_CTRL :: EXP9B :: LVL1_PROG_FREQ_DIV [08:05] */
#define Wr_BRPHY4_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9B,0x1e0,5,x)
#define Rd_BRPHY4_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9B,0x1e0,5)
#define BRPHY4_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_MASK               0x01e0
#define BRPHY4_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_ALIGN              0
#define BRPHY4_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_BITS               4
#define BRPHY4_BR_CTRL_EXP9B_LVL1_PROG_FREQ_DIV_SHIFT              5

/* BRPHY4_BR_CTRL :: EXP9B :: LVL2_PROG_FREQ_DIV [04:01] */
#define Wr_BRPHY4_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9B,0x1e,1,x)
#define Rd_BRPHY4_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9B,0x1e,1)
#define BRPHY4_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_MASK               0x001e
#define BRPHY4_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_ALIGN              0
#define BRPHY4_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_BITS               4
#define BRPHY4_BR_CTRL_EXP9B_LVL2_PROG_FREQ_DIV_SHIFT              1

/* BRPHY4_BR_CTRL :: EXP9B :: BR_PLL_CTL_EN [00:00] */
#define Wr_BRPHY4_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9B,0x1,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP9B_BR_PLL_CTL_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9B,0x1,0)
#define BRPHY4_BR_CTRL_EXP9B_BR_PLL_CTL_EN_MASK                    0x0001
#define BRPHY4_BR_CTRL_EXP9B_BR_PLL_CTL_EN_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP9B_BR_PLL_CTL_EN_BITS                    1
#define BRPHY4_BR_CTRL_EXP9B_BR_PLL_CTL_EN_SHIFT                   0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP9D
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP9D :: BR_IPR_BYPASS [15:15] */
#define Wr_BRPHY4_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9D,0x8000,15,x)
#define Rd_BRPHY4_BR_CTRL_EXP9D_BR_IPR_BYPASS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9D,0x8000,15)
#define BRPHY4_BR_CTRL_EXP9D_BR_IPR_BYPASS_MASK                    0x8000
#define BRPHY4_BR_CTRL_EXP9D_BR_IPR_BYPASS_ALIGN                   0
#define BRPHY4_BR_CTRL_EXP9D_BR_IPR_BYPASS_BITS                    1
#define BRPHY4_BR_CTRL_EXP9D_BR_IPR_BYPASS_SHIFT                   15

/* BRPHY4_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_VAL [14:14] */
#define Wr_BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9D,0x4000,14,x)
#define Rd_BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9D,0x4000,14)
#define BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_MASK               0x4000
#define BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_ALIGN              0
#define BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_BITS               1
#define BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_VAL_SHIFT              14

/* BRPHY4_BR_CTRL :: EXP9D :: BR_CLOCK_ON_OV_EN [13:13] */
#define Wr_BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9D,0x2000,13,x)
#define Rd_BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9D,0x2000,13)
#define BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_MASK                0x2000
#define BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_ALIGN               0
#define BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_BITS                1
#define BRPHY4_BR_CTRL_EXP9D_BR_CLOCK_ON_OV_EN_SHIFT               13

/* BRPHY4_BR_CTRL :: EXP9D :: LDS_SD_THR [12:08] */
#define Wr_BRPHY4_BR_CTRL_EXP9D_LDS_SD_THR(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9D,0x1f00,8,x)
#define Rd_BRPHY4_BR_CTRL_EXP9D_LDS_SD_THR(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9D,0x1f00,8)
#define BRPHY4_BR_CTRL_EXP9D_LDS_SD_THR_MASK                       0x1f00
#define BRPHY4_BR_CTRL_EXP9D_LDS_SD_THR_ALIGN                      0
#define BRPHY4_BR_CTRL_EXP9D_LDS_SD_THR_BITS                       5
#define BRPHY4_BR_CTRL_EXP9D_LDS_SD_THR_SHIFT                      8

/* BRPHY4_BR_CTRL :: EXP9D :: LDS_PEAK_THR_T125 [07:00] */
#define Wr_BRPHY4_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9D,0xff,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP9D_LDS_PEAK_THR_T125(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9D,0xff,0)
#define BRPHY4_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_MASK                0x00ff
#define BRPHY4_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_ALIGN               0
#define BRPHY4_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_BITS                8
#define BRPHY4_BR_CTRL_EXP9D_LDS_PEAK_THR_T125_SHIFT               0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP9E
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP9E :: LDS_LEN_THR1_T125 [15:08] */
#define Wr_BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9E,0xff00,8,x)
#define Rd_BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR1_T125(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9E,0xff00,8)
#define BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_MASK                0xff00
#define BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_ALIGN               0
#define BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_BITS                8
#define BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR1_T125_SHIFT               8

/* BRPHY4_BR_CTRL :: EXP9E :: LDS_LEN_THR0_T125 [07:00] */
#define Wr_BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9E,0xff,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR0_T125(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9E,0xff,0)
#define BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_MASK                0x00ff
#define BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_ALIGN               0
#define BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_BITS                8
#define BRPHY4_BR_CTRL_EXP9E_LDS_LEN_THR0_T125_SHIFT               0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXP9F
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXP9F :: LDS_LEN_THR3_T125 [15:08] */
#define Wr_BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9F,0xff00,8,x)
#define Rd_BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR3_T125(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9F,0xff00,8)
#define BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_MASK                0xff00
#define BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_ALIGN               0
#define BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_BITS                8
#define BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR3_T125_SHIFT               8

/* BRPHY4_BR_CTRL :: EXP9F :: LDS_LEN_THR2_T125 [07:00] */
#define Wr_BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) WriteRegBits16(BRPHY4_BR_CTRL_EXP9F,0xff,0,x)
#define Rd_BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR2_T125(x) ReadRegBits16(BRPHY4_BR_CTRL_EXP9F,0xff,0)
#define BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_MASK                0x00ff
#define BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_ALIGN               0
#define BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_BITS                8
#define BRPHY4_BR_CTRL_EXP9F_LDS_LEN_THR2_T125_SHIFT               0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXPA0
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXPA0 :: EPAGE_SPARE [15:02] */
#define Wr_BRPHY4_BR_CTRL_EXPA0_EPAGE_SPARE(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA0,0xfffc,2,x)
#define Rd_BRPHY4_BR_CTRL_EXPA0_EPAGE_SPARE(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA0,0xfffc,2)
#define BRPHY4_BR_CTRL_EXPA0_EPAGE_SPARE_MASK                      0xfffc
#define BRPHY4_BR_CTRL_EXPA0_EPAGE_SPARE_ALIGN                     0
#define BRPHY4_BR_CTRL_EXPA0_EPAGE_SPARE_BITS                      14
#define BRPHY4_BR_CTRL_EXPA0_EPAGE_SPARE_SHIFT                     2

/* BRPHY4_BR_CTRL :: EXPA0 :: PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY4_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA0,0x2,1,x)
#define Rd_BRPHY4_BR_CTRL_EXPA0_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA0,0x2,1)
#define BRPHY4_BR_CTRL_EXPA0_PAIR_1_250MBPS_MASK                   0x0002
#define BRPHY4_BR_CTRL_EXPA0_PAIR_1_250MBPS_ALIGN                  0
#define BRPHY4_BR_CTRL_EXPA0_PAIR_1_250MBPS_BITS                   1
#define BRPHY4_BR_CTRL_EXPA0_PAIR_1_250MBPS_SHIFT                  1

/* BRPHY4_BR_CTRL :: EXPA0 :: PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY4_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA0,0x1,0,x)
#define Rd_BRPHY4_BR_CTRL_EXPA0_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA0,0x1,0)
#define BRPHY4_BR_CTRL_EXPA0_PAIR_1_200MBPS_MASK                   0x0001
#define BRPHY4_BR_CTRL_EXPA0_PAIR_1_200MBPS_ALIGN                  0
#define BRPHY4_BR_CTRL_EXPA0_PAIR_1_200MBPS_BITS                   1
#define BRPHY4_BR_CTRL_EXPA0_PAIR_1_200MBPS_SHIFT                  0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXPA1
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXPA1 :: LP_EPAGE_SPARE [15:02] */
#define Wr_BRPHY4_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA1,0xfffc,2,x)
#define Rd_BRPHY4_BR_CTRL_EXPA1_LP_EPAGE_SPARE(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA1,0xfffc,2)
#define BRPHY4_BR_CTRL_EXPA1_LP_EPAGE_SPARE_MASK                   0xfffc
#define BRPHY4_BR_CTRL_EXPA1_LP_EPAGE_SPARE_ALIGN                  0
#define BRPHY4_BR_CTRL_EXPA1_LP_EPAGE_SPARE_BITS                   14
#define BRPHY4_BR_CTRL_EXPA1_LP_EPAGE_SPARE_SHIFT                  2

/* BRPHY4_BR_CTRL :: EXPA1 :: LP_PAIR_1_250MBPS [01:01] */
#define Wr_BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA1,0x2,1,x)
#define Rd_BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA1,0x2,1)
#define BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_MASK                0x0002
#define BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_ALIGN               0
#define BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_BITS                1
#define BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_250MBPS_SHIFT               1

/* BRPHY4_BR_CTRL :: EXPA1 :: LP_PAIR_1_200MBPS [00:00] */
#define Wr_BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA1,0x1,0,x)
#define Rd_BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA1,0x1,0)
#define BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_MASK                0x0001
#define BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_ALIGN               0
#define BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_BITS                1
#define BRPHY4_BR_CTRL_EXPA1_LP_PAIR_1_200MBPS_SHIFT               0


/****************************************************************************
 * BRPHY4_BR_CTRL :: EXPA2
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV_EN [15:15] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0x8000,15,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0x8000,15)
#define BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_MASK                  0x8000
#define BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_ALIGN                 0
#define BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_BITS                  1
#define BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_EN_SHIFT                 15

/* BRPHY4_BR_CTRL :: EXPA2 :: TFREQ_SEL_OV [14:14] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0x4000,14,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0x4000,14)
#define BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_MASK                     0x4000
#define BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_ALIGN                    0
#define BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_BITS                     1
#define BRPHY4_BR_CTRL_EXPA2_TFREQ_SEL_OV_SHIFT                    14

/* BRPHY4_BR_CTRL :: EXPA2 :: LOW_FREQ_TONE [13:13] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0x2000,13,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_LOW_FREQ_TONE(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0x2000,13)
#define BRPHY4_BR_CTRL_EXPA2_LOW_FREQ_TONE_MASK                    0x2000
#define BRPHY4_BR_CTRL_EXPA2_LOW_FREQ_TONE_ALIGN                   0
#define BRPHY4_BR_CTRL_EXPA2_LOW_FREQ_TONE_BITS                    1
#define BRPHY4_BR_CTRL_EXPA2_LOW_FREQ_TONE_SHIFT                   13

/* BRPHY4_BR_CTRL :: EXPA2 :: BR_MAXWAIT_CTL [12:11] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0x1800,11,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_BR_MAXWAIT_CTL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0x1800,11)
#define BRPHY4_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_MASK                   0x1800
#define BRPHY4_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_ALIGN                  0
#define BRPHY4_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_BITS                   2
#define BRPHY4_BR_CTRL_EXPA2_BR_MAXWAIT_CTL_SHIFT                  11

/* BRPHY4_BR_CTRL :: EXPA2 :: BR_M2S2_TMR_CTL [10:10] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0x400,10,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0x400,10)
#define BRPHY4_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_MASK                  0x0400
#define BRPHY4_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_ALIGN                 0
#define BRPHY4_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_BITS                  1
#define BRPHY4_BR_CTRL_EXPA2_BR_M2S2_TMR_CTL_SHIFT                 10

/* BRPHY4_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_FDX_S [09:09] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0x200,9,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0x200,9)
#define BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_MASK               0x0200
#define BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_ALIGN              0
#define BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_BITS               1
#define BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_FDX_S_SHIFT              9

/* BRPHY4_BR_CTRL :: EXPA2 :: BR_SKIP_FIFO_HDX [08:08] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0x100,8,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0x100,8)
#define BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_MASK                 0x0100
#define BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_ALIGN                0
#define BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_BITS                 1
#define BRPHY4_BR_CTRL_EXPA2_BR_SKIP_FIFO_HDX_SHIFT                8

/* BRPHY4_BR_CTRL :: EXPA2 :: BR_PSD_TIMER_CTL [07:06] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0xc0,6,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0xc0,6)
#define BRPHY4_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_MASK                 0x00c0
#define BRPHY4_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_ALIGN                0
#define BRPHY4_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_BITS                 2
#define BRPHY4_BR_CTRL_EXPA2_BR_PSD_TIMER_CTL_SHIFT                6

/* BRPHY4_BR_CTRL :: EXPA2 :: MAN_PHASE_CK1X [05:03] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0x38,3,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_MAN_PHASE_CK1X(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0x38,3)
#define BRPHY4_BR_CTRL_EXPA2_MAN_PHASE_CK1X_MASK                   0x0038
#define BRPHY4_BR_CTRL_EXPA2_MAN_PHASE_CK1X_ALIGN                  0
#define BRPHY4_BR_CTRL_EXPA2_MAN_PHASE_CK1X_BITS                   3
#define BRPHY4_BR_CTRL_EXPA2_MAN_PHASE_CK1X_SHIFT                  3

/* BRPHY4_BR_CTRL :: EXPA2 :: LDS_PHASE_CK1X [02:00] */
#define Wr_BRPHY4_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) WriteRegBits16(BRPHY4_BR_CTRL_EXPA2,0x7,0,x)
#define Rd_BRPHY4_BR_CTRL_EXPA2_LDS_PHASE_CK1X(x) ReadRegBits16(BRPHY4_BR_CTRL_EXPA2,0x7,0)
#define BRPHY4_BR_CTRL_EXPA2_LDS_PHASE_CK1X_MASK                   0x0007
#define BRPHY4_BR_CTRL_EXPA2_LDS_PHASE_CK1X_ALIGN                  0
#define BRPHY4_BR_CTRL_EXPA2_LDS_PHASE_CK1X_BITS                   3
#define BRPHY4_BR_CTRL_EXPA2_LDS_PHASE_CK1X_SHIFT                  0


/****************************************************************************
 * BRPHY4_BR_CTRL :: BR_MISC_CONTROL_STATUS
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_2ND_FILTER [15:15] */
#define Wr_BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) WriteRegBits16(BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15,x)
#define Rd_BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER(x) ReadRegBits16(BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS,0x8000,15)
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_MASK 0x8000
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_ALIGN 0
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_BITS 1
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_2ND_FILTER_SHIFT 15

/* BRPHY4_BR_CTRL :: BR_MISC_CONTROL_STATUS :: ENABLE_PR_DATAPATH [14:14] */
#define Wr_BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) WriteRegBits16(BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14,x)
#define Rd_BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH(x) ReadRegBits16(BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS,0x4000,14)
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_MASK 0x4000
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_ALIGN 0
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_BITS 1
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_ENABLE_PR_DATAPATH_SHIFT 14

/* BRPHY4_BR_CTRL :: BR_MISC_CONTROL_STATUS :: reserved0 [13:03] */
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_MASK       0x3ff8
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_ALIGN      0
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_BITS       11
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_RESERVED0_SHIFT      3

/* BRPHY4_BR_CTRL :: BR_MISC_CONTROL_STATUS :: BR_1P_PCS_SOL [02:00] */
#define Wr_BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) WriteRegBits16(BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0,x)
#define Rd_BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL(x) ReadRegBits16(BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS,0x7,0)
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_MASK   0x0007
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_ALIGN  0
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_BITS   3
#define BRPHY4_BR_CTRL_BR_MISC_CONTROL_STATUS_BR_1P_PCS_SOL_SHIFT  0


/****************************************************************************
 * BRPHY4_BR_CTRL :: BR250_CTL
 ***************************************************************************/
/* BRPHY4_BR_CTRL :: BR250_CTL :: BR_CURR_RATE [15:12] */
#define Wr_BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) WriteRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0xf000,12,x)
#define Rd_BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_RATE(x) ReadRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0xf000,12)
#define BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_RATE_MASK                 0xf000
#define BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_RATE_ALIGN                0
#define BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_RATE_BITS                 4
#define BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_RATE_SHIFT                12

/* BRPHY4_BR_CTRL :: BR250_CTL :: BR_CURR_PAIR [11:10] */
#define Wr_BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) WriteRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0xc00,10,x)
#define Rd_BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_PAIR(x) ReadRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0xc00,10)
#define BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_PAIR_MASK                 0x0c00
#define BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_PAIR_ALIGN                0
#define BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_PAIR_BITS                 2
#define BRPHY4_BR_CTRL_BR250_CTL_BR_CURR_PAIR_SHIFT                10

/* BRPHY4_BR_CTRL :: BR250_CTL :: reserved0 [09:08] */
#define BRPHY4_BR_CTRL_BR250_CTL_RESERVED0_MASK                    0x0300
#define BRPHY4_BR_CTRL_BR250_CTL_RESERVED0_ALIGN                   0
#define BRPHY4_BR_CTRL_BR250_CTL_RESERVED0_BITS                    2
#define BRPHY4_BR_CTRL_BR250_CTL_RESERVED0_SHIFT                   8

/* BRPHY4_BR_CTRL :: BR250_CTL :: BR_PAM5_200_sel [07:07] */
#define Wr_BRPHY4_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) WriteRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0x80,7,x)
#define Rd_BRPHY4_BR_CTRL_BR250_CTL_BR_PAM5_200_sel(x) ReadRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0x80,7)
#define BRPHY4_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_MASK              0x0080
#define BRPHY4_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_ALIGN             0
#define BRPHY4_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_BITS              1
#define BRPHY4_BR_CTRL_BR250_CTL_BR_PAM5_200_SEL_SHIFT             7

/* BRPHY4_BR_CTRL :: BR250_CTL :: LBKTst2 [06:06] */
#define Wr_BRPHY4_BR_CTRL_BR250_CTL_LBKTst2(x) WriteRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0x40,6,x)
#define Rd_BRPHY4_BR_CTRL_BR250_CTL_LBKTst2(x) ReadRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0x40,6)
#define BRPHY4_BR_CTRL_BR250_CTL_LBKTST2_MASK                      0x0040
#define BRPHY4_BR_CTRL_BR250_CTL_LBKTST2_ALIGN                     0
#define BRPHY4_BR_CTRL_BR250_CTL_LBKTST2_BITS                      1
#define BRPHY4_BR_CTRL_BR250_CTL_LBKTST2_SHIFT                     6

/* BRPHY4_BR_CTRL :: BR250_CTL :: CONF_GPLL_125 [05:05] */
#define Wr_BRPHY4_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) WriteRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0x20,5,x)
#define Rd_BRPHY4_BR_CTRL_BR250_CTL_CONF_GPLL_125(x) ReadRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0x20,5)
#define BRPHY4_BR_CTRL_BR250_CTL_CONF_GPLL_125_MASK                0x0020
#define BRPHY4_BR_CTRL_BR250_CTL_CONF_GPLL_125_ALIGN               0
#define BRPHY4_BR_CTRL_BR250_CTL_CONF_GPLL_125_BITS                1
#define BRPHY4_BR_CTRL_BR250_CTL_CONF_GPLL_125_SHIFT               5

/* BRPHY4_BR_CTRL :: BR250_CTL :: reserved1 [04:04] */
#define BRPHY4_BR_CTRL_BR250_CTL_RESERVED1_MASK                    0x0010
#define BRPHY4_BR_CTRL_BR250_CTL_RESERVED1_ALIGN                   0
#define BRPHY4_BR_CTRL_BR250_CTL_RESERVED1_BITS                    1
#define BRPHY4_BR_CTRL_BR250_CTL_RESERVED1_SHIFT                   4

/* BRPHY4_BR_CTRL :: BR250_CTL :: INTRLV_CTL [03:02] */
#define Wr_BRPHY4_BR_CTRL_BR250_CTL_INTRLV_CTL(x) WriteRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0xc,2,x)
#define Rd_BRPHY4_BR_CTRL_BR250_CTL_INTRLV_CTL(x) ReadRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0xc,2)
#define BRPHY4_BR_CTRL_BR250_CTL_INTRLV_CTL_MASK                   0x000c
#define BRPHY4_BR_CTRL_BR250_CTL_INTRLV_CTL_ALIGN                  0
#define BRPHY4_BR_CTRL_BR250_CTL_INTRLV_CTL_BITS                   2
#define BRPHY4_BR_CTRL_BR250_CTL_INTRLV_CTL_SHIFT                  2

/* BRPHY4_BR_CTRL :: BR250_CTL :: PAIR_CFG [01:00] */
#define Wr_BRPHY4_BR_CTRL_BR250_CTL_PAIR_CFG(x) WriteRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0x3,0,x)
#define Rd_BRPHY4_BR_CTRL_BR250_CTL_PAIR_CFG(x) ReadRegBits16(BRPHY4_BR_CTRL_BR250_CTL,0x3,0)
#define BRPHY4_BR_CTRL_BR250_CTL_PAIR_CFG_MASK                     0x0003
#define BRPHY4_BR_CTRL_BR250_CTL_PAIR_CFG_ALIGN                    0
#define BRPHY4_BR_CTRL_BR250_CTL_PAIR_CFG_BITS                     2
#define BRPHY4_BR_CTRL_BR250_CTL_PAIR_CFG_SHIFT                    0


/****************************************************************************
 * bcm89530_top_bridge_brphys_brphys4_BRPHY4_BR_CL22_IEEE
 ***************************************************************************/
/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: MII_CTRL
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: RESET [15:15] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_RESET(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x8000,15,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_RESET(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x8000,15)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESET_MASK                    0x8000
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESET_ALIGN                   0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESET_BITS                    1
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESET_SHIFT                   15

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: LOOPBACK [14:14] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x4000,14,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_LOOPBACK(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x4000,14)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_LOOPBACK_MASK                 0x4000
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_LOOPBACK_ALIGN                0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_LOOPBACK_BITS                 1
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_LOOPBACK_SHIFT                14

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: RESTART_LDS [13:13] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x2000,13,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_RESTART_LDS(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x2000,13)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_MASK              0x2000
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_ALIGN             0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_BITS              1
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESTART_LDS_SHIFT             13

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: LDS_ENABLE [12:12] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x1000,12,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x1000,12)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_MASK               0x1000
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_ALIGN              0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_BITS               1
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_LDS_ENABLE_SHIFT              12

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: POWER_DOWN [11:11] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x800,11,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_POWER_DOWN(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x800,11)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_MASK               0x0800
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_ALIGN              0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_BITS               1
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_POWER_DOWN_SHIFT              11

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: ISOLATE [10:10] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x400,10,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_ISOLATE(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x400,10)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_ISOLATE_MASK                  0x0400
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_ISOLATE_ALIGN                 0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_ISOLATE_BITS                  1
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_ISOLATE_SHIFT                 10

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: manual_speed_select_enable [09:09] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x200,9,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_manual_speed_select_enable(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x200,9)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_MASK 0x0200
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_BITS 1
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_MANUAL_SPEED_SELECT_ENABLE_SHIFT 9

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: Speed_Selection [08:06] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x1c0,6,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_Speed_Selection(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x1c0,6)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_MASK          0x01c0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_ALIGN         0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_BITS          3
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_SPEED_SELECTION_SHIFT         6

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: Pair_Selection [05:04] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x30,4,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_Pair_Selection(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x30,4)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_MASK           0x0030
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_ALIGN          0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_BITS           2
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_PAIR_SELECTION_SHIFT          4

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: Master_mode [03:03] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_Master_mode(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x8,3,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_Master_mode(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x8,3)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_MASK              0x0008
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_ALIGN             0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_BITS              1
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_MASTER_MODE_SHIFT             3

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: Unidirection_Enable [02:02] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x4,2,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_CTRL_Unidirection_Enable(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_CTRL,0x4,2)
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_MASK      0x0004
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_ALIGN     0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_BITS      1
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_UNIDIRECTION_ENABLE_SHIFT     2

/* BRPHY4_BR_CL22_IEEE :: MII_CTRL :: reserved0 [01:00] */
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESERVED0_MASK                0x0003
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESERVED0_ALIGN               0
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESERVED0_BITS                2
#define BRPHY4_BR_CL22_IEEE_MII_CTRL_RESERVED0_SHIFT               0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: MII_STAT
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: MII_STAT :: reserved0 [15:15] */
#define BRPHY4_BR_CL22_IEEE_MII_STAT_RESERVED0_MASK                0x8000
#define BRPHY4_BR_CL22_IEEE_MII_STAT_RESERVED0_ALIGN               0
#define BRPHY4_BR_CL22_IEEE_MII_STAT_RESERVED0_BITS                1
#define BRPHY4_BR_CL22_IEEE_MII_STAT_RESERVED0_SHIFT               15

/* BRPHY4_BR_CL22_IEEE :: MII_STAT :: Capability [14:09] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_STAT_Capability(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x7e00,9,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_STAT_Capability(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x7e00,9)
#define BRPHY4_BR_CL22_IEEE_MII_STAT_CAPABILITY_MASK               0x7e00
#define BRPHY4_BR_CL22_IEEE_MII_STAT_CAPABILITY_ALIGN              0
#define BRPHY4_BR_CL22_IEEE_MII_STAT_CAPABILITY_BITS               6
#define BRPHY4_BR_CL22_IEEE_MII_STAT_CAPABILITY_SHIFT              9

/* BRPHY4_BR_CL22_IEEE :: MII_STAT :: EXTENDED_STAT [08:06] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x1c0,6,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x1c0,6)
#define BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_MASK            0x01c0
#define BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_ALIGN           0
#define BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_BITS            3
#define BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_STAT_SHIFT           6

/* BRPHY4_BR_CL22_IEEE :: MII_STAT :: LDS_complete [05:05] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_STAT_LDS_complete(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x20,5,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_STAT_LDS_complete(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x20,5)
#define BRPHY4_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_MASK             0x0020
#define BRPHY4_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_ALIGN            0
#define BRPHY4_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_BITS             1
#define BRPHY4_BR_CL22_IEEE_MII_STAT_LDS_COMPLETE_SHIFT            5

/* BRPHY4_BR_CL22_IEEE :: MII_STAT :: reserved1 [04:03] */
#define BRPHY4_BR_CL22_IEEE_MII_STAT_RESERVED1_MASK                0x0018
#define BRPHY4_BR_CL22_IEEE_MII_STAT_RESERVED1_ALIGN               0
#define BRPHY4_BR_CL22_IEEE_MII_STAT_RESERVED1_BITS                2
#define BRPHY4_BR_CL22_IEEE_MII_STAT_RESERVED1_SHIFT               3

/* BRPHY4_BR_CL22_IEEE :: MII_STAT :: LNK_STAT [02:02] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x4,2,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_STAT_LNK_STAT(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x4,2)
#define BRPHY4_BR_CL22_IEEE_MII_STAT_LNK_STAT_MASK                 0x0004
#define BRPHY4_BR_CL22_IEEE_MII_STAT_LNK_STAT_ALIGN                0
#define BRPHY4_BR_CL22_IEEE_MII_STAT_LNK_STAT_BITS                 1
#define BRPHY4_BR_CL22_IEEE_MII_STAT_LNK_STAT_SHIFT                2

/* BRPHY4_BR_CL22_IEEE :: MII_STAT :: JABBER_DETECT [01:01] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x2,1,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_STAT_JABBER_DETECT(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x2,1)
#define BRPHY4_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_MASK            0x0002
#define BRPHY4_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_ALIGN           0
#define BRPHY4_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_BITS            1
#define BRPHY4_BR_CL22_IEEE_MII_STAT_JABBER_DETECT_SHIFT           1

/* BRPHY4_BR_CL22_IEEE :: MII_STAT :: EXTENDED_CAPABILITY [00:00] */
#define Wr_BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x1,0,x)
#define Rd_BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_MII_STAT,0x1,0)
#define BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_MASK      0x0001
#define BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_ALIGN     0
#define BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_BITS      1
#define BRPHY4_BR_CL22_IEEE_MII_STAT_EXTENDED_CAPABILITY_SHIFT     0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: PHY_ID_MSB
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: PHY_ID_MSB :: OUI_MSB [15:00] */
#define Wr_BRPHY4_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) WriteReg16(BRPHY4_BR_CL22_IEEE_PHY_ID_MSB,x)
#define Rd_BRPHY4_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB(x) ReadReg16(BRPHY4_BR_CL22_IEEE_PHY_ID_MSB)
#define BRPHY4_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_MASK                0xffff
#define BRPHY4_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_ALIGN               0
#define BRPHY4_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_BITS                16
#define BRPHY4_BR_CL22_IEEE_PHY_ID_MSB_OUI_MSB_SHIFT               0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: PHY_ID_LSB
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: PHY_ID_LSB :: OUI_LSB [15:10] */
#define Wr_BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10,x)
#define Rd_BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_PHY_ID_LSB,0xfc00,10)
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_MASK                0xfc00
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_ALIGN               0
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_BITS                6
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_OUI_LSB_SHIFT               10

/* BRPHY4_BR_CL22_IEEE :: PHY_ID_LSB :: MODEL [09:04] */
#define Wr_BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4,x)
#define Rd_BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_MODEL(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_PHY_ID_LSB,0x3f0,4)
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_MODEL_MASK                  0x03f0
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_MODEL_ALIGN                 0
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_MODEL_BITS                  6
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_MODEL_SHIFT                 4

/* BRPHY4_BR_CL22_IEEE :: PHY_ID_LSB :: REVISION [03:00] */
#define Wr_BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_PHY_ID_LSB,0xf,0,x)
#define Rd_BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_REVISION(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_PHY_ID_LSB,0xf,0)
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_REVISION_MASK               0x000f
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_REVISION_ALIGN              0
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_REVISION_BITS               4
#define BRPHY4_BR_CL22_IEEE_PHY_ID_LSB_REVISION_SHIFT              0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8000,15)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4000,14)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved0 [13:06] */
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_MASK      0x3fc0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_ALIGN     0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_BITS      8
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED0_SHIFT     6

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x20,5)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_MASK   0x0020
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_ALIGN  0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_BITS   1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_PAIR_100MBPS_SHIFT  5

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_four_Pairs_100Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x10,4)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_100Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x8,3)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_two_Pairs_10Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x4,2)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP,0x2,1)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Ability_BP :: reserved1 [00:00] */
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_MASK      0x0001
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_ALIGN     0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_BITS      1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_ABILITY_BP_RESERVED1_SHIFT     0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: LDS_Adv_Control
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Control :: Test_Mode [15:13] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Control_Test_Mode(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL,0xe000,13)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_MASK         0xe000
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_ALIGN        0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_BITS         3
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_TEST_MODE_SHIFT        13

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Control :: reserved0 [12:10] */
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_MASK         0x1c00
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_ALIGN        0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_BITS         3
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_RESERVED0_SHIFT        10

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Control :: Port_Type [09:09] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Control_Port_Type(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL,0x200,9)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_MASK         0x0200
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_ALIGN        0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_BITS         1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_PORT_TYPE_SHIFT        9

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Control :: Abilities_Field_Update [08:08] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Control_Abilities_Field_Update(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL,0x100,8)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_MASK 0x0100
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_ABILITIES_FIELD_UPDATE_SHIFT 8

/* BRPHY4_BR_CL22_IEEE :: LDS_Adv_Control :: Local_Field_Number [07:00] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Adv_Control_Local_Field_Number(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL,0xff,0)
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_MASK 0x00ff
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_BITS 8
#define BRPHY4_BR_CL22_IEEE_LDS_ADV_CONTROL_LOCAL_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: LDS_Ability
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: LDS_Ability :: LDS_Ability [15:00] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) WriteReg16(BRPHY4_BR_CL22_IEEE_LDS_ABILITY,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_Ability_LDS_Ability(x) ReadReg16(BRPHY4_BR_CL22_IEEE_LDS_ABILITY)
#define BRPHY4_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_MASK           0xffff
#define BRPHY4_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_ALIGN          0
#define BRPHY4_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_BITS           16
#define BRPHY4_BR_CL22_IEEE_LDS_ABILITY_LDS_ABILITY_SHIFT          0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Asymmetric_PAUSE_operation [15:15] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Asymmetric_PAUSE_operation(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8000,15)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_MASK 0x8000
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ASYMMETRIC_PAUSE_OPERATION_SHIFT 15

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP :: PAUSE_operation [14:14] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_PAUSE_operation(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4000,14)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_MASK 0x4000
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAUSE_OPERATION_SHIFT 14

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved0 [13:06] */
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_MASK       0x3fc0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_ALIGN      0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_BITS       8
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED0_SHIFT      6

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Pair_100Mbps [05:05] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Pair_100Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x20,5)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_MASK    0x0020
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_ALIGN   0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_BITS    1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_PAIR_100MBPS_SHIFT   5

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Four_Pairs_100Mbps [04:04] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Four_Pairs_100Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x10,4)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_MASK 0x0010
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_FOUR_PAIRS_100MBPS_SHIFT 4

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_100Mbps [03:03] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_100Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x8,3)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_MASK 0x0008
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_100MBPS_SHIFT 3

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP :: Two_Pairs_10Mbps [02:02] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_Two_Pairs_10Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x4,2)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_MASK 0x0004
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_TWO_PAIRS_10MBPS_SHIFT 2

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP :: One_Pair_10Mbps [01:01] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_BP_One_Pair_10Mbps(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP,0x2,1)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_MASK 0x0002
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_ONE_PAIR_10MBPS_SHIFT 1

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_BP :: reserved1 [00:00] */
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_MASK       0x0001
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_ALIGN      0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_BITS       1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_BP_RESERVED1_SHIFT      0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: LDS_LP_MSG_NxtP
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: LDS_LP_MSG_NxtP :: Link_Partner_Nxt_Pg_Msg [15:00] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) WriteReg16(BRPHY4_BR_CL22_IEEE_LDS_LP_MSG_NXTP,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_MSG_NxtP_Link_Partner_Nxt_Pg_Msg(x) ReadReg16(BRPHY4_BR_CL22_IEEE_LDS_LP_MSG_NXTP)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_MASK 0xffff
#define BRPHY4_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_BITS 16
#define BRPHY4_BR_CL22_IEEE_LDS_LP_MSG_NXTP_LINK_PARTNER_NXT_PG_MSG_SHIFT 0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_NxtP
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: NextPage_Read_Flag [15:15] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_NxtP_NextPage_Read_Flag(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x8000,15)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_MASK 0x8000
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_BITS 1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_NEXTPAGE_READ_FLAG_SHIFT 15

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: reserved0 [14:09] */
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_MASK     0x7e00
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_ALIGN    0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_BITS     6
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_RESERVED0_SHIFT    9

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_ACQ [08:08] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_ACQ(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0x100,8)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_MASK    0x0100
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_ALIGN   0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_BITS    1
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_ACQ_SHIFT   8

/* BRPHY4_BR_CL22_IEEE :: LDS_LP_Ability_NxtP :: Remote_Field_Number [07:00] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LP_Ability_NxtP_Remote_Field_Number(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP,0xff,0)
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_MASK 0x00ff
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_BITS 8
#define BRPHY4_BR_CL22_IEEE_LDS_LP_ABILITY_NXTP_REMOTE_FIELD_NUMBER_SHIFT 0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: LDS_LDS_EXP
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: LDS_LDS_EXP :: Downgrade_Ability [15:15] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_Downgrade_Ability(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP,0x8000,15)
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_MASK     0x8000
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_ALIGN    0
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_BITS     1
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_DOWNGRADE_ABILITY_SHIFT    15

/* BRPHY4_BR_CL22_IEEE :: LDS_LDS_EXP :: Master_Slave [14:14] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_Master_Slave(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP,0x4000,14)
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_MASK          0x4000
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_ALIGN         0
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_BITS          1
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_MASTER_SLAVE_SHIFT         14

/* BRPHY4_BR_CL22_IEEE :: LDS_LDS_EXP :: Pair_Number [13:12] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_Pair_Number(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP,0x3000,12)
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_MASK           0x3000
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_ALIGN          0
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_BITS           2
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_PAIR_NUMBER_SHIFT          12

/* BRPHY4_BR_CL22_IEEE :: LDS_LDS_EXP :: Estimated_Wire_Length [11:00] */
#define Wr_BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_Estimated_Wire_Length(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP,0xfff,0)
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_MASK 0x0fff
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_BITS 12
#define BRPHY4_BR_CL22_IEEE_LDS_LDS_EXP_ESTIMATED_WIRE_LENGTH_SHIFT 0


/****************************************************************************
 * BRPHY4_BR_CL22_IEEE :: LRE_EXTENDED_STAT
 ***************************************************************************/
/* BRPHY4_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: reserved0 [15:10] */
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_MASK       0xfc00
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_ALIGN      0
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_BITS       6
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_RESERVED0_SHIFT      10

/* BRPHY4_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: LOCAL_RECEIVE_STATUS [09:09] */
#define Wr_BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x200,9)
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_MASK 0x0200
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_LOCAL_RECEIVE_STATUS_SHIFT 9

/* BRPHY4_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: REMOTE_RECEIVE_STATUS [08:08] */
#define Wr_BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT,0x100,8)
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_MASK 0x0100
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_BITS 1
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_REMOTE_RECEIVE_STATUS_SHIFT 8

/* BRPHY4_BR_CL22_IEEE :: LRE_EXTENDED_STAT :: IDLE_ERROR_CNTR [07:00] */
#define Wr_BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) WriteRegBits16(BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0,x)
#define Rd_BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR(x) ReadRegBits16(BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT,0xff,0)
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_MASK 0x00ff
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_ALIGN 0
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_BITS 8
#define BRPHY4_BR_CL22_IEEE_LRE_EXTENDED_STAT_IDLE_ERROR_CNTR_SHIFT 0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_CL22_B0
 ***************************************************************************/
/****************************************************************************
 * SGMII0_CL22_B0 :: MIICntl
 ***************************************************************************/
/* SGMII0_CL22_B0 :: MIICntl :: rst_hw [15:15] */
#define Wr_SGMII0_CL22_B0_MIICntl_rst_hw(x) WriteRegBits16(SGMII0_CL22_B0_MIICNTL,0x8000,15,x)
#define Rd_SGMII0_CL22_B0_MIICntl_rst_hw(x) ReadRegBits16(SGMII0_CL22_B0_MIICNTL,0x8000,15)
#define SGMII0_CL22_B0_MIICNTL_RST_HW_MASK                         0x8000
#define SGMII0_CL22_B0_MIICNTL_RST_HW_ALIGN                        0
#define SGMII0_CL22_B0_MIICNTL_RST_HW_BITS                         1
#define SGMII0_CL22_B0_MIICNTL_RST_HW_SHIFT                        15

/* SGMII0_CL22_B0 :: MIICntl :: gloopback [14:14] */
#define Wr_SGMII0_CL22_B0_MIICntl_gloopback(x) WriteRegBits16(SGMII0_CL22_B0_MIICNTL,0x4000,14,x)
#define Rd_SGMII0_CL22_B0_MIICntl_gloopback(x) ReadRegBits16(SGMII0_CL22_B0_MIICNTL,0x4000,14)
#define SGMII0_CL22_B0_MIICNTL_GLOOPBACK_MASK                      0x4000
#define SGMII0_CL22_B0_MIICNTL_GLOOPBACK_ALIGN                     0
#define SGMII0_CL22_B0_MIICNTL_GLOOPBACK_BITS                      1
#define SGMII0_CL22_B0_MIICNTL_GLOOPBACK_SHIFT                     14

/* SGMII0_CL22_B0 :: MIICntl :: manual_speed0 [13:13] */
#define Wr_SGMII0_CL22_B0_MIICntl_manual_speed0(x) WriteRegBits16(SGMII0_CL22_B0_MIICNTL,0x2000,13,x)
#define Rd_SGMII0_CL22_B0_MIICntl_manual_speed0(x) ReadRegBits16(SGMII0_CL22_B0_MIICNTL,0x2000,13)
#define SGMII0_CL22_B0_MIICNTL_MANUAL_SPEED0_MASK                  0x2000
#define SGMII0_CL22_B0_MIICNTL_MANUAL_SPEED0_ALIGN                 0
#define SGMII0_CL22_B0_MIICNTL_MANUAL_SPEED0_BITS                  1
#define SGMII0_CL22_B0_MIICNTL_MANUAL_SPEED0_SHIFT                 13

/* SGMII0_CL22_B0 :: MIICntl :: autoneg_enable [12:12] */
#define Wr_SGMII0_CL22_B0_MIICntl_autoneg_enable(x) WriteRegBits16(SGMII0_CL22_B0_MIICNTL,0x1000,12,x)
#define Rd_SGMII0_CL22_B0_MIICntl_autoneg_enable(x) ReadRegBits16(SGMII0_CL22_B0_MIICNTL,0x1000,12)
#define SGMII0_CL22_B0_MIICNTL_AUTONEG_ENABLE_MASK                 0x1000
#define SGMII0_CL22_B0_MIICNTL_AUTONEG_ENABLE_ALIGN                0
#define SGMII0_CL22_B0_MIICNTL_AUTONEG_ENABLE_BITS                 1
#define SGMII0_CL22_B0_MIICNTL_AUTONEG_ENABLE_SHIFT                12

/* SGMII0_CL22_B0 :: MIICntl :: pwrdwn_sw [11:11] */
#define Wr_SGMII0_CL22_B0_MIICntl_pwrdwn_sw(x) WriteRegBits16(SGMII0_CL22_B0_MIICNTL,0x800,11,x)
#define Rd_SGMII0_CL22_B0_MIICntl_pwrdwn_sw(x) ReadRegBits16(SGMII0_CL22_B0_MIICNTL,0x800,11)
#define SGMII0_CL22_B0_MIICNTL_PWRDWN_SW_MASK                      0x0800
#define SGMII0_CL22_B0_MIICNTL_PWRDWN_SW_ALIGN                     0
#define SGMII0_CL22_B0_MIICNTL_PWRDWN_SW_BITS                      1
#define SGMII0_CL22_B0_MIICNTL_PWRDWN_SW_SHIFT                     11

/* SGMII0_CL22_B0 :: MIICntl :: reserved0 [10:10] */
#define SGMII0_CL22_B0_MIICNTL_RESERVED0_MASK                      0x0400
#define SGMII0_CL22_B0_MIICNTL_RESERVED0_ALIGN                     0
#define SGMII0_CL22_B0_MIICNTL_RESERVED0_BITS                      1
#define SGMII0_CL22_B0_MIICNTL_RESERVED0_SHIFT                     10

/* SGMII0_CL22_B0 :: MIICntl :: restart_autoneg [09:09] */
#define Wr_SGMII0_CL22_B0_MIICntl_restart_autoneg(x) WriteRegBits16(SGMII0_CL22_B0_MIICNTL,0x200,9,x)
#define Rd_SGMII0_CL22_B0_MIICntl_restart_autoneg(x) ReadRegBits16(SGMII0_CL22_B0_MIICNTL,0x200,9)
#define SGMII0_CL22_B0_MIICNTL_RESTART_AUTONEG_MASK                0x0200
#define SGMII0_CL22_B0_MIICNTL_RESTART_AUTONEG_ALIGN               0
#define SGMII0_CL22_B0_MIICNTL_RESTART_AUTONEG_BITS                1
#define SGMII0_CL22_B0_MIICNTL_RESTART_AUTONEG_SHIFT               9

/* SGMII0_CL22_B0 :: MIICntl :: full_duplex [08:08] */
#define Wr_SGMII0_CL22_B0_MIICntl_full_duplex(x) WriteRegBits16(SGMII0_CL22_B0_MIICNTL,0x100,8,x)
#define Rd_SGMII0_CL22_B0_MIICntl_full_duplex(x) ReadRegBits16(SGMII0_CL22_B0_MIICNTL,0x100,8)
#define SGMII0_CL22_B0_MIICNTL_FULL_DUPLEX_MASK                    0x0100
#define SGMII0_CL22_B0_MIICNTL_FULL_DUPLEX_ALIGN                   0
#define SGMII0_CL22_B0_MIICNTL_FULL_DUPLEX_BITS                    1
#define SGMII0_CL22_B0_MIICNTL_FULL_DUPLEX_SHIFT                   8

/* SGMII0_CL22_B0 :: MIICntl :: collision_test_en [07:07] */
#define Wr_SGMII0_CL22_B0_MIICntl_collision_test_en(x) WriteRegBits16(SGMII0_CL22_B0_MIICNTL,0x80,7,x)
#define Rd_SGMII0_CL22_B0_MIICntl_collision_test_en(x) ReadRegBits16(SGMII0_CL22_B0_MIICNTL,0x80,7)
#define SGMII0_CL22_B0_MIICNTL_COLLISION_TEST_EN_MASK              0x0080
#define SGMII0_CL22_B0_MIICNTL_COLLISION_TEST_EN_ALIGN             0
#define SGMII0_CL22_B0_MIICNTL_COLLISION_TEST_EN_BITS              1
#define SGMII0_CL22_B0_MIICNTL_COLLISION_TEST_EN_SHIFT             7

/* SGMII0_CL22_B0 :: MIICntl :: manual_speed1 [06:06] */
#define Wr_SGMII0_CL22_B0_MIICntl_manual_speed1(x) WriteRegBits16(SGMII0_CL22_B0_MIICNTL,0x40,6,x)
#define Rd_SGMII0_CL22_B0_MIICntl_manual_speed1(x) ReadRegBits16(SGMII0_CL22_B0_MIICNTL,0x40,6)
#define SGMII0_CL22_B0_MIICNTL_MANUAL_SPEED1_MASK                  0x0040
#define SGMII0_CL22_B0_MIICNTL_MANUAL_SPEED1_ALIGN                 0
#define SGMII0_CL22_B0_MIICNTL_MANUAL_SPEED1_BITS                  1
#define SGMII0_CL22_B0_MIICNTL_MANUAL_SPEED1_SHIFT                 6

/* SGMII0_CL22_B0 :: MIICntl :: reserved1 [05:00] */
#define SGMII0_CL22_B0_MIICNTL_RESERVED1_MASK                      0x003f
#define SGMII0_CL22_B0_MIICNTL_RESERVED1_ALIGN                     0
#define SGMII0_CL22_B0_MIICNTL_RESERVED1_BITS                      6
#define SGMII0_CL22_B0_MIICNTL_RESERVED1_SHIFT                     0


/****************************************************************************
 * SGMII0_CL22_B0 :: MIIStat
 ***************************************************************************/
/* SGMII0_CL22_B0 :: MIIStat :: s100BASE_T4_capable [15:15] */
#define Wr_SGMII0_CL22_B0_MIIStat_s100BASE_T4_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x8000,15,x)
#define Rd_SGMII0_CL22_B0_MIIStat_s100BASE_T4_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x8000,15)
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_MASK            0x8000
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN           0
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_BITS            1
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT           15

/* SGMII0_CL22_B0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
#define Wr_SGMII0_CL22_B0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x4000,14,x)
#define Rd_SGMII0_CL22_B0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x4000,14)
#define SGMII0_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII0_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII0_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14

/* SGMII0_CL22_B0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
#define Wr_SGMII0_CL22_B0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x2000,13,x)
#define Rd_SGMII0_CL22_B0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x2000,13)
#define SGMII0_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII0_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII0_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13

/* SGMII0_CL22_B0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
#define Wr_SGMII0_CL22_B0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x1000,12,x)
#define Rd_SGMII0_CL22_B0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x1000,12)
#define SGMII0_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK  0x1000
#define SGMII0_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS  1
#define SGMII0_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12

/* SGMII0_CL22_B0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
#define Wr_SGMII0_CL22_B0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x800,11,x)
#define Rd_SGMII0_CL22_B0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x800,11)
#define SGMII0_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK  0x0800
#define SGMII0_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS  1
#define SGMII0_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11

/* SGMII0_CL22_B0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
#define Wr_SGMII0_CL22_B0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x400,10,x)
#define Rd_SGMII0_CL22_B0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x400,10)
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10

/* SGMII0_CL22_B0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
#define Wr_SGMII0_CL22_B0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x200,9,x)
#define Rd_SGMII0_CL22_B0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x200,9)
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII0_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9

/* SGMII0_CL22_B0 :: MIIStat :: extended_status [08:08] */
#define Wr_SGMII0_CL22_B0_MIIStat_extended_status(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x100,8,x)
#define Rd_SGMII0_CL22_B0_MIIStat_extended_status(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x100,8)
#define SGMII0_CL22_B0_MIISTAT_EXTENDED_STATUS_MASK                0x0100
#define SGMII0_CL22_B0_MIISTAT_EXTENDED_STATUS_ALIGN               0
#define SGMII0_CL22_B0_MIISTAT_EXTENDED_STATUS_BITS                1
#define SGMII0_CL22_B0_MIISTAT_EXTENDED_STATUS_SHIFT               8

/* SGMII0_CL22_B0 :: MIIStat :: reserved0 [07:07] */
#define SGMII0_CL22_B0_MIISTAT_RESERVED0_MASK                      0x0080
#define SGMII0_CL22_B0_MIISTAT_RESERVED0_ALIGN                     0
#define SGMII0_CL22_B0_MIISTAT_RESERVED0_BITS                      1
#define SGMII0_CL22_B0_MIISTAT_RESERVED0_SHIFT                     7

/* SGMII0_CL22_B0 :: MIIStat :: mf_preamble_supression [06:06] */
#define Wr_SGMII0_CL22_B0_MIIStat_mf_preamble_supression(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x40,6,x)
#define Rd_SGMII0_CL22_B0_MIIStat_mf_preamble_supression(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x40,6)
#define SGMII0_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK         0x0040
#define SGMII0_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN        0
#define SGMII0_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS         1
#define SGMII0_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT        6

/* SGMII0_CL22_B0 :: MIIStat :: autoneg_complete [05:05] */
#define Wr_SGMII0_CL22_B0_MIIStat_autoneg_complete(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x20,5,x)
#define Rd_SGMII0_CL22_B0_MIIStat_autoneg_complete(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x20,5)
#define SGMII0_CL22_B0_MIISTAT_AUTONEG_COMPLETE_MASK               0x0020
#define SGMII0_CL22_B0_MIISTAT_AUTONEG_COMPLETE_ALIGN              0
#define SGMII0_CL22_B0_MIISTAT_AUTONEG_COMPLETE_BITS               1
#define SGMII0_CL22_B0_MIISTAT_AUTONEG_COMPLETE_SHIFT              5

/* SGMII0_CL22_B0 :: MIIStat :: remote_fault [04:04] */
#define Wr_SGMII0_CL22_B0_MIIStat_remote_fault(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x10,4,x)
#define Rd_SGMII0_CL22_B0_MIIStat_remote_fault(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x10,4)
#define SGMII0_CL22_B0_MIISTAT_REMOTE_FAULT_MASK                   0x0010
#define SGMII0_CL22_B0_MIISTAT_REMOTE_FAULT_ALIGN                  0
#define SGMII0_CL22_B0_MIISTAT_REMOTE_FAULT_BITS                   1
#define SGMII0_CL22_B0_MIISTAT_REMOTE_FAULT_SHIFT                  4

/* SGMII0_CL22_B0 :: MIIStat :: autoneg_ability [03:03] */
#define Wr_SGMII0_CL22_B0_MIIStat_autoneg_ability(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x8,3,x)
#define Rd_SGMII0_CL22_B0_MIIStat_autoneg_ability(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x8,3)
#define SGMII0_CL22_B0_MIISTAT_AUTONEG_ABILITY_MASK                0x0008
#define SGMII0_CL22_B0_MIISTAT_AUTONEG_ABILITY_ALIGN               0
#define SGMII0_CL22_B0_MIISTAT_AUTONEG_ABILITY_BITS                1
#define SGMII0_CL22_B0_MIISTAT_AUTONEG_ABILITY_SHIFT               3

/* SGMII0_CL22_B0 :: MIIStat :: link_status [02:02] */
#define Wr_SGMII0_CL22_B0_MIIStat_link_status(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x4,2,x)
#define Rd_SGMII0_CL22_B0_MIIStat_link_status(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x4,2)
#define SGMII0_CL22_B0_MIISTAT_LINK_STATUS_MASK                    0x0004
#define SGMII0_CL22_B0_MIISTAT_LINK_STATUS_ALIGN                   0
#define SGMII0_CL22_B0_MIISTAT_LINK_STATUS_BITS                    1
#define SGMII0_CL22_B0_MIISTAT_LINK_STATUS_SHIFT                   2

/* SGMII0_CL22_B0 :: MIIStat :: jabber_detect [01:01] */
#define Wr_SGMII0_CL22_B0_MIIStat_jabber_detect(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x2,1,x)
#define Rd_SGMII0_CL22_B0_MIIStat_jabber_detect(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x2,1)
#define SGMII0_CL22_B0_MIISTAT_JABBER_DETECT_MASK                  0x0002
#define SGMII0_CL22_B0_MIISTAT_JABBER_DETECT_ALIGN                 0
#define SGMII0_CL22_B0_MIISTAT_JABBER_DETECT_BITS                  1
#define SGMII0_CL22_B0_MIISTAT_JABBER_DETECT_SHIFT                 1

/* SGMII0_CL22_B0 :: MIIStat :: extended_capability [00:00] */
#define Wr_SGMII0_CL22_B0_MIIStat_extended_capability(x) WriteRegBits16(SGMII0_CL22_B0_MIISTAT,0x1,0,x)
#define Rd_SGMII0_CL22_B0_MIIStat_extended_capability(x) ReadRegBits16(SGMII0_CL22_B0_MIISTAT,0x1,0)
#define SGMII0_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_MASK            0x0001
#define SGMII0_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_ALIGN           0
#define SGMII0_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_BITS            1
#define SGMII0_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_SHIFT           0


/****************************************************************************
 * SGMII0_CL22_B0 :: Id1
 ***************************************************************************/
/* SGMII0_CL22_B0 :: Id1 :: regid [15:00] */
#define Wr_SGMII0_CL22_B0_Id1_regid(x) WriteReg16(SGMII0_CL22_B0_ID1,x)
#define Rd_SGMII0_CL22_B0_Id1_regid(x) ReadReg16(SGMII0_CL22_B0_ID1)
#define SGMII0_CL22_B0_ID1_REGID_MASK                              0xffff
#define SGMII0_CL22_B0_ID1_REGID_ALIGN                             0
#define SGMII0_CL22_B0_ID1_REGID_BITS                              16
#define SGMII0_CL22_B0_ID1_REGID_SHIFT                             0


/****************************************************************************
 * SGMII0_CL22_B0 :: Id2
 ***************************************************************************/
/* SGMII0_CL22_B0 :: Id2 :: regid [15:00] */
#define Wr_SGMII0_CL22_B0_Id2_regid(x) WriteReg16(SGMII0_CL22_B0_ID2,x)
#define Rd_SGMII0_CL22_B0_Id2_regid(x) ReadReg16(SGMII0_CL22_B0_ID2)
#define SGMII0_CL22_B0_ID2_REGID_MASK                              0xffff
#define SGMII0_CL22_B0_ID2_REGID_ALIGN                             0
#define SGMII0_CL22_B0_ID2_REGID_BITS                              16
#define SGMII0_CL22_B0_ID2_REGID_SHIFT                             0


/****************************************************************************
 * SGMII0_CL22_B0 :: AutoNegAdv
 ***************************************************************************/
/* SGMII0_CL22_B0 :: AutoNegAdv :: next_page [15:15] */
#define Wr_SGMII0_CL22_B0_AutoNegAdv_next_page(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x8000,15,x)
#define Rd_SGMII0_CL22_B0_AutoNegAdv_next_page(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x8000,15)
#define SGMII0_CL22_B0_AUTONEGADV_NEXT_PAGE_MASK                   0x8000
#define SGMII0_CL22_B0_AUTONEGADV_NEXT_PAGE_ALIGN                  0
#define SGMII0_CL22_B0_AUTONEGADV_NEXT_PAGE_BITS                   1
#define SGMII0_CL22_B0_AUTONEGADV_NEXT_PAGE_SHIFT                  15

/* SGMII0_CL22_B0 :: AutoNegAdv :: reserved0 [14:14] */
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED0_MASK                   0x4000
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED0_ALIGN                  0
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED0_BITS                   1
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED0_SHIFT                  14

/* SGMII0_CL22_B0 :: AutoNegAdv :: remote_fault [13:12] */
#define Wr_SGMII0_CL22_B0_AutoNegAdv_remote_fault(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x3000,12,x)
#define Rd_SGMII0_CL22_B0_AutoNegAdv_remote_fault(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x3000,12)
#define SGMII0_CL22_B0_AUTONEGADV_REMOTE_FAULT_MASK                0x3000
#define SGMII0_CL22_B0_AUTONEGADV_REMOTE_FAULT_ALIGN               0
#define SGMII0_CL22_B0_AUTONEGADV_REMOTE_FAULT_BITS                2
#define SGMII0_CL22_B0_AUTONEGADV_REMOTE_FAULT_SHIFT               12

/* SGMII0_CL22_B0 :: AutoNegAdv :: reserved1 [11:09] */
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED1_MASK                   0x0e00
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED1_ALIGN                  0
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED1_BITS                   3
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED1_SHIFT                  9

/* SGMII0_CL22_B0 :: AutoNegAdv :: pause [08:07] */
#define Wr_SGMII0_CL22_B0_AutoNegAdv_pause(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x180,7,x)
#define Rd_SGMII0_CL22_B0_AutoNegAdv_pause(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x180,7)
#define SGMII0_CL22_B0_AUTONEGADV_PAUSE_MASK                       0x0180
#define SGMII0_CL22_B0_AUTONEGADV_PAUSE_ALIGN                      0
#define SGMII0_CL22_B0_AUTONEGADV_PAUSE_BITS                       2
#define SGMII0_CL22_B0_AUTONEGADV_PAUSE_SHIFT                      7

/* SGMII0_CL22_B0 :: AutoNegAdv :: half_duplex [06:06] */
#define Wr_SGMII0_CL22_B0_AutoNegAdv_half_duplex(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x40,6,x)
#define Rd_SGMII0_CL22_B0_AutoNegAdv_half_duplex(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x40,6)
#define SGMII0_CL22_B0_AUTONEGADV_HALF_DUPLEX_MASK                 0x0040
#define SGMII0_CL22_B0_AUTONEGADV_HALF_DUPLEX_ALIGN                0
#define SGMII0_CL22_B0_AUTONEGADV_HALF_DUPLEX_BITS                 1
#define SGMII0_CL22_B0_AUTONEGADV_HALF_DUPLEX_SHIFT                6

/* SGMII0_CL22_B0 :: AutoNegAdv :: full_duplex [05:05] */
#define Wr_SGMII0_CL22_B0_AutoNegAdv_full_duplex(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x20,5,x)
#define Rd_SGMII0_CL22_B0_AutoNegAdv_full_duplex(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGADV,0x20,5)
#define SGMII0_CL22_B0_AUTONEGADV_FULL_DUPLEX_MASK                 0x0020
#define SGMII0_CL22_B0_AUTONEGADV_FULL_DUPLEX_ALIGN                0
#define SGMII0_CL22_B0_AUTONEGADV_FULL_DUPLEX_BITS                 1
#define SGMII0_CL22_B0_AUTONEGADV_FULL_DUPLEX_SHIFT                5

/* SGMII0_CL22_B0 :: AutoNegAdv :: reserved2 [04:00] */
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED2_MASK                   0x001f
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED2_ALIGN                  0
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED2_BITS                   5
#define SGMII0_CL22_B0_AUTONEGADV_RESERVED2_SHIFT                  0


/****************************************************************************
 * SGMII0_CL22_B0 :: AutoNegLPAbil
 ***************************************************************************/
/* SGMII0_CL22_B0 :: AutoNegLPAbil :: next_page [15:15] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil_next_page(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x8000,15,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil_next_page(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x8000,15)
#define SGMII0_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_MASK                0x8000
#define SGMII0_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_ALIGN               0
#define SGMII0_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_BITS                1
#define SGMII0_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_SHIFT               15

/* SGMII0_CL22_B0 :: AutoNegLPAbil :: acknowledge [14:14] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil_acknowledge(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x4000,14,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil_acknowledge(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x4000,14)
#define SGMII0_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_MASK              0x4000
#define SGMII0_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN             0
#define SGMII0_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_BITS              1
#define SGMII0_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT             14

/* SGMII0_CL22_B0 :: AutoNegLPAbil :: remote_fault [13:12] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil_remote_fault(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x3000,12,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil_remote_fault(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x3000,12)
#define SGMII0_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_MASK             0x3000
#define SGMII0_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN            0
#define SGMII0_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_BITS             2
#define SGMII0_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT            12

/* SGMII0_CL22_B0 :: AutoNegLPAbil :: reserved0 [11:09] */
#define SGMII0_CL22_B0_AUTONEGLPABIL_RESERVED0_MASK                0x0e00
#define SGMII0_CL22_B0_AUTONEGLPABIL_RESERVED0_ALIGN               0
#define SGMII0_CL22_B0_AUTONEGLPABIL_RESERVED0_BITS                3
#define SGMII0_CL22_B0_AUTONEGLPABIL_RESERVED0_SHIFT               9

/* SGMII0_CL22_B0 :: AutoNegLPAbil :: pause [08:07] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil_pause(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x180,7,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil_pause(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x180,7)
#define SGMII0_CL22_B0_AUTONEGLPABIL_PAUSE_MASK                    0x0180
#define SGMII0_CL22_B0_AUTONEGLPABIL_PAUSE_ALIGN                   0
#define SGMII0_CL22_B0_AUTONEGLPABIL_PAUSE_BITS                    2
#define SGMII0_CL22_B0_AUTONEGLPABIL_PAUSE_SHIFT                   7

/* SGMII0_CL22_B0 :: AutoNegLPAbil :: half_duplex [06:06] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil_half_duplex(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x40,6,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil_half_duplex(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x40,6)
#define SGMII0_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_MASK              0x0040
#define SGMII0_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN             0
#define SGMII0_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_BITS              1
#define SGMII0_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT             6

/* SGMII0_CL22_B0 :: AutoNegLPAbil :: full_duplex [05:05] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil_full_duplex(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x20,5,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil_full_duplex(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x20,5)
#define SGMII0_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_MASK              0x0020
#define SGMII0_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN             0
#define SGMII0_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_BITS              1
#define SGMII0_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT             5

/* SGMII0_CL22_B0 :: AutoNegLPAbil :: reserved1 [04:01] */
#define SGMII0_CL22_B0_AUTONEGLPABIL_RESERVED1_MASK                0x001e
#define SGMII0_CL22_B0_AUTONEGLPABIL_RESERVED1_ALIGN               0
#define SGMII0_CL22_B0_AUTONEGLPABIL_RESERVED1_BITS                4
#define SGMII0_CL22_B0_AUTONEGLPABIL_RESERVED1_SHIFT               1

/* SGMII0_CL22_B0 :: AutoNegLPAbil :: sgmii_mode [00:00] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil_sgmii_mode(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x1,0,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil_sgmii_mode(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL,0x1,0)
#define SGMII0_CL22_B0_AUTONEGLPABIL_SGMII_MODE_MASK               0x0001
#define SGMII0_CL22_B0_AUTONEGLPABIL_SGMII_MODE_ALIGN              0
#define SGMII0_CL22_B0_AUTONEGLPABIL_SGMII_MODE_BITS               1
#define SGMII0_CL22_B0_AUTONEGLPABIL_SGMII_MODE_SHIFT              0


/****************************************************************************
 * SGMII0_CL22_B0 :: AutoNegExp
 ***************************************************************************/
/* SGMII0_CL22_B0 :: AutoNegExp :: reserved0 [15:03] */
#define SGMII0_CL22_B0_AUTONEGEXP_RESERVED0_MASK                   0xfff8
#define SGMII0_CL22_B0_AUTONEGEXP_RESERVED0_ALIGN                  0
#define SGMII0_CL22_B0_AUTONEGEXP_RESERVED0_BITS                   13
#define SGMII0_CL22_B0_AUTONEGEXP_RESERVED0_SHIFT                  3

/* SGMII0_CL22_B0 :: AutoNegExp :: next_page_ability [02:02] */
#define Wr_SGMII0_CL22_B0_AutoNegExp_next_page_ability(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGEXP,0x4,2,x)
#define Rd_SGMII0_CL22_B0_AutoNegExp_next_page_ability(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGEXP,0x4,2)
#define SGMII0_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK           0x0004
#define SGMII0_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN          0
#define SGMII0_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS           1
#define SGMII0_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT          2

/* SGMII0_CL22_B0 :: AutoNegExp :: page_received [01:01] */
#define Wr_SGMII0_CL22_B0_AutoNegExp_page_received(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGEXP,0x2,1,x)
#define Rd_SGMII0_CL22_B0_AutoNegExp_page_received(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGEXP,0x2,1)
#define SGMII0_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_MASK               0x0002
#define SGMII0_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_ALIGN              0
#define SGMII0_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_BITS               1
#define SGMII0_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_SHIFT              1

/* SGMII0_CL22_B0 :: AutoNegExp :: reserved1 [00:00] */
#define SGMII0_CL22_B0_AUTONEGEXP_RESERVED1_MASK                   0x0001
#define SGMII0_CL22_B0_AUTONEGEXP_RESERVED1_ALIGN                  0
#define SGMII0_CL22_B0_AUTONEGEXP_RESERVED1_BITS                   1
#define SGMII0_CL22_B0_AUTONEGEXP_RESERVED1_SHIFT                  0


/****************************************************************************
 * SGMII0_CL22_B0 :: AutoNegNP
 ***************************************************************************/
/* SGMII0_CL22_B0 :: AutoNegNP :: Next_Page [15:15] */
#define Wr_SGMII0_CL22_B0_AutoNegNP_Next_Page(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x8000,15,x)
#define Rd_SGMII0_CL22_B0_AutoNegNP_Next_Page(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x8000,15)
#define SGMII0_CL22_B0_AUTONEGNP_NEXT_PAGE_MASK                    0x8000
#define SGMII0_CL22_B0_AUTONEGNP_NEXT_PAGE_ALIGN                   0
#define SGMII0_CL22_B0_AUTONEGNP_NEXT_PAGE_BITS                    1
#define SGMII0_CL22_B0_AUTONEGNP_NEXT_PAGE_SHIFT                   15

/* SGMII0_CL22_B0 :: AutoNegNP :: Ack [14:14] */
#define Wr_SGMII0_CL22_B0_AutoNegNP_Ack(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x4000,14,x)
#define Rd_SGMII0_CL22_B0_AutoNegNP_Ack(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x4000,14)
#define SGMII0_CL22_B0_AUTONEGNP_ACK_MASK                          0x4000
#define SGMII0_CL22_B0_AUTONEGNP_ACK_ALIGN                         0
#define SGMII0_CL22_B0_AUTONEGNP_ACK_BITS                          1
#define SGMII0_CL22_B0_AUTONEGNP_ACK_SHIFT                         14

/* SGMII0_CL22_B0 :: AutoNegNP :: Message_Page [13:13] */
#define Wr_SGMII0_CL22_B0_AutoNegNP_Message_Page(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x2000,13,x)
#define Rd_SGMII0_CL22_B0_AutoNegNP_Message_Page(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x2000,13)
#define SGMII0_CL22_B0_AUTONEGNP_MESSAGE_PAGE_MASK                 0x2000
#define SGMII0_CL22_B0_AUTONEGNP_MESSAGE_PAGE_ALIGN                0
#define SGMII0_CL22_B0_AUTONEGNP_MESSAGE_PAGE_BITS                 1
#define SGMII0_CL22_B0_AUTONEGNP_MESSAGE_PAGE_SHIFT                13

/* SGMII0_CL22_B0 :: AutoNegNP :: Ack2 [12:12] */
#define Wr_SGMII0_CL22_B0_AutoNegNP_Ack2(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x1000,12,x)
#define Rd_SGMII0_CL22_B0_AutoNegNP_Ack2(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x1000,12)
#define SGMII0_CL22_B0_AUTONEGNP_ACK2_MASK                         0x1000
#define SGMII0_CL22_B0_AUTONEGNP_ACK2_ALIGN                        0
#define SGMII0_CL22_B0_AUTONEGNP_ACK2_BITS                         1
#define SGMII0_CL22_B0_AUTONEGNP_ACK2_SHIFT                        12

/* SGMII0_CL22_B0 :: AutoNegNP :: Toggle [11:11] */
#define Wr_SGMII0_CL22_B0_AutoNegNP_Toggle(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x800,11,x)
#define Rd_SGMII0_CL22_B0_AutoNegNP_Toggle(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x800,11)
#define SGMII0_CL22_B0_AUTONEGNP_TOGGLE_MASK                       0x0800
#define SGMII0_CL22_B0_AUTONEGNP_TOGGLE_ALIGN                      0
#define SGMII0_CL22_B0_AUTONEGNP_TOGGLE_BITS                       1
#define SGMII0_CL22_B0_AUTONEGNP_TOGGLE_SHIFT                      11

/* SGMII0_CL22_B0 :: AutoNegNP :: Message [10:00] */
#define Wr_SGMII0_CL22_B0_AutoNegNP_Message(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x7ff,0,x)
#define Rd_SGMII0_CL22_B0_AutoNegNP_Message(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGNP,0x7ff,0)
#define SGMII0_CL22_B0_AUTONEGNP_MESSAGE_MASK                      0x07ff
#define SGMII0_CL22_B0_AUTONEGNP_MESSAGE_ALIGN                     0
#define SGMII0_CL22_B0_AUTONEGNP_MESSAGE_BITS                      11
#define SGMII0_CL22_B0_AUTONEGNP_MESSAGE_SHIFT                     0


/****************************************************************************
 * SGMII0_CL22_B0 :: AutoNegLPAbil2
 ***************************************************************************/
/* SGMII0_CL22_B0 :: AutoNegLPAbil2 :: Next_Page [15:15] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil2_Next_Page(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x8000,15,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil2_Next_Page(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x8000,15)
#define SGMII0_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_MASK               0x8000
#define SGMII0_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN              0
#define SGMII0_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_BITS               1
#define SGMII0_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT              15

/* SGMII0_CL22_B0 :: AutoNegLPAbil2 :: Ack [14:14] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil2_Ack(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x4000,14,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil2_Ack(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x4000,14)
#define SGMII0_CL22_B0_AUTONEGLPABIL2_ACK_MASK                     0x4000
#define SGMII0_CL22_B0_AUTONEGLPABIL2_ACK_ALIGN                    0
#define SGMII0_CL22_B0_AUTONEGLPABIL2_ACK_BITS                     1
#define SGMII0_CL22_B0_AUTONEGLPABIL2_ACK_SHIFT                    14

/* SGMII0_CL22_B0 :: AutoNegLPAbil2 :: Message_Page [13:13] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil2_Message_Page(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x2000,13,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil2_Message_Page(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x2000,13)
#define SGMII0_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK            0x2000
#define SGMII0_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN           0
#define SGMII0_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS            1
#define SGMII0_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT           13

/* SGMII0_CL22_B0 :: AutoNegLPAbil2 :: Ack2 [12:12] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil2_Ack2(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x1000,12,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil2_Ack2(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x1000,12)
#define SGMII0_CL22_B0_AUTONEGLPABIL2_ACK2_MASK                    0x1000
#define SGMII0_CL22_B0_AUTONEGLPABIL2_ACK2_ALIGN                   0
#define SGMII0_CL22_B0_AUTONEGLPABIL2_ACK2_BITS                    1
#define SGMII0_CL22_B0_AUTONEGLPABIL2_ACK2_SHIFT                   12

/* SGMII0_CL22_B0 :: AutoNegLPAbil2 :: Toggle [11:11] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil2_Toggle(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x800,11,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil2_Toggle(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x800,11)
#define SGMII0_CL22_B0_AUTONEGLPABIL2_TOGGLE_MASK                  0x0800
#define SGMII0_CL22_B0_AUTONEGLPABIL2_TOGGLE_ALIGN                 0
#define SGMII0_CL22_B0_AUTONEGLPABIL2_TOGGLE_BITS                  1
#define SGMII0_CL22_B0_AUTONEGLPABIL2_TOGGLE_SHIFT                 11

/* SGMII0_CL22_B0 :: AutoNegLPAbil2 :: Message [10:00] */
#define Wr_SGMII0_CL22_B0_AutoNegLPAbil2_Message(x) WriteRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x7ff,0,x)
#define Rd_SGMII0_CL22_B0_AutoNegLPAbil2_Message(x) ReadRegBits16(SGMII0_CL22_B0_AUTONEGLPABIL2,0x7ff,0)
#define SGMII0_CL22_B0_AUTONEGLPABIL2_MESSAGE_MASK                 0x07ff
#define SGMII0_CL22_B0_AUTONEGLPABIL2_MESSAGE_ALIGN                0
#define SGMII0_CL22_B0_AUTONEGLPABIL2_MESSAGE_BITS                 11
#define SGMII0_CL22_B0_AUTONEGLPABIL2_MESSAGE_SHIFT                0


/****************************************************************************
 * SGMII0_CL22_B0 :: MIIextStat
 ***************************************************************************/
/* SGMII0_CL22_B0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
#define Wr_SGMII0_CL22_B0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIIEXTSTAT,0x8000,15,x)
#define Rd_SGMII0_CL22_B0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIIEXTSTAT,0x8000,15)
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15

/* SGMII0_CL22_B0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
#define Wr_SGMII0_CL22_B0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIIEXTSTAT,0x4000,14,x)
#define Rd_SGMII0_CL22_B0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIIEXTSTAT,0x4000,14)
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14

/* SGMII0_CL22_B0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
#define Wr_SGMII0_CL22_B0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIIEXTSTAT,0x2000,13,x)
#define Rd_SGMII0_CL22_B0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIIEXTSTAT,0x2000,13)
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13

/* SGMII0_CL22_B0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
#define Wr_SGMII0_CL22_B0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_CL22_B0_MIIEXTSTAT,0x1000,12,x)
#define Rd_SGMII0_CL22_B0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_CL22_B0_MIIEXTSTAT,0x1000,12)
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII0_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12

/* SGMII0_CL22_B0 :: MIIextStat :: reserved0 [11:00] */
#define SGMII0_CL22_B0_MIIEXTSTAT_RESERVED0_MASK                   0x0fff
#define SGMII0_CL22_B0_MIIEXTSTAT_RESERVED0_ALIGN                  0
#define SGMII0_CL22_B0_MIIEXTSTAT_RESERVED0_BITS                   12
#define SGMII0_CL22_B0_MIIEXTSTAT_RESERVED0_SHIFT                  0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk0
 ***************************************************************************/
/****************************************************************************
 * SGMII_Blk0 :: xgxsControl
 ***************************************************************************/
/* SGMII_Blk0 :: xgxsControl :: pgen_en [15:15] */
#define Wr_SGMII_Blk0_xgxsControl_pgen_en(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x8000,15,x)
#define Rd_SGMII_Blk0_xgxsControl_pgen_en(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x8000,15)
#define SGMII_BLK0_XGXSCONTROL_PGEN_EN_MASK                        0x8000
#define SGMII_BLK0_XGXSCONTROL_PGEN_EN_ALIGN                       0
#define SGMII_BLK0_XGXSCONTROL_PGEN_EN_BITS                        1
#define SGMII_BLK0_XGXSCONTROL_PGEN_EN_SHIFT                       15

/* SGMII_Blk0 :: xgxsControl :: pcmp_en [14:14] */
#define Wr_SGMII_Blk0_xgxsControl_pcmp_en(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x4000,14,x)
#define Rd_SGMII_Blk0_xgxsControl_pcmp_en(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x4000,14)
#define SGMII_BLK0_XGXSCONTROL_PCMP_EN_MASK                        0x4000
#define SGMII_BLK0_XGXSCONTROL_PCMP_EN_ALIGN                       0
#define SGMII_BLK0_XGXSCONTROL_PCMP_EN_BITS                        1
#define SGMII_BLK0_XGXSCONTROL_PCMP_EN_SHIFT                       14

/* SGMII_Blk0 :: xgxsControl :: start_sequencer [13:13] */
#define Wr_SGMII_Blk0_xgxsControl_start_sequencer(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x2000,13,x)
#define Rd_SGMII_Blk0_xgxsControl_start_sequencer(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x2000,13)
#define SGMII_BLK0_XGXSCONTROL_START_SEQUENCER_MASK                0x2000
#define SGMII_BLK0_XGXSCONTROL_START_SEQUENCER_ALIGN               0
#define SGMII_BLK0_XGXSCONTROL_START_SEQUENCER_BITS                1
#define SGMII_BLK0_XGXSCONTROL_START_SEQUENCER_SHIFT               13

/* SGMII_Blk0 :: xgxsControl :: reset_anlg [12:12] */
#define Wr_SGMII_Blk0_xgxsControl_reset_anlg(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x1000,12,x)
#define Rd_SGMII_Blk0_xgxsControl_reset_anlg(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x1000,12)
#define SGMII_BLK0_XGXSCONTROL_RESET_ANLG_MASK                     0x1000
#define SGMII_BLK0_XGXSCONTROL_RESET_ANLG_ALIGN                    0
#define SGMII_BLK0_XGXSCONTROL_RESET_ANLG_BITS                     1
#define SGMII_BLK0_XGXSCONTROL_RESET_ANLG_SHIFT                    12

/* SGMII_Blk0 :: xgxsControl :: mode [11:08] */
#define Wr_SGMII_Blk0_xgxsControl_mode(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0xf00,8,x)
#define Rd_SGMII_Blk0_xgxsControl_mode(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0xf00,8)
#define SGMII_BLK0_XGXSCONTROL_MODE_MASK                           0x0f00
#define SGMII_BLK0_XGXSCONTROL_MODE_ALIGN                          0
#define SGMII_BLK0_XGXSCONTROL_MODE_BITS                           4
#define SGMII_BLK0_XGXSCONTROL_MODE_SHIFT                          8
#define SGMII_BLK0_XGXSCONTROL_MODE_XGXS                           0
#define SGMII_BLK0_XGXSCONTROL_MODE_XGXG_nCC                       1
#define SGMII_BLK0_XGXSCONTROL_MODE_Indlane_OS8                    4
#define SGMII_BLK0_XGXSCONTROL_MODE_IndLane_OS5                    5
#define SGMII_BLK0_XGXSCONTROL_MODE_IndLane_OS4                    6
#define SGMII_BLK0_XGXSCONTROL_MODE_PCI                            7
#define SGMII_BLK0_XGXSCONTROL_MODE_XGXS_nLQ                       8
#define SGMII_BLK0_XGXSCONTROL_MODE_XGXS_nLQnCC                    9
#define SGMII_BLK0_XGXSCONTROL_MODE_PBypass                        10
#define SGMII_BLK0_XGXSCONTROL_MODE_PBypass_nDSK                   11
#define SGMII_BLK0_XGXSCONTROL_MODE_ComboCoreMode                  12
#define SGMII_BLK0_XGXSCONTROL_MODE_Clocks_off                     15

/* SGMII_Blk0 :: xgxsControl :: pll_bypass [07:07] */
#define Wr_SGMII_Blk0_xgxsControl_pll_bypass(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x80,7,x)
#define Rd_SGMII_Blk0_xgxsControl_pll_bypass(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x80,7)
#define SGMII_BLK0_XGXSCONTROL_PLL_BYPASS_MASK                     0x0080
#define SGMII_BLK0_XGXSCONTROL_PLL_BYPASS_ALIGN                    0
#define SGMII_BLK0_XGXSCONTROL_PLL_BYPASS_BITS                     1
#define SGMII_BLK0_XGXSCONTROL_PLL_BYPASS_SHIFT                    7

/* SGMII_Blk0 :: xgxsControl :: rloop [06:06] */
#define Wr_SGMII_Blk0_xgxsControl_rloop(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x40,6,x)
#define Rd_SGMII_Blk0_xgxsControl_rloop(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x40,6)
#define SGMII_BLK0_XGXSCONTROL_RLOOP_MASK                          0x0040
#define SGMII_BLK0_XGXSCONTROL_RLOOP_ALIGN                         0
#define SGMII_BLK0_XGXSCONTROL_RLOOP_BITS                          1
#define SGMII_BLK0_XGXSCONTROL_RLOOP_SHIFT                         6

/* SGMII_Blk0 :: xgxsControl :: reserved_5 [05:05] */
#define SGMII_BLK0_XGXSCONTROL_RESERVED_5_MASK                     0x0020
#define SGMII_BLK0_XGXSCONTROL_RESERVED_5_ALIGN                    0
#define SGMII_BLK0_XGXSCONTROL_RESERVED_5_BITS                     1
#define SGMII_BLK0_XGXSCONTROL_RESERVED_5_SHIFT                    5

/* SGMII_Blk0 :: xgxsControl :: mdio_cont_en [04:04] */
#define Wr_SGMII_Blk0_xgxsControl_mdio_cont_en(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x10,4,x)
#define Rd_SGMII_Blk0_xgxsControl_mdio_cont_en(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x10,4)
#define SGMII_BLK0_XGXSCONTROL_MDIO_CONT_EN_MASK                   0x0010
#define SGMII_BLK0_XGXSCONTROL_MDIO_CONT_EN_ALIGN                  0
#define SGMII_BLK0_XGXSCONTROL_MDIO_CONT_EN_BITS                   1
#define SGMII_BLK0_XGXSCONTROL_MDIO_CONT_EN_SHIFT                  4

/* SGMII_Blk0 :: xgxsControl :: cdet_en [03:03] */
#define Wr_SGMII_Blk0_xgxsControl_cdet_en(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x8,3,x)
#define Rd_SGMII_Blk0_xgxsControl_cdet_en(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x8,3)
#define SGMII_BLK0_XGXSCONTROL_CDET_EN_MASK                        0x0008
#define SGMII_BLK0_XGXSCONTROL_CDET_EN_ALIGN                       0
#define SGMII_BLK0_XGXSCONTROL_CDET_EN_BITS                        1
#define SGMII_BLK0_XGXSCONTROL_CDET_EN_SHIFT                       3

/* SGMII_Blk0 :: xgxsControl :: eden [02:02] */
#define Wr_SGMII_Blk0_xgxsControl_eden(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x4,2,x)
#define Rd_SGMII_Blk0_xgxsControl_eden(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x4,2)
#define SGMII_BLK0_XGXSCONTROL_EDEN_MASK                           0x0004
#define SGMII_BLK0_XGXSCONTROL_EDEN_ALIGN                          0
#define SGMII_BLK0_XGXSCONTROL_EDEN_BITS                           1
#define SGMII_BLK0_XGXSCONTROL_EDEN_SHIFT                          2

/* SGMII_Blk0 :: xgxsControl :: afrst_en [01:01] */
#define Wr_SGMII_Blk0_xgxsControl_afrst_en(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x2,1,x)
#define Rd_SGMII_Blk0_xgxsControl_afrst_en(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x2,1)
#define SGMII_BLK0_XGXSCONTROL_AFRST_EN_MASK                       0x0002
#define SGMII_BLK0_XGXSCONTROL_AFRST_EN_ALIGN                      0
#define SGMII_BLK0_XGXSCONTROL_AFRST_EN_BITS                       1
#define SGMII_BLK0_XGXSCONTROL_AFRST_EN_SHIFT                      1

/* SGMII_Blk0 :: xgxsControl :: txcko_div [00:00] */
#define Wr_SGMII_Blk0_xgxsControl_txcko_div(x) WriteRegBits16(SGMII_BLK0_XGXSCONTROL,0x1,0,x)
#define Rd_SGMII_Blk0_xgxsControl_txcko_div(x) ReadRegBits16(SGMII_BLK0_XGXSCONTROL,0x1,0)
#define SGMII_BLK0_XGXSCONTROL_TXCKO_DIV_MASK                      0x0001
#define SGMII_BLK0_XGXSCONTROL_TXCKO_DIV_ALIGN                     0
#define SGMII_BLK0_XGXSCONTROL_TXCKO_DIV_BITS                      1
#define SGMII_BLK0_XGXSCONTROL_TXCKO_DIV_SHIFT                     0


/****************************************************************************
 * SGMII_Blk0 :: mmdSelect
 ***************************************************************************/
/* SGMII_Blk0 :: mmdSelect :: multiPRTs_en [15:15] */
#define Wr_SGMII_Blk0_mmdSelect_multiPRTs_en(x) WriteRegBits16(SGMII_BLK0_MMDSELECT,0x8000,15,x)
#define Rd_SGMII_Blk0_mmdSelect_multiPRTs_en(x) ReadRegBits16(SGMII_BLK0_MMDSELECT,0x8000,15)
#define SGMII_BLK0_MMDSELECT_MULTIPRTS_EN_MASK                     0x8000
#define SGMII_BLK0_MMDSELECT_MULTIPRTS_EN_ALIGN                    0
#define SGMII_BLK0_MMDSELECT_MULTIPRTS_EN_BITS                     1
#define SGMII_BLK0_MMDSELECT_MULTIPRTS_EN_SHIFT                    15

/* SGMII_Blk0 :: mmdSelect :: multiMMDs_en [14:14] */
#define Wr_SGMII_Blk0_mmdSelect_multiMMDs_en(x) WriteRegBits16(SGMII_BLK0_MMDSELECT,0x4000,14,x)
#define Rd_SGMII_Blk0_mmdSelect_multiMMDs_en(x) ReadRegBits16(SGMII_BLK0_MMDSELECT,0x4000,14)
#define SGMII_BLK0_MMDSELECT_MULTIMMDS_EN_MASK                     0x4000
#define SGMII_BLK0_MMDSELECT_MULTIMMDS_EN_ALIGN                    0
#define SGMII_BLK0_MMDSELECT_MULTIMMDS_EN_BITS                     1
#define SGMII_BLK0_MMDSELECT_MULTIMMDS_EN_SHIFT                    14

/* SGMII_Blk0 :: mmdSelect :: reserved0 [13:04] */
#define SGMII_BLK0_MMDSELECT_RESERVED0_MASK                        0x3ff0
#define SGMII_BLK0_MMDSELECT_RESERVED0_ALIGN                       0
#define SGMII_BLK0_MMDSELECT_RESERVED0_BITS                        10
#define SGMII_BLK0_MMDSELECT_RESERVED0_SHIFT                       4

/* SGMII_Blk0 :: mmdSelect :: devAN_en [03:03] */
#define Wr_SGMII_Blk0_mmdSelect_devAN_en(x) WriteRegBits16(SGMII_BLK0_MMDSELECT,0x8,3,x)
#define Rd_SGMII_Blk0_mmdSelect_devAN_en(x) ReadRegBits16(SGMII_BLK0_MMDSELECT,0x8,3)
#define SGMII_BLK0_MMDSELECT_DEVAN_EN_MASK                         0x0008
#define SGMII_BLK0_MMDSELECT_DEVAN_EN_ALIGN                        0
#define SGMII_BLK0_MMDSELECT_DEVAN_EN_BITS                         1
#define SGMII_BLK0_MMDSELECT_DEVAN_EN_SHIFT                        3

/* SGMII_Blk0 :: mmdSelect :: devPMD_en [02:02] */
#define Wr_SGMII_Blk0_mmdSelect_devPMD_en(x) WriteRegBits16(SGMII_BLK0_MMDSELECT,0x4,2,x)
#define Rd_SGMII_Blk0_mmdSelect_devPMD_en(x) ReadRegBits16(SGMII_BLK0_MMDSELECT,0x4,2)
#define SGMII_BLK0_MMDSELECT_DEVPMD_EN_MASK                        0x0004
#define SGMII_BLK0_MMDSELECT_DEVPMD_EN_ALIGN                       0
#define SGMII_BLK0_MMDSELECT_DEVPMD_EN_BITS                        1
#define SGMII_BLK0_MMDSELECT_DEVPMD_EN_SHIFT                       2

/* SGMII_Blk0 :: mmdSelect :: devDEVAD_en [01:01] */
#define Wr_SGMII_Blk0_mmdSelect_devDEVAD_en(x) WriteRegBits16(SGMII_BLK0_MMDSELECT,0x2,1,x)
#define Rd_SGMII_Blk0_mmdSelect_devDEVAD_en(x) ReadRegBits16(SGMII_BLK0_MMDSELECT,0x2,1)
#define SGMII_BLK0_MMDSELECT_DEVDEVAD_EN_MASK                      0x0002
#define SGMII_BLK0_MMDSELECT_DEVDEVAD_EN_ALIGN                     0
#define SGMII_BLK0_MMDSELECT_DEVDEVAD_EN_BITS                      1
#define SGMII_BLK0_MMDSELECT_DEVDEVAD_EN_SHIFT                     1

/* SGMII_Blk0 :: mmdSelect :: devCL22_en [00:00] */
#define Wr_SGMII_Blk0_mmdSelect_devCL22_en(x) WriteRegBits16(SGMII_BLK0_MMDSELECT,0x1,0,x)
#define Rd_SGMII_Blk0_mmdSelect_devCL22_en(x) ReadRegBits16(SGMII_BLK0_MMDSELECT,0x1,0)
#define SGMII_BLK0_MMDSELECT_DEVCL22_EN_MASK                       0x0001
#define SGMII_BLK0_MMDSELECT_DEVCL22_EN_ALIGN                      0
#define SGMII_BLK0_MMDSELECT_DEVCL22_EN_BITS                       1
#define SGMII_BLK0_MMDSELECT_DEVCL22_EN_SHIFT                      0


/****************************************************************************
 * SGMII_Blk0 :: miscControl1
 ***************************************************************************/
/* SGMII_Blk0 :: miscControl1 :: reserved0 [15:13] */
#define SGMII_BLK0_MISCCONTROL1_RESERVED0_MASK                     0xe000
#define SGMII_BLK0_MISCCONTROL1_RESERVED0_ALIGN                    0
#define SGMII_BLK0_MISCCONTROL1_RESERVED0_BITS                     3
#define SGMII_BLK0_MISCCONTROL1_RESERVED0_SHIFT                    13

/* SGMII_Blk0 :: miscControl1 :: PMD_Lane0_tx_disable [12:12] */
#define Wr_SGMII_Blk0_miscControl1_PMD_Lane0_tx_disable(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x1000,12,x)
#define Rd_SGMII_Blk0_miscControl1_PMD_Lane0_tx_disable(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x1000,12)
#define SGMII_BLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_MASK          0x1000
#define SGMII_BLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_ALIGN         0
#define SGMII_BLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_BITS          1
#define SGMII_BLK0_MISCCONTROL1_PMD_LANE0_TX_DISABLE_SHIFT         12

/* SGMII_Blk0 :: miscControl1 :: Global_PMD_tx_disable [11:11] */
#define Wr_SGMII_Blk0_miscControl1_Global_PMD_tx_disable(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x800,11,x)
#define Rd_SGMII_Blk0_miscControl1_Global_PMD_tx_disable(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x800,11)
#define SGMII_BLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_MASK         0x0800
#define SGMII_BLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_ALIGN        0
#define SGMII_BLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_BITS         1
#define SGMII_BLK0_MISCCONTROL1_GLOBAL_PMD_TX_DISABLE_SHIFT        11

/* SGMII_Blk0 :: miscControl1 :: PCS_dev_en_override [10:10] */
#define Wr_SGMII_Blk0_miscControl1_PCS_dev_en_override(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x400,10,x)
#define Rd_SGMII_Blk0_miscControl1_PCS_dev_en_override(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x400,10)
#define SGMII_BLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_MASK           0x0400
#define SGMII_BLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_ALIGN          0
#define SGMII_BLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_BITS           1
#define SGMII_BLK0_MISCCONTROL1_PCS_DEV_EN_OVERRIDE_SHIFT          10

/* SGMII_Blk0 :: miscControl1 :: PMD_dev_en_override [09:09] */
#define Wr_SGMII_Blk0_miscControl1_PMD_dev_en_override(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x200,9,x)
#define Rd_SGMII_Blk0_miscControl1_PMD_dev_en_override(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x200,9)
#define SGMII_BLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_MASK           0x0200
#define SGMII_BLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_ALIGN          0
#define SGMII_BLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_BITS           1
#define SGMII_BLK0_MISCCONTROL1_PMD_DEV_EN_OVERRIDE_SHIFT          9

/* SGMII_Blk0 :: miscControl1 :: reserved1 [08:08] */
#define SGMII_BLK0_MISCCONTROL1_RESERVED1_MASK                     0x0100
#define SGMII_BLK0_MISCCONTROL1_RESERVED1_ALIGN                    0
#define SGMII_BLK0_MISCCONTROL1_RESERVED1_BITS                     1
#define SGMII_BLK0_MISCCONTROL1_RESERVED1_SHIFT                    8

/* SGMII_Blk0 :: miscControl1 :: clear_linkdown [07:07] */
#define Wr_SGMII_Blk0_miscControl1_clear_linkdown(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x80,7,x)
#define Rd_SGMII_Blk0_miscControl1_clear_linkdown(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x80,7)
#define SGMII_BLK0_MISCCONTROL1_CLEAR_LINKDOWN_MASK                0x0080
#define SGMII_BLK0_MISCCONTROL1_CLEAR_LINKDOWN_ALIGN               0
#define SGMII_BLK0_MISCCONTROL1_CLEAR_LINKDOWN_BITS                1
#define SGMII_BLK0_MISCCONTROL1_CLEAR_LINKDOWN_SHIFT               7

/* SGMII_Blk0 :: miscControl1 :: latch_linkdown_enable [06:06] */
#define Wr_SGMII_Blk0_miscControl1_latch_linkdown_enable(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x40,6,x)
#define Rd_SGMII_Blk0_miscControl1_latch_linkdown_enable(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x40,6)
#define SGMII_BLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_MASK         0x0040
#define SGMII_BLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_ALIGN        0
#define SGMII_BLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_BITS         1
#define SGMII_BLK0_MISCCONTROL1_LATCH_LINKDOWN_ENABLE_SHIFT        6

/* SGMII_Blk0 :: miscControl1 :: reserved2 [05:05] */
#define SGMII_BLK0_MISCCONTROL1_RESERVED2_MASK                     0x0020
#define SGMII_BLK0_MISCCONTROL1_RESERVED2_ALIGN                    0
#define SGMII_BLK0_MISCCONTROL1_RESERVED2_BITS                     1
#define SGMII_BLK0_MISCCONTROL1_RESERVED2_SHIFT                    5

/* SGMII_Blk0 :: miscControl1 :: force_div5_for_lxck25 [04:04] */
#define Wr_SGMII_Blk0_miscControl1_force_div5_for_lxck25(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x10,4,x)
#define Rd_SGMII_Blk0_miscControl1_force_div5_for_lxck25(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x10,4)
#define SGMII_BLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_MASK         0x0010
#define SGMII_BLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_ALIGN        0
#define SGMII_BLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_BITS         1
#define SGMII_BLK0_MISCCONTROL1_FORCE_DIV5_FOR_LXCK25_SHIFT        4

/* SGMII_Blk0 :: miscControl1 :: pardet10g_pwrdnLink_en [03:03] */
#define Wr_SGMII_Blk0_miscControl1_pardet10g_pwrdnLink_en(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x8,3,x)
#define Rd_SGMII_Blk0_miscControl1_pardet10g_pwrdnLink_en(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x8,3)
#define SGMII_BLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_MASK        0x0008
#define SGMII_BLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_ALIGN       0
#define SGMII_BLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_BITS        1
#define SGMII_BLK0_MISCCONTROL1_PARDET10G_PWRDNLINK_EN_SHIFT       3

/* SGMII_Blk0 :: miscControl1 :: invert_rx_sigdet [02:02] */
#define Wr_SGMII_Blk0_miscControl1_invert_rx_sigdet(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x4,2,x)
#define Rd_SGMII_Blk0_miscControl1_invert_rx_sigdet(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x4,2)
#define SGMII_BLK0_MISCCONTROL1_INVERT_RX_SIGDET_MASK              0x0004
#define SGMII_BLK0_MISCCONTROL1_INVERT_RX_SIGDET_ALIGN             0
#define SGMII_BLK0_MISCCONTROL1_INVERT_RX_SIGDET_BITS              1
#define SGMII_BLK0_MISCCONTROL1_INVERT_RX_SIGDET_SHIFT             2

/* SGMII_Blk0 :: miscControl1 :: ieee_blksel_autodet [01:01] */
#define Wr_SGMII_Blk0_miscControl1_ieee_blksel_autodet(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x2,1,x)
#define Rd_SGMII_Blk0_miscControl1_ieee_blksel_autodet(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x2,1)
#define SGMII_BLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_MASK           0x0002
#define SGMII_BLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_ALIGN          0
#define SGMII_BLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_BITS           1
#define SGMII_BLK0_MISCCONTROL1_IEEE_BLKSEL_AUTODET_SHIFT          1

/* SGMII_Blk0 :: miscControl1 :: ieee_blksel_val [00:00] */
#define Wr_SGMII_Blk0_miscControl1_ieee_blksel_val(x) WriteRegBits16(SGMII_BLK0_MISCCONTROL1,0x1,0,x)
#define Rd_SGMII_Blk0_miscControl1_ieee_blksel_val(x) ReadRegBits16(SGMII_BLK0_MISCCONTROL1,0x1,0)
#define SGMII_BLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_MASK               0x0001
#define SGMII_BLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_ALIGN              0
#define SGMII_BLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_BITS               1
#define SGMII_BLK0_MISCCONTROL1_IEEE_BLKSEL_VAL_SHIFT              0


/****************************************************************************
 * SGMII_Blk0 :: BlockAddress
 ***************************************************************************/
/* SGMII_Blk0 :: BlockAddress :: reserved0 [15:15] */
#define SGMII_BLK0_BLOCKADDRESS_RESERVED0_MASK                     0x8000
#define SGMII_BLK0_BLOCKADDRESS_RESERVED0_ALIGN                    0
#define SGMII_BLK0_BLOCKADDRESS_RESERVED0_BITS                     1
#define SGMII_BLK0_BLOCKADDRESS_RESERVED0_SHIFT                    15

/* SGMII_Blk0 :: BlockAddress :: BlockAddress [14:04] */
#define Wr_SGMII_Blk0_BlockAddress_BlockAddress(x) WriteRegBits16(SGMII_BLK0_BLOCKADDRESS,0x7ff0,4,x)
#define Rd_SGMII_Blk0_BlockAddress_BlockAddress(x) ReadRegBits16(SGMII_BLK0_BLOCKADDRESS,0x7ff0,4)
#define SGMII_BLK0_BLOCKADDRESS_BLOCKADDRESS_MASK                  0x7ff0
#define SGMII_BLK0_BLOCKADDRESS_BLOCKADDRESS_ALIGN                 0
#define SGMII_BLK0_BLOCKADDRESS_BLOCKADDRESS_BITS                  11
#define SGMII_BLK0_BLOCKADDRESS_BLOCKADDRESS_SHIFT                 4

/* SGMII_Blk0 :: BlockAddress :: reserved1 [03:00] */
#define SGMII_BLK0_BLOCKADDRESS_RESERVED1_MASK                     0x000f
#define SGMII_BLK0_BLOCKADDRESS_RESERVED1_ALIGN                    0
#define SGMII_BLK0_BLOCKADDRESS_RESERVED1_BITS                     4
#define SGMII_BLK0_BLOCKADDRESS_RESERVED1_SHIFT                    0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk1
 ***************************************************************************/
/****************************************************************************
 * SGMII_Blk1 :: laneCtrl0
 ***************************************************************************/
/* SGMII_Blk1 :: laneCtrl0 :: reserved0 [15:08] */
#define SGMII_BLK1_LANECTRL0_RESERVED0_MASK                        0xff00
#define SGMII_BLK1_LANECTRL0_RESERVED0_ALIGN                       0
#define SGMII_BLK1_LANECTRL0_RESERVED0_BITS                        8
#define SGMII_BLK1_LANECTRL0_RESERVED0_SHIFT                       8

/* SGMII_Blk1 :: laneCtrl0 :: cl36_pcs_en_rx [07:04] */
#define Wr_SGMII_Blk1_laneCtrl0_cl36_pcs_en_rx(x) WriteRegBits16(SGMII_BLK1_LANECTRL0,0xf0,4,x)
#define Rd_SGMII_Blk1_laneCtrl0_cl36_pcs_en_rx(x) ReadRegBits16(SGMII_BLK1_LANECTRL0,0xf0,4)
#define SGMII_BLK1_LANECTRL0_CL36_PCS_EN_RX_MASK                   0x00f0
#define SGMII_BLK1_LANECTRL0_CL36_PCS_EN_RX_ALIGN                  0
#define SGMII_BLK1_LANECTRL0_CL36_PCS_EN_RX_BITS                   4
#define SGMII_BLK1_LANECTRL0_CL36_PCS_EN_RX_SHIFT                  4

/* SGMII_Blk1 :: laneCtrl0 :: cl36_pcs_en_tx [03:00] */
#define Wr_SGMII_Blk1_laneCtrl0_cl36_pcs_en_tx(x) WriteRegBits16(SGMII_BLK1_LANECTRL0,0xf,0,x)
#define Rd_SGMII_Blk1_laneCtrl0_cl36_pcs_en_tx(x) ReadRegBits16(SGMII_BLK1_LANECTRL0,0xf,0)
#define SGMII_BLK1_LANECTRL0_CL36_PCS_EN_TX_MASK                   0x000f
#define SGMII_BLK1_LANECTRL0_CL36_PCS_EN_TX_ALIGN                  0
#define SGMII_BLK1_LANECTRL0_CL36_PCS_EN_TX_BITS                   4
#define SGMII_BLK1_LANECTRL0_CL36_PCS_EN_TX_SHIFT                  0


/****************************************************************************
 * SGMII_Blk1 :: laneCtrl1
 ***************************************************************************/
/* SGMII_Blk1 :: laneCtrl1 :: rx1g_mode_ln3 [15:14] */
#define Wr_SGMII_Blk1_laneCtrl1_rx1g_mode_ln3(x) WriteRegBits16(SGMII_BLK1_LANECTRL1,0xc000,14,x)
#define Rd_SGMII_Blk1_laneCtrl1_rx1g_mode_ln3(x) ReadRegBits16(SGMII_BLK1_LANECTRL1,0xc000,14)
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN3_MASK                    0xc000
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN3_ALIGN                   0
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN3_BITS                    2
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN3_SHIFT                   14
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div2              0
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN3_SWSDR_div1              1
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div2              2
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN3_DWSDR_div1              3

/* SGMII_Blk1 :: laneCtrl1 :: rx1g_mode_ln2 [13:12] */
#define Wr_SGMII_Blk1_laneCtrl1_rx1g_mode_ln2(x) WriteRegBits16(SGMII_BLK1_LANECTRL1,0x3000,12,x)
#define Rd_SGMII_Blk1_laneCtrl1_rx1g_mode_ln2(x) ReadRegBits16(SGMII_BLK1_LANECTRL1,0x3000,12)
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN2_MASK                    0x3000
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN2_ALIGN                   0
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN2_BITS                    2
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN2_SHIFT                   12
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div2              0
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN2_SWSDR_div1              1
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div2              2
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN2_DWSDR_div1              3

/* SGMII_Blk1 :: laneCtrl1 :: rx1g_mode_ln1 [11:10] */
#define Wr_SGMII_Blk1_laneCtrl1_rx1g_mode_ln1(x) WriteRegBits16(SGMII_BLK1_LANECTRL1,0xc00,10,x)
#define Rd_SGMII_Blk1_laneCtrl1_rx1g_mode_ln1(x) ReadRegBits16(SGMII_BLK1_LANECTRL1,0xc00,10)
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN1_MASK                    0x0c00
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN1_ALIGN                   0
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN1_BITS                    2
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN1_SHIFT                   10
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div2              0
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN1_SWSDR_div1              1
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div2              2
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN1_DWSDR_div1              3

/* SGMII_Blk1 :: laneCtrl1 :: rx1g_mode_ln0 [09:08] */
#define Wr_SGMII_Blk1_laneCtrl1_rx1g_mode_ln0(x) WriteRegBits16(SGMII_BLK1_LANECTRL1,0x300,8,x)
#define Rd_SGMII_Blk1_laneCtrl1_rx1g_mode_ln0(x) ReadRegBits16(SGMII_BLK1_LANECTRL1,0x300,8)
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN0_MASK                    0x0300
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN0_ALIGN                   0
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN0_BITS                    2
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN0_SHIFT                   8
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div2              0
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN0_SWSDR_div1              1
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div2              2
#define SGMII_BLK1_LANECTRL1_RX1G_MODE_LN0_DWSDR_div1              3

/* SGMII_Blk1 :: laneCtrl1 :: tx1g_mode_ln3 [07:06] */
#define Wr_SGMII_Blk1_laneCtrl1_tx1g_mode_ln3(x) WriteRegBits16(SGMII_BLK1_LANECTRL1,0xc0,6,x)
#define Rd_SGMII_Blk1_laneCtrl1_tx1g_mode_ln3(x) ReadRegBits16(SGMII_BLK1_LANECTRL1,0xc0,6)
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN3_MASK                    0x00c0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN3_ALIGN                   0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN3_BITS                    2
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN3_SHIFT                   6
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div2              0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN3_SWSDR_div1              1
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div2              2
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN3_DWSDR_div1              3

/* SGMII_Blk1 :: laneCtrl1 :: tx1g_mode_ln2 [05:04] */
#define Wr_SGMII_Blk1_laneCtrl1_tx1g_mode_ln2(x) WriteRegBits16(SGMII_BLK1_LANECTRL1,0x30,4,x)
#define Rd_SGMII_Blk1_laneCtrl1_tx1g_mode_ln2(x) ReadRegBits16(SGMII_BLK1_LANECTRL1,0x30,4)
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN2_MASK                    0x0030
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN2_ALIGN                   0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN2_BITS                    2
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN2_SHIFT                   4
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div2              0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN2_SWSDR_div1              1
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div2              2
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN2_DWSDR_div1              3

/* SGMII_Blk1 :: laneCtrl1 :: tx1g_mode_ln1 [03:02] */
#define Wr_SGMII_Blk1_laneCtrl1_tx1g_mode_ln1(x) WriteRegBits16(SGMII_BLK1_LANECTRL1,0xc,2,x)
#define Rd_SGMII_Blk1_laneCtrl1_tx1g_mode_ln1(x) ReadRegBits16(SGMII_BLK1_LANECTRL1,0xc,2)
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN1_MASK                    0x000c
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN1_ALIGN                   0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN1_BITS                    2
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN1_SHIFT                   2
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div2              0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN1_SWSDR_div1              1
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div2              2
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN1_DWSDR_div1              3

/* SGMII_Blk1 :: laneCtrl1 :: tx1g_mode_ln0 [01:00] */
#define Wr_SGMII_Blk1_laneCtrl1_tx1g_mode_ln0(x) WriteRegBits16(SGMII_BLK1_LANECTRL1,0x3,0,x)
#define Rd_SGMII_Blk1_laneCtrl1_tx1g_mode_ln0(x) ReadRegBits16(SGMII_BLK1_LANECTRL1,0x3,0)
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN0_MASK                    0x0003
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN0_ALIGN                   0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN0_BITS                    2
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN0_SHIFT                   0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div2              0
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN0_SWSDR_div1              1
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div2              2
#define SGMII_BLK1_LANECTRL1_TX1G_MODE_LN0_DWSDR_div1              3


/****************************************************************************
 * SGMII_Blk1 :: laneCtrl2
 ***************************************************************************/
/* SGMII_Blk1 :: laneCtrl2 :: reserved_15_13 [15:13] */
#define SGMII_BLK1_LANECTRL2_RESERVED_15_13_MASK                   0xe000
#define SGMII_BLK1_LANECTRL2_RESERVED_15_13_ALIGN                  0
#define SGMII_BLK1_LANECTRL2_RESERVED_15_13_BITS                   3
#define SGMII_BLK1_LANECTRL2_RESERVED_15_13_SHIFT                  13

/* SGMII_Blk1 :: laneCtrl2 :: cdet_en1g [12:12] */
#define Wr_SGMII_Blk1_laneCtrl2_cdet_en1g(x) WriteRegBits16(SGMII_BLK1_LANECTRL2,0x1000,12,x)
#define Rd_SGMII_Blk1_laneCtrl2_cdet_en1g(x) ReadRegBits16(SGMII_BLK1_LANECTRL2,0x1000,12)
#define SGMII_BLK1_LANECTRL2_CDET_EN1G_MASK                        0x1000
#define SGMII_BLK1_LANECTRL2_CDET_EN1G_ALIGN                       0
#define SGMII_BLK1_LANECTRL2_CDET_EN1G_BITS                        1
#define SGMII_BLK1_LANECTRL2_CDET_EN1G_SHIFT                       12

/* SGMII_Blk1 :: laneCtrl2 :: reserved_11_10 [11:09] */
#define SGMII_BLK1_LANECTRL2_RESERVED_11_10_MASK                   0x0e00
#define SGMII_BLK1_LANECTRL2_RESERVED_11_10_ALIGN                  0
#define SGMII_BLK1_LANECTRL2_RESERVED_11_10_BITS                   3
#define SGMII_BLK1_LANECTRL2_RESERVED_11_10_SHIFT                  9

/* SGMII_Blk1 :: laneCtrl2 :: eden1g [08:08] */
#define Wr_SGMII_Blk1_laneCtrl2_eden1g(x) WriteRegBits16(SGMII_BLK1_LANECTRL2,0x100,8,x)
#define Rd_SGMII_Blk1_laneCtrl2_eden1g(x) ReadRegBits16(SGMII_BLK1_LANECTRL2,0x100,8)
#define SGMII_BLK1_LANECTRL2_EDEN1G_MASK                           0x0100
#define SGMII_BLK1_LANECTRL2_EDEN1G_ALIGN                          0
#define SGMII_BLK1_LANECTRL2_EDEN1G_BITS                           1
#define SGMII_BLK1_LANECTRL2_EDEN1G_SHIFT                          8

/* SGMII_Blk1 :: laneCtrl2 :: reserved0 [07:01] */
#define SGMII_BLK1_LANECTRL2_RESERVED0_MASK                        0x00fe
#define SGMII_BLK1_LANECTRL2_RESERVED0_ALIGN                       0
#define SGMII_BLK1_LANECTRL2_RESERVED0_BITS                        7
#define SGMII_BLK1_LANECTRL2_RESERVED0_SHIFT                       1

/* SGMII_Blk1 :: laneCtrl2 :: gloop1g [00:00] */
#define Wr_SGMII_Blk1_laneCtrl2_gloop1g(x) WriteRegBits16(SGMII_BLK1_LANECTRL2,0x1,0,x)
#define Rd_SGMII_Blk1_laneCtrl2_gloop1g(x) ReadRegBits16(SGMII_BLK1_LANECTRL2,0x1,0)
#define SGMII_BLK1_LANECTRL2_GLOOP1G_MASK                          0x0001
#define SGMII_BLK1_LANECTRL2_GLOOP1G_ALIGN                         0
#define SGMII_BLK1_LANECTRL2_GLOOP1G_BITS                          1
#define SGMII_BLK1_LANECTRL2_GLOOP1G_SHIFT                         0


/****************************************************************************
 * SGMII_Blk1 :: laneCtrl3
 ***************************************************************************/
/* SGMII_Blk1 :: laneCtrl3 :: reserved0 [15:13] */
#define SGMII_BLK1_LANECTRL3_RESERVED0_MASK                        0xe000
#define SGMII_BLK1_LANECTRL3_RESERVED0_ALIGN                       0
#define SGMII_BLK1_LANECTRL3_RESERVED0_BITS                        3
#define SGMII_BLK1_LANECTRL3_RESERVED0_SHIFT                       13

/* SGMII_Blk1 :: laneCtrl3 :: lock_ref [12:12] */
#define Wr_SGMII_Blk1_laneCtrl3_lock_ref(x) WriteRegBits16(SGMII_BLK1_LANECTRL3,0x1000,12,x)
#define Rd_SGMII_Blk1_laneCtrl3_lock_ref(x) ReadRegBits16(SGMII_BLK1_LANECTRL3,0x1000,12)
#define SGMII_BLK1_LANECTRL3_LOCK_REF_MASK                         0x1000
#define SGMII_BLK1_LANECTRL3_LOCK_REF_ALIGN                        0
#define SGMII_BLK1_LANECTRL3_LOCK_REF_BITS                         1
#define SGMII_BLK1_LANECTRL3_LOCK_REF_SHIFT                        12

/* SGMII_Blk1 :: laneCtrl3 :: pwrdwn_force [11:11] */
#define Wr_SGMII_Blk1_laneCtrl3_pwrdwn_force(x) WriteRegBits16(SGMII_BLK1_LANECTRL3,0x800,11,x)
#define Rd_SGMII_Blk1_laneCtrl3_pwrdwn_force(x) ReadRegBits16(SGMII_BLK1_LANECTRL3,0x800,11)
#define SGMII_BLK1_LANECTRL3_PWRDWN_FORCE_MASK                     0x0800
#define SGMII_BLK1_LANECTRL3_PWRDWN_FORCE_ALIGN                    0
#define SGMII_BLK1_LANECTRL3_PWRDWN_FORCE_BITS                     1
#define SGMII_BLK1_LANECTRL3_PWRDWN_FORCE_SHIFT                    11

/* SGMII_Blk1 :: laneCtrl3 :: lock_ref_en [10:10] */
#define Wr_SGMII_Blk1_laneCtrl3_lock_ref_en(x) WriteRegBits16(SGMII_BLK1_LANECTRL3,0x400,10,x)
#define Rd_SGMII_Blk1_laneCtrl3_lock_ref_en(x) ReadRegBits16(SGMII_BLK1_LANECTRL3,0x400,10)
#define SGMII_BLK1_LANECTRL3_LOCK_REF_EN_MASK                      0x0400
#define SGMII_BLK1_LANECTRL3_LOCK_REF_EN_ALIGN                     0
#define SGMII_BLK1_LANECTRL3_LOCK_REF_EN_BITS                      1
#define SGMII_BLK1_LANECTRL3_LOCK_REF_EN_SHIFT                     10

/* SGMII_Blk1 :: laneCtrl3 :: reserved_9 [09:09] */
#define SGMII_BLK1_LANECTRL3_RESERVED_9_MASK                       0x0200
#define SGMII_BLK1_LANECTRL3_RESERVED_9_ALIGN                      0
#define SGMII_BLK1_LANECTRL3_RESERVED_9_BITS                       1
#define SGMII_BLK1_LANECTRL3_RESERVED_9_SHIFT                      9

/* SGMII_Blk1 :: laneCtrl3 :: pwrdwn_pll [08:08] */
#define Wr_SGMII_Blk1_laneCtrl3_pwrdwn_pll(x) WriteRegBits16(SGMII_BLK1_LANECTRL3,0x100,8,x)
#define Rd_SGMII_Blk1_laneCtrl3_pwrdwn_pll(x) ReadRegBits16(SGMII_BLK1_LANECTRL3,0x100,8)
#define SGMII_BLK1_LANECTRL3_PWRDWN_PLL_MASK                       0x0100
#define SGMII_BLK1_LANECTRL3_PWRDWN_PLL_ALIGN                      0
#define SGMII_BLK1_LANECTRL3_PWRDWN_PLL_BITS                       1
#define SGMII_BLK1_LANECTRL3_PWRDWN_PLL_SHIFT                      8

/* SGMII_Blk1 :: laneCtrl3 :: reserved1 [07:05] */
#define SGMII_BLK1_LANECTRL3_RESERVED1_MASK                        0x00e0
#define SGMII_BLK1_LANECTRL3_RESERVED1_ALIGN                       0
#define SGMII_BLK1_LANECTRL3_RESERVED1_BITS                        3
#define SGMII_BLK1_LANECTRL3_RESERVED1_SHIFT                       5

/* SGMII_Blk1 :: laneCtrl3 :: pwrdn_tx [04:04] */
#define Wr_SGMII_Blk1_laneCtrl3_pwrdn_tx(x) WriteRegBits16(SGMII_BLK1_LANECTRL3,0x10,4,x)
#define Rd_SGMII_Blk1_laneCtrl3_pwrdn_tx(x) ReadRegBits16(SGMII_BLK1_LANECTRL3,0x10,4)
#define SGMII_BLK1_LANECTRL3_PWRDN_TX_MASK                         0x0010
#define SGMII_BLK1_LANECTRL3_PWRDN_TX_ALIGN                        0
#define SGMII_BLK1_LANECTRL3_PWRDN_TX_BITS                         1
#define SGMII_BLK1_LANECTRL3_PWRDN_TX_SHIFT                        4

/* SGMII_Blk1 :: laneCtrl3 :: reserved2 [03:01] */
#define SGMII_BLK1_LANECTRL3_RESERVED2_MASK                        0x000e
#define SGMII_BLK1_LANECTRL3_RESERVED2_ALIGN                       0
#define SGMII_BLK1_LANECTRL3_RESERVED2_BITS                        3
#define SGMII_BLK1_LANECTRL3_RESERVED2_SHIFT                       1

/* SGMII_Blk1 :: laneCtrl3 :: pwrdn_rx [00:00] */
#define Wr_SGMII_Blk1_laneCtrl3_pwrdn_rx(x) WriteRegBits16(SGMII_BLK1_LANECTRL3,0x1,0,x)
#define Rd_SGMII_Blk1_laneCtrl3_pwrdn_rx(x) ReadRegBits16(SGMII_BLK1_LANECTRL3,0x1,0)
#define SGMII_BLK1_LANECTRL3_PWRDN_RX_MASK                         0x0001
#define SGMII_BLK1_LANECTRL3_PWRDN_RX_ALIGN                        0
#define SGMII_BLK1_LANECTRL3_PWRDN_RX_BITS                         1
#define SGMII_BLK1_LANECTRL3_PWRDN_RX_SHIFT                        0


/****************************************************************************
 * SGMII_Blk1 :: lanePrbs
 ***************************************************************************/
/* SGMII_Blk1 :: lanePrbs :: reserved0 [15:04] */
#define SGMII_BLK1_LANEPRBS_RESERVED0_MASK                         0xfff0
#define SGMII_BLK1_LANEPRBS_RESERVED0_ALIGN                        0
#define SGMII_BLK1_LANEPRBS_RESERVED0_BITS                         12
#define SGMII_BLK1_LANEPRBS_RESERVED0_SHIFT                        4

/* SGMII_Blk1 :: lanePrbs :: prbs_en0 [03:03] */
#define Wr_SGMII_Blk1_lanePrbs_prbs_en0(x) WriteRegBits16(SGMII_BLK1_LANEPRBS,0x8,3,x)
#define Rd_SGMII_Blk1_lanePrbs_prbs_en0(x) ReadRegBits16(SGMII_BLK1_LANEPRBS,0x8,3)
#define SGMII_BLK1_LANEPRBS_PRBS_EN0_MASK                          0x0008
#define SGMII_BLK1_LANEPRBS_PRBS_EN0_ALIGN                         0
#define SGMII_BLK1_LANEPRBS_PRBS_EN0_BITS                          1
#define SGMII_BLK1_LANEPRBS_PRBS_EN0_SHIFT                         3

/* SGMII_Blk1 :: lanePrbs :: prbs_inv0 [02:02] */
#define Wr_SGMII_Blk1_lanePrbs_prbs_inv0(x) WriteRegBits16(SGMII_BLK1_LANEPRBS,0x4,2,x)
#define Rd_SGMII_Blk1_lanePrbs_prbs_inv0(x) ReadRegBits16(SGMII_BLK1_LANEPRBS,0x4,2)
#define SGMII_BLK1_LANEPRBS_PRBS_INV0_MASK                         0x0004
#define SGMII_BLK1_LANEPRBS_PRBS_INV0_ALIGN                        0
#define SGMII_BLK1_LANEPRBS_PRBS_INV0_BITS                         1
#define SGMII_BLK1_LANEPRBS_PRBS_INV0_SHIFT                        2

/* SGMII_Blk1 :: lanePrbs :: prbs_order0 [01:00] */
#define Wr_SGMII_Blk1_lanePrbs_prbs_order0(x) WriteRegBits16(SGMII_BLK1_LANEPRBS,0x3,0,x)
#define Rd_SGMII_Blk1_lanePrbs_prbs_order0(x) ReadRegBits16(SGMII_BLK1_LANEPRBS,0x3,0)
#define SGMII_BLK1_LANEPRBS_PRBS_ORDER0_MASK                       0x0003
#define SGMII_BLK1_LANEPRBS_PRBS_ORDER0_ALIGN                      0
#define SGMII_BLK1_LANEPRBS_PRBS_ORDER0_BITS                       2
#define SGMII_BLK1_LANEPRBS_PRBS_ORDER0_SHIFT                      0
#define SGMII_BLK1_LANEPRBS_PRBS_ORDER0_prbs7                      0
#define SGMII_BLK1_LANEPRBS_PRBS_ORDER0_prbs15                     1
#define SGMII_BLK1_LANEPRBS_PRBS_ORDER0_prbs23                     2
#define SGMII_BLK1_LANEPRBS_PRBS_ORDER0_prbs31                     3


/****************************************************************************
 * SGMII_Blk1 :: laneTest
 ***************************************************************************/
/* SGMII_Blk1 :: laneTest :: tmux_sel [15:12] */
#define Wr_SGMII_Blk1_laneTest_tmux_sel(x) WriteRegBits16(SGMII_BLK1_LANETEST,0xf000,12,x)
#define Rd_SGMII_Blk1_laneTest_tmux_sel(x) ReadRegBits16(SGMII_BLK1_LANETEST,0xf000,12)
#define SGMII_BLK1_LANETEST_TMUX_SEL_MASK                          0xf000
#define SGMII_BLK1_LANETEST_TMUX_SEL_ALIGN                         0
#define SGMII_BLK1_LANETEST_TMUX_SEL_BITS                          4
#define SGMII_BLK1_LANETEST_TMUX_SEL_SHIFT                         12
#define SGMII_BLK1_LANETEST_TMUX_SEL_off                           0
#define SGMII_BLK1_LANETEST_TMUX_SEL_rx_ln0                        1
#define SGMII_BLK1_LANETEST_TMUX_SEL_rx_ln1                        2
#define SGMII_BLK1_LANETEST_TMUX_SEL_rx_ln2                        3
#define SGMII_BLK1_LANETEST_TMUX_SEL_rx_ln3                        4
#define SGMII_BLK1_LANETEST_TMUX_SEL_tx_ln0                        5
#define SGMII_BLK1_LANETEST_TMUX_SEL_tx_ln1                        6
#define SGMII_BLK1_LANETEST_TMUX_SEL_tx_ln2                        7
#define SGMII_BLK1_LANETEST_TMUX_SEL_tx_ln3                        8
#define SGMII_BLK1_LANETEST_TMUX_SEL_pll                           11
#define SGMII_BLK1_LANETEST_TMUX_SEL_mdio                          12
#define SGMII_BLK1_LANETEST_TMUX_SEL_tMux1G                        15

/* SGMII_Blk1 :: laneTest :: reserved0 [11:11] */
#define SGMII_BLK1_LANETEST_RESERVED0_MASK                         0x0800
#define SGMII_BLK1_LANETEST_RESERVED0_ALIGN                        0
#define SGMII_BLK1_LANETEST_RESERVED0_BITS                         1
#define SGMII_BLK1_LANETEST_RESERVED0_SHIFT                        11

/* SGMII_Blk1 :: laneTest :: pwrdn_ext_dis [10:10] */
#define Wr_SGMII_Blk1_laneTest_pwrdn_ext_dis(x) WriteRegBits16(SGMII_BLK1_LANETEST,0x400,10,x)
#define Rd_SGMII_Blk1_laneTest_pwrdn_ext_dis(x) ReadRegBits16(SGMII_BLK1_LANETEST,0x400,10)
#define SGMII_BLK1_LANETEST_PWRDN_EXT_DIS_MASK                     0x0400
#define SGMII_BLK1_LANETEST_PWRDN_EXT_DIS_ALIGN                    0
#define SGMII_BLK1_LANETEST_PWRDN_EXT_DIS_BITS                     1
#define SGMII_BLK1_LANETEST_PWRDN_EXT_DIS_SHIFT                    10

/* SGMII_Blk1 :: laneTest :: pwrdn_safe_dis [09:09] */
#define Wr_SGMII_Blk1_laneTest_pwrdn_safe_dis(x) WriteRegBits16(SGMII_BLK1_LANETEST,0x200,9,x)
#define Rd_SGMII_Blk1_laneTest_pwrdn_safe_dis(x) ReadRegBits16(SGMII_BLK1_LANETEST,0x200,9)
#define SGMII_BLK1_LANETEST_PWRDN_SAFE_DIS_MASK                    0x0200
#define SGMII_BLK1_LANETEST_PWRDN_SAFE_DIS_ALIGN                   0
#define SGMII_BLK1_LANETEST_PWRDN_SAFE_DIS_BITS                    1
#define SGMII_BLK1_LANETEST_PWRDN_SAFE_DIS_SHIFT                   9

/* SGMII_Blk1 :: laneTest :: pwrdwn_clks_en [08:08] */
#define Wr_SGMII_Blk1_laneTest_pwrdwn_clks_en(x) WriteRegBits16(SGMII_BLK1_LANETEST,0x100,8,x)
#define Rd_SGMII_Blk1_laneTest_pwrdwn_clks_en(x) ReadRegBits16(SGMII_BLK1_LANETEST,0x100,8)
#define SGMII_BLK1_LANETEST_PWRDWN_CLKS_EN_MASK                    0x0100
#define SGMII_BLK1_LANETEST_PWRDWN_CLKS_EN_ALIGN                   0
#define SGMII_BLK1_LANETEST_PWRDWN_CLKS_EN_BITS                    1
#define SGMII_BLK1_LANETEST_PWRDWN_CLKS_EN_SHIFT                   8

/* SGMII_Blk1 :: laneTest :: rxSeqStart_ext_dis [07:07] */
#define Wr_SGMII_Blk1_laneTest_rxSeqStart_ext_dis(x) WriteRegBits16(SGMII_BLK1_LANETEST,0x80,7,x)
#define Rd_SGMII_Blk1_laneTest_rxSeqStart_ext_dis(x) ReadRegBits16(SGMII_BLK1_LANETEST,0x80,7)
#define SGMII_BLK1_LANETEST_RXSEQSTART_EXT_DIS_MASK                0x0080
#define SGMII_BLK1_LANETEST_RXSEQSTART_EXT_DIS_ALIGN               0
#define SGMII_BLK1_LANETEST_RXSEQSTART_EXT_DIS_BITS                1
#define SGMII_BLK1_LANETEST_RXSEQSTART_EXT_DIS_SHIFT               7

/* SGMII_Blk1 :: laneTest :: pll_lock_rstb_r [06:06] */
#define Wr_SGMII_Blk1_laneTest_pll_lock_rstb_r(x) WriteRegBits16(SGMII_BLK1_LANETEST,0x40,6,x)
#define Rd_SGMII_Blk1_laneTest_pll_lock_rstb_r(x) ReadRegBits16(SGMII_BLK1_LANETEST,0x40,6)
#define SGMII_BLK1_LANETEST_PLL_LOCK_RSTB_R_MASK                   0x0040
#define SGMII_BLK1_LANETEST_PLL_LOCK_RSTB_R_ALIGN                  0
#define SGMII_BLK1_LANETEST_PLL_LOCK_RSTB_R_BITS                   1
#define SGMII_BLK1_LANETEST_PLL_LOCK_RSTB_R_SHIFT                  6

/* SGMII_Blk1 :: laneTest :: lfck_bypass [05:05] */
#define Wr_SGMII_Blk1_laneTest_lfck_bypass(x) WriteRegBits16(SGMII_BLK1_LANETEST,0x20,5,x)
#define Rd_SGMII_Blk1_laneTest_lfck_bypass(x) ReadRegBits16(SGMII_BLK1_LANETEST,0x20,5)
#define SGMII_BLK1_LANETEST_LFCK_BYPASS_MASK                       0x0020
#define SGMII_BLK1_LANETEST_LFCK_BYPASS_ALIGN                      0
#define SGMII_BLK1_LANETEST_LFCK_BYPASS_BITS                       1
#define SGMII_BLK1_LANETEST_LFCK_BYPASS_SHIFT                      5

/* SGMII_Blk1 :: laneTest :: reserved1 [04:00] */
#define SGMII_BLK1_LANETEST_RESERVED1_MASK                         0x001f
#define SGMII_BLK1_LANETEST_RESERVED1_ALIGN                        0
#define SGMII_BLK1_LANETEST_RESERVED1_BITS                         5
#define SGMII_BLK1_LANETEST_RESERVED1_SHIFT                        0


/****************************************************************************
 * SGMII_Blk1 :: BlockAddress
 ***************************************************************************/
/* SGMII_Blk1 :: BlockAddress :: reserved0 [15:15] */
#define SGMII_BLK1_BLOCKADDRESS_RESERVED0_MASK                     0x8000
#define SGMII_BLK1_BLOCKADDRESS_RESERVED0_ALIGN                    0
#define SGMII_BLK1_BLOCKADDRESS_RESERVED0_BITS                     1
#define SGMII_BLK1_BLOCKADDRESS_RESERVED0_SHIFT                    15

/* SGMII_Blk1 :: BlockAddress :: BlockAddress [14:04] */
#define Wr_SGMII_Blk1_BlockAddress_BlockAddress(x) WriteRegBits16(SGMII_BLK1_BLOCKADDRESS,0x7ff0,4,x)
#define Rd_SGMII_Blk1_BlockAddress_BlockAddress(x) ReadRegBits16(SGMII_BLK1_BLOCKADDRESS,0x7ff0,4)
#define SGMII_BLK1_BLOCKADDRESS_BLOCKADDRESS_MASK                  0x7ff0
#define SGMII_BLK1_BLOCKADDRESS_BLOCKADDRESS_ALIGN                 0
#define SGMII_BLK1_BLOCKADDRESS_BLOCKADDRESS_BITS                  11
#define SGMII_BLK1_BLOCKADDRESS_BLOCKADDRESS_SHIFT                 4

/* SGMII_Blk1 :: BlockAddress :: reserved1 [03:00] */
#define SGMII_BLK1_BLOCKADDRESS_RESERVED1_MASK                     0x000f
#define SGMII_BLK1_BLOCKADDRESS_RESERVED1_ALIGN                    0
#define SGMII_BLK1_BLOCKADDRESS_RESERVED1_BITS                     4
#define SGMII_BLK1_BLOCKADDRESS_RESERVED1_SHIFT                    0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_PLL_afe
 ***************************************************************************/
/****************************************************************************
 * SGMII_PLL_afe :: ctrl0
 ***************************************************************************/
/* SGMII_PLL_afe :: ctrl0 :: en_test_integer_clk [15:15] */
#define Wr_SGMII_PLL_afe_ctrl0_en_test_integer_clk(x) WriteRegBits16(SGMII_PLL_AFE_CTRL0,0x8000,15,x)
#define Rd_SGMII_PLL_afe_ctrl0_en_test_integer_clk(x) ReadRegBits16(SGMII_PLL_AFE_CTRL0,0x8000,15)
#define SGMII_PLL_AFE_CTRL0_EN_TEST_INTEGER_CLK_MASK               0x8000
#define SGMII_PLL_AFE_CTRL0_EN_TEST_INTEGER_CLK_ALIGN              0
#define SGMII_PLL_AFE_CTRL0_EN_TEST_INTEGER_CLK_BITS               1
#define SGMII_PLL_AFE_CTRL0_EN_TEST_INTEGER_CLK_SHIFT              15

/* SGMII_PLL_afe :: ctrl0 :: xtal_bias [14:12] */
#define Wr_SGMII_PLL_afe_ctrl0_xtal_bias(x) WriteRegBits16(SGMII_PLL_AFE_CTRL0,0x7000,12,x)
#define Rd_SGMII_PLL_afe_ctrl0_xtal_bias(x) ReadRegBits16(SGMII_PLL_AFE_CTRL0,0x7000,12)
#define SGMII_PLL_AFE_CTRL0_XTAL_BIAS_MASK                         0x7000
#define SGMII_PLL_AFE_CTRL0_XTAL_BIAS_ALIGN                        0
#define SGMII_PLL_AFE_CTRL0_XTAL_BIAS_BITS                         3
#define SGMII_PLL_AFE_CTRL0_XTAL_BIAS_SHIFT                        12

/* SGMII_PLL_afe :: ctrl0 :: cpar [11:10] */
#define Wr_SGMII_PLL_afe_ctrl0_cpar(x) WriteRegBits16(SGMII_PLL_AFE_CTRL0,0xc00,10,x)
#define Rd_SGMII_PLL_afe_ctrl0_cpar(x) ReadRegBits16(SGMII_PLL_AFE_CTRL0,0xc00,10)
#define SGMII_PLL_AFE_CTRL0_CPAR_MASK                              0x0c00
#define SGMII_PLL_AFE_CTRL0_CPAR_ALIGN                             0
#define SGMII_PLL_AFE_CTRL0_CPAR_BITS                              2
#define SGMII_PLL_AFE_CTRL0_CPAR_SHIFT                             10

/* SGMII_PLL_afe :: ctrl0 :: rpar [09:06] */
#define Wr_SGMII_PLL_afe_ctrl0_rpar(x) WriteRegBits16(SGMII_PLL_AFE_CTRL0,0x3c0,6,x)
#define Rd_SGMII_PLL_afe_ctrl0_rpar(x) ReadRegBits16(SGMII_PLL_AFE_CTRL0,0x3c0,6)
#define SGMII_PLL_AFE_CTRL0_RPAR_MASK                              0x03c0
#define SGMII_PLL_AFE_CTRL0_RPAR_ALIGN                             0
#define SGMII_PLL_AFE_CTRL0_RPAR_BITS                              4
#define SGMII_PLL_AFE_CTRL0_RPAR_SHIFT                             6

/* SGMII_PLL_afe :: ctrl0 :: curr_sel [05:02] */
#define Wr_SGMII_PLL_afe_ctrl0_curr_sel(x) WriteRegBits16(SGMII_PLL_AFE_CTRL0,0x3c,2,x)
#define Rd_SGMII_PLL_afe_ctrl0_curr_sel(x) ReadRegBits16(SGMII_PLL_AFE_CTRL0,0x3c,2)
#define SGMII_PLL_AFE_CTRL0_CURR_SEL_MASK                          0x003c
#define SGMII_PLL_AFE_CTRL0_CURR_SEL_ALIGN                         0
#define SGMII_PLL_AFE_CTRL0_CURR_SEL_BITS                          4
#define SGMII_PLL_AFE_CTRL0_CURR_SEL_SHIFT                         2

/* SGMII_PLL_afe :: ctrl0 :: hipass [01:01] */
#define Wr_SGMII_PLL_afe_ctrl0_hipass(x) WriteRegBits16(SGMII_PLL_AFE_CTRL0,0x2,1,x)
#define Rd_SGMII_PLL_afe_ctrl0_hipass(x) ReadRegBits16(SGMII_PLL_AFE_CTRL0,0x2,1)
#define SGMII_PLL_AFE_CTRL0_HIPASS_MASK                            0x0002
#define SGMII_PLL_AFE_CTRL0_HIPASS_ALIGN                           0
#define SGMII_PLL_AFE_CTRL0_HIPASS_BITS                            1
#define SGMII_PLL_AFE_CTRL0_HIPASS_SHIFT                           1

/* SGMII_PLL_afe :: ctrl0 :: CM_sel [00:00] */
#define Wr_SGMII_PLL_afe_ctrl0_CM_sel(x) WriteRegBits16(SGMII_PLL_AFE_CTRL0,0x1,0,x)
#define Rd_SGMII_PLL_afe_ctrl0_CM_sel(x) ReadRegBits16(SGMII_PLL_AFE_CTRL0,0x1,0)
#define SGMII_PLL_AFE_CTRL0_CM_SEL_MASK                            0x0001
#define SGMII_PLL_AFE_CTRL0_CM_SEL_ALIGN                           0
#define SGMII_PLL_AFE_CTRL0_CM_SEL_BITS                            1
#define SGMII_PLL_AFE_CTRL0_CM_SEL_SHIFT                           0


/****************************************************************************
 * SGMII_PLL_afe :: ctrl1
 ***************************************************************************/
/* SGMII_PLL_afe :: ctrl1 :: reserved_31_28 [15:12] */
#define SGMII_PLL_AFE_CTRL1_RESERVED_31_28_MASK                    0xf000
#define SGMII_PLL_AFE_CTRL1_RESERVED_31_28_ALIGN                   0
#define SGMII_PLL_AFE_CTRL1_RESERVED_31_28_BITS                    4
#define SGMII_PLL_AFE_CTRL1_RESERVED_31_28_SHIFT                   12

/* SGMII_PLL_afe :: ctrl1 :: leakage_test [11:10] */
#define Wr_SGMII_PLL_afe_ctrl1_leakage_test(x) WriteRegBits16(SGMII_PLL_AFE_CTRL1,0xc00,10,x)
#define Rd_SGMII_PLL_afe_ctrl1_leakage_test(x) ReadRegBits16(SGMII_PLL_AFE_CTRL1,0xc00,10)
#define SGMII_PLL_AFE_CTRL1_LEAKAGE_TEST_MASK                      0x0c00
#define SGMII_PLL_AFE_CTRL1_LEAKAGE_TEST_ALIGN                     0
#define SGMII_PLL_AFE_CTRL1_LEAKAGE_TEST_BITS                      2
#define SGMII_PLL_AFE_CTRL1_LEAKAGE_TEST_SHIFT                     10

/* SGMII_PLL_afe :: ctrl1 :: PLL_pon [09:06] */
#define Wr_SGMII_PLL_afe_ctrl1_PLL_pon(x) WriteRegBits16(SGMII_PLL_AFE_CTRL1,0x3c0,6,x)
#define Rd_SGMII_PLL_afe_ctrl1_PLL_pon(x) ReadRegBits16(SGMII_PLL_AFE_CTRL1,0x3c0,6)
#define SGMII_PLL_AFE_CTRL1_PLL_PON_MASK                           0x03c0
#define SGMII_PLL_AFE_CTRL1_PLL_PON_ALIGN                          0
#define SGMII_PLL_AFE_CTRL1_PLL_PON_BITS                           4
#define SGMII_PLL_AFE_CTRL1_PLL_PON_SHIFT                          6

/* SGMII_PLL_afe :: ctrl1 :: xtal_core_bias [05:02] */
#define Wr_SGMII_PLL_afe_ctrl1_xtal_core_bias(x) WriteRegBits16(SGMII_PLL_AFE_CTRL1,0x3c,2,x)
#define Rd_SGMII_PLL_afe_ctrl1_xtal_core_bias(x) ReadRegBits16(SGMII_PLL_AFE_CTRL1,0x3c,2)
#define SGMII_PLL_AFE_CTRL1_XTAL_CORE_BIAS_MASK                    0x003c
#define SGMII_PLL_AFE_CTRL1_XTAL_CORE_BIAS_ALIGN                   0
#define SGMII_PLL_AFE_CTRL1_XTAL_CORE_BIAS_BITS                    4
#define SGMII_PLL_AFE_CTRL1_XTAL_CORE_BIAS_SHIFT                   2

/* SGMII_PLL_afe :: ctrl1 :: lv_en [01:01] */
#define Wr_SGMII_PLL_afe_ctrl1_lv_en(x) WriteRegBits16(SGMII_PLL_AFE_CTRL1,0x2,1,x)
#define Rd_SGMII_PLL_afe_ctrl1_lv_en(x) ReadRegBits16(SGMII_PLL_AFE_CTRL1,0x2,1)
#define SGMII_PLL_AFE_CTRL1_LV_EN_MASK                             0x0002
#define SGMII_PLL_AFE_CTRL1_LV_EN_ALIGN                            0
#define SGMII_PLL_AFE_CTRL1_LV_EN_BITS                             1
#define SGMII_PLL_AFE_CTRL1_LV_EN_SHIFT                            1

/* SGMII_PLL_afe :: ctrl1 :: en_test_frac_clk [00:00] */
#define Wr_SGMII_PLL_afe_ctrl1_en_test_frac_clk(x) WriteRegBits16(SGMII_PLL_AFE_CTRL1,0x1,0,x)
#define Rd_SGMII_PLL_afe_ctrl1_en_test_frac_clk(x) ReadRegBits16(SGMII_PLL_AFE_CTRL1,0x1,0)
#define SGMII_PLL_AFE_CTRL1_EN_TEST_FRAC_CLK_MASK                  0x0001
#define SGMII_PLL_AFE_CTRL1_EN_TEST_FRAC_CLK_ALIGN                 0
#define SGMII_PLL_AFE_CTRL1_EN_TEST_FRAC_CLK_BITS                  1
#define SGMII_PLL_AFE_CTRL1_EN_TEST_FRAC_CLK_SHIFT                 0


/****************************************************************************
 * SGMII_PLL_afe :: ctrl2
 ***************************************************************************/
/* SGMII_PLL_afe :: ctrl2 :: i_pll_frac_mode [15:14] */
#define Wr_SGMII_PLL_afe_ctrl2_i_pll_frac_mode(x) WriteRegBits16(SGMII_PLL_AFE_CTRL2,0xc000,14,x)
#define Rd_SGMII_PLL_afe_ctrl2_i_pll_frac_mode(x) ReadRegBits16(SGMII_PLL_AFE_CTRL2,0xc000,14)
#define SGMII_PLL_AFE_CTRL2_I_PLL_FRAC_MODE_MASK                   0xc000
#define SGMII_PLL_AFE_CTRL2_I_PLL_FRAC_MODE_ALIGN                  0
#define SGMII_PLL_AFE_CTRL2_I_PLL_FRAC_MODE_BITS                   2
#define SGMII_PLL_AFE_CTRL2_I_PLL_FRAC_MODE_SHIFT                  14

/* SGMII_PLL_afe :: ctrl2 :: vco_ictr [13:11] */
#define Wr_SGMII_PLL_afe_ctrl2_vco_ictr(x) WriteRegBits16(SGMII_PLL_AFE_CTRL2,0x3800,11,x)
#define Rd_SGMII_PLL_afe_ctrl2_vco_ictr(x) ReadRegBits16(SGMII_PLL_AFE_CTRL2,0x3800,11)
#define SGMII_PLL_AFE_CTRL2_VCO_ICTR_MASK                          0x3800
#define SGMII_PLL_AFE_CTRL2_VCO_ICTR_ALIGN                         0
#define SGMII_PLL_AFE_CTRL2_VCO_ICTR_BITS                          3
#define SGMII_PLL_AFE_CTRL2_VCO_ICTR_SHIFT                         11

/* SGMII_PLL_afe :: ctrl2 :: test_pll_mode [10:10] */
#define Wr_SGMII_PLL_afe_ctrl2_test_pll_mode(x) WriteRegBits16(SGMII_PLL_AFE_CTRL2,0x400,10,x)
#define Rd_SGMII_PLL_afe_ctrl2_test_pll_mode(x) ReadRegBits16(SGMII_PLL_AFE_CTRL2,0x400,10)
#define SGMII_PLL_AFE_CTRL2_TEST_PLL_MODE_MASK                     0x0400
#define SGMII_PLL_AFE_CTRL2_TEST_PLL_MODE_ALIGN                    0
#define SGMII_PLL_AFE_CTRL2_TEST_PLL_MODE_BITS                     1
#define SGMII_PLL_AFE_CTRL2_TEST_PLL_MODE_SHIFT                    10

/* SGMII_PLL_afe :: ctrl2 :: reserved_41 [09:09] */
#define SGMII_PLL_AFE_CTRL2_RESERVED_41_MASK                       0x0200
#define SGMII_PLL_AFE_CTRL2_RESERVED_41_ALIGN                      0
#define SGMII_PLL_AFE_CTRL2_RESERVED_41_BITS                       1
#define SGMII_PLL_AFE_CTRL2_RESERVED_41_SHIFT                      9

/* SGMII_PLL_afe :: ctrl2 :: test_amp [08:05] */
#define Wr_SGMII_PLL_afe_ctrl2_test_amp(x) WriteRegBits16(SGMII_PLL_AFE_CTRL2,0x1e0,5,x)
#define Rd_SGMII_PLL_afe_ctrl2_test_amp(x) ReadRegBits16(SGMII_PLL_AFE_CTRL2,0x1e0,5)
#define SGMII_PLL_AFE_CTRL2_TEST_AMP_MASK                          0x01e0
#define SGMII_PLL_AFE_CTRL2_TEST_AMP_ALIGN                         0
#define SGMII_PLL_AFE_CTRL2_TEST_AMP_BITS                          4
#define SGMII_PLL_AFE_CTRL2_TEST_AMP_SHIFT                         5

/* SGMII_PLL_afe :: ctrl2 :: intN_fb_en [04:04] */
#define Wr_SGMII_PLL_afe_ctrl2_intN_fb_en(x) WriteRegBits16(SGMII_PLL_AFE_CTRL2,0x10,4,x)
#define Rd_SGMII_PLL_afe_ctrl2_intN_fb_en(x) ReadRegBits16(SGMII_PLL_AFE_CTRL2,0x10,4)
#define SGMII_PLL_AFE_CTRL2_INTN_FB_EN_MASK                        0x0010
#define SGMII_PLL_AFE_CTRL2_INTN_FB_EN_ALIGN                       0
#define SGMII_PLL_AFE_CTRL2_INTN_FB_EN_BITS                        1
#define SGMII_PLL_AFE_CTRL2_INTN_FB_EN_SHIFT                       4

/* SGMII_PLL_afe :: ctrl2 :: en10T [03:03] */
#define Wr_SGMII_PLL_afe_ctrl2_en10T(x) WriteRegBits16(SGMII_PLL_AFE_CTRL2,0x8,3,x)
#define Rd_SGMII_PLL_afe_ctrl2_en10T(x) ReadRegBits16(SGMII_PLL_AFE_CTRL2,0x8,3)
#define SGMII_PLL_AFE_CTRL2_EN10T_MASK                             0x0008
#define SGMII_PLL_AFE_CTRL2_EN10T_ALIGN                            0
#define SGMII_PLL_AFE_CTRL2_EN10T_BITS                             1
#define SGMII_PLL_AFE_CTRL2_EN10T_SHIFT                            3

/* SGMII_PLL_afe :: ctrl2 :: test_vc [02:02] */
#define Wr_SGMII_PLL_afe_ctrl2_test_vc(x) WriteRegBits16(SGMII_PLL_AFE_CTRL2,0x4,2,x)
#define Rd_SGMII_PLL_afe_ctrl2_test_vc(x) ReadRegBits16(SGMII_PLL_AFE_CTRL2,0x4,2)
#define SGMII_PLL_AFE_CTRL2_TEST_VC_MASK                           0x0004
#define SGMII_PLL_AFE_CTRL2_TEST_VC_ALIGN                          0
#define SGMII_PLL_AFE_CTRL2_TEST_VC_BITS                           1
#define SGMII_PLL_AFE_CTRL2_TEST_VC_SHIFT                          2

/* SGMII_PLL_afe :: ctrl2 :: reserved_33_32 [01:00] */
#define SGMII_PLL_AFE_CTRL2_RESERVED_33_32_MASK                    0x0003
#define SGMII_PLL_AFE_CTRL2_RESERVED_33_32_ALIGN                   0
#define SGMII_PLL_AFE_CTRL2_RESERVED_33_32_BITS                    2
#define SGMII_PLL_AFE_CTRL2_RESERVED_33_32_SHIFT                   0


/****************************************************************************
 * SGMII_PLL_afe :: ctrl3
 ***************************************************************************/
/* SGMII_PLL_afe :: ctrl3 :: pll_mode [15:15] */
#define Wr_SGMII_PLL_afe_ctrl3_pll_mode(x) WriteRegBits16(SGMII_PLL_AFE_CTRL3,0x8000,15,x)
#define Rd_SGMII_PLL_afe_ctrl3_pll_mode(x) ReadRegBits16(SGMII_PLL_AFE_CTRL3,0x8000,15)
#define SGMII_PLL_AFE_CTRL3_PLL_MODE_MASK                          0x8000
#define SGMII_PLL_AFE_CTRL3_PLL_MODE_ALIGN                         0
#define SGMII_PLL_AFE_CTRL3_PLL_MODE_BITS                          1
#define SGMII_PLL_AFE_CTRL3_PLL_MODE_SHIFT                         15

/* SGMII_PLL_afe :: ctrl3 :: refclk_in_bias [14:09] */
#define Wr_SGMII_PLL_afe_ctrl3_refclk_in_bias(x) WriteRegBits16(SGMII_PLL_AFE_CTRL3,0x7e00,9,x)
#define Rd_SGMII_PLL_afe_ctrl3_refclk_in_bias(x) ReadRegBits16(SGMII_PLL_AFE_CTRL3,0x7e00,9)
#define SGMII_PLL_AFE_CTRL3_REFCLK_IN_BIAS_MASK                    0x7e00
#define SGMII_PLL_AFE_CTRL3_REFCLK_IN_BIAS_ALIGN                   0
#define SGMII_PLL_AFE_CTRL3_REFCLK_IN_BIAS_BITS                    6
#define SGMII_PLL_AFE_CTRL3_REFCLK_IN_BIAS_SHIFT                   9

/* SGMII_PLL_afe :: ctrl3 :: int_div_en [08:08] */
#define Wr_SGMII_PLL_afe_ctrl3_int_div_en(x) WriteRegBits16(SGMII_PLL_AFE_CTRL3,0x100,8,x)
#define Rd_SGMII_PLL_afe_ctrl3_int_div_en(x) ReadRegBits16(SGMII_PLL_AFE_CTRL3,0x100,8)
#define SGMII_PLL_AFE_CTRL3_INT_DIV_EN_MASK                        0x0100
#define SGMII_PLL_AFE_CTRL3_INT_DIV_EN_ALIGN                       0
#define SGMII_PLL_AFE_CTRL3_INT_DIV_EN_BITS                        1
#define SGMII_PLL_AFE_CTRL3_INT_DIV_EN_SHIFT                       8

/* SGMII_PLL_afe :: ctrl3 :: mmd_en [07:07] */
#define Wr_SGMII_PLL_afe_ctrl3_mmd_en(x) WriteRegBits16(SGMII_PLL_AFE_CTRL3,0x80,7,x)
#define Rd_SGMII_PLL_afe_ctrl3_mmd_en(x) ReadRegBits16(SGMII_PLL_AFE_CTRL3,0x80,7)
#define SGMII_PLL_AFE_CTRL3_MMD_EN_MASK                            0x0080
#define SGMII_PLL_AFE_CTRL3_MMD_EN_ALIGN                           0
#define SGMII_PLL_AFE_CTRL3_MMD_EN_BITS                            1
#define SGMII_PLL_AFE_CTRL3_MMD_EN_SHIFT                           7

/* SGMII_PLL_afe :: ctrl3 :: test_sel [06:04] */
#define Wr_SGMII_PLL_afe_ctrl3_test_sel(x) WriteRegBits16(SGMII_PLL_AFE_CTRL3,0x70,4,x)
#define Rd_SGMII_PLL_afe_ctrl3_test_sel(x) ReadRegBits16(SGMII_PLL_AFE_CTRL3,0x70,4)
#define SGMII_PLL_AFE_CTRL3_TEST_SEL_MASK                          0x0070
#define SGMII_PLL_AFE_CTRL3_TEST_SEL_ALIGN                         0
#define SGMII_PLL_AFE_CTRL3_TEST_SEL_BITS                          3
#define SGMII_PLL_AFE_CTRL3_TEST_SEL_SHIFT                         4

/* SGMII_PLL_afe :: ctrl3 :: testclk_en [03:03] */
#define Wr_SGMII_PLL_afe_ctrl3_testclk_en(x) WriteRegBits16(SGMII_PLL_AFE_CTRL3,0x8,3,x)
#define Rd_SGMII_PLL_afe_ctrl3_testclk_en(x) ReadRegBits16(SGMII_PLL_AFE_CTRL3,0x8,3)
#define SGMII_PLL_AFE_CTRL3_TESTCLK_EN_MASK                        0x0008
#define SGMII_PLL_AFE_CTRL3_TESTCLK_EN_ALIGN                       0
#define SGMII_PLL_AFE_CTRL3_TESTCLK_EN_BITS                        1
#define SGMII_PLL_AFE_CTRL3_TESTCLK_EN_SHIFT                       3

/* SGMII_PLL_afe :: ctrl3 :: tcest_neg [02:00] */
#define Wr_SGMII_PLL_afe_ctrl3_tcest_neg(x) WriteRegBits16(SGMII_PLL_AFE_CTRL3,0x7,0,x)
#define Rd_SGMII_PLL_afe_ctrl3_tcest_neg(x) ReadRegBits16(SGMII_PLL_AFE_CTRL3,0x7,0)
#define SGMII_PLL_AFE_CTRL3_TCEST_NEG_MASK                         0x0007
#define SGMII_PLL_AFE_CTRL3_TCEST_NEG_ALIGN                        0
#define SGMII_PLL_AFE_CTRL3_TCEST_NEG_BITS                         3
#define SGMII_PLL_AFE_CTRL3_TCEST_NEG_SHIFT                        0


/****************************************************************************
 * SGMII_PLL_afe :: ctrl4
 ***************************************************************************/
/* SGMII_PLL_afe :: ctrl4 :: mmd_prsc8or9pwdb [15:15] */
#define Wr_SGMII_PLL_afe_ctrl4_mmd_prsc8or9pwdb(x) WriteRegBits16(SGMII_PLL_AFE_CTRL4,0x8000,15,x)
#define Rd_SGMII_PLL_afe_ctrl4_mmd_prsc8or9pwdb(x) ReadRegBits16(SGMII_PLL_AFE_CTRL4,0x8000,15)
#define SGMII_PLL_AFE_CTRL4_MMD_PRSC8OR9PWDB_MASK                  0x8000
#define SGMII_PLL_AFE_CTRL4_MMD_PRSC8OR9PWDB_ALIGN                 0
#define SGMII_PLL_AFE_CTRL4_MMD_PRSC8OR9PWDB_BITS                  1
#define SGMII_PLL_AFE_CTRL4_MMD_PRSC8OR9PWDB_SHIFT                 15

/* SGMII_PLL_afe :: ctrl4 :: adj [14:12] */
#define Wr_SGMII_PLL_afe_ctrl4_adj(x) WriteRegBits16(SGMII_PLL_AFE_CTRL4,0x7000,12,x)
#define Rd_SGMII_PLL_afe_ctrl4_adj(x) ReadRegBits16(SGMII_PLL_AFE_CTRL4,0x7000,12)
#define SGMII_PLL_AFE_CTRL4_ADJ_MASK                               0x7000
#define SGMII_PLL_AFE_CTRL4_ADJ_ALIGN                              0
#define SGMII_PLL_AFE_CTRL4_ADJ_BITS                               3
#define SGMII_PLL_AFE_CTRL4_ADJ_SHIFT                              12

/* SGMII_PLL_afe :: ctrl4 :: mmd_resetb [11:11] */
#define Wr_SGMII_PLL_afe_ctrl4_mmd_resetb(x) WriteRegBits16(SGMII_PLL_AFE_CTRL4,0x800,11,x)
#define Rd_SGMII_PLL_afe_ctrl4_mmd_resetb(x) ReadRegBits16(SGMII_PLL_AFE_CTRL4,0x800,11)
#define SGMII_PLL_AFE_CTRL4_MMD_RESETB_MASK                        0x0800
#define SGMII_PLL_AFE_CTRL4_MMD_RESETB_ALIGN                       0
#define SGMII_PLL_AFE_CTRL4_MMD_RESETB_BITS                        1
#define SGMII_PLL_AFE_CTRL4_MMD_RESETB_SHIFT                       11

/* SGMII_PLL_afe :: ctrl4 :: reserved_74_71 [10:07] */
#define SGMII_PLL_AFE_CTRL4_RESERVED_74_71_MASK                    0x0780
#define SGMII_PLL_AFE_CTRL4_RESERVED_74_71_ALIGN                   0
#define SGMII_PLL_AFE_CTRL4_RESERVED_74_71_BITS                    4
#define SGMII_PLL_AFE_CTRL4_RESERVED_74_71_SHIFT                   7

/* SGMII_PLL_afe :: ctrl4 :: en_cap [06:04] */
#define Wr_SGMII_PLL_afe_ctrl4_en_cap(x) WriteRegBits16(SGMII_PLL_AFE_CTRL4,0x70,4,x)
#define Rd_SGMII_PLL_afe_ctrl4_en_cap(x) ReadRegBits16(SGMII_PLL_AFE_CTRL4,0x70,4)
#define SGMII_PLL_AFE_CTRL4_EN_CAP_MASK                            0x0070
#define SGMII_PLL_AFE_CTRL4_EN_CAP_ALIGN                           0
#define SGMII_PLL_AFE_CTRL4_EN_CAP_BITS                            3
#define SGMII_PLL_AFE_CTRL4_EN_CAP_SHIFT                           4

/* SGMII_PLL_afe :: ctrl4 :: div [03:00] */
#define Wr_SGMII_PLL_afe_ctrl4_div(x) WriteRegBits16(SGMII_PLL_AFE_CTRL4,0xf,0,x)
#define Rd_SGMII_PLL_afe_ctrl4_div(x) ReadRegBits16(SGMII_PLL_AFE_CTRL4,0xf,0)
#define SGMII_PLL_AFE_CTRL4_DIV_MASK                               0x000f
#define SGMII_PLL_AFE_CTRL4_DIV_ALIGN                              0
#define SGMII_PLL_AFE_CTRL4_DIV_BITS                               4
#define SGMII_PLL_AFE_CTRL4_DIV_SHIFT                              0


/****************************************************************************
 * SGMII_PLL_afe :: ctrl5
 ***************************************************************************/
/* SGMII_PLL_afe :: ctrl5 :: i_ndiv_frac_3_0 [15:12] */
#define Wr_SGMII_PLL_afe_ctrl5_i_ndiv_frac_3_0(x) WriteRegBits16(SGMII_PLL_AFE_CTRL5,0xf000,12,x)
#define Rd_SGMII_PLL_afe_ctrl5_i_ndiv_frac_3_0(x) ReadRegBits16(SGMII_PLL_AFE_CTRL5,0xf000,12)
#define SGMII_PLL_AFE_CTRL5_I_NDIV_FRAC_3_0_MASK                   0xf000
#define SGMII_PLL_AFE_CTRL5_I_NDIV_FRAC_3_0_ALIGN                  0
#define SGMII_PLL_AFE_CTRL5_I_NDIV_FRAC_3_0_BITS                   4
#define SGMII_PLL_AFE_CTRL5_I_NDIV_FRAC_3_0_SHIFT                  12

/* SGMII_PLL_afe :: ctrl5 :: i_pfd_offset [11:10] */
#define Wr_SGMII_PLL_afe_ctrl5_i_pfd_offset(x) WriteRegBits16(SGMII_PLL_AFE_CTRL5,0xc00,10,x)
#define Rd_SGMII_PLL_afe_ctrl5_i_pfd_offset(x) ReadRegBits16(SGMII_PLL_AFE_CTRL5,0xc00,10)
#define SGMII_PLL_AFE_CTRL5_I_PFD_OFFSET_MASK                      0x0c00
#define SGMII_PLL_AFE_CTRL5_I_PFD_OFFSET_ALIGN                     0
#define SGMII_PLL_AFE_CTRL5_I_PFD_OFFSET_BITS                      2
#define SGMII_PLL_AFE_CTRL5_I_PFD_OFFSET_SHIFT                     10

/* SGMII_PLL_afe :: ctrl5 :: Ref_doubler_en [09:09] */
#define Wr_SGMII_PLL_afe_ctrl5_Ref_doubler_en(x) WriteRegBits16(SGMII_PLL_AFE_CTRL5,0x200,9,x)
#define Rd_SGMII_PLL_afe_ctrl5_Ref_doubler_en(x) ReadRegBits16(SGMII_PLL_AFE_CTRL5,0x200,9)
#define SGMII_PLL_AFE_CTRL5_REF_DOUBLER_EN_MASK                    0x0200
#define SGMII_PLL_AFE_CTRL5_REF_DOUBLER_EN_ALIGN                   0
#define SGMII_PLL_AFE_CTRL5_REF_DOUBLER_EN_BITS                    1
#define SGMII_PLL_AFE_CTRL5_REF_DOUBLER_EN_SHIFT                   9

/* SGMII_PLL_afe :: ctrl5 :: I_pfd_offset_enlarge [08:08] */
#define Wr_SGMII_PLL_afe_ctrl5_I_pfd_offset_enlarge(x) WriteRegBits16(SGMII_PLL_AFE_CTRL5,0x100,8,x)
#define Rd_SGMII_PLL_afe_ctrl5_I_pfd_offset_enlarge(x) ReadRegBits16(SGMII_PLL_AFE_CTRL5,0x100,8)
#define SGMII_PLL_AFE_CTRL5_I_PFD_OFFSET_ENLARGE_MASK              0x0100
#define SGMII_PLL_AFE_CTRL5_I_PFD_OFFSET_ENLARGE_ALIGN             0
#define SGMII_PLL_AFE_CTRL5_I_PFD_OFFSET_ENLARGE_BITS              1
#define SGMII_PLL_AFE_CTRL5_I_PFD_OFFSET_ENLARGE_SHIFT             8

/* SGMII_PLL_afe :: ctrl5 :: en_cur [07:05] */
#define Wr_SGMII_PLL_afe_ctrl5_en_cur(x) WriteRegBits16(SGMII_PLL_AFE_CTRL5,0xe0,5,x)
#define Rd_SGMII_PLL_afe_ctrl5_en_cur(x) ReadRegBits16(SGMII_PLL_AFE_CTRL5,0xe0,5)
#define SGMII_PLL_AFE_CTRL5_EN_CUR_MASK                            0x00e0
#define SGMII_PLL_AFE_CTRL5_EN_CUR_ALIGN                           0
#define SGMII_PLL_AFE_CTRL5_EN_CUR_BITS                            3
#define SGMII_PLL_AFE_CTRL5_EN_CUR_SHIFT                           5

/* SGMII_PLL_afe :: ctrl5 :: reserved_84 [04:04] */
#define SGMII_PLL_AFE_CTRL5_RESERVED_84_MASK                       0x0010
#define SGMII_PLL_AFE_CTRL5_RESERVED_84_ALIGN                      0
#define SGMII_PLL_AFE_CTRL5_RESERVED_84_BITS                       1
#define SGMII_PLL_AFE_CTRL5_RESERVED_84_SHIFT                      4

/* SGMII_PLL_afe :: ctrl5 :: calib_adj [03:01] */
#define Wr_SGMII_PLL_afe_ctrl5_calib_adj(x) WriteRegBits16(SGMII_PLL_AFE_CTRL5,0xe,1,x)
#define Rd_SGMII_PLL_afe_ctrl5_calib_adj(x) ReadRegBits16(SGMII_PLL_AFE_CTRL5,0xe,1)
#define SGMII_PLL_AFE_CTRL5_CALIB_ADJ_MASK                         0x000e
#define SGMII_PLL_AFE_CTRL5_CALIB_ADJ_ALIGN                        0
#define SGMII_PLL_AFE_CTRL5_CALIB_ADJ_BITS                         3
#define SGMII_PLL_AFE_CTRL5_CALIB_ADJ_SHIFT                        1

/* SGMII_PLL_afe :: ctrl5 :: mmd_prsc4or5pwdb [00:00] */
#define Wr_SGMII_PLL_afe_ctrl5_mmd_prsc4or5pwdb(x) WriteRegBits16(SGMII_PLL_AFE_CTRL5,0x1,0,x)
#define Rd_SGMII_PLL_afe_ctrl5_mmd_prsc4or5pwdb(x) ReadRegBits16(SGMII_PLL_AFE_CTRL5,0x1,0)
#define SGMII_PLL_AFE_CTRL5_MMD_PRSC4OR5PWDB_MASK                  0x0001
#define SGMII_PLL_AFE_CTRL5_MMD_PRSC4OR5PWDB_ALIGN                 0
#define SGMII_PLL_AFE_CTRL5_MMD_PRSC4OR5PWDB_BITS                  1
#define SGMII_PLL_AFE_CTRL5_MMD_PRSC4OR5PWDB_SHIFT                 0


/****************************************************************************
 * SGMII_PLL_afe :: ctrl6
 ***************************************************************************/
/* SGMII_PLL_afe :: ctrl6 :: i_ndiv_int_1_0 [15:14] */
#define Wr_SGMII_PLL_afe_ctrl6_i_ndiv_int_1_0(x) WriteRegBits16(SGMII_PLL_AFE_CTRL6,0xc000,14,x)
#define Rd_SGMII_PLL_afe_ctrl6_i_ndiv_int_1_0(x) ReadRegBits16(SGMII_PLL_AFE_CTRL6,0xc000,14)
#define SGMII_PLL_AFE_CTRL6_I_NDIV_INT_1_0_MASK                    0xc000
#define SGMII_PLL_AFE_CTRL6_I_NDIV_INT_1_0_ALIGN                   0
#define SGMII_PLL_AFE_CTRL6_I_NDIV_INT_1_0_BITS                    2
#define SGMII_PLL_AFE_CTRL6_I_NDIV_INT_1_0_SHIFT                   14

/* SGMII_PLL_afe :: ctrl6 :: i_ndiv_frac_17_4 [13:00] */
#define Wr_SGMII_PLL_afe_ctrl6_i_ndiv_frac_17_4(x) WriteRegBits16(SGMII_PLL_AFE_CTRL6,0x3fff,0,x)
#define Rd_SGMII_PLL_afe_ctrl6_i_ndiv_frac_17_4(x) ReadRegBits16(SGMII_PLL_AFE_CTRL6,0x3fff,0)
#define SGMII_PLL_AFE_CTRL6_I_NDIV_FRAC_17_4_MASK                  0x3fff
#define SGMII_PLL_AFE_CTRL6_I_NDIV_FRAC_17_4_ALIGN                 0
#define SGMII_PLL_AFE_CTRL6_I_NDIV_FRAC_17_4_BITS                  14
#define SGMII_PLL_AFE_CTRL6_I_NDIV_FRAC_17_4_SHIFT                 0


/****************************************************************************
 * SGMII_PLL_afe :: ctrl7
 ***************************************************************************/
/* SGMII_PLL_afe :: ctrl7 :: sel_fp3cap [15:12] */
#define Wr_SGMII_PLL_afe_ctrl7_sel_fp3cap(x) WriteRegBits16(SGMII_PLL_AFE_CTRL7,0xf000,12,x)
#define Rd_SGMII_PLL_afe_ctrl7_sel_fp3cap(x) ReadRegBits16(SGMII_PLL_AFE_CTRL7,0xf000,12)
#define SGMII_PLL_AFE_CTRL7_SEL_FP3CAP_MASK                        0xf000
#define SGMII_PLL_AFE_CTRL7_SEL_FP3CAP_ALIGN                       0
#define SGMII_PLL_AFE_CTRL7_SEL_FP3CAP_BITS                        4
#define SGMII_PLL_AFE_CTRL7_SEL_FP3CAP_SHIFT                       12

/* SGMII_PLL_afe :: ctrl7 :: i_pll_sdm_pwrdnb [11:11] */
#define Wr_SGMII_PLL_afe_ctrl7_i_pll_sdm_pwrdnb(x) WriteRegBits16(SGMII_PLL_AFE_CTRL7,0x800,11,x)
#define Rd_SGMII_PLL_afe_ctrl7_i_pll_sdm_pwrdnb(x) ReadRegBits16(SGMII_PLL_AFE_CTRL7,0x800,11)
#define SGMII_PLL_AFE_CTRL7_I_PLL_SDM_PWRDNB_MASK                  0x0800
#define SGMII_PLL_AFE_CTRL7_I_PLL_SDM_PWRDNB_ALIGN                 0
#define SGMII_PLL_AFE_CTRL7_I_PLL_SDM_PWRDNB_BITS                  1
#define SGMII_PLL_AFE_CTRL7_I_PLL_SDM_PWRDNB_SHIFT                 11

/* SGMII_PLL_afe :: ctrl7 :: inv_vco_cal [10:10] */
#define Wr_SGMII_PLL_afe_ctrl7_inv_vco_cal(x) WriteRegBits16(SGMII_PLL_AFE_CTRL7,0x400,10,x)
#define Rd_SGMII_PLL_afe_ctrl7_inv_vco_cal(x) ReadRegBits16(SGMII_PLL_AFE_CTRL7,0x400,10)
#define SGMII_PLL_AFE_CTRL7_INV_VCO_CAL_MASK                       0x0400
#define SGMII_PLL_AFE_CTRL7_INV_VCO_CAL_ALIGN                      0
#define SGMII_PLL_AFE_CTRL7_INV_VCO_CAL_BITS                       1
#define SGMII_PLL_AFE_CTRL7_INV_VCO_CAL_SHIFT                      10

/* SGMII_PLL_afe :: ctrl7 :: i_ndiv_dither_en [09:09] */
#define Wr_SGMII_PLL_afe_ctrl7_i_ndiv_dither_en(x) WriteRegBits16(SGMII_PLL_AFE_CTRL7,0x200,9,x)
#define Rd_SGMII_PLL_afe_ctrl7_i_ndiv_dither_en(x) ReadRegBits16(SGMII_PLL_AFE_CTRL7,0x200,9)
#define SGMII_PLL_AFE_CTRL7_I_NDIV_DITHER_EN_MASK                  0x0200
#define SGMII_PLL_AFE_CTRL7_I_NDIV_DITHER_EN_ALIGN                 0
#define SGMII_PLL_AFE_CTRL7_I_NDIV_DITHER_EN_BITS                  1
#define SGMII_PLL_AFE_CTRL7_I_NDIV_DITHER_EN_SHIFT                 9

/* SGMII_PLL_afe :: ctrl7 :: mmd_div_range [08:08] */
#define Wr_SGMII_PLL_afe_ctrl7_mmd_div_range(x) WriteRegBits16(SGMII_PLL_AFE_CTRL7,0x100,8,x)
#define Rd_SGMII_PLL_afe_ctrl7_mmd_div_range(x) ReadRegBits16(SGMII_PLL_AFE_CTRL7,0x100,8)
#define SGMII_PLL_AFE_CTRL7_MMD_DIV_RANGE_MASK                     0x0100
#define SGMII_PLL_AFE_CTRL7_MMD_DIV_RANGE_ALIGN                    0
#define SGMII_PLL_AFE_CTRL7_MMD_DIV_RANGE_BITS                     1
#define SGMII_PLL_AFE_CTRL7_MMD_DIV_RANGE_SHIFT                    8

/* SGMII_PLL_afe :: ctrl7 :: i_ndiv_int_9_2 [07:00] */
#define Wr_SGMII_PLL_afe_ctrl7_i_ndiv_int_9_2(x) WriteRegBits16(SGMII_PLL_AFE_CTRL7,0xff,0,x)
#define Rd_SGMII_PLL_afe_ctrl7_i_ndiv_int_9_2(x) ReadRegBits16(SGMII_PLL_AFE_CTRL7,0xff,0)
#define SGMII_PLL_AFE_CTRL7_I_NDIV_INT_9_2_MASK                    0x00ff
#define SGMII_PLL_AFE_CTRL7_I_NDIV_INT_9_2_ALIGN                   0
#define SGMII_PLL_AFE_CTRL7_I_NDIV_INT_9_2_BITS                    8
#define SGMII_PLL_AFE_CTRL7_I_NDIV_INT_9_2_SHIFT                   0


/****************************************************************************
 * SGMII_PLL_afe :: ctrl8
 ***************************************************************************/
/* SGMII_PLL_afe :: ctrl8 :: reserved_143_129 [15:01] */
#define SGMII_PLL_AFE_CTRL8_RESERVED_143_129_MASK                  0xfffe
#define SGMII_PLL_AFE_CTRL8_RESERVED_143_129_ALIGN                 0
#define SGMII_PLL_AFE_CTRL8_RESERVED_143_129_BITS                  15
#define SGMII_PLL_AFE_CTRL8_RESERVED_143_129_SHIFT                 1

/* SGMII_PLL_afe :: ctrl8 :: vdd1p0_pll_en [00:00] */
#define Wr_SGMII_PLL_afe_ctrl8_vdd1p0_pll_en(x) WriteRegBits16(SGMII_PLL_AFE_CTRL8,0x1,0,x)
#define Rd_SGMII_PLL_afe_ctrl8_vdd1p0_pll_en(x) ReadRegBits16(SGMII_PLL_AFE_CTRL8,0x1,0)
#define SGMII_PLL_AFE_CTRL8_VDD1P0_PLL_EN_MASK                     0x0001
#define SGMII_PLL_AFE_CTRL8_VDD1P0_PLL_EN_ALIGN                    0
#define SGMII_PLL_AFE_CTRL8_VDD1P0_PLL_EN_BITS                     1
#define SGMII_PLL_AFE_CTRL8_VDD1P0_PLL_EN_SHIFT                    0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_TX_afe
 ***************************************************************************/
/****************************************************************************
 * SGMII0_TX_afe :: anaTxAStatus0
 ***************************************************************************/
/* SGMII0_TX_afe :: anaTxAStatus0 :: reserved0 [15:07] */
#define SGMII0_TX_AFE_ANATXASTATUS0_RESERVED0_MASK                 0xff80
#define SGMII0_TX_AFE_ANATXASTATUS0_RESERVED0_ALIGN                0
#define SGMII0_TX_AFE_ANATXASTATUS0_RESERVED0_BITS                 9
#define SGMII0_TX_AFE_ANATXASTATUS0_RESERVED0_SHIFT                7

/* SGMII0_TX_afe :: anaTxAStatus0 :: txdisable_ln [06:06] */
#define Wr_SGMII0_TX_afe_anaTxAStatus0_txdisable_ln(x) WriteRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x40,6,x)
#define Rd_SGMII0_TX_afe_anaTxAStatus0_txdisable_ln(x) ReadRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x40,6)
#define SGMII0_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_MASK              0x0040
#define SGMII0_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_ALIGN             0
#define SGMII0_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_BITS              1
#define SGMII0_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_SHIFT             6

/* SGMII0_TX_afe :: anaTxAStatus0 :: txferr_stky [05:05] */
#define Wr_SGMII0_TX_afe_anaTxAStatus0_txferr_stky(x) WriteRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x20,5,x)
#define Rd_SGMII0_TX_afe_anaTxAStatus0_txferr_stky(x) ReadRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x20,5)
#define SGMII0_TX_AFE_ANATXASTATUS0_TXFERR_STKY_MASK               0x0020
#define SGMII0_TX_AFE_ANATXASTATUS0_TXFERR_STKY_ALIGN              0
#define SGMII0_TX_AFE_ANATXASTATUS0_TXFERR_STKY_BITS               1
#define SGMII0_TX_AFE_ANATXASTATUS0_TXFERR_STKY_SHIFT              5

/* SGMII0_TX_afe :: anaTxAStatus0 :: tbi_mode [04:04] */
#define Wr_SGMII0_TX_afe_anaTxAStatus0_tbi_mode(x) WriteRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x10,4,x)
#define Rd_SGMII0_TX_afe_anaTxAStatus0_tbi_mode(x) ReadRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x10,4)
#define SGMII0_TX_AFE_ANATXASTATUS0_TBI_MODE_MASK                  0x0010
#define SGMII0_TX_AFE_ANATXASTATUS0_TBI_MODE_ALIGN                 0
#define SGMII0_TX_AFE_ANATXASTATUS0_TBI_MODE_BITS                  1
#define SGMII0_TX_AFE_ANATXASTATUS0_TBI_MODE_SHIFT                 4

/* SGMII0_TX_afe :: anaTxAStatus0 :: tx_reset [03:03] */
#define Wr_SGMII0_TX_afe_anaTxAStatus0_tx_reset(x) WriteRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x8,3,x)
#define Rd_SGMII0_TX_afe_anaTxAStatus0_tx_reset(x) ReadRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x8,3)
#define SGMII0_TX_AFE_ANATXASTATUS0_TX_RESET_MASK                  0x0008
#define SGMII0_TX_AFE_ANATXASTATUS0_TX_RESET_ALIGN                 0
#define SGMII0_TX_AFE_ANATXASTATUS0_TX_RESET_BITS                  1
#define SGMII0_TX_AFE_ANATXASTATUS0_TX_RESET_SHIFT                 3

/* SGMII0_TX_afe :: anaTxAStatus0 :: tx_pwrdn [02:02] */
#define Wr_SGMII0_TX_afe_anaTxAStatus0_tx_pwrdn(x) WriteRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x4,2,x)
#define Rd_SGMII0_TX_afe_anaTxAStatus0_tx_pwrdn(x) ReadRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x4,2)
#define SGMII0_TX_AFE_ANATXASTATUS0_TX_PWRDN_MASK                  0x0004
#define SGMII0_TX_AFE_ANATXASTATUS0_TX_PWRDN_ALIGN                 0
#define SGMII0_TX_AFE_ANATXASTATUS0_TX_PWRDN_BITS                  1
#define SGMII0_TX_AFE_ANATXASTATUS0_TX_PWRDN_SHIFT                 2

/* SGMII0_TX_afe :: anaTxAStatus0 :: rltxferr_stky [01:01] */
#define Wr_SGMII0_TX_afe_anaTxAStatus0_rltxferr_stky(x) WriteRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x2,1,x)
#define Rd_SGMII0_TX_afe_anaTxAStatus0_rltxferr_stky(x) ReadRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x2,1)
#define SGMII0_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_MASK             0x0002
#define SGMII0_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_ALIGN            0
#define SGMII0_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_BITS             1
#define SGMII0_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_SHIFT            1

/* SGMII0_TX_afe :: anaTxAStatus0 :: txpll_lock [00:00] */
#define Wr_SGMII0_TX_afe_anaTxAStatus0_txpll_lock(x) WriteRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x1,0,x)
#define Rd_SGMII0_TX_afe_anaTxAStatus0_txpll_lock(x) ReadRegBits16(SGMII0_TX_AFE_ANATXASTATUS0,0x1,0)
#define SGMII0_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_MASK                0x0001
#define SGMII0_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_ALIGN               0
#define SGMII0_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_BITS                1
#define SGMII0_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_SHIFT               0


/****************************************************************************
 * SGMII0_TX_afe :: anaTxAControl0
 ***************************************************************************/
/* SGMII0_TX_afe :: anaTxAControl0 :: mdio_force [15:15] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_mdio_force(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x8000,15,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_mdio_force(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x8000,15)
#define SGMII0_TX_AFE_ANATXACONTROL0_MDIO_FORCE_MASK               0x8000
#define SGMII0_TX_AFE_ANATXACONTROL0_MDIO_FORCE_ALIGN              0
#define SGMII0_TX_AFE_ANATXACONTROL0_MDIO_FORCE_BITS               1
#define SGMII0_TX_AFE_ANATXACONTROL0_MDIO_FORCE_SHIFT              15

/* SGMII0_TX_afe :: anaTxAControl0 :: force_txclk [14:14] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_force_txclk(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x4000,14,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_force_txclk(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x4000,14)
#define SGMII0_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_MASK              0x4000
#define SGMII0_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_ALIGN             0
#define SGMII0_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_BITS              1
#define SGMII0_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_SHIFT             14

/* SGMII0_TX_afe :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_tx1g_fifo_rst(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x2000,13,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_tx1g_fifo_rst(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x2000,13)
#define SGMII0_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_MASK            0x2000
#define SGMII0_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN           0
#define SGMII0_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_BITS            1
#define SGMII0_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT           13

/* SGMII0_TX_afe :: anaTxAControl0 :: force_ext_frst_SM [12:12] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_force_ext_frst_SM(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x1000,12,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_force_ext_frst_SM(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x1000,12)
#define SGMII0_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK        0x1000
#define SGMII0_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN       0
#define SGMII0_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS        1
#define SGMII0_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT       12

/* SGMII0_TX_afe :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_catch_all_8b10b_dis(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x800,11,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_catch_all_8b10b_dis(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x800,11)
#define SGMII0_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK      0x0800
#define SGMII0_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN     0
#define SGMII0_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS      1
#define SGMII0_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT     11

/* SGMII0_TX_afe :: anaTxAControl0 :: txck_dme_en_SM [10:10] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_txck_dme_en_SM(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x400,10,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_txck_dme_en_SM(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x400,10)
#define SGMII0_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_MASK           0x0400
#define SGMII0_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN          0
#define SGMII0_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_BITS           1
#define SGMII0_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT          10

/* SGMII0_TX_afe :: anaTxAControl0 :: gloopOutDis [09:09] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_gloopOutDis(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x200,9,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_gloopOutDis(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x200,9)
#define SGMII0_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_MASK              0x0200
#define SGMII0_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_ALIGN             0
#define SGMII0_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_BITS              1
#define SGMII0_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_SHIFT             9

/* SGMII0_TX_afe :: anaTxAControl0 :: prbs_en [08:08] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_prbs_en(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x100,8,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_prbs_en(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x100,8)
#define SGMII0_TX_AFE_ANATXACONTROL0_PRBS_EN_MASK                  0x0100
#define SGMII0_TX_AFE_ANATXACONTROL0_PRBS_EN_ALIGN                 0
#define SGMII0_TX_AFE_ANATXACONTROL0_PRBS_EN_BITS                  1
#define SGMII0_TX_AFE_ANATXACONTROL0_PRBS_EN_SHIFT                 8

/* SGMII0_TX_afe :: anaTxAControl0 :: pckt_en [07:07] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_pckt_en(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x80,7,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_pckt_en(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x80,7)
#define SGMII0_TX_AFE_ANATXACONTROL0_PCKT_EN_MASK                  0x0080
#define SGMII0_TX_AFE_ANATXACONTROL0_PCKT_EN_ALIGN                 0
#define SGMII0_TX_AFE_ANATXACONTROL0_PCKT_EN_BITS                  1
#define SGMII0_TX_AFE_ANATXACONTROL0_PCKT_EN_SHIFT                 7

/* SGMII0_TX_afe :: anaTxAControl0 :: pckt_strt [06:06] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_pckt_strt(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x40,6,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_pckt_strt(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x40,6)
#define SGMII0_TX_AFE_ANATXACONTROL0_PCKT_STRT_MASK                0x0040
#define SGMII0_TX_AFE_ANATXACONTROL0_PCKT_STRT_ALIGN               0
#define SGMII0_TX_AFE_ANATXACONTROL0_PCKT_STRT_BITS                1
#define SGMII0_TX_AFE_ANATXACONTROL0_PCKT_STRT_SHIFT               6

/* SGMII0_TX_afe :: anaTxAControl0 :: txpol_flip [05:05] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_txpol_flip(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x20,5,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_txpol_flip(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x20,5)
#define SGMII0_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_MASK               0x0020
#define SGMII0_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_ALIGN              0
#define SGMII0_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_BITS               1
#define SGMII0_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_SHIFT              5

/* SGMII0_TX_afe :: anaTxAControl0 :: rtbi_flip [04:04] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_rtbi_flip(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x10,4,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_rtbi_flip(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x10,4)
#define SGMII0_TX_AFE_ANATXACONTROL0_RTBI_FLIP_MASK                0x0010
#define SGMII0_TX_AFE_ANATXACONTROL0_RTBI_FLIP_ALIGN               0
#define SGMII0_TX_AFE_ANATXACONTROL0_RTBI_FLIP_BITS                1
#define SGMII0_TX_AFE_ANATXACONTROL0_RTBI_FLIP_SHIFT               4

/* SGMII0_TX_afe :: anaTxAControl0 :: eden_r [03:03] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_eden_r(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x8,3,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_eden_r(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x8,3)
#define SGMII0_TX_AFE_ANATXACONTROL0_EDEN_R_MASK                   0x0008
#define SGMII0_TX_AFE_ANATXACONTROL0_EDEN_R_ALIGN                  0
#define SGMII0_TX_AFE_ANATXACONTROL0_EDEN_R_BITS                   1
#define SGMII0_TX_AFE_ANATXACONTROL0_EDEN_R_SHIFT                  3

/* SGMII0_TX_afe :: anaTxAControl0 :: eden_force_r [02:02] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_eden_force_r(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x4,2,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_eden_force_r(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x4,2)
#define SGMII0_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_MASK             0x0004
#define SGMII0_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_ALIGN            0
#define SGMII0_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_BITS             1
#define SGMII0_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_SHIFT            2

/* SGMII0_TX_afe :: anaTxAControl0 :: txpat_en [01:01] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_txpat_en(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x2,1,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_txpat_en(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x2,1)
#define SGMII0_TX_AFE_ANATXACONTROL0_TXPAT_EN_MASK                 0x0002
#define SGMII0_TX_AFE_ANATXACONTROL0_TXPAT_EN_ALIGN                0
#define SGMII0_TX_AFE_ANATXACONTROL0_TXPAT_EN_BITS                 1
#define SGMII0_TX_AFE_ANATXACONTROL0_TXPAT_EN_SHIFT                1

/* SGMII0_TX_afe :: anaTxAControl0 :: tx_mdata_en [00:00] */
#define Wr_SGMII0_TX_afe_anaTxAControl0_tx_mdata_en(x) WriteRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x1,0,x)
#define Rd_SGMII0_TX_afe_anaTxAControl0_tx_mdata_en(x) ReadRegBits16(SGMII0_TX_AFE_ANATXACONTROL0,0x1,0)
#define SGMII0_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_MASK              0x0001
#define SGMII0_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_ALIGN             0
#define SGMII0_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_BITS              1
#define SGMII0_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_SHIFT             0


/****************************************************************************
 * SGMII0_TX_afe :: anaTxmdata0
 ***************************************************************************/
/* SGMII0_TX_afe :: anaTxmdata0 :: txTestMuxSel [15:13] */
#define Wr_SGMII0_TX_afe_anaTxmdata0_txTestMuxSel(x) WriteRegBits16(SGMII0_TX_AFE_ANATXMDATA0,0xe000,13,x)
#define Rd_SGMII0_TX_afe_anaTxmdata0_txTestMuxSel(x) ReadRegBits16(SGMII0_TX_AFE_ANATXMDATA0,0xe000,13)
#define SGMII0_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_MASK                0xe000
#define SGMII0_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_ALIGN               0
#define SGMII0_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_BITS                3
#define SGMII0_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_SHIFT               13

/* SGMII0_TX_afe :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
#define Wr_SGMII0_TX_afe_anaTxmdata0_rlfifo_tstsel(x) WriteRegBits16(SGMII0_TX_AFE_ANATXMDATA0,0x1c00,10,x)
#define Rd_SGMII0_TX_afe_anaTxmdata0_rlfifo_tstsel(x) ReadRegBits16(SGMII0_TX_AFE_ANATXMDATA0,0x1c00,10)
#define SGMII0_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_MASK               0x1c00
#define SGMII0_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN              0
#define SGMII0_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_BITS               3
#define SGMII0_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT              10

/* SGMII0_TX_afe :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
#define Wr_SGMII0_TX_afe_anaTxmdata0_TxMdioTstDataL(x) WriteRegBits16(SGMII0_TX_AFE_ANATXMDATA0,0x3ff,0,x)
#define Rd_SGMII0_TX_afe_anaTxmdata0_TxMdioTstDataL(x) ReadRegBits16(SGMII0_TX_AFE_ANATXMDATA0,0x3ff,0)
#define SGMII0_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_MASK              0x03ff
#define SGMII0_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN             0
#define SGMII0_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_BITS              10
#define SGMII0_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT             0


/****************************************************************************
 * SGMII0_TX_afe :: anaTxmdata1
 ***************************************************************************/
/* SGMII0_TX_afe :: anaTxmdata1 :: reserved0 [15:14] */
#define SGMII0_TX_AFE_ANATXMDATA1_RESERVED0_MASK                   0xc000
#define SGMII0_TX_AFE_ANATXMDATA1_RESERVED0_ALIGN                  0
#define SGMII0_TX_AFE_ANATXMDATA1_RESERVED0_BITS                   2
#define SGMII0_TX_AFE_ANATXMDATA1_RESERVED0_SHIFT                  14

/* SGMII0_TX_afe :: anaTxmdata1 :: tx_elecidle [13:13] */
#define Wr_SGMII0_TX_afe_anaTxmdata1_tx_elecidle(x) WriteRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x2000,13,x)
#define Rd_SGMII0_TX_afe_anaTxmdata1_tx_elecidle(x) ReadRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x2000,13)
#define SGMII0_TX_AFE_ANATXMDATA1_TX_ELECIDLE_MASK                 0x2000
#define SGMII0_TX_AFE_ANATXMDATA1_TX_ELECIDLE_ALIGN                0
#define SGMII0_TX_AFE_ANATXMDATA1_TX_ELECIDLE_BITS                 1
#define SGMII0_TX_AFE_ANATXMDATA1_TX_ELECIDLE_SHIFT                13

/* SGMII0_TX_afe :: anaTxmdata1 :: glpbk_clk_en [12:12] */
#define Wr_SGMII0_TX_afe_anaTxmdata1_glpbk_clk_en(x) WriteRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x1000,12,x)
#define Rd_SGMII0_TX_afe_anaTxmdata1_glpbk_clk_en(x) ReadRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x1000,12)
#define SGMII0_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_MASK                0x1000
#define SGMII0_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_ALIGN               0
#define SGMII0_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_BITS                1
#define SGMII0_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_SHIFT               12

/* SGMII0_TX_afe :: anaTxmdata1 :: pre_emph_stair_rev_en [11:11] */
#define Wr_SGMII0_TX_afe_anaTxmdata1_pre_emph_stair_rev_en(x) WriteRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x800,11,x)
#define Rd_SGMII0_TX_afe_anaTxmdata1_pre_emph_stair_rev_en(x) ReadRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x800,11)
#define SGMII0_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_MASK       0x0800
#define SGMII0_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_ALIGN      0
#define SGMII0_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_BITS       1
#define SGMII0_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_SHIFT      11

/* SGMII0_TX_afe :: anaTxmdata1 :: pre_emph_stair_en [10:10] */
#define Wr_SGMII0_TX_afe_anaTxmdata1_pre_emph_stair_en(x) WriteRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x400,10,x)
#define Rd_SGMII0_TX_afe_anaTxmdata1_pre_emph_stair_en(x) ReadRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x400,10)
#define SGMII0_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_MASK           0x0400
#define SGMII0_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_ALIGN          0
#define SGMII0_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_BITS           1
#define SGMII0_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_SHIFT          10

/* SGMII0_TX_afe :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
#define Wr_SGMII0_TX_afe_anaTxmdata1_TxMdioTstDataH(x) WriteRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x3ff,0,x)
#define Rd_SGMII0_TX_afe_anaTxmdata1_TxMdioTstDataH(x) ReadRegBits16(SGMII0_TX_AFE_ANATXMDATA1,0x3ff,0)
#define SGMII0_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_MASK              0x03ff
#define SGMII0_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN             0
#define SGMII0_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_BITS              10
#define SGMII0_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT             0


/****************************************************************************
 * SGMII0_TX_afe :: control0
 ***************************************************************************/
/* SGMII0_TX_afe :: control0 :: Fix_10units_en [15:15] */
#define Wr_SGMII0_TX_afe_control0_Fix_10units_en(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL0,0x8000,15,x)
#define Rd_SGMII0_TX_afe_control0_Fix_10units_en(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL0,0x8000,15)
#define SGMII0_TX_AFE_CONTROL0_FIX_10UNITS_EN_MASK                 0x8000
#define SGMII0_TX_AFE_CONTROL0_FIX_10UNITS_EN_ALIGN                0
#define SGMII0_TX_AFE_CONTROL0_FIX_10UNITS_EN_BITS                 1
#define SGMII0_TX_AFE_CONTROL0_FIX_10UNITS_EN_SHIFT                15

/* SGMII0_TX_afe :: control0 :: Quarter_unit_en [14:14] */
#define Wr_SGMII0_TX_afe_control0_Quarter_unit_en(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL0,0x4000,14,x)
#define Rd_SGMII0_TX_afe_control0_Quarter_unit_en(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL0,0x4000,14)
#define SGMII0_TX_AFE_CONTROL0_QUARTER_UNIT_EN_MASK                0x4000
#define SGMII0_TX_AFE_CONTROL0_QUARTER_UNIT_EN_ALIGN               0
#define SGMII0_TX_AFE_CONTROL0_QUARTER_UNIT_EN_BITS                1
#define SGMII0_TX_AFE_CONTROL0_QUARTER_UNIT_EN_SHIFT               14

/* SGMII0_TX_afe :: control0 :: main_control [13:08] */
#define Wr_SGMII0_TX_afe_control0_main_control(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL0,0x3f00,8,x)
#define Rd_SGMII0_TX_afe_control0_main_control(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL0,0x3f00,8)
#define SGMII0_TX_AFE_CONTROL0_MAIN_CONTROL_MASK                   0x3f00
#define SGMII0_TX_AFE_CONTROL0_MAIN_CONTROL_ALIGN                  0
#define SGMII0_TX_AFE_CONTROL0_MAIN_CONTROL_BITS                   6
#define SGMII0_TX_AFE_CONTROL0_MAIN_CONTROL_SHIFT                  8

/* SGMII0_TX_afe :: control0 :: reserved_7 [07:07] */
#define SGMII0_TX_AFE_CONTROL0_RESERVED_7_MASK                     0x0080
#define SGMII0_TX_AFE_CONTROL0_RESERVED_7_ALIGN                    0
#define SGMII0_TX_AFE_CONTROL0_RESERVED_7_BITS                     1
#define SGMII0_TX_AFE_CONTROL0_RESERVED_7_SHIFT                    7

/* SGMII0_TX_afe :: control0 :: rxdetect_th [06:05] */
#define Wr_SGMII0_TX_afe_control0_rxdetect_th(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL0,0x60,5,x)
#define Rd_SGMII0_TX_afe_control0_rxdetect_th(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL0,0x60,5)
#define SGMII0_TX_AFE_CONTROL0_RXDETECT_TH_MASK                    0x0060
#define SGMII0_TX_AFE_CONTROL0_RXDETECT_TH_ALIGN                   0
#define SGMII0_TX_AFE_CONTROL0_RXDETECT_TH_BITS                    2
#define SGMII0_TX_AFE_CONTROL0_RXDETECT_TH_SHIFT                   5

/* SGMII0_TX_afe :: control0 :: idle_ena [04:04] */
#define Wr_SGMII0_TX_afe_control0_idle_ena(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL0,0x10,4,x)
#define Rd_SGMII0_TX_afe_control0_idle_ena(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL0,0x10,4)
#define SGMII0_TX_AFE_CONTROL0_IDLE_ENA_MASK                       0x0010
#define SGMII0_TX_AFE_CONTROL0_IDLE_ENA_ALIGN                      0
#define SGMII0_TX_AFE_CONTROL0_IDLE_ENA_BITS                       1
#define SGMII0_TX_AFE_CONTROL0_IDLE_ENA_SHIFT                      4

/* SGMII0_TX_afe :: control0 :: reserved_3_2 [03:02] */
#define SGMII0_TX_AFE_CONTROL0_RESERVED_3_2_MASK                   0x000c
#define SGMII0_TX_AFE_CONTROL0_RESERVED_3_2_ALIGN                  0
#define SGMII0_TX_AFE_CONTROL0_RESERVED_3_2_BITS                   2
#define SGMII0_TX_AFE_CONTROL0_RESERVED_3_2_SHIFT                  2

/* SGMII0_TX_afe :: control0 :: Testsel [01:01] */
#define Wr_SGMII0_TX_afe_control0_Testsel(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL0,0x2,1,x)
#define Rd_SGMII0_TX_afe_control0_Testsel(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL0,0x2,1)
#define SGMII0_TX_AFE_CONTROL0_TESTSEL_MASK                        0x0002
#define SGMII0_TX_AFE_CONTROL0_TESTSEL_ALIGN                       0
#define SGMII0_TX_AFE_CONTROL0_TESTSEL_BITS                        1
#define SGMII0_TX_AFE_CONTROL0_TESTSEL_SHIFT                       1

/* SGMII0_TX_afe :: control0 :: tx_pwrdn [00:00] */
#define Wr_SGMII0_TX_afe_control0_tx_pwrdn(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL0,0x1,0,x)
#define Rd_SGMII0_TX_afe_control0_tx_pwrdn(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL0,0x1,0)
#define SGMII0_TX_AFE_CONTROL0_TX_PWRDN_MASK                       0x0001
#define SGMII0_TX_AFE_CONTROL0_TX_PWRDN_ALIGN                      0
#define SGMII0_TX_AFE_CONTROL0_TX_PWRDN_BITS                       1
#define SGMII0_TX_AFE_CONTROL0_TX_PWRDN_SHIFT                      0


/****************************************************************************
 * SGMII0_TX_afe :: control1
 ***************************************************************************/
/* SGMII0_TX_afe :: control1 :: Slew_rate_control [15:14] */
#define Wr_SGMII0_TX_afe_control1_Slew_rate_control(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL1,0xc000,14,x)
#define Rd_SGMII0_TX_afe_control1_Slew_rate_control(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL1,0xc000,14)
#define SGMII0_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_MASK              0xc000
#define SGMII0_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_ALIGN             0
#define SGMII0_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_BITS              2
#define SGMII0_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_SHIFT             14

/* SGMII0_TX_afe :: control1 :: reserved_29 [13:13] */
#define SGMII0_TX_AFE_CONTROL1_RESERVED_29_MASK                    0x2000
#define SGMII0_TX_AFE_CONTROL1_RESERVED_29_ALIGN                   0
#define SGMII0_TX_AFE_CONTROL1_RESERVED_29_BITS                    1
#define SGMII0_TX_AFE_CONTROL1_RESERVED_29_SHIFT                   13

/* SGMII0_TX_afe :: control1 :: Post_enable [12:12] */
#define Wr_SGMII0_TX_afe_control1_Post_enable(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL1,0x1000,12,x)
#define Rd_SGMII0_TX_afe_control1_Post_enable(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL1,0x1000,12)
#define SGMII0_TX_AFE_CONTROL1_POST_ENABLE_MASK                    0x1000
#define SGMII0_TX_AFE_CONTROL1_POST_ENABLE_ALIGN                   0
#define SGMII0_TX_AFE_CONTROL1_POST_ENABLE_BITS                    1
#define SGMII0_TX_AFE_CONTROL1_POST_ENABLE_SHIFT                   12

/* SGMII0_TX_afe :: control1 :: Post_control [11:06] */
#define Wr_SGMII0_TX_afe_control1_Post_control(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL1,0xfc0,6,x)
#define Rd_SGMII0_TX_afe_control1_Post_control(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL1,0xfc0,6)
#define SGMII0_TX_AFE_CONTROL1_POST_CONTROL_MASK                   0x0fc0
#define SGMII0_TX_AFE_CONTROL1_POST_CONTROL_ALIGN                  0
#define SGMII0_TX_AFE_CONTROL1_POST_CONTROL_BITS                   6
#define SGMII0_TX_AFE_CONTROL1_POST_CONTROL_SHIFT                  6

/* SGMII0_TX_afe :: control1 :: reserved_21 [05:05] */
#define SGMII0_TX_AFE_CONTROL1_RESERVED_21_MASK                    0x0020
#define SGMII0_TX_AFE_CONTROL1_RESERVED_21_ALIGN                   0
#define SGMII0_TX_AFE_CONTROL1_RESERVED_21_BITS                    1
#define SGMII0_TX_AFE_CONTROL1_RESERVED_21_SHIFT                   5

/* SGMII0_TX_afe :: control1 :: Pwd_lvl2pi [04:04] */
#define Wr_SGMII0_TX_afe_control1_Pwd_lvl2pi(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL1,0x10,4,x)
#define Rd_SGMII0_TX_afe_control1_Pwd_lvl2pi(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL1,0x10,4)
#define SGMII0_TX_AFE_CONTROL1_PWD_LVL2PI_MASK                     0x0010
#define SGMII0_TX_AFE_CONTROL1_PWD_LVL2PI_ALIGN                    0
#define SGMII0_TX_AFE_CONTROL1_PWD_LVL2PI_BITS                     1
#define SGMII0_TX_AFE_CONTROL1_PWD_LVL2PI_SHIFT                    4

/* SGMII0_TX_afe :: control1 :: PI_bw_sel [03:03] */
#define Wr_SGMII0_TX_afe_control1_PI_bw_sel(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL1,0x8,3,x)
#define Rd_SGMII0_TX_afe_control1_PI_bw_sel(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL1,0x8,3)
#define SGMII0_TX_AFE_CONTROL1_PI_BW_SEL_MASK                      0x0008
#define SGMII0_TX_AFE_CONTROL1_PI_BW_SEL_ALIGN                     0
#define SGMII0_TX_AFE_CONTROL1_PI_BW_SEL_BITS                      1
#define SGMII0_TX_AFE_CONTROL1_PI_BW_SEL_SHIFT                     3

/* SGMII0_TX_afe :: control1 :: Const_Impedance [02:02] */
#define Wr_SGMII0_TX_afe_control1_Const_Impedance(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL1,0x4,2,x)
#define Rd_SGMII0_TX_afe_control1_Const_Impedance(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL1,0x4,2)
#define SGMII0_TX_AFE_CONTROL1_CONST_IMPEDANCE_MASK                0x0004
#define SGMII0_TX_AFE_CONTROL1_CONST_IMPEDANCE_ALIGN               0
#define SGMII0_TX_AFE_CONTROL1_CONST_IMPEDANCE_BITS                1
#define SGMII0_TX_AFE_CONTROL1_CONST_IMPEDANCE_SHIFT               2

/* SGMII0_TX_afe :: control1 :: Amp_mode [01:01] */
#define Wr_SGMII0_TX_afe_control1_Amp_mode(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL1,0x2,1,x)
#define Rd_SGMII0_TX_afe_control1_Amp_mode(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL1,0x2,1)
#define SGMII0_TX_AFE_CONTROL1_AMP_MODE_MASK                       0x0002
#define SGMII0_TX_AFE_CONTROL1_AMP_MODE_ALIGN                      0
#define SGMII0_TX_AFE_CONTROL1_AMP_MODE_BITS                       1
#define SGMII0_TX_AFE_CONTROL1_AMP_MODE_SHIFT                      1

/* SGMII0_TX_afe :: control1 :: Vdd1p0_enb [00:00] */
#define Wr_SGMII0_TX_afe_control1_Vdd1p0_enb(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL1,0x1,0,x)
#define Rd_SGMII0_TX_afe_control1_Vdd1p0_enb(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL1,0x1,0)
#define SGMII0_TX_AFE_CONTROL1_VDD1P0_ENB_MASK                     0x0001
#define SGMII0_TX_AFE_CONTROL1_VDD1P0_ENB_ALIGN                    0
#define SGMII0_TX_AFE_CONTROL1_VDD1P0_ENB_BITS                     1
#define SGMII0_TX_AFE_CONTROL1_VDD1P0_ENB_SHIFT                    0


/****************************************************************************
 * SGMII0_TX_afe :: control2
 ***************************************************************************/
/* SGMII0_TX_afe :: control2 :: leakage_test [15:15] */
#define Wr_SGMII0_TX_afe_control2_leakage_test(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL2,0x8000,15,x)
#define Rd_SGMII0_TX_afe_control2_leakage_test(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL2,0x8000,15)
#define SGMII0_TX_AFE_CONTROL2_LEAKAGE_TEST_MASK                   0x8000
#define SGMII0_TX_AFE_CONTROL2_LEAKAGE_TEST_ALIGN                  0
#define SGMII0_TX_AFE_CONTROL2_LEAKAGE_TEST_BITS                   1
#define SGMII0_TX_AFE_CONTROL2_LEAKAGE_TEST_SHIFT                  15

/* SGMII0_TX_afe :: control2 :: Vdd_noise_cncl_en [14:14] */
#define Wr_SGMII0_TX_afe_control2_Vdd_noise_cncl_en(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL2,0x4000,14,x)
#define Rd_SGMII0_TX_afe_control2_Vdd_noise_cncl_en(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL2,0x4000,14)
#define SGMII0_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_MASK              0x4000
#define SGMII0_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_ALIGN             0
#define SGMII0_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_BITS              1
#define SGMII0_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_SHIFT             14

/* SGMII0_TX_afe :: control2 :: Noise_cncl_bias [13:10] */
#define Wr_SGMII0_TX_afe_control2_Noise_cncl_bias(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL2,0x3c00,10,x)
#define Rd_SGMII0_TX_afe_control2_Noise_cncl_bias(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL2,0x3c00,10)
#define SGMII0_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_MASK                0x3c00
#define SGMII0_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_ALIGN               0
#define SGMII0_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_BITS                4
#define SGMII0_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_SHIFT               10

/* SGMII0_TX_afe :: control2 :: Vdd_noise_shape [09:07] */
#define Wr_SGMII0_TX_afe_control2_Vdd_noise_shape(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL2,0x380,7,x)
#define Rd_SGMII0_TX_afe_control2_Vdd_noise_shape(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL2,0x380,7)
#define SGMII0_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_MASK                0x0380
#define SGMII0_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_ALIGN               0
#define SGMII0_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_BITS                3
#define SGMII0_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_SHIFT               7

/* SGMII0_TX_afe :: control2 :: tx_pon [06:03] */
#define Wr_SGMII0_TX_afe_control2_tx_pon(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL2,0x78,3,x)
#define Rd_SGMII0_TX_afe_control2_tx_pon(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL2,0x78,3)
#define SGMII0_TX_AFE_CONTROL2_TX_PON_MASK                         0x0078
#define SGMII0_TX_AFE_CONTROL2_TX_PON_ALIGN                        0
#define SGMII0_TX_AFE_CONTROL2_TX_PON_BITS                         4
#define SGMII0_TX_AFE_CONTROL2_TX_PON_SHIFT                        3

/* SGMII0_TX_afe :: control2 :: ticksel [02:01] */
#define Wr_SGMII0_TX_afe_control2_ticksel(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL2,0x6,1,x)
#define Rd_SGMII0_TX_afe_control2_ticksel(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL2,0x6,1)
#define SGMII0_TX_AFE_CONTROL2_TICKSEL_MASK                        0x0006
#define SGMII0_TX_AFE_CONTROL2_TICKSEL_ALIGN                       0
#define SGMII0_TX_AFE_CONTROL2_TICKSEL_BITS                        2
#define SGMII0_TX_AFE_CONTROL2_TICKSEL_SHIFT                       1

/* SGMII0_TX_afe :: control2 :: testck_en [00:00] */
#define Wr_SGMII0_TX_afe_control2_testck_en(x) WriteRegBits16(SGMII0_TX_AFE_CONTROL2,0x1,0,x)
#define Rd_SGMII0_TX_afe_control2_testck_en(x) ReadRegBits16(SGMII0_TX_AFE_CONTROL2,0x1,0)
#define SGMII0_TX_AFE_CONTROL2_TESTCK_EN_MASK                      0x0001
#define SGMII0_TX_AFE_CONTROL2_TESTCK_EN_ALIGN                     0
#define SGMII0_TX_AFE_CONTROL2_TESTCK_EN_BITS                      1
#define SGMII0_TX_AFE_CONTROL2_TESTCK_EN_SHIFT                     0


/****************************************************************************
 * SGMII0_TX_afe :: control3
 ***************************************************************************/
/* SGMII0_TX_afe :: control3 :: reserved_63_48 [15:00] */
#define SGMII0_TX_AFE_CONTROL3_RESERVED_63_48_MASK                 0xffff
#define SGMII0_TX_AFE_CONTROL3_RESERVED_63_48_ALIGN                0
#define SGMII0_TX_AFE_CONTROL3_RESERVED_63_48_BITS                 16
#define SGMII0_TX_AFE_CONTROL3_RESERVED_63_48_SHIFT                0


/****************************************************************************
 * SGMII0_TX_afe :: interp
 ***************************************************************************/
/* SGMII0_TX_afe :: interp :: reserved0 [15:07] */
#define SGMII0_TX_AFE_INTERP_RESERVED0_MASK                        0xff80
#define SGMII0_TX_AFE_INTERP_RESERVED0_ALIGN                       0
#define SGMII0_TX_AFE_INTERP_RESERVED0_BITS                        9
#define SGMII0_TX_AFE_INTERP_RESERVED0_SHIFT                       7

/* SGMII0_TX_afe :: interp :: interp_ctrl_quadrant [06:05] */
#define Wr_SGMII0_TX_afe_interp_interp_ctrl_quadrant(x) WriteRegBits16(SGMII0_TX_AFE_INTERP,0x60,5,x)
#define Rd_SGMII0_TX_afe_interp_interp_ctrl_quadrant(x) ReadRegBits16(SGMII0_TX_AFE_INTERP,0x60,5)
#define SGMII0_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_MASK             0x0060
#define SGMII0_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_ALIGN            0
#define SGMII0_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_BITS             2
#define SGMII0_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_SHIFT            5

/* SGMII0_TX_afe :: interp :: interp_ctrl_phs [04:00] */
#define Wr_SGMII0_TX_afe_interp_interp_ctrl_phs(x) WriteRegBits16(SGMII0_TX_AFE_INTERP,0x1f,0,x)
#define Rd_SGMII0_TX_afe_interp_interp_ctrl_phs(x) ReadRegBits16(SGMII0_TX_AFE_INTERP,0x1f,0)
#define SGMII0_TX_AFE_INTERP_INTERP_CTRL_PHS_MASK                  0x001f
#define SGMII0_TX_AFE_INTERP_INTERP_CTRL_PHS_ALIGN                 0
#define SGMII0_TX_AFE_INTERP_INTERP_CTRL_PHS_BITS                  5
#define SGMII0_TX_AFE_INTERP_INTERP_CTRL_PHS_SHIFT                 0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_RX_afe
 ***************************************************************************/
/****************************************************************************
 * SGMII0_RX_afe :: anaRxStatus
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: cx4_sigdet [15:15] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sigdet_Status_cx4_sigdet(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x8000,15,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sigdet_Status_cx4_sigdet(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x8000,15)
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK    0x8000
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS    1
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT   15

/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [14:13] */
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK     0x6000
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS     2
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT    13

/* SGMII0_RX_afe :: anaRxStatus :: rxSeqDone [12:12] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sigdet_Status_rxSeqDone(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x1000,12,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sigdet_Status_rxSeqDone(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x1000,12)
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK     0x1000
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT    12

/* SGMII0_RX_afe :: anaRxStatus :: rx_sigdet_ll [11:11] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sigdet_Status_rx_sigdet_ll(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x800,11,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sigdet_Status_rx_sigdet_ll(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x800,11)
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK  0x0800
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS  1
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11

/* SGMII0_RX_afe :: anaRxStatus :: cs4_sigdet_ll [10:10] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sigdet_Status_cs4_sigdet_ll(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x400,10,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sigdet_Status_cs4_sigdet_ll(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x400,10)
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10

/* SGMII0_RX_afe :: anaRxStatus :: rx_reset [09:09] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sigdet_Status_rx_reset(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x200,9,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sigdet_Status_rx_reset(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x200,9)
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK      0x0200
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN     0
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS      1
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT     9

/* SGMII0_RX_afe :: anaRxStatus :: rx_pwrdn [08:08] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sigdet_Status_rx_pwrdn(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x100,8,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sigdet_Status_rx_pwrdn(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x100,8)
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK      0x0100
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN     0
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS      1
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT     8

/* SGMII0_RX_afe :: anaRxStatus :: reserved1 [07:00] */
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK     0x00ff
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS     8
#define SGMII0_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT    0


/* union - case sync_Status [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:11] */
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK       0xf800
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS       5
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT      11

/* SGMII0_RX_afe :: anaRxStatus :: test_acq_en [10:10] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sync_Status_test_acq_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x400,10,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sync_Status_test_acq_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x400,10)
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK     0x0400
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT    10

/* SGMII0_RX_afe :: anaRxStatus :: reserved1 [09:09] */
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK       0x0200
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS       1
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT      9

/* SGMII0_RX_afe :: anaRxStatus :: rxSeqStart [08:08] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sync_Status_rxSeqStart(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x100,8,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sync_Status_rxSeqStart(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x100,8)
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK      0x0100
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN     0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS      1
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT     8

/* SGMII0_RX_afe :: anaRxStatus :: mux_comadj_sync_status [07:07] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sync_Status_mux_comadj_sync_status(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x80,7,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sync_Status_mux_comadj_sync_status(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x80,7)
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7

/* SGMII0_RX_afe :: anaRxStatus :: sync_status [06:06] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sync_Status_sync_status(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x40,6,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sync_Status_sync_status(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x40,6)
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK     0x0040
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT    6

/* SGMII0_RX_afe :: anaRxStatus :: rx_sigdet [05:05] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sync_Status_rx_sigdet(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sync_Status_rx_sigdet(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x20,5)
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK       0x0020
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS       1
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT      5

/* SGMII0_RX_afe :: anaRxStatus :: reserved2 [04:03] */
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK       0x0018
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS       2
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT      3

/* SGMII0_RX_afe :: anaRxStatus :: saturate_status [02:02] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sync_Status_saturate_status(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sync_Status_saturate_status(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x4,2)
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2

/* SGMII0_RX_afe :: anaRxStatus :: cx4_sigdet [01:01] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sync_Status_cx4_sigdet(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x2,1,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sync_Status_cx4_sigdet(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x2,1)
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK      0x0002
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN     0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS      1
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT     1

/* SGMII0_RX_afe :: anaRxStatus :: rxSeqDone [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_sync_Status_rxSeqDone(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_sync_Status_rxSeqDone(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK       0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS       1
#define SGMII0_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT      0


/* union - case rxTestSel_0 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:10] */
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK       0xfc00
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS       6
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT      10

/* SGMII0_RX_afe :: anaRxStatus :: indck_mode_en [09:09] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_indck_mode_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x200,9,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_indck_mode_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x200,9)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK   0x0200
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT  9

/* SGMII0_RX_afe :: anaRxStatus :: pci_mode_en [08:08] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_pci_mode_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x100,8,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_pci_mode_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x100,8)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK     0x0100
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT    8

/* SGMII0_RX_afe :: anaRxStatus :: rx_polarity [07:07] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_rx_polarity(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x80,7,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_rx_polarity(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x80,7)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK     0x0080
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT    7

/* SGMII0_RX_afe :: anaRxStatus :: rxpol_flip [06:06] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_rxpol_flip(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x40,6,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_rxpol_flip(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x40,6)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK      0x0040
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN     0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS      1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT     6

/* SGMII0_RX_afe :: anaRxStatus :: comma_mask [05:05] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_comma_mask(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_comma_mask(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x20,5)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK      0x0020
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN     0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS      1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT     5

/* SGMII0_RX_afe :: anaRxStatus :: link_en_r [04:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_link_en_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_link_en_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x10,4)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK       0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS       1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT      4

/* SGMII0_RX_afe :: anaRxStatus :: comma_adj_en [03:03] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x8,3)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK    0x0008
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS    1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT   3

/* SGMII0_RX_afe :: anaRxStatus :: comma_adj_en_ext [02:02] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en_ext(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en_ext(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x4,2)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2

/* SGMII0_RX_afe :: anaRxStatus :: reserved1 [01:00] */
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK       0x0003
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS       2
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT      0


/* union - case rxTestSel_1 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK       0xffe0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS       11
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT      5

/* SGMII0_RX_afe :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_1_cdrAcqDone_r2(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_1_cdrAcqDone_r2(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x10,4)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK   0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT  4

/* SGMII0_RX_afe :: anaRxStatus :: freq_sel_PC [03:03] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_PC(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_PC(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x8,3)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK     0x0008
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT    3

/* SGMII0_RX_afe :: anaRxStatus :: freq_sel_SM [02:02] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x4,2)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK     0x0004
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT    2

/* SGMII0_RX_afe :: anaRxStatus :: integ_mode_SM [01:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_rxTestSel_1_integ_mode_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x3,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_rxTestSel_1_integ_mode_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x3,0)
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK   0x0003
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS   2
#define SGMII0_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT  0


/* union - case scale_Status [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: prop_scale [15:12] */
#define Wr_SGMII0_RX_afe_anaRxStatus_scale_Status_prop_scale(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf000,12,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_scale_Status_prop_scale(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf000,12)
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK     0xf000
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS     4
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT    12

/* SGMII0_RX_afe :: anaRxStatus :: integ_scale [11:08] */
#define Wr_SGMII0_RX_afe_anaRxStatus_scale_Status_integ_scale(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf00,8,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_scale_Status_integ_scale(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf00,8)
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK    0x0f00
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS    4
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT   8

/* SGMII0_RX_afe :: anaRxStatus :: prop_scale_acq [07:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_scale_Status_prop_scale_acq(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf0,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_scale_Status_prop_scale_acq(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf0,4)
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4

/* SGMII0_RX_afe :: anaRxStatus :: integ_scale_acq [03:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_scale_Status_integ_scale_acq(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_scale_Status_integ_scale_acq(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf,0)
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4
#define SGMII0_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0


/* union - case adc_CdrStatus1 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:07] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK    0xff80
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS    9
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT   7

/* SGMII0_RX_afe :: anaRxStatus :: rxMuxCkSel [06:06] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_rxMuxCkSel(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x40,6,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_rxMuxCkSel(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x40,6)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK   0x0040
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT  6

/* SGMII0_RX_afe :: anaRxStatus :: glpbk_combo [05:05] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_glpbk_combo(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_glpbk_combo(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x20,5)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK  0x0020
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS  1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5

/* SGMII0_RX_afe :: anaRxStatus :: clockSwitchSel [04:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_clockSwitchSel(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_clockSwitchSel(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x10,4)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4

/* SGMII0_RX_afe :: anaRxStatus :: rxck_tst [03:03] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_tst(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_tst(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x8,3)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK     0x0008
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT    3

/* SGMII0_RX_afe :: anaRxStatus :: rxck_i [02:02] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_i(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_i(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x4,2)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK       0x0004
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS       1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT      2

/* SGMII0_RX_afe :: anaRxStatus :: refclk [01:01] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_refclk(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x2,1,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_refclk(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x2,1)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK       0x0002
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS       1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT      1

/* SGMII0_RX_afe :: anaRxStatus :: pll_bypass [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_pll_bypass(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus1_pll_bypass(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK   0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT  0


/* union - case adc_CdrStatus2 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:06] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK    0xffc0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS    10
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT   6

/* SGMII0_RX_afe :: anaRxStatus :: rxMuxCkSel [05:05] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus2_rxMuxCkSel(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus2_rxMuxCkSel(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x20,5)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK   0x0020
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT  5

/* SGMII0_RX_afe :: anaRxStatus :: rxSeqStart [04:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqStart(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqStart(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x10,4)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK   0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT  4

/* SGMII0_RX_afe :: anaRxStatus :: reserved1 [03:01] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK    0x000e
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS    3
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT   1

/* SGMII0_RX_afe :: anaRxStatus :: rxSeqDone [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqDone(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqDone(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK    0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS    1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT   0


/* union - case adc_CdrStatus3 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:04] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK    0xfff0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS    12
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT   4

/* SGMII0_RX_afe :: anaRxStatus :: rxSeqStart [03:03] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus3_rxSeqStart(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus3_rxSeqStart(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x8,3)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK   0x0008
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT  3

/* SGMII0_RX_afe :: anaRxStatus :: reserved1 [02:01] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK    0x0006
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS    2
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT   1

/* SGMII0_RX_afe :: anaRxStatus :: allow_increment_PC [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus3_allow_increment_PC(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus3_allow_increment_PC(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0


/* union - case adc_CdrStatus4 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:08] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK    0xff00
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS    8
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT   8

/* SGMII0_RX_afe :: anaRxStatus :: rx_pwrdn [07:07] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus4_rx_pwrdn(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x80,7,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus4_rx_pwrdn(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x80,7)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK     0x0080
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT    7

/* SGMII0_RX_afe :: anaRxStatus :: freq_sel [06:06] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus4_freq_sel(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x40,6,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus4_freq_sel(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x40,6)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK     0x0040
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT    6

/* SGMII0_RX_afe :: anaRxStatus :: pll_lock_rstb [05:05] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus4_pll_lock_rstb(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus4_pll_lock_rstb(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x20,5)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5

/* SGMII0_RX_afe :: anaRxStatus :: pwrdn [04:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus4_pwrdn(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus4_pwrdn(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x10,4)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK        0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN       0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS        1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT       4

/* SGMII0_RX_afe :: anaRxStatus :: reserved1 [03:00] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK    0x000f
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS    4
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT   0


/* union - case adc_CdrStatus5 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:00] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK    0xffff
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS    16
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT   0


/* union - case adc_CdrStatus6 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK    0xffe0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS    11
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT   5

/* SGMII0_RX_afe :: anaRxStatus :: rx_reset [04:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_rx_reset(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_rx_reset(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x10,4)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK     0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT    4

/* SGMII0_RX_afe :: anaRxStatus :: rx_pwrdn [03:03] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_rx_pwrdn(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_rx_pwrdn(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x8,3)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK     0x0008
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT    3

/* SGMII0_RX_afe :: anaRxStatus :: reset_anlg [02:02] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_reset_anlg(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_reset_anlg(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x4,2)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK   0x0004
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT  2

/* SGMII0_RX_afe :: anaRxStatus :: pwrdn_rx [01:01] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_rx(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x2,1,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_rx(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x2,1)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK     0x0002
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT    1

/* SGMII0_RX_afe :: anaRxStatus :: pwrdn_pll [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_pll(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_pll(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK    0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS    1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT   0


/* union - case adc_CdrStatus7e [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK   0xffe0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS   11
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT  5

/* SGMII0_RX_afe :: anaRxStatus :: rxck0_even [04:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck0_even(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck0_even(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x10,4)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK  0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS  1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4

/* SGMII0_RX_afe :: anaRxStatus :: rxck1_even [03:03] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck1_even(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck1_even(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x8,3)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK  0x0008
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS  1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3

/* SGMII0_RX_afe :: anaRxStatus :: comdet_even [02:02] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_comdet_even(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_comdet_even(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x4,2)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2

/* SGMII0_RX_afe :: anaRxStatus :: en_cdet_even [01:01] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_en_cdet_even(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x2,1,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_en_cdet_even(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x2,1)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1

/* SGMII0_RX_afe :: anaRxStatus :: comma_adj_en_even [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_comma_adj_en_even(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7e_comma_adj_en_even(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0


/* union - case adc_CdrStatus7o [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK   0xffe0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS   11
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT  5

/* SGMII0_RX_afe :: anaRxStatus :: rxck0_odd [04:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck0_odd(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck0_odd(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x10,4)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK   0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT  4

/* SGMII0_RX_afe :: anaRxStatus :: rxck1_odd [03:03] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck1_odd(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck1_odd(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x8,3)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK   0x0008
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT  3

/* SGMII0_RX_afe :: anaRxStatus :: comdet_odd [02:02] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_comdet_odd(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_comdet_odd(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x4,2)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK  0x0004
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS  1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2

/* SGMII0_RX_afe :: anaRxStatus :: en_cdet_odd [01:01] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_en_cdet_odd(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x2,1,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_en_cdet_odd(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x2,1)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1

/* SGMII0_RX_afe :: anaRxStatus :: comma_adj_en_odd [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_comma_adj_en_odd(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus7o_comma_adj_en_odd(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0


/* union - case adc_CdrStatus8 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:01] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK    0xfffe
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS    15
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT   1

/* SGMII0_RX_afe :: anaRxStatus :: sigdet [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus8_sigdet(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus8_sigdet(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK       0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS       1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT      0


/* union - case adc_CdrStatus9 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:00] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK    0xffff
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS    16
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT   0


/* union - case adc_CdrStatus10 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:07] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK   0xff80
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS   9
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT  7

/* SGMII0_RX_afe :: anaRxStatus :: prbs_en [06:06] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x40,6,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x40,6)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK     0x0040
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS     1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT    6

/* SGMII0_RX_afe :: anaRxStatus :: rstb_tst [05:05] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus10_rstb_tst(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus10_rstb_tst(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x20,5)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK    0x0020
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN   0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS    1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT   5

/* SGMII0_RX_afe :: anaRxStatus :: reserved1 [04:04] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK   0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT  4

/* SGMII0_RX_afe :: anaRxStatus :: prbs_state [03:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_state(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0xf,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_state(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0xf,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK  0x000f
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS  4
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0


/* union - case adc_CdrStatus11 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:00] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK   0xffff
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS   16
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT  0


/* union - case adc_CdrStatus12_1 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:06] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6

/* SGMII0_RX_afe :: anaRxStatus :: enable4 [05:05] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_1_enable4(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_1_enable4(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x20,5)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK   0x0020
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT  5

/* SGMII0_RX_afe :: anaRxStatus :: radr_test [04:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_1_radr_test(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x1f,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_1_radr_test(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x1f,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0


/* union - case adc_CdrStatus12_2 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5

/* SGMII0_RX_afe :: anaRxStatus :: wadr_test [04:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_2_wadr_test(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2,0x1f,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_2_wadr_test(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2,0x1f,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0


/* union - case adc_CdrStatus12_3 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:06] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6

/* SGMII0_RX_afe :: anaRxStatus :: rxck_66B_tmux [05:05] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_66B_tmux(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_66B_tmux(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x20,5)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5

/* SGMII0_RX_afe :: anaRxStatus :: rstb_66B [04:04] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_66B(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_66B(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x10,4)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK  0x0010
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS  1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4

/* SGMII0_RX_afe :: anaRxStatus :: prstb_66B_mux [03:03] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_66B_mux(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_66B_mux(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x8,3)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3

/* SGMII0_RX_afe :: anaRxStatus :: rxck_i66_tmux [02:02] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_i66_tmux(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_i66_tmux(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x4,2)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2

/* SGMII0_RX_afe :: anaRxStatus :: rstb_i66 [01:01] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_i66(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x2,1,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_i66(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x2,1)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK  0x0002
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS  1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1

/* SGMII0_RX_afe :: anaRxStatus :: prstb_i66_mux [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_i66_mux(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_i66_mux(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0


/* union - case adc_CdrStatus12_4 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: reserved0 [15:04] */
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4

/* SGMII0_RX_afe :: anaRxStatus :: rfifo_error_r [03:02] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_error_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0xc,2,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_error_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0xc,2)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2

/* SGMII0_RX_afe :: anaRxStatus :: rfifo_unflow [01:01] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_unflow(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x2,1,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_unflow(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x2,1)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1

/* SGMII0_RX_afe :: anaRxStatus :: rfifo_ovflow [00:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_ovflow(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_ovflow(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x1,0)
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1
#define SGMII0_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0


/* union - case integ_Status [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: integ_status [15:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_integ_Status_integ_status(x) WriteReg16(SGMII0_RX_AFE_ANARXSTATUS_INTEG_STATUS,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_integ_Status_integ_status(x) ReadReg16(SGMII0_RX_AFE_ANARXSTATUS_INTEG_STATUS)
#define SGMII0_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK   0xffff
#define SGMII0_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS   16
#define SGMII0_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT  0


/* union - case vco_Status [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: vco_status [15:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_vco_Status_vco_status(x) WriteReg16(SGMII0_RX_AFE_ANARXSTATUS_VCO_STATUS,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_vco_Status_vco_status(x) ReadReg16(SGMII0_RX_AFE_ANARXSTATUS_VCO_STATUS)
#define SGMII0_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK       0xffff
#define SGMII0_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS       16
#define SGMII0_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT      0


/* union - case prbs_Status [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: prbs_lock [15:15] */
#define Wr_SGMII0_RX_afe_anaRxStatus_prbs_Status_prbs_lock(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x8000,15,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_prbs_Status_prbs_lock(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x8000,15)
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK       0x8000
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS       1
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT      15

/* SGMII0_RX_afe :: anaRxStatus :: prbs_stky [14:14] */
#define Wr_SGMII0_RX_afe_anaRxStatus_prbs_Status_prbs_stky(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x4000,14,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_prbs_Status_prbs_stky(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x4000,14)
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK       0x4000
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS       1
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT      14

/* SGMII0_RX_afe :: anaRxStatus :: prbs_errors [13:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_prbs_Status_prbs_errors(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x3fff,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_prbs_Status_prbs_errors(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x3fff,0)
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_MASK     0x3fff
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_ALIGN    0
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_BITS     14
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_SHIFT    0


/* union - case prbs_Status_1 [15:00] */
/* SGMII0_RX_afe :: anaRxStatus :: sync_status [15:15] */
#define Wr_SGMII0_RX_afe_anaRxStatus_prbs_Status_1_sync_status(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x8000,15,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_prbs_Status_1_sync_status(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x8000,15)
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_MASK   0x8000
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_ALIGN  0
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_BITS   1
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_SHIFT  15

/* SGMII0_RX_afe :: anaRxStatus :: E_count [14:00] */
#define Wr_SGMII0_RX_afe_anaRxStatus_prbs_Status_1_E_count(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x7fff,0,x)
#define Rd_SGMII0_RX_afe_anaRxStatus_prbs_Status_1_E_count(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x7fff,0)
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_MASK       0x7fff
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_ALIGN      0
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_BITS       15
#define SGMII0_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_SHIFT      0



/****************************************************************************
 * SGMII0_RX_afe :: anaRxControl
 ***************************************************************************/
/* SGMII0_RX_afe :: anaRxControl :: rxSeqRestart_SM [15:15] */
#define Wr_SGMII0_RX_afe_anaRxControl_rxSeqRestart_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x8000,15,x)
#define Rd_SGMII0_RX_afe_anaRxControl_rxSeqRestart_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x8000,15)
#define SGMII0_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_MASK            0x8000
#define SGMII0_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_ALIGN           0
#define SGMII0_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_BITS            1
#define SGMII0_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_SHIFT           15

/* SGMII0_RX_afe :: anaRxControl :: fast_acq_en_r [14:14] */
#define Wr_SGMII0_RX_afe_anaRxControl_fast_acq_en_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x4000,14,x)
#define Rd_SGMII0_RX_afe_anaRxControl_fast_acq_en_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x4000,14)
#define SGMII0_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_MASK              0x4000
#define SGMII0_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_ALIGN             0
#define SGMII0_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_BITS              1
#define SGMII0_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_SHIFT             14

/* SGMII0_RX_afe :: anaRxControl :: fast_acq_en_force_r [13:13] */
#define Wr_SGMII0_RX_afe_anaRxControl_fast_acq_en_force_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x2000,13,x)
#define Rd_SGMII0_RX_afe_anaRxControl_fast_acq_en_force_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x2000,13)
#define SGMII0_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_MASK        0x2000
#define SGMII0_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_ALIGN       0
#define SGMII0_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_BITS        1
#define SGMII0_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_SHIFT       13

/* SGMII0_RX_afe :: anaRxControl :: sigDetected_en_SM [12:12] */
#define Wr_SGMII0_RX_afe_anaRxControl_sigDetected_en_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x1000,12,x)
#define Rd_SGMII0_RX_afe_anaRxControl_sigDetected_en_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x1000,12)
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_MASK          0x1000
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_ALIGN         0
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_BITS          1
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_SHIFT         12

/* SGMII0_RX_afe :: anaRxControl :: sigdetRestart_en_SM [11:11] */
#define Wr_SGMII0_RX_afe_anaRxControl_sigdetRestart_en_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x800,11,x)
#define Rd_SGMII0_RX_afe_anaRxControl_sigdetRestart_en_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x800,11)
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_MASK        0x0800
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_ALIGN       0
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_BITS        1
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_SHIFT       11

/* SGMII0_RX_afe :: anaRxControl :: sigdetMonitor_en_SM [10:10] */
#define Wr_SGMII0_RX_afe_anaRxControl_sigdetMonitor_en_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x400,10,x)
#define Rd_SGMII0_RX_afe_anaRxControl_sigdetMonitor_en_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x400,10)
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_MASK        0x0400
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_ALIGN       0
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_BITS        1
#define SGMII0_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_SHIFT       10

/* SGMII0_RX_afe :: anaRxControl :: override_sigdet_en [09:09] */
#define Wr_SGMII0_RX_afe_anaRxControl_override_sigdet_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x200,9,x)
#define Rd_SGMII0_RX_afe_anaRxControl_override_sigdet_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x200,9)
#define SGMII0_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK         0x0200
#define SGMII0_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN        0
#define SGMII0_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS         1
#define SGMII0_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT        9

/* SGMII0_RX_afe :: anaRxControl :: override_sigdet_val [08:08] */
#define Wr_SGMII0_RX_afe_anaRxControl_override_sigdet_val(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x100,8,x)
#define Rd_SGMII0_RX_afe_anaRxControl_override_sigdet_val(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x100,8)
#define SGMII0_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK        0x0100
#define SGMII0_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN       0
#define SGMII0_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS        1
#define SGMII0_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT       8

/* SGMII0_RX_afe :: anaRxControl :: reserved0 [07:07] */
#define SGMII0_RX_AFE_ANARXCONTROL_RESERVED0_MASK                  0x0080
#define SGMII0_RX_AFE_ANARXCONTROL_RESERVED0_ALIGN                 0
#define SGMII0_RX_AFE_ANARXCONTROL_RESERVED0_BITS                  1
#define SGMII0_RX_AFE_ANARXCONTROL_RESERVED0_SHIFT                 7

/* SGMII0_RX_afe :: anaRxControl :: phfreq_rst_dis_fst_SM [06:06] */
#define Wr_SGMII0_RX_afe_anaRxControl_phfreq_rst_dis_fst_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x40,6,x)
#define Rd_SGMII0_RX_afe_anaRxControl_phfreq_rst_dis_fst_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x40,6)
#define SGMII0_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_MASK      0x0040
#define SGMII0_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_ALIGN     0
#define SGMII0_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_BITS      1
#define SGMII0_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_SHIFT     6

/* SGMII0_RX_afe :: anaRxControl :: phfreq_rst_dis_nrml_SM [05:05] */
#define Wr_SGMII0_RX_afe_anaRxControl_phfreq_rst_dis_nrml_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxControl_phfreq_rst_dis_nrml_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x20,5)
#define SGMII0_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_MASK     0x0020
#define SGMII0_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_ALIGN    0
#define SGMII0_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_BITS     1
#define SGMII0_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_SHIFT    5

/* SGMII0_RX_afe :: anaRxControl :: forceRxSeqDone_SM [04:04] */
#define Wr_SGMII0_RX_afe_anaRxControl_forceRxSeqDone_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxControl_forceRxSeqDone_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x10,4)
#define SGMII0_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_MASK          0x0010
#define SGMII0_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_ALIGN         0
#define SGMII0_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_BITS          1
#define SGMII0_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_SHIFT         4

/* SGMII0_RX_afe :: anaRxControl :: flip_eyemon_polarity [03:03] */
#define Wr_SGMII0_RX_afe_anaRxControl_flip_eyemon_polarity(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxControl_flip_eyemon_polarity(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x8,3)
#define SGMII0_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_MASK       0x0008
#define SGMII0_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_ALIGN      0
#define SGMII0_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_BITS       1
#define SGMII0_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_SHIFT      3

/* SGMII0_RX_afe :: anaRxControl :: status_sel [02:00] */
#define Wr_SGMII0_RX_afe_anaRxControl_status_sel(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x7,0,x)
#define Rd_SGMII0_RX_afe_anaRxControl_status_sel(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL,0x7,0)
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_MASK                 0x0007
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_ALIGN                0
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_BITS                 3
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_SHIFT                0
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_sigdetStatus         0
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_syncStatus           1
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_rxTestSel            2
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_scaleStatus          3
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_adcCdrStatus         4
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_integStatus          5
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_vcoStatus            6
#define SGMII0_RX_AFE_ANARXCONTROL_STATUS_SEL_prbsStatus           7


/****************************************************************************
 * SGMII0_RX_afe :: ctrl0
 ***************************************************************************/
/* SGMII0_RX_afe :: ctrl0 :: slicer_pd [15:15] */
#define Wr_SGMII0_RX_afe_ctrl0_slicer_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL0,0x8000,15,x)
#define Rd_SGMII0_RX_afe_ctrl0_slicer_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL0,0x8000,15)
#define SGMII0_RX_AFE_CTRL0_SLICER_PD_MASK                         0x8000
#define SGMII0_RX_AFE_CTRL0_SLICER_PD_ALIGN                        0
#define SGMII0_RX_AFE_CTRL0_SLICER_PD_BITS                         1
#define SGMII0_RX_AFE_CTRL0_SLICER_PD_SHIFT                        15

/* SGMII0_RX_afe :: ctrl0 :: reserved_14_12 [14:12] */
#define SGMII0_RX_AFE_CTRL0_RESERVED_14_12_MASK                    0x7000
#define SGMII0_RX_AFE_CTRL0_RESERVED_14_12_ALIGN                   0
#define SGMII0_RX_AFE_CTRL0_RESERVED_14_12_BITS                    3
#define SGMII0_RX_AFE_CTRL0_RESERVED_14_12_SHIFT                   12

/* SGMII0_RX_afe :: ctrl0 :: RX_pon [11:08] */
#define Wr_SGMII0_RX_afe_ctrl0_RX_pon(x) WriteRegBits16(SGMII0_RX_AFE_CTRL0,0xf00,8,x)
#define Rd_SGMII0_RX_afe_ctrl0_RX_pon(x) ReadRegBits16(SGMII0_RX_AFE_CTRL0,0xf00,8)
#define SGMII0_RX_AFE_CTRL0_RX_PON_MASK                            0x0f00
#define SGMII0_RX_AFE_CTRL0_RX_PON_ALIGN                           0
#define SGMII0_RX_AFE_CTRL0_RX_PON_BITS                            4
#define SGMII0_RX_AFE_CTRL0_RX_PON_SHIFT                           8

/* SGMII0_RX_afe :: ctrl0 :: Filter_band [07:06] */
#define Wr_SGMII0_RX_afe_ctrl0_Filter_band(x) WriteRegBits16(SGMII0_RX_AFE_CTRL0,0xc0,6,x)
#define Rd_SGMII0_RX_afe_ctrl0_Filter_band(x) ReadRegBits16(SGMII0_RX_AFE_CTRL0,0xc0,6)
#define SGMII0_RX_AFE_CTRL0_FILTER_BAND_MASK                       0x00c0
#define SGMII0_RX_AFE_CTRL0_FILTER_BAND_ALIGN                      0
#define SGMII0_RX_AFE_CTRL0_FILTER_BAND_BITS                       2
#define SGMII0_RX_AFE_CTRL0_FILTER_BAND_SHIFT                      6

/* SGMII0_RX_afe :: ctrl0 :: reserved_5_3 [05:03] */
#define SGMII0_RX_AFE_CTRL0_RESERVED_5_3_MASK                      0x0038
#define SGMII0_RX_AFE_CTRL0_RESERVED_5_3_ALIGN                     0
#define SGMII0_RX_AFE_CTRL0_RESERVED_5_3_BITS                      3
#define SGMII0_RX_AFE_CTRL0_RESERVED_5_3_SHIFT                     3

/* SGMII0_RX_afe :: ctrl0 :: pd_lmtng [02:02] */
#define Wr_SGMII0_RX_afe_ctrl0_pd_lmtng(x) WriteRegBits16(SGMII0_RX_AFE_CTRL0,0x4,2,x)
#define Rd_SGMII0_RX_afe_ctrl0_pd_lmtng(x) ReadRegBits16(SGMII0_RX_AFE_CTRL0,0x4,2)
#define SGMII0_RX_AFE_CTRL0_PD_LMTNG_MASK                          0x0004
#define SGMII0_RX_AFE_CTRL0_PD_LMTNG_ALIGN                         0
#define SGMII0_RX_AFE_CTRL0_PD_LMTNG_BITS                          1
#define SGMII0_RX_AFE_CTRL0_PD_LMTNG_SHIFT                         2

/* SGMII0_RX_afe :: ctrl0 :: pd_eqz [01:01] */
#define Wr_SGMII0_RX_afe_ctrl0_pd_eqz(x) WriteRegBits16(SGMII0_RX_AFE_CTRL0,0x2,1,x)
#define Rd_SGMII0_RX_afe_ctrl0_pd_eqz(x) ReadRegBits16(SGMII0_RX_AFE_CTRL0,0x2,1)
#define SGMII0_RX_AFE_CTRL0_PD_EQZ_MASK                            0x0002
#define SGMII0_RX_AFE_CTRL0_PD_EQZ_ALIGN                           0
#define SGMII0_RX_AFE_CTRL0_PD_EQZ_BITS                            1
#define SGMII0_RX_AFE_CTRL0_PD_EQZ_SHIFT                           1

/* SGMII0_RX_afe :: ctrl0 :: reserved_0 [00:00] */
#define SGMII0_RX_AFE_CTRL0_RESERVED_0_MASK                        0x0001
#define SGMII0_RX_AFE_CTRL0_RESERVED_0_ALIGN                       0
#define SGMII0_RX_AFE_CTRL0_RESERVED_0_BITS                        1
#define SGMII0_RX_AFE_CTRL0_RESERVED_0_SHIFT                       0


/****************************************************************************
 * SGMII0_RX_afe :: ctrl1
 ***************************************************************************/
/* SGMII0_RX_afe :: ctrl1 :: demux_eyem_pd [15:15] */
#define Wr_SGMII0_RX_afe_ctrl1_demux_eyem_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL1,0x8000,15,x)
#define Rd_SGMII0_RX_afe_ctrl1_demux_eyem_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL1,0x8000,15)
#define SGMII0_RX_AFE_CTRL1_DEMUX_EYEM_PD_MASK                     0x8000
#define SGMII0_RX_AFE_CTRL1_DEMUX_EYEM_PD_ALIGN                    0
#define SGMII0_RX_AFE_CTRL1_DEMUX_EYEM_PD_BITS                     1
#define SGMII0_RX_AFE_CTRL1_DEMUX_EYEM_PD_SHIFT                    15

/* SGMII0_RX_afe :: ctrl1 :: demux_pd [14:14] */
#define Wr_SGMII0_RX_afe_ctrl1_demux_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL1,0x4000,14,x)
#define Rd_SGMII0_RX_afe_ctrl1_demux_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL1,0x4000,14)
#define SGMII0_RX_AFE_CTRL1_DEMUX_PD_MASK                          0x4000
#define SGMII0_RX_AFE_CTRL1_DEMUX_PD_ALIGN                         0
#define SGMII0_RX_AFE_CTRL1_DEMUX_PD_BITS                          1
#define SGMII0_RX_AFE_CTRL1_DEMUX_PD_SHIFT                         14

/* SGMII0_RX_afe :: ctrl1 :: demux_peak_pd [13:13] */
#define Wr_SGMII0_RX_afe_ctrl1_demux_peak_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL1,0x2000,13,x)
#define Rd_SGMII0_RX_afe_ctrl1_demux_peak_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL1,0x2000,13)
#define SGMII0_RX_AFE_CTRL1_DEMUX_PEAK_PD_MASK                     0x2000
#define SGMII0_RX_AFE_CTRL1_DEMUX_PEAK_PD_ALIGN                    0
#define SGMII0_RX_AFE_CTRL1_DEMUX_PEAK_PD_BITS                     1
#define SGMII0_RX_AFE_CTRL1_DEMUX_PEAK_PD_SHIFT                    13

/* SGMII0_RX_afe :: ctrl1 :: demux_zero_pd [12:12] */
#define Wr_SGMII0_RX_afe_ctrl1_demux_zero_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL1,0x1000,12,x)
#define Rd_SGMII0_RX_afe_ctrl1_demux_zero_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL1,0x1000,12)
#define SGMII0_RX_AFE_CTRL1_DEMUX_ZERO_PD_MASK                     0x1000
#define SGMII0_RX_AFE_CTRL1_DEMUX_ZERO_PD_ALIGN                    0
#define SGMII0_RX_AFE_CTRL1_DEMUX_ZERO_PD_BITS                     1
#define SGMII0_RX_AFE_CTRL1_DEMUX_ZERO_PD_SHIFT                    12

/* SGMII0_RX_afe :: ctrl1 :: div_4_demux_enable [11:11] */
#define Wr_SGMII0_RX_afe_ctrl1_div_4_demux_enable(x) WriteRegBits16(SGMII0_RX_AFE_CTRL1,0x800,11,x)
#define Rd_SGMII0_RX_afe_ctrl1_div_4_demux_enable(x) ReadRegBits16(SGMII0_RX_AFE_CTRL1,0x800,11)
#define SGMII0_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_MASK                0x0800
#define SGMII0_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_ALIGN               0
#define SGMII0_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_BITS                1
#define SGMII0_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_SHIFT               11

/* SGMII0_RX_afe :: ctrl1 :: reserved_26_17 [10:01] */
#define SGMII0_RX_AFE_CTRL1_RESERVED_26_17_MASK                    0x07fe
#define SGMII0_RX_AFE_CTRL1_RESERVED_26_17_ALIGN                   0
#define SGMII0_RX_AFE_CTRL1_RESERVED_26_17_BITS                    10
#define SGMII0_RX_AFE_CTRL1_RESERVED_26_17_SHIFT                   1

/* SGMII0_RX_afe :: ctrl1 :: eyem_pd [00:00] */
#define Wr_SGMII0_RX_afe_ctrl1_eyem_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL1,0x1,0,x)
#define Rd_SGMII0_RX_afe_ctrl1_eyem_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL1,0x1,0)
#define SGMII0_RX_AFE_CTRL1_EYEM_PD_MASK                           0x0001
#define SGMII0_RX_AFE_CTRL1_EYEM_PD_ALIGN                          0
#define SGMII0_RX_AFE_CTRL1_EYEM_PD_BITS                           1
#define SGMII0_RX_AFE_CTRL1_EYEM_PD_SHIFT                          0


/****************************************************************************
 * SGMII0_RX_afe :: anaRxSigdet
 ***************************************************************************/
/* SGMII0_RX_afe :: anaRxSigdet :: reserved0 [15:08] */
#define SGMII0_RX_AFE_ANARXSIGDET_RESERVED0_MASK                   0xff00
#define SGMII0_RX_AFE_ANARXSIGDET_RESERVED0_ALIGN                  0
#define SGMII0_RX_AFE_ANARXSIGDET_RESERVED0_BITS                   8
#define SGMII0_RX_AFE_ANARXSIGDET_RESERVED0_SHIFT                  8

/* SGMII0_RX_afe :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */
#define Wr_SGMII0_RX_afe_anaRxSigdet_cx4_sigdet_cnt_ld_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x80,7,x)
#define Rd_SGMII0_RX_afe_anaRxSigdet_cx4_sigdet_cnt_ld_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x80,7)
#define SGMII0_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK        0x0080
#define SGMII0_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN       0
#define SGMII0_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS        1
#define SGMII0_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT       7

/* SGMII0_RX_afe :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */
#define Wr_SGMII0_RX_afe_anaRxSigdet_ext_sigdet_en_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x40,6,x)
#define Rd_SGMII0_RX_afe_anaRxSigdet_ext_sigdet_en_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x40,6)
#define SGMII0_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK            0x0040
#define SGMII0_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN           0
#define SGMII0_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS            1
#define SGMII0_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT           6

/* SGMII0_RX_afe :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */
#define Wr_SGMII0_RX_afe_anaRxSigdet_cx4_sigdet_en_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxSigdet_cx4_sigdet_en_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x20,5)
#define SGMII0_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK            0x0020
#define SGMII0_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN           0
#define SGMII0_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS            1
#define SGMII0_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT           5

/* SGMII0_RX_afe :: anaRxSigdet :: rx_sigdet_r [04:04] */
#define Wr_SGMII0_RX_afe_anaRxSigdet_rx_sigdet_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxSigdet_rx_sigdet_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x10,4)
#define SGMII0_RX_AFE_ANARXSIGDET_RX_SIGDET_R_MASK                 0x0010
#define SGMII0_RX_AFE_ANARXSIGDET_RX_SIGDET_R_ALIGN                0
#define SGMII0_RX_AFE_ANARXSIGDET_RX_SIGDET_R_BITS                 1
#define SGMII0_RX_AFE_ANARXSIGDET_RX_SIGDET_R_SHIFT                4

/* SGMII0_RX_afe :: anaRxSigdet :: rx_sigdet_force_r [03:03] */
#define Wr_SGMII0_RX_afe_anaRxSigdet_rx_sigdet_force_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxSigdet_rx_sigdet_force_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x8,3)
#define SGMII0_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK           0x0008
#define SGMII0_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN          0
#define SGMII0_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS           1
#define SGMII0_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT          3

/* SGMII0_RX_afe :: anaRxSigdet :: invert_rx_sigdet [02:02] */
#define Wr_SGMII0_RX_afe_anaRxSigdet_invert_rx_sigdet(x) WriteRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxSigdet_invert_rx_sigdet(x) ReadRegBits16(SGMII0_RX_AFE_ANARXSIGDET,0x4,2)
#define SGMII0_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_MASK            0x0004
#define SGMII0_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN           0
#define SGMII0_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_BITS            1
#define SGMII0_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT           2

/* SGMII0_RX_afe :: anaRxSigdet :: reserved1 [01:00] */
#define SGMII0_RX_AFE_ANARXSIGDET_RESERVED1_MASK                   0x0003
#define SGMII0_RX_AFE_ANARXSIGDET_RESERVED1_ALIGN                  0
#define SGMII0_RX_AFE_ANARXSIGDET_RESERVED1_BITS                   2
#define SGMII0_RX_AFE_ANARXSIGDET_RESERVED1_SHIFT                  0


/****************************************************************************
 * SGMII0_RX_afe :: ctrl2
 ***************************************************************************/
/* SGMII0_RX_afe :: ctrl2 :: reserved_47_39 [15:07] */
#define SGMII0_RX_AFE_CTRL2_RESERVED_47_39_MASK                    0xff80
#define SGMII0_RX_AFE_CTRL2_RESERVED_47_39_ALIGN                   0
#define SGMII0_RX_AFE_CTRL2_RESERVED_47_39_BITS                    9
#define SGMII0_RX_AFE_CTRL2_RESERVED_47_39_SHIFT                   7

/* SGMII0_RX_afe :: ctrl2 :: inputerm_lowZvdd_en [06:06] */
#define Wr_SGMII0_RX_afe_ctrl2_inputerm_lowZvdd_en(x) WriteRegBits16(SGMII0_RX_AFE_CTRL2,0x40,6,x)
#define Rd_SGMII0_RX_afe_ctrl2_inputerm_lowZvdd_en(x) ReadRegBits16(SGMII0_RX_AFE_CTRL2,0x40,6)
#define SGMII0_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_MASK               0x0040
#define SGMII0_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_ALIGN              0
#define SGMII0_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_BITS               1
#define SGMII0_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_SHIFT              6

/* SGMII0_RX_afe :: ctrl2 :: inputerm_lowZgnd_en [05:05] */
#define Wr_SGMII0_RX_afe_ctrl2_inputerm_lowZgnd_en(x) WriteRegBits16(SGMII0_RX_AFE_CTRL2,0x20,5,x)
#define Rd_SGMII0_RX_afe_ctrl2_inputerm_lowZgnd_en(x) ReadRegBits16(SGMII0_RX_AFE_CTRL2,0x20,5)
#define SGMII0_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_MASK               0x0020
#define SGMII0_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_ALIGN              0
#define SGMII0_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_BITS               1
#define SGMII0_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_SHIFT              5

/* SGMII0_RX_afe :: ctrl2 :: inputerm_cmult_en [04:04] */
#define Wr_SGMII0_RX_afe_ctrl2_inputerm_cmult_en(x) WriteRegBits16(SGMII0_RX_AFE_CTRL2,0x10,4,x)
#define Rd_SGMII0_RX_afe_ctrl2_inputerm_cmult_en(x) ReadRegBits16(SGMII0_RX_AFE_CTRL2,0x10,4)
#define SGMII0_RX_AFE_CTRL2_INPUTERM_CMULT_EN_MASK                 0x0010
#define SGMII0_RX_AFE_CTRL2_INPUTERM_CMULT_EN_ALIGN                0
#define SGMII0_RX_AFE_CTRL2_INPUTERM_CMULT_EN_BITS                 1
#define SGMII0_RX_AFE_CTRL2_INPUTERM_CMULT_EN_SHIFT                4

/* SGMII0_RX_afe :: ctrl2 :: inputerm_cm_en [03:03] */
#define Wr_SGMII0_RX_afe_ctrl2_inputerm_cm_en(x) WriteRegBits16(SGMII0_RX_AFE_CTRL2,0x8,3,x)
#define Rd_SGMII0_RX_afe_ctrl2_inputerm_cm_en(x) ReadRegBits16(SGMII0_RX_AFE_CTRL2,0x8,3)
#define SGMII0_RX_AFE_CTRL2_INPUTERM_CM_EN_MASK                    0x0008
#define SGMII0_RX_AFE_CTRL2_INPUTERM_CM_EN_ALIGN                   0
#define SGMII0_RX_AFE_CTRL2_INPUTERM_CM_EN_BITS                    1
#define SGMII0_RX_AFE_CTRL2_INPUTERM_CM_EN_SHIFT                   3

/* SGMII0_RX_afe :: ctrl2 :: div10_pd [02:02] */
#define Wr_SGMII0_RX_afe_ctrl2_div10_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL2,0x4,2,x)
#define Rd_SGMII0_RX_afe_ctrl2_div10_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL2,0x4,2)
#define SGMII0_RX_AFE_CTRL2_DIV10_PD_MASK                          0x0004
#define SGMII0_RX_AFE_CTRL2_DIV10_PD_ALIGN                         0
#define SGMII0_RX_AFE_CTRL2_DIV10_PD_BITS                          1
#define SGMII0_RX_AFE_CTRL2_DIV10_PD_SHIFT                         2

/* SGMII0_RX_afe :: ctrl2 :: div4_pd [01:01] */
#define Wr_SGMII0_RX_afe_ctrl2_div4_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL2,0x2,1,x)
#define Rd_SGMII0_RX_afe_ctrl2_div4_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL2,0x2,1)
#define SGMII0_RX_AFE_CTRL2_DIV4_PD_MASK                           0x0002
#define SGMII0_RX_AFE_CTRL2_DIV4_PD_ALIGN                          0
#define SGMII0_RX_AFE_CTRL2_DIV4_PD_BITS                           1
#define SGMII0_RX_AFE_CTRL2_DIV4_PD_SHIFT                          1

/* SGMII0_RX_afe :: ctrl2 :: reserved_32 [00:00] */
#define SGMII0_RX_AFE_CTRL2_RESERVED_32_MASK                       0x0001
#define SGMII0_RX_AFE_CTRL2_RESERVED_32_ALIGN                      0
#define SGMII0_RX_AFE_CTRL2_RESERVED_32_BITS                       1
#define SGMII0_RX_AFE_CTRL2_RESERVED_32_SHIFT                      0


/****************************************************************************
 * SGMII0_RX_afe :: ctrl3
 ***************************************************************************/
/* SGMII0_RX_afe :: ctrl3 :: reserved_63_58 [15:10] */
#define SGMII0_RX_AFE_CTRL3_RESERVED_63_58_MASK                    0xfc00
#define SGMII0_RX_AFE_CTRL3_RESERVED_63_58_ALIGN                   0
#define SGMII0_RX_AFE_CTRL3_RESERVED_63_58_BITS                    6
#define SGMII0_RX_AFE_CTRL3_RESERVED_63_58_SHIFT                   10

/* SGMII0_RX_afe :: ctrl3 :: pd_bias [09:09] */
#define Wr_SGMII0_RX_afe_ctrl3_pd_bias(x) WriteRegBits16(SGMII0_RX_AFE_CTRL3,0x200,9,x)
#define Rd_SGMII0_RX_afe_ctrl3_pd_bias(x) ReadRegBits16(SGMII0_RX_AFE_CTRL3,0x200,9)
#define SGMII0_RX_AFE_CTRL3_PD_BIAS_MASK                           0x0200
#define SGMII0_RX_AFE_CTRL3_PD_BIAS_ALIGN                          0
#define SGMII0_RX_AFE_CTRL3_PD_BIAS_BITS                           1
#define SGMII0_RX_AFE_CTRL3_PD_BIAS_SHIFT                          9

/* SGMII0_RX_afe :: ctrl3 :: Duty_Cycle [08:06] */
#define Wr_SGMII0_RX_afe_ctrl3_Duty_Cycle(x) WriteRegBits16(SGMII0_RX_AFE_CTRL3,0x1c0,6,x)
#define Rd_SGMII0_RX_afe_ctrl3_Duty_Cycle(x) ReadRegBits16(SGMII0_RX_AFE_CTRL3,0x1c0,6)
#define SGMII0_RX_AFE_CTRL3_DUTY_CYCLE_MASK                        0x01c0
#define SGMII0_RX_AFE_CTRL3_DUTY_CYCLE_ALIGN                       0
#define SGMII0_RX_AFE_CTRL3_DUTY_CYCLE_BITS                        3
#define SGMII0_RX_AFE_CTRL3_DUTY_CYCLE_SHIFT                       6

/* SGMII0_RX_afe :: ctrl3 :: Dcc_en [05:05] */
#define Wr_SGMII0_RX_afe_ctrl3_Dcc_en(x) WriteRegBits16(SGMII0_RX_AFE_CTRL3,0x20,5,x)
#define Rd_SGMII0_RX_afe_ctrl3_Dcc_en(x) ReadRegBits16(SGMII0_RX_AFE_CTRL3,0x20,5)
#define SGMII0_RX_AFE_CTRL3_DCC_EN_MASK                            0x0020
#define SGMII0_RX_AFE_CTRL3_DCC_EN_ALIGN                           0
#define SGMII0_RX_AFE_CTRL3_DCC_EN_BITS                            1
#define SGMII0_RX_AFE_CTRL3_DCC_EN_SHIFT                           5

/* SGMII0_RX_afe :: ctrl3 :: reserved_52_48 [04:00] */
#define SGMII0_RX_AFE_CTRL3_RESERVED_52_48_MASK                    0x001f
#define SGMII0_RX_AFE_CTRL3_RESERVED_52_48_ALIGN                   0
#define SGMII0_RX_AFE_CTRL3_RESERVED_52_48_BITS                    5
#define SGMII0_RX_AFE_CTRL3_RESERVED_52_48_SHIFT                   0


/****************************************************************************
 * SGMII0_RX_afe :: ctrl4
 ***************************************************************************/
/* SGMII0_RX_afe :: ctrl4 :: en_testmux [15:15] */
#define Wr_SGMII0_RX_afe_ctrl4_en_testmux(x) WriteRegBits16(SGMII0_RX_AFE_CTRL4,0x8000,15,x)
#define Rd_SGMII0_RX_afe_ctrl4_en_testmux(x) ReadRegBits16(SGMII0_RX_AFE_CTRL4,0x8000,15)
#define SGMII0_RX_AFE_CTRL4_EN_TESTMUX_MASK                        0x8000
#define SGMII0_RX_AFE_CTRL4_EN_TESTMUX_ALIGN                       0
#define SGMII0_RX_AFE_CTRL4_EN_TESTMUX_BITS                        1
#define SGMII0_RX_AFE_CTRL4_EN_TESTMUX_SHIFT                       15

/* SGMII0_RX_afe :: ctrl4 :: Sigdet_modeselect [14:14] */
#define Wr_SGMII0_RX_afe_ctrl4_Sigdet_modeselect(x) WriteRegBits16(SGMII0_RX_AFE_CTRL4,0x4000,14,x)
#define Rd_SGMII0_RX_afe_ctrl4_Sigdet_modeselect(x) ReadRegBits16(SGMII0_RX_AFE_CTRL4,0x4000,14)
#define SGMII0_RX_AFE_CTRL4_SIGDET_MODESELECT_MASK                 0x4000
#define SGMII0_RX_AFE_CTRL4_SIGDET_MODESELECT_ALIGN                0
#define SGMII0_RX_AFE_CTRL4_SIGDET_MODESELECT_BITS                 1
#define SGMII0_RX_AFE_CTRL4_SIGDET_MODESELECT_SHIFT                14

/* SGMII0_RX_afe :: ctrl4 :: sigdet_pd [13:13] */
#define Wr_SGMII0_RX_afe_ctrl4_sigdet_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL4,0x2000,13,x)
#define Rd_SGMII0_RX_afe_ctrl4_sigdet_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL4,0x2000,13)
#define SGMII0_RX_AFE_CTRL4_SIGDET_PD_MASK                         0x2000
#define SGMII0_RX_AFE_CTRL4_SIGDET_PD_ALIGN                        0
#define SGMII0_RX_AFE_CTRL4_SIGDET_PD_BITS                         1
#define SGMII0_RX_AFE_CTRL4_SIGDET_PD_SHIFT                        13

/* SGMII0_RX_afe :: ctrl4 :: sigdet_bypass [12:12] */
#define Wr_SGMII0_RX_afe_ctrl4_sigdet_bypass(x) WriteRegBits16(SGMII0_RX_AFE_CTRL4,0x1000,12,x)
#define Rd_SGMII0_RX_afe_ctrl4_sigdet_bypass(x) ReadRegBits16(SGMII0_RX_AFE_CTRL4,0x1000,12)
#define SGMII0_RX_AFE_CTRL4_SIGDET_BYPASS_MASK                     0x1000
#define SGMII0_RX_AFE_CTRL4_SIGDET_BYPASS_ALIGN                    0
#define SGMII0_RX_AFE_CTRL4_SIGDET_BYPASS_BITS                     1
#define SGMII0_RX_AFE_CTRL4_SIGDET_BYPASS_SHIFT                    12

/* SGMII0_RX_afe :: ctrl4 :: bias_sigdet_ctrl [11:09] */
#define Wr_SGMII0_RX_afe_ctrl4_bias_sigdet_ctrl(x) WriteRegBits16(SGMII0_RX_AFE_CTRL4,0xe00,9,x)
#define Rd_SGMII0_RX_afe_ctrl4_bias_sigdet_ctrl(x) ReadRegBits16(SGMII0_RX_AFE_CTRL4,0xe00,9)
#define SGMII0_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_MASK                  0x0e00
#define SGMII0_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_ALIGN                 0
#define SGMII0_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_BITS                  3
#define SGMII0_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_SHIFT                 9

/* SGMII0_RX_afe :: ctrl4 :: bias_eyem_ctrl [08:06] */
#define Wr_SGMII0_RX_afe_ctrl4_bias_eyem_ctrl(x) WriteRegBits16(SGMII0_RX_AFE_CTRL4,0x1c0,6,x)
#define Rd_SGMII0_RX_afe_ctrl4_bias_eyem_ctrl(x) ReadRegBits16(SGMII0_RX_AFE_CTRL4,0x1c0,6)
#define SGMII0_RX_AFE_CTRL4_BIAS_EYEM_CTRL_MASK                    0x01c0
#define SGMII0_RX_AFE_CTRL4_BIAS_EYEM_CTRL_ALIGN                   0
#define SGMII0_RX_AFE_CTRL4_BIAS_EYEM_CTRL_BITS                    3
#define SGMII0_RX_AFE_CTRL4_BIAS_EYEM_CTRL_SHIFT                   6

/* SGMII0_RX_afe :: ctrl4 :: bias_la_dac_ctrl [05:03] */
#define Wr_SGMII0_RX_afe_ctrl4_bias_la_dac_ctrl(x) WriteRegBits16(SGMII0_RX_AFE_CTRL4,0x38,3,x)
#define Rd_SGMII0_RX_afe_ctrl4_bias_la_dac_ctrl(x) ReadRegBits16(SGMII0_RX_AFE_CTRL4,0x38,3)
#define SGMII0_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_MASK                  0x0038
#define SGMII0_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_ALIGN                 0
#define SGMII0_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_BITS                  3
#define SGMII0_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_SHIFT                 3

/* SGMII0_RX_afe :: ctrl4 :: bias_la_ctrl [02:00] */
#define Wr_SGMII0_RX_afe_ctrl4_bias_la_ctrl(x) WriteRegBits16(SGMII0_RX_AFE_CTRL4,0x7,0,x)
#define Rd_SGMII0_RX_afe_ctrl4_bias_la_ctrl(x) ReadRegBits16(SGMII0_RX_AFE_CTRL4,0x7,0)
#define SGMII0_RX_AFE_CTRL4_BIAS_LA_CTRL_MASK                      0x0007
#define SGMII0_RX_AFE_CTRL4_BIAS_LA_CTRL_ALIGN                     0
#define SGMII0_RX_AFE_CTRL4_BIAS_LA_CTRL_BITS                      3
#define SGMII0_RX_AFE_CTRL4_BIAS_LA_CTRL_SHIFT                     0


/****************************************************************************
 * SGMII0_RX_afe :: anaRxTest
 ***************************************************************************/
/* SGMII0_RX_afe :: anaRxTest :: sigdet_mux_SM [15:12] */
#define Wr_SGMII0_RX_afe_anaRxTest_sigdet_mux_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXTEST,0xf000,12,x)
#define Rd_SGMII0_RX_afe_anaRxTest_sigdet_mux_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXTEST,0xf000,12)
#define SGMII0_RX_AFE_ANARXTEST_SIGDET_MUX_SM_MASK                 0xf000
#define SGMII0_RX_AFE_ANARXTEST_SIGDET_MUX_SM_ALIGN                0
#define SGMII0_RX_AFE_ANARXTEST_SIGDET_MUX_SM_BITS                 4
#define SGMII0_RX_AFE_ANARXTEST_SIGDET_MUX_SM_SHIFT                12

/* SGMII0_RX_afe :: anaRxTest :: reserved0 [11:09] */
#define SGMII0_RX_AFE_ANARXTEST_RESERVED0_MASK                     0x0e00
#define SGMII0_RX_AFE_ANARXTEST_RESERVED0_ALIGN                    0
#define SGMII0_RX_AFE_ANARXTEST_RESERVED0_BITS                     3
#define SGMII0_RX_AFE_ANARXTEST_RESERVED0_SHIFT                    9

/* SGMII0_RX_afe :: anaRxTest :: tpctrl_SM [08:04] */
#define Wr_SGMII0_RX_afe_anaRxTest_tpctrl_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXTEST,0x1f0,4,x)
#define Rd_SGMII0_RX_afe_anaRxTest_tpctrl_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXTEST,0x1f0,4)
#define SGMII0_RX_AFE_ANARXTEST_TPCTRL_SM_MASK                     0x01f0
#define SGMII0_RX_AFE_ANARXTEST_TPCTRL_SM_ALIGN                    0
#define SGMII0_RX_AFE_ANARXTEST_TPCTRL_SM_BITS                     5
#define SGMII0_RX_AFE_ANARXTEST_TPCTRL_SM_SHIFT                    4

/* SGMII0_RX_afe :: anaRxTest :: testMuxSelect_SM [03:00] */
#define Wr_SGMII0_RX_afe_anaRxTest_testMuxSelect_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXTEST,0xf,0,x)
#define Rd_SGMII0_RX_afe_anaRxTest_testMuxSelect_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXTEST,0xf,0)
#define SGMII0_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_MASK              0x000f
#define SGMII0_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_ALIGN             0
#define SGMII0_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_BITS              4
#define SGMII0_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_SHIFT             0


/****************************************************************************
 * SGMII0_RX_afe :: anaRxControl1G
 ***************************************************************************/
/* SGMII0_RX_afe :: anaRxControl1G :: fpat_md [15:15] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_fpat_md(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x8000,15,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_fpat_md(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x8000,15)
#define SGMII0_RX_AFE_ANARXCONTROL1G_FPAT_MD_MASK                  0x8000
#define SGMII0_RX_AFE_ANARXCONTROL1G_FPAT_MD_ALIGN                 0
#define SGMII0_RX_AFE_ANARXCONTROL1G_FPAT_MD_BITS                  1
#define SGMII0_RX_AFE_ANARXCONTROL1G_FPAT_MD_SHIFT                 15

/* SGMII0_RX_afe :: anaRxControl1G :: pkt_count_en [14:14] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_pkt_count_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x4000,14,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_pkt_count_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x4000,14)
#define SGMII0_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_MASK             0x4000
#define SGMII0_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN            0
#define SGMII0_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_BITS             1
#define SGMII0_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT            14

/* SGMII0_RX_afe :: anaRxControl1G :: staMuxRegDis [13:13] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_staMuxRegDis(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x2000,13,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_staMuxRegDis(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x2000,13)
#define SGMII0_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_MASK             0x2000
#define SGMII0_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_ALIGN            0
#define SGMII0_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_BITS             1
#define SGMII0_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_SHIFT            13

/* SGMII0_RX_afe :: anaRxControl1G :: prbs_clr_dis [12:12] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_prbs_clr_dis(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x1000,12,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_prbs_clr_dis(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x1000,12)
#define SGMII0_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_MASK             0x1000
#define SGMII0_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN            0
#define SGMII0_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_BITS             1
#define SGMII0_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT            12

/* SGMII0_RX_afe :: anaRxControl1G :: rxd_dec_sel [11:11] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_rxd_dec_sel(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x800,11,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_rxd_dec_sel(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x800,11)
#define SGMII0_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_MASK              0x0800
#define SGMII0_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN             0
#define SGMII0_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_BITS              1
#define SGMII0_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT             11

/* SGMII0_RX_afe :: anaRxControl1G :: cgbad_tst [10:10] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_cgbad_tst(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x400,10,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_cgbad_tst(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x400,10)
#define SGMII0_RX_AFE_ANARXCONTROL1G_CGBAD_TST_MASK                0x0400
#define SGMII0_RX_AFE_ANARXCONTROL1G_CGBAD_TST_ALIGN               0
#define SGMII0_RX_AFE_ANARXCONTROL1G_CGBAD_TST_BITS                1
#define SGMII0_RX_AFE_ANARXCONTROL1G_CGBAD_TST_SHIFT               10

/* SGMII0_RX_afe :: anaRxControl1G :: Emon_en [09:09] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_Emon_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x200,9,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_Emon_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x200,9)
#define SGMII0_RX_AFE_ANARXCONTROL1G_EMON_EN_MASK                  0x0200
#define SGMII0_RX_AFE_ANARXCONTROL1G_EMON_EN_ALIGN                 0
#define SGMII0_RX_AFE_ANARXCONTROL1G_EMON_EN_BITS                  1
#define SGMII0_RX_AFE_ANARXCONTROL1G_EMON_EN_SHIFT                 9

/* SGMII0_RX_afe :: anaRxControl1G :: prbs_en [08:08] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_prbs_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x100,8,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_prbs_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x100,8)
#define SGMII0_RX_AFE_ANARXCONTROL1G_PRBS_EN_MASK                  0x0100
#define SGMII0_RX_AFE_ANARXCONTROL1G_PRBS_EN_ALIGN                 0
#define SGMII0_RX_AFE_ANARXCONTROL1G_PRBS_EN_BITS                  1
#define SGMII0_RX_AFE_ANARXCONTROL1G_PRBS_EN_SHIFT                 8

/* SGMII0_RX_afe :: anaRxControl1G :: cgbad_en [07:07] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_cgbad_en(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x80,7,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_cgbad_en(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x80,7)
#define SGMII0_RX_AFE_ANARXCONTROL1G_CGBAD_EN_MASK                 0x0080
#define SGMII0_RX_AFE_ANARXCONTROL1G_CGBAD_EN_ALIGN                0
#define SGMII0_RX_AFE_ANARXCONTROL1G_CGBAD_EN_BITS                 1
#define SGMII0_RX_AFE_ANARXCONTROL1G_CGBAD_EN_SHIFT                7

/* SGMII0_RX_afe :: anaRxControl1G :: cstretch [06:06] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_cstretch(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x40,6,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_cstretch(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x40,6)
#define SGMII0_RX_AFE_ANARXCONTROL1G_CSTRETCH_MASK                 0x0040
#define SGMII0_RX_AFE_ANARXCONTROL1G_CSTRETCH_ALIGN                0
#define SGMII0_RX_AFE_ANARXCONTROL1G_CSTRETCH_BITS                 1
#define SGMII0_RX_AFE_ANARXCONTROL1G_CSTRETCH_SHIFT                6

/* SGMII0_RX_afe :: anaRxControl1G :: rtbi_ckflip [05:05] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_rtbi_ckflip(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_rtbi_ckflip(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x20,5)
#define SGMII0_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_MASK              0x0020
#define SGMII0_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_ALIGN             0
#define SGMII0_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_BITS              1
#define SGMII0_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_SHIFT             5

/* SGMII0_RX_afe :: anaRxControl1G :: rtbi_flip [04:04] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_rtbi_flip(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_rtbi_flip(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x10,4)
#define SGMII0_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_MASK                0x0010
#define SGMII0_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_ALIGN               0
#define SGMII0_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_BITS                1
#define SGMII0_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_SHIFT               4

/* SGMII0_RX_afe :: anaRxControl1G :: phase_sel_SM [03:03] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_phase_sel_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_phase_sel_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x8,3)
#define SGMII0_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_MASK             0x0008
#define SGMII0_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_ALIGN            0
#define SGMII0_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_BITS             1
#define SGMII0_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_SHIFT            3

/* SGMII0_RX_afe :: anaRxControl1G :: spd_rstb_dis_SM [02:02] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_spd_rstb_dis_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_spd_rstb_dis_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x4,2)
#define SGMII0_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_MASK          0x0004
#define SGMII0_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_ALIGN         0
#define SGMII0_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_BITS          1
#define SGMII0_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_SHIFT         2

/* SGMII0_RX_afe :: anaRxControl1G :: freq_sel_force [01:01] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_freq_sel_force(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x2,1,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_freq_sel_force(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x2,1)
#define SGMII0_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK           0x0002
#define SGMII0_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN          0
#define SGMII0_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS           1
#define SGMII0_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT          1

/* SGMII0_RX_afe :: anaRxControl1G :: freq_sel [00:00] */
#define Wr_SGMII0_RX_afe_anaRxControl1G_freq_sel(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x1,0,x)
#define Rd_SGMII0_RX_afe_anaRxControl1G_freq_sel(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROL1G,0x1,0)
#define SGMII0_RX_AFE_ANARXCONTROL1G_FREQ_SEL_MASK                 0x0001
#define SGMII0_RX_AFE_ANARXCONTROL1G_FREQ_SEL_ALIGN                0
#define SGMII0_RX_AFE_ANARXCONTROL1G_FREQ_SEL_BITS                 1
#define SGMII0_RX_AFE_ANARXCONTROL1G_FREQ_SEL_SHIFT                0


/****************************************************************************
 * SGMII0_RX_afe :: anaRxControlPci
 ***************************************************************************/
/* SGMII0_RX_afe :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_comma_adj_sync_sel(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x8000,15,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_comma_adj_sync_sel(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x8000,15)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK      0x8000
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN     0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS      1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT     15

/* SGMII0_RX_afe :: anaRxControlPci :: comma_mask_force_r [14:14] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_comma_mask_force_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x4000,14,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_comma_mask_force_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x4000,14)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK      0x4000
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN     0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS      1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT     14

/* SGMII0_RX_afe :: anaRxControlPci :: comma_mask_r [13:13] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_comma_mask_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x2000,13,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_comma_mask_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x2000,13)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_MASK            0x2000
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN           0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_BITS            1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT           13

/* SGMII0_RX_afe :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_sync_status_force_sync_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x1000,12,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_sync_status_force_sync_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x1000,12)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12

/* SGMII0_RX_afe :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_sync_status_force_r_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x800,11,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_sync_status_force_r_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x800,11)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK  0x0800
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS  1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11

/* SGMII0_RX_afe :: anaRxControlPci :: sync_status_force_r [10:10] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_sync_status_force_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x400,10,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_sync_status_force_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x400,10)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK     0x0400
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN    0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS     1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT    10

/* SGMII0_RX_afe :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_comma_adj_en_force_ext_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x200,9,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_comma_adj_en_force_ext_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x200,9)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9

/* SGMII0_RX_afe :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_comma_adj_en_force_sync_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x100,8,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_comma_adj_en_force_sync_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x100,8)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8

/* SGMII0_RX_afe :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_comma_adj_en_force_r_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x80,7,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_comma_adj_en_force_r_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x80,7)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7

/* SGMII0_RX_afe :: anaRxControlPci :: comma_adj_en_r [06:06] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_comma_adj_en_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x40,6,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_comma_adj_en_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x40,6)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK          0x0040
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN         0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS          1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT         6

/* SGMII0_RX_afe :: anaRxControlPci :: link_en_force_SM [05:05] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_link_en_force_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x20,5,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_link_en_force_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x20,5)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK        0x0020
#define SGMII0_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN       0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS        1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT       5

/* SGMII0_RX_afe :: anaRxControlPci :: link_en_r [04:04] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_link_en_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x10,4,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_link_en_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x10,4)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_MASK               0x0010
#define SGMII0_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_ALIGN              0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_BITS               1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_SHIFT              4

/* SGMII0_RX_afe :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_rx_polarity_force_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x8,3,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_rx_polarity_force_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x8,3)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK    0x0008
#define SGMII0_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN   0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS    1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT   3

/* SGMII0_RX_afe :: anaRxControlPci :: rx_polarity_r [02:02] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_rx_polarity_r(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x4,2,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_rx_polarity_r(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x4,2)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_MASK           0x0004
#define SGMII0_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN          0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_BITS           1
#define SGMII0_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT          2

/* SGMII0_RX_afe :: anaRxControlPci :: integ_mode_SM [01:00] */
#define Wr_SGMII0_RX_afe_anaRxControlPci_integ_mode_SM(x) WriteRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x3,0,x)
#define Rd_SGMII0_RX_afe_anaRxControlPci_integ_mode_SM(x) ReadRegBits16(SGMII0_RX_AFE_ANARXCONTROLPCI,0x3,0)
#define SGMII0_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_MASK           0x0003
#define SGMII0_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN          0
#define SGMII0_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_BITS           2
#define SGMII0_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT          0


/****************************************************************************
 * SGMII0_RX_afe :: anaRxAstatus
 ***************************************************************************/
/* SGMII0_RX_afe :: anaRxAstatus :: genstat [15:00] */
#define Wr_SGMII0_RX_afe_anaRxAstatus_genstat(x) WriteReg16(SGMII0_RX_AFE_ANARXASTATUS,x)
#define Rd_SGMII0_RX_afe_anaRxAstatus_genstat(x) ReadReg16(SGMII0_RX_AFE_ANARXASTATUS)
#define SGMII0_RX_AFE_ANARXASTATUS_GENSTAT_MASK                    0xffff
#define SGMII0_RX_AFE_ANARXASTATUS_GENSTAT_ALIGN                   0
#define SGMII0_RX_AFE_ANARXASTATUS_GENSTAT_BITS                    16
#define SGMII0_RX_AFE_ANARXASTATUS_GENSTAT_SHIFT                   0


/****************************************************************************
 * SGMII0_RX_afe :: ctrl5
 ***************************************************************************/
/* SGMII0_RX_afe :: ctrl5 :: sigdet_usb_en [15:15] */
#define Wr_SGMII0_RX_afe_ctrl5_sigdet_usb_en(x) WriteRegBits16(SGMII0_RX_AFE_CTRL5,0x8000,15,x)
#define Rd_SGMII0_RX_afe_ctrl5_sigdet_usb_en(x) ReadRegBits16(SGMII0_RX_AFE_CTRL5,0x8000,15)
#define SGMII0_RX_AFE_CTRL5_SIGDET_USB_EN_MASK                     0x8000
#define SGMII0_RX_AFE_CTRL5_SIGDET_USB_EN_ALIGN                    0
#define SGMII0_RX_AFE_CTRL5_SIGDET_USB_EN_BITS                     1
#define SGMII0_RX_AFE_CTRL5_SIGDET_USB_EN_SHIFT                    15

/* SGMII0_RX_afe :: ctrl5 :: pi_eyem_enable [14:14] */
#define Wr_SGMII0_RX_afe_ctrl5_pi_eyem_enable(x) WriteRegBits16(SGMII0_RX_AFE_CTRL5,0x4000,14,x)
#define Rd_SGMII0_RX_afe_ctrl5_pi_eyem_enable(x) ReadRegBits16(SGMII0_RX_AFE_CTRL5,0x4000,14)
#define SGMII0_RX_AFE_CTRL5_PI_EYEM_ENABLE_MASK                    0x4000
#define SGMII0_RX_AFE_CTRL5_PI_EYEM_ENABLE_ALIGN                   0
#define SGMII0_RX_AFE_CTRL5_PI_EYEM_ENABLE_BITS                    1
#define SGMII0_RX_AFE_CTRL5_PI_EYEM_ENABLE_SHIFT                   14

/* SGMII0_RX_afe :: ctrl5 :: pi_main_enable [13:13] */
#define Wr_SGMII0_RX_afe_ctrl5_pi_main_enable(x) WriteRegBits16(SGMII0_RX_AFE_CTRL5,0x2000,13,x)
#define Rd_SGMII0_RX_afe_ctrl5_pi_main_enable(x) ReadRegBits16(SGMII0_RX_AFE_CTRL5,0x2000,13)
#define SGMII0_RX_AFE_CTRL5_PI_MAIN_ENABLE_MASK                    0x2000
#define SGMII0_RX_AFE_CTRL5_PI_MAIN_ENABLE_ALIGN                   0
#define SGMII0_RX_AFE_CTRL5_PI_MAIN_ENABLE_BITS                    1
#define SGMII0_RX_AFE_CTRL5_PI_MAIN_ENABLE_SHIFT                   13

/* SGMII0_RX_afe :: ctrl5 :: eyemonitor_ref_zero [12:12] */
#define Wr_SGMII0_RX_afe_ctrl5_eyemonitor_ref_zero(x) WriteRegBits16(SGMII0_RX_AFE_CTRL5,0x1000,12,x)
#define Rd_SGMII0_RX_afe_ctrl5_eyemonitor_ref_zero(x) ReadRegBits16(SGMII0_RX_AFE_CTRL5,0x1000,12)
#define SGMII0_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_MASK               0x1000
#define SGMII0_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_ALIGN              0
#define SGMII0_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_BITS               1
#define SGMII0_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_SHIFT              12

/* SGMII0_RX_afe :: ctrl5 :: eyemonitorref_pd [11:11] */
#define Wr_SGMII0_RX_afe_ctrl5_eyemonitorref_pd(x) WriteRegBits16(SGMII0_RX_AFE_CTRL5,0x800,11,x)
#define Rd_SGMII0_RX_afe_ctrl5_eyemonitorref_pd(x) ReadRegBits16(SGMII0_RX_AFE_CTRL5,0x800,11)
#define SGMII0_RX_AFE_CTRL5_EYEMONITORREF_PD_MASK                  0x0800
#define SGMII0_RX_AFE_CTRL5_EYEMONITORREF_PD_ALIGN                 0
#define SGMII0_RX_AFE_CTRL5_EYEMONITORREF_PD_BITS                  1
#define SGMII0_RX_AFE_CTRL5_EYEMONITORREF_PD_SHIFT                 11

/* SGMII0_RX_afe :: ctrl5 :: eyem_refadjust [10:06] */
#define Wr_SGMII0_RX_afe_ctrl5_eyem_refadjust(x) WriteRegBits16(SGMII0_RX_AFE_CTRL5,0x7c0,6,x)
#define Rd_SGMII0_RX_afe_ctrl5_eyem_refadjust(x) ReadRegBits16(SGMII0_RX_AFE_CTRL5,0x7c0,6)
#define SGMII0_RX_AFE_CTRL5_EYEM_REFADJUST_MASK                    0x07c0
#define SGMII0_RX_AFE_CTRL5_EYEM_REFADJUST_ALIGN                   0
#define SGMII0_RX_AFE_CTRL5_EYEM_REFADJUST_BITS                    5
#define SGMII0_RX_AFE_CTRL5_EYEM_REFADJUST_SHIFT                   6

/* SGMII0_RX_afe :: ctrl5 :: sel_clk [05:04] */
#define Wr_SGMII0_RX_afe_ctrl5_sel_clk(x) WriteRegBits16(SGMII0_RX_AFE_CTRL5,0x30,4,x)
#define Rd_SGMII0_RX_afe_ctrl5_sel_clk(x) ReadRegBits16(SGMII0_RX_AFE_CTRL5,0x30,4)
#define SGMII0_RX_AFE_CTRL5_SEL_CLK_MASK                           0x0030
#define SGMII0_RX_AFE_CTRL5_SEL_CLK_ALIGN                          0
#define SGMII0_RX_AFE_CTRL5_SEL_CLK_BITS                           2
#define SGMII0_RX_AFE_CTRL5_SEL_CLK_SHIFT                          4

/* SGMII0_RX_afe :: ctrl5 :: Sigdet_threshold [03:00] */
#define Wr_SGMII0_RX_afe_ctrl5_Sigdet_threshold(x) WriteRegBits16(SGMII0_RX_AFE_CTRL5,0xf,0,x)
#define Rd_SGMII0_RX_afe_ctrl5_Sigdet_threshold(x) ReadRegBits16(SGMII0_RX_AFE_CTRL5,0xf,0)
#define SGMII0_RX_AFE_CTRL5_SIGDET_THRESHOLD_MASK                  0x000f
#define SGMII0_RX_AFE_CTRL5_SIGDET_THRESHOLD_ALIGN                 0
#define SGMII0_RX_AFE_CTRL5_SIGDET_THRESHOLD_BITS                  4
#define SGMII0_RX_AFE_CTRL5_SIGDET_THRESHOLD_SHIFT                 0


/****************************************************************************
 * SGMII0_RX_afe :: ctrl6
 ***************************************************************************/
/* SGMII0_RX_afe :: ctrl6 :: reserved0 [15:10] */
#define SGMII0_RX_AFE_CTRL6_RESERVED0_MASK                         0xfc00
#define SGMII0_RX_AFE_CTRL6_RESERVED0_ALIGN                        0
#define SGMII0_RX_AFE_CTRL6_RESERVED0_BITS                         6
#define SGMII0_RX_AFE_CTRL6_RESERVED0_SHIFT                        10

/* SGMII0_RX_afe :: ctrl6 :: reserved_105_103 [09:07] */
#define SGMII0_RX_AFE_CTRL6_RESERVED_105_103_MASK                  0x0380
#define SGMII0_RX_AFE_CTRL6_RESERVED_105_103_ALIGN                 0
#define SGMII0_RX_AFE_CTRL6_RESERVED_105_103_BITS                  3
#define SGMII0_RX_AFE_CTRL6_RESERVED_105_103_SHIFT                 7

/* SGMII0_RX_afe :: ctrl6 :: Eye_Monitor_PI_BW_sel [06:06] */
#define Wr_SGMII0_RX_afe_ctrl6_Eye_Monitor_PI_BW_sel(x) WriteRegBits16(SGMII0_RX_AFE_CTRL6,0x40,6,x)
#define Rd_SGMII0_RX_afe_ctrl6_Eye_Monitor_PI_BW_sel(x) ReadRegBits16(SGMII0_RX_AFE_CTRL6,0x40,6)
#define SGMII0_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_MASK             0x0040
#define SGMII0_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_ALIGN            0
#define SGMII0_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_BITS             1
#define SGMII0_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_SHIFT            6

/* SGMII0_RX_afe :: ctrl6 :: Eye_Monitor_PI_pwd_lvl2pi [05:05] */
#define Wr_SGMII0_RX_afe_ctrl6_Eye_Monitor_PI_pwd_lvl2pi(x) WriteRegBits16(SGMII0_RX_AFE_CTRL6,0x20,5,x)
#define Rd_SGMII0_RX_afe_ctrl6_Eye_Monitor_PI_pwd_lvl2pi(x) ReadRegBits16(SGMII0_RX_AFE_CTRL6,0x20,5)
#define SGMII0_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_MASK         0x0020
#define SGMII0_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_ALIGN        0
#define SGMII0_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_BITS         1
#define SGMII0_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_SHIFT        5

/* SGMII0_RX_afe :: ctrl6 :: reserved_100 [04:04] */
#define SGMII0_RX_AFE_CTRL6_RESERVED_100_MASK                      0x0010
#define SGMII0_RX_AFE_CTRL6_RESERVED_100_ALIGN                     0
#define SGMII0_RX_AFE_CTRL6_RESERVED_100_BITS                      1
#define SGMII0_RX_AFE_CTRL6_RESERVED_100_SHIFT                     4

/* SGMII0_RX_afe :: ctrl6 :: PI_lowvdd_enb [03:03] */
#define Wr_SGMII0_RX_afe_ctrl6_PI_lowvdd_enb(x) WriteRegBits16(SGMII0_RX_AFE_CTRL6,0x8,3,x)
#define Rd_SGMII0_RX_afe_ctrl6_PI_lowvdd_enb(x) ReadRegBits16(SGMII0_RX_AFE_CTRL6,0x8,3)
#define SGMII0_RX_AFE_CTRL6_PI_LOWVDD_ENB_MASK                     0x0008
#define SGMII0_RX_AFE_CTRL6_PI_LOWVDD_ENB_ALIGN                    0
#define SGMII0_RX_AFE_CTRL6_PI_LOWVDD_ENB_BITS                     1
#define SGMII0_RX_AFE_CTRL6_PI_LOWVDD_ENB_SHIFT                    3

/* SGMII0_RX_afe :: ctrl6 :: Main_PI_BW_sel [02:02] */
#define Wr_SGMII0_RX_afe_ctrl6_Main_PI_BW_sel(x) WriteRegBits16(SGMII0_RX_AFE_CTRL6,0x4,2,x)
#define Rd_SGMII0_RX_afe_ctrl6_Main_PI_BW_sel(x) ReadRegBits16(SGMII0_RX_AFE_CTRL6,0x4,2)
#define SGMII0_RX_AFE_CTRL6_MAIN_PI_BW_SEL_MASK                    0x0004
#define SGMII0_RX_AFE_CTRL6_MAIN_PI_BW_SEL_ALIGN                   0
#define SGMII0_RX_AFE_CTRL6_MAIN_PI_BW_SEL_BITS                    1
#define SGMII0_RX_AFE_CTRL6_MAIN_PI_BW_SEL_SHIFT                   2

/* SGMII0_RX_afe :: ctrl6 :: Main_PI_pwd_lvl2pi [01:01] */
#define Wr_SGMII0_RX_afe_ctrl6_Main_PI_pwd_lvl2pi(x) WriteRegBits16(SGMII0_RX_AFE_CTRL6,0x2,1,x)
#define Rd_SGMII0_RX_afe_ctrl6_Main_PI_pwd_lvl2pi(x) ReadRegBits16(SGMII0_RX_AFE_CTRL6,0x2,1)
#define SGMII0_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_MASK                0x0002
#define SGMII0_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_ALIGN               0
#define SGMII0_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_BITS                1
#define SGMII0_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_SHIFT               1

/* SGMII0_RX_afe :: ctrl6 :: reserved_96 [00:00] */
#define SGMII0_RX_AFE_CTRL6_RESERVED_96_MASK                       0x0001
#define SGMII0_RX_AFE_CTRL6_RESERVED_96_ALIGN                      0
#define SGMII0_RX_AFE_CTRL6_RESERVED_96_BITS                       1
#define SGMII0_RX_AFE_CTRL6_RESERVED_96_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk2
 ***************************************************************************/
/****************************************************************************
 * SGMII_Blk2 :: TestModeLane
 ***************************************************************************/
/* SGMII_Blk2 :: TestModeLane :: eee_fast_timer_en [15:15] */
#define Wr_SGMII_Blk2_TestModeLane_eee_fast_timer_en(x) WriteRegBits16(SGMII_BLK2_TESTMODELANE,0x8000,15,x)
#define Rd_SGMII_Blk2_TestModeLane_eee_fast_timer_en(x) ReadRegBits16(SGMII_BLK2_TESTMODELANE,0x8000,15)
#define SGMII_BLK2_TESTMODELANE_EEE_FAST_TIMER_EN_MASK             0x8000
#define SGMII_BLK2_TESTMODELANE_EEE_FAST_TIMER_EN_ALIGN            0
#define SGMII_BLK2_TESTMODELANE_EEE_FAST_TIMER_EN_BITS             1
#define SGMII_BLK2_TESTMODELANE_EEE_FAST_TIMER_EN_SHIFT            15

/* SGMII_Blk2 :: TestModeLane :: eee_gateclk_en [14:14] */
#define Wr_SGMII_Blk2_TestModeLane_eee_gateclk_en(x) WriteRegBits16(SGMII_BLK2_TESTMODELANE,0x4000,14,x)
#define Rd_SGMII_Blk2_TestModeLane_eee_gateclk_en(x) ReadRegBits16(SGMII_BLK2_TESTMODELANE,0x4000,14)
#define SGMII_BLK2_TESTMODELANE_EEE_GATECLK_EN_MASK                0x4000
#define SGMII_BLK2_TESTMODELANE_EEE_GATECLK_EN_ALIGN               0
#define SGMII_BLK2_TESTMODELANE_EEE_GATECLK_EN_BITS                1
#define SGMII_BLK2_TESTMODELANE_EEE_GATECLK_EN_SHIFT               14

/* SGMII_Blk2 :: TestModeLane :: eee_gateoutclk_en [13:13] */
#define Wr_SGMII_Blk2_TestModeLane_eee_gateoutclk_en(x) WriteRegBits16(SGMII_BLK2_TESTMODELANE,0x2000,13,x)
#define Rd_SGMII_Blk2_TestModeLane_eee_gateoutclk_en(x) ReadRegBits16(SGMII_BLK2_TESTMODELANE,0x2000,13)
#define SGMII_BLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_MASK             0x2000
#define SGMII_BLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_ALIGN            0
#define SGMII_BLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_BITS             1
#define SGMII_BLK2_TESTMODELANE_EEE_GATEOUTCLK_EN_SHIFT            13

/* SGMII_Blk2 :: TestModeLane :: reserved0 [12:11] */
#define SGMII_BLK2_TESTMODELANE_RESERVED0_MASK                     0x1800
#define SGMII_BLK2_TESTMODELANE_RESERVED0_ALIGN                    0
#define SGMII_BLK2_TESTMODELANE_RESERVED0_BITS                     2
#define SGMII_BLK2_TESTMODELANE_RESERVED0_SHIFT                    11

/* SGMII_Blk2 :: TestModeLane :: indck_mode_en_rx_force [10:10] */
#define Wr_SGMII_Blk2_TestModeLane_indck_mode_en_rx_force(x) WriteRegBits16(SGMII_BLK2_TESTMODELANE,0x400,10,x)
#define Rd_SGMII_Blk2_TestModeLane_indck_mode_en_rx_force(x) ReadRegBits16(SGMII_BLK2_TESTMODELANE,0x400,10)
#define SGMII_BLK2_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_MASK        0x0400
#define SGMII_BLK2_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_ALIGN       0
#define SGMII_BLK2_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_BITS        1
#define SGMII_BLK2_TESTMODELANE_INDCK_MODE_EN_RX_FORCE_SHIFT       10

/* SGMII_Blk2 :: TestModeLane :: indck_mode_en_rx_val [09:09] */
#define Wr_SGMII_Blk2_TestModeLane_indck_mode_en_rx_val(x) WriteRegBits16(SGMII_BLK2_TESTMODELANE,0x200,9,x)
#define Rd_SGMII_Blk2_TestModeLane_indck_mode_en_rx_val(x) ReadRegBits16(SGMII_BLK2_TESTMODELANE,0x200,9)
#define SGMII_BLK2_TESTMODELANE_INDCK_MODE_EN_RX_VAL_MASK          0x0200
#define SGMII_BLK2_TESTMODELANE_INDCK_MODE_EN_RX_VAL_ALIGN         0
#define SGMII_BLK2_TESTMODELANE_INDCK_MODE_EN_RX_VAL_BITS          1
#define SGMII_BLK2_TESTMODELANE_INDCK_MODE_EN_RX_VAL_SHIFT         9

/* SGMII_Blk2 :: TestModeLane :: reserved1 [08:08] */
#define SGMII_BLK2_TESTMODELANE_RESERVED1_MASK                     0x0100
#define SGMII_BLK2_TESTMODELANE_RESERVED1_ALIGN                    0
#define SGMII_BLK2_TESTMODELANE_RESERVED1_BITS                     1
#define SGMII_BLK2_TESTMODELANE_RESERVED1_SHIFT                    8

/* SGMII_Blk2 :: TestModeLane :: txfifo_bypass [07:07] */
#define Wr_SGMII_Blk2_TestModeLane_txfifo_bypass(x) WriteRegBits16(SGMII_BLK2_TESTMODELANE,0x80,7,x)
#define Rd_SGMII_Blk2_TestModeLane_txfifo_bypass(x) ReadRegBits16(SGMII_BLK2_TESTMODELANE,0x80,7)
#define SGMII_BLK2_TESTMODELANE_TXFIFO_BYPASS_MASK                 0x0080
#define SGMII_BLK2_TESTMODELANE_TXFIFO_BYPASS_ALIGN                0
#define SGMII_BLK2_TESTMODELANE_TXFIFO_BYPASS_BITS                 1
#define SGMII_BLK2_TESTMODELANE_TXFIFO_BYPASS_SHIFT                7

/* SGMII_Blk2 :: TestModeLane :: reserved2 [06:00] */
#define SGMII_BLK2_TESTMODELANE_RESERVED2_MASK                     0x007f
#define SGMII_BLK2_TESTMODELANE_RESERVED2_ALIGN                    0
#define SGMII_BLK2_TESTMODELANE_RESERVED2_BITS                     7
#define SGMII_BLK2_TESTMODELANE_RESERVED2_SHIFT                    0


/****************************************************************************
 * SGMII_Blk2 :: TestModeCombo
 ***************************************************************************/
/* SGMII_Blk2 :: TestModeCombo :: reserved0 [15:12] */
#define SGMII_BLK2_TESTMODECOMBO_RESERVED0_MASK                    0xf000
#define SGMII_BLK2_TESTMODECOMBO_RESERVED0_ALIGN                   0
#define SGMII_BLK2_TESTMODECOMBO_RESERVED0_BITS                    4
#define SGMII_BLK2_TESTMODECOMBO_RESERVED0_SHIFT                   12

/* SGMII_Blk2 :: TestModeCombo :: test_monitor_mode2 [11:06] */
#define Wr_SGMII_Blk2_TestModeCombo_test_monitor_mode2(x) WriteRegBits16(SGMII_BLK2_TESTMODECOMBO,0xfc0,6,x)
#define Rd_SGMII_Blk2_TestModeCombo_test_monitor_mode2(x) ReadRegBits16(SGMII_BLK2_TESTMODECOMBO,0xfc0,6)
#define SGMII_BLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_MASK           0x0fc0
#define SGMII_BLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_ALIGN          0
#define SGMII_BLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_BITS           6
#define SGMII_BLK2_TESTMODECOMBO_TEST_MONITOR_MODE2_SHIFT          6

/* SGMII_Blk2 :: TestModeCombo :: test_monitor_mode1 [05:00] */
#define Wr_SGMII_Blk2_TestModeCombo_test_monitor_mode1(x) WriteRegBits16(SGMII_BLK2_TESTMODECOMBO,0x3f,0,x)
#define Rd_SGMII_Blk2_TestModeCombo_test_monitor_mode1(x) ReadRegBits16(SGMII_BLK2_TESTMODECOMBO,0x3f,0)
#define SGMII_BLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_MASK           0x003f
#define SGMII_BLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_ALIGN          0
#define SGMII_BLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_BITS           6
#define SGMII_BLK2_TESTMODECOMBO_TEST_MONITOR_MODE1_SHIFT          0


/****************************************************************************
 * SGMII_Blk2 :: TestModeMux
 ***************************************************************************/
/* SGMII_Blk2 :: TestModeMux :: reserved0 [15:04] */
#define SGMII_BLK2_TESTMODEMUX_RESERVED0_MASK                      0xfff0
#define SGMII_BLK2_TESTMODEMUX_RESERVED0_ALIGN                     0
#define SGMII_BLK2_TESTMODEMUX_RESERVED0_BITS                      12
#define SGMII_BLK2_TESTMODEMUX_RESERVED0_SHIFT                     4

/* SGMII_Blk2 :: TestModeMux :: tmux_sel [03:01] */
#define Wr_SGMII_Blk2_TestModeMux_tmux_sel(x) WriteRegBits16(SGMII_BLK2_TESTMODEMUX,0xe,1,x)
#define Rd_SGMII_Blk2_TestModeMux_tmux_sel(x) ReadRegBits16(SGMII_BLK2_TESTMODEMUX,0xe,1)
#define SGMII_BLK2_TESTMODEMUX_TMUX_SEL_MASK                       0x000e
#define SGMII_BLK2_TESTMODEMUX_TMUX_SEL_ALIGN                      0
#define SGMII_BLK2_TESTMODEMUX_TMUX_SEL_BITS                       3
#define SGMII_BLK2_TESTMODEMUX_TMUX_SEL_SHIFT                      1

/* SGMII_Blk2 :: TestModeMux :: tmux_en [00:00] */
#define Wr_SGMII_Blk2_TestModeMux_tmux_en(x) WriteRegBits16(SGMII_BLK2_TESTMODEMUX,0x1,0,x)
#define Rd_SGMII_Blk2_TestModeMux_tmux_en(x) ReadRegBits16(SGMII_BLK2_TESTMODEMUX,0x1,0)
#define SGMII_BLK2_TESTMODEMUX_TMUX_EN_MASK                        0x0001
#define SGMII_BLK2_TESTMODEMUX_TMUX_EN_ALIGN                       0
#define SGMII_BLK2_TESTMODEMUX_TMUX_EN_BITS                        1
#define SGMII_BLK2_TESTMODEMUX_TMUX_EN_SHIFT                       0


/****************************************************************************
 * SGMII_Blk2 :: cx4SigdetCnt
 ***************************************************************************/
/* SGMII_Blk2 :: cx4SigdetCnt :: cx4SigdetCnt [15:00] */
#define Wr_SGMII_Blk2_cx4SigdetCnt_cx4SigdetCnt(x) WriteReg16(SGMII_BLK2_CX4SIGDETCNT,x)
#define Rd_SGMII_Blk2_cx4SigdetCnt_cx4SigdetCnt(x) ReadReg16(SGMII_BLK2_CX4SIGDETCNT)
#define SGMII_BLK2_CX4SIGDETCNT_CX4SIGDETCNT_MASK                  0xffff
#define SGMII_BLK2_CX4SIGDETCNT_CX4SIGDETCNT_ALIGN                 0
#define SGMII_BLK2_CX4SIGDETCNT_CX4SIGDETCNT_BITS                  16
#define SGMII_BLK2_CX4SIGDETCNT_CX4SIGDETCNT_SHIFT                 0


/****************************************************************************
 * SGMII_Blk2 :: laneReset
 ***************************************************************************/
/* SGMII_Blk2 :: laneReset :: reset_mdio [15:15] */
#define Wr_SGMII_Blk2_laneReset_reset_mdio(x) WriteRegBits16(SGMII_BLK2_LANERESET,0x8000,15,x)
#define Rd_SGMII_Blk2_laneReset_reset_mdio(x) ReadRegBits16(SGMII_BLK2_LANERESET,0x8000,15)
#define SGMII_BLK2_LANERESET_RESET_MDIO_MASK                       0x8000
#define SGMII_BLK2_LANERESET_RESET_MDIO_ALIGN                      0
#define SGMII_BLK2_LANERESET_RESET_MDIO_BITS                       1
#define SGMII_BLK2_LANERESET_RESET_MDIO_SHIFT                      15

/* SGMII_Blk2 :: laneReset :: reserved0 [14:09] */
#define SGMII_BLK2_LANERESET_RESERVED0_MASK                        0x7e00
#define SGMII_BLK2_LANERESET_RESERVED0_ALIGN                       0
#define SGMII_BLK2_LANERESET_RESERVED0_BITS                        6
#define SGMII_BLK2_LANERESET_RESERVED0_SHIFT                       9

/* SGMII_Blk2 :: laneReset :: reset_pll [08:08] */
#define Wr_SGMII_Blk2_laneReset_reset_pll(x) WriteRegBits16(SGMII_BLK2_LANERESET,0x100,8,x)
#define Rd_SGMII_Blk2_laneReset_reset_pll(x) ReadRegBits16(SGMII_BLK2_LANERESET,0x100,8)
#define SGMII_BLK2_LANERESET_RESET_PLL_MASK                        0x0100
#define SGMII_BLK2_LANERESET_RESET_PLL_ALIGN                       0
#define SGMII_BLK2_LANERESET_RESET_PLL_BITS                        1
#define SGMII_BLK2_LANERESET_RESET_PLL_SHIFT                       8

/* SGMII_Blk2 :: laneReset :: reserved1 [07:05] */
#define SGMII_BLK2_LANERESET_RESERVED1_MASK                        0x00e0
#define SGMII_BLK2_LANERESET_RESERVED1_ALIGN                       0
#define SGMII_BLK2_LANERESET_RESERVED1_BITS                        3
#define SGMII_BLK2_LANERESET_RESERVED1_SHIFT                       5

/* SGMII_Blk2 :: laneReset :: reset_tx [04:04] */
#define Wr_SGMII_Blk2_laneReset_reset_tx(x) WriteRegBits16(SGMII_BLK2_LANERESET,0x10,4,x)
#define Rd_SGMII_Blk2_laneReset_reset_tx(x) ReadRegBits16(SGMII_BLK2_LANERESET,0x10,4)
#define SGMII_BLK2_LANERESET_RESET_TX_MASK                         0x0010
#define SGMII_BLK2_LANERESET_RESET_TX_ALIGN                        0
#define SGMII_BLK2_LANERESET_RESET_TX_BITS                         1
#define SGMII_BLK2_LANERESET_RESET_TX_SHIFT                        4

/* SGMII_Blk2 :: laneReset :: reserved2 [03:01] */
#define SGMII_BLK2_LANERESET_RESERVED2_MASK                        0x000e
#define SGMII_BLK2_LANERESET_RESERVED2_ALIGN                       0
#define SGMII_BLK2_LANERESET_RESERVED2_BITS                        3
#define SGMII_BLK2_LANERESET_RESERVED2_SHIFT                       1

/* SGMII_Blk2 :: laneReset :: reset_rx [00:00] */
#define Wr_SGMII_Blk2_laneReset_reset_rx(x) WriteRegBits16(SGMII_BLK2_LANERESET,0x1,0,x)
#define Rd_SGMII_Blk2_laneReset_reset_rx(x) ReadRegBits16(SGMII_BLK2_LANERESET,0x1,0)
#define SGMII_BLK2_LANERESET_RESET_RX_MASK                         0x0001
#define SGMII_BLK2_LANERESET_RESET_RX_ALIGN                        0
#define SGMII_BLK2_LANERESET_RESET_RX_BITS                         1
#define SGMII_BLK2_LANERESET_RESET_RX_SHIFT                        0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk4
 ***************************************************************************/
/****************************************************************************
 * SGMII_Blk4 :: xgxsStatus1
 ***************************************************************************/
/* SGMII_Blk4 :: xgxsStatus1 :: mode_tx [15:12] */
#define Wr_SGMII_Blk4_xgxsStatus1_mode_tx(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS1,0xf000,12,x)
#define Rd_SGMII_Blk4_xgxsStatus1_mode_tx(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS1,0xf000,12)
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_MASK                        0xf000
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_ALIGN                       0
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_BITS                        4
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_SHIFT                       12
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_XGXS                        0
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_XGXG_nCC                    1
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_Indlane_OS8                 4
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_IndLane_OS5                 5
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_IndLane_OS4                 6
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_PCI                         7
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_XGXS_nLQ                    8
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_XGXS_nLQnCC                 9
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_PBypass                     10
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_PBypass_nDSK                11
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_ComboCoreMode               12
#define SGMII_BLK4_XGXSSTATUS1_MODE_TX_Clocks_off                  15

/* SGMII_Blk4 :: xgxsStatus1 :: serdesMode_en_tx [11:11] */
#define Wr_SGMII_Blk4_xgxsStatus1_serdesMode_en_tx(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS1,0x800,11,x)
#define Rd_SGMII_Blk4_xgxsStatus1_serdesMode_en_tx(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS1,0x800,11)
#define SGMII_BLK4_XGXSSTATUS1_SERDESMODE_EN_TX_MASK               0x0800
#define SGMII_BLK4_XGXSSTATUS1_SERDESMODE_EN_TX_ALIGN              0
#define SGMII_BLK4_XGXSSTATUS1_SERDESMODE_EN_TX_BITS               1
#define SGMII_BLK4_XGXSSTATUS1_SERDESMODE_EN_TX_SHIFT              11

/* SGMII_Blk4 :: xgxsStatus1 :: sgmii_mode [10:10] */
#define Wr_SGMII_Blk4_xgxsStatus1_sgmii_mode(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS1,0x400,10,x)
#define Rd_SGMII_Blk4_xgxsStatus1_sgmii_mode(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS1,0x400,10)
#define SGMII_BLK4_XGXSSTATUS1_SGMII_MODE_MASK                     0x0400
#define SGMII_BLK4_XGXSSTATUS1_SGMII_MODE_ALIGN                    0
#define SGMII_BLK4_XGXSSTATUS1_SGMII_MODE_BITS                     1
#define SGMII_BLK4_XGXSSTATUS1_SGMII_MODE_SHIFT                    10

/* SGMII_Blk4 :: xgxsStatus1 :: reserved0 [09:09] */
#define SGMII_BLK4_XGXSSTATUS1_RESERVED0_MASK                      0x0200
#define SGMII_BLK4_XGXSSTATUS1_RESERVED0_ALIGN                     0
#define SGMII_BLK4_XGXSSTATUS1_RESERVED0_BITS                      1
#define SGMII_BLK4_XGXSSTATUS1_RESERVED0_SHIFT                     9

/* SGMII_Blk4 :: xgxsStatus1 :: linkstat [08:08] */
#define Wr_SGMII_Blk4_xgxsStatus1_linkstat(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS1,0x100,8,x)
#define Rd_SGMII_Blk4_xgxsStatus1_linkstat(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS1,0x100,8)
#define SGMII_BLK4_XGXSSTATUS1_LINKSTAT_MASK                       0x0100
#define SGMII_BLK4_XGXSSTATUS1_LINKSTAT_ALIGN                      0
#define SGMII_BLK4_XGXSSTATUS1_LINKSTAT_BITS                       1
#define SGMII_BLK4_XGXSSTATUS1_LINKSTAT_SHIFT                      8

/* SGMII_Blk4 :: xgxsStatus1 :: autoneg_complete [07:07] */
#define Wr_SGMII_Blk4_xgxsStatus1_autoneg_complete(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS1,0x80,7,x)
#define Rd_SGMII_Blk4_xgxsStatus1_autoneg_complete(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS1,0x80,7)
#define SGMII_BLK4_XGXSSTATUS1_AUTONEG_COMPLETE_MASK               0x0080
#define SGMII_BLK4_XGXSSTATUS1_AUTONEG_COMPLETE_ALIGN              0
#define SGMII_BLK4_XGXSSTATUS1_AUTONEG_COMPLETE_BITS               1
#define SGMII_BLK4_XGXSSTATUS1_AUTONEG_COMPLETE_SHIFT              7

/* SGMII_Blk4 :: xgxsStatus1 :: reserved1 [06:04] */
#define SGMII_BLK4_XGXSSTATUS1_RESERVED1_MASK                      0x0070
#define SGMII_BLK4_XGXSSTATUS1_RESERVED1_ALIGN                     0
#define SGMII_BLK4_XGXSSTATUS1_RESERVED1_BITS                      3
#define SGMII_BLK4_XGXSSTATUS1_RESERVED1_SHIFT                     4

/* SGMII_Blk4 :: xgxsStatus1 :: actual_speed_ln0 [03:00] */
#define Wr_SGMII_Blk4_xgxsStatus1_actual_speed_ln0(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS1,0xf,0,x)
#define Rd_SGMII_Blk4_xgxsStatus1_actual_speed_ln0(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS1,0xf,0)
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_MASK               0x000f
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_ALIGN              0
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_BITS               4
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_SHIFT              0
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10M             0
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_100M            1
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_1G              2
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_2p5G            3
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_5G_X4           4
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_6G_X4           5
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_HiG         6
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_10G_CX4         7
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12G_HiG         8
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_12p5G_X4        9
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_13G_X4          10
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_15G_X4          11
#define SGMII_BLK4_XGXSSTATUS1_ACTUAL_SPEED_LN0_dr_16G_X4          12


/****************************************************************************
 * SGMII_Blk4 :: xgxsStatus2
 ***************************************************************************/
/* SGMII_Blk4 :: xgxsStatus2 :: reserved0 [15:13] */
#define SGMII_BLK4_XGXSSTATUS2_RESERVED0_MASK                      0xe000
#define SGMII_BLK4_XGXSSTATUS2_RESERVED0_ALIGN                     0
#define SGMII_BLK4_XGXSSTATUS2_RESERVED0_BITS                      3
#define SGMII_BLK4_XGXSSTATUS2_RESERVED0_SHIFT                     13

/* SGMII_Blk4 :: xgxsStatus2 :: gpwrdwn_rx [12:12] */
#define Wr_SGMII_Blk4_xgxsStatus2_gpwrdwn_rx(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS2,0x1000,12,x)
#define Rd_SGMII_Blk4_xgxsStatus2_gpwrdwn_rx(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS2,0x1000,12)
#define SGMII_BLK4_XGXSSTATUS2_GPWRDWN_RX_MASK                     0x1000
#define SGMII_BLK4_XGXSSTATUS2_GPWRDWN_RX_ALIGN                    0
#define SGMII_BLK4_XGXSSTATUS2_GPWRDWN_RX_BITS                     1
#define SGMII_BLK4_XGXSSTATUS2_GPWRDWN_RX_SHIFT                    12

/* SGMII_Blk4 :: xgxsStatus2 :: reserved1 [11:09] */
#define SGMII_BLK4_XGXSSTATUS2_RESERVED1_MASK                      0x0e00
#define SGMII_BLK4_XGXSSTATUS2_RESERVED1_ALIGN                     0
#define SGMII_BLK4_XGXSSTATUS2_RESERVED1_BITS                      3
#define SGMII_BLK4_XGXSSTATUS2_RESERVED1_SHIFT                     9

/* SGMII_Blk4 :: xgxsStatus2 :: gpwrdwn_tx [08:08] */
#define Wr_SGMII_Blk4_xgxsStatus2_gpwrdwn_tx(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS2,0x100,8,x)
#define Rd_SGMII_Blk4_xgxsStatus2_gpwrdwn_tx(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS2,0x100,8)
#define SGMII_BLK4_XGXSSTATUS2_GPWRDWN_TX_MASK                     0x0100
#define SGMII_BLK4_XGXSSTATUS2_GPWRDWN_TX_ALIGN                    0
#define SGMII_BLK4_XGXSSTATUS2_GPWRDWN_TX_BITS                     1
#define SGMII_BLK4_XGXSSTATUS2_GPWRDWN_TX_SHIFT                    8

/* SGMII_Blk4 :: xgxsStatus2 :: reserved2 [07:05] */
#define SGMII_BLK4_XGXSSTATUS2_RESERVED2_MASK                      0x00e0
#define SGMII_BLK4_XGXSSTATUS2_RESERVED2_ALIGN                     0
#define SGMII_BLK4_XGXSSTATUS2_RESERVED2_BITS                      3
#define SGMII_BLK4_XGXSSTATUS2_RESERVED2_SHIFT                     5

/* SGMII_Blk4 :: xgxsStatus2 :: freq_sel_rx [04:04] */
#define Wr_SGMII_Blk4_xgxsStatus2_freq_sel_rx(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS2,0x10,4,x)
#define Rd_SGMII_Blk4_xgxsStatus2_freq_sel_rx(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS2,0x10,4)
#define SGMII_BLK4_XGXSSTATUS2_FREQ_SEL_RX_MASK                    0x0010
#define SGMII_BLK4_XGXSSTATUS2_FREQ_SEL_RX_ALIGN                   0
#define SGMII_BLK4_XGXSSTATUS2_FREQ_SEL_RX_BITS                    1
#define SGMII_BLK4_XGXSSTATUS2_FREQ_SEL_RX_SHIFT                   4

/* SGMII_Blk4 :: xgxsStatus2 :: reserved3 [03:01] */
#define SGMII_BLK4_XGXSSTATUS2_RESERVED3_MASK                      0x000e
#define SGMII_BLK4_XGXSSTATUS2_RESERVED3_ALIGN                     0
#define SGMII_BLK4_XGXSSTATUS2_RESERVED3_BITS                      3
#define SGMII_BLK4_XGXSSTATUS2_RESERVED3_SHIFT                     1

/* SGMII_Blk4 :: xgxsStatus2 :: freq_sel_tx [00:00] */
#define Wr_SGMII_Blk4_xgxsStatus2_freq_sel_tx(x) WriteRegBits16(SGMII_BLK4_XGXSSTATUS2,0x1,0,x)
#define Rd_SGMII_Blk4_xgxsStatus2_freq_sel_tx(x) ReadRegBits16(SGMII_BLK4_XGXSSTATUS2,0x1,0)
#define SGMII_BLK4_XGXSSTATUS2_FREQ_SEL_TX_MASK                    0x0001
#define SGMII_BLK4_XGXSSTATUS2_FREQ_SEL_TX_ALIGN                   0
#define SGMII_BLK4_XGXSSTATUS2_FREQ_SEL_TX_BITS                    1
#define SGMII_BLK4_XGXSSTATUS2_FREQ_SEL_TX_SHIFT                   0


/****************************************************************************
 * SGMII_Blk4 :: Status1000X1
 ***************************************************************************/
/* SGMII_Blk4 :: Status1000X1 :: txfifo_err_detected [15:15] */
#define Wr_SGMII_Blk4_Status1000X1_txfifo_err_detected(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x8000,15,x)
#define Rd_SGMII_Blk4_Status1000X1_txfifo_err_detected(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x8000,15)
#define SGMII_BLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK           0x8000
#define SGMII_BLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN          0
#define SGMII_BLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS           1
#define SGMII_BLK4_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT          15

/* SGMII_Blk4 :: Status1000X1 :: rxfifo_err_detected [14:14] */
#define Wr_SGMII_Blk4_Status1000X1_rxfifo_err_detected(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x4000,14,x)
#define Rd_SGMII_Blk4_Status1000X1_rxfifo_err_detected(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x4000,14)
#define SGMII_BLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK           0x4000
#define SGMII_BLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN          0
#define SGMII_BLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS           1
#define SGMII_BLK4_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT          14

/* SGMII_Blk4 :: Status1000X1 :: false_carrier_detected [13:13] */
#define Wr_SGMII_Blk4_Status1000X1_false_carrier_detected(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x2000,13,x)
#define Rd_SGMII_Blk4_Status1000X1_false_carrier_detected(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x2000,13)
#define SGMII_BLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK        0x2000
#define SGMII_BLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN       0
#define SGMII_BLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS        1
#define SGMII_BLK4_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT       13

/* SGMII_Blk4 :: Status1000X1 :: crc_err_detected [12:12] */
#define Wr_SGMII_Blk4_Status1000X1_crc_err_detected(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x1000,12,x)
#define Rd_SGMII_Blk4_Status1000X1_crc_err_detected(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x1000,12)
#define SGMII_BLK4_STATUS1000X1_CRC_ERR_DETECTED_MASK              0x1000
#define SGMII_BLK4_STATUS1000X1_CRC_ERR_DETECTED_ALIGN             0
#define SGMII_BLK4_STATUS1000X1_CRC_ERR_DETECTED_BITS              1
#define SGMII_BLK4_STATUS1000X1_CRC_ERR_DETECTED_SHIFT             12

/* SGMII_Blk4 :: Status1000X1 :: tx_err_detected [11:11] */
#define Wr_SGMII_Blk4_Status1000X1_tx_err_detected(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x800,11,x)
#define Rd_SGMII_Blk4_Status1000X1_tx_err_detected(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x800,11)
#define SGMII_BLK4_STATUS1000X1_TX_ERR_DETECTED_MASK               0x0800
#define SGMII_BLK4_STATUS1000X1_TX_ERR_DETECTED_ALIGN              0
#define SGMII_BLK4_STATUS1000X1_TX_ERR_DETECTED_BITS               1
#define SGMII_BLK4_STATUS1000X1_TX_ERR_DETECTED_SHIFT              11

/* SGMII_Blk4 :: Status1000X1 :: rx_err_detected [10:10] */
#define Wr_SGMII_Blk4_Status1000X1_rx_err_detected(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x400,10,x)
#define Rd_SGMII_Blk4_Status1000X1_rx_err_detected(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x400,10)
#define SGMII_BLK4_STATUS1000X1_RX_ERR_DETECTED_MASK               0x0400
#define SGMII_BLK4_STATUS1000X1_RX_ERR_DETECTED_ALIGN              0
#define SGMII_BLK4_STATUS1000X1_RX_ERR_DETECTED_BITS               1
#define SGMII_BLK4_STATUS1000X1_RX_ERR_DETECTED_SHIFT              10

/* SGMII_Blk4 :: Status1000X1 :: carrier_extend_err_detected [09:09] */
#define Wr_SGMII_Blk4_Status1000X1_carrier_extend_err_detected(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x200,9,x)
#define Rd_SGMII_Blk4_Status1000X1_carrier_extend_err_detected(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x200,9)
#define SGMII_BLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK   0x0200
#define SGMII_BLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN  0
#define SGMII_BLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS   1
#define SGMII_BLK4_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT  9

/* SGMII_Blk4 :: Status1000X1 :: early_end_extension_detected [08:08] */
#define Wr_SGMII_Blk4_Status1000X1_early_end_extension_detected(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x100,8,x)
#define Rd_SGMII_Blk4_Status1000X1_early_end_extension_detected(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x100,8)
#define SGMII_BLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK  0x0100
#define SGMII_BLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0
#define SGMII_BLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS  1
#define SGMII_BLK4_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8

/* SGMII_Blk4 :: Status1000X1 :: link_status_change [07:07] */
#define Wr_SGMII_Blk4_Status1000X1_link_status_change(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x80,7,x)
#define Rd_SGMII_Blk4_Status1000X1_link_status_change(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x80,7)
#define SGMII_BLK4_STATUS1000X1_LINK_STATUS_CHANGE_MASK            0x0080
#define SGMII_BLK4_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN           0
#define SGMII_BLK4_STATUS1000X1_LINK_STATUS_CHANGE_BITS            1
#define SGMII_BLK4_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT           7

/* SGMII_Blk4 :: Status1000X1 :: pause_resolution_rxside [06:06] */
#define Wr_SGMII_Blk4_Status1000X1_pause_resolution_rxside(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x40,6,x)
#define Rd_SGMII_Blk4_Status1000X1_pause_resolution_rxside(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x40,6)
#define SGMII_BLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK       0x0040
#define SGMII_BLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN      0
#define SGMII_BLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS       1
#define SGMII_BLK4_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT      6

/* SGMII_Blk4 :: Status1000X1 :: pause_resolution_txside [05:05] */
#define Wr_SGMII_Blk4_Status1000X1_pause_resolution_txside(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x20,5,x)
#define Rd_SGMII_Blk4_Status1000X1_pause_resolution_txside(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x20,5)
#define SGMII_BLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK       0x0020
#define SGMII_BLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN      0
#define SGMII_BLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS       1
#define SGMII_BLK4_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT      5

/* SGMII_Blk4 :: Status1000X1 :: speed_status [04:03] */
#define Wr_SGMII_Blk4_Status1000X1_speed_status(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x18,3,x)
#define Rd_SGMII_Blk4_Status1000X1_speed_status(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x18,3)
#define SGMII_BLK4_STATUS1000X1_SPEED_STATUS_MASK                  0x0018
#define SGMII_BLK4_STATUS1000X1_SPEED_STATUS_ALIGN                 0
#define SGMII_BLK4_STATUS1000X1_SPEED_STATUS_BITS                  2
#define SGMII_BLK4_STATUS1000X1_SPEED_STATUS_SHIFT                 3

/* SGMII_Blk4 :: Status1000X1 :: duplex_status [02:02] */
#define Wr_SGMII_Blk4_Status1000X1_duplex_status(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x4,2,x)
#define Rd_SGMII_Blk4_Status1000X1_duplex_status(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x4,2)
#define SGMII_BLK4_STATUS1000X1_DUPLEX_STATUS_MASK                 0x0004
#define SGMII_BLK4_STATUS1000X1_DUPLEX_STATUS_ALIGN                0
#define SGMII_BLK4_STATUS1000X1_DUPLEX_STATUS_BITS                 1
#define SGMII_BLK4_STATUS1000X1_DUPLEX_STATUS_SHIFT                2

/* SGMII_Blk4 :: Status1000X1 :: link_status [01:01] */
#define Wr_SGMII_Blk4_Status1000X1_link_status(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x2,1,x)
#define Rd_SGMII_Blk4_Status1000X1_link_status(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x2,1)
#define SGMII_BLK4_STATUS1000X1_LINK_STATUS_MASK                   0x0002
#define SGMII_BLK4_STATUS1000X1_LINK_STATUS_ALIGN                  0
#define SGMII_BLK4_STATUS1000X1_LINK_STATUS_BITS                   1
#define SGMII_BLK4_STATUS1000X1_LINK_STATUS_SHIFT                  1

/* SGMII_Blk4 :: Status1000X1 :: sgmii_mode [00:00] */
#define Wr_SGMII_Blk4_Status1000X1_sgmii_mode(x) WriteRegBits16(SGMII_BLK4_STATUS1000X1,0x1,0,x)
#define Rd_SGMII_Blk4_Status1000X1_sgmii_mode(x) ReadRegBits16(SGMII_BLK4_STATUS1000X1,0x1,0)
#define SGMII_BLK4_STATUS1000X1_SGMII_MODE_MASK                    0x0001
#define SGMII_BLK4_STATUS1000X1_SGMII_MODE_ALIGN                   0
#define SGMII_BLK4_STATUS1000X1_SGMII_MODE_BITS                    1
#define SGMII_BLK4_STATUS1000X1_SGMII_MODE_SHIFT                   0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_Blk7
 ***************************************************************************/
/****************************************************************************
 * SGMII_Blk7 :: prbs_decouple
 ***************************************************************************/
/* SGMII_Blk7 :: prbs_decouple :: reserved0 [15:05] */
#define SGMII_BLK7_PRBS_DECOUPLE_RESERVED0_MASK                    0xffe0
#define SGMII_BLK7_PRBS_DECOUPLE_RESERVED0_ALIGN                   0
#define SGMII_BLK7_PRBS_DECOUPLE_RESERVED0_BITS                    11
#define SGMII_BLK7_PRBS_DECOUPLE_RESERVED0_SHIFT                   5

/* SGMII_Blk7 :: prbs_decouple :: tx_datai_prbs_sel [04:04] */
#define Wr_SGMII_Blk7_prbs_decouple_tx_datai_prbs_sel(x) WriteRegBits16(SGMII_BLK7_PRBS_DECOUPLE,0x10,4,x)
#define Rd_SGMII_Blk7_prbs_decouple_tx_datai_prbs_sel(x) ReadRegBits16(SGMII_BLK7_PRBS_DECOUPLE,0x10,4)
#define SGMII_BLK7_PRBS_DECOUPLE_TX_DATAI_PRBS_SEL_MASK            0x0010
#define SGMII_BLK7_PRBS_DECOUPLE_TX_DATAI_PRBS_SEL_ALIGN           0
#define SGMII_BLK7_PRBS_DECOUPLE_TX_DATAI_PRBS_SEL_BITS            1
#define SGMII_BLK7_PRBS_DECOUPLE_TX_DATAI_PRBS_SEL_SHIFT           4

/* SGMII_Blk7 :: prbs_decouple :: reserved1 [03:00] */
#define SGMII_BLK7_PRBS_DECOUPLE_RESERVED1_MASK                    0x000f
#define SGMII_BLK7_PRBS_DECOUPLE_RESERVED1_ALIGN                   0
#define SGMII_BLK7_PRBS_DECOUPLE_RESERVED1_BITS                    4
#define SGMII_BLK7_PRBS_DECOUPLE_RESERVED1_SHIFT                   0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_PLL2
 ***************************************************************************/
/****************************************************************************
 * SGMII_PLL2 :: stat0
 ***************************************************************************/
/* SGMII_PLL2 :: stat0 :: reserved0 [15:13] */
#define SGMII_PLL2_STAT0_RESERVED0_MASK                            0xe000
#define SGMII_PLL2_STAT0_RESERVED0_ALIGN                           0
#define SGMII_PLL2_STAT0_RESERVED0_BITS                            3
#define SGMII_PLL2_STAT0_RESERVED0_SHIFT                           13

/* SGMII_PLL2 :: stat0 :: vco_range [12:06] */
#define Wr_SGMII_PLL2_stat0_vco_range(x) WriteRegBits16(SGMII_PLL2_STAT0,0x1fc0,6,x)
#define Rd_SGMII_PLL2_stat0_vco_range(x) ReadRegBits16(SGMII_PLL2_STAT0,0x1fc0,6)
#define SGMII_PLL2_STAT0_VCO_RANGE_MASK                            0x1fc0
#define SGMII_PLL2_STAT0_VCO_RANGE_ALIGN                           0
#define SGMII_PLL2_STAT0_VCO_RANGE_BITS                            7
#define SGMII_PLL2_STAT0_VCO_RANGE_SHIFT                           6

/* SGMII_PLL2 :: stat0 :: cal_state [05:02] */
#define Wr_SGMII_PLL2_stat0_cal_state(x) WriteRegBits16(SGMII_PLL2_STAT0,0x3c,2,x)
#define Rd_SGMII_PLL2_stat0_cal_state(x) ReadRegBits16(SGMII_PLL2_STAT0,0x3c,2)
#define SGMII_PLL2_STAT0_CAL_STATE_MASK                            0x003c
#define SGMII_PLL2_STAT0_CAL_STATE_ALIGN                           0
#define SGMII_PLL2_STAT0_CAL_STATE_BITS                            4
#define SGMII_PLL2_STAT0_CAL_STATE_SHIFT                           2

/* SGMII_PLL2 :: stat0 :: cal_valid [01:01] */
#define Wr_SGMII_PLL2_stat0_cal_valid(x) WriteRegBits16(SGMII_PLL2_STAT0,0x2,1,x)
#define Rd_SGMII_PLL2_stat0_cal_valid(x) ReadRegBits16(SGMII_PLL2_STAT0,0x2,1)
#define SGMII_PLL2_STAT0_CAL_VALID_MASK                            0x0002
#define SGMII_PLL2_STAT0_CAL_VALID_ALIGN                           0
#define SGMII_PLL2_STAT0_CAL_VALID_BITS                            1
#define SGMII_PLL2_STAT0_CAL_VALID_SHIFT                           1

/* SGMII_PLL2 :: stat0 :: cal_error [00:00] */
#define Wr_SGMII_PLL2_stat0_cal_error(x) WriteRegBits16(SGMII_PLL2_STAT0,0x1,0,x)
#define Rd_SGMII_PLL2_stat0_cal_error(x) ReadRegBits16(SGMII_PLL2_STAT0,0x1,0)
#define SGMII_PLL2_STAT0_CAL_ERROR_MASK                            0x0001
#define SGMII_PLL2_STAT0_CAL_ERROR_ALIGN                           0
#define SGMII_PLL2_STAT0_CAL_ERROR_BITS                            1
#define SGMII_PLL2_STAT0_CAL_ERROR_SHIFT                           0


/****************************************************************************
 * SGMII_PLL2 :: ctrl1
 ***************************************************************************/
/* SGMII_PLL2 :: ctrl1 :: reserved0 [15:11] */
#define SGMII_PLL2_CTRL1_RESERVED0_MASK                            0xf800
#define SGMII_PLL2_CTRL1_RESERVED0_ALIGN                           0
#define SGMII_PLL2_CTRL1_RESERVED0_BITS                            5
#define SGMII_PLL2_CTRL1_RESERVED0_SHIFT                           11

/* SGMII_PLL2 :: ctrl1 :: cal_th [10:07] */
#define Wr_SGMII_PLL2_ctrl1_cal_th(x) WriteRegBits16(SGMII_PLL2_CTRL1,0x780,7,x)
#define Rd_SGMII_PLL2_ctrl1_cal_th(x) ReadRegBits16(SGMII_PLL2_CTRL1,0x780,7)
#define SGMII_PLL2_CTRL1_CAL_TH_MASK                               0x0780
#define SGMII_PLL2_CTRL1_CAL_TH_ALIGN                              0
#define SGMII_PLL2_CTRL1_CAL_TH_BITS                               4
#define SGMII_PLL2_CTRL1_CAL_TH_SHIFT                              7

/* SGMII_PLL2 :: ctrl1 :: ext_range [06:00] */
#define Wr_SGMII_PLL2_ctrl1_ext_range(x) WriteRegBits16(SGMII_PLL2_CTRL1,0x7f,0,x)
#define Rd_SGMII_PLL2_ctrl1_ext_range(x) ReadRegBits16(SGMII_PLL2_CTRL1,0x7f,0)
#define SGMII_PLL2_CTRL1_EXT_RANGE_MASK                            0x007f
#define SGMII_PLL2_CTRL1_EXT_RANGE_ALIGN                           0
#define SGMII_PLL2_CTRL1_EXT_RANGE_BITS                            7
#define SGMII_PLL2_CTRL1_EXT_RANGE_SHIFT                           0


/****************************************************************************
 * SGMII_PLL2 :: ctrl2
 ***************************************************************************/
/* SGMII_PLL2 :: ctrl2 :: reserved0 [15:15] */
#define SGMII_PLL2_CTRL2_RESERVED0_MASK                            0x8000
#define SGMII_PLL2_CTRL2_RESERVED0_ALIGN                           0
#define SGMII_PLL2_CTRL2_RESERVED0_BITS                            1
#define SGMII_PLL2_CTRL2_RESERVED0_SHIFT                           15

/* SGMII_PLL2 :: ctrl2 :: range_dfs [14:08] */
#define Wr_SGMII_PLL2_ctrl2_range_dfs(x) WriteRegBits16(SGMII_PLL2_CTRL2,0x7f00,8,x)
#define Rd_SGMII_PLL2_ctrl2_range_dfs(x) ReadRegBits16(SGMII_PLL2_CTRL2,0x7f00,8)
#define SGMII_PLL2_CTRL2_RANGE_DFS_MASK                            0x7f00
#define SGMII_PLL2_CTRL2_RANGE_DFS_ALIGN                           0
#define SGMII_PLL2_CTRL2_RANGE_DFS_BITS                            7
#define SGMII_PLL2_CTRL2_RANGE_DFS_SHIFT                           8

/* SGMII_PLL2 :: ctrl2 :: range_ovrd [07:07] */
#define Wr_SGMII_PLL2_ctrl2_range_ovrd(x) WriteRegBits16(SGMII_PLL2_CTRL2,0x80,7,x)
#define Rd_SGMII_PLL2_ctrl2_range_ovrd(x) ReadRegBits16(SGMII_PLL2_CTRL2,0x80,7)
#define SGMII_PLL2_CTRL2_RANGE_OVRD_MASK                           0x0080
#define SGMII_PLL2_CTRL2_RANGE_OVRD_ALIGN                          0
#define SGMII_PLL2_CTRL2_RANGE_OVRD_BITS                           1
#define SGMII_PLL2_CTRL2_RANGE_OVRD_SHIFT                          7

/* SGMII_PLL2 :: ctrl2 :: range_ovrd_val [06:00] */
#define Wr_SGMII_PLL2_ctrl2_range_ovrd_val(x) WriteRegBits16(SGMII_PLL2_CTRL2,0x7f,0,x)
#define Rd_SGMII_PLL2_ctrl2_range_ovrd_val(x) ReadRegBits16(SGMII_PLL2_CTRL2,0x7f,0)
#define SGMII_PLL2_CTRL2_RANGE_OVRD_VAL_MASK                       0x007f
#define SGMII_PLL2_CTRL2_RANGE_OVRD_VAL_ALIGN                      0
#define SGMII_PLL2_CTRL2_RANGE_OVRD_VAL_BITS                       7
#define SGMII_PLL2_CTRL2_RANGE_OVRD_VAL_SHIFT                      0


/****************************************************************************
 * SGMII_PLL2 :: ctrl3
 ***************************************************************************/
/* SGMII_PLL2 :: ctrl3 :: calib_cap_charge_time [15:00] */
#define Wr_SGMII_PLL2_ctrl3_calib_cap_charge_time(x) WriteReg16(SGMII_PLL2_CTRL3,x)
#define Rd_SGMII_PLL2_ctrl3_calib_cap_charge_time(x) ReadReg16(SGMII_PLL2_CTRL3)
#define SGMII_PLL2_CTRL3_CALIB_CAP_CHARGE_TIME_MASK                0xffff
#define SGMII_PLL2_CTRL3_CALIB_CAP_CHARGE_TIME_ALIGN               0
#define SGMII_PLL2_CTRL3_CALIB_CAP_CHARGE_TIME_BITS                16
#define SGMII_PLL2_CTRL3_CALIB_CAP_CHARGE_TIME_SHIFT               0


/****************************************************************************
 * SGMII_PLL2 :: ctrl4
 ***************************************************************************/
/* SGMII_PLL2 :: ctrl4 :: calib_delay_time [15:00] */
#define Wr_SGMII_PLL2_ctrl4_calib_delay_time(x) WriteReg16(SGMII_PLL2_CTRL4,x)
#define Rd_SGMII_PLL2_ctrl4_calib_delay_time(x) ReadReg16(SGMII_PLL2_CTRL4)
#define SGMII_PLL2_CTRL4_CALIB_DELAY_TIME_MASK                     0xffff
#define SGMII_PLL2_CTRL4_CALIB_DELAY_TIME_ALIGN                    0
#define SGMII_PLL2_CTRL4_CALIB_DELAY_TIME_BITS                     16
#define SGMII_PLL2_CTRL4_CALIB_DELAY_TIME_SHIFT                    0


/****************************************************************************
 * SGMII_PLL2 :: ctrl5
 ***************************************************************************/
/* SGMII_PLL2 :: ctrl5 :: calib_step_time [15:00] */
#define Wr_SGMII_PLL2_ctrl5_calib_step_time(x) WriteReg16(SGMII_PLL2_CTRL5,x)
#define Rd_SGMII_PLL2_ctrl5_calib_step_time(x) ReadReg16(SGMII_PLL2_CTRL5)
#define SGMII_PLL2_CTRL5_CALIB_STEP_TIME_MASK                      0xffff
#define SGMII_PLL2_CTRL5_CALIB_STEP_TIME_ALIGN                     0
#define SGMII_PLL2_CTRL5_CALIB_STEP_TIME_BITS                      16
#define SGMII_PLL2_CTRL5_CALIB_STEP_TIME_SHIFT                     0


/****************************************************************************
 * SGMII_PLL2 :: ctrl6
 ***************************************************************************/
/* SGMII_PLL2 :: ctrl6 :: reserved0 [15:07] */
#define SGMII_PLL2_CTRL6_RESERVED0_MASK                            0xff80
#define SGMII_PLL2_CTRL6_RESERVED0_ALIGN                           0
#define SGMII_PLL2_CTRL6_RESERVED0_BITS                            9
#define SGMII_PLL2_CTRL6_RESERVED0_SHIFT                           7

/* SGMII_PLL2 :: ctrl6 :: dfe0_en_calib_n [06:06] */
#define Wr_SGMII_PLL2_ctrl6_dfe0_en_calib_n(x) WriteRegBits16(SGMII_PLL2_CTRL6,0x40,6,x)
#define Rd_SGMII_PLL2_ctrl6_dfe0_en_calib_n(x) ReadRegBits16(SGMII_PLL2_CTRL6,0x40,6)
#define SGMII_PLL2_CTRL6_DFE0_EN_CALIB_N_MASK                      0x0040
#define SGMII_PLL2_CTRL6_DFE0_EN_CALIB_N_ALIGN                     0
#define SGMII_PLL2_CTRL6_DFE0_EN_CALIB_N_BITS                      1
#define SGMII_PLL2_CTRL6_DFE0_EN_CALIB_N_SHIFT                     6

/* SGMII_PLL2 :: ctrl6 :: dfe0_halfstep_en [05:05] */
#define Wr_SGMII_PLL2_ctrl6_dfe0_halfstep_en(x) WriteRegBits16(SGMII_PLL2_CTRL6,0x20,5,x)
#define Rd_SGMII_PLL2_ctrl6_dfe0_halfstep_en(x) ReadRegBits16(SGMII_PLL2_CTRL6,0x20,5)
#define SGMII_PLL2_CTRL6_DFE0_HALFSTEP_EN_MASK                     0x0020
#define SGMII_PLL2_CTRL6_DFE0_HALFSTEP_EN_ALIGN                    0
#define SGMII_PLL2_CTRL6_DFE0_HALFSTEP_EN_BITS                     1
#define SGMII_PLL2_CTRL6_DFE0_HALFSTEP_EN_SHIFT                    5

/* SGMII_PLL2 :: ctrl6 :: dfe0_calib_search_bit [04:02] */
#define Wr_SGMII_PLL2_ctrl6_dfe0_calib_search_bit(x) WriteRegBits16(SGMII_PLL2_CTRL6,0x1c,2,x)
#define Rd_SGMII_PLL2_ctrl6_dfe0_calib_search_bit(x) ReadRegBits16(SGMII_PLL2_CTRL6,0x1c,2)
#define SGMII_PLL2_CTRL6_DFE0_CALIB_SEARCH_BIT_MASK                0x001c
#define SGMII_PLL2_CTRL6_DFE0_CALIB_SEARCH_BIT_ALIGN               0
#define SGMII_PLL2_CTRL6_DFE0_CALIB_SEARCH_BIT_BITS                3
#define SGMII_PLL2_CTRL6_DFE0_CALIB_SEARCH_BIT_SHIFT               2

/* SGMII_PLL2 :: ctrl6 :: dfe0_vcocal_valid_ovrd [01:01] */
#define Wr_SGMII_PLL2_ctrl6_dfe0_vcocal_valid_ovrd(x) WriteRegBits16(SGMII_PLL2_CTRL6,0x2,1,x)
#define Rd_SGMII_PLL2_ctrl6_dfe0_vcocal_valid_ovrd(x) ReadRegBits16(SGMII_PLL2_CTRL6,0x2,1)
#define SGMII_PLL2_CTRL6_DFE0_VCOCAL_VALID_OVRD_MASK               0x0002
#define SGMII_PLL2_CTRL6_DFE0_VCOCAL_VALID_OVRD_ALIGN              0
#define SGMII_PLL2_CTRL6_DFE0_VCOCAL_VALID_OVRD_BITS               1
#define SGMII_PLL2_CTRL6_DFE0_VCOCAL_VALID_OVRD_SHIFT              1

/* SGMII_PLL2 :: ctrl6 :: dfe0_vcocal_valid_ovrd_val [00:00] */
#define Wr_SGMII_PLL2_ctrl6_dfe0_vcocal_valid_ovrd_val(x) WriteRegBits16(SGMII_PLL2_CTRL6,0x1,0,x)
#define Rd_SGMII_PLL2_ctrl6_dfe0_vcocal_valid_ovrd_val(x) ReadRegBits16(SGMII_PLL2_CTRL6,0x1,0)
#define SGMII_PLL2_CTRL6_DFE0_VCOCAL_VALID_OVRD_VAL_MASK           0x0001
#define SGMII_PLL2_CTRL6_DFE0_VCOCAL_VALID_OVRD_VAL_ALIGN          0
#define SGMII_PLL2_CTRL6_DFE0_VCOCAL_VALID_OVRD_VAL_BITS           1
#define SGMII_PLL2_CTRL6_DFE0_VCOCAL_VALID_OVRD_VAL_SHIFT          0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_Digital
 ***************************************************************************/
/****************************************************************************
 * SGMII0_Digital :: Control1000X1
 ***************************************************************************/
/* SGMII0_Digital :: Control1000X1 :: reserved0 [15:15] */
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED0_MASK                0x8000
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED0_ALIGN               0
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED0_BITS                1
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED0_SHIFT               15

/* SGMII0_Digital :: Control1000X1 :: disable_signal_detect_filter [14:14] */
#define Wr_SGMII0_Digital_Control1000X1_disable_signal_detect_filter(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x4000,14,x)
#define Rd_SGMII0_Digital_Control1000X1_disable_signal_detect_filter(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x4000,14)
#define SGMII0_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000
#define SGMII0_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1
#define SGMII0_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14

/* SGMII0_Digital :: Control1000X1 :: reserved1 [13:12] */
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED1_MASK                0x3000
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED1_ALIGN               0
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED1_BITS                2
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED1_SHIFT               12

/* SGMII0_Digital :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */
#define Wr_SGMII0_Digital_Control1000X1_sel_rx_pkts_for_cntr(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x800,11,x)
#define Rd_SGMII0_Digital_Control1000X1_sel_rx_pkts_for_cntr(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x800,11)
#define SGMII0_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK     0x0800
#define SGMII0_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN    0
#define SGMII0_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS     1
#define SGMII0_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT    11

/* SGMII0_Digital :: Control1000X1 :: remote_loopback [10:10] */
#define Wr_SGMII0_Digital_Control1000X1_remote_loopback(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x400,10,x)
#define Rd_SGMII0_Digital_Control1000X1_remote_loopback(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x400,10)
#define SGMII0_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_MASK          0x0400
#define SGMII0_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN         0
#define SGMII0_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_BITS          1
#define SGMII0_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT         10

/* SGMII0_Digital :: Control1000X1 :: zero_comma_detector_phase [09:09] */
#define Wr_SGMII0_Digital_Control1000X1_zero_comma_detector_phase(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x200,9,x)
#define Rd_SGMII0_Digital_Control1000X1_zero_comma_detector_phase(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x200,9)
#define SGMII0_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200
#define SGMII0_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1
#define SGMII0_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9

/* SGMII0_Digital :: Control1000X1 :: comma_det_en [08:08] */
#define Wr_SGMII0_Digital_Control1000X1_comma_det_en(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x100,8,x)
#define Rd_SGMII0_Digital_Control1000X1_comma_det_en(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x100,8)
#define SGMII0_DIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK             0x0100
#define SGMII0_DIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN            0
#define SGMII0_DIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS             1
#define SGMII0_DIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT            8

/* SGMII0_Digital :: Control1000X1 :: crc_checker_disable [07:07] */
#define Wr_SGMII0_Digital_Control1000X1_crc_checker_disable(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x80,7,x)
#define Rd_SGMII0_Digital_Control1000X1_crc_checker_disable(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x80,7)
#define SGMII0_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK      0x0080
#define SGMII0_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN     0
#define SGMII0_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS      1
#define SGMII0_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT     7

/* SGMII0_Digital :: Control1000X1 :: disable_pll_pwrdwn [06:06] */
#define Wr_SGMII0_Digital_Control1000X1_disable_pll_pwrdwn(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x40,6,x)
#define Rd_SGMII0_Digital_Control1000X1_disable_pll_pwrdwn(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x40,6)
#define SGMII0_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK       0x0040
#define SGMII0_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN      0
#define SGMII0_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS       1
#define SGMII0_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT      6

/* SGMII0_Digital :: Control1000X1 :: sgmii_master_mode [05:05] */
#define Wr_SGMII0_Digital_Control1000X1_sgmii_master_mode(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x20,5,x)
#define Rd_SGMII0_Digital_Control1000X1_sgmii_master_mode(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x20,5)
#define SGMII0_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_MASK        0x0020
#define SGMII0_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN       0
#define SGMII0_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_BITS        1
#define SGMII0_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT       5

/* SGMII0_Digital :: Control1000X1 :: reserved2 [04:04] */
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED2_MASK                0x0010
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED2_ALIGN               0
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED2_BITS                1
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED2_SHIFT               4

/* SGMII0_Digital :: Control1000X1 :: invert_signal_detect [03:03] */
#define Wr_SGMII0_Digital_Control1000X1_invert_signal_detect(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x8,3,x)
#define Rd_SGMII0_Digital_Control1000X1_invert_signal_detect(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x8,3)
#define SGMII0_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK     0x0008
#define SGMII0_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN    0
#define SGMII0_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS     1
#define SGMII0_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT    3

/* SGMII0_Digital :: Control1000X1 :: signal_detect_en [02:02] */
#define Wr_SGMII0_Digital_Control1000X1_signal_detect_en(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x4,2,x)
#define Rd_SGMII0_Digital_Control1000X1_signal_detect_en(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x4,2)
#define SGMII0_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_MASK         0x0004
#define SGMII0_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN        0
#define SGMII0_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_BITS         1
#define SGMII0_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT        2

/* SGMII0_Digital :: Control1000X1 :: reserved3 [01:01] */
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED3_MASK                0x0002
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED3_ALIGN               0
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED3_BITS                1
#define SGMII0_DIGITAL_CONTROL1000X1_RESERVED3_SHIFT               1

/* SGMII0_Digital :: Control1000X1 :: fiber_mode_1000X [00:00] */
#define Wr_SGMII0_Digital_Control1000X1_fiber_mode_1000X(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x1,0,x)
#define Rd_SGMII0_Digital_Control1000X1_fiber_mode_1000X(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X1,0x1,0)
#define SGMII0_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_MASK         0x0001
#define SGMII0_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_ALIGN        0
#define SGMII0_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_BITS         1
#define SGMII0_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_SHIFT        0


/****************************************************************************
 * SGMII0_Digital :: Control1000X2
 ***************************************************************************/
/* SGMII0_Digital :: Control1000X2 :: disable_extend_fdx_only [15:15] */
#define Wr_SGMII0_Digital_Control1000X2_disable_extend_fdx_only(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x8000,15,x)
#define Rd_SGMII0_Digital_Control1000X2_disable_extend_fdx_only(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x8000,15)
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK  0x8000
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS  1
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT 15

/* SGMII0_Digital :: Control1000X2 :: clear_ber_counter [14:14] */
#define Wr_SGMII0_Digital_Control1000X2_clear_ber_counter(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x4000,14,x)
#define Rd_SGMII0_Digital_Control1000X2_clear_ber_counter(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x4000,14)
#define SGMII0_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK        0x4000
#define SGMII0_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN       0
#define SGMII0_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS        1
#define SGMII0_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT       14

/* SGMII0_Digital :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */
#define Wr_SGMII0_Digital_Control1000X2_transmit_idlejam_seq_test(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x2000,13,x)
#define Rd_SGMII0_Digital_Control1000X2_transmit_idlejam_seq_test(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x2000,13)
#define SGMII0_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000
#define SGMII0_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1
#define SGMII0_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13

/* SGMII0_Digital :: Control1000X2 :: transmit_packet_seq_test [12:12] */
#define Wr_SGMII0_Digital_Control1000X2_transmit_packet_seq_test(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x1000,12,x)
#define Rd_SGMII0_Digital_Control1000X2_transmit_packet_seq_test(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x1000,12)
#define SGMII0_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK 0x1000
#define SGMII0_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS 1
#define SGMII0_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12

/* SGMII0_Digital :: Control1000X2 :: test_cntr [11:11] */
#define Wr_SGMII0_Digital_Control1000X2_test_cntr(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x800,11,x)
#define Rd_SGMII0_Digital_Control1000X2_test_cntr(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x800,11)
#define SGMII0_DIGITAL_CONTROL1000X2_TEST_CNTR_MASK                0x0800
#define SGMII0_DIGITAL_CONTROL1000X2_TEST_CNTR_ALIGN               0
#define SGMII0_DIGITAL_CONTROL1000X2_TEST_CNTR_BITS                1
#define SGMII0_DIGITAL_CONTROL1000X2_TEST_CNTR_SHIFT               11

/* SGMII0_Digital :: Control1000X2 :: bypass_pcs_tx [10:10] */
#define Wr_SGMII0_Digital_Control1000X2_bypass_pcs_tx(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x400,10,x)
#define Rd_SGMII0_Digital_Control1000X2_bypass_pcs_tx(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x400,10)
#define SGMII0_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_MASK            0x0400
#define SGMII0_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_ALIGN           0
#define SGMII0_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_BITS            1
#define SGMII0_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_SHIFT           10

/* SGMII0_Digital :: Control1000X2 :: bypass_pcs_rx [09:09] */
#define Wr_SGMII0_Digital_Control1000X2_bypass_pcs_rx(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x200,9,x)
#define Rd_SGMII0_Digital_Control1000X2_bypass_pcs_rx(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x200,9)
#define SGMII0_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_MASK            0x0200
#define SGMII0_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_ALIGN           0
#define SGMII0_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_BITS            1
#define SGMII0_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_SHIFT           9

/* SGMII0_Digital :: Control1000X2 :: disable_TRRR_generation [08:08] */
#define Wr_SGMII0_Digital_Control1000X2_disable_TRRR_generation(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x100,8,x)
#define Rd_SGMII0_Digital_Control1000X2_disable_TRRR_generation(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x100,8)
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK  0x0100
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS  1
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT 8

/* SGMII0_Digital :: Control1000X2 :: disable_carrier_extend [07:07] */
#define Wr_SGMII0_Digital_Control1000X2_disable_carrier_extend(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x80,7,x)
#define Rd_SGMII0_Digital_Control1000X2_disable_carrier_extend(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x80,7)
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK   0x0080
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN  0
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS   1
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT  7

/* SGMII0_Digital :: Control1000X2 :: autoneg_fast_timers [06:06] */
#define Wr_SGMII0_Digital_Control1000X2_autoneg_fast_timers(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x40,6,x)
#define Rd_SGMII0_Digital_Control1000X2_autoneg_fast_timers(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x40,6)
#define SGMII0_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK      0x0040
#define SGMII0_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN     0
#define SGMII0_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS      1
#define SGMII0_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT     6

/* SGMII0_Digital :: Control1000X2 :: force_xmit_data_on_txside [05:05] */
#define Wr_SGMII0_Digital_Control1000X2_force_xmit_data_on_txside(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x20,5,x)
#define Rd_SGMII0_Digital_Control1000X2_force_xmit_data_on_txside(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x20,5)
#define SGMII0_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020
#define SGMII0_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1
#define SGMII0_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5

/* SGMII0_Digital :: Control1000X2 :: disable_remote_fault_sensing [04:04] */
#define Wr_SGMII0_Digital_Control1000X2_disable_remote_fault_sensing(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x10,4,x)
#define Rd_SGMII0_Digital_Control1000X2_disable_remote_fault_sensing(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x10,4)
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4

/* SGMII0_Digital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */
#define Wr_SGMII0_Digital_Control1000X2_enable_autoneg_err_timer(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x8,3,x)
#define Rd_SGMII0_Digital_Control1000X2_enable_autoneg_err_timer(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x8,3)
#define SGMII0_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK 0x0008
#define SGMII0_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS 1
#define SGMII0_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3

/* SGMII0_Digital :: Control1000X2 :: filter_force_link [02:02] */
#define Wr_SGMII0_Digital_Control1000X2_filter_force_link(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x4,2,x)
#define Rd_SGMII0_Digital_Control1000X2_filter_force_link(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x4,2)
#define SGMII0_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK        0x0004
#define SGMII0_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN       0
#define SGMII0_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS        1
#define SGMII0_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT       2

/* SGMII0_Digital :: Control1000X2 :: disable_false_link [01:01] */
#define Wr_SGMII0_Digital_Control1000X2_disable_false_link(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x2,1,x)
#define Rd_SGMII0_Digital_Control1000X2_disable_false_link(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X2,0x2,1)
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_MASK       0x0002
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN      0
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_BITS       1
#define SGMII0_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT      1

/* SGMII0_Digital :: Control1000X2 :: reserved0 [00:00] */
#define SGMII0_DIGITAL_CONTROL1000X2_RESERVED0_MASK                0x0001
#define SGMII0_DIGITAL_CONTROL1000X2_RESERVED0_ALIGN               0
#define SGMII0_DIGITAL_CONTROL1000X2_RESERVED0_BITS                1
#define SGMII0_DIGITAL_CONTROL1000X2_RESERVED0_SHIFT               0


/****************************************************************************
 * SGMII0_Digital :: Control1000X3
 ***************************************************************************/
/* SGMII0_Digital :: Control1000X3 :: disable_packet_misalign [15:15] */
#define Wr_SGMII0_Digital_Control1000X3_disable_packet_misalign(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x8000,15,x)
#define Rd_SGMII0_Digital_Control1000X3_disable_packet_misalign(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x8000,15)
#define SGMII0_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK  0x8000
#define SGMII0_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS  1
#define SGMII0_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT 15

/* SGMII0_Digital :: Control1000X3 :: rxfifo_gmii_reset [14:14] */
#define Wr_SGMII0_Digital_Control1000X3_rxfifo_gmii_reset(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x4000,14,x)
#define Rd_SGMII0_Digital_Control1000X3_rxfifo_gmii_reset(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x4000,14)
#define SGMII0_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_MASK        0x4000
#define SGMII0_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN       0
#define SGMII0_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_BITS        1
#define SGMII0_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT       14

/* SGMII0_Digital :: Control1000X3 :: disable_tx_crs [13:13] */
#define Wr_SGMII0_Digital_Control1000X3_disable_tx_crs(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x2000,13,x)
#define Rd_SGMII0_Digital_Control1000X3_disable_tx_crs(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x2000,13)
#define SGMII0_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_MASK           0x2000
#define SGMII0_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_ALIGN          0
#define SGMII0_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_BITS           1
#define SGMII0_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_SHIFT          13

/* SGMII0_Digital :: Control1000X3 :: invert_ext_phy_crs [12:12] */
#define Wr_SGMII0_Digital_Control1000X3_invert_ext_phy_crs(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x1000,12,x)
#define Rd_SGMII0_Digital_Control1000X3_invert_ext_phy_crs(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x1000,12)
#define SGMII0_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK       0x1000
#define SGMII0_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN      0
#define SGMII0_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS       1
#define SGMII0_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT      12

/* SGMII0_Digital :: Control1000X3 :: ext_phy_crs_mode [11:11] */
#define Wr_SGMII0_Digital_Control1000X3_ext_phy_crs_mode(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x800,11,x)
#define Rd_SGMII0_Digital_Control1000X3_ext_phy_crs_mode(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x800,11)
#define SGMII0_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK         0x0800
#define SGMII0_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN        0
#define SGMII0_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS         1
#define SGMII0_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT        11

/* SGMII0_Digital :: Control1000X3 :: jam_false_carrier_mode [10:10] */
#define Wr_SGMII0_Digital_Control1000X3_jam_false_carrier_mode(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x400,10,x)
#define Rd_SGMII0_Digital_Control1000X3_jam_false_carrier_mode(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x400,10)
#define SGMII0_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK   0x0400
#define SGMII0_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN  0
#define SGMII0_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS   1
#define SGMII0_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT  10

/* SGMII0_Digital :: Control1000X3 :: block_txen_mode [09:09] */
#define Wr_SGMII0_Digital_Control1000X3_block_txen_mode(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x200,9,x)
#define Rd_SGMII0_Digital_Control1000X3_block_txen_mode(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x200,9)
#define SGMII0_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_MASK          0x0200
#define SGMII0_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN         0
#define SGMII0_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_BITS          1
#define SGMII0_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT         9

/* SGMII0_Digital :: Control1000X3 :: force_txfifo_on [08:08] */
#define Wr_SGMII0_Digital_Control1000X3_force_txfifo_on(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x100,8,x)
#define Rd_SGMII0_Digital_Control1000X3_force_txfifo_on(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x100,8)
#define SGMII0_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_MASK          0x0100
#define SGMII0_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN         0
#define SGMII0_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_BITS          1
#define SGMII0_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT         8

/* SGMII0_Digital :: Control1000X3 :: bypass_txfifo1000 [07:07] */
#define Wr_SGMII0_Digital_Control1000X3_bypass_txfifo1000(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x80,7,x)
#define Rd_SGMII0_Digital_Control1000X3_bypass_txfifo1000(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x80,7)
#define SGMII0_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_MASK        0x0080
#define SGMII0_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN       0
#define SGMII0_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_BITS        1
#define SGMII0_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT       7

/* SGMII0_Digital :: Control1000X3 :: reserved_6 [06:06] */
#define SGMII0_DIGITAL_CONTROL1000X3_RESERVED_6_MASK               0x0040
#define SGMII0_DIGITAL_CONTROL1000X3_RESERVED_6_ALIGN              0
#define SGMII0_DIGITAL_CONTROL1000X3_RESERVED_6_BITS               1
#define SGMII0_DIGITAL_CONTROL1000X3_RESERVED_6_SHIFT              6

/* SGMII0_Digital :: Control1000X3 :: reserved_5 [05:05] */
#define SGMII0_DIGITAL_CONTROL1000X3_RESERVED_5_MASK               0x0020
#define SGMII0_DIGITAL_CONTROL1000X3_RESERVED_5_ALIGN              0
#define SGMII0_DIGITAL_CONTROL1000X3_RESERVED_5_BITS               1
#define SGMII0_DIGITAL_CONTROL1000X3_RESERVED_5_SHIFT              5

/* SGMII0_Digital :: Control1000X3 :: early_preamble_rx [04:04] */
#define Wr_SGMII0_Digital_Control1000X3_early_preamble_rx(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x10,4,x)
#define Rd_SGMII0_Digital_Control1000X3_early_preamble_rx(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x10,4)
#define SGMII0_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK        0x0010
#define SGMII0_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN       0
#define SGMII0_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS        1
#define SGMII0_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT       4

/* SGMII0_Digital :: Control1000X3 :: early_preamble_tx [03:03] */
#define Wr_SGMII0_Digital_Control1000X3_early_preamble_tx(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x8,3,x)
#define Rd_SGMII0_Digital_Control1000X3_early_preamble_tx(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x8,3)
#define SGMII0_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK        0x0008
#define SGMII0_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN       0
#define SGMII0_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS        1
#define SGMII0_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT       3

/* SGMII0_Digital :: Control1000X3 :: fifo_elasicity_tx [02:01] */
#define Wr_SGMII0_Digital_Control1000X3_fifo_elasicity_tx(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x6,1,x)
#define Rd_SGMII0_Digital_Control1000X3_fifo_elasicity_tx(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x6,1)
#define SGMII0_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_MASK        0x0006
#define SGMII0_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_ALIGN       0
#define SGMII0_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_BITS        2
#define SGMII0_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_SHIFT       1

/* SGMII0_Digital :: Control1000X3 :: tx_fifo_rst [00:00] */
#define Wr_SGMII0_Digital_Control1000X3_tx_fifo_rst(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x1,0,x)
#define Rd_SGMII0_Digital_Control1000X3_tx_fifo_rst(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X3,0x1,0)
#define SGMII0_DIGITAL_CONTROL1000X3_TX_FIFO_RST_MASK              0x0001
#define SGMII0_DIGITAL_CONTROL1000X3_TX_FIFO_RST_ALIGN             0
#define SGMII0_DIGITAL_CONTROL1000X3_TX_FIFO_RST_BITS              1
#define SGMII0_DIGITAL_CONTROL1000X3_TX_FIFO_RST_SHIFT             0


/****************************************************************************
 * SGMII0_Digital :: Control1000X4
 ***************************************************************************/
/* SGMII0_Digital :: Control1000X4 :: reserved0 [15:14] */
#define SGMII0_DIGITAL_CONTROL1000X4_RESERVED0_MASK                0xc000
#define SGMII0_DIGITAL_CONTROL1000X4_RESERVED0_ALIGN               0
#define SGMII0_DIGITAL_CONTROL1000X4_RESERVED0_BITS                2
#define SGMII0_DIGITAL_CONTROL1000X4_RESERVED0_SHIFT               14

/* SGMII0_Digital :: Control1000X4 :: disable_resolution_err_restart [13:13] */
#define Wr_SGMII0_Digital_Control1000X4_disable_resolution_err_restart(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x2000,13,x)
#define Rd_SGMII0_Digital_Control1000X4_disable_resolution_err_restart(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x2000,13)
#define SGMII0_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000
#define SGMII0_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1
#define SGMII0_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13

/* SGMII0_Digital :: Control1000X4 :: enable_last_resolution_err [12:12] */
#define Wr_SGMII0_Digital_Control1000X4_enable_last_resolution_err(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x1000,12,x)
#define Rd_SGMII0_Digital_Control1000X4_enable_last_resolution_err(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x1000,12)
#define SGMII0_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000
#define SGMII0_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0
#define SGMII0_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1
#define SGMII0_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12

/* SGMII0_Digital :: Control1000X4 :: tx_config_reg_sel [11:11] */
#define Wr_SGMII0_Digital_Control1000X4_tx_config_reg_sel(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x800,11,x)
#define Rd_SGMII0_Digital_Control1000X4_tx_config_reg_sel(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x800,11)
#define SGMII0_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK        0x0800
#define SGMII0_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN       0
#define SGMII0_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS        1
#define SGMII0_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT       11

/* SGMII0_Digital :: Control1000X4 :: zero_rxdgmii [10:10] */
#define Wr_SGMII0_Digital_Control1000X4_zero_rxdgmii(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x400,10,x)
#define Rd_SGMII0_Digital_Control1000X4_zero_rxdgmii(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x400,10)
#define SGMII0_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_MASK             0x0400
#define SGMII0_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_ALIGN            0
#define SGMII0_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_BITS             1
#define SGMII0_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_SHIFT            10

/* SGMII0_Digital :: Control1000X4 :: clear_linkdown [09:09] */
#define Wr_SGMII0_Digital_Control1000X4_clear_linkdown(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x200,9,x)
#define Rd_SGMII0_Digital_Control1000X4_clear_linkdown(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x200,9)
#define SGMII0_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK           0x0200
#define SGMII0_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN          0
#define SGMII0_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS           1
#define SGMII0_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT          9

/* SGMII0_Digital :: Control1000X4 :: latch_linkdown_enable [08:08] */
#define Wr_SGMII0_Digital_Control1000X4_latch_linkdown_enable(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x100,8,x)
#define Rd_SGMII0_Digital_Control1000X4_latch_linkdown_enable(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x100,8)
#define SGMII0_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK    0x0100
#define SGMII0_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN   0
#define SGMII0_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS    1
#define SGMII0_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT   8

/* SGMII0_Digital :: Control1000X4 :: link_force [07:07] */
#define Wr_SGMII0_Digital_Control1000X4_link_force(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x80,7,x)
#define Rd_SGMII0_Digital_Control1000X4_link_force(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x80,7)
#define SGMII0_DIGITAL_CONTROL1000X4_LINK_FORCE_MASK               0x0080
#define SGMII0_DIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN              0
#define SGMII0_DIGITAL_CONTROL1000X4_LINK_FORCE_BITS               1
#define SGMII0_DIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT              7

/* SGMII0_Digital :: Control1000X4 :: reserved1 [06:03] */
#define SGMII0_DIGITAL_CONTROL1000X4_RESERVED1_MASK                0x0078
#define SGMII0_DIGITAL_CONTROL1000X4_RESERVED1_ALIGN               0
#define SGMII0_DIGITAL_CONTROL1000X4_RESERVED1_BITS                4
#define SGMII0_DIGITAL_CONTROL1000X4_RESERVED1_SHIFT               3

/* SGMII0_Digital :: Control1000X4 :: MiscRxStatus_sel [02:00] */
#define Wr_SGMII0_Digital_Control1000X4_MiscRxStatus_sel(x) WriteRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x7,0,x)
#define Rd_SGMII0_Digital_Control1000X4_MiscRxStatus_sel(x) ReadRegBits16(SGMII0_DIGITAL_CONTROL1000X4,0x7,0)
#define SGMII0_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK         0x0007
#define SGMII0_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN        0
#define SGMII0_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS         3
#define SGMII0_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT        0


/****************************************************************************
 * SGMII0_Digital :: Status1000X1
 ***************************************************************************/
/* SGMII0_Digital :: Status1000X1 :: txfifo_err_detected [15:15] */
#define Wr_SGMII0_Digital_Status1000X1_txfifo_err_detected(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x8000,15,x)
#define Rd_SGMII0_Digital_Status1000X1_txfifo_err_detected(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x8000,15)
#define SGMII0_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK       0x8000
#define SGMII0_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN      0
#define SGMII0_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS       1
#define SGMII0_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT      15

/* SGMII0_Digital :: Status1000X1 :: rxfifo_err_detected [14:14] */
#define Wr_SGMII0_Digital_Status1000X1_rxfifo_err_detected(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x4000,14,x)
#define Rd_SGMII0_Digital_Status1000X1_rxfifo_err_detected(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x4000,14)
#define SGMII0_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK       0x4000
#define SGMII0_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN      0
#define SGMII0_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS       1
#define SGMII0_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT      14

/* SGMII0_Digital :: Status1000X1 :: false_carrier_detected [13:13] */
#define Wr_SGMII0_Digital_Status1000X1_false_carrier_detected(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x2000,13,x)
#define Rd_SGMII0_Digital_Status1000X1_false_carrier_detected(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x2000,13)
#define SGMII0_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK    0x2000
#define SGMII0_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN   0
#define SGMII0_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS    1
#define SGMII0_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT   13

/* SGMII0_Digital :: Status1000X1 :: crc_err_detected [12:12] */
#define Wr_SGMII0_Digital_Status1000X1_crc_err_detected(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x1000,12,x)
#define Rd_SGMII0_Digital_Status1000X1_crc_err_detected(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x1000,12)
#define SGMII0_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_MASK          0x1000
#define SGMII0_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_ALIGN         0
#define SGMII0_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_BITS          1
#define SGMII0_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_SHIFT         12

/* SGMII0_Digital :: Status1000X1 :: tx_err_detected [11:11] */
#define Wr_SGMII0_Digital_Status1000X1_tx_err_detected(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x800,11,x)
#define Rd_SGMII0_Digital_Status1000X1_tx_err_detected(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x800,11)
#define SGMII0_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK           0x0800
#define SGMII0_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN          0
#define SGMII0_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS           1
#define SGMII0_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT          11

/* SGMII0_Digital :: Status1000X1 :: rx_err_detected [10:10] */
#define Wr_SGMII0_Digital_Status1000X1_rx_err_detected(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x400,10,x)
#define Rd_SGMII0_Digital_Status1000X1_rx_err_detected(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x400,10)
#define SGMII0_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK           0x0400
#define SGMII0_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN          0
#define SGMII0_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS           1
#define SGMII0_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT          10

/* SGMII0_Digital :: Status1000X1 :: carrier_extend_err_detected [09:09] */
#define Wr_SGMII0_Digital_Status1000X1_carrier_extend_err_detected(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x200,9,x)
#define Rd_SGMII0_Digital_Status1000X1_carrier_extend_err_detected(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x200,9)
#define SGMII0_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200
#define SGMII0_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0
#define SGMII0_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1
#define SGMII0_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9

/* SGMII0_Digital :: Status1000X1 :: early_end_extension_detected [08:08] */
#define Wr_SGMII0_Digital_Status1000X1_early_end_extension_detected(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x100,8,x)
#define Rd_SGMII0_Digital_Status1000X1_early_end_extension_detected(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x100,8)
#define SGMII0_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100
#define SGMII0_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0
#define SGMII0_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1
#define SGMII0_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8

/* SGMII0_Digital :: Status1000X1 :: link_status_change [07:07] */
#define Wr_SGMII0_Digital_Status1000X1_link_status_change(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x80,7,x)
#define Rd_SGMII0_Digital_Status1000X1_link_status_change(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x80,7)
#define SGMII0_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK        0x0080
#define SGMII0_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN       0
#define SGMII0_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS        1
#define SGMII0_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT       7

/* SGMII0_Digital :: Status1000X1 :: pause_resolution_rxside [06:06] */
#define Wr_SGMII0_Digital_Status1000X1_pause_resolution_rxside(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x40,6,x)
#define Rd_SGMII0_Digital_Status1000X1_pause_resolution_rxside(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x40,6)
#define SGMII0_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK   0x0040
#define SGMII0_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN  0
#define SGMII0_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS   1
#define SGMII0_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT  6

/* SGMII0_Digital :: Status1000X1 :: pause_resolution_txside [05:05] */
#define Wr_SGMII0_Digital_Status1000X1_pause_resolution_txside(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x20,5,x)
#define Rd_SGMII0_Digital_Status1000X1_pause_resolution_txside(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x20,5)
#define SGMII0_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK   0x0020
#define SGMII0_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN  0
#define SGMII0_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS   1
#define SGMII0_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT  5

/* SGMII0_Digital :: Status1000X1 :: speed_status [04:03] */
#define Wr_SGMII0_Digital_Status1000X1_speed_status(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x18,3,x)
#define Rd_SGMII0_Digital_Status1000X1_speed_status(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x18,3)
#define SGMII0_DIGITAL_STATUS1000X1_SPEED_STATUS_MASK              0x0018
#define SGMII0_DIGITAL_STATUS1000X1_SPEED_STATUS_ALIGN             0
#define SGMII0_DIGITAL_STATUS1000X1_SPEED_STATUS_BITS              2
#define SGMII0_DIGITAL_STATUS1000X1_SPEED_STATUS_SHIFT             3

/* SGMII0_Digital :: Status1000X1 :: duplex_status [02:02] */
#define Wr_SGMII0_Digital_Status1000X1_duplex_status(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x4,2,x)
#define Rd_SGMII0_Digital_Status1000X1_duplex_status(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x4,2)
#define SGMII0_DIGITAL_STATUS1000X1_DUPLEX_STATUS_MASK             0x0004
#define SGMII0_DIGITAL_STATUS1000X1_DUPLEX_STATUS_ALIGN            0
#define SGMII0_DIGITAL_STATUS1000X1_DUPLEX_STATUS_BITS             1
#define SGMII0_DIGITAL_STATUS1000X1_DUPLEX_STATUS_SHIFT            2

/* SGMII0_Digital :: Status1000X1 :: link_status [01:01] */
#define Wr_SGMII0_Digital_Status1000X1_link_status(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x2,1,x)
#define Rd_SGMII0_Digital_Status1000X1_link_status(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x2,1)
#define SGMII0_DIGITAL_STATUS1000X1_LINK_STATUS_MASK               0x0002
#define SGMII0_DIGITAL_STATUS1000X1_LINK_STATUS_ALIGN              0
#define SGMII0_DIGITAL_STATUS1000X1_LINK_STATUS_BITS               1
#define SGMII0_DIGITAL_STATUS1000X1_LINK_STATUS_SHIFT              1

/* SGMII0_Digital :: Status1000X1 :: sgmii_mode [00:00] */
#define Wr_SGMII0_Digital_Status1000X1_sgmii_mode(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x1,0,x)
#define Rd_SGMII0_Digital_Status1000X1_sgmii_mode(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X1,0x1,0)
#define SGMII0_DIGITAL_STATUS1000X1_SGMII_MODE_MASK                0x0001
#define SGMII0_DIGITAL_STATUS1000X1_SGMII_MODE_ALIGN               0
#define SGMII0_DIGITAL_STATUS1000X1_SGMII_MODE_BITS                1
#define SGMII0_DIGITAL_STATUS1000X1_SGMII_MODE_SHIFT               0


/****************************************************************************
 * SGMII0_Digital :: Status1000X2
 ***************************************************************************/
/* SGMII0_Digital :: Status1000X2 :: sgmii_mode_change [15:15] */
#define Wr_SGMII0_Digital_Status1000X2_sgmii_mode_change(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x8000,15,x)
#define Rd_SGMII0_Digital_Status1000X2_sgmii_mode_change(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x8000,15)
#define SGMII0_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_MASK         0x8000
#define SGMII0_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN        0
#define SGMII0_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_BITS         1
#define SGMII0_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT        15

/* SGMII0_Digital :: Status1000X2 :: consistency_mismatch [14:14] */
#define Wr_SGMII0_Digital_Status1000X2_consistency_mismatch(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x4000,14,x)
#define Rd_SGMII0_Digital_Status1000X2_consistency_mismatch(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x4000,14)
#define SGMII0_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_MASK      0x4000
#define SGMII0_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN     0
#define SGMII0_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_BITS      1
#define SGMII0_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT     14

/* SGMII0_Digital :: Status1000X2 :: autoneg_resolution_err [13:13] */
#define Wr_SGMII0_Digital_Status1000X2_autoneg_resolution_err(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x2000,13,x)
#define Rd_SGMII0_Digital_Status1000X2_autoneg_resolution_err(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x2000,13)
#define SGMII0_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK    0x2000
#define SGMII0_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN   0
#define SGMII0_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS    1
#define SGMII0_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT   13

/* SGMII0_Digital :: Status1000X2 :: sgmii_selector_mismatch [12:12] */
#define Wr_SGMII0_Digital_Status1000X2_sgmii_selector_mismatch(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x1000,12,x)
#define Rd_SGMII0_Digital_Status1000X2_sgmii_selector_mismatch(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x1000,12)
#define SGMII0_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK   0x1000
#define SGMII0_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN  0
#define SGMII0_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS   1
#define SGMII0_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT  12

/* SGMII0_Digital :: Status1000X2 :: sync_status_fail [11:11] */
#define Wr_SGMII0_Digital_Status1000X2_sync_status_fail(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x800,11,x)
#define Rd_SGMII0_Digital_Status1000X2_sync_status_fail(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x800,11)
#define SGMII0_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_MASK          0x0800
#define SGMII0_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN         0
#define SGMII0_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_BITS          1
#define SGMII0_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT         11

/* SGMII0_Digital :: Status1000X2 :: sync_status_ok [10:10] */
#define Wr_SGMII0_Digital_Status1000X2_sync_status_ok(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x400,10,x)
#define Rd_SGMII0_Digital_Status1000X2_sync_status_ok(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x400,10)
#define SGMII0_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_MASK            0x0400
#define SGMII0_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_ALIGN           0
#define SGMII0_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_BITS            1
#define SGMII0_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_SHIFT           10

/* SGMII0_Digital :: Status1000X2 :: rudi_c [09:09] */
#define Wr_SGMII0_Digital_Status1000X2_rudi_c(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x200,9,x)
#define Rd_SGMII0_Digital_Status1000X2_rudi_c(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x200,9)
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_C_MASK                    0x0200
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_C_ALIGN                   0
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_C_BITS                    1
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_C_SHIFT                   9

/* SGMII0_Digital :: Status1000X2 :: rudi_I [08:08] */
#define Wr_SGMII0_Digital_Status1000X2_rudi_I(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x100,8,x)
#define Rd_SGMII0_Digital_Status1000X2_rudi_I(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x100,8)
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_I_MASK                    0x0100
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_I_ALIGN                   0
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_I_BITS                    1
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_I_SHIFT                   8

/* SGMII0_Digital :: Status1000X2 :: rudi_invalid [07:07] */
#define Wr_SGMII0_Digital_Status1000X2_rudi_invalid(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x80,7,x)
#define Rd_SGMII0_Digital_Status1000X2_rudi_invalid(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x80,7)
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_INVALID_MASK              0x0080
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_INVALID_ALIGN             0
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_INVALID_BITS              1
#define SGMII0_DIGITAL_STATUS1000X2_RUDI_INVALID_SHIFT             7

/* SGMII0_Digital :: Status1000X2 :: linkDown_syncLoss [06:06] */
#define Wr_SGMII0_Digital_Status1000X2_linkDown_syncLoss(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x40,6,x)
#define Rd_SGMII0_Digital_Status1000X2_linkDown_syncLoss(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x40,6)
#define SGMII0_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK         0x0040
#define SGMII0_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN        0
#define SGMII0_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS         1
#define SGMII0_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT        6

/* SGMII0_Digital :: Status1000X2 :: idle_detect_state [05:05] */
#define Wr_SGMII0_Digital_Status1000X2_idle_detect_state(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x20,5,x)
#define Rd_SGMII0_Digital_Status1000X2_idle_detect_state(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x20,5)
#define SGMII0_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_MASK         0x0020
#define SGMII0_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_ALIGN        0
#define SGMII0_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_BITS         1
#define SGMII0_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_SHIFT        5

/* SGMII0_Digital :: Status1000X2 :: complete_acknowledge_state [04:04] */
#define Wr_SGMII0_Digital_Status1000X2_complete_acknowledge_state(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x10,4,x)
#define Rd_SGMII0_Digital_Status1000X2_complete_acknowledge_state(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x10,4)
#define SGMII0_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010
#define SGMII0_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0
#define SGMII0_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1
#define SGMII0_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4

/* SGMII0_Digital :: Status1000X2 :: acknowledge_detect_state [03:03] */
#define Wr_SGMII0_Digital_Status1000X2_acknowledge_detect_state(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x8,3,x)
#define Rd_SGMII0_Digital_Status1000X2_acknowledge_detect_state(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x8,3)
#define SGMII0_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK  0x0008
#define SGMII0_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0
#define SGMII0_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS  1
#define SGMII0_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3

/* SGMII0_Digital :: Status1000X2 :: ability_detect_state [02:02] */
#define Wr_SGMII0_Digital_Status1000X2_ability_detect_state(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x4,2,x)
#define Rd_SGMII0_Digital_Status1000X2_ability_detect_state(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x4,2)
#define SGMII0_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_MASK      0x0004
#define SGMII0_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN     0
#define SGMII0_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_BITS      1
#define SGMII0_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT     2

/* union - case anError [01:01] */
/* SGMII0_Digital :: Status1000X2 :: an_error_state [01:01] */
#define Wr_SGMII0_Digital_Status1000X2_anError_an_error_state(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2_ANERROR,0x2,1,x)
#define Rd_SGMII0_Digital_Status1000X2_anError_an_error_state(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2_ANERROR,0x2,1)
#define SGMII0_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK    0x0002
#define SGMII0_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN   0
#define SGMII0_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS    1
#define SGMII0_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT   1


/* union - case anDisableLink [01:01] */
/* SGMII0_Digital :: Status1000X2 :: an_disable_link_ok_state [01:01] */
#define Wr_SGMII0_Digital_Status1000X2_anDisableLink_an_disable_link_ok_state(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2_ANDISABLELINK,0x2,1,x)
#define Rd_SGMII0_Digital_Status1000X2_anDisableLink_an_disable_link_ok_state(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2_ANDISABLELINK,0x2,1)
#define SGMII0_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002
#define SGMII0_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0
#define SGMII0_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1
#define SGMII0_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1


/* SGMII0_Digital :: Status1000X2 :: an_enable_state [00:00] */
#define Wr_SGMII0_Digital_Status1000X2_an_enable_state(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x1,0,x)
#define Rd_SGMII0_Digital_Status1000X2_an_enable_state(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X2,0x1,0)
#define SGMII0_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_MASK           0x0001
#define SGMII0_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_ALIGN          0
#define SGMII0_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_BITS           1
#define SGMII0_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_SHIFT          0


/****************************************************************************
 * SGMII0_Digital :: Status1000X3
 ***************************************************************************/
/* SGMII0_Digital :: Status1000X3 :: reserved0 [15:13] */
#define SGMII0_DIGITAL_STATUS1000X3_RESERVED0_MASK                 0xe000
#define SGMII0_DIGITAL_STATUS1000X3_RESERVED0_ALIGN                0
#define SGMII0_DIGITAL_STATUS1000X3_RESERVED0_BITS                 3
#define SGMII0_DIGITAL_STATUS1000X3_RESERVED0_SHIFT                13

/* SGMII0_Digital :: Status1000X3 :: pd_park_an [12:12] */
#define Wr_SGMII0_Digital_Status1000X3_pd_park_an(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x1000,12,x)
#define Rd_SGMII0_Digital_Status1000X3_pd_park_an(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x1000,12)
#define SGMII0_DIGITAL_STATUS1000X3_PD_PARK_AN_MASK                0x1000
#define SGMII0_DIGITAL_STATUS1000X3_PD_PARK_AN_ALIGN               0
#define SGMII0_DIGITAL_STATUS1000X3_PD_PARK_AN_BITS                1
#define SGMII0_DIGITAL_STATUS1000X3_PD_PARK_AN_SHIFT               12

/* SGMII0_Digital :: Status1000X3 :: remotePhy_autosel [11:11] */
#define Wr_SGMII0_Digital_Status1000X3_remotePhy_autosel(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x800,11,x)
#define Rd_SGMII0_Digital_Status1000X3_remotePhy_autosel(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x800,11)
#define SGMII0_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK         0x0800
#define SGMII0_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN        0
#define SGMII0_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS         1
#define SGMII0_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT        11

/* SGMII0_Digital :: Status1000X3 :: latch_linkdown [10:10] */
#define Wr_SGMII0_Digital_Status1000X3_latch_linkdown(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x400,10,x)
#define Rd_SGMII0_Digital_Status1000X3_latch_linkdown(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x400,10)
#define SGMII0_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_MASK            0x0400
#define SGMII0_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_ALIGN           0
#define SGMII0_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_BITS            1
#define SGMII0_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_SHIFT           10

/* SGMII0_Digital :: Status1000X3 :: sd_filter [09:09] */
#define Wr_SGMII0_Digital_Status1000X3_sd_filter(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x200,9,x)
#define Rd_SGMII0_Digital_Status1000X3_sd_filter(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x200,9)
#define SGMII0_DIGITAL_STATUS1000X3_SD_FILTER_MASK                 0x0200
#define SGMII0_DIGITAL_STATUS1000X3_SD_FILTER_ALIGN                0
#define SGMII0_DIGITAL_STATUS1000X3_SD_FILTER_BITS                 1
#define SGMII0_DIGITAL_STATUS1000X3_SD_FILTER_SHIFT                9

/* SGMII0_Digital :: Status1000X3 :: sd_mux [08:08] */
#define Wr_SGMII0_Digital_Status1000X3_sd_mux(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x100,8,x)
#define Rd_SGMII0_Digital_Status1000X3_sd_mux(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x100,8)
#define SGMII0_DIGITAL_STATUS1000X3_SD_MUX_MASK                    0x0100
#define SGMII0_DIGITAL_STATUS1000X3_SD_MUX_ALIGN                   0
#define SGMII0_DIGITAL_STATUS1000X3_SD_MUX_BITS                    1
#define SGMII0_DIGITAL_STATUS1000X3_SD_MUX_SHIFT                   8

/* SGMII0_Digital :: Status1000X3 :: sd_filter_chg [07:07] */
#define Wr_SGMII0_Digital_Status1000X3_sd_filter_chg(x) WriteRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x80,7,x)
#define Rd_SGMII0_Digital_Status1000X3_sd_filter_chg(x) ReadRegBits16(SGMII0_DIGITAL_STATUS1000X3,0x80,7)
#define SGMII0_DIGITAL_STATUS1000X3_SD_FILTER_CHG_MASK             0x0080
#define SGMII0_DIGITAL_STATUS1000X3_SD_FILTER_CHG_ALIGN            0
#define SGMII0_DIGITAL_STATUS1000X3_SD_FILTER_CHG_BITS             1
#define SGMII0_DIGITAL_STATUS1000X3_SD_FILTER_CHG_SHIFT            7

/* SGMII0_Digital :: Status1000X3 :: reserved1 [06:00] */
#define SGMII0_DIGITAL_STATUS1000X3_RESERVED1_MASK                 0x007f
#define SGMII0_DIGITAL_STATUS1000X3_RESERVED1_ALIGN                0
#define SGMII0_DIGITAL_STATUS1000X3_RESERVED1_BITS                 7
#define SGMII0_DIGITAL_STATUS1000X3_RESERVED1_SHIFT                0


/****************************************************************************
 * SGMII0_Digital :: BadCodeGroup
 ***************************************************************************/
/* SGMII0_Digital :: BadCodeGroup :: badCodeGroups [15:08] */
#define Wr_SGMII0_Digital_BadCodeGroup_badCodeGroups(x) WriteRegBits16(SGMII0_DIGITAL_BADCODEGROUP,0xff00,8,x)
#define Rd_SGMII0_Digital_BadCodeGroup_badCodeGroups(x) ReadRegBits16(SGMII0_DIGITAL_BADCODEGROUP,0xff00,8)
#define SGMII0_DIGITAL_BADCODEGROUP_BADCODEGROUPS_MASK             0xff00
#define SGMII0_DIGITAL_BADCODEGROUP_BADCODEGROUPS_ALIGN            0
#define SGMII0_DIGITAL_BADCODEGROUP_BADCODEGROUPS_BITS             8
#define SGMII0_DIGITAL_BADCODEGROUP_BADCODEGROUPS_SHIFT            8

/* SGMII0_Digital :: BadCodeGroup :: reserved0 [07:00] */
#define SGMII0_DIGITAL_BADCODEGROUP_RESERVED0_MASK                 0x00ff
#define SGMII0_DIGITAL_BADCODEGROUP_RESERVED0_ALIGN                0
#define SGMII0_DIGITAL_BADCODEGROUP_RESERVED0_BITS                 8
#define SGMII0_DIGITAL_BADCODEGROUP_RESERVED0_SHIFT                0


/****************************************************************************
 * SGMII0_Digital :: Misc1
 ***************************************************************************/
/* SGMII0_Digital :: Misc1 :: refclk_sel [15:13] */
#define Wr_SGMII0_Digital_Misc1_refclk_sel(x) WriteRegBits16(SGMII0_DIGITAL_MISC1,0xe000,13,x)
#define Rd_SGMII0_Digital_Misc1_refclk_sel(x) ReadRegBits16(SGMII0_DIGITAL_MISC1,0xe000,13)
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_MASK                       0xe000
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_ALIGN                      0
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_BITS                       3
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_SHIFT                      13
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_clk_25MHz                  0
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_clk_100MHz                 1
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_clk_125MHz                 2
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_clk_156p25MHz              3
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_clk_187p5MHz               4
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_clk_161p25Mhz              5
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_clk_50Mhz                  6
#define SGMII0_DIGITAL_MISC1_REFCLK_SEL_clk_106p25Mhz              7

/* SGMII0_Digital :: Misc1 :: reserved0 [12:07] */
#define SGMII0_DIGITAL_MISC1_RESERVED0_MASK                        0x1f80
#define SGMII0_DIGITAL_MISC1_RESERVED0_ALIGN                       0
#define SGMII0_DIGITAL_MISC1_RESERVED0_BITS                        6
#define SGMII0_DIGITAL_MISC1_RESERVED0_SHIFT                       7

/* SGMII0_Digital :: Misc1 :: tx_underrun_1000_dis [06:06] */
#define Wr_SGMII0_Digital_Misc1_tx_underrun_1000_dis(x) WriteRegBits16(SGMII0_DIGITAL_MISC1,0x40,6,x)
#define Rd_SGMII0_Digital_Misc1_tx_underrun_1000_dis(x) ReadRegBits16(SGMII0_DIGITAL_MISC1,0x40,6)
#define SGMII0_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_MASK             0x0040
#define SGMII0_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_ALIGN            0
#define SGMII0_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_BITS             1
#define SGMII0_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_SHIFT            6

/* SGMII0_Digital :: Misc1 :: force_ln_mode [05:05] */
#define Wr_SGMII0_Digital_Misc1_force_ln_mode(x) WriteRegBits16(SGMII0_DIGITAL_MISC1,0x20,5,x)
#define Rd_SGMII0_Digital_Misc1_force_ln_mode(x) ReadRegBits16(SGMII0_DIGITAL_MISC1,0x20,5)
#define SGMII0_DIGITAL_MISC1_FORCE_LN_MODE_MASK                    0x0020
#define SGMII0_DIGITAL_MISC1_FORCE_LN_MODE_ALIGN                   0
#define SGMII0_DIGITAL_MISC1_FORCE_LN_MODE_BITS                    1
#define SGMII0_DIGITAL_MISC1_FORCE_LN_MODE_SHIFT                   5

/* SGMII0_Digital :: Misc1 :: force_speed [04:00] */
#define Wr_SGMII0_Digital_Misc1_force_speed(x) WriteRegBits16(SGMII0_DIGITAL_MISC1,0x1f,0,x)
#define Rd_SGMII0_Digital_Misc1_force_speed(x) ReadRegBits16(SGMII0_DIGITAL_MISC1,0x1f,0)
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_MASK                      0x001f
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_ALIGN                     0
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_BITS                      5
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_SHIFT                     0
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_2500BRCM_X1            16
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X4            17
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_6000BRCM_X4            18
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_10GHiGig_X4            19
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_10GBASE_CX4            20
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_12GHiGig_X4            21
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_12p5GHiGig_X4          22
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_13GHiGig_X4            23
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_15GHiGig_X4            24
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_16GHiGig_X4            25
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X1            26
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_6363BRCM_X1            27
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_20GHiGig_X4            28
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_21GHiGig_X4            29
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_25p45GHiGig_X4         30
#define SGMII0_DIGITAL_MISC1_FORCE_SPEED_dr_10G_HiG_DXGXS          31


/****************************************************************************
 * SGMII0_Digital :: Misc2
 ***************************************************************************/
/* SGMII0_Digital :: Misc2 :: rxckpl_sel_combo [15:15] */
#define Wr_SGMII0_Digital_Misc2_rxckpl_sel_combo(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x8000,15,x)
#define Rd_SGMII0_Digital_Misc2_rxckpl_sel_combo(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x8000,15)
#define SGMII0_DIGITAL_MISC2_RXCKPL_SEL_COMBO_MASK                 0x8000
#define SGMII0_DIGITAL_MISC2_RXCKPL_SEL_COMBO_ALIGN                0
#define SGMII0_DIGITAL_MISC2_RXCKPL_SEL_COMBO_BITS                 1
#define SGMII0_DIGITAL_MISC2_RXCKPL_SEL_COMBO_SHIFT                15

/* SGMII0_Digital :: Misc2 :: reserved_14_13 [14:13] */
#define SGMII0_DIGITAL_MISC2_RESERVED_14_13_MASK                   0x6000
#define SGMII0_DIGITAL_MISC2_RESERVED_14_13_ALIGN                  0
#define SGMII0_DIGITAL_MISC2_RESERVED_14_13_BITS                   2
#define SGMII0_DIGITAL_MISC2_RESERVED_14_13_SHIFT                  13

/* SGMII0_Digital :: Misc2 :: rlpbk_sw_force [12:12] */
#define Wr_SGMII0_Digital_Misc2_rlpbk_sw_force(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x1000,12,x)
#define Rd_SGMII0_Digital_Misc2_rlpbk_sw_force(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x1000,12)
#define SGMII0_DIGITAL_MISC2_RLPBK_SW_FORCE_MASK                   0x1000
#define SGMII0_DIGITAL_MISC2_RLPBK_SW_FORCE_ALIGN                  0
#define SGMII0_DIGITAL_MISC2_RLPBK_SW_FORCE_BITS                   1
#define SGMII0_DIGITAL_MISC2_RLPBK_SW_FORCE_SHIFT                  12

/* SGMII0_Digital :: Misc2 :: rlpbk_RxRst_en [11:11] */
#define Wr_SGMII0_Digital_Misc2_rlpbk_RxRst_en(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x800,11,x)
#define Rd_SGMII0_Digital_Misc2_rlpbk_RxRst_en(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x800,11)
#define SGMII0_DIGITAL_MISC2_RLPBK_RXRST_EN_MASK                   0x0800
#define SGMII0_DIGITAL_MISC2_RLPBK_RXRST_EN_ALIGN                  0
#define SGMII0_DIGITAL_MISC2_RLPBK_RXRST_EN_BITS                   1
#define SGMII0_DIGITAL_MISC2_RLPBK_RXRST_EN_SHIFT                  11

/* SGMII0_Digital :: Misc2 :: clkSigdet_bypass [10:10] */
#define Wr_SGMII0_Digital_Misc2_clkSigdet_bypass(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x400,10,x)
#define Rd_SGMII0_Digital_Misc2_clkSigdet_bypass(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x400,10)
#define SGMII0_DIGITAL_MISC2_CLKSIGDET_BYPASS_MASK                 0x0400
#define SGMII0_DIGITAL_MISC2_CLKSIGDET_BYPASS_ALIGN                0
#define SGMII0_DIGITAL_MISC2_CLKSIGDET_BYPASS_BITS                 1
#define SGMII0_DIGITAL_MISC2_CLKSIGDET_BYPASS_SHIFT                10

/* SGMII0_Digital :: Misc2 :: clk41_bypass [09:09] */
#define Wr_SGMII0_Digital_Misc2_clk41_bypass(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x200,9,x)
#define Rd_SGMII0_Digital_Misc2_clk41_bypass(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x200,9)
#define SGMII0_DIGITAL_MISC2_CLK41_BYPASS_MASK                     0x0200
#define SGMII0_DIGITAL_MISC2_CLK41_BYPASS_ALIGN                    0
#define SGMII0_DIGITAL_MISC2_CLK41_BYPASS_BITS                     1
#define SGMII0_DIGITAL_MISC2_CLK41_BYPASS_SHIFT                    9

/* SGMII0_Digital :: Misc2 :: miiGmiiDly_en [08:08] */
#define Wr_SGMII0_Digital_Misc2_miiGmiiDly_en(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x100,8,x)
#define Rd_SGMII0_Digital_Misc2_miiGmiiDly_en(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x100,8)
#define SGMII0_DIGITAL_MISC2_MIIGMIIDLY_EN_MASK                    0x0100
#define SGMII0_DIGITAL_MISC2_MIIGMIIDLY_EN_ALIGN                   0
#define SGMII0_DIGITAL_MISC2_MIIGMIIDLY_EN_BITS                    1
#define SGMII0_DIGITAL_MISC2_MIIGMIIDLY_EN_SHIFT                   8

/* SGMII0_Digital :: Misc2 :: miiGmiiMux_en [07:07] */
#define Wr_SGMII0_Digital_Misc2_miiGmiiMux_en(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x80,7,x)
#define Rd_SGMII0_Digital_Misc2_miiGmiiMux_en(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x80,7)
#define SGMII0_DIGITAL_MISC2_MIIGMIIMUX_EN_MASK                    0x0080
#define SGMII0_DIGITAL_MISC2_MIIGMIIMUX_EN_ALIGN                   0
#define SGMII0_DIGITAL_MISC2_MIIGMIIMUX_EN_BITS                    1
#define SGMII0_DIGITAL_MISC2_MIIGMIIMUX_EN_SHIFT                   7

/* SGMII0_Digital :: Misc2 :: reserved0 [06:06] */
#define SGMII0_DIGITAL_MISC2_RESERVED0_MASK                        0x0040
#define SGMII0_DIGITAL_MISC2_RESERVED0_ALIGN                       0
#define SGMII0_DIGITAL_MISC2_RESERVED0_BITS                        1
#define SGMII0_DIGITAL_MISC2_RESERVED0_SHIFT                       6

/* SGMII0_Digital :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */
#define Wr_SGMII0_Digital_Misc2_pma_pmd_forced_speed_enc_en(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x20,5,x)
#define Rd_SGMII0_Digital_Misc2_pma_pmd_forced_speed_enc_en(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x20,5)
#define SGMII0_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK      0x0020
#define SGMII0_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN     0
#define SGMII0_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS      1
#define SGMII0_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT     5

/* SGMII0_Digital :: Misc2 :: fifo_err_cya [04:04] */
#define Wr_SGMII0_Digital_Misc2_fifo_err_cya(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x10,4,x)
#define Rd_SGMII0_Digital_Misc2_fifo_err_cya(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x10,4)
#define SGMII0_DIGITAL_MISC2_FIFO_ERR_CYA_MASK                     0x0010
#define SGMII0_DIGITAL_MISC2_FIFO_ERR_CYA_ALIGN                    0
#define SGMII0_DIGITAL_MISC2_FIFO_ERR_CYA_BITS                     1
#define SGMII0_DIGITAL_MISC2_FIFO_ERR_CYA_SHIFT                    4

/* SGMII0_Digital :: Misc2 :: an_txdisablePhase [03:03] */
#define Wr_SGMII0_Digital_Misc2_an_txdisablePhase(x) WriteRegBits16(SGMII0_DIGITAL_MISC2,0x8,3,x)
#define Rd_SGMII0_Digital_Misc2_an_txdisablePhase(x) ReadRegBits16(SGMII0_DIGITAL_MISC2,0x8,3)
#define SGMII0_DIGITAL_MISC2_AN_TXDISABLEPHASE_MASK                0x0008
#define SGMII0_DIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN               0
#define SGMII0_DIGITAL_MISC2_AN_TXDISABLEPHASE_BITS                1
#define SGMII0_DIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT               3

/* SGMII0_Digital :: Misc2 :: reserved1 [02:00] */
#define SGMII0_DIGITAL_MISC2_RESERVED1_MASK                        0x0007
#define SGMII0_DIGITAL_MISC2_RESERVED1_ALIGN                       0
#define SGMII0_DIGITAL_MISC2_RESERVED1_BITS                        3
#define SGMII0_DIGITAL_MISC2_RESERVED1_SHIFT                       0


/****************************************************************************
 * SGMII0_Digital :: PatGenCtrl
 ***************************************************************************/
/* SGMII0_Digital :: PatGenCtrl :: patgen_lpi_en [15:15] */
#define Wr_SGMII0_Digital_PatGenCtrl_patgen_lpi_en(x) WriteRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x8000,15,x)
#define Rd_SGMII0_Digital_PatGenCtrl_patgen_lpi_en(x) ReadRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x8000,15)
#define SGMII0_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_MASK               0x8000
#define SGMII0_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_ALIGN              0
#define SGMII0_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_BITS               1
#define SGMII0_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_SHIFT              15

/* SGMII0_Digital :: PatGenCtrl :: tx_err [14:14] */
#define Wr_SGMII0_Digital_PatGenCtrl_tx_err(x) WriteRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x4000,14,x)
#define Rd_SGMII0_Digital_PatGenCtrl_tx_err(x) ReadRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x4000,14)
#define SGMII0_DIGITAL_PATGENCTRL_TX_ERR_MASK                      0x4000
#define SGMII0_DIGITAL_PATGENCTRL_TX_ERR_ALIGN                     0
#define SGMII0_DIGITAL_PATGENCTRL_TX_ERR_BITS                      1
#define SGMII0_DIGITAL_PATGENCTRL_TX_ERR_SHIFT                     14

/* SGMII0_Digital :: PatGenCtrl :: skip_crc [13:13] */
#define Wr_SGMII0_Digital_PatGenCtrl_skip_crc(x) WriteRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x2000,13,x)
#define Rd_SGMII0_Digital_PatGenCtrl_skip_crc(x) ReadRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x2000,13)
#define SGMII0_DIGITAL_PATGENCTRL_SKIP_CRC_MASK                    0x2000
#define SGMII0_DIGITAL_PATGENCTRL_SKIP_CRC_ALIGN                   0
#define SGMII0_DIGITAL_PATGENCTRL_SKIP_CRC_BITS                    1
#define SGMII0_DIGITAL_PATGENCTRL_SKIP_CRC_SHIFT                   13

/* SGMII0_Digital :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */
#define Wr_SGMII0_Digital_PatGenCtrl_en_crc_checker_fragment_err_det(x) WriteRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x1000,12,x)
#define Rd_SGMII0_Digital_PatGenCtrl_en_crc_checker_fragment_err_det(x) ReadRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x1000,12)
#define SGMII0_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000
#define SGMII0_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0
#define SGMII0_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1
#define SGMII0_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12

/* SGMII0_Digital :: PatGenCtrl :: ipg_select [11:09] */
#define Wr_SGMII0_Digital_PatGenCtrl_ipg_select(x) WriteRegBits16(SGMII0_DIGITAL_PATGENCTRL,0xe00,9,x)
#define Rd_SGMII0_Digital_PatGenCtrl_ipg_select(x) ReadRegBits16(SGMII0_DIGITAL_PATGENCTRL,0xe00,9)
#define SGMII0_DIGITAL_PATGENCTRL_IPG_SELECT_MASK                  0x0e00
#define SGMII0_DIGITAL_PATGENCTRL_IPG_SELECT_ALIGN                 0
#define SGMII0_DIGITAL_PATGENCTRL_IPG_SELECT_BITS                  3
#define SGMII0_DIGITAL_PATGENCTRL_IPG_SELECT_SHIFT                 9

/* SGMII0_Digital :: PatGenCtrl :: pkt_size [08:03] */
#define Wr_SGMII0_Digital_PatGenCtrl_pkt_size(x) WriteRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x1f8,3,x)
#define Rd_SGMII0_Digital_PatGenCtrl_pkt_size(x) ReadRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x1f8,3)
#define SGMII0_DIGITAL_PATGENCTRL_PKT_SIZE_MASK                    0x01f8
#define SGMII0_DIGITAL_PATGENCTRL_PKT_SIZE_ALIGN                   0
#define SGMII0_DIGITAL_PATGENCTRL_PKT_SIZE_BITS                    6
#define SGMII0_DIGITAL_PATGENCTRL_PKT_SIZE_SHIFT                   3

/* SGMII0_Digital :: PatGenCtrl :: single_pass_mode [02:02] */
#define Wr_SGMII0_Digital_PatGenCtrl_single_pass_mode(x) WriteRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x4,2,x)
#define Rd_SGMII0_Digital_PatGenCtrl_single_pass_mode(x) ReadRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x4,2)
#define SGMII0_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_MASK            0x0004
#define SGMII0_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_ALIGN           0
#define SGMII0_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_BITS            1
#define SGMII0_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_SHIFT           2

/* SGMII0_Digital :: PatGenCtrl :: run_pattern_gen [01:01] */
#define Wr_SGMII0_Digital_PatGenCtrl_run_pattern_gen(x) WriteRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x2,1,x)
#define Rd_SGMII0_Digital_PatGenCtrl_run_pattern_gen(x) ReadRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x2,1)
#define SGMII0_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_MASK             0x0002
#define SGMII0_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_ALIGN            0
#define SGMII0_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_BITS             1
#define SGMII0_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_SHIFT            1

/* SGMII0_Digital :: PatGenCtrl :: sel_pattern_gen_data [00:00] */
#define Wr_SGMII0_Digital_PatGenCtrl_sel_pattern_gen_data(x) WriteRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x1,0,x)
#define Rd_SGMII0_Digital_PatGenCtrl_sel_pattern_gen_data(x) ReadRegBits16(SGMII0_DIGITAL_PATGENCTRL,0x1,0)
#define SGMII0_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK        0x0001
#define SGMII0_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN       0
#define SGMII0_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS        1
#define SGMII0_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT       0


/****************************************************************************
 * SGMII0_Digital :: PatGenStat
 ***************************************************************************/
/* SGMII0_Digital :: PatGenStat :: reserved0 [15:04] */
#define SGMII0_DIGITAL_PATGENSTAT_RESERVED0_MASK                   0xfff0
#define SGMII0_DIGITAL_PATGENSTAT_RESERVED0_ALIGN                  0
#define SGMII0_DIGITAL_PATGENSTAT_RESERVED0_BITS                   12
#define SGMII0_DIGITAL_PATGENSTAT_RESERVED0_SHIFT                  4

/* SGMII0_Digital :: PatGenStat :: pattern_gen_active [03:03] */
#define Wr_SGMII0_Digital_PatGenStat_pattern_gen_active(x) WriteRegBits16(SGMII0_DIGITAL_PATGENSTAT,0x8,3,x)
#define Rd_SGMII0_Digital_PatGenStat_pattern_gen_active(x) ReadRegBits16(SGMII0_DIGITAL_PATGENSTAT,0x8,3)
#define SGMII0_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK          0x0008
#define SGMII0_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN         0
#define SGMII0_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS          1
#define SGMII0_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT         3

/* SGMII0_Digital :: PatGenStat :: pattern_gen_fsm [02:00] */
#define Wr_SGMII0_Digital_PatGenStat_pattern_gen_fsm(x) WriteRegBits16(SGMII0_DIGITAL_PATGENSTAT,0x7,0,x)
#define Rd_SGMII0_Digital_PatGenStat_pattern_gen_fsm(x) ReadRegBits16(SGMII0_DIGITAL_PATGENSTAT,0x7,0)
#define SGMII0_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_MASK             0x0007
#define SGMII0_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_ALIGN            0
#define SGMII0_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_BITS             3
#define SGMII0_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_SHIFT            0


/****************************************************************************
 * SGMII0_Digital :: TestMode
 ***************************************************************************/
/* SGMII0_Digital :: TestMode :: disable_reset_cnt [15:15] */
#define Wr_SGMII0_Digital_TestMode_disable_reset_cnt(x) WriteRegBits16(SGMII0_DIGITAL_TESTMODE,0x8000,15,x)
#define Rd_SGMII0_Digital_TestMode_disable_reset_cnt(x) ReadRegBits16(SGMII0_DIGITAL_TESTMODE,0x8000,15)
#define SGMII0_DIGITAL_TESTMODE_DISABLE_RESET_CNT_MASK             0x8000
#define SGMII0_DIGITAL_TESTMODE_DISABLE_RESET_CNT_ALIGN            0
#define SGMII0_DIGITAL_TESTMODE_DISABLE_RESET_CNT_BITS             1
#define SGMII0_DIGITAL_TESTMODE_DISABLE_RESET_CNT_SHIFT            15

/* SGMII0_Digital :: TestMode :: clear_packet_counters [14:14] */
#define Wr_SGMII0_Digital_TestMode_clear_packet_counters(x) WriteRegBits16(SGMII0_DIGITAL_TESTMODE,0x4000,14,x)
#define Rd_SGMII0_Digital_TestMode_clear_packet_counters(x) ReadRegBits16(SGMII0_DIGITAL_TESTMODE,0x4000,14)
#define SGMII0_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_MASK         0x4000
#define SGMII0_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN        0
#define SGMII0_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_BITS         1
#define SGMII0_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT        14

/* SGMII0_Digital :: TestMode :: reserved0 [13:05] */
#define SGMII0_DIGITAL_TESTMODE_RESERVED0_MASK                     0x3fe0
#define SGMII0_DIGITAL_TESTMODE_RESERVED0_ALIGN                    0
#define SGMII0_DIGITAL_TESTMODE_RESERVED0_BITS                     9
#define SGMII0_DIGITAL_TESTMODE_RESERVED0_SHIFT                    5

/* SGMII0_Digital :: TestMode :: fifo_fsm_cya_rx [04:04] */
#define Wr_SGMII0_Digital_TestMode_fifo_fsm_cya_rx(x) WriteRegBits16(SGMII0_DIGITAL_TESTMODE,0x10,4,x)
#define Rd_SGMII0_Digital_TestMode_fifo_fsm_cya_rx(x) ReadRegBits16(SGMII0_DIGITAL_TESTMODE,0x10,4)
#define SGMII0_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_MASK               0x0010
#define SGMII0_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_ALIGN              0
#define SGMII0_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_BITS               1
#define SGMII0_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_SHIFT              4

/* SGMII0_Digital :: TestMode :: dig1000x_afrst_cya [03:03] */
#define Wr_SGMII0_Digital_TestMode_dig1000x_afrst_cya(x) WriteRegBits16(SGMII0_DIGITAL_TESTMODE,0x8,3,x)
#define Rd_SGMII0_Digital_TestMode_dig1000x_afrst_cya(x) ReadRegBits16(SGMII0_DIGITAL_TESTMODE,0x8,3)
#define SGMII0_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_MASK            0x0008
#define SGMII0_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_ALIGN           0
#define SGMII0_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_BITS            1
#define SGMII0_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_SHIFT           3

/* SGMII0_Digital :: TestMode :: fifo_elasticity_rx [02:01] */
#define Wr_SGMII0_Digital_TestMode_fifo_elasticity_rx(x) WriteRegBits16(SGMII0_DIGITAL_TESTMODE,0x6,1,x)
#define Rd_SGMII0_Digital_TestMode_fifo_elasticity_rx(x) ReadRegBits16(SGMII0_DIGITAL_TESTMODE,0x6,1)
#define SGMII0_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_MASK            0x0006
#define SGMII0_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_ALIGN           0
#define SGMII0_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_BITS            2
#define SGMII0_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_SHIFT           1

/* SGMII0_Digital :: TestMode :: fifo_ipg_rx_cya [00:00] */
#define Wr_SGMII0_Digital_TestMode_fifo_ipg_rx_cya(x) WriteRegBits16(SGMII0_DIGITAL_TESTMODE,0x1,0,x)
#define Rd_SGMII0_Digital_TestMode_fifo_ipg_rx_cya(x) ReadRegBits16(SGMII0_DIGITAL_TESTMODE,0x1,0)
#define SGMII0_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_MASK               0x0001
#define SGMII0_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_ALIGN              0
#define SGMII0_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_BITS               1
#define SGMII0_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_SHIFT              0


/****************************************************************************
 * SGMII0_Digital :: TxPktCnt
 ***************************************************************************/
/* SGMII0_Digital :: TxPktCnt :: TxPktCnt [15:00] */
#define Wr_SGMII0_Digital_TxPktCnt_TxPktCnt(x) WriteReg16(SGMII0_DIGITAL_TXPKTCNT,x)
#define Rd_SGMII0_Digital_TxPktCnt_TxPktCnt(x) ReadReg16(SGMII0_DIGITAL_TXPKTCNT)
#define SGMII0_DIGITAL_TXPKTCNT_TXPKTCNT_MASK                      0xffff
#define SGMII0_DIGITAL_TXPKTCNT_TXPKTCNT_ALIGN                     0
#define SGMII0_DIGITAL_TXPKTCNT_TXPKTCNT_BITS                      16
#define SGMII0_DIGITAL_TXPKTCNT_TXPKTCNT_SHIFT                     0


/****************************************************************************
 * SGMII0_Digital :: RxPktCnt
 ***************************************************************************/
/* SGMII0_Digital :: RxPktCnt :: RxPktCnt [15:00] */
#define Wr_SGMII0_Digital_RxPktCnt_RxPktCnt(x) WriteReg16(SGMII0_DIGITAL_RXPKTCNT,x)
#define Rd_SGMII0_Digital_RxPktCnt_RxPktCnt(x) ReadReg16(SGMII0_DIGITAL_RXPKTCNT)
#define SGMII0_DIGITAL_RXPKTCNT_RXPKTCNT_MASK                      0xffff
#define SGMII0_DIGITAL_RXPKTCNT_RXPKTCNT_ALIGN                     0
#define SGMII0_DIGITAL_RXPKTCNT_RXPKTCNT_BITS                      16
#define SGMII0_DIGITAL_RXPKTCNT_RXPKTCNT_SHIFT                     0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_serdesID
 ***************************************************************************/
/****************************************************************************
 * SGMII0_serdesID :: serdesID0
 ***************************************************************************/
/* SGMII0_serdesID :: serdesID0 :: rev_letter [15:14] */
#define Wr_SGMII0_serdesID_serdesID0_rev_letter(x) WriteRegBits16(SGMII0_SERDESID_SERDESID0,0xc000,14,x)
#define Rd_SGMII0_serdesID_serdesID0_rev_letter(x) ReadRegBits16(SGMII0_SERDESID_SERDESID0,0xc000,14)
#define SGMII0_SERDESID_SERDESID0_REV_LETTER_MASK                  0xc000
#define SGMII0_SERDESID_SERDESID0_REV_LETTER_ALIGN                 0
#define SGMII0_SERDESID_SERDESID0_REV_LETTER_BITS                  2
#define SGMII0_SERDESID_SERDESID0_REV_LETTER_SHIFT                 14

/* SGMII0_serdesID :: serdesID0 :: rev_number [13:11] */
#define Wr_SGMII0_serdesID_serdesID0_rev_number(x) WriteRegBits16(SGMII0_SERDESID_SERDESID0,0x3800,11,x)
#define Rd_SGMII0_serdesID_serdesID0_rev_number(x) ReadRegBits16(SGMII0_SERDESID_SERDESID0,0x3800,11)
#define SGMII0_SERDESID_SERDESID0_REV_NUMBER_MASK                  0x3800
#define SGMII0_SERDESID_SERDESID0_REV_NUMBER_ALIGN                 0
#define SGMII0_SERDESID_SERDESID0_REV_NUMBER_BITS                  3
#define SGMII0_SERDESID_SERDESID0_REV_NUMBER_SHIFT                 11

/* SGMII0_serdesID :: serdesID0 :: bonding [10:09] */
#define Wr_SGMII0_serdesID_serdesID0_bonding(x) WriteRegBits16(SGMII0_SERDESID_SERDESID0,0x600,9,x)
#define Rd_SGMII0_serdesID_serdesID0_bonding(x) ReadRegBits16(SGMII0_SERDESID_SERDESID0,0x600,9)
#define SGMII0_SERDESID_SERDESID0_BONDING_MASK                     0x0600
#define SGMII0_SERDESID_SERDESID0_BONDING_ALIGN                    0
#define SGMII0_SERDESID_SERDESID0_BONDING_BITS                     2
#define SGMII0_SERDESID_SERDESID0_BONDING_SHIFT                    9

/* SGMII0_serdesID :: serdesID0 :: tech_proc [08:06] */
#define Wr_SGMII0_serdesID_serdesID0_tech_proc(x) WriteRegBits16(SGMII0_SERDESID_SERDESID0,0x1c0,6,x)
#define Rd_SGMII0_serdesID_serdesID0_tech_proc(x) ReadRegBits16(SGMII0_SERDESID_SERDESID0,0x1c0,6)
#define SGMII0_SERDESID_SERDESID0_TECH_PROC_MASK                   0x01c0
#define SGMII0_SERDESID_SERDESID0_TECH_PROC_ALIGN                  0
#define SGMII0_SERDESID_SERDESID0_TECH_PROC_BITS                   3
#define SGMII0_SERDESID_SERDESID0_TECH_PROC_SHIFT                  6

/* SGMII0_serdesID :: serdesID0 :: model_number [05:00] */
#define Wr_SGMII0_serdesID_serdesID0_model_number(x) WriteRegBits16(SGMII0_SERDESID_SERDESID0,0x3f,0,x)
#define Rd_SGMII0_serdesID_serdesID0_model_number(x) ReadRegBits16(SGMII0_SERDESID_SERDESID0,0x3f,0)
#define SGMII0_SERDESID_SERDESID0_MODEL_NUMBER_MASK                0x003f
#define SGMII0_SERDESID_SERDESID0_MODEL_NUMBER_ALIGN               0
#define SGMII0_SERDESID_SERDESID0_MODEL_NUMBER_BITS                6
#define SGMII0_SERDESID_SERDESID0_MODEL_NUMBER_SHIFT               0


/****************************************************************************
 * SGMII0_serdesID :: serdesID1
 ***************************************************************************/
/* SGMII0_serdesID :: serdesID1 :: multiplicity [15:12] */
#define Wr_SGMII0_serdesID_serdesID1_multiplicity(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0xf000,12,x)
#define Rd_SGMII0_serdesID_serdesID1_multiplicity(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0xf000,12)
#define SGMII0_SERDESID_SERDESID1_MULTIPLICITY_MASK                0xf000
#define SGMII0_SERDESID_SERDESID1_MULTIPLICITY_ALIGN               0
#define SGMII0_SERDESID_SERDESID1_MULTIPLICITY_BITS                4
#define SGMII0_SERDESID_SERDESID1_MULTIPLICITY_SHIFT               12

/* SGMII0_serdesID :: serdesID1 :: CL37 [11:11] */
#define Wr_SGMII0_serdesID_serdesID1_CL37(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x800,11,x)
#define Rd_SGMII0_serdesID_serdesID1_CL37(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x800,11)
#define SGMII0_SERDESID_SERDESID1_CL37_MASK                        0x0800
#define SGMII0_SERDESID_SERDESID1_CL37_ALIGN                       0
#define SGMII0_SERDESID_SERDESID1_CL37_BITS                        1
#define SGMII0_SERDESID_SERDESID1_CL37_SHIFT                       11

/* SGMII0_serdesID :: serdesID1 :: CL73 [10:10] */
#define Wr_SGMII0_serdesID_serdesID1_CL73(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x400,10,x)
#define Rd_SGMII0_serdesID_serdesID1_CL73(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x400,10)
#define SGMII0_SERDESID_SERDESID1_CL73_MASK                        0x0400
#define SGMII0_SERDESID_SERDESID1_CL73_ALIGN                       0
#define SGMII0_SERDESID_SERDESID1_CL73_BITS                        1
#define SGMII0_SERDESID_SERDESID1_CL73_SHIFT                       10

/* SGMII0_serdesID :: serdesID1 :: CL36 [09:09] */
#define Wr_SGMII0_serdesID_serdesID1_CL36(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x200,9,x)
#define Rd_SGMII0_serdesID_serdesID1_CL36(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x200,9)
#define SGMII0_SERDESID_SERDESID1_CL36_MASK                        0x0200
#define SGMII0_SERDESID_SERDESID1_CL36_ALIGN                       0
#define SGMII0_SERDESID_SERDESID1_CL36_BITS                        1
#define SGMII0_SERDESID_SERDESID1_CL36_SHIFT                       9

/* SGMII0_serdesID :: serdesID1 :: CL48 [08:08] */
#define Wr_SGMII0_serdesID_serdesID1_CL48(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x100,8,x)
#define Rd_SGMII0_serdesID_serdesID1_CL48(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x100,8)
#define SGMII0_SERDESID_SERDESID1_CL48_MASK                        0x0100
#define SGMII0_SERDESID_SERDESID1_CL48_ALIGN                       0
#define SGMII0_SERDESID_SERDESID1_CL48_BITS                        1
#define SGMII0_SERDESID_SERDESID1_CL48_SHIFT                       8

/* SGMII0_serdesID :: serdesID1 :: HiGig [07:07] */
#define Wr_SGMII0_serdesID_serdesID1_HiGig(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x80,7,x)
#define Rd_SGMII0_serdesID_serdesID1_HiGig(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x80,7)
#define SGMII0_SERDESID_SERDESID1_HIGIG_MASK                       0x0080
#define SGMII0_SERDESID_SERDESID1_HIGIG_ALIGN                      0
#define SGMII0_SERDESID_SERDESID1_HIGIG_BITS                       1
#define SGMII0_SERDESID_SERDESID1_HIGIG_SHIFT                      7

/* SGMII0_serdesID :: serdesID1 :: HiGigII [06:06] */
#define Wr_SGMII0_serdesID_serdesID1_HiGigII(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x40,6,x)
#define Rd_SGMII0_serdesID_serdesID1_HiGigII(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x40,6)
#define SGMII0_SERDESID_SERDESID1_HIGIGII_MASK                     0x0040
#define SGMII0_SERDESID_SERDESID1_HIGIGII_ALIGN                    0
#define SGMII0_SERDESID_SERDESID1_HIGIGII_BITS                     1
#define SGMII0_SERDESID_SERDESID1_HIGIGII_SHIFT                    6

/* SGMII0_serdesID :: serdesID1 :: PCIE [05:05] */
#define Wr_SGMII0_serdesID_serdesID1_PCIE(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x20,5,x)
#define Rd_SGMII0_serdesID_serdesID1_PCIE(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x20,5)
#define SGMII0_SERDESID_SERDESID1_PCIE_MASK                        0x0020
#define SGMII0_SERDESID_SERDESID1_PCIE_ALIGN                       0
#define SGMII0_SERDESID_SERDESID1_PCIE_BITS                        1
#define SGMII0_SERDESID_SERDESID1_PCIE_SHIFT                       5

/* SGMII0_serdesID :: serdesID1 :: PCIE_II [04:04] */
#define Wr_SGMII0_serdesID_serdesID1_PCIE_II(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x10,4,x)
#define Rd_SGMII0_serdesID_serdesID1_PCIE_II(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x10,4)
#define SGMII0_SERDESID_SERDESID1_PCIE_II_MASK                     0x0010
#define SGMII0_SERDESID_SERDESID1_PCIE_II_ALIGN                    0
#define SGMII0_SERDESID_SERDESID1_PCIE_II_BITS                     1
#define SGMII0_SERDESID_SERDESID1_PCIE_II_SHIFT                    4

/* SGMII0_serdesID :: serdesID1 :: brcm_64B66B [03:03] */
#define Wr_SGMII0_serdesID_serdesID1_brcm_64B66B(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x8,3,x)
#define Rd_SGMII0_serdesID_serdesID1_brcm_64B66B(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x8,3)
#define SGMII0_SERDESID_SERDESID1_BRCM_64B66B_MASK                 0x0008
#define SGMII0_SERDESID_SERDESID1_BRCM_64B66B_ALIGN                0
#define SGMII0_SERDESID_SERDESID1_BRCM_64B66B_BITS                 1
#define SGMII0_SERDESID_SERDESID1_BRCM_64B66B_SHIFT                3

/* SGMII0_serdesID :: serdesID1 :: Scrambler [02:02] */
#define Wr_SGMII0_serdesID_serdesID1_Scrambler(x) WriteRegBits16(SGMII0_SERDESID_SERDESID1,0x4,2,x)
#define Rd_SGMII0_serdesID_serdesID1_Scrambler(x) ReadRegBits16(SGMII0_SERDESID_SERDESID1,0x4,2)
#define SGMII0_SERDESID_SERDESID1_SCRAMBLER_MASK                   0x0004
#define SGMII0_SERDESID_SERDESID1_SCRAMBLER_ALIGN                  0
#define SGMII0_SERDESID_SERDESID1_SCRAMBLER_BITS                   1
#define SGMII0_SERDESID_SERDESID1_SCRAMBLER_SHIFT                  2

/* SGMII0_serdesID :: serdesID1 :: reserved0 [01:00] */
#define SGMII0_SERDESID_SERDESID1_RESERVED0_MASK                   0x0003
#define SGMII0_SERDESID_SERDESID1_RESERVED0_ALIGN                  0
#define SGMII0_SERDESID_SERDESID1_RESERVED0_BITS                   2
#define SGMII0_SERDESID_SERDESID1_RESERVED0_SHIFT                  0


/****************************************************************************
 * SGMII0_serdesID :: serdesID2
 ***************************************************************************/
/* SGMII0_serdesID :: serdesID2 :: ID3present [15:15] */
#define Wr_SGMII0_serdesID_serdesID2_ID3present(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x8000,15,x)
#define Rd_SGMII0_serdesID_serdesID2_ID3present(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x8000,15)
#define SGMII0_SERDESID_SERDESID2_ID3PRESENT_MASK                  0x8000
#define SGMII0_SERDESID_SERDESID2_ID3PRESENT_ALIGN                 0
#define SGMII0_SERDESID_SERDESID2_ID3PRESENT_BITS                  1
#define SGMII0_SERDESID_SERDESID2_ID3PRESENT_SHIFT                 15

/* SGMII0_serdesID :: serdesID2 :: dr_25G_4L [14:14] */
#define Wr_SGMII0_serdesID_serdesID2_dr_25G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x4000,14,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_25G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x4000,14)
#define SGMII0_SERDESID_SERDESID2_DR_25G_4L_MASK                   0x4000
#define SGMII0_SERDESID_SERDESID2_DR_25G_4L_ALIGN                  0
#define SGMII0_SERDESID_SERDESID2_DR_25G_4L_BITS                   1
#define SGMII0_SERDESID_SERDESID2_DR_25G_4L_SHIFT                  14

/* SGMII0_serdesID :: serdesID2 :: dr_21G_4L [13:13] */
#define Wr_SGMII0_serdesID_serdesID2_dr_21G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x2000,13,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_21G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x2000,13)
#define SGMII0_SERDESID_SERDESID2_DR_21G_4L_MASK                   0x2000
#define SGMII0_SERDESID_SERDESID2_DR_21G_4L_ALIGN                  0
#define SGMII0_SERDESID_SERDESID2_DR_21G_4L_BITS                   1
#define SGMII0_SERDESID_SERDESID2_DR_21G_4L_SHIFT                  13

/* SGMII0_serdesID :: serdesID2 :: dr_20G_4L [12:12] */
#define Wr_SGMII0_serdesID_serdesID2_dr_20G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x1000,12,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_20G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x1000,12)
#define SGMII0_SERDESID_SERDESID2_DR_20G_4L_MASK                   0x1000
#define SGMII0_SERDESID_SERDESID2_DR_20G_4L_ALIGN                  0
#define SGMII0_SERDESID_SERDESID2_DR_20G_4L_BITS                   1
#define SGMII0_SERDESID_SERDESID2_DR_20G_4L_SHIFT                  12

/* SGMII0_serdesID :: serdesID2 :: dr_16G_4L [11:11] */
#define Wr_SGMII0_serdesID_serdesID2_dr_16G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x800,11,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_16G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x800,11)
#define SGMII0_SERDESID_SERDESID2_DR_16G_4L_MASK                   0x0800
#define SGMII0_SERDESID_SERDESID2_DR_16G_4L_ALIGN                  0
#define SGMII0_SERDESID_SERDESID2_DR_16G_4L_BITS                   1
#define SGMII0_SERDESID_SERDESID2_DR_16G_4L_SHIFT                  11

/* SGMII0_serdesID :: serdesID2 :: dr_15G_4L [10:10] */
#define Wr_SGMII0_serdesID_serdesID2_dr_15G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x400,10,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_15G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x400,10)
#define SGMII0_SERDESID_SERDESID2_DR_15G_4L_MASK                   0x0400
#define SGMII0_SERDESID_SERDESID2_DR_15G_4L_ALIGN                  0
#define SGMII0_SERDESID_SERDESID2_DR_15G_4L_BITS                   1
#define SGMII0_SERDESID_SERDESID2_DR_15G_4L_SHIFT                  10

/* SGMII0_serdesID :: serdesID2 :: dr_13G_4L [09:09] */
#define Wr_SGMII0_serdesID_serdesID2_dr_13G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x200,9,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_13G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x200,9)
#define SGMII0_SERDESID_SERDESID2_DR_13G_4L_MASK                   0x0200
#define SGMII0_SERDESID_SERDESID2_DR_13G_4L_ALIGN                  0
#define SGMII0_SERDESID_SERDESID2_DR_13G_4L_BITS                   1
#define SGMII0_SERDESID_SERDESID2_DR_13G_4L_SHIFT                  9

/* SGMII0_serdesID :: serdesID2 :: dr_12_5G_4L [08:08] */
#define Wr_SGMII0_serdesID_serdesID2_dr_12_5G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x100,8,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_12_5G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x100,8)
#define SGMII0_SERDESID_SERDESID2_DR_12_5G_4L_MASK                 0x0100
#define SGMII0_SERDESID_SERDESID2_DR_12_5G_4L_ALIGN                0
#define SGMII0_SERDESID_SERDESID2_DR_12_5G_4L_BITS                 1
#define SGMII0_SERDESID_SERDESID2_DR_12_5G_4L_SHIFT                8

/* SGMII0_serdesID :: serdesID2 :: dr_12G_4L [07:07] */
#define Wr_SGMII0_serdesID_serdesID2_dr_12G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x80,7,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_12G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x80,7)
#define SGMII0_SERDESID_SERDESID2_DR_12G_4L_MASK                   0x0080
#define SGMII0_SERDESID_SERDESID2_DR_12G_4L_ALIGN                  0
#define SGMII0_SERDESID_SERDESID2_DR_12G_4L_BITS                   1
#define SGMII0_SERDESID_SERDESID2_DR_12G_4L_SHIFT                  7

/* SGMII0_serdesID :: serdesID2 :: dr_10G_4L [06:06] */
#define Wr_SGMII0_serdesID_serdesID2_dr_10G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x40,6,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_10G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x40,6)
#define SGMII0_SERDESID_SERDESID2_DR_10G_4L_MASK                   0x0040
#define SGMII0_SERDESID_SERDESID2_DR_10G_4L_ALIGN                  0
#define SGMII0_SERDESID_SERDESID2_DR_10G_4L_BITS                   1
#define SGMII0_SERDESID_SERDESID2_DR_10G_4L_SHIFT                  6

/* SGMII0_serdesID :: serdesID2 :: dr_6G_4L [05:05] */
#define Wr_SGMII0_serdesID_serdesID2_dr_6G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x20,5,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_6G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x20,5)
#define SGMII0_SERDESID_SERDESID2_DR_6G_4L_MASK                    0x0020
#define SGMII0_SERDESID_SERDESID2_DR_6G_4L_ALIGN                   0
#define SGMII0_SERDESID_SERDESID2_DR_6G_4L_BITS                    1
#define SGMII0_SERDESID_SERDESID2_DR_6G_4L_SHIFT                   5

/* SGMII0_serdesID :: serdesID2 :: dr_5G_4L [04:04] */
#define Wr_SGMII0_serdesID_serdesID2_dr_5G_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x10,4,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_5G_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x10,4)
#define SGMII0_SERDESID_SERDESID2_DR_5G_4L_MASK                    0x0010
#define SGMII0_SERDESID_SERDESID2_DR_5G_4L_ALIGN                   0
#define SGMII0_SERDESID_SERDESID2_DR_5G_4L_BITS                    1
#define SGMII0_SERDESID_SERDESID2_DR_5G_4L_SHIFT                   4

/* SGMII0_serdesID :: serdesID2 :: dr_2p5G_SL [03:03] */
#define Wr_SGMII0_serdesID_serdesID2_dr_2p5G_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x8,3,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_2p5G_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x8,3)
#define SGMII0_SERDESID_SERDESID2_DR_2P5G_SL_MASK                  0x0008
#define SGMII0_SERDESID_SERDESID2_DR_2P5G_SL_ALIGN                 0
#define SGMII0_SERDESID_SERDESID2_DR_2P5G_SL_BITS                  1
#define SGMII0_SERDESID_SERDESID2_DR_2P5G_SL_SHIFT                 3

/* SGMII0_serdesID :: serdesID2 :: dr_1G_SL [02:02] */
#define Wr_SGMII0_serdesID_serdesID2_dr_1G_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x4,2,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_1G_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x4,2)
#define SGMII0_SERDESID_SERDESID2_DR_1G_SL_MASK                    0x0004
#define SGMII0_SERDESID_SERDESID2_DR_1G_SL_ALIGN                   0
#define SGMII0_SERDESID_SERDESID2_DR_1G_SL_BITS                    1
#define SGMII0_SERDESID_SERDESID2_DR_1G_SL_SHIFT                   2

/* SGMII0_serdesID :: serdesID2 :: dr_100M_SL [01:01] */
#define Wr_SGMII0_serdesID_serdesID2_dr_100M_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x2,1,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_100M_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x2,1)
#define SGMII0_SERDESID_SERDESID2_DR_100M_SL_MASK                  0x0002
#define SGMII0_SERDESID_SERDESID2_DR_100M_SL_ALIGN                 0
#define SGMII0_SERDESID_SERDESID2_DR_100M_SL_BITS                  1
#define SGMII0_SERDESID_SERDESID2_DR_100M_SL_SHIFT                 1

/* SGMII0_serdesID :: serdesID2 :: dr_10M_SL [00:00] */
#define Wr_SGMII0_serdesID_serdesID2_dr_10M_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID2,0x1,0,x)
#define Rd_SGMII0_serdesID_serdesID2_dr_10M_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID2,0x1,0)
#define SGMII0_SERDESID_SERDESID2_DR_10M_SL_MASK                   0x0001
#define SGMII0_SERDESID_SERDESID2_DR_10M_SL_ALIGN                  0
#define SGMII0_SERDESID_SERDESID2_DR_10M_SL_BITS                   1
#define SGMII0_SERDESID_SERDESID2_DR_10M_SL_SHIFT                  0


/****************************************************************************
 * SGMII0_serdesID :: serdesID3
 ***************************************************************************/
/* SGMII0_serdesID :: serdesID3 :: ID4present [15:15] */
#define Wr_SGMII0_serdesID_serdesID3_ID4present(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x8000,15,x)
#define Rd_SGMII0_serdesID_serdesID3_ID4present(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x8000,15)
#define SGMII0_SERDESID_SERDESID3_ID4PRESENT_MASK                  0x8000
#define SGMII0_SERDESID_SERDESID3_ID4PRESENT_ALIGN                 0
#define SGMII0_SERDESID_SERDESID3_ID4PRESENT_BITS                  1
#define SGMII0_SERDESID_SERDESID3_ID4PRESENT_SHIFT                 15

/* SGMII0_serdesID :: serdesID3 :: reserved0 [14:10] */
#define SGMII0_SERDESID_SERDESID3_RESERVED0_MASK                   0x7c00
#define SGMII0_SERDESID_SERDESID3_RESERVED0_ALIGN                  0
#define SGMII0_SERDESID_SERDESID3_RESERVED0_BITS                   5
#define SGMII0_SERDESID_SERDESID3_RESERVED0_SHIFT                  10

/* SGMII0_serdesID :: serdesID3 :: dr_40000_4L [09:09] */
#define Wr_SGMII0_serdesID_serdesID3_dr_40000_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x200,9,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_40000_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x200,9)
#define SGMII0_SERDESID_SERDESID3_DR_40000_4L_MASK                 0x0200
#define SGMII0_SERDESID_SERDESID3_DR_40000_4L_ALIGN                0
#define SGMII0_SERDESID_SERDESID3_DR_40000_4L_BITS                 1
#define SGMII0_SERDESID_SERDESID3_DR_40000_4L_SHIFT                9

/* SGMII0_serdesID :: serdesID3 :: dr_32700_4L [08:08] */
#define Wr_SGMII0_serdesID_serdesID3_dr_32700_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x100,8,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_32700_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x100,8)
#define SGMII0_SERDESID_SERDESID3_DR_32700_4L_MASK                 0x0100
#define SGMII0_SERDESID_SERDESID3_DR_32700_4L_ALIGN                0
#define SGMII0_SERDESID_SERDESID3_DR_32700_4L_BITS                 1
#define SGMII0_SERDESID_SERDESID3_DR_32700_4L_SHIFT                8

/* SGMII0_serdesID :: serdesID3 :: dr_31500_4L [07:07] */
#define Wr_SGMII0_serdesID_serdesID3_dr_31500_4L(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x80,7,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_31500_4L(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x80,7)
#define SGMII0_SERDESID_SERDESID3_DR_31500_4L_MASK                 0x0080
#define SGMII0_SERDESID_SERDESID3_DR_31500_4L_ALIGN                0
#define SGMII0_SERDESID_SERDESID3_DR_31500_4L_BITS                 1
#define SGMII0_SERDESID_SERDESID3_DR_31500_4L_SHIFT                7

/* SGMII0_serdesID :: serdesID3 :: dr_2400_SL [06:06] */
#define Wr_SGMII0_serdesID_serdesID3_dr_2400_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x40,6,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_2400_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x40,6)
#define SGMII0_SERDESID_SERDESID3_DR_2400_SL_MASK                  0x0040
#define SGMII0_SERDESID_SERDESID3_DR_2400_SL_ALIGN                 0
#define SGMII0_SERDESID_SERDESID3_DR_2400_SL_BITS                  1
#define SGMII0_SERDESID_SERDESID3_DR_2400_SL_SHIFT                 6

/* SGMII0_serdesID :: serdesID3 :: dr_1200_SL [05:05] */
#define Wr_SGMII0_serdesID_serdesID3_dr_1200_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x20,5,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_1200_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x20,5)
#define SGMII0_SERDESID_SERDESID3_DR_1200_SL_MASK                  0x0020
#define SGMII0_SERDESID_SERDESID3_DR_1200_SL_ALIGN                 0
#define SGMII0_SERDESID_SERDESID3_DR_1200_SL_BITS                  1
#define SGMII0_SERDESID_SERDESID3_DR_1200_SL_SHIFT                 5

/* SGMII0_serdesID :: serdesID3 :: dr_6400_SL [04:04] */
#define Wr_SGMII0_serdesID_serdesID3_dr_6400_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x10,4,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_6400_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x10,4)
#define SGMII0_SERDESID_SERDESID3_DR_6400_SL_MASK                  0x0010
#define SGMII0_SERDESID_SERDESID3_DR_6400_SL_ALIGN                 0
#define SGMII0_SERDESID_SERDESID3_DR_6400_SL_BITS                  1
#define SGMII0_SERDESID_SERDESID3_DR_6400_SL_SHIFT                 4

/* SGMII0_serdesID :: serdesID3 :: dr_5000_SL [03:03] */
#define Wr_SGMII0_serdesID_serdesID3_dr_5000_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x8,3,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_5000_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x8,3)
#define SGMII0_SERDESID_SERDESID3_DR_5000_SL_MASK                  0x0008
#define SGMII0_SERDESID_SERDESID3_DR_5000_SL_ALIGN                 0
#define SGMII0_SERDESID_SERDESID3_DR_5000_SL_BITS                  1
#define SGMII0_SERDESID_SERDESID3_DR_5000_SL_SHIFT                 3

/* SGMII0_serdesID :: serdesID3 :: dr_4000_SL [02:02] */
#define Wr_SGMII0_serdesID_serdesID3_dr_4000_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x4,2,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_4000_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x4,2)
#define SGMII0_SERDESID_SERDESID3_DR_4000_SL_MASK                  0x0004
#define SGMII0_SERDESID_SERDESID3_DR_4000_SL_ALIGN                 0
#define SGMII0_SERDESID_SERDESID3_DR_4000_SL_BITS                  1
#define SGMII0_SERDESID_SERDESID3_DR_4000_SL_SHIFT                 2

/* SGMII0_serdesID :: serdesID3 :: dr_2000_SL [01:01] */
#define Wr_SGMII0_serdesID_serdesID3_dr_2000_SL(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x2,1,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_2000_SL(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x2,1)
#define SGMII0_SERDESID_SERDESID3_DR_2000_SL_MASK                  0x0002
#define SGMII0_SERDESID_SERDESID3_DR_2000_SL_ALIGN                 0
#define SGMII0_SERDESID_SERDESID3_DR_2000_SL_BITS                  1
#define SGMII0_SERDESID_SERDESID3_DR_2000_SL_SHIFT                 1

/* SGMII0_serdesID :: serdesID3 :: dr_100FX [00:00] */
#define Wr_SGMII0_serdesID_serdesID3_dr_100FX(x) WriteRegBits16(SGMII0_SERDESID_SERDESID3,0x1,0,x)
#define Rd_SGMII0_serdesID_serdesID3_dr_100FX(x) ReadRegBits16(SGMII0_SERDESID_SERDESID3,0x1,0)
#define SGMII0_SERDESID_SERDESID3_DR_100FX_MASK                    0x0001
#define SGMII0_SERDESID_SERDESID3_DR_100FX_ALIGN                   0
#define SGMII0_SERDESID_SERDESID3_DR_100FX_BITS                    1
#define SGMII0_SERDESID_SERDESID3_DR_100FX_SHIFT                   0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_Digital3
 ***************************************************************************/
/****************************************************************************
 * SGMII0_Digital3 :: TPOUT_1
 ***************************************************************************/
/* SGMII0_Digital3 :: TPOUT_1 :: tpout1 [15:00] */
#define Wr_SGMII0_Digital3_TPOUT_1_tpout1(x) WriteReg16(SGMII0_DIGITAL3_TPOUT_1,x)
#define Rd_SGMII0_Digital3_TPOUT_1_tpout1(x) ReadReg16(SGMII0_DIGITAL3_TPOUT_1)
#define SGMII0_DIGITAL3_TPOUT_1_TPOUT1_MASK                        0xffff
#define SGMII0_DIGITAL3_TPOUT_1_TPOUT1_ALIGN                       0
#define SGMII0_DIGITAL3_TPOUT_1_TPOUT1_BITS                        16
#define SGMII0_DIGITAL3_TPOUT_1_TPOUT1_SHIFT                       0


/****************************************************************************
 * SGMII0_Digital3 :: TPOUT_2
 ***************************************************************************/
/* SGMII0_Digital3 :: TPOUT_2 :: tpout2 [15:00] */
#define Wr_SGMII0_Digital3_TPOUT_2_tpout2(x) WriteReg16(SGMII0_DIGITAL3_TPOUT_2,x)
#define Rd_SGMII0_Digital3_TPOUT_2_tpout2(x) ReadReg16(SGMII0_DIGITAL3_TPOUT_2)
#define SGMII0_DIGITAL3_TPOUT_2_TPOUT2_MASK                        0xffff
#define SGMII0_DIGITAL3_TPOUT_2_TPOUT2_ALIGN                       0
#define SGMII0_DIGITAL3_TPOUT_2_TPOUT2_BITS                        16
#define SGMII0_DIGITAL3_TPOUT_2_TPOUT2_SHIFT                       0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_Digital4
 ***************************************************************************/
/****************************************************************************
 * SGMII0_Digital4 :: Misc3
 ***************************************************************************/
/* SGMII0_Digital4 :: Misc3 :: reserved0 [15:10] */
#define SGMII0_DIGITAL4_MISC3_RESERVED0_MASK                       0xfc00
#define SGMII0_DIGITAL4_MISC3_RESERVED0_ALIGN                      0
#define SGMII0_DIGITAL4_MISC3_RESERVED0_BITS                       6
#define SGMII0_DIGITAL4_MISC3_RESERVED0_SHIFT                      10

/* SGMII0_Digital4 :: Misc3 :: fifo_ipg_cya [09:09] */
#define Wr_SGMII0_Digital4_Misc3_fifo_ipg_cya(x) WriteRegBits16(SGMII0_DIGITAL4_MISC3,0x200,9,x)
#define Rd_SGMII0_Digital4_Misc3_fifo_ipg_cya(x) ReadRegBits16(SGMII0_DIGITAL4_MISC3,0x200,9)
#define SGMII0_DIGITAL4_MISC3_FIFO_IPG_CYA_MASK                    0x0200
#define SGMII0_DIGITAL4_MISC3_FIFO_IPG_CYA_ALIGN                   0
#define SGMII0_DIGITAL4_MISC3_FIFO_IPG_CYA_BITS                    1
#define SGMII0_DIGITAL4_MISC3_FIFO_IPG_CYA_SHIFT                   9

/* SGMII0_Digital4 :: Misc3 :: reserved1 [08:07] */
#define SGMII0_DIGITAL4_MISC3_RESERVED1_MASK                       0x0180
#define SGMII0_DIGITAL4_MISC3_RESERVED1_ALIGN                      0
#define SGMII0_DIGITAL4_MISC3_RESERVED1_BITS                       2
#define SGMII0_DIGITAL4_MISC3_RESERVED1_SHIFT                      7

/* SGMII0_Digital4 :: Misc3 :: laneDisable [06:06] */
#define Wr_SGMII0_Digital4_Misc3_laneDisable(x) WriteRegBits16(SGMII0_DIGITAL4_MISC3,0x40,6,x)
#define Rd_SGMII0_Digital4_Misc3_laneDisable(x) ReadRegBits16(SGMII0_DIGITAL4_MISC3,0x40,6)
#define SGMII0_DIGITAL4_MISC3_LANEDISABLE_MASK                     0x0040
#define SGMII0_DIGITAL4_MISC3_LANEDISABLE_ALIGN                    0
#define SGMII0_DIGITAL4_MISC3_LANEDISABLE_BITS                     1
#define SGMII0_DIGITAL4_MISC3_LANEDISABLE_SHIFT                    6

/* SGMII0_Digital4 :: Misc3 :: reserved2 [05:00] */
#define SGMII0_DIGITAL4_MISC3_RESERVED2_MASK                       0x003f
#define SGMII0_DIGITAL4_MISC3_RESERVED2_ALIGN                      0
#define SGMII0_DIGITAL4_MISC3_RESERVED2_BITS                       6
#define SGMII0_DIGITAL4_MISC3_RESERVED2_SHIFT                      0


/****************************************************************************
 * SGMII0_Digital4 :: Misc5
 ***************************************************************************/
/* SGMII0_Digital4 :: Misc5 :: LPI_en_rx [15:15] */
#define Wr_SGMII0_Digital4_Misc5_LPI_en_rx(x) WriteRegBits16(SGMII0_DIGITAL4_MISC5,0x8000,15,x)
#define Rd_SGMII0_Digital4_Misc5_LPI_en_rx(x) ReadRegBits16(SGMII0_DIGITAL4_MISC5,0x8000,15)
#define SGMII0_DIGITAL4_MISC5_LPI_EN_RX_MASK                       0x8000
#define SGMII0_DIGITAL4_MISC5_LPI_EN_RX_ALIGN                      0
#define SGMII0_DIGITAL4_MISC5_LPI_EN_RX_BITS                       1
#define SGMII0_DIGITAL4_MISC5_LPI_EN_RX_SHIFT                      15

/* SGMII0_Digital4 :: Misc5 :: LPI_en_tx [14:14] */
#define Wr_SGMII0_Digital4_Misc5_LPI_en_tx(x) WriteRegBits16(SGMII0_DIGITAL4_MISC5,0x4000,14,x)
#define Rd_SGMII0_Digital4_Misc5_LPI_en_tx(x) ReadRegBits16(SGMII0_DIGITAL4_MISC5,0x4000,14)
#define SGMII0_DIGITAL4_MISC5_LPI_EN_TX_MASK                       0x4000
#define SGMII0_DIGITAL4_MISC5_LPI_EN_TX_ALIGN                      0
#define SGMII0_DIGITAL4_MISC5_LPI_EN_TX_BITS                       1
#define SGMII0_DIGITAL4_MISC5_LPI_EN_TX_SHIFT                      14

/* SGMII0_Digital4 :: Misc5 :: reserved0 [13:00] */
#define SGMII0_DIGITAL4_MISC5_RESERVED0_MASK                       0x3fff
#define SGMII0_DIGITAL4_MISC5_RESERVED0_ALIGN                      0
#define SGMII0_DIGITAL4_MISC5_RESERVED0_BITS                       14
#define SGMII0_DIGITAL4_MISC5_RESERVED0_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_FX100
 ***************************************************************************/
/****************************************************************************
 * SGMII0_FX100 :: Control1
 ***************************************************************************/
/* SGMII0_FX100 :: Control1 :: data_sampler_en [15:15] */
#define Wr_SGMII0_FX100_Control1_data_sampler_en(x) WriteRegBits16(SGMII0_FX100_CONTROL1,0x8000,15,x)
#define Rd_SGMII0_FX100_Control1_data_sampler_en(x) ReadRegBits16(SGMII0_FX100_CONTROL1,0x8000,15)
#define SGMII0_FX100_CONTROL1_DATA_SAMPLER_EN_MASK                 0x8000
#define SGMII0_FX100_CONTROL1_DATA_SAMPLER_EN_ALIGN                0
#define SGMII0_FX100_CONTROL1_DATA_SAMPLER_EN_BITS                 1
#define SGMII0_FX100_CONTROL1_DATA_SAMPLER_EN_SHIFT                15

/* SGMII0_FX100 :: Control1 :: reserved0 [14:10] */
#define SGMII0_FX100_CONTROL1_RESERVED0_MASK                       0x7c00
#define SGMII0_FX100_CONTROL1_RESERVED0_ALIGN                      0
#define SGMII0_FX100_CONTROL1_RESERVED0_BITS                       5
#define SGMII0_FX100_CONTROL1_RESERVED0_SHIFT                      10

/* SGMII0_FX100 :: Control1 :: rxdata_sel [09:06] */
#define Wr_SGMII0_FX100_Control1_rxdata_sel(x) WriteRegBits16(SGMII0_FX100_CONTROL1,0x3c0,6,x)
#define Rd_SGMII0_FX100_Control1_rxdata_sel(x) ReadRegBits16(SGMII0_FX100_CONTROL1,0x3c0,6)
#define SGMII0_FX100_CONTROL1_RXDATA_SEL_MASK                      0x03c0
#define SGMII0_FX100_CONTROL1_RXDATA_SEL_ALIGN                     0
#define SGMII0_FX100_CONTROL1_RXDATA_SEL_BITS                      4
#define SGMII0_FX100_CONTROL1_RXDATA_SEL_SHIFT                     6

/* SGMII0_FX100 :: Control1 :: disable_rx_qual [05:05] */
#define Wr_SGMII0_FX100_Control1_disable_rx_qual(x) WriteRegBits16(SGMII0_FX100_CONTROL1,0x20,5,x)
#define Rd_SGMII0_FX100_Control1_disable_rx_qual(x) ReadRegBits16(SGMII0_FX100_CONTROL1,0x20,5)
#define SGMII0_FX100_CONTROL1_DISABLE_RX_QUAL_MASK                 0x0020
#define SGMII0_FX100_CONTROL1_DISABLE_RX_QUAL_ALIGN                0
#define SGMII0_FX100_CONTROL1_DISABLE_RX_QUAL_BITS                 1
#define SGMII0_FX100_CONTROL1_DISABLE_RX_QUAL_SHIFT                5

/* SGMII0_FX100 :: Control1 :: force_rx_qual [04:04] */
#define Wr_SGMII0_FX100_Control1_force_rx_qual(x) WriteRegBits16(SGMII0_FX100_CONTROL1,0x10,4,x)
#define Rd_SGMII0_FX100_Control1_force_rx_qual(x) ReadRegBits16(SGMII0_FX100_CONTROL1,0x10,4)
#define SGMII0_FX100_CONTROL1_FORCE_RX_QUAL_MASK                   0x0010
#define SGMII0_FX100_CONTROL1_FORCE_RX_QUAL_ALIGN                  0
#define SGMII0_FX100_CONTROL1_FORCE_RX_QUAL_BITS                   1
#define SGMII0_FX100_CONTROL1_FORCE_RX_QUAL_SHIFT                  4

/* SGMII0_FX100 :: Control1 :: far_end_fault_en [03:03] */
#define Wr_SGMII0_FX100_Control1_far_end_fault_en(x) WriteRegBits16(SGMII0_FX100_CONTROL1,0x8,3,x)
#define Rd_SGMII0_FX100_Control1_far_end_fault_en(x) ReadRegBits16(SGMII0_FX100_CONTROL1,0x8,3)
#define SGMII0_FX100_CONTROL1_FAR_END_FAULT_EN_MASK                0x0008
#define SGMII0_FX100_CONTROL1_FAR_END_FAULT_EN_ALIGN               0
#define SGMII0_FX100_CONTROL1_FAR_END_FAULT_EN_BITS                1
#define SGMII0_FX100_CONTROL1_FAR_END_FAULT_EN_SHIFT               3

/* SGMII0_FX100 :: Control1 :: auto_detect_fx_mode [02:02] */
#define Wr_SGMII0_FX100_Control1_auto_detect_fx_mode(x) WriteRegBits16(SGMII0_FX100_CONTROL1,0x4,2,x)
#define Rd_SGMII0_FX100_Control1_auto_detect_fx_mode(x) ReadRegBits16(SGMII0_FX100_CONTROL1,0x4,2)
#define SGMII0_FX100_CONTROL1_AUTO_DETECT_FX_MODE_MASK             0x0004
#define SGMII0_FX100_CONTROL1_AUTO_DETECT_FX_MODE_ALIGN            0
#define SGMII0_FX100_CONTROL1_AUTO_DETECT_FX_MODE_BITS             1
#define SGMII0_FX100_CONTROL1_AUTO_DETECT_FX_MODE_SHIFT            2

/* SGMII0_FX100 :: Control1 :: full_duplex [01:01] */
#define Wr_SGMII0_FX100_Control1_full_duplex(x) WriteRegBits16(SGMII0_FX100_CONTROL1,0x2,1,x)
#define Rd_SGMII0_FX100_Control1_full_duplex(x) ReadRegBits16(SGMII0_FX100_CONTROL1,0x2,1)
#define SGMII0_FX100_CONTROL1_FULL_DUPLEX_MASK                     0x0002
#define SGMII0_FX100_CONTROL1_FULL_DUPLEX_ALIGN                    0
#define SGMII0_FX100_CONTROL1_FULL_DUPLEX_BITS                     1
#define SGMII0_FX100_CONTROL1_FULL_DUPLEX_SHIFT                    1

/* SGMII0_FX100 :: Control1 :: enable [00:00] */
#define Wr_SGMII0_FX100_Control1_enable(x) WriteRegBits16(SGMII0_FX100_CONTROL1,0x1,0,x)
#define Rd_SGMII0_FX100_Control1_enable(x) ReadRegBits16(SGMII0_FX100_CONTROL1,0x1,0)
#define SGMII0_FX100_CONTROL1_ENABLE_MASK                          0x0001
#define SGMII0_FX100_CONTROL1_ENABLE_ALIGN                         0
#define SGMII0_FX100_CONTROL1_ENABLE_BITS                          1
#define SGMII0_FX100_CONTROL1_ENABLE_SHIFT                         0


/****************************************************************************
 * SGMII0_FX100 :: Control2
 ***************************************************************************/
/* SGMII0_FX100 :: Control2 :: reserved0 [15:12] */
#define SGMII0_FX100_CONTROL2_RESERVED0_MASK                       0xf000
#define SGMII0_FX100_CONTROL2_RESERVED0_ALIGN                      0
#define SGMII0_FX100_CONTROL2_RESERVED0_BITS                       4
#define SGMII0_FX100_CONTROL2_RESERVED0_SHIFT                      12

/* SGMII0_FX100 :: Control2 :: ping_pong_disable [11:11] */
#define Wr_SGMII0_FX100_Control2_ping_pong_disable(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x800,11,x)
#define Rd_SGMII0_FX100_Control2_ping_pong_disable(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x800,11)
#define SGMII0_FX100_CONTROL2_PING_PONG_DISABLE_MASK               0x0800
#define SGMII0_FX100_CONTROL2_PING_PONG_DISABLE_ALIGN              0
#define SGMII0_FX100_CONTROL2_PING_PONG_DISABLE_BITS               1
#define SGMII0_FX100_CONTROL2_PING_PONG_DISABLE_SHIFT              11

/* SGMII0_FX100 :: Control2 :: pll_clk125_sw_ref [10:10] */
#define Wr_SGMII0_FX100_Control2_pll_clk125_sw_ref(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x400,10,x)
#define Rd_SGMII0_FX100_Control2_pll_clk125_sw_ref(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x400,10)
#define SGMII0_FX100_CONTROL2_PLL_CLK125_SW_REF_MASK               0x0400
#define SGMII0_FX100_CONTROL2_PLL_CLK125_SW_REF_ALIGN              0
#define SGMII0_FX100_CONTROL2_PLL_CLK125_SW_REF_BITS               1
#define SGMII0_FX100_CONTROL2_PLL_CLK125_SW_REF_SHIFT              10

/* SGMII0_FX100 :: Control2 :: pll_clk125_sw_en [09:09] */
#define Wr_SGMII0_FX100_Control2_pll_clk125_sw_en(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x200,9,x)
#define Rd_SGMII0_FX100_Control2_pll_clk125_sw_en(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x200,9)
#define SGMII0_FX100_CONTROL2_PLL_CLK125_SW_EN_MASK                0x0200
#define SGMII0_FX100_CONTROL2_PLL_CLK125_SW_EN_ALIGN               0
#define SGMII0_FX100_CONTROL2_PLL_CLK125_SW_EN_BITS                1
#define SGMII0_FX100_CONTROL2_PLL_CLK125_SW_EN_SHIFT               9

/* SGMII0_FX100 :: Control2 :: clk_out_1000_sw_def [08:08] */
#define Wr_SGMII0_FX100_Control2_clk_out_1000_sw_def(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x100,8,x)
#define Rd_SGMII0_FX100_Control2_clk_out_1000_sw_def(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x100,8)
#define SGMII0_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_MASK             0x0100
#define SGMII0_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_ALIGN            0
#define SGMII0_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_BITS             1
#define SGMII0_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_SHIFT            8

/* SGMII0_FX100 :: Control2 :: clk_out_1000_sw_en [07:07] */
#define Wr_SGMII0_FX100_Control2_clk_out_1000_sw_en(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x80,7,x)
#define Rd_SGMII0_FX100_Control2_clk_out_1000_sw_en(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x80,7)
#define SGMII0_FX100_CONTROL2_CLK_OUT_1000_SW_EN_MASK              0x0080
#define SGMII0_FX100_CONTROL2_CLK_OUT_1000_SW_EN_ALIGN             0
#define SGMII0_FX100_CONTROL2_CLK_OUT_1000_SW_EN_BITS              1
#define SGMII0_FX100_CONTROL2_CLK_OUT_1000_SW_EN_SHIFT             7

/* SGMII0_FX100 :: Control2 :: mii_rxc_out_sw_ref [06:06] */
#define Wr_SGMII0_FX100_Control2_mii_rxc_out_sw_ref(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x40,6,x)
#define Rd_SGMII0_FX100_Control2_mii_rxc_out_sw_ref(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x40,6)
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SW_REF_MASK              0x0040
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SW_REF_ALIGN             0
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SW_REF_BITS              1
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SW_REF_SHIFT             6

/* SGMII0_FX100 :: Control2 :: mii_rxc_out_sw_en [05:05] */
#define Wr_SGMII0_FX100_Control2_mii_rxc_out_sw_en(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x20,5,x)
#define Rd_SGMII0_FX100_Control2_mii_rxc_out_sw_en(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x20,5)
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SW_EN_MASK               0x0020
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SW_EN_ALIGN              0
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SW_EN_BITS               1
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SW_EN_SHIFT              5

/* SGMII0_FX100 :: Control2 :: mii_rxc_out_sm_rst [04:04] */
#define Wr_SGMII0_FX100_Control2_mii_rxc_out_sm_rst(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x10,4,x)
#define Rd_SGMII0_FX100_Control2_mii_rxc_out_sm_rst(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x10,4)
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SM_RST_MASK              0x0010
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SM_RST_ALIGN             0
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SM_RST_BITS              1
#define SGMII0_FX100_CONTROL2_MII_RXC_OUT_SM_RST_SHIFT             4

/* SGMII0_FX100 :: Control2 :: mode_chg_nrst [03:03] */
#define Wr_SGMII0_FX100_Control2_mode_chg_nrst(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x8,3,x)
#define Rd_SGMII0_FX100_Control2_mode_chg_nrst(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x8,3)
#define SGMII0_FX100_CONTROL2_MODE_CHG_NRST_MASK                   0x0008
#define SGMII0_FX100_CONTROL2_MODE_CHG_NRST_ALIGN                  0
#define SGMII0_FX100_CONTROL2_MODE_CHG_NRST_BITS                   1
#define SGMII0_FX100_CONTROL2_MODE_CHG_NRST_SHIFT                  3

/* SGMII0_FX100 :: Control2 :: reset_rxfifo [02:02] */
#define Wr_SGMII0_FX100_Control2_reset_rxfifo(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x4,2,x)
#define Rd_SGMII0_FX100_Control2_reset_rxfifo(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x4,2)
#define SGMII0_FX100_CONTROL2_RESET_RXFIFO_MASK                    0x0004
#define SGMII0_FX100_CONTROL2_RESET_RXFIFO_ALIGN                   0
#define SGMII0_FX100_CONTROL2_RESET_RXFIFO_BITS                    1
#define SGMII0_FX100_CONTROL2_RESET_RXFIFO_SHIFT                   2

/* SGMII0_FX100 :: Control2 :: bypass_rxfifo [01:01] */
#define Wr_SGMII0_FX100_Control2_bypass_rxfifo(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x2,1,x)
#define Rd_SGMII0_FX100_Control2_bypass_rxfifo(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x2,1)
#define SGMII0_FX100_CONTROL2_BYPASS_RXFIFO_MASK                   0x0002
#define SGMII0_FX100_CONTROL2_BYPASS_RXFIFO_ALIGN                  0
#define SGMII0_FX100_CONTROL2_BYPASS_RXFIFO_BITS                   1
#define SGMII0_FX100_CONTROL2_BYPASS_RXFIFO_SHIFT                  1

/* SGMII0_FX100 :: Control2 :: extend_pkt_size [00:00] */
#define Wr_SGMII0_FX100_Control2_extend_pkt_size(x) WriteRegBits16(SGMII0_FX100_CONTROL2,0x1,0,x)
#define Rd_SGMII0_FX100_Control2_extend_pkt_size(x) ReadRegBits16(SGMII0_FX100_CONTROL2,0x1,0)
#define SGMII0_FX100_CONTROL2_EXTEND_PKT_SIZE_MASK                 0x0001
#define SGMII0_FX100_CONTROL2_EXTEND_PKT_SIZE_ALIGN                0
#define SGMII0_FX100_CONTROL2_EXTEND_PKT_SIZE_BITS                 1
#define SGMII0_FX100_CONTROL2_EXTEND_PKT_SIZE_SHIFT                0


/****************************************************************************
 * SGMII0_FX100 :: Control3
 ***************************************************************************/
/* SGMII0_FX100 :: Control3 :: number_of_idle [15:08] */
#define Wr_SGMII0_FX100_Control3_number_of_idle(x) WriteRegBits16(SGMII0_FX100_CONTROL3,0xff00,8,x)
#define Rd_SGMII0_FX100_Control3_number_of_idle(x) ReadRegBits16(SGMII0_FX100_CONTROL3,0xff00,8)
#define SGMII0_FX100_CONTROL3_NUMBER_OF_IDLE_MASK                  0xff00
#define SGMII0_FX100_CONTROL3_NUMBER_OF_IDLE_ALIGN                 0
#define SGMII0_FX100_CONTROL3_NUMBER_OF_IDLE_BITS                  8
#define SGMII0_FX100_CONTROL3_NUMBER_OF_IDLE_SHIFT                 8

/* SGMII0_FX100 :: Control3 :: correlator_disable [07:07] */
#define Wr_SGMII0_FX100_Control3_correlator_disable(x) WriteRegBits16(SGMII0_FX100_CONTROL3,0x80,7,x)
#define Rd_SGMII0_FX100_Control3_correlator_disable(x) ReadRegBits16(SGMII0_FX100_CONTROL3,0x80,7)
#define SGMII0_FX100_CONTROL3_CORRELATOR_DISABLE_MASK              0x0080
#define SGMII0_FX100_CONTROL3_CORRELATOR_DISABLE_ALIGN             0
#define SGMII0_FX100_CONTROL3_CORRELATOR_DISABLE_BITS              1
#define SGMII0_FX100_CONTROL3_CORRELATOR_DISABLE_SHIFT             7

/* SGMII0_FX100 :: Control3 :: bypass_nrz [06:06] */
#define Wr_SGMII0_FX100_Control3_bypass_nrz(x) WriteRegBits16(SGMII0_FX100_CONTROL3,0x40,6,x)
#define Rd_SGMII0_FX100_Control3_bypass_nrz(x) ReadRegBits16(SGMII0_FX100_CONTROL3,0x40,6)
#define SGMII0_FX100_CONTROL3_BYPASS_NRZ_MASK                      0x0040
#define SGMII0_FX100_CONTROL3_BYPASS_NRZ_ALIGN                     0
#define SGMII0_FX100_CONTROL3_BYPASS_NRZ_BITS                      1
#define SGMII0_FX100_CONTROL3_BYPASS_NRZ_SHIFT                     6

/* SGMII0_FX100 :: Control3 :: bypass_encoder [05:05] */
#define Wr_SGMII0_FX100_Control3_bypass_encoder(x) WriteRegBits16(SGMII0_FX100_CONTROL3,0x20,5,x)
#define Rd_SGMII0_FX100_Control3_bypass_encoder(x) ReadRegBits16(SGMII0_FX100_CONTROL3,0x20,5)
#define SGMII0_FX100_CONTROL3_BYPASS_ENCODER_MASK                  0x0020
#define SGMII0_FX100_CONTROL3_BYPASS_ENCODER_ALIGN                 0
#define SGMII0_FX100_CONTROL3_BYPASS_ENCODER_BITS                  1
#define SGMII0_FX100_CONTROL3_BYPASS_ENCODER_SHIFT                 5

/* SGMII0_FX100 :: Control3 :: bypass_alignment [04:04] */
#define Wr_SGMII0_FX100_Control3_bypass_alignment(x) WriteRegBits16(SGMII0_FX100_CONTROL3,0x10,4,x)
#define Rd_SGMII0_FX100_Control3_bypass_alignment(x) ReadRegBits16(SGMII0_FX100_CONTROL3,0x10,4)
#define SGMII0_FX100_CONTROL3_BYPASS_ALIGNMENT_MASK                0x0010
#define SGMII0_FX100_CONTROL3_BYPASS_ALIGNMENT_ALIGN               0
#define SGMII0_FX100_CONTROL3_BYPASS_ALIGNMENT_BITS                1
#define SGMII0_FX100_CONTROL3_BYPASS_ALIGNMENT_SHIFT               4

/* SGMII0_FX100 :: Control3 :: force_link [03:03] */
#define Wr_SGMII0_FX100_Control3_force_link(x) WriteRegBits16(SGMII0_FX100_CONTROL3,0x8,3,x)
#define Rd_SGMII0_FX100_Control3_force_link(x) ReadRegBits16(SGMII0_FX100_CONTROL3,0x8,3)
#define SGMII0_FX100_CONTROL3_FORCE_LINK_MASK                      0x0008
#define SGMII0_FX100_CONTROL3_FORCE_LINK_ALIGN                     0
#define SGMII0_FX100_CONTROL3_FORCE_LINK_BITS                      1
#define SGMII0_FX100_CONTROL3_FORCE_LINK_SHIFT                     3

/* SGMII0_FX100 :: Control3 :: force_lock [02:02] */
#define Wr_SGMII0_FX100_Control3_force_lock(x) WriteRegBits16(SGMII0_FX100_CONTROL3,0x4,2,x)
#define Rd_SGMII0_FX100_Control3_force_lock(x) ReadRegBits16(SGMII0_FX100_CONTROL3,0x4,2)
#define SGMII0_FX100_CONTROL3_FORCE_LOCK_MASK                      0x0004
#define SGMII0_FX100_CONTROL3_FORCE_LOCK_ALIGN                     0
#define SGMII0_FX100_CONTROL3_FORCE_LOCK_BITS                      1
#define SGMII0_FX100_CONTROL3_FORCE_LOCK_SHIFT                     2

/* SGMII0_FX100 :: Control3 :: fast_unlock_timer [01:01] */
#define Wr_SGMII0_FX100_Control3_fast_unlock_timer(x) WriteRegBits16(SGMII0_FX100_CONTROL3,0x2,1,x)
#define Rd_SGMII0_FX100_Control3_fast_unlock_timer(x) ReadRegBits16(SGMII0_FX100_CONTROL3,0x2,1)
#define SGMII0_FX100_CONTROL3_FAST_UNLOCK_TIMER_MASK               0x0002
#define SGMII0_FX100_CONTROL3_FAST_UNLOCK_TIMER_ALIGN              0
#define SGMII0_FX100_CONTROL3_FAST_UNLOCK_TIMER_BITS               1
#define SGMII0_FX100_CONTROL3_FAST_UNLOCK_TIMER_SHIFT              1

/* SGMII0_FX100 :: Control3 :: fast_timers [00:00] */
#define Wr_SGMII0_FX100_Control3_fast_timers(x) WriteRegBits16(SGMII0_FX100_CONTROL3,0x1,0,x)
#define Rd_SGMII0_FX100_Control3_fast_timers(x) ReadRegBits16(SGMII0_FX100_CONTROL3,0x1,0)
#define SGMII0_FX100_CONTROL3_FAST_TIMERS_MASK                     0x0001
#define SGMII0_FX100_CONTROL3_FAST_TIMERS_ALIGN                    0
#define SGMII0_FX100_CONTROL3_FAST_TIMERS_BITS                     1
#define SGMII0_FX100_CONTROL3_FAST_TIMERS_SHIFT                    0


/****************************************************************************
 * SGMII0_FX100 :: Status1
 ***************************************************************************/
/* SGMII0_FX100 :: Status1 :: mode_change [15:15] */
#define Wr_SGMII0_FX100_Status1_mode_change(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x8000,15,x)
#define Rd_SGMII0_FX100_Status1_mode_change(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x8000,15)
#define SGMII0_FX100_STATUS1_MODE_CHANGE_MASK                      0x8000
#define SGMII0_FX100_STATUS1_MODE_CHANGE_ALIGN                     0
#define SGMII0_FX100_STATUS1_MODE_CHANGE_BITS                      1
#define SGMII0_FX100_STATUS1_MODE_CHANGE_SHIFT                     15

/* SGMII0_FX100 :: Status1 :: reserved0 [14:12] */
#define SGMII0_FX100_STATUS1_RESERVED0_MASK                        0x7000
#define SGMII0_FX100_STATUS1_RESERVED0_ALIGN                       0
#define SGMII0_FX100_STATUS1_RESERVED0_BITS                        3
#define SGMII0_FX100_STATUS1_RESERVED0_SHIFT                       12

/* SGMII0_FX100 :: Status1 :: fiber_pwrdwn_status_chg [11:11] */
#define Wr_SGMII0_FX100_Status1_fiber_pwrdwn_status_chg(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x800,11,x)
#define Rd_SGMII0_FX100_Status1_fiber_pwrdwn_status_chg(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x800,11)
#define SGMII0_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_MASK          0x0800
#define SGMII0_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_ALIGN         0
#define SGMII0_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_BITS          1
#define SGMII0_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_SHIFT         11

/* SGMII0_FX100 :: Status1 :: fiber_pwrdwn [10:10] */
#define Wr_SGMII0_FX100_Status1_fiber_pwrdwn(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x400,10,x)
#define Rd_SGMII0_FX100_Status1_fiber_pwrdwn(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x400,10)
#define SGMII0_FX100_STATUS1_FIBER_PWRDWN_MASK                     0x0400
#define SGMII0_FX100_STATUS1_FIBER_PWRDWN_ALIGN                    0
#define SGMII0_FX100_STATUS1_FIBER_PWRDWN_BITS                     1
#define SGMII0_FX100_STATUS1_FIBER_PWRDWN_SHIFT                    10

/* SGMII0_FX100 :: Status1 :: link_status_chg [09:09] */
#define Wr_SGMII0_FX100_Status1_link_status_chg(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x200,9,x)
#define Rd_SGMII0_FX100_Status1_link_status_chg(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x200,9)
#define SGMII0_FX100_STATUS1_LINK_STATUS_CHG_MASK                  0x0200
#define SGMII0_FX100_STATUS1_LINK_STATUS_CHG_ALIGN                 0
#define SGMII0_FX100_STATUS1_LINK_STATUS_CHG_BITS                  1
#define SGMII0_FX100_STATUS1_LINK_STATUS_CHG_SHIFT                 9

/* SGMII0_FX100 :: Status1 :: bad_esd_detected [08:08] */
#define Wr_SGMII0_FX100_Status1_bad_esd_detected(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x100,8,x)
#define Rd_SGMII0_FX100_Status1_bad_esd_detected(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x100,8)
#define SGMII0_FX100_STATUS1_BAD_ESD_DETECTED_MASK                 0x0100
#define SGMII0_FX100_STATUS1_BAD_ESD_DETECTED_ALIGN                0
#define SGMII0_FX100_STATUS1_BAD_ESD_DETECTED_BITS                 1
#define SGMII0_FX100_STATUS1_BAD_ESD_DETECTED_SHIFT                8

/* SGMII0_FX100 :: Status1 :: false_carrier_detected [07:07] */
#define Wr_SGMII0_FX100_Status1_false_carrier_detected(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x80,7,x)
#define Rd_SGMII0_FX100_Status1_false_carrier_detected(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x80,7)
#define SGMII0_FX100_STATUS1_FALSE_CARRIER_DETECTED_MASK           0x0080
#define SGMII0_FX100_STATUS1_FALSE_CARRIER_DETECTED_ALIGN          0
#define SGMII0_FX100_STATUS1_FALSE_CARRIER_DETECTED_BITS           1
#define SGMII0_FX100_STATUS1_FALSE_CARRIER_DETECTED_SHIFT          7

/* SGMII0_FX100 :: Status1 :: tx_err_detected [06:06] */
#define Wr_SGMII0_FX100_Status1_tx_err_detected(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x40,6,x)
#define Rd_SGMII0_FX100_Status1_tx_err_detected(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x40,6)
#define SGMII0_FX100_STATUS1_TX_ERR_DETECTED_MASK                  0x0040
#define SGMII0_FX100_STATUS1_TX_ERR_DETECTED_ALIGN                 0
#define SGMII0_FX100_STATUS1_TX_ERR_DETECTED_BITS                  1
#define SGMII0_FX100_STATUS1_TX_ERR_DETECTED_SHIFT                 6

/* SGMII0_FX100 :: Status1 :: rx_err_detected [05:05] */
#define Wr_SGMII0_FX100_Status1_rx_err_detected(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x20,5,x)
#define Rd_SGMII0_FX100_Status1_rx_err_detected(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x20,5)
#define SGMII0_FX100_STATUS1_RX_ERR_DETECTED_MASK                  0x0020
#define SGMII0_FX100_STATUS1_RX_ERR_DETECTED_ALIGN                 0
#define SGMII0_FX100_STATUS1_RX_ERR_DETECTED_BITS                  1
#define SGMII0_FX100_STATUS1_RX_ERR_DETECTED_SHIFT                 5

/* SGMII0_FX100 :: Status1 :: lock_timer_expired [04:04] */
#define Wr_SGMII0_FX100_Status1_lock_timer_expired(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x10,4,x)
#define Rd_SGMII0_FX100_Status1_lock_timer_expired(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x10,4)
#define SGMII0_FX100_STATUS1_LOCK_TIMER_EXPIRED_MASK               0x0010
#define SGMII0_FX100_STATUS1_LOCK_TIMER_EXPIRED_ALIGN              0
#define SGMII0_FX100_STATUS1_LOCK_TIMER_EXPIRED_BITS               1
#define SGMII0_FX100_STATUS1_LOCK_TIMER_EXPIRED_SHIFT              4

/* SGMII0_FX100 :: Status1 :: lost_lock [03:03] */
#define Wr_SGMII0_FX100_Status1_lost_lock(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x8,3,x)
#define Rd_SGMII0_FX100_Status1_lost_lock(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x8,3)
#define SGMII0_FX100_STATUS1_LOST_LOCK_MASK                        0x0008
#define SGMII0_FX100_STATUS1_LOST_LOCK_ALIGN                       0
#define SGMII0_FX100_STATUS1_LOST_LOCK_BITS                        1
#define SGMII0_FX100_STATUS1_LOST_LOCK_SHIFT                       3

/* SGMII0_FX100 :: Status1 :: faulting [02:02] */
#define Wr_SGMII0_FX100_Status1_faulting(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x4,2,x)
#define Rd_SGMII0_FX100_Status1_faulting(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x4,2)
#define SGMII0_FX100_STATUS1_FAULTING_MASK                         0x0004
#define SGMII0_FX100_STATUS1_FAULTING_ALIGN                        0
#define SGMII0_FX100_STATUS1_FAULTING_BITS                         1
#define SGMII0_FX100_STATUS1_FAULTING_SHIFT                        2

/* SGMII0_FX100 :: Status1 :: locked [01:01] */
#define Wr_SGMII0_FX100_Status1_locked(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x2,1,x)
#define Rd_SGMII0_FX100_Status1_locked(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x2,1)
#define SGMII0_FX100_STATUS1_LOCKED_MASK                           0x0002
#define SGMII0_FX100_STATUS1_LOCKED_ALIGN                          0
#define SGMII0_FX100_STATUS1_LOCKED_BITS                           1
#define SGMII0_FX100_STATUS1_LOCKED_SHIFT                          1

/* SGMII0_FX100 :: Status1 :: link [00:00] */
#define Wr_SGMII0_FX100_Status1_link(x) WriteRegBits16(SGMII0_FX100_STATUS1,0x1,0,x)
#define Rd_SGMII0_FX100_Status1_link(x) ReadRegBits16(SGMII0_FX100_STATUS1,0x1,0)
#define SGMII0_FX100_STATUS1_LINK_MASK                             0x0001
#define SGMII0_FX100_STATUS1_LINK_ALIGN                            0
#define SGMII0_FX100_STATUS1_LINK_BITS                             1
#define SGMII0_FX100_STATUS1_LINK_SHIFT                            0


/****************************************************************************
 * SGMII0_FX100 :: Status3
 ***************************************************************************/
/* SGMII0_FX100 :: Status3 :: linkmon_cntr [15:08] */
#define Wr_SGMII0_FX100_Status3_linkmon_cntr(x) WriteRegBits16(SGMII0_FX100_STATUS3,0xff00,8,x)
#define Rd_SGMII0_FX100_Status3_linkmon_cntr(x) ReadRegBits16(SGMII0_FX100_STATUS3,0xff00,8)
#define SGMII0_FX100_STATUS3_LINKMON_CNTR_MASK                     0xff00
#define SGMII0_FX100_STATUS3_LINKMON_CNTR_ALIGN                    0
#define SGMII0_FX100_STATUS3_LINKMON_CNTR_BITS                     8
#define SGMII0_FX100_STATUS3_LINKMON_CNTR_SHIFT                    8

/* SGMII0_FX100 :: Status3 :: reserved0 [07:07] */
#define SGMII0_FX100_STATUS3_RESERVED0_MASK                        0x0080
#define SGMII0_FX100_STATUS3_RESERVED0_ALIGN                       0
#define SGMII0_FX100_STATUS3_RESERVED0_BITS                        1
#define SGMII0_FX100_STATUS3_RESERVED0_SHIFT                       7

/* SGMII0_FX100 :: Status3 :: idles_detected_5b [06:06] */
#define Wr_SGMII0_FX100_Status3_idles_detected_5b(x) WriteRegBits16(SGMII0_FX100_STATUS3,0x40,6,x)
#define Rd_SGMII0_FX100_Status3_idles_detected_5b(x) ReadRegBits16(SGMII0_FX100_STATUS3,0x40,6)
#define SGMII0_FX100_STATUS3_IDLES_DETECTED_5B_MASK                0x0040
#define SGMII0_FX100_STATUS3_IDLES_DETECTED_5B_ALIGN               0
#define SGMII0_FX100_STATUS3_IDLES_DETECTED_5B_BITS                1
#define SGMII0_FX100_STATUS3_IDLES_DETECTED_5B_SHIFT               6

/* SGMII0_FX100 :: Status3 :: crs_ind_detected [05:05] */
#define Wr_SGMII0_FX100_Status3_crs_ind_detected(x) WriteRegBits16(SGMII0_FX100_STATUS3,0x20,5,x)
#define Rd_SGMII0_FX100_Status3_crs_ind_detected(x) ReadRegBits16(SGMII0_FX100_STATUS3,0x20,5)
#define SGMII0_FX100_STATUS3_CRS_IND_DETECTED_MASK                 0x0020
#define SGMII0_FX100_STATUS3_CRS_IND_DETECTED_ALIGN                0
#define SGMII0_FX100_STATUS3_CRS_IND_DETECTED_BITS                 1
#define SGMII0_FX100_STATUS3_CRS_IND_DETECTED_SHIFT                5

/* SGMII0_FX100 :: Status3 :: err_detected [04:04] */
#define Wr_SGMII0_FX100_Status3_err_detected(x) WriteRegBits16(SGMII0_FX100_STATUS3,0x10,4,x)
#define Rd_SGMII0_FX100_Status3_err_detected(x) ReadRegBits16(SGMII0_FX100_STATUS3,0x10,4)
#define SGMII0_FX100_STATUS3_ERR_DETECTED_MASK                     0x0010
#define SGMII0_FX100_STATUS3_ERR_DETECTED_ALIGN                    0
#define SGMII0_FX100_STATUS3_ERR_DETECTED_BITS                     1
#define SGMII0_FX100_STATUS3_ERR_DETECTED_SHIFT                    4

/* SGMII0_FX100 :: Status3 :: esd_detected [03:03] */
#define Wr_SGMII0_FX100_Status3_esd_detected(x) WriteRegBits16(SGMII0_FX100_STATUS3,0x8,3,x)
#define Rd_SGMII0_FX100_Status3_esd_detected(x) ReadRegBits16(SGMII0_FX100_STATUS3,0x8,3)
#define SGMII0_FX100_STATUS3_ESD_DETECTED_MASK                     0x0008
#define SGMII0_FX100_STATUS3_ESD_DETECTED_ALIGN                    0
#define SGMII0_FX100_STATUS3_ESD_DETECTED_BITS                     1
#define SGMII0_FX100_STATUS3_ESD_DETECTED_SHIFT                    3

/* SGMII0_FX100 :: Status3 :: ssd_detected [02:02] */
#define Wr_SGMII0_FX100_Status3_ssd_detected(x) WriteRegBits16(SGMII0_FX100_STATUS3,0x4,2,x)
#define Rd_SGMII0_FX100_Status3_ssd_detected(x) ReadRegBits16(SGMII0_FX100_STATUS3,0x4,2)
#define SGMII0_FX100_STATUS3_SSD_DETECTED_MASK                     0x0004
#define SGMII0_FX100_STATUS3_SSD_DETECTED_ALIGN                    0
#define SGMII0_FX100_STATUS3_SSD_DETECTED_BITS                     1
#define SGMII0_FX100_STATUS3_SSD_DETECTED_SHIFT                    2

/* SGMII0_FX100 :: Status3 :: ij_detected [01:01] */
#define Wr_SGMII0_FX100_Status3_ij_detected(x) WriteRegBits16(SGMII0_FX100_STATUS3,0x2,1,x)
#define Rd_SGMII0_FX100_Status3_ij_detected(x) ReadRegBits16(SGMII0_FX100_STATUS3,0x2,1)
#define SGMII0_FX100_STATUS3_IJ_DETECTED_MASK                      0x0002
#define SGMII0_FX100_STATUS3_IJ_DETECTED_ALIGN                     0
#define SGMII0_FX100_STATUS3_IJ_DETECTED_BITS                      1
#define SGMII0_FX100_STATUS3_IJ_DETECTED_SHIFT                     1

/* SGMII0_FX100 :: Status3 :: idles_detected [00:00] */
#define Wr_SGMII0_FX100_Status3_idles_detected(x) WriteRegBits16(SGMII0_FX100_STATUS3,0x1,0,x)
#define Rd_SGMII0_FX100_Status3_idles_detected(x) ReadRegBits16(SGMII0_FX100_STATUS3,0x1,0)
#define SGMII0_FX100_STATUS3_IDLES_DETECTED_MASK                   0x0001
#define SGMII0_FX100_STATUS3_IDLES_DETECTED_ALIGN                  0
#define SGMII0_FX100_STATUS3_IDLES_DETECTED_BITS                   1
#define SGMII0_FX100_STATUS3_IDLES_DETECTED_SHIFT                  0


/****************************************************************************
 * SGMII0_FX100 :: Status4
 ***************************************************************************/
/* SGMII0_FX100 :: Status4 :: reserved0 [15:15] */
#define SGMII0_FX100_STATUS4_RESERVED0_MASK                        0x8000
#define SGMII0_FX100_STATUS4_RESERVED0_ALIGN                       0
#define SGMII0_FX100_STATUS4_RESERVED0_BITS                        1
#define SGMII0_FX100_STATUS4_RESERVED0_SHIFT                       15

/* SGMII0_FX100 :: Status4 :: rx_badend [14:14] */
#define Wr_SGMII0_FX100_Status4_rx_badend(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x4000,14,x)
#define Rd_SGMII0_FX100_Status4_rx_badend(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x4000,14)
#define SGMII0_FX100_STATUS4_RX_BADEND_MASK                        0x4000
#define SGMII0_FX100_STATUS4_RX_BADEND_ALIGN                       0
#define SGMII0_FX100_STATUS4_RX_BADEND_BITS                        1
#define SGMII0_FX100_STATUS4_RX_BADEND_SHIFT                       14

/* SGMII0_FX100 :: Status4 :: rx_data [13:13] */
#define Wr_SGMII0_FX100_Status4_rx_data(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x2000,13,x)
#define Rd_SGMII0_FX100_Status4_rx_data(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x2000,13)
#define SGMII0_FX100_STATUS4_RX_DATA_MASK                          0x2000
#define SGMII0_FX100_STATUS4_RX_DATA_ALIGN                         0
#define SGMII0_FX100_STATUS4_RX_DATA_BITS                          1
#define SGMII0_FX100_STATUS4_RX_DATA_SHIFT                         13

/* SGMII0_FX100 :: Status4 :: rx_ssk [12:12] */
#define Wr_SGMII0_FX100_Status4_rx_ssk(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x1000,12,x)
#define Rd_SGMII0_FX100_Status4_rx_ssk(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x1000,12)
#define SGMII0_FX100_STATUS4_RX_SSK_MASK                           0x1000
#define SGMII0_FX100_STATUS4_RX_SSK_ALIGN                          0
#define SGMII0_FX100_STATUS4_RX_SSK_BITS                           1
#define SGMII0_FX100_STATUS4_RX_SSK_SHIFT                          12

/* SGMII0_FX100 :: Status4 :: rx_ssj [11:11] */
#define Wr_SGMII0_FX100_Status4_rx_ssj(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x800,11,x)
#define Rd_SGMII0_FX100_Status4_rx_ssj(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x800,11)
#define SGMII0_FX100_STATUS4_RX_SSJ_MASK                           0x0800
#define SGMII0_FX100_STATUS4_RX_SSJ_ALIGN                          0
#define SGMII0_FX100_STATUS4_RX_SSJ_BITS                           1
#define SGMII0_FX100_STATUS4_RX_SSJ_SHIFT                          11

/* SGMII0_FX100 :: Status4 :: rx_confirmk [10:10] */
#define Wr_SGMII0_FX100_Status4_rx_confirmk(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x400,10,x)
#define Rd_SGMII0_FX100_Status4_rx_confirmk(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x400,10)
#define SGMII0_FX100_STATUS4_RX_CONFIRMK_MASK                      0x0400
#define SGMII0_FX100_STATUS4_RX_CONFIRMK_ALIGN                     0
#define SGMII0_FX100_STATUS4_RX_CONFIRMK_BITS                      1
#define SGMII0_FX100_STATUS4_RX_CONFIRMK_SHIFT                     10

/* SGMII0_FX100 :: Status4 :: rx_badssd [09:09] */
#define Wr_SGMII0_FX100_Status4_rx_badssd(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x200,9,x)
#define Rd_SGMII0_FX100_Status4_rx_badssd(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x200,9)
#define SGMII0_FX100_STATUS4_RX_BADSSD_MASK                        0x0200
#define SGMII0_FX100_STATUS4_RX_BADSSD_ALIGN                       0
#define SGMII0_FX100_STATUS4_RX_BADSSD_BITS                        1
#define SGMII0_FX100_STATUS4_RX_BADSSD_SHIFT                       9

/* SGMII0_FX100 :: Status4 :: fx_linkfail [08:08] */
#define Wr_SGMII0_FX100_Status4_fx_linkfail(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x100,8,x)
#define Rd_SGMII0_FX100_Status4_fx_linkfail(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x100,8)
#define SGMII0_FX100_STATUS4_FX_LINKFAIL_MASK                      0x0100
#define SGMII0_FX100_STATUS4_FX_LINKFAIL_ALIGN                     0
#define SGMII0_FX100_STATUS4_FX_LINKFAIL_BITS                      1
#define SGMII0_FX100_STATUS4_FX_LINKFAIL_SHIFT                     8

/* SGMII0_FX100 :: Status4 :: tx_esr [07:07] */
#define Wr_SGMII0_FX100_Status4_tx_esr(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x80,7,x)
#define Rd_SGMII0_FX100_Status4_tx_esr(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x80,7)
#define SGMII0_FX100_STATUS4_TX_ESR_MASK                           0x0080
#define SGMII0_FX100_STATUS4_TX_ESR_ALIGN                          0
#define SGMII0_FX100_STATUS4_TX_ESR_BITS                           1
#define SGMII0_FX100_STATUS4_TX_ESR_SHIFT                          7

/* SGMII0_FX100 :: Status4 :: tx_est [06:06] */
#define Wr_SGMII0_FX100_Status4_tx_est(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x40,6,x)
#define Rd_SGMII0_FX100_Status4_tx_est(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x40,6)
#define SGMII0_FX100_STATUS4_TX_EST_MASK                           0x0040
#define SGMII0_FX100_STATUS4_TX_EST_ALIGN                          0
#define SGMII0_FX100_STATUS4_TX_EST_BITS                           1
#define SGMII0_FX100_STATUS4_TX_EST_SHIFT                          6

/* SGMII0_FX100 :: Status4 :: tx_terror [05:05] */
#define Wr_SGMII0_FX100_Status4_tx_terror(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x20,5,x)
#define Rd_SGMII0_FX100_Status4_tx_terror(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x20,5)
#define SGMII0_FX100_STATUS4_TX_TERROR_MASK                        0x0020
#define SGMII0_FX100_STATUS4_TX_TERROR_ALIGN                       0
#define SGMII0_FX100_STATUS4_TX_TERROR_BITS                        1
#define SGMII0_FX100_STATUS4_TX_TERROR_SHIFT                       5

/* SGMII0_FX100 :: Status4 :: tx_tdata [04:04] */
#define Wr_SGMII0_FX100_Status4_tx_tdata(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x10,4,x)
#define Rd_SGMII0_FX100_Status4_tx_tdata(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x10,4)
#define SGMII0_FX100_STATUS4_TX_TDATA_MASK                         0x0010
#define SGMII0_FX100_STATUS4_TX_TDATA_ALIGN                        0
#define SGMII0_FX100_STATUS4_TX_TDATA_BITS                         1
#define SGMII0_FX100_STATUS4_TX_TDATA_SHIFT                        4

/* SGMII0_FX100 :: Status4 :: tx_ssk [03:03] */
#define Wr_SGMII0_FX100_Status4_tx_ssk(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x8,3,x)
#define Rd_SGMII0_FX100_Status4_tx_ssk(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x8,3)
#define SGMII0_FX100_STATUS4_TX_SSK_MASK                           0x0008
#define SGMII0_FX100_STATUS4_TX_SSK_ALIGN                          0
#define SGMII0_FX100_STATUS4_TX_SSK_BITS                           1
#define SGMII0_FX100_STATUS4_TX_SSK_SHIFT                          3

/* SGMII0_FX100 :: Status4 :: tx_sek [02:02] */
#define Wr_SGMII0_FX100_Status4_tx_sek(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x4,2,x)
#define Rd_SGMII0_FX100_Status4_tx_sek(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x4,2)
#define SGMII0_FX100_STATUS4_TX_SEK_MASK                           0x0004
#define SGMII0_FX100_STATUS4_TX_SEK_ALIGN                          0
#define SGMII0_FX100_STATUS4_TX_SEK_BITS                           1
#define SGMII0_FX100_STATUS4_TX_SEK_SHIFT                          2

/* SGMII0_FX100 :: Status4 :: tx_ssj [01:01] */
#define Wr_SGMII0_FX100_Status4_tx_ssj(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x2,1,x)
#define Rd_SGMII0_FX100_Status4_tx_ssj(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x2,1)
#define SGMII0_FX100_STATUS4_TX_SSJ_MASK                           0x0002
#define SGMII0_FX100_STATUS4_TX_SSJ_ALIGN                          0
#define SGMII0_FX100_STATUS4_TX_SSJ_BITS                           1
#define SGMII0_FX100_STATUS4_TX_SSJ_SHIFT                          1

/* SGMII0_FX100 :: Status4 :: tx_sej [00:00] */
#define Wr_SGMII0_FX100_Status4_tx_sej(x) WriteRegBits16(SGMII0_FX100_STATUS4,0x1,0,x)
#define Rd_SGMII0_FX100_Status4_tx_sej(x) ReadRegBits16(SGMII0_FX100_STATUS4,0x1,0)
#define SGMII0_FX100_STATUS4_TX_SEJ_MASK                           0x0001
#define SGMII0_FX100_STATUS4_TX_SEJ_ALIGN                          0
#define SGMII0_FX100_STATUS4_TX_SEJ_BITS                           1
#define SGMII0_FX100_STATUS4_TX_SEJ_SHIFT                          0


/****************************************************************************
 * SGMII0_FX100 :: fx100Idle1
 ***************************************************************************/
/* SGMII0_FX100 :: fx100Idle1 :: reserved0 [15:10] */
#define SGMII0_FX100_FX100IDLE1_RESERVED0_MASK                     0xfc00
#define SGMII0_FX100_FX100IDLE1_RESERVED0_ALIGN                    0
#define SGMII0_FX100_FX100IDLE1_RESERVED0_BITS                     6
#define SGMII0_FX100_FX100IDLE1_RESERVED0_SHIFT                    10

/* SGMII0_FX100 :: fx100Idle1 :: fx100_idle1 [09:00] */
#define Wr_SGMII0_FX100_fx100Idle1_fx100_idle1(x) WriteRegBits16(SGMII0_FX100_FX100IDLE1,0x3ff,0,x)
#define Rd_SGMII0_FX100_fx100Idle1_fx100_idle1(x) ReadRegBits16(SGMII0_FX100_FX100IDLE1,0x3ff,0)
#define SGMII0_FX100_FX100IDLE1_FX100_IDLE1_MASK                   0x03ff
#define SGMII0_FX100_FX100IDLE1_FX100_IDLE1_ALIGN                  0
#define SGMII0_FX100_FX100IDLE1_FX100_IDLE1_BITS                   10
#define SGMII0_FX100_FX100IDLE1_FX100_IDLE1_SHIFT                  0


/****************************************************************************
 * SGMII0_FX100 :: fx100idle2
 ***************************************************************************/
/* SGMII0_FX100 :: fx100idle2 :: reserved0 [15:10] */
#define SGMII0_FX100_FX100IDLE2_RESERVED0_MASK                     0xfc00
#define SGMII0_FX100_FX100IDLE2_RESERVED0_ALIGN                    0
#define SGMII0_FX100_FX100IDLE2_RESERVED0_BITS                     6
#define SGMII0_FX100_FX100IDLE2_RESERVED0_SHIFT                    10

/* SGMII0_FX100 :: fx100idle2 :: fx100_idle2 [09:00] */
#define Wr_SGMII0_FX100_fx100idle2_fx100_idle2(x) WriteRegBits16(SGMII0_FX100_FX100IDLE2,0x3ff,0,x)
#define Rd_SGMII0_FX100_fx100idle2_fx100_idle2(x) ReadRegBits16(SGMII0_FX100_FX100IDLE2,0x3ff,0)
#define SGMII0_FX100_FX100IDLE2_FX100_IDLE2_MASK                   0x03ff
#define SGMII0_FX100_FX100IDLE2_FX100_IDLE2_ALIGN                  0
#define SGMII0_FX100_FX100IDLE2_FX100_IDLE2_BITS                   10
#define SGMII0_FX100_FX100IDLE2_FX100_IDLE2_SHIFT                  0


/****************************************************************************
 * SGMII0_FX100 :: fx100IdleStatus
 ***************************************************************************/
/* SGMII0_FX100 :: fx100IdleStatus :: reserved0 [15:07] */
#define SGMII0_FX100_FX100IDLESTATUS_RESERVED0_MASK                0xff80
#define SGMII0_FX100_FX100IDLESTATUS_RESERVED0_ALIGN               0
#define SGMII0_FX100_FX100IDLESTATUS_RESERVED0_BITS                9
#define SGMII0_FX100_FX100IDLESTATUS_RESERVED0_SHIFT               7

/* SGMII0_FX100 :: fx100IdleStatus :: fx100_idleCorr_cnt [06:00] */
#define Wr_SGMII0_FX100_fx100IdleStatus_fx100_idleCorr_cnt(x) WriteRegBits16(SGMII0_FX100_FX100IDLESTATUS,0x7f,0,x)
#define Rd_SGMII0_FX100_fx100IdleStatus_fx100_idleCorr_cnt(x) ReadRegBits16(SGMII0_FX100_FX100IDLESTATUS,0x7f,0)
#define SGMII0_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_MASK       0x007f
#define SGMII0_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_ALIGN      0
#define SGMII0_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_BITS       7
#define SGMII0_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_SHIFT      0


/****************************************************************************
 * SGMII0_FX100 :: fx100IdleThres
 ***************************************************************************/
/* SGMII0_FX100 :: fx100IdleThres :: reserved0 [15:14] */
#define SGMII0_FX100_FX100IDLETHRES_RESERVED0_MASK                 0xc000
#define SGMII0_FX100_FX100IDLETHRES_RESERVED0_ALIGN                0
#define SGMII0_FX100_FX100IDLETHRES_RESERVED0_BITS                 2
#define SGMII0_FX100_FX100IDLETHRES_RESERVED0_SHIFT                14

/* SGMII0_FX100 :: fx100IdleThres :: fx100_idle_min_thres [13:07] */
#define Wr_SGMII0_FX100_fx100IdleThres_fx100_idle_min_thres(x) WriteRegBits16(SGMII0_FX100_FX100IDLETHRES,0x3f80,7,x)
#define Rd_SGMII0_FX100_fx100IdleThres_fx100_idle_min_thres(x) ReadRegBits16(SGMII0_FX100_FX100IDLETHRES,0x3f80,7)
#define SGMII0_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_MASK      0x3f80
#define SGMII0_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_ALIGN     0
#define SGMII0_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_BITS      7
#define SGMII0_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_SHIFT     7

/* SGMII0_FX100 :: fx100IdleThres :: fx100_idle_max_thres [06:00] */
#define Wr_SGMII0_FX100_fx100IdleThres_fx100_idle_max_thres(x) WriteRegBits16(SGMII0_FX100_FX100IDLETHRES,0x7f,0,x)
#define Rd_SGMII0_FX100_fx100IdleThres_fx100_idle_max_thres(x) ReadRegBits16(SGMII0_FX100_FX100IDLETHRES,0x7f,0)
#define SGMII0_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_MASK      0x007f
#define SGMII0_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_ALIGN     0
#define SGMII0_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_BITS      7
#define SGMII0_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_SHIFT     0


/****************************************************************************
 * SGMII0_FX100 :: fx100LockTmr
 ***************************************************************************/
/* SGMII0_FX100 :: fx100LockTmr :: fx100_lock_thres [15:12] */
#define Wr_SGMII0_FX100_fx100LockTmr_fx100_lock_thres(x) WriteRegBits16(SGMII0_FX100_FX100LOCKTMR,0xf000,12,x)
#define Rd_SGMII0_FX100_fx100LockTmr_fx100_lock_thres(x) ReadRegBits16(SGMII0_FX100_FX100LOCKTMR,0xf000,12)
#define SGMII0_FX100_FX100LOCKTMR_FX100_LOCK_THRES_MASK            0xf000
#define SGMII0_FX100_FX100LOCKTMR_FX100_LOCK_THRES_ALIGN           0
#define SGMII0_FX100_FX100LOCKTMR_FX100_LOCK_THRES_BITS            4
#define SGMII0_FX100_FX100LOCKTMR_FX100_LOCK_THRES_SHIFT           12

/* SGMII0_FX100 :: fx100LockTmr :: fx100_unlock_thres [11:08] */
#define Wr_SGMII0_FX100_fx100LockTmr_fx100_unlock_thres(x) WriteRegBits16(SGMII0_FX100_FX100LOCKTMR,0xf00,8,x)
#define Rd_SGMII0_FX100_fx100LockTmr_fx100_unlock_thres(x) ReadRegBits16(SGMII0_FX100_FX100LOCKTMR,0xf00,8)
#define SGMII0_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_MASK          0x0f00
#define SGMII0_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_ALIGN         0
#define SGMII0_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_BITS          4
#define SGMII0_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_SHIFT         8

/* SGMII0_FX100 :: fx100LockTmr :: fx100_lock_maxtime [07:00] */
#define Wr_SGMII0_FX100_fx100LockTmr_fx100_lock_maxtime(x) WriteRegBits16(SGMII0_FX100_FX100LOCKTMR,0xff,0,x)
#define Rd_SGMII0_FX100_fx100LockTmr_fx100_lock_maxtime(x) ReadRegBits16(SGMII0_FX100_FX100LOCKTMR,0xff,0)
#define SGMII0_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_MASK          0x00ff
#define SGMII0_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_ALIGN         0
#define SGMII0_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_BITS          8
#define SGMII0_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_SHIFT         0


/****************************************************************************
 * SGMII0_FX100 :: fx100LinkTmr
 ***************************************************************************/
/* SGMII0_FX100 :: fx100LinkTmr :: fx100_linkup_count [15:08] */
#define Wr_SGMII0_FX100_fx100LinkTmr_fx100_linkup_count(x) WriteRegBits16(SGMII0_FX100_FX100LINKTMR,0xff00,8,x)
#define Rd_SGMII0_FX100_fx100LinkTmr_fx100_linkup_count(x) ReadRegBits16(SGMII0_FX100_FX100LINKTMR,0xff00,8)
#define SGMII0_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_MASK          0xff00
#define SGMII0_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_ALIGN         0
#define SGMII0_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_BITS          8
#define SGMII0_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_SHIFT         8

/* SGMII0_FX100 :: fx100LinkTmr :: fx100_linkdn_count [07:00] */
#define Wr_SGMII0_FX100_fx100LinkTmr_fx100_linkdn_count(x) WriteRegBits16(SGMII0_FX100_FX100LINKTMR,0xff,0,x)
#define Rd_SGMII0_FX100_fx100LinkTmr_fx100_linkdn_count(x) ReadRegBits16(SGMII0_FX100_FX100LINKTMR,0xff,0)
#define SGMII0_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_MASK          0x00ff
#define SGMII0_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_ALIGN         0
#define SGMII0_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_BITS          8
#define SGMII0_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_SHIFT         0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_RX2
 ***************************************************************************/
/****************************************************************************
 * SGMII0_RX2 :: rxseq0
 ***************************************************************************/
/* SGMII0_RX2 :: rxseq0 :: cdrLockTimeTrckNrml_SM [15:08] */
#define Wr_SGMII0_RX2_rxseq0_cdrLockTimeTrckNrml_SM(x) WriteRegBits16(SGMII0_RX2_RXSEQ0,0xff00,8,x)
#define Rd_SGMII0_RX2_rxseq0_cdrLockTimeTrckNrml_SM(x) ReadRegBits16(SGMII0_RX2_RXSEQ0,0xff00,8)
#define SGMII0_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_MASK              0xff00
#define SGMII0_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_ALIGN             0
#define SGMII0_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_BITS              8
#define SGMII0_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_SHIFT             8

/* SGMII0_RX2 :: rxseq0 :: cdrLockTimeAcq_S1_SM [07:00] */
#define Wr_SGMII0_RX2_rxseq0_cdrLockTimeAcq_S1_SM(x) WriteRegBits16(SGMII0_RX2_RXSEQ0,0xff,0,x)
#define Rd_SGMII0_RX2_rxseq0_cdrLockTimeAcq_S1_SM(x) ReadRegBits16(SGMII0_RX2_RXSEQ0,0xff,0)
#define SGMII0_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_MASK                0x00ff
#define SGMII0_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_ALIGN               0
#define SGMII0_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_BITS                8
#define SGMII0_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_SHIFT               0


/****************************************************************************
 * SGMII0_RX2 :: rxseq1
 ***************************************************************************/
/* SGMII0_RX2 :: rxseq1 :: cdrLockTimeAcq_S2_SM [15:08] */
#define Wr_SGMII0_RX2_rxseq1_cdrLockTimeAcq_S2_SM(x) WriteRegBits16(SGMII0_RX2_RXSEQ1,0xff00,8,x)
#define Rd_SGMII0_RX2_rxseq1_cdrLockTimeAcq_S2_SM(x) ReadRegBits16(SGMII0_RX2_RXSEQ1,0xff00,8)
#define SGMII0_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_MASK                0xff00
#define SGMII0_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_ALIGN               0
#define SGMII0_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_BITS                8
#define SGMII0_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_SHIFT               8

/* SGMII0_RX2 :: rxseq1 :: cdrLockTimeAcq_S3_SM [07:00] */
#define Wr_SGMII0_RX2_rxseq1_cdrLockTimeAcq_S3_SM(x) WriteRegBits16(SGMII0_RX2_RXSEQ1,0xff,0,x)
#define Rd_SGMII0_RX2_rxseq1_cdrLockTimeAcq_S3_SM(x) ReadRegBits16(SGMII0_RX2_RXSEQ1,0xff,0)
#define SGMII0_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_MASK                0x00ff
#define SGMII0_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_ALIGN               0
#define SGMII0_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_BITS                8
#define SGMII0_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_SHIFT               0


/****************************************************************************
 * SGMII0_RX2 :: rxcdr0
 ***************************************************************************/
/* SGMII0_RX2 :: rxcdr0 :: sigdetTime_SM [15:12] */
#define Wr_SGMII0_RX2_rxcdr0_sigdetTime_SM(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0xf000,12,x)
#define Rd_SGMII0_RX2_rxcdr0_sigdetTime_SM(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0xf000,12)
#define SGMII0_RX2_RXCDR0_SIGDETTIME_SM_MASK                       0xf000
#define SGMII0_RX2_RXCDR0_SIGDETTIME_SM_ALIGN                      0
#define SGMII0_RX2_RXCDR0_SIGDETTIME_SM_BITS                       4
#define SGMII0_RX2_RXCDR0_SIGDETTIME_SM_SHIFT                      12

/* SGMII0_RX2 :: rxcdr0 :: em_phase_shift_360_ovrd_val [11:11] */
#define Wr_SGMII0_RX2_rxcdr0_em_phase_shift_360_ovrd_val(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x800,11,x)
#define Rd_SGMII0_RX2_rxcdr0_em_phase_shift_360_ovrd_val(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x800,11)
#define SGMII0_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_MASK         0x0800
#define SGMII0_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_ALIGN        0
#define SGMII0_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_BITS         1
#define SGMII0_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_SHIFT        11

/* SGMII0_RX2 :: rxcdr0 :: em_phase_shift_360_ovrd [10:10] */
#define Wr_SGMII0_RX2_rxcdr0_em_phase_shift_360_ovrd(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x400,10,x)
#define Rd_SGMII0_RX2_rxcdr0_em_phase_shift_360_ovrd(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x400,10)
#define SGMII0_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_MASK             0x0400
#define SGMII0_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_ALIGN            0
#define SGMII0_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_BITS             1
#define SGMII0_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_SHIFT            10

/* SGMII0_RX2 :: rxcdr0 :: rx_interp_ctrl_cap [09:09] */
#define Wr_SGMII0_RX2_rxcdr0_rx_interp_ctrl_cap(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x200,9,x)
#define Rd_SGMII0_RX2_rxcdr0_rx_interp_ctrl_cap(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x200,9)
#define SGMII0_RX2_RXCDR0_RX_INTERP_CTRL_CAP_MASK                  0x0200
#define SGMII0_RX2_RXCDR0_RX_INTERP_CTRL_CAP_ALIGN                 0
#define SGMII0_RX2_RXCDR0_RX_INTERP_CTRL_CAP_BITS                  1
#define SGMII0_RX2_RXCDR0_RX_INTERP_CTRL_CAP_SHIFT                 9

/* SGMII0_RX2 :: rxcdr0 :: rx_interp_status_sel [08:06] */
#define Wr_SGMII0_RX2_rxcdr0_rx_interp_status_sel(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x1c0,6,x)
#define Rd_SGMII0_RX2_rxcdr0_rx_interp_status_sel(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x1c0,6)
#define SGMII0_RX2_RXCDR0_RX_INTERP_STATUS_SEL_MASK                0x01c0
#define SGMII0_RX2_RXCDR0_RX_INTERP_STATUS_SEL_ALIGN               0
#define SGMII0_RX2_RXCDR0_RX_INTERP_STATUS_SEL_BITS                3
#define SGMII0_RX2_RXCDR0_RX_INTERP_STATUS_SEL_SHIFT               6

/* SGMII0_RX2 :: rxcdr0 :: pi_clk90_offset_override [05:05] */
#define Wr_SGMII0_RX2_rxcdr0_pi_clk90_offset_override(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x20,5,x)
#define Rd_SGMII0_RX2_rxcdr0_pi_clk90_offset_override(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x20,5)
#define SGMII0_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_MASK            0x0020
#define SGMII0_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_ALIGN           0
#define SGMII0_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_BITS            1
#define SGMII0_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_SHIFT           5

/* SGMII0_RX2 :: rxcdr0 :: pi_phase_rotate_override [04:04] */
#define Wr_SGMII0_RX2_rxcdr0_pi_phase_rotate_override(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x10,4,x)
#define Rd_SGMII0_RX2_rxcdr0_pi_phase_rotate_override(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x10,4)
#define SGMII0_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_MASK            0x0010
#define SGMII0_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_ALIGN           0
#define SGMII0_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_BITS            1
#define SGMII0_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_SHIFT           4

/* SGMII0_RX2 :: rxcdr0 :: mdio_em_err_cnt_clr [03:03] */
#define Wr_SGMII0_RX2_rxcdr0_mdio_em_err_cnt_clr(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x8,3,x)
#define Rd_SGMII0_RX2_rxcdr0_mdio_em_err_cnt_clr(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x8,3)
#define SGMII0_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_MASK                 0x0008
#define SGMII0_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_ALIGN                0
#define SGMII0_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_BITS                 1
#define SGMII0_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_SHIFT                3

/* SGMII0_RX2 :: rxcdr0 :: mdio_em_err_cnt_frz [02:02] */
#define Wr_SGMII0_RX2_rxcdr0_mdio_em_err_cnt_frz(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x4,2,x)
#define Rd_SGMII0_RX2_rxcdr0_mdio_em_err_cnt_frz(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x4,2)
#define SGMII0_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_MASK                 0x0004
#define SGMII0_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_ALIGN                0
#define SGMII0_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_BITS                 1
#define SGMII0_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_SHIFT                2

/* SGMII0_RX2 :: rxcdr0 :: mdio_em_pwrdn [01:01] */
#define Wr_SGMII0_RX2_rxcdr0_mdio_em_pwrdn(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x2,1,x)
#define Rd_SGMII0_RX2_rxcdr0_mdio_em_pwrdn(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x2,1)
#define SGMII0_RX2_RXCDR0_MDIO_EM_PWRDN_MASK                       0x0002
#define SGMII0_RX2_RXCDR0_MDIO_EM_PWRDN_ALIGN                      0
#define SGMII0_RX2_RXCDR0_MDIO_EM_PWRDN_BITS                       1
#define SGMII0_RX2_RXCDR0_MDIO_EM_PWRDN_SHIFT                      1

/* SGMII0_RX2 :: rxcdr0 :: pi_phase_invert [00:00] */
#define Wr_SGMII0_RX2_rxcdr0_pi_phase_invert(x) WriteRegBits16(SGMII0_RX2_RXCDR0,0x1,0,x)
#define Rd_SGMII0_RX2_rxcdr0_pi_phase_invert(x) ReadRegBits16(SGMII0_RX2_RXCDR0,0x1,0)
#define SGMII0_RX2_RXCDR0_PI_PHASE_INVERT_MASK                     0x0001
#define SGMII0_RX2_RXCDR0_PI_PHASE_INVERT_ALIGN                    0
#define SGMII0_RX2_RXCDR0_PI_PHASE_INVERT_BITS                     1
#define SGMII0_RX2_RXCDR0_PI_PHASE_INVERT_SHIFT                    0


/****************************************************************************
 * SGMII0_RX2 :: rxcdr1
 ***************************************************************************/
/* SGMII0_RX2 :: rxcdr1 :: reserved0 [15:13] */
#define SGMII0_RX2_RXCDR1_RESERVED0_MASK                           0xe000
#define SGMII0_RX2_RXCDR1_RESERVED0_ALIGN                          0
#define SGMII0_RX2_RXCDR1_RESERVED0_BITS                           3
#define SGMII0_RX2_RXCDR1_RESERVED0_SHIFT                          13

/* SGMII0_RX2 :: rxcdr1 :: step_two [12:11] */
#define Wr_SGMII0_RX2_rxcdr1_step_two(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x1800,11,x)
#define Rd_SGMII0_RX2_rxcdr1_step_two(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x1800,11)
#define SGMII0_RX2_RXCDR1_STEP_TWO_MASK                            0x1800
#define SGMII0_RX2_RXCDR1_STEP_TWO_ALIGN                           0
#define SGMII0_RX2_RXCDR1_STEP_TWO_BITS                            2
#define SGMII0_RX2_RXCDR1_STEP_TWO_SHIFT                           11

/* SGMII0_RX2 :: rxcdr1 :: step_one [10:09] */
#define Wr_SGMII0_RX2_rxcdr1_step_one(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x600,9,x)
#define Rd_SGMII0_RX2_rxcdr1_step_one(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x600,9)
#define SGMII0_RX2_RXCDR1_STEP_ONE_MASK                            0x0600
#define SGMII0_RX2_RXCDR1_STEP_ONE_ALIGN                           0
#define SGMII0_RX2_RXCDR1_STEP_ONE_BITS                            2
#define SGMII0_RX2_RXCDR1_STEP_ONE_SHIFT                           9

/* SGMII0_RX2 :: rxcdr1 :: flip_zero_polarity [08:08] */
#define Wr_SGMII0_RX2_rxcdr1_flip_zero_polarity(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x100,8,x)
#define Rd_SGMII0_RX2_rxcdr1_flip_zero_polarity(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x100,8)
#define SGMII0_RX2_RXCDR1_FLIP_ZERO_POLARITY_MASK                  0x0100
#define SGMII0_RX2_RXCDR1_FLIP_ZERO_POLARITY_ALIGN                 0
#define SGMII0_RX2_RXCDR1_FLIP_ZERO_POLARITY_BITS                  1
#define SGMII0_RX2_RXCDR1_FLIP_ZERO_POLARITY_SHIFT                 8

/* SGMII0_RX2 :: rxcdr1 :: flip_peak_polarity [07:07] */
#define Wr_SGMII0_RX2_rxcdr1_flip_peak_polarity(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x80,7,x)
#define Rd_SGMII0_RX2_rxcdr1_flip_peak_polarity(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x80,7)
#define SGMII0_RX2_RXCDR1_FLIP_PEAK_POLARITY_MASK                  0x0080
#define SGMII0_RX2_RXCDR1_FLIP_PEAK_POLARITY_ALIGN                 0
#define SGMII0_RX2_RXCDR1_FLIP_PEAK_POLARITY_BITS                  1
#define SGMII0_RX2_RXCDR1_FLIP_PEAK_POLARITY_SHIFT                 7

/* SGMII0_RX2 :: rxcdr1 :: rising_edge [06:06] */
#define Wr_SGMII0_RX2_rxcdr1_rising_edge(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x40,6,x)
#define Rd_SGMII0_RX2_rxcdr1_rising_edge(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x40,6)
#define SGMII0_RX2_RXCDR1_RISING_EDGE_MASK                         0x0040
#define SGMII0_RX2_RXCDR1_RISING_EDGE_ALIGN                        0
#define SGMII0_RX2_RXCDR1_RISING_EDGE_BITS                         1
#define SGMII0_RX2_RXCDR1_RISING_EDGE_SHIFT                        6

/* SGMII0_RX2 :: rxcdr1 :: falling_edge [05:05] */
#define Wr_SGMII0_RX2_rxcdr1_falling_edge(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x20,5,x)
#define Rd_SGMII0_RX2_rxcdr1_falling_edge(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x20,5)
#define SGMII0_RX2_RXCDR1_FALLING_EDGE_MASK                        0x0020
#define SGMII0_RX2_RXCDR1_FALLING_EDGE_ALIGN                       0
#define SGMII0_RX2_RXCDR1_FALLING_EDGE_BITS                        1
#define SGMII0_RX2_RXCDR1_FALLING_EDGE_SHIFT                       5

/* SGMII0_RX2 :: rxcdr1 :: freq_upd_en [04:04] */
#define Wr_SGMII0_RX2_rxcdr1_freq_upd_en(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x10,4,x)
#define Rd_SGMII0_RX2_rxcdr1_freq_upd_en(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x10,4)
#define SGMII0_RX2_RXCDR1_FREQ_UPD_EN_MASK                         0x0010
#define SGMII0_RX2_RXCDR1_FREQ_UPD_EN_ALIGN                        0
#define SGMII0_RX2_RXCDR1_FREQ_UPD_EN_BITS                         1
#define SGMII0_RX2_RXCDR1_FREQ_UPD_EN_SHIFT                        4

/* SGMII0_RX2 :: rxcdr1 :: phase_delta [03:03] */
#define Wr_SGMII0_RX2_rxcdr1_phase_delta(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x8,3,x)
#define Rd_SGMII0_RX2_rxcdr1_phase_delta(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x8,3)
#define SGMII0_RX2_RXCDR1_PHASE_DELTA_MASK                         0x0008
#define SGMII0_RX2_RXCDR1_PHASE_DELTA_ALIGN                        0
#define SGMII0_RX2_RXCDR1_PHASE_DELTA_BITS                         1
#define SGMII0_RX2_RXCDR1_PHASE_DELTA_SHIFT                        3

/* SGMII0_RX2 :: rxcdr1 :: phs_counter_clr [02:02] */
#define Wr_SGMII0_RX2_rxcdr1_phs_counter_clr(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x4,2,x)
#define Rd_SGMII0_RX2_rxcdr1_phs_counter_clr(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x4,2)
#define SGMII0_RX2_RXCDR1_PHS_COUNTER_CLR_MASK                     0x0004
#define SGMII0_RX2_RXCDR1_PHS_COUNTER_CLR_ALIGN                    0
#define SGMII0_RX2_RXCDR1_PHS_COUNTER_CLR_BITS                     1
#define SGMII0_RX2_RXCDR1_PHS_COUNTER_CLR_SHIFT                    2

/* SGMII0_RX2 :: rxcdr1 :: phase_sat_ctrl [01:00] */
#define Wr_SGMII0_RX2_rxcdr1_phase_sat_ctrl(x) WriteRegBits16(SGMII0_RX2_RXCDR1,0x3,0,x)
#define Rd_SGMII0_RX2_rxcdr1_phase_sat_ctrl(x) ReadRegBits16(SGMII0_RX2_RXCDR1,0x3,0)
#define SGMII0_RX2_RXCDR1_PHASE_SAT_CTRL_MASK                      0x0003
#define SGMII0_RX2_RXCDR1_PHASE_SAT_CTRL_ALIGN                     0
#define SGMII0_RX2_RXCDR1_PHASE_SAT_CTRL_BITS                      2
#define SGMII0_RX2_RXCDR1_PHASE_SAT_CTRL_SHIFT                     0


/****************************************************************************
 * SGMII0_RX2 :: rxcdr2
 ***************************************************************************/
/* SGMII0_RX2 :: rxcdr2 :: reserved0 [15:14] */
#define SGMII0_RX2_RXCDR2_RESERVED0_MASK                           0xc000
#define SGMII0_RX2_RXCDR2_RESERVED0_ALIGN                          0
#define SGMII0_RX2_RXCDR2_RESERVED0_BITS                           2
#define SGMII0_RX2_RXCDR2_RESERVED0_SHIFT                          14

/* SGMII0_RX2 :: rxcdr2 :: phsacq_enable [13:13] */
#define Wr_SGMII0_RX2_rxcdr2_phsacq_enable(x) WriteRegBits16(SGMII0_RX2_RXCDR2,0x2000,13,x)
#define Rd_SGMII0_RX2_rxcdr2_phsacq_enable(x) ReadRegBits16(SGMII0_RX2_RXCDR2,0x2000,13)
#define SGMII0_RX2_RXCDR2_PHSACQ_ENABLE_MASK                       0x2000
#define SGMII0_RX2_RXCDR2_PHSACQ_ENABLE_ALIGN                      0
#define SGMII0_RX2_RXCDR2_PHSACQ_ENABLE_BITS                       1
#define SGMII0_RX2_RXCDR2_PHSACQ_ENABLE_SHIFT                      13

/* SGMII0_RX2 :: rxcdr2 :: rate_select [12:12] */
#define Wr_SGMII0_RX2_rxcdr2_rate_select(x) WriteRegBits16(SGMII0_RX2_RXCDR2,0x1000,12,x)
#define Rd_SGMII0_RX2_rxcdr2_rate_select(x) ReadRegBits16(SGMII0_RX2_RXCDR2,0x1000,12)
#define SGMII0_RX2_RXCDR2_RATE_SELECT_MASK                         0x1000
#define SGMII0_RX2_RXCDR2_RATE_SELECT_ALIGN                        0
#define SGMII0_RX2_RXCDR2_RATE_SELECT_BITS                         1
#define SGMII0_RX2_RXCDR2_RATE_SELECT_SHIFT                        12

/* SGMII0_RX2 :: rxcdr2 :: phsacq_dir [11:11] */
#define Wr_SGMII0_RX2_rxcdr2_phsacq_dir(x) WriteRegBits16(SGMII0_RX2_RXCDR2,0x800,11,x)
#define Rd_SGMII0_RX2_rxcdr2_phsacq_dir(x) ReadRegBits16(SGMII0_RX2_RXCDR2,0x800,11)
#define SGMII0_RX2_RXCDR2_PHSACQ_DIR_MASK                          0x0800
#define SGMII0_RX2_RXCDR2_PHSACQ_DIR_ALIGN                         0
#define SGMII0_RX2_RXCDR2_PHSACQ_DIR_BITS                          1
#define SGMII0_RX2_RXCDR2_PHSACQ_DIR_SHIFT                         11

/* SGMII0_RX2 :: rxcdr2 :: reserved1 [10:10] */
#define SGMII0_RX2_RXCDR2_RESERVED1_MASK                           0x0400
#define SGMII0_RX2_RXCDR2_RESERVED1_ALIGN                          0
#define SGMII0_RX2_RXCDR2_RESERVED1_BITS                           1
#define SGMII0_RX2_RXCDR2_RESERVED1_SHIFT                          10

/* SGMII0_RX2 :: rxcdr2 :: phsacq_freq_sel [09:09] */
#define Wr_SGMII0_RX2_rxcdr2_phsacq_freq_sel(x) WriteRegBits16(SGMII0_RX2_RXCDR2,0x200,9,x)
#define Rd_SGMII0_RX2_rxcdr2_phsacq_freq_sel(x) ReadRegBits16(SGMII0_RX2_RXCDR2,0x200,9)
#define SGMII0_RX2_RXCDR2_PHSACQ_FREQ_SEL_MASK                     0x0200
#define SGMII0_RX2_RXCDR2_PHSACQ_FREQ_SEL_ALIGN                    0
#define SGMII0_RX2_RXCDR2_PHSACQ_FREQ_SEL_BITS                     1
#define SGMII0_RX2_RXCDR2_PHSACQ_FREQ_SEL_SHIFT                    9

/* SGMII0_RX2 :: rxcdr2 :: phsacq_step [08:08] */
#define Wr_SGMII0_RX2_rxcdr2_phsacq_step(x) WriteRegBits16(SGMII0_RX2_RXCDR2,0x100,8,x)
#define Rd_SGMII0_RX2_rxcdr2_phsacq_step(x) ReadRegBits16(SGMII0_RX2_RXCDR2,0x100,8)
#define SGMII0_RX2_RXCDR2_PHSACQ_STEP_MASK                         0x0100
#define SGMII0_RX2_RXCDR2_PHSACQ_STEP_ALIGN                        0
#define SGMII0_RX2_RXCDR2_PHSACQ_STEP_BITS                         1
#define SGMII0_RX2_RXCDR2_PHSACQ_STEP_SHIFT                        8

/* SGMII0_RX2 :: rxcdr2 :: phsacq_timeout [07:00] */
#define Wr_SGMII0_RX2_rxcdr2_phsacq_timeout(x) WriteRegBits16(SGMII0_RX2_RXCDR2,0xff,0,x)
#define Rd_SGMII0_RX2_rxcdr2_phsacq_timeout(x) ReadRegBits16(SGMII0_RX2_RXCDR2,0xff,0)
#define SGMII0_RX2_RXCDR2_PHSACQ_TIMEOUT_MASK                      0x00ff
#define SGMII0_RX2_RXCDR2_PHSACQ_TIMEOUT_ALIGN                     0
#define SGMII0_RX2_RXCDR2_PHSACQ_TIMEOUT_BITS                      8
#define SGMII0_RX2_RXCDR2_PHSACQ_TIMEOUT_SHIFT                     0


/****************************************************************************
 * SGMII0_RX2 :: rxcdr3
 ***************************************************************************/
/* SGMII0_RX2 :: rxcdr3 :: reserved0 [15:13] */
#define SGMII0_RX2_RXCDR3_RESERVED0_MASK                           0xe000
#define SGMII0_RX2_RXCDR3_RESERVED0_ALIGN                          0
#define SGMII0_RX2_RXCDR3_RESERVED0_BITS                           3
#define SGMII0_RX2_RXCDR3_RESERVED0_SHIFT                          13

/* SGMII0_RX2 :: rxcdr3 :: phase_step [12:11] */
#define Wr_SGMII0_RX2_rxcdr3_phase_step(x) WriteRegBits16(SGMII0_RX2_RXCDR3,0x1800,11,x)
#define Rd_SGMII0_RX2_rxcdr3_phase_step(x) ReadRegBits16(SGMII0_RX2_RXCDR3,0x1800,11)
#define SGMII0_RX2_RXCDR3_PHASE_STEP_MASK                          0x1800
#define SGMII0_RX2_RXCDR3_PHASE_STEP_ALIGN                         0
#define SGMII0_RX2_RXCDR3_PHASE_STEP_BITS                          2
#define SGMII0_RX2_RXCDR3_PHASE_STEP_SHIFT                         11

/* SGMII0_RX2 :: rxcdr3 :: phase_frz_1 [10:10] */
#define Wr_SGMII0_RX2_rxcdr3_phase_frz_1(x) WriteRegBits16(SGMII0_RX2_RXCDR3,0x400,10,x)
#define Rd_SGMII0_RX2_rxcdr3_phase_frz_1(x) ReadRegBits16(SGMII0_RX2_RXCDR3,0x400,10)
#define SGMII0_RX2_RXCDR3_PHASE_FRZ_1_MASK                         0x0400
#define SGMII0_RX2_RXCDR3_PHASE_FRZ_1_ALIGN                        0
#define SGMII0_RX2_RXCDR3_PHASE_FRZ_1_BITS                         1
#define SGMII0_RX2_RXCDR3_PHASE_FRZ_1_SHIFT                        10

/* SGMII0_RX2 :: rxcdr3 :: phase_frz_1_en [09:09] */
#define Wr_SGMII0_RX2_rxcdr3_phase_frz_1_en(x) WriteRegBits16(SGMII0_RX2_RXCDR3,0x200,9,x)
#define Rd_SGMII0_RX2_rxcdr3_phase_frz_1_en(x) ReadRegBits16(SGMII0_RX2_RXCDR3,0x200,9)
#define SGMII0_RX2_RXCDR3_PHASE_FRZ_1_EN_MASK                      0x0200
#define SGMII0_RX2_RXCDR3_PHASE_FRZ_1_EN_ALIGN                     0
#define SGMII0_RX2_RXCDR3_PHASE_FRZ_1_EN_BITS                      1
#define SGMII0_RX2_RXCDR3_PHASE_FRZ_1_EN_SHIFT                     9

/* SGMII0_RX2 :: rxcdr3 :: phase_override_SM [08:08] */
#define Wr_SGMII0_RX2_rxcdr3_phase_override_SM(x) WriteRegBits16(SGMII0_RX2_RXCDR3,0x100,8,x)
#define Rd_SGMII0_RX2_rxcdr3_phase_override_SM(x) ReadRegBits16(SGMII0_RX2_RXCDR3,0x100,8)
#define SGMII0_RX2_RXCDR3_PHASE_OVERRIDE_SM_MASK                   0x0100
#define SGMII0_RX2_RXCDR3_PHASE_OVERRIDE_SM_ALIGN                  0
#define SGMII0_RX2_RXCDR3_PHASE_OVERRIDE_SM_BITS                   1
#define SGMII0_RX2_RXCDR3_PHASE_OVERRIDE_SM_SHIFT                  8

/* SGMII0_RX2 :: rxcdr3 :: phase_inc_SM [07:07] */
#define Wr_SGMII0_RX2_rxcdr3_phase_inc_SM(x) WriteRegBits16(SGMII0_RX2_RXCDR3,0x80,7,x)
#define Rd_SGMII0_RX2_rxcdr3_phase_inc_SM(x) ReadRegBits16(SGMII0_RX2_RXCDR3,0x80,7)
#define SGMII0_RX2_RXCDR3_PHASE_INC_SM_MASK                        0x0080
#define SGMII0_RX2_RXCDR3_PHASE_INC_SM_ALIGN                       0
#define SGMII0_RX2_RXCDR3_PHASE_INC_SM_BITS                        1
#define SGMII0_RX2_RXCDR3_PHASE_INC_SM_SHIFT                       7

/* SGMII0_RX2 :: rxcdr3 :: phase_dec_SM [06:06] */
#define Wr_SGMII0_RX2_rxcdr3_phase_dec_SM(x) WriteRegBits16(SGMII0_RX2_RXCDR3,0x40,6,x)
#define Rd_SGMII0_RX2_rxcdr3_phase_dec_SM(x) ReadRegBits16(SGMII0_RX2_RXCDR3,0x40,6)
#define SGMII0_RX2_RXCDR3_PHASE_DEC_SM_MASK                        0x0040
#define SGMII0_RX2_RXCDR3_PHASE_DEC_SM_ALIGN                       0
#define SGMII0_RX2_RXCDR3_PHASE_DEC_SM_BITS                        1
#define SGMII0_RX2_RXCDR3_PHASE_DEC_SM_SHIFT                       6

/* SGMII0_RX2 :: rxcdr3 :: phase_strobe_SM [05:05] */
#define Wr_SGMII0_RX2_rxcdr3_phase_strobe_SM(x) WriteRegBits16(SGMII0_RX2_RXCDR3,0x20,5,x)
#define Rd_SGMII0_RX2_rxcdr3_phase_strobe_SM(x) ReadRegBits16(SGMII0_RX2_RXCDR3,0x20,5)
#define SGMII0_RX2_RXCDR3_PHASE_STROBE_SM_MASK                     0x0020
#define SGMII0_RX2_RXCDR3_PHASE_STROBE_SM_ALIGN                    0
#define SGMII0_RX2_RXCDR3_PHASE_STROBE_SM_BITS                     1
#define SGMII0_RX2_RXCDR3_PHASE_STROBE_SM_SHIFT                    5

/* SGMII0_RX2 :: rxcdr3 :: phase_delta_SM [04:00] */
#define Wr_SGMII0_RX2_rxcdr3_phase_delta_SM(x) WriteRegBits16(SGMII0_RX2_RXCDR3,0x1f,0,x)
#define Rd_SGMII0_RX2_rxcdr3_phase_delta_SM(x) ReadRegBits16(SGMII0_RX2_RXCDR3,0x1f,0)
#define SGMII0_RX2_RXCDR3_PHASE_DELTA_SM_MASK                      0x001f
#define SGMII0_RX2_RXCDR3_PHASE_DELTA_SM_ALIGN                     0
#define SGMII0_RX2_RXCDR3_PHASE_DELTA_SM_BITS                      5
#define SGMII0_RX2_RXCDR3_PHASE_DELTA_SM_SHIFT                     0


/****************************************************************************
 * SGMII0_RX2 :: rxcdr4
 ***************************************************************************/
/* SGMII0_RX2 :: rxcdr4 :: bwsel_integ [15:12] */
#define Wr_SGMII0_RX2_rxcdr4_bwsel_integ(x) WriteRegBits16(SGMII0_RX2_RXCDR4,0xf000,12,x)
#define Rd_SGMII0_RX2_rxcdr4_bwsel_integ(x) ReadRegBits16(SGMII0_RX2_RXCDR4,0xf000,12)
#define SGMII0_RX2_RXCDR4_BWSEL_INTEG_MASK                         0xf000
#define SGMII0_RX2_RXCDR4_BWSEL_INTEG_ALIGN                        0
#define SGMII0_RX2_RXCDR4_BWSEL_INTEG_BITS                         4
#define SGMII0_RX2_RXCDR4_BWSEL_INTEG_SHIFT                        12

/* SGMII0_RX2 :: rxcdr4 :: bwsel_prop [11:08] */
#define Wr_SGMII0_RX2_rxcdr4_bwsel_prop(x) WriteRegBits16(SGMII0_RX2_RXCDR4,0xf00,8,x)
#define Rd_SGMII0_RX2_rxcdr4_bwsel_prop(x) ReadRegBits16(SGMII0_RX2_RXCDR4,0xf00,8)
#define SGMII0_RX2_RXCDR4_BWSEL_PROP_MASK                          0x0f00
#define SGMII0_RX2_RXCDR4_BWSEL_PROP_ALIGN                         0
#define SGMII0_RX2_RXCDR4_BWSEL_PROP_BITS                          4
#define SGMII0_RX2_RXCDR4_BWSEL_PROP_SHIFT                         8

/* SGMII0_RX2 :: rxcdr4 :: integ_clr [07:07] */
#define Wr_SGMII0_RX2_rxcdr4_integ_clr(x) WriteRegBits16(SGMII0_RX2_RXCDR4,0x80,7,x)
#define Rd_SGMII0_RX2_rxcdr4_integ_clr(x) ReadRegBits16(SGMII0_RX2_RXCDR4,0x80,7)
#define SGMII0_RX2_RXCDR4_INTEG_CLR_MASK                           0x0080
#define SGMII0_RX2_RXCDR4_INTEG_CLR_ALIGN                          0
#define SGMII0_RX2_RXCDR4_INTEG_CLR_BITS                           1
#define SGMII0_RX2_RXCDR4_INTEG_CLR_SHIFT                          7

/* SGMII0_RX2 :: rxcdr4 :: freq_en [06:06] */
#define Wr_SGMII0_RX2_rxcdr4_freq_en(x) WriteRegBits16(SGMII0_RX2_RXCDR4,0x40,6,x)
#define Rd_SGMII0_RX2_rxcdr4_freq_en(x) ReadRegBits16(SGMII0_RX2_RXCDR4,0x40,6)
#define SGMII0_RX2_RXCDR4_FREQ_EN_MASK                             0x0040
#define SGMII0_RX2_RXCDR4_FREQ_EN_ALIGN                            0
#define SGMII0_RX2_RXCDR4_FREQ_EN_BITS                             1
#define SGMII0_RX2_RXCDR4_FREQ_EN_SHIFT                            6

/* SGMII0_RX2 :: rxcdr4 :: freq_override_en [05:05] */
#define Wr_SGMII0_RX2_rxcdr4_freq_override_en(x) WriteRegBits16(SGMII0_RX2_RXCDR4,0x20,5,x)
#define Rd_SGMII0_RX2_rxcdr4_freq_override_en(x) ReadRegBits16(SGMII0_RX2_RXCDR4,0x20,5)
#define SGMII0_RX2_RXCDR4_FREQ_OVERRIDE_EN_MASK                    0x0020
#define SGMII0_RX2_RXCDR4_FREQ_OVERRIDE_EN_ALIGN                   0
#define SGMII0_RX2_RXCDR4_FREQ_OVERRIDE_EN_BITS                    1
#define SGMII0_RX2_RXCDR4_FREQ_OVERRIDE_EN_SHIFT                   5

/* SGMII0_RX2 :: rxcdr4 :: freq_override_val [04:00] */
#define Wr_SGMII0_RX2_rxcdr4_freq_override_val(x) WriteRegBits16(SGMII0_RX2_RXCDR4,0x1f,0,x)
#define Rd_SGMII0_RX2_rxcdr4_freq_override_val(x) ReadRegBits16(SGMII0_RX2_RXCDR4,0x1f,0)
#define SGMII0_RX2_RXCDR4_FREQ_OVERRIDE_VAL_MASK                   0x001f
#define SGMII0_RX2_RXCDR4_FREQ_OVERRIDE_VAL_ALIGN                  0
#define SGMII0_RX2_RXCDR4_FREQ_OVERRIDE_VAL_BITS                   5
#define SGMII0_RX2_RXCDR4_FREQ_OVERRIDE_VAL_SHIFT                  0


/****************************************************************************
 * SGMII0_RX2 :: status0
 ***************************************************************************/
/* SGMII0_RX2 :: status0 :: reserved0 [15:10] */
#define SGMII0_RX2_STATUS0_RESERVED0_MASK                          0xfc00
#define SGMII0_RX2_STATUS0_RESERVED0_ALIGN                         0
#define SGMII0_RX2_STATUS0_RESERVED0_BITS                          6
#define SGMII0_RX2_STATUS0_RESERVED0_SHIFT                         10

/* SGMII0_RX2 :: status0 :: rx_lmtoff [09:04] */
#define Wr_SGMII0_RX2_status0_rx_lmtoff(x) WriteRegBits16(SGMII0_RX2_STATUS0,0x3f0,4,x)
#define Rd_SGMII0_RX2_status0_rx_lmtoff(x) ReadRegBits16(SGMII0_RX2_STATUS0,0x3f0,4)
#define SGMII0_RX2_STATUS0_RX_LMTOFF_MASK                          0x03f0
#define SGMII0_RX2_STATUS0_RX_LMTOFF_ALIGN                         0
#define SGMII0_RX2_STATUS0_RX_LMTOFF_BITS                          6
#define SGMII0_RX2_STATUS0_RX_LMTOFF_SHIFT                         4

/* SGMII0_RX2 :: status0 :: rx_slicer_cal_done [03:03] */
#define Wr_SGMII0_RX2_status0_rx_slicer_cal_done(x) WriteRegBits16(SGMII0_RX2_STATUS0,0x8,3,x)
#define Rd_SGMII0_RX2_status0_rx_slicer_cal_done(x) ReadRegBits16(SGMII0_RX2_STATUS0,0x8,3)
#define SGMII0_RX2_STATUS0_RX_SLICER_CAL_DONE_MASK                 0x0008
#define SGMII0_RX2_STATUS0_RX_SLICER_CAL_DONE_ALIGN                0
#define SGMII0_RX2_STATUS0_RX_SLICER_CAL_DONE_BITS                 1
#define SGMII0_RX2_STATUS0_RX_SLICER_CAL_DONE_SHIFT                3

/* SGMII0_RX2 :: status0 :: rx_sloff0_invalid [02:02] */
#define Wr_SGMII0_RX2_status0_rx_sloff0_invalid(x) WriteRegBits16(SGMII0_RX2_STATUS0,0x4,2,x)
#define Rd_SGMII0_RX2_status0_rx_sloff0_invalid(x) ReadRegBits16(SGMII0_RX2_STATUS0,0x4,2)
#define SGMII0_RX2_STATUS0_RX_SLOFF0_INVALID_MASK                  0x0004
#define SGMII0_RX2_STATUS0_RX_SLOFF0_INVALID_ALIGN                 0
#define SGMII0_RX2_STATUS0_RX_SLOFF0_INVALID_BITS                  1
#define SGMII0_RX2_STATUS0_RX_SLOFF0_INVALID_SHIFT                 2

/* SGMII0_RX2 :: status0 :: rx_sloff1_invalid [01:01] */
#define Wr_SGMII0_RX2_status0_rx_sloff1_invalid(x) WriteRegBits16(SGMII0_RX2_STATUS0,0x2,1,x)
#define Rd_SGMII0_RX2_status0_rx_sloff1_invalid(x) ReadRegBits16(SGMII0_RX2_STATUS0,0x2,1)
#define SGMII0_RX2_STATUS0_RX_SLOFF1_INVALID_MASK                  0x0002
#define SGMII0_RX2_STATUS0_RX_SLOFF1_INVALID_ALIGN                 0
#define SGMII0_RX2_STATUS0_RX_SLOFF1_INVALID_BITS                  1
#define SGMII0_RX2_STATUS0_RX_SLOFF1_INVALID_SHIFT                 1

/* SGMII0_RX2 :: status0 :: rx_sloff2_invalid [00:00] */
#define Wr_SGMII0_RX2_status0_rx_sloff2_invalid(x) WriteRegBits16(SGMII0_RX2_STATUS0,0x1,0,x)
#define Rd_SGMII0_RX2_status0_rx_sloff2_invalid(x) ReadRegBits16(SGMII0_RX2_STATUS0,0x1,0)
#define SGMII0_RX2_STATUS0_RX_SLOFF2_INVALID_MASK                  0x0001
#define SGMII0_RX2_STATUS0_RX_SLOFF2_INVALID_ALIGN                 0
#define SGMII0_RX2_STATUS0_RX_SLOFF2_INVALID_BITS                  1
#define SGMII0_RX2_STATUS0_RX_SLOFF2_INVALID_SHIFT                 0


/****************************************************************************
 * SGMII0_RX2 :: status1
 ***************************************************************************/
/* SGMII0_RX2 :: status1 :: reserved0 [15:15] */
#define SGMII0_RX2_STATUS1_RESERVED0_MASK                          0x8000
#define SGMII0_RX2_STATUS1_RESERVED0_ALIGN                         0
#define SGMII0_RX2_STATUS1_RESERVED0_BITS                          1
#define SGMII0_RX2_STATUS1_RESERVED0_SHIFT                         15

/* SGMII0_RX2 :: status1 :: up_sloffx_val [14:11] */
#define Wr_SGMII0_RX2_status1_up_sloffx_val(x) WriteRegBits16(SGMII0_RX2_STATUS1,0x7800,11,x)
#define Rd_SGMII0_RX2_status1_up_sloffx_val(x) ReadRegBits16(SGMII0_RX2_STATUS1,0x7800,11)
#define SGMII0_RX2_STATUS1_UP_SLOFFX_VAL_MASK                      0x7800
#define SGMII0_RX2_STATUS1_UP_SLOFFX_VAL_ALIGN                     0
#define SGMII0_RX2_STATUS1_UP_SLOFFX_VAL_BITS                      4
#define SGMII0_RX2_STATUS1_UP_SLOFFX_VAL_SHIFT                     11

/* SGMII0_RX2 :: status1 :: dn_sloffx_val [10:07] */
#define Wr_SGMII0_RX2_status1_dn_sloffx_val(x) WriteRegBits16(SGMII0_RX2_STATUS1,0x780,7,x)
#define Rd_SGMII0_RX2_status1_dn_sloffx_val(x) ReadRegBits16(SGMII0_RX2_STATUS1,0x780,7)
#define SGMII0_RX2_STATUS1_DN_SLOFFX_VAL_MASK                      0x0780
#define SGMII0_RX2_STATUS1_DN_SLOFFX_VAL_ALIGN                     0
#define SGMII0_RX2_STATUS1_DN_SLOFFX_VAL_BITS                      4
#define SGMII0_RX2_STATUS1_DN_SLOFFX_VAL_SHIFT                     7

/* SGMII0_RX2 :: status1 :: sloffx_val [06:03] */
#define Wr_SGMII0_RX2_status1_sloffx_val(x) WriteRegBits16(SGMII0_RX2_STATUS1,0x78,3,x)
#define Rd_SGMII0_RX2_status1_sloffx_val(x) ReadRegBits16(SGMII0_RX2_STATUS1,0x78,3)
#define SGMII0_RX2_STATUS1_SLOFFX_VAL_MASK                         0x0078
#define SGMII0_RX2_STATUS1_SLOFFX_VAL_ALIGN                        0
#define SGMII0_RX2_STATUS1_SLOFFX_VAL_BITS                         4
#define SGMII0_RX2_STATUS1_SLOFFX_VAL_SHIFT                        3

/* SGMII0_RX2 :: status1 :: slcal_state [02:00] */
#define Wr_SGMII0_RX2_status1_slcal_state(x) WriteRegBits16(SGMII0_RX2_STATUS1,0x7,0,x)
#define Rd_SGMII0_RX2_status1_slcal_state(x) ReadRegBits16(SGMII0_RX2_STATUS1,0x7,0)
#define SGMII0_RX2_STATUS1_SLCAL_STATE_MASK                        0x0007
#define SGMII0_RX2_STATUS1_SLCAL_STATE_ALIGN                       0
#define SGMII0_RX2_STATUS1_SLCAL_STATE_BITS                        3
#define SGMII0_RX2_STATUS1_SLCAL_STATE_SHIFT                       0


/****************************************************************************
 * SGMII0_RX2 :: status2
 ***************************************************************************/
/* SGMII0_RX2 :: status2 :: lmtcal_acc [15:00] */
#define Wr_SGMII0_RX2_status2_lmtcal_acc(x) WriteReg16(SGMII0_RX2_STATUS2,x)
#define Rd_SGMII0_RX2_status2_lmtcal_acc(x) ReadReg16(SGMII0_RX2_STATUS2)
#define SGMII0_RX2_STATUS2_LMTCAL_ACC_MASK                         0xffff
#define SGMII0_RX2_STATUS2_LMTCAL_ACC_ALIGN                        0
#define SGMII0_RX2_STATUS2_LMTCAL_ACC_BITS                         16
#define SGMII0_RX2_STATUS2_LMTCAL_ACC_SHIFT                        0


/****************************************************************************
 * SGMII0_RX2 :: status3
 ***************************************************************************/
/* SGMII0_RX2 :: status3 :: reserved0 [15:11] */
#define SGMII0_RX2_STATUS3_RESERVED0_MASK                          0xf800
#define SGMII0_RX2_STATUS3_RESERVED0_ALIGN                         0
#define SGMII0_RX2_STATUS3_RESERVED0_BITS                          5
#define SGMII0_RX2_STATUS3_RESERVED0_SHIFT                         11

/* SGMII0_RX2 :: status3 :: lmtcal_state [10:08] */
#define Wr_SGMII0_RX2_status3_lmtcal_state(x) WriteRegBits16(SGMII0_RX2_STATUS3,0x700,8,x)
#define Rd_SGMII0_RX2_status3_lmtcal_state(x) ReadRegBits16(SGMII0_RX2_STATUS3,0x700,8)
#define SGMII0_RX2_STATUS3_LMTCAL_STATE_MASK                       0x0700
#define SGMII0_RX2_STATUS3_LMTCAL_STATE_ALIGN                      0
#define SGMII0_RX2_STATUS3_LMTCAL_STATE_BITS                       3
#define SGMII0_RX2_STATUS3_LMTCAL_STATE_SHIFT                      8

/* SGMII0_RX2 :: status3 :: rx_LA_cal_done [07:07] */
#define Wr_SGMII0_RX2_status3_rx_LA_cal_done(x) WriteRegBits16(SGMII0_RX2_STATUS3,0x80,7,x)
#define Rd_SGMII0_RX2_status3_rx_LA_cal_done(x) ReadRegBits16(SGMII0_RX2_STATUS3,0x80,7)
#define SGMII0_RX2_STATUS3_RX_LA_CAL_DONE_MASK                     0x0080
#define SGMII0_RX2_STATUS3_RX_LA_CAL_DONE_ALIGN                    0
#define SGMII0_RX2_STATUS3_RX_LA_CAL_DONE_BITS                     1
#define SGMII0_RX2_STATUS3_RX_LA_CAL_DONE_SHIFT                    7

/* SGMII0_RX2 :: status3 :: lmtcal_valid [06:06] */
#define Wr_SGMII0_RX2_status3_lmtcal_valid(x) WriteRegBits16(SGMII0_RX2_STATUS3,0x40,6,x)
#define Rd_SGMII0_RX2_status3_lmtcal_valid(x) ReadRegBits16(SGMII0_RX2_STATUS3,0x40,6)
#define SGMII0_RX2_STATUS3_LMTCAL_VALID_MASK                       0x0040
#define SGMII0_RX2_STATUS3_LMTCAL_VALID_ALIGN                      0
#define SGMII0_RX2_STATUS3_LMTCAL_VALID_BITS                       1
#define SGMII0_RX2_STATUS3_LMTCAL_VALID_SHIFT                      6

/* SGMII0_RX2 :: status3 :: lmtcal_adj_cnt [05:01] */
#define Wr_SGMII0_RX2_status3_lmtcal_adj_cnt(x) WriteRegBits16(SGMII0_RX2_STATUS3,0x3e,1,x)
#define Rd_SGMII0_RX2_status3_lmtcal_adj_cnt(x) ReadRegBits16(SGMII0_RX2_STATUS3,0x3e,1)
#define SGMII0_RX2_STATUS3_LMTCAL_ADJ_CNT_MASK                     0x003e
#define SGMII0_RX2_STATUS3_LMTCAL_ADJ_CNT_ALIGN                    0
#define SGMII0_RX2_STATUS3_LMTCAL_ADJ_CNT_BITS                     5
#define SGMII0_RX2_STATUS3_LMTCAL_ADJ_CNT_SHIFT                    1

/* SGMII0_RX2 :: status3 :: recal_ind [00:00] */
#define Wr_SGMII0_RX2_status3_recal_ind(x) WriteRegBits16(SGMII0_RX2_STATUS3,0x1,0,x)
#define Rd_SGMII0_RX2_status3_recal_ind(x) ReadRegBits16(SGMII0_RX2_STATUS3,0x1,0)
#define SGMII0_RX2_STATUS3_RECAL_IND_MASK                          0x0001
#define SGMII0_RX2_STATUS3_RECAL_IND_ALIGN                         0
#define SGMII0_RX2_STATUS3_RECAL_IND_BITS                          1
#define SGMII0_RX2_STATUS3_RECAL_IND_SHIFT                         0


/****************************************************************************
 * SGMII0_RX2 :: status4
 ***************************************************************************/
/* SGMII0_RX2 :: status4 :: em_err_cnt_H [15:00] */
#define Wr_SGMII0_RX2_status4_em_err_cnt_H(x) WriteReg16(SGMII0_RX2_STATUS4,x)
#define Rd_SGMII0_RX2_status4_em_err_cnt_H(x) ReadReg16(SGMII0_RX2_STATUS4)
#define SGMII0_RX2_STATUS4_EM_ERR_CNT_H_MASK                       0xffff
#define SGMII0_RX2_STATUS4_EM_ERR_CNT_H_ALIGN                      0
#define SGMII0_RX2_STATUS4_EM_ERR_CNT_H_BITS                       16
#define SGMII0_RX2_STATUS4_EM_ERR_CNT_H_SHIFT                      0


/****************************************************************************
 * SGMII0_RX2 :: status5
 ***************************************************************************/
/* SGMII0_RX2 :: status5 :: em_err_cnt_L [15:00] */
#define Wr_SGMII0_RX2_status5_em_err_cnt_L(x) WriteReg16(SGMII0_RX2_STATUS5,x)
#define Rd_SGMII0_RX2_status5_em_err_cnt_L(x) ReadReg16(SGMII0_RX2_STATUS5)
#define SGMII0_RX2_STATUS5_EM_ERR_CNT_L_MASK                       0xffff
#define SGMII0_RX2_STATUS5_EM_ERR_CNT_L_ALIGN                      0
#define SGMII0_RX2_STATUS5_EM_ERR_CNT_L_BITS                       16
#define SGMII0_RX2_STATUS5_EM_ERR_CNT_L_SHIFT                      0


/****************************************************************************
 * SGMII0_RX2 :: status6
 ***************************************************************************/
/* SGMII0_RX2 :: status6 :: rx_phs_interp_status [15:00] */
#define Wr_SGMII0_RX2_status6_rx_phs_interp_status(x) WriteReg16(SGMII0_RX2_STATUS6,x)
#define Rd_SGMII0_RX2_status6_rx_phs_interp_status(x) ReadReg16(SGMII0_RX2_STATUS6)
#define SGMII0_RX2_STATUS6_RX_PHS_INTERP_STATUS_MASK               0xffff
#define SGMII0_RX2_STATUS6_RX_PHS_INTERP_STATUS_ALIGN              0
#define SGMII0_RX2_STATUS6_RX_PHS_INTERP_STATUS_BITS               16
#define SGMII0_RX2_STATUS6_RX_PHS_INTERP_STATUS_SHIFT              0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_RX3
 ***************************************************************************/
/****************************************************************************
 * SGMII0_RX3 :: control0
 ***************************************************************************/
/* SGMII0_RX3 :: control0 :: lmtcal_max_adj [15:11] */
#define Wr_SGMII0_RX3_control0_lmtcal_max_adj(x) WriteRegBits16(SGMII0_RX3_CONTROL0,0xf800,11,x)
#define Rd_SGMII0_RX3_control0_lmtcal_max_adj(x) ReadRegBits16(SGMII0_RX3_CONTROL0,0xf800,11)
#define SGMII0_RX3_CONTROL0_LMTCAL_MAX_ADJ_MASK                    0xf800
#define SGMII0_RX3_CONTROL0_LMTCAL_MAX_ADJ_ALIGN                   0
#define SGMII0_RX3_CONTROL0_LMTCAL_MAX_ADJ_BITS                    5
#define SGMII0_RX3_CONTROL0_LMTCAL_MAX_ADJ_SHIFT                   11

/* SGMII0_RX3 :: control0 :: lmtcal_intv_time [10:00] */
#define Wr_SGMII0_RX3_control0_lmtcal_intv_time(x) WriteRegBits16(SGMII0_RX3_CONTROL0,0x7ff,0,x)
#define Rd_SGMII0_RX3_control0_lmtcal_intv_time(x) ReadRegBits16(SGMII0_RX3_CONTROL0,0x7ff,0)
#define SGMII0_RX3_CONTROL0_LMTCAL_INTV_TIME_MASK                  0x07ff
#define SGMII0_RX3_CONTROL0_LMTCAL_INTV_TIME_ALIGN                 0
#define SGMII0_RX3_CONTROL0_LMTCAL_INTV_TIME_BITS                  11
#define SGMII0_RX3_CONTROL0_LMTCAL_INTV_TIME_SHIFT                 0


/****************************************************************************
 * SGMII0_RX3 :: control1
 ***************************************************************************/
/* SGMII0_RX3 :: control1 :: lmtcal_falling_edge_en [15:15] */
#define Wr_SGMII0_RX3_control1_lmtcal_falling_edge_en(x) WriteRegBits16(SGMII0_RX3_CONTROL1,0x8000,15,x)
#define Rd_SGMII0_RX3_control1_lmtcal_falling_edge_en(x) ReadRegBits16(SGMII0_RX3_CONTROL1,0x8000,15)
#define SGMII0_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_MASK            0x8000
#define SGMII0_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_ALIGN           0
#define SGMII0_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_BITS            1
#define SGMII0_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_SHIFT           15

/* SGMII0_RX3 :: control1 :: lmtcal_rising_edge_en [14:14] */
#define Wr_SGMII0_RX3_control1_lmtcal_rising_edge_en(x) WriteRegBits16(SGMII0_RX3_CONTROL1,0x4000,14,x)
#define Rd_SGMII0_RX3_control1_lmtcal_rising_edge_en(x) ReadRegBits16(SGMII0_RX3_CONTROL1,0x4000,14)
#define SGMII0_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_MASK             0x4000
#define SGMII0_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_ALIGN            0
#define SGMII0_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_BITS             1
#define SGMII0_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_SHIFT            14

/* SGMII0_RX3 :: control1 :: lmtcal_kp [13:12] */
#define Wr_SGMII0_RX3_control1_lmtcal_kp(x) WriteRegBits16(SGMII0_RX3_CONTROL1,0x3000,12,x)
#define Rd_SGMII0_RX3_control1_lmtcal_kp(x) ReadRegBits16(SGMII0_RX3_CONTROL1,0x3000,12)
#define SGMII0_RX3_CONTROL1_LMTCAL_KP_MASK                         0x3000
#define SGMII0_RX3_CONTROL1_LMTCAL_KP_ALIGN                        0
#define SGMII0_RX3_CONTROL1_LMTCAL_KP_BITS                         2
#define SGMII0_RX3_CONTROL1_LMTCAL_KP_SHIFT                        12

/* SGMII0_RX3 :: control1 :: lmtcal_adj_dir [11:11] */
#define Wr_SGMII0_RX3_control1_lmtcal_adj_dir(x) WriteRegBits16(SGMII0_RX3_CONTROL1,0x800,11,x)
#define Rd_SGMII0_RX3_control1_lmtcal_adj_dir(x) ReadRegBits16(SGMII0_RX3_CONTROL1,0x800,11)
#define SGMII0_RX3_CONTROL1_LMTCAL_ADJ_DIR_MASK                    0x0800
#define SGMII0_RX3_CONTROL1_LMTCAL_ADJ_DIR_ALIGN                   0
#define SGMII0_RX3_CONTROL1_LMTCAL_ADJ_DIR_BITS                    1
#define SGMII0_RX3_CONTROL1_LMTCAL_ADJ_DIR_SHIFT                   11

/* SGMII0_RX3 :: control1 :: lmtcal_init_time [10:00] */
#define Wr_SGMII0_RX3_control1_lmtcal_init_time(x) WriteRegBits16(SGMII0_RX3_CONTROL1,0x7ff,0,x)
#define Rd_SGMII0_RX3_control1_lmtcal_init_time(x) ReadRegBits16(SGMII0_RX3_CONTROL1,0x7ff,0)
#define SGMII0_RX3_CONTROL1_LMTCAL_INIT_TIME_MASK                  0x07ff
#define SGMII0_RX3_CONTROL1_LMTCAL_INIT_TIME_ALIGN                 0
#define SGMII0_RX3_CONTROL1_LMTCAL_INIT_TIME_BITS                  11
#define SGMII0_RX3_CONTROL1_LMTCAL_INIT_TIME_SHIFT                 0


/****************************************************************************
 * SGMII0_RX3 :: control2
 ***************************************************************************/
/* SGMII0_RX3 :: control2 :: lmtcal_pd_polarity [15:15] */
#define Wr_SGMII0_RX3_control2_lmtcal_pd_polarity(x) WriteRegBits16(SGMII0_RX3_CONTROL2,0x8000,15,x)
#define Rd_SGMII0_RX3_control2_lmtcal_pd_polarity(x) ReadRegBits16(SGMII0_RX3_CONTROL2,0x8000,15)
#define SGMII0_RX3_CONTROL2_LMTCAL_PD_POLARITY_MASK                0x8000
#define SGMII0_RX3_CONTROL2_LMTCAL_PD_POLARITY_ALIGN               0
#define SGMII0_RX3_CONTROL2_LMTCAL_PD_POLARITY_BITS                1
#define SGMII0_RX3_CONTROL2_LMTCAL_PD_POLARITY_SHIFT               15

/* SGMII0_RX3 :: control2 :: lmtcal_acc_time [14:04] */
#define Wr_SGMII0_RX3_control2_lmtcal_acc_time(x) WriteRegBits16(SGMII0_RX3_CONTROL2,0x7ff0,4,x)
#define Rd_SGMII0_RX3_control2_lmtcal_acc_time(x) ReadRegBits16(SGMII0_RX3_CONTROL2,0x7ff0,4)
#define SGMII0_RX3_CONTROL2_LMTCAL_ACC_TIME_MASK                   0x7ff0
#define SGMII0_RX3_CONTROL2_LMTCAL_ACC_TIME_ALIGN                  0
#define SGMII0_RX3_CONTROL2_LMTCAL_ACC_TIME_BITS                   11
#define SGMII0_RX3_CONTROL2_LMTCAL_ACC_TIME_SHIFT                  4

/* SGMII0_RX3 :: control2 :: lmtcal_en_ovrd [03:03] */
#define Wr_SGMII0_RX3_control2_lmtcal_en_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL2,0x8,3,x)
#define Rd_SGMII0_RX3_control2_lmtcal_en_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL2,0x8,3)
#define SGMII0_RX3_CONTROL2_LMTCAL_EN_OVRD_MASK                    0x0008
#define SGMII0_RX3_CONTROL2_LMTCAL_EN_OVRD_ALIGN                   0
#define SGMII0_RX3_CONTROL2_LMTCAL_EN_OVRD_BITS                    1
#define SGMII0_RX3_CONTROL2_LMTCAL_EN_OVRD_SHIFT                   3

/* SGMII0_RX3 :: control2 :: lmtcal_en_ovrd_val [02:02] */
#define Wr_SGMII0_RX3_control2_lmtcal_en_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL2,0x4,2,x)
#define Rd_SGMII0_RX3_control2_lmtcal_en_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL2,0x4,2)
#define SGMII0_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_MASK                0x0004
#define SGMII0_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_ALIGN               0
#define SGMII0_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_BITS                1
#define SGMII0_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_SHIFT               2

/* SGMII0_RX3 :: control2 :: lmtcal_done_ovrd [01:01] */
#define Wr_SGMII0_RX3_control2_lmtcal_done_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL2,0x2,1,x)
#define Rd_SGMII0_RX3_control2_lmtcal_done_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL2,0x2,1)
#define SGMII0_RX3_CONTROL2_LMTCAL_DONE_OVRD_MASK                  0x0002
#define SGMII0_RX3_CONTROL2_LMTCAL_DONE_OVRD_ALIGN                 0
#define SGMII0_RX3_CONTROL2_LMTCAL_DONE_OVRD_BITS                  1
#define SGMII0_RX3_CONTROL2_LMTCAL_DONE_OVRD_SHIFT                 1

/* SGMII0_RX3 :: control2 :: lmtcal_done_ovrd_val [00:00] */
#define Wr_SGMII0_RX3_control2_lmtcal_done_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL2,0x1,0,x)
#define Rd_SGMII0_RX3_control2_lmtcal_done_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL2,0x1,0)
#define SGMII0_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_MASK              0x0001
#define SGMII0_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_ALIGN             0
#define SGMII0_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_BITS              1
#define SGMII0_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_SHIFT             0


/****************************************************************************
 * SGMII0_RX3 :: control3
 ***************************************************************************/
/* SGMII0_RX3 :: control3 :: recal_pos_thres [15:00] */
#define Wr_SGMII0_RX3_control3_recal_pos_thres(x) WriteReg16(SGMII0_RX3_CONTROL3,x)
#define Rd_SGMII0_RX3_control3_recal_pos_thres(x) ReadReg16(SGMII0_RX3_CONTROL3)
#define SGMII0_RX3_CONTROL3_RECAL_POS_THRES_MASK                   0xffff
#define SGMII0_RX3_CONTROL3_RECAL_POS_THRES_ALIGN                  0
#define SGMII0_RX3_CONTROL3_RECAL_POS_THRES_BITS                   16
#define SGMII0_RX3_CONTROL3_RECAL_POS_THRES_SHIFT                  0


/****************************************************************************
 * SGMII0_RX3 :: control4
 ***************************************************************************/
/* SGMII0_RX3 :: control4 :: recal_neg_thres [15:00] */
#define Wr_SGMII0_RX3_control4_recal_neg_thres(x) WriteReg16(SGMII0_RX3_CONTROL4,x)
#define Rd_SGMII0_RX3_control4_recal_neg_thres(x) ReadReg16(SGMII0_RX3_CONTROL4)
#define SGMII0_RX3_CONTROL4_RECAL_NEG_THRES_MASK                   0xffff
#define SGMII0_RX3_CONTROL4_RECAL_NEG_THRES_ALIGN                  0
#define SGMII0_RX3_CONTROL4_RECAL_NEG_THRES_BITS                   16
#define SGMII0_RX3_CONTROL4_RECAL_NEG_THRES_SHIFT                  0


/****************************************************************************
 * SGMII0_RX3 :: control5
 ***************************************************************************/
/* SGMII0_RX3 :: control5 :: reserved0 [15:12] */
#define SGMII0_RX3_CONTROL5_RESERVED0_MASK                         0xf000
#define SGMII0_RX3_CONTROL5_RESERVED0_ALIGN                        0
#define SGMII0_RX3_CONTROL5_RESERVED0_BITS                         4
#define SGMII0_RX3_CONTROL5_RESERVED0_SHIFT                        12

/* SGMII0_RX3 :: control5 :: lmtcal_cont_acc_time [11:01] */
#define Wr_SGMII0_RX3_control5_lmtcal_cont_acc_time(x) WriteRegBits16(SGMII0_RX3_CONTROL5,0xffe,1,x)
#define Rd_SGMII0_RX3_control5_lmtcal_cont_acc_time(x) ReadRegBits16(SGMII0_RX3_CONTROL5,0xffe,1)
#define SGMII0_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_MASK              0x0ffe
#define SGMII0_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_ALIGN             0
#define SGMII0_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_BITS              11
#define SGMII0_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_SHIFT             1

/* SGMII0_RX3 :: control5 :: cont_lmtcal_en [00:00] */
#define Wr_SGMII0_RX3_control5_cont_lmtcal_en(x) WriteRegBits16(SGMII0_RX3_CONTROL5,0x1,0,x)
#define Rd_SGMII0_RX3_control5_cont_lmtcal_en(x) ReadRegBits16(SGMII0_RX3_CONTROL5,0x1,0)
#define SGMII0_RX3_CONTROL5_CONT_LMTCAL_EN_MASK                    0x0001
#define SGMII0_RX3_CONTROL5_CONT_LMTCAL_EN_ALIGN                   0
#define SGMII0_RX3_CONTROL5_CONT_LMTCAL_EN_BITS                    1
#define SGMII0_RX3_CONTROL5_CONT_LMTCAL_EN_SHIFT                   0


/****************************************************************************
 * SGMII0_RX3 :: control6
 ***************************************************************************/
/* SGMII0_RX3 :: control6 :: reserved0 [15:12] */
#define SGMII0_RX3_CONTROL6_RESERVED0_MASK                         0xf000
#define SGMII0_RX3_CONTROL6_RESERVED0_ALIGN                        0
#define SGMII0_RX3_CONTROL6_RESERVED0_BITS                         4
#define SGMII0_RX3_CONTROL6_RESERVED0_SHIFT                        12

/* SGMII0_RX3 :: control6 :: lmtcal_interval_time [11:07] */
#define Wr_SGMII0_RX3_control6_lmtcal_interval_time(x) WriteRegBits16(SGMII0_RX3_CONTROL6,0xf80,7,x)
#define Rd_SGMII0_RX3_control6_lmtcal_interval_time(x) ReadRegBits16(SGMII0_RX3_CONTROL6,0xf80,7)
#define SGMII0_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_MASK              0x0f80
#define SGMII0_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_ALIGN             0
#define SGMII0_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_BITS              5
#define SGMII0_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_SHIFT             7

/* SGMII0_RX3 :: control6 :: rx_lmtoff_ovrd [06:06] */
#define Wr_SGMII0_RX3_control6_rx_lmtoff_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL6,0x40,6,x)
#define Rd_SGMII0_RX3_control6_rx_lmtoff_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL6,0x40,6)
#define SGMII0_RX3_CONTROL6_RX_LMTOFF_OVRD_MASK                    0x0040
#define SGMII0_RX3_CONTROL6_RX_LMTOFF_OVRD_ALIGN                   0
#define SGMII0_RX3_CONTROL6_RX_LMTOFF_OVRD_BITS                    1
#define SGMII0_RX3_CONTROL6_RX_LMTOFF_OVRD_SHIFT                   6

/* SGMII0_RX3 :: control6 :: rx_lmtoff_ovrd_val [05:00] */
#define Wr_SGMII0_RX3_control6_rx_lmtoff_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL6,0x3f,0,x)
#define Rd_SGMII0_RX3_control6_rx_lmtoff_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL6,0x3f,0)
#define SGMII0_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_MASK                0x003f
#define SGMII0_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_ALIGN               0
#define SGMII0_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_BITS                6
#define SGMII0_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_SHIFT               0


/****************************************************************************
 * SGMII0_RX3 :: control7
 ***************************************************************************/
/* SGMII0_RX3 :: control7 :: cal_state_ovrd [15:15] */
#define Wr_SGMII0_RX3_control7_cal_state_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL7,0x8000,15,x)
#define Rd_SGMII0_RX3_control7_cal_state_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL7,0x8000,15)
#define SGMII0_RX3_CONTROL7_CAL_STATE_OVRD_MASK                    0x8000
#define SGMII0_RX3_CONTROL7_CAL_STATE_OVRD_ALIGN                   0
#define SGMII0_RX3_CONTROL7_CAL_STATE_OVRD_BITS                    1
#define SGMII0_RX3_CONTROL7_CAL_STATE_OVRD_SHIFT                   15

/* SGMII0_RX3 :: control7 :: slcal_en_ovrd [14:14] */
#define Wr_SGMII0_RX3_control7_slcal_en_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL7,0x4000,14,x)
#define Rd_SGMII0_RX3_control7_slcal_en_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL7,0x4000,14)
#define SGMII0_RX3_CONTROL7_SLCAL_EN_OVRD_MASK                     0x4000
#define SGMII0_RX3_CONTROL7_SLCAL_EN_OVRD_ALIGN                    0
#define SGMII0_RX3_CONTROL7_SLCAL_EN_OVRD_BITS                     1
#define SGMII0_RX3_CONTROL7_SLCAL_EN_OVRD_SHIFT                    14

/* SGMII0_RX3 :: control7 :: slcal_en_ovrd_val [13:13] */
#define Wr_SGMII0_RX3_control7_slcal_en_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL7,0x2000,13,x)
#define Rd_SGMII0_RX3_control7_slcal_en_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL7,0x2000,13)
#define SGMII0_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_MASK                 0x2000
#define SGMII0_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_ALIGN                0
#define SGMII0_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_BITS                 1
#define SGMII0_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_SHIFT                13

/* SGMII0_RX3 :: control7 :: slcal_acc_opt [12:11] */
#define Wr_SGMII0_RX3_control7_slcal_acc_opt(x) WriteRegBits16(SGMII0_RX3_CONTROL7,0x1800,11,x)
#define Rd_SGMII0_RX3_control7_slcal_acc_opt(x) ReadRegBits16(SGMII0_RX3_CONTROL7,0x1800,11)
#define SGMII0_RX3_CONTROL7_SLCAL_ACC_OPT_MASK                     0x1800
#define SGMII0_RX3_CONTROL7_SLCAL_ACC_OPT_ALIGN                    0
#define SGMII0_RX3_CONTROL7_SLCAL_ACC_OPT_BITS                     2
#define SGMII0_RX3_CONTROL7_SLCAL_ACC_OPT_SHIFT                    11

/* SGMII0_RX3 :: control7 :: slcal_pol [10:10] */
#define Wr_SGMII0_RX3_control7_slcal_pol(x) WriteRegBits16(SGMII0_RX3_CONTROL7,0x400,10,x)
#define Rd_SGMII0_RX3_control7_slcal_pol(x) ReadRegBits16(SGMII0_RX3_CONTROL7,0x400,10)
#define SGMII0_RX3_CONTROL7_SLCAL_POL_MASK                         0x0400
#define SGMII0_RX3_CONTROL7_SLCAL_POL_ALIGN                        0
#define SGMII0_RX3_CONTROL7_SLCAL_POL_BITS                         1
#define SGMII0_RX3_CONTROL7_SLCAL_POL_SHIFT                        10

/* SGMII0_RX3 :: control7 :: reserved0 [09:02] */
#define SGMII0_RX3_CONTROL7_RESERVED0_MASK                         0x03fc
#define SGMII0_RX3_CONTROL7_RESERVED0_ALIGN                        0
#define SGMII0_RX3_CONTROL7_RESERVED0_BITS                         8
#define SGMII0_RX3_CONTROL7_RESERVED0_SHIFT                        2

/* SGMII0_RX3 :: control7 :: slcal_valid_ovrd [01:01] */
#define Wr_SGMII0_RX3_control7_slcal_valid_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL7,0x2,1,x)
#define Rd_SGMII0_RX3_control7_slcal_valid_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL7,0x2,1)
#define SGMII0_RX3_CONTROL7_SLCAL_VALID_OVRD_MASK                  0x0002
#define SGMII0_RX3_CONTROL7_SLCAL_VALID_OVRD_ALIGN                 0
#define SGMII0_RX3_CONTROL7_SLCAL_VALID_OVRD_BITS                  1
#define SGMII0_RX3_CONTROL7_SLCAL_VALID_OVRD_SHIFT                 1

/* SGMII0_RX3 :: control7 :: slcal_valid_ovrd_val [00:00] */
#define Wr_SGMII0_RX3_control7_slcal_valid_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL7,0x1,0,x)
#define Rd_SGMII0_RX3_control7_slcal_valid_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL7,0x1,0)
#define SGMII0_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_MASK              0x0001
#define SGMII0_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_ALIGN             0
#define SGMII0_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_BITS              1
#define SGMII0_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_SHIFT             0


/****************************************************************************
 * SGMII0_RX3 :: control8
 ***************************************************************************/
/* SGMII0_RX3 :: control8 :: reserved0 [15:15] */
#define SGMII0_RX3_CONTROL8_RESERVED0_MASK                         0x8000
#define SGMII0_RX3_CONTROL8_RESERVED0_ALIGN                        0
#define SGMII0_RX3_CONTROL8_RESERVED0_BITS                         1
#define SGMII0_RX3_CONTROL8_RESERVED0_SHIFT                        15

/* SGMII0_RX3 :: control8 :: rx_sloff2_ovrd [14:14] */
#define Wr_SGMII0_RX3_control8_rx_sloff2_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL8,0x4000,14,x)
#define Rd_SGMII0_RX3_control8_rx_sloff2_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL8,0x4000,14)
#define SGMII0_RX3_CONTROL8_RX_SLOFF2_OVRD_MASK                    0x4000
#define SGMII0_RX3_CONTROL8_RX_SLOFF2_OVRD_ALIGN                   0
#define SGMII0_RX3_CONTROL8_RX_SLOFF2_OVRD_BITS                    1
#define SGMII0_RX3_CONTROL8_RX_SLOFF2_OVRD_SHIFT                   14

/* SGMII0_RX3 :: control8 :: rx_sloff2_ovrd_val [13:10] */
#define Wr_SGMII0_RX3_control8_rx_sloff2_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL8,0x3c00,10,x)
#define Rd_SGMII0_RX3_control8_rx_sloff2_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL8,0x3c00,10)
#define SGMII0_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_MASK                0x3c00
#define SGMII0_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_ALIGN               0
#define SGMII0_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_BITS                4
#define SGMII0_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_SHIFT               10

/* SGMII0_RX3 :: control8 :: rx_sloff1_ovrd [09:09] */
#define Wr_SGMII0_RX3_control8_rx_sloff1_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL8,0x200,9,x)
#define Rd_SGMII0_RX3_control8_rx_sloff1_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL8,0x200,9)
#define SGMII0_RX3_CONTROL8_RX_SLOFF1_OVRD_MASK                    0x0200
#define SGMII0_RX3_CONTROL8_RX_SLOFF1_OVRD_ALIGN                   0
#define SGMII0_RX3_CONTROL8_RX_SLOFF1_OVRD_BITS                    1
#define SGMII0_RX3_CONTROL8_RX_SLOFF1_OVRD_SHIFT                   9

/* SGMII0_RX3 :: control8 :: rx_sloff1_ovrd_val [08:05] */
#define Wr_SGMII0_RX3_control8_rx_sloff1_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL8,0x1e0,5,x)
#define Rd_SGMII0_RX3_control8_rx_sloff1_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL8,0x1e0,5)
#define SGMII0_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_MASK                0x01e0
#define SGMII0_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_ALIGN               0
#define SGMII0_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_BITS                4
#define SGMII0_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_SHIFT               5

/* SGMII0_RX3 :: control8 :: rx_sloff0_ovrd [04:04] */
#define Wr_SGMII0_RX3_control8_rx_sloff0_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL8,0x10,4,x)
#define Rd_SGMII0_RX3_control8_rx_sloff0_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL8,0x10,4)
#define SGMII0_RX3_CONTROL8_RX_SLOFF0_OVRD_MASK                    0x0010
#define SGMII0_RX3_CONTROL8_RX_SLOFF0_OVRD_ALIGN                   0
#define SGMII0_RX3_CONTROL8_RX_SLOFF0_OVRD_BITS                    1
#define SGMII0_RX3_CONTROL8_RX_SLOFF0_OVRD_SHIFT                   4

/* SGMII0_RX3 :: control8 :: rx_sloff0_ovrd_val [03:00] */
#define Wr_SGMII0_RX3_control8_rx_sloff0_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL8,0xf,0,x)
#define Rd_SGMII0_RX3_control8_rx_sloff0_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL8,0xf,0)
#define SGMII0_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_MASK                0x000f
#define SGMII0_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_ALIGN               0
#define SGMII0_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_BITS                4
#define SGMII0_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_SHIFT               0


/****************************************************************************
 * SGMII0_RX3 :: control9
 ***************************************************************************/
/* SGMII0_RX3 :: control9 :: cal_state_ovrd_val [15:13] */
#define Wr_SGMII0_RX3_control9_cal_state_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL9,0xe000,13,x)
#define Rd_SGMII0_RX3_control9_cal_state_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL9,0xe000,13)
#define SGMII0_RX3_CONTROL9_CAL_STATE_OVRD_VAL_MASK                0xe000
#define SGMII0_RX3_CONTROL9_CAL_STATE_OVRD_VAL_ALIGN               0
#define SGMII0_RX3_CONTROL9_CAL_STATE_OVRD_VAL_BITS                3
#define SGMII0_RX3_CONTROL9_CAL_STATE_OVRD_VAL_SHIFT               13

/* SGMII0_RX3 :: control9 :: rx_slicer_calvalid_ovrd [12:12] */
#define Wr_SGMII0_RX3_control9_rx_slicer_calvalid_ovrd(x) WriteRegBits16(SGMII0_RX3_CONTROL9,0x1000,12,x)
#define Rd_SGMII0_RX3_control9_rx_slicer_calvalid_ovrd(x) ReadRegBits16(SGMII0_RX3_CONTROL9,0x1000,12)
#define SGMII0_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_MASK           0x1000
#define SGMII0_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_ALIGN          0
#define SGMII0_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_BITS           1
#define SGMII0_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_SHIFT          12

/* SGMII0_RX3 :: control9 :: rx_slicer_calvalid_ovrd_val [11:11] */
#define Wr_SGMII0_RX3_control9_rx_slicer_calvalid_ovrd_val(x) WriteRegBits16(SGMII0_RX3_CONTROL9,0x800,11,x)
#define Rd_SGMII0_RX3_control9_rx_slicer_calvalid_ovrd_val(x) ReadRegBits16(SGMII0_RX3_CONTROL9,0x800,11)
#define SGMII0_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_MASK       0x0800
#define SGMII0_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_ALIGN      0
#define SGMII0_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_BITS       1
#define SGMII0_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_SHIFT      11

/* SGMII0_RX3 :: control9 :: slcal_up_thres [10:00] */
#define Wr_SGMII0_RX3_control9_slcal_up_thres(x) WriteRegBits16(SGMII0_RX3_CONTROL9,0x7ff,0,x)
#define Rd_SGMII0_RX3_control9_slcal_up_thres(x) ReadRegBits16(SGMII0_RX3_CONTROL9,0x7ff,0)
#define SGMII0_RX3_CONTROL9_SLCAL_UP_THRES_MASK                    0x07ff
#define SGMII0_RX3_CONTROL9_SLCAL_UP_THRES_ALIGN                   0
#define SGMII0_RX3_CONTROL9_SLCAL_UP_THRES_BITS                    11
#define SGMII0_RX3_CONTROL9_SLCAL_UP_THRES_SHIFT                   0


/****************************************************************************
 * SGMII0_RX3 :: control10
 ***************************************************************************/
/* SGMII0_RX3 :: control10 :: slicer_interval_time [15:11] */
#define Wr_SGMII0_RX3_control10_slicer_interval_time(x) WriteRegBits16(SGMII0_RX3_CONTROL10,0xf800,11,x)
#define Rd_SGMII0_RX3_control10_slicer_interval_time(x) ReadRegBits16(SGMII0_RX3_CONTROL10,0xf800,11)
#define SGMII0_RX3_CONTROL10_SLICER_INTERVAL_TIME_MASK             0xf800
#define SGMII0_RX3_CONTROL10_SLICER_INTERVAL_TIME_ALIGN            0
#define SGMII0_RX3_CONTROL10_SLICER_INTERVAL_TIME_BITS             5
#define SGMII0_RX3_CONTROL10_SLICER_INTERVAL_TIME_SHIFT            11

/* SGMII0_RX3 :: control10 :: slcal_dn_thres [10:00] */
#define Wr_SGMII0_RX3_control10_slcal_dn_thres(x) WriteRegBits16(SGMII0_RX3_CONTROL10,0x7ff,0,x)
#define Rd_SGMII0_RX3_control10_slcal_dn_thres(x) ReadRegBits16(SGMII0_RX3_CONTROL10,0x7ff,0)
#define SGMII0_RX3_CONTROL10_SLCAL_DN_THRES_MASK                   0x07ff
#define SGMII0_RX3_CONTROL10_SLCAL_DN_THRES_ALIGN                  0
#define SGMII0_RX3_CONTROL10_SLCAL_DN_THRES_BITS                   11
#define SGMII0_RX3_CONTROL10_SLCAL_DN_THRES_SHIFT                  0


/****************************************************************************
 * SGMII0_RX3 :: control11
 ***************************************************************************/
/* SGMII0_RX3 :: control11 :: recal_ind_clr [15:15] */
#define Wr_SGMII0_RX3_control11_recal_ind_clr(x) WriteRegBits16(SGMII0_RX3_CONTROL11,0x8000,15,x)
#define Rd_SGMII0_RX3_control11_recal_ind_clr(x) ReadRegBits16(SGMII0_RX3_CONTROL11,0x8000,15)
#define SGMII0_RX3_CONTROL11_RECAL_IND_CLR_MASK                    0x8000
#define SGMII0_RX3_CONTROL11_RECAL_IND_CLR_ALIGN                   0
#define SGMII0_RX3_CONTROL11_RECAL_IND_CLR_BITS                    1
#define SGMII0_RX3_CONTROL11_RECAL_IND_CLR_SHIFT                   15

/* SGMII0_RX3 :: control11 :: slcal_init_time [14:07] */
#define Wr_SGMII0_RX3_control11_slcal_init_time(x) WriteRegBits16(SGMII0_RX3_CONTROL11,0x7f80,7,x)
#define Rd_SGMII0_RX3_control11_slcal_init_time(x) ReadRegBits16(SGMII0_RX3_CONTROL11,0x7f80,7)
#define SGMII0_RX3_CONTROL11_SLCAL_INIT_TIME_MASK                  0x7f80
#define SGMII0_RX3_CONTROL11_SLCAL_INIT_TIME_ALIGN                 0
#define SGMII0_RX3_CONTROL11_SLCAL_INIT_TIME_BITS                  8
#define SGMII0_RX3_CONTROL11_SLCAL_INIT_TIME_SHIFT                 7

/* SGMII0_RX3 :: control11 :: reserved0 [06:02] */
#define SGMII0_RX3_CONTROL11_RESERVED0_MASK                        0x007c
#define SGMII0_RX3_CONTROL11_RESERVED0_ALIGN                       0
#define SGMII0_RX3_CONTROL11_RESERVED0_BITS                        5
#define SGMII0_RX3_CONTROL11_RESERVED0_SHIFT                       2

/* SGMII0_RX3 :: control11 :: pm_RxSlicerCalByp [01:01] */
#define Wr_SGMII0_RX3_control11_pm_RxSlicerCalByp(x) WriteRegBits16(SGMII0_RX3_CONTROL11,0x2,1,x)
#define Rd_SGMII0_RX3_control11_pm_RxSlicerCalByp(x) ReadRegBits16(SGMII0_RX3_CONTROL11,0x2,1)
#define SGMII0_RX3_CONTROL11_PM_RXSLICERCALBYP_MASK                0x0002
#define SGMII0_RX3_CONTROL11_PM_RXSLICERCALBYP_ALIGN               0
#define SGMII0_RX3_CONTROL11_PM_RXSLICERCALBYP_BITS                1
#define SGMII0_RX3_CONTROL11_PM_RXSLICERCALBYP_SHIFT               1

/* SGMII0_RX3 :: control11 :: pm_RxLimitAmpCalByp [00:00] */
#define Wr_SGMII0_RX3_control11_pm_RxLimitAmpCalByp(x) WriteRegBits16(SGMII0_RX3_CONTROL11,0x1,0,x)
#define Rd_SGMII0_RX3_control11_pm_RxLimitAmpCalByp(x) ReadRegBits16(SGMII0_RX3_CONTROL11,0x1,0)
#define SGMII0_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_MASK              0x0001
#define SGMII0_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_ALIGN             0
#define SGMII0_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_BITS              1
#define SGMII0_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_SHIFT             0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII_aerBlk
 ***************************************************************************/
/****************************************************************************
 * SGMII_aerBlk :: aer
 ***************************************************************************/
/* SGMII_aerBlk :: aer :: MMD_deviceType [15:11] */
#define Wr_SGMII_aerBlk_aer_MMD_deviceType(x) WriteRegBits16(SGMII_AERBLK_AER,0xf800,11,x)
#define Rd_SGMII_aerBlk_aer_MMD_deviceType(x) ReadRegBits16(SGMII_AERBLK_AER,0xf800,11)
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_MASK                       0xf800
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_ALIGN                      0
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_BITS                       5
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_SHIFT                      11
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_combo_core                 0
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_PMA_PMD                    1
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_PCS                        3
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_PHY                        4
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_DTE                        5
#define SGMII_AERBLK_AER_MMD_DEVICETYPE_CL73_AN                    7

/* SGMII_aerBlk :: aer :: MMD_port [10:00] */
#define Wr_SGMII_aerBlk_aer_MMD_port(x) WriteRegBits16(SGMII_AERBLK_AER,0x7ff,0,x)
#define Rd_SGMII_aerBlk_aer_MMD_port(x) ReadRegBits16(SGMII_AERBLK_AER,0x7ff,0)
#define SGMII_AERBLK_AER_MMD_PORT_MASK                             0x07ff
#define SGMII_AERBLK_AER_MMD_PORT_ALIGN                            0
#define SGMII_AERBLK_AER_MMD_PORT_BITS                             11
#define SGMII_AERBLK_AER_MMD_PORT_SHIFT                            0
#define SGMII_AERBLK_AER_MMD_PORT_ln0                              0
#define SGMII_AERBLK_AER_MMD_PORT_ln1                              1
#define SGMII_AERBLK_AER_MMD_PORT_ln2                              2
#define SGMII_AERBLK_AER_MMD_PORT_ln3                              3
#define SGMII_AERBLK_AER_MMD_PORT_BCST                             511


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE0_SGMII0_Combo_IEEE0
 ***************************************************************************/
/****************************************************************************
 * SGMII0_Combo_IEEE0 :: MIICntl
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: MIICntl :: rst_hw [15:15] */
#define Wr_SGMII0_Combo_IEEE0_MIICntl_rst_hw(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x8000,15,x)
#define Rd_SGMII0_Combo_IEEE0_MIICntl_rst_hw(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x8000,15)
#define SGMII0_COMBO_IEEE0_MIICNTL_RST_HW_MASK                     0x8000
#define SGMII0_COMBO_IEEE0_MIICNTL_RST_HW_ALIGN                    0
#define SGMII0_COMBO_IEEE0_MIICNTL_RST_HW_BITS                     1
#define SGMII0_COMBO_IEEE0_MIICNTL_RST_HW_SHIFT                    15

/* SGMII0_Combo_IEEE0 :: MIICntl :: gloopback [14:14] */
#define Wr_SGMII0_Combo_IEEE0_MIICntl_gloopback(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x4000,14,x)
#define Rd_SGMII0_Combo_IEEE0_MIICntl_gloopback(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x4000,14)
#define SGMII0_COMBO_IEEE0_MIICNTL_GLOOPBACK_MASK                  0x4000
#define SGMII0_COMBO_IEEE0_MIICNTL_GLOOPBACK_ALIGN                 0
#define SGMII0_COMBO_IEEE0_MIICNTL_GLOOPBACK_BITS                  1
#define SGMII0_COMBO_IEEE0_MIICNTL_GLOOPBACK_SHIFT                 14

/* SGMII0_Combo_IEEE0 :: MIICntl :: manual_speed0 [13:13] */
#define Wr_SGMII0_Combo_IEEE0_MIICntl_manual_speed0(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x2000,13,x)
#define Rd_SGMII0_Combo_IEEE0_MIICntl_manual_speed0(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x2000,13)
#define SGMII0_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_MASK              0x2000
#define SGMII0_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_ALIGN             0
#define SGMII0_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_BITS              1
#define SGMII0_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_SHIFT             13

/* SGMII0_Combo_IEEE0 :: MIICntl :: autoneg_enable [12:12] */
#define Wr_SGMII0_Combo_IEEE0_MIICntl_autoneg_enable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x1000,12,x)
#define Rd_SGMII0_Combo_IEEE0_MIICntl_autoneg_enable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x1000,12)
#define SGMII0_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_MASK             0x1000
#define SGMII0_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_ALIGN            0
#define SGMII0_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_BITS             1
#define SGMII0_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_SHIFT            12

/* SGMII0_Combo_IEEE0 :: MIICntl :: pwrdwn_sw [11:11] */
#define Wr_SGMII0_Combo_IEEE0_MIICntl_pwrdwn_sw(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x800,11,x)
#define Rd_SGMII0_Combo_IEEE0_MIICntl_pwrdwn_sw(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x800,11)
#define SGMII0_COMBO_IEEE0_MIICNTL_PWRDWN_SW_MASK                  0x0800
#define SGMII0_COMBO_IEEE0_MIICNTL_PWRDWN_SW_ALIGN                 0
#define SGMII0_COMBO_IEEE0_MIICNTL_PWRDWN_SW_BITS                  1
#define SGMII0_COMBO_IEEE0_MIICNTL_PWRDWN_SW_SHIFT                 11

/* SGMII0_Combo_IEEE0 :: MIICntl :: reserved0 [10:10] */
#define SGMII0_COMBO_IEEE0_MIICNTL_RESERVED0_MASK                  0x0400
#define SGMII0_COMBO_IEEE0_MIICNTL_RESERVED0_ALIGN                 0
#define SGMII0_COMBO_IEEE0_MIICNTL_RESERVED0_BITS                  1
#define SGMII0_COMBO_IEEE0_MIICNTL_RESERVED0_SHIFT                 10

/* SGMII0_Combo_IEEE0 :: MIICntl :: restart_autoneg [09:09] */
#define Wr_SGMII0_Combo_IEEE0_MIICntl_restart_autoneg(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x200,9,x)
#define Rd_SGMII0_Combo_IEEE0_MIICntl_restart_autoneg(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x200,9)
#define SGMII0_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_MASK            0x0200
#define SGMII0_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_ALIGN           0
#define SGMII0_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_BITS            1
#define SGMII0_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_SHIFT           9

/* SGMII0_Combo_IEEE0 :: MIICntl :: full_duplex [08:08] */
#define Wr_SGMII0_Combo_IEEE0_MIICntl_full_duplex(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x100,8,x)
#define Rd_SGMII0_Combo_IEEE0_MIICntl_full_duplex(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x100,8)
#define SGMII0_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_MASK                0x0100
#define SGMII0_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_ALIGN               0
#define SGMII0_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_BITS                1
#define SGMII0_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_SHIFT               8

/* SGMII0_Combo_IEEE0 :: MIICntl :: collision_test_en [07:07] */
#define Wr_SGMII0_Combo_IEEE0_MIICntl_collision_test_en(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x80,7,x)
#define Rd_SGMII0_Combo_IEEE0_MIICntl_collision_test_en(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x80,7)
#define SGMII0_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_MASK          0x0080
#define SGMII0_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_ALIGN         0
#define SGMII0_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_BITS          1
#define SGMII0_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_SHIFT         7

/* SGMII0_Combo_IEEE0 :: MIICntl :: manual_speed1 [06:06] */
#define Wr_SGMII0_Combo_IEEE0_MIICntl_manual_speed1(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x40,6,x)
#define Rd_SGMII0_Combo_IEEE0_MIICntl_manual_speed1(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIICNTL,0x40,6)
#define SGMII0_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_MASK              0x0040
#define SGMII0_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_ALIGN             0
#define SGMII0_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_BITS              1
#define SGMII0_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_SHIFT             6

/* SGMII0_Combo_IEEE0 :: MIICntl :: reserved1 [05:00] */
#define SGMII0_COMBO_IEEE0_MIICNTL_RESERVED1_MASK                  0x003f
#define SGMII0_COMBO_IEEE0_MIICNTL_RESERVED1_ALIGN                 0
#define SGMII0_COMBO_IEEE0_MIICNTL_RESERVED1_BITS                  6
#define SGMII0_COMBO_IEEE0_MIICNTL_RESERVED1_SHIFT                 0


/****************************************************************************
 * SGMII0_Combo_IEEE0 :: MIIStat
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: MIIStat :: s100BASE_T4_capable [15:15] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_s100BASE_T4_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x8000,15,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_s100BASE_T4_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x8000,15)
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_MASK        0x8000
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN       0
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_BITS        1
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT       15

/* SGMII0_Combo_IEEE0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x4000,14,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x4000,14)
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14

/* SGMII0_Combo_IEEE0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x2000,13,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x2000,13)
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13

/* SGMII0_Combo_IEEE0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x1000,12,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x1000,12)
#define SGMII0_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x1000
#define SGMII0_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12

/* SGMII0_Combo_IEEE0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x800,11,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x800,11)
#define SGMII0_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x0800
#define SGMII0_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11

/* SGMII0_Combo_IEEE0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x400,10,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x400,10)
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10

/* SGMII0_Combo_IEEE0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x200,9,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x200,9)
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9

/* SGMII0_Combo_IEEE0 :: MIIStat :: extended_status [08:08] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_extended_status(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x100,8,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_extended_status(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x100,8)
#define SGMII0_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_MASK            0x0100
#define SGMII0_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_ALIGN           0
#define SGMII0_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_BITS            1
#define SGMII0_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_SHIFT           8

/* SGMII0_Combo_IEEE0 :: MIIStat :: reserved0 [07:07] */
#define SGMII0_COMBO_IEEE0_MIISTAT_RESERVED0_MASK                  0x0080
#define SGMII0_COMBO_IEEE0_MIISTAT_RESERVED0_ALIGN                 0
#define SGMII0_COMBO_IEEE0_MIISTAT_RESERVED0_BITS                  1
#define SGMII0_COMBO_IEEE0_MIISTAT_RESERVED0_SHIFT                 7

/* SGMII0_Combo_IEEE0 :: MIIStat :: mf_preamble_supression [06:06] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_mf_preamble_supression(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x40,6,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_mf_preamble_supression(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x40,6)
#define SGMII0_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK     0x0040
#define SGMII0_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN    0
#define SGMII0_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS     1
#define SGMII0_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT    6

/* SGMII0_Combo_IEEE0 :: MIIStat :: autoneg_complete [05:05] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_autoneg_complete(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x20,5,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_autoneg_complete(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x20,5)
#define SGMII0_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_MASK           0x0020
#define SGMII0_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_ALIGN          0
#define SGMII0_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_BITS           1
#define SGMII0_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_SHIFT          5

/* SGMII0_Combo_IEEE0 :: MIIStat :: remote_fault [04:04] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_remote_fault(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x10,4,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_remote_fault(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x10,4)
#define SGMII0_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_MASK               0x0010
#define SGMII0_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_ALIGN              0
#define SGMII0_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_BITS               1
#define SGMII0_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_SHIFT              4

/* SGMII0_Combo_IEEE0 :: MIIStat :: autoneg_ability [03:03] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_autoneg_ability(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x8,3,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_autoneg_ability(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x8,3)
#define SGMII0_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_MASK            0x0008
#define SGMII0_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_ALIGN           0
#define SGMII0_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_BITS            1
#define SGMII0_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_SHIFT           3

/* SGMII0_Combo_IEEE0 :: MIIStat :: link_status [02:02] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_link_status(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x4,2,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_link_status(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x4,2)
#define SGMII0_COMBO_IEEE0_MIISTAT_LINK_STATUS_MASK                0x0004
#define SGMII0_COMBO_IEEE0_MIISTAT_LINK_STATUS_ALIGN               0
#define SGMII0_COMBO_IEEE0_MIISTAT_LINK_STATUS_BITS                1
#define SGMII0_COMBO_IEEE0_MIISTAT_LINK_STATUS_SHIFT               2

/* SGMII0_Combo_IEEE0 :: MIIStat :: jabber_detect [01:01] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_jabber_detect(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x2,1,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_jabber_detect(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x2,1)
#define SGMII0_COMBO_IEEE0_MIISTAT_JABBER_DETECT_MASK              0x0002
#define SGMII0_COMBO_IEEE0_MIISTAT_JABBER_DETECT_ALIGN             0
#define SGMII0_COMBO_IEEE0_MIISTAT_JABBER_DETECT_BITS              1
#define SGMII0_COMBO_IEEE0_MIISTAT_JABBER_DETECT_SHIFT             1

/* SGMII0_Combo_IEEE0 :: MIIStat :: extended_capability [00:00] */
#define Wr_SGMII0_Combo_IEEE0_MIIStat_extended_capability(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x1,0,x)
#define Rd_SGMII0_Combo_IEEE0_MIIStat_extended_capability(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIISTAT,0x1,0)
#define SGMII0_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_MASK        0x0001
#define SGMII0_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_ALIGN       0
#define SGMII0_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_BITS        1
#define SGMII0_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_SHIFT       0


/****************************************************************************
 * SGMII0_Combo_IEEE0 :: Id1
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: Id1 :: regid [15:00] */
#define Wr_SGMII0_Combo_IEEE0_Id1_regid(x) WriteReg16(SGMII0_COMBO_IEEE0_ID1,x)
#define Rd_SGMII0_Combo_IEEE0_Id1_regid(x) ReadReg16(SGMII0_COMBO_IEEE0_ID1)
#define SGMII0_COMBO_IEEE0_ID1_REGID_MASK                          0xffff
#define SGMII0_COMBO_IEEE0_ID1_REGID_ALIGN                         0
#define SGMII0_COMBO_IEEE0_ID1_REGID_BITS                          16
#define SGMII0_COMBO_IEEE0_ID1_REGID_SHIFT                         0


/****************************************************************************
 * SGMII0_Combo_IEEE0 :: Id2
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: Id2 :: regid [15:00] */
#define Wr_SGMII0_Combo_IEEE0_Id2_regid(x) WriteReg16(SGMII0_COMBO_IEEE0_ID2,x)
#define Rd_SGMII0_Combo_IEEE0_Id2_regid(x) ReadReg16(SGMII0_COMBO_IEEE0_ID2)
#define SGMII0_COMBO_IEEE0_ID2_REGID_MASK                          0xffff
#define SGMII0_COMBO_IEEE0_ID2_REGID_ALIGN                         0
#define SGMII0_COMBO_IEEE0_ID2_REGID_BITS                          16
#define SGMII0_COMBO_IEEE0_ID2_REGID_SHIFT                         0


/****************************************************************************
 * SGMII0_Combo_IEEE0 :: AutoNegAdv
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: AutoNegAdv :: next_page [15:15] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegAdv_next_page(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x8000,15,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegAdv_next_page(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x8000,15)
#define SGMII0_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_MASK               0x8000
#define SGMII0_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_ALIGN              0
#define SGMII0_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_BITS               1
#define SGMII0_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_SHIFT              15

/* SGMII0_Combo_IEEE0 :: AutoNegAdv :: reserved0 [14:14] */
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED0_MASK               0x4000
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED0_ALIGN              0
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED0_BITS               1
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED0_SHIFT              14

/* SGMII0_Combo_IEEE0 :: AutoNegAdv :: remote_fault [13:12] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegAdv_remote_fault(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x3000,12,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegAdv_remote_fault(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x3000,12)
#define SGMII0_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_MASK            0x3000
#define SGMII0_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_ALIGN           0
#define SGMII0_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_BITS            2
#define SGMII0_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_SHIFT           12

/* SGMII0_Combo_IEEE0 :: AutoNegAdv :: reserved1 [11:09] */
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED1_MASK               0x0e00
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED1_ALIGN              0
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED1_BITS               3
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED1_SHIFT              9

/* SGMII0_Combo_IEEE0 :: AutoNegAdv :: pause [08:07] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegAdv_pause(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x180,7,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegAdv_pause(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x180,7)
#define SGMII0_COMBO_IEEE0_AUTONEGADV_PAUSE_MASK                   0x0180
#define SGMII0_COMBO_IEEE0_AUTONEGADV_PAUSE_ALIGN                  0
#define SGMII0_COMBO_IEEE0_AUTONEGADV_PAUSE_BITS                   2
#define SGMII0_COMBO_IEEE0_AUTONEGADV_PAUSE_SHIFT                  7

/* SGMII0_Combo_IEEE0 :: AutoNegAdv :: half_duplex [06:06] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegAdv_half_duplex(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x40,6,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegAdv_half_duplex(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x40,6)
#define SGMII0_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_MASK             0x0040
#define SGMII0_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_ALIGN            0
#define SGMII0_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_BITS             1
#define SGMII0_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_SHIFT            6

/* SGMII0_Combo_IEEE0 :: AutoNegAdv :: full_duplex [05:05] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegAdv_full_duplex(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x20,5,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegAdv_full_duplex(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGADV,0x20,5)
#define SGMII0_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_MASK             0x0020
#define SGMII0_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_ALIGN            0
#define SGMII0_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_BITS             1
#define SGMII0_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_SHIFT            5

/* SGMII0_Combo_IEEE0 :: AutoNegAdv :: reserved2 [04:00] */
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED2_MASK               0x001f
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED2_ALIGN              0
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED2_BITS               5
#define SGMII0_COMBO_IEEE0_AUTONEGADV_RESERVED2_SHIFT              0


/****************************************************************************
 * SGMII0_Combo_IEEE0 :: AutoNegLPAbil
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil :: next_page [15:15] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil_next_page(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x8000,15,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil_next_page(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x8000,15)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_MASK            0x8000
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_ALIGN           0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_BITS            1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_SHIFT           15

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil :: acknowledge [14:14] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil_acknowledge(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x4000,14,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil_acknowledge(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x4000,14)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_MASK          0x4000
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN         0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_BITS          1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT         14

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil :: remote_fault [13:12] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil_remote_fault(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x3000,12,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil_remote_fault(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x3000,12)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_MASK         0x3000
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN        0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_BITS         2
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT        12

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil :: reserved0 [11:09] */
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_MASK            0x0e00
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_ALIGN           0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_BITS            3
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_SHIFT           9

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil :: pause [08:07] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil_pause(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x180,7,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil_pause(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x180,7)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_MASK                0x0180
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_ALIGN               0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_BITS                2
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_SHIFT               7

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil :: half_duplex [06:06] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil_half_duplex(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x40,6,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil_half_duplex(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x40,6)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_MASK          0x0040
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN         0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_BITS          1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT         6

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil :: full_duplex [05:05] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil_full_duplex(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x20,5,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil_full_duplex(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x20,5)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_MASK          0x0020
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN         0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_BITS          1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT         5

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil :: reserved1 [04:01] */
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_MASK            0x001e
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_ALIGN           0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_BITS            4
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_SHIFT           1

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil :: sgmii_mode [00:00] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil_sgmii_mode(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x1,0,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil_sgmii_mode(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL,0x1,0)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_MASK           0x0001
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_ALIGN          0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_BITS           1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_SHIFT          0


/****************************************************************************
 * SGMII0_Combo_IEEE0 :: AutoNegExp
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: AutoNegExp :: reserved0 [15:03] */
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_RESERVED0_MASK               0xfff8
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_RESERVED0_ALIGN              0
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_RESERVED0_BITS               13
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_RESERVED0_SHIFT              3

/* SGMII0_Combo_IEEE0 :: AutoNegExp :: next_page_ability [02:02] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegExp_next_page_ability(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGEXP,0x4,2,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegExp_next_page_ability(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGEXP,0x4,2)
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK       0x0004
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN      0
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS       1
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT      2

/* SGMII0_Combo_IEEE0 :: AutoNegExp :: page_received [01:01] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegExp_page_received(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGEXP,0x2,1,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegExp_page_received(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGEXP,0x2,1)
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_MASK           0x0002
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_ALIGN          0
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_BITS           1
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_SHIFT          1

/* SGMII0_Combo_IEEE0 :: AutoNegExp :: reserved1 [00:00] */
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_RESERVED1_MASK               0x0001
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_RESERVED1_ALIGN              0
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_RESERVED1_BITS               1
#define SGMII0_COMBO_IEEE0_AUTONEGEXP_RESERVED1_SHIFT              0


/****************************************************************************
 * SGMII0_Combo_IEEE0 :: AutoNegNP
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: AutoNegNP :: Next_Page [15:15] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegNP_Next_Page(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x8000,15,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegNP_Next_Page(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x8000,15)
#define SGMII0_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_MASK                0x8000
#define SGMII0_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_ALIGN               0
#define SGMII0_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_BITS                1
#define SGMII0_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_SHIFT               15

/* SGMII0_Combo_IEEE0 :: AutoNegNP :: Ack [14:14] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegNP_Ack(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x4000,14,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegNP_Ack(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x4000,14)
#define SGMII0_COMBO_IEEE0_AUTONEGNP_ACK_MASK                      0x4000
#define SGMII0_COMBO_IEEE0_AUTONEGNP_ACK_ALIGN                     0
#define SGMII0_COMBO_IEEE0_AUTONEGNP_ACK_BITS                      1
#define SGMII0_COMBO_IEEE0_AUTONEGNP_ACK_SHIFT                     14

/* SGMII0_Combo_IEEE0 :: AutoNegNP :: Message_Page [13:13] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegNP_Message_Page(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x2000,13,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegNP_Message_Page(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x2000,13)
#define SGMII0_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_MASK             0x2000
#define SGMII0_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_ALIGN            0
#define SGMII0_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_BITS             1
#define SGMII0_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_SHIFT            13

/* SGMII0_Combo_IEEE0 :: AutoNegNP :: Ack2 [12:12] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegNP_Ack2(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x1000,12,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegNP_Ack2(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x1000,12)
#define SGMII0_COMBO_IEEE0_AUTONEGNP_ACK2_MASK                     0x1000
#define SGMII0_COMBO_IEEE0_AUTONEGNP_ACK2_ALIGN                    0
#define SGMII0_COMBO_IEEE0_AUTONEGNP_ACK2_BITS                     1
#define SGMII0_COMBO_IEEE0_AUTONEGNP_ACK2_SHIFT                    12

/* SGMII0_Combo_IEEE0 :: AutoNegNP :: Toggle [11:11] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegNP_Toggle(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x800,11,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegNP_Toggle(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x800,11)
#define SGMII0_COMBO_IEEE0_AUTONEGNP_TOGGLE_MASK                   0x0800
#define SGMII0_COMBO_IEEE0_AUTONEGNP_TOGGLE_ALIGN                  0
#define SGMII0_COMBO_IEEE0_AUTONEGNP_TOGGLE_BITS                   1
#define SGMII0_COMBO_IEEE0_AUTONEGNP_TOGGLE_SHIFT                  11

/* SGMII0_Combo_IEEE0 :: AutoNegNP :: Message [10:00] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegNP_Message(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x7ff,0,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegNP_Message(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGNP,0x7ff,0)
#define SGMII0_COMBO_IEEE0_AUTONEGNP_MESSAGE_MASK                  0x07ff
#define SGMII0_COMBO_IEEE0_AUTONEGNP_MESSAGE_ALIGN                 0
#define SGMII0_COMBO_IEEE0_AUTONEGNP_MESSAGE_BITS                  11
#define SGMII0_COMBO_IEEE0_AUTONEGNP_MESSAGE_SHIFT                 0


/****************************************************************************
 * SGMII0_Combo_IEEE0 :: AutoNegLPAbil2
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil2 :: Next_Page [15:15] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Next_Page(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x8000,15,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Next_Page(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x8000,15)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_MASK           0x8000
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN          0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_BITS           1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT          15

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil2 :: Ack [14:14] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Ack(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x4000,14,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Ack(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x4000,14)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_ACK_MASK                 0x4000
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_ACK_ALIGN                0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_ACK_BITS                 1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_ACK_SHIFT                14

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil2 :: Message_Page [13:13] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Message_Page(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x2000,13,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Message_Page(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x2000,13)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK        0x2000
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN       0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS        1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT       13

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil2 :: Ack2 [12:12] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Ack2(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x1000,12,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Ack2(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x1000,12)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_MASK                0x1000
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_ALIGN               0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_BITS                1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_SHIFT               12

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil2 :: Toggle [11:11] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Toggle(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x800,11,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Toggle(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x800,11)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_MASK              0x0800
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_ALIGN             0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_BITS              1
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_SHIFT             11

/* SGMII0_Combo_IEEE0 :: AutoNegLPAbil2 :: Message [10:00] */
#define Wr_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Message(x) WriteRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x7ff,0,x)
#define Rd_SGMII0_Combo_IEEE0_AutoNegLPAbil2_Message(x) ReadRegBits16(SGMII0_COMBO_IEEE0_AUTONEGLPABIL2,0x7ff,0)
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_MASK             0x07ff
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_ALIGN            0
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_BITS             11
#define SGMII0_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_SHIFT            0


/****************************************************************************
 * SGMII0_Combo_IEEE0 :: MIIextStat
 ***************************************************************************/
/* SGMII0_Combo_IEEE0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
#define Wr_SGMII0_Combo_IEEE0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIIEXTSTAT,0x8000,15,x)
#define Rd_SGMII0_Combo_IEEE0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIIEXTSTAT,0x8000,15)
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15

/* SGMII0_Combo_IEEE0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
#define Wr_SGMII0_Combo_IEEE0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIIEXTSTAT,0x4000,14,x)
#define Rd_SGMII0_Combo_IEEE0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIIEXTSTAT,0x4000,14)
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14

/* SGMII0_Combo_IEEE0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
#define Wr_SGMII0_Combo_IEEE0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIIEXTSTAT,0x2000,13,x)
#define Rd_SGMII0_Combo_IEEE0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIIEXTSTAT,0x2000,13)
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13

/* SGMII0_Combo_IEEE0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
#define Wr_SGMII0_Combo_IEEE0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII0_COMBO_IEEE0_MIIEXTSTAT,0x1000,12,x)
#define Rd_SGMII0_Combo_IEEE0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII0_COMBO_IEEE0_MIIEXTSTAT,0x1000,12)
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12

/* SGMII0_Combo_IEEE0 :: MIIextStat :: reserved0 [11:00] */
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_MASK               0x0fff
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_ALIGN              0
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_BITS               12
#define SGMII0_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_SHIFT              0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_CL22_B0
 ***************************************************************************/
/****************************************************************************
 * SGMII1_CL22_B0 :: MIICntl
 ***************************************************************************/
/* SGMII1_CL22_B0 :: MIICntl :: rst_hw [15:15] */
#define Wr_SGMII1_CL22_B0_MIICntl_rst_hw(x) WriteRegBits16(SGMII1_CL22_B0_MIICNTL,0x8000,15,x)
#define Rd_SGMII1_CL22_B0_MIICntl_rst_hw(x) ReadRegBits16(SGMII1_CL22_B0_MIICNTL,0x8000,15)
#define SGMII1_CL22_B0_MIICNTL_RST_HW_MASK                         0x8000
#define SGMII1_CL22_B0_MIICNTL_RST_HW_ALIGN                        0
#define SGMII1_CL22_B0_MIICNTL_RST_HW_BITS                         1
#define SGMII1_CL22_B0_MIICNTL_RST_HW_SHIFT                        15

/* SGMII1_CL22_B0 :: MIICntl :: gloopback [14:14] */
#define Wr_SGMII1_CL22_B0_MIICntl_gloopback(x) WriteRegBits16(SGMII1_CL22_B0_MIICNTL,0x4000,14,x)
#define Rd_SGMII1_CL22_B0_MIICntl_gloopback(x) ReadRegBits16(SGMII1_CL22_B0_MIICNTL,0x4000,14)
#define SGMII1_CL22_B0_MIICNTL_GLOOPBACK_MASK                      0x4000
#define SGMII1_CL22_B0_MIICNTL_GLOOPBACK_ALIGN                     0
#define SGMII1_CL22_B0_MIICNTL_GLOOPBACK_BITS                      1
#define SGMII1_CL22_B0_MIICNTL_GLOOPBACK_SHIFT                     14

/* SGMII1_CL22_B0 :: MIICntl :: manual_speed0 [13:13] */
#define Wr_SGMII1_CL22_B0_MIICntl_manual_speed0(x) WriteRegBits16(SGMII1_CL22_B0_MIICNTL,0x2000,13,x)
#define Rd_SGMII1_CL22_B0_MIICntl_manual_speed0(x) ReadRegBits16(SGMII1_CL22_B0_MIICNTL,0x2000,13)
#define SGMII1_CL22_B0_MIICNTL_MANUAL_SPEED0_MASK                  0x2000
#define SGMII1_CL22_B0_MIICNTL_MANUAL_SPEED0_ALIGN                 0
#define SGMII1_CL22_B0_MIICNTL_MANUAL_SPEED0_BITS                  1
#define SGMII1_CL22_B0_MIICNTL_MANUAL_SPEED0_SHIFT                 13

/* SGMII1_CL22_B0 :: MIICntl :: autoneg_enable [12:12] */
#define Wr_SGMII1_CL22_B0_MIICntl_autoneg_enable(x) WriteRegBits16(SGMII1_CL22_B0_MIICNTL,0x1000,12,x)
#define Rd_SGMII1_CL22_B0_MIICntl_autoneg_enable(x) ReadRegBits16(SGMII1_CL22_B0_MIICNTL,0x1000,12)
#define SGMII1_CL22_B0_MIICNTL_AUTONEG_ENABLE_MASK                 0x1000
#define SGMII1_CL22_B0_MIICNTL_AUTONEG_ENABLE_ALIGN                0
#define SGMII1_CL22_B0_MIICNTL_AUTONEG_ENABLE_BITS                 1
#define SGMII1_CL22_B0_MIICNTL_AUTONEG_ENABLE_SHIFT                12

/* SGMII1_CL22_B0 :: MIICntl :: pwrdwn_sw [11:11] */
#define Wr_SGMII1_CL22_B0_MIICntl_pwrdwn_sw(x) WriteRegBits16(SGMII1_CL22_B0_MIICNTL,0x800,11,x)
#define Rd_SGMII1_CL22_B0_MIICntl_pwrdwn_sw(x) ReadRegBits16(SGMII1_CL22_B0_MIICNTL,0x800,11)
#define SGMII1_CL22_B0_MIICNTL_PWRDWN_SW_MASK                      0x0800
#define SGMII1_CL22_B0_MIICNTL_PWRDWN_SW_ALIGN                     0
#define SGMII1_CL22_B0_MIICNTL_PWRDWN_SW_BITS                      1
#define SGMII1_CL22_B0_MIICNTL_PWRDWN_SW_SHIFT                     11

/* SGMII1_CL22_B0 :: MIICntl :: reserved0 [10:10] */
#define SGMII1_CL22_B0_MIICNTL_RESERVED0_MASK                      0x0400
#define SGMII1_CL22_B0_MIICNTL_RESERVED0_ALIGN                     0
#define SGMII1_CL22_B0_MIICNTL_RESERVED0_BITS                      1
#define SGMII1_CL22_B0_MIICNTL_RESERVED0_SHIFT                     10

/* SGMII1_CL22_B0 :: MIICntl :: restart_autoneg [09:09] */
#define Wr_SGMII1_CL22_B0_MIICntl_restart_autoneg(x) WriteRegBits16(SGMII1_CL22_B0_MIICNTL,0x200,9,x)
#define Rd_SGMII1_CL22_B0_MIICntl_restart_autoneg(x) ReadRegBits16(SGMII1_CL22_B0_MIICNTL,0x200,9)
#define SGMII1_CL22_B0_MIICNTL_RESTART_AUTONEG_MASK                0x0200
#define SGMII1_CL22_B0_MIICNTL_RESTART_AUTONEG_ALIGN               0
#define SGMII1_CL22_B0_MIICNTL_RESTART_AUTONEG_BITS                1
#define SGMII1_CL22_B0_MIICNTL_RESTART_AUTONEG_SHIFT               9

/* SGMII1_CL22_B0 :: MIICntl :: full_duplex [08:08] */
#define Wr_SGMII1_CL22_B0_MIICntl_full_duplex(x) WriteRegBits16(SGMII1_CL22_B0_MIICNTL,0x100,8,x)
#define Rd_SGMII1_CL22_B0_MIICntl_full_duplex(x) ReadRegBits16(SGMII1_CL22_B0_MIICNTL,0x100,8)
#define SGMII1_CL22_B0_MIICNTL_FULL_DUPLEX_MASK                    0x0100
#define SGMII1_CL22_B0_MIICNTL_FULL_DUPLEX_ALIGN                   0
#define SGMII1_CL22_B0_MIICNTL_FULL_DUPLEX_BITS                    1
#define SGMII1_CL22_B0_MIICNTL_FULL_DUPLEX_SHIFT                   8

/* SGMII1_CL22_B0 :: MIICntl :: collision_test_en [07:07] */
#define Wr_SGMII1_CL22_B0_MIICntl_collision_test_en(x) WriteRegBits16(SGMII1_CL22_B0_MIICNTL,0x80,7,x)
#define Rd_SGMII1_CL22_B0_MIICntl_collision_test_en(x) ReadRegBits16(SGMII1_CL22_B0_MIICNTL,0x80,7)
#define SGMII1_CL22_B0_MIICNTL_COLLISION_TEST_EN_MASK              0x0080
#define SGMII1_CL22_B0_MIICNTL_COLLISION_TEST_EN_ALIGN             0
#define SGMII1_CL22_B0_MIICNTL_COLLISION_TEST_EN_BITS              1
#define SGMII1_CL22_B0_MIICNTL_COLLISION_TEST_EN_SHIFT             7

/* SGMII1_CL22_B0 :: MIICntl :: manual_speed1 [06:06] */
#define Wr_SGMII1_CL22_B0_MIICntl_manual_speed1(x) WriteRegBits16(SGMII1_CL22_B0_MIICNTL,0x40,6,x)
#define Rd_SGMII1_CL22_B0_MIICntl_manual_speed1(x) ReadRegBits16(SGMII1_CL22_B0_MIICNTL,0x40,6)
#define SGMII1_CL22_B0_MIICNTL_MANUAL_SPEED1_MASK                  0x0040
#define SGMII1_CL22_B0_MIICNTL_MANUAL_SPEED1_ALIGN                 0
#define SGMII1_CL22_B0_MIICNTL_MANUAL_SPEED1_BITS                  1
#define SGMII1_CL22_B0_MIICNTL_MANUAL_SPEED1_SHIFT                 6

/* SGMII1_CL22_B0 :: MIICntl :: reserved1 [05:00] */
#define SGMII1_CL22_B0_MIICNTL_RESERVED1_MASK                      0x003f
#define SGMII1_CL22_B0_MIICNTL_RESERVED1_ALIGN                     0
#define SGMII1_CL22_B0_MIICNTL_RESERVED1_BITS                      6
#define SGMII1_CL22_B0_MIICNTL_RESERVED1_SHIFT                     0


/****************************************************************************
 * SGMII1_CL22_B0 :: MIIStat
 ***************************************************************************/
/* SGMII1_CL22_B0 :: MIIStat :: s100BASE_T4_capable [15:15] */
#define Wr_SGMII1_CL22_B0_MIIStat_s100BASE_T4_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x8000,15,x)
#define Rd_SGMII1_CL22_B0_MIIStat_s100BASE_T4_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x8000,15)
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_MASK            0x8000
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN           0
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_BITS            1
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT           15

/* SGMII1_CL22_B0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
#define Wr_SGMII1_CL22_B0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x4000,14,x)
#define Rd_SGMII1_CL22_B0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x4000,14)
#define SGMII1_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII1_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII1_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14

/* SGMII1_CL22_B0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
#define Wr_SGMII1_CL22_B0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x2000,13,x)
#define Rd_SGMII1_CL22_B0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x2000,13)
#define SGMII1_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII1_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII1_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13

/* SGMII1_CL22_B0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
#define Wr_SGMII1_CL22_B0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x1000,12,x)
#define Rd_SGMII1_CL22_B0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x1000,12)
#define SGMII1_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK  0x1000
#define SGMII1_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS  1
#define SGMII1_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12

/* SGMII1_CL22_B0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
#define Wr_SGMII1_CL22_B0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x800,11,x)
#define Rd_SGMII1_CL22_B0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x800,11)
#define SGMII1_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK  0x0800
#define SGMII1_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS  1
#define SGMII1_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11

/* SGMII1_CL22_B0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
#define Wr_SGMII1_CL22_B0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x400,10,x)
#define Rd_SGMII1_CL22_B0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x400,10)
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10

/* SGMII1_CL22_B0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
#define Wr_SGMII1_CL22_B0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x200,9,x)
#define Rd_SGMII1_CL22_B0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x200,9)
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII1_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9

/* SGMII1_CL22_B0 :: MIIStat :: extended_status [08:08] */
#define Wr_SGMII1_CL22_B0_MIIStat_extended_status(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x100,8,x)
#define Rd_SGMII1_CL22_B0_MIIStat_extended_status(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x100,8)
#define SGMII1_CL22_B0_MIISTAT_EXTENDED_STATUS_MASK                0x0100
#define SGMII1_CL22_B0_MIISTAT_EXTENDED_STATUS_ALIGN               0
#define SGMII1_CL22_B0_MIISTAT_EXTENDED_STATUS_BITS                1
#define SGMII1_CL22_B0_MIISTAT_EXTENDED_STATUS_SHIFT               8

/* SGMII1_CL22_B0 :: MIIStat :: reserved0 [07:07] */
#define SGMII1_CL22_B0_MIISTAT_RESERVED0_MASK                      0x0080
#define SGMII1_CL22_B0_MIISTAT_RESERVED0_ALIGN                     0
#define SGMII1_CL22_B0_MIISTAT_RESERVED0_BITS                      1
#define SGMII1_CL22_B0_MIISTAT_RESERVED0_SHIFT                     7

/* SGMII1_CL22_B0 :: MIIStat :: mf_preamble_supression [06:06] */
#define Wr_SGMII1_CL22_B0_MIIStat_mf_preamble_supression(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x40,6,x)
#define Rd_SGMII1_CL22_B0_MIIStat_mf_preamble_supression(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x40,6)
#define SGMII1_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK         0x0040
#define SGMII1_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN        0
#define SGMII1_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS         1
#define SGMII1_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT        6

/* SGMII1_CL22_B0 :: MIIStat :: autoneg_complete [05:05] */
#define Wr_SGMII1_CL22_B0_MIIStat_autoneg_complete(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x20,5,x)
#define Rd_SGMII1_CL22_B0_MIIStat_autoneg_complete(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x20,5)
#define SGMII1_CL22_B0_MIISTAT_AUTONEG_COMPLETE_MASK               0x0020
#define SGMII1_CL22_B0_MIISTAT_AUTONEG_COMPLETE_ALIGN              0
#define SGMII1_CL22_B0_MIISTAT_AUTONEG_COMPLETE_BITS               1
#define SGMII1_CL22_B0_MIISTAT_AUTONEG_COMPLETE_SHIFT              5

/* SGMII1_CL22_B0 :: MIIStat :: remote_fault [04:04] */
#define Wr_SGMII1_CL22_B0_MIIStat_remote_fault(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x10,4,x)
#define Rd_SGMII1_CL22_B0_MIIStat_remote_fault(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x10,4)
#define SGMII1_CL22_B0_MIISTAT_REMOTE_FAULT_MASK                   0x0010
#define SGMII1_CL22_B0_MIISTAT_REMOTE_FAULT_ALIGN                  0
#define SGMII1_CL22_B0_MIISTAT_REMOTE_FAULT_BITS                   1
#define SGMII1_CL22_B0_MIISTAT_REMOTE_FAULT_SHIFT                  4

/* SGMII1_CL22_B0 :: MIIStat :: autoneg_ability [03:03] */
#define Wr_SGMII1_CL22_B0_MIIStat_autoneg_ability(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x8,3,x)
#define Rd_SGMII1_CL22_B0_MIIStat_autoneg_ability(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x8,3)
#define SGMII1_CL22_B0_MIISTAT_AUTONEG_ABILITY_MASK                0x0008
#define SGMII1_CL22_B0_MIISTAT_AUTONEG_ABILITY_ALIGN               0
#define SGMII1_CL22_B0_MIISTAT_AUTONEG_ABILITY_BITS                1
#define SGMII1_CL22_B0_MIISTAT_AUTONEG_ABILITY_SHIFT               3

/* SGMII1_CL22_B0 :: MIIStat :: link_status [02:02] */
#define Wr_SGMII1_CL22_B0_MIIStat_link_status(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x4,2,x)
#define Rd_SGMII1_CL22_B0_MIIStat_link_status(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x4,2)
#define SGMII1_CL22_B0_MIISTAT_LINK_STATUS_MASK                    0x0004
#define SGMII1_CL22_B0_MIISTAT_LINK_STATUS_ALIGN                   0
#define SGMII1_CL22_B0_MIISTAT_LINK_STATUS_BITS                    1
#define SGMII1_CL22_B0_MIISTAT_LINK_STATUS_SHIFT                   2

/* SGMII1_CL22_B0 :: MIIStat :: jabber_detect [01:01] */
#define Wr_SGMII1_CL22_B0_MIIStat_jabber_detect(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x2,1,x)
#define Rd_SGMII1_CL22_B0_MIIStat_jabber_detect(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x2,1)
#define SGMII1_CL22_B0_MIISTAT_JABBER_DETECT_MASK                  0x0002
#define SGMII1_CL22_B0_MIISTAT_JABBER_DETECT_ALIGN                 0
#define SGMII1_CL22_B0_MIISTAT_JABBER_DETECT_BITS                  1
#define SGMII1_CL22_B0_MIISTAT_JABBER_DETECT_SHIFT                 1

/* SGMII1_CL22_B0 :: MIIStat :: extended_capability [00:00] */
#define Wr_SGMII1_CL22_B0_MIIStat_extended_capability(x) WriteRegBits16(SGMII1_CL22_B0_MIISTAT,0x1,0,x)
#define Rd_SGMII1_CL22_B0_MIIStat_extended_capability(x) ReadRegBits16(SGMII1_CL22_B0_MIISTAT,0x1,0)
#define SGMII1_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_MASK            0x0001
#define SGMII1_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_ALIGN           0
#define SGMII1_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_BITS            1
#define SGMII1_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_SHIFT           0


/****************************************************************************
 * SGMII1_CL22_B0 :: Id1
 ***************************************************************************/
/* SGMII1_CL22_B0 :: Id1 :: regid [15:00] */
#define Wr_SGMII1_CL22_B0_Id1_regid(x) WriteReg16(SGMII1_CL22_B0_ID1,x)
#define Rd_SGMII1_CL22_B0_Id1_regid(x) ReadReg16(SGMII1_CL22_B0_ID1)
#define SGMII1_CL22_B0_ID1_REGID_MASK                              0xffff
#define SGMII1_CL22_B0_ID1_REGID_ALIGN                             0
#define SGMII1_CL22_B0_ID1_REGID_BITS                              16
#define SGMII1_CL22_B0_ID1_REGID_SHIFT                             0


/****************************************************************************
 * SGMII1_CL22_B0 :: Id2
 ***************************************************************************/
/* SGMII1_CL22_B0 :: Id2 :: regid [15:00] */
#define Wr_SGMII1_CL22_B0_Id2_regid(x) WriteReg16(SGMII1_CL22_B0_ID2,x)
#define Rd_SGMII1_CL22_B0_Id2_regid(x) ReadReg16(SGMII1_CL22_B0_ID2)
#define SGMII1_CL22_B0_ID2_REGID_MASK                              0xffff
#define SGMII1_CL22_B0_ID2_REGID_ALIGN                             0
#define SGMII1_CL22_B0_ID2_REGID_BITS                              16
#define SGMII1_CL22_B0_ID2_REGID_SHIFT                             0


/****************************************************************************
 * SGMII1_CL22_B0 :: AutoNegAdv
 ***************************************************************************/
/* SGMII1_CL22_B0 :: AutoNegAdv :: next_page [15:15] */
#define Wr_SGMII1_CL22_B0_AutoNegAdv_next_page(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x8000,15,x)
#define Rd_SGMII1_CL22_B0_AutoNegAdv_next_page(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x8000,15)
#define SGMII1_CL22_B0_AUTONEGADV_NEXT_PAGE_MASK                   0x8000
#define SGMII1_CL22_B0_AUTONEGADV_NEXT_PAGE_ALIGN                  0
#define SGMII1_CL22_B0_AUTONEGADV_NEXT_PAGE_BITS                   1
#define SGMII1_CL22_B0_AUTONEGADV_NEXT_PAGE_SHIFT                  15

/* SGMII1_CL22_B0 :: AutoNegAdv :: reserved0 [14:14] */
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED0_MASK                   0x4000
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED0_ALIGN                  0
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED0_BITS                   1
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED0_SHIFT                  14

/* SGMII1_CL22_B0 :: AutoNegAdv :: remote_fault [13:12] */
#define Wr_SGMII1_CL22_B0_AutoNegAdv_remote_fault(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x3000,12,x)
#define Rd_SGMII1_CL22_B0_AutoNegAdv_remote_fault(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x3000,12)
#define SGMII1_CL22_B0_AUTONEGADV_REMOTE_FAULT_MASK                0x3000
#define SGMII1_CL22_B0_AUTONEGADV_REMOTE_FAULT_ALIGN               0
#define SGMII1_CL22_B0_AUTONEGADV_REMOTE_FAULT_BITS                2
#define SGMII1_CL22_B0_AUTONEGADV_REMOTE_FAULT_SHIFT               12

/* SGMII1_CL22_B0 :: AutoNegAdv :: reserved1 [11:09] */
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED1_MASK                   0x0e00
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED1_ALIGN                  0
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED1_BITS                   3
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED1_SHIFT                  9

/* SGMII1_CL22_B0 :: AutoNegAdv :: pause [08:07] */
#define Wr_SGMII1_CL22_B0_AutoNegAdv_pause(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x180,7,x)
#define Rd_SGMII1_CL22_B0_AutoNegAdv_pause(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x180,7)
#define SGMII1_CL22_B0_AUTONEGADV_PAUSE_MASK                       0x0180
#define SGMII1_CL22_B0_AUTONEGADV_PAUSE_ALIGN                      0
#define SGMII1_CL22_B0_AUTONEGADV_PAUSE_BITS                       2
#define SGMII1_CL22_B0_AUTONEGADV_PAUSE_SHIFT                      7

/* SGMII1_CL22_B0 :: AutoNegAdv :: half_duplex [06:06] */
#define Wr_SGMII1_CL22_B0_AutoNegAdv_half_duplex(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x40,6,x)
#define Rd_SGMII1_CL22_B0_AutoNegAdv_half_duplex(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x40,6)
#define SGMII1_CL22_B0_AUTONEGADV_HALF_DUPLEX_MASK                 0x0040
#define SGMII1_CL22_B0_AUTONEGADV_HALF_DUPLEX_ALIGN                0
#define SGMII1_CL22_B0_AUTONEGADV_HALF_DUPLEX_BITS                 1
#define SGMII1_CL22_B0_AUTONEGADV_HALF_DUPLEX_SHIFT                6

/* SGMII1_CL22_B0 :: AutoNegAdv :: full_duplex [05:05] */
#define Wr_SGMII1_CL22_B0_AutoNegAdv_full_duplex(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x20,5,x)
#define Rd_SGMII1_CL22_B0_AutoNegAdv_full_duplex(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGADV,0x20,5)
#define SGMII1_CL22_B0_AUTONEGADV_FULL_DUPLEX_MASK                 0x0020
#define SGMII1_CL22_B0_AUTONEGADV_FULL_DUPLEX_ALIGN                0
#define SGMII1_CL22_B0_AUTONEGADV_FULL_DUPLEX_BITS                 1
#define SGMII1_CL22_B0_AUTONEGADV_FULL_DUPLEX_SHIFT                5

/* SGMII1_CL22_B0 :: AutoNegAdv :: reserved2 [04:00] */
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED2_MASK                   0x001f
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED2_ALIGN                  0
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED2_BITS                   5
#define SGMII1_CL22_B0_AUTONEGADV_RESERVED2_SHIFT                  0


/****************************************************************************
 * SGMII1_CL22_B0 :: AutoNegLPAbil
 ***************************************************************************/
/* SGMII1_CL22_B0 :: AutoNegLPAbil :: next_page [15:15] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil_next_page(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x8000,15,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil_next_page(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x8000,15)
#define SGMII1_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_MASK                0x8000
#define SGMII1_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_ALIGN               0
#define SGMII1_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_BITS                1
#define SGMII1_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_SHIFT               15

/* SGMII1_CL22_B0 :: AutoNegLPAbil :: acknowledge [14:14] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil_acknowledge(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x4000,14,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil_acknowledge(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x4000,14)
#define SGMII1_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_MASK              0x4000
#define SGMII1_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN             0
#define SGMII1_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_BITS              1
#define SGMII1_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT             14

/* SGMII1_CL22_B0 :: AutoNegLPAbil :: remote_fault [13:12] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil_remote_fault(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x3000,12,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil_remote_fault(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x3000,12)
#define SGMII1_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_MASK             0x3000
#define SGMII1_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN            0
#define SGMII1_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_BITS             2
#define SGMII1_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT            12

/* SGMII1_CL22_B0 :: AutoNegLPAbil :: reserved0 [11:09] */
#define SGMII1_CL22_B0_AUTONEGLPABIL_RESERVED0_MASK                0x0e00
#define SGMII1_CL22_B0_AUTONEGLPABIL_RESERVED0_ALIGN               0
#define SGMII1_CL22_B0_AUTONEGLPABIL_RESERVED0_BITS                3
#define SGMII1_CL22_B0_AUTONEGLPABIL_RESERVED0_SHIFT               9

/* SGMII1_CL22_B0 :: AutoNegLPAbil :: pause [08:07] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil_pause(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x180,7,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil_pause(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x180,7)
#define SGMII1_CL22_B0_AUTONEGLPABIL_PAUSE_MASK                    0x0180
#define SGMII1_CL22_B0_AUTONEGLPABIL_PAUSE_ALIGN                   0
#define SGMII1_CL22_B0_AUTONEGLPABIL_PAUSE_BITS                    2
#define SGMII1_CL22_B0_AUTONEGLPABIL_PAUSE_SHIFT                   7

/* SGMII1_CL22_B0 :: AutoNegLPAbil :: half_duplex [06:06] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil_half_duplex(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x40,6,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil_half_duplex(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x40,6)
#define SGMII1_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_MASK              0x0040
#define SGMII1_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN             0
#define SGMII1_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_BITS              1
#define SGMII1_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT             6

/* SGMII1_CL22_B0 :: AutoNegLPAbil :: full_duplex [05:05] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil_full_duplex(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x20,5,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil_full_duplex(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x20,5)
#define SGMII1_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_MASK              0x0020
#define SGMII1_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN             0
#define SGMII1_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_BITS              1
#define SGMII1_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT             5

/* SGMII1_CL22_B0 :: AutoNegLPAbil :: reserved1 [04:01] */
#define SGMII1_CL22_B0_AUTONEGLPABIL_RESERVED1_MASK                0x001e
#define SGMII1_CL22_B0_AUTONEGLPABIL_RESERVED1_ALIGN               0
#define SGMII1_CL22_B0_AUTONEGLPABIL_RESERVED1_BITS                4
#define SGMII1_CL22_B0_AUTONEGLPABIL_RESERVED1_SHIFT               1

/* SGMII1_CL22_B0 :: AutoNegLPAbil :: sgmii_mode [00:00] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil_sgmii_mode(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x1,0,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil_sgmii_mode(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL,0x1,0)
#define SGMII1_CL22_B0_AUTONEGLPABIL_SGMII_MODE_MASK               0x0001
#define SGMII1_CL22_B0_AUTONEGLPABIL_SGMII_MODE_ALIGN              0
#define SGMII1_CL22_B0_AUTONEGLPABIL_SGMII_MODE_BITS               1
#define SGMII1_CL22_B0_AUTONEGLPABIL_SGMII_MODE_SHIFT              0


/****************************************************************************
 * SGMII1_CL22_B0 :: AutoNegExp
 ***************************************************************************/
/* SGMII1_CL22_B0 :: AutoNegExp :: reserved0 [15:03] */
#define SGMII1_CL22_B0_AUTONEGEXP_RESERVED0_MASK                   0xfff8
#define SGMII1_CL22_B0_AUTONEGEXP_RESERVED0_ALIGN                  0
#define SGMII1_CL22_B0_AUTONEGEXP_RESERVED0_BITS                   13
#define SGMII1_CL22_B0_AUTONEGEXP_RESERVED0_SHIFT                  3

/* SGMII1_CL22_B0 :: AutoNegExp :: next_page_ability [02:02] */
#define Wr_SGMII1_CL22_B0_AutoNegExp_next_page_ability(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGEXP,0x4,2,x)
#define Rd_SGMII1_CL22_B0_AutoNegExp_next_page_ability(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGEXP,0x4,2)
#define SGMII1_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK           0x0004
#define SGMII1_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN          0
#define SGMII1_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS           1
#define SGMII1_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT          2

/* SGMII1_CL22_B0 :: AutoNegExp :: page_received [01:01] */
#define Wr_SGMII1_CL22_B0_AutoNegExp_page_received(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGEXP,0x2,1,x)
#define Rd_SGMII1_CL22_B0_AutoNegExp_page_received(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGEXP,0x2,1)
#define SGMII1_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_MASK               0x0002
#define SGMII1_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_ALIGN              0
#define SGMII1_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_BITS               1
#define SGMII1_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_SHIFT              1

/* SGMII1_CL22_B0 :: AutoNegExp :: reserved1 [00:00] */
#define SGMII1_CL22_B0_AUTONEGEXP_RESERVED1_MASK                   0x0001
#define SGMII1_CL22_B0_AUTONEGEXP_RESERVED1_ALIGN                  0
#define SGMII1_CL22_B0_AUTONEGEXP_RESERVED1_BITS                   1
#define SGMII1_CL22_B0_AUTONEGEXP_RESERVED1_SHIFT                  0


/****************************************************************************
 * SGMII1_CL22_B0 :: AutoNegNP
 ***************************************************************************/
/* SGMII1_CL22_B0 :: AutoNegNP :: Next_Page [15:15] */
#define Wr_SGMII1_CL22_B0_AutoNegNP_Next_Page(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x8000,15,x)
#define Rd_SGMII1_CL22_B0_AutoNegNP_Next_Page(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x8000,15)
#define SGMII1_CL22_B0_AUTONEGNP_NEXT_PAGE_MASK                    0x8000
#define SGMII1_CL22_B0_AUTONEGNP_NEXT_PAGE_ALIGN                   0
#define SGMII1_CL22_B0_AUTONEGNP_NEXT_PAGE_BITS                    1
#define SGMII1_CL22_B0_AUTONEGNP_NEXT_PAGE_SHIFT                   15

/* SGMII1_CL22_B0 :: AutoNegNP :: Ack [14:14] */
#define Wr_SGMII1_CL22_B0_AutoNegNP_Ack(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x4000,14,x)
#define Rd_SGMII1_CL22_B0_AutoNegNP_Ack(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x4000,14)
#define SGMII1_CL22_B0_AUTONEGNP_ACK_MASK                          0x4000
#define SGMII1_CL22_B0_AUTONEGNP_ACK_ALIGN                         0
#define SGMII1_CL22_B0_AUTONEGNP_ACK_BITS                          1
#define SGMII1_CL22_B0_AUTONEGNP_ACK_SHIFT                         14

/* SGMII1_CL22_B0 :: AutoNegNP :: Message_Page [13:13] */
#define Wr_SGMII1_CL22_B0_AutoNegNP_Message_Page(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x2000,13,x)
#define Rd_SGMII1_CL22_B0_AutoNegNP_Message_Page(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x2000,13)
#define SGMII1_CL22_B0_AUTONEGNP_MESSAGE_PAGE_MASK                 0x2000
#define SGMII1_CL22_B0_AUTONEGNP_MESSAGE_PAGE_ALIGN                0
#define SGMII1_CL22_B0_AUTONEGNP_MESSAGE_PAGE_BITS                 1
#define SGMII1_CL22_B0_AUTONEGNP_MESSAGE_PAGE_SHIFT                13

/* SGMII1_CL22_B0 :: AutoNegNP :: Ack2 [12:12] */
#define Wr_SGMII1_CL22_B0_AutoNegNP_Ack2(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x1000,12,x)
#define Rd_SGMII1_CL22_B0_AutoNegNP_Ack2(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x1000,12)
#define SGMII1_CL22_B0_AUTONEGNP_ACK2_MASK                         0x1000
#define SGMII1_CL22_B0_AUTONEGNP_ACK2_ALIGN                        0
#define SGMII1_CL22_B0_AUTONEGNP_ACK2_BITS                         1
#define SGMII1_CL22_B0_AUTONEGNP_ACK2_SHIFT                        12

/* SGMII1_CL22_B0 :: AutoNegNP :: Toggle [11:11] */
#define Wr_SGMII1_CL22_B0_AutoNegNP_Toggle(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x800,11,x)
#define Rd_SGMII1_CL22_B0_AutoNegNP_Toggle(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x800,11)
#define SGMII1_CL22_B0_AUTONEGNP_TOGGLE_MASK                       0x0800
#define SGMII1_CL22_B0_AUTONEGNP_TOGGLE_ALIGN                      0
#define SGMII1_CL22_B0_AUTONEGNP_TOGGLE_BITS                       1
#define SGMII1_CL22_B0_AUTONEGNP_TOGGLE_SHIFT                      11

/* SGMII1_CL22_B0 :: AutoNegNP :: Message [10:00] */
#define Wr_SGMII1_CL22_B0_AutoNegNP_Message(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x7ff,0,x)
#define Rd_SGMII1_CL22_B0_AutoNegNP_Message(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGNP,0x7ff,0)
#define SGMII1_CL22_B0_AUTONEGNP_MESSAGE_MASK                      0x07ff
#define SGMII1_CL22_B0_AUTONEGNP_MESSAGE_ALIGN                     0
#define SGMII1_CL22_B0_AUTONEGNP_MESSAGE_BITS                      11
#define SGMII1_CL22_B0_AUTONEGNP_MESSAGE_SHIFT                     0


/****************************************************************************
 * SGMII1_CL22_B0 :: AutoNegLPAbil2
 ***************************************************************************/
/* SGMII1_CL22_B0 :: AutoNegLPAbil2 :: Next_Page [15:15] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil2_Next_Page(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x8000,15,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil2_Next_Page(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x8000,15)
#define SGMII1_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_MASK               0x8000
#define SGMII1_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN              0
#define SGMII1_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_BITS               1
#define SGMII1_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT              15

/* SGMII1_CL22_B0 :: AutoNegLPAbil2 :: Ack [14:14] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil2_Ack(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x4000,14,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil2_Ack(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x4000,14)
#define SGMII1_CL22_B0_AUTONEGLPABIL2_ACK_MASK                     0x4000
#define SGMII1_CL22_B0_AUTONEGLPABIL2_ACK_ALIGN                    0
#define SGMII1_CL22_B0_AUTONEGLPABIL2_ACK_BITS                     1
#define SGMII1_CL22_B0_AUTONEGLPABIL2_ACK_SHIFT                    14

/* SGMII1_CL22_B0 :: AutoNegLPAbil2 :: Message_Page [13:13] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil2_Message_Page(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x2000,13,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil2_Message_Page(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x2000,13)
#define SGMII1_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK            0x2000
#define SGMII1_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN           0
#define SGMII1_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS            1
#define SGMII1_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT           13

/* SGMII1_CL22_B0 :: AutoNegLPAbil2 :: Ack2 [12:12] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil2_Ack2(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x1000,12,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil2_Ack2(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x1000,12)
#define SGMII1_CL22_B0_AUTONEGLPABIL2_ACK2_MASK                    0x1000
#define SGMII1_CL22_B0_AUTONEGLPABIL2_ACK2_ALIGN                   0
#define SGMII1_CL22_B0_AUTONEGLPABIL2_ACK2_BITS                    1
#define SGMII1_CL22_B0_AUTONEGLPABIL2_ACK2_SHIFT                   12

/* SGMII1_CL22_B0 :: AutoNegLPAbil2 :: Toggle [11:11] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil2_Toggle(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x800,11,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil2_Toggle(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x800,11)
#define SGMII1_CL22_B0_AUTONEGLPABIL2_TOGGLE_MASK                  0x0800
#define SGMII1_CL22_B0_AUTONEGLPABIL2_TOGGLE_ALIGN                 0
#define SGMII1_CL22_B0_AUTONEGLPABIL2_TOGGLE_BITS                  1
#define SGMII1_CL22_B0_AUTONEGLPABIL2_TOGGLE_SHIFT                 11

/* SGMII1_CL22_B0 :: AutoNegLPAbil2 :: Message [10:00] */
#define Wr_SGMII1_CL22_B0_AutoNegLPAbil2_Message(x) WriteRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x7ff,0,x)
#define Rd_SGMII1_CL22_B0_AutoNegLPAbil2_Message(x) ReadRegBits16(SGMII1_CL22_B0_AUTONEGLPABIL2,0x7ff,0)
#define SGMII1_CL22_B0_AUTONEGLPABIL2_MESSAGE_MASK                 0x07ff
#define SGMII1_CL22_B0_AUTONEGLPABIL2_MESSAGE_ALIGN                0
#define SGMII1_CL22_B0_AUTONEGLPABIL2_MESSAGE_BITS                 11
#define SGMII1_CL22_B0_AUTONEGLPABIL2_MESSAGE_SHIFT                0


/****************************************************************************
 * SGMII1_CL22_B0 :: MIIextStat
 ***************************************************************************/
/* SGMII1_CL22_B0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
#define Wr_SGMII1_CL22_B0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIIEXTSTAT,0x8000,15,x)
#define Rd_SGMII1_CL22_B0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIIEXTSTAT,0x8000,15)
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15

/* SGMII1_CL22_B0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
#define Wr_SGMII1_CL22_B0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIIEXTSTAT,0x4000,14,x)
#define Rd_SGMII1_CL22_B0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIIEXTSTAT,0x4000,14)
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14

/* SGMII1_CL22_B0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
#define Wr_SGMII1_CL22_B0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIIEXTSTAT,0x2000,13,x)
#define Rd_SGMII1_CL22_B0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIIEXTSTAT,0x2000,13)
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13

/* SGMII1_CL22_B0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
#define Wr_SGMII1_CL22_B0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_CL22_B0_MIIEXTSTAT,0x1000,12,x)
#define Rd_SGMII1_CL22_B0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_CL22_B0_MIIEXTSTAT,0x1000,12)
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII1_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12

/* SGMII1_CL22_B0 :: MIIextStat :: reserved0 [11:00] */
#define SGMII1_CL22_B0_MIIEXTSTAT_RESERVED0_MASK                   0x0fff
#define SGMII1_CL22_B0_MIIEXTSTAT_RESERVED0_ALIGN                  0
#define SGMII1_CL22_B0_MIIEXTSTAT_RESERVED0_BITS                   12
#define SGMII1_CL22_B0_MIIEXTSTAT_RESERVED0_SHIFT                  0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_TX_afe
 ***************************************************************************/
/****************************************************************************
 * SGMII1_TX_afe :: anaTxAStatus0
 ***************************************************************************/
/* SGMII1_TX_afe :: anaTxAStatus0 :: reserved0 [15:07] */
#define SGMII1_TX_AFE_ANATXASTATUS0_RESERVED0_MASK                 0xff80
#define SGMII1_TX_AFE_ANATXASTATUS0_RESERVED0_ALIGN                0
#define SGMII1_TX_AFE_ANATXASTATUS0_RESERVED0_BITS                 9
#define SGMII1_TX_AFE_ANATXASTATUS0_RESERVED0_SHIFT                7

/* SGMII1_TX_afe :: anaTxAStatus0 :: txdisable_ln [06:06] */
#define Wr_SGMII1_TX_afe_anaTxAStatus0_txdisable_ln(x) WriteRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x40,6,x)
#define Rd_SGMII1_TX_afe_anaTxAStatus0_txdisable_ln(x) ReadRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x40,6)
#define SGMII1_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_MASK              0x0040
#define SGMII1_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_ALIGN             0
#define SGMII1_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_BITS              1
#define SGMII1_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_SHIFT             6

/* SGMII1_TX_afe :: anaTxAStatus0 :: txferr_stky [05:05] */
#define Wr_SGMII1_TX_afe_anaTxAStatus0_txferr_stky(x) WriteRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x20,5,x)
#define Rd_SGMII1_TX_afe_anaTxAStatus0_txferr_stky(x) ReadRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x20,5)
#define SGMII1_TX_AFE_ANATXASTATUS0_TXFERR_STKY_MASK               0x0020
#define SGMII1_TX_AFE_ANATXASTATUS0_TXFERR_STKY_ALIGN              0
#define SGMII1_TX_AFE_ANATXASTATUS0_TXFERR_STKY_BITS               1
#define SGMII1_TX_AFE_ANATXASTATUS0_TXFERR_STKY_SHIFT              5

/* SGMII1_TX_afe :: anaTxAStatus0 :: tbi_mode [04:04] */
#define Wr_SGMII1_TX_afe_anaTxAStatus0_tbi_mode(x) WriteRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x10,4,x)
#define Rd_SGMII1_TX_afe_anaTxAStatus0_tbi_mode(x) ReadRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x10,4)
#define SGMII1_TX_AFE_ANATXASTATUS0_TBI_MODE_MASK                  0x0010
#define SGMII1_TX_AFE_ANATXASTATUS0_TBI_MODE_ALIGN                 0
#define SGMII1_TX_AFE_ANATXASTATUS0_TBI_MODE_BITS                  1
#define SGMII1_TX_AFE_ANATXASTATUS0_TBI_MODE_SHIFT                 4

/* SGMII1_TX_afe :: anaTxAStatus0 :: tx_reset [03:03] */
#define Wr_SGMII1_TX_afe_anaTxAStatus0_tx_reset(x) WriteRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x8,3,x)
#define Rd_SGMII1_TX_afe_anaTxAStatus0_tx_reset(x) ReadRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x8,3)
#define SGMII1_TX_AFE_ANATXASTATUS0_TX_RESET_MASK                  0x0008
#define SGMII1_TX_AFE_ANATXASTATUS0_TX_RESET_ALIGN                 0
#define SGMII1_TX_AFE_ANATXASTATUS0_TX_RESET_BITS                  1
#define SGMII1_TX_AFE_ANATXASTATUS0_TX_RESET_SHIFT                 3

/* SGMII1_TX_afe :: anaTxAStatus0 :: tx_pwrdn [02:02] */
#define Wr_SGMII1_TX_afe_anaTxAStatus0_tx_pwrdn(x) WriteRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x4,2,x)
#define Rd_SGMII1_TX_afe_anaTxAStatus0_tx_pwrdn(x) ReadRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x4,2)
#define SGMII1_TX_AFE_ANATXASTATUS0_TX_PWRDN_MASK                  0x0004
#define SGMII1_TX_AFE_ANATXASTATUS0_TX_PWRDN_ALIGN                 0
#define SGMII1_TX_AFE_ANATXASTATUS0_TX_PWRDN_BITS                  1
#define SGMII1_TX_AFE_ANATXASTATUS0_TX_PWRDN_SHIFT                 2

/* SGMII1_TX_afe :: anaTxAStatus0 :: rltxferr_stky [01:01] */
#define Wr_SGMII1_TX_afe_anaTxAStatus0_rltxferr_stky(x) WriteRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x2,1,x)
#define Rd_SGMII1_TX_afe_anaTxAStatus0_rltxferr_stky(x) ReadRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x2,1)
#define SGMII1_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_MASK             0x0002
#define SGMII1_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_ALIGN            0
#define SGMII1_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_BITS             1
#define SGMII1_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_SHIFT            1

/* SGMII1_TX_afe :: anaTxAStatus0 :: txpll_lock [00:00] */
#define Wr_SGMII1_TX_afe_anaTxAStatus0_txpll_lock(x) WriteRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x1,0,x)
#define Rd_SGMII1_TX_afe_anaTxAStatus0_txpll_lock(x) ReadRegBits16(SGMII1_TX_AFE_ANATXASTATUS0,0x1,0)
#define SGMII1_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_MASK                0x0001
#define SGMII1_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_ALIGN               0
#define SGMII1_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_BITS                1
#define SGMII1_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_SHIFT               0


/****************************************************************************
 * SGMII1_TX_afe :: anaTxAControl0
 ***************************************************************************/
/* SGMII1_TX_afe :: anaTxAControl0 :: mdio_force [15:15] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_mdio_force(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x8000,15,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_mdio_force(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x8000,15)
#define SGMII1_TX_AFE_ANATXACONTROL0_MDIO_FORCE_MASK               0x8000
#define SGMII1_TX_AFE_ANATXACONTROL0_MDIO_FORCE_ALIGN              0
#define SGMII1_TX_AFE_ANATXACONTROL0_MDIO_FORCE_BITS               1
#define SGMII1_TX_AFE_ANATXACONTROL0_MDIO_FORCE_SHIFT              15

/* SGMII1_TX_afe :: anaTxAControl0 :: force_txclk [14:14] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_force_txclk(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x4000,14,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_force_txclk(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x4000,14)
#define SGMII1_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_MASK              0x4000
#define SGMII1_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_ALIGN             0
#define SGMII1_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_BITS              1
#define SGMII1_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_SHIFT             14

/* SGMII1_TX_afe :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_tx1g_fifo_rst(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x2000,13,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_tx1g_fifo_rst(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x2000,13)
#define SGMII1_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_MASK            0x2000
#define SGMII1_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN           0
#define SGMII1_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_BITS            1
#define SGMII1_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT           13

/* SGMII1_TX_afe :: anaTxAControl0 :: force_ext_frst_SM [12:12] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_force_ext_frst_SM(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x1000,12,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_force_ext_frst_SM(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x1000,12)
#define SGMII1_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK        0x1000
#define SGMII1_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN       0
#define SGMII1_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS        1
#define SGMII1_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT       12

/* SGMII1_TX_afe :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_catch_all_8b10b_dis(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x800,11,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_catch_all_8b10b_dis(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x800,11)
#define SGMII1_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK      0x0800
#define SGMII1_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN     0
#define SGMII1_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS      1
#define SGMII1_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT     11

/* SGMII1_TX_afe :: anaTxAControl0 :: txck_dme_en_SM [10:10] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_txck_dme_en_SM(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x400,10,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_txck_dme_en_SM(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x400,10)
#define SGMII1_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_MASK           0x0400
#define SGMII1_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN          0
#define SGMII1_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_BITS           1
#define SGMII1_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT          10

/* SGMII1_TX_afe :: anaTxAControl0 :: gloopOutDis [09:09] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_gloopOutDis(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x200,9,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_gloopOutDis(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x200,9)
#define SGMII1_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_MASK              0x0200
#define SGMII1_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_ALIGN             0
#define SGMII1_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_BITS              1
#define SGMII1_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_SHIFT             9

/* SGMII1_TX_afe :: anaTxAControl0 :: prbs_en [08:08] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_prbs_en(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x100,8,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_prbs_en(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x100,8)
#define SGMII1_TX_AFE_ANATXACONTROL0_PRBS_EN_MASK                  0x0100
#define SGMII1_TX_AFE_ANATXACONTROL0_PRBS_EN_ALIGN                 0
#define SGMII1_TX_AFE_ANATXACONTROL0_PRBS_EN_BITS                  1
#define SGMII1_TX_AFE_ANATXACONTROL0_PRBS_EN_SHIFT                 8

/* SGMII1_TX_afe :: anaTxAControl0 :: pckt_en [07:07] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_pckt_en(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x80,7,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_pckt_en(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x80,7)
#define SGMII1_TX_AFE_ANATXACONTROL0_PCKT_EN_MASK                  0x0080
#define SGMII1_TX_AFE_ANATXACONTROL0_PCKT_EN_ALIGN                 0
#define SGMII1_TX_AFE_ANATXACONTROL0_PCKT_EN_BITS                  1
#define SGMII1_TX_AFE_ANATXACONTROL0_PCKT_EN_SHIFT                 7

/* SGMII1_TX_afe :: anaTxAControl0 :: pckt_strt [06:06] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_pckt_strt(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x40,6,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_pckt_strt(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x40,6)
#define SGMII1_TX_AFE_ANATXACONTROL0_PCKT_STRT_MASK                0x0040
#define SGMII1_TX_AFE_ANATXACONTROL0_PCKT_STRT_ALIGN               0
#define SGMII1_TX_AFE_ANATXACONTROL0_PCKT_STRT_BITS                1
#define SGMII1_TX_AFE_ANATXACONTROL0_PCKT_STRT_SHIFT               6

/* SGMII1_TX_afe :: anaTxAControl0 :: txpol_flip [05:05] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_txpol_flip(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x20,5,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_txpol_flip(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x20,5)
#define SGMII1_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_MASK               0x0020
#define SGMII1_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_ALIGN              0
#define SGMII1_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_BITS               1
#define SGMII1_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_SHIFT              5

/* SGMII1_TX_afe :: anaTxAControl0 :: rtbi_flip [04:04] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_rtbi_flip(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x10,4,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_rtbi_flip(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x10,4)
#define SGMII1_TX_AFE_ANATXACONTROL0_RTBI_FLIP_MASK                0x0010
#define SGMII1_TX_AFE_ANATXACONTROL0_RTBI_FLIP_ALIGN               0
#define SGMII1_TX_AFE_ANATXACONTROL0_RTBI_FLIP_BITS                1
#define SGMII1_TX_AFE_ANATXACONTROL0_RTBI_FLIP_SHIFT               4

/* SGMII1_TX_afe :: anaTxAControl0 :: eden_r [03:03] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_eden_r(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x8,3,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_eden_r(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x8,3)
#define SGMII1_TX_AFE_ANATXACONTROL0_EDEN_R_MASK                   0x0008
#define SGMII1_TX_AFE_ANATXACONTROL0_EDEN_R_ALIGN                  0
#define SGMII1_TX_AFE_ANATXACONTROL0_EDEN_R_BITS                   1
#define SGMII1_TX_AFE_ANATXACONTROL0_EDEN_R_SHIFT                  3

/* SGMII1_TX_afe :: anaTxAControl0 :: eden_force_r [02:02] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_eden_force_r(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x4,2,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_eden_force_r(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x4,2)
#define SGMII1_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_MASK             0x0004
#define SGMII1_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_ALIGN            0
#define SGMII1_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_BITS             1
#define SGMII1_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_SHIFT            2

/* SGMII1_TX_afe :: anaTxAControl0 :: txpat_en [01:01] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_txpat_en(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x2,1,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_txpat_en(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x2,1)
#define SGMII1_TX_AFE_ANATXACONTROL0_TXPAT_EN_MASK                 0x0002
#define SGMII1_TX_AFE_ANATXACONTROL0_TXPAT_EN_ALIGN                0
#define SGMII1_TX_AFE_ANATXACONTROL0_TXPAT_EN_BITS                 1
#define SGMII1_TX_AFE_ANATXACONTROL0_TXPAT_EN_SHIFT                1

/* SGMII1_TX_afe :: anaTxAControl0 :: tx_mdata_en [00:00] */
#define Wr_SGMII1_TX_afe_anaTxAControl0_tx_mdata_en(x) WriteRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x1,0,x)
#define Rd_SGMII1_TX_afe_anaTxAControl0_tx_mdata_en(x) ReadRegBits16(SGMII1_TX_AFE_ANATXACONTROL0,0x1,0)
#define SGMII1_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_MASK              0x0001
#define SGMII1_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_ALIGN             0
#define SGMII1_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_BITS              1
#define SGMII1_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_SHIFT             0


/****************************************************************************
 * SGMII1_TX_afe :: anaTxmdata0
 ***************************************************************************/
/* SGMII1_TX_afe :: anaTxmdata0 :: txTestMuxSel [15:13] */
#define Wr_SGMII1_TX_afe_anaTxmdata0_txTestMuxSel(x) WriteRegBits16(SGMII1_TX_AFE_ANATXMDATA0,0xe000,13,x)
#define Rd_SGMII1_TX_afe_anaTxmdata0_txTestMuxSel(x) ReadRegBits16(SGMII1_TX_AFE_ANATXMDATA0,0xe000,13)
#define SGMII1_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_MASK                0xe000
#define SGMII1_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_ALIGN               0
#define SGMII1_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_BITS                3
#define SGMII1_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_SHIFT               13

/* SGMII1_TX_afe :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
#define Wr_SGMII1_TX_afe_anaTxmdata0_rlfifo_tstsel(x) WriteRegBits16(SGMII1_TX_AFE_ANATXMDATA0,0x1c00,10,x)
#define Rd_SGMII1_TX_afe_anaTxmdata0_rlfifo_tstsel(x) ReadRegBits16(SGMII1_TX_AFE_ANATXMDATA0,0x1c00,10)
#define SGMII1_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_MASK               0x1c00
#define SGMII1_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN              0
#define SGMII1_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_BITS               3
#define SGMII1_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT              10

/* SGMII1_TX_afe :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
#define Wr_SGMII1_TX_afe_anaTxmdata0_TxMdioTstDataL(x) WriteRegBits16(SGMII1_TX_AFE_ANATXMDATA0,0x3ff,0,x)
#define Rd_SGMII1_TX_afe_anaTxmdata0_TxMdioTstDataL(x) ReadRegBits16(SGMII1_TX_AFE_ANATXMDATA0,0x3ff,0)
#define SGMII1_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_MASK              0x03ff
#define SGMII1_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN             0
#define SGMII1_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_BITS              10
#define SGMII1_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT             0


/****************************************************************************
 * SGMII1_TX_afe :: anaTxmdata1
 ***************************************************************************/
/* SGMII1_TX_afe :: anaTxmdata1 :: reserved0 [15:14] */
#define SGMII1_TX_AFE_ANATXMDATA1_RESERVED0_MASK                   0xc000
#define SGMII1_TX_AFE_ANATXMDATA1_RESERVED0_ALIGN                  0
#define SGMII1_TX_AFE_ANATXMDATA1_RESERVED0_BITS                   2
#define SGMII1_TX_AFE_ANATXMDATA1_RESERVED0_SHIFT                  14

/* SGMII1_TX_afe :: anaTxmdata1 :: tx_elecidle [13:13] */
#define Wr_SGMII1_TX_afe_anaTxmdata1_tx_elecidle(x) WriteRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x2000,13,x)
#define Rd_SGMII1_TX_afe_anaTxmdata1_tx_elecidle(x) ReadRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x2000,13)
#define SGMII1_TX_AFE_ANATXMDATA1_TX_ELECIDLE_MASK                 0x2000
#define SGMII1_TX_AFE_ANATXMDATA1_TX_ELECIDLE_ALIGN                0
#define SGMII1_TX_AFE_ANATXMDATA1_TX_ELECIDLE_BITS                 1
#define SGMII1_TX_AFE_ANATXMDATA1_TX_ELECIDLE_SHIFT                13

/* SGMII1_TX_afe :: anaTxmdata1 :: glpbk_clk_en [12:12] */
#define Wr_SGMII1_TX_afe_anaTxmdata1_glpbk_clk_en(x) WriteRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x1000,12,x)
#define Rd_SGMII1_TX_afe_anaTxmdata1_glpbk_clk_en(x) ReadRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x1000,12)
#define SGMII1_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_MASK                0x1000
#define SGMII1_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_ALIGN               0
#define SGMII1_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_BITS                1
#define SGMII1_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_SHIFT               12

/* SGMII1_TX_afe :: anaTxmdata1 :: pre_emph_stair_rev_en [11:11] */
#define Wr_SGMII1_TX_afe_anaTxmdata1_pre_emph_stair_rev_en(x) WriteRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x800,11,x)
#define Rd_SGMII1_TX_afe_anaTxmdata1_pre_emph_stair_rev_en(x) ReadRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x800,11)
#define SGMII1_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_MASK       0x0800
#define SGMII1_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_ALIGN      0
#define SGMII1_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_BITS       1
#define SGMII1_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_SHIFT      11

/* SGMII1_TX_afe :: anaTxmdata1 :: pre_emph_stair_en [10:10] */
#define Wr_SGMII1_TX_afe_anaTxmdata1_pre_emph_stair_en(x) WriteRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x400,10,x)
#define Rd_SGMII1_TX_afe_anaTxmdata1_pre_emph_stair_en(x) ReadRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x400,10)
#define SGMII1_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_MASK           0x0400
#define SGMII1_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_ALIGN          0
#define SGMII1_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_BITS           1
#define SGMII1_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_SHIFT          10

/* SGMII1_TX_afe :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
#define Wr_SGMII1_TX_afe_anaTxmdata1_TxMdioTstDataH(x) WriteRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x3ff,0,x)
#define Rd_SGMII1_TX_afe_anaTxmdata1_TxMdioTstDataH(x) ReadRegBits16(SGMII1_TX_AFE_ANATXMDATA1,0x3ff,0)
#define SGMII1_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_MASK              0x03ff
#define SGMII1_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN             0
#define SGMII1_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_BITS              10
#define SGMII1_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT             0


/****************************************************************************
 * SGMII1_TX_afe :: control0
 ***************************************************************************/
/* SGMII1_TX_afe :: control0 :: Fix_10units_en [15:15] */
#define Wr_SGMII1_TX_afe_control0_Fix_10units_en(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL0,0x8000,15,x)
#define Rd_SGMII1_TX_afe_control0_Fix_10units_en(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL0,0x8000,15)
#define SGMII1_TX_AFE_CONTROL0_FIX_10UNITS_EN_MASK                 0x8000
#define SGMII1_TX_AFE_CONTROL0_FIX_10UNITS_EN_ALIGN                0
#define SGMII1_TX_AFE_CONTROL0_FIX_10UNITS_EN_BITS                 1
#define SGMII1_TX_AFE_CONTROL0_FIX_10UNITS_EN_SHIFT                15

/* SGMII1_TX_afe :: control0 :: Quarter_unit_en [14:14] */
#define Wr_SGMII1_TX_afe_control0_Quarter_unit_en(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL0,0x4000,14,x)
#define Rd_SGMII1_TX_afe_control0_Quarter_unit_en(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL0,0x4000,14)
#define SGMII1_TX_AFE_CONTROL0_QUARTER_UNIT_EN_MASK                0x4000
#define SGMII1_TX_AFE_CONTROL0_QUARTER_UNIT_EN_ALIGN               0
#define SGMII1_TX_AFE_CONTROL0_QUARTER_UNIT_EN_BITS                1
#define SGMII1_TX_AFE_CONTROL0_QUARTER_UNIT_EN_SHIFT               14

/* SGMII1_TX_afe :: control0 :: main_control [13:08] */
#define Wr_SGMII1_TX_afe_control0_main_control(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL0,0x3f00,8,x)
#define Rd_SGMII1_TX_afe_control0_main_control(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL0,0x3f00,8)
#define SGMII1_TX_AFE_CONTROL0_MAIN_CONTROL_MASK                   0x3f00
#define SGMII1_TX_AFE_CONTROL0_MAIN_CONTROL_ALIGN                  0
#define SGMII1_TX_AFE_CONTROL0_MAIN_CONTROL_BITS                   6
#define SGMII1_TX_AFE_CONTROL0_MAIN_CONTROL_SHIFT                  8

/* SGMII1_TX_afe :: control0 :: reserved_7 [07:07] */
#define SGMII1_TX_AFE_CONTROL0_RESERVED_7_MASK                     0x0080
#define SGMII1_TX_AFE_CONTROL0_RESERVED_7_ALIGN                    0
#define SGMII1_TX_AFE_CONTROL0_RESERVED_7_BITS                     1
#define SGMII1_TX_AFE_CONTROL0_RESERVED_7_SHIFT                    7

/* SGMII1_TX_afe :: control0 :: rxdetect_th [06:05] */
#define Wr_SGMII1_TX_afe_control0_rxdetect_th(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL0,0x60,5,x)
#define Rd_SGMII1_TX_afe_control0_rxdetect_th(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL0,0x60,5)
#define SGMII1_TX_AFE_CONTROL0_RXDETECT_TH_MASK                    0x0060
#define SGMII1_TX_AFE_CONTROL0_RXDETECT_TH_ALIGN                   0
#define SGMII1_TX_AFE_CONTROL0_RXDETECT_TH_BITS                    2
#define SGMII1_TX_AFE_CONTROL0_RXDETECT_TH_SHIFT                   5

/* SGMII1_TX_afe :: control0 :: idle_ena [04:04] */
#define Wr_SGMII1_TX_afe_control0_idle_ena(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL0,0x10,4,x)
#define Rd_SGMII1_TX_afe_control0_idle_ena(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL0,0x10,4)
#define SGMII1_TX_AFE_CONTROL0_IDLE_ENA_MASK                       0x0010
#define SGMII1_TX_AFE_CONTROL0_IDLE_ENA_ALIGN                      0
#define SGMII1_TX_AFE_CONTROL0_IDLE_ENA_BITS                       1
#define SGMII1_TX_AFE_CONTROL0_IDLE_ENA_SHIFT                      4

/* SGMII1_TX_afe :: control0 :: reserved_3_2 [03:02] */
#define SGMII1_TX_AFE_CONTROL0_RESERVED_3_2_MASK                   0x000c
#define SGMII1_TX_AFE_CONTROL0_RESERVED_3_2_ALIGN                  0
#define SGMII1_TX_AFE_CONTROL0_RESERVED_3_2_BITS                   2
#define SGMII1_TX_AFE_CONTROL0_RESERVED_3_2_SHIFT                  2

/* SGMII1_TX_afe :: control0 :: Testsel [01:01] */
#define Wr_SGMII1_TX_afe_control0_Testsel(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL0,0x2,1,x)
#define Rd_SGMII1_TX_afe_control0_Testsel(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL0,0x2,1)
#define SGMII1_TX_AFE_CONTROL0_TESTSEL_MASK                        0x0002
#define SGMII1_TX_AFE_CONTROL0_TESTSEL_ALIGN                       0
#define SGMII1_TX_AFE_CONTROL0_TESTSEL_BITS                        1
#define SGMII1_TX_AFE_CONTROL0_TESTSEL_SHIFT                       1

/* SGMII1_TX_afe :: control0 :: tx_pwrdn [00:00] */
#define Wr_SGMII1_TX_afe_control0_tx_pwrdn(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL0,0x1,0,x)
#define Rd_SGMII1_TX_afe_control0_tx_pwrdn(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL0,0x1,0)
#define SGMII1_TX_AFE_CONTROL0_TX_PWRDN_MASK                       0x0001
#define SGMII1_TX_AFE_CONTROL0_TX_PWRDN_ALIGN                      0
#define SGMII1_TX_AFE_CONTROL0_TX_PWRDN_BITS                       1
#define SGMII1_TX_AFE_CONTROL0_TX_PWRDN_SHIFT                      0


/****************************************************************************
 * SGMII1_TX_afe :: control1
 ***************************************************************************/
/* SGMII1_TX_afe :: control1 :: Slew_rate_control [15:14] */
#define Wr_SGMII1_TX_afe_control1_Slew_rate_control(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL1,0xc000,14,x)
#define Rd_SGMII1_TX_afe_control1_Slew_rate_control(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL1,0xc000,14)
#define SGMII1_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_MASK              0xc000
#define SGMII1_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_ALIGN             0
#define SGMII1_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_BITS              2
#define SGMII1_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_SHIFT             14

/* SGMII1_TX_afe :: control1 :: reserved_29 [13:13] */
#define SGMII1_TX_AFE_CONTROL1_RESERVED_29_MASK                    0x2000
#define SGMII1_TX_AFE_CONTROL1_RESERVED_29_ALIGN                   0
#define SGMII1_TX_AFE_CONTROL1_RESERVED_29_BITS                    1
#define SGMII1_TX_AFE_CONTROL1_RESERVED_29_SHIFT                   13

/* SGMII1_TX_afe :: control1 :: Post_enable [12:12] */
#define Wr_SGMII1_TX_afe_control1_Post_enable(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL1,0x1000,12,x)
#define Rd_SGMII1_TX_afe_control1_Post_enable(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL1,0x1000,12)
#define SGMII1_TX_AFE_CONTROL1_POST_ENABLE_MASK                    0x1000
#define SGMII1_TX_AFE_CONTROL1_POST_ENABLE_ALIGN                   0
#define SGMII1_TX_AFE_CONTROL1_POST_ENABLE_BITS                    1
#define SGMII1_TX_AFE_CONTROL1_POST_ENABLE_SHIFT                   12

/* SGMII1_TX_afe :: control1 :: Post_control [11:06] */
#define Wr_SGMII1_TX_afe_control1_Post_control(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL1,0xfc0,6,x)
#define Rd_SGMII1_TX_afe_control1_Post_control(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL1,0xfc0,6)
#define SGMII1_TX_AFE_CONTROL1_POST_CONTROL_MASK                   0x0fc0
#define SGMII1_TX_AFE_CONTROL1_POST_CONTROL_ALIGN                  0
#define SGMII1_TX_AFE_CONTROL1_POST_CONTROL_BITS                   6
#define SGMII1_TX_AFE_CONTROL1_POST_CONTROL_SHIFT                  6

/* SGMII1_TX_afe :: control1 :: reserved_21 [05:05] */
#define SGMII1_TX_AFE_CONTROL1_RESERVED_21_MASK                    0x0020
#define SGMII1_TX_AFE_CONTROL1_RESERVED_21_ALIGN                   0
#define SGMII1_TX_AFE_CONTROL1_RESERVED_21_BITS                    1
#define SGMII1_TX_AFE_CONTROL1_RESERVED_21_SHIFT                   5

/* SGMII1_TX_afe :: control1 :: Pwd_lvl2pi [04:04] */
#define Wr_SGMII1_TX_afe_control1_Pwd_lvl2pi(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL1,0x10,4,x)
#define Rd_SGMII1_TX_afe_control1_Pwd_lvl2pi(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL1,0x10,4)
#define SGMII1_TX_AFE_CONTROL1_PWD_LVL2PI_MASK                     0x0010
#define SGMII1_TX_AFE_CONTROL1_PWD_LVL2PI_ALIGN                    0
#define SGMII1_TX_AFE_CONTROL1_PWD_LVL2PI_BITS                     1
#define SGMII1_TX_AFE_CONTROL1_PWD_LVL2PI_SHIFT                    4

/* SGMII1_TX_afe :: control1 :: PI_bw_sel [03:03] */
#define Wr_SGMII1_TX_afe_control1_PI_bw_sel(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL1,0x8,3,x)
#define Rd_SGMII1_TX_afe_control1_PI_bw_sel(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL1,0x8,3)
#define SGMII1_TX_AFE_CONTROL1_PI_BW_SEL_MASK                      0x0008
#define SGMII1_TX_AFE_CONTROL1_PI_BW_SEL_ALIGN                     0
#define SGMII1_TX_AFE_CONTROL1_PI_BW_SEL_BITS                      1
#define SGMII1_TX_AFE_CONTROL1_PI_BW_SEL_SHIFT                     3

/* SGMII1_TX_afe :: control1 :: Const_Impedance [02:02] */
#define Wr_SGMII1_TX_afe_control1_Const_Impedance(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL1,0x4,2,x)
#define Rd_SGMII1_TX_afe_control1_Const_Impedance(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL1,0x4,2)
#define SGMII1_TX_AFE_CONTROL1_CONST_IMPEDANCE_MASK                0x0004
#define SGMII1_TX_AFE_CONTROL1_CONST_IMPEDANCE_ALIGN               0
#define SGMII1_TX_AFE_CONTROL1_CONST_IMPEDANCE_BITS                1
#define SGMII1_TX_AFE_CONTROL1_CONST_IMPEDANCE_SHIFT               2

/* SGMII1_TX_afe :: control1 :: Amp_mode [01:01] */
#define Wr_SGMII1_TX_afe_control1_Amp_mode(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL1,0x2,1,x)
#define Rd_SGMII1_TX_afe_control1_Amp_mode(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL1,0x2,1)
#define SGMII1_TX_AFE_CONTROL1_AMP_MODE_MASK                       0x0002
#define SGMII1_TX_AFE_CONTROL1_AMP_MODE_ALIGN                      0
#define SGMII1_TX_AFE_CONTROL1_AMP_MODE_BITS                       1
#define SGMII1_TX_AFE_CONTROL1_AMP_MODE_SHIFT                      1

/* SGMII1_TX_afe :: control1 :: Vdd1p0_enb [00:00] */
#define Wr_SGMII1_TX_afe_control1_Vdd1p0_enb(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL1,0x1,0,x)
#define Rd_SGMII1_TX_afe_control1_Vdd1p0_enb(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL1,0x1,0)
#define SGMII1_TX_AFE_CONTROL1_VDD1P0_ENB_MASK                     0x0001
#define SGMII1_TX_AFE_CONTROL1_VDD1P0_ENB_ALIGN                    0
#define SGMII1_TX_AFE_CONTROL1_VDD1P0_ENB_BITS                     1
#define SGMII1_TX_AFE_CONTROL1_VDD1P0_ENB_SHIFT                    0


/****************************************************************************
 * SGMII1_TX_afe :: control2
 ***************************************************************************/
/* SGMII1_TX_afe :: control2 :: leakage_test [15:15] */
#define Wr_SGMII1_TX_afe_control2_leakage_test(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL2,0x8000,15,x)
#define Rd_SGMII1_TX_afe_control2_leakage_test(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL2,0x8000,15)
#define SGMII1_TX_AFE_CONTROL2_LEAKAGE_TEST_MASK                   0x8000
#define SGMII1_TX_AFE_CONTROL2_LEAKAGE_TEST_ALIGN                  0
#define SGMII1_TX_AFE_CONTROL2_LEAKAGE_TEST_BITS                   1
#define SGMII1_TX_AFE_CONTROL2_LEAKAGE_TEST_SHIFT                  15

/* SGMII1_TX_afe :: control2 :: Vdd_noise_cncl_en [14:14] */
#define Wr_SGMII1_TX_afe_control2_Vdd_noise_cncl_en(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL2,0x4000,14,x)
#define Rd_SGMII1_TX_afe_control2_Vdd_noise_cncl_en(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL2,0x4000,14)
#define SGMII1_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_MASK              0x4000
#define SGMII1_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_ALIGN             0
#define SGMII1_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_BITS              1
#define SGMII1_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_SHIFT             14

/* SGMII1_TX_afe :: control2 :: Noise_cncl_bias [13:10] */
#define Wr_SGMII1_TX_afe_control2_Noise_cncl_bias(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL2,0x3c00,10,x)
#define Rd_SGMII1_TX_afe_control2_Noise_cncl_bias(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL2,0x3c00,10)
#define SGMII1_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_MASK                0x3c00
#define SGMII1_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_ALIGN               0
#define SGMII1_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_BITS                4
#define SGMII1_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_SHIFT               10

/* SGMII1_TX_afe :: control2 :: Vdd_noise_shape [09:07] */
#define Wr_SGMII1_TX_afe_control2_Vdd_noise_shape(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL2,0x380,7,x)
#define Rd_SGMII1_TX_afe_control2_Vdd_noise_shape(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL2,0x380,7)
#define SGMII1_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_MASK                0x0380
#define SGMII1_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_ALIGN               0
#define SGMII1_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_BITS                3
#define SGMII1_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_SHIFT               7

/* SGMII1_TX_afe :: control2 :: tx_pon [06:03] */
#define Wr_SGMII1_TX_afe_control2_tx_pon(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL2,0x78,3,x)
#define Rd_SGMII1_TX_afe_control2_tx_pon(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL2,0x78,3)
#define SGMII1_TX_AFE_CONTROL2_TX_PON_MASK                         0x0078
#define SGMII1_TX_AFE_CONTROL2_TX_PON_ALIGN                        0
#define SGMII1_TX_AFE_CONTROL2_TX_PON_BITS                         4
#define SGMII1_TX_AFE_CONTROL2_TX_PON_SHIFT                        3

/* SGMII1_TX_afe :: control2 :: ticksel [02:01] */
#define Wr_SGMII1_TX_afe_control2_ticksel(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL2,0x6,1,x)
#define Rd_SGMII1_TX_afe_control2_ticksel(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL2,0x6,1)
#define SGMII1_TX_AFE_CONTROL2_TICKSEL_MASK                        0x0006
#define SGMII1_TX_AFE_CONTROL2_TICKSEL_ALIGN                       0
#define SGMII1_TX_AFE_CONTROL2_TICKSEL_BITS                        2
#define SGMII1_TX_AFE_CONTROL2_TICKSEL_SHIFT                       1

/* SGMII1_TX_afe :: control2 :: testck_en [00:00] */
#define Wr_SGMII1_TX_afe_control2_testck_en(x) WriteRegBits16(SGMII1_TX_AFE_CONTROL2,0x1,0,x)
#define Rd_SGMII1_TX_afe_control2_testck_en(x) ReadRegBits16(SGMII1_TX_AFE_CONTROL2,0x1,0)
#define SGMII1_TX_AFE_CONTROL2_TESTCK_EN_MASK                      0x0001
#define SGMII1_TX_AFE_CONTROL2_TESTCK_EN_ALIGN                     0
#define SGMII1_TX_AFE_CONTROL2_TESTCK_EN_BITS                      1
#define SGMII1_TX_AFE_CONTROL2_TESTCK_EN_SHIFT                     0


/****************************************************************************
 * SGMII1_TX_afe :: control3
 ***************************************************************************/
/* SGMII1_TX_afe :: control3 :: reserved_63_48 [15:00] */
#define SGMII1_TX_AFE_CONTROL3_RESERVED_63_48_MASK                 0xffff
#define SGMII1_TX_AFE_CONTROL3_RESERVED_63_48_ALIGN                0
#define SGMII1_TX_AFE_CONTROL3_RESERVED_63_48_BITS                 16
#define SGMII1_TX_AFE_CONTROL3_RESERVED_63_48_SHIFT                0


/****************************************************************************
 * SGMII1_TX_afe :: interp
 ***************************************************************************/
/* SGMII1_TX_afe :: interp :: reserved0 [15:07] */
#define SGMII1_TX_AFE_INTERP_RESERVED0_MASK                        0xff80
#define SGMII1_TX_AFE_INTERP_RESERVED0_ALIGN                       0
#define SGMII1_TX_AFE_INTERP_RESERVED0_BITS                        9
#define SGMII1_TX_AFE_INTERP_RESERVED0_SHIFT                       7

/* SGMII1_TX_afe :: interp :: interp_ctrl_quadrant [06:05] */
#define Wr_SGMII1_TX_afe_interp_interp_ctrl_quadrant(x) WriteRegBits16(SGMII1_TX_AFE_INTERP,0x60,5,x)
#define Rd_SGMII1_TX_afe_interp_interp_ctrl_quadrant(x) ReadRegBits16(SGMII1_TX_AFE_INTERP,0x60,5)
#define SGMII1_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_MASK             0x0060
#define SGMII1_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_ALIGN            0
#define SGMII1_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_BITS             2
#define SGMII1_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_SHIFT            5

/* SGMII1_TX_afe :: interp :: interp_ctrl_phs [04:00] */
#define Wr_SGMII1_TX_afe_interp_interp_ctrl_phs(x) WriteRegBits16(SGMII1_TX_AFE_INTERP,0x1f,0,x)
#define Rd_SGMII1_TX_afe_interp_interp_ctrl_phs(x) ReadRegBits16(SGMII1_TX_AFE_INTERP,0x1f,0)
#define SGMII1_TX_AFE_INTERP_INTERP_CTRL_PHS_MASK                  0x001f
#define SGMII1_TX_AFE_INTERP_INTERP_CTRL_PHS_ALIGN                 0
#define SGMII1_TX_AFE_INTERP_INTERP_CTRL_PHS_BITS                  5
#define SGMII1_TX_AFE_INTERP_INTERP_CTRL_PHS_SHIFT                 0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_RX_afe
 ***************************************************************************/
/****************************************************************************
 * SGMII1_RX_afe :: anaRxStatus
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: cx4_sigdet [15:15] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sigdet_Status_cx4_sigdet(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x8000,15,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sigdet_Status_cx4_sigdet(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x8000,15)
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK    0x8000
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS    1
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT   15

/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [14:13] */
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK     0x6000
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS     2
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT    13

/* SGMII1_RX_afe :: anaRxStatus :: rxSeqDone [12:12] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sigdet_Status_rxSeqDone(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x1000,12,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sigdet_Status_rxSeqDone(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x1000,12)
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK     0x1000
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT    12

/* SGMII1_RX_afe :: anaRxStatus :: rx_sigdet_ll [11:11] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sigdet_Status_rx_sigdet_ll(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x800,11,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sigdet_Status_rx_sigdet_ll(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x800,11)
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK  0x0800
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS  1
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11

/* SGMII1_RX_afe :: anaRxStatus :: cs4_sigdet_ll [10:10] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sigdet_Status_cs4_sigdet_ll(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x400,10,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sigdet_Status_cs4_sigdet_ll(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x400,10)
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10

/* SGMII1_RX_afe :: anaRxStatus :: rx_reset [09:09] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sigdet_Status_rx_reset(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x200,9,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sigdet_Status_rx_reset(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x200,9)
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK      0x0200
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN     0
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS      1
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT     9

/* SGMII1_RX_afe :: anaRxStatus :: rx_pwrdn [08:08] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sigdet_Status_rx_pwrdn(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x100,8,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sigdet_Status_rx_pwrdn(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x100,8)
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK      0x0100
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN     0
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS      1
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT     8

/* SGMII1_RX_afe :: anaRxStatus :: reserved1 [07:00] */
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK     0x00ff
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS     8
#define SGMII1_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT    0


/* union - case sync_Status [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:11] */
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK       0xf800
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS       5
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT      11

/* SGMII1_RX_afe :: anaRxStatus :: test_acq_en [10:10] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sync_Status_test_acq_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x400,10,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sync_Status_test_acq_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x400,10)
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK     0x0400
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT    10

/* SGMII1_RX_afe :: anaRxStatus :: reserved1 [09:09] */
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK       0x0200
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS       1
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT      9

/* SGMII1_RX_afe :: anaRxStatus :: rxSeqStart [08:08] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sync_Status_rxSeqStart(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x100,8,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sync_Status_rxSeqStart(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x100,8)
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK      0x0100
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN     0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS      1
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT     8

/* SGMII1_RX_afe :: anaRxStatus :: mux_comadj_sync_status [07:07] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sync_Status_mux_comadj_sync_status(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x80,7,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sync_Status_mux_comadj_sync_status(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x80,7)
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7

/* SGMII1_RX_afe :: anaRxStatus :: sync_status [06:06] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sync_Status_sync_status(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x40,6,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sync_Status_sync_status(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x40,6)
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK     0x0040
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT    6

/* SGMII1_RX_afe :: anaRxStatus :: rx_sigdet [05:05] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sync_Status_rx_sigdet(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sync_Status_rx_sigdet(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x20,5)
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK       0x0020
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS       1
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT      5

/* SGMII1_RX_afe :: anaRxStatus :: reserved2 [04:03] */
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK       0x0018
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS       2
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT      3

/* SGMII1_RX_afe :: anaRxStatus :: saturate_status [02:02] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sync_Status_saturate_status(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sync_Status_saturate_status(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x4,2)
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2

/* SGMII1_RX_afe :: anaRxStatus :: cx4_sigdet [01:01] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sync_Status_cx4_sigdet(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x2,1,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sync_Status_cx4_sigdet(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x2,1)
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK      0x0002
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN     0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS      1
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT     1

/* SGMII1_RX_afe :: anaRxStatus :: rxSeqDone [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_sync_Status_rxSeqDone(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_sync_Status_rxSeqDone(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK       0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS       1
#define SGMII1_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT      0


/* union - case rxTestSel_0 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:10] */
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK       0xfc00
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS       6
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT      10

/* SGMII1_RX_afe :: anaRxStatus :: indck_mode_en [09:09] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_indck_mode_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x200,9,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_indck_mode_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x200,9)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK   0x0200
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT  9

/* SGMII1_RX_afe :: anaRxStatus :: pci_mode_en [08:08] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_pci_mode_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x100,8,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_pci_mode_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x100,8)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK     0x0100
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT    8

/* SGMII1_RX_afe :: anaRxStatus :: rx_polarity [07:07] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_rx_polarity(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x80,7,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_rx_polarity(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x80,7)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK     0x0080
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT    7

/* SGMII1_RX_afe :: anaRxStatus :: rxpol_flip [06:06] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_rxpol_flip(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x40,6,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_rxpol_flip(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x40,6)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK      0x0040
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN     0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS      1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT     6

/* SGMII1_RX_afe :: anaRxStatus :: comma_mask [05:05] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_comma_mask(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_comma_mask(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x20,5)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK      0x0020
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN     0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS      1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT     5

/* SGMII1_RX_afe :: anaRxStatus :: link_en_r [04:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_link_en_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_link_en_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x10,4)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK       0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS       1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT      4

/* SGMII1_RX_afe :: anaRxStatus :: comma_adj_en [03:03] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x8,3)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK    0x0008
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS    1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT   3

/* SGMII1_RX_afe :: anaRxStatus :: comma_adj_en_ext [02:02] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en_ext(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en_ext(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x4,2)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2

/* SGMII1_RX_afe :: anaRxStatus :: reserved1 [01:00] */
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK       0x0003
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS       2
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT      0


/* union - case rxTestSel_1 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK       0xffe0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS       11
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT      5

/* SGMII1_RX_afe :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_1_cdrAcqDone_r2(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_1_cdrAcqDone_r2(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x10,4)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK   0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT  4

/* SGMII1_RX_afe :: anaRxStatus :: freq_sel_PC [03:03] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_PC(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_PC(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x8,3)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK     0x0008
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT    3

/* SGMII1_RX_afe :: anaRxStatus :: freq_sel_SM [02:02] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x4,2)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK     0x0004
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT    2

/* SGMII1_RX_afe :: anaRxStatus :: integ_mode_SM [01:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_rxTestSel_1_integ_mode_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x3,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_rxTestSel_1_integ_mode_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x3,0)
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK   0x0003
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS   2
#define SGMII1_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT  0


/* union - case scale_Status [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: prop_scale [15:12] */
#define Wr_SGMII1_RX_afe_anaRxStatus_scale_Status_prop_scale(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf000,12,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_scale_Status_prop_scale(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf000,12)
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK     0xf000
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS     4
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT    12

/* SGMII1_RX_afe :: anaRxStatus :: integ_scale [11:08] */
#define Wr_SGMII1_RX_afe_anaRxStatus_scale_Status_integ_scale(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf00,8,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_scale_Status_integ_scale(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf00,8)
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK    0x0f00
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS    4
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT   8

/* SGMII1_RX_afe :: anaRxStatus :: prop_scale_acq [07:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_scale_Status_prop_scale_acq(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf0,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_scale_Status_prop_scale_acq(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf0,4)
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4

/* SGMII1_RX_afe :: anaRxStatus :: integ_scale_acq [03:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_scale_Status_integ_scale_acq(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_scale_Status_integ_scale_acq(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf,0)
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4
#define SGMII1_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0


/* union - case adc_CdrStatus1 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:07] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK    0xff80
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS    9
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT   7

/* SGMII1_RX_afe :: anaRxStatus :: rxMuxCkSel [06:06] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_rxMuxCkSel(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x40,6,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_rxMuxCkSel(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x40,6)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK   0x0040
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT  6

/* SGMII1_RX_afe :: anaRxStatus :: glpbk_combo [05:05] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_glpbk_combo(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_glpbk_combo(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x20,5)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK  0x0020
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS  1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5

/* SGMII1_RX_afe :: anaRxStatus :: clockSwitchSel [04:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_clockSwitchSel(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_clockSwitchSel(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x10,4)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4

/* SGMII1_RX_afe :: anaRxStatus :: rxck_tst [03:03] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_tst(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_tst(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x8,3)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK     0x0008
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT    3

/* SGMII1_RX_afe :: anaRxStatus :: rxck_i [02:02] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_i(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_i(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x4,2)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK       0x0004
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS       1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT      2

/* SGMII1_RX_afe :: anaRxStatus :: refclk [01:01] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_refclk(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x2,1,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_refclk(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x2,1)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK       0x0002
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS       1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT      1

/* SGMII1_RX_afe :: anaRxStatus :: pll_bypass [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_pll_bypass(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus1_pll_bypass(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK   0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT  0


/* union - case adc_CdrStatus2 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:06] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK    0xffc0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS    10
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT   6

/* SGMII1_RX_afe :: anaRxStatus :: rxMuxCkSel [05:05] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus2_rxMuxCkSel(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus2_rxMuxCkSel(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x20,5)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK   0x0020
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT  5

/* SGMII1_RX_afe :: anaRxStatus :: rxSeqStart [04:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqStart(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqStart(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x10,4)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK   0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT  4

/* SGMII1_RX_afe :: anaRxStatus :: reserved1 [03:01] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK    0x000e
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS    3
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT   1

/* SGMII1_RX_afe :: anaRxStatus :: rxSeqDone [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqDone(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqDone(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK    0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS    1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT   0


/* union - case adc_CdrStatus3 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:04] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK    0xfff0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS    12
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT   4

/* SGMII1_RX_afe :: anaRxStatus :: rxSeqStart [03:03] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus3_rxSeqStart(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus3_rxSeqStart(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x8,3)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK   0x0008
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT  3

/* SGMII1_RX_afe :: anaRxStatus :: reserved1 [02:01] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK    0x0006
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS    2
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT   1

/* SGMII1_RX_afe :: anaRxStatus :: allow_increment_PC [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus3_allow_increment_PC(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus3_allow_increment_PC(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0


/* union - case adc_CdrStatus4 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:08] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK    0xff00
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS    8
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT   8

/* SGMII1_RX_afe :: anaRxStatus :: rx_pwrdn [07:07] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus4_rx_pwrdn(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x80,7,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus4_rx_pwrdn(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x80,7)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK     0x0080
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT    7

/* SGMII1_RX_afe :: anaRxStatus :: freq_sel [06:06] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus4_freq_sel(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x40,6,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus4_freq_sel(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x40,6)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK     0x0040
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT    6

/* SGMII1_RX_afe :: anaRxStatus :: pll_lock_rstb [05:05] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus4_pll_lock_rstb(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus4_pll_lock_rstb(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x20,5)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5

/* SGMII1_RX_afe :: anaRxStatus :: pwrdn [04:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus4_pwrdn(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus4_pwrdn(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x10,4)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK        0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN       0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS        1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT       4

/* SGMII1_RX_afe :: anaRxStatus :: reserved1 [03:00] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK    0x000f
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS    4
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT   0


/* union - case adc_CdrStatus5 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:00] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK    0xffff
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS    16
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT   0


/* union - case adc_CdrStatus6 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK    0xffe0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS    11
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT   5

/* SGMII1_RX_afe :: anaRxStatus :: rx_reset [04:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_rx_reset(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_rx_reset(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x10,4)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK     0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT    4

/* SGMII1_RX_afe :: anaRxStatus :: rx_pwrdn [03:03] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_rx_pwrdn(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_rx_pwrdn(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x8,3)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK     0x0008
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT    3

/* SGMII1_RX_afe :: anaRxStatus :: reset_anlg [02:02] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_reset_anlg(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_reset_anlg(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x4,2)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK   0x0004
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT  2

/* SGMII1_RX_afe :: anaRxStatus :: pwrdn_rx [01:01] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_rx(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x2,1,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_rx(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x2,1)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK     0x0002
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT    1

/* SGMII1_RX_afe :: anaRxStatus :: pwrdn_pll [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_pll(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_pll(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK    0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS    1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT   0


/* union - case adc_CdrStatus7e [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK   0xffe0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS   11
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT  5

/* SGMII1_RX_afe :: anaRxStatus :: rxck0_even [04:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck0_even(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck0_even(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x10,4)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK  0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS  1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4

/* SGMII1_RX_afe :: anaRxStatus :: rxck1_even [03:03] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck1_even(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck1_even(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x8,3)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK  0x0008
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS  1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3

/* SGMII1_RX_afe :: anaRxStatus :: comdet_even [02:02] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_comdet_even(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_comdet_even(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x4,2)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2

/* SGMII1_RX_afe :: anaRxStatus :: en_cdet_even [01:01] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_en_cdet_even(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x2,1,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_en_cdet_even(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x2,1)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1

/* SGMII1_RX_afe :: anaRxStatus :: comma_adj_en_even [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_comma_adj_en_even(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7e_comma_adj_en_even(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0


/* union - case adc_CdrStatus7o [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK   0xffe0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS   11
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT  5

/* SGMII1_RX_afe :: anaRxStatus :: rxck0_odd [04:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck0_odd(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck0_odd(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x10,4)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK   0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT  4

/* SGMII1_RX_afe :: anaRxStatus :: rxck1_odd [03:03] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck1_odd(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck1_odd(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x8,3)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK   0x0008
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT  3

/* SGMII1_RX_afe :: anaRxStatus :: comdet_odd [02:02] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_comdet_odd(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_comdet_odd(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x4,2)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK  0x0004
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS  1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2

/* SGMII1_RX_afe :: anaRxStatus :: en_cdet_odd [01:01] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_en_cdet_odd(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x2,1,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_en_cdet_odd(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x2,1)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1

/* SGMII1_RX_afe :: anaRxStatus :: comma_adj_en_odd [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_comma_adj_en_odd(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus7o_comma_adj_en_odd(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0


/* union - case adc_CdrStatus8 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:01] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK    0xfffe
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS    15
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT   1

/* SGMII1_RX_afe :: anaRxStatus :: sigdet [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus8_sigdet(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus8_sigdet(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK       0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS       1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT      0


/* union - case adc_CdrStatus9 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:00] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK    0xffff
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS    16
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT   0


/* union - case adc_CdrStatus10 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:07] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK   0xff80
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS   9
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT  7

/* SGMII1_RX_afe :: anaRxStatus :: prbs_en [06:06] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x40,6,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x40,6)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK     0x0040
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS     1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT    6

/* SGMII1_RX_afe :: anaRxStatus :: rstb_tst [05:05] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus10_rstb_tst(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus10_rstb_tst(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x20,5)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK    0x0020
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN   0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS    1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT   5

/* SGMII1_RX_afe :: anaRxStatus :: reserved1 [04:04] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK   0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT  4

/* SGMII1_RX_afe :: anaRxStatus :: prbs_state [03:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_state(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0xf,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_state(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0xf,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK  0x000f
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS  4
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0


/* union - case adc_CdrStatus11 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:00] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK   0xffff
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS   16
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT  0


/* union - case adc_CdrStatus12_1 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:06] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6

/* SGMII1_RX_afe :: anaRxStatus :: enable4 [05:05] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_1_enable4(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_1_enable4(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x20,5)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK   0x0020
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT  5

/* SGMII1_RX_afe :: anaRxStatus :: radr_test [04:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_1_radr_test(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x1f,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_1_radr_test(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x1f,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0


/* union - case adc_CdrStatus12_2 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5

/* SGMII1_RX_afe :: anaRxStatus :: wadr_test [04:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_2_wadr_test(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2,0x1f,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_2_wadr_test(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2,0x1f,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0


/* union - case adc_CdrStatus12_3 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:06] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6

/* SGMII1_RX_afe :: anaRxStatus :: rxck_66B_tmux [05:05] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_66B_tmux(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_66B_tmux(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x20,5)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5

/* SGMII1_RX_afe :: anaRxStatus :: rstb_66B [04:04] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_66B(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_66B(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x10,4)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK  0x0010
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS  1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4

/* SGMII1_RX_afe :: anaRxStatus :: prstb_66B_mux [03:03] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_66B_mux(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_66B_mux(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x8,3)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3

/* SGMII1_RX_afe :: anaRxStatus :: rxck_i66_tmux [02:02] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_i66_tmux(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_i66_tmux(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x4,2)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2

/* SGMII1_RX_afe :: anaRxStatus :: rstb_i66 [01:01] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_i66(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x2,1,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_i66(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x2,1)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK  0x0002
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS  1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1

/* SGMII1_RX_afe :: anaRxStatus :: prstb_i66_mux [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_i66_mux(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_i66_mux(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0


/* union - case adc_CdrStatus12_4 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: reserved0 [15:04] */
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4

/* SGMII1_RX_afe :: anaRxStatus :: rfifo_error_r [03:02] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_error_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0xc,2,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_error_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0xc,2)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2

/* SGMII1_RX_afe :: anaRxStatus :: rfifo_unflow [01:01] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_unflow(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x2,1,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_unflow(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x2,1)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1

/* SGMII1_RX_afe :: anaRxStatus :: rfifo_ovflow [00:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_ovflow(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_ovflow(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x1,0)
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1
#define SGMII1_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0


/* union - case integ_Status [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: integ_status [15:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_integ_Status_integ_status(x) WriteReg16(SGMII1_RX_AFE_ANARXSTATUS_INTEG_STATUS,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_integ_Status_integ_status(x) ReadReg16(SGMII1_RX_AFE_ANARXSTATUS_INTEG_STATUS)
#define SGMII1_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK   0xffff
#define SGMII1_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS   16
#define SGMII1_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT  0


/* union - case vco_Status [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: vco_status [15:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_vco_Status_vco_status(x) WriteReg16(SGMII1_RX_AFE_ANARXSTATUS_VCO_STATUS,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_vco_Status_vco_status(x) ReadReg16(SGMII1_RX_AFE_ANARXSTATUS_VCO_STATUS)
#define SGMII1_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK       0xffff
#define SGMII1_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS       16
#define SGMII1_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT      0


/* union - case prbs_Status [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: prbs_lock [15:15] */
#define Wr_SGMII1_RX_afe_anaRxStatus_prbs_Status_prbs_lock(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x8000,15,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_prbs_Status_prbs_lock(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x8000,15)
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK       0x8000
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS       1
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT      15

/* SGMII1_RX_afe :: anaRxStatus :: prbs_stky [14:14] */
#define Wr_SGMII1_RX_afe_anaRxStatus_prbs_Status_prbs_stky(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x4000,14,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_prbs_Status_prbs_stky(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x4000,14)
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK       0x4000
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS       1
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT      14

/* SGMII1_RX_afe :: anaRxStatus :: prbs_errors [13:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_prbs_Status_prbs_errors(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x3fff,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_prbs_Status_prbs_errors(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x3fff,0)
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_MASK     0x3fff
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_ALIGN    0
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_BITS     14
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_SHIFT    0


/* union - case prbs_Status_1 [15:00] */
/* SGMII1_RX_afe :: anaRxStatus :: sync_status [15:15] */
#define Wr_SGMII1_RX_afe_anaRxStatus_prbs_Status_1_sync_status(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x8000,15,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_prbs_Status_1_sync_status(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x8000,15)
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_MASK   0x8000
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_ALIGN  0
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_BITS   1
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_SHIFT  15

/* SGMII1_RX_afe :: anaRxStatus :: E_count [14:00] */
#define Wr_SGMII1_RX_afe_anaRxStatus_prbs_Status_1_E_count(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x7fff,0,x)
#define Rd_SGMII1_RX_afe_anaRxStatus_prbs_Status_1_E_count(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x7fff,0)
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_MASK       0x7fff
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_ALIGN      0
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_BITS       15
#define SGMII1_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_SHIFT      0



/****************************************************************************
 * SGMII1_RX_afe :: anaRxControl
 ***************************************************************************/
/* SGMII1_RX_afe :: anaRxControl :: rxSeqRestart_SM [15:15] */
#define Wr_SGMII1_RX_afe_anaRxControl_rxSeqRestart_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x8000,15,x)
#define Rd_SGMII1_RX_afe_anaRxControl_rxSeqRestart_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x8000,15)
#define SGMII1_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_MASK            0x8000
#define SGMII1_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_ALIGN           0
#define SGMII1_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_BITS            1
#define SGMII1_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_SHIFT           15

/* SGMII1_RX_afe :: anaRxControl :: fast_acq_en_r [14:14] */
#define Wr_SGMII1_RX_afe_anaRxControl_fast_acq_en_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x4000,14,x)
#define Rd_SGMII1_RX_afe_anaRxControl_fast_acq_en_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x4000,14)
#define SGMII1_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_MASK              0x4000
#define SGMII1_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_ALIGN             0
#define SGMII1_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_BITS              1
#define SGMII1_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_SHIFT             14

/* SGMII1_RX_afe :: anaRxControl :: fast_acq_en_force_r [13:13] */
#define Wr_SGMII1_RX_afe_anaRxControl_fast_acq_en_force_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x2000,13,x)
#define Rd_SGMII1_RX_afe_anaRxControl_fast_acq_en_force_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x2000,13)
#define SGMII1_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_MASK        0x2000
#define SGMII1_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_ALIGN       0
#define SGMII1_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_BITS        1
#define SGMII1_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_SHIFT       13

/* SGMII1_RX_afe :: anaRxControl :: sigDetected_en_SM [12:12] */
#define Wr_SGMII1_RX_afe_anaRxControl_sigDetected_en_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x1000,12,x)
#define Rd_SGMII1_RX_afe_anaRxControl_sigDetected_en_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x1000,12)
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_MASK          0x1000
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_ALIGN         0
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_BITS          1
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_SHIFT         12

/* SGMII1_RX_afe :: anaRxControl :: sigdetRestart_en_SM [11:11] */
#define Wr_SGMII1_RX_afe_anaRxControl_sigdetRestart_en_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x800,11,x)
#define Rd_SGMII1_RX_afe_anaRxControl_sigdetRestart_en_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x800,11)
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_MASK        0x0800
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_ALIGN       0
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_BITS        1
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_SHIFT       11

/* SGMII1_RX_afe :: anaRxControl :: sigdetMonitor_en_SM [10:10] */
#define Wr_SGMII1_RX_afe_anaRxControl_sigdetMonitor_en_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x400,10,x)
#define Rd_SGMII1_RX_afe_anaRxControl_sigdetMonitor_en_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x400,10)
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_MASK        0x0400
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_ALIGN       0
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_BITS        1
#define SGMII1_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_SHIFT       10

/* SGMII1_RX_afe :: anaRxControl :: override_sigdet_en [09:09] */
#define Wr_SGMII1_RX_afe_anaRxControl_override_sigdet_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x200,9,x)
#define Rd_SGMII1_RX_afe_anaRxControl_override_sigdet_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x200,9)
#define SGMII1_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK         0x0200
#define SGMII1_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN        0
#define SGMII1_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS         1
#define SGMII1_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT        9

/* SGMII1_RX_afe :: anaRxControl :: override_sigdet_val [08:08] */
#define Wr_SGMII1_RX_afe_anaRxControl_override_sigdet_val(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x100,8,x)
#define Rd_SGMII1_RX_afe_anaRxControl_override_sigdet_val(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x100,8)
#define SGMII1_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK        0x0100
#define SGMII1_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN       0
#define SGMII1_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS        1
#define SGMII1_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT       8

/* SGMII1_RX_afe :: anaRxControl :: reserved0 [07:07] */
#define SGMII1_RX_AFE_ANARXCONTROL_RESERVED0_MASK                  0x0080
#define SGMII1_RX_AFE_ANARXCONTROL_RESERVED0_ALIGN                 0
#define SGMII1_RX_AFE_ANARXCONTROL_RESERVED0_BITS                  1
#define SGMII1_RX_AFE_ANARXCONTROL_RESERVED0_SHIFT                 7

/* SGMII1_RX_afe :: anaRxControl :: phfreq_rst_dis_fst_SM [06:06] */
#define Wr_SGMII1_RX_afe_anaRxControl_phfreq_rst_dis_fst_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x40,6,x)
#define Rd_SGMII1_RX_afe_anaRxControl_phfreq_rst_dis_fst_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x40,6)
#define SGMII1_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_MASK      0x0040
#define SGMII1_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_ALIGN     0
#define SGMII1_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_BITS      1
#define SGMII1_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_SHIFT     6

/* SGMII1_RX_afe :: anaRxControl :: phfreq_rst_dis_nrml_SM [05:05] */
#define Wr_SGMII1_RX_afe_anaRxControl_phfreq_rst_dis_nrml_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxControl_phfreq_rst_dis_nrml_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x20,5)
#define SGMII1_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_MASK     0x0020
#define SGMII1_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_ALIGN    0
#define SGMII1_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_BITS     1
#define SGMII1_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_SHIFT    5

/* SGMII1_RX_afe :: anaRxControl :: forceRxSeqDone_SM [04:04] */
#define Wr_SGMII1_RX_afe_anaRxControl_forceRxSeqDone_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxControl_forceRxSeqDone_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x10,4)
#define SGMII1_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_MASK          0x0010
#define SGMII1_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_ALIGN         0
#define SGMII1_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_BITS          1
#define SGMII1_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_SHIFT         4

/* SGMII1_RX_afe :: anaRxControl :: flip_eyemon_polarity [03:03] */
#define Wr_SGMII1_RX_afe_anaRxControl_flip_eyemon_polarity(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxControl_flip_eyemon_polarity(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x8,3)
#define SGMII1_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_MASK       0x0008
#define SGMII1_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_ALIGN      0
#define SGMII1_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_BITS       1
#define SGMII1_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_SHIFT      3

/* SGMII1_RX_afe :: anaRxControl :: status_sel [02:00] */
#define Wr_SGMII1_RX_afe_anaRxControl_status_sel(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x7,0,x)
#define Rd_SGMII1_RX_afe_anaRxControl_status_sel(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL,0x7,0)
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_MASK                 0x0007
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_ALIGN                0
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_BITS                 3
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_SHIFT                0
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_sigdetStatus         0
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_syncStatus           1
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_rxTestSel            2
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_scaleStatus          3
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_adcCdrStatus         4
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_integStatus          5
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_vcoStatus            6
#define SGMII1_RX_AFE_ANARXCONTROL_STATUS_SEL_prbsStatus           7


/****************************************************************************
 * SGMII1_RX_afe :: ctrl0
 ***************************************************************************/
/* SGMII1_RX_afe :: ctrl0 :: slicer_pd [15:15] */
#define Wr_SGMII1_RX_afe_ctrl0_slicer_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL0,0x8000,15,x)
#define Rd_SGMII1_RX_afe_ctrl0_slicer_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL0,0x8000,15)
#define SGMII1_RX_AFE_CTRL0_SLICER_PD_MASK                         0x8000
#define SGMII1_RX_AFE_CTRL0_SLICER_PD_ALIGN                        0
#define SGMII1_RX_AFE_CTRL0_SLICER_PD_BITS                         1
#define SGMII1_RX_AFE_CTRL0_SLICER_PD_SHIFT                        15

/* SGMII1_RX_afe :: ctrl0 :: reserved_14_12 [14:12] */
#define SGMII1_RX_AFE_CTRL0_RESERVED_14_12_MASK                    0x7000
#define SGMII1_RX_AFE_CTRL0_RESERVED_14_12_ALIGN                   0
#define SGMII1_RX_AFE_CTRL0_RESERVED_14_12_BITS                    3
#define SGMII1_RX_AFE_CTRL0_RESERVED_14_12_SHIFT                   12

/* SGMII1_RX_afe :: ctrl0 :: RX_pon [11:08] */
#define Wr_SGMII1_RX_afe_ctrl0_RX_pon(x) WriteRegBits16(SGMII1_RX_AFE_CTRL0,0xf00,8,x)
#define Rd_SGMII1_RX_afe_ctrl0_RX_pon(x) ReadRegBits16(SGMII1_RX_AFE_CTRL0,0xf00,8)
#define SGMII1_RX_AFE_CTRL0_RX_PON_MASK                            0x0f00
#define SGMII1_RX_AFE_CTRL0_RX_PON_ALIGN                           0
#define SGMII1_RX_AFE_CTRL0_RX_PON_BITS                            4
#define SGMII1_RX_AFE_CTRL0_RX_PON_SHIFT                           8

/* SGMII1_RX_afe :: ctrl0 :: Filter_band [07:06] */
#define Wr_SGMII1_RX_afe_ctrl0_Filter_band(x) WriteRegBits16(SGMII1_RX_AFE_CTRL0,0xc0,6,x)
#define Rd_SGMII1_RX_afe_ctrl0_Filter_band(x) ReadRegBits16(SGMII1_RX_AFE_CTRL0,0xc0,6)
#define SGMII1_RX_AFE_CTRL0_FILTER_BAND_MASK                       0x00c0
#define SGMII1_RX_AFE_CTRL0_FILTER_BAND_ALIGN                      0
#define SGMII1_RX_AFE_CTRL0_FILTER_BAND_BITS                       2
#define SGMII1_RX_AFE_CTRL0_FILTER_BAND_SHIFT                      6

/* SGMII1_RX_afe :: ctrl0 :: reserved_5_3 [05:03] */
#define SGMII1_RX_AFE_CTRL0_RESERVED_5_3_MASK                      0x0038
#define SGMII1_RX_AFE_CTRL0_RESERVED_5_3_ALIGN                     0
#define SGMII1_RX_AFE_CTRL0_RESERVED_5_3_BITS                      3
#define SGMII1_RX_AFE_CTRL0_RESERVED_5_3_SHIFT                     3

/* SGMII1_RX_afe :: ctrl0 :: pd_lmtng [02:02] */
#define Wr_SGMII1_RX_afe_ctrl0_pd_lmtng(x) WriteRegBits16(SGMII1_RX_AFE_CTRL0,0x4,2,x)
#define Rd_SGMII1_RX_afe_ctrl0_pd_lmtng(x) ReadRegBits16(SGMII1_RX_AFE_CTRL0,0x4,2)
#define SGMII1_RX_AFE_CTRL0_PD_LMTNG_MASK                          0x0004
#define SGMII1_RX_AFE_CTRL0_PD_LMTNG_ALIGN                         0
#define SGMII1_RX_AFE_CTRL0_PD_LMTNG_BITS                          1
#define SGMII1_RX_AFE_CTRL0_PD_LMTNG_SHIFT                         2

/* SGMII1_RX_afe :: ctrl0 :: pd_eqz [01:01] */
#define Wr_SGMII1_RX_afe_ctrl0_pd_eqz(x) WriteRegBits16(SGMII1_RX_AFE_CTRL0,0x2,1,x)
#define Rd_SGMII1_RX_afe_ctrl0_pd_eqz(x) ReadRegBits16(SGMII1_RX_AFE_CTRL0,0x2,1)
#define SGMII1_RX_AFE_CTRL0_PD_EQZ_MASK                            0x0002
#define SGMII1_RX_AFE_CTRL0_PD_EQZ_ALIGN                           0
#define SGMII1_RX_AFE_CTRL0_PD_EQZ_BITS                            1
#define SGMII1_RX_AFE_CTRL0_PD_EQZ_SHIFT                           1

/* SGMII1_RX_afe :: ctrl0 :: reserved_0 [00:00] */
#define SGMII1_RX_AFE_CTRL0_RESERVED_0_MASK                        0x0001
#define SGMII1_RX_AFE_CTRL0_RESERVED_0_ALIGN                       0
#define SGMII1_RX_AFE_CTRL0_RESERVED_0_BITS                        1
#define SGMII1_RX_AFE_CTRL0_RESERVED_0_SHIFT                       0


/****************************************************************************
 * SGMII1_RX_afe :: ctrl1
 ***************************************************************************/
/* SGMII1_RX_afe :: ctrl1 :: demux_eyem_pd [15:15] */
#define Wr_SGMII1_RX_afe_ctrl1_demux_eyem_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL1,0x8000,15,x)
#define Rd_SGMII1_RX_afe_ctrl1_demux_eyem_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL1,0x8000,15)
#define SGMII1_RX_AFE_CTRL1_DEMUX_EYEM_PD_MASK                     0x8000
#define SGMII1_RX_AFE_CTRL1_DEMUX_EYEM_PD_ALIGN                    0
#define SGMII1_RX_AFE_CTRL1_DEMUX_EYEM_PD_BITS                     1
#define SGMII1_RX_AFE_CTRL1_DEMUX_EYEM_PD_SHIFT                    15

/* SGMII1_RX_afe :: ctrl1 :: demux_pd [14:14] */
#define Wr_SGMII1_RX_afe_ctrl1_demux_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL1,0x4000,14,x)
#define Rd_SGMII1_RX_afe_ctrl1_demux_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL1,0x4000,14)
#define SGMII1_RX_AFE_CTRL1_DEMUX_PD_MASK                          0x4000
#define SGMII1_RX_AFE_CTRL1_DEMUX_PD_ALIGN                         0
#define SGMII1_RX_AFE_CTRL1_DEMUX_PD_BITS                          1
#define SGMII1_RX_AFE_CTRL1_DEMUX_PD_SHIFT                         14

/* SGMII1_RX_afe :: ctrl1 :: demux_peak_pd [13:13] */
#define Wr_SGMII1_RX_afe_ctrl1_demux_peak_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL1,0x2000,13,x)
#define Rd_SGMII1_RX_afe_ctrl1_demux_peak_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL1,0x2000,13)
#define SGMII1_RX_AFE_CTRL1_DEMUX_PEAK_PD_MASK                     0x2000
#define SGMII1_RX_AFE_CTRL1_DEMUX_PEAK_PD_ALIGN                    0
#define SGMII1_RX_AFE_CTRL1_DEMUX_PEAK_PD_BITS                     1
#define SGMII1_RX_AFE_CTRL1_DEMUX_PEAK_PD_SHIFT                    13

/* SGMII1_RX_afe :: ctrl1 :: demux_zero_pd [12:12] */
#define Wr_SGMII1_RX_afe_ctrl1_demux_zero_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL1,0x1000,12,x)
#define Rd_SGMII1_RX_afe_ctrl1_demux_zero_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL1,0x1000,12)
#define SGMII1_RX_AFE_CTRL1_DEMUX_ZERO_PD_MASK                     0x1000
#define SGMII1_RX_AFE_CTRL1_DEMUX_ZERO_PD_ALIGN                    0
#define SGMII1_RX_AFE_CTRL1_DEMUX_ZERO_PD_BITS                     1
#define SGMII1_RX_AFE_CTRL1_DEMUX_ZERO_PD_SHIFT                    12

/* SGMII1_RX_afe :: ctrl1 :: div_4_demux_enable [11:11] */
#define Wr_SGMII1_RX_afe_ctrl1_div_4_demux_enable(x) WriteRegBits16(SGMII1_RX_AFE_CTRL1,0x800,11,x)
#define Rd_SGMII1_RX_afe_ctrl1_div_4_demux_enable(x) ReadRegBits16(SGMII1_RX_AFE_CTRL1,0x800,11)
#define SGMII1_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_MASK                0x0800
#define SGMII1_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_ALIGN               0
#define SGMII1_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_BITS                1
#define SGMII1_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_SHIFT               11

/* SGMII1_RX_afe :: ctrl1 :: reserved_26_17 [10:01] */
#define SGMII1_RX_AFE_CTRL1_RESERVED_26_17_MASK                    0x07fe
#define SGMII1_RX_AFE_CTRL1_RESERVED_26_17_ALIGN                   0
#define SGMII1_RX_AFE_CTRL1_RESERVED_26_17_BITS                    10
#define SGMII1_RX_AFE_CTRL1_RESERVED_26_17_SHIFT                   1

/* SGMII1_RX_afe :: ctrl1 :: eyem_pd [00:00] */
#define Wr_SGMII1_RX_afe_ctrl1_eyem_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL1,0x1,0,x)
#define Rd_SGMII1_RX_afe_ctrl1_eyem_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL1,0x1,0)
#define SGMII1_RX_AFE_CTRL1_EYEM_PD_MASK                           0x0001
#define SGMII1_RX_AFE_CTRL1_EYEM_PD_ALIGN                          0
#define SGMII1_RX_AFE_CTRL1_EYEM_PD_BITS                           1
#define SGMII1_RX_AFE_CTRL1_EYEM_PD_SHIFT                          0


/****************************************************************************
 * SGMII1_RX_afe :: anaRxSigdet
 ***************************************************************************/
/* SGMII1_RX_afe :: anaRxSigdet :: reserved0 [15:08] */
#define SGMII1_RX_AFE_ANARXSIGDET_RESERVED0_MASK                   0xff00
#define SGMII1_RX_AFE_ANARXSIGDET_RESERVED0_ALIGN                  0
#define SGMII1_RX_AFE_ANARXSIGDET_RESERVED0_BITS                   8
#define SGMII1_RX_AFE_ANARXSIGDET_RESERVED0_SHIFT                  8

/* SGMII1_RX_afe :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */
#define Wr_SGMII1_RX_afe_anaRxSigdet_cx4_sigdet_cnt_ld_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x80,7,x)
#define Rd_SGMII1_RX_afe_anaRxSigdet_cx4_sigdet_cnt_ld_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x80,7)
#define SGMII1_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK        0x0080
#define SGMII1_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN       0
#define SGMII1_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS        1
#define SGMII1_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT       7

/* SGMII1_RX_afe :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */
#define Wr_SGMII1_RX_afe_anaRxSigdet_ext_sigdet_en_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x40,6,x)
#define Rd_SGMII1_RX_afe_anaRxSigdet_ext_sigdet_en_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x40,6)
#define SGMII1_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK            0x0040
#define SGMII1_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN           0
#define SGMII1_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS            1
#define SGMII1_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT           6

/* SGMII1_RX_afe :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */
#define Wr_SGMII1_RX_afe_anaRxSigdet_cx4_sigdet_en_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxSigdet_cx4_sigdet_en_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x20,5)
#define SGMII1_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK            0x0020
#define SGMII1_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN           0
#define SGMII1_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS            1
#define SGMII1_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT           5

/* SGMII1_RX_afe :: anaRxSigdet :: rx_sigdet_r [04:04] */
#define Wr_SGMII1_RX_afe_anaRxSigdet_rx_sigdet_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxSigdet_rx_sigdet_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x10,4)
#define SGMII1_RX_AFE_ANARXSIGDET_RX_SIGDET_R_MASK                 0x0010
#define SGMII1_RX_AFE_ANARXSIGDET_RX_SIGDET_R_ALIGN                0
#define SGMII1_RX_AFE_ANARXSIGDET_RX_SIGDET_R_BITS                 1
#define SGMII1_RX_AFE_ANARXSIGDET_RX_SIGDET_R_SHIFT                4

/* SGMII1_RX_afe :: anaRxSigdet :: rx_sigdet_force_r [03:03] */
#define Wr_SGMII1_RX_afe_anaRxSigdet_rx_sigdet_force_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxSigdet_rx_sigdet_force_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x8,3)
#define SGMII1_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK           0x0008
#define SGMII1_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN          0
#define SGMII1_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS           1
#define SGMII1_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT          3

/* SGMII1_RX_afe :: anaRxSigdet :: invert_rx_sigdet [02:02] */
#define Wr_SGMII1_RX_afe_anaRxSigdet_invert_rx_sigdet(x) WriteRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxSigdet_invert_rx_sigdet(x) ReadRegBits16(SGMII1_RX_AFE_ANARXSIGDET,0x4,2)
#define SGMII1_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_MASK            0x0004
#define SGMII1_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN           0
#define SGMII1_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_BITS            1
#define SGMII1_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT           2

/* SGMII1_RX_afe :: anaRxSigdet :: reserved1 [01:00] */
#define SGMII1_RX_AFE_ANARXSIGDET_RESERVED1_MASK                   0x0003
#define SGMII1_RX_AFE_ANARXSIGDET_RESERVED1_ALIGN                  0
#define SGMII1_RX_AFE_ANARXSIGDET_RESERVED1_BITS                   2
#define SGMII1_RX_AFE_ANARXSIGDET_RESERVED1_SHIFT                  0


/****************************************************************************
 * SGMII1_RX_afe :: ctrl2
 ***************************************************************************/
/* SGMII1_RX_afe :: ctrl2 :: reserved_47_39 [15:07] */
#define SGMII1_RX_AFE_CTRL2_RESERVED_47_39_MASK                    0xff80
#define SGMII1_RX_AFE_CTRL2_RESERVED_47_39_ALIGN                   0
#define SGMII1_RX_AFE_CTRL2_RESERVED_47_39_BITS                    9
#define SGMII1_RX_AFE_CTRL2_RESERVED_47_39_SHIFT                   7

/* SGMII1_RX_afe :: ctrl2 :: inputerm_lowZvdd_en [06:06] */
#define Wr_SGMII1_RX_afe_ctrl2_inputerm_lowZvdd_en(x) WriteRegBits16(SGMII1_RX_AFE_CTRL2,0x40,6,x)
#define Rd_SGMII1_RX_afe_ctrl2_inputerm_lowZvdd_en(x) ReadRegBits16(SGMII1_RX_AFE_CTRL2,0x40,6)
#define SGMII1_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_MASK               0x0040
#define SGMII1_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_ALIGN              0
#define SGMII1_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_BITS               1
#define SGMII1_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_SHIFT              6

/* SGMII1_RX_afe :: ctrl2 :: inputerm_lowZgnd_en [05:05] */
#define Wr_SGMII1_RX_afe_ctrl2_inputerm_lowZgnd_en(x) WriteRegBits16(SGMII1_RX_AFE_CTRL2,0x20,5,x)
#define Rd_SGMII1_RX_afe_ctrl2_inputerm_lowZgnd_en(x) ReadRegBits16(SGMII1_RX_AFE_CTRL2,0x20,5)
#define SGMII1_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_MASK               0x0020
#define SGMII1_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_ALIGN              0
#define SGMII1_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_BITS               1
#define SGMII1_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_SHIFT              5

/* SGMII1_RX_afe :: ctrl2 :: inputerm_cmult_en [04:04] */
#define Wr_SGMII1_RX_afe_ctrl2_inputerm_cmult_en(x) WriteRegBits16(SGMII1_RX_AFE_CTRL2,0x10,4,x)
#define Rd_SGMII1_RX_afe_ctrl2_inputerm_cmult_en(x) ReadRegBits16(SGMII1_RX_AFE_CTRL2,0x10,4)
#define SGMII1_RX_AFE_CTRL2_INPUTERM_CMULT_EN_MASK                 0x0010
#define SGMII1_RX_AFE_CTRL2_INPUTERM_CMULT_EN_ALIGN                0
#define SGMII1_RX_AFE_CTRL2_INPUTERM_CMULT_EN_BITS                 1
#define SGMII1_RX_AFE_CTRL2_INPUTERM_CMULT_EN_SHIFT                4

/* SGMII1_RX_afe :: ctrl2 :: inputerm_cm_en [03:03] */
#define Wr_SGMII1_RX_afe_ctrl2_inputerm_cm_en(x) WriteRegBits16(SGMII1_RX_AFE_CTRL2,0x8,3,x)
#define Rd_SGMII1_RX_afe_ctrl2_inputerm_cm_en(x) ReadRegBits16(SGMII1_RX_AFE_CTRL2,0x8,3)
#define SGMII1_RX_AFE_CTRL2_INPUTERM_CM_EN_MASK                    0x0008
#define SGMII1_RX_AFE_CTRL2_INPUTERM_CM_EN_ALIGN                   0
#define SGMII1_RX_AFE_CTRL2_INPUTERM_CM_EN_BITS                    1
#define SGMII1_RX_AFE_CTRL2_INPUTERM_CM_EN_SHIFT                   3

/* SGMII1_RX_afe :: ctrl2 :: div10_pd [02:02] */
#define Wr_SGMII1_RX_afe_ctrl2_div10_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL2,0x4,2,x)
#define Rd_SGMII1_RX_afe_ctrl2_div10_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL2,0x4,2)
#define SGMII1_RX_AFE_CTRL2_DIV10_PD_MASK                          0x0004
#define SGMII1_RX_AFE_CTRL2_DIV10_PD_ALIGN                         0
#define SGMII1_RX_AFE_CTRL2_DIV10_PD_BITS                          1
#define SGMII1_RX_AFE_CTRL2_DIV10_PD_SHIFT                         2

/* SGMII1_RX_afe :: ctrl2 :: div4_pd [01:01] */
#define Wr_SGMII1_RX_afe_ctrl2_div4_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL2,0x2,1,x)
#define Rd_SGMII1_RX_afe_ctrl2_div4_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL2,0x2,1)
#define SGMII1_RX_AFE_CTRL2_DIV4_PD_MASK                           0x0002
#define SGMII1_RX_AFE_CTRL2_DIV4_PD_ALIGN                          0
#define SGMII1_RX_AFE_CTRL2_DIV4_PD_BITS                           1
#define SGMII1_RX_AFE_CTRL2_DIV4_PD_SHIFT                          1

/* SGMII1_RX_afe :: ctrl2 :: reserved_32 [00:00] */
#define SGMII1_RX_AFE_CTRL2_RESERVED_32_MASK                       0x0001
#define SGMII1_RX_AFE_CTRL2_RESERVED_32_ALIGN                      0
#define SGMII1_RX_AFE_CTRL2_RESERVED_32_BITS                       1
#define SGMII1_RX_AFE_CTRL2_RESERVED_32_SHIFT                      0


/****************************************************************************
 * SGMII1_RX_afe :: ctrl3
 ***************************************************************************/
/* SGMII1_RX_afe :: ctrl3 :: reserved_63_58 [15:10] */
#define SGMII1_RX_AFE_CTRL3_RESERVED_63_58_MASK                    0xfc00
#define SGMII1_RX_AFE_CTRL3_RESERVED_63_58_ALIGN                   0
#define SGMII1_RX_AFE_CTRL3_RESERVED_63_58_BITS                    6
#define SGMII1_RX_AFE_CTRL3_RESERVED_63_58_SHIFT                   10

/* SGMII1_RX_afe :: ctrl3 :: pd_bias [09:09] */
#define Wr_SGMII1_RX_afe_ctrl3_pd_bias(x) WriteRegBits16(SGMII1_RX_AFE_CTRL3,0x200,9,x)
#define Rd_SGMII1_RX_afe_ctrl3_pd_bias(x) ReadRegBits16(SGMII1_RX_AFE_CTRL3,0x200,9)
#define SGMII1_RX_AFE_CTRL3_PD_BIAS_MASK                           0x0200
#define SGMII1_RX_AFE_CTRL3_PD_BIAS_ALIGN                          0
#define SGMII1_RX_AFE_CTRL3_PD_BIAS_BITS                           1
#define SGMII1_RX_AFE_CTRL3_PD_BIAS_SHIFT                          9

/* SGMII1_RX_afe :: ctrl3 :: Duty_Cycle [08:06] */
#define Wr_SGMII1_RX_afe_ctrl3_Duty_Cycle(x) WriteRegBits16(SGMII1_RX_AFE_CTRL3,0x1c0,6,x)
#define Rd_SGMII1_RX_afe_ctrl3_Duty_Cycle(x) ReadRegBits16(SGMII1_RX_AFE_CTRL3,0x1c0,6)
#define SGMII1_RX_AFE_CTRL3_DUTY_CYCLE_MASK                        0x01c0
#define SGMII1_RX_AFE_CTRL3_DUTY_CYCLE_ALIGN                       0
#define SGMII1_RX_AFE_CTRL3_DUTY_CYCLE_BITS                        3
#define SGMII1_RX_AFE_CTRL3_DUTY_CYCLE_SHIFT                       6

/* SGMII1_RX_afe :: ctrl3 :: Dcc_en [05:05] */
#define Wr_SGMII1_RX_afe_ctrl3_Dcc_en(x) WriteRegBits16(SGMII1_RX_AFE_CTRL3,0x20,5,x)
#define Rd_SGMII1_RX_afe_ctrl3_Dcc_en(x) ReadRegBits16(SGMII1_RX_AFE_CTRL3,0x20,5)
#define SGMII1_RX_AFE_CTRL3_DCC_EN_MASK                            0x0020
#define SGMII1_RX_AFE_CTRL3_DCC_EN_ALIGN                           0
#define SGMII1_RX_AFE_CTRL3_DCC_EN_BITS                            1
#define SGMII1_RX_AFE_CTRL3_DCC_EN_SHIFT                           5

/* SGMII1_RX_afe :: ctrl3 :: reserved_52_48 [04:00] */
#define SGMII1_RX_AFE_CTRL3_RESERVED_52_48_MASK                    0x001f
#define SGMII1_RX_AFE_CTRL3_RESERVED_52_48_ALIGN                   0
#define SGMII1_RX_AFE_CTRL3_RESERVED_52_48_BITS                    5
#define SGMII1_RX_AFE_CTRL3_RESERVED_52_48_SHIFT                   0


/****************************************************************************
 * SGMII1_RX_afe :: ctrl4
 ***************************************************************************/
/* SGMII1_RX_afe :: ctrl4 :: en_testmux [15:15] */
#define Wr_SGMII1_RX_afe_ctrl4_en_testmux(x) WriteRegBits16(SGMII1_RX_AFE_CTRL4,0x8000,15,x)
#define Rd_SGMII1_RX_afe_ctrl4_en_testmux(x) ReadRegBits16(SGMII1_RX_AFE_CTRL4,0x8000,15)
#define SGMII1_RX_AFE_CTRL4_EN_TESTMUX_MASK                        0x8000
#define SGMII1_RX_AFE_CTRL4_EN_TESTMUX_ALIGN                       0
#define SGMII1_RX_AFE_CTRL4_EN_TESTMUX_BITS                        1
#define SGMII1_RX_AFE_CTRL4_EN_TESTMUX_SHIFT                       15

/* SGMII1_RX_afe :: ctrl4 :: Sigdet_modeselect [14:14] */
#define Wr_SGMII1_RX_afe_ctrl4_Sigdet_modeselect(x) WriteRegBits16(SGMII1_RX_AFE_CTRL4,0x4000,14,x)
#define Rd_SGMII1_RX_afe_ctrl4_Sigdet_modeselect(x) ReadRegBits16(SGMII1_RX_AFE_CTRL4,0x4000,14)
#define SGMII1_RX_AFE_CTRL4_SIGDET_MODESELECT_MASK                 0x4000
#define SGMII1_RX_AFE_CTRL4_SIGDET_MODESELECT_ALIGN                0
#define SGMII1_RX_AFE_CTRL4_SIGDET_MODESELECT_BITS                 1
#define SGMII1_RX_AFE_CTRL4_SIGDET_MODESELECT_SHIFT                14

/* SGMII1_RX_afe :: ctrl4 :: sigdet_pd [13:13] */
#define Wr_SGMII1_RX_afe_ctrl4_sigdet_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL4,0x2000,13,x)
#define Rd_SGMII1_RX_afe_ctrl4_sigdet_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL4,0x2000,13)
#define SGMII1_RX_AFE_CTRL4_SIGDET_PD_MASK                         0x2000
#define SGMII1_RX_AFE_CTRL4_SIGDET_PD_ALIGN                        0
#define SGMII1_RX_AFE_CTRL4_SIGDET_PD_BITS                         1
#define SGMII1_RX_AFE_CTRL4_SIGDET_PD_SHIFT                        13

/* SGMII1_RX_afe :: ctrl4 :: sigdet_bypass [12:12] */
#define Wr_SGMII1_RX_afe_ctrl4_sigdet_bypass(x) WriteRegBits16(SGMII1_RX_AFE_CTRL4,0x1000,12,x)
#define Rd_SGMII1_RX_afe_ctrl4_sigdet_bypass(x) ReadRegBits16(SGMII1_RX_AFE_CTRL4,0x1000,12)
#define SGMII1_RX_AFE_CTRL4_SIGDET_BYPASS_MASK                     0x1000
#define SGMII1_RX_AFE_CTRL4_SIGDET_BYPASS_ALIGN                    0
#define SGMII1_RX_AFE_CTRL4_SIGDET_BYPASS_BITS                     1
#define SGMII1_RX_AFE_CTRL4_SIGDET_BYPASS_SHIFT                    12

/* SGMII1_RX_afe :: ctrl4 :: bias_sigdet_ctrl [11:09] */
#define Wr_SGMII1_RX_afe_ctrl4_bias_sigdet_ctrl(x) WriteRegBits16(SGMII1_RX_AFE_CTRL4,0xe00,9,x)
#define Rd_SGMII1_RX_afe_ctrl4_bias_sigdet_ctrl(x) ReadRegBits16(SGMII1_RX_AFE_CTRL4,0xe00,9)
#define SGMII1_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_MASK                  0x0e00
#define SGMII1_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_ALIGN                 0
#define SGMII1_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_BITS                  3
#define SGMII1_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_SHIFT                 9

/* SGMII1_RX_afe :: ctrl4 :: bias_eyem_ctrl [08:06] */
#define Wr_SGMII1_RX_afe_ctrl4_bias_eyem_ctrl(x) WriteRegBits16(SGMII1_RX_AFE_CTRL4,0x1c0,6,x)
#define Rd_SGMII1_RX_afe_ctrl4_bias_eyem_ctrl(x) ReadRegBits16(SGMII1_RX_AFE_CTRL4,0x1c0,6)
#define SGMII1_RX_AFE_CTRL4_BIAS_EYEM_CTRL_MASK                    0x01c0
#define SGMII1_RX_AFE_CTRL4_BIAS_EYEM_CTRL_ALIGN                   0
#define SGMII1_RX_AFE_CTRL4_BIAS_EYEM_CTRL_BITS                    3
#define SGMII1_RX_AFE_CTRL4_BIAS_EYEM_CTRL_SHIFT                   6

/* SGMII1_RX_afe :: ctrl4 :: bias_la_dac_ctrl [05:03] */
#define Wr_SGMII1_RX_afe_ctrl4_bias_la_dac_ctrl(x) WriteRegBits16(SGMII1_RX_AFE_CTRL4,0x38,3,x)
#define Rd_SGMII1_RX_afe_ctrl4_bias_la_dac_ctrl(x) ReadRegBits16(SGMII1_RX_AFE_CTRL4,0x38,3)
#define SGMII1_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_MASK                  0x0038
#define SGMII1_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_ALIGN                 0
#define SGMII1_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_BITS                  3
#define SGMII1_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_SHIFT                 3

/* SGMII1_RX_afe :: ctrl4 :: bias_la_ctrl [02:00] */
#define Wr_SGMII1_RX_afe_ctrl4_bias_la_ctrl(x) WriteRegBits16(SGMII1_RX_AFE_CTRL4,0x7,0,x)
#define Rd_SGMII1_RX_afe_ctrl4_bias_la_ctrl(x) ReadRegBits16(SGMII1_RX_AFE_CTRL4,0x7,0)
#define SGMII1_RX_AFE_CTRL4_BIAS_LA_CTRL_MASK                      0x0007
#define SGMII1_RX_AFE_CTRL4_BIAS_LA_CTRL_ALIGN                     0
#define SGMII1_RX_AFE_CTRL4_BIAS_LA_CTRL_BITS                      3
#define SGMII1_RX_AFE_CTRL4_BIAS_LA_CTRL_SHIFT                     0


/****************************************************************************
 * SGMII1_RX_afe :: anaRxTest
 ***************************************************************************/
/* SGMII1_RX_afe :: anaRxTest :: sigdet_mux_SM [15:12] */
#define Wr_SGMII1_RX_afe_anaRxTest_sigdet_mux_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXTEST,0xf000,12,x)
#define Rd_SGMII1_RX_afe_anaRxTest_sigdet_mux_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXTEST,0xf000,12)
#define SGMII1_RX_AFE_ANARXTEST_SIGDET_MUX_SM_MASK                 0xf000
#define SGMII1_RX_AFE_ANARXTEST_SIGDET_MUX_SM_ALIGN                0
#define SGMII1_RX_AFE_ANARXTEST_SIGDET_MUX_SM_BITS                 4
#define SGMII1_RX_AFE_ANARXTEST_SIGDET_MUX_SM_SHIFT                12

/* SGMII1_RX_afe :: anaRxTest :: reserved0 [11:09] */
#define SGMII1_RX_AFE_ANARXTEST_RESERVED0_MASK                     0x0e00
#define SGMII1_RX_AFE_ANARXTEST_RESERVED0_ALIGN                    0
#define SGMII1_RX_AFE_ANARXTEST_RESERVED0_BITS                     3
#define SGMII1_RX_AFE_ANARXTEST_RESERVED0_SHIFT                    9

/* SGMII1_RX_afe :: anaRxTest :: tpctrl_SM [08:04] */
#define Wr_SGMII1_RX_afe_anaRxTest_tpctrl_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXTEST,0x1f0,4,x)
#define Rd_SGMII1_RX_afe_anaRxTest_tpctrl_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXTEST,0x1f0,4)
#define SGMII1_RX_AFE_ANARXTEST_TPCTRL_SM_MASK                     0x01f0
#define SGMII1_RX_AFE_ANARXTEST_TPCTRL_SM_ALIGN                    0
#define SGMII1_RX_AFE_ANARXTEST_TPCTRL_SM_BITS                     5
#define SGMII1_RX_AFE_ANARXTEST_TPCTRL_SM_SHIFT                    4

/* SGMII1_RX_afe :: anaRxTest :: testMuxSelect_SM [03:00] */
#define Wr_SGMII1_RX_afe_anaRxTest_testMuxSelect_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXTEST,0xf,0,x)
#define Rd_SGMII1_RX_afe_anaRxTest_testMuxSelect_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXTEST,0xf,0)
#define SGMII1_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_MASK              0x000f
#define SGMII1_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_ALIGN             0
#define SGMII1_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_BITS              4
#define SGMII1_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_SHIFT             0


/****************************************************************************
 * SGMII1_RX_afe :: anaRxControl1G
 ***************************************************************************/
/* SGMII1_RX_afe :: anaRxControl1G :: fpat_md [15:15] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_fpat_md(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x8000,15,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_fpat_md(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x8000,15)
#define SGMII1_RX_AFE_ANARXCONTROL1G_FPAT_MD_MASK                  0x8000
#define SGMII1_RX_AFE_ANARXCONTROL1G_FPAT_MD_ALIGN                 0
#define SGMII1_RX_AFE_ANARXCONTROL1G_FPAT_MD_BITS                  1
#define SGMII1_RX_AFE_ANARXCONTROL1G_FPAT_MD_SHIFT                 15

/* SGMII1_RX_afe :: anaRxControl1G :: pkt_count_en [14:14] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_pkt_count_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x4000,14,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_pkt_count_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x4000,14)
#define SGMII1_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_MASK             0x4000
#define SGMII1_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN            0
#define SGMII1_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_BITS             1
#define SGMII1_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT            14

/* SGMII1_RX_afe :: anaRxControl1G :: staMuxRegDis [13:13] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_staMuxRegDis(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x2000,13,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_staMuxRegDis(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x2000,13)
#define SGMII1_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_MASK             0x2000
#define SGMII1_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_ALIGN            0
#define SGMII1_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_BITS             1
#define SGMII1_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_SHIFT            13

/* SGMII1_RX_afe :: anaRxControl1G :: prbs_clr_dis [12:12] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_prbs_clr_dis(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x1000,12,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_prbs_clr_dis(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x1000,12)
#define SGMII1_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_MASK             0x1000
#define SGMII1_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN            0
#define SGMII1_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_BITS             1
#define SGMII1_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT            12

/* SGMII1_RX_afe :: anaRxControl1G :: rxd_dec_sel [11:11] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_rxd_dec_sel(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x800,11,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_rxd_dec_sel(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x800,11)
#define SGMII1_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_MASK              0x0800
#define SGMII1_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN             0
#define SGMII1_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_BITS              1
#define SGMII1_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT             11

/* SGMII1_RX_afe :: anaRxControl1G :: cgbad_tst [10:10] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_cgbad_tst(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x400,10,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_cgbad_tst(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x400,10)
#define SGMII1_RX_AFE_ANARXCONTROL1G_CGBAD_TST_MASK                0x0400
#define SGMII1_RX_AFE_ANARXCONTROL1G_CGBAD_TST_ALIGN               0
#define SGMII1_RX_AFE_ANARXCONTROL1G_CGBAD_TST_BITS                1
#define SGMII1_RX_AFE_ANARXCONTROL1G_CGBAD_TST_SHIFT               10

/* SGMII1_RX_afe :: anaRxControl1G :: Emon_en [09:09] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_Emon_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x200,9,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_Emon_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x200,9)
#define SGMII1_RX_AFE_ANARXCONTROL1G_EMON_EN_MASK                  0x0200
#define SGMII1_RX_AFE_ANARXCONTROL1G_EMON_EN_ALIGN                 0
#define SGMII1_RX_AFE_ANARXCONTROL1G_EMON_EN_BITS                  1
#define SGMII1_RX_AFE_ANARXCONTROL1G_EMON_EN_SHIFT                 9

/* SGMII1_RX_afe :: anaRxControl1G :: prbs_en [08:08] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_prbs_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x100,8,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_prbs_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x100,8)
#define SGMII1_RX_AFE_ANARXCONTROL1G_PRBS_EN_MASK                  0x0100
#define SGMII1_RX_AFE_ANARXCONTROL1G_PRBS_EN_ALIGN                 0
#define SGMII1_RX_AFE_ANARXCONTROL1G_PRBS_EN_BITS                  1
#define SGMII1_RX_AFE_ANARXCONTROL1G_PRBS_EN_SHIFT                 8

/* SGMII1_RX_afe :: anaRxControl1G :: cgbad_en [07:07] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_cgbad_en(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x80,7,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_cgbad_en(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x80,7)
#define SGMII1_RX_AFE_ANARXCONTROL1G_CGBAD_EN_MASK                 0x0080
#define SGMII1_RX_AFE_ANARXCONTROL1G_CGBAD_EN_ALIGN                0
#define SGMII1_RX_AFE_ANARXCONTROL1G_CGBAD_EN_BITS                 1
#define SGMII1_RX_AFE_ANARXCONTROL1G_CGBAD_EN_SHIFT                7

/* SGMII1_RX_afe :: anaRxControl1G :: cstretch [06:06] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_cstretch(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x40,6,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_cstretch(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x40,6)
#define SGMII1_RX_AFE_ANARXCONTROL1G_CSTRETCH_MASK                 0x0040
#define SGMII1_RX_AFE_ANARXCONTROL1G_CSTRETCH_ALIGN                0
#define SGMII1_RX_AFE_ANARXCONTROL1G_CSTRETCH_BITS                 1
#define SGMII1_RX_AFE_ANARXCONTROL1G_CSTRETCH_SHIFT                6

/* SGMII1_RX_afe :: anaRxControl1G :: rtbi_ckflip [05:05] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_rtbi_ckflip(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_rtbi_ckflip(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x20,5)
#define SGMII1_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_MASK              0x0020
#define SGMII1_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_ALIGN             0
#define SGMII1_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_BITS              1
#define SGMII1_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_SHIFT             5

/* SGMII1_RX_afe :: anaRxControl1G :: rtbi_flip [04:04] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_rtbi_flip(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_rtbi_flip(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x10,4)
#define SGMII1_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_MASK                0x0010
#define SGMII1_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_ALIGN               0
#define SGMII1_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_BITS                1
#define SGMII1_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_SHIFT               4

/* SGMII1_RX_afe :: anaRxControl1G :: phase_sel_SM [03:03] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_phase_sel_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_phase_sel_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x8,3)
#define SGMII1_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_MASK             0x0008
#define SGMII1_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_ALIGN            0
#define SGMII1_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_BITS             1
#define SGMII1_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_SHIFT            3

/* SGMII1_RX_afe :: anaRxControl1G :: spd_rstb_dis_SM [02:02] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_spd_rstb_dis_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_spd_rstb_dis_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x4,2)
#define SGMII1_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_MASK          0x0004
#define SGMII1_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_ALIGN         0
#define SGMII1_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_BITS          1
#define SGMII1_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_SHIFT         2

/* SGMII1_RX_afe :: anaRxControl1G :: freq_sel_force [01:01] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_freq_sel_force(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x2,1,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_freq_sel_force(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x2,1)
#define SGMII1_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK           0x0002
#define SGMII1_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN          0
#define SGMII1_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS           1
#define SGMII1_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT          1

/* SGMII1_RX_afe :: anaRxControl1G :: freq_sel [00:00] */
#define Wr_SGMII1_RX_afe_anaRxControl1G_freq_sel(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x1,0,x)
#define Rd_SGMII1_RX_afe_anaRxControl1G_freq_sel(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROL1G,0x1,0)
#define SGMII1_RX_AFE_ANARXCONTROL1G_FREQ_SEL_MASK                 0x0001
#define SGMII1_RX_AFE_ANARXCONTROL1G_FREQ_SEL_ALIGN                0
#define SGMII1_RX_AFE_ANARXCONTROL1G_FREQ_SEL_BITS                 1
#define SGMII1_RX_AFE_ANARXCONTROL1G_FREQ_SEL_SHIFT                0


/****************************************************************************
 * SGMII1_RX_afe :: anaRxControlPci
 ***************************************************************************/
/* SGMII1_RX_afe :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_comma_adj_sync_sel(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x8000,15,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_comma_adj_sync_sel(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x8000,15)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK      0x8000
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN     0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS      1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT     15

/* SGMII1_RX_afe :: anaRxControlPci :: comma_mask_force_r [14:14] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_comma_mask_force_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x4000,14,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_comma_mask_force_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x4000,14)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK      0x4000
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN     0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS      1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT     14

/* SGMII1_RX_afe :: anaRxControlPci :: comma_mask_r [13:13] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_comma_mask_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x2000,13,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_comma_mask_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x2000,13)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_MASK            0x2000
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN           0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_BITS            1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT           13

/* SGMII1_RX_afe :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_sync_status_force_sync_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x1000,12,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_sync_status_force_sync_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x1000,12)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12

/* SGMII1_RX_afe :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_sync_status_force_r_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x800,11,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_sync_status_force_r_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x800,11)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK  0x0800
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS  1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11

/* SGMII1_RX_afe :: anaRxControlPci :: sync_status_force_r [10:10] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_sync_status_force_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x400,10,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_sync_status_force_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x400,10)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK     0x0400
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN    0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS     1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT    10

/* SGMII1_RX_afe :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_comma_adj_en_force_ext_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x200,9,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_comma_adj_en_force_ext_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x200,9)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9

/* SGMII1_RX_afe :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_comma_adj_en_force_sync_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x100,8,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_comma_adj_en_force_sync_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x100,8)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8

/* SGMII1_RX_afe :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_comma_adj_en_force_r_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x80,7,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_comma_adj_en_force_r_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x80,7)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7

/* SGMII1_RX_afe :: anaRxControlPci :: comma_adj_en_r [06:06] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_comma_adj_en_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x40,6,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_comma_adj_en_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x40,6)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK          0x0040
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN         0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS          1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT         6

/* SGMII1_RX_afe :: anaRxControlPci :: link_en_force_SM [05:05] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_link_en_force_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x20,5,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_link_en_force_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x20,5)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK        0x0020
#define SGMII1_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN       0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS        1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT       5

/* SGMII1_RX_afe :: anaRxControlPci :: link_en_r [04:04] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_link_en_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x10,4,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_link_en_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x10,4)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_MASK               0x0010
#define SGMII1_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_ALIGN              0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_BITS               1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_SHIFT              4

/* SGMII1_RX_afe :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_rx_polarity_force_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x8,3,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_rx_polarity_force_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x8,3)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK    0x0008
#define SGMII1_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN   0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS    1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT   3

/* SGMII1_RX_afe :: anaRxControlPci :: rx_polarity_r [02:02] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_rx_polarity_r(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x4,2,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_rx_polarity_r(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x4,2)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_MASK           0x0004
#define SGMII1_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN          0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_BITS           1
#define SGMII1_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT          2

/* SGMII1_RX_afe :: anaRxControlPci :: integ_mode_SM [01:00] */
#define Wr_SGMII1_RX_afe_anaRxControlPci_integ_mode_SM(x) WriteRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x3,0,x)
#define Rd_SGMII1_RX_afe_anaRxControlPci_integ_mode_SM(x) ReadRegBits16(SGMII1_RX_AFE_ANARXCONTROLPCI,0x3,0)
#define SGMII1_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_MASK           0x0003
#define SGMII1_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN          0
#define SGMII1_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_BITS           2
#define SGMII1_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT          0


/****************************************************************************
 * SGMII1_RX_afe :: anaRxAstatus
 ***************************************************************************/
/* SGMII1_RX_afe :: anaRxAstatus :: genstat [15:00] */
#define Wr_SGMII1_RX_afe_anaRxAstatus_genstat(x) WriteReg16(SGMII1_RX_AFE_ANARXASTATUS,x)
#define Rd_SGMII1_RX_afe_anaRxAstatus_genstat(x) ReadReg16(SGMII1_RX_AFE_ANARXASTATUS)
#define SGMII1_RX_AFE_ANARXASTATUS_GENSTAT_MASK                    0xffff
#define SGMII1_RX_AFE_ANARXASTATUS_GENSTAT_ALIGN                   0
#define SGMII1_RX_AFE_ANARXASTATUS_GENSTAT_BITS                    16
#define SGMII1_RX_AFE_ANARXASTATUS_GENSTAT_SHIFT                   0


/****************************************************************************
 * SGMII1_RX_afe :: ctrl5
 ***************************************************************************/
/* SGMII1_RX_afe :: ctrl5 :: sigdet_usb_en [15:15] */
#define Wr_SGMII1_RX_afe_ctrl5_sigdet_usb_en(x) WriteRegBits16(SGMII1_RX_AFE_CTRL5,0x8000,15,x)
#define Rd_SGMII1_RX_afe_ctrl5_sigdet_usb_en(x) ReadRegBits16(SGMII1_RX_AFE_CTRL5,0x8000,15)
#define SGMII1_RX_AFE_CTRL5_SIGDET_USB_EN_MASK                     0x8000
#define SGMII1_RX_AFE_CTRL5_SIGDET_USB_EN_ALIGN                    0
#define SGMII1_RX_AFE_CTRL5_SIGDET_USB_EN_BITS                     1
#define SGMII1_RX_AFE_CTRL5_SIGDET_USB_EN_SHIFT                    15

/* SGMII1_RX_afe :: ctrl5 :: pi_eyem_enable [14:14] */
#define Wr_SGMII1_RX_afe_ctrl5_pi_eyem_enable(x) WriteRegBits16(SGMII1_RX_AFE_CTRL5,0x4000,14,x)
#define Rd_SGMII1_RX_afe_ctrl5_pi_eyem_enable(x) ReadRegBits16(SGMII1_RX_AFE_CTRL5,0x4000,14)
#define SGMII1_RX_AFE_CTRL5_PI_EYEM_ENABLE_MASK                    0x4000
#define SGMII1_RX_AFE_CTRL5_PI_EYEM_ENABLE_ALIGN                   0
#define SGMII1_RX_AFE_CTRL5_PI_EYEM_ENABLE_BITS                    1
#define SGMII1_RX_AFE_CTRL5_PI_EYEM_ENABLE_SHIFT                   14

/* SGMII1_RX_afe :: ctrl5 :: pi_main_enable [13:13] */
#define Wr_SGMII1_RX_afe_ctrl5_pi_main_enable(x) WriteRegBits16(SGMII1_RX_AFE_CTRL5,0x2000,13,x)
#define Rd_SGMII1_RX_afe_ctrl5_pi_main_enable(x) ReadRegBits16(SGMII1_RX_AFE_CTRL5,0x2000,13)
#define SGMII1_RX_AFE_CTRL5_PI_MAIN_ENABLE_MASK                    0x2000
#define SGMII1_RX_AFE_CTRL5_PI_MAIN_ENABLE_ALIGN                   0
#define SGMII1_RX_AFE_CTRL5_PI_MAIN_ENABLE_BITS                    1
#define SGMII1_RX_AFE_CTRL5_PI_MAIN_ENABLE_SHIFT                   13

/* SGMII1_RX_afe :: ctrl5 :: eyemonitor_ref_zero [12:12] */
#define Wr_SGMII1_RX_afe_ctrl5_eyemonitor_ref_zero(x) WriteRegBits16(SGMII1_RX_AFE_CTRL5,0x1000,12,x)
#define Rd_SGMII1_RX_afe_ctrl5_eyemonitor_ref_zero(x) ReadRegBits16(SGMII1_RX_AFE_CTRL5,0x1000,12)
#define SGMII1_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_MASK               0x1000
#define SGMII1_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_ALIGN              0
#define SGMII1_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_BITS               1
#define SGMII1_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_SHIFT              12

/* SGMII1_RX_afe :: ctrl5 :: eyemonitorref_pd [11:11] */
#define Wr_SGMII1_RX_afe_ctrl5_eyemonitorref_pd(x) WriteRegBits16(SGMII1_RX_AFE_CTRL5,0x800,11,x)
#define Rd_SGMII1_RX_afe_ctrl5_eyemonitorref_pd(x) ReadRegBits16(SGMII1_RX_AFE_CTRL5,0x800,11)
#define SGMII1_RX_AFE_CTRL5_EYEMONITORREF_PD_MASK                  0x0800
#define SGMII1_RX_AFE_CTRL5_EYEMONITORREF_PD_ALIGN                 0
#define SGMII1_RX_AFE_CTRL5_EYEMONITORREF_PD_BITS                  1
#define SGMII1_RX_AFE_CTRL5_EYEMONITORREF_PD_SHIFT                 11

/* SGMII1_RX_afe :: ctrl5 :: eyem_refadjust [10:06] */
#define Wr_SGMII1_RX_afe_ctrl5_eyem_refadjust(x) WriteRegBits16(SGMII1_RX_AFE_CTRL5,0x7c0,6,x)
#define Rd_SGMII1_RX_afe_ctrl5_eyem_refadjust(x) ReadRegBits16(SGMII1_RX_AFE_CTRL5,0x7c0,6)
#define SGMII1_RX_AFE_CTRL5_EYEM_REFADJUST_MASK                    0x07c0
#define SGMII1_RX_AFE_CTRL5_EYEM_REFADJUST_ALIGN                   0
#define SGMII1_RX_AFE_CTRL5_EYEM_REFADJUST_BITS                    5
#define SGMII1_RX_AFE_CTRL5_EYEM_REFADJUST_SHIFT                   6

/* SGMII1_RX_afe :: ctrl5 :: sel_clk [05:04] */
#define Wr_SGMII1_RX_afe_ctrl5_sel_clk(x) WriteRegBits16(SGMII1_RX_AFE_CTRL5,0x30,4,x)
#define Rd_SGMII1_RX_afe_ctrl5_sel_clk(x) ReadRegBits16(SGMII1_RX_AFE_CTRL5,0x30,4)
#define SGMII1_RX_AFE_CTRL5_SEL_CLK_MASK                           0x0030
#define SGMII1_RX_AFE_CTRL5_SEL_CLK_ALIGN                          0
#define SGMII1_RX_AFE_CTRL5_SEL_CLK_BITS                           2
#define SGMII1_RX_AFE_CTRL5_SEL_CLK_SHIFT                          4

/* SGMII1_RX_afe :: ctrl5 :: Sigdet_threshold [03:00] */
#define Wr_SGMII1_RX_afe_ctrl5_Sigdet_threshold(x) WriteRegBits16(SGMII1_RX_AFE_CTRL5,0xf,0,x)
#define Rd_SGMII1_RX_afe_ctrl5_Sigdet_threshold(x) ReadRegBits16(SGMII1_RX_AFE_CTRL5,0xf,0)
#define SGMII1_RX_AFE_CTRL5_SIGDET_THRESHOLD_MASK                  0x000f
#define SGMII1_RX_AFE_CTRL5_SIGDET_THRESHOLD_ALIGN                 0
#define SGMII1_RX_AFE_CTRL5_SIGDET_THRESHOLD_BITS                  4
#define SGMII1_RX_AFE_CTRL5_SIGDET_THRESHOLD_SHIFT                 0


/****************************************************************************
 * SGMII1_RX_afe :: ctrl6
 ***************************************************************************/
/* SGMII1_RX_afe :: ctrl6 :: reserved0 [15:10] */
#define SGMII1_RX_AFE_CTRL6_RESERVED0_MASK                         0xfc00
#define SGMII1_RX_AFE_CTRL6_RESERVED0_ALIGN                        0
#define SGMII1_RX_AFE_CTRL6_RESERVED0_BITS                         6
#define SGMII1_RX_AFE_CTRL6_RESERVED0_SHIFT                        10

/* SGMII1_RX_afe :: ctrl6 :: reserved_105_103 [09:07] */
#define SGMII1_RX_AFE_CTRL6_RESERVED_105_103_MASK                  0x0380
#define SGMII1_RX_AFE_CTRL6_RESERVED_105_103_ALIGN                 0
#define SGMII1_RX_AFE_CTRL6_RESERVED_105_103_BITS                  3
#define SGMII1_RX_AFE_CTRL6_RESERVED_105_103_SHIFT                 7

/* SGMII1_RX_afe :: ctrl6 :: Eye_Monitor_PI_BW_sel [06:06] */
#define Wr_SGMII1_RX_afe_ctrl6_Eye_Monitor_PI_BW_sel(x) WriteRegBits16(SGMII1_RX_AFE_CTRL6,0x40,6,x)
#define Rd_SGMII1_RX_afe_ctrl6_Eye_Monitor_PI_BW_sel(x) ReadRegBits16(SGMII1_RX_AFE_CTRL6,0x40,6)
#define SGMII1_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_MASK             0x0040
#define SGMII1_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_ALIGN            0
#define SGMII1_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_BITS             1
#define SGMII1_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_SHIFT            6

/* SGMII1_RX_afe :: ctrl6 :: Eye_Monitor_PI_pwd_lvl2pi [05:05] */
#define Wr_SGMII1_RX_afe_ctrl6_Eye_Monitor_PI_pwd_lvl2pi(x) WriteRegBits16(SGMII1_RX_AFE_CTRL6,0x20,5,x)
#define Rd_SGMII1_RX_afe_ctrl6_Eye_Monitor_PI_pwd_lvl2pi(x) ReadRegBits16(SGMII1_RX_AFE_CTRL6,0x20,5)
#define SGMII1_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_MASK         0x0020
#define SGMII1_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_ALIGN        0
#define SGMII1_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_BITS         1
#define SGMII1_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_SHIFT        5

/* SGMII1_RX_afe :: ctrl6 :: reserved_100 [04:04] */
#define SGMII1_RX_AFE_CTRL6_RESERVED_100_MASK                      0x0010
#define SGMII1_RX_AFE_CTRL6_RESERVED_100_ALIGN                     0
#define SGMII1_RX_AFE_CTRL6_RESERVED_100_BITS                      1
#define SGMII1_RX_AFE_CTRL6_RESERVED_100_SHIFT                     4

/* SGMII1_RX_afe :: ctrl6 :: PI_lowvdd_enb [03:03] */
#define Wr_SGMII1_RX_afe_ctrl6_PI_lowvdd_enb(x) WriteRegBits16(SGMII1_RX_AFE_CTRL6,0x8,3,x)
#define Rd_SGMII1_RX_afe_ctrl6_PI_lowvdd_enb(x) ReadRegBits16(SGMII1_RX_AFE_CTRL6,0x8,3)
#define SGMII1_RX_AFE_CTRL6_PI_LOWVDD_ENB_MASK                     0x0008
#define SGMII1_RX_AFE_CTRL6_PI_LOWVDD_ENB_ALIGN                    0
#define SGMII1_RX_AFE_CTRL6_PI_LOWVDD_ENB_BITS                     1
#define SGMII1_RX_AFE_CTRL6_PI_LOWVDD_ENB_SHIFT                    3

/* SGMII1_RX_afe :: ctrl6 :: Main_PI_BW_sel [02:02] */
#define Wr_SGMII1_RX_afe_ctrl6_Main_PI_BW_sel(x) WriteRegBits16(SGMII1_RX_AFE_CTRL6,0x4,2,x)
#define Rd_SGMII1_RX_afe_ctrl6_Main_PI_BW_sel(x) ReadRegBits16(SGMII1_RX_AFE_CTRL6,0x4,2)
#define SGMII1_RX_AFE_CTRL6_MAIN_PI_BW_SEL_MASK                    0x0004
#define SGMII1_RX_AFE_CTRL6_MAIN_PI_BW_SEL_ALIGN                   0
#define SGMII1_RX_AFE_CTRL6_MAIN_PI_BW_SEL_BITS                    1
#define SGMII1_RX_AFE_CTRL6_MAIN_PI_BW_SEL_SHIFT                   2

/* SGMII1_RX_afe :: ctrl6 :: Main_PI_pwd_lvl2pi [01:01] */
#define Wr_SGMII1_RX_afe_ctrl6_Main_PI_pwd_lvl2pi(x) WriteRegBits16(SGMII1_RX_AFE_CTRL6,0x2,1,x)
#define Rd_SGMII1_RX_afe_ctrl6_Main_PI_pwd_lvl2pi(x) ReadRegBits16(SGMII1_RX_AFE_CTRL6,0x2,1)
#define SGMII1_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_MASK                0x0002
#define SGMII1_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_ALIGN               0
#define SGMII1_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_BITS                1
#define SGMII1_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_SHIFT               1

/* SGMII1_RX_afe :: ctrl6 :: reserved_96 [00:00] */
#define SGMII1_RX_AFE_CTRL6_RESERVED_96_MASK                       0x0001
#define SGMII1_RX_AFE_CTRL6_RESERVED_96_ALIGN                      0
#define SGMII1_RX_AFE_CTRL6_RESERVED_96_BITS                       1
#define SGMII1_RX_AFE_CTRL6_RESERVED_96_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_Digital
 ***************************************************************************/
/****************************************************************************
 * SGMII1_Digital :: Control1000X1
 ***************************************************************************/
/* SGMII1_Digital :: Control1000X1 :: reserved0 [15:15] */
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED0_MASK                0x8000
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED0_ALIGN               0
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED0_BITS                1
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED0_SHIFT               15

/* SGMII1_Digital :: Control1000X1 :: disable_signal_detect_filter [14:14] */
#define Wr_SGMII1_Digital_Control1000X1_disable_signal_detect_filter(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x4000,14,x)
#define Rd_SGMII1_Digital_Control1000X1_disable_signal_detect_filter(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x4000,14)
#define SGMII1_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000
#define SGMII1_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1
#define SGMII1_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14

/* SGMII1_Digital :: Control1000X1 :: reserved1 [13:12] */
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED1_MASK                0x3000
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED1_ALIGN               0
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED1_BITS                2
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED1_SHIFT               12

/* SGMII1_Digital :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */
#define Wr_SGMII1_Digital_Control1000X1_sel_rx_pkts_for_cntr(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x800,11,x)
#define Rd_SGMII1_Digital_Control1000X1_sel_rx_pkts_for_cntr(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x800,11)
#define SGMII1_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK     0x0800
#define SGMII1_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN    0
#define SGMII1_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS     1
#define SGMII1_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT    11

/* SGMII1_Digital :: Control1000X1 :: remote_loopback [10:10] */
#define Wr_SGMII1_Digital_Control1000X1_remote_loopback(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x400,10,x)
#define Rd_SGMII1_Digital_Control1000X1_remote_loopback(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x400,10)
#define SGMII1_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_MASK          0x0400
#define SGMII1_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN         0
#define SGMII1_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_BITS          1
#define SGMII1_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT         10

/* SGMII1_Digital :: Control1000X1 :: zero_comma_detector_phase [09:09] */
#define Wr_SGMII1_Digital_Control1000X1_zero_comma_detector_phase(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x200,9,x)
#define Rd_SGMII1_Digital_Control1000X1_zero_comma_detector_phase(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x200,9)
#define SGMII1_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200
#define SGMII1_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1
#define SGMII1_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9

/* SGMII1_Digital :: Control1000X1 :: comma_det_en [08:08] */
#define Wr_SGMII1_Digital_Control1000X1_comma_det_en(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x100,8,x)
#define Rd_SGMII1_Digital_Control1000X1_comma_det_en(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x100,8)
#define SGMII1_DIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK             0x0100
#define SGMII1_DIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN            0
#define SGMII1_DIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS             1
#define SGMII1_DIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT            8

/* SGMII1_Digital :: Control1000X1 :: crc_checker_disable [07:07] */
#define Wr_SGMII1_Digital_Control1000X1_crc_checker_disable(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x80,7,x)
#define Rd_SGMII1_Digital_Control1000X1_crc_checker_disable(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x80,7)
#define SGMII1_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK      0x0080
#define SGMII1_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN     0
#define SGMII1_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS      1
#define SGMII1_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT     7

/* SGMII1_Digital :: Control1000X1 :: disable_pll_pwrdwn [06:06] */
#define Wr_SGMII1_Digital_Control1000X1_disable_pll_pwrdwn(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x40,6,x)
#define Rd_SGMII1_Digital_Control1000X1_disable_pll_pwrdwn(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x40,6)
#define SGMII1_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK       0x0040
#define SGMII1_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN      0
#define SGMII1_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS       1
#define SGMII1_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT      6

/* SGMII1_Digital :: Control1000X1 :: sgmii_master_mode [05:05] */
#define Wr_SGMII1_Digital_Control1000X1_sgmii_master_mode(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x20,5,x)
#define Rd_SGMII1_Digital_Control1000X1_sgmii_master_mode(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x20,5)
#define SGMII1_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_MASK        0x0020
#define SGMII1_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN       0
#define SGMII1_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_BITS        1
#define SGMII1_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT       5

/* SGMII1_Digital :: Control1000X1 :: reserved2 [04:04] */
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED2_MASK                0x0010
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED2_ALIGN               0
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED2_BITS                1
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED2_SHIFT               4

/* SGMII1_Digital :: Control1000X1 :: invert_signal_detect [03:03] */
#define Wr_SGMII1_Digital_Control1000X1_invert_signal_detect(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x8,3,x)
#define Rd_SGMII1_Digital_Control1000X1_invert_signal_detect(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x8,3)
#define SGMII1_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK     0x0008
#define SGMII1_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN    0
#define SGMII1_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS     1
#define SGMII1_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT    3

/* SGMII1_Digital :: Control1000X1 :: signal_detect_en [02:02] */
#define Wr_SGMII1_Digital_Control1000X1_signal_detect_en(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x4,2,x)
#define Rd_SGMII1_Digital_Control1000X1_signal_detect_en(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x4,2)
#define SGMII1_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_MASK         0x0004
#define SGMII1_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN        0
#define SGMII1_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_BITS         1
#define SGMII1_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT        2

/* SGMII1_Digital :: Control1000X1 :: reserved3 [01:01] */
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED3_MASK                0x0002
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED3_ALIGN               0
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED3_BITS                1
#define SGMII1_DIGITAL_CONTROL1000X1_RESERVED3_SHIFT               1

/* SGMII1_Digital :: Control1000X1 :: fiber_mode_1000X [00:00] */
#define Wr_SGMII1_Digital_Control1000X1_fiber_mode_1000X(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x1,0,x)
#define Rd_SGMII1_Digital_Control1000X1_fiber_mode_1000X(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X1,0x1,0)
#define SGMII1_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_MASK         0x0001
#define SGMII1_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_ALIGN        0
#define SGMII1_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_BITS         1
#define SGMII1_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_SHIFT        0


/****************************************************************************
 * SGMII1_Digital :: Control1000X2
 ***************************************************************************/
/* SGMII1_Digital :: Control1000X2 :: disable_extend_fdx_only [15:15] */
#define Wr_SGMII1_Digital_Control1000X2_disable_extend_fdx_only(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x8000,15,x)
#define Rd_SGMII1_Digital_Control1000X2_disable_extend_fdx_only(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x8000,15)
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK  0x8000
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS  1
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT 15

/* SGMII1_Digital :: Control1000X2 :: clear_ber_counter [14:14] */
#define Wr_SGMII1_Digital_Control1000X2_clear_ber_counter(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x4000,14,x)
#define Rd_SGMII1_Digital_Control1000X2_clear_ber_counter(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x4000,14)
#define SGMII1_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK        0x4000
#define SGMII1_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN       0
#define SGMII1_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS        1
#define SGMII1_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT       14

/* SGMII1_Digital :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */
#define Wr_SGMII1_Digital_Control1000X2_transmit_idlejam_seq_test(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x2000,13,x)
#define Rd_SGMII1_Digital_Control1000X2_transmit_idlejam_seq_test(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x2000,13)
#define SGMII1_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000
#define SGMII1_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1
#define SGMII1_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13

/* SGMII1_Digital :: Control1000X2 :: transmit_packet_seq_test [12:12] */
#define Wr_SGMII1_Digital_Control1000X2_transmit_packet_seq_test(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x1000,12,x)
#define Rd_SGMII1_Digital_Control1000X2_transmit_packet_seq_test(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x1000,12)
#define SGMII1_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK 0x1000
#define SGMII1_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS 1
#define SGMII1_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12

/* SGMII1_Digital :: Control1000X2 :: test_cntr [11:11] */
#define Wr_SGMII1_Digital_Control1000X2_test_cntr(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x800,11,x)
#define Rd_SGMII1_Digital_Control1000X2_test_cntr(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x800,11)
#define SGMII1_DIGITAL_CONTROL1000X2_TEST_CNTR_MASK                0x0800
#define SGMII1_DIGITAL_CONTROL1000X2_TEST_CNTR_ALIGN               0
#define SGMII1_DIGITAL_CONTROL1000X2_TEST_CNTR_BITS                1
#define SGMII1_DIGITAL_CONTROL1000X2_TEST_CNTR_SHIFT               11

/* SGMII1_Digital :: Control1000X2 :: bypass_pcs_tx [10:10] */
#define Wr_SGMII1_Digital_Control1000X2_bypass_pcs_tx(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x400,10,x)
#define Rd_SGMII1_Digital_Control1000X2_bypass_pcs_tx(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x400,10)
#define SGMII1_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_MASK            0x0400
#define SGMII1_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_ALIGN           0
#define SGMII1_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_BITS            1
#define SGMII1_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_SHIFT           10

/* SGMII1_Digital :: Control1000X2 :: bypass_pcs_rx [09:09] */
#define Wr_SGMII1_Digital_Control1000X2_bypass_pcs_rx(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x200,9,x)
#define Rd_SGMII1_Digital_Control1000X2_bypass_pcs_rx(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x200,9)
#define SGMII1_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_MASK            0x0200
#define SGMII1_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_ALIGN           0
#define SGMII1_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_BITS            1
#define SGMII1_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_SHIFT           9

/* SGMII1_Digital :: Control1000X2 :: disable_TRRR_generation [08:08] */
#define Wr_SGMII1_Digital_Control1000X2_disable_TRRR_generation(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x100,8,x)
#define Rd_SGMII1_Digital_Control1000X2_disable_TRRR_generation(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x100,8)
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK  0x0100
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS  1
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT 8

/* SGMII1_Digital :: Control1000X2 :: disable_carrier_extend [07:07] */
#define Wr_SGMII1_Digital_Control1000X2_disable_carrier_extend(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x80,7,x)
#define Rd_SGMII1_Digital_Control1000X2_disable_carrier_extend(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x80,7)
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK   0x0080
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN  0
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS   1
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT  7

/* SGMII1_Digital :: Control1000X2 :: autoneg_fast_timers [06:06] */
#define Wr_SGMII1_Digital_Control1000X2_autoneg_fast_timers(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x40,6,x)
#define Rd_SGMII1_Digital_Control1000X2_autoneg_fast_timers(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x40,6)
#define SGMII1_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK      0x0040
#define SGMII1_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN     0
#define SGMII1_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS      1
#define SGMII1_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT     6

/* SGMII1_Digital :: Control1000X2 :: force_xmit_data_on_txside [05:05] */
#define Wr_SGMII1_Digital_Control1000X2_force_xmit_data_on_txside(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x20,5,x)
#define Rd_SGMII1_Digital_Control1000X2_force_xmit_data_on_txside(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x20,5)
#define SGMII1_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020
#define SGMII1_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1
#define SGMII1_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5

/* SGMII1_Digital :: Control1000X2 :: disable_remote_fault_sensing [04:04] */
#define Wr_SGMII1_Digital_Control1000X2_disable_remote_fault_sensing(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x10,4,x)
#define Rd_SGMII1_Digital_Control1000X2_disable_remote_fault_sensing(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x10,4)
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4

/* SGMII1_Digital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */
#define Wr_SGMII1_Digital_Control1000X2_enable_autoneg_err_timer(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x8,3,x)
#define Rd_SGMII1_Digital_Control1000X2_enable_autoneg_err_timer(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x8,3)
#define SGMII1_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK 0x0008
#define SGMII1_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS 1
#define SGMII1_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3

/* SGMII1_Digital :: Control1000X2 :: filter_force_link [02:02] */
#define Wr_SGMII1_Digital_Control1000X2_filter_force_link(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x4,2,x)
#define Rd_SGMII1_Digital_Control1000X2_filter_force_link(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x4,2)
#define SGMII1_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK        0x0004
#define SGMII1_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN       0
#define SGMII1_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS        1
#define SGMII1_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT       2

/* SGMII1_Digital :: Control1000X2 :: disable_false_link [01:01] */
#define Wr_SGMII1_Digital_Control1000X2_disable_false_link(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x2,1,x)
#define Rd_SGMII1_Digital_Control1000X2_disable_false_link(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X2,0x2,1)
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_MASK       0x0002
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN      0
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_BITS       1
#define SGMII1_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT      1

/* SGMII1_Digital :: Control1000X2 :: reserved0 [00:00] */
#define SGMII1_DIGITAL_CONTROL1000X2_RESERVED0_MASK                0x0001
#define SGMII1_DIGITAL_CONTROL1000X2_RESERVED0_ALIGN               0
#define SGMII1_DIGITAL_CONTROL1000X2_RESERVED0_BITS                1
#define SGMII1_DIGITAL_CONTROL1000X2_RESERVED0_SHIFT               0


/****************************************************************************
 * SGMII1_Digital :: Control1000X3
 ***************************************************************************/
/* SGMII1_Digital :: Control1000X3 :: disable_packet_misalign [15:15] */
#define Wr_SGMII1_Digital_Control1000X3_disable_packet_misalign(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x8000,15,x)
#define Rd_SGMII1_Digital_Control1000X3_disable_packet_misalign(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x8000,15)
#define SGMII1_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK  0x8000
#define SGMII1_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS  1
#define SGMII1_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT 15

/* SGMII1_Digital :: Control1000X3 :: rxfifo_gmii_reset [14:14] */
#define Wr_SGMII1_Digital_Control1000X3_rxfifo_gmii_reset(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x4000,14,x)
#define Rd_SGMII1_Digital_Control1000X3_rxfifo_gmii_reset(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x4000,14)
#define SGMII1_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_MASK        0x4000
#define SGMII1_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN       0
#define SGMII1_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_BITS        1
#define SGMII1_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT       14

/* SGMII1_Digital :: Control1000X3 :: disable_tx_crs [13:13] */
#define Wr_SGMII1_Digital_Control1000X3_disable_tx_crs(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x2000,13,x)
#define Rd_SGMII1_Digital_Control1000X3_disable_tx_crs(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x2000,13)
#define SGMII1_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_MASK           0x2000
#define SGMII1_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_ALIGN          0
#define SGMII1_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_BITS           1
#define SGMII1_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_SHIFT          13

/* SGMII1_Digital :: Control1000X3 :: invert_ext_phy_crs [12:12] */
#define Wr_SGMII1_Digital_Control1000X3_invert_ext_phy_crs(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x1000,12,x)
#define Rd_SGMII1_Digital_Control1000X3_invert_ext_phy_crs(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x1000,12)
#define SGMII1_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK       0x1000
#define SGMII1_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN      0
#define SGMII1_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS       1
#define SGMII1_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT      12

/* SGMII1_Digital :: Control1000X3 :: ext_phy_crs_mode [11:11] */
#define Wr_SGMII1_Digital_Control1000X3_ext_phy_crs_mode(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x800,11,x)
#define Rd_SGMII1_Digital_Control1000X3_ext_phy_crs_mode(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x800,11)
#define SGMII1_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK         0x0800
#define SGMII1_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN        0
#define SGMII1_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS         1
#define SGMII1_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT        11

/* SGMII1_Digital :: Control1000X3 :: jam_false_carrier_mode [10:10] */
#define Wr_SGMII1_Digital_Control1000X3_jam_false_carrier_mode(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x400,10,x)
#define Rd_SGMII1_Digital_Control1000X3_jam_false_carrier_mode(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x400,10)
#define SGMII1_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK   0x0400
#define SGMII1_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN  0
#define SGMII1_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS   1
#define SGMII1_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT  10

/* SGMII1_Digital :: Control1000X3 :: block_txen_mode [09:09] */
#define Wr_SGMII1_Digital_Control1000X3_block_txen_mode(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x200,9,x)
#define Rd_SGMII1_Digital_Control1000X3_block_txen_mode(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x200,9)
#define SGMII1_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_MASK          0x0200
#define SGMII1_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN         0
#define SGMII1_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_BITS          1
#define SGMII1_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT         9

/* SGMII1_Digital :: Control1000X3 :: force_txfifo_on [08:08] */
#define Wr_SGMII1_Digital_Control1000X3_force_txfifo_on(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x100,8,x)
#define Rd_SGMII1_Digital_Control1000X3_force_txfifo_on(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x100,8)
#define SGMII1_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_MASK          0x0100
#define SGMII1_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN         0
#define SGMII1_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_BITS          1
#define SGMII1_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT         8

/* SGMII1_Digital :: Control1000X3 :: bypass_txfifo1000 [07:07] */
#define Wr_SGMII1_Digital_Control1000X3_bypass_txfifo1000(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x80,7,x)
#define Rd_SGMII1_Digital_Control1000X3_bypass_txfifo1000(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x80,7)
#define SGMII1_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_MASK        0x0080
#define SGMII1_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN       0
#define SGMII1_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_BITS        1
#define SGMII1_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT       7

/* SGMII1_Digital :: Control1000X3 :: reserved_6 [06:06] */
#define SGMII1_DIGITAL_CONTROL1000X3_RESERVED_6_MASK               0x0040
#define SGMII1_DIGITAL_CONTROL1000X3_RESERVED_6_ALIGN              0
#define SGMII1_DIGITAL_CONTROL1000X3_RESERVED_6_BITS               1
#define SGMII1_DIGITAL_CONTROL1000X3_RESERVED_6_SHIFT              6

/* SGMII1_Digital :: Control1000X3 :: reserved_5 [05:05] */
#define SGMII1_DIGITAL_CONTROL1000X3_RESERVED_5_MASK               0x0020
#define SGMII1_DIGITAL_CONTROL1000X3_RESERVED_5_ALIGN              0
#define SGMII1_DIGITAL_CONTROL1000X3_RESERVED_5_BITS               1
#define SGMII1_DIGITAL_CONTROL1000X3_RESERVED_5_SHIFT              5

/* SGMII1_Digital :: Control1000X3 :: early_preamble_rx [04:04] */
#define Wr_SGMII1_Digital_Control1000X3_early_preamble_rx(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x10,4,x)
#define Rd_SGMII1_Digital_Control1000X3_early_preamble_rx(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x10,4)
#define SGMII1_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK        0x0010
#define SGMII1_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN       0
#define SGMII1_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS        1
#define SGMII1_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT       4

/* SGMII1_Digital :: Control1000X3 :: early_preamble_tx [03:03] */
#define Wr_SGMII1_Digital_Control1000X3_early_preamble_tx(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x8,3,x)
#define Rd_SGMII1_Digital_Control1000X3_early_preamble_tx(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x8,3)
#define SGMII1_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK        0x0008
#define SGMII1_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN       0
#define SGMII1_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS        1
#define SGMII1_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT       3

/* SGMII1_Digital :: Control1000X3 :: fifo_elasicity_tx [02:01] */
#define Wr_SGMII1_Digital_Control1000X3_fifo_elasicity_tx(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x6,1,x)
#define Rd_SGMII1_Digital_Control1000X3_fifo_elasicity_tx(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x6,1)
#define SGMII1_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_MASK        0x0006
#define SGMII1_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_ALIGN       0
#define SGMII1_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_BITS        2
#define SGMII1_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_SHIFT       1

/* SGMII1_Digital :: Control1000X3 :: tx_fifo_rst [00:00] */
#define Wr_SGMII1_Digital_Control1000X3_tx_fifo_rst(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x1,0,x)
#define Rd_SGMII1_Digital_Control1000X3_tx_fifo_rst(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X3,0x1,0)
#define SGMII1_DIGITAL_CONTROL1000X3_TX_FIFO_RST_MASK              0x0001
#define SGMII1_DIGITAL_CONTROL1000X3_TX_FIFO_RST_ALIGN             0
#define SGMII1_DIGITAL_CONTROL1000X3_TX_FIFO_RST_BITS              1
#define SGMII1_DIGITAL_CONTROL1000X3_TX_FIFO_RST_SHIFT             0


/****************************************************************************
 * SGMII1_Digital :: Control1000X4
 ***************************************************************************/
/* SGMII1_Digital :: Control1000X4 :: reserved0 [15:14] */
#define SGMII1_DIGITAL_CONTROL1000X4_RESERVED0_MASK                0xc000
#define SGMII1_DIGITAL_CONTROL1000X4_RESERVED0_ALIGN               0
#define SGMII1_DIGITAL_CONTROL1000X4_RESERVED0_BITS                2
#define SGMII1_DIGITAL_CONTROL1000X4_RESERVED0_SHIFT               14

/* SGMII1_Digital :: Control1000X4 :: disable_resolution_err_restart [13:13] */
#define Wr_SGMII1_Digital_Control1000X4_disable_resolution_err_restart(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x2000,13,x)
#define Rd_SGMII1_Digital_Control1000X4_disable_resolution_err_restart(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x2000,13)
#define SGMII1_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000
#define SGMII1_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1
#define SGMII1_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13

/* SGMII1_Digital :: Control1000X4 :: enable_last_resolution_err [12:12] */
#define Wr_SGMII1_Digital_Control1000X4_enable_last_resolution_err(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x1000,12,x)
#define Rd_SGMII1_Digital_Control1000X4_enable_last_resolution_err(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x1000,12)
#define SGMII1_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000
#define SGMII1_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0
#define SGMII1_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1
#define SGMII1_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12

/* SGMII1_Digital :: Control1000X4 :: tx_config_reg_sel [11:11] */
#define Wr_SGMII1_Digital_Control1000X4_tx_config_reg_sel(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x800,11,x)
#define Rd_SGMII1_Digital_Control1000X4_tx_config_reg_sel(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x800,11)
#define SGMII1_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK        0x0800
#define SGMII1_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN       0
#define SGMII1_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS        1
#define SGMII1_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT       11

/* SGMII1_Digital :: Control1000X4 :: zero_rxdgmii [10:10] */
#define Wr_SGMII1_Digital_Control1000X4_zero_rxdgmii(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x400,10,x)
#define Rd_SGMII1_Digital_Control1000X4_zero_rxdgmii(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x400,10)
#define SGMII1_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_MASK             0x0400
#define SGMII1_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_ALIGN            0
#define SGMII1_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_BITS             1
#define SGMII1_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_SHIFT            10

/* SGMII1_Digital :: Control1000X4 :: clear_linkdown [09:09] */
#define Wr_SGMII1_Digital_Control1000X4_clear_linkdown(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x200,9,x)
#define Rd_SGMII1_Digital_Control1000X4_clear_linkdown(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x200,9)
#define SGMII1_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK           0x0200
#define SGMII1_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN          0
#define SGMII1_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS           1
#define SGMII1_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT          9

/* SGMII1_Digital :: Control1000X4 :: latch_linkdown_enable [08:08] */
#define Wr_SGMII1_Digital_Control1000X4_latch_linkdown_enable(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x100,8,x)
#define Rd_SGMII1_Digital_Control1000X4_latch_linkdown_enable(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x100,8)
#define SGMII1_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK    0x0100
#define SGMII1_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN   0
#define SGMII1_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS    1
#define SGMII1_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT   8

/* SGMII1_Digital :: Control1000X4 :: link_force [07:07] */
#define Wr_SGMII1_Digital_Control1000X4_link_force(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x80,7,x)
#define Rd_SGMII1_Digital_Control1000X4_link_force(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x80,7)
#define SGMII1_DIGITAL_CONTROL1000X4_LINK_FORCE_MASK               0x0080
#define SGMII1_DIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN              0
#define SGMII1_DIGITAL_CONTROL1000X4_LINK_FORCE_BITS               1
#define SGMII1_DIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT              7

/* SGMII1_Digital :: Control1000X4 :: reserved1 [06:03] */
#define SGMII1_DIGITAL_CONTROL1000X4_RESERVED1_MASK                0x0078
#define SGMII1_DIGITAL_CONTROL1000X4_RESERVED1_ALIGN               0
#define SGMII1_DIGITAL_CONTROL1000X4_RESERVED1_BITS                4
#define SGMII1_DIGITAL_CONTROL1000X4_RESERVED1_SHIFT               3

/* SGMII1_Digital :: Control1000X4 :: MiscRxStatus_sel [02:00] */
#define Wr_SGMII1_Digital_Control1000X4_MiscRxStatus_sel(x) WriteRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x7,0,x)
#define Rd_SGMII1_Digital_Control1000X4_MiscRxStatus_sel(x) ReadRegBits16(SGMII1_DIGITAL_CONTROL1000X4,0x7,0)
#define SGMII1_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK         0x0007
#define SGMII1_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN        0
#define SGMII1_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS         3
#define SGMII1_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT        0


/****************************************************************************
 * SGMII1_Digital :: Status1000X1
 ***************************************************************************/
/* SGMII1_Digital :: Status1000X1 :: txfifo_err_detected [15:15] */
#define Wr_SGMII1_Digital_Status1000X1_txfifo_err_detected(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x8000,15,x)
#define Rd_SGMII1_Digital_Status1000X1_txfifo_err_detected(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x8000,15)
#define SGMII1_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK       0x8000
#define SGMII1_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN      0
#define SGMII1_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS       1
#define SGMII1_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT      15

/* SGMII1_Digital :: Status1000X1 :: rxfifo_err_detected [14:14] */
#define Wr_SGMII1_Digital_Status1000X1_rxfifo_err_detected(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x4000,14,x)
#define Rd_SGMII1_Digital_Status1000X1_rxfifo_err_detected(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x4000,14)
#define SGMII1_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK       0x4000
#define SGMII1_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN      0
#define SGMII1_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS       1
#define SGMII1_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT      14

/* SGMII1_Digital :: Status1000X1 :: false_carrier_detected [13:13] */
#define Wr_SGMII1_Digital_Status1000X1_false_carrier_detected(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x2000,13,x)
#define Rd_SGMII1_Digital_Status1000X1_false_carrier_detected(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x2000,13)
#define SGMII1_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK    0x2000
#define SGMII1_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN   0
#define SGMII1_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS    1
#define SGMII1_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT   13

/* SGMII1_Digital :: Status1000X1 :: crc_err_detected [12:12] */
#define Wr_SGMII1_Digital_Status1000X1_crc_err_detected(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x1000,12,x)
#define Rd_SGMII1_Digital_Status1000X1_crc_err_detected(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x1000,12)
#define SGMII1_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_MASK          0x1000
#define SGMII1_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_ALIGN         0
#define SGMII1_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_BITS          1
#define SGMII1_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_SHIFT         12

/* SGMII1_Digital :: Status1000X1 :: tx_err_detected [11:11] */
#define Wr_SGMII1_Digital_Status1000X1_tx_err_detected(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x800,11,x)
#define Rd_SGMII1_Digital_Status1000X1_tx_err_detected(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x800,11)
#define SGMII1_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK           0x0800
#define SGMII1_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN          0
#define SGMII1_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS           1
#define SGMII1_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT          11

/* SGMII1_Digital :: Status1000X1 :: rx_err_detected [10:10] */
#define Wr_SGMII1_Digital_Status1000X1_rx_err_detected(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x400,10,x)
#define Rd_SGMII1_Digital_Status1000X1_rx_err_detected(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x400,10)
#define SGMII1_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK           0x0400
#define SGMII1_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN          0
#define SGMII1_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS           1
#define SGMII1_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT          10

/* SGMII1_Digital :: Status1000X1 :: carrier_extend_err_detected [09:09] */
#define Wr_SGMII1_Digital_Status1000X1_carrier_extend_err_detected(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x200,9,x)
#define Rd_SGMII1_Digital_Status1000X1_carrier_extend_err_detected(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x200,9)
#define SGMII1_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200
#define SGMII1_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0
#define SGMII1_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1
#define SGMII1_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9

/* SGMII1_Digital :: Status1000X1 :: early_end_extension_detected [08:08] */
#define Wr_SGMII1_Digital_Status1000X1_early_end_extension_detected(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x100,8,x)
#define Rd_SGMII1_Digital_Status1000X1_early_end_extension_detected(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x100,8)
#define SGMII1_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100
#define SGMII1_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0
#define SGMII1_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1
#define SGMII1_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8

/* SGMII1_Digital :: Status1000X1 :: link_status_change [07:07] */
#define Wr_SGMII1_Digital_Status1000X1_link_status_change(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x80,7,x)
#define Rd_SGMII1_Digital_Status1000X1_link_status_change(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x80,7)
#define SGMII1_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK        0x0080
#define SGMII1_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN       0
#define SGMII1_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS        1
#define SGMII1_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT       7

/* SGMII1_Digital :: Status1000X1 :: pause_resolution_rxside [06:06] */
#define Wr_SGMII1_Digital_Status1000X1_pause_resolution_rxside(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x40,6,x)
#define Rd_SGMII1_Digital_Status1000X1_pause_resolution_rxside(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x40,6)
#define SGMII1_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK   0x0040
#define SGMII1_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN  0
#define SGMII1_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS   1
#define SGMII1_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT  6

/* SGMII1_Digital :: Status1000X1 :: pause_resolution_txside [05:05] */
#define Wr_SGMII1_Digital_Status1000X1_pause_resolution_txside(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x20,5,x)
#define Rd_SGMII1_Digital_Status1000X1_pause_resolution_txside(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x20,5)
#define SGMII1_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK   0x0020
#define SGMII1_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN  0
#define SGMII1_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS   1
#define SGMII1_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT  5

/* SGMII1_Digital :: Status1000X1 :: speed_status [04:03] */
#define Wr_SGMII1_Digital_Status1000X1_speed_status(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x18,3,x)
#define Rd_SGMII1_Digital_Status1000X1_speed_status(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x18,3)
#define SGMII1_DIGITAL_STATUS1000X1_SPEED_STATUS_MASK              0x0018
#define SGMII1_DIGITAL_STATUS1000X1_SPEED_STATUS_ALIGN             0
#define SGMII1_DIGITAL_STATUS1000X1_SPEED_STATUS_BITS              2
#define SGMII1_DIGITAL_STATUS1000X1_SPEED_STATUS_SHIFT             3

/* SGMII1_Digital :: Status1000X1 :: duplex_status [02:02] */
#define Wr_SGMII1_Digital_Status1000X1_duplex_status(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x4,2,x)
#define Rd_SGMII1_Digital_Status1000X1_duplex_status(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x4,2)
#define SGMII1_DIGITAL_STATUS1000X1_DUPLEX_STATUS_MASK             0x0004
#define SGMII1_DIGITAL_STATUS1000X1_DUPLEX_STATUS_ALIGN            0
#define SGMII1_DIGITAL_STATUS1000X1_DUPLEX_STATUS_BITS             1
#define SGMII1_DIGITAL_STATUS1000X1_DUPLEX_STATUS_SHIFT            2

/* SGMII1_Digital :: Status1000X1 :: link_status [01:01] */
#define Wr_SGMII1_Digital_Status1000X1_link_status(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x2,1,x)
#define Rd_SGMII1_Digital_Status1000X1_link_status(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x2,1)
#define SGMII1_DIGITAL_STATUS1000X1_LINK_STATUS_MASK               0x0002
#define SGMII1_DIGITAL_STATUS1000X1_LINK_STATUS_ALIGN              0
#define SGMII1_DIGITAL_STATUS1000X1_LINK_STATUS_BITS               1
#define SGMII1_DIGITAL_STATUS1000X1_LINK_STATUS_SHIFT              1

/* SGMII1_Digital :: Status1000X1 :: sgmii_mode [00:00] */
#define Wr_SGMII1_Digital_Status1000X1_sgmii_mode(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x1,0,x)
#define Rd_SGMII1_Digital_Status1000X1_sgmii_mode(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X1,0x1,0)
#define SGMII1_DIGITAL_STATUS1000X1_SGMII_MODE_MASK                0x0001
#define SGMII1_DIGITAL_STATUS1000X1_SGMII_MODE_ALIGN               0
#define SGMII1_DIGITAL_STATUS1000X1_SGMII_MODE_BITS                1
#define SGMII1_DIGITAL_STATUS1000X1_SGMII_MODE_SHIFT               0


/****************************************************************************
 * SGMII1_Digital :: Status1000X2
 ***************************************************************************/
/* SGMII1_Digital :: Status1000X2 :: sgmii_mode_change [15:15] */
#define Wr_SGMII1_Digital_Status1000X2_sgmii_mode_change(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x8000,15,x)
#define Rd_SGMII1_Digital_Status1000X2_sgmii_mode_change(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x8000,15)
#define SGMII1_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_MASK         0x8000
#define SGMII1_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN        0
#define SGMII1_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_BITS         1
#define SGMII1_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT        15

/* SGMII1_Digital :: Status1000X2 :: consistency_mismatch [14:14] */
#define Wr_SGMII1_Digital_Status1000X2_consistency_mismatch(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x4000,14,x)
#define Rd_SGMII1_Digital_Status1000X2_consistency_mismatch(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x4000,14)
#define SGMII1_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_MASK      0x4000
#define SGMII1_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN     0
#define SGMII1_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_BITS      1
#define SGMII1_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT     14

/* SGMII1_Digital :: Status1000X2 :: autoneg_resolution_err [13:13] */
#define Wr_SGMII1_Digital_Status1000X2_autoneg_resolution_err(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x2000,13,x)
#define Rd_SGMII1_Digital_Status1000X2_autoneg_resolution_err(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x2000,13)
#define SGMII1_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK    0x2000
#define SGMII1_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN   0
#define SGMII1_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS    1
#define SGMII1_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT   13

/* SGMII1_Digital :: Status1000X2 :: sgmii_selector_mismatch [12:12] */
#define Wr_SGMII1_Digital_Status1000X2_sgmii_selector_mismatch(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x1000,12,x)
#define Rd_SGMII1_Digital_Status1000X2_sgmii_selector_mismatch(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x1000,12)
#define SGMII1_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK   0x1000
#define SGMII1_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN  0
#define SGMII1_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS   1
#define SGMII1_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT  12

/* SGMII1_Digital :: Status1000X2 :: sync_status_fail [11:11] */
#define Wr_SGMII1_Digital_Status1000X2_sync_status_fail(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x800,11,x)
#define Rd_SGMII1_Digital_Status1000X2_sync_status_fail(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x800,11)
#define SGMII1_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_MASK          0x0800
#define SGMII1_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN         0
#define SGMII1_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_BITS          1
#define SGMII1_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT         11

/* SGMII1_Digital :: Status1000X2 :: sync_status_ok [10:10] */
#define Wr_SGMII1_Digital_Status1000X2_sync_status_ok(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x400,10,x)
#define Rd_SGMII1_Digital_Status1000X2_sync_status_ok(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x400,10)
#define SGMII1_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_MASK            0x0400
#define SGMII1_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_ALIGN           0
#define SGMII1_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_BITS            1
#define SGMII1_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_SHIFT           10

/* SGMII1_Digital :: Status1000X2 :: rudi_c [09:09] */
#define Wr_SGMII1_Digital_Status1000X2_rudi_c(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x200,9,x)
#define Rd_SGMII1_Digital_Status1000X2_rudi_c(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x200,9)
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_C_MASK                    0x0200
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_C_ALIGN                   0
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_C_BITS                    1
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_C_SHIFT                   9

/* SGMII1_Digital :: Status1000X2 :: rudi_I [08:08] */
#define Wr_SGMII1_Digital_Status1000X2_rudi_I(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x100,8,x)
#define Rd_SGMII1_Digital_Status1000X2_rudi_I(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x100,8)
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_I_MASK                    0x0100
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_I_ALIGN                   0
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_I_BITS                    1
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_I_SHIFT                   8

/* SGMII1_Digital :: Status1000X2 :: rudi_invalid [07:07] */
#define Wr_SGMII1_Digital_Status1000X2_rudi_invalid(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x80,7,x)
#define Rd_SGMII1_Digital_Status1000X2_rudi_invalid(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x80,7)
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_INVALID_MASK              0x0080
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_INVALID_ALIGN             0
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_INVALID_BITS              1
#define SGMII1_DIGITAL_STATUS1000X2_RUDI_INVALID_SHIFT             7

/* SGMII1_Digital :: Status1000X2 :: linkDown_syncLoss [06:06] */
#define Wr_SGMII1_Digital_Status1000X2_linkDown_syncLoss(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x40,6,x)
#define Rd_SGMII1_Digital_Status1000X2_linkDown_syncLoss(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x40,6)
#define SGMII1_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK         0x0040
#define SGMII1_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN        0
#define SGMII1_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS         1
#define SGMII1_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT        6

/* SGMII1_Digital :: Status1000X2 :: idle_detect_state [05:05] */
#define Wr_SGMII1_Digital_Status1000X2_idle_detect_state(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x20,5,x)
#define Rd_SGMII1_Digital_Status1000X2_idle_detect_state(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x20,5)
#define SGMII1_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_MASK         0x0020
#define SGMII1_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_ALIGN        0
#define SGMII1_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_BITS         1
#define SGMII1_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_SHIFT        5

/* SGMII1_Digital :: Status1000X2 :: complete_acknowledge_state [04:04] */
#define Wr_SGMII1_Digital_Status1000X2_complete_acknowledge_state(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x10,4,x)
#define Rd_SGMII1_Digital_Status1000X2_complete_acknowledge_state(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x10,4)
#define SGMII1_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010
#define SGMII1_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0
#define SGMII1_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1
#define SGMII1_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4

/* SGMII1_Digital :: Status1000X2 :: acknowledge_detect_state [03:03] */
#define Wr_SGMII1_Digital_Status1000X2_acknowledge_detect_state(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x8,3,x)
#define Rd_SGMII1_Digital_Status1000X2_acknowledge_detect_state(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x8,3)
#define SGMII1_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK  0x0008
#define SGMII1_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0
#define SGMII1_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS  1
#define SGMII1_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3

/* SGMII1_Digital :: Status1000X2 :: ability_detect_state [02:02] */
#define Wr_SGMII1_Digital_Status1000X2_ability_detect_state(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x4,2,x)
#define Rd_SGMII1_Digital_Status1000X2_ability_detect_state(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x4,2)
#define SGMII1_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_MASK      0x0004
#define SGMII1_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN     0
#define SGMII1_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_BITS      1
#define SGMII1_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT     2

/* union - case anError [01:01] */
/* SGMII1_Digital :: Status1000X2 :: an_error_state [01:01] */
#define Wr_SGMII1_Digital_Status1000X2_anError_an_error_state(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2_ANERROR,0x2,1,x)
#define Rd_SGMII1_Digital_Status1000X2_anError_an_error_state(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2_ANERROR,0x2,1)
#define SGMII1_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK    0x0002
#define SGMII1_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN   0
#define SGMII1_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS    1
#define SGMII1_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT   1


/* union - case anDisableLink [01:01] */
/* SGMII1_Digital :: Status1000X2 :: an_disable_link_ok_state [01:01] */
#define Wr_SGMII1_Digital_Status1000X2_anDisableLink_an_disable_link_ok_state(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2_ANDISABLELINK,0x2,1,x)
#define Rd_SGMII1_Digital_Status1000X2_anDisableLink_an_disable_link_ok_state(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2_ANDISABLELINK,0x2,1)
#define SGMII1_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002
#define SGMII1_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0
#define SGMII1_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1
#define SGMII1_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1


/* SGMII1_Digital :: Status1000X2 :: an_enable_state [00:00] */
#define Wr_SGMII1_Digital_Status1000X2_an_enable_state(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x1,0,x)
#define Rd_SGMII1_Digital_Status1000X2_an_enable_state(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X2,0x1,0)
#define SGMII1_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_MASK           0x0001
#define SGMII1_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_ALIGN          0
#define SGMII1_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_BITS           1
#define SGMII1_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_SHIFT          0


/****************************************************************************
 * SGMII1_Digital :: Status1000X3
 ***************************************************************************/
/* SGMII1_Digital :: Status1000X3 :: reserved0 [15:13] */
#define SGMII1_DIGITAL_STATUS1000X3_RESERVED0_MASK                 0xe000
#define SGMII1_DIGITAL_STATUS1000X3_RESERVED0_ALIGN                0
#define SGMII1_DIGITAL_STATUS1000X3_RESERVED0_BITS                 3
#define SGMII1_DIGITAL_STATUS1000X3_RESERVED0_SHIFT                13

/* SGMII1_Digital :: Status1000X3 :: pd_park_an [12:12] */
#define Wr_SGMII1_Digital_Status1000X3_pd_park_an(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x1000,12,x)
#define Rd_SGMII1_Digital_Status1000X3_pd_park_an(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x1000,12)
#define SGMII1_DIGITAL_STATUS1000X3_PD_PARK_AN_MASK                0x1000
#define SGMII1_DIGITAL_STATUS1000X3_PD_PARK_AN_ALIGN               0
#define SGMII1_DIGITAL_STATUS1000X3_PD_PARK_AN_BITS                1
#define SGMII1_DIGITAL_STATUS1000X3_PD_PARK_AN_SHIFT               12

/* SGMII1_Digital :: Status1000X3 :: remotePhy_autosel [11:11] */
#define Wr_SGMII1_Digital_Status1000X3_remotePhy_autosel(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x800,11,x)
#define Rd_SGMII1_Digital_Status1000X3_remotePhy_autosel(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x800,11)
#define SGMII1_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK         0x0800
#define SGMII1_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN        0
#define SGMII1_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS         1
#define SGMII1_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT        11

/* SGMII1_Digital :: Status1000X3 :: latch_linkdown [10:10] */
#define Wr_SGMII1_Digital_Status1000X3_latch_linkdown(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x400,10,x)
#define Rd_SGMII1_Digital_Status1000X3_latch_linkdown(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x400,10)
#define SGMII1_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_MASK            0x0400
#define SGMII1_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_ALIGN           0
#define SGMII1_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_BITS            1
#define SGMII1_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_SHIFT           10

/* SGMII1_Digital :: Status1000X3 :: sd_filter [09:09] */
#define Wr_SGMII1_Digital_Status1000X3_sd_filter(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x200,9,x)
#define Rd_SGMII1_Digital_Status1000X3_sd_filter(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x200,9)
#define SGMII1_DIGITAL_STATUS1000X3_SD_FILTER_MASK                 0x0200
#define SGMII1_DIGITAL_STATUS1000X3_SD_FILTER_ALIGN                0
#define SGMII1_DIGITAL_STATUS1000X3_SD_FILTER_BITS                 1
#define SGMII1_DIGITAL_STATUS1000X3_SD_FILTER_SHIFT                9

/* SGMII1_Digital :: Status1000X3 :: sd_mux [08:08] */
#define Wr_SGMII1_Digital_Status1000X3_sd_mux(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x100,8,x)
#define Rd_SGMII1_Digital_Status1000X3_sd_mux(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x100,8)
#define SGMII1_DIGITAL_STATUS1000X3_SD_MUX_MASK                    0x0100
#define SGMII1_DIGITAL_STATUS1000X3_SD_MUX_ALIGN                   0
#define SGMII1_DIGITAL_STATUS1000X3_SD_MUX_BITS                    1
#define SGMII1_DIGITAL_STATUS1000X3_SD_MUX_SHIFT                   8

/* SGMII1_Digital :: Status1000X3 :: sd_filter_chg [07:07] */
#define Wr_SGMII1_Digital_Status1000X3_sd_filter_chg(x) WriteRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x80,7,x)
#define Rd_SGMII1_Digital_Status1000X3_sd_filter_chg(x) ReadRegBits16(SGMII1_DIGITAL_STATUS1000X3,0x80,7)
#define SGMII1_DIGITAL_STATUS1000X3_SD_FILTER_CHG_MASK             0x0080
#define SGMII1_DIGITAL_STATUS1000X3_SD_FILTER_CHG_ALIGN            0
#define SGMII1_DIGITAL_STATUS1000X3_SD_FILTER_CHG_BITS             1
#define SGMII1_DIGITAL_STATUS1000X3_SD_FILTER_CHG_SHIFT            7

/* SGMII1_Digital :: Status1000X3 :: reserved1 [06:00] */
#define SGMII1_DIGITAL_STATUS1000X3_RESERVED1_MASK                 0x007f
#define SGMII1_DIGITAL_STATUS1000X3_RESERVED1_ALIGN                0
#define SGMII1_DIGITAL_STATUS1000X3_RESERVED1_BITS                 7
#define SGMII1_DIGITAL_STATUS1000X3_RESERVED1_SHIFT                0


/****************************************************************************
 * SGMII1_Digital :: BadCodeGroup
 ***************************************************************************/
/* SGMII1_Digital :: BadCodeGroup :: badCodeGroups [15:08] */
#define Wr_SGMII1_Digital_BadCodeGroup_badCodeGroups(x) WriteRegBits16(SGMII1_DIGITAL_BADCODEGROUP,0xff00,8,x)
#define Rd_SGMII1_Digital_BadCodeGroup_badCodeGroups(x) ReadRegBits16(SGMII1_DIGITAL_BADCODEGROUP,0xff00,8)
#define SGMII1_DIGITAL_BADCODEGROUP_BADCODEGROUPS_MASK             0xff00
#define SGMII1_DIGITAL_BADCODEGROUP_BADCODEGROUPS_ALIGN            0
#define SGMII1_DIGITAL_BADCODEGROUP_BADCODEGROUPS_BITS             8
#define SGMII1_DIGITAL_BADCODEGROUP_BADCODEGROUPS_SHIFT            8

/* SGMII1_Digital :: BadCodeGroup :: reserved0 [07:00] */
#define SGMII1_DIGITAL_BADCODEGROUP_RESERVED0_MASK                 0x00ff
#define SGMII1_DIGITAL_BADCODEGROUP_RESERVED0_ALIGN                0
#define SGMII1_DIGITAL_BADCODEGROUP_RESERVED0_BITS                 8
#define SGMII1_DIGITAL_BADCODEGROUP_RESERVED0_SHIFT                0


/****************************************************************************
 * SGMII1_Digital :: Misc1
 ***************************************************************************/
/* SGMII1_Digital :: Misc1 :: refclk_sel [15:13] */
#define Wr_SGMII1_Digital_Misc1_refclk_sel(x) WriteRegBits16(SGMII1_DIGITAL_MISC1,0xe000,13,x)
#define Rd_SGMII1_Digital_Misc1_refclk_sel(x) ReadRegBits16(SGMII1_DIGITAL_MISC1,0xe000,13)
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_MASK                       0xe000
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_ALIGN                      0
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_BITS                       3
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_SHIFT                      13
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_clk_25MHz                  0
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_clk_100MHz                 1
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_clk_125MHz                 2
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_clk_156p25MHz              3
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_clk_187p5MHz               4
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_clk_161p25Mhz              5
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_clk_50Mhz                  6
#define SGMII1_DIGITAL_MISC1_REFCLK_SEL_clk_106p25Mhz              7

/* SGMII1_Digital :: Misc1 :: reserved0 [12:07] */
#define SGMII1_DIGITAL_MISC1_RESERVED0_MASK                        0x1f80
#define SGMII1_DIGITAL_MISC1_RESERVED0_ALIGN                       0
#define SGMII1_DIGITAL_MISC1_RESERVED0_BITS                        6
#define SGMII1_DIGITAL_MISC1_RESERVED0_SHIFT                       7

/* SGMII1_Digital :: Misc1 :: tx_underrun_1000_dis [06:06] */
#define Wr_SGMII1_Digital_Misc1_tx_underrun_1000_dis(x) WriteRegBits16(SGMII1_DIGITAL_MISC1,0x40,6,x)
#define Rd_SGMII1_Digital_Misc1_tx_underrun_1000_dis(x) ReadRegBits16(SGMII1_DIGITAL_MISC1,0x40,6)
#define SGMII1_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_MASK             0x0040
#define SGMII1_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_ALIGN            0
#define SGMII1_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_BITS             1
#define SGMII1_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_SHIFT            6

/* SGMII1_Digital :: Misc1 :: force_ln_mode [05:05] */
#define Wr_SGMII1_Digital_Misc1_force_ln_mode(x) WriteRegBits16(SGMII1_DIGITAL_MISC1,0x20,5,x)
#define Rd_SGMII1_Digital_Misc1_force_ln_mode(x) ReadRegBits16(SGMII1_DIGITAL_MISC1,0x20,5)
#define SGMII1_DIGITAL_MISC1_FORCE_LN_MODE_MASK                    0x0020
#define SGMII1_DIGITAL_MISC1_FORCE_LN_MODE_ALIGN                   0
#define SGMII1_DIGITAL_MISC1_FORCE_LN_MODE_BITS                    1
#define SGMII1_DIGITAL_MISC1_FORCE_LN_MODE_SHIFT                   5

/* SGMII1_Digital :: Misc1 :: force_speed [04:00] */
#define Wr_SGMII1_Digital_Misc1_force_speed(x) WriteRegBits16(SGMII1_DIGITAL_MISC1,0x1f,0,x)
#define Rd_SGMII1_Digital_Misc1_force_speed(x) ReadRegBits16(SGMII1_DIGITAL_MISC1,0x1f,0)
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_MASK                      0x001f
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_ALIGN                     0
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_BITS                      5
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_SHIFT                     0
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_2500BRCM_X1            16
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X4            17
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_6000BRCM_X4            18
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_10GHiGig_X4            19
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_10GBASE_CX4            20
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_12GHiGig_X4            21
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_12p5GHiGig_X4          22
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_13GHiGig_X4            23
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_15GHiGig_X4            24
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_16GHiGig_X4            25
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X1            26
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_6363BRCM_X1            27
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_20GHiGig_X4            28
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_21GHiGig_X4            29
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_25p45GHiGig_X4         30
#define SGMII1_DIGITAL_MISC1_FORCE_SPEED_dr_10G_HiG_DXGXS          31


/****************************************************************************
 * SGMII1_Digital :: Misc2
 ***************************************************************************/
/* SGMII1_Digital :: Misc2 :: rxckpl_sel_combo [15:15] */
#define Wr_SGMII1_Digital_Misc2_rxckpl_sel_combo(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x8000,15,x)
#define Rd_SGMII1_Digital_Misc2_rxckpl_sel_combo(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x8000,15)
#define SGMII1_DIGITAL_MISC2_RXCKPL_SEL_COMBO_MASK                 0x8000
#define SGMII1_DIGITAL_MISC2_RXCKPL_SEL_COMBO_ALIGN                0
#define SGMII1_DIGITAL_MISC2_RXCKPL_SEL_COMBO_BITS                 1
#define SGMII1_DIGITAL_MISC2_RXCKPL_SEL_COMBO_SHIFT                15

/* SGMII1_Digital :: Misc2 :: reserved_14_13 [14:13] */
#define SGMII1_DIGITAL_MISC2_RESERVED_14_13_MASK                   0x6000
#define SGMII1_DIGITAL_MISC2_RESERVED_14_13_ALIGN                  0
#define SGMII1_DIGITAL_MISC2_RESERVED_14_13_BITS                   2
#define SGMII1_DIGITAL_MISC2_RESERVED_14_13_SHIFT                  13

/* SGMII1_Digital :: Misc2 :: rlpbk_sw_force [12:12] */
#define Wr_SGMII1_Digital_Misc2_rlpbk_sw_force(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x1000,12,x)
#define Rd_SGMII1_Digital_Misc2_rlpbk_sw_force(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x1000,12)
#define SGMII1_DIGITAL_MISC2_RLPBK_SW_FORCE_MASK                   0x1000
#define SGMII1_DIGITAL_MISC2_RLPBK_SW_FORCE_ALIGN                  0
#define SGMII1_DIGITAL_MISC2_RLPBK_SW_FORCE_BITS                   1
#define SGMII1_DIGITAL_MISC2_RLPBK_SW_FORCE_SHIFT                  12

/* SGMII1_Digital :: Misc2 :: rlpbk_RxRst_en [11:11] */
#define Wr_SGMII1_Digital_Misc2_rlpbk_RxRst_en(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x800,11,x)
#define Rd_SGMII1_Digital_Misc2_rlpbk_RxRst_en(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x800,11)
#define SGMII1_DIGITAL_MISC2_RLPBK_RXRST_EN_MASK                   0x0800
#define SGMII1_DIGITAL_MISC2_RLPBK_RXRST_EN_ALIGN                  0
#define SGMII1_DIGITAL_MISC2_RLPBK_RXRST_EN_BITS                   1
#define SGMII1_DIGITAL_MISC2_RLPBK_RXRST_EN_SHIFT                  11

/* SGMII1_Digital :: Misc2 :: clkSigdet_bypass [10:10] */
#define Wr_SGMII1_Digital_Misc2_clkSigdet_bypass(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x400,10,x)
#define Rd_SGMII1_Digital_Misc2_clkSigdet_bypass(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x400,10)
#define SGMII1_DIGITAL_MISC2_CLKSIGDET_BYPASS_MASK                 0x0400
#define SGMII1_DIGITAL_MISC2_CLKSIGDET_BYPASS_ALIGN                0
#define SGMII1_DIGITAL_MISC2_CLKSIGDET_BYPASS_BITS                 1
#define SGMII1_DIGITAL_MISC2_CLKSIGDET_BYPASS_SHIFT                10

/* SGMII1_Digital :: Misc2 :: clk41_bypass [09:09] */
#define Wr_SGMII1_Digital_Misc2_clk41_bypass(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x200,9,x)
#define Rd_SGMII1_Digital_Misc2_clk41_bypass(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x200,9)
#define SGMII1_DIGITAL_MISC2_CLK41_BYPASS_MASK                     0x0200
#define SGMII1_DIGITAL_MISC2_CLK41_BYPASS_ALIGN                    0
#define SGMII1_DIGITAL_MISC2_CLK41_BYPASS_BITS                     1
#define SGMII1_DIGITAL_MISC2_CLK41_BYPASS_SHIFT                    9

/* SGMII1_Digital :: Misc2 :: miiGmiiDly_en [08:08] */
#define Wr_SGMII1_Digital_Misc2_miiGmiiDly_en(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x100,8,x)
#define Rd_SGMII1_Digital_Misc2_miiGmiiDly_en(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x100,8)
#define SGMII1_DIGITAL_MISC2_MIIGMIIDLY_EN_MASK                    0x0100
#define SGMII1_DIGITAL_MISC2_MIIGMIIDLY_EN_ALIGN                   0
#define SGMII1_DIGITAL_MISC2_MIIGMIIDLY_EN_BITS                    1
#define SGMII1_DIGITAL_MISC2_MIIGMIIDLY_EN_SHIFT                   8

/* SGMII1_Digital :: Misc2 :: miiGmiiMux_en [07:07] */
#define Wr_SGMII1_Digital_Misc2_miiGmiiMux_en(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x80,7,x)
#define Rd_SGMII1_Digital_Misc2_miiGmiiMux_en(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x80,7)
#define SGMII1_DIGITAL_MISC2_MIIGMIIMUX_EN_MASK                    0x0080
#define SGMII1_DIGITAL_MISC2_MIIGMIIMUX_EN_ALIGN                   0
#define SGMII1_DIGITAL_MISC2_MIIGMIIMUX_EN_BITS                    1
#define SGMII1_DIGITAL_MISC2_MIIGMIIMUX_EN_SHIFT                   7

/* SGMII1_Digital :: Misc2 :: reserved0 [06:06] */
#define SGMII1_DIGITAL_MISC2_RESERVED0_MASK                        0x0040
#define SGMII1_DIGITAL_MISC2_RESERVED0_ALIGN                       0
#define SGMII1_DIGITAL_MISC2_RESERVED0_BITS                        1
#define SGMII1_DIGITAL_MISC2_RESERVED0_SHIFT                       6

/* SGMII1_Digital :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */
#define Wr_SGMII1_Digital_Misc2_pma_pmd_forced_speed_enc_en(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x20,5,x)
#define Rd_SGMII1_Digital_Misc2_pma_pmd_forced_speed_enc_en(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x20,5)
#define SGMII1_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK      0x0020
#define SGMII1_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN     0
#define SGMII1_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS      1
#define SGMII1_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT     5

/* SGMII1_Digital :: Misc2 :: fifo_err_cya [04:04] */
#define Wr_SGMII1_Digital_Misc2_fifo_err_cya(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x10,4,x)
#define Rd_SGMII1_Digital_Misc2_fifo_err_cya(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x10,4)
#define SGMII1_DIGITAL_MISC2_FIFO_ERR_CYA_MASK                     0x0010
#define SGMII1_DIGITAL_MISC2_FIFO_ERR_CYA_ALIGN                    0
#define SGMII1_DIGITAL_MISC2_FIFO_ERR_CYA_BITS                     1
#define SGMII1_DIGITAL_MISC2_FIFO_ERR_CYA_SHIFT                    4

/* SGMII1_Digital :: Misc2 :: an_txdisablePhase [03:03] */
#define Wr_SGMII1_Digital_Misc2_an_txdisablePhase(x) WriteRegBits16(SGMII1_DIGITAL_MISC2,0x8,3,x)
#define Rd_SGMII1_Digital_Misc2_an_txdisablePhase(x) ReadRegBits16(SGMII1_DIGITAL_MISC2,0x8,3)
#define SGMII1_DIGITAL_MISC2_AN_TXDISABLEPHASE_MASK                0x0008
#define SGMII1_DIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN               0
#define SGMII1_DIGITAL_MISC2_AN_TXDISABLEPHASE_BITS                1
#define SGMII1_DIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT               3

/* SGMII1_Digital :: Misc2 :: reserved1 [02:00] */
#define SGMII1_DIGITAL_MISC2_RESERVED1_MASK                        0x0007
#define SGMII1_DIGITAL_MISC2_RESERVED1_ALIGN                       0
#define SGMII1_DIGITAL_MISC2_RESERVED1_BITS                        3
#define SGMII1_DIGITAL_MISC2_RESERVED1_SHIFT                       0


/****************************************************************************
 * SGMII1_Digital :: PatGenCtrl
 ***************************************************************************/
/* SGMII1_Digital :: PatGenCtrl :: patgen_lpi_en [15:15] */
#define Wr_SGMII1_Digital_PatGenCtrl_patgen_lpi_en(x) WriteRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x8000,15,x)
#define Rd_SGMII1_Digital_PatGenCtrl_patgen_lpi_en(x) ReadRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x8000,15)
#define SGMII1_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_MASK               0x8000
#define SGMII1_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_ALIGN              0
#define SGMII1_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_BITS               1
#define SGMII1_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_SHIFT              15

/* SGMII1_Digital :: PatGenCtrl :: tx_err [14:14] */
#define Wr_SGMII1_Digital_PatGenCtrl_tx_err(x) WriteRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x4000,14,x)
#define Rd_SGMII1_Digital_PatGenCtrl_tx_err(x) ReadRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x4000,14)
#define SGMII1_DIGITAL_PATGENCTRL_TX_ERR_MASK                      0x4000
#define SGMII1_DIGITAL_PATGENCTRL_TX_ERR_ALIGN                     0
#define SGMII1_DIGITAL_PATGENCTRL_TX_ERR_BITS                      1
#define SGMII1_DIGITAL_PATGENCTRL_TX_ERR_SHIFT                     14

/* SGMII1_Digital :: PatGenCtrl :: skip_crc [13:13] */
#define Wr_SGMII1_Digital_PatGenCtrl_skip_crc(x) WriteRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x2000,13,x)
#define Rd_SGMII1_Digital_PatGenCtrl_skip_crc(x) ReadRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x2000,13)
#define SGMII1_DIGITAL_PATGENCTRL_SKIP_CRC_MASK                    0x2000
#define SGMII1_DIGITAL_PATGENCTRL_SKIP_CRC_ALIGN                   0
#define SGMII1_DIGITAL_PATGENCTRL_SKIP_CRC_BITS                    1
#define SGMII1_DIGITAL_PATGENCTRL_SKIP_CRC_SHIFT                   13

/* SGMII1_Digital :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */
#define Wr_SGMII1_Digital_PatGenCtrl_en_crc_checker_fragment_err_det(x) WriteRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x1000,12,x)
#define Rd_SGMII1_Digital_PatGenCtrl_en_crc_checker_fragment_err_det(x) ReadRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x1000,12)
#define SGMII1_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000
#define SGMII1_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0
#define SGMII1_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1
#define SGMII1_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12

/* SGMII1_Digital :: PatGenCtrl :: ipg_select [11:09] */
#define Wr_SGMII1_Digital_PatGenCtrl_ipg_select(x) WriteRegBits16(SGMII1_DIGITAL_PATGENCTRL,0xe00,9,x)
#define Rd_SGMII1_Digital_PatGenCtrl_ipg_select(x) ReadRegBits16(SGMII1_DIGITAL_PATGENCTRL,0xe00,9)
#define SGMII1_DIGITAL_PATGENCTRL_IPG_SELECT_MASK                  0x0e00
#define SGMII1_DIGITAL_PATGENCTRL_IPG_SELECT_ALIGN                 0
#define SGMII1_DIGITAL_PATGENCTRL_IPG_SELECT_BITS                  3
#define SGMII1_DIGITAL_PATGENCTRL_IPG_SELECT_SHIFT                 9

/* SGMII1_Digital :: PatGenCtrl :: pkt_size [08:03] */
#define Wr_SGMII1_Digital_PatGenCtrl_pkt_size(x) WriteRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x1f8,3,x)
#define Rd_SGMII1_Digital_PatGenCtrl_pkt_size(x) ReadRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x1f8,3)
#define SGMII1_DIGITAL_PATGENCTRL_PKT_SIZE_MASK                    0x01f8
#define SGMII1_DIGITAL_PATGENCTRL_PKT_SIZE_ALIGN                   0
#define SGMII1_DIGITAL_PATGENCTRL_PKT_SIZE_BITS                    6
#define SGMII1_DIGITAL_PATGENCTRL_PKT_SIZE_SHIFT                   3

/* SGMII1_Digital :: PatGenCtrl :: single_pass_mode [02:02] */
#define Wr_SGMII1_Digital_PatGenCtrl_single_pass_mode(x) WriteRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x4,2,x)
#define Rd_SGMII1_Digital_PatGenCtrl_single_pass_mode(x) ReadRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x4,2)
#define SGMII1_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_MASK            0x0004
#define SGMII1_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_ALIGN           0
#define SGMII1_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_BITS            1
#define SGMII1_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_SHIFT           2

/* SGMII1_Digital :: PatGenCtrl :: run_pattern_gen [01:01] */
#define Wr_SGMII1_Digital_PatGenCtrl_run_pattern_gen(x) WriteRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x2,1,x)
#define Rd_SGMII1_Digital_PatGenCtrl_run_pattern_gen(x) ReadRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x2,1)
#define SGMII1_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_MASK             0x0002
#define SGMII1_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_ALIGN            0
#define SGMII1_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_BITS             1
#define SGMII1_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_SHIFT            1

/* SGMII1_Digital :: PatGenCtrl :: sel_pattern_gen_data [00:00] */
#define Wr_SGMII1_Digital_PatGenCtrl_sel_pattern_gen_data(x) WriteRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x1,0,x)
#define Rd_SGMII1_Digital_PatGenCtrl_sel_pattern_gen_data(x) ReadRegBits16(SGMII1_DIGITAL_PATGENCTRL,0x1,0)
#define SGMII1_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK        0x0001
#define SGMII1_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN       0
#define SGMII1_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS        1
#define SGMII1_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT       0


/****************************************************************************
 * SGMII1_Digital :: PatGenStat
 ***************************************************************************/
/* SGMII1_Digital :: PatGenStat :: reserved0 [15:04] */
#define SGMII1_DIGITAL_PATGENSTAT_RESERVED0_MASK                   0xfff0
#define SGMII1_DIGITAL_PATGENSTAT_RESERVED0_ALIGN                  0
#define SGMII1_DIGITAL_PATGENSTAT_RESERVED0_BITS                   12
#define SGMII1_DIGITAL_PATGENSTAT_RESERVED0_SHIFT                  4

/* SGMII1_Digital :: PatGenStat :: pattern_gen_active [03:03] */
#define Wr_SGMII1_Digital_PatGenStat_pattern_gen_active(x) WriteRegBits16(SGMII1_DIGITAL_PATGENSTAT,0x8,3,x)
#define Rd_SGMII1_Digital_PatGenStat_pattern_gen_active(x) ReadRegBits16(SGMII1_DIGITAL_PATGENSTAT,0x8,3)
#define SGMII1_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK          0x0008
#define SGMII1_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN         0
#define SGMII1_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS          1
#define SGMII1_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT         3

/* SGMII1_Digital :: PatGenStat :: pattern_gen_fsm [02:00] */
#define Wr_SGMII1_Digital_PatGenStat_pattern_gen_fsm(x) WriteRegBits16(SGMII1_DIGITAL_PATGENSTAT,0x7,0,x)
#define Rd_SGMII1_Digital_PatGenStat_pattern_gen_fsm(x) ReadRegBits16(SGMII1_DIGITAL_PATGENSTAT,0x7,0)
#define SGMII1_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_MASK             0x0007
#define SGMII1_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_ALIGN            0
#define SGMII1_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_BITS             3
#define SGMII1_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_SHIFT            0


/****************************************************************************
 * SGMII1_Digital :: TestMode
 ***************************************************************************/
/* SGMII1_Digital :: TestMode :: disable_reset_cnt [15:15] */
#define Wr_SGMII1_Digital_TestMode_disable_reset_cnt(x) WriteRegBits16(SGMII1_DIGITAL_TESTMODE,0x8000,15,x)
#define Rd_SGMII1_Digital_TestMode_disable_reset_cnt(x) ReadRegBits16(SGMII1_DIGITAL_TESTMODE,0x8000,15)
#define SGMII1_DIGITAL_TESTMODE_DISABLE_RESET_CNT_MASK             0x8000
#define SGMII1_DIGITAL_TESTMODE_DISABLE_RESET_CNT_ALIGN            0
#define SGMII1_DIGITAL_TESTMODE_DISABLE_RESET_CNT_BITS             1
#define SGMII1_DIGITAL_TESTMODE_DISABLE_RESET_CNT_SHIFT            15

/* SGMII1_Digital :: TestMode :: clear_packet_counters [14:14] */
#define Wr_SGMII1_Digital_TestMode_clear_packet_counters(x) WriteRegBits16(SGMII1_DIGITAL_TESTMODE,0x4000,14,x)
#define Rd_SGMII1_Digital_TestMode_clear_packet_counters(x) ReadRegBits16(SGMII1_DIGITAL_TESTMODE,0x4000,14)
#define SGMII1_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_MASK         0x4000
#define SGMII1_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN        0
#define SGMII1_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_BITS         1
#define SGMII1_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT        14

/* SGMII1_Digital :: TestMode :: reserved0 [13:05] */
#define SGMII1_DIGITAL_TESTMODE_RESERVED0_MASK                     0x3fe0
#define SGMII1_DIGITAL_TESTMODE_RESERVED0_ALIGN                    0
#define SGMII1_DIGITAL_TESTMODE_RESERVED0_BITS                     9
#define SGMII1_DIGITAL_TESTMODE_RESERVED0_SHIFT                    5

/* SGMII1_Digital :: TestMode :: fifo_fsm_cya_rx [04:04] */
#define Wr_SGMII1_Digital_TestMode_fifo_fsm_cya_rx(x) WriteRegBits16(SGMII1_DIGITAL_TESTMODE,0x10,4,x)
#define Rd_SGMII1_Digital_TestMode_fifo_fsm_cya_rx(x) ReadRegBits16(SGMII1_DIGITAL_TESTMODE,0x10,4)
#define SGMII1_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_MASK               0x0010
#define SGMII1_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_ALIGN              0
#define SGMII1_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_BITS               1
#define SGMII1_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_SHIFT              4

/* SGMII1_Digital :: TestMode :: dig1000x_afrst_cya [03:03] */
#define Wr_SGMII1_Digital_TestMode_dig1000x_afrst_cya(x) WriteRegBits16(SGMII1_DIGITAL_TESTMODE,0x8,3,x)
#define Rd_SGMII1_Digital_TestMode_dig1000x_afrst_cya(x) ReadRegBits16(SGMII1_DIGITAL_TESTMODE,0x8,3)
#define SGMII1_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_MASK            0x0008
#define SGMII1_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_ALIGN           0
#define SGMII1_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_BITS            1
#define SGMII1_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_SHIFT           3

/* SGMII1_Digital :: TestMode :: fifo_elasticity_rx [02:01] */
#define Wr_SGMII1_Digital_TestMode_fifo_elasticity_rx(x) WriteRegBits16(SGMII1_DIGITAL_TESTMODE,0x6,1,x)
#define Rd_SGMII1_Digital_TestMode_fifo_elasticity_rx(x) ReadRegBits16(SGMII1_DIGITAL_TESTMODE,0x6,1)
#define SGMII1_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_MASK            0x0006
#define SGMII1_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_ALIGN           0
#define SGMII1_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_BITS            2
#define SGMII1_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_SHIFT           1

/* SGMII1_Digital :: TestMode :: fifo_ipg_rx_cya [00:00] */
#define Wr_SGMII1_Digital_TestMode_fifo_ipg_rx_cya(x) WriteRegBits16(SGMII1_DIGITAL_TESTMODE,0x1,0,x)
#define Rd_SGMII1_Digital_TestMode_fifo_ipg_rx_cya(x) ReadRegBits16(SGMII1_DIGITAL_TESTMODE,0x1,0)
#define SGMII1_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_MASK               0x0001
#define SGMII1_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_ALIGN              0
#define SGMII1_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_BITS               1
#define SGMII1_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_SHIFT              0


/****************************************************************************
 * SGMII1_Digital :: TxPktCnt
 ***************************************************************************/
/* SGMII1_Digital :: TxPktCnt :: TxPktCnt [15:00] */
#define Wr_SGMII1_Digital_TxPktCnt_TxPktCnt(x) WriteReg16(SGMII1_DIGITAL_TXPKTCNT,x)
#define Rd_SGMII1_Digital_TxPktCnt_TxPktCnt(x) ReadReg16(SGMII1_DIGITAL_TXPKTCNT)
#define SGMII1_DIGITAL_TXPKTCNT_TXPKTCNT_MASK                      0xffff
#define SGMII1_DIGITAL_TXPKTCNT_TXPKTCNT_ALIGN                     0
#define SGMII1_DIGITAL_TXPKTCNT_TXPKTCNT_BITS                      16
#define SGMII1_DIGITAL_TXPKTCNT_TXPKTCNT_SHIFT                     0


/****************************************************************************
 * SGMII1_Digital :: RxPktCnt
 ***************************************************************************/
/* SGMII1_Digital :: RxPktCnt :: RxPktCnt [15:00] */
#define Wr_SGMII1_Digital_RxPktCnt_RxPktCnt(x) WriteReg16(SGMII1_DIGITAL_RXPKTCNT,x)
#define Rd_SGMII1_Digital_RxPktCnt_RxPktCnt(x) ReadReg16(SGMII1_DIGITAL_RXPKTCNT)
#define SGMII1_DIGITAL_RXPKTCNT_RXPKTCNT_MASK                      0xffff
#define SGMII1_DIGITAL_RXPKTCNT_RXPKTCNT_ALIGN                     0
#define SGMII1_DIGITAL_RXPKTCNT_RXPKTCNT_BITS                      16
#define SGMII1_DIGITAL_RXPKTCNT_RXPKTCNT_SHIFT                     0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_serdesID
 ***************************************************************************/
/****************************************************************************
 * SGMII1_serdesID :: serdesID0
 ***************************************************************************/
/* SGMII1_serdesID :: serdesID0 :: rev_letter [15:14] */
#define Wr_SGMII1_serdesID_serdesID0_rev_letter(x) WriteRegBits16(SGMII1_SERDESID_SERDESID0,0xc000,14,x)
#define Rd_SGMII1_serdesID_serdesID0_rev_letter(x) ReadRegBits16(SGMII1_SERDESID_SERDESID0,0xc000,14)
#define SGMII1_SERDESID_SERDESID0_REV_LETTER_MASK                  0xc000
#define SGMII1_SERDESID_SERDESID0_REV_LETTER_ALIGN                 0
#define SGMII1_SERDESID_SERDESID0_REV_LETTER_BITS                  2
#define SGMII1_SERDESID_SERDESID0_REV_LETTER_SHIFT                 14

/* SGMII1_serdesID :: serdesID0 :: rev_number [13:11] */
#define Wr_SGMII1_serdesID_serdesID0_rev_number(x) WriteRegBits16(SGMII1_SERDESID_SERDESID0,0x3800,11,x)
#define Rd_SGMII1_serdesID_serdesID0_rev_number(x) ReadRegBits16(SGMII1_SERDESID_SERDESID0,0x3800,11)
#define SGMII1_SERDESID_SERDESID0_REV_NUMBER_MASK                  0x3800
#define SGMII1_SERDESID_SERDESID0_REV_NUMBER_ALIGN                 0
#define SGMII1_SERDESID_SERDESID0_REV_NUMBER_BITS                  3
#define SGMII1_SERDESID_SERDESID0_REV_NUMBER_SHIFT                 11

/* SGMII1_serdesID :: serdesID0 :: bonding [10:09] */
#define Wr_SGMII1_serdesID_serdesID0_bonding(x) WriteRegBits16(SGMII1_SERDESID_SERDESID0,0x600,9,x)
#define Rd_SGMII1_serdesID_serdesID0_bonding(x) ReadRegBits16(SGMII1_SERDESID_SERDESID0,0x600,9)
#define SGMII1_SERDESID_SERDESID0_BONDING_MASK                     0x0600
#define SGMII1_SERDESID_SERDESID0_BONDING_ALIGN                    0
#define SGMII1_SERDESID_SERDESID0_BONDING_BITS                     2
#define SGMII1_SERDESID_SERDESID0_BONDING_SHIFT                    9

/* SGMII1_serdesID :: serdesID0 :: tech_proc [08:06] */
#define Wr_SGMII1_serdesID_serdesID0_tech_proc(x) WriteRegBits16(SGMII1_SERDESID_SERDESID0,0x1c0,6,x)
#define Rd_SGMII1_serdesID_serdesID0_tech_proc(x) ReadRegBits16(SGMII1_SERDESID_SERDESID0,0x1c0,6)
#define SGMII1_SERDESID_SERDESID0_TECH_PROC_MASK                   0x01c0
#define SGMII1_SERDESID_SERDESID0_TECH_PROC_ALIGN                  0
#define SGMII1_SERDESID_SERDESID0_TECH_PROC_BITS                   3
#define SGMII1_SERDESID_SERDESID0_TECH_PROC_SHIFT                  6

/* SGMII1_serdesID :: serdesID0 :: model_number [05:00] */
#define Wr_SGMII1_serdesID_serdesID0_model_number(x) WriteRegBits16(SGMII1_SERDESID_SERDESID0,0x3f,0,x)
#define Rd_SGMII1_serdesID_serdesID0_model_number(x) ReadRegBits16(SGMII1_SERDESID_SERDESID0,0x3f,0)
#define SGMII1_SERDESID_SERDESID0_MODEL_NUMBER_MASK                0x003f
#define SGMII1_SERDESID_SERDESID0_MODEL_NUMBER_ALIGN               0
#define SGMII1_SERDESID_SERDESID0_MODEL_NUMBER_BITS                6
#define SGMII1_SERDESID_SERDESID0_MODEL_NUMBER_SHIFT               0


/****************************************************************************
 * SGMII1_serdesID :: serdesID1
 ***************************************************************************/
/* SGMII1_serdesID :: serdesID1 :: multiplicity [15:12] */
#define Wr_SGMII1_serdesID_serdesID1_multiplicity(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0xf000,12,x)
#define Rd_SGMII1_serdesID_serdesID1_multiplicity(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0xf000,12)
#define SGMII1_SERDESID_SERDESID1_MULTIPLICITY_MASK                0xf000
#define SGMII1_SERDESID_SERDESID1_MULTIPLICITY_ALIGN               0
#define SGMII1_SERDESID_SERDESID1_MULTIPLICITY_BITS                4
#define SGMII1_SERDESID_SERDESID1_MULTIPLICITY_SHIFT               12

/* SGMII1_serdesID :: serdesID1 :: CL37 [11:11] */
#define Wr_SGMII1_serdesID_serdesID1_CL37(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x800,11,x)
#define Rd_SGMII1_serdesID_serdesID1_CL37(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x800,11)
#define SGMII1_SERDESID_SERDESID1_CL37_MASK                        0x0800
#define SGMII1_SERDESID_SERDESID1_CL37_ALIGN                       0
#define SGMII1_SERDESID_SERDESID1_CL37_BITS                        1
#define SGMII1_SERDESID_SERDESID1_CL37_SHIFT                       11

/* SGMII1_serdesID :: serdesID1 :: CL73 [10:10] */
#define Wr_SGMII1_serdesID_serdesID1_CL73(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x400,10,x)
#define Rd_SGMII1_serdesID_serdesID1_CL73(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x400,10)
#define SGMII1_SERDESID_SERDESID1_CL73_MASK                        0x0400
#define SGMII1_SERDESID_SERDESID1_CL73_ALIGN                       0
#define SGMII1_SERDESID_SERDESID1_CL73_BITS                        1
#define SGMII1_SERDESID_SERDESID1_CL73_SHIFT                       10

/* SGMII1_serdesID :: serdesID1 :: CL36 [09:09] */
#define Wr_SGMII1_serdesID_serdesID1_CL36(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x200,9,x)
#define Rd_SGMII1_serdesID_serdesID1_CL36(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x200,9)
#define SGMII1_SERDESID_SERDESID1_CL36_MASK                        0x0200
#define SGMII1_SERDESID_SERDESID1_CL36_ALIGN                       0
#define SGMII1_SERDESID_SERDESID1_CL36_BITS                        1
#define SGMII1_SERDESID_SERDESID1_CL36_SHIFT                       9

/* SGMII1_serdesID :: serdesID1 :: CL48 [08:08] */
#define Wr_SGMII1_serdesID_serdesID1_CL48(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x100,8,x)
#define Rd_SGMII1_serdesID_serdesID1_CL48(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x100,8)
#define SGMII1_SERDESID_SERDESID1_CL48_MASK                        0x0100
#define SGMII1_SERDESID_SERDESID1_CL48_ALIGN                       0
#define SGMII1_SERDESID_SERDESID1_CL48_BITS                        1
#define SGMII1_SERDESID_SERDESID1_CL48_SHIFT                       8

/* SGMII1_serdesID :: serdesID1 :: HiGig [07:07] */
#define Wr_SGMII1_serdesID_serdesID1_HiGig(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x80,7,x)
#define Rd_SGMII1_serdesID_serdesID1_HiGig(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x80,7)
#define SGMII1_SERDESID_SERDESID1_HIGIG_MASK                       0x0080
#define SGMII1_SERDESID_SERDESID1_HIGIG_ALIGN                      0
#define SGMII1_SERDESID_SERDESID1_HIGIG_BITS                       1
#define SGMII1_SERDESID_SERDESID1_HIGIG_SHIFT                      7

/* SGMII1_serdesID :: serdesID1 :: HiGigII [06:06] */
#define Wr_SGMII1_serdesID_serdesID1_HiGigII(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x40,6,x)
#define Rd_SGMII1_serdesID_serdesID1_HiGigII(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x40,6)
#define SGMII1_SERDESID_SERDESID1_HIGIGII_MASK                     0x0040
#define SGMII1_SERDESID_SERDESID1_HIGIGII_ALIGN                    0
#define SGMII1_SERDESID_SERDESID1_HIGIGII_BITS                     1
#define SGMII1_SERDESID_SERDESID1_HIGIGII_SHIFT                    6

/* SGMII1_serdesID :: serdesID1 :: PCIE [05:05] */
#define Wr_SGMII1_serdesID_serdesID1_PCIE(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x20,5,x)
#define Rd_SGMII1_serdesID_serdesID1_PCIE(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x20,5)
#define SGMII1_SERDESID_SERDESID1_PCIE_MASK                        0x0020
#define SGMII1_SERDESID_SERDESID1_PCIE_ALIGN                       0
#define SGMII1_SERDESID_SERDESID1_PCIE_BITS                        1
#define SGMII1_SERDESID_SERDESID1_PCIE_SHIFT                       5

/* SGMII1_serdesID :: serdesID1 :: PCIE_II [04:04] */
#define Wr_SGMII1_serdesID_serdesID1_PCIE_II(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x10,4,x)
#define Rd_SGMII1_serdesID_serdesID1_PCIE_II(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x10,4)
#define SGMII1_SERDESID_SERDESID1_PCIE_II_MASK                     0x0010
#define SGMII1_SERDESID_SERDESID1_PCIE_II_ALIGN                    0
#define SGMII1_SERDESID_SERDESID1_PCIE_II_BITS                     1
#define SGMII1_SERDESID_SERDESID1_PCIE_II_SHIFT                    4

/* SGMII1_serdesID :: serdesID1 :: brcm_64B66B [03:03] */
#define Wr_SGMII1_serdesID_serdesID1_brcm_64B66B(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x8,3,x)
#define Rd_SGMII1_serdesID_serdesID1_brcm_64B66B(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x8,3)
#define SGMII1_SERDESID_SERDESID1_BRCM_64B66B_MASK                 0x0008
#define SGMII1_SERDESID_SERDESID1_BRCM_64B66B_ALIGN                0
#define SGMII1_SERDESID_SERDESID1_BRCM_64B66B_BITS                 1
#define SGMII1_SERDESID_SERDESID1_BRCM_64B66B_SHIFT                3

/* SGMII1_serdesID :: serdesID1 :: Scrambler [02:02] */
#define Wr_SGMII1_serdesID_serdesID1_Scrambler(x) WriteRegBits16(SGMII1_SERDESID_SERDESID1,0x4,2,x)
#define Rd_SGMII1_serdesID_serdesID1_Scrambler(x) ReadRegBits16(SGMII1_SERDESID_SERDESID1,0x4,2)
#define SGMII1_SERDESID_SERDESID1_SCRAMBLER_MASK                   0x0004
#define SGMII1_SERDESID_SERDESID1_SCRAMBLER_ALIGN                  0
#define SGMII1_SERDESID_SERDESID1_SCRAMBLER_BITS                   1
#define SGMII1_SERDESID_SERDESID1_SCRAMBLER_SHIFT                  2

/* SGMII1_serdesID :: serdesID1 :: reserved0 [01:00] */
#define SGMII1_SERDESID_SERDESID1_RESERVED0_MASK                   0x0003
#define SGMII1_SERDESID_SERDESID1_RESERVED0_ALIGN                  0
#define SGMII1_SERDESID_SERDESID1_RESERVED0_BITS                   2
#define SGMII1_SERDESID_SERDESID1_RESERVED0_SHIFT                  0


/****************************************************************************
 * SGMII1_serdesID :: serdesID2
 ***************************************************************************/
/* SGMII1_serdesID :: serdesID2 :: ID3present [15:15] */
#define Wr_SGMII1_serdesID_serdesID2_ID3present(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x8000,15,x)
#define Rd_SGMII1_serdesID_serdesID2_ID3present(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x8000,15)
#define SGMII1_SERDESID_SERDESID2_ID3PRESENT_MASK                  0x8000
#define SGMII1_SERDESID_SERDESID2_ID3PRESENT_ALIGN                 0
#define SGMII1_SERDESID_SERDESID2_ID3PRESENT_BITS                  1
#define SGMII1_SERDESID_SERDESID2_ID3PRESENT_SHIFT                 15

/* SGMII1_serdesID :: serdesID2 :: dr_25G_4L [14:14] */
#define Wr_SGMII1_serdesID_serdesID2_dr_25G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x4000,14,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_25G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x4000,14)
#define SGMII1_SERDESID_SERDESID2_DR_25G_4L_MASK                   0x4000
#define SGMII1_SERDESID_SERDESID2_DR_25G_4L_ALIGN                  0
#define SGMII1_SERDESID_SERDESID2_DR_25G_4L_BITS                   1
#define SGMII1_SERDESID_SERDESID2_DR_25G_4L_SHIFT                  14

/* SGMII1_serdesID :: serdesID2 :: dr_21G_4L [13:13] */
#define Wr_SGMII1_serdesID_serdesID2_dr_21G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x2000,13,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_21G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x2000,13)
#define SGMII1_SERDESID_SERDESID2_DR_21G_4L_MASK                   0x2000
#define SGMII1_SERDESID_SERDESID2_DR_21G_4L_ALIGN                  0
#define SGMII1_SERDESID_SERDESID2_DR_21G_4L_BITS                   1
#define SGMII1_SERDESID_SERDESID2_DR_21G_4L_SHIFT                  13

/* SGMII1_serdesID :: serdesID2 :: dr_20G_4L [12:12] */
#define Wr_SGMII1_serdesID_serdesID2_dr_20G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x1000,12,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_20G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x1000,12)
#define SGMII1_SERDESID_SERDESID2_DR_20G_4L_MASK                   0x1000
#define SGMII1_SERDESID_SERDESID2_DR_20G_4L_ALIGN                  0
#define SGMII1_SERDESID_SERDESID2_DR_20G_4L_BITS                   1
#define SGMII1_SERDESID_SERDESID2_DR_20G_4L_SHIFT                  12

/* SGMII1_serdesID :: serdesID2 :: dr_16G_4L [11:11] */
#define Wr_SGMII1_serdesID_serdesID2_dr_16G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x800,11,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_16G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x800,11)
#define SGMII1_SERDESID_SERDESID2_DR_16G_4L_MASK                   0x0800
#define SGMII1_SERDESID_SERDESID2_DR_16G_4L_ALIGN                  0
#define SGMII1_SERDESID_SERDESID2_DR_16G_4L_BITS                   1
#define SGMII1_SERDESID_SERDESID2_DR_16G_4L_SHIFT                  11

/* SGMII1_serdesID :: serdesID2 :: dr_15G_4L [10:10] */
#define Wr_SGMII1_serdesID_serdesID2_dr_15G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x400,10,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_15G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x400,10)
#define SGMII1_SERDESID_SERDESID2_DR_15G_4L_MASK                   0x0400
#define SGMII1_SERDESID_SERDESID2_DR_15G_4L_ALIGN                  0
#define SGMII1_SERDESID_SERDESID2_DR_15G_4L_BITS                   1
#define SGMII1_SERDESID_SERDESID2_DR_15G_4L_SHIFT                  10

/* SGMII1_serdesID :: serdesID2 :: dr_13G_4L [09:09] */
#define Wr_SGMII1_serdesID_serdesID2_dr_13G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x200,9,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_13G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x200,9)
#define SGMII1_SERDESID_SERDESID2_DR_13G_4L_MASK                   0x0200
#define SGMII1_SERDESID_SERDESID2_DR_13G_4L_ALIGN                  0
#define SGMII1_SERDESID_SERDESID2_DR_13G_4L_BITS                   1
#define SGMII1_SERDESID_SERDESID2_DR_13G_4L_SHIFT                  9

/* SGMII1_serdesID :: serdesID2 :: dr_12_5G_4L [08:08] */
#define Wr_SGMII1_serdesID_serdesID2_dr_12_5G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x100,8,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_12_5G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x100,8)
#define SGMII1_SERDESID_SERDESID2_DR_12_5G_4L_MASK                 0x0100
#define SGMII1_SERDESID_SERDESID2_DR_12_5G_4L_ALIGN                0
#define SGMII1_SERDESID_SERDESID2_DR_12_5G_4L_BITS                 1
#define SGMII1_SERDESID_SERDESID2_DR_12_5G_4L_SHIFT                8

/* SGMII1_serdesID :: serdesID2 :: dr_12G_4L [07:07] */
#define Wr_SGMII1_serdesID_serdesID2_dr_12G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x80,7,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_12G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x80,7)
#define SGMII1_SERDESID_SERDESID2_DR_12G_4L_MASK                   0x0080
#define SGMII1_SERDESID_SERDESID2_DR_12G_4L_ALIGN                  0
#define SGMII1_SERDESID_SERDESID2_DR_12G_4L_BITS                   1
#define SGMII1_SERDESID_SERDESID2_DR_12G_4L_SHIFT                  7

/* SGMII1_serdesID :: serdesID2 :: dr_10G_4L [06:06] */
#define Wr_SGMII1_serdesID_serdesID2_dr_10G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x40,6,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_10G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x40,6)
#define SGMII1_SERDESID_SERDESID2_DR_10G_4L_MASK                   0x0040
#define SGMII1_SERDESID_SERDESID2_DR_10G_4L_ALIGN                  0
#define SGMII1_SERDESID_SERDESID2_DR_10G_4L_BITS                   1
#define SGMII1_SERDESID_SERDESID2_DR_10G_4L_SHIFT                  6

/* SGMII1_serdesID :: serdesID2 :: dr_6G_4L [05:05] */
#define Wr_SGMII1_serdesID_serdesID2_dr_6G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x20,5,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_6G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x20,5)
#define SGMII1_SERDESID_SERDESID2_DR_6G_4L_MASK                    0x0020
#define SGMII1_SERDESID_SERDESID2_DR_6G_4L_ALIGN                   0
#define SGMII1_SERDESID_SERDESID2_DR_6G_4L_BITS                    1
#define SGMII1_SERDESID_SERDESID2_DR_6G_4L_SHIFT                   5

/* SGMII1_serdesID :: serdesID2 :: dr_5G_4L [04:04] */
#define Wr_SGMII1_serdesID_serdesID2_dr_5G_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x10,4,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_5G_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x10,4)
#define SGMII1_SERDESID_SERDESID2_DR_5G_4L_MASK                    0x0010
#define SGMII1_SERDESID_SERDESID2_DR_5G_4L_ALIGN                   0
#define SGMII1_SERDESID_SERDESID2_DR_5G_4L_BITS                    1
#define SGMII1_SERDESID_SERDESID2_DR_5G_4L_SHIFT                   4

/* SGMII1_serdesID :: serdesID2 :: dr_2p5G_SL [03:03] */
#define Wr_SGMII1_serdesID_serdesID2_dr_2p5G_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x8,3,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_2p5G_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x8,3)
#define SGMII1_SERDESID_SERDESID2_DR_2P5G_SL_MASK                  0x0008
#define SGMII1_SERDESID_SERDESID2_DR_2P5G_SL_ALIGN                 0
#define SGMII1_SERDESID_SERDESID2_DR_2P5G_SL_BITS                  1
#define SGMII1_SERDESID_SERDESID2_DR_2P5G_SL_SHIFT                 3

/* SGMII1_serdesID :: serdesID2 :: dr_1G_SL [02:02] */
#define Wr_SGMII1_serdesID_serdesID2_dr_1G_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x4,2,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_1G_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x4,2)
#define SGMII1_SERDESID_SERDESID2_DR_1G_SL_MASK                    0x0004
#define SGMII1_SERDESID_SERDESID2_DR_1G_SL_ALIGN                   0
#define SGMII1_SERDESID_SERDESID2_DR_1G_SL_BITS                    1
#define SGMII1_SERDESID_SERDESID2_DR_1G_SL_SHIFT                   2

/* SGMII1_serdesID :: serdesID2 :: dr_100M_SL [01:01] */
#define Wr_SGMII1_serdesID_serdesID2_dr_100M_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x2,1,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_100M_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x2,1)
#define SGMII1_SERDESID_SERDESID2_DR_100M_SL_MASK                  0x0002
#define SGMII1_SERDESID_SERDESID2_DR_100M_SL_ALIGN                 0
#define SGMII1_SERDESID_SERDESID2_DR_100M_SL_BITS                  1
#define SGMII1_SERDESID_SERDESID2_DR_100M_SL_SHIFT                 1

/* SGMII1_serdesID :: serdesID2 :: dr_10M_SL [00:00] */
#define Wr_SGMII1_serdesID_serdesID2_dr_10M_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID2,0x1,0,x)
#define Rd_SGMII1_serdesID_serdesID2_dr_10M_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID2,0x1,0)
#define SGMII1_SERDESID_SERDESID2_DR_10M_SL_MASK                   0x0001
#define SGMII1_SERDESID_SERDESID2_DR_10M_SL_ALIGN                  0
#define SGMII1_SERDESID_SERDESID2_DR_10M_SL_BITS                   1
#define SGMII1_SERDESID_SERDESID2_DR_10M_SL_SHIFT                  0


/****************************************************************************
 * SGMII1_serdesID :: serdesID3
 ***************************************************************************/
/* SGMII1_serdesID :: serdesID3 :: ID4present [15:15] */
#define Wr_SGMII1_serdesID_serdesID3_ID4present(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x8000,15,x)
#define Rd_SGMII1_serdesID_serdesID3_ID4present(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x8000,15)
#define SGMII1_SERDESID_SERDESID3_ID4PRESENT_MASK                  0x8000
#define SGMII1_SERDESID_SERDESID3_ID4PRESENT_ALIGN                 0
#define SGMII1_SERDESID_SERDESID3_ID4PRESENT_BITS                  1
#define SGMII1_SERDESID_SERDESID3_ID4PRESENT_SHIFT                 15

/* SGMII1_serdesID :: serdesID3 :: reserved0 [14:10] */
#define SGMII1_SERDESID_SERDESID3_RESERVED0_MASK                   0x7c00
#define SGMII1_SERDESID_SERDESID3_RESERVED0_ALIGN                  0
#define SGMII1_SERDESID_SERDESID3_RESERVED0_BITS                   5
#define SGMII1_SERDESID_SERDESID3_RESERVED0_SHIFT                  10

/* SGMII1_serdesID :: serdesID3 :: dr_40000_4L [09:09] */
#define Wr_SGMII1_serdesID_serdesID3_dr_40000_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x200,9,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_40000_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x200,9)
#define SGMII1_SERDESID_SERDESID3_DR_40000_4L_MASK                 0x0200
#define SGMII1_SERDESID_SERDESID3_DR_40000_4L_ALIGN                0
#define SGMII1_SERDESID_SERDESID3_DR_40000_4L_BITS                 1
#define SGMII1_SERDESID_SERDESID3_DR_40000_4L_SHIFT                9

/* SGMII1_serdesID :: serdesID3 :: dr_32700_4L [08:08] */
#define Wr_SGMII1_serdesID_serdesID3_dr_32700_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x100,8,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_32700_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x100,8)
#define SGMII1_SERDESID_SERDESID3_DR_32700_4L_MASK                 0x0100
#define SGMII1_SERDESID_SERDESID3_DR_32700_4L_ALIGN                0
#define SGMII1_SERDESID_SERDESID3_DR_32700_4L_BITS                 1
#define SGMII1_SERDESID_SERDESID3_DR_32700_4L_SHIFT                8

/* SGMII1_serdesID :: serdesID3 :: dr_31500_4L [07:07] */
#define Wr_SGMII1_serdesID_serdesID3_dr_31500_4L(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x80,7,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_31500_4L(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x80,7)
#define SGMII1_SERDESID_SERDESID3_DR_31500_4L_MASK                 0x0080
#define SGMII1_SERDESID_SERDESID3_DR_31500_4L_ALIGN                0
#define SGMII1_SERDESID_SERDESID3_DR_31500_4L_BITS                 1
#define SGMII1_SERDESID_SERDESID3_DR_31500_4L_SHIFT                7

/* SGMII1_serdesID :: serdesID3 :: dr_2400_SL [06:06] */
#define Wr_SGMII1_serdesID_serdesID3_dr_2400_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x40,6,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_2400_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x40,6)
#define SGMII1_SERDESID_SERDESID3_DR_2400_SL_MASK                  0x0040
#define SGMII1_SERDESID_SERDESID3_DR_2400_SL_ALIGN                 0
#define SGMII1_SERDESID_SERDESID3_DR_2400_SL_BITS                  1
#define SGMII1_SERDESID_SERDESID3_DR_2400_SL_SHIFT                 6

/* SGMII1_serdesID :: serdesID3 :: dr_1200_SL [05:05] */
#define Wr_SGMII1_serdesID_serdesID3_dr_1200_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x20,5,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_1200_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x20,5)
#define SGMII1_SERDESID_SERDESID3_DR_1200_SL_MASK                  0x0020
#define SGMII1_SERDESID_SERDESID3_DR_1200_SL_ALIGN                 0
#define SGMII1_SERDESID_SERDESID3_DR_1200_SL_BITS                  1
#define SGMII1_SERDESID_SERDESID3_DR_1200_SL_SHIFT                 5

/* SGMII1_serdesID :: serdesID3 :: dr_6400_SL [04:04] */
#define Wr_SGMII1_serdesID_serdesID3_dr_6400_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x10,4,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_6400_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x10,4)
#define SGMII1_SERDESID_SERDESID3_DR_6400_SL_MASK                  0x0010
#define SGMII1_SERDESID_SERDESID3_DR_6400_SL_ALIGN                 0
#define SGMII1_SERDESID_SERDESID3_DR_6400_SL_BITS                  1
#define SGMII1_SERDESID_SERDESID3_DR_6400_SL_SHIFT                 4

/* SGMII1_serdesID :: serdesID3 :: dr_5000_SL [03:03] */
#define Wr_SGMII1_serdesID_serdesID3_dr_5000_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x8,3,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_5000_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x8,3)
#define SGMII1_SERDESID_SERDESID3_DR_5000_SL_MASK                  0x0008
#define SGMII1_SERDESID_SERDESID3_DR_5000_SL_ALIGN                 0
#define SGMII1_SERDESID_SERDESID3_DR_5000_SL_BITS                  1
#define SGMII1_SERDESID_SERDESID3_DR_5000_SL_SHIFT                 3

/* SGMII1_serdesID :: serdesID3 :: dr_4000_SL [02:02] */
#define Wr_SGMII1_serdesID_serdesID3_dr_4000_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x4,2,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_4000_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x4,2)
#define SGMII1_SERDESID_SERDESID3_DR_4000_SL_MASK                  0x0004
#define SGMII1_SERDESID_SERDESID3_DR_4000_SL_ALIGN                 0
#define SGMII1_SERDESID_SERDESID3_DR_4000_SL_BITS                  1
#define SGMII1_SERDESID_SERDESID3_DR_4000_SL_SHIFT                 2

/* SGMII1_serdesID :: serdesID3 :: dr_2000_SL [01:01] */
#define Wr_SGMII1_serdesID_serdesID3_dr_2000_SL(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x2,1,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_2000_SL(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x2,1)
#define SGMII1_SERDESID_SERDESID3_DR_2000_SL_MASK                  0x0002
#define SGMII1_SERDESID_SERDESID3_DR_2000_SL_ALIGN                 0
#define SGMII1_SERDESID_SERDESID3_DR_2000_SL_BITS                  1
#define SGMII1_SERDESID_SERDESID3_DR_2000_SL_SHIFT                 1

/* SGMII1_serdesID :: serdesID3 :: dr_100FX [00:00] */
#define Wr_SGMII1_serdesID_serdesID3_dr_100FX(x) WriteRegBits16(SGMII1_SERDESID_SERDESID3,0x1,0,x)
#define Rd_SGMII1_serdesID_serdesID3_dr_100FX(x) ReadRegBits16(SGMII1_SERDESID_SERDESID3,0x1,0)
#define SGMII1_SERDESID_SERDESID3_DR_100FX_MASK                    0x0001
#define SGMII1_SERDESID_SERDESID3_DR_100FX_ALIGN                   0
#define SGMII1_SERDESID_SERDESID3_DR_100FX_BITS                    1
#define SGMII1_SERDESID_SERDESID3_DR_100FX_SHIFT                   0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_Digital3
 ***************************************************************************/
/****************************************************************************
 * SGMII1_Digital3 :: TPOUT_1
 ***************************************************************************/
/* SGMII1_Digital3 :: TPOUT_1 :: tpout1 [15:00] */
#define Wr_SGMII1_Digital3_TPOUT_1_tpout1(x) WriteReg16(SGMII1_DIGITAL3_TPOUT_1,x)
#define Rd_SGMII1_Digital3_TPOUT_1_tpout1(x) ReadReg16(SGMII1_DIGITAL3_TPOUT_1)
#define SGMII1_DIGITAL3_TPOUT_1_TPOUT1_MASK                        0xffff
#define SGMII1_DIGITAL3_TPOUT_1_TPOUT1_ALIGN                       0
#define SGMII1_DIGITAL3_TPOUT_1_TPOUT1_BITS                        16
#define SGMII1_DIGITAL3_TPOUT_1_TPOUT1_SHIFT                       0


/****************************************************************************
 * SGMII1_Digital3 :: TPOUT_2
 ***************************************************************************/
/* SGMII1_Digital3 :: TPOUT_2 :: tpout2 [15:00] */
#define Wr_SGMII1_Digital3_TPOUT_2_tpout2(x) WriteReg16(SGMII1_DIGITAL3_TPOUT_2,x)
#define Rd_SGMII1_Digital3_TPOUT_2_tpout2(x) ReadReg16(SGMII1_DIGITAL3_TPOUT_2)
#define SGMII1_DIGITAL3_TPOUT_2_TPOUT2_MASK                        0xffff
#define SGMII1_DIGITAL3_TPOUT_2_TPOUT2_ALIGN                       0
#define SGMII1_DIGITAL3_TPOUT_2_TPOUT2_BITS                        16
#define SGMII1_DIGITAL3_TPOUT_2_TPOUT2_SHIFT                       0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_Digital4
 ***************************************************************************/
/****************************************************************************
 * SGMII1_Digital4 :: Misc3
 ***************************************************************************/
/* SGMII1_Digital4 :: Misc3 :: reserved0 [15:10] */
#define SGMII1_DIGITAL4_MISC3_RESERVED0_MASK                       0xfc00
#define SGMII1_DIGITAL4_MISC3_RESERVED0_ALIGN                      0
#define SGMII1_DIGITAL4_MISC3_RESERVED0_BITS                       6
#define SGMII1_DIGITAL4_MISC3_RESERVED0_SHIFT                      10

/* SGMII1_Digital4 :: Misc3 :: fifo_ipg_cya [09:09] */
#define Wr_SGMII1_Digital4_Misc3_fifo_ipg_cya(x) WriteRegBits16(SGMII1_DIGITAL4_MISC3,0x200,9,x)
#define Rd_SGMII1_Digital4_Misc3_fifo_ipg_cya(x) ReadRegBits16(SGMII1_DIGITAL4_MISC3,0x200,9)
#define SGMII1_DIGITAL4_MISC3_FIFO_IPG_CYA_MASK                    0x0200
#define SGMII1_DIGITAL4_MISC3_FIFO_IPG_CYA_ALIGN                   0
#define SGMII1_DIGITAL4_MISC3_FIFO_IPG_CYA_BITS                    1
#define SGMII1_DIGITAL4_MISC3_FIFO_IPG_CYA_SHIFT                   9

/* SGMII1_Digital4 :: Misc3 :: reserved1 [08:07] */
#define SGMII1_DIGITAL4_MISC3_RESERVED1_MASK                       0x0180
#define SGMII1_DIGITAL4_MISC3_RESERVED1_ALIGN                      0
#define SGMII1_DIGITAL4_MISC3_RESERVED1_BITS                       2
#define SGMII1_DIGITAL4_MISC3_RESERVED1_SHIFT                      7

/* SGMII1_Digital4 :: Misc3 :: laneDisable [06:06] */
#define Wr_SGMII1_Digital4_Misc3_laneDisable(x) WriteRegBits16(SGMII1_DIGITAL4_MISC3,0x40,6,x)
#define Rd_SGMII1_Digital4_Misc3_laneDisable(x) ReadRegBits16(SGMII1_DIGITAL4_MISC3,0x40,6)
#define SGMII1_DIGITAL4_MISC3_LANEDISABLE_MASK                     0x0040
#define SGMII1_DIGITAL4_MISC3_LANEDISABLE_ALIGN                    0
#define SGMII1_DIGITAL4_MISC3_LANEDISABLE_BITS                     1
#define SGMII1_DIGITAL4_MISC3_LANEDISABLE_SHIFT                    6

/* SGMII1_Digital4 :: Misc3 :: reserved2 [05:00] */
#define SGMII1_DIGITAL4_MISC3_RESERVED2_MASK                       0x003f
#define SGMII1_DIGITAL4_MISC3_RESERVED2_ALIGN                      0
#define SGMII1_DIGITAL4_MISC3_RESERVED2_BITS                       6
#define SGMII1_DIGITAL4_MISC3_RESERVED2_SHIFT                      0


/****************************************************************************
 * SGMII1_Digital4 :: Misc5
 ***************************************************************************/
/* SGMII1_Digital4 :: Misc5 :: LPI_en_rx [15:15] */
#define Wr_SGMII1_Digital4_Misc5_LPI_en_rx(x) WriteRegBits16(SGMII1_DIGITAL4_MISC5,0x8000,15,x)
#define Rd_SGMII1_Digital4_Misc5_LPI_en_rx(x) ReadRegBits16(SGMII1_DIGITAL4_MISC5,0x8000,15)
#define SGMII1_DIGITAL4_MISC5_LPI_EN_RX_MASK                       0x8000
#define SGMII1_DIGITAL4_MISC5_LPI_EN_RX_ALIGN                      0
#define SGMII1_DIGITAL4_MISC5_LPI_EN_RX_BITS                       1
#define SGMII1_DIGITAL4_MISC5_LPI_EN_RX_SHIFT                      15

/* SGMII1_Digital4 :: Misc5 :: LPI_en_tx [14:14] */
#define Wr_SGMII1_Digital4_Misc5_LPI_en_tx(x) WriteRegBits16(SGMII1_DIGITAL4_MISC5,0x4000,14,x)
#define Rd_SGMII1_Digital4_Misc5_LPI_en_tx(x) ReadRegBits16(SGMII1_DIGITAL4_MISC5,0x4000,14)
#define SGMII1_DIGITAL4_MISC5_LPI_EN_TX_MASK                       0x4000
#define SGMII1_DIGITAL4_MISC5_LPI_EN_TX_ALIGN                      0
#define SGMII1_DIGITAL4_MISC5_LPI_EN_TX_BITS                       1
#define SGMII1_DIGITAL4_MISC5_LPI_EN_TX_SHIFT                      14

/* SGMII1_Digital4 :: Misc5 :: reserved0 [13:00] */
#define SGMII1_DIGITAL4_MISC5_RESERVED0_MASK                       0x3fff
#define SGMII1_DIGITAL4_MISC5_RESERVED0_ALIGN                      0
#define SGMII1_DIGITAL4_MISC5_RESERVED0_BITS                       14
#define SGMII1_DIGITAL4_MISC5_RESERVED0_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_FX100
 ***************************************************************************/
/****************************************************************************
 * SGMII1_FX100 :: Control1
 ***************************************************************************/
/* SGMII1_FX100 :: Control1 :: data_sampler_en [15:15] */
#define Wr_SGMII1_FX100_Control1_data_sampler_en(x) WriteRegBits16(SGMII1_FX100_CONTROL1,0x8000,15,x)
#define Rd_SGMII1_FX100_Control1_data_sampler_en(x) ReadRegBits16(SGMII1_FX100_CONTROL1,0x8000,15)
#define SGMII1_FX100_CONTROL1_DATA_SAMPLER_EN_MASK                 0x8000
#define SGMII1_FX100_CONTROL1_DATA_SAMPLER_EN_ALIGN                0
#define SGMII1_FX100_CONTROL1_DATA_SAMPLER_EN_BITS                 1
#define SGMII1_FX100_CONTROL1_DATA_SAMPLER_EN_SHIFT                15

/* SGMII1_FX100 :: Control1 :: reserved0 [14:10] */
#define SGMII1_FX100_CONTROL1_RESERVED0_MASK                       0x7c00
#define SGMII1_FX100_CONTROL1_RESERVED0_ALIGN                      0
#define SGMII1_FX100_CONTROL1_RESERVED0_BITS                       5
#define SGMII1_FX100_CONTROL1_RESERVED0_SHIFT                      10

/* SGMII1_FX100 :: Control1 :: rxdata_sel [09:06] */
#define Wr_SGMII1_FX100_Control1_rxdata_sel(x) WriteRegBits16(SGMII1_FX100_CONTROL1,0x3c0,6,x)
#define Rd_SGMII1_FX100_Control1_rxdata_sel(x) ReadRegBits16(SGMII1_FX100_CONTROL1,0x3c0,6)
#define SGMII1_FX100_CONTROL1_RXDATA_SEL_MASK                      0x03c0
#define SGMII1_FX100_CONTROL1_RXDATA_SEL_ALIGN                     0
#define SGMII1_FX100_CONTROL1_RXDATA_SEL_BITS                      4
#define SGMII1_FX100_CONTROL1_RXDATA_SEL_SHIFT                     6

/* SGMII1_FX100 :: Control1 :: disable_rx_qual [05:05] */
#define Wr_SGMII1_FX100_Control1_disable_rx_qual(x) WriteRegBits16(SGMII1_FX100_CONTROL1,0x20,5,x)
#define Rd_SGMII1_FX100_Control1_disable_rx_qual(x) ReadRegBits16(SGMII1_FX100_CONTROL1,0x20,5)
#define SGMII1_FX100_CONTROL1_DISABLE_RX_QUAL_MASK                 0x0020
#define SGMII1_FX100_CONTROL1_DISABLE_RX_QUAL_ALIGN                0
#define SGMII1_FX100_CONTROL1_DISABLE_RX_QUAL_BITS                 1
#define SGMII1_FX100_CONTROL1_DISABLE_RX_QUAL_SHIFT                5

/* SGMII1_FX100 :: Control1 :: force_rx_qual [04:04] */
#define Wr_SGMII1_FX100_Control1_force_rx_qual(x) WriteRegBits16(SGMII1_FX100_CONTROL1,0x10,4,x)
#define Rd_SGMII1_FX100_Control1_force_rx_qual(x) ReadRegBits16(SGMII1_FX100_CONTROL1,0x10,4)
#define SGMII1_FX100_CONTROL1_FORCE_RX_QUAL_MASK                   0x0010
#define SGMII1_FX100_CONTROL1_FORCE_RX_QUAL_ALIGN                  0
#define SGMII1_FX100_CONTROL1_FORCE_RX_QUAL_BITS                   1
#define SGMII1_FX100_CONTROL1_FORCE_RX_QUAL_SHIFT                  4

/* SGMII1_FX100 :: Control1 :: far_end_fault_en [03:03] */
#define Wr_SGMII1_FX100_Control1_far_end_fault_en(x) WriteRegBits16(SGMII1_FX100_CONTROL1,0x8,3,x)
#define Rd_SGMII1_FX100_Control1_far_end_fault_en(x) ReadRegBits16(SGMII1_FX100_CONTROL1,0x8,3)
#define SGMII1_FX100_CONTROL1_FAR_END_FAULT_EN_MASK                0x0008
#define SGMII1_FX100_CONTROL1_FAR_END_FAULT_EN_ALIGN               0
#define SGMII1_FX100_CONTROL1_FAR_END_FAULT_EN_BITS                1
#define SGMII1_FX100_CONTROL1_FAR_END_FAULT_EN_SHIFT               3

/* SGMII1_FX100 :: Control1 :: auto_detect_fx_mode [02:02] */
#define Wr_SGMII1_FX100_Control1_auto_detect_fx_mode(x) WriteRegBits16(SGMII1_FX100_CONTROL1,0x4,2,x)
#define Rd_SGMII1_FX100_Control1_auto_detect_fx_mode(x) ReadRegBits16(SGMII1_FX100_CONTROL1,0x4,2)
#define SGMII1_FX100_CONTROL1_AUTO_DETECT_FX_MODE_MASK             0x0004
#define SGMII1_FX100_CONTROL1_AUTO_DETECT_FX_MODE_ALIGN            0
#define SGMII1_FX100_CONTROL1_AUTO_DETECT_FX_MODE_BITS             1
#define SGMII1_FX100_CONTROL1_AUTO_DETECT_FX_MODE_SHIFT            2

/* SGMII1_FX100 :: Control1 :: full_duplex [01:01] */
#define Wr_SGMII1_FX100_Control1_full_duplex(x) WriteRegBits16(SGMII1_FX100_CONTROL1,0x2,1,x)
#define Rd_SGMII1_FX100_Control1_full_duplex(x) ReadRegBits16(SGMII1_FX100_CONTROL1,0x2,1)
#define SGMII1_FX100_CONTROL1_FULL_DUPLEX_MASK                     0x0002
#define SGMII1_FX100_CONTROL1_FULL_DUPLEX_ALIGN                    0
#define SGMII1_FX100_CONTROL1_FULL_DUPLEX_BITS                     1
#define SGMII1_FX100_CONTROL1_FULL_DUPLEX_SHIFT                    1

/* SGMII1_FX100 :: Control1 :: enable [00:00] */
#define Wr_SGMII1_FX100_Control1_enable(x) WriteRegBits16(SGMII1_FX100_CONTROL1,0x1,0,x)
#define Rd_SGMII1_FX100_Control1_enable(x) ReadRegBits16(SGMII1_FX100_CONTROL1,0x1,0)
#define SGMII1_FX100_CONTROL1_ENABLE_MASK                          0x0001
#define SGMII1_FX100_CONTROL1_ENABLE_ALIGN                         0
#define SGMII1_FX100_CONTROL1_ENABLE_BITS                          1
#define SGMII1_FX100_CONTROL1_ENABLE_SHIFT                         0


/****************************************************************************
 * SGMII1_FX100 :: Control2
 ***************************************************************************/
/* SGMII1_FX100 :: Control2 :: reserved0 [15:12] */
#define SGMII1_FX100_CONTROL2_RESERVED0_MASK                       0xf000
#define SGMII1_FX100_CONTROL2_RESERVED0_ALIGN                      0
#define SGMII1_FX100_CONTROL2_RESERVED0_BITS                       4
#define SGMII1_FX100_CONTROL2_RESERVED0_SHIFT                      12

/* SGMII1_FX100 :: Control2 :: ping_pong_disable [11:11] */
#define Wr_SGMII1_FX100_Control2_ping_pong_disable(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x800,11,x)
#define Rd_SGMII1_FX100_Control2_ping_pong_disable(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x800,11)
#define SGMII1_FX100_CONTROL2_PING_PONG_DISABLE_MASK               0x0800
#define SGMII1_FX100_CONTROL2_PING_PONG_DISABLE_ALIGN              0
#define SGMII1_FX100_CONTROL2_PING_PONG_DISABLE_BITS               1
#define SGMII1_FX100_CONTROL2_PING_PONG_DISABLE_SHIFT              11

/* SGMII1_FX100 :: Control2 :: pll_clk125_sw_ref [10:10] */
#define Wr_SGMII1_FX100_Control2_pll_clk125_sw_ref(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x400,10,x)
#define Rd_SGMII1_FX100_Control2_pll_clk125_sw_ref(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x400,10)
#define SGMII1_FX100_CONTROL2_PLL_CLK125_SW_REF_MASK               0x0400
#define SGMII1_FX100_CONTROL2_PLL_CLK125_SW_REF_ALIGN              0
#define SGMII1_FX100_CONTROL2_PLL_CLK125_SW_REF_BITS               1
#define SGMII1_FX100_CONTROL2_PLL_CLK125_SW_REF_SHIFT              10

/* SGMII1_FX100 :: Control2 :: pll_clk125_sw_en [09:09] */
#define Wr_SGMII1_FX100_Control2_pll_clk125_sw_en(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x200,9,x)
#define Rd_SGMII1_FX100_Control2_pll_clk125_sw_en(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x200,9)
#define SGMII1_FX100_CONTROL2_PLL_CLK125_SW_EN_MASK                0x0200
#define SGMII1_FX100_CONTROL2_PLL_CLK125_SW_EN_ALIGN               0
#define SGMII1_FX100_CONTROL2_PLL_CLK125_SW_EN_BITS                1
#define SGMII1_FX100_CONTROL2_PLL_CLK125_SW_EN_SHIFT               9

/* SGMII1_FX100 :: Control2 :: clk_out_1000_sw_def [08:08] */
#define Wr_SGMII1_FX100_Control2_clk_out_1000_sw_def(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x100,8,x)
#define Rd_SGMII1_FX100_Control2_clk_out_1000_sw_def(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x100,8)
#define SGMII1_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_MASK             0x0100
#define SGMII1_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_ALIGN            0
#define SGMII1_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_BITS             1
#define SGMII1_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_SHIFT            8

/* SGMII1_FX100 :: Control2 :: clk_out_1000_sw_en [07:07] */
#define Wr_SGMII1_FX100_Control2_clk_out_1000_sw_en(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x80,7,x)
#define Rd_SGMII1_FX100_Control2_clk_out_1000_sw_en(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x80,7)
#define SGMII1_FX100_CONTROL2_CLK_OUT_1000_SW_EN_MASK              0x0080
#define SGMII1_FX100_CONTROL2_CLK_OUT_1000_SW_EN_ALIGN             0
#define SGMII1_FX100_CONTROL2_CLK_OUT_1000_SW_EN_BITS              1
#define SGMII1_FX100_CONTROL2_CLK_OUT_1000_SW_EN_SHIFT             7

/* SGMII1_FX100 :: Control2 :: mii_rxc_out_sw_ref [06:06] */
#define Wr_SGMII1_FX100_Control2_mii_rxc_out_sw_ref(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x40,6,x)
#define Rd_SGMII1_FX100_Control2_mii_rxc_out_sw_ref(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x40,6)
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SW_REF_MASK              0x0040
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SW_REF_ALIGN             0
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SW_REF_BITS              1
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SW_REF_SHIFT             6

/* SGMII1_FX100 :: Control2 :: mii_rxc_out_sw_en [05:05] */
#define Wr_SGMII1_FX100_Control2_mii_rxc_out_sw_en(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x20,5,x)
#define Rd_SGMII1_FX100_Control2_mii_rxc_out_sw_en(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x20,5)
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SW_EN_MASK               0x0020
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SW_EN_ALIGN              0
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SW_EN_BITS               1
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SW_EN_SHIFT              5

/* SGMII1_FX100 :: Control2 :: mii_rxc_out_sm_rst [04:04] */
#define Wr_SGMII1_FX100_Control2_mii_rxc_out_sm_rst(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x10,4,x)
#define Rd_SGMII1_FX100_Control2_mii_rxc_out_sm_rst(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x10,4)
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SM_RST_MASK              0x0010
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SM_RST_ALIGN             0
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SM_RST_BITS              1
#define SGMII1_FX100_CONTROL2_MII_RXC_OUT_SM_RST_SHIFT             4

/* SGMII1_FX100 :: Control2 :: mode_chg_nrst [03:03] */
#define Wr_SGMII1_FX100_Control2_mode_chg_nrst(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x8,3,x)
#define Rd_SGMII1_FX100_Control2_mode_chg_nrst(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x8,3)
#define SGMII1_FX100_CONTROL2_MODE_CHG_NRST_MASK                   0x0008
#define SGMII1_FX100_CONTROL2_MODE_CHG_NRST_ALIGN                  0
#define SGMII1_FX100_CONTROL2_MODE_CHG_NRST_BITS                   1
#define SGMII1_FX100_CONTROL2_MODE_CHG_NRST_SHIFT                  3

/* SGMII1_FX100 :: Control2 :: reset_rxfifo [02:02] */
#define Wr_SGMII1_FX100_Control2_reset_rxfifo(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x4,2,x)
#define Rd_SGMII1_FX100_Control2_reset_rxfifo(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x4,2)
#define SGMII1_FX100_CONTROL2_RESET_RXFIFO_MASK                    0x0004
#define SGMII1_FX100_CONTROL2_RESET_RXFIFO_ALIGN                   0
#define SGMII1_FX100_CONTROL2_RESET_RXFIFO_BITS                    1
#define SGMII1_FX100_CONTROL2_RESET_RXFIFO_SHIFT                   2

/* SGMII1_FX100 :: Control2 :: bypass_rxfifo [01:01] */
#define Wr_SGMII1_FX100_Control2_bypass_rxfifo(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x2,1,x)
#define Rd_SGMII1_FX100_Control2_bypass_rxfifo(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x2,1)
#define SGMII1_FX100_CONTROL2_BYPASS_RXFIFO_MASK                   0x0002
#define SGMII1_FX100_CONTROL2_BYPASS_RXFIFO_ALIGN                  0
#define SGMII1_FX100_CONTROL2_BYPASS_RXFIFO_BITS                   1
#define SGMII1_FX100_CONTROL2_BYPASS_RXFIFO_SHIFT                  1

/* SGMII1_FX100 :: Control2 :: extend_pkt_size [00:00] */
#define Wr_SGMII1_FX100_Control2_extend_pkt_size(x) WriteRegBits16(SGMII1_FX100_CONTROL2,0x1,0,x)
#define Rd_SGMII1_FX100_Control2_extend_pkt_size(x) ReadRegBits16(SGMII1_FX100_CONTROL2,0x1,0)
#define SGMII1_FX100_CONTROL2_EXTEND_PKT_SIZE_MASK                 0x0001
#define SGMII1_FX100_CONTROL2_EXTEND_PKT_SIZE_ALIGN                0
#define SGMII1_FX100_CONTROL2_EXTEND_PKT_SIZE_BITS                 1
#define SGMII1_FX100_CONTROL2_EXTEND_PKT_SIZE_SHIFT                0


/****************************************************************************
 * SGMII1_FX100 :: Control3
 ***************************************************************************/
/* SGMII1_FX100 :: Control3 :: number_of_idle [15:08] */
#define Wr_SGMII1_FX100_Control3_number_of_idle(x) WriteRegBits16(SGMII1_FX100_CONTROL3,0xff00,8,x)
#define Rd_SGMII1_FX100_Control3_number_of_idle(x) ReadRegBits16(SGMII1_FX100_CONTROL3,0xff00,8)
#define SGMII1_FX100_CONTROL3_NUMBER_OF_IDLE_MASK                  0xff00
#define SGMII1_FX100_CONTROL3_NUMBER_OF_IDLE_ALIGN                 0
#define SGMII1_FX100_CONTROL3_NUMBER_OF_IDLE_BITS                  8
#define SGMII1_FX100_CONTROL3_NUMBER_OF_IDLE_SHIFT                 8

/* SGMII1_FX100 :: Control3 :: correlator_disable [07:07] */
#define Wr_SGMII1_FX100_Control3_correlator_disable(x) WriteRegBits16(SGMII1_FX100_CONTROL3,0x80,7,x)
#define Rd_SGMII1_FX100_Control3_correlator_disable(x) ReadRegBits16(SGMII1_FX100_CONTROL3,0x80,7)
#define SGMII1_FX100_CONTROL3_CORRELATOR_DISABLE_MASK              0x0080
#define SGMII1_FX100_CONTROL3_CORRELATOR_DISABLE_ALIGN             0
#define SGMII1_FX100_CONTROL3_CORRELATOR_DISABLE_BITS              1
#define SGMII1_FX100_CONTROL3_CORRELATOR_DISABLE_SHIFT             7

/* SGMII1_FX100 :: Control3 :: bypass_nrz [06:06] */
#define Wr_SGMII1_FX100_Control3_bypass_nrz(x) WriteRegBits16(SGMII1_FX100_CONTROL3,0x40,6,x)
#define Rd_SGMII1_FX100_Control3_bypass_nrz(x) ReadRegBits16(SGMII1_FX100_CONTROL3,0x40,6)
#define SGMII1_FX100_CONTROL3_BYPASS_NRZ_MASK                      0x0040
#define SGMII1_FX100_CONTROL3_BYPASS_NRZ_ALIGN                     0
#define SGMII1_FX100_CONTROL3_BYPASS_NRZ_BITS                      1
#define SGMII1_FX100_CONTROL3_BYPASS_NRZ_SHIFT                     6

/* SGMII1_FX100 :: Control3 :: bypass_encoder [05:05] */
#define Wr_SGMII1_FX100_Control3_bypass_encoder(x) WriteRegBits16(SGMII1_FX100_CONTROL3,0x20,5,x)
#define Rd_SGMII1_FX100_Control3_bypass_encoder(x) ReadRegBits16(SGMII1_FX100_CONTROL3,0x20,5)
#define SGMII1_FX100_CONTROL3_BYPASS_ENCODER_MASK                  0x0020
#define SGMII1_FX100_CONTROL3_BYPASS_ENCODER_ALIGN                 0
#define SGMII1_FX100_CONTROL3_BYPASS_ENCODER_BITS                  1
#define SGMII1_FX100_CONTROL3_BYPASS_ENCODER_SHIFT                 5

/* SGMII1_FX100 :: Control3 :: bypass_alignment [04:04] */
#define Wr_SGMII1_FX100_Control3_bypass_alignment(x) WriteRegBits16(SGMII1_FX100_CONTROL3,0x10,4,x)
#define Rd_SGMII1_FX100_Control3_bypass_alignment(x) ReadRegBits16(SGMII1_FX100_CONTROL3,0x10,4)
#define SGMII1_FX100_CONTROL3_BYPASS_ALIGNMENT_MASK                0x0010
#define SGMII1_FX100_CONTROL3_BYPASS_ALIGNMENT_ALIGN               0
#define SGMII1_FX100_CONTROL3_BYPASS_ALIGNMENT_BITS                1
#define SGMII1_FX100_CONTROL3_BYPASS_ALIGNMENT_SHIFT               4

/* SGMII1_FX100 :: Control3 :: force_link [03:03] */
#define Wr_SGMII1_FX100_Control3_force_link(x) WriteRegBits16(SGMII1_FX100_CONTROL3,0x8,3,x)
#define Rd_SGMII1_FX100_Control3_force_link(x) ReadRegBits16(SGMII1_FX100_CONTROL3,0x8,3)
#define SGMII1_FX100_CONTROL3_FORCE_LINK_MASK                      0x0008
#define SGMII1_FX100_CONTROL3_FORCE_LINK_ALIGN                     0
#define SGMII1_FX100_CONTROL3_FORCE_LINK_BITS                      1
#define SGMII1_FX100_CONTROL3_FORCE_LINK_SHIFT                     3

/* SGMII1_FX100 :: Control3 :: force_lock [02:02] */
#define Wr_SGMII1_FX100_Control3_force_lock(x) WriteRegBits16(SGMII1_FX100_CONTROL3,0x4,2,x)
#define Rd_SGMII1_FX100_Control3_force_lock(x) ReadRegBits16(SGMII1_FX100_CONTROL3,0x4,2)
#define SGMII1_FX100_CONTROL3_FORCE_LOCK_MASK                      0x0004
#define SGMII1_FX100_CONTROL3_FORCE_LOCK_ALIGN                     0
#define SGMII1_FX100_CONTROL3_FORCE_LOCK_BITS                      1
#define SGMII1_FX100_CONTROL3_FORCE_LOCK_SHIFT                     2

/* SGMII1_FX100 :: Control3 :: fast_unlock_timer [01:01] */
#define Wr_SGMII1_FX100_Control3_fast_unlock_timer(x) WriteRegBits16(SGMII1_FX100_CONTROL3,0x2,1,x)
#define Rd_SGMII1_FX100_Control3_fast_unlock_timer(x) ReadRegBits16(SGMII1_FX100_CONTROL3,0x2,1)
#define SGMII1_FX100_CONTROL3_FAST_UNLOCK_TIMER_MASK               0x0002
#define SGMII1_FX100_CONTROL3_FAST_UNLOCK_TIMER_ALIGN              0
#define SGMII1_FX100_CONTROL3_FAST_UNLOCK_TIMER_BITS               1
#define SGMII1_FX100_CONTROL3_FAST_UNLOCK_TIMER_SHIFT              1

/* SGMII1_FX100 :: Control3 :: fast_timers [00:00] */
#define Wr_SGMII1_FX100_Control3_fast_timers(x) WriteRegBits16(SGMII1_FX100_CONTROL3,0x1,0,x)
#define Rd_SGMII1_FX100_Control3_fast_timers(x) ReadRegBits16(SGMII1_FX100_CONTROL3,0x1,0)
#define SGMII1_FX100_CONTROL3_FAST_TIMERS_MASK                     0x0001
#define SGMII1_FX100_CONTROL3_FAST_TIMERS_ALIGN                    0
#define SGMII1_FX100_CONTROL3_FAST_TIMERS_BITS                     1
#define SGMII1_FX100_CONTROL3_FAST_TIMERS_SHIFT                    0


/****************************************************************************
 * SGMII1_FX100 :: Status1
 ***************************************************************************/
/* SGMII1_FX100 :: Status1 :: mode_change [15:15] */
#define Wr_SGMII1_FX100_Status1_mode_change(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x8000,15,x)
#define Rd_SGMII1_FX100_Status1_mode_change(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x8000,15)
#define SGMII1_FX100_STATUS1_MODE_CHANGE_MASK                      0x8000
#define SGMII1_FX100_STATUS1_MODE_CHANGE_ALIGN                     0
#define SGMII1_FX100_STATUS1_MODE_CHANGE_BITS                      1
#define SGMII1_FX100_STATUS1_MODE_CHANGE_SHIFT                     15

/* SGMII1_FX100 :: Status1 :: reserved0 [14:12] */
#define SGMII1_FX100_STATUS1_RESERVED0_MASK                        0x7000
#define SGMII1_FX100_STATUS1_RESERVED0_ALIGN                       0
#define SGMII1_FX100_STATUS1_RESERVED0_BITS                        3
#define SGMII1_FX100_STATUS1_RESERVED0_SHIFT                       12

/* SGMII1_FX100 :: Status1 :: fiber_pwrdwn_status_chg [11:11] */
#define Wr_SGMII1_FX100_Status1_fiber_pwrdwn_status_chg(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x800,11,x)
#define Rd_SGMII1_FX100_Status1_fiber_pwrdwn_status_chg(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x800,11)
#define SGMII1_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_MASK          0x0800
#define SGMII1_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_ALIGN         0
#define SGMII1_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_BITS          1
#define SGMII1_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_SHIFT         11

/* SGMII1_FX100 :: Status1 :: fiber_pwrdwn [10:10] */
#define Wr_SGMII1_FX100_Status1_fiber_pwrdwn(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x400,10,x)
#define Rd_SGMII1_FX100_Status1_fiber_pwrdwn(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x400,10)
#define SGMII1_FX100_STATUS1_FIBER_PWRDWN_MASK                     0x0400
#define SGMII1_FX100_STATUS1_FIBER_PWRDWN_ALIGN                    0
#define SGMII1_FX100_STATUS1_FIBER_PWRDWN_BITS                     1
#define SGMII1_FX100_STATUS1_FIBER_PWRDWN_SHIFT                    10

/* SGMII1_FX100 :: Status1 :: link_status_chg [09:09] */
#define Wr_SGMII1_FX100_Status1_link_status_chg(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x200,9,x)
#define Rd_SGMII1_FX100_Status1_link_status_chg(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x200,9)
#define SGMII1_FX100_STATUS1_LINK_STATUS_CHG_MASK                  0x0200
#define SGMII1_FX100_STATUS1_LINK_STATUS_CHG_ALIGN                 0
#define SGMII1_FX100_STATUS1_LINK_STATUS_CHG_BITS                  1
#define SGMII1_FX100_STATUS1_LINK_STATUS_CHG_SHIFT                 9

/* SGMII1_FX100 :: Status1 :: bad_esd_detected [08:08] */
#define Wr_SGMII1_FX100_Status1_bad_esd_detected(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x100,8,x)
#define Rd_SGMII1_FX100_Status1_bad_esd_detected(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x100,8)
#define SGMII1_FX100_STATUS1_BAD_ESD_DETECTED_MASK                 0x0100
#define SGMII1_FX100_STATUS1_BAD_ESD_DETECTED_ALIGN                0
#define SGMII1_FX100_STATUS1_BAD_ESD_DETECTED_BITS                 1
#define SGMII1_FX100_STATUS1_BAD_ESD_DETECTED_SHIFT                8

/* SGMII1_FX100 :: Status1 :: false_carrier_detected [07:07] */
#define Wr_SGMII1_FX100_Status1_false_carrier_detected(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x80,7,x)
#define Rd_SGMII1_FX100_Status1_false_carrier_detected(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x80,7)
#define SGMII1_FX100_STATUS1_FALSE_CARRIER_DETECTED_MASK           0x0080
#define SGMII1_FX100_STATUS1_FALSE_CARRIER_DETECTED_ALIGN          0
#define SGMII1_FX100_STATUS1_FALSE_CARRIER_DETECTED_BITS           1
#define SGMII1_FX100_STATUS1_FALSE_CARRIER_DETECTED_SHIFT          7

/* SGMII1_FX100 :: Status1 :: tx_err_detected [06:06] */
#define Wr_SGMII1_FX100_Status1_tx_err_detected(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x40,6,x)
#define Rd_SGMII1_FX100_Status1_tx_err_detected(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x40,6)
#define SGMII1_FX100_STATUS1_TX_ERR_DETECTED_MASK                  0x0040
#define SGMII1_FX100_STATUS1_TX_ERR_DETECTED_ALIGN                 0
#define SGMII1_FX100_STATUS1_TX_ERR_DETECTED_BITS                  1
#define SGMII1_FX100_STATUS1_TX_ERR_DETECTED_SHIFT                 6

/* SGMII1_FX100 :: Status1 :: rx_err_detected [05:05] */
#define Wr_SGMII1_FX100_Status1_rx_err_detected(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x20,5,x)
#define Rd_SGMII1_FX100_Status1_rx_err_detected(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x20,5)
#define SGMII1_FX100_STATUS1_RX_ERR_DETECTED_MASK                  0x0020
#define SGMII1_FX100_STATUS1_RX_ERR_DETECTED_ALIGN                 0
#define SGMII1_FX100_STATUS1_RX_ERR_DETECTED_BITS                  1
#define SGMII1_FX100_STATUS1_RX_ERR_DETECTED_SHIFT                 5

/* SGMII1_FX100 :: Status1 :: lock_timer_expired [04:04] */
#define Wr_SGMII1_FX100_Status1_lock_timer_expired(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x10,4,x)
#define Rd_SGMII1_FX100_Status1_lock_timer_expired(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x10,4)
#define SGMII1_FX100_STATUS1_LOCK_TIMER_EXPIRED_MASK               0x0010
#define SGMII1_FX100_STATUS1_LOCK_TIMER_EXPIRED_ALIGN              0
#define SGMII1_FX100_STATUS1_LOCK_TIMER_EXPIRED_BITS               1
#define SGMII1_FX100_STATUS1_LOCK_TIMER_EXPIRED_SHIFT              4

/* SGMII1_FX100 :: Status1 :: lost_lock [03:03] */
#define Wr_SGMII1_FX100_Status1_lost_lock(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x8,3,x)
#define Rd_SGMII1_FX100_Status1_lost_lock(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x8,3)
#define SGMII1_FX100_STATUS1_LOST_LOCK_MASK                        0x0008
#define SGMII1_FX100_STATUS1_LOST_LOCK_ALIGN                       0
#define SGMII1_FX100_STATUS1_LOST_LOCK_BITS                        1
#define SGMII1_FX100_STATUS1_LOST_LOCK_SHIFT                       3

/* SGMII1_FX100 :: Status1 :: faulting [02:02] */
#define Wr_SGMII1_FX100_Status1_faulting(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x4,2,x)
#define Rd_SGMII1_FX100_Status1_faulting(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x4,2)
#define SGMII1_FX100_STATUS1_FAULTING_MASK                         0x0004
#define SGMII1_FX100_STATUS1_FAULTING_ALIGN                        0
#define SGMII1_FX100_STATUS1_FAULTING_BITS                         1
#define SGMII1_FX100_STATUS1_FAULTING_SHIFT                        2

/* SGMII1_FX100 :: Status1 :: locked [01:01] */
#define Wr_SGMII1_FX100_Status1_locked(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x2,1,x)
#define Rd_SGMII1_FX100_Status1_locked(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x2,1)
#define SGMII1_FX100_STATUS1_LOCKED_MASK                           0x0002
#define SGMII1_FX100_STATUS1_LOCKED_ALIGN                          0
#define SGMII1_FX100_STATUS1_LOCKED_BITS                           1
#define SGMII1_FX100_STATUS1_LOCKED_SHIFT                          1

/* SGMII1_FX100 :: Status1 :: link [00:00] */
#define Wr_SGMII1_FX100_Status1_link(x) WriteRegBits16(SGMII1_FX100_STATUS1,0x1,0,x)
#define Rd_SGMII1_FX100_Status1_link(x) ReadRegBits16(SGMII1_FX100_STATUS1,0x1,0)
#define SGMII1_FX100_STATUS1_LINK_MASK                             0x0001
#define SGMII1_FX100_STATUS1_LINK_ALIGN                            0
#define SGMII1_FX100_STATUS1_LINK_BITS                             1
#define SGMII1_FX100_STATUS1_LINK_SHIFT                            0


/****************************************************************************
 * SGMII1_FX100 :: Status3
 ***************************************************************************/
/* SGMII1_FX100 :: Status3 :: linkmon_cntr [15:08] */
#define Wr_SGMII1_FX100_Status3_linkmon_cntr(x) WriteRegBits16(SGMII1_FX100_STATUS3,0xff00,8,x)
#define Rd_SGMII1_FX100_Status3_linkmon_cntr(x) ReadRegBits16(SGMII1_FX100_STATUS3,0xff00,8)
#define SGMII1_FX100_STATUS3_LINKMON_CNTR_MASK                     0xff00
#define SGMII1_FX100_STATUS3_LINKMON_CNTR_ALIGN                    0
#define SGMII1_FX100_STATUS3_LINKMON_CNTR_BITS                     8
#define SGMII1_FX100_STATUS3_LINKMON_CNTR_SHIFT                    8

/* SGMII1_FX100 :: Status3 :: reserved0 [07:07] */
#define SGMII1_FX100_STATUS3_RESERVED0_MASK                        0x0080
#define SGMII1_FX100_STATUS3_RESERVED0_ALIGN                       0
#define SGMII1_FX100_STATUS3_RESERVED0_BITS                        1
#define SGMII1_FX100_STATUS3_RESERVED0_SHIFT                       7

/* SGMII1_FX100 :: Status3 :: idles_detected_5b [06:06] */
#define Wr_SGMII1_FX100_Status3_idles_detected_5b(x) WriteRegBits16(SGMII1_FX100_STATUS3,0x40,6,x)
#define Rd_SGMII1_FX100_Status3_idles_detected_5b(x) ReadRegBits16(SGMII1_FX100_STATUS3,0x40,6)
#define SGMII1_FX100_STATUS3_IDLES_DETECTED_5B_MASK                0x0040
#define SGMII1_FX100_STATUS3_IDLES_DETECTED_5B_ALIGN               0
#define SGMII1_FX100_STATUS3_IDLES_DETECTED_5B_BITS                1
#define SGMII1_FX100_STATUS3_IDLES_DETECTED_5B_SHIFT               6

/* SGMII1_FX100 :: Status3 :: crs_ind_detected [05:05] */
#define Wr_SGMII1_FX100_Status3_crs_ind_detected(x) WriteRegBits16(SGMII1_FX100_STATUS3,0x20,5,x)
#define Rd_SGMII1_FX100_Status3_crs_ind_detected(x) ReadRegBits16(SGMII1_FX100_STATUS3,0x20,5)
#define SGMII1_FX100_STATUS3_CRS_IND_DETECTED_MASK                 0x0020
#define SGMII1_FX100_STATUS3_CRS_IND_DETECTED_ALIGN                0
#define SGMII1_FX100_STATUS3_CRS_IND_DETECTED_BITS                 1
#define SGMII1_FX100_STATUS3_CRS_IND_DETECTED_SHIFT                5

/* SGMII1_FX100 :: Status3 :: err_detected [04:04] */
#define Wr_SGMII1_FX100_Status3_err_detected(x) WriteRegBits16(SGMII1_FX100_STATUS3,0x10,4,x)
#define Rd_SGMII1_FX100_Status3_err_detected(x) ReadRegBits16(SGMII1_FX100_STATUS3,0x10,4)
#define SGMII1_FX100_STATUS3_ERR_DETECTED_MASK                     0x0010
#define SGMII1_FX100_STATUS3_ERR_DETECTED_ALIGN                    0
#define SGMII1_FX100_STATUS3_ERR_DETECTED_BITS                     1
#define SGMII1_FX100_STATUS3_ERR_DETECTED_SHIFT                    4

/* SGMII1_FX100 :: Status3 :: esd_detected [03:03] */
#define Wr_SGMII1_FX100_Status3_esd_detected(x) WriteRegBits16(SGMII1_FX100_STATUS3,0x8,3,x)
#define Rd_SGMII1_FX100_Status3_esd_detected(x) ReadRegBits16(SGMII1_FX100_STATUS3,0x8,3)
#define SGMII1_FX100_STATUS3_ESD_DETECTED_MASK                     0x0008
#define SGMII1_FX100_STATUS3_ESD_DETECTED_ALIGN                    0
#define SGMII1_FX100_STATUS3_ESD_DETECTED_BITS                     1
#define SGMII1_FX100_STATUS3_ESD_DETECTED_SHIFT                    3

/* SGMII1_FX100 :: Status3 :: ssd_detected [02:02] */
#define Wr_SGMII1_FX100_Status3_ssd_detected(x) WriteRegBits16(SGMII1_FX100_STATUS3,0x4,2,x)
#define Rd_SGMII1_FX100_Status3_ssd_detected(x) ReadRegBits16(SGMII1_FX100_STATUS3,0x4,2)
#define SGMII1_FX100_STATUS3_SSD_DETECTED_MASK                     0x0004
#define SGMII1_FX100_STATUS3_SSD_DETECTED_ALIGN                    0
#define SGMII1_FX100_STATUS3_SSD_DETECTED_BITS                     1
#define SGMII1_FX100_STATUS3_SSD_DETECTED_SHIFT                    2

/* SGMII1_FX100 :: Status3 :: ij_detected [01:01] */
#define Wr_SGMII1_FX100_Status3_ij_detected(x) WriteRegBits16(SGMII1_FX100_STATUS3,0x2,1,x)
#define Rd_SGMII1_FX100_Status3_ij_detected(x) ReadRegBits16(SGMII1_FX100_STATUS3,0x2,1)
#define SGMII1_FX100_STATUS3_IJ_DETECTED_MASK                      0x0002
#define SGMII1_FX100_STATUS3_IJ_DETECTED_ALIGN                     0
#define SGMII1_FX100_STATUS3_IJ_DETECTED_BITS                      1
#define SGMII1_FX100_STATUS3_IJ_DETECTED_SHIFT                     1

/* SGMII1_FX100 :: Status3 :: idles_detected [00:00] */
#define Wr_SGMII1_FX100_Status3_idles_detected(x) WriteRegBits16(SGMII1_FX100_STATUS3,0x1,0,x)
#define Rd_SGMII1_FX100_Status3_idles_detected(x) ReadRegBits16(SGMII1_FX100_STATUS3,0x1,0)
#define SGMII1_FX100_STATUS3_IDLES_DETECTED_MASK                   0x0001
#define SGMII1_FX100_STATUS3_IDLES_DETECTED_ALIGN                  0
#define SGMII1_FX100_STATUS3_IDLES_DETECTED_BITS                   1
#define SGMII1_FX100_STATUS3_IDLES_DETECTED_SHIFT                  0


/****************************************************************************
 * SGMII1_FX100 :: Status4
 ***************************************************************************/
/* SGMII1_FX100 :: Status4 :: reserved0 [15:15] */
#define SGMII1_FX100_STATUS4_RESERVED0_MASK                        0x8000
#define SGMII1_FX100_STATUS4_RESERVED0_ALIGN                       0
#define SGMII1_FX100_STATUS4_RESERVED0_BITS                        1
#define SGMII1_FX100_STATUS4_RESERVED0_SHIFT                       15

/* SGMII1_FX100 :: Status4 :: rx_badend [14:14] */
#define Wr_SGMII1_FX100_Status4_rx_badend(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x4000,14,x)
#define Rd_SGMII1_FX100_Status4_rx_badend(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x4000,14)
#define SGMII1_FX100_STATUS4_RX_BADEND_MASK                        0x4000
#define SGMII1_FX100_STATUS4_RX_BADEND_ALIGN                       0
#define SGMII1_FX100_STATUS4_RX_BADEND_BITS                        1
#define SGMII1_FX100_STATUS4_RX_BADEND_SHIFT                       14

/* SGMII1_FX100 :: Status4 :: rx_data [13:13] */
#define Wr_SGMII1_FX100_Status4_rx_data(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x2000,13,x)
#define Rd_SGMII1_FX100_Status4_rx_data(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x2000,13)
#define SGMII1_FX100_STATUS4_RX_DATA_MASK                          0x2000
#define SGMII1_FX100_STATUS4_RX_DATA_ALIGN                         0
#define SGMII1_FX100_STATUS4_RX_DATA_BITS                          1
#define SGMII1_FX100_STATUS4_RX_DATA_SHIFT                         13

/* SGMII1_FX100 :: Status4 :: rx_ssk [12:12] */
#define Wr_SGMII1_FX100_Status4_rx_ssk(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x1000,12,x)
#define Rd_SGMII1_FX100_Status4_rx_ssk(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x1000,12)
#define SGMII1_FX100_STATUS4_RX_SSK_MASK                           0x1000
#define SGMII1_FX100_STATUS4_RX_SSK_ALIGN                          0
#define SGMII1_FX100_STATUS4_RX_SSK_BITS                           1
#define SGMII1_FX100_STATUS4_RX_SSK_SHIFT                          12

/* SGMII1_FX100 :: Status4 :: rx_ssj [11:11] */
#define Wr_SGMII1_FX100_Status4_rx_ssj(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x800,11,x)
#define Rd_SGMII1_FX100_Status4_rx_ssj(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x800,11)
#define SGMII1_FX100_STATUS4_RX_SSJ_MASK                           0x0800
#define SGMII1_FX100_STATUS4_RX_SSJ_ALIGN                          0
#define SGMII1_FX100_STATUS4_RX_SSJ_BITS                           1
#define SGMII1_FX100_STATUS4_RX_SSJ_SHIFT                          11

/* SGMII1_FX100 :: Status4 :: rx_confirmk [10:10] */
#define Wr_SGMII1_FX100_Status4_rx_confirmk(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x400,10,x)
#define Rd_SGMII1_FX100_Status4_rx_confirmk(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x400,10)
#define SGMII1_FX100_STATUS4_RX_CONFIRMK_MASK                      0x0400
#define SGMII1_FX100_STATUS4_RX_CONFIRMK_ALIGN                     0
#define SGMII1_FX100_STATUS4_RX_CONFIRMK_BITS                      1
#define SGMII1_FX100_STATUS4_RX_CONFIRMK_SHIFT                     10

/* SGMII1_FX100 :: Status4 :: rx_badssd [09:09] */
#define Wr_SGMII1_FX100_Status4_rx_badssd(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x200,9,x)
#define Rd_SGMII1_FX100_Status4_rx_badssd(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x200,9)
#define SGMII1_FX100_STATUS4_RX_BADSSD_MASK                        0x0200
#define SGMII1_FX100_STATUS4_RX_BADSSD_ALIGN                       0
#define SGMII1_FX100_STATUS4_RX_BADSSD_BITS                        1
#define SGMII1_FX100_STATUS4_RX_BADSSD_SHIFT                       9

/* SGMII1_FX100 :: Status4 :: fx_linkfail [08:08] */
#define Wr_SGMII1_FX100_Status4_fx_linkfail(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x100,8,x)
#define Rd_SGMII1_FX100_Status4_fx_linkfail(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x100,8)
#define SGMII1_FX100_STATUS4_FX_LINKFAIL_MASK                      0x0100
#define SGMII1_FX100_STATUS4_FX_LINKFAIL_ALIGN                     0
#define SGMII1_FX100_STATUS4_FX_LINKFAIL_BITS                      1
#define SGMII1_FX100_STATUS4_FX_LINKFAIL_SHIFT                     8

/* SGMII1_FX100 :: Status4 :: tx_esr [07:07] */
#define Wr_SGMII1_FX100_Status4_tx_esr(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x80,7,x)
#define Rd_SGMII1_FX100_Status4_tx_esr(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x80,7)
#define SGMII1_FX100_STATUS4_TX_ESR_MASK                           0x0080
#define SGMII1_FX100_STATUS4_TX_ESR_ALIGN                          0
#define SGMII1_FX100_STATUS4_TX_ESR_BITS                           1
#define SGMII1_FX100_STATUS4_TX_ESR_SHIFT                          7

/* SGMII1_FX100 :: Status4 :: tx_est [06:06] */
#define Wr_SGMII1_FX100_Status4_tx_est(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x40,6,x)
#define Rd_SGMII1_FX100_Status4_tx_est(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x40,6)
#define SGMII1_FX100_STATUS4_TX_EST_MASK                           0x0040
#define SGMII1_FX100_STATUS4_TX_EST_ALIGN                          0
#define SGMII1_FX100_STATUS4_TX_EST_BITS                           1
#define SGMII1_FX100_STATUS4_TX_EST_SHIFT                          6

/* SGMII1_FX100 :: Status4 :: tx_terror [05:05] */
#define Wr_SGMII1_FX100_Status4_tx_terror(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x20,5,x)
#define Rd_SGMII1_FX100_Status4_tx_terror(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x20,5)
#define SGMII1_FX100_STATUS4_TX_TERROR_MASK                        0x0020
#define SGMII1_FX100_STATUS4_TX_TERROR_ALIGN                       0
#define SGMII1_FX100_STATUS4_TX_TERROR_BITS                        1
#define SGMII1_FX100_STATUS4_TX_TERROR_SHIFT                       5

/* SGMII1_FX100 :: Status4 :: tx_tdata [04:04] */
#define Wr_SGMII1_FX100_Status4_tx_tdata(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x10,4,x)
#define Rd_SGMII1_FX100_Status4_tx_tdata(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x10,4)
#define SGMII1_FX100_STATUS4_TX_TDATA_MASK                         0x0010
#define SGMII1_FX100_STATUS4_TX_TDATA_ALIGN                        0
#define SGMII1_FX100_STATUS4_TX_TDATA_BITS                         1
#define SGMII1_FX100_STATUS4_TX_TDATA_SHIFT                        4

/* SGMII1_FX100 :: Status4 :: tx_ssk [03:03] */
#define Wr_SGMII1_FX100_Status4_tx_ssk(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x8,3,x)
#define Rd_SGMII1_FX100_Status4_tx_ssk(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x8,3)
#define SGMII1_FX100_STATUS4_TX_SSK_MASK                           0x0008
#define SGMII1_FX100_STATUS4_TX_SSK_ALIGN                          0
#define SGMII1_FX100_STATUS4_TX_SSK_BITS                           1
#define SGMII1_FX100_STATUS4_TX_SSK_SHIFT                          3

/* SGMII1_FX100 :: Status4 :: tx_sek [02:02] */
#define Wr_SGMII1_FX100_Status4_tx_sek(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x4,2,x)
#define Rd_SGMII1_FX100_Status4_tx_sek(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x4,2)
#define SGMII1_FX100_STATUS4_TX_SEK_MASK                           0x0004
#define SGMII1_FX100_STATUS4_TX_SEK_ALIGN                          0
#define SGMII1_FX100_STATUS4_TX_SEK_BITS                           1
#define SGMII1_FX100_STATUS4_TX_SEK_SHIFT                          2

/* SGMII1_FX100 :: Status4 :: tx_ssj [01:01] */
#define Wr_SGMII1_FX100_Status4_tx_ssj(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x2,1,x)
#define Rd_SGMII1_FX100_Status4_tx_ssj(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x2,1)
#define SGMII1_FX100_STATUS4_TX_SSJ_MASK                           0x0002
#define SGMII1_FX100_STATUS4_TX_SSJ_ALIGN                          0
#define SGMII1_FX100_STATUS4_TX_SSJ_BITS                           1
#define SGMII1_FX100_STATUS4_TX_SSJ_SHIFT                          1

/* SGMII1_FX100 :: Status4 :: tx_sej [00:00] */
#define Wr_SGMII1_FX100_Status4_tx_sej(x) WriteRegBits16(SGMII1_FX100_STATUS4,0x1,0,x)
#define Rd_SGMII1_FX100_Status4_tx_sej(x) ReadRegBits16(SGMII1_FX100_STATUS4,0x1,0)
#define SGMII1_FX100_STATUS4_TX_SEJ_MASK                           0x0001
#define SGMII1_FX100_STATUS4_TX_SEJ_ALIGN                          0
#define SGMII1_FX100_STATUS4_TX_SEJ_BITS                           1
#define SGMII1_FX100_STATUS4_TX_SEJ_SHIFT                          0


/****************************************************************************
 * SGMII1_FX100 :: fx100Idle1
 ***************************************************************************/
/* SGMII1_FX100 :: fx100Idle1 :: reserved0 [15:10] */
#define SGMII1_FX100_FX100IDLE1_RESERVED0_MASK                     0xfc00
#define SGMII1_FX100_FX100IDLE1_RESERVED0_ALIGN                    0
#define SGMII1_FX100_FX100IDLE1_RESERVED0_BITS                     6
#define SGMII1_FX100_FX100IDLE1_RESERVED0_SHIFT                    10

/* SGMII1_FX100 :: fx100Idle1 :: fx100_idle1 [09:00] */
#define Wr_SGMII1_FX100_fx100Idle1_fx100_idle1(x) WriteRegBits16(SGMII1_FX100_FX100IDLE1,0x3ff,0,x)
#define Rd_SGMII1_FX100_fx100Idle1_fx100_idle1(x) ReadRegBits16(SGMII1_FX100_FX100IDLE1,0x3ff,0)
#define SGMII1_FX100_FX100IDLE1_FX100_IDLE1_MASK                   0x03ff
#define SGMII1_FX100_FX100IDLE1_FX100_IDLE1_ALIGN                  0
#define SGMII1_FX100_FX100IDLE1_FX100_IDLE1_BITS                   10
#define SGMII1_FX100_FX100IDLE1_FX100_IDLE1_SHIFT                  0


/****************************************************************************
 * SGMII1_FX100 :: fx100idle2
 ***************************************************************************/
/* SGMII1_FX100 :: fx100idle2 :: reserved0 [15:10] */
#define SGMII1_FX100_FX100IDLE2_RESERVED0_MASK                     0xfc00
#define SGMII1_FX100_FX100IDLE2_RESERVED0_ALIGN                    0
#define SGMII1_FX100_FX100IDLE2_RESERVED0_BITS                     6
#define SGMII1_FX100_FX100IDLE2_RESERVED0_SHIFT                    10

/* SGMII1_FX100 :: fx100idle2 :: fx100_idle2 [09:00] */
#define Wr_SGMII1_FX100_fx100idle2_fx100_idle2(x) WriteRegBits16(SGMII1_FX100_FX100IDLE2,0x3ff,0,x)
#define Rd_SGMII1_FX100_fx100idle2_fx100_idle2(x) ReadRegBits16(SGMII1_FX100_FX100IDLE2,0x3ff,0)
#define SGMII1_FX100_FX100IDLE2_FX100_IDLE2_MASK                   0x03ff
#define SGMII1_FX100_FX100IDLE2_FX100_IDLE2_ALIGN                  0
#define SGMII1_FX100_FX100IDLE2_FX100_IDLE2_BITS                   10
#define SGMII1_FX100_FX100IDLE2_FX100_IDLE2_SHIFT                  0


/****************************************************************************
 * SGMII1_FX100 :: fx100IdleStatus
 ***************************************************************************/
/* SGMII1_FX100 :: fx100IdleStatus :: reserved0 [15:07] */
#define SGMII1_FX100_FX100IDLESTATUS_RESERVED0_MASK                0xff80
#define SGMII1_FX100_FX100IDLESTATUS_RESERVED0_ALIGN               0
#define SGMII1_FX100_FX100IDLESTATUS_RESERVED0_BITS                9
#define SGMII1_FX100_FX100IDLESTATUS_RESERVED0_SHIFT               7

/* SGMII1_FX100 :: fx100IdleStatus :: fx100_idleCorr_cnt [06:00] */
#define Wr_SGMII1_FX100_fx100IdleStatus_fx100_idleCorr_cnt(x) WriteRegBits16(SGMII1_FX100_FX100IDLESTATUS,0x7f,0,x)
#define Rd_SGMII1_FX100_fx100IdleStatus_fx100_idleCorr_cnt(x) ReadRegBits16(SGMII1_FX100_FX100IDLESTATUS,0x7f,0)
#define SGMII1_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_MASK       0x007f
#define SGMII1_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_ALIGN      0
#define SGMII1_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_BITS       7
#define SGMII1_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_SHIFT      0


/****************************************************************************
 * SGMII1_FX100 :: fx100IdleThres
 ***************************************************************************/
/* SGMII1_FX100 :: fx100IdleThres :: reserved0 [15:14] */
#define SGMII1_FX100_FX100IDLETHRES_RESERVED0_MASK                 0xc000
#define SGMII1_FX100_FX100IDLETHRES_RESERVED0_ALIGN                0
#define SGMII1_FX100_FX100IDLETHRES_RESERVED0_BITS                 2
#define SGMII1_FX100_FX100IDLETHRES_RESERVED0_SHIFT                14

/* SGMII1_FX100 :: fx100IdleThres :: fx100_idle_min_thres [13:07] */
#define Wr_SGMII1_FX100_fx100IdleThres_fx100_idle_min_thres(x) WriteRegBits16(SGMII1_FX100_FX100IDLETHRES,0x3f80,7,x)
#define Rd_SGMII1_FX100_fx100IdleThres_fx100_idle_min_thres(x) ReadRegBits16(SGMII1_FX100_FX100IDLETHRES,0x3f80,7)
#define SGMII1_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_MASK      0x3f80
#define SGMII1_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_ALIGN     0
#define SGMII1_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_BITS      7
#define SGMII1_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_SHIFT     7

/* SGMII1_FX100 :: fx100IdleThres :: fx100_idle_max_thres [06:00] */
#define Wr_SGMII1_FX100_fx100IdleThres_fx100_idle_max_thres(x) WriteRegBits16(SGMII1_FX100_FX100IDLETHRES,0x7f,0,x)
#define Rd_SGMII1_FX100_fx100IdleThres_fx100_idle_max_thres(x) ReadRegBits16(SGMII1_FX100_FX100IDLETHRES,0x7f,0)
#define SGMII1_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_MASK      0x007f
#define SGMII1_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_ALIGN     0
#define SGMII1_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_BITS      7
#define SGMII1_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_SHIFT     0


/****************************************************************************
 * SGMII1_FX100 :: fx100LockTmr
 ***************************************************************************/
/* SGMII1_FX100 :: fx100LockTmr :: fx100_lock_thres [15:12] */
#define Wr_SGMII1_FX100_fx100LockTmr_fx100_lock_thres(x) WriteRegBits16(SGMII1_FX100_FX100LOCKTMR,0xf000,12,x)
#define Rd_SGMII1_FX100_fx100LockTmr_fx100_lock_thres(x) ReadRegBits16(SGMII1_FX100_FX100LOCKTMR,0xf000,12)
#define SGMII1_FX100_FX100LOCKTMR_FX100_LOCK_THRES_MASK            0xf000
#define SGMII1_FX100_FX100LOCKTMR_FX100_LOCK_THRES_ALIGN           0
#define SGMII1_FX100_FX100LOCKTMR_FX100_LOCK_THRES_BITS            4
#define SGMII1_FX100_FX100LOCKTMR_FX100_LOCK_THRES_SHIFT           12

/* SGMII1_FX100 :: fx100LockTmr :: fx100_unlock_thres [11:08] */
#define Wr_SGMII1_FX100_fx100LockTmr_fx100_unlock_thres(x) WriteRegBits16(SGMII1_FX100_FX100LOCKTMR,0xf00,8,x)
#define Rd_SGMII1_FX100_fx100LockTmr_fx100_unlock_thres(x) ReadRegBits16(SGMII1_FX100_FX100LOCKTMR,0xf00,8)
#define SGMII1_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_MASK          0x0f00
#define SGMII1_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_ALIGN         0
#define SGMII1_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_BITS          4
#define SGMII1_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_SHIFT         8

/* SGMII1_FX100 :: fx100LockTmr :: fx100_lock_maxtime [07:00] */
#define Wr_SGMII1_FX100_fx100LockTmr_fx100_lock_maxtime(x) WriteRegBits16(SGMII1_FX100_FX100LOCKTMR,0xff,0,x)
#define Rd_SGMII1_FX100_fx100LockTmr_fx100_lock_maxtime(x) ReadRegBits16(SGMII1_FX100_FX100LOCKTMR,0xff,0)
#define SGMII1_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_MASK          0x00ff
#define SGMII1_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_ALIGN         0
#define SGMII1_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_BITS          8
#define SGMII1_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_SHIFT         0


/****************************************************************************
 * SGMII1_FX100 :: fx100LinkTmr
 ***************************************************************************/
/* SGMII1_FX100 :: fx100LinkTmr :: fx100_linkup_count [15:08] */
#define Wr_SGMII1_FX100_fx100LinkTmr_fx100_linkup_count(x) WriteRegBits16(SGMII1_FX100_FX100LINKTMR,0xff00,8,x)
#define Rd_SGMII1_FX100_fx100LinkTmr_fx100_linkup_count(x) ReadRegBits16(SGMII1_FX100_FX100LINKTMR,0xff00,8)
#define SGMII1_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_MASK          0xff00
#define SGMII1_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_ALIGN         0
#define SGMII1_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_BITS          8
#define SGMII1_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_SHIFT         8

/* SGMII1_FX100 :: fx100LinkTmr :: fx100_linkdn_count [07:00] */
#define Wr_SGMII1_FX100_fx100LinkTmr_fx100_linkdn_count(x) WriteRegBits16(SGMII1_FX100_FX100LINKTMR,0xff,0,x)
#define Rd_SGMII1_FX100_fx100LinkTmr_fx100_linkdn_count(x) ReadRegBits16(SGMII1_FX100_FX100LINKTMR,0xff,0)
#define SGMII1_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_MASK          0x00ff
#define SGMII1_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_ALIGN         0
#define SGMII1_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_BITS          8
#define SGMII1_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_SHIFT         0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_RX2
 ***************************************************************************/
/****************************************************************************
 * SGMII1_RX2 :: rxseq0
 ***************************************************************************/
/* SGMII1_RX2 :: rxseq0 :: cdrLockTimeTrckNrml_SM [15:08] */
#define Wr_SGMII1_RX2_rxseq0_cdrLockTimeTrckNrml_SM(x) WriteRegBits16(SGMII1_RX2_RXSEQ0,0xff00,8,x)
#define Rd_SGMII1_RX2_rxseq0_cdrLockTimeTrckNrml_SM(x) ReadRegBits16(SGMII1_RX2_RXSEQ0,0xff00,8)
#define SGMII1_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_MASK              0xff00
#define SGMII1_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_ALIGN             0
#define SGMII1_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_BITS              8
#define SGMII1_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_SHIFT             8

/* SGMII1_RX2 :: rxseq0 :: cdrLockTimeAcq_S1_SM [07:00] */
#define Wr_SGMII1_RX2_rxseq0_cdrLockTimeAcq_S1_SM(x) WriteRegBits16(SGMII1_RX2_RXSEQ0,0xff,0,x)
#define Rd_SGMII1_RX2_rxseq0_cdrLockTimeAcq_S1_SM(x) ReadRegBits16(SGMII1_RX2_RXSEQ0,0xff,0)
#define SGMII1_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_MASK                0x00ff
#define SGMII1_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_ALIGN               0
#define SGMII1_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_BITS                8
#define SGMII1_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_SHIFT               0


/****************************************************************************
 * SGMII1_RX2 :: rxseq1
 ***************************************************************************/
/* SGMII1_RX2 :: rxseq1 :: cdrLockTimeAcq_S2_SM [15:08] */
#define Wr_SGMII1_RX2_rxseq1_cdrLockTimeAcq_S2_SM(x) WriteRegBits16(SGMII1_RX2_RXSEQ1,0xff00,8,x)
#define Rd_SGMII1_RX2_rxseq1_cdrLockTimeAcq_S2_SM(x) ReadRegBits16(SGMII1_RX2_RXSEQ1,0xff00,8)
#define SGMII1_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_MASK                0xff00
#define SGMII1_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_ALIGN               0
#define SGMII1_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_BITS                8
#define SGMII1_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_SHIFT               8

/* SGMII1_RX2 :: rxseq1 :: cdrLockTimeAcq_S3_SM [07:00] */
#define Wr_SGMII1_RX2_rxseq1_cdrLockTimeAcq_S3_SM(x) WriteRegBits16(SGMII1_RX2_RXSEQ1,0xff,0,x)
#define Rd_SGMII1_RX2_rxseq1_cdrLockTimeAcq_S3_SM(x) ReadRegBits16(SGMII1_RX2_RXSEQ1,0xff,0)
#define SGMII1_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_MASK                0x00ff
#define SGMII1_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_ALIGN               0
#define SGMII1_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_BITS                8
#define SGMII1_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_SHIFT               0


/****************************************************************************
 * SGMII1_RX2 :: rxcdr0
 ***************************************************************************/
/* SGMII1_RX2 :: rxcdr0 :: sigdetTime_SM [15:12] */
#define Wr_SGMII1_RX2_rxcdr0_sigdetTime_SM(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0xf000,12,x)
#define Rd_SGMII1_RX2_rxcdr0_sigdetTime_SM(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0xf000,12)
#define SGMII1_RX2_RXCDR0_SIGDETTIME_SM_MASK                       0xf000
#define SGMII1_RX2_RXCDR0_SIGDETTIME_SM_ALIGN                      0
#define SGMII1_RX2_RXCDR0_SIGDETTIME_SM_BITS                       4
#define SGMII1_RX2_RXCDR0_SIGDETTIME_SM_SHIFT                      12

/* SGMII1_RX2 :: rxcdr0 :: em_phase_shift_360_ovrd_val [11:11] */
#define Wr_SGMII1_RX2_rxcdr0_em_phase_shift_360_ovrd_val(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x800,11,x)
#define Rd_SGMII1_RX2_rxcdr0_em_phase_shift_360_ovrd_val(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x800,11)
#define SGMII1_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_MASK         0x0800
#define SGMII1_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_ALIGN        0
#define SGMII1_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_BITS         1
#define SGMII1_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_SHIFT        11

/* SGMII1_RX2 :: rxcdr0 :: em_phase_shift_360_ovrd [10:10] */
#define Wr_SGMII1_RX2_rxcdr0_em_phase_shift_360_ovrd(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x400,10,x)
#define Rd_SGMII1_RX2_rxcdr0_em_phase_shift_360_ovrd(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x400,10)
#define SGMII1_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_MASK             0x0400
#define SGMII1_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_ALIGN            0
#define SGMII1_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_BITS             1
#define SGMII1_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_SHIFT            10

/* SGMII1_RX2 :: rxcdr0 :: rx_interp_ctrl_cap [09:09] */
#define Wr_SGMII1_RX2_rxcdr0_rx_interp_ctrl_cap(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x200,9,x)
#define Rd_SGMII1_RX2_rxcdr0_rx_interp_ctrl_cap(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x200,9)
#define SGMII1_RX2_RXCDR0_RX_INTERP_CTRL_CAP_MASK                  0x0200
#define SGMII1_RX2_RXCDR0_RX_INTERP_CTRL_CAP_ALIGN                 0
#define SGMII1_RX2_RXCDR0_RX_INTERP_CTRL_CAP_BITS                  1
#define SGMII1_RX2_RXCDR0_RX_INTERP_CTRL_CAP_SHIFT                 9

/* SGMII1_RX2 :: rxcdr0 :: rx_interp_status_sel [08:06] */
#define Wr_SGMII1_RX2_rxcdr0_rx_interp_status_sel(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x1c0,6,x)
#define Rd_SGMII1_RX2_rxcdr0_rx_interp_status_sel(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x1c0,6)
#define SGMII1_RX2_RXCDR0_RX_INTERP_STATUS_SEL_MASK                0x01c0
#define SGMII1_RX2_RXCDR0_RX_INTERP_STATUS_SEL_ALIGN               0
#define SGMII1_RX2_RXCDR0_RX_INTERP_STATUS_SEL_BITS                3
#define SGMII1_RX2_RXCDR0_RX_INTERP_STATUS_SEL_SHIFT               6

/* SGMII1_RX2 :: rxcdr0 :: pi_clk90_offset_override [05:05] */
#define Wr_SGMII1_RX2_rxcdr0_pi_clk90_offset_override(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x20,5,x)
#define Rd_SGMII1_RX2_rxcdr0_pi_clk90_offset_override(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x20,5)
#define SGMII1_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_MASK            0x0020
#define SGMII1_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_ALIGN           0
#define SGMII1_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_BITS            1
#define SGMII1_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_SHIFT           5

/* SGMII1_RX2 :: rxcdr0 :: pi_phase_rotate_override [04:04] */
#define Wr_SGMII1_RX2_rxcdr0_pi_phase_rotate_override(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x10,4,x)
#define Rd_SGMII1_RX2_rxcdr0_pi_phase_rotate_override(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x10,4)
#define SGMII1_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_MASK            0x0010
#define SGMII1_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_ALIGN           0
#define SGMII1_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_BITS            1
#define SGMII1_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_SHIFT           4

/* SGMII1_RX2 :: rxcdr0 :: mdio_em_err_cnt_clr [03:03] */
#define Wr_SGMII1_RX2_rxcdr0_mdio_em_err_cnt_clr(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x8,3,x)
#define Rd_SGMII1_RX2_rxcdr0_mdio_em_err_cnt_clr(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x8,3)
#define SGMII1_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_MASK                 0x0008
#define SGMII1_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_ALIGN                0
#define SGMII1_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_BITS                 1
#define SGMII1_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_SHIFT                3

/* SGMII1_RX2 :: rxcdr0 :: mdio_em_err_cnt_frz [02:02] */
#define Wr_SGMII1_RX2_rxcdr0_mdio_em_err_cnt_frz(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x4,2,x)
#define Rd_SGMII1_RX2_rxcdr0_mdio_em_err_cnt_frz(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x4,2)
#define SGMII1_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_MASK                 0x0004
#define SGMII1_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_ALIGN                0
#define SGMII1_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_BITS                 1
#define SGMII1_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_SHIFT                2

/* SGMII1_RX2 :: rxcdr0 :: mdio_em_pwrdn [01:01] */
#define Wr_SGMII1_RX2_rxcdr0_mdio_em_pwrdn(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x2,1,x)
#define Rd_SGMII1_RX2_rxcdr0_mdio_em_pwrdn(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x2,1)
#define SGMII1_RX2_RXCDR0_MDIO_EM_PWRDN_MASK                       0x0002
#define SGMII1_RX2_RXCDR0_MDIO_EM_PWRDN_ALIGN                      0
#define SGMII1_RX2_RXCDR0_MDIO_EM_PWRDN_BITS                       1
#define SGMII1_RX2_RXCDR0_MDIO_EM_PWRDN_SHIFT                      1

/* SGMII1_RX2 :: rxcdr0 :: pi_phase_invert [00:00] */
#define Wr_SGMII1_RX2_rxcdr0_pi_phase_invert(x) WriteRegBits16(SGMII1_RX2_RXCDR0,0x1,0,x)
#define Rd_SGMII1_RX2_rxcdr0_pi_phase_invert(x) ReadRegBits16(SGMII1_RX2_RXCDR0,0x1,0)
#define SGMII1_RX2_RXCDR0_PI_PHASE_INVERT_MASK                     0x0001
#define SGMII1_RX2_RXCDR0_PI_PHASE_INVERT_ALIGN                    0
#define SGMII1_RX2_RXCDR0_PI_PHASE_INVERT_BITS                     1
#define SGMII1_RX2_RXCDR0_PI_PHASE_INVERT_SHIFT                    0


/****************************************************************************
 * SGMII1_RX2 :: rxcdr1
 ***************************************************************************/
/* SGMII1_RX2 :: rxcdr1 :: reserved0 [15:13] */
#define SGMII1_RX2_RXCDR1_RESERVED0_MASK                           0xe000
#define SGMII1_RX2_RXCDR1_RESERVED0_ALIGN                          0
#define SGMII1_RX2_RXCDR1_RESERVED0_BITS                           3
#define SGMII1_RX2_RXCDR1_RESERVED0_SHIFT                          13

/* SGMII1_RX2 :: rxcdr1 :: step_two [12:11] */
#define Wr_SGMII1_RX2_rxcdr1_step_two(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x1800,11,x)
#define Rd_SGMII1_RX2_rxcdr1_step_two(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x1800,11)
#define SGMII1_RX2_RXCDR1_STEP_TWO_MASK                            0x1800
#define SGMII1_RX2_RXCDR1_STEP_TWO_ALIGN                           0
#define SGMII1_RX2_RXCDR1_STEP_TWO_BITS                            2
#define SGMII1_RX2_RXCDR1_STEP_TWO_SHIFT                           11

/* SGMII1_RX2 :: rxcdr1 :: step_one [10:09] */
#define Wr_SGMII1_RX2_rxcdr1_step_one(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x600,9,x)
#define Rd_SGMII1_RX2_rxcdr1_step_one(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x600,9)
#define SGMII1_RX2_RXCDR1_STEP_ONE_MASK                            0x0600
#define SGMII1_RX2_RXCDR1_STEP_ONE_ALIGN                           0
#define SGMII1_RX2_RXCDR1_STEP_ONE_BITS                            2
#define SGMII1_RX2_RXCDR1_STEP_ONE_SHIFT                           9

/* SGMII1_RX2 :: rxcdr1 :: flip_zero_polarity [08:08] */
#define Wr_SGMII1_RX2_rxcdr1_flip_zero_polarity(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x100,8,x)
#define Rd_SGMII1_RX2_rxcdr1_flip_zero_polarity(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x100,8)
#define SGMII1_RX2_RXCDR1_FLIP_ZERO_POLARITY_MASK                  0x0100
#define SGMII1_RX2_RXCDR1_FLIP_ZERO_POLARITY_ALIGN                 0
#define SGMII1_RX2_RXCDR1_FLIP_ZERO_POLARITY_BITS                  1
#define SGMII1_RX2_RXCDR1_FLIP_ZERO_POLARITY_SHIFT                 8

/* SGMII1_RX2 :: rxcdr1 :: flip_peak_polarity [07:07] */
#define Wr_SGMII1_RX2_rxcdr1_flip_peak_polarity(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x80,7,x)
#define Rd_SGMII1_RX2_rxcdr1_flip_peak_polarity(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x80,7)
#define SGMII1_RX2_RXCDR1_FLIP_PEAK_POLARITY_MASK                  0x0080
#define SGMII1_RX2_RXCDR1_FLIP_PEAK_POLARITY_ALIGN                 0
#define SGMII1_RX2_RXCDR1_FLIP_PEAK_POLARITY_BITS                  1
#define SGMII1_RX2_RXCDR1_FLIP_PEAK_POLARITY_SHIFT                 7

/* SGMII1_RX2 :: rxcdr1 :: rising_edge [06:06] */
#define Wr_SGMII1_RX2_rxcdr1_rising_edge(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x40,6,x)
#define Rd_SGMII1_RX2_rxcdr1_rising_edge(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x40,6)
#define SGMII1_RX2_RXCDR1_RISING_EDGE_MASK                         0x0040
#define SGMII1_RX2_RXCDR1_RISING_EDGE_ALIGN                        0
#define SGMII1_RX2_RXCDR1_RISING_EDGE_BITS                         1
#define SGMII1_RX2_RXCDR1_RISING_EDGE_SHIFT                        6

/* SGMII1_RX2 :: rxcdr1 :: falling_edge [05:05] */
#define Wr_SGMII1_RX2_rxcdr1_falling_edge(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x20,5,x)
#define Rd_SGMII1_RX2_rxcdr1_falling_edge(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x20,5)
#define SGMII1_RX2_RXCDR1_FALLING_EDGE_MASK                        0x0020
#define SGMII1_RX2_RXCDR1_FALLING_EDGE_ALIGN                       0
#define SGMII1_RX2_RXCDR1_FALLING_EDGE_BITS                        1
#define SGMII1_RX2_RXCDR1_FALLING_EDGE_SHIFT                       5

/* SGMII1_RX2 :: rxcdr1 :: freq_upd_en [04:04] */
#define Wr_SGMII1_RX2_rxcdr1_freq_upd_en(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x10,4,x)
#define Rd_SGMII1_RX2_rxcdr1_freq_upd_en(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x10,4)
#define SGMII1_RX2_RXCDR1_FREQ_UPD_EN_MASK                         0x0010
#define SGMII1_RX2_RXCDR1_FREQ_UPD_EN_ALIGN                        0
#define SGMII1_RX2_RXCDR1_FREQ_UPD_EN_BITS                         1
#define SGMII1_RX2_RXCDR1_FREQ_UPD_EN_SHIFT                        4

/* SGMII1_RX2 :: rxcdr1 :: phase_delta [03:03] */
#define Wr_SGMII1_RX2_rxcdr1_phase_delta(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x8,3,x)
#define Rd_SGMII1_RX2_rxcdr1_phase_delta(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x8,3)
#define SGMII1_RX2_RXCDR1_PHASE_DELTA_MASK                         0x0008
#define SGMII1_RX2_RXCDR1_PHASE_DELTA_ALIGN                        0
#define SGMII1_RX2_RXCDR1_PHASE_DELTA_BITS                         1
#define SGMII1_RX2_RXCDR1_PHASE_DELTA_SHIFT                        3

/* SGMII1_RX2 :: rxcdr1 :: phs_counter_clr [02:02] */
#define Wr_SGMII1_RX2_rxcdr1_phs_counter_clr(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x4,2,x)
#define Rd_SGMII1_RX2_rxcdr1_phs_counter_clr(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x4,2)
#define SGMII1_RX2_RXCDR1_PHS_COUNTER_CLR_MASK                     0x0004
#define SGMII1_RX2_RXCDR1_PHS_COUNTER_CLR_ALIGN                    0
#define SGMII1_RX2_RXCDR1_PHS_COUNTER_CLR_BITS                     1
#define SGMII1_RX2_RXCDR1_PHS_COUNTER_CLR_SHIFT                    2

/* SGMII1_RX2 :: rxcdr1 :: phase_sat_ctrl [01:00] */
#define Wr_SGMII1_RX2_rxcdr1_phase_sat_ctrl(x) WriteRegBits16(SGMII1_RX2_RXCDR1,0x3,0,x)
#define Rd_SGMII1_RX2_rxcdr1_phase_sat_ctrl(x) ReadRegBits16(SGMII1_RX2_RXCDR1,0x3,0)
#define SGMII1_RX2_RXCDR1_PHASE_SAT_CTRL_MASK                      0x0003
#define SGMII1_RX2_RXCDR1_PHASE_SAT_CTRL_ALIGN                     0
#define SGMII1_RX2_RXCDR1_PHASE_SAT_CTRL_BITS                      2
#define SGMII1_RX2_RXCDR1_PHASE_SAT_CTRL_SHIFT                     0


/****************************************************************************
 * SGMII1_RX2 :: rxcdr2
 ***************************************************************************/
/* SGMII1_RX2 :: rxcdr2 :: reserved0 [15:14] */
#define SGMII1_RX2_RXCDR2_RESERVED0_MASK                           0xc000
#define SGMII1_RX2_RXCDR2_RESERVED0_ALIGN                          0
#define SGMII1_RX2_RXCDR2_RESERVED0_BITS                           2
#define SGMII1_RX2_RXCDR2_RESERVED0_SHIFT                          14

/* SGMII1_RX2 :: rxcdr2 :: phsacq_enable [13:13] */
#define Wr_SGMII1_RX2_rxcdr2_phsacq_enable(x) WriteRegBits16(SGMII1_RX2_RXCDR2,0x2000,13,x)
#define Rd_SGMII1_RX2_rxcdr2_phsacq_enable(x) ReadRegBits16(SGMII1_RX2_RXCDR2,0x2000,13)
#define SGMII1_RX2_RXCDR2_PHSACQ_ENABLE_MASK                       0x2000
#define SGMII1_RX2_RXCDR2_PHSACQ_ENABLE_ALIGN                      0
#define SGMII1_RX2_RXCDR2_PHSACQ_ENABLE_BITS                       1
#define SGMII1_RX2_RXCDR2_PHSACQ_ENABLE_SHIFT                      13

/* SGMII1_RX2 :: rxcdr2 :: rate_select [12:12] */
#define Wr_SGMII1_RX2_rxcdr2_rate_select(x) WriteRegBits16(SGMII1_RX2_RXCDR2,0x1000,12,x)
#define Rd_SGMII1_RX2_rxcdr2_rate_select(x) ReadRegBits16(SGMII1_RX2_RXCDR2,0x1000,12)
#define SGMII1_RX2_RXCDR2_RATE_SELECT_MASK                         0x1000
#define SGMII1_RX2_RXCDR2_RATE_SELECT_ALIGN                        0
#define SGMII1_RX2_RXCDR2_RATE_SELECT_BITS                         1
#define SGMII1_RX2_RXCDR2_RATE_SELECT_SHIFT                        12

/* SGMII1_RX2 :: rxcdr2 :: phsacq_dir [11:11] */
#define Wr_SGMII1_RX2_rxcdr2_phsacq_dir(x) WriteRegBits16(SGMII1_RX2_RXCDR2,0x800,11,x)
#define Rd_SGMII1_RX2_rxcdr2_phsacq_dir(x) ReadRegBits16(SGMII1_RX2_RXCDR2,0x800,11)
#define SGMII1_RX2_RXCDR2_PHSACQ_DIR_MASK                          0x0800
#define SGMII1_RX2_RXCDR2_PHSACQ_DIR_ALIGN                         0
#define SGMII1_RX2_RXCDR2_PHSACQ_DIR_BITS                          1
#define SGMII1_RX2_RXCDR2_PHSACQ_DIR_SHIFT                         11

/* SGMII1_RX2 :: rxcdr2 :: reserved1 [10:10] */
#define SGMII1_RX2_RXCDR2_RESERVED1_MASK                           0x0400
#define SGMII1_RX2_RXCDR2_RESERVED1_ALIGN                          0
#define SGMII1_RX2_RXCDR2_RESERVED1_BITS                           1
#define SGMII1_RX2_RXCDR2_RESERVED1_SHIFT                          10

/* SGMII1_RX2 :: rxcdr2 :: phsacq_freq_sel [09:09] */
#define Wr_SGMII1_RX2_rxcdr2_phsacq_freq_sel(x) WriteRegBits16(SGMII1_RX2_RXCDR2,0x200,9,x)
#define Rd_SGMII1_RX2_rxcdr2_phsacq_freq_sel(x) ReadRegBits16(SGMII1_RX2_RXCDR2,0x200,9)
#define SGMII1_RX2_RXCDR2_PHSACQ_FREQ_SEL_MASK                     0x0200
#define SGMII1_RX2_RXCDR2_PHSACQ_FREQ_SEL_ALIGN                    0
#define SGMII1_RX2_RXCDR2_PHSACQ_FREQ_SEL_BITS                     1
#define SGMII1_RX2_RXCDR2_PHSACQ_FREQ_SEL_SHIFT                    9

/* SGMII1_RX2 :: rxcdr2 :: phsacq_step [08:08] */
#define Wr_SGMII1_RX2_rxcdr2_phsacq_step(x) WriteRegBits16(SGMII1_RX2_RXCDR2,0x100,8,x)
#define Rd_SGMII1_RX2_rxcdr2_phsacq_step(x) ReadRegBits16(SGMII1_RX2_RXCDR2,0x100,8)
#define SGMII1_RX2_RXCDR2_PHSACQ_STEP_MASK                         0x0100
#define SGMII1_RX2_RXCDR2_PHSACQ_STEP_ALIGN                        0
#define SGMII1_RX2_RXCDR2_PHSACQ_STEP_BITS                         1
#define SGMII1_RX2_RXCDR2_PHSACQ_STEP_SHIFT                        8

/* SGMII1_RX2 :: rxcdr2 :: phsacq_timeout [07:00] */
#define Wr_SGMII1_RX2_rxcdr2_phsacq_timeout(x) WriteRegBits16(SGMII1_RX2_RXCDR2,0xff,0,x)
#define Rd_SGMII1_RX2_rxcdr2_phsacq_timeout(x) ReadRegBits16(SGMII1_RX2_RXCDR2,0xff,0)
#define SGMII1_RX2_RXCDR2_PHSACQ_TIMEOUT_MASK                      0x00ff
#define SGMII1_RX2_RXCDR2_PHSACQ_TIMEOUT_ALIGN                     0
#define SGMII1_RX2_RXCDR2_PHSACQ_TIMEOUT_BITS                      8
#define SGMII1_RX2_RXCDR2_PHSACQ_TIMEOUT_SHIFT                     0


/****************************************************************************
 * SGMII1_RX2 :: rxcdr3
 ***************************************************************************/
/* SGMII1_RX2 :: rxcdr3 :: reserved0 [15:13] */
#define SGMII1_RX2_RXCDR3_RESERVED0_MASK                           0xe000
#define SGMII1_RX2_RXCDR3_RESERVED0_ALIGN                          0
#define SGMII1_RX2_RXCDR3_RESERVED0_BITS                           3
#define SGMII1_RX2_RXCDR3_RESERVED0_SHIFT                          13

/* SGMII1_RX2 :: rxcdr3 :: phase_step [12:11] */
#define Wr_SGMII1_RX2_rxcdr3_phase_step(x) WriteRegBits16(SGMII1_RX2_RXCDR3,0x1800,11,x)
#define Rd_SGMII1_RX2_rxcdr3_phase_step(x) ReadRegBits16(SGMII1_RX2_RXCDR3,0x1800,11)
#define SGMII1_RX2_RXCDR3_PHASE_STEP_MASK                          0x1800
#define SGMII1_RX2_RXCDR3_PHASE_STEP_ALIGN                         0
#define SGMII1_RX2_RXCDR3_PHASE_STEP_BITS                          2
#define SGMII1_RX2_RXCDR3_PHASE_STEP_SHIFT                         11

/* SGMII1_RX2 :: rxcdr3 :: phase_frz_1 [10:10] */
#define Wr_SGMII1_RX2_rxcdr3_phase_frz_1(x) WriteRegBits16(SGMII1_RX2_RXCDR3,0x400,10,x)
#define Rd_SGMII1_RX2_rxcdr3_phase_frz_1(x) ReadRegBits16(SGMII1_RX2_RXCDR3,0x400,10)
#define SGMII1_RX2_RXCDR3_PHASE_FRZ_1_MASK                         0x0400
#define SGMII1_RX2_RXCDR3_PHASE_FRZ_1_ALIGN                        0
#define SGMII1_RX2_RXCDR3_PHASE_FRZ_1_BITS                         1
#define SGMII1_RX2_RXCDR3_PHASE_FRZ_1_SHIFT                        10

/* SGMII1_RX2 :: rxcdr3 :: phase_frz_1_en [09:09] */
#define Wr_SGMII1_RX2_rxcdr3_phase_frz_1_en(x) WriteRegBits16(SGMII1_RX2_RXCDR3,0x200,9,x)
#define Rd_SGMII1_RX2_rxcdr3_phase_frz_1_en(x) ReadRegBits16(SGMII1_RX2_RXCDR3,0x200,9)
#define SGMII1_RX2_RXCDR3_PHASE_FRZ_1_EN_MASK                      0x0200
#define SGMII1_RX2_RXCDR3_PHASE_FRZ_1_EN_ALIGN                     0
#define SGMII1_RX2_RXCDR3_PHASE_FRZ_1_EN_BITS                      1
#define SGMII1_RX2_RXCDR3_PHASE_FRZ_1_EN_SHIFT                     9

/* SGMII1_RX2 :: rxcdr3 :: phase_override_SM [08:08] */
#define Wr_SGMII1_RX2_rxcdr3_phase_override_SM(x) WriteRegBits16(SGMII1_RX2_RXCDR3,0x100,8,x)
#define Rd_SGMII1_RX2_rxcdr3_phase_override_SM(x) ReadRegBits16(SGMII1_RX2_RXCDR3,0x100,8)
#define SGMII1_RX2_RXCDR3_PHASE_OVERRIDE_SM_MASK                   0x0100
#define SGMII1_RX2_RXCDR3_PHASE_OVERRIDE_SM_ALIGN                  0
#define SGMII1_RX2_RXCDR3_PHASE_OVERRIDE_SM_BITS                   1
#define SGMII1_RX2_RXCDR3_PHASE_OVERRIDE_SM_SHIFT                  8

/* SGMII1_RX2 :: rxcdr3 :: phase_inc_SM [07:07] */
#define Wr_SGMII1_RX2_rxcdr3_phase_inc_SM(x) WriteRegBits16(SGMII1_RX2_RXCDR3,0x80,7,x)
#define Rd_SGMII1_RX2_rxcdr3_phase_inc_SM(x) ReadRegBits16(SGMII1_RX2_RXCDR3,0x80,7)
#define SGMII1_RX2_RXCDR3_PHASE_INC_SM_MASK                        0x0080
#define SGMII1_RX2_RXCDR3_PHASE_INC_SM_ALIGN                       0
#define SGMII1_RX2_RXCDR3_PHASE_INC_SM_BITS                        1
#define SGMII1_RX2_RXCDR3_PHASE_INC_SM_SHIFT                       7

/* SGMII1_RX2 :: rxcdr3 :: phase_dec_SM [06:06] */
#define Wr_SGMII1_RX2_rxcdr3_phase_dec_SM(x) WriteRegBits16(SGMII1_RX2_RXCDR3,0x40,6,x)
#define Rd_SGMII1_RX2_rxcdr3_phase_dec_SM(x) ReadRegBits16(SGMII1_RX2_RXCDR3,0x40,6)
#define SGMII1_RX2_RXCDR3_PHASE_DEC_SM_MASK                        0x0040
#define SGMII1_RX2_RXCDR3_PHASE_DEC_SM_ALIGN                       0
#define SGMII1_RX2_RXCDR3_PHASE_DEC_SM_BITS                        1
#define SGMII1_RX2_RXCDR3_PHASE_DEC_SM_SHIFT                       6

/* SGMII1_RX2 :: rxcdr3 :: phase_strobe_SM [05:05] */
#define Wr_SGMII1_RX2_rxcdr3_phase_strobe_SM(x) WriteRegBits16(SGMII1_RX2_RXCDR3,0x20,5,x)
#define Rd_SGMII1_RX2_rxcdr3_phase_strobe_SM(x) ReadRegBits16(SGMII1_RX2_RXCDR3,0x20,5)
#define SGMII1_RX2_RXCDR3_PHASE_STROBE_SM_MASK                     0x0020
#define SGMII1_RX2_RXCDR3_PHASE_STROBE_SM_ALIGN                    0
#define SGMII1_RX2_RXCDR3_PHASE_STROBE_SM_BITS                     1
#define SGMII1_RX2_RXCDR3_PHASE_STROBE_SM_SHIFT                    5

/* SGMII1_RX2 :: rxcdr3 :: phase_delta_SM [04:00] */
#define Wr_SGMII1_RX2_rxcdr3_phase_delta_SM(x) WriteRegBits16(SGMII1_RX2_RXCDR3,0x1f,0,x)
#define Rd_SGMII1_RX2_rxcdr3_phase_delta_SM(x) ReadRegBits16(SGMII1_RX2_RXCDR3,0x1f,0)
#define SGMII1_RX2_RXCDR3_PHASE_DELTA_SM_MASK                      0x001f
#define SGMII1_RX2_RXCDR3_PHASE_DELTA_SM_ALIGN                     0
#define SGMII1_RX2_RXCDR3_PHASE_DELTA_SM_BITS                      5
#define SGMII1_RX2_RXCDR3_PHASE_DELTA_SM_SHIFT                     0


/****************************************************************************
 * SGMII1_RX2 :: rxcdr4
 ***************************************************************************/
/* SGMII1_RX2 :: rxcdr4 :: bwsel_integ [15:12] */
#define Wr_SGMII1_RX2_rxcdr4_bwsel_integ(x) WriteRegBits16(SGMII1_RX2_RXCDR4,0xf000,12,x)
#define Rd_SGMII1_RX2_rxcdr4_bwsel_integ(x) ReadRegBits16(SGMII1_RX2_RXCDR4,0xf000,12)
#define SGMII1_RX2_RXCDR4_BWSEL_INTEG_MASK                         0xf000
#define SGMII1_RX2_RXCDR4_BWSEL_INTEG_ALIGN                        0
#define SGMII1_RX2_RXCDR4_BWSEL_INTEG_BITS                         4
#define SGMII1_RX2_RXCDR4_BWSEL_INTEG_SHIFT                        12

/* SGMII1_RX2 :: rxcdr4 :: bwsel_prop [11:08] */
#define Wr_SGMII1_RX2_rxcdr4_bwsel_prop(x) WriteRegBits16(SGMII1_RX2_RXCDR4,0xf00,8,x)
#define Rd_SGMII1_RX2_rxcdr4_bwsel_prop(x) ReadRegBits16(SGMII1_RX2_RXCDR4,0xf00,8)
#define SGMII1_RX2_RXCDR4_BWSEL_PROP_MASK                          0x0f00
#define SGMII1_RX2_RXCDR4_BWSEL_PROP_ALIGN                         0
#define SGMII1_RX2_RXCDR4_BWSEL_PROP_BITS                          4
#define SGMII1_RX2_RXCDR4_BWSEL_PROP_SHIFT                         8

/* SGMII1_RX2 :: rxcdr4 :: integ_clr [07:07] */
#define Wr_SGMII1_RX2_rxcdr4_integ_clr(x) WriteRegBits16(SGMII1_RX2_RXCDR4,0x80,7,x)
#define Rd_SGMII1_RX2_rxcdr4_integ_clr(x) ReadRegBits16(SGMII1_RX2_RXCDR4,0x80,7)
#define SGMII1_RX2_RXCDR4_INTEG_CLR_MASK                           0x0080
#define SGMII1_RX2_RXCDR4_INTEG_CLR_ALIGN                          0
#define SGMII1_RX2_RXCDR4_INTEG_CLR_BITS                           1
#define SGMII1_RX2_RXCDR4_INTEG_CLR_SHIFT                          7

/* SGMII1_RX2 :: rxcdr4 :: freq_en [06:06] */
#define Wr_SGMII1_RX2_rxcdr4_freq_en(x) WriteRegBits16(SGMII1_RX2_RXCDR4,0x40,6,x)
#define Rd_SGMII1_RX2_rxcdr4_freq_en(x) ReadRegBits16(SGMII1_RX2_RXCDR4,0x40,6)
#define SGMII1_RX2_RXCDR4_FREQ_EN_MASK                             0x0040
#define SGMII1_RX2_RXCDR4_FREQ_EN_ALIGN                            0
#define SGMII1_RX2_RXCDR4_FREQ_EN_BITS                             1
#define SGMII1_RX2_RXCDR4_FREQ_EN_SHIFT                            6

/* SGMII1_RX2 :: rxcdr4 :: freq_override_en [05:05] */
#define Wr_SGMII1_RX2_rxcdr4_freq_override_en(x) WriteRegBits16(SGMII1_RX2_RXCDR4,0x20,5,x)
#define Rd_SGMII1_RX2_rxcdr4_freq_override_en(x) ReadRegBits16(SGMII1_RX2_RXCDR4,0x20,5)
#define SGMII1_RX2_RXCDR4_FREQ_OVERRIDE_EN_MASK                    0x0020
#define SGMII1_RX2_RXCDR4_FREQ_OVERRIDE_EN_ALIGN                   0
#define SGMII1_RX2_RXCDR4_FREQ_OVERRIDE_EN_BITS                    1
#define SGMII1_RX2_RXCDR4_FREQ_OVERRIDE_EN_SHIFT                   5

/* SGMII1_RX2 :: rxcdr4 :: freq_override_val [04:00] */
#define Wr_SGMII1_RX2_rxcdr4_freq_override_val(x) WriteRegBits16(SGMII1_RX2_RXCDR4,0x1f,0,x)
#define Rd_SGMII1_RX2_rxcdr4_freq_override_val(x) ReadRegBits16(SGMII1_RX2_RXCDR4,0x1f,0)
#define SGMII1_RX2_RXCDR4_FREQ_OVERRIDE_VAL_MASK                   0x001f
#define SGMII1_RX2_RXCDR4_FREQ_OVERRIDE_VAL_ALIGN                  0
#define SGMII1_RX2_RXCDR4_FREQ_OVERRIDE_VAL_BITS                   5
#define SGMII1_RX2_RXCDR4_FREQ_OVERRIDE_VAL_SHIFT                  0


/****************************************************************************
 * SGMII1_RX2 :: status0
 ***************************************************************************/
/* SGMII1_RX2 :: status0 :: reserved0 [15:10] */
#define SGMII1_RX2_STATUS0_RESERVED0_MASK                          0xfc00
#define SGMII1_RX2_STATUS0_RESERVED0_ALIGN                         0
#define SGMII1_RX2_STATUS0_RESERVED0_BITS                          6
#define SGMII1_RX2_STATUS0_RESERVED0_SHIFT                         10

/* SGMII1_RX2 :: status0 :: rx_lmtoff [09:04] */
#define Wr_SGMII1_RX2_status0_rx_lmtoff(x) WriteRegBits16(SGMII1_RX2_STATUS0,0x3f0,4,x)
#define Rd_SGMII1_RX2_status0_rx_lmtoff(x) ReadRegBits16(SGMII1_RX2_STATUS0,0x3f0,4)
#define SGMII1_RX2_STATUS0_RX_LMTOFF_MASK                          0x03f0
#define SGMII1_RX2_STATUS0_RX_LMTOFF_ALIGN                         0
#define SGMII1_RX2_STATUS0_RX_LMTOFF_BITS                          6
#define SGMII1_RX2_STATUS0_RX_LMTOFF_SHIFT                         4

/* SGMII1_RX2 :: status0 :: rx_slicer_cal_done [03:03] */
#define Wr_SGMII1_RX2_status0_rx_slicer_cal_done(x) WriteRegBits16(SGMII1_RX2_STATUS0,0x8,3,x)
#define Rd_SGMII1_RX2_status0_rx_slicer_cal_done(x) ReadRegBits16(SGMII1_RX2_STATUS0,0x8,3)
#define SGMII1_RX2_STATUS0_RX_SLICER_CAL_DONE_MASK                 0x0008
#define SGMII1_RX2_STATUS0_RX_SLICER_CAL_DONE_ALIGN                0
#define SGMII1_RX2_STATUS0_RX_SLICER_CAL_DONE_BITS                 1
#define SGMII1_RX2_STATUS0_RX_SLICER_CAL_DONE_SHIFT                3

/* SGMII1_RX2 :: status0 :: rx_sloff0_invalid [02:02] */
#define Wr_SGMII1_RX2_status0_rx_sloff0_invalid(x) WriteRegBits16(SGMII1_RX2_STATUS0,0x4,2,x)
#define Rd_SGMII1_RX2_status0_rx_sloff0_invalid(x) ReadRegBits16(SGMII1_RX2_STATUS0,0x4,2)
#define SGMII1_RX2_STATUS0_RX_SLOFF0_INVALID_MASK                  0x0004
#define SGMII1_RX2_STATUS0_RX_SLOFF0_INVALID_ALIGN                 0
#define SGMII1_RX2_STATUS0_RX_SLOFF0_INVALID_BITS                  1
#define SGMII1_RX2_STATUS0_RX_SLOFF0_INVALID_SHIFT                 2

/* SGMII1_RX2 :: status0 :: rx_sloff1_invalid [01:01] */
#define Wr_SGMII1_RX2_status0_rx_sloff1_invalid(x) WriteRegBits16(SGMII1_RX2_STATUS0,0x2,1,x)
#define Rd_SGMII1_RX2_status0_rx_sloff1_invalid(x) ReadRegBits16(SGMII1_RX2_STATUS0,0x2,1)
#define SGMII1_RX2_STATUS0_RX_SLOFF1_INVALID_MASK                  0x0002
#define SGMII1_RX2_STATUS0_RX_SLOFF1_INVALID_ALIGN                 0
#define SGMII1_RX2_STATUS0_RX_SLOFF1_INVALID_BITS                  1
#define SGMII1_RX2_STATUS0_RX_SLOFF1_INVALID_SHIFT                 1

/* SGMII1_RX2 :: status0 :: rx_sloff2_invalid [00:00] */
#define Wr_SGMII1_RX2_status0_rx_sloff2_invalid(x) WriteRegBits16(SGMII1_RX2_STATUS0,0x1,0,x)
#define Rd_SGMII1_RX2_status0_rx_sloff2_invalid(x) ReadRegBits16(SGMII1_RX2_STATUS0,0x1,0)
#define SGMII1_RX2_STATUS0_RX_SLOFF2_INVALID_MASK                  0x0001
#define SGMII1_RX2_STATUS0_RX_SLOFF2_INVALID_ALIGN                 0
#define SGMII1_RX2_STATUS0_RX_SLOFF2_INVALID_BITS                  1
#define SGMII1_RX2_STATUS0_RX_SLOFF2_INVALID_SHIFT                 0


/****************************************************************************
 * SGMII1_RX2 :: status1
 ***************************************************************************/
/* SGMII1_RX2 :: status1 :: reserved0 [15:15] */
#define SGMII1_RX2_STATUS1_RESERVED0_MASK                          0x8000
#define SGMII1_RX2_STATUS1_RESERVED0_ALIGN                         0
#define SGMII1_RX2_STATUS1_RESERVED0_BITS                          1
#define SGMII1_RX2_STATUS1_RESERVED0_SHIFT                         15

/* SGMII1_RX2 :: status1 :: up_sloffx_val [14:11] */
#define Wr_SGMII1_RX2_status1_up_sloffx_val(x) WriteRegBits16(SGMII1_RX2_STATUS1,0x7800,11,x)
#define Rd_SGMII1_RX2_status1_up_sloffx_val(x) ReadRegBits16(SGMII1_RX2_STATUS1,0x7800,11)
#define SGMII1_RX2_STATUS1_UP_SLOFFX_VAL_MASK                      0x7800
#define SGMII1_RX2_STATUS1_UP_SLOFFX_VAL_ALIGN                     0
#define SGMII1_RX2_STATUS1_UP_SLOFFX_VAL_BITS                      4
#define SGMII1_RX2_STATUS1_UP_SLOFFX_VAL_SHIFT                     11

/* SGMII1_RX2 :: status1 :: dn_sloffx_val [10:07] */
#define Wr_SGMII1_RX2_status1_dn_sloffx_val(x) WriteRegBits16(SGMII1_RX2_STATUS1,0x780,7,x)
#define Rd_SGMII1_RX2_status1_dn_sloffx_val(x) ReadRegBits16(SGMII1_RX2_STATUS1,0x780,7)
#define SGMII1_RX2_STATUS1_DN_SLOFFX_VAL_MASK                      0x0780
#define SGMII1_RX2_STATUS1_DN_SLOFFX_VAL_ALIGN                     0
#define SGMII1_RX2_STATUS1_DN_SLOFFX_VAL_BITS                      4
#define SGMII1_RX2_STATUS1_DN_SLOFFX_VAL_SHIFT                     7

/* SGMII1_RX2 :: status1 :: sloffx_val [06:03] */
#define Wr_SGMII1_RX2_status1_sloffx_val(x) WriteRegBits16(SGMII1_RX2_STATUS1,0x78,3,x)
#define Rd_SGMII1_RX2_status1_sloffx_val(x) ReadRegBits16(SGMII1_RX2_STATUS1,0x78,3)
#define SGMII1_RX2_STATUS1_SLOFFX_VAL_MASK                         0x0078
#define SGMII1_RX2_STATUS1_SLOFFX_VAL_ALIGN                        0
#define SGMII1_RX2_STATUS1_SLOFFX_VAL_BITS                         4
#define SGMII1_RX2_STATUS1_SLOFFX_VAL_SHIFT                        3

/* SGMII1_RX2 :: status1 :: slcal_state [02:00] */
#define Wr_SGMII1_RX2_status1_slcal_state(x) WriteRegBits16(SGMII1_RX2_STATUS1,0x7,0,x)
#define Rd_SGMII1_RX2_status1_slcal_state(x) ReadRegBits16(SGMII1_RX2_STATUS1,0x7,0)
#define SGMII1_RX2_STATUS1_SLCAL_STATE_MASK                        0x0007
#define SGMII1_RX2_STATUS1_SLCAL_STATE_ALIGN                       0
#define SGMII1_RX2_STATUS1_SLCAL_STATE_BITS                        3
#define SGMII1_RX2_STATUS1_SLCAL_STATE_SHIFT                       0


/****************************************************************************
 * SGMII1_RX2 :: status2
 ***************************************************************************/
/* SGMII1_RX2 :: status2 :: lmtcal_acc [15:00] */
#define Wr_SGMII1_RX2_status2_lmtcal_acc(x) WriteReg16(SGMII1_RX2_STATUS2,x)
#define Rd_SGMII1_RX2_status2_lmtcal_acc(x) ReadReg16(SGMII1_RX2_STATUS2)
#define SGMII1_RX2_STATUS2_LMTCAL_ACC_MASK                         0xffff
#define SGMII1_RX2_STATUS2_LMTCAL_ACC_ALIGN                        0
#define SGMII1_RX2_STATUS2_LMTCAL_ACC_BITS                         16
#define SGMII1_RX2_STATUS2_LMTCAL_ACC_SHIFT                        0


/****************************************************************************
 * SGMII1_RX2 :: status3
 ***************************************************************************/
/* SGMII1_RX2 :: status3 :: reserved0 [15:11] */
#define SGMII1_RX2_STATUS3_RESERVED0_MASK                          0xf800
#define SGMII1_RX2_STATUS3_RESERVED0_ALIGN                         0
#define SGMII1_RX2_STATUS3_RESERVED0_BITS                          5
#define SGMII1_RX2_STATUS3_RESERVED0_SHIFT                         11

/* SGMII1_RX2 :: status3 :: lmtcal_state [10:08] */
#define Wr_SGMII1_RX2_status3_lmtcal_state(x) WriteRegBits16(SGMII1_RX2_STATUS3,0x700,8,x)
#define Rd_SGMII1_RX2_status3_lmtcal_state(x) ReadRegBits16(SGMII1_RX2_STATUS3,0x700,8)
#define SGMII1_RX2_STATUS3_LMTCAL_STATE_MASK                       0x0700
#define SGMII1_RX2_STATUS3_LMTCAL_STATE_ALIGN                      0
#define SGMII1_RX2_STATUS3_LMTCAL_STATE_BITS                       3
#define SGMII1_RX2_STATUS3_LMTCAL_STATE_SHIFT                      8

/* SGMII1_RX2 :: status3 :: rx_LA_cal_done [07:07] */
#define Wr_SGMII1_RX2_status3_rx_LA_cal_done(x) WriteRegBits16(SGMII1_RX2_STATUS3,0x80,7,x)
#define Rd_SGMII1_RX2_status3_rx_LA_cal_done(x) ReadRegBits16(SGMII1_RX2_STATUS3,0x80,7)
#define SGMII1_RX2_STATUS3_RX_LA_CAL_DONE_MASK                     0x0080
#define SGMII1_RX2_STATUS3_RX_LA_CAL_DONE_ALIGN                    0
#define SGMII1_RX2_STATUS3_RX_LA_CAL_DONE_BITS                     1
#define SGMII1_RX2_STATUS3_RX_LA_CAL_DONE_SHIFT                    7

/* SGMII1_RX2 :: status3 :: lmtcal_valid [06:06] */
#define Wr_SGMII1_RX2_status3_lmtcal_valid(x) WriteRegBits16(SGMII1_RX2_STATUS3,0x40,6,x)
#define Rd_SGMII1_RX2_status3_lmtcal_valid(x) ReadRegBits16(SGMII1_RX2_STATUS3,0x40,6)
#define SGMII1_RX2_STATUS3_LMTCAL_VALID_MASK                       0x0040
#define SGMII1_RX2_STATUS3_LMTCAL_VALID_ALIGN                      0
#define SGMII1_RX2_STATUS3_LMTCAL_VALID_BITS                       1
#define SGMII1_RX2_STATUS3_LMTCAL_VALID_SHIFT                      6

/* SGMII1_RX2 :: status3 :: lmtcal_adj_cnt [05:01] */
#define Wr_SGMII1_RX2_status3_lmtcal_adj_cnt(x) WriteRegBits16(SGMII1_RX2_STATUS3,0x3e,1,x)
#define Rd_SGMII1_RX2_status3_lmtcal_adj_cnt(x) ReadRegBits16(SGMII1_RX2_STATUS3,0x3e,1)
#define SGMII1_RX2_STATUS3_LMTCAL_ADJ_CNT_MASK                     0x003e
#define SGMII1_RX2_STATUS3_LMTCAL_ADJ_CNT_ALIGN                    0
#define SGMII1_RX2_STATUS3_LMTCAL_ADJ_CNT_BITS                     5
#define SGMII1_RX2_STATUS3_LMTCAL_ADJ_CNT_SHIFT                    1

/* SGMII1_RX2 :: status3 :: recal_ind [00:00] */
#define Wr_SGMII1_RX2_status3_recal_ind(x) WriteRegBits16(SGMII1_RX2_STATUS3,0x1,0,x)
#define Rd_SGMII1_RX2_status3_recal_ind(x) ReadRegBits16(SGMII1_RX2_STATUS3,0x1,0)
#define SGMII1_RX2_STATUS3_RECAL_IND_MASK                          0x0001
#define SGMII1_RX2_STATUS3_RECAL_IND_ALIGN                         0
#define SGMII1_RX2_STATUS3_RECAL_IND_BITS                          1
#define SGMII1_RX2_STATUS3_RECAL_IND_SHIFT                         0


/****************************************************************************
 * SGMII1_RX2 :: status4
 ***************************************************************************/
/* SGMII1_RX2 :: status4 :: em_err_cnt_H [15:00] */
#define Wr_SGMII1_RX2_status4_em_err_cnt_H(x) WriteReg16(SGMII1_RX2_STATUS4,x)
#define Rd_SGMII1_RX2_status4_em_err_cnt_H(x) ReadReg16(SGMII1_RX2_STATUS4)
#define SGMII1_RX2_STATUS4_EM_ERR_CNT_H_MASK                       0xffff
#define SGMII1_RX2_STATUS4_EM_ERR_CNT_H_ALIGN                      0
#define SGMII1_RX2_STATUS4_EM_ERR_CNT_H_BITS                       16
#define SGMII1_RX2_STATUS4_EM_ERR_CNT_H_SHIFT                      0


/****************************************************************************
 * SGMII1_RX2 :: status5
 ***************************************************************************/
/* SGMII1_RX2 :: status5 :: em_err_cnt_L [15:00] */
#define Wr_SGMII1_RX2_status5_em_err_cnt_L(x) WriteReg16(SGMII1_RX2_STATUS5,x)
#define Rd_SGMII1_RX2_status5_em_err_cnt_L(x) ReadReg16(SGMII1_RX2_STATUS5)
#define SGMII1_RX2_STATUS5_EM_ERR_CNT_L_MASK                       0xffff
#define SGMII1_RX2_STATUS5_EM_ERR_CNT_L_ALIGN                      0
#define SGMII1_RX2_STATUS5_EM_ERR_CNT_L_BITS                       16
#define SGMII1_RX2_STATUS5_EM_ERR_CNT_L_SHIFT                      0


/****************************************************************************
 * SGMII1_RX2 :: status6
 ***************************************************************************/
/* SGMII1_RX2 :: status6 :: rx_phs_interp_status [15:00] */
#define Wr_SGMII1_RX2_status6_rx_phs_interp_status(x) WriteReg16(SGMII1_RX2_STATUS6,x)
#define Rd_SGMII1_RX2_status6_rx_phs_interp_status(x) ReadReg16(SGMII1_RX2_STATUS6)
#define SGMII1_RX2_STATUS6_RX_PHS_INTERP_STATUS_MASK               0xffff
#define SGMII1_RX2_STATUS6_RX_PHS_INTERP_STATUS_ALIGN              0
#define SGMII1_RX2_STATUS6_RX_PHS_INTERP_STATUS_BITS               16
#define SGMII1_RX2_STATUS6_RX_PHS_INTERP_STATUS_SHIFT              0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_RX3
 ***************************************************************************/
/****************************************************************************
 * SGMII1_RX3 :: control0
 ***************************************************************************/
/* SGMII1_RX3 :: control0 :: lmtcal_max_adj [15:11] */
#define Wr_SGMII1_RX3_control0_lmtcal_max_adj(x) WriteRegBits16(SGMII1_RX3_CONTROL0,0xf800,11,x)
#define Rd_SGMII1_RX3_control0_lmtcal_max_adj(x) ReadRegBits16(SGMII1_RX3_CONTROL0,0xf800,11)
#define SGMII1_RX3_CONTROL0_LMTCAL_MAX_ADJ_MASK                    0xf800
#define SGMII1_RX3_CONTROL0_LMTCAL_MAX_ADJ_ALIGN                   0
#define SGMII1_RX3_CONTROL0_LMTCAL_MAX_ADJ_BITS                    5
#define SGMII1_RX3_CONTROL0_LMTCAL_MAX_ADJ_SHIFT                   11

/* SGMII1_RX3 :: control0 :: lmtcal_intv_time [10:00] */
#define Wr_SGMII1_RX3_control0_lmtcal_intv_time(x) WriteRegBits16(SGMII1_RX3_CONTROL0,0x7ff,0,x)
#define Rd_SGMII1_RX3_control0_lmtcal_intv_time(x) ReadRegBits16(SGMII1_RX3_CONTROL0,0x7ff,0)
#define SGMII1_RX3_CONTROL0_LMTCAL_INTV_TIME_MASK                  0x07ff
#define SGMII1_RX3_CONTROL0_LMTCAL_INTV_TIME_ALIGN                 0
#define SGMII1_RX3_CONTROL0_LMTCAL_INTV_TIME_BITS                  11
#define SGMII1_RX3_CONTROL0_LMTCAL_INTV_TIME_SHIFT                 0


/****************************************************************************
 * SGMII1_RX3 :: control1
 ***************************************************************************/
/* SGMII1_RX3 :: control1 :: lmtcal_falling_edge_en [15:15] */
#define Wr_SGMII1_RX3_control1_lmtcal_falling_edge_en(x) WriteRegBits16(SGMII1_RX3_CONTROL1,0x8000,15,x)
#define Rd_SGMII1_RX3_control1_lmtcal_falling_edge_en(x) ReadRegBits16(SGMII1_RX3_CONTROL1,0x8000,15)
#define SGMII1_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_MASK            0x8000
#define SGMII1_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_ALIGN           0
#define SGMII1_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_BITS            1
#define SGMII1_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_SHIFT           15

/* SGMII1_RX3 :: control1 :: lmtcal_rising_edge_en [14:14] */
#define Wr_SGMII1_RX3_control1_lmtcal_rising_edge_en(x) WriteRegBits16(SGMII1_RX3_CONTROL1,0x4000,14,x)
#define Rd_SGMII1_RX3_control1_lmtcal_rising_edge_en(x) ReadRegBits16(SGMII1_RX3_CONTROL1,0x4000,14)
#define SGMII1_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_MASK             0x4000
#define SGMII1_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_ALIGN            0
#define SGMII1_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_BITS             1
#define SGMII1_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_SHIFT            14

/* SGMII1_RX3 :: control1 :: lmtcal_kp [13:12] */
#define Wr_SGMII1_RX3_control1_lmtcal_kp(x) WriteRegBits16(SGMII1_RX3_CONTROL1,0x3000,12,x)
#define Rd_SGMII1_RX3_control1_lmtcal_kp(x) ReadRegBits16(SGMII1_RX3_CONTROL1,0x3000,12)
#define SGMII1_RX3_CONTROL1_LMTCAL_KP_MASK                         0x3000
#define SGMII1_RX3_CONTROL1_LMTCAL_KP_ALIGN                        0
#define SGMII1_RX3_CONTROL1_LMTCAL_KP_BITS                         2
#define SGMII1_RX3_CONTROL1_LMTCAL_KP_SHIFT                        12

/* SGMII1_RX3 :: control1 :: lmtcal_adj_dir [11:11] */
#define Wr_SGMII1_RX3_control1_lmtcal_adj_dir(x) WriteRegBits16(SGMII1_RX3_CONTROL1,0x800,11,x)
#define Rd_SGMII1_RX3_control1_lmtcal_adj_dir(x) ReadRegBits16(SGMII1_RX3_CONTROL1,0x800,11)
#define SGMII1_RX3_CONTROL1_LMTCAL_ADJ_DIR_MASK                    0x0800
#define SGMII1_RX3_CONTROL1_LMTCAL_ADJ_DIR_ALIGN                   0
#define SGMII1_RX3_CONTROL1_LMTCAL_ADJ_DIR_BITS                    1
#define SGMII1_RX3_CONTROL1_LMTCAL_ADJ_DIR_SHIFT                   11

/* SGMII1_RX3 :: control1 :: lmtcal_init_time [10:00] */
#define Wr_SGMII1_RX3_control1_lmtcal_init_time(x) WriteRegBits16(SGMII1_RX3_CONTROL1,0x7ff,0,x)
#define Rd_SGMII1_RX3_control1_lmtcal_init_time(x) ReadRegBits16(SGMII1_RX3_CONTROL1,0x7ff,0)
#define SGMII1_RX3_CONTROL1_LMTCAL_INIT_TIME_MASK                  0x07ff
#define SGMII1_RX3_CONTROL1_LMTCAL_INIT_TIME_ALIGN                 0
#define SGMII1_RX3_CONTROL1_LMTCAL_INIT_TIME_BITS                  11
#define SGMII1_RX3_CONTROL1_LMTCAL_INIT_TIME_SHIFT                 0


/****************************************************************************
 * SGMII1_RX3 :: control2
 ***************************************************************************/
/* SGMII1_RX3 :: control2 :: lmtcal_pd_polarity [15:15] */
#define Wr_SGMII1_RX3_control2_lmtcal_pd_polarity(x) WriteRegBits16(SGMII1_RX3_CONTROL2,0x8000,15,x)
#define Rd_SGMII1_RX3_control2_lmtcal_pd_polarity(x) ReadRegBits16(SGMII1_RX3_CONTROL2,0x8000,15)
#define SGMII1_RX3_CONTROL2_LMTCAL_PD_POLARITY_MASK                0x8000
#define SGMII1_RX3_CONTROL2_LMTCAL_PD_POLARITY_ALIGN               0
#define SGMII1_RX3_CONTROL2_LMTCAL_PD_POLARITY_BITS                1
#define SGMII1_RX3_CONTROL2_LMTCAL_PD_POLARITY_SHIFT               15

/* SGMII1_RX3 :: control2 :: lmtcal_acc_time [14:04] */
#define Wr_SGMII1_RX3_control2_lmtcal_acc_time(x) WriteRegBits16(SGMII1_RX3_CONTROL2,0x7ff0,4,x)
#define Rd_SGMII1_RX3_control2_lmtcal_acc_time(x) ReadRegBits16(SGMII1_RX3_CONTROL2,0x7ff0,4)
#define SGMII1_RX3_CONTROL2_LMTCAL_ACC_TIME_MASK                   0x7ff0
#define SGMII1_RX3_CONTROL2_LMTCAL_ACC_TIME_ALIGN                  0
#define SGMII1_RX3_CONTROL2_LMTCAL_ACC_TIME_BITS                   11
#define SGMII1_RX3_CONTROL2_LMTCAL_ACC_TIME_SHIFT                  4

/* SGMII1_RX3 :: control2 :: lmtcal_en_ovrd [03:03] */
#define Wr_SGMII1_RX3_control2_lmtcal_en_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL2,0x8,3,x)
#define Rd_SGMII1_RX3_control2_lmtcal_en_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL2,0x8,3)
#define SGMII1_RX3_CONTROL2_LMTCAL_EN_OVRD_MASK                    0x0008
#define SGMII1_RX3_CONTROL2_LMTCAL_EN_OVRD_ALIGN                   0
#define SGMII1_RX3_CONTROL2_LMTCAL_EN_OVRD_BITS                    1
#define SGMII1_RX3_CONTROL2_LMTCAL_EN_OVRD_SHIFT                   3

/* SGMII1_RX3 :: control2 :: lmtcal_en_ovrd_val [02:02] */
#define Wr_SGMII1_RX3_control2_lmtcal_en_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL2,0x4,2,x)
#define Rd_SGMII1_RX3_control2_lmtcal_en_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL2,0x4,2)
#define SGMII1_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_MASK                0x0004
#define SGMII1_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_ALIGN               0
#define SGMII1_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_BITS                1
#define SGMII1_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_SHIFT               2

/* SGMII1_RX3 :: control2 :: lmtcal_done_ovrd [01:01] */
#define Wr_SGMII1_RX3_control2_lmtcal_done_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL2,0x2,1,x)
#define Rd_SGMII1_RX3_control2_lmtcal_done_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL2,0x2,1)
#define SGMII1_RX3_CONTROL2_LMTCAL_DONE_OVRD_MASK                  0x0002
#define SGMII1_RX3_CONTROL2_LMTCAL_DONE_OVRD_ALIGN                 0
#define SGMII1_RX3_CONTROL2_LMTCAL_DONE_OVRD_BITS                  1
#define SGMII1_RX3_CONTROL2_LMTCAL_DONE_OVRD_SHIFT                 1

/* SGMII1_RX3 :: control2 :: lmtcal_done_ovrd_val [00:00] */
#define Wr_SGMII1_RX3_control2_lmtcal_done_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL2,0x1,0,x)
#define Rd_SGMII1_RX3_control2_lmtcal_done_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL2,0x1,0)
#define SGMII1_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_MASK              0x0001
#define SGMII1_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_ALIGN             0
#define SGMII1_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_BITS              1
#define SGMII1_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_SHIFT             0


/****************************************************************************
 * SGMII1_RX3 :: control3
 ***************************************************************************/
/* SGMII1_RX3 :: control3 :: recal_pos_thres [15:00] */
#define Wr_SGMII1_RX3_control3_recal_pos_thres(x) WriteReg16(SGMII1_RX3_CONTROL3,x)
#define Rd_SGMII1_RX3_control3_recal_pos_thres(x) ReadReg16(SGMII1_RX3_CONTROL3)
#define SGMII1_RX3_CONTROL3_RECAL_POS_THRES_MASK                   0xffff
#define SGMII1_RX3_CONTROL3_RECAL_POS_THRES_ALIGN                  0
#define SGMII1_RX3_CONTROL3_RECAL_POS_THRES_BITS                   16
#define SGMII1_RX3_CONTROL3_RECAL_POS_THRES_SHIFT                  0


/****************************************************************************
 * SGMII1_RX3 :: control4
 ***************************************************************************/
/* SGMII1_RX3 :: control4 :: recal_neg_thres [15:00] */
#define Wr_SGMII1_RX3_control4_recal_neg_thres(x) WriteReg16(SGMII1_RX3_CONTROL4,x)
#define Rd_SGMII1_RX3_control4_recal_neg_thres(x) ReadReg16(SGMII1_RX3_CONTROL4)
#define SGMII1_RX3_CONTROL4_RECAL_NEG_THRES_MASK                   0xffff
#define SGMII1_RX3_CONTROL4_RECAL_NEG_THRES_ALIGN                  0
#define SGMII1_RX3_CONTROL4_RECAL_NEG_THRES_BITS                   16
#define SGMII1_RX3_CONTROL4_RECAL_NEG_THRES_SHIFT                  0


/****************************************************************************
 * SGMII1_RX3 :: control5
 ***************************************************************************/
/* SGMII1_RX3 :: control5 :: reserved0 [15:12] */
#define SGMII1_RX3_CONTROL5_RESERVED0_MASK                         0xf000
#define SGMII1_RX3_CONTROL5_RESERVED0_ALIGN                        0
#define SGMII1_RX3_CONTROL5_RESERVED0_BITS                         4
#define SGMII1_RX3_CONTROL5_RESERVED0_SHIFT                        12

/* SGMII1_RX3 :: control5 :: lmtcal_cont_acc_time [11:01] */
#define Wr_SGMII1_RX3_control5_lmtcal_cont_acc_time(x) WriteRegBits16(SGMII1_RX3_CONTROL5,0xffe,1,x)
#define Rd_SGMII1_RX3_control5_lmtcal_cont_acc_time(x) ReadRegBits16(SGMII1_RX3_CONTROL5,0xffe,1)
#define SGMII1_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_MASK              0x0ffe
#define SGMII1_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_ALIGN             0
#define SGMII1_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_BITS              11
#define SGMII1_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_SHIFT             1

/* SGMII1_RX3 :: control5 :: cont_lmtcal_en [00:00] */
#define Wr_SGMII1_RX3_control5_cont_lmtcal_en(x) WriteRegBits16(SGMII1_RX3_CONTROL5,0x1,0,x)
#define Rd_SGMII1_RX3_control5_cont_lmtcal_en(x) ReadRegBits16(SGMII1_RX3_CONTROL5,0x1,0)
#define SGMII1_RX3_CONTROL5_CONT_LMTCAL_EN_MASK                    0x0001
#define SGMII1_RX3_CONTROL5_CONT_LMTCAL_EN_ALIGN                   0
#define SGMII1_RX3_CONTROL5_CONT_LMTCAL_EN_BITS                    1
#define SGMII1_RX3_CONTROL5_CONT_LMTCAL_EN_SHIFT                   0


/****************************************************************************
 * SGMII1_RX3 :: control6
 ***************************************************************************/
/* SGMII1_RX3 :: control6 :: reserved0 [15:12] */
#define SGMII1_RX3_CONTROL6_RESERVED0_MASK                         0xf000
#define SGMII1_RX3_CONTROL6_RESERVED0_ALIGN                        0
#define SGMII1_RX3_CONTROL6_RESERVED0_BITS                         4
#define SGMII1_RX3_CONTROL6_RESERVED0_SHIFT                        12

/* SGMII1_RX3 :: control6 :: lmtcal_interval_time [11:07] */
#define Wr_SGMII1_RX3_control6_lmtcal_interval_time(x) WriteRegBits16(SGMII1_RX3_CONTROL6,0xf80,7,x)
#define Rd_SGMII1_RX3_control6_lmtcal_interval_time(x) ReadRegBits16(SGMII1_RX3_CONTROL6,0xf80,7)
#define SGMII1_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_MASK              0x0f80
#define SGMII1_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_ALIGN             0
#define SGMII1_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_BITS              5
#define SGMII1_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_SHIFT             7

/* SGMII1_RX3 :: control6 :: rx_lmtoff_ovrd [06:06] */
#define Wr_SGMII1_RX3_control6_rx_lmtoff_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL6,0x40,6,x)
#define Rd_SGMII1_RX3_control6_rx_lmtoff_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL6,0x40,6)
#define SGMII1_RX3_CONTROL6_RX_LMTOFF_OVRD_MASK                    0x0040
#define SGMII1_RX3_CONTROL6_RX_LMTOFF_OVRD_ALIGN                   0
#define SGMII1_RX3_CONTROL6_RX_LMTOFF_OVRD_BITS                    1
#define SGMII1_RX3_CONTROL6_RX_LMTOFF_OVRD_SHIFT                   6

/* SGMII1_RX3 :: control6 :: rx_lmtoff_ovrd_val [05:00] */
#define Wr_SGMII1_RX3_control6_rx_lmtoff_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL6,0x3f,0,x)
#define Rd_SGMII1_RX3_control6_rx_lmtoff_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL6,0x3f,0)
#define SGMII1_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_MASK                0x003f
#define SGMII1_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_ALIGN               0
#define SGMII1_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_BITS                6
#define SGMII1_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_SHIFT               0


/****************************************************************************
 * SGMII1_RX3 :: control7
 ***************************************************************************/
/* SGMII1_RX3 :: control7 :: cal_state_ovrd [15:15] */
#define Wr_SGMII1_RX3_control7_cal_state_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL7,0x8000,15,x)
#define Rd_SGMII1_RX3_control7_cal_state_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL7,0x8000,15)
#define SGMII1_RX3_CONTROL7_CAL_STATE_OVRD_MASK                    0x8000
#define SGMII1_RX3_CONTROL7_CAL_STATE_OVRD_ALIGN                   0
#define SGMII1_RX3_CONTROL7_CAL_STATE_OVRD_BITS                    1
#define SGMII1_RX3_CONTROL7_CAL_STATE_OVRD_SHIFT                   15

/* SGMII1_RX3 :: control7 :: slcal_en_ovrd [14:14] */
#define Wr_SGMII1_RX3_control7_slcal_en_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL7,0x4000,14,x)
#define Rd_SGMII1_RX3_control7_slcal_en_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL7,0x4000,14)
#define SGMII1_RX3_CONTROL7_SLCAL_EN_OVRD_MASK                     0x4000
#define SGMII1_RX3_CONTROL7_SLCAL_EN_OVRD_ALIGN                    0
#define SGMII1_RX3_CONTROL7_SLCAL_EN_OVRD_BITS                     1
#define SGMII1_RX3_CONTROL7_SLCAL_EN_OVRD_SHIFT                    14

/* SGMII1_RX3 :: control7 :: slcal_en_ovrd_val [13:13] */
#define Wr_SGMII1_RX3_control7_slcal_en_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL7,0x2000,13,x)
#define Rd_SGMII1_RX3_control7_slcal_en_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL7,0x2000,13)
#define SGMII1_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_MASK                 0x2000
#define SGMII1_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_ALIGN                0
#define SGMII1_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_BITS                 1
#define SGMII1_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_SHIFT                13

/* SGMII1_RX3 :: control7 :: slcal_acc_opt [12:11] */
#define Wr_SGMII1_RX3_control7_slcal_acc_opt(x) WriteRegBits16(SGMII1_RX3_CONTROL7,0x1800,11,x)
#define Rd_SGMII1_RX3_control7_slcal_acc_opt(x) ReadRegBits16(SGMII1_RX3_CONTROL7,0x1800,11)
#define SGMII1_RX3_CONTROL7_SLCAL_ACC_OPT_MASK                     0x1800
#define SGMII1_RX3_CONTROL7_SLCAL_ACC_OPT_ALIGN                    0
#define SGMII1_RX3_CONTROL7_SLCAL_ACC_OPT_BITS                     2
#define SGMII1_RX3_CONTROL7_SLCAL_ACC_OPT_SHIFT                    11

/* SGMII1_RX3 :: control7 :: slcal_pol [10:10] */
#define Wr_SGMII1_RX3_control7_slcal_pol(x) WriteRegBits16(SGMII1_RX3_CONTROL7,0x400,10,x)
#define Rd_SGMII1_RX3_control7_slcal_pol(x) ReadRegBits16(SGMII1_RX3_CONTROL7,0x400,10)
#define SGMII1_RX3_CONTROL7_SLCAL_POL_MASK                         0x0400
#define SGMII1_RX3_CONTROL7_SLCAL_POL_ALIGN                        0
#define SGMII1_RX3_CONTROL7_SLCAL_POL_BITS                         1
#define SGMII1_RX3_CONTROL7_SLCAL_POL_SHIFT                        10

/* SGMII1_RX3 :: control7 :: reserved0 [09:02] */
#define SGMII1_RX3_CONTROL7_RESERVED0_MASK                         0x03fc
#define SGMII1_RX3_CONTROL7_RESERVED0_ALIGN                        0
#define SGMII1_RX3_CONTROL7_RESERVED0_BITS                         8
#define SGMII1_RX3_CONTROL7_RESERVED0_SHIFT                        2

/* SGMII1_RX3 :: control7 :: slcal_valid_ovrd [01:01] */
#define Wr_SGMII1_RX3_control7_slcal_valid_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL7,0x2,1,x)
#define Rd_SGMII1_RX3_control7_slcal_valid_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL7,0x2,1)
#define SGMII1_RX3_CONTROL7_SLCAL_VALID_OVRD_MASK                  0x0002
#define SGMII1_RX3_CONTROL7_SLCAL_VALID_OVRD_ALIGN                 0
#define SGMII1_RX3_CONTROL7_SLCAL_VALID_OVRD_BITS                  1
#define SGMII1_RX3_CONTROL7_SLCAL_VALID_OVRD_SHIFT                 1

/* SGMII1_RX3 :: control7 :: slcal_valid_ovrd_val [00:00] */
#define Wr_SGMII1_RX3_control7_slcal_valid_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL7,0x1,0,x)
#define Rd_SGMII1_RX3_control7_slcal_valid_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL7,0x1,0)
#define SGMII1_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_MASK              0x0001
#define SGMII1_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_ALIGN             0
#define SGMII1_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_BITS              1
#define SGMII1_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_SHIFT             0


/****************************************************************************
 * SGMII1_RX3 :: control8
 ***************************************************************************/
/* SGMII1_RX3 :: control8 :: reserved0 [15:15] */
#define SGMII1_RX3_CONTROL8_RESERVED0_MASK                         0x8000
#define SGMII1_RX3_CONTROL8_RESERVED0_ALIGN                        0
#define SGMII1_RX3_CONTROL8_RESERVED0_BITS                         1
#define SGMII1_RX3_CONTROL8_RESERVED0_SHIFT                        15

/* SGMII1_RX3 :: control8 :: rx_sloff2_ovrd [14:14] */
#define Wr_SGMII1_RX3_control8_rx_sloff2_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL8,0x4000,14,x)
#define Rd_SGMII1_RX3_control8_rx_sloff2_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL8,0x4000,14)
#define SGMII1_RX3_CONTROL8_RX_SLOFF2_OVRD_MASK                    0x4000
#define SGMII1_RX3_CONTROL8_RX_SLOFF2_OVRD_ALIGN                   0
#define SGMII1_RX3_CONTROL8_RX_SLOFF2_OVRD_BITS                    1
#define SGMII1_RX3_CONTROL8_RX_SLOFF2_OVRD_SHIFT                   14

/* SGMII1_RX3 :: control8 :: rx_sloff2_ovrd_val [13:10] */
#define Wr_SGMII1_RX3_control8_rx_sloff2_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL8,0x3c00,10,x)
#define Rd_SGMII1_RX3_control8_rx_sloff2_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL8,0x3c00,10)
#define SGMII1_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_MASK                0x3c00
#define SGMII1_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_ALIGN               0
#define SGMII1_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_BITS                4
#define SGMII1_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_SHIFT               10

/* SGMII1_RX3 :: control8 :: rx_sloff1_ovrd [09:09] */
#define Wr_SGMII1_RX3_control8_rx_sloff1_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL8,0x200,9,x)
#define Rd_SGMII1_RX3_control8_rx_sloff1_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL8,0x200,9)
#define SGMII1_RX3_CONTROL8_RX_SLOFF1_OVRD_MASK                    0x0200
#define SGMII1_RX3_CONTROL8_RX_SLOFF1_OVRD_ALIGN                   0
#define SGMII1_RX3_CONTROL8_RX_SLOFF1_OVRD_BITS                    1
#define SGMII1_RX3_CONTROL8_RX_SLOFF1_OVRD_SHIFT                   9

/* SGMII1_RX3 :: control8 :: rx_sloff1_ovrd_val [08:05] */
#define Wr_SGMII1_RX3_control8_rx_sloff1_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL8,0x1e0,5,x)
#define Rd_SGMII1_RX3_control8_rx_sloff1_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL8,0x1e0,5)
#define SGMII1_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_MASK                0x01e0
#define SGMII1_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_ALIGN               0
#define SGMII1_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_BITS                4
#define SGMII1_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_SHIFT               5

/* SGMII1_RX3 :: control8 :: rx_sloff0_ovrd [04:04] */
#define Wr_SGMII1_RX3_control8_rx_sloff0_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL8,0x10,4,x)
#define Rd_SGMII1_RX3_control8_rx_sloff0_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL8,0x10,4)
#define SGMII1_RX3_CONTROL8_RX_SLOFF0_OVRD_MASK                    0x0010
#define SGMII1_RX3_CONTROL8_RX_SLOFF0_OVRD_ALIGN                   0
#define SGMII1_RX3_CONTROL8_RX_SLOFF0_OVRD_BITS                    1
#define SGMII1_RX3_CONTROL8_RX_SLOFF0_OVRD_SHIFT                   4

/* SGMII1_RX3 :: control8 :: rx_sloff0_ovrd_val [03:00] */
#define Wr_SGMII1_RX3_control8_rx_sloff0_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL8,0xf,0,x)
#define Rd_SGMII1_RX3_control8_rx_sloff0_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL8,0xf,0)
#define SGMII1_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_MASK                0x000f
#define SGMII1_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_ALIGN               0
#define SGMII1_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_BITS                4
#define SGMII1_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_SHIFT               0


/****************************************************************************
 * SGMII1_RX3 :: control9
 ***************************************************************************/
/* SGMII1_RX3 :: control9 :: cal_state_ovrd_val [15:13] */
#define Wr_SGMII1_RX3_control9_cal_state_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL9,0xe000,13,x)
#define Rd_SGMII1_RX3_control9_cal_state_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL9,0xe000,13)
#define SGMII1_RX3_CONTROL9_CAL_STATE_OVRD_VAL_MASK                0xe000
#define SGMII1_RX3_CONTROL9_CAL_STATE_OVRD_VAL_ALIGN               0
#define SGMII1_RX3_CONTROL9_CAL_STATE_OVRD_VAL_BITS                3
#define SGMII1_RX3_CONTROL9_CAL_STATE_OVRD_VAL_SHIFT               13

/* SGMII1_RX3 :: control9 :: rx_slicer_calvalid_ovrd [12:12] */
#define Wr_SGMII1_RX3_control9_rx_slicer_calvalid_ovrd(x) WriteRegBits16(SGMII1_RX3_CONTROL9,0x1000,12,x)
#define Rd_SGMII1_RX3_control9_rx_slicer_calvalid_ovrd(x) ReadRegBits16(SGMII1_RX3_CONTROL9,0x1000,12)
#define SGMII1_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_MASK           0x1000
#define SGMII1_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_ALIGN          0
#define SGMII1_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_BITS           1
#define SGMII1_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_SHIFT          12

/* SGMII1_RX3 :: control9 :: rx_slicer_calvalid_ovrd_val [11:11] */
#define Wr_SGMII1_RX3_control9_rx_slicer_calvalid_ovrd_val(x) WriteRegBits16(SGMII1_RX3_CONTROL9,0x800,11,x)
#define Rd_SGMII1_RX3_control9_rx_slicer_calvalid_ovrd_val(x) ReadRegBits16(SGMII1_RX3_CONTROL9,0x800,11)
#define SGMII1_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_MASK       0x0800
#define SGMII1_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_ALIGN      0
#define SGMII1_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_BITS       1
#define SGMII1_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_SHIFT      11

/* SGMII1_RX3 :: control9 :: slcal_up_thres [10:00] */
#define Wr_SGMII1_RX3_control9_slcal_up_thres(x) WriteRegBits16(SGMII1_RX3_CONTROL9,0x7ff,0,x)
#define Rd_SGMII1_RX3_control9_slcal_up_thres(x) ReadRegBits16(SGMII1_RX3_CONTROL9,0x7ff,0)
#define SGMII1_RX3_CONTROL9_SLCAL_UP_THRES_MASK                    0x07ff
#define SGMII1_RX3_CONTROL9_SLCAL_UP_THRES_ALIGN                   0
#define SGMII1_RX3_CONTROL9_SLCAL_UP_THRES_BITS                    11
#define SGMII1_RX3_CONTROL9_SLCAL_UP_THRES_SHIFT                   0


/****************************************************************************
 * SGMII1_RX3 :: control10
 ***************************************************************************/
/* SGMII1_RX3 :: control10 :: slicer_interval_time [15:11] */
#define Wr_SGMII1_RX3_control10_slicer_interval_time(x) WriteRegBits16(SGMII1_RX3_CONTROL10,0xf800,11,x)
#define Rd_SGMII1_RX3_control10_slicer_interval_time(x) ReadRegBits16(SGMII1_RX3_CONTROL10,0xf800,11)
#define SGMII1_RX3_CONTROL10_SLICER_INTERVAL_TIME_MASK             0xf800
#define SGMII1_RX3_CONTROL10_SLICER_INTERVAL_TIME_ALIGN            0
#define SGMII1_RX3_CONTROL10_SLICER_INTERVAL_TIME_BITS             5
#define SGMII1_RX3_CONTROL10_SLICER_INTERVAL_TIME_SHIFT            11

/* SGMII1_RX3 :: control10 :: slcal_dn_thres [10:00] */
#define Wr_SGMII1_RX3_control10_slcal_dn_thres(x) WriteRegBits16(SGMII1_RX3_CONTROL10,0x7ff,0,x)
#define Rd_SGMII1_RX3_control10_slcal_dn_thres(x) ReadRegBits16(SGMII1_RX3_CONTROL10,0x7ff,0)
#define SGMII1_RX3_CONTROL10_SLCAL_DN_THRES_MASK                   0x07ff
#define SGMII1_RX3_CONTROL10_SLCAL_DN_THRES_ALIGN                  0
#define SGMII1_RX3_CONTROL10_SLCAL_DN_THRES_BITS                   11
#define SGMII1_RX3_CONTROL10_SLCAL_DN_THRES_SHIFT                  0


/****************************************************************************
 * SGMII1_RX3 :: control11
 ***************************************************************************/
/* SGMII1_RX3 :: control11 :: recal_ind_clr [15:15] */
#define Wr_SGMII1_RX3_control11_recal_ind_clr(x) WriteRegBits16(SGMII1_RX3_CONTROL11,0x8000,15,x)
#define Rd_SGMII1_RX3_control11_recal_ind_clr(x) ReadRegBits16(SGMII1_RX3_CONTROL11,0x8000,15)
#define SGMII1_RX3_CONTROL11_RECAL_IND_CLR_MASK                    0x8000
#define SGMII1_RX3_CONTROL11_RECAL_IND_CLR_ALIGN                   0
#define SGMII1_RX3_CONTROL11_RECAL_IND_CLR_BITS                    1
#define SGMII1_RX3_CONTROL11_RECAL_IND_CLR_SHIFT                   15

/* SGMII1_RX3 :: control11 :: slcal_init_time [14:07] */
#define Wr_SGMII1_RX3_control11_slcal_init_time(x) WriteRegBits16(SGMII1_RX3_CONTROL11,0x7f80,7,x)
#define Rd_SGMII1_RX3_control11_slcal_init_time(x) ReadRegBits16(SGMII1_RX3_CONTROL11,0x7f80,7)
#define SGMII1_RX3_CONTROL11_SLCAL_INIT_TIME_MASK                  0x7f80
#define SGMII1_RX3_CONTROL11_SLCAL_INIT_TIME_ALIGN                 0
#define SGMII1_RX3_CONTROL11_SLCAL_INIT_TIME_BITS                  8
#define SGMII1_RX3_CONTROL11_SLCAL_INIT_TIME_SHIFT                 7

/* SGMII1_RX3 :: control11 :: reserved0 [06:02] */
#define SGMII1_RX3_CONTROL11_RESERVED0_MASK                        0x007c
#define SGMII1_RX3_CONTROL11_RESERVED0_ALIGN                       0
#define SGMII1_RX3_CONTROL11_RESERVED0_BITS                        5
#define SGMII1_RX3_CONTROL11_RESERVED0_SHIFT                       2

/* SGMII1_RX3 :: control11 :: pm_RxSlicerCalByp [01:01] */
#define Wr_SGMII1_RX3_control11_pm_RxSlicerCalByp(x) WriteRegBits16(SGMII1_RX3_CONTROL11,0x2,1,x)
#define Rd_SGMII1_RX3_control11_pm_RxSlicerCalByp(x) ReadRegBits16(SGMII1_RX3_CONTROL11,0x2,1)
#define SGMII1_RX3_CONTROL11_PM_RXSLICERCALBYP_MASK                0x0002
#define SGMII1_RX3_CONTROL11_PM_RXSLICERCALBYP_ALIGN               0
#define SGMII1_RX3_CONTROL11_PM_RXSLICERCALBYP_BITS                1
#define SGMII1_RX3_CONTROL11_PM_RXSLICERCALBYP_SHIFT               1

/* SGMII1_RX3 :: control11 :: pm_RxLimitAmpCalByp [00:00] */
#define Wr_SGMII1_RX3_control11_pm_RxLimitAmpCalByp(x) WriteRegBits16(SGMII1_RX3_CONTROL11,0x1,0,x)
#define Rd_SGMII1_RX3_control11_pm_RxLimitAmpCalByp(x) ReadRegBits16(SGMII1_RX3_CONTROL11,0x1,0)
#define SGMII1_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_MASK              0x0001
#define SGMII1_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_ALIGN             0
#define SGMII1_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_BITS              1
#define SGMII1_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_SHIFT             0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE1_SGMII1_Combo_IEEE0
 ***************************************************************************/
/****************************************************************************
 * SGMII1_Combo_IEEE0 :: MIICntl
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: MIICntl :: rst_hw [15:15] */
#define Wr_SGMII1_Combo_IEEE0_MIICntl_rst_hw(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x8000,15,x)
#define Rd_SGMII1_Combo_IEEE0_MIICntl_rst_hw(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x8000,15)
#define SGMII1_COMBO_IEEE0_MIICNTL_RST_HW_MASK                     0x8000
#define SGMII1_COMBO_IEEE0_MIICNTL_RST_HW_ALIGN                    0
#define SGMII1_COMBO_IEEE0_MIICNTL_RST_HW_BITS                     1
#define SGMII1_COMBO_IEEE0_MIICNTL_RST_HW_SHIFT                    15

/* SGMII1_Combo_IEEE0 :: MIICntl :: gloopback [14:14] */
#define Wr_SGMII1_Combo_IEEE0_MIICntl_gloopback(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x4000,14,x)
#define Rd_SGMII1_Combo_IEEE0_MIICntl_gloopback(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x4000,14)
#define SGMII1_COMBO_IEEE0_MIICNTL_GLOOPBACK_MASK                  0x4000
#define SGMII1_COMBO_IEEE0_MIICNTL_GLOOPBACK_ALIGN                 0
#define SGMII1_COMBO_IEEE0_MIICNTL_GLOOPBACK_BITS                  1
#define SGMII1_COMBO_IEEE0_MIICNTL_GLOOPBACK_SHIFT                 14

/* SGMII1_Combo_IEEE0 :: MIICntl :: manual_speed0 [13:13] */
#define Wr_SGMII1_Combo_IEEE0_MIICntl_manual_speed0(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x2000,13,x)
#define Rd_SGMII1_Combo_IEEE0_MIICntl_manual_speed0(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x2000,13)
#define SGMII1_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_MASK              0x2000
#define SGMII1_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_ALIGN             0
#define SGMII1_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_BITS              1
#define SGMII1_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_SHIFT             13

/* SGMII1_Combo_IEEE0 :: MIICntl :: autoneg_enable [12:12] */
#define Wr_SGMII1_Combo_IEEE0_MIICntl_autoneg_enable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x1000,12,x)
#define Rd_SGMII1_Combo_IEEE0_MIICntl_autoneg_enable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x1000,12)
#define SGMII1_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_MASK             0x1000
#define SGMII1_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_ALIGN            0
#define SGMII1_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_BITS             1
#define SGMII1_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_SHIFT            12

/* SGMII1_Combo_IEEE0 :: MIICntl :: pwrdwn_sw [11:11] */
#define Wr_SGMII1_Combo_IEEE0_MIICntl_pwrdwn_sw(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x800,11,x)
#define Rd_SGMII1_Combo_IEEE0_MIICntl_pwrdwn_sw(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x800,11)
#define SGMII1_COMBO_IEEE0_MIICNTL_PWRDWN_SW_MASK                  0x0800
#define SGMII1_COMBO_IEEE0_MIICNTL_PWRDWN_SW_ALIGN                 0
#define SGMII1_COMBO_IEEE0_MIICNTL_PWRDWN_SW_BITS                  1
#define SGMII1_COMBO_IEEE0_MIICNTL_PWRDWN_SW_SHIFT                 11

/* SGMII1_Combo_IEEE0 :: MIICntl :: reserved0 [10:10] */
#define SGMII1_COMBO_IEEE0_MIICNTL_RESERVED0_MASK                  0x0400
#define SGMII1_COMBO_IEEE0_MIICNTL_RESERVED0_ALIGN                 0
#define SGMII1_COMBO_IEEE0_MIICNTL_RESERVED0_BITS                  1
#define SGMII1_COMBO_IEEE0_MIICNTL_RESERVED0_SHIFT                 10

/* SGMII1_Combo_IEEE0 :: MIICntl :: restart_autoneg [09:09] */
#define Wr_SGMII1_Combo_IEEE0_MIICntl_restart_autoneg(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x200,9,x)
#define Rd_SGMII1_Combo_IEEE0_MIICntl_restart_autoneg(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x200,9)
#define SGMII1_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_MASK            0x0200
#define SGMII1_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_ALIGN           0
#define SGMII1_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_BITS            1
#define SGMII1_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_SHIFT           9

/* SGMII1_Combo_IEEE0 :: MIICntl :: full_duplex [08:08] */
#define Wr_SGMII1_Combo_IEEE0_MIICntl_full_duplex(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x100,8,x)
#define Rd_SGMII1_Combo_IEEE0_MIICntl_full_duplex(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x100,8)
#define SGMII1_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_MASK                0x0100
#define SGMII1_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_ALIGN               0
#define SGMII1_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_BITS                1
#define SGMII1_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_SHIFT               8

/* SGMII1_Combo_IEEE0 :: MIICntl :: collision_test_en [07:07] */
#define Wr_SGMII1_Combo_IEEE0_MIICntl_collision_test_en(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x80,7,x)
#define Rd_SGMII1_Combo_IEEE0_MIICntl_collision_test_en(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x80,7)
#define SGMII1_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_MASK          0x0080
#define SGMII1_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_ALIGN         0
#define SGMII1_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_BITS          1
#define SGMII1_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_SHIFT         7

/* SGMII1_Combo_IEEE0 :: MIICntl :: manual_speed1 [06:06] */
#define Wr_SGMII1_Combo_IEEE0_MIICntl_manual_speed1(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x40,6,x)
#define Rd_SGMII1_Combo_IEEE0_MIICntl_manual_speed1(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIICNTL,0x40,6)
#define SGMII1_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_MASK              0x0040
#define SGMII1_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_ALIGN             0
#define SGMII1_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_BITS              1
#define SGMII1_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_SHIFT             6

/* SGMII1_Combo_IEEE0 :: MIICntl :: reserved1 [05:00] */
#define SGMII1_COMBO_IEEE0_MIICNTL_RESERVED1_MASK                  0x003f
#define SGMII1_COMBO_IEEE0_MIICNTL_RESERVED1_ALIGN                 0
#define SGMII1_COMBO_IEEE0_MIICNTL_RESERVED1_BITS                  6
#define SGMII1_COMBO_IEEE0_MIICNTL_RESERVED1_SHIFT                 0


/****************************************************************************
 * SGMII1_Combo_IEEE0 :: MIIStat
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: MIIStat :: s100BASE_T4_capable [15:15] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_s100BASE_T4_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x8000,15,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_s100BASE_T4_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x8000,15)
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_MASK        0x8000
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN       0
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_BITS        1
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT       15

/* SGMII1_Combo_IEEE0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x4000,14,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x4000,14)
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14

/* SGMII1_Combo_IEEE0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x2000,13,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x2000,13)
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13

/* SGMII1_Combo_IEEE0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x1000,12,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x1000,12)
#define SGMII1_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x1000
#define SGMII1_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12

/* SGMII1_Combo_IEEE0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x800,11,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x800,11)
#define SGMII1_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x0800
#define SGMII1_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11

/* SGMII1_Combo_IEEE0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x400,10,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x400,10)
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10

/* SGMII1_Combo_IEEE0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x200,9,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x200,9)
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9

/* SGMII1_Combo_IEEE0 :: MIIStat :: extended_status [08:08] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_extended_status(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x100,8,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_extended_status(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x100,8)
#define SGMII1_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_MASK            0x0100
#define SGMII1_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_ALIGN           0
#define SGMII1_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_BITS            1
#define SGMII1_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_SHIFT           8

/* SGMII1_Combo_IEEE0 :: MIIStat :: reserved0 [07:07] */
#define SGMII1_COMBO_IEEE0_MIISTAT_RESERVED0_MASK                  0x0080
#define SGMII1_COMBO_IEEE0_MIISTAT_RESERVED0_ALIGN                 0
#define SGMII1_COMBO_IEEE0_MIISTAT_RESERVED0_BITS                  1
#define SGMII1_COMBO_IEEE0_MIISTAT_RESERVED0_SHIFT                 7

/* SGMII1_Combo_IEEE0 :: MIIStat :: mf_preamble_supression [06:06] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_mf_preamble_supression(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x40,6,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_mf_preamble_supression(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x40,6)
#define SGMII1_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK     0x0040
#define SGMII1_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN    0
#define SGMII1_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS     1
#define SGMII1_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT    6

/* SGMII1_Combo_IEEE0 :: MIIStat :: autoneg_complete [05:05] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_autoneg_complete(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x20,5,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_autoneg_complete(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x20,5)
#define SGMII1_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_MASK           0x0020
#define SGMII1_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_ALIGN          0
#define SGMII1_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_BITS           1
#define SGMII1_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_SHIFT          5

/* SGMII1_Combo_IEEE0 :: MIIStat :: remote_fault [04:04] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_remote_fault(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x10,4,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_remote_fault(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x10,4)
#define SGMII1_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_MASK               0x0010
#define SGMII1_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_ALIGN              0
#define SGMII1_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_BITS               1
#define SGMII1_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_SHIFT              4

/* SGMII1_Combo_IEEE0 :: MIIStat :: autoneg_ability [03:03] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_autoneg_ability(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x8,3,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_autoneg_ability(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x8,3)
#define SGMII1_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_MASK            0x0008
#define SGMII1_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_ALIGN           0
#define SGMII1_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_BITS            1
#define SGMII1_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_SHIFT           3

/* SGMII1_Combo_IEEE0 :: MIIStat :: link_status [02:02] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_link_status(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x4,2,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_link_status(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x4,2)
#define SGMII1_COMBO_IEEE0_MIISTAT_LINK_STATUS_MASK                0x0004
#define SGMII1_COMBO_IEEE0_MIISTAT_LINK_STATUS_ALIGN               0
#define SGMII1_COMBO_IEEE0_MIISTAT_LINK_STATUS_BITS                1
#define SGMII1_COMBO_IEEE0_MIISTAT_LINK_STATUS_SHIFT               2

/* SGMII1_Combo_IEEE0 :: MIIStat :: jabber_detect [01:01] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_jabber_detect(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x2,1,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_jabber_detect(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x2,1)
#define SGMII1_COMBO_IEEE0_MIISTAT_JABBER_DETECT_MASK              0x0002
#define SGMII1_COMBO_IEEE0_MIISTAT_JABBER_DETECT_ALIGN             0
#define SGMII1_COMBO_IEEE0_MIISTAT_JABBER_DETECT_BITS              1
#define SGMII1_COMBO_IEEE0_MIISTAT_JABBER_DETECT_SHIFT             1

/* SGMII1_Combo_IEEE0 :: MIIStat :: extended_capability [00:00] */
#define Wr_SGMII1_Combo_IEEE0_MIIStat_extended_capability(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x1,0,x)
#define Rd_SGMII1_Combo_IEEE0_MIIStat_extended_capability(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIISTAT,0x1,0)
#define SGMII1_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_MASK        0x0001
#define SGMII1_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_ALIGN       0
#define SGMII1_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_BITS        1
#define SGMII1_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_SHIFT       0


/****************************************************************************
 * SGMII1_Combo_IEEE0 :: Id1
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: Id1 :: regid [15:00] */
#define Wr_SGMII1_Combo_IEEE0_Id1_regid(x) WriteReg16(SGMII1_COMBO_IEEE0_ID1,x)
#define Rd_SGMII1_Combo_IEEE0_Id1_regid(x) ReadReg16(SGMII1_COMBO_IEEE0_ID1)
#define SGMII1_COMBO_IEEE0_ID1_REGID_MASK                          0xffff
#define SGMII1_COMBO_IEEE0_ID1_REGID_ALIGN                         0
#define SGMII1_COMBO_IEEE0_ID1_REGID_BITS                          16
#define SGMII1_COMBO_IEEE0_ID1_REGID_SHIFT                         0


/****************************************************************************
 * SGMII1_Combo_IEEE0 :: Id2
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: Id2 :: regid [15:00] */
#define Wr_SGMII1_Combo_IEEE0_Id2_regid(x) WriteReg16(SGMII1_COMBO_IEEE0_ID2,x)
#define Rd_SGMII1_Combo_IEEE0_Id2_regid(x) ReadReg16(SGMII1_COMBO_IEEE0_ID2)
#define SGMII1_COMBO_IEEE0_ID2_REGID_MASK                          0xffff
#define SGMII1_COMBO_IEEE0_ID2_REGID_ALIGN                         0
#define SGMII1_COMBO_IEEE0_ID2_REGID_BITS                          16
#define SGMII1_COMBO_IEEE0_ID2_REGID_SHIFT                         0


/****************************************************************************
 * SGMII1_Combo_IEEE0 :: AutoNegAdv
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: AutoNegAdv :: next_page [15:15] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegAdv_next_page(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x8000,15,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegAdv_next_page(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x8000,15)
#define SGMII1_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_MASK               0x8000
#define SGMII1_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_ALIGN              0
#define SGMII1_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_BITS               1
#define SGMII1_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_SHIFT              15

/* SGMII1_Combo_IEEE0 :: AutoNegAdv :: reserved0 [14:14] */
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED0_MASK               0x4000
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED0_ALIGN              0
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED0_BITS               1
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED0_SHIFT              14

/* SGMII1_Combo_IEEE0 :: AutoNegAdv :: remote_fault [13:12] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegAdv_remote_fault(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x3000,12,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegAdv_remote_fault(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x3000,12)
#define SGMII1_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_MASK            0x3000
#define SGMII1_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_ALIGN           0
#define SGMII1_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_BITS            2
#define SGMII1_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_SHIFT           12

/* SGMII1_Combo_IEEE0 :: AutoNegAdv :: reserved1 [11:09] */
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED1_MASK               0x0e00
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED1_ALIGN              0
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED1_BITS               3
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED1_SHIFT              9

/* SGMII1_Combo_IEEE0 :: AutoNegAdv :: pause [08:07] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegAdv_pause(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x180,7,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegAdv_pause(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x180,7)
#define SGMII1_COMBO_IEEE0_AUTONEGADV_PAUSE_MASK                   0x0180
#define SGMII1_COMBO_IEEE0_AUTONEGADV_PAUSE_ALIGN                  0
#define SGMII1_COMBO_IEEE0_AUTONEGADV_PAUSE_BITS                   2
#define SGMII1_COMBO_IEEE0_AUTONEGADV_PAUSE_SHIFT                  7

/* SGMII1_Combo_IEEE0 :: AutoNegAdv :: half_duplex [06:06] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegAdv_half_duplex(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x40,6,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegAdv_half_duplex(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x40,6)
#define SGMII1_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_MASK             0x0040
#define SGMII1_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_ALIGN            0
#define SGMII1_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_BITS             1
#define SGMII1_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_SHIFT            6

/* SGMII1_Combo_IEEE0 :: AutoNegAdv :: full_duplex [05:05] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegAdv_full_duplex(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x20,5,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegAdv_full_duplex(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGADV,0x20,5)
#define SGMII1_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_MASK             0x0020
#define SGMII1_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_ALIGN            0
#define SGMII1_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_BITS             1
#define SGMII1_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_SHIFT            5

/* SGMII1_Combo_IEEE0 :: AutoNegAdv :: reserved2 [04:00] */
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED2_MASK               0x001f
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED2_ALIGN              0
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED2_BITS               5
#define SGMII1_COMBO_IEEE0_AUTONEGADV_RESERVED2_SHIFT              0


/****************************************************************************
 * SGMII1_Combo_IEEE0 :: AutoNegLPAbil
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil :: next_page [15:15] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil_next_page(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x8000,15,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil_next_page(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x8000,15)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_MASK            0x8000
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_ALIGN           0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_BITS            1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_SHIFT           15

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil :: acknowledge [14:14] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil_acknowledge(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x4000,14,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil_acknowledge(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x4000,14)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_MASK          0x4000
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN         0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_BITS          1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT         14

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil :: remote_fault [13:12] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil_remote_fault(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x3000,12,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil_remote_fault(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x3000,12)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_MASK         0x3000
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN        0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_BITS         2
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT        12

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil :: reserved0 [11:09] */
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_MASK            0x0e00
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_ALIGN           0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_BITS            3
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_SHIFT           9

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil :: pause [08:07] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil_pause(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x180,7,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil_pause(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x180,7)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_MASK                0x0180
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_ALIGN               0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_BITS                2
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_SHIFT               7

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil :: half_duplex [06:06] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil_half_duplex(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x40,6,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil_half_duplex(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x40,6)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_MASK          0x0040
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN         0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_BITS          1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT         6

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil :: full_duplex [05:05] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil_full_duplex(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x20,5,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil_full_duplex(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x20,5)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_MASK          0x0020
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN         0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_BITS          1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT         5

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil :: reserved1 [04:01] */
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_MASK            0x001e
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_ALIGN           0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_BITS            4
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_SHIFT           1

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil :: sgmii_mode [00:00] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil_sgmii_mode(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x1,0,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil_sgmii_mode(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL,0x1,0)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_MASK           0x0001
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_ALIGN          0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_BITS           1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_SHIFT          0


/****************************************************************************
 * SGMII1_Combo_IEEE0 :: AutoNegExp
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: AutoNegExp :: reserved0 [15:03] */
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_RESERVED0_MASK               0xfff8
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_RESERVED0_ALIGN              0
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_RESERVED0_BITS               13
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_RESERVED0_SHIFT              3

/* SGMII1_Combo_IEEE0 :: AutoNegExp :: next_page_ability [02:02] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegExp_next_page_ability(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGEXP,0x4,2,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegExp_next_page_ability(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGEXP,0x4,2)
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK       0x0004
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN      0
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS       1
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT      2

/* SGMII1_Combo_IEEE0 :: AutoNegExp :: page_received [01:01] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegExp_page_received(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGEXP,0x2,1,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegExp_page_received(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGEXP,0x2,1)
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_MASK           0x0002
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_ALIGN          0
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_BITS           1
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_SHIFT          1

/* SGMII1_Combo_IEEE0 :: AutoNegExp :: reserved1 [00:00] */
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_RESERVED1_MASK               0x0001
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_RESERVED1_ALIGN              0
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_RESERVED1_BITS               1
#define SGMII1_COMBO_IEEE0_AUTONEGEXP_RESERVED1_SHIFT              0


/****************************************************************************
 * SGMII1_Combo_IEEE0 :: AutoNegNP
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: AutoNegNP :: Next_Page [15:15] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegNP_Next_Page(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x8000,15,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegNP_Next_Page(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x8000,15)
#define SGMII1_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_MASK                0x8000
#define SGMII1_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_ALIGN               0
#define SGMII1_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_BITS                1
#define SGMII1_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_SHIFT               15

/* SGMII1_Combo_IEEE0 :: AutoNegNP :: Ack [14:14] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegNP_Ack(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x4000,14,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegNP_Ack(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x4000,14)
#define SGMII1_COMBO_IEEE0_AUTONEGNP_ACK_MASK                      0x4000
#define SGMII1_COMBO_IEEE0_AUTONEGNP_ACK_ALIGN                     0
#define SGMII1_COMBO_IEEE0_AUTONEGNP_ACK_BITS                      1
#define SGMII1_COMBO_IEEE0_AUTONEGNP_ACK_SHIFT                     14

/* SGMII1_Combo_IEEE0 :: AutoNegNP :: Message_Page [13:13] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegNP_Message_Page(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x2000,13,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegNP_Message_Page(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x2000,13)
#define SGMII1_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_MASK             0x2000
#define SGMII1_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_ALIGN            0
#define SGMII1_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_BITS             1
#define SGMII1_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_SHIFT            13

/* SGMII1_Combo_IEEE0 :: AutoNegNP :: Ack2 [12:12] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegNP_Ack2(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x1000,12,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegNP_Ack2(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x1000,12)
#define SGMII1_COMBO_IEEE0_AUTONEGNP_ACK2_MASK                     0x1000
#define SGMII1_COMBO_IEEE0_AUTONEGNP_ACK2_ALIGN                    0
#define SGMII1_COMBO_IEEE0_AUTONEGNP_ACK2_BITS                     1
#define SGMII1_COMBO_IEEE0_AUTONEGNP_ACK2_SHIFT                    12

/* SGMII1_Combo_IEEE0 :: AutoNegNP :: Toggle [11:11] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegNP_Toggle(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x800,11,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegNP_Toggle(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x800,11)
#define SGMII1_COMBO_IEEE0_AUTONEGNP_TOGGLE_MASK                   0x0800
#define SGMII1_COMBO_IEEE0_AUTONEGNP_TOGGLE_ALIGN                  0
#define SGMII1_COMBO_IEEE0_AUTONEGNP_TOGGLE_BITS                   1
#define SGMII1_COMBO_IEEE0_AUTONEGNP_TOGGLE_SHIFT                  11

/* SGMII1_Combo_IEEE0 :: AutoNegNP :: Message [10:00] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegNP_Message(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x7ff,0,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegNP_Message(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGNP,0x7ff,0)
#define SGMII1_COMBO_IEEE0_AUTONEGNP_MESSAGE_MASK                  0x07ff
#define SGMII1_COMBO_IEEE0_AUTONEGNP_MESSAGE_ALIGN                 0
#define SGMII1_COMBO_IEEE0_AUTONEGNP_MESSAGE_BITS                  11
#define SGMII1_COMBO_IEEE0_AUTONEGNP_MESSAGE_SHIFT                 0


/****************************************************************************
 * SGMII1_Combo_IEEE0 :: AutoNegLPAbil2
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil2 :: Next_Page [15:15] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Next_Page(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x8000,15,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Next_Page(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x8000,15)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_MASK           0x8000
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN          0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_BITS           1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT          15

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil2 :: Ack [14:14] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Ack(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x4000,14,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Ack(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x4000,14)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_ACK_MASK                 0x4000
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_ACK_ALIGN                0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_ACK_BITS                 1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_ACK_SHIFT                14

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil2 :: Message_Page [13:13] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Message_Page(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x2000,13,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Message_Page(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x2000,13)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK        0x2000
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN       0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS        1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT       13

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil2 :: Ack2 [12:12] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Ack2(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x1000,12,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Ack2(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x1000,12)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_MASK                0x1000
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_ALIGN               0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_BITS                1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_SHIFT               12

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil2 :: Toggle [11:11] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Toggle(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x800,11,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Toggle(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x800,11)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_MASK              0x0800
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_ALIGN             0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_BITS              1
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_SHIFT             11

/* SGMII1_Combo_IEEE0 :: AutoNegLPAbil2 :: Message [10:00] */
#define Wr_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Message(x) WriteRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x7ff,0,x)
#define Rd_SGMII1_Combo_IEEE0_AutoNegLPAbil2_Message(x) ReadRegBits16(SGMII1_COMBO_IEEE0_AUTONEGLPABIL2,0x7ff,0)
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_MASK             0x07ff
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_ALIGN            0
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_BITS             11
#define SGMII1_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_SHIFT            0


/****************************************************************************
 * SGMII1_Combo_IEEE0 :: MIIextStat
 ***************************************************************************/
/* SGMII1_Combo_IEEE0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
#define Wr_SGMII1_Combo_IEEE0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIIEXTSTAT,0x8000,15,x)
#define Rd_SGMII1_Combo_IEEE0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIIEXTSTAT,0x8000,15)
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15

/* SGMII1_Combo_IEEE0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
#define Wr_SGMII1_Combo_IEEE0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIIEXTSTAT,0x4000,14,x)
#define Rd_SGMII1_Combo_IEEE0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIIEXTSTAT,0x4000,14)
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14

/* SGMII1_Combo_IEEE0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
#define Wr_SGMII1_Combo_IEEE0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIIEXTSTAT,0x2000,13,x)
#define Rd_SGMII1_Combo_IEEE0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIIEXTSTAT,0x2000,13)
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13

/* SGMII1_Combo_IEEE0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
#define Wr_SGMII1_Combo_IEEE0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII1_COMBO_IEEE0_MIIEXTSTAT,0x1000,12,x)
#define Rd_SGMII1_Combo_IEEE0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII1_COMBO_IEEE0_MIIEXTSTAT,0x1000,12)
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12

/* SGMII1_Combo_IEEE0 :: MIIextStat :: reserved0 [11:00] */
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_MASK               0x0fff
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_ALIGN              0
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_BITS               12
#define SGMII1_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_SHIFT              0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_CL22_B0
 ***************************************************************************/
/****************************************************************************
 * SGMII2_CL22_B0 :: MIICntl
 ***************************************************************************/
/* SGMII2_CL22_B0 :: MIICntl :: rst_hw [15:15] */
#define Wr_SGMII2_CL22_B0_MIICntl_rst_hw(x) WriteRegBits16(SGMII2_CL22_B0_MIICNTL,0x8000,15,x)
#define Rd_SGMII2_CL22_B0_MIICntl_rst_hw(x) ReadRegBits16(SGMII2_CL22_B0_MIICNTL,0x8000,15)
#define SGMII2_CL22_B0_MIICNTL_RST_HW_MASK                         0x8000
#define SGMII2_CL22_B0_MIICNTL_RST_HW_ALIGN                        0
#define SGMII2_CL22_B0_MIICNTL_RST_HW_BITS                         1
#define SGMII2_CL22_B0_MIICNTL_RST_HW_SHIFT                        15

/* SGMII2_CL22_B0 :: MIICntl :: gloopback [14:14] */
#define Wr_SGMII2_CL22_B0_MIICntl_gloopback(x) WriteRegBits16(SGMII2_CL22_B0_MIICNTL,0x4000,14,x)
#define Rd_SGMII2_CL22_B0_MIICntl_gloopback(x) ReadRegBits16(SGMII2_CL22_B0_MIICNTL,0x4000,14)
#define SGMII2_CL22_B0_MIICNTL_GLOOPBACK_MASK                      0x4000
#define SGMII2_CL22_B0_MIICNTL_GLOOPBACK_ALIGN                     0
#define SGMII2_CL22_B0_MIICNTL_GLOOPBACK_BITS                      1
#define SGMII2_CL22_B0_MIICNTL_GLOOPBACK_SHIFT                     14

/* SGMII2_CL22_B0 :: MIICntl :: manual_speed0 [13:13] */
#define Wr_SGMII2_CL22_B0_MIICntl_manual_speed0(x) WriteRegBits16(SGMII2_CL22_B0_MIICNTL,0x2000,13,x)
#define Rd_SGMII2_CL22_B0_MIICntl_manual_speed0(x) ReadRegBits16(SGMII2_CL22_B0_MIICNTL,0x2000,13)
#define SGMII2_CL22_B0_MIICNTL_MANUAL_SPEED0_MASK                  0x2000
#define SGMII2_CL22_B0_MIICNTL_MANUAL_SPEED0_ALIGN                 0
#define SGMII2_CL22_B0_MIICNTL_MANUAL_SPEED0_BITS                  1
#define SGMII2_CL22_B0_MIICNTL_MANUAL_SPEED0_SHIFT                 13

/* SGMII2_CL22_B0 :: MIICntl :: autoneg_enable [12:12] */
#define Wr_SGMII2_CL22_B0_MIICntl_autoneg_enable(x) WriteRegBits16(SGMII2_CL22_B0_MIICNTL,0x1000,12,x)
#define Rd_SGMII2_CL22_B0_MIICntl_autoneg_enable(x) ReadRegBits16(SGMII2_CL22_B0_MIICNTL,0x1000,12)
#define SGMII2_CL22_B0_MIICNTL_AUTONEG_ENABLE_MASK                 0x1000
#define SGMII2_CL22_B0_MIICNTL_AUTONEG_ENABLE_ALIGN                0
#define SGMII2_CL22_B0_MIICNTL_AUTONEG_ENABLE_BITS                 1
#define SGMII2_CL22_B0_MIICNTL_AUTONEG_ENABLE_SHIFT                12

/* SGMII2_CL22_B0 :: MIICntl :: pwrdwn_sw [11:11] */
#define Wr_SGMII2_CL22_B0_MIICntl_pwrdwn_sw(x) WriteRegBits16(SGMII2_CL22_B0_MIICNTL,0x800,11,x)
#define Rd_SGMII2_CL22_B0_MIICntl_pwrdwn_sw(x) ReadRegBits16(SGMII2_CL22_B0_MIICNTL,0x800,11)
#define SGMII2_CL22_B0_MIICNTL_PWRDWN_SW_MASK                      0x0800
#define SGMII2_CL22_B0_MIICNTL_PWRDWN_SW_ALIGN                     0
#define SGMII2_CL22_B0_MIICNTL_PWRDWN_SW_BITS                      1
#define SGMII2_CL22_B0_MIICNTL_PWRDWN_SW_SHIFT                     11

/* SGMII2_CL22_B0 :: MIICntl :: reserved0 [10:10] */
#define SGMII2_CL22_B0_MIICNTL_RESERVED0_MASK                      0x0400
#define SGMII2_CL22_B0_MIICNTL_RESERVED0_ALIGN                     0
#define SGMII2_CL22_B0_MIICNTL_RESERVED0_BITS                      1
#define SGMII2_CL22_B0_MIICNTL_RESERVED0_SHIFT                     10

/* SGMII2_CL22_B0 :: MIICntl :: restart_autoneg [09:09] */
#define Wr_SGMII2_CL22_B0_MIICntl_restart_autoneg(x) WriteRegBits16(SGMII2_CL22_B0_MIICNTL,0x200,9,x)
#define Rd_SGMII2_CL22_B0_MIICntl_restart_autoneg(x) ReadRegBits16(SGMII2_CL22_B0_MIICNTL,0x200,9)
#define SGMII2_CL22_B0_MIICNTL_RESTART_AUTONEG_MASK                0x0200
#define SGMII2_CL22_B0_MIICNTL_RESTART_AUTONEG_ALIGN               0
#define SGMII2_CL22_B0_MIICNTL_RESTART_AUTONEG_BITS                1
#define SGMII2_CL22_B0_MIICNTL_RESTART_AUTONEG_SHIFT               9

/* SGMII2_CL22_B0 :: MIICntl :: full_duplex [08:08] */
#define Wr_SGMII2_CL22_B0_MIICntl_full_duplex(x) WriteRegBits16(SGMII2_CL22_B0_MIICNTL,0x100,8,x)
#define Rd_SGMII2_CL22_B0_MIICntl_full_duplex(x) ReadRegBits16(SGMII2_CL22_B0_MIICNTL,0x100,8)
#define SGMII2_CL22_B0_MIICNTL_FULL_DUPLEX_MASK                    0x0100
#define SGMII2_CL22_B0_MIICNTL_FULL_DUPLEX_ALIGN                   0
#define SGMII2_CL22_B0_MIICNTL_FULL_DUPLEX_BITS                    1
#define SGMII2_CL22_B0_MIICNTL_FULL_DUPLEX_SHIFT                   8

/* SGMII2_CL22_B0 :: MIICntl :: collision_test_en [07:07] */
#define Wr_SGMII2_CL22_B0_MIICntl_collision_test_en(x) WriteRegBits16(SGMII2_CL22_B0_MIICNTL,0x80,7,x)
#define Rd_SGMII2_CL22_B0_MIICntl_collision_test_en(x) ReadRegBits16(SGMII2_CL22_B0_MIICNTL,0x80,7)
#define SGMII2_CL22_B0_MIICNTL_COLLISION_TEST_EN_MASK              0x0080
#define SGMII2_CL22_B0_MIICNTL_COLLISION_TEST_EN_ALIGN             0
#define SGMII2_CL22_B0_MIICNTL_COLLISION_TEST_EN_BITS              1
#define SGMII2_CL22_B0_MIICNTL_COLLISION_TEST_EN_SHIFT             7

/* SGMII2_CL22_B0 :: MIICntl :: manual_speed1 [06:06] */
#define Wr_SGMII2_CL22_B0_MIICntl_manual_speed1(x) WriteRegBits16(SGMII2_CL22_B0_MIICNTL,0x40,6,x)
#define Rd_SGMII2_CL22_B0_MIICntl_manual_speed1(x) ReadRegBits16(SGMII2_CL22_B0_MIICNTL,0x40,6)
#define SGMII2_CL22_B0_MIICNTL_MANUAL_SPEED1_MASK                  0x0040
#define SGMII2_CL22_B0_MIICNTL_MANUAL_SPEED1_ALIGN                 0
#define SGMII2_CL22_B0_MIICNTL_MANUAL_SPEED1_BITS                  1
#define SGMII2_CL22_B0_MIICNTL_MANUAL_SPEED1_SHIFT                 6

/* SGMII2_CL22_B0 :: MIICntl :: reserved1 [05:00] */
#define SGMII2_CL22_B0_MIICNTL_RESERVED1_MASK                      0x003f
#define SGMII2_CL22_B0_MIICNTL_RESERVED1_ALIGN                     0
#define SGMII2_CL22_B0_MIICNTL_RESERVED1_BITS                      6
#define SGMII2_CL22_B0_MIICNTL_RESERVED1_SHIFT                     0


/****************************************************************************
 * SGMII2_CL22_B0 :: MIIStat
 ***************************************************************************/
/* SGMII2_CL22_B0 :: MIIStat :: s100BASE_T4_capable [15:15] */
#define Wr_SGMII2_CL22_B0_MIIStat_s100BASE_T4_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x8000,15,x)
#define Rd_SGMII2_CL22_B0_MIIStat_s100BASE_T4_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x8000,15)
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_MASK            0x8000
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN           0
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_BITS            1
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT           15

/* SGMII2_CL22_B0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
#define Wr_SGMII2_CL22_B0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x4000,14,x)
#define Rd_SGMII2_CL22_B0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x4000,14)
#define SGMII2_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII2_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII2_CL22_B0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14

/* SGMII2_CL22_B0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
#define Wr_SGMII2_CL22_B0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x2000,13,x)
#define Rd_SGMII2_CL22_B0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x2000,13)
#define SGMII2_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII2_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII2_CL22_B0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13

/* SGMII2_CL22_B0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
#define Wr_SGMII2_CL22_B0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x1000,12,x)
#define Rd_SGMII2_CL22_B0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x1000,12)
#define SGMII2_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK  0x1000
#define SGMII2_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS  1
#define SGMII2_CL22_B0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12

/* SGMII2_CL22_B0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
#define Wr_SGMII2_CL22_B0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x800,11,x)
#define Rd_SGMII2_CL22_B0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x800,11)
#define SGMII2_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK  0x0800
#define SGMII2_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS  1
#define SGMII2_CL22_B0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11

/* SGMII2_CL22_B0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
#define Wr_SGMII2_CL22_B0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x400,10,x)
#define Rd_SGMII2_CL22_B0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x400,10)
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10

/* SGMII2_CL22_B0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
#define Wr_SGMII2_CL22_B0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x200,9,x)
#define Rd_SGMII2_CL22_B0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x200,9)
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII2_CL22_B0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9

/* SGMII2_CL22_B0 :: MIIStat :: extended_status [08:08] */
#define Wr_SGMII2_CL22_B0_MIIStat_extended_status(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x100,8,x)
#define Rd_SGMII2_CL22_B0_MIIStat_extended_status(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x100,8)
#define SGMII2_CL22_B0_MIISTAT_EXTENDED_STATUS_MASK                0x0100
#define SGMII2_CL22_B0_MIISTAT_EXTENDED_STATUS_ALIGN               0
#define SGMII2_CL22_B0_MIISTAT_EXTENDED_STATUS_BITS                1
#define SGMII2_CL22_B0_MIISTAT_EXTENDED_STATUS_SHIFT               8

/* SGMII2_CL22_B0 :: MIIStat :: reserved0 [07:07] */
#define SGMII2_CL22_B0_MIISTAT_RESERVED0_MASK                      0x0080
#define SGMII2_CL22_B0_MIISTAT_RESERVED0_ALIGN                     0
#define SGMII2_CL22_B0_MIISTAT_RESERVED0_BITS                      1
#define SGMII2_CL22_B0_MIISTAT_RESERVED0_SHIFT                     7

/* SGMII2_CL22_B0 :: MIIStat :: mf_preamble_supression [06:06] */
#define Wr_SGMII2_CL22_B0_MIIStat_mf_preamble_supression(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x40,6,x)
#define Rd_SGMII2_CL22_B0_MIIStat_mf_preamble_supression(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x40,6)
#define SGMII2_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK         0x0040
#define SGMII2_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN        0
#define SGMII2_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS         1
#define SGMII2_CL22_B0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT        6

/* SGMII2_CL22_B0 :: MIIStat :: autoneg_complete [05:05] */
#define Wr_SGMII2_CL22_B0_MIIStat_autoneg_complete(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x20,5,x)
#define Rd_SGMII2_CL22_B0_MIIStat_autoneg_complete(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x20,5)
#define SGMII2_CL22_B0_MIISTAT_AUTONEG_COMPLETE_MASK               0x0020
#define SGMII2_CL22_B0_MIISTAT_AUTONEG_COMPLETE_ALIGN              0
#define SGMII2_CL22_B0_MIISTAT_AUTONEG_COMPLETE_BITS               1
#define SGMII2_CL22_B0_MIISTAT_AUTONEG_COMPLETE_SHIFT              5

/* SGMII2_CL22_B0 :: MIIStat :: remote_fault [04:04] */
#define Wr_SGMII2_CL22_B0_MIIStat_remote_fault(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x10,4,x)
#define Rd_SGMII2_CL22_B0_MIIStat_remote_fault(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x10,4)
#define SGMII2_CL22_B0_MIISTAT_REMOTE_FAULT_MASK                   0x0010
#define SGMII2_CL22_B0_MIISTAT_REMOTE_FAULT_ALIGN                  0
#define SGMII2_CL22_B0_MIISTAT_REMOTE_FAULT_BITS                   1
#define SGMII2_CL22_B0_MIISTAT_REMOTE_FAULT_SHIFT                  4

/* SGMII2_CL22_B0 :: MIIStat :: autoneg_ability [03:03] */
#define Wr_SGMII2_CL22_B0_MIIStat_autoneg_ability(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x8,3,x)
#define Rd_SGMII2_CL22_B0_MIIStat_autoneg_ability(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x8,3)
#define SGMII2_CL22_B0_MIISTAT_AUTONEG_ABILITY_MASK                0x0008
#define SGMII2_CL22_B0_MIISTAT_AUTONEG_ABILITY_ALIGN               0
#define SGMII2_CL22_B0_MIISTAT_AUTONEG_ABILITY_BITS                1
#define SGMII2_CL22_B0_MIISTAT_AUTONEG_ABILITY_SHIFT               3

/* SGMII2_CL22_B0 :: MIIStat :: link_status [02:02] */
#define Wr_SGMII2_CL22_B0_MIIStat_link_status(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x4,2,x)
#define Rd_SGMII2_CL22_B0_MIIStat_link_status(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x4,2)
#define SGMII2_CL22_B0_MIISTAT_LINK_STATUS_MASK                    0x0004
#define SGMII2_CL22_B0_MIISTAT_LINK_STATUS_ALIGN                   0
#define SGMII2_CL22_B0_MIISTAT_LINK_STATUS_BITS                    1
#define SGMII2_CL22_B0_MIISTAT_LINK_STATUS_SHIFT                   2

/* SGMII2_CL22_B0 :: MIIStat :: jabber_detect [01:01] */
#define Wr_SGMII2_CL22_B0_MIIStat_jabber_detect(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x2,1,x)
#define Rd_SGMII2_CL22_B0_MIIStat_jabber_detect(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x2,1)
#define SGMII2_CL22_B0_MIISTAT_JABBER_DETECT_MASK                  0x0002
#define SGMII2_CL22_B0_MIISTAT_JABBER_DETECT_ALIGN                 0
#define SGMII2_CL22_B0_MIISTAT_JABBER_DETECT_BITS                  1
#define SGMII2_CL22_B0_MIISTAT_JABBER_DETECT_SHIFT                 1

/* SGMII2_CL22_B0 :: MIIStat :: extended_capability [00:00] */
#define Wr_SGMII2_CL22_B0_MIIStat_extended_capability(x) WriteRegBits16(SGMII2_CL22_B0_MIISTAT,0x1,0,x)
#define Rd_SGMII2_CL22_B0_MIIStat_extended_capability(x) ReadRegBits16(SGMII2_CL22_B0_MIISTAT,0x1,0)
#define SGMII2_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_MASK            0x0001
#define SGMII2_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_ALIGN           0
#define SGMII2_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_BITS            1
#define SGMII2_CL22_B0_MIISTAT_EXTENDED_CAPABILITY_SHIFT           0


/****************************************************************************
 * SGMII2_CL22_B0 :: Id1
 ***************************************************************************/
/* SGMII2_CL22_B0 :: Id1 :: regid [15:00] */
#define Wr_SGMII2_CL22_B0_Id1_regid(x) WriteReg16(SGMII2_CL22_B0_ID1,x)
#define Rd_SGMII2_CL22_B0_Id1_regid(x) ReadReg16(SGMII2_CL22_B0_ID1)
#define SGMII2_CL22_B0_ID1_REGID_MASK                              0xffff
#define SGMII2_CL22_B0_ID1_REGID_ALIGN                             0
#define SGMII2_CL22_B0_ID1_REGID_BITS                              16
#define SGMII2_CL22_B0_ID1_REGID_SHIFT                             0


/****************************************************************************
 * SGMII2_CL22_B0 :: Id2
 ***************************************************************************/
/* SGMII2_CL22_B0 :: Id2 :: regid [15:00] */
#define Wr_SGMII2_CL22_B0_Id2_regid(x) WriteReg16(SGMII2_CL22_B0_ID2,x)
#define Rd_SGMII2_CL22_B0_Id2_regid(x) ReadReg16(SGMII2_CL22_B0_ID2)
#define SGMII2_CL22_B0_ID2_REGID_MASK                              0xffff
#define SGMII2_CL22_B0_ID2_REGID_ALIGN                             0
#define SGMII2_CL22_B0_ID2_REGID_BITS                              16
#define SGMII2_CL22_B0_ID2_REGID_SHIFT                             0


/****************************************************************************
 * SGMII2_CL22_B0 :: AutoNegAdv
 ***************************************************************************/
/* SGMII2_CL22_B0 :: AutoNegAdv :: next_page [15:15] */
#define Wr_SGMII2_CL22_B0_AutoNegAdv_next_page(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x8000,15,x)
#define Rd_SGMII2_CL22_B0_AutoNegAdv_next_page(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x8000,15)
#define SGMII2_CL22_B0_AUTONEGADV_NEXT_PAGE_MASK                   0x8000
#define SGMII2_CL22_B0_AUTONEGADV_NEXT_PAGE_ALIGN                  0
#define SGMII2_CL22_B0_AUTONEGADV_NEXT_PAGE_BITS                   1
#define SGMII2_CL22_B0_AUTONEGADV_NEXT_PAGE_SHIFT                  15

/* SGMII2_CL22_B0 :: AutoNegAdv :: reserved0 [14:14] */
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED0_MASK                   0x4000
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED0_ALIGN                  0
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED0_BITS                   1
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED0_SHIFT                  14

/* SGMII2_CL22_B0 :: AutoNegAdv :: remote_fault [13:12] */
#define Wr_SGMII2_CL22_B0_AutoNegAdv_remote_fault(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x3000,12,x)
#define Rd_SGMII2_CL22_B0_AutoNegAdv_remote_fault(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x3000,12)
#define SGMII2_CL22_B0_AUTONEGADV_REMOTE_FAULT_MASK                0x3000
#define SGMII2_CL22_B0_AUTONEGADV_REMOTE_FAULT_ALIGN               0
#define SGMII2_CL22_B0_AUTONEGADV_REMOTE_FAULT_BITS                2
#define SGMII2_CL22_B0_AUTONEGADV_REMOTE_FAULT_SHIFT               12

/* SGMII2_CL22_B0 :: AutoNegAdv :: reserved1 [11:09] */
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED1_MASK                   0x0e00
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED1_ALIGN                  0
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED1_BITS                   3
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED1_SHIFT                  9

/* SGMII2_CL22_B0 :: AutoNegAdv :: pause [08:07] */
#define Wr_SGMII2_CL22_B0_AutoNegAdv_pause(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x180,7,x)
#define Rd_SGMII2_CL22_B0_AutoNegAdv_pause(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x180,7)
#define SGMII2_CL22_B0_AUTONEGADV_PAUSE_MASK                       0x0180
#define SGMII2_CL22_B0_AUTONEGADV_PAUSE_ALIGN                      0
#define SGMII2_CL22_B0_AUTONEGADV_PAUSE_BITS                       2
#define SGMII2_CL22_B0_AUTONEGADV_PAUSE_SHIFT                      7

/* SGMII2_CL22_B0 :: AutoNegAdv :: half_duplex [06:06] */
#define Wr_SGMII2_CL22_B0_AutoNegAdv_half_duplex(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x40,6,x)
#define Rd_SGMII2_CL22_B0_AutoNegAdv_half_duplex(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x40,6)
#define SGMII2_CL22_B0_AUTONEGADV_HALF_DUPLEX_MASK                 0x0040
#define SGMII2_CL22_B0_AUTONEGADV_HALF_DUPLEX_ALIGN                0
#define SGMII2_CL22_B0_AUTONEGADV_HALF_DUPLEX_BITS                 1
#define SGMII2_CL22_B0_AUTONEGADV_HALF_DUPLEX_SHIFT                6

/* SGMII2_CL22_B0 :: AutoNegAdv :: full_duplex [05:05] */
#define Wr_SGMII2_CL22_B0_AutoNegAdv_full_duplex(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x20,5,x)
#define Rd_SGMII2_CL22_B0_AutoNegAdv_full_duplex(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGADV,0x20,5)
#define SGMII2_CL22_B0_AUTONEGADV_FULL_DUPLEX_MASK                 0x0020
#define SGMII2_CL22_B0_AUTONEGADV_FULL_DUPLEX_ALIGN                0
#define SGMII2_CL22_B0_AUTONEGADV_FULL_DUPLEX_BITS                 1
#define SGMII2_CL22_B0_AUTONEGADV_FULL_DUPLEX_SHIFT                5

/* SGMII2_CL22_B0 :: AutoNegAdv :: reserved2 [04:00] */
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED2_MASK                   0x001f
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED2_ALIGN                  0
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED2_BITS                   5
#define SGMII2_CL22_B0_AUTONEGADV_RESERVED2_SHIFT                  0


/****************************************************************************
 * SGMII2_CL22_B0 :: AutoNegLPAbil
 ***************************************************************************/
/* SGMII2_CL22_B0 :: AutoNegLPAbil :: next_page [15:15] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil_next_page(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x8000,15,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil_next_page(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x8000,15)
#define SGMII2_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_MASK                0x8000
#define SGMII2_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_ALIGN               0
#define SGMII2_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_BITS                1
#define SGMII2_CL22_B0_AUTONEGLPABIL_NEXT_PAGE_SHIFT               15

/* SGMII2_CL22_B0 :: AutoNegLPAbil :: acknowledge [14:14] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil_acknowledge(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x4000,14,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil_acknowledge(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x4000,14)
#define SGMII2_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_MASK              0x4000
#define SGMII2_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN             0
#define SGMII2_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_BITS              1
#define SGMII2_CL22_B0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT             14

/* SGMII2_CL22_B0 :: AutoNegLPAbil :: remote_fault [13:12] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil_remote_fault(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x3000,12,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil_remote_fault(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x3000,12)
#define SGMII2_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_MASK             0x3000
#define SGMII2_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN            0
#define SGMII2_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_BITS             2
#define SGMII2_CL22_B0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT            12

/* SGMII2_CL22_B0 :: AutoNegLPAbil :: reserved0 [11:09] */
#define SGMII2_CL22_B0_AUTONEGLPABIL_RESERVED0_MASK                0x0e00
#define SGMII2_CL22_B0_AUTONEGLPABIL_RESERVED0_ALIGN               0
#define SGMII2_CL22_B0_AUTONEGLPABIL_RESERVED0_BITS                3
#define SGMII2_CL22_B0_AUTONEGLPABIL_RESERVED0_SHIFT               9

/* SGMII2_CL22_B0 :: AutoNegLPAbil :: pause [08:07] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil_pause(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x180,7,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil_pause(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x180,7)
#define SGMII2_CL22_B0_AUTONEGLPABIL_PAUSE_MASK                    0x0180
#define SGMII2_CL22_B0_AUTONEGLPABIL_PAUSE_ALIGN                   0
#define SGMII2_CL22_B0_AUTONEGLPABIL_PAUSE_BITS                    2
#define SGMII2_CL22_B0_AUTONEGLPABIL_PAUSE_SHIFT                   7

/* SGMII2_CL22_B0 :: AutoNegLPAbil :: half_duplex [06:06] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil_half_duplex(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x40,6,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil_half_duplex(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x40,6)
#define SGMII2_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_MASK              0x0040
#define SGMII2_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN             0
#define SGMII2_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_BITS              1
#define SGMII2_CL22_B0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT             6

/* SGMII2_CL22_B0 :: AutoNegLPAbil :: full_duplex [05:05] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil_full_duplex(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x20,5,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil_full_duplex(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x20,5)
#define SGMII2_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_MASK              0x0020
#define SGMII2_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN             0
#define SGMII2_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_BITS              1
#define SGMII2_CL22_B0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT             5

/* SGMII2_CL22_B0 :: AutoNegLPAbil :: reserved1 [04:01] */
#define SGMII2_CL22_B0_AUTONEGLPABIL_RESERVED1_MASK                0x001e
#define SGMII2_CL22_B0_AUTONEGLPABIL_RESERVED1_ALIGN               0
#define SGMII2_CL22_B0_AUTONEGLPABIL_RESERVED1_BITS                4
#define SGMII2_CL22_B0_AUTONEGLPABIL_RESERVED1_SHIFT               1

/* SGMII2_CL22_B0 :: AutoNegLPAbil :: sgmii_mode [00:00] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil_sgmii_mode(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x1,0,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil_sgmii_mode(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL,0x1,0)
#define SGMII2_CL22_B0_AUTONEGLPABIL_SGMII_MODE_MASK               0x0001
#define SGMII2_CL22_B0_AUTONEGLPABIL_SGMII_MODE_ALIGN              0
#define SGMII2_CL22_B0_AUTONEGLPABIL_SGMII_MODE_BITS               1
#define SGMII2_CL22_B0_AUTONEGLPABIL_SGMII_MODE_SHIFT              0


/****************************************************************************
 * SGMII2_CL22_B0 :: AutoNegExp
 ***************************************************************************/
/* SGMII2_CL22_B0 :: AutoNegExp :: reserved0 [15:03] */
#define SGMII2_CL22_B0_AUTONEGEXP_RESERVED0_MASK                   0xfff8
#define SGMII2_CL22_B0_AUTONEGEXP_RESERVED0_ALIGN                  0
#define SGMII2_CL22_B0_AUTONEGEXP_RESERVED0_BITS                   13
#define SGMII2_CL22_B0_AUTONEGEXP_RESERVED0_SHIFT                  3

/* SGMII2_CL22_B0 :: AutoNegExp :: next_page_ability [02:02] */
#define Wr_SGMII2_CL22_B0_AutoNegExp_next_page_ability(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGEXP,0x4,2,x)
#define Rd_SGMII2_CL22_B0_AutoNegExp_next_page_ability(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGEXP,0x4,2)
#define SGMII2_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK           0x0004
#define SGMII2_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN          0
#define SGMII2_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS           1
#define SGMII2_CL22_B0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT          2

/* SGMII2_CL22_B0 :: AutoNegExp :: page_received [01:01] */
#define Wr_SGMII2_CL22_B0_AutoNegExp_page_received(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGEXP,0x2,1,x)
#define Rd_SGMII2_CL22_B0_AutoNegExp_page_received(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGEXP,0x2,1)
#define SGMII2_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_MASK               0x0002
#define SGMII2_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_ALIGN              0
#define SGMII2_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_BITS               1
#define SGMII2_CL22_B0_AUTONEGEXP_PAGE_RECEIVED_SHIFT              1

/* SGMII2_CL22_B0 :: AutoNegExp :: reserved1 [00:00] */
#define SGMII2_CL22_B0_AUTONEGEXP_RESERVED1_MASK                   0x0001
#define SGMII2_CL22_B0_AUTONEGEXP_RESERVED1_ALIGN                  0
#define SGMII2_CL22_B0_AUTONEGEXP_RESERVED1_BITS                   1
#define SGMII2_CL22_B0_AUTONEGEXP_RESERVED1_SHIFT                  0


/****************************************************************************
 * SGMII2_CL22_B0 :: AutoNegNP
 ***************************************************************************/
/* SGMII2_CL22_B0 :: AutoNegNP :: Next_Page [15:15] */
#define Wr_SGMII2_CL22_B0_AutoNegNP_Next_Page(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x8000,15,x)
#define Rd_SGMII2_CL22_B0_AutoNegNP_Next_Page(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x8000,15)
#define SGMII2_CL22_B0_AUTONEGNP_NEXT_PAGE_MASK                    0x8000
#define SGMII2_CL22_B0_AUTONEGNP_NEXT_PAGE_ALIGN                   0
#define SGMII2_CL22_B0_AUTONEGNP_NEXT_PAGE_BITS                    1
#define SGMII2_CL22_B0_AUTONEGNP_NEXT_PAGE_SHIFT                   15

/* SGMII2_CL22_B0 :: AutoNegNP :: Ack [14:14] */
#define Wr_SGMII2_CL22_B0_AutoNegNP_Ack(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x4000,14,x)
#define Rd_SGMII2_CL22_B0_AutoNegNP_Ack(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x4000,14)
#define SGMII2_CL22_B0_AUTONEGNP_ACK_MASK                          0x4000
#define SGMII2_CL22_B0_AUTONEGNP_ACK_ALIGN                         0
#define SGMII2_CL22_B0_AUTONEGNP_ACK_BITS                          1
#define SGMII2_CL22_B0_AUTONEGNP_ACK_SHIFT                         14

/* SGMII2_CL22_B0 :: AutoNegNP :: Message_Page [13:13] */
#define Wr_SGMII2_CL22_B0_AutoNegNP_Message_Page(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x2000,13,x)
#define Rd_SGMII2_CL22_B0_AutoNegNP_Message_Page(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x2000,13)
#define SGMII2_CL22_B0_AUTONEGNP_MESSAGE_PAGE_MASK                 0x2000
#define SGMII2_CL22_B0_AUTONEGNP_MESSAGE_PAGE_ALIGN                0
#define SGMII2_CL22_B0_AUTONEGNP_MESSAGE_PAGE_BITS                 1
#define SGMII2_CL22_B0_AUTONEGNP_MESSAGE_PAGE_SHIFT                13

/* SGMII2_CL22_B0 :: AutoNegNP :: Ack2 [12:12] */
#define Wr_SGMII2_CL22_B0_AutoNegNP_Ack2(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x1000,12,x)
#define Rd_SGMII2_CL22_B0_AutoNegNP_Ack2(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x1000,12)
#define SGMII2_CL22_B0_AUTONEGNP_ACK2_MASK                         0x1000
#define SGMII2_CL22_B0_AUTONEGNP_ACK2_ALIGN                        0
#define SGMII2_CL22_B0_AUTONEGNP_ACK2_BITS                         1
#define SGMII2_CL22_B0_AUTONEGNP_ACK2_SHIFT                        12

/* SGMII2_CL22_B0 :: AutoNegNP :: Toggle [11:11] */
#define Wr_SGMII2_CL22_B0_AutoNegNP_Toggle(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x800,11,x)
#define Rd_SGMII2_CL22_B0_AutoNegNP_Toggle(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x800,11)
#define SGMII2_CL22_B0_AUTONEGNP_TOGGLE_MASK                       0x0800
#define SGMII2_CL22_B0_AUTONEGNP_TOGGLE_ALIGN                      0
#define SGMII2_CL22_B0_AUTONEGNP_TOGGLE_BITS                       1
#define SGMII2_CL22_B0_AUTONEGNP_TOGGLE_SHIFT                      11

/* SGMII2_CL22_B0 :: AutoNegNP :: Message [10:00] */
#define Wr_SGMII2_CL22_B0_AutoNegNP_Message(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x7ff,0,x)
#define Rd_SGMII2_CL22_B0_AutoNegNP_Message(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGNP,0x7ff,0)
#define SGMII2_CL22_B0_AUTONEGNP_MESSAGE_MASK                      0x07ff
#define SGMII2_CL22_B0_AUTONEGNP_MESSAGE_ALIGN                     0
#define SGMII2_CL22_B0_AUTONEGNP_MESSAGE_BITS                      11
#define SGMII2_CL22_B0_AUTONEGNP_MESSAGE_SHIFT                     0


/****************************************************************************
 * SGMII2_CL22_B0 :: AutoNegLPAbil2
 ***************************************************************************/
/* SGMII2_CL22_B0 :: AutoNegLPAbil2 :: Next_Page [15:15] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil2_Next_Page(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x8000,15,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil2_Next_Page(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x8000,15)
#define SGMII2_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_MASK               0x8000
#define SGMII2_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN              0
#define SGMII2_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_BITS               1
#define SGMII2_CL22_B0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT              15

/* SGMII2_CL22_B0 :: AutoNegLPAbil2 :: Ack [14:14] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil2_Ack(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x4000,14,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil2_Ack(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x4000,14)
#define SGMII2_CL22_B0_AUTONEGLPABIL2_ACK_MASK                     0x4000
#define SGMII2_CL22_B0_AUTONEGLPABIL2_ACK_ALIGN                    0
#define SGMII2_CL22_B0_AUTONEGLPABIL2_ACK_BITS                     1
#define SGMII2_CL22_B0_AUTONEGLPABIL2_ACK_SHIFT                    14

/* SGMII2_CL22_B0 :: AutoNegLPAbil2 :: Message_Page [13:13] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil2_Message_Page(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x2000,13,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil2_Message_Page(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x2000,13)
#define SGMII2_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK            0x2000
#define SGMII2_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN           0
#define SGMII2_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS            1
#define SGMII2_CL22_B0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT           13

/* SGMII2_CL22_B0 :: AutoNegLPAbil2 :: Ack2 [12:12] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil2_Ack2(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x1000,12,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil2_Ack2(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x1000,12)
#define SGMII2_CL22_B0_AUTONEGLPABIL2_ACK2_MASK                    0x1000
#define SGMII2_CL22_B0_AUTONEGLPABIL2_ACK2_ALIGN                   0
#define SGMII2_CL22_B0_AUTONEGLPABIL2_ACK2_BITS                    1
#define SGMII2_CL22_B0_AUTONEGLPABIL2_ACK2_SHIFT                   12

/* SGMII2_CL22_B0 :: AutoNegLPAbil2 :: Toggle [11:11] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil2_Toggle(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x800,11,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil2_Toggle(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x800,11)
#define SGMII2_CL22_B0_AUTONEGLPABIL2_TOGGLE_MASK                  0x0800
#define SGMII2_CL22_B0_AUTONEGLPABIL2_TOGGLE_ALIGN                 0
#define SGMII2_CL22_B0_AUTONEGLPABIL2_TOGGLE_BITS                  1
#define SGMII2_CL22_B0_AUTONEGLPABIL2_TOGGLE_SHIFT                 11

/* SGMII2_CL22_B0 :: AutoNegLPAbil2 :: Message [10:00] */
#define Wr_SGMII2_CL22_B0_AutoNegLPAbil2_Message(x) WriteRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x7ff,0,x)
#define Rd_SGMII2_CL22_B0_AutoNegLPAbil2_Message(x) ReadRegBits16(SGMII2_CL22_B0_AUTONEGLPABIL2,0x7ff,0)
#define SGMII2_CL22_B0_AUTONEGLPABIL2_MESSAGE_MASK                 0x07ff
#define SGMII2_CL22_B0_AUTONEGLPABIL2_MESSAGE_ALIGN                0
#define SGMII2_CL22_B0_AUTONEGLPABIL2_MESSAGE_BITS                 11
#define SGMII2_CL22_B0_AUTONEGLPABIL2_MESSAGE_SHIFT                0


/****************************************************************************
 * SGMII2_CL22_B0 :: MIIextStat
 ***************************************************************************/
/* SGMII2_CL22_B0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
#define Wr_SGMII2_CL22_B0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIIEXTSTAT,0x8000,15,x)
#define Rd_SGMII2_CL22_B0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIIEXTSTAT,0x8000,15)
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15

/* SGMII2_CL22_B0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
#define Wr_SGMII2_CL22_B0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIIEXTSTAT,0x4000,14,x)
#define Rd_SGMII2_CL22_B0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIIEXTSTAT,0x4000,14)
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14

/* SGMII2_CL22_B0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
#define Wr_SGMII2_CL22_B0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIIEXTSTAT,0x2000,13,x)
#define Rd_SGMII2_CL22_B0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIIEXTSTAT,0x2000,13)
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13

/* SGMII2_CL22_B0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
#define Wr_SGMII2_CL22_B0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_CL22_B0_MIIEXTSTAT,0x1000,12,x)
#define Rd_SGMII2_CL22_B0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_CL22_B0_MIIEXTSTAT,0x1000,12)
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII2_CL22_B0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12

/* SGMII2_CL22_B0 :: MIIextStat :: reserved0 [11:00] */
#define SGMII2_CL22_B0_MIIEXTSTAT_RESERVED0_MASK                   0x0fff
#define SGMII2_CL22_B0_MIIEXTSTAT_RESERVED0_ALIGN                  0
#define SGMII2_CL22_B0_MIIEXTSTAT_RESERVED0_BITS                   12
#define SGMII2_CL22_B0_MIIEXTSTAT_RESERVED0_SHIFT                  0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_TX_afe
 ***************************************************************************/
/****************************************************************************
 * SGMII2_TX_afe :: anaTxAStatus0
 ***************************************************************************/
/* SGMII2_TX_afe :: anaTxAStatus0 :: reserved0 [15:07] */
#define SGMII2_TX_AFE_ANATXASTATUS0_RESERVED0_MASK                 0xff80
#define SGMII2_TX_AFE_ANATXASTATUS0_RESERVED0_ALIGN                0
#define SGMII2_TX_AFE_ANATXASTATUS0_RESERVED0_BITS                 9
#define SGMII2_TX_AFE_ANATXASTATUS0_RESERVED0_SHIFT                7

/* SGMII2_TX_afe :: anaTxAStatus0 :: txdisable_ln [06:06] */
#define Wr_SGMII2_TX_afe_anaTxAStatus0_txdisable_ln(x) WriteRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x40,6,x)
#define Rd_SGMII2_TX_afe_anaTxAStatus0_txdisable_ln(x) ReadRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x40,6)
#define SGMII2_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_MASK              0x0040
#define SGMII2_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_ALIGN             0
#define SGMII2_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_BITS              1
#define SGMII2_TX_AFE_ANATXASTATUS0_TXDISABLE_LN_SHIFT             6

/* SGMII2_TX_afe :: anaTxAStatus0 :: txferr_stky [05:05] */
#define Wr_SGMII2_TX_afe_anaTxAStatus0_txferr_stky(x) WriteRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x20,5,x)
#define Rd_SGMII2_TX_afe_anaTxAStatus0_txferr_stky(x) ReadRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x20,5)
#define SGMII2_TX_AFE_ANATXASTATUS0_TXFERR_STKY_MASK               0x0020
#define SGMII2_TX_AFE_ANATXASTATUS0_TXFERR_STKY_ALIGN              0
#define SGMII2_TX_AFE_ANATXASTATUS0_TXFERR_STKY_BITS               1
#define SGMII2_TX_AFE_ANATXASTATUS0_TXFERR_STKY_SHIFT              5

/* SGMII2_TX_afe :: anaTxAStatus0 :: tbi_mode [04:04] */
#define Wr_SGMII2_TX_afe_anaTxAStatus0_tbi_mode(x) WriteRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x10,4,x)
#define Rd_SGMII2_TX_afe_anaTxAStatus0_tbi_mode(x) ReadRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x10,4)
#define SGMII2_TX_AFE_ANATXASTATUS0_TBI_MODE_MASK                  0x0010
#define SGMII2_TX_AFE_ANATXASTATUS0_TBI_MODE_ALIGN                 0
#define SGMII2_TX_AFE_ANATXASTATUS0_TBI_MODE_BITS                  1
#define SGMII2_TX_AFE_ANATXASTATUS0_TBI_MODE_SHIFT                 4

/* SGMII2_TX_afe :: anaTxAStatus0 :: tx_reset [03:03] */
#define Wr_SGMII2_TX_afe_anaTxAStatus0_tx_reset(x) WriteRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x8,3,x)
#define Rd_SGMII2_TX_afe_anaTxAStatus0_tx_reset(x) ReadRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x8,3)
#define SGMII2_TX_AFE_ANATXASTATUS0_TX_RESET_MASK                  0x0008
#define SGMII2_TX_AFE_ANATXASTATUS0_TX_RESET_ALIGN                 0
#define SGMII2_TX_AFE_ANATXASTATUS0_TX_RESET_BITS                  1
#define SGMII2_TX_AFE_ANATXASTATUS0_TX_RESET_SHIFT                 3

/* SGMII2_TX_afe :: anaTxAStatus0 :: tx_pwrdn [02:02] */
#define Wr_SGMII2_TX_afe_anaTxAStatus0_tx_pwrdn(x) WriteRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x4,2,x)
#define Rd_SGMII2_TX_afe_anaTxAStatus0_tx_pwrdn(x) ReadRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x4,2)
#define SGMII2_TX_AFE_ANATXASTATUS0_TX_PWRDN_MASK                  0x0004
#define SGMII2_TX_AFE_ANATXASTATUS0_TX_PWRDN_ALIGN                 0
#define SGMII2_TX_AFE_ANATXASTATUS0_TX_PWRDN_BITS                  1
#define SGMII2_TX_AFE_ANATXASTATUS0_TX_PWRDN_SHIFT                 2

/* SGMII2_TX_afe :: anaTxAStatus0 :: rltxferr_stky [01:01] */
#define Wr_SGMII2_TX_afe_anaTxAStatus0_rltxferr_stky(x) WriteRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x2,1,x)
#define Rd_SGMII2_TX_afe_anaTxAStatus0_rltxferr_stky(x) ReadRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x2,1)
#define SGMII2_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_MASK             0x0002
#define SGMII2_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_ALIGN            0
#define SGMII2_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_BITS             1
#define SGMII2_TX_AFE_ANATXASTATUS0_RLTXFERR_STKY_SHIFT            1

/* SGMII2_TX_afe :: anaTxAStatus0 :: txpll_lock [00:00] */
#define Wr_SGMII2_TX_afe_anaTxAStatus0_txpll_lock(x) WriteRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x1,0,x)
#define Rd_SGMII2_TX_afe_anaTxAStatus0_txpll_lock(x) ReadRegBits16(SGMII2_TX_AFE_ANATXASTATUS0,0x1,0)
#define SGMII2_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_MASK                0x0001
#define SGMII2_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_ALIGN               0
#define SGMII2_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_BITS                1
#define SGMII2_TX_AFE_ANATXASTATUS0_TXPLL_LOCK_SHIFT               0


/****************************************************************************
 * SGMII2_TX_afe :: anaTxAControl0
 ***************************************************************************/
/* SGMII2_TX_afe :: anaTxAControl0 :: mdio_force [15:15] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_mdio_force(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x8000,15,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_mdio_force(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x8000,15)
#define SGMII2_TX_AFE_ANATXACONTROL0_MDIO_FORCE_MASK               0x8000
#define SGMII2_TX_AFE_ANATXACONTROL0_MDIO_FORCE_ALIGN              0
#define SGMII2_TX_AFE_ANATXACONTROL0_MDIO_FORCE_BITS               1
#define SGMII2_TX_AFE_ANATXACONTROL0_MDIO_FORCE_SHIFT              15

/* SGMII2_TX_afe :: anaTxAControl0 :: force_txclk [14:14] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_force_txclk(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x4000,14,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_force_txclk(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x4000,14)
#define SGMII2_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_MASK              0x4000
#define SGMII2_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_ALIGN             0
#define SGMII2_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_BITS              1
#define SGMII2_TX_AFE_ANATXACONTROL0_FORCE_TXCLK_SHIFT             14

/* SGMII2_TX_afe :: anaTxAControl0 :: tx1g_fifo_rst [13:13] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_tx1g_fifo_rst(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x2000,13,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_tx1g_fifo_rst(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x2000,13)
#define SGMII2_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_MASK            0x2000
#define SGMII2_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_ALIGN           0
#define SGMII2_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_BITS            1
#define SGMII2_TX_AFE_ANATXACONTROL0_TX1G_FIFO_RST_SHIFT           13

/* SGMII2_TX_afe :: anaTxAControl0 :: force_ext_frst_SM [12:12] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_force_ext_frst_SM(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x1000,12,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_force_ext_frst_SM(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x1000,12)
#define SGMII2_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_MASK        0x1000
#define SGMII2_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_ALIGN       0
#define SGMII2_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_BITS        1
#define SGMII2_TX_AFE_ANATXACONTROL0_FORCE_EXT_FRST_SM_SHIFT       12

/* SGMII2_TX_afe :: anaTxAControl0 :: catch_all_8b10b_dis [11:11] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_catch_all_8b10b_dis(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x800,11,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_catch_all_8b10b_dis(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x800,11)
#define SGMII2_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_MASK      0x0800
#define SGMII2_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_ALIGN     0
#define SGMII2_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_BITS      1
#define SGMII2_TX_AFE_ANATXACONTROL0_CATCH_ALL_8B10B_DIS_SHIFT     11

/* SGMII2_TX_afe :: anaTxAControl0 :: txck_dme_en_SM [10:10] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_txck_dme_en_SM(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x400,10,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_txck_dme_en_SM(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x400,10)
#define SGMII2_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_MASK           0x0400
#define SGMII2_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_ALIGN          0
#define SGMII2_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_BITS           1
#define SGMII2_TX_AFE_ANATXACONTROL0_TXCK_DME_EN_SM_SHIFT          10

/* SGMII2_TX_afe :: anaTxAControl0 :: gloopOutDis [09:09] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_gloopOutDis(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x200,9,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_gloopOutDis(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x200,9)
#define SGMII2_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_MASK              0x0200
#define SGMII2_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_ALIGN             0
#define SGMII2_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_BITS              1
#define SGMII2_TX_AFE_ANATXACONTROL0_GLOOPOUTDIS_SHIFT             9

/* SGMII2_TX_afe :: anaTxAControl0 :: prbs_en [08:08] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_prbs_en(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x100,8,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_prbs_en(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x100,8)
#define SGMII2_TX_AFE_ANATXACONTROL0_PRBS_EN_MASK                  0x0100
#define SGMII2_TX_AFE_ANATXACONTROL0_PRBS_EN_ALIGN                 0
#define SGMII2_TX_AFE_ANATXACONTROL0_PRBS_EN_BITS                  1
#define SGMII2_TX_AFE_ANATXACONTROL0_PRBS_EN_SHIFT                 8

/* SGMII2_TX_afe :: anaTxAControl0 :: pckt_en [07:07] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_pckt_en(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x80,7,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_pckt_en(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x80,7)
#define SGMII2_TX_AFE_ANATXACONTROL0_PCKT_EN_MASK                  0x0080
#define SGMII2_TX_AFE_ANATXACONTROL0_PCKT_EN_ALIGN                 0
#define SGMII2_TX_AFE_ANATXACONTROL0_PCKT_EN_BITS                  1
#define SGMII2_TX_AFE_ANATXACONTROL0_PCKT_EN_SHIFT                 7

/* SGMII2_TX_afe :: anaTxAControl0 :: pckt_strt [06:06] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_pckt_strt(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x40,6,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_pckt_strt(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x40,6)
#define SGMII2_TX_AFE_ANATXACONTROL0_PCKT_STRT_MASK                0x0040
#define SGMII2_TX_AFE_ANATXACONTROL0_PCKT_STRT_ALIGN               0
#define SGMII2_TX_AFE_ANATXACONTROL0_PCKT_STRT_BITS                1
#define SGMII2_TX_AFE_ANATXACONTROL0_PCKT_STRT_SHIFT               6

/* SGMII2_TX_afe :: anaTxAControl0 :: txpol_flip [05:05] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_txpol_flip(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x20,5,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_txpol_flip(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x20,5)
#define SGMII2_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_MASK               0x0020
#define SGMII2_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_ALIGN              0
#define SGMII2_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_BITS               1
#define SGMII2_TX_AFE_ANATXACONTROL0_TXPOL_FLIP_SHIFT              5

/* SGMII2_TX_afe :: anaTxAControl0 :: rtbi_flip [04:04] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_rtbi_flip(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x10,4,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_rtbi_flip(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x10,4)
#define SGMII2_TX_AFE_ANATXACONTROL0_RTBI_FLIP_MASK                0x0010
#define SGMII2_TX_AFE_ANATXACONTROL0_RTBI_FLIP_ALIGN               0
#define SGMII2_TX_AFE_ANATXACONTROL0_RTBI_FLIP_BITS                1
#define SGMII2_TX_AFE_ANATXACONTROL0_RTBI_FLIP_SHIFT               4

/* SGMII2_TX_afe :: anaTxAControl0 :: eden_r [03:03] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_eden_r(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x8,3,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_eden_r(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x8,3)
#define SGMII2_TX_AFE_ANATXACONTROL0_EDEN_R_MASK                   0x0008
#define SGMII2_TX_AFE_ANATXACONTROL0_EDEN_R_ALIGN                  0
#define SGMII2_TX_AFE_ANATXACONTROL0_EDEN_R_BITS                   1
#define SGMII2_TX_AFE_ANATXACONTROL0_EDEN_R_SHIFT                  3

/* SGMII2_TX_afe :: anaTxAControl0 :: eden_force_r [02:02] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_eden_force_r(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x4,2,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_eden_force_r(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x4,2)
#define SGMII2_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_MASK             0x0004
#define SGMII2_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_ALIGN            0
#define SGMII2_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_BITS             1
#define SGMII2_TX_AFE_ANATXACONTROL0_EDEN_FORCE_R_SHIFT            2

/* SGMII2_TX_afe :: anaTxAControl0 :: txpat_en [01:01] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_txpat_en(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x2,1,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_txpat_en(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x2,1)
#define SGMII2_TX_AFE_ANATXACONTROL0_TXPAT_EN_MASK                 0x0002
#define SGMII2_TX_AFE_ANATXACONTROL0_TXPAT_EN_ALIGN                0
#define SGMII2_TX_AFE_ANATXACONTROL0_TXPAT_EN_BITS                 1
#define SGMII2_TX_AFE_ANATXACONTROL0_TXPAT_EN_SHIFT                1

/* SGMII2_TX_afe :: anaTxAControl0 :: tx_mdata_en [00:00] */
#define Wr_SGMII2_TX_afe_anaTxAControl0_tx_mdata_en(x) WriteRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x1,0,x)
#define Rd_SGMII2_TX_afe_anaTxAControl0_tx_mdata_en(x) ReadRegBits16(SGMII2_TX_AFE_ANATXACONTROL0,0x1,0)
#define SGMII2_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_MASK              0x0001
#define SGMII2_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_ALIGN             0
#define SGMII2_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_BITS              1
#define SGMII2_TX_AFE_ANATXACONTROL0_TX_MDATA_EN_SHIFT             0


/****************************************************************************
 * SGMII2_TX_afe :: anaTxmdata0
 ***************************************************************************/
/* SGMII2_TX_afe :: anaTxmdata0 :: txTestMuxSel [15:13] */
#define Wr_SGMII2_TX_afe_anaTxmdata0_txTestMuxSel(x) WriteRegBits16(SGMII2_TX_AFE_ANATXMDATA0,0xe000,13,x)
#define Rd_SGMII2_TX_afe_anaTxmdata0_txTestMuxSel(x) ReadRegBits16(SGMII2_TX_AFE_ANATXMDATA0,0xe000,13)
#define SGMII2_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_MASK                0xe000
#define SGMII2_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_ALIGN               0
#define SGMII2_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_BITS                3
#define SGMII2_TX_AFE_ANATXMDATA0_TXTESTMUXSEL_SHIFT               13

/* SGMII2_TX_afe :: anaTxmdata0 :: rlfifo_tstsel [12:10] */
#define Wr_SGMII2_TX_afe_anaTxmdata0_rlfifo_tstsel(x) WriteRegBits16(SGMII2_TX_AFE_ANATXMDATA0,0x1c00,10,x)
#define Rd_SGMII2_TX_afe_anaTxmdata0_rlfifo_tstsel(x) ReadRegBits16(SGMII2_TX_AFE_ANATXMDATA0,0x1c00,10)
#define SGMII2_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_MASK               0x1c00
#define SGMII2_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_ALIGN              0
#define SGMII2_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_BITS               3
#define SGMII2_TX_AFE_ANATXMDATA0_RLFIFO_TSTSEL_SHIFT              10

/* SGMII2_TX_afe :: anaTxmdata0 :: TxMdioTstDataL [09:00] */
#define Wr_SGMII2_TX_afe_anaTxmdata0_TxMdioTstDataL(x) WriteRegBits16(SGMII2_TX_AFE_ANATXMDATA0,0x3ff,0,x)
#define Rd_SGMII2_TX_afe_anaTxmdata0_TxMdioTstDataL(x) ReadRegBits16(SGMII2_TX_AFE_ANATXMDATA0,0x3ff,0)
#define SGMII2_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_MASK              0x03ff
#define SGMII2_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_ALIGN             0
#define SGMII2_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_BITS              10
#define SGMII2_TX_AFE_ANATXMDATA0_TXMDIOTSTDATAL_SHIFT             0


/****************************************************************************
 * SGMII2_TX_afe :: anaTxmdata1
 ***************************************************************************/
/* SGMII2_TX_afe :: anaTxmdata1 :: reserved0 [15:14] */
#define SGMII2_TX_AFE_ANATXMDATA1_RESERVED0_MASK                   0xc000
#define SGMII2_TX_AFE_ANATXMDATA1_RESERVED0_ALIGN                  0
#define SGMII2_TX_AFE_ANATXMDATA1_RESERVED0_BITS                   2
#define SGMII2_TX_AFE_ANATXMDATA1_RESERVED0_SHIFT                  14

/* SGMII2_TX_afe :: anaTxmdata1 :: tx_elecidle [13:13] */
#define Wr_SGMII2_TX_afe_anaTxmdata1_tx_elecidle(x) WriteRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x2000,13,x)
#define Rd_SGMII2_TX_afe_anaTxmdata1_tx_elecidle(x) ReadRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x2000,13)
#define SGMII2_TX_AFE_ANATXMDATA1_TX_ELECIDLE_MASK                 0x2000
#define SGMII2_TX_AFE_ANATXMDATA1_TX_ELECIDLE_ALIGN                0
#define SGMII2_TX_AFE_ANATXMDATA1_TX_ELECIDLE_BITS                 1
#define SGMII2_TX_AFE_ANATXMDATA1_TX_ELECIDLE_SHIFT                13

/* SGMII2_TX_afe :: anaTxmdata1 :: glpbk_clk_en [12:12] */
#define Wr_SGMII2_TX_afe_anaTxmdata1_glpbk_clk_en(x) WriteRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x1000,12,x)
#define Rd_SGMII2_TX_afe_anaTxmdata1_glpbk_clk_en(x) ReadRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x1000,12)
#define SGMII2_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_MASK                0x1000
#define SGMII2_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_ALIGN               0
#define SGMII2_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_BITS                1
#define SGMII2_TX_AFE_ANATXMDATA1_GLPBK_CLK_EN_SHIFT               12

/* SGMII2_TX_afe :: anaTxmdata1 :: pre_emph_stair_rev_en [11:11] */
#define Wr_SGMII2_TX_afe_anaTxmdata1_pre_emph_stair_rev_en(x) WriteRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x800,11,x)
#define Rd_SGMII2_TX_afe_anaTxmdata1_pre_emph_stair_rev_en(x) ReadRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x800,11)
#define SGMII2_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_MASK       0x0800
#define SGMII2_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_ALIGN      0
#define SGMII2_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_BITS       1
#define SGMII2_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_REV_EN_SHIFT      11

/* SGMII2_TX_afe :: anaTxmdata1 :: pre_emph_stair_en [10:10] */
#define Wr_SGMII2_TX_afe_anaTxmdata1_pre_emph_stair_en(x) WriteRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x400,10,x)
#define Rd_SGMII2_TX_afe_anaTxmdata1_pre_emph_stair_en(x) ReadRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x400,10)
#define SGMII2_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_MASK           0x0400
#define SGMII2_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_ALIGN          0
#define SGMII2_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_BITS           1
#define SGMII2_TX_AFE_ANATXMDATA1_PRE_EMPH_STAIR_EN_SHIFT          10

/* SGMII2_TX_afe :: anaTxmdata1 :: TxMdioTstDataH [09:00] */
#define Wr_SGMII2_TX_afe_anaTxmdata1_TxMdioTstDataH(x) WriteRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x3ff,0,x)
#define Rd_SGMII2_TX_afe_anaTxmdata1_TxMdioTstDataH(x) ReadRegBits16(SGMII2_TX_AFE_ANATXMDATA1,0x3ff,0)
#define SGMII2_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_MASK              0x03ff
#define SGMII2_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_ALIGN             0
#define SGMII2_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_BITS              10
#define SGMII2_TX_AFE_ANATXMDATA1_TXMDIOTSTDATAH_SHIFT             0


/****************************************************************************
 * SGMII2_TX_afe :: control0
 ***************************************************************************/
/* SGMII2_TX_afe :: control0 :: Fix_10units_en [15:15] */
#define Wr_SGMII2_TX_afe_control0_Fix_10units_en(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL0,0x8000,15,x)
#define Rd_SGMII2_TX_afe_control0_Fix_10units_en(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL0,0x8000,15)
#define SGMII2_TX_AFE_CONTROL0_FIX_10UNITS_EN_MASK                 0x8000
#define SGMII2_TX_AFE_CONTROL0_FIX_10UNITS_EN_ALIGN                0
#define SGMII2_TX_AFE_CONTROL0_FIX_10UNITS_EN_BITS                 1
#define SGMII2_TX_AFE_CONTROL0_FIX_10UNITS_EN_SHIFT                15

/* SGMII2_TX_afe :: control0 :: Quarter_unit_en [14:14] */
#define Wr_SGMII2_TX_afe_control0_Quarter_unit_en(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL0,0x4000,14,x)
#define Rd_SGMII2_TX_afe_control0_Quarter_unit_en(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL0,0x4000,14)
#define SGMII2_TX_AFE_CONTROL0_QUARTER_UNIT_EN_MASK                0x4000
#define SGMII2_TX_AFE_CONTROL0_QUARTER_UNIT_EN_ALIGN               0
#define SGMII2_TX_AFE_CONTROL0_QUARTER_UNIT_EN_BITS                1
#define SGMII2_TX_AFE_CONTROL0_QUARTER_UNIT_EN_SHIFT               14

/* SGMII2_TX_afe :: control0 :: main_control [13:08] */
#define Wr_SGMII2_TX_afe_control0_main_control(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL0,0x3f00,8,x)
#define Rd_SGMII2_TX_afe_control0_main_control(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL0,0x3f00,8)
#define SGMII2_TX_AFE_CONTROL0_MAIN_CONTROL_MASK                   0x3f00
#define SGMII2_TX_AFE_CONTROL0_MAIN_CONTROL_ALIGN                  0
#define SGMII2_TX_AFE_CONTROL0_MAIN_CONTROL_BITS                   6
#define SGMII2_TX_AFE_CONTROL0_MAIN_CONTROL_SHIFT                  8

/* SGMII2_TX_afe :: control0 :: reserved_7 [07:07] */
#define SGMII2_TX_AFE_CONTROL0_RESERVED_7_MASK                     0x0080
#define SGMII2_TX_AFE_CONTROL0_RESERVED_7_ALIGN                    0
#define SGMII2_TX_AFE_CONTROL0_RESERVED_7_BITS                     1
#define SGMII2_TX_AFE_CONTROL0_RESERVED_7_SHIFT                    7

/* SGMII2_TX_afe :: control0 :: rxdetect_th [06:05] */
#define Wr_SGMII2_TX_afe_control0_rxdetect_th(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL0,0x60,5,x)
#define Rd_SGMII2_TX_afe_control0_rxdetect_th(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL0,0x60,5)
#define SGMII2_TX_AFE_CONTROL0_RXDETECT_TH_MASK                    0x0060
#define SGMII2_TX_AFE_CONTROL0_RXDETECT_TH_ALIGN                   0
#define SGMII2_TX_AFE_CONTROL0_RXDETECT_TH_BITS                    2
#define SGMII2_TX_AFE_CONTROL0_RXDETECT_TH_SHIFT                   5

/* SGMII2_TX_afe :: control0 :: idle_ena [04:04] */
#define Wr_SGMII2_TX_afe_control0_idle_ena(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL0,0x10,4,x)
#define Rd_SGMII2_TX_afe_control0_idle_ena(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL0,0x10,4)
#define SGMII2_TX_AFE_CONTROL0_IDLE_ENA_MASK                       0x0010
#define SGMII2_TX_AFE_CONTROL0_IDLE_ENA_ALIGN                      0
#define SGMII2_TX_AFE_CONTROL0_IDLE_ENA_BITS                       1
#define SGMII2_TX_AFE_CONTROL0_IDLE_ENA_SHIFT                      4

/* SGMII2_TX_afe :: control0 :: reserved_3_2 [03:02] */
#define SGMII2_TX_AFE_CONTROL0_RESERVED_3_2_MASK                   0x000c
#define SGMII2_TX_AFE_CONTROL0_RESERVED_3_2_ALIGN                  0
#define SGMII2_TX_AFE_CONTROL0_RESERVED_3_2_BITS                   2
#define SGMII2_TX_AFE_CONTROL0_RESERVED_3_2_SHIFT                  2

/* SGMII2_TX_afe :: control0 :: Testsel [01:01] */
#define Wr_SGMII2_TX_afe_control0_Testsel(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL0,0x2,1,x)
#define Rd_SGMII2_TX_afe_control0_Testsel(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL0,0x2,1)
#define SGMII2_TX_AFE_CONTROL0_TESTSEL_MASK                        0x0002
#define SGMII2_TX_AFE_CONTROL0_TESTSEL_ALIGN                       0
#define SGMII2_TX_AFE_CONTROL0_TESTSEL_BITS                        1
#define SGMII2_TX_AFE_CONTROL0_TESTSEL_SHIFT                       1

/* SGMII2_TX_afe :: control0 :: tx_pwrdn [00:00] */
#define Wr_SGMII2_TX_afe_control0_tx_pwrdn(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL0,0x1,0,x)
#define Rd_SGMII2_TX_afe_control0_tx_pwrdn(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL0,0x1,0)
#define SGMII2_TX_AFE_CONTROL0_TX_PWRDN_MASK                       0x0001
#define SGMII2_TX_AFE_CONTROL0_TX_PWRDN_ALIGN                      0
#define SGMII2_TX_AFE_CONTROL0_TX_PWRDN_BITS                       1
#define SGMII2_TX_AFE_CONTROL0_TX_PWRDN_SHIFT                      0


/****************************************************************************
 * SGMII2_TX_afe :: control1
 ***************************************************************************/
/* SGMII2_TX_afe :: control1 :: Slew_rate_control [15:14] */
#define Wr_SGMII2_TX_afe_control1_Slew_rate_control(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL1,0xc000,14,x)
#define Rd_SGMII2_TX_afe_control1_Slew_rate_control(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL1,0xc000,14)
#define SGMII2_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_MASK              0xc000
#define SGMII2_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_ALIGN             0
#define SGMII2_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_BITS              2
#define SGMII2_TX_AFE_CONTROL1_SLEW_RATE_CONTROL_SHIFT             14

/* SGMII2_TX_afe :: control1 :: reserved_29 [13:13] */
#define SGMII2_TX_AFE_CONTROL1_RESERVED_29_MASK                    0x2000
#define SGMII2_TX_AFE_CONTROL1_RESERVED_29_ALIGN                   0
#define SGMII2_TX_AFE_CONTROL1_RESERVED_29_BITS                    1
#define SGMII2_TX_AFE_CONTROL1_RESERVED_29_SHIFT                   13

/* SGMII2_TX_afe :: control1 :: Post_enable [12:12] */
#define Wr_SGMII2_TX_afe_control1_Post_enable(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL1,0x1000,12,x)
#define Rd_SGMII2_TX_afe_control1_Post_enable(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL1,0x1000,12)
#define SGMII2_TX_AFE_CONTROL1_POST_ENABLE_MASK                    0x1000
#define SGMII2_TX_AFE_CONTROL1_POST_ENABLE_ALIGN                   0
#define SGMII2_TX_AFE_CONTROL1_POST_ENABLE_BITS                    1
#define SGMII2_TX_AFE_CONTROL1_POST_ENABLE_SHIFT                   12

/* SGMII2_TX_afe :: control1 :: Post_control [11:06] */
#define Wr_SGMII2_TX_afe_control1_Post_control(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL1,0xfc0,6,x)
#define Rd_SGMII2_TX_afe_control1_Post_control(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL1,0xfc0,6)
#define SGMII2_TX_AFE_CONTROL1_POST_CONTROL_MASK                   0x0fc0
#define SGMII2_TX_AFE_CONTROL1_POST_CONTROL_ALIGN                  0
#define SGMII2_TX_AFE_CONTROL1_POST_CONTROL_BITS                   6
#define SGMII2_TX_AFE_CONTROL1_POST_CONTROL_SHIFT                  6

/* SGMII2_TX_afe :: control1 :: reserved_21 [05:05] */
#define SGMII2_TX_AFE_CONTROL1_RESERVED_21_MASK                    0x0020
#define SGMII2_TX_AFE_CONTROL1_RESERVED_21_ALIGN                   0
#define SGMII2_TX_AFE_CONTROL1_RESERVED_21_BITS                    1
#define SGMII2_TX_AFE_CONTROL1_RESERVED_21_SHIFT                   5

/* SGMII2_TX_afe :: control1 :: Pwd_lvl2pi [04:04] */
#define Wr_SGMII2_TX_afe_control1_Pwd_lvl2pi(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL1,0x10,4,x)
#define Rd_SGMII2_TX_afe_control1_Pwd_lvl2pi(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL1,0x10,4)
#define SGMII2_TX_AFE_CONTROL1_PWD_LVL2PI_MASK                     0x0010
#define SGMII2_TX_AFE_CONTROL1_PWD_LVL2PI_ALIGN                    0
#define SGMII2_TX_AFE_CONTROL1_PWD_LVL2PI_BITS                     1
#define SGMII2_TX_AFE_CONTROL1_PWD_LVL2PI_SHIFT                    4

/* SGMII2_TX_afe :: control1 :: PI_bw_sel [03:03] */
#define Wr_SGMII2_TX_afe_control1_PI_bw_sel(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL1,0x8,3,x)
#define Rd_SGMII2_TX_afe_control1_PI_bw_sel(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL1,0x8,3)
#define SGMII2_TX_AFE_CONTROL1_PI_BW_SEL_MASK                      0x0008
#define SGMII2_TX_AFE_CONTROL1_PI_BW_SEL_ALIGN                     0
#define SGMII2_TX_AFE_CONTROL1_PI_BW_SEL_BITS                      1
#define SGMII2_TX_AFE_CONTROL1_PI_BW_SEL_SHIFT                     3

/* SGMII2_TX_afe :: control1 :: Const_Impedance [02:02] */
#define Wr_SGMII2_TX_afe_control1_Const_Impedance(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL1,0x4,2,x)
#define Rd_SGMII2_TX_afe_control1_Const_Impedance(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL1,0x4,2)
#define SGMII2_TX_AFE_CONTROL1_CONST_IMPEDANCE_MASK                0x0004
#define SGMII2_TX_AFE_CONTROL1_CONST_IMPEDANCE_ALIGN               0
#define SGMII2_TX_AFE_CONTROL1_CONST_IMPEDANCE_BITS                1
#define SGMII2_TX_AFE_CONTROL1_CONST_IMPEDANCE_SHIFT               2

/* SGMII2_TX_afe :: control1 :: Amp_mode [01:01] */
#define Wr_SGMII2_TX_afe_control1_Amp_mode(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL1,0x2,1,x)
#define Rd_SGMII2_TX_afe_control1_Amp_mode(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL1,0x2,1)
#define SGMII2_TX_AFE_CONTROL1_AMP_MODE_MASK                       0x0002
#define SGMII2_TX_AFE_CONTROL1_AMP_MODE_ALIGN                      0
#define SGMII2_TX_AFE_CONTROL1_AMP_MODE_BITS                       1
#define SGMII2_TX_AFE_CONTROL1_AMP_MODE_SHIFT                      1

/* SGMII2_TX_afe :: control1 :: Vdd1p0_enb [00:00] */
#define Wr_SGMII2_TX_afe_control1_Vdd1p0_enb(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL1,0x1,0,x)
#define Rd_SGMII2_TX_afe_control1_Vdd1p0_enb(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL1,0x1,0)
#define SGMII2_TX_AFE_CONTROL1_VDD1P0_ENB_MASK                     0x0001
#define SGMII2_TX_AFE_CONTROL1_VDD1P0_ENB_ALIGN                    0
#define SGMII2_TX_AFE_CONTROL1_VDD1P0_ENB_BITS                     1
#define SGMII2_TX_AFE_CONTROL1_VDD1P0_ENB_SHIFT                    0


/****************************************************************************
 * SGMII2_TX_afe :: control2
 ***************************************************************************/
/* SGMII2_TX_afe :: control2 :: leakage_test [15:15] */
#define Wr_SGMII2_TX_afe_control2_leakage_test(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL2,0x8000,15,x)
#define Rd_SGMII2_TX_afe_control2_leakage_test(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL2,0x8000,15)
#define SGMII2_TX_AFE_CONTROL2_LEAKAGE_TEST_MASK                   0x8000
#define SGMII2_TX_AFE_CONTROL2_LEAKAGE_TEST_ALIGN                  0
#define SGMII2_TX_AFE_CONTROL2_LEAKAGE_TEST_BITS                   1
#define SGMII2_TX_AFE_CONTROL2_LEAKAGE_TEST_SHIFT                  15

/* SGMII2_TX_afe :: control2 :: Vdd_noise_cncl_en [14:14] */
#define Wr_SGMII2_TX_afe_control2_Vdd_noise_cncl_en(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL2,0x4000,14,x)
#define Rd_SGMII2_TX_afe_control2_Vdd_noise_cncl_en(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL2,0x4000,14)
#define SGMII2_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_MASK              0x4000
#define SGMII2_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_ALIGN             0
#define SGMII2_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_BITS              1
#define SGMII2_TX_AFE_CONTROL2_VDD_NOISE_CNCL_EN_SHIFT             14

/* SGMII2_TX_afe :: control2 :: Noise_cncl_bias [13:10] */
#define Wr_SGMII2_TX_afe_control2_Noise_cncl_bias(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL2,0x3c00,10,x)
#define Rd_SGMII2_TX_afe_control2_Noise_cncl_bias(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL2,0x3c00,10)
#define SGMII2_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_MASK                0x3c00
#define SGMII2_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_ALIGN               0
#define SGMII2_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_BITS                4
#define SGMII2_TX_AFE_CONTROL2_NOISE_CNCL_BIAS_SHIFT               10

/* SGMII2_TX_afe :: control2 :: Vdd_noise_shape [09:07] */
#define Wr_SGMII2_TX_afe_control2_Vdd_noise_shape(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL2,0x380,7,x)
#define Rd_SGMII2_TX_afe_control2_Vdd_noise_shape(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL2,0x380,7)
#define SGMII2_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_MASK                0x0380
#define SGMII2_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_ALIGN               0
#define SGMII2_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_BITS                3
#define SGMII2_TX_AFE_CONTROL2_VDD_NOISE_SHAPE_SHIFT               7

/* SGMII2_TX_afe :: control2 :: tx_pon [06:03] */
#define Wr_SGMII2_TX_afe_control2_tx_pon(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL2,0x78,3,x)
#define Rd_SGMII2_TX_afe_control2_tx_pon(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL2,0x78,3)
#define SGMII2_TX_AFE_CONTROL2_TX_PON_MASK                         0x0078
#define SGMII2_TX_AFE_CONTROL2_TX_PON_ALIGN                        0
#define SGMII2_TX_AFE_CONTROL2_TX_PON_BITS                         4
#define SGMII2_TX_AFE_CONTROL2_TX_PON_SHIFT                        3

/* SGMII2_TX_afe :: control2 :: ticksel [02:01] */
#define Wr_SGMII2_TX_afe_control2_ticksel(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL2,0x6,1,x)
#define Rd_SGMII2_TX_afe_control2_ticksel(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL2,0x6,1)
#define SGMII2_TX_AFE_CONTROL2_TICKSEL_MASK                        0x0006
#define SGMII2_TX_AFE_CONTROL2_TICKSEL_ALIGN                       0
#define SGMII2_TX_AFE_CONTROL2_TICKSEL_BITS                        2
#define SGMII2_TX_AFE_CONTROL2_TICKSEL_SHIFT                       1

/* SGMII2_TX_afe :: control2 :: testck_en [00:00] */
#define Wr_SGMII2_TX_afe_control2_testck_en(x) WriteRegBits16(SGMII2_TX_AFE_CONTROL2,0x1,0,x)
#define Rd_SGMII2_TX_afe_control2_testck_en(x) ReadRegBits16(SGMII2_TX_AFE_CONTROL2,0x1,0)
#define SGMII2_TX_AFE_CONTROL2_TESTCK_EN_MASK                      0x0001
#define SGMII2_TX_AFE_CONTROL2_TESTCK_EN_ALIGN                     0
#define SGMII2_TX_AFE_CONTROL2_TESTCK_EN_BITS                      1
#define SGMII2_TX_AFE_CONTROL2_TESTCK_EN_SHIFT                     0


/****************************************************************************
 * SGMII2_TX_afe :: control3
 ***************************************************************************/
/* SGMII2_TX_afe :: control3 :: reserved_63_48 [15:00] */
#define SGMII2_TX_AFE_CONTROL3_RESERVED_63_48_MASK                 0xffff
#define SGMII2_TX_AFE_CONTROL3_RESERVED_63_48_ALIGN                0
#define SGMII2_TX_AFE_CONTROL3_RESERVED_63_48_BITS                 16
#define SGMII2_TX_AFE_CONTROL3_RESERVED_63_48_SHIFT                0


/****************************************************************************
 * SGMII2_TX_afe :: interp
 ***************************************************************************/
/* SGMII2_TX_afe :: interp :: reserved0 [15:07] */
#define SGMII2_TX_AFE_INTERP_RESERVED0_MASK                        0xff80
#define SGMII2_TX_AFE_INTERP_RESERVED0_ALIGN                       0
#define SGMII2_TX_AFE_INTERP_RESERVED0_BITS                        9
#define SGMII2_TX_AFE_INTERP_RESERVED0_SHIFT                       7

/* SGMII2_TX_afe :: interp :: interp_ctrl_quadrant [06:05] */
#define Wr_SGMII2_TX_afe_interp_interp_ctrl_quadrant(x) WriteRegBits16(SGMII2_TX_AFE_INTERP,0x60,5,x)
#define Rd_SGMII2_TX_afe_interp_interp_ctrl_quadrant(x) ReadRegBits16(SGMII2_TX_AFE_INTERP,0x60,5)
#define SGMII2_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_MASK             0x0060
#define SGMII2_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_ALIGN            0
#define SGMII2_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_BITS             2
#define SGMII2_TX_AFE_INTERP_INTERP_CTRL_QUADRANT_SHIFT            5

/* SGMII2_TX_afe :: interp :: interp_ctrl_phs [04:00] */
#define Wr_SGMII2_TX_afe_interp_interp_ctrl_phs(x) WriteRegBits16(SGMII2_TX_AFE_INTERP,0x1f,0,x)
#define Rd_SGMII2_TX_afe_interp_interp_ctrl_phs(x) ReadRegBits16(SGMII2_TX_AFE_INTERP,0x1f,0)
#define SGMII2_TX_AFE_INTERP_INTERP_CTRL_PHS_MASK                  0x001f
#define SGMII2_TX_AFE_INTERP_INTERP_CTRL_PHS_ALIGN                 0
#define SGMII2_TX_AFE_INTERP_INTERP_CTRL_PHS_BITS                  5
#define SGMII2_TX_AFE_INTERP_INTERP_CTRL_PHS_SHIFT                 0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_RX_afe
 ***************************************************************************/
/****************************************************************************
 * SGMII2_RX_afe :: anaRxStatus
 ***************************************************************************/
/* union - case sigdet_Status [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: cx4_sigdet [15:15] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sigdet_Status_cx4_sigdet(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x8000,15,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sigdet_Status_cx4_sigdet(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x8000,15)
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_MASK    0x8000
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_BITS    1
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CX4_SIGDET_SHIFT   15

/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [14:13] */
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_MASK     0x6000
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_BITS     2
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED0_SHIFT    13

/* SGMII2_RX_afe :: anaRxStatus :: rxSeqDone [12:12] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sigdet_Status_rxSeqDone(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x1000,12,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sigdet_Status_rxSeqDone(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x1000,12)
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_MASK     0x1000
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RXSEQDONE_SHIFT    12

/* SGMII2_RX_afe :: anaRxStatus :: rx_sigdet_ll [11:11] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sigdet_Status_rx_sigdet_ll(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x800,11,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sigdet_Status_rx_sigdet_ll(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x800,11)
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_MASK  0x0800
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_BITS  1
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_SIGDET_LL_SHIFT 11

/* SGMII2_RX_afe :: anaRxStatus :: cs4_sigdet_ll [10:10] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sigdet_Status_cs4_sigdet_ll(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x400,10,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sigdet_Status_cs4_sigdet_ll(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x400,10)
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_MASK 0x0400
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_CS4_SIGDET_LL_SHIFT 10

/* SGMII2_RX_afe :: anaRxStatus :: rx_reset [09:09] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sigdet_Status_rx_reset(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x200,9,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sigdet_Status_rx_reset(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x200,9)
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_MASK      0x0200
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_ALIGN     0
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_BITS      1
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_RESET_SHIFT     9

/* SGMII2_RX_afe :: anaRxStatus :: rx_pwrdn [08:08] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sigdet_Status_rx_pwrdn(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x100,8,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sigdet_Status_rx_pwrdn(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS,0x100,8)
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_MASK      0x0100
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_ALIGN     0
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_BITS      1
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RX_PWRDN_SHIFT     8

/* SGMII2_RX_afe :: anaRxStatus :: reserved1 [07:00] */
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_MASK     0x00ff
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_BITS     8
#define SGMII2_RX_AFE_ANARXSTATUS_SIGDET_STATUS_RESERVED1_SHIFT    0


/* union - case sync_Status [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:11] */
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_MASK       0xf800
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_BITS       5
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED0_SHIFT      11

/* SGMII2_RX_afe :: anaRxStatus :: test_acq_en [10:10] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sync_Status_test_acq_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x400,10,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sync_Status_test_acq_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x400,10)
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_MASK     0x0400
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_TEST_ACQ_EN_SHIFT    10

/* SGMII2_RX_afe :: anaRxStatus :: reserved1 [09:09] */
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_MASK       0x0200
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_BITS       1
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED1_SHIFT      9

/* SGMII2_RX_afe :: anaRxStatus :: rxSeqStart [08:08] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sync_Status_rxSeqStart(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x100,8,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sync_Status_rxSeqStart(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x100,8)
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_MASK      0x0100
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_ALIGN     0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_BITS      1
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQSTART_SHIFT     8

/* SGMII2_RX_afe :: anaRxStatus :: mux_comadj_sync_status [07:07] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sync_Status_mux_comadj_sync_status(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x80,7,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sync_Status_mux_comadj_sync_status(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x80,7)
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_MASK 0x0080
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_MUX_COMADJ_SYNC_STATUS_SHIFT 7

/* SGMII2_RX_afe :: anaRxStatus :: sync_status [06:06] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sync_Status_sync_status(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x40,6,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sync_Status_sync_status(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x40,6)
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_MASK     0x0040
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_SYNC_STATUS_SHIFT    6

/* SGMII2_RX_afe :: anaRxStatus :: rx_sigdet [05:05] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sync_Status_rx_sigdet(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sync_Status_rx_sigdet(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x20,5)
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_MASK       0x0020
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_BITS       1
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RX_SIGDET_SHIFT      5

/* SGMII2_RX_afe :: anaRxStatus :: reserved2 [04:03] */
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_MASK       0x0018
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_BITS       2
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RESERVED2_SHIFT      3

/* SGMII2_RX_afe :: anaRxStatus :: saturate_status [02:02] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sync_Status_saturate_status(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sync_Status_saturate_status(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x4,2)
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_MASK 0x0004
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_SATURATE_STATUS_SHIFT 2

/* SGMII2_RX_afe :: anaRxStatus :: cx4_sigdet [01:01] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sync_Status_cx4_sigdet(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x2,1,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sync_Status_cx4_sigdet(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x2,1)
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_MASK      0x0002
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_ALIGN     0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_BITS      1
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_CX4_SIGDET_SHIFT     1

/* SGMII2_RX_afe :: anaRxStatus :: rxSeqDone [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_sync_Status_rxSeqDone(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_sync_Status_rxSeqDone(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_MASK       0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_BITS       1
#define SGMII2_RX_AFE_ANARXSTATUS_SYNC_STATUS_RXSEQDONE_SHIFT      0


/* union - case rxTestSel_0 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:10] */
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_MASK       0xfc00
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_BITS       6
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED0_SHIFT      10

/* SGMII2_RX_afe :: anaRxStatus :: indck_mode_en [09:09] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_indck_mode_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x200,9,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_indck_mode_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x200,9)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_MASK   0x0200
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_INDCK_MODE_EN_SHIFT  9

/* SGMII2_RX_afe :: anaRxStatus :: pci_mode_en [08:08] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_pci_mode_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x100,8,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_pci_mode_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x100,8)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_MASK     0x0100
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_PCI_MODE_EN_SHIFT    8

/* SGMII2_RX_afe :: anaRxStatus :: rx_polarity [07:07] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_rx_polarity(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x80,7,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_rx_polarity(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x80,7)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_MASK     0x0080
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RX_POLARITY_SHIFT    7

/* SGMII2_RX_afe :: anaRxStatus :: rxpol_flip [06:06] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_rxpol_flip(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x40,6,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_rxpol_flip(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x40,6)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_MASK      0x0040
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_ALIGN     0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_BITS      1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RXPOL_FLIP_SHIFT     6

/* SGMII2_RX_afe :: anaRxStatus :: comma_mask [05:05] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_comma_mask(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_comma_mask(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x20,5)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_MASK      0x0020
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_ALIGN     0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_BITS      1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_MASK_SHIFT     5

/* SGMII2_RX_afe :: anaRxStatus :: link_en_r [04:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_link_en_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_link_en_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x10,4)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_MASK       0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_BITS       1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_LINK_EN_R_SHIFT      4

/* SGMII2_RX_afe :: anaRxStatus :: comma_adj_en [03:03] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x8,3)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_MASK    0x0008
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_BITS    1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_SHIFT   3

/* SGMII2_RX_afe :: anaRxStatus :: comma_adj_en_ext [02:02] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en_ext(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_0_comma_adj_en_ext(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0,0x4,2)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_MASK 0x0004
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_COMMA_ADJ_EN_EXT_SHIFT 2

/* SGMII2_RX_afe :: anaRxStatus :: reserved1 [01:00] */
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_MASK       0x0003
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_BITS       2
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_0_RESERVED1_SHIFT      0


/* union - case rxTestSel_1 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_MASK       0xffe0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_BITS       11
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_RESERVED0_SHIFT      5

/* SGMII2_RX_afe :: anaRxStatus :: cdrAcqDone_r2 [04:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_1_cdrAcqDone_r2(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_1_cdrAcqDone_r2(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x10,4)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_MASK   0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_CDRACQDONE_R2_SHIFT  4

/* SGMII2_RX_afe :: anaRxStatus :: freq_sel_PC [03:03] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_PC(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_PC(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x8,3)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_MASK     0x0008
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_PC_SHIFT    3

/* SGMII2_RX_afe :: anaRxStatus :: freq_sel_SM [02:02] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_1_freq_sel_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x4,2)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_MASK     0x0004
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_FREQ_SEL_SM_SHIFT    2

/* SGMII2_RX_afe :: anaRxStatus :: integ_mode_SM [01:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_rxTestSel_1_integ_mode_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x3,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_rxTestSel_1_integ_mode_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1,0x3,0)
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_MASK   0x0003
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_BITS   2
#define SGMII2_RX_AFE_ANARXSTATUS_RXTESTSEL_1_INTEG_MODE_SM_SHIFT  0


/* union - case scale_Status [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: prop_scale [15:12] */
#define Wr_SGMII2_RX_afe_anaRxStatus_scale_Status_prop_scale(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf000,12,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_scale_Status_prop_scale(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf000,12)
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_MASK     0xf000
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_BITS     4
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_SHIFT    12

/* SGMII2_RX_afe :: anaRxStatus :: integ_scale [11:08] */
#define Wr_SGMII2_RX_afe_anaRxStatus_scale_Status_integ_scale(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf00,8,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_scale_Status_integ_scale(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf00,8)
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_MASK    0x0f00
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_BITS    4
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_SHIFT   8

/* SGMII2_RX_afe :: anaRxStatus :: prop_scale_acq [07:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_scale_Status_prop_scale_acq(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf0,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_scale_Status_prop_scale_acq(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf0,4)
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_MASK 0x00f0
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_BITS 4
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_PROP_SCALE_ACQ_SHIFT 4

/* SGMII2_RX_afe :: anaRxStatus :: integ_scale_acq [03:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_scale_Status_integ_scale_acq(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_scale_Status_integ_scale_acq(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS,0xf,0)
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_MASK 0x000f
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_BITS 4
#define SGMII2_RX_AFE_ANARXSTATUS_SCALE_STATUS_INTEG_SCALE_ACQ_SHIFT 0


/* union - case adc_CdrStatus1 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:07] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_MASK    0xff80
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_BITS    9
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RESERVED0_SHIFT   7

/* SGMII2_RX_afe :: anaRxStatus :: rxMuxCkSel [06:06] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_rxMuxCkSel(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x40,6,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_rxMuxCkSel(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x40,6)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_MASK   0x0040
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXMUXCKSEL_SHIFT  6

/* SGMII2_RX_afe :: anaRxStatus :: glpbk_combo [05:05] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_glpbk_combo(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_glpbk_combo(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x20,5)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_MASK  0x0020
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_BITS  1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_GLPBK_COMBO_SHIFT 5

/* SGMII2_RX_afe :: anaRxStatus :: clockSwitchSel [04:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_clockSwitchSel(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_clockSwitchSel(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x10,4)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_MASK 0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_CLOCKSWITCHSEL_SHIFT 4

/* SGMII2_RX_afe :: anaRxStatus :: rxck_tst [03:03] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_tst(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_tst(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x8,3)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_MASK     0x0008
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_TST_SHIFT    3

/* SGMII2_RX_afe :: anaRxStatus :: rxck_i [02:02] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_i(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_rxck_i(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x4,2)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_MASK       0x0004
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_BITS       1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_RXCK_I_SHIFT      2

/* SGMII2_RX_afe :: anaRxStatus :: refclk [01:01] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_refclk(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x2,1,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_refclk(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x2,1)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_MASK       0x0002
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_BITS       1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_REFCLK_SHIFT      1

/* SGMII2_RX_afe :: anaRxStatus :: pll_bypass [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_pll_bypass(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus1_pll_bypass(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_MASK   0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS1_PLL_BYPASS_SHIFT  0


/* union - case adc_CdrStatus2 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:06] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_MASK    0xffc0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_BITS    10
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED0_SHIFT   6

/* SGMII2_RX_afe :: anaRxStatus :: rxMuxCkSel [05:05] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus2_rxMuxCkSel(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus2_rxMuxCkSel(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x20,5)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_MASK   0x0020
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXMUXCKSEL_SHIFT  5

/* SGMII2_RX_afe :: anaRxStatus :: rxSeqStart [04:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqStart(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqStart(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x10,4)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_MASK   0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQSTART_SHIFT  4

/* SGMII2_RX_afe :: anaRxStatus :: reserved1 [03:01] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_MASK    0x000e
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_BITS    3
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RESERVED1_SHIFT   1

/* SGMII2_RX_afe :: anaRxStatus :: rxSeqDone [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqDone(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus2_rxSeqDone(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_MASK    0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_BITS    1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS2_RXSEQDONE_SHIFT   0


/* union - case adc_CdrStatus3 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:04] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_MASK    0xfff0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_BITS    12
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED0_SHIFT   4

/* SGMII2_RX_afe :: anaRxStatus :: rxSeqStart [03:03] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus3_rxSeqStart(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus3_rxSeqStart(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x8,3)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_MASK   0x0008
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RXSEQSTART_SHIFT  3

/* SGMII2_RX_afe :: anaRxStatus :: reserved1 [02:01] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_MASK    0x0006
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_BITS    2
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_RESERVED1_SHIFT   1

/* SGMII2_RX_afe :: anaRxStatus :: allow_increment_PC [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus3_allow_increment_PC(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus3_allow_increment_PC(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_MASK 0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS3_ALLOW_INCREMENT_PC_SHIFT 0


/* union - case adc_CdrStatus4 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:08] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_MASK    0xff00
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_BITS    8
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED0_SHIFT   8

/* SGMII2_RX_afe :: anaRxStatus :: rx_pwrdn [07:07] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus4_rx_pwrdn(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x80,7,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus4_rx_pwrdn(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x80,7)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_MASK     0x0080
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RX_PWRDN_SHIFT    7

/* SGMII2_RX_afe :: anaRxStatus :: freq_sel [06:06] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus4_freq_sel(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x40,6,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus4_freq_sel(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x40,6)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_MASK     0x0040
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_FREQ_SEL_SHIFT    6

/* SGMII2_RX_afe :: anaRxStatus :: pll_lock_rstb [05:05] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus4_pll_lock_rstb(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus4_pll_lock_rstb(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x20,5)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_MASK 0x0020
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PLL_LOCK_RSTB_SHIFT 5

/* SGMII2_RX_afe :: anaRxStatus :: pwrdn [04:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus4_pwrdn(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus4_pwrdn(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4,0x10,4)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_MASK        0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_ALIGN       0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_BITS        1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_PWRDN_SHIFT       4

/* SGMII2_RX_afe :: anaRxStatus :: reserved1 [03:00] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_MASK    0x000f
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_BITS    4
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS4_RESERVED1_SHIFT   0


/* union - case adc_CdrStatus5 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:00] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_MASK    0xffff
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_BITS    16
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS5_RESERVED0_SHIFT   0


/* union - case adc_CdrStatus6 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_MASK    0xffe0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_BITS    11
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESERVED0_SHIFT   5

/* SGMII2_RX_afe :: anaRxStatus :: rx_reset [04:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_rx_reset(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_rx_reset(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x10,4)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_MASK     0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_RESET_SHIFT    4

/* SGMII2_RX_afe :: anaRxStatus :: rx_pwrdn [03:03] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_rx_pwrdn(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_rx_pwrdn(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x8,3)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_MASK     0x0008
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RX_PWRDN_SHIFT    3

/* SGMII2_RX_afe :: anaRxStatus :: reset_anlg [02:02] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_reset_anlg(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_reset_anlg(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x4,2)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_MASK   0x0004
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_RESET_ANLG_SHIFT  2

/* SGMII2_RX_afe :: anaRxStatus :: pwrdn_rx [01:01] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_rx(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x2,1,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_rx(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x2,1)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_MASK     0x0002
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_RX_SHIFT    1

/* SGMII2_RX_afe :: anaRxStatus :: pwrdn_pll [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_pll(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus6_pwrdn_pll(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_MASK    0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_BITS    1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS6_PWRDN_PLL_SHIFT   0


/* union - case adc_CdrStatus7e [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_MASK   0xffe0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_BITS   11
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RESERVED0_SHIFT  5

/* SGMII2_RX_afe :: anaRxStatus :: rxck0_even [04:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck0_even(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck0_even(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x10,4)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_MASK  0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_BITS  1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK0_EVEN_SHIFT 4

/* SGMII2_RX_afe :: anaRxStatus :: rxck1_even [03:03] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck1_even(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_rxck1_even(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x8,3)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_MASK  0x0008
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_BITS  1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_RXCK1_EVEN_SHIFT 3

/* SGMII2_RX_afe :: anaRxStatus :: comdet_even [02:02] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_comdet_even(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_comdet_even(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x4,2)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_MASK 0x0004
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMDET_EVEN_SHIFT 2

/* SGMII2_RX_afe :: anaRxStatus :: en_cdet_even [01:01] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_en_cdet_even(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x2,1,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_en_cdet_even(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x2,1)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_MASK 0x0002
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_EN_CDET_EVEN_SHIFT 1

/* SGMII2_RX_afe :: anaRxStatus :: comma_adj_en_even [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_comma_adj_en_even(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7e_comma_adj_en_even(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_MASK 0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7E_COMMA_ADJ_EN_EVEN_SHIFT 0


/* union - case adc_CdrStatus7o [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_MASK   0xffe0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_BITS   11
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RESERVED0_SHIFT  5

/* SGMII2_RX_afe :: anaRxStatus :: rxck0_odd [04:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck0_odd(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck0_odd(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x10,4)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_MASK   0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK0_ODD_SHIFT  4

/* SGMII2_RX_afe :: anaRxStatus :: rxck1_odd [03:03] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck1_odd(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_rxck1_odd(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x8,3)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_MASK   0x0008
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_RXCK1_ODD_SHIFT  3

/* SGMII2_RX_afe :: anaRxStatus :: comdet_odd [02:02] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_comdet_odd(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_comdet_odd(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x4,2)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_MASK  0x0004
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_BITS  1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMDET_ODD_SHIFT 2

/* SGMII2_RX_afe :: anaRxStatus :: en_cdet_odd [01:01] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_en_cdet_odd(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x2,1,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_en_cdet_odd(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x2,1)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_MASK 0x0002
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_EN_CDET_ODD_SHIFT 1

/* SGMII2_RX_afe :: anaRxStatus :: comma_adj_en_odd [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_comma_adj_en_odd(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus7o_comma_adj_en_odd(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_MASK 0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS7O_COMMA_ADJ_EN_ODD_SHIFT 0


/* union - case adc_CdrStatus8 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:01] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_MASK    0xfffe
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_BITS    15
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_RESERVED0_SHIFT   1

/* SGMII2_RX_afe :: anaRxStatus :: sigdet [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus8_sigdet(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus8_sigdet(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_MASK       0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_BITS       1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS8_SIGDET_SHIFT      0


/* union - case adc_CdrStatus9 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:00] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_MASK    0xffff
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_BITS    16
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS9_RESERVED0_SHIFT   0


/* union - case adc_CdrStatus10 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:07] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_MASK   0xff80
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_BITS   9
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED0_SHIFT  7

/* SGMII2_RX_afe :: anaRxStatus :: prbs_en [06:06] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x40,6,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x40,6)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_MASK     0x0040
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_BITS     1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_EN_SHIFT    6

/* SGMII2_RX_afe :: anaRxStatus :: rstb_tst [05:05] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus10_rstb_tst(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus10_rstb_tst(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0x20,5)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_MASK    0x0020
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_ALIGN   0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_BITS    1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RSTB_TST_SHIFT   5

/* SGMII2_RX_afe :: anaRxStatus :: reserved1 [04:04] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_MASK   0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_RESERVED1_SHIFT  4

/* SGMII2_RX_afe :: anaRxStatus :: prbs_state [03:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_state(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0xf,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus10_prbs_state(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10,0xf,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_MASK  0x000f
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_BITS  4
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS10_PRBS_STATE_SHIFT 0


/* union - case adc_CdrStatus11 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:00] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_MASK   0xffff
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_BITS   16
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS11_RESERVED0_SHIFT  0


/* union - case adc_CdrStatus12_1 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:06] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_MASK 0xffc0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_BITS 10
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RESERVED0_SHIFT 6

/* SGMII2_RX_afe :: anaRxStatus :: enable4 [05:05] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_1_enable4(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_1_enable4(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x20,5)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_MASK   0x0020
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_ENABLE4_SHIFT  5

/* SGMII2_RX_afe :: anaRxStatus :: radr_test [04:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_1_radr_test(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x1f,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_1_radr_test(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1,0x1f,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_MASK 0x001f
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_BITS 5
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_1_RADR_TEST_SHIFT 0


/* union - case adc_CdrStatus12_2 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:05] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_MASK 0xffe0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_BITS 11
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_RESERVED0_SHIFT 5

/* SGMII2_RX_afe :: anaRxStatus :: wadr_test [04:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_2_wadr_test(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2,0x1f,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_2_wadr_test(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2,0x1f,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_MASK 0x001f
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_BITS 5
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_2_WADR_TEST_SHIFT 0


/* union - case adc_CdrStatus12_3 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:06] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_MASK 0xffc0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_BITS 10
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RESERVED0_SHIFT 6

/* SGMII2_RX_afe :: anaRxStatus :: rxck_66B_tmux [05:05] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_66B_tmux(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_66B_tmux(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x20,5)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_MASK 0x0020
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_66B_TMUX_SHIFT 5

/* SGMII2_RX_afe :: anaRxStatus :: rstb_66B [04:04] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_66B(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_66B(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x10,4)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_MASK  0x0010
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_BITS  1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_66B_SHIFT 4

/* SGMII2_RX_afe :: anaRxStatus :: prstb_66B_mux [03:03] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_66B_mux(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_66B_mux(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x8,3)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_MASK 0x0008
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_66B_MUX_SHIFT 3

/* SGMII2_RX_afe :: anaRxStatus :: rxck_i66_tmux [02:02] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_i66_tmux(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_rxck_i66_tmux(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x4,2)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_MASK 0x0004
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RXCK_I66_TMUX_SHIFT 2

/* SGMII2_RX_afe :: anaRxStatus :: rstb_i66 [01:01] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_i66(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x2,1,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_rstb_i66(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x2,1)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_MASK  0x0002
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_BITS  1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_RSTB_I66_SHIFT 1

/* SGMII2_RX_afe :: anaRxStatus :: prstb_i66_mux [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_i66_mux(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_3_prstb_i66_mux(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_MASK 0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_3_PRSTB_I66_MUX_SHIFT 0


/* union - case adc_CdrStatus12_4 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: reserved0 [15:04] */
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_MASK 0xfff0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_BITS 12
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RESERVED0_SHIFT 4

/* SGMII2_RX_afe :: anaRxStatus :: rfifo_error_r [03:02] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_error_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0xc,2,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_error_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0xc,2)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_MASK 0x000c
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_BITS 2
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_ERROR_R_SHIFT 2

/* SGMII2_RX_afe :: anaRxStatus :: rfifo_unflow [01:01] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_unflow(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x2,1,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_unflow(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x2,1)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_MASK 0x0002
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_UNFLOW_SHIFT 1

/* SGMII2_RX_afe :: anaRxStatus :: rfifo_ovflow [00:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_ovflow(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_adc_CdrStatus12_4_rfifo_ovflow(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4,0x1,0)
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_MASK 0x0001
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_ALIGN 0
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_BITS 1
#define SGMII2_RX_AFE_ANARXSTATUS_ADC_CDRSTATUS12_4_RFIFO_OVFLOW_SHIFT 0


/* union - case integ_Status [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: integ_status [15:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_integ_Status_integ_status(x) WriteReg16(SGMII2_RX_AFE_ANARXSTATUS_INTEG_STATUS,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_integ_Status_integ_status(x) ReadReg16(SGMII2_RX_AFE_ANARXSTATUS_INTEG_STATUS)
#define SGMII2_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_MASK   0xffff
#define SGMII2_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_BITS   16
#define SGMII2_RX_AFE_ANARXSTATUS_INTEG_STATUS_INTEG_STATUS_SHIFT  0


/* union - case vco_Status [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: vco_status [15:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_vco_Status_vco_status(x) WriteReg16(SGMII2_RX_AFE_ANARXSTATUS_VCO_STATUS,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_vco_Status_vco_status(x) ReadReg16(SGMII2_RX_AFE_ANARXSTATUS_VCO_STATUS)
#define SGMII2_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_MASK       0xffff
#define SGMII2_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_BITS       16
#define SGMII2_RX_AFE_ANARXSTATUS_VCO_STATUS_VCO_STATUS_SHIFT      0


/* union - case prbs_Status [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: prbs_lock [15:15] */
#define Wr_SGMII2_RX_afe_anaRxStatus_prbs_Status_prbs_lock(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x8000,15,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_prbs_Status_prbs_lock(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x8000,15)
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_MASK       0x8000
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_BITS       1
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_LOCK_SHIFT      15

/* SGMII2_RX_afe :: anaRxStatus :: prbs_stky [14:14] */
#define Wr_SGMII2_RX_afe_anaRxStatus_prbs_Status_prbs_stky(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x4000,14,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_prbs_Status_prbs_stky(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x4000,14)
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_MASK       0x4000
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_BITS       1
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_STKY_SHIFT      14

/* SGMII2_RX_afe :: anaRxStatus :: prbs_errors [13:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_prbs_Status_prbs_errors(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x3fff,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_prbs_Status_prbs_errors(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS,0x3fff,0)
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_MASK     0x3fff
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_ALIGN    0
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_BITS     14
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_PRBS_ERRORS_SHIFT    0


/* union - case prbs_Status_1 [15:00] */
/* SGMII2_RX_afe :: anaRxStatus :: sync_status [15:15] */
#define Wr_SGMII2_RX_afe_anaRxStatus_prbs_Status_1_sync_status(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x8000,15,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_prbs_Status_1_sync_status(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x8000,15)
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_MASK   0x8000
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_ALIGN  0
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_BITS   1
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_SYNC_STATUS_SHIFT  15

/* SGMII2_RX_afe :: anaRxStatus :: E_count [14:00] */
#define Wr_SGMII2_RX_afe_anaRxStatus_prbs_Status_1_E_count(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x7fff,0,x)
#define Rd_SGMII2_RX_afe_anaRxStatus_prbs_Status_1_E_count(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1,0x7fff,0)
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_MASK       0x7fff
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_ALIGN      0
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_BITS       15
#define SGMII2_RX_AFE_ANARXSTATUS_PRBS_STATUS_1_E_COUNT_SHIFT      0



/****************************************************************************
 * SGMII2_RX_afe :: anaRxControl
 ***************************************************************************/
/* SGMII2_RX_afe :: anaRxControl :: rxSeqRestart_SM [15:15] */
#define Wr_SGMII2_RX_afe_anaRxControl_rxSeqRestart_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x8000,15,x)
#define Rd_SGMII2_RX_afe_anaRxControl_rxSeqRestart_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x8000,15)
#define SGMII2_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_MASK            0x8000
#define SGMII2_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_ALIGN           0
#define SGMII2_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_BITS            1
#define SGMII2_RX_AFE_ANARXCONTROL_RXSEQRESTART_SM_SHIFT           15

/* SGMII2_RX_afe :: anaRxControl :: fast_acq_en_r [14:14] */
#define Wr_SGMII2_RX_afe_anaRxControl_fast_acq_en_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x4000,14,x)
#define Rd_SGMII2_RX_afe_anaRxControl_fast_acq_en_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x4000,14)
#define SGMII2_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_MASK              0x4000
#define SGMII2_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_ALIGN             0
#define SGMII2_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_BITS              1
#define SGMII2_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_R_SHIFT             14

/* SGMII2_RX_afe :: anaRxControl :: fast_acq_en_force_r [13:13] */
#define Wr_SGMII2_RX_afe_anaRxControl_fast_acq_en_force_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x2000,13,x)
#define Rd_SGMII2_RX_afe_anaRxControl_fast_acq_en_force_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x2000,13)
#define SGMII2_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_MASK        0x2000
#define SGMII2_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_ALIGN       0
#define SGMII2_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_BITS        1
#define SGMII2_RX_AFE_ANARXCONTROL_FAST_ACQ_EN_FORCE_R_SHIFT       13

/* SGMII2_RX_afe :: anaRxControl :: sigDetected_en_SM [12:12] */
#define Wr_SGMII2_RX_afe_anaRxControl_sigDetected_en_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x1000,12,x)
#define Rd_SGMII2_RX_afe_anaRxControl_sigDetected_en_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x1000,12)
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_MASK          0x1000
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_ALIGN         0
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_BITS          1
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETECTED_EN_SM_SHIFT         12

/* SGMII2_RX_afe :: anaRxControl :: sigdetRestart_en_SM [11:11] */
#define Wr_SGMII2_RX_afe_anaRxControl_sigdetRestart_en_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x800,11,x)
#define Rd_SGMII2_RX_afe_anaRxControl_sigdetRestart_en_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x800,11)
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_MASK        0x0800
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_ALIGN       0
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_BITS        1
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETRESTART_EN_SM_SHIFT       11

/* SGMII2_RX_afe :: anaRxControl :: sigdetMonitor_en_SM [10:10] */
#define Wr_SGMII2_RX_afe_anaRxControl_sigdetMonitor_en_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x400,10,x)
#define Rd_SGMII2_RX_afe_anaRxControl_sigdetMonitor_en_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x400,10)
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_MASK        0x0400
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_ALIGN       0
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_BITS        1
#define SGMII2_RX_AFE_ANARXCONTROL_SIGDETMONITOR_EN_SM_SHIFT       10

/* SGMII2_RX_afe :: anaRxControl :: override_sigdet_en [09:09] */
#define Wr_SGMII2_RX_afe_anaRxControl_override_sigdet_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x200,9,x)
#define Rd_SGMII2_RX_afe_anaRxControl_override_sigdet_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x200,9)
#define SGMII2_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_MASK         0x0200
#define SGMII2_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_ALIGN        0
#define SGMII2_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_BITS         1
#define SGMII2_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_EN_SHIFT        9

/* SGMII2_RX_afe :: anaRxControl :: override_sigdet_val [08:08] */
#define Wr_SGMII2_RX_afe_anaRxControl_override_sigdet_val(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x100,8,x)
#define Rd_SGMII2_RX_afe_anaRxControl_override_sigdet_val(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x100,8)
#define SGMII2_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_MASK        0x0100
#define SGMII2_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_ALIGN       0
#define SGMII2_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_BITS        1
#define SGMII2_RX_AFE_ANARXCONTROL_OVERRIDE_SIGDET_VAL_SHIFT       8

/* SGMII2_RX_afe :: anaRxControl :: reserved0 [07:07] */
#define SGMII2_RX_AFE_ANARXCONTROL_RESERVED0_MASK                  0x0080
#define SGMII2_RX_AFE_ANARXCONTROL_RESERVED0_ALIGN                 0
#define SGMII2_RX_AFE_ANARXCONTROL_RESERVED0_BITS                  1
#define SGMII2_RX_AFE_ANARXCONTROL_RESERVED0_SHIFT                 7

/* SGMII2_RX_afe :: anaRxControl :: phfreq_rst_dis_fst_SM [06:06] */
#define Wr_SGMII2_RX_afe_anaRxControl_phfreq_rst_dis_fst_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x40,6,x)
#define Rd_SGMII2_RX_afe_anaRxControl_phfreq_rst_dis_fst_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x40,6)
#define SGMII2_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_MASK      0x0040
#define SGMII2_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_ALIGN     0
#define SGMII2_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_BITS      1
#define SGMII2_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_FST_SM_SHIFT     6

/* SGMII2_RX_afe :: anaRxControl :: phfreq_rst_dis_nrml_SM [05:05] */
#define Wr_SGMII2_RX_afe_anaRxControl_phfreq_rst_dis_nrml_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxControl_phfreq_rst_dis_nrml_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x20,5)
#define SGMII2_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_MASK     0x0020
#define SGMII2_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_ALIGN    0
#define SGMII2_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_BITS     1
#define SGMII2_RX_AFE_ANARXCONTROL_PHFREQ_RST_DIS_NRML_SM_SHIFT    5

/* SGMII2_RX_afe :: anaRxControl :: forceRxSeqDone_SM [04:04] */
#define Wr_SGMII2_RX_afe_anaRxControl_forceRxSeqDone_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxControl_forceRxSeqDone_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x10,4)
#define SGMII2_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_MASK          0x0010
#define SGMII2_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_ALIGN         0
#define SGMII2_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_BITS          1
#define SGMII2_RX_AFE_ANARXCONTROL_FORCERXSEQDONE_SM_SHIFT         4

/* SGMII2_RX_afe :: anaRxControl :: flip_eyemon_polarity [03:03] */
#define Wr_SGMII2_RX_afe_anaRxControl_flip_eyemon_polarity(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxControl_flip_eyemon_polarity(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x8,3)
#define SGMII2_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_MASK       0x0008
#define SGMII2_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_ALIGN      0
#define SGMII2_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_BITS       1
#define SGMII2_RX_AFE_ANARXCONTROL_FLIP_EYEMON_POLARITY_SHIFT      3

/* SGMII2_RX_afe :: anaRxControl :: status_sel [02:00] */
#define Wr_SGMII2_RX_afe_anaRxControl_status_sel(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x7,0,x)
#define Rd_SGMII2_RX_afe_anaRxControl_status_sel(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL,0x7,0)
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_MASK                 0x0007
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_ALIGN                0
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_BITS                 3
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_SHIFT                0
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_sigdetStatus         0
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_syncStatus           1
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_rxTestSel            2
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_scaleStatus          3
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_adcCdrStatus         4
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_integStatus          5
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_vcoStatus            6
#define SGMII2_RX_AFE_ANARXCONTROL_STATUS_SEL_prbsStatus           7


/****************************************************************************
 * SGMII2_RX_afe :: ctrl0
 ***************************************************************************/
/* SGMII2_RX_afe :: ctrl0 :: slicer_pd [15:15] */
#define Wr_SGMII2_RX_afe_ctrl0_slicer_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL0,0x8000,15,x)
#define Rd_SGMII2_RX_afe_ctrl0_slicer_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL0,0x8000,15)
#define SGMII2_RX_AFE_CTRL0_SLICER_PD_MASK                         0x8000
#define SGMII2_RX_AFE_CTRL0_SLICER_PD_ALIGN                        0
#define SGMII2_RX_AFE_CTRL0_SLICER_PD_BITS                         1
#define SGMII2_RX_AFE_CTRL0_SLICER_PD_SHIFT                        15

/* SGMII2_RX_afe :: ctrl0 :: reserved_14_12 [14:12] */
#define SGMII2_RX_AFE_CTRL0_RESERVED_14_12_MASK                    0x7000
#define SGMII2_RX_AFE_CTRL0_RESERVED_14_12_ALIGN                   0
#define SGMII2_RX_AFE_CTRL0_RESERVED_14_12_BITS                    3
#define SGMII2_RX_AFE_CTRL0_RESERVED_14_12_SHIFT                   12

/* SGMII2_RX_afe :: ctrl0 :: RX_pon [11:08] */
#define Wr_SGMII2_RX_afe_ctrl0_RX_pon(x) WriteRegBits16(SGMII2_RX_AFE_CTRL0,0xf00,8,x)
#define Rd_SGMII2_RX_afe_ctrl0_RX_pon(x) ReadRegBits16(SGMII2_RX_AFE_CTRL0,0xf00,8)
#define SGMII2_RX_AFE_CTRL0_RX_PON_MASK                            0x0f00
#define SGMII2_RX_AFE_CTRL0_RX_PON_ALIGN                           0
#define SGMII2_RX_AFE_CTRL0_RX_PON_BITS                            4
#define SGMII2_RX_AFE_CTRL0_RX_PON_SHIFT                           8

/* SGMII2_RX_afe :: ctrl0 :: Filter_band [07:06] */
#define Wr_SGMII2_RX_afe_ctrl0_Filter_band(x) WriteRegBits16(SGMII2_RX_AFE_CTRL0,0xc0,6,x)
#define Rd_SGMII2_RX_afe_ctrl0_Filter_band(x) ReadRegBits16(SGMII2_RX_AFE_CTRL0,0xc0,6)
#define SGMII2_RX_AFE_CTRL0_FILTER_BAND_MASK                       0x00c0
#define SGMII2_RX_AFE_CTRL0_FILTER_BAND_ALIGN                      0
#define SGMII2_RX_AFE_CTRL0_FILTER_BAND_BITS                       2
#define SGMII2_RX_AFE_CTRL0_FILTER_BAND_SHIFT                      6

/* SGMII2_RX_afe :: ctrl0 :: reserved_5_3 [05:03] */
#define SGMII2_RX_AFE_CTRL0_RESERVED_5_3_MASK                      0x0038
#define SGMII2_RX_AFE_CTRL0_RESERVED_5_3_ALIGN                     0
#define SGMII2_RX_AFE_CTRL0_RESERVED_5_3_BITS                      3
#define SGMII2_RX_AFE_CTRL0_RESERVED_5_3_SHIFT                     3

/* SGMII2_RX_afe :: ctrl0 :: pd_lmtng [02:02] */
#define Wr_SGMII2_RX_afe_ctrl0_pd_lmtng(x) WriteRegBits16(SGMII2_RX_AFE_CTRL0,0x4,2,x)
#define Rd_SGMII2_RX_afe_ctrl0_pd_lmtng(x) ReadRegBits16(SGMII2_RX_AFE_CTRL0,0x4,2)
#define SGMII2_RX_AFE_CTRL0_PD_LMTNG_MASK                          0x0004
#define SGMII2_RX_AFE_CTRL0_PD_LMTNG_ALIGN                         0
#define SGMII2_RX_AFE_CTRL0_PD_LMTNG_BITS                          1
#define SGMII2_RX_AFE_CTRL0_PD_LMTNG_SHIFT                         2

/* SGMII2_RX_afe :: ctrl0 :: pd_eqz [01:01] */
#define Wr_SGMII2_RX_afe_ctrl0_pd_eqz(x) WriteRegBits16(SGMII2_RX_AFE_CTRL0,0x2,1,x)
#define Rd_SGMII2_RX_afe_ctrl0_pd_eqz(x) ReadRegBits16(SGMII2_RX_AFE_CTRL0,0x2,1)
#define SGMII2_RX_AFE_CTRL0_PD_EQZ_MASK                            0x0002
#define SGMII2_RX_AFE_CTRL0_PD_EQZ_ALIGN                           0
#define SGMII2_RX_AFE_CTRL0_PD_EQZ_BITS                            1
#define SGMII2_RX_AFE_CTRL0_PD_EQZ_SHIFT                           1

/* SGMII2_RX_afe :: ctrl0 :: reserved_0 [00:00] */
#define SGMII2_RX_AFE_CTRL0_RESERVED_0_MASK                        0x0001
#define SGMII2_RX_AFE_CTRL0_RESERVED_0_ALIGN                       0
#define SGMII2_RX_AFE_CTRL0_RESERVED_0_BITS                        1
#define SGMII2_RX_AFE_CTRL0_RESERVED_0_SHIFT                       0


/****************************************************************************
 * SGMII2_RX_afe :: ctrl1
 ***************************************************************************/
/* SGMII2_RX_afe :: ctrl1 :: demux_eyem_pd [15:15] */
#define Wr_SGMII2_RX_afe_ctrl1_demux_eyem_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL1,0x8000,15,x)
#define Rd_SGMII2_RX_afe_ctrl1_demux_eyem_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL1,0x8000,15)
#define SGMII2_RX_AFE_CTRL1_DEMUX_EYEM_PD_MASK                     0x8000
#define SGMII2_RX_AFE_CTRL1_DEMUX_EYEM_PD_ALIGN                    0
#define SGMII2_RX_AFE_CTRL1_DEMUX_EYEM_PD_BITS                     1
#define SGMII2_RX_AFE_CTRL1_DEMUX_EYEM_PD_SHIFT                    15

/* SGMII2_RX_afe :: ctrl1 :: demux_pd [14:14] */
#define Wr_SGMII2_RX_afe_ctrl1_demux_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL1,0x4000,14,x)
#define Rd_SGMII2_RX_afe_ctrl1_demux_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL1,0x4000,14)
#define SGMII2_RX_AFE_CTRL1_DEMUX_PD_MASK                          0x4000
#define SGMII2_RX_AFE_CTRL1_DEMUX_PD_ALIGN                         0
#define SGMII2_RX_AFE_CTRL1_DEMUX_PD_BITS                          1
#define SGMII2_RX_AFE_CTRL1_DEMUX_PD_SHIFT                         14

/* SGMII2_RX_afe :: ctrl1 :: demux_peak_pd [13:13] */
#define Wr_SGMII2_RX_afe_ctrl1_demux_peak_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL1,0x2000,13,x)
#define Rd_SGMII2_RX_afe_ctrl1_demux_peak_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL1,0x2000,13)
#define SGMII2_RX_AFE_CTRL1_DEMUX_PEAK_PD_MASK                     0x2000
#define SGMII2_RX_AFE_CTRL1_DEMUX_PEAK_PD_ALIGN                    0
#define SGMII2_RX_AFE_CTRL1_DEMUX_PEAK_PD_BITS                     1
#define SGMII2_RX_AFE_CTRL1_DEMUX_PEAK_PD_SHIFT                    13

/* SGMII2_RX_afe :: ctrl1 :: demux_zero_pd [12:12] */
#define Wr_SGMII2_RX_afe_ctrl1_demux_zero_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL1,0x1000,12,x)
#define Rd_SGMII2_RX_afe_ctrl1_demux_zero_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL1,0x1000,12)
#define SGMII2_RX_AFE_CTRL1_DEMUX_ZERO_PD_MASK                     0x1000
#define SGMII2_RX_AFE_CTRL1_DEMUX_ZERO_PD_ALIGN                    0
#define SGMII2_RX_AFE_CTRL1_DEMUX_ZERO_PD_BITS                     1
#define SGMII2_RX_AFE_CTRL1_DEMUX_ZERO_PD_SHIFT                    12

/* SGMII2_RX_afe :: ctrl1 :: div_4_demux_enable [11:11] */
#define Wr_SGMII2_RX_afe_ctrl1_div_4_demux_enable(x) WriteRegBits16(SGMII2_RX_AFE_CTRL1,0x800,11,x)
#define Rd_SGMII2_RX_afe_ctrl1_div_4_demux_enable(x) ReadRegBits16(SGMII2_RX_AFE_CTRL1,0x800,11)
#define SGMII2_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_MASK                0x0800
#define SGMII2_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_ALIGN               0
#define SGMII2_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_BITS                1
#define SGMII2_RX_AFE_CTRL1_DIV_4_DEMUX_ENABLE_SHIFT               11

/* SGMII2_RX_afe :: ctrl1 :: reserved_26_17 [10:01] */
#define SGMII2_RX_AFE_CTRL1_RESERVED_26_17_MASK                    0x07fe
#define SGMII2_RX_AFE_CTRL1_RESERVED_26_17_ALIGN                   0
#define SGMII2_RX_AFE_CTRL1_RESERVED_26_17_BITS                    10
#define SGMII2_RX_AFE_CTRL1_RESERVED_26_17_SHIFT                   1

/* SGMII2_RX_afe :: ctrl1 :: eyem_pd [00:00] */
#define Wr_SGMII2_RX_afe_ctrl1_eyem_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL1,0x1,0,x)
#define Rd_SGMII2_RX_afe_ctrl1_eyem_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL1,0x1,0)
#define SGMII2_RX_AFE_CTRL1_EYEM_PD_MASK                           0x0001
#define SGMII2_RX_AFE_CTRL1_EYEM_PD_ALIGN                          0
#define SGMII2_RX_AFE_CTRL1_EYEM_PD_BITS                           1
#define SGMII2_RX_AFE_CTRL1_EYEM_PD_SHIFT                          0


/****************************************************************************
 * SGMII2_RX_afe :: anaRxSigdet
 ***************************************************************************/
/* SGMII2_RX_afe :: anaRxSigdet :: reserved0 [15:08] */
#define SGMII2_RX_AFE_ANARXSIGDET_RESERVED0_MASK                   0xff00
#define SGMII2_RX_AFE_ANARXSIGDET_RESERVED0_ALIGN                  0
#define SGMII2_RX_AFE_ANARXSIGDET_RESERVED0_BITS                   8
#define SGMII2_RX_AFE_ANARXSIGDET_RESERVED0_SHIFT                  8

/* SGMII2_RX_afe :: anaRxSigdet :: cx4_sigdet_cnt_ld_SM [07:07] */
#define Wr_SGMII2_RX_afe_anaRxSigdet_cx4_sigdet_cnt_ld_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x80,7,x)
#define Rd_SGMII2_RX_afe_anaRxSigdet_cx4_sigdet_cnt_ld_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x80,7)
#define SGMII2_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_MASK        0x0080
#define SGMII2_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_ALIGN       0
#define SGMII2_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_BITS        1
#define SGMII2_RX_AFE_ANARXSIGDET_CX4_SIGDET_CNT_LD_SM_SHIFT       7

/* SGMII2_RX_afe :: anaRxSigdet :: ext_sigdet_en_SM [06:06] */
#define Wr_SGMII2_RX_afe_anaRxSigdet_ext_sigdet_en_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x40,6,x)
#define Rd_SGMII2_RX_afe_anaRxSigdet_ext_sigdet_en_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x40,6)
#define SGMII2_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_MASK            0x0040
#define SGMII2_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_ALIGN           0
#define SGMII2_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_BITS            1
#define SGMII2_RX_AFE_ANARXSIGDET_EXT_SIGDET_EN_SM_SHIFT           6

/* SGMII2_RX_afe :: anaRxSigdet :: cx4_sigdet_en_SM [05:05] */
#define Wr_SGMII2_RX_afe_anaRxSigdet_cx4_sigdet_en_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxSigdet_cx4_sigdet_en_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x20,5)
#define SGMII2_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_MASK            0x0020
#define SGMII2_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_ALIGN           0
#define SGMII2_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_BITS            1
#define SGMII2_RX_AFE_ANARXSIGDET_CX4_SIGDET_EN_SM_SHIFT           5

/* SGMII2_RX_afe :: anaRxSigdet :: rx_sigdet_r [04:04] */
#define Wr_SGMII2_RX_afe_anaRxSigdet_rx_sigdet_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxSigdet_rx_sigdet_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x10,4)
#define SGMII2_RX_AFE_ANARXSIGDET_RX_SIGDET_R_MASK                 0x0010
#define SGMII2_RX_AFE_ANARXSIGDET_RX_SIGDET_R_ALIGN                0
#define SGMII2_RX_AFE_ANARXSIGDET_RX_SIGDET_R_BITS                 1
#define SGMII2_RX_AFE_ANARXSIGDET_RX_SIGDET_R_SHIFT                4

/* SGMII2_RX_afe :: anaRxSigdet :: rx_sigdet_force_r [03:03] */
#define Wr_SGMII2_RX_afe_anaRxSigdet_rx_sigdet_force_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxSigdet_rx_sigdet_force_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x8,3)
#define SGMII2_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_MASK           0x0008
#define SGMII2_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_ALIGN          0
#define SGMII2_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_BITS           1
#define SGMII2_RX_AFE_ANARXSIGDET_RX_SIGDET_FORCE_R_SHIFT          3

/* SGMII2_RX_afe :: anaRxSigdet :: invert_rx_sigdet [02:02] */
#define Wr_SGMII2_RX_afe_anaRxSigdet_invert_rx_sigdet(x) WriteRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxSigdet_invert_rx_sigdet(x) ReadRegBits16(SGMII2_RX_AFE_ANARXSIGDET,0x4,2)
#define SGMII2_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_MASK            0x0004
#define SGMII2_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_ALIGN           0
#define SGMII2_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_BITS            1
#define SGMII2_RX_AFE_ANARXSIGDET_INVERT_RX_SIGDET_SHIFT           2

/* SGMII2_RX_afe :: anaRxSigdet :: reserved1 [01:00] */
#define SGMII2_RX_AFE_ANARXSIGDET_RESERVED1_MASK                   0x0003
#define SGMII2_RX_AFE_ANARXSIGDET_RESERVED1_ALIGN                  0
#define SGMII2_RX_AFE_ANARXSIGDET_RESERVED1_BITS                   2
#define SGMII2_RX_AFE_ANARXSIGDET_RESERVED1_SHIFT                  0


/****************************************************************************
 * SGMII2_RX_afe :: ctrl2
 ***************************************************************************/
/* SGMII2_RX_afe :: ctrl2 :: reserved_47_39 [15:07] */
#define SGMII2_RX_AFE_CTRL2_RESERVED_47_39_MASK                    0xff80
#define SGMII2_RX_AFE_CTRL2_RESERVED_47_39_ALIGN                   0
#define SGMII2_RX_AFE_CTRL2_RESERVED_47_39_BITS                    9
#define SGMII2_RX_AFE_CTRL2_RESERVED_47_39_SHIFT                   7

/* SGMII2_RX_afe :: ctrl2 :: inputerm_lowZvdd_en [06:06] */
#define Wr_SGMII2_RX_afe_ctrl2_inputerm_lowZvdd_en(x) WriteRegBits16(SGMII2_RX_AFE_CTRL2,0x40,6,x)
#define Rd_SGMII2_RX_afe_ctrl2_inputerm_lowZvdd_en(x) ReadRegBits16(SGMII2_RX_AFE_CTRL2,0x40,6)
#define SGMII2_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_MASK               0x0040
#define SGMII2_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_ALIGN              0
#define SGMII2_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_BITS               1
#define SGMII2_RX_AFE_CTRL2_INPUTERM_LOWZVDD_EN_SHIFT              6

/* SGMII2_RX_afe :: ctrl2 :: inputerm_lowZgnd_en [05:05] */
#define Wr_SGMII2_RX_afe_ctrl2_inputerm_lowZgnd_en(x) WriteRegBits16(SGMII2_RX_AFE_CTRL2,0x20,5,x)
#define Rd_SGMII2_RX_afe_ctrl2_inputerm_lowZgnd_en(x) ReadRegBits16(SGMII2_RX_AFE_CTRL2,0x20,5)
#define SGMII2_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_MASK               0x0020
#define SGMII2_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_ALIGN              0
#define SGMII2_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_BITS               1
#define SGMII2_RX_AFE_CTRL2_INPUTERM_LOWZGND_EN_SHIFT              5

/* SGMII2_RX_afe :: ctrl2 :: inputerm_cmult_en [04:04] */
#define Wr_SGMII2_RX_afe_ctrl2_inputerm_cmult_en(x) WriteRegBits16(SGMII2_RX_AFE_CTRL2,0x10,4,x)
#define Rd_SGMII2_RX_afe_ctrl2_inputerm_cmult_en(x) ReadRegBits16(SGMII2_RX_AFE_CTRL2,0x10,4)
#define SGMII2_RX_AFE_CTRL2_INPUTERM_CMULT_EN_MASK                 0x0010
#define SGMII2_RX_AFE_CTRL2_INPUTERM_CMULT_EN_ALIGN                0
#define SGMII2_RX_AFE_CTRL2_INPUTERM_CMULT_EN_BITS                 1
#define SGMII2_RX_AFE_CTRL2_INPUTERM_CMULT_EN_SHIFT                4

/* SGMII2_RX_afe :: ctrl2 :: inputerm_cm_en [03:03] */
#define Wr_SGMII2_RX_afe_ctrl2_inputerm_cm_en(x) WriteRegBits16(SGMII2_RX_AFE_CTRL2,0x8,3,x)
#define Rd_SGMII2_RX_afe_ctrl2_inputerm_cm_en(x) ReadRegBits16(SGMII2_RX_AFE_CTRL2,0x8,3)
#define SGMII2_RX_AFE_CTRL2_INPUTERM_CM_EN_MASK                    0x0008
#define SGMII2_RX_AFE_CTRL2_INPUTERM_CM_EN_ALIGN                   0
#define SGMII2_RX_AFE_CTRL2_INPUTERM_CM_EN_BITS                    1
#define SGMII2_RX_AFE_CTRL2_INPUTERM_CM_EN_SHIFT                   3

/* SGMII2_RX_afe :: ctrl2 :: div10_pd [02:02] */
#define Wr_SGMII2_RX_afe_ctrl2_div10_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL2,0x4,2,x)
#define Rd_SGMII2_RX_afe_ctrl2_div10_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL2,0x4,2)
#define SGMII2_RX_AFE_CTRL2_DIV10_PD_MASK                          0x0004
#define SGMII2_RX_AFE_CTRL2_DIV10_PD_ALIGN                         0
#define SGMII2_RX_AFE_CTRL2_DIV10_PD_BITS                          1
#define SGMII2_RX_AFE_CTRL2_DIV10_PD_SHIFT                         2

/* SGMII2_RX_afe :: ctrl2 :: div4_pd [01:01] */
#define Wr_SGMII2_RX_afe_ctrl2_div4_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL2,0x2,1,x)
#define Rd_SGMII2_RX_afe_ctrl2_div4_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL2,0x2,1)
#define SGMII2_RX_AFE_CTRL2_DIV4_PD_MASK                           0x0002
#define SGMII2_RX_AFE_CTRL2_DIV4_PD_ALIGN                          0
#define SGMII2_RX_AFE_CTRL2_DIV4_PD_BITS                           1
#define SGMII2_RX_AFE_CTRL2_DIV4_PD_SHIFT                          1

/* SGMII2_RX_afe :: ctrl2 :: reserved_32 [00:00] */
#define SGMII2_RX_AFE_CTRL2_RESERVED_32_MASK                       0x0001
#define SGMII2_RX_AFE_CTRL2_RESERVED_32_ALIGN                      0
#define SGMII2_RX_AFE_CTRL2_RESERVED_32_BITS                       1
#define SGMII2_RX_AFE_CTRL2_RESERVED_32_SHIFT                      0


/****************************************************************************
 * SGMII2_RX_afe :: ctrl3
 ***************************************************************************/
/* SGMII2_RX_afe :: ctrl3 :: reserved_63_58 [15:10] */
#define SGMII2_RX_AFE_CTRL3_RESERVED_63_58_MASK                    0xfc00
#define SGMII2_RX_AFE_CTRL3_RESERVED_63_58_ALIGN                   0
#define SGMII2_RX_AFE_CTRL3_RESERVED_63_58_BITS                    6
#define SGMII2_RX_AFE_CTRL3_RESERVED_63_58_SHIFT                   10

/* SGMII2_RX_afe :: ctrl3 :: pd_bias [09:09] */
#define Wr_SGMII2_RX_afe_ctrl3_pd_bias(x) WriteRegBits16(SGMII2_RX_AFE_CTRL3,0x200,9,x)
#define Rd_SGMII2_RX_afe_ctrl3_pd_bias(x) ReadRegBits16(SGMII2_RX_AFE_CTRL3,0x200,9)
#define SGMII2_RX_AFE_CTRL3_PD_BIAS_MASK                           0x0200
#define SGMII2_RX_AFE_CTRL3_PD_BIAS_ALIGN                          0
#define SGMII2_RX_AFE_CTRL3_PD_BIAS_BITS                           1
#define SGMII2_RX_AFE_CTRL3_PD_BIAS_SHIFT                          9

/* SGMII2_RX_afe :: ctrl3 :: Duty_Cycle [08:06] */
#define Wr_SGMII2_RX_afe_ctrl3_Duty_Cycle(x) WriteRegBits16(SGMII2_RX_AFE_CTRL3,0x1c0,6,x)
#define Rd_SGMII2_RX_afe_ctrl3_Duty_Cycle(x) ReadRegBits16(SGMII2_RX_AFE_CTRL3,0x1c0,6)
#define SGMII2_RX_AFE_CTRL3_DUTY_CYCLE_MASK                        0x01c0
#define SGMII2_RX_AFE_CTRL3_DUTY_CYCLE_ALIGN                       0
#define SGMII2_RX_AFE_CTRL3_DUTY_CYCLE_BITS                        3
#define SGMII2_RX_AFE_CTRL3_DUTY_CYCLE_SHIFT                       6

/* SGMII2_RX_afe :: ctrl3 :: Dcc_en [05:05] */
#define Wr_SGMII2_RX_afe_ctrl3_Dcc_en(x) WriteRegBits16(SGMII2_RX_AFE_CTRL3,0x20,5,x)
#define Rd_SGMII2_RX_afe_ctrl3_Dcc_en(x) ReadRegBits16(SGMII2_RX_AFE_CTRL3,0x20,5)
#define SGMII2_RX_AFE_CTRL3_DCC_EN_MASK                            0x0020
#define SGMII2_RX_AFE_CTRL3_DCC_EN_ALIGN                           0
#define SGMII2_RX_AFE_CTRL3_DCC_EN_BITS                            1
#define SGMII2_RX_AFE_CTRL3_DCC_EN_SHIFT                           5

/* SGMII2_RX_afe :: ctrl3 :: reserved_52_48 [04:00] */
#define SGMII2_RX_AFE_CTRL3_RESERVED_52_48_MASK                    0x001f
#define SGMII2_RX_AFE_CTRL3_RESERVED_52_48_ALIGN                   0
#define SGMII2_RX_AFE_CTRL3_RESERVED_52_48_BITS                    5
#define SGMII2_RX_AFE_CTRL3_RESERVED_52_48_SHIFT                   0


/****************************************************************************
 * SGMII2_RX_afe :: ctrl4
 ***************************************************************************/
/* SGMII2_RX_afe :: ctrl4 :: en_testmux [15:15] */
#define Wr_SGMII2_RX_afe_ctrl4_en_testmux(x) WriteRegBits16(SGMII2_RX_AFE_CTRL4,0x8000,15,x)
#define Rd_SGMII2_RX_afe_ctrl4_en_testmux(x) ReadRegBits16(SGMII2_RX_AFE_CTRL4,0x8000,15)
#define SGMII2_RX_AFE_CTRL4_EN_TESTMUX_MASK                        0x8000
#define SGMII2_RX_AFE_CTRL4_EN_TESTMUX_ALIGN                       0
#define SGMII2_RX_AFE_CTRL4_EN_TESTMUX_BITS                        1
#define SGMII2_RX_AFE_CTRL4_EN_TESTMUX_SHIFT                       15

/* SGMII2_RX_afe :: ctrl4 :: Sigdet_modeselect [14:14] */
#define Wr_SGMII2_RX_afe_ctrl4_Sigdet_modeselect(x) WriteRegBits16(SGMII2_RX_AFE_CTRL4,0x4000,14,x)
#define Rd_SGMII2_RX_afe_ctrl4_Sigdet_modeselect(x) ReadRegBits16(SGMII2_RX_AFE_CTRL4,0x4000,14)
#define SGMII2_RX_AFE_CTRL4_SIGDET_MODESELECT_MASK                 0x4000
#define SGMII2_RX_AFE_CTRL4_SIGDET_MODESELECT_ALIGN                0
#define SGMII2_RX_AFE_CTRL4_SIGDET_MODESELECT_BITS                 1
#define SGMII2_RX_AFE_CTRL4_SIGDET_MODESELECT_SHIFT                14

/* SGMII2_RX_afe :: ctrl4 :: sigdet_pd [13:13] */
#define Wr_SGMII2_RX_afe_ctrl4_sigdet_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL4,0x2000,13,x)
#define Rd_SGMII2_RX_afe_ctrl4_sigdet_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL4,0x2000,13)
#define SGMII2_RX_AFE_CTRL4_SIGDET_PD_MASK                         0x2000
#define SGMII2_RX_AFE_CTRL4_SIGDET_PD_ALIGN                        0
#define SGMII2_RX_AFE_CTRL4_SIGDET_PD_BITS                         1
#define SGMII2_RX_AFE_CTRL4_SIGDET_PD_SHIFT                        13

/* SGMII2_RX_afe :: ctrl4 :: sigdet_bypass [12:12] */
#define Wr_SGMII2_RX_afe_ctrl4_sigdet_bypass(x) WriteRegBits16(SGMII2_RX_AFE_CTRL4,0x1000,12,x)
#define Rd_SGMII2_RX_afe_ctrl4_sigdet_bypass(x) ReadRegBits16(SGMII2_RX_AFE_CTRL4,0x1000,12)
#define SGMII2_RX_AFE_CTRL4_SIGDET_BYPASS_MASK                     0x1000
#define SGMII2_RX_AFE_CTRL4_SIGDET_BYPASS_ALIGN                    0
#define SGMII2_RX_AFE_CTRL4_SIGDET_BYPASS_BITS                     1
#define SGMII2_RX_AFE_CTRL4_SIGDET_BYPASS_SHIFT                    12

/* SGMII2_RX_afe :: ctrl4 :: bias_sigdet_ctrl [11:09] */
#define Wr_SGMII2_RX_afe_ctrl4_bias_sigdet_ctrl(x) WriteRegBits16(SGMII2_RX_AFE_CTRL4,0xe00,9,x)
#define Rd_SGMII2_RX_afe_ctrl4_bias_sigdet_ctrl(x) ReadRegBits16(SGMII2_RX_AFE_CTRL4,0xe00,9)
#define SGMII2_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_MASK                  0x0e00
#define SGMII2_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_ALIGN                 0
#define SGMII2_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_BITS                  3
#define SGMII2_RX_AFE_CTRL4_BIAS_SIGDET_CTRL_SHIFT                 9

/* SGMII2_RX_afe :: ctrl4 :: bias_eyem_ctrl [08:06] */
#define Wr_SGMII2_RX_afe_ctrl4_bias_eyem_ctrl(x) WriteRegBits16(SGMII2_RX_AFE_CTRL4,0x1c0,6,x)
#define Rd_SGMII2_RX_afe_ctrl4_bias_eyem_ctrl(x) ReadRegBits16(SGMII2_RX_AFE_CTRL4,0x1c0,6)
#define SGMII2_RX_AFE_CTRL4_BIAS_EYEM_CTRL_MASK                    0x01c0
#define SGMII2_RX_AFE_CTRL4_BIAS_EYEM_CTRL_ALIGN                   0
#define SGMII2_RX_AFE_CTRL4_BIAS_EYEM_CTRL_BITS                    3
#define SGMII2_RX_AFE_CTRL4_BIAS_EYEM_CTRL_SHIFT                   6

/* SGMII2_RX_afe :: ctrl4 :: bias_la_dac_ctrl [05:03] */
#define Wr_SGMII2_RX_afe_ctrl4_bias_la_dac_ctrl(x) WriteRegBits16(SGMII2_RX_AFE_CTRL4,0x38,3,x)
#define Rd_SGMII2_RX_afe_ctrl4_bias_la_dac_ctrl(x) ReadRegBits16(SGMII2_RX_AFE_CTRL4,0x38,3)
#define SGMII2_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_MASK                  0x0038
#define SGMII2_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_ALIGN                 0
#define SGMII2_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_BITS                  3
#define SGMII2_RX_AFE_CTRL4_BIAS_LA_DAC_CTRL_SHIFT                 3

/* SGMII2_RX_afe :: ctrl4 :: bias_la_ctrl [02:00] */
#define Wr_SGMII2_RX_afe_ctrl4_bias_la_ctrl(x) WriteRegBits16(SGMII2_RX_AFE_CTRL4,0x7,0,x)
#define Rd_SGMII2_RX_afe_ctrl4_bias_la_ctrl(x) ReadRegBits16(SGMII2_RX_AFE_CTRL4,0x7,0)
#define SGMII2_RX_AFE_CTRL4_BIAS_LA_CTRL_MASK                      0x0007
#define SGMII2_RX_AFE_CTRL4_BIAS_LA_CTRL_ALIGN                     0
#define SGMII2_RX_AFE_CTRL4_BIAS_LA_CTRL_BITS                      3
#define SGMII2_RX_AFE_CTRL4_BIAS_LA_CTRL_SHIFT                     0


/****************************************************************************
 * SGMII2_RX_afe :: anaRxTest
 ***************************************************************************/
/* SGMII2_RX_afe :: anaRxTest :: sigdet_mux_SM [15:12] */
#define Wr_SGMII2_RX_afe_anaRxTest_sigdet_mux_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXTEST,0xf000,12,x)
#define Rd_SGMII2_RX_afe_anaRxTest_sigdet_mux_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXTEST,0xf000,12)
#define SGMII2_RX_AFE_ANARXTEST_SIGDET_MUX_SM_MASK                 0xf000
#define SGMII2_RX_AFE_ANARXTEST_SIGDET_MUX_SM_ALIGN                0
#define SGMII2_RX_AFE_ANARXTEST_SIGDET_MUX_SM_BITS                 4
#define SGMII2_RX_AFE_ANARXTEST_SIGDET_MUX_SM_SHIFT                12

/* SGMII2_RX_afe :: anaRxTest :: reserved0 [11:09] */
#define SGMII2_RX_AFE_ANARXTEST_RESERVED0_MASK                     0x0e00
#define SGMII2_RX_AFE_ANARXTEST_RESERVED0_ALIGN                    0
#define SGMII2_RX_AFE_ANARXTEST_RESERVED0_BITS                     3
#define SGMII2_RX_AFE_ANARXTEST_RESERVED0_SHIFT                    9

/* SGMII2_RX_afe :: anaRxTest :: tpctrl_SM [08:04] */
#define Wr_SGMII2_RX_afe_anaRxTest_tpctrl_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXTEST,0x1f0,4,x)
#define Rd_SGMII2_RX_afe_anaRxTest_tpctrl_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXTEST,0x1f0,4)
#define SGMII2_RX_AFE_ANARXTEST_TPCTRL_SM_MASK                     0x01f0
#define SGMII2_RX_AFE_ANARXTEST_TPCTRL_SM_ALIGN                    0
#define SGMII2_RX_AFE_ANARXTEST_TPCTRL_SM_BITS                     5
#define SGMII2_RX_AFE_ANARXTEST_TPCTRL_SM_SHIFT                    4

/* SGMII2_RX_afe :: anaRxTest :: testMuxSelect_SM [03:00] */
#define Wr_SGMII2_RX_afe_anaRxTest_testMuxSelect_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXTEST,0xf,0,x)
#define Rd_SGMII2_RX_afe_anaRxTest_testMuxSelect_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXTEST,0xf,0)
#define SGMII2_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_MASK              0x000f
#define SGMII2_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_ALIGN             0
#define SGMII2_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_BITS              4
#define SGMII2_RX_AFE_ANARXTEST_TESTMUXSELECT_SM_SHIFT             0


/****************************************************************************
 * SGMII2_RX_afe :: anaRxControl1G
 ***************************************************************************/
/* SGMII2_RX_afe :: anaRxControl1G :: fpat_md [15:15] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_fpat_md(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x8000,15,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_fpat_md(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x8000,15)
#define SGMII2_RX_AFE_ANARXCONTROL1G_FPAT_MD_MASK                  0x8000
#define SGMII2_RX_AFE_ANARXCONTROL1G_FPAT_MD_ALIGN                 0
#define SGMII2_RX_AFE_ANARXCONTROL1G_FPAT_MD_BITS                  1
#define SGMII2_RX_AFE_ANARXCONTROL1G_FPAT_MD_SHIFT                 15

/* SGMII2_RX_afe :: anaRxControl1G :: pkt_count_en [14:14] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_pkt_count_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x4000,14,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_pkt_count_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x4000,14)
#define SGMII2_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_MASK             0x4000
#define SGMII2_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_ALIGN            0
#define SGMII2_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_BITS             1
#define SGMII2_RX_AFE_ANARXCONTROL1G_PKT_COUNT_EN_SHIFT            14

/* SGMII2_RX_afe :: anaRxControl1G :: staMuxRegDis [13:13] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_staMuxRegDis(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x2000,13,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_staMuxRegDis(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x2000,13)
#define SGMII2_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_MASK             0x2000
#define SGMII2_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_ALIGN            0
#define SGMII2_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_BITS             1
#define SGMII2_RX_AFE_ANARXCONTROL1G_STAMUXREGDIS_SHIFT            13

/* SGMII2_RX_afe :: anaRxControl1G :: prbs_clr_dis [12:12] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_prbs_clr_dis(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x1000,12,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_prbs_clr_dis(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x1000,12)
#define SGMII2_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_MASK             0x1000
#define SGMII2_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_ALIGN            0
#define SGMII2_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_BITS             1
#define SGMII2_RX_AFE_ANARXCONTROL1G_PRBS_CLR_DIS_SHIFT            12

/* SGMII2_RX_afe :: anaRxControl1G :: rxd_dec_sel [11:11] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_rxd_dec_sel(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x800,11,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_rxd_dec_sel(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x800,11)
#define SGMII2_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_MASK              0x0800
#define SGMII2_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_ALIGN             0
#define SGMII2_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_BITS              1
#define SGMII2_RX_AFE_ANARXCONTROL1G_RXD_DEC_SEL_SHIFT             11

/* SGMII2_RX_afe :: anaRxControl1G :: cgbad_tst [10:10] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_cgbad_tst(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x400,10,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_cgbad_tst(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x400,10)
#define SGMII2_RX_AFE_ANARXCONTROL1G_CGBAD_TST_MASK                0x0400
#define SGMII2_RX_AFE_ANARXCONTROL1G_CGBAD_TST_ALIGN               0
#define SGMII2_RX_AFE_ANARXCONTROL1G_CGBAD_TST_BITS                1
#define SGMII2_RX_AFE_ANARXCONTROL1G_CGBAD_TST_SHIFT               10

/* SGMII2_RX_afe :: anaRxControl1G :: Emon_en [09:09] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_Emon_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x200,9,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_Emon_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x200,9)
#define SGMII2_RX_AFE_ANARXCONTROL1G_EMON_EN_MASK                  0x0200
#define SGMII2_RX_AFE_ANARXCONTROL1G_EMON_EN_ALIGN                 0
#define SGMII2_RX_AFE_ANARXCONTROL1G_EMON_EN_BITS                  1
#define SGMII2_RX_AFE_ANARXCONTROL1G_EMON_EN_SHIFT                 9

/* SGMII2_RX_afe :: anaRxControl1G :: prbs_en [08:08] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_prbs_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x100,8,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_prbs_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x100,8)
#define SGMII2_RX_AFE_ANARXCONTROL1G_PRBS_EN_MASK                  0x0100
#define SGMII2_RX_AFE_ANARXCONTROL1G_PRBS_EN_ALIGN                 0
#define SGMII2_RX_AFE_ANARXCONTROL1G_PRBS_EN_BITS                  1
#define SGMII2_RX_AFE_ANARXCONTROL1G_PRBS_EN_SHIFT                 8

/* SGMII2_RX_afe :: anaRxControl1G :: cgbad_en [07:07] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_cgbad_en(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x80,7,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_cgbad_en(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x80,7)
#define SGMII2_RX_AFE_ANARXCONTROL1G_CGBAD_EN_MASK                 0x0080
#define SGMII2_RX_AFE_ANARXCONTROL1G_CGBAD_EN_ALIGN                0
#define SGMII2_RX_AFE_ANARXCONTROL1G_CGBAD_EN_BITS                 1
#define SGMII2_RX_AFE_ANARXCONTROL1G_CGBAD_EN_SHIFT                7

/* SGMII2_RX_afe :: anaRxControl1G :: cstretch [06:06] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_cstretch(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x40,6,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_cstretch(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x40,6)
#define SGMII2_RX_AFE_ANARXCONTROL1G_CSTRETCH_MASK                 0x0040
#define SGMII2_RX_AFE_ANARXCONTROL1G_CSTRETCH_ALIGN                0
#define SGMII2_RX_AFE_ANARXCONTROL1G_CSTRETCH_BITS                 1
#define SGMII2_RX_AFE_ANARXCONTROL1G_CSTRETCH_SHIFT                6

/* SGMII2_RX_afe :: anaRxControl1G :: rtbi_ckflip [05:05] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_rtbi_ckflip(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_rtbi_ckflip(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x20,5)
#define SGMII2_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_MASK              0x0020
#define SGMII2_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_ALIGN             0
#define SGMII2_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_BITS              1
#define SGMII2_RX_AFE_ANARXCONTROL1G_RTBI_CKFLIP_SHIFT             5

/* SGMII2_RX_afe :: anaRxControl1G :: rtbi_flip [04:04] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_rtbi_flip(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_rtbi_flip(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x10,4)
#define SGMII2_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_MASK                0x0010
#define SGMII2_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_ALIGN               0
#define SGMII2_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_BITS                1
#define SGMII2_RX_AFE_ANARXCONTROL1G_RTBI_FLIP_SHIFT               4

/* SGMII2_RX_afe :: anaRxControl1G :: phase_sel_SM [03:03] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_phase_sel_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_phase_sel_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x8,3)
#define SGMII2_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_MASK             0x0008
#define SGMII2_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_ALIGN            0
#define SGMII2_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_BITS             1
#define SGMII2_RX_AFE_ANARXCONTROL1G_PHASE_SEL_SM_SHIFT            3

/* SGMII2_RX_afe :: anaRxControl1G :: spd_rstb_dis_SM [02:02] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_spd_rstb_dis_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_spd_rstb_dis_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x4,2)
#define SGMII2_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_MASK          0x0004
#define SGMII2_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_ALIGN         0
#define SGMII2_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_BITS          1
#define SGMII2_RX_AFE_ANARXCONTROL1G_SPD_RSTB_DIS_SM_SHIFT         2

/* SGMII2_RX_afe :: anaRxControl1G :: freq_sel_force [01:01] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_freq_sel_force(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x2,1,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_freq_sel_force(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x2,1)
#define SGMII2_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_MASK           0x0002
#define SGMII2_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_ALIGN          0
#define SGMII2_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_BITS           1
#define SGMII2_RX_AFE_ANARXCONTROL1G_FREQ_SEL_FORCE_SHIFT          1

/* SGMII2_RX_afe :: anaRxControl1G :: freq_sel [00:00] */
#define Wr_SGMII2_RX_afe_anaRxControl1G_freq_sel(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x1,0,x)
#define Rd_SGMII2_RX_afe_anaRxControl1G_freq_sel(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROL1G,0x1,0)
#define SGMII2_RX_AFE_ANARXCONTROL1G_FREQ_SEL_MASK                 0x0001
#define SGMII2_RX_AFE_ANARXCONTROL1G_FREQ_SEL_ALIGN                0
#define SGMII2_RX_AFE_ANARXCONTROL1G_FREQ_SEL_BITS                 1
#define SGMII2_RX_AFE_ANARXCONTROL1G_FREQ_SEL_SHIFT                0


/****************************************************************************
 * SGMII2_RX_afe :: anaRxControlPci
 ***************************************************************************/
/* SGMII2_RX_afe :: anaRxControlPci :: comma_adj_sync_sel [15:15] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_comma_adj_sync_sel(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x8000,15,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_comma_adj_sync_sel(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x8000,15)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_MASK      0x8000
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_ALIGN     0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_BITS      1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_SYNC_SEL_SHIFT     15

/* SGMII2_RX_afe :: anaRxControlPci :: comma_mask_force_r [14:14] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_comma_mask_force_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x4000,14,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_comma_mask_force_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x4000,14)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_MASK      0x4000
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_ALIGN     0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_BITS      1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_FORCE_R_SHIFT     14

/* SGMII2_RX_afe :: anaRxControlPci :: comma_mask_r [13:13] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_comma_mask_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x2000,13,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_comma_mask_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x2000,13)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_MASK            0x2000
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_ALIGN           0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_BITS            1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_MASK_R_SHIFT           13

/* SGMII2_RX_afe :: anaRxControlPci :: sync_status_force_sync_SM [12:12] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_sync_status_force_sync_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x1000,12,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_sync_status_force_sync_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x1000,12)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_MASK 0x1000
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_ALIGN 0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_BITS 1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_SYNC_SM_SHIFT 12

/* SGMII2_RX_afe :: anaRxControlPci :: sync_status_force_r_SM [11:11] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_sync_status_force_r_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x800,11,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_sync_status_force_r_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x800,11)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_MASK  0x0800
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_ALIGN 0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_BITS  1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SM_SHIFT 11

/* SGMII2_RX_afe :: anaRxControlPci :: sync_status_force_r [10:10] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_sync_status_force_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x400,10,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_sync_status_force_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x400,10)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_MASK     0x0400
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_ALIGN    0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_BITS     1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_SYNC_STATUS_FORCE_R_SHIFT    10

/* SGMII2_RX_afe :: anaRxControlPci :: comma_adj_en_force_ext_SM [09:09] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_comma_adj_en_force_ext_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x200,9,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_comma_adj_en_force_ext_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x200,9)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_MASK 0x0200
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_ALIGN 0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_BITS 1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_EXT_SM_SHIFT 9

/* SGMII2_RX_afe :: anaRxControlPci :: comma_adj_en_force_sync_SM [08:08] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_comma_adj_en_force_sync_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x100,8,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_comma_adj_en_force_sync_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x100,8)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_MASK 0x0100
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_ALIGN 0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_BITS 1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_SYNC_SM_SHIFT 8

/* SGMII2_RX_afe :: anaRxControlPci :: comma_adj_en_force_r_SM [07:07] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_comma_adj_en_force_r_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x80,7,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_comma_adj_en_force_r_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x80,7)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_MASK 0x0080
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_ALIGN 0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_BITS 1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_FORCE_R_SM_SHIFT 7

/* SGMII2_RX_afe :: anaRxControlPci :: comma_adj_en_r [06:06] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_comma_adj_en_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x40,6,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_comma_adj_en_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x40,6)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_MASK          0x0040
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_ALIGN         0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_BITS          1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_COMMA_ADJ_EN_R_SHIFT         6

/* SGMII2_RX_afe :: anaRxControlPci :: link_en_force_SM [05:05] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_link_en_force_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x20,5,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_link_en_force_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x20,5)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_MASK        0x0020
#define SGMII2_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_ALIGN       0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_BITS        1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_LINK_EN_FORCE_SM_SHIFT       5

/* SGMII2_RX_afe :: anaRxControlPci :: link_en_r [04:04] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_link_en_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x10,4,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_link_en_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x10,4)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_MASK               0x0010
#define SGMII2_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_ALIGN              0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_BITS               1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_LINK_EN_R_SHIFT              4

/* SGMII2_RX_afe :: anaRxControlPci :: rx_polarity_force_SM [03:03] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_rx_polarity_force_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x8,3,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_rx_polarity_force_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x8,3)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_MASK    0x0008
#define SGMII2_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_ALIGN   0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_BITS    1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_FORCE_SM_SHIFT   3

/* SGMII2_RX_afe :: anaRxControlPci :: rx_polarity_r [02:02] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_rx_polarity_r(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x4,2,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_rx_polarity_r(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x4,2)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_MASK           0x0004
#define SGMII2_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_ALIGN          0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_BITS           1
#define SGMII2_RX_AFE_ANARXCONTROLPCI_RX_POLARITY_R_SHIFT          2

/* SGMII2_RX_afe :: anaRxControlPci :: integ_mode_SM [01:00] */
#define Wr_SGMII2_RX_afe_anaRxControlPci_integ_mode_SM(x) WriteRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x3,0,x)
#define Rd_SGMII2_RX_afe_anaRxControlPci_integ_mode_SM(x) ReadRegBits16(SGMII2_RX_AFE_ANARXCONTROLPCI,0x3,0)
#define SGMII2_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_MASK           0x0003
#define SGMII2_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_ALIGN          0
#define SGMII2_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_BITS           2
#define SGMII2_RX_AFE_ANARXCONTROLPCI_INTEG_MODE_SM_SHIFT          0


/****************************************************************************
 * SGMII2_RX_afe :: anaRxAstatus
 ***************************************************************************/
/* SGMII2_RX_afe :: anaRxAstatus :: genstat [15:00] */
#define Wr_SGMII2_RX_afe_anaRxAstatus_genstat(x) WriteReg16(SGMII2_RX_AFE_ANARXASTATUS,x)
#define Rd_SGMII2_RX_afe_anaRxAstatus_genstat(x) ReadReg16(SGMII2_RX_AFE_ANARXASTATUS)
#define SGMII2_RX_AFE_ANARXASTATUS_GENSTAT_MASK                    0xffff
#define SGMII2_RX_AFE_ANARXASTATUS_GENSTAT_ALIGN                   0
#define SGMII2_RX_AFE_ANARXASTATUS_GENSTAT_BITS                    16
#define SGMII2_RX_AFE_ANARXASTATUS_GENSTAT_SHIFT                   0


/****************************************************************************
 * SGMII2_RX_afe :: ctrl5
 ***************************************************************************/
/* SGMII2_RX_afe :: ctrl5 :: sigdet_usb_en [15:15] */
#define Wr_SGMII2_RX_afe_ctrl5_sigdet_usb_en(x) WriteRegBits16(SGMII2_RX_AFE_CTRL5,0x8000,15,x)
#define Rd_SGMII2_RX_afe_ctrl5_sigdet_usb_en(x) ReadRegBits16(SGMII2_RX_AFE_CTRL5,0x8000,15)
#define SGMII2_RX_AFE_CTRL5_SIGDET_USB_EN_MASK                     0x8000
#define SGMII2_RX_AFE_CTRL5_SIGDET_USB_EN_ALIGN                    0
#define SGMII2_RX_AFE_CTRL5_SIGDET_USB_EN_BITS                     1
#define SGMII2_RX_AFE_CTRL5_SIGDET_USB_EN_SHIFT                    15

/* SGMII2_RX_afe :: ctrl5 :: pi_eyem_enable [14:14] */
#define Wr_SGMII2_RX_afe_ctrl5_pi_eyem_enable(x) WriteRegBits16(SGMII2_RX_AFE_CTRL5,0x4000,14,x)
#define Rd_SGMII2_RX_afe_ctrl5_pi_eyem_enable(x) ReadRegBits16(SGMII2_RX_AFE_CTRL5,0x4000,14)
#define SGMII2_RX_AFE_CTRL5_PI_EYEM_ENABLE_MASK                    0x4000
#define SGMII2_RX_AFE_CTRL5_PI_EYEM_ENABLE_ALIGN                   0
#define SGMII2_RX_AFE_CTRL5_PI_EYEM_ENABLE_BITS                    1
#define SGMII2_RX_AFE_CTRL5_PI_EYEM_ENABLE_SHIFT                   14

/* SGMII2_RX_afe :: ctrl5 :: pi_main_enable [13:13] */
#define Wr_SGMII2_RX_afe_ctrl5_pi_main_enable(x) WriteRegBits16(SGMII2_RX_AFE_CTRL5,0x2000,13,x)
#define Rd_SGMII2_RX_afe_ctrl5_pi_main_enable(x) ReadRegBits16(SGMII2_RX_AFE_CTRL5,0x2000,13)
#define SGMII2_RX_AFE_CTRL5_PI_MAIN_ENABLE_MASK                    0x2000
#define SGMII2_RX_AFE_CTRL5_PI_MAIN_ENABLE_ALIGN                   0
#define SGMII2_RX_AFE_CTRL5_PI_MAIN_ENABLE_BITS                    1
#define SGMII2_RX_AFE_CTRL5_PI_MAIN_ENABLE_SHIFT                   13

/* SGMII2_RX_afe :: ctrl5 :: eyemonitor_ref_zero [12:12] */
#define Wr_SGMII2_RX_afe_ctrl5_eyemonitor_ref_zero(x) WriteRegBits16(SGMII2_RX_AFE_CTRL5,0x1000,12,x)
#define Rd_SGMII2_RX_afe_ctrl5_eyemonitor_ref_zero(x) ReadRegBits16(SGMII2_RX_AFE_CTRL5,0x1000,12)
#define SGMII2_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_MASK               0x1000
#define SGMII2_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_ALIGN              0
#define SGMII2_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_BITS               1
#define SGMII2_RX_AFE_CTRL5_EYEMONITOR_REF_ZERO_SHIFT              12

/* SGMII2_RX_afe :: ctrl5 :: eyemonitorref_pd [11:11] */
#define Wr_SGMII2_RX_afe_ctrl5_eyemonitorref_pd(x) WriteRegBits16(SGMII2_RX_AFE_CTRL5,0x800,11,x)
#define Rd_SGMII2_RX_afe_ctrl5_eyemonitorref_pd(x) ReadRegBits16(SGMII2_RX_AFE_CTRL5,0x800,11)
#define SGMII2_RX_AFE_CTRL5_EYEMONITORREF_PD_MASK                  0x0800
#define SGMII2_RX_AFE_CTRL5_EYEMONITORREF_PD_ALIGN                 0
#define SGMII2_RX_AFE_CTRL5_EYEMONITORREF_PD_BITS                  1
#define SGMII2_RX_AFE_CTRL5_EYEMONITORREF_PD_SHIFT                 11

/* SGMII2_RX_afe :: ctrl5 :: eyem_refadjust [10:06] */
#define Wr_SGMII2_RX_afe_ctrl5_eyem_refadjust(x) WriteRegBits16(SGMII2_RX_AFE_CTRL5,0x7c0,6,x)
#define Rd_SGMII2_RX_afe_ctrl5_eyem_refadjust(x) ReadRegBits16(SGMII2_RX_AFE_CTRL5,0x7c0,6)
#define SGMII2_RX_AFE_CTRL5_EYEM_REFADJUST_MASK                    0x07c0
#define SGMII2_RX_AFE_CTRL5_EYEM_REFADJUST_ALIGN                   0
#define SGMII2_RX_AFE_CTRL5_EYEM_REFADJUST_BITS                    5
#define SGMII2_RX_AFE_CTRL5_EYEM_REFADJUST_SHIFT                   6

/* SGMII2_RX_afe :: ctrl5 :: sel_clk [05:04] */
#define Wr_SGMII2_RX_afe_ctrl5_sel_clk(x) WriteRegBits16(SGMII2_RX_AFE_CTRL5,0x30,4,x)
#define Rd_SGMII2_RX_afe_ctrl5_sel_clk(x) ReadRegBits16(SGMII2_RX_AFE_CTRL5,0x30,4)
#define SGMII2_RX_AFE_CTRL5_SEL_CLK_MASK                           0x0030
#define SGMII2_RX_AFE_CTRL5_SEL_CLK_ALIGN                          0
#define SGMII2_RX_AFE_CTRL5_SEL_CLK_BITS                           2
#define SGMII2_RX_AFE_CTRL5_SEL_CLK_SHIFT                          4

/* SGMII2_RX_afe :: ctrl5 :: Sigdet_threshold [03:00] */
#define Wr_SGMII2_RX_afe_ctrl5_Sigdet_threshold(x) WriteRegBits16(SGMII2_RX_AFE_CTRL5,0xf,0,x)
#define Rd_SGMII2_RX_afe_ctrl5_Sigdet_threshold(x) ReadRegBits16(SGMII2_RX_AFE_CTRL5,0xf,0)
#define SGMII2_RX_AFE_CTRL5_SIGDET_THRESHOLD_MASK                  0x000f
#define SGMII2_RX_AFE_CTRL5_SIGDET_THRESHOLD_ALIGN                 0
#define SGMII2_RX_AFE_CTRL5_SIGDET_THRESHOLD_BITS                  4
#define SGMII2_RX_AFE_CTRL5_SIGDET_THRESHOLD_SHIFT                 0


/****************************************************************************
 * SGMII2_RX_afe :: ctrl6
 ***************************************************************************/
/* SGMII2_RX_afe :: ctrl6 :: reserved0 [15:10] */
#define SGMII2_RX_AFE_CTRL6_RESERVED0_MASK                         0xfc00
#define SGMII2_RX_AFE_CTRL6_RESERVED0_ALIGN                        0
#define SGMII2_RX_AFE_CTRL6_RESERVED0_BITS                         6
#define SGMII2_RX_AFE_CTRL6_RESERVED0_SHIFT                        10

/* SGMII2_RX_afe :: ctrl6 :: reserved_105_103 [09:07] */
#define SGMII2_RX_AFE_CTRL6_RESERVED_105_103_MASK                  0x0380
#define SGMII2_RX_AFE_CTRL6_RESERVED_105_103_ALIGN                 0
#define SGMII2_RX_AFE_CTRL6_RESERVED_105_103_BITS                  3
#define SGMII2_RX_AFE_CTRL6_RESERVED_105_103_SHIFT                 7

/* SGMII2_RX_afe :: ctrl6 :: Eye_Monitor_PI_BW_sel [06:06] */
#define Wr_SGMII2_RX_afe_ctrl6_Eye_Monitor_PI_BW_sel(x) WriteRegBits16(SGMII2_RX_AFE_CTRL6,0x40,6,x)
#define Rd_SGMII2_RX_afe_ctrl6_Eye_Monitor_PI_BW_sel(x) ReadRegBits16(SGMII2_RX_AFE_CTRL6,0x40,6)
#define SGMII2_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_MASK             0x0040
#define SGMII2_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_ALIGN            0
#define SGMII2_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_BITS             1
#define SGMII2_RX_AFE_CTRL6_EYE_MONITOR_PI_BW_SEL_SHIFT            6

/* SGMII2_RX_afe :: ctrl6 :: Eye_Monitor_PI_pwd_lvl2pi [05:05] */
#define Wr_SGMII2_RX_afe_ctrl6_Eye_Monitor_PI_pwd_lvl2pi(x) WriteRegBits16(SGMII2_RX_AFE_CTRL6,0x20,5,x)
#define Rd_SGMII2_RX_afe_ctrl6_Eye_Monitor_PI_pwd_lvl2pi(x) ReadRegBits16(SGMII2_RX_AFE_CTRL6,0x20,5)
#define SGMII2_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_MASK         0x0020
#define SGMII2_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_ALIGN        0
#define SGMII2_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_BITS         1
#define SGMII2_RX_AFE_CTRL6_EYE_MONITOR_PI_PWD_LVL2PI_SHIFT        5

/* SGMII2_RX_afe :: ctrl6 :: reserved_100 [04:04] */
#define SGMII2_RX_AFE_CTRL6_RESERVED_100_MASK                      0x0010
#define SGMII2_RX_AFE_CTRL6_RESERVED_100_ALIGN                     0
#define SGMII2_RX_AFE_CTRL6_RESERVED_100_BITS                      1
#define SGMII2_RX_AFE_CTRL6_RESERVED_100_SHIFT                     4

/* SGMII2_RX_afe :: ctrl6 :: PI_lowvdd_enb [03:03] */
#define Wr_SGMII2_RX_afe_ctrl6_PI_lowvdd_enb(x) WriteRegBits16(SGMII2_RX_AFE_CTRL6,0x8,3,x)
#define Rd_SGMII2_RX_afe_ctrl6_PI_lowvdd_enb(x) ReadRegBits16(SGMII2_RX_AFE_CTRL6,0x8,3)
#define SGMII2_RX_AFE_CTRL6_PI_LOWVDD_ENB_MASK                     0x0008
#define SGMII2_RX_AFE_CTRL6_PI_LOWVDD_ENB_ALIGN                    0
#define SGMII2_RX_AFE_CTRL6_PI_LOWVDD_ENB_BITS                     1
#define SGMII2_RX_AFE_CTRL6_PI_LOWVDD_ENB_SHIFT                    3

/* SGMII2_RX_afe :: ctrl6 :: Main_PI_BW_sel [02:02] */
#define Wr_SGMII2_RX_afe_ctrl6_Main_PI_BW_sel(x) WriteRegBits16(SGMII2_RX_AFE_CTRL6,0x4,2,x)
#define Rd_SGMII2_RX_afe_ctrl6_Main_PI_BW_sel(x) ReadRegBits16(SGMII2_RX_AFE_CTRL6,0x4,2)
#define SGMII2_RX_AFE_CTRL6_MAIN_PI_BW_SEL_MASK                    0x0004
#define SGMII2_RX_AFE_CTRL6_MAIN_PI_BW_SEL_ALIGN                   0
#define SGMII2_RX_AFE_CTRL6_MAIN_PI_BW_SEL_BITS                    1
#define SGMII2_RX_AFE_CTRL6_MAIN_PI_BW_SEL_SHIFT                   2

/* SGMII2_RX_afe :: ctrl6 :: Main_PI_pwd_lvl2pi [01:01] */
#define Wr_SGMII2_RX_afe_ctrl6_Main_PI_pwd_lvl2pi(x) WriteRegBits16(SGMII2_RX_AFE_CTRL6,0x2,1,x)
#define Rd_SGMII2_RX_afe_ctrl6_Main_PI_pwd_lvl2pi(x) ReadRegBits16(SGMII2_RX_AFE_CTRL6,0x2,1)
#define SGMII2_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_MASK                0x0002
#define SGMII2_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_ALIGN               0
#define SGMII2_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_BITS                1
#define SGMII2_RX_AFE_CTRL6_MAIN_PI_PWD_LVL2PI_SHIFT               1

/* SGMII2_RX_afe :: ctrl6 :: reserved_96 [00:00] */
#define SGMII2_RX_AFE_CTRL6_RESERVED_96_MASK                       0x0001
#define SGMII2_RX_AFE_CTRL6_RESERVED_96_ALIGN                      0
#define SGMII2_RX_AFE_CTRL6_RESERVED_96_BITS                       1
#define SGMII2_RX_AFE_CTRL6_RESERVED_96_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_Digital
 ***************************************************************************/
/****************************************************************************
 * SGMII2_Digital :: Control1000X1
 ***************************************************************************/
/* SGMII2_Digital :: Control1000X1 :: reserved0 [15:15] */
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED0_MASK                0x8000
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED0_ALIGN               0
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED0_BITS                1
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED0_SHIFT               15

/* SGMII2_Digital :: Control1000X1 :: disable_signal_detect_filter [14:14] */
#define Wr_SGMII2_Digital_Control1000X1_disable_signal_detect_filter(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x4000,14,x)
#define Rd_SGMII2_Digital_Control1000X1_disable_signal_detect_filter(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x4000,14)
#define SGMII2_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_MASK 0x4000
#define SGMII2_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_BITS 1
#define SGMII2_DIGITAL_CONTROL1000X1_DISABLE_SIGNAL_DETECT_FILTER_SHIFT 14

/* SGMII2_Digital :: Control1000X1 :: reserved1 [13:12] */
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED1_MASK                0x3000
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED1_ALIGN               0
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED1_BITS                2
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED1_SHIFT               12

/* SGMII2_Digital :: Control1000X1 :: sel_rx_pkts_for_cntr [11:11] */
#define Wr_SGMII2_Digital_Control1000X1_sel_rx_pkts_for_cntr(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x800,11,x)
#define Rd_SGMII2_Digital_Control1000X1_sel_rx_pkts_for_cntr(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x800,11)
#define SGMII2_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_MASK     0x0800
#define SGMII2_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_ALIGN    0
#define SGMII2_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_BITS     1
#define SGMII2_DIGITAL_CONTROL1000X1_SEL_RX_PKTS_FOR_CNTR_SHIFT    11

/* SGMII2_Digital :: Control1000X1 :: remote_loopback [10:10] */
#define Wr_SGMII2_Digital_Control1000X1_remote_loopback(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x400,10,x)
#define Rd_SGMII2_Digital_Control1000X1_remote_loopback(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x400,10)
#define SGMII2_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_MASK          0x0400
#define SGMII2_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_ALIGN         0
#define SGMII2_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_BITS          1
#define SGMII2_DIGITAL_CONTROL1000X1_REMOTE_LOOPBACK_SHIFT         10

/* SGMII2_Digital :: Control1000X1 :: zero_comma_detector_phase [09:09] */
#define Wr_SGMII2_Digital_Control1000X1_zero_comma_detector_phase(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x200,9,x)
#define Rd_SGMII2_Digital_Control1000X1_zero_comma_detector_phase(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x200,9)
#define SGMII2_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_MASK 0x0200
#define SGMII2_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_BITS 1
#define SGMII2_DIGITAL_CONTROL1000X1_ZERO_COMMA_DETECTOR_PHASE_SHIFT 9

/* SGMII2_Digital :: Control1000X1 :: comma_det_en [08:08] */
#define Wr_SGMII2_Digital_Control1000X1_comma_det_en(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x100,8,x)
#define Rd_SGMII2_Digital_Control1000X1_comma_det_en(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x100,8)
#define SGMII2_DIGITAL_CONTROL1000X1_COMMA_DET_EN_MASK             0x0100
#define SGMII2_DIGITAL_CONTROL1000X1_COMMA_DET_EN_ALIGN            0
#define SGMII2_DIGITAL_CONTROL1000X1_COMMA_DET_EN_BITS             1
#define SGMII2_DIGITAL_CONTROL1000X1_COMMA_DET_EN_SHIFT            8

/* SGMII2_Digital :: Control1000X1 :: crc_checker_disable [07:07] */
#define Wr_SGMII2_Digital_Control1000X1_crc_checker_disable(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x80,7,x)
#define Rd_SGMII2_Digital_Control1000X1_crc_checker_disable(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x80,7)
#define SGMII2_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_MASK      0x0080
#define SGMII2_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_ALIGN     0
#define SGMII2_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_BITS      1
#define SGMII2_DIGITAL_CONTROL1000X1_CRC_CHECKER_DISABLE_SHIFT     7

/* SGMII2_Digital :: Control1000X1 :: disable_pll_pwrdwn [06:06] */
#define Wr_SGMII2_Digital_Control1000X1_disable_pll_pwrdwn(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x40,6,x)
#define Rd_SGMII2_Digital_Control1000X1_disable_pll_pwrdwn(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x40,6)
#define SGMII2_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_MASK       0x0040
#define SGMII2_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_ALIGN      0
#define SGMII2_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_BITS       1
#define SGMII2_DIGITAL_CONTROL1000X1_DISABLE_PLL_PWRDWN_SHIFT      6

/* SGMII2_Digital :: Control1000X1 :: sgmii_master_mode [05:05] */
#define Wr_SGMII2_Digital_Control1000X1_sgmii_master_mode(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x20,5,x)
#define Rd_SGMII2_Digital_Control1000X1_sgmii_master_mode(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x20,5)
#define SGMII2_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_MASK        0x0020
#define SGMII2_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_ALIGN       0
#define SGMII2_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_BITS        1
#define SGMII2_DIGITAL_CONTROL1000X1_SGMII_MASTER_MODE_SHIFT       5

/* SGMII2_Digital :: Control1000X1 :: reserved2 [04:04] */
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED2_MASK                0x0010
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED2_ALIGN               0
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED2_BITS                1
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED2_SHIFT               4

/* SGMII2_Digital :: Control1000X1 :: invert_signal_detect [03:03] */
#define Wr_SGMII2_Digital_Control1000X1_invert_signal_detect(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x8,3,x)
#define Rd_SGMII2_Digital_Control1000X1_invert_signal_detect(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x8,3)
#define SGMII2_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_MASK     0x0008
#define SGMII2_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_ALIGN    0
#define SGMII2_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_BITS     1
#define SGMII2_DIGITAL_CONTROL1000X1_INVERT_SIGNAL_DETECT_SHIFT    3

/* SGMII2_Digital :: Control1000X1 :: signal_detect_en [02:02] */
#define Wr_SGMII2_Digital_Control1000X1_signal_detect_en(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x4,2,x)
#define Rd_SGMII2_Digital_Control1000X1_signal_detect_en(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x4,2)
#define SGMII2_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_MASK         0x0004
#define SGMII2_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_ALIGN        0
#define SGMII2_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_BITS         1
#define SGMII2_DIGITAL_CONTROL1000X1_SIGNAL_DETECT_EN_SHIFT        2

/* SGMII2_Digital :: Control1000X1 :: reserved3 [01:01] */
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED3_MASK                0x0002
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED3_ALIGN               0
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED3_BITS                1
#define SGMII2_DIGITAL_CONTROL1000X1_RESERVED3_SHIFT               1

/* SGMII2_Digital :: Control1000X1 :: fiber_mode_1000X [00:00] */
#define Wr_SGMII2_Digital_Control1000X1_fiber_mode_1000X(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x1,0,x)
#define Rd_SGMII2_Digital_Control1000X1_fiber_mode_1000X(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X1,0x1,0)
#define SGMII2_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_MASK         0x0001
#define SGMII2_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_ALIGN        0
#define SGMII2_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_BITS         1
#define SGMII2_DIGITAL_CONTROL1000X1_FIBER_MODE_1000X_SHIFT        0


/****************************************************************************
 * SGMII2_Digital :: Control1000X2
 ***************************************************************************/
/* SGMII2_Digital :: Control1000X2 :: disable_extend_fdx_only [15:15] */
#define Wr_SGMII2_Digital_Control1000X2_disable_extend_fdx_only(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x8000,15,x)
#define Rd_SGMII2_Digital_Control1000X2_disable_extend_fdx_only(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x8000,15)
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_MASK  0x8000
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_BITS  1
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_EXTEND_FDX_ONLY_SHIFT 15

/* SGMII2_Digital :: Control1000X2 :: clear_ber_counter [14:14] */
#define Wr_SGMII2_Digital_Control1000X2_clear_ber_counter(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x4000,14,x)
#define Rd_SGMII2_Digital_Control1000X2_clear_ber_counter(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x4000,14)
#define SGMII2_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_MASK        0x4000
#define SGMII2_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_ALIGN       0
#define SGMII2_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_BITS        1
#define SGMII2_DIGITAL_CONTROL1000X2_CLEAR_BER_COUNTER_SHIFT       14

/* SGMII2_Digital :: Control1000X2 :: transmit_idlejam_seq_test [13:13] */
#define Wr_SGMII2_Digital_Control1000X2_transmit_idlejam_seq_test(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x2000,13,x)
#define Rd_SGMII2_Digital_Control1000X2_transmit_idlejam_seq_test(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x2000,13)
#define SGMII2_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_MASK 0x2000
#define SGMII2_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_BITS 1
#define SGMII2_DIGITAL_CONTROL1000X2_TRANSMIT_IDLEJAM_SEQ_TEST_SHIFT 13

/* SGMII2_Digital :: Control1000X2 :: transmit_packet_seq_test [12:12] */
#define Wr_SGMII2_Digital_Control1000X2_transmit_packet_seq_test(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x1000,12,x)
#define Rd_SGMII2_Digital_Control1000X2_transmit_packet_seq_test(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x1000,12)
#define SGMII2_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_MASK 0x1000
#define SGMII2_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_BITS 1
#define SGMII2_DIGITAL_CONTROL1000X2_TRANSMIT_PACKET_SEQ_TEST_SHIFT 12

/* SGMII2_Digital :: Control1000X2 :: test_cntr [11:11] */
#define Wr_SGMII2_Digital_Control1000X2_test_cntr(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x800,11,x)
#define Rd_SGMII2_Digital_Control1000X2_test_cntr(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x800,11)
#define SGMII2_DIGITAL_CONTROL1000X2_TEST_CNTR_MASK                0x0800
#define SGMII2_DIGITAL_CONTROL1000X2_TEST_CNTR_ALIGN               0
#define SGMII2_DIGITAL_CONTROL1000X2_TEST_CNTR_BITS                1
#define SGMII2_DIGITAL_CONTROL1000X2_TEST_CNTR_SHIFT               11

/* SGMII2_Digital :: Control1000X2 :: bypass_pcs_tx [10:10] */
#define Wr_SGMII2_Digital_Control1000X2_bypass_pcs_tx(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x400,10,x)
#define Rd_SGMII2_Digital_Control1000X2_bypass_pcs_tx(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x400,10)
#define SGMII2_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_MASK            0x0400
#define SGMII2_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_ALIGN           0
#define SGMII2_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_BITS            1
#define SGMII2_DIGITAL_CONTROL1000X2_BYPASS_PCS_TX_SHIFT           10

/* SGMII2_Digital :: Control1000X2 :: bypass_pcs_rx [09:09] */
#define Wr_SGMII2_Digital_Control1000X2_bypass_pcs_rx(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x200,9,x)
#define Rd_SGMII2_Digital_Control1000X2_bypass_pcs_rx(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x200,9)
#define SGMII2_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_MASK            0x0200
#define SGMII2_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_ALIGN           0
#define SGMII2_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_BITS            1
#define SGMII2_DIGITAL_CONTROL1000X2_BYPASS_PCS_RX_SHIFT           9

/* SGMII2_Digital :: Control1000X2 :: disable_TRRR_generation [08:08] */
#define Wr_SGMII2_Digital_Control1000X2_disable_TRRR_generation(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x100,8,x)
#define Rd_SGMII2_Digital_Control1000X2_disable_TRRR_generation(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x100,8)
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_MASK  0x0100
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_BITS  1
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_TRRR_GENERATION_SHIFT 8

/* SGMII2_Digital :: Control1000X2 :: disable_carrier_extend [07:07] */
#define Wr_SGMII2_Digital_Control1000X2_disable_carrier_extend(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x80,7,x)
#define Rd_SGMII2_Digital_Control1000X2_disable_carrier_extend(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x80,7)
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_MASK   0x0080
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_ALIGN  0
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_BITS   1
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_CARRIER_EXTEND_SHIFT  7

/* SGMII2_Digital :: Control1000X2 :: autoneg_fast_timers [06:06] */
#define Wr_SGMII2_Digital_Control1000X2_autoneg_fast_timers(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x40,6,x)
#define Rd_SGMII2_Digital_Control1000X2_autoneg_fast_timers(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x40,6)
#define SGMII2_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_MASK      0x0040
#define SGMII2_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_ALIGN     0
#define SGMII2_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_BITS      1
#define SGMII2_DIGITAL_CONTROL1000X2_AUTONEG_FAST_TIMERS_SHIFT     6

/* SGMII2_Digital :: Control1000X2 :: force_xmit_data_on_txside [05:05] */
#define Wr_SGMII2_Digital_Control1000X2_force_xmit_data_on_txside(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x20,5,x)
#define Rd_SGMII2_Digital_Control1000X2_force_xmit_data_on_txside(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x20,5)
#define SGMII2_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_MASK 0x0020
#define SGMII2_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_BITS 1
#define SGMII2_DIGITAL_CONTROL1000X2_FORCE_XMIT_DATA_ON_TXSIDE_SHIFT 5

/* SGMII2_Digital :: Control1000X2 :: disable_remote_fault_sensing [04:04] */
#define Wr_SGMII2_Digital_Control1000X2_disable_remote_fault_sensing(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x10,4,x)
#define Rd_SGMII2_Digital_Control1000X2_disable_remote_fault_sensing(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x10,4)
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_MASK 0x0010
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_BITS 1
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_REMOTE_FAULT_SENSING_SHIFT 4

/* SGMII2_Digital :: Control1000X2 :: enable_autoneg_err_timer [03:03] */
#define Wr_SGMII2_Digital_Control1000X2_enable_autoneg_err_timer(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x8,3,x)
#define Rd_SGMII2_Digital_Control1000X2_enable_autoneg_err_timer(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x8,3)
#define SGMII2_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_MASK 0x0008
#define SGMII2_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_BITS 1
#define SGMII2_DIGITAL_CONTROL1000X2_ENABLE_AUTONEG_ERR_TIMER_SHIFT 3

/* SGMII2_Digital :: Control1000X2 :: filter_force_link [02:02] */
#define Wr_SGMII2_Digital_Control1000X2_filter_force_link(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x4,2,x)
#define Rd_SGMII2_Digital_Control1000X2_filter_force_link(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x4,2)
#define SGMII2_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_MASK        0x0004
#define SGMII2_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_ALIGN       0
#define SGMII2_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_BITS        1
#define SGMII2_DIGITAL_CONTROL1000X2_FILTER_FORCE_LINK_SHIFT       2

/* SGMII2_Digital :: Control1000X2 :: disable_false_link [01:01] */
#define Wr_SGMII2_Digital_Control1000X2_disable_false_link(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x2,1,x)
#define Rd_SGMII2_Digital_Control1000X2_disable_false_link(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X2,0x2,1)
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_MASK       0x0002
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_ALIGN      0
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_BITS       1
#define SGMII2_DIGITAL_CONTROL1000X2_DISABLE_FALSE_LINK_SHIFT      1

/* SGMII2_Digital :: Control1000X2 :: reserved0 [00:00] */
#define SGMII2_DIGITAL_CONTROL1000X2_RESERVED0_MASK                0x0001
#define SGMII2_DIGITAL_CONTROL1000X2_RESERVED0_ALIGN               0
#define SGMII2_DIGITAL_CONTROL1000X2_RESERVED0_BITS                1
#define SGMII2_DIGITAL_CONTROL1000X2_RESERVED0_SHIFT               0


/****************************************************************************
 * SGMII2_Digital :: Control1000X3
 ***************************************************************************/
/* SGMII2_Digital :: Control1000X3 :: disable_packet_misalign [15:15] */
#define Wr_SGMII2_Digital_Control1000X3_disable_packet_misalign(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x8000,15,x)
#define Rd_SGMII2_Digital_Control1000X3_disable_packet_misalign(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x8000,15)
#define SGMII2_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_MASK  0x8000
#define SGMII2_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_BITS  1
#define SGMII2_DIGITAL_CONTROL1000X3_DISABLE_PACKET_MISALIGN_SHIFT 15

/* SGMII2_Digital :: Control1000X3 :: rxfifo_gmii_reset [14:14] */
#define Wr_SGMII2_Digital_Control1000X3_rxfifo_gmii_reset(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x4000,14,x)
#define Rd_SGMII2_Digital_Control1000X3_rxfifo_gmii_reset(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x4000,14)
#define SGMII2_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_MASK        0x4000
#define SGMII2_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_ALIGN       0
#define SGMII2_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_BITS        1
#define SGMII2_DIGITAL_CONTROL1000X3_RXFIFO_GMII_RESET_SHIFT       14

/* SGMII2_Digital :: Control1000X3 :: disable_tx_crs [13:13] */
#define Wr_SGMII2_Digital_Control1000X3_disable_tx_crs(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x2000,13,x)
#define Rd_SGMII2_Digital_Control1000X3_disable_tx_crs(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x2000,13)
#define SGMII2_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_MASK           0x2000
#define SGMII2_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_ALIGN          0
#define SGMII2_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_BITS           1
#define SGMII2_DIGITAL_CONTROL1000X3_DISABLE_TX_CRS_SHIFT          13

/* SGMII2_Digital :: Control1000X3 :: invert_ext_phy_crs [12:12] */
#define Wr_SGMII2_Digital_Control1000X3_invert_ext_phy_crs(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x1000,12,x)
#define Rd_SGMII2_Digital_Control1000X3_invert_ext_phy_crs(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x1000,12)
#define SGMII2_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_MASK       0x1000
#define SGMII2_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_ALIGN      0
#define SGMII2_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_BITS       1
#define SGMII2_DIGITAL_CONTROL1000X3_INVERT_EXT_PHY_CRS_SHIFT      12

/* SGMII2_Digital :: Control1000X3 :: ext_phy_crs_mode [11:11] */
#define Wr_SGMII2_Digital_Control1000X3_ext_phy_crs_mode(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x800,11,x)
#define Rd_SGMII2_Digital_Control1000X3_ext_phy_crs_mode(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x800,11)
#define SGMII2_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_MASK         0x0800
#define SGMII2_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_ALIGN        0
#define SGMII2_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_BITS         1
#define SGMII2_DIGITAL_CONTROL1000X3_EXT_PHY_CRS_MODE_SHIFT        11

/* SGMII2_Digital :: Control1000X3 :: jam_false_carrier_mode [10:10] */
#define Wr_SGMII2_Digital_Control1000X3_jam_false_carrier_mode(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x400,10,x)
#define Rd_SGMII2_Digital_Control1000X3_jam_false_carrier_mode(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x400,10)
#define SGMII2_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_MASK   0x0400
#define SGMII2_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_ALIGN  0
#define SGMII2_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_BITS   1
#define SGMII2_DIGITAL_CONTROL1000X3_JAM_FALSE_CARRIER_MODE_SHIFT  10

/* SGMII2_Digital :: Control1000X3 :: block_txen_mode [09:09] */
#define Wr_SGMII2_Digital_Control1000X3_block_txen_mode(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x200,9,x)
#define Rd_SGMII2_Digital_Control1000X3_block_txen_mode(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x200,9)
#define SGMII2_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_MASK          0x0200
#define SGMII2_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_ALIGN         0
#define SGMII2_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_BITS          1
#define SGMII2_DIGITAL_CONTROL1000X3_BLOCK_TXEN_MODE_SHIFT         9

/* SGMII2_Digital :: Control1000X3 :: force_txfifo_on [08:08] */
#define Wr_SGMII2_Digital_Control1000X3_force_txfifo_on(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x100,8,x)
#define Rd_SGMII2_Digital_Control1000X3_force_txfifo_on(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x100,8)
#define SGMII2_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_MASK          0x0100
#define SGMII2_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_ALIGN         0
#define SGMII2_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_BITS          1
#define SGMII2_DIGITAL_CONTROL1000X3_FORCE_TXFIFO_ON_SHIFT         8

/* SGMII2_Digital :: Control1000X3 :: bypass_txfifo1000 [07:07] */
#define Wr_SGMII2_Digital_Control1000X3_bypass_txfifo1000(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x80,7,x)
#define Rd_SGMII2_Digital_Control1000X3_bypass_txfifo1000(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x80,7)
#define SGMII2_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_MASK        0x0080
#define SGMII2_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_ALIGN       0
#define SGMII2_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_BITS        1
#define SGMII2_DIGITAL_CONTROL1000X3_BYPASS_TXFIFO1000_SHIFT       7

/* SGMII2_Digital :: Control1000X3 :: reserved_6 [06:06] */
#define SGMII2_DIGITAL_CONTROL1000X3_RESERVED_6_MASK               0x0040
#define SGMII2_DIGITAL_CONTROL1000X3_RESERVED_6_ALIGN              0
#define SGMII2_DIGITAL_CONTROL1000X3_RESERVED_6_BITS               1
#define SGMII2_DIGITAL_CONTROL1000X3_RESERVED_6_SHIFT              6

/* SGMII2_Digital :: Control1000X3 :: reserved_5 [05:05] */
#define SGMII2_DIGITAL_CONTROL1000X3_RESERVED_5_MASK               0x0020
#define SGMII2_DIGITAL_CONTROL1000X3_RESERVED_5_ALIGN              0
#define SGMII2_DIGITAL_CONTROL1000X3_RESERVED_5_BITS               1
#define SGMII2_DIGITAL_CONTROL1000X3_RESERVED_5_SHIFT              5

/* SGMII2_Digital :: Control1000X3 :: early_preamble_rx [04:04] */
#define Wr_SGMII2_Digital_Control1000X3_early_preamble_rx(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x10,4,x)
#define Rd_SGMII2_Digital_Control1000X3_early_preamble_rx(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x10,4)
#define SGMII2_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_MASK        0x0010
#define SGMII2_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_ALIGN       0
#define SGMII2_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_BITS        1
#define SGMII2_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_RX_SHIFT       4

/* SGMII2_Digital :: Control1000X3 :: early_preamble_tx [03:03] */
#define Wr_SGMII2_Digital_Control1000X3_early_preamble_tx(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x8,3,x)
#define Rd_SGMII2_Digital_Control1000X3_early_preamble_tx(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x8,3)
#define SGMII2_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_MASK        0x0008
#define SGMII2_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_ALIGN       0
#define SGMII2_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_BITS        1
#define SGMII2_DIGITAL_CONTROL1000X3_EARLY_PREAMBLE_TX_SHIFT       3

/* SGMII2_Digital :: Control1000X3 :: fifo_elasicity_tx [02:01] */
#define Wr_SGMII2_Digital_Control1000X3_fifo_elasicity_tx(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x6,1,x)
#define Rd_SGMII2_Digital_Control1000X3_fifo_elasicity_tx(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x6,1)
#define SGMII2_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_MASK        0x0006
#define SGMII2_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_ALIGN       0
#define SGMII2_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_BITS        2
#define SGMII2_DIGITAL_CONTROL1000X3_FIFO_ELASICITY_TX_SHIFT       1

/* SGMII2_Digital :: Control1000X3 :: tx_fifo_rst [00:00] */
#define Wr_SGMII2_Digital_Control1000X3_tx_fifo_rst(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x1,0,x)
#define Rd_SGMII2_Digital_Control1000X3_tx_fifo_rst(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X3,0x1,0)
#define SGMII2_DIGITAL_CONTROL1000X3_TX_FIFO_RST_MASK              0x0001
#define SGMII2_DIGITAL_CONTROL1000X3_TX_FIFO_RST_ALIGN             0
#define SGMII2_DIGITAL_CONTROL1000X3_TX_FIFO_RST_BITS              1
#define SGMII2_DIGITAL_CONTROL1000X3_TX_FIFO_RST_SHIFT             0


/****************************************************************************
 * SGMII2_Digital :: Control1000X4
 ***************************************************************************/
/* SGMII2_Digital :: Control1000X4 :: reserved0 [15:14] */
#define SGMII2_DIGITAL_CONTROL1000X4_RESERVED0_MASK                0xc000
#define SGMII2_DIGITAL_CONTROL1000X4_RESERVED0_ALIGN               0
#define SGMII2_DIGITAL_CONTROL1000X4_RESERVED0_BITS                2
#define SGMII2_DIGITAL_CONTROL1000X4_RESERVED0_SHIFT               14

/* SGMII2_Digital :: Control1000X4 :: disable_resolution_err_restart [13:13] */
#define Wr_SGMII2_Digital_Control1000X4_disable_resolution_err_restart(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x2000,13,x)
#define Rd_SGMII2_Digital_Control1000X4_disable_resolution_err_restart(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x2000,13)
#define SGMII2_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_MASK 0x2000
#define SGMII2_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_BITS 1
#define SGMII2_DIGITAL_CONTROL1000X4_DISABLE_RESOLUTION_ERR_RESTART_SHIFT 13

/* SGMII2_Digital :: Control1000X4 :: enable_last_resolution_err [12:12] */
#define Wr_SGMII2_Digital_Control1000X4_enable_last_resolution_err(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x1000,12,x)
#define Rd_SGMII2_Digital_Control1000X4_enable_last_resolution_err(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x1000,12)
#define SGMII2_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_MASK 0x1000
#define SGMII2_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_ALIGN 0
#define SGMII2_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_BITS 1
#define SGMII2_DIGITAL_CONTROL1000X4_ENABLE_LAST_RESOLUTION_ERR_SHIFT 12

/* SGMII2_Digital :: Control1000X4 :: tx_config_reg_sel [11:11] */
#define Wr_SGMII2_Digital_Control1000X4_tx_config_reg_sel(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x800,11,x)
#define Rd_SGMII2_Digital_Control1000X4_tx_config_reg_sel(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x800,11)
#define SGMII2_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_MASK        0x0800
#define SGMII2_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_ALIGN       0
#define SGMII2_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_BITS        1
#define SGMII2_DIGITAL_CONTROL1000X4_TX_CONFIG_REG_SEL_SHIFT       11

/* SGMII2_Digital :: Control1000X4 :: zero_rxdgmii [10:10] */
#define Wr_SGMII2_Digital_Control1000X4_zero_rxdgmii(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x400,10,x)
#define Rd_SGMII2_Digital_Control1000X4_zero_rxdgmii(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x400,10)
#define SGMII2_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_MASK             0x0400
#define SGMII2_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_ALIGN            0
#define SGMII2_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_BITS             1
#define SGMII2_DIGITAL_CONTROL1000X4_ZERO_RXDGMII_SHIFT            10

/* SGMII2_Digital :: Control1000X4 :: clear_linkdown [09:09] */
#define Wr_SGMII2_Digital_Control1000X4_clear_linkdown(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x200,9,x)
#define Rd_SGMII2_Digital_Control1000X4_clear_linkdown(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x200,9)
#define SGMII2_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_MASK           0x0200
#define SGMII2_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_ALIGN          0
#define SGMII2_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_BITS           1
#define SGMII2_DIGITAL_CONTROL1000X4_CLEAR_LINKDOWN_SHIFT          9

/* SGMII2_Digital :: Control1000X4 :: latch_linkdown_enable [08:08] */
#define Wr_SGMII2_Digital_Control1000X4_latch_linkdown_enable(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x100,8,x)
#define Rd_SGMII2_Digital_Control1000X4_latch_linkdown_enable(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x100,8)
#define SGMII2_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_MASK    0x0100
#define SGMII2_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_ALIGN   0
#define SGMII2_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_BITS    1
#define SGMII2_DIGITAL_CONTROL1000X4_LATCH_LINKDOWN_ENABLE_SHIFT   8

/* SGMII2_Digital :: Control1000X4 :: link_force [07:07] */
#define Wr_SGMII2_Digital_Control1000X4_link_force(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x80,7,x)
#define Rd_SGMII2_Digital_Control1000X4_link_force(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x80,7)
#define SGMII2_DIGITAL_CONTROL1000X4_LINK_FORCE_MASK               0x0080
#define SGMII2_DIGITAL_CONTROL1000X4_LINK_FORCE_ALIGN              0
#define SGMII2_DIGITAL_CONTROL1000X4_LINK_FORCE_BITS               1
#define SGMII2_DIGITAL_CONTROL1000X4_LINK_FORCE_SHIFT              7

/* SGMII2_Digital :: Control1000X4 :: reserved1 [06:03] */
#define SGMII2_DIGITAL_CONTROL1000X4_RESERVED1_MASK                0x0078
#define SGMII2_DIGITAL_CONTROL1000X4_RESERVED1_ALIGN               0
#define SGMII2_DIGITAL_CONTROL1000X4_RESERVED1_BITS                4
#define SGMII2_DIGITAL_CONTROL1000X4_RESERVED1_SHIFT               3

/* SGMII2_Digital :: Control1000X4 :: MiscRxStatus_sel [02:00] */
#define Wr_SGMII2_Digital_Control1000X4_MiscRxStatus_sel(x) WriteRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x7,0,x)
#define Rd_SGMII2_Digital_Control1000X4_MiscRxStatus_sel(x) ReadRegBits16(SGMII2_DIGITAL_CONTROL1000X4,0x7,0)
#define SGMII2_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_MASK         0x0007
#define SGMII2_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_ALIGN        0
#define SGMII2_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_BITS         3
#define SGMII2_DIGITAL_CONTROL1000X4_MISCRXSTATUS_SEL_SHIFT        0


/****************************************************************************
 * SGMII2_Digital :: Status1000X1
 ***************************************************************************/
/* SGMII2_Digital :: Status1000X1 :: txfifo_err_detected [15:15] */
#define Wr_SGMII2_Digital_Status1000X1_txfifo_err_detected(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x8000,15,x)
#define Rd_SGMII2_Digital_Status1000X1_txfifo_err_detected(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x8000,15)
#define SGMII2_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_MASK       0x8000
#define SGMII2_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_ALIGN      0
#define SGMII2_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_BITS       1
#define SGMII2_DIGITAL_STATUS1000X1_TXFIFO_ERR_DETECTED_SHIFT      15

/* SGMII2_Digital :: Status1000X1 :: rxfifo_err_detected [14:14] */
#define Wr_SGMII2_Digital_Status1000X1_rxfifo_err_detected(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x4000,14,x)
#define Rd_SGMII2_Digital_Status1000X1_rxfifo_err_detected(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x4000,14)
#define SGMII2_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_MASK       0x4000
#define SGMII2_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_ALIGN      0
#define SGMII2_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_BITS       1
#define SGMII2_DIGITAL_STATUS1000X1_RXFIFO_ERR_DETECTED_SHIFT      14

/* SGMII2_Digital :: Status1000X1 :: false_carrier_detected [13:13] */
#define Wr_SGMII2_Digital_Status1000X1_false_carrier_detected(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x2000,13,x)
#define Rd_SGMII2_Digital_Status1000X1_false_carrier_detected(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x2000,13)
#define SGMII2_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_MASK    0x2000
#define SGMII2_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_ALIGN   0
#define SGMII2_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_BITS    1
#define SGMII2_DIGITAL_STATUS1000X1_FALSE_CARRIER_DETECTED_SHIFT   13

/* SGMII2_Digital :: Status1000X1 :: crc_err_detected [12:12] */
#define Wr_SGMII2_Digital_Status1000X1_crc_err_detected(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x1000,12,x)
#define Rd_SGMII2_Digital_Status1000X1_crc_err_detected(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x1000,12)
#define SGMII2_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_MASK          0x1000
#define SGMII2_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_ALIGN         0
#define SGMII2_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_BITS          1
#define SGMII2_DIGITAL_STATUS1000X1_CRC_ERR_DETECTED_SHIFT         12

/* SGMII2_Digital :: Status1000X1 :: tx_err_detected [11:11] */
#define Wr_SGMII2_Digital_Status1000X1_tx_err_detected(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x800,11,x)
#define Rd_SGMII2_Digital_Status1000X1_tx_err_detected(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x800,11)
#define SGMII2_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_MASK           0x0800
#define SGMII2_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_ALIGN          0
#define SGMII2_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_BITS           1
#define SGMII2_DIGITAL_STATUS1000X1_TX_ERR_DETECTED_SHIFT          11

/* SGMII2_Digital :: Status1000X1 :: rx_err_detected [10:10] */
#define Wr_SGMII2_Digital_Status1000X1_rx_err_detected(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x400,10,x)
#define Rd_SGMII2_Digital_Status1000X1_rx_err_detected(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x400,10)
#define SGMII2_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_MASK           0x0400
#define SGMII2_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_ALIGN          0
#define SGMII2_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_BITS           1
#define SGMII2_DIGITAL_STATUS1000X1_RX_ERR_DETECTED_SHIFT          10

/* SGMII2_Digital :: Status1000X1 :: carrier_extend_err_detected [09:09] */
#define Wr_SGMII2_Digital_Status1000X1_carrier_extend_err_detected(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x200,9,x)
#define Rd_SGMII2_Digital_Status1000X1_carrier_extend_err_detected(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x200,9)
#define SGMII2_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_MASK 0x0200
#define SGMII2_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_ALIGN 0
#define SGMII2_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_BITS 1
#define SGMII2_DIGITAL_STATUS1000X1_CARRIER_EXTEND_ERR_DETECTED_SHIFT 9

/* SGMII2_Digital :: Status1000X1 :: early_end_extension_detected [08:08] */
#define Wr_SGMII2_Digital_Status1000X1_early_end_extension_detected(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x100,8,x)
#define Rd_SGMII2_Digital_Status1000X1_early_end_extension_detected(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x100,8)
#define SGMII2_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_MASK 0x0100
#define SGMII2_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_ALIGN 0
#define SGMII2_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_BITS 1
#define SGMII2_DIGITAL_STATUS1000X1_EARLY_END_EXTENSION_DETECTED_SHIFT 8

/* SGMII2_Digital :: Status1000X1 :: link_status_change [07:07] */
#define Wr_SGMII2_Digital_Status1000X1_link_status_change(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x80,7,x)
#define Rd_SGMII2_Digital_Status1000X1_link_status_change(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x80,7)
#define SGMII2_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_MASK        0x0080
#define SGMII2_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_ALIGN       0
#define SGMII2_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_BITS        1
#define SGMII2_DIGITAL_STATUS1000X1_LINK_STATUS_CHANGE_SHIFT       7

/* SGMII2_Digital :: Status1000X1 :: pause_resolution_rxside [06:06] */
#define Wr_SGMII2_Digital_Status1000X1_pause_resolution_rxside(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x40,6,x)
#define Rd_SGMII2_Digital_Status1000X1_pause_resolution_rxside(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x40,6)
#define SGMII2_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_MASK   0x0040
#define SGMII2_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_ALIGN  0
#define SGMII2_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_BITS   1
#define SGMII2_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_RXSIDE_SHIFT  6

/* SGMII2_Digital :: Status1000X1 :: pause_resolution_txside [05:05] */
#define Wr_SGMII2_Digital_Status1000X1_pause_resolution_txside(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x20,5,x)
#define Rd_SGMII2_Digital_Status1000X1_pause_resolution_txside(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x20,5)
#define SGMII2_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_MASK   0x0020
#define SGMII2_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_ALIGN  0
#define SGMII2_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_BITS   1
#define SGMII2_DIGITAL_STATUS1000X1_PAUSE_RESOLUTION_TXSIDE_SHIFT  5

/* SGMII2_Digital :: Status1000X1 :: speed_status [04:03] */
#define Wr_SGMII2_Digital_Status1000X1_speed_status(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x18,3,x)
#define Rd_SGMII2_Digital_Status1000X1_speed_status(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x18,3)
#define SGMII2_DIGITAL_STATUS1000X1_SPEED_STATUS_MASK              0x0018
#define SGMII2_DIGITAL_STATUS1000X1_SPEED_STATUS_ALIGN             0
#define SGMII2_DIGITAL_STATUS1000X1_SPEED_STATUS_BITS              2
#define SGMII2_DIGITAL_STATUS1000X1_SPEED_STATUS_SHIFT             3

/* SGMII2_Digital :: Status1000X1 :: duplex_status [02:02] */
#define Wr_SGMII2_Digital_Status1000X1_duplex_status(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x4,2,x)
#define Rd_SGMII2_Digital_Status1000X1_duplex_status(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x4,2)
#define SGMII2_DIGITAL_STATUS1000X1_DUPLEX_STATUS_MASK             0x0004
#define SGMII2_DIGITAL_STATUS1000X1_DUPLEX_STATUS_ALIGN            0
#define SGMII2_DIGITAL_STATUS1000X1_DUPLEX_STATUS_BITS             1
#define SGMII2_DIGITAL_STATUS1000X1_DUPLEX_STATUS_SHIFT            2

/* SGMII2_Digital :: Status1000X1 :: link_status [01:01] */
#define Wr_SGMII2_Digital_Status1000X1_link_status(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x2,1,x)
#define Rd_SGMII2_Digital_Status1000X1_link_status(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x2,1)
#define SGMII2_DIGITAL_STATUS1000X1_LINK_STATUS_MASK               0x0002
#define SGMII2_DIGITAL_STATUS1000X1_LINK_STATUS_ALIGN              0
#define SGMII2_DIGITAL_STATUS1000X1_LINK_STATUS_BITS               1
#define SGMII2_DIGITAL_STATUS1000X1_LINK_STATUS_SHIFT              1

/* SGMII2_Digital :: Status1000X1 :: sgmii_mode [00:00] */
#define Wr_SGMII2_Digital_Status1000X1_sgmii_mode(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x1,0,x)
#define Rd_SGMII2_Digital_Status1000X1_sgmii_mode(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X1,0x1,0)
#define SGMII2_DIGITAL_STATUS1000X1_SGMII_MODE_MASK                0x0001
#define SGMII2_DIGITAL_STATUS1000X1_SGMII_MODE_ALIGN               0
#define SGMII2_DIGITAL_STATUS1000X1_SGMII_MODE_BITS                1
#define SGMII2_DIGITAL_STATUS1000X1_SGMII_MODE_SHIFT               0


/****************************************************************************
 * SGMII2_Digital :: Status1000X2
 ***************************************************************************/
/* SGMII2_Digital :: Status1000X2 :: sgmii_mode_change [15:15] */
#define Wr_SGMII2_Digital_Status1000X2_sgmii_mode_change(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x8000,15,x)
#define Rd_SGMII2_Digital_Status1000X2_sgmii_mode_change(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x8000,15)
#define SGMII2_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_MASK         0x8000
#define SGMII2_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_ALIGN        0
#define SGMII2_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_BITS         1
#define SGMII2_DIGITAL_STATUS1000X2_SGMII_MODE_CHANGE_SHIFT        15

/* SGMII2_Digital :: Status1000X2 :: consistency_mismatch [14:14] */
#define Wr_SGMII2_Digital_Status1000X2_consistency_mismatch(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x4000,14,x)
#define Rd_SGMII2_Digital_Status1000X2_consistency_mismatch(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x4000,14)
#define SGMII2_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_MASK      0x4000
#define SGMII2_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_ALIGN     0
#define SGMII2_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_BITS      1
#define SGMII2_DIGITAL_STATUS1000X2_CONSISTENCY_MISMATCH_SHIFT     14

/* SGMII2_Digital :: Status1000X2 :: autoneg_resolution_err [13:13] */
#define Wr_SGMII2_Digital_Status1000X2_autoneg_resolution_err(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x2000,13,x)
#define Rd_SGMII2_Digital_Status1000X2_autoneg_resolution_err(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x2000,13)
#define SGMII2_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_MASK    0x2000
#define SGMII2_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_ALIGN   0
#define SGMII2_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_BITS    1
#define SGMII2_DIGITAL_STATUS1000X2_AUTONEG_RESOLUTION_ERR_SHIFT   13

/* SGMII2_Digital :: Status1000X2 :: sgmii_selector_mismatch [12:12] */
#define Wr_SGMII2_Digital_Status1000X2_sgmii_selector_mismatch(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x1000,12,x)
#define Rd_SGMII2_Digital_Status1000X2_sgmii_selector_mismatch(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x1000,12)
#define SGMII2_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_MASK   0x1000
#define SGMII2_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_ALIGN  0
#define SGMII2_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_BITS   1
#define SGMII2_DIGITAL_STATUS1000X2_SGMII_SELECTOR_MISMATCH_SHIFT  12

/* SGMII2_Digital :: Status1000X2 :: sync_status_fail [11:11] */
#define Wr_SGMII2_Digital_Status1000X2_sync_status_fail(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x800,11,x)
#define Rd_SGMII2_Digital_Status1000X2_sync_status_fail(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x800,11)
#define SGMII2_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_MASK          0x0800
#define SGMII2_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_ALIGN         0
#define SGMII2_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_BITS          1
#define SGMII2_DIGITAL_STATUS1000X2_SYNC_STATUS_FAIL_SHIFT         11

/* SGMII2_Digital :: Status1000X2 :: sync_status_ok [10:10] */
#define Wr_SGMII2_Digital_Status1000X2_sync_status_ok(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x400,10,x)
#define Rd_SGMII2_Digital_Status1000X2_sync_status_ok(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x400,10)
#define SGMII2_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_MASK            0x0400
#define SGMII2_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_ALIGN           0
#define SGMII2_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_BITS            1
#define SGMII2_DIGITAL_STATUS1000X2_SYNC_STATUS_OK_SHIFT           10

/* SGMII2_Digital :: Status1000X2 :: rudi_c [09:09] */
#define Wr_SGMII2_Digital_Status1000X2_rudi_c(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x200,9,x)
#define Rd_SGMII2_Digital_Status1000X2_rudi_c(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x200,9)
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_C_MASK                    0x0200
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_C_ALIGN                   0
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_C_BITS                    1
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_C_SHIFT                   9

/* SGMII2_Digital :: Status1000X2 :: rudi_I [08:08] */
#define Wr_SGMII2_Digital_Status1000X2_rudi_I(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x100,8,x)
#define Rd_SGMII2_Digital_Status1000X2_rudi_I(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x100,8)
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_I_MASK                    0x0100
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_I_ALIGN                   0
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_I_BITS                    1
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_I_SHIFT                   8

/* SGMII2_Digital :: Status1000X2 :: rudi_invalid [07:07] */
#define Wr_SGMII2_Digital_Status1000X2_rudi_invalid(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x80,7,x)
#define Rd_SGMII2_Digital_Status1000X2_rudi_invalid(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x80,7)
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_INVALID_MASK              0x0080
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_INVALID_ALIGN             0
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_INVALID_BITS              1
#define SGMII2_DIGITAL_STATUS1000X2_RUDI_INVALID_SHIFT             7

/* SGMII2_Digital :: Status1000X2 :: linkDown_syncLoss [06:06] */
#define Wr_SGMII2_Digital_Status1000X2_linkDown_syncLoss(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x40,6,x)
#define Rd_SGMII2_Digital_Status1000X2_linkDown_syncLoss(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x40,6)
#define SGMII2_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_MASK         0x0040
#define SGMII2_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_ALIGN        0
#define SGMII2_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_BITS         1
#define SGMII2_DIGITAL_STATUS1000X2_LINKDOWN_SYNCLOSS_SHIFT        6

/* SGMII2_Digital :: Status1000X2 :: idle_detect_state [05:05] */
#define Wr_SGMII2_Digital_Status1000X2_idle_detect_state(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x20,5,x)
#define Rd_SGMII2_Digital_Status1000X2_idle_detect_state(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x20,5)
#define SGMII2_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_MASK         0x0020
#define SGMII2_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_ALIGN        0
#define SGMII2_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_BITS         1
#define SGMII2_DIGITAL_STATUS1000X2_IDLE_DETECT_STATE_SHIFT        5

/* SGMII2_Digital :: Status1000X2 :: complete_acknowledge_state [04:04] */
#define Wr_SGMII2_Digital_Status1000X2_complete_acknowledge_state(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x10,4,x)
#define Rd_SGMII2_Digital_Status1000X2_complete_acknowledge_state(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x10,4)
#define SGMII2_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_MASK 0x0010
#define SGMII2_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_ALIGN 0
#define SGMII2_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_BITS 1
#define SGMII2_DIGITAL_STATUS1000X2_COMPLETE_ACKNOWLEDGE_STATE_SHIFT 4

/* SGMII2_Digital :: Status1000X2 :: acknowledge_detect_state [03:03] */
#define Wr_SGMII2_Digital_Status1000X2_acknowledge_detect_state(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x8,3,x)
#define Rd_SGMII2_Digital_Status1000X2_acknowledge_detect_state(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x8,3)
#define SGMII2_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_MASK  0x0008
#define SGMII2_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_ALIGN 0
#define SGMII2_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_BITS  1
#define SGMII2_DIGITAL_STATUS1000X2_ACKNOWLEDGE_DETECT_STATE_SHIFT 3

/* SGMII2_Digital :: Status1000X2 :: ability_detect_state [02:02] */
#define Wr_SGMII2_Digital_Status1000X2_ability_detect_state(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x4,2,x)
#define Rd_SGMII2_Digital_Status1000X2_ability_detect_state(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x4,2)
#define SGMII2_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_MASK      0x0004
#define SGMII2_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_ALIGN     0
#define SGMII2_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_BITS      1
#define SGMII2_DIGITAL_STATUS1000X2_ABILITY_DETECT_STATE_SHIFT     2

/* union - case anError [01:01] */
/* SGMII2_Digital :: Status1000X2 :: an_error_state [01:01] */
#define Wr_SGMII2_Digital_Status1000X2_anError_an_error_state(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2_ANERROR,0x2,1,x)
#define Rd_SGMII2_Digital_Status1000X2_anError_an_error_state(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2_ANERROR,0x2,1)
#define SGMII2_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_MASK    0x0002
#define SGMII2_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_ALIGN   0
#define SGMII2_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_BITS    1
#define SGMII2_DIGITAL_STATUS1000X2_ANERROR_AN_ERROR_STATE_SHIFT   1


/* union - case anDisableLink [01:01] */
/* SGMII2_Digital :: Status1000X2 :: an_disable_link_ok_state [01:01] */
#define Wr_SGMII2_Digital_Status1000X2_anDisableLink_an_disable_link_ok_state(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2_ANDISABLELINK,0x2,1,x)
#define Rd_SGMII2_Digital_Status1000X2_anDisableLink_an_disable_link_ok_state(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2_ANDISABLELINK,0x2,1)
#define SGMII2_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_MASK 0x0002
#define SGMII2_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_ALIGN 0
#define SGMII2_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_BITS 1
#define SGMII2_DIGITAL_STATUS1000X2_ANDISABLELINK_AN_DISABLE_LINK_OK_STATE_SHIFT 1


/* SGMII2_Digital :: Status1000X2 :: an_enable_state [00:00] */
#define Wr_SGMII2_Digital_Status1000X2_an_enable_state(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x1,0,x)
#define Rd_SGMII2_Digital_Status1000X2_an_enable_state(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X2,0x1,0)
#define SGMII2_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_MASK           0x0001
#define SGMII2_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_ALIGN          0
#define SGMII2_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_BITS           1
#define SGMII2_DIGITAL_STATUS1000X2_AN_ENABLE_STATE_SHIFT          0


/****************************************************************************
 * SGMII2_Digital :: Status1000X3
 ***************************************************************************/
/* SGMII2_Digital :: Status1000X3 :: reserved0 [15:13] */
#define SGMII2_DIGITAL_STATUS1000X3_RESERVED0_MASK                 0xe000
#define SGMII2_DIGITAL_STATUS1000X3_RESERVED0_ALIGN                0
#define SGMII2_DIGITAL_STATUS1000X3_RESERVED0_BITS                 3
#define SGMII2_DIGITAL_STATUS1000X3_RESERVED0_SHIFT                13

/* SGMII2_Digital :: Status1000X3 :: pd_park_an [12:12] */
#define Wr_SGMII2_Digital_Status1000X3_pd_park_an(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x1000,12,x)
#define Rd_SGMII2_Digital_Status1000X3_pd_park_an(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x1000,12)
#define SGMII2_DIGITAL_STATUS1000X3_PD_PARK_AN_MASK                0x1000
#define SGMII2_DIGITAL_STATUS1000X3_PD_PARK_AN_ALIGN               0
#define SGMII2_DIGITAL_STATUS1000X3_PD_PARK_AN_BITS                1
#define SGMII2_DIGITAL_STATUS1000X3_PD_PARK_AN_SHIFT               12

/* SGMII2_Digital :: Status1000X3 :: remotePhy_autosel [11:11] */
#define Wr_SGMII2_Digital_Status1000X3_remotePhy_autosel(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x800,11,x)
#define Rd_SGMII2_Digital_Status1000X3_remotePhy_autosel(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x800,11)
#define SGMII2_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_MASK         0x0800
#define SGMII2_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_ALIGN        0
#define SGMII2_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_BITS         1
#define SGMII2_DIGITAL_STATUS1000X3_REMOTEPHY_AUTOSEL_SHIFT        11

/* SGMII2_Digital :: Status1000X3 :: latch_linkdown [10:10] */
#define Wr_SGMII2_Digital_Status1000X3_latch_linkdown(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x400,10,x)
#define Rd_SGMII2_Digital_Status1000X3_latch_linkdown(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x400,10)
#define SGMII2_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_MASK            0x0400
#define SGMII2_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_ALIGN           0
#define SGMII2_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_BITS            1
#define SGMII2_DIGITAL_STATUS1000X3_LATCH_LINKDOWN_SHIFT           10

/* SGMII2_Digital :: Status1000X3 :: sd_filter [09:09] */
#define Wr_SGMII2_Digital_Status1000X3_sd_filter(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x200,9,x)
#define Rd_SGMII2_Digital_Status1000X3_sd_filter(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x200,9)
#define SGMII2_DIGITAL_STATUS1000X3_SD_FILTER_MASK                 0x0200
#define SGMII2_DIGITAL_STATUS1000X3_SD_FILTER_ALIGN                0
#define SGMII2_DIGITAL_STATUS1000X3_SD_FILTER_BITS                 1
#define SGMII2_DIGITAL_STATUS1000X3_SD_FILTER_SHIFT                9

/* SGMII2_Digital :: Status1000X3 :: sd_mux [08:08] */
#define Wr_SGMII2_Digital_Status1000X3_sd_mux(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x100,8,x)
#define Rd_SGMII2_Digital_Status1000X3_sd_mux(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x100,8)
#define SGMII2_DIGITAL_STATUS1000X3_SD_MUX_MASK                    0x0100
#define SGMII2_DIGITAL_STATUS1000X3_SD_MUX_ALIGN                   0
#define SGMII2_DIGITAL_STATUS1000X3_SD_MUX_BITS                    1
#define SGMII2_DIGITAL_STATUS1000X3_SD_MUX_SHIFT                   8

/* SGMII2_Digital :: Status1000X3 :: sd_filter_chg [07:07] */
#define Wr_SGMII2_Digital_Status1000X3_sd_filter_chg(x) WriteRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x80,7,x)
#define Rd_SGMII2_Digital_Status1000X3_sd_filter_chg(x) ReadRegBits16(SGMII2_DIGITAL_STATUS1000X3,0x80,7)
#define SGMII2_DIGITAL_STATUS1000X3_SD_FILTER_CHG_MASK             0x0080
#define SGMII2_DIGITAL_STATUS1000X3_SD_FILTER_CHG_ALIGN            0
#define SGMII2_DIGITAL_STATUS1000X3_SD_FILTER_CHG_BITS             1
#define SGMII2_DIGITAL_STATUS1000X3_SD_FILTER_CHG_SHIFT            7

/* SGMII2_Digital :: Status1000X3 :: reserved1 [06:00] */
#define SGMII2_DIGITAL_STATUS1000X3_RESERVED1_MASK                 0x007f
#define SGMII2_DIGITAL_STATUS1000X3_RESERVED1_ALIGN                0
#define SGMII2_DIGITAL_STATUS1000X3_RESERVED1_BITS                 7
#define SGMII2_DIGITAL_STATUS1000X3_RESERVED1_SHIFT                0


/****************************************************************************
 * SGMII2_Digital :: BadCodeGroup
 ***************************************************************************/
/* SGMII2_Digital :: BadCodeGroup :: badCodeGroups [15:08] */
#define Wr_SGMII2_Digital_BadCodeGroup_badCodeGroups(x) WriteRegBits16(SGMII2_DIGITAL_BADCODEGROUP,0xff00,8,x)
#define Rd_SGMII2_Digital_BadCodeGroup_badCodeGroups(x) ReadRegBits16(SGMII2_DIGITAL_BADCODEGROUP,0xff00,8)
#define SGMII2_DIGITAL_BADCODEGROUP_BADCODEGROUPS_MASK             0xff00
#define SGMII2_DIGITAL_BADCODEGROUP_BADCODEGROUPS_ALIGN            0
#define SGMII2_DIGITAL_BADCODEGROUP_BADCODEGROUPS_BITS             8
#define SGMII2_DIGITAL_BADCODEGROUP_BADCODEGROUPS_SHIFT            8

/* SGMII2_Digital :: BadCodeGroup :: reserved0 [07:00] */
#define SGMII2_DIGITAL_BADCODEGROUP_RESERVED0_MASK                 0x00ff
#define SGMII2_DIGITAL_BADCODEGROUP_RESERVED0_ALIGN                0
#define SGMII2_DIGITAL_BADCODEGROUP_RESERVED0_BITS                 8
#define SGMII2_DIGITAL_BADCODEGROUP_RESERVED0_SHIFT                0


/****************************************************************************
 * SGMII2_Digital :: Misc1
 ***************************************************************************/
/* SGMII2_Digital :: Misc1 :: refclk_sel [15:13] */
#define Wr_SGMII2_Digital_Misc1_refclk_sel(x) WriteRegBits16(SGMII2_DIGITAL_MISC1,0xe000,13,x)
#define Rd_SGMII2_Digital_Misc1_refclk_sel(x) ReadRegBits16(SGMII2_DIGITAL_MISC1,0xe000,13)
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_MASK                       0xe000
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_ALIGN                      0
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_BITS                       3
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_SHIFT                      13
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_clk_25MHz                  0
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_clk_100MHz                 1
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_clk_125MHz                 2
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_clk_156p25MHz              3
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_clk_187p5MHz               4
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_clk_161p25Mhz              5
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_clk_50Mhz                  6
#define SGMII2_DIGITAL_MISC1_REFCLK_SEL_clk_106p25Mhz              7

/* SGMII2_Digital :: Misc1 :: reserved0 [12:07] */
#define SGMII2_DIGITAL_MISC1_RESERVED0_MASK                        0x1f80
#define SGMII2_DIGITAL_MISC1_RESERVED0_ALIGN                       0
#define SGMII2_DIGITAL_MISC1_RESERVED0_BITS                        6
#define SGMII2_DIGITAL_MISC1_RESERVED0_SHIFT                       7

/* SGMII2_Digital :: Misc1 :: tx_underrun_1000_dis [06:06] */
#define Wr_SGMII2_Digital_Misc1_tx_underrun_1000_dis(x) WriteRegBits16(SGMII2_DIGITAL_MISC1,0x40,6,x)
#define Rd_SGMII2_Digital_Misc1_tx_underrun_1000_dis(x) ReadRegBits16(SGMII2_DIGITAL_MISC1,0x40,6)
#define SGMII2_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_MASK             0x0040
#define SGMII2_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_ALIGN            0
#define SGMII2_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_BITS             1
#define SGMII2_DIGITAL_MISC1_TX_UNDERRUN_1000_DIS_SHIFT            6

/* SGMII2_Digital :: Misc1 :: force_ln_mode [05:05] */
#define Wr_SGMII2_Digital_Misc1_force_ln_mode(x) WriteRegBits16(SGMII2_DIGITAL_MISC1,0x20,5,x)
#define Rd_SGMII2_Digital_Misc1_force_ln_mode(x) ReadRegBits16(SGMII2_DIGITAL_MISC1,0x20,5)
#define SGMII2_DIGITAL_MISC1_FORCE_LN_MODE_MASK                    0x0020
#define SGMII2_DIGITAL_MISC1_FORCE_LN_MODE_ALIGN                   0
#define SGMII2_DIGITAL_MISC1_FORCE_LN_MODE_BITS                    1
#define SGMII2_DIGITAL_MISC1_FORCE_LN_MODE_SHIFT                   5

/* SGMII2_Digital :: Misc1 :: force_speed [04:00] */
#define Wr_SGMII2_Digital_Misc1_force_speed(x) WriteRegBits16(SGMII2_DIGITAL_MISC1,0x1f,0,x)
#define Rd_SGMII2_Digital_Misc1_force_speed(x) ReadRegBits16(SGMII2_DIGITAL_MISC1,0x1f,0)
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_MASK                      0x001f
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_ALIGN                     0
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_BITS                      5
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_SHIFT                     0
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_2500BRCM_X1            16
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X4            17
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_6000BRCM_X4            18
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_10GHiGig_X4            19
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_10GBASE_CX4            20
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_12GHiGig_X4            21
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_12p5GHiGig_X4          22
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_13GHiGig_X4            23
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_15GHiGig_X4            24
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_16GHiGig_X4            25
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_5000BRCM_X1            26
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_6363BRCM_X1            27
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_20GHiGig_X4            28
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_21GHiGig_X4            29
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_25p45GHiGig_X4         30
#define SGMII2_DIGITAL_MISC1_FORCE_SPEED_dr_10G_HiG_DXGXS          31


/****************************************************************************
 * SGMII2_Digital :: Misc2
 ***************************************************************************/
/* SGMII2_Digital :: Misc2 :: rxckpl_sel_combo [15:15] */
#define Wr_SGMII2_Digital_Misc2_rxckpl_sel_combo(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x8000,15,x)
#define Rd_SGMII2_Digital_Misc2_rxckpl_sel_combo(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x8000,15)
#define SGMII2_DIGITAL_MISC2_RXCKPL_SEL_COMBO_MASK                 0x8000
#define SGMII2_DIGITAL_MISC2_RXCKPL_SEL_COMBO_ALIGN                0
#define SGMII2_DIGITAL_MISC2_RXCKPL_SEL_COMBO_BITS                 1
#define SGMII2_DIGITAL_MISC2_RXCKPL_SEL_COMBO_SHIFT                15

/* SGMII2_Digital :: Misc2 :: reserved_14_13 [14:13] */
#define SGMII2_DIGITAL_MISC2_RESERVED_14_13_MASK                   0x6000
#define SGMII2_DIGITAL_MISC2_RESERVED_14_13_ALIGN                  0
#define SGMII2_DIGITAL_MISC2_RESERVED_14_13_BITS                   2
#define SGMII2_DIGITAL_MISC2_RESERVED_14_13_SHIFT                  13

/* SGMII2_Digital :: Misc2 :: rlpbk_sw_force [12:12] */
#define Wr_SGMII2_Digital_Misc2_rlpbk_sw_force(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x1000,12,x)
#define Rd_SGMII2_Digital_Misc2_rlpbk_sw_force(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x1000,12)
#define SGMII2_DIGITAL_MISC2_RLPBK_SW_FORCE_MASK                   0x1000
#define SGMII2_DIGITAL_MISC2_RLPBK_SW_FORCE_ALIGN                  0
#define SGMII2_DIGITAL_MISC2_RLPBK_SW_FORCE_BITS                   1
#define SGMII2_DIGITAL_MISC2_RLPBK_SW_FORCE_SHIFT                  12

/* SGMII2_Digital :: Misc2 :: rlpbk_RxRst_en [11:11] */
#define Wr_SGMII2_Digital_Misc2_rlpbk_RxRst_en(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x800,11,x)
#define Rd_SGMII2_Digital_Misc2_rlpbk_RxRst_en(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x800,11)
#define SGMII2_DIGITAL_MISC2_RLPBK_RXRST_EN_MASK                   0x0800
#define SGMII2_DIGITAL_MISC2_RLPBK_RXRST_EN_ALIGN                  0
#define SGMII2_DIGITAL_MISC2_RLPBK_RXRST_EN_BITS                   1
#define SGMII2_DIGITAL_MISC2_RLPBK_RXRST_EN_SHIFT                  11

/* SGMII2_Digital :: Misc2 :: clkSigdet_bypass [10:10] */
#define Wr_SGMII2_Digital_Misc2_clkSigdet_bypass(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x400,10,x)
#define Rd_SGMII2_Digital_Misc2_clkSigdet_bypass(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x400,10)
#define SGMII2_DIGITAL_MISC2_CLKSIGDET_BYPASS_MASK                 0x0400
#define SGMII2_DIGITAL_MISC2_CLKSIGDET_BYPASS_ALIGN                0
#define SGMII2_DIGITAL_MISC2_CLKSIGDET_BYPASS_BITS                 1
#define SGMII2_DIGITAL_MISC2_CLKSIGDET_BYPASS_SHIFT                10

/* SGMII2_Digital :: Misc2 :: clk41_bypass [09:09] */
#define Wr_SGMII2_Digital_Misc2_clk41_bypass(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x200,9,x)
#define Rd_SGMII2_Digital_Misc2_clk41_bypass(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x200,9)
#define SGMII2_DIGITAL_MISC2_CLK41_BYPASS_MASK                     0x0200
#define SGMII2_DIGITAL_MISC2_CLK41_BYPASS_ALIGN                    0
#define SGMII2_DIGITAL_MISC2_CLK41_BYPASS_BITS                     1
#define SGMII2_DIGITAL_MISC2_CLK41_BYPASS_SHIFT                    9

/* SGMII2_Digital :: Misc2 :: miiGmiiDly_en [08:08] */
#define Wr_SGMII2_Digital_Misc2_miiGmiiDly_en(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x100,8,x)
#define Rd_SGMII2_Digital_Misc2_miiGmiiDly_en(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x100,8)
#define SGMII2_DIGITAL_MISC2_MIIGMIIDLY_EN_MASK                    0x0100
#define SGMII2_DIGITAL_MISC2_MIIGMIIDLY_EN_ALIGN                   0
#define SGMII2_DIGITAL_MISC2_MIIGMIIDLY_EN_BITS                    1
#define SGMII2_DIGITAL_MISC2_MIIGMIIDLY_EN_SHIFT                   8

/* SGMII2_Digital :: Misc2 :: miiGmiiMux_en [07:07] */
#define Wr_SGMII2_Digital_Misc2_miiGmiiMux_en(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x80,7,x)
#define Rd_SGMII2_Digital_Misc2_miiGmiiMux_en(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x80,7)
#define SGMII2_DIGITAL_MISC2_MIIGMIIMUX_EN_MASK                    0x0080
#define SGMII2_DIGITAL_MISC2_MIIGMIIMUX_EN_ALIGN                   0
#define SGMII2_DIGITAL_MISC2_MIIGMIIMUX_EN_BITS                    1
#define SGMII2_DIGITAL_MISC2_MIIGMIIMUX_EN_SHIFT                   7

/* SGMII2_Digital :: Misc2 :: reserved0 [06:06] */
#define SGMII2_DIGITAL_MISC2_RESERVED0_MASK                        0x0040
#define SGMII2_DIGITAL_MISC2_RESERVED0_ALIGN                       0
#define SGMII2_DIGITAL_MISC2_RESERVED0_BITS                        1
#define SGMII2_DIGITAL_MISC2_RESERVED0_SHIFT                       6

/* SGMII2_Digital :: Misc2 :: pma_pmd_forced_speed_enc_en [05:05] */
#define Wr_SGMII2_Digital_Misc2_pma_pmd_forced_speed_enc_en(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x20,5,x)
#define Rd_SGMII2_Digital_Misc2_pma_pmd_forced_speed_enc_en(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x20,5)
#define SGMII2_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_MASK      0x0020
#define SGMII2_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_ALIGN     0
#define SGMII2_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_BITS      1
#define SGMII2_DIGITAL_MISC2_PMA_PMD_FORCED_SPEED_ENC_EN_SHIFT     5

/* SGMII2_Digital :: Misc2 :: fifo_err_cya [04:04] */
#define Wr_SGMII2_Digital_Misc2_fifo_err_cya(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x10,4,x)
#define Rd_SGMII2_Digital_Misc2_fifo_err_cya(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x10,4)
#define SGMII2_DIGITAL_MISC2_FIFO_ERR_CYA_MASK                     0x0010
#define SGMII2_DIGITAL_MISC2_FIFO_ERR_CYA_ALIGN                    0
#define SGMII2_DIGITAL_MISC2_FIFO_ERR_CYA_BITS                     1
#define SGMII2_DIGITAL_MISC2_FIFO_ERR_CYA_SHIFT                    4

/* SGMII2_Digital :: Misc2 :: an_txdisablePhase [03:03] */
#define Wr_SGMII2_Digital_Misc2_an_txdisablePhase(x) WriteRegBits16(SGMII2_DIGITAL_MISC2,0x8,3,x)
#define Rd_SGMII2_Digital_Misc2_an_txdisablePhase(x) ReadRegBits16(SGMII2_DIGITAL_MISC2,0x8,3)
#define SGMII2_DIGITAL_MISC2_AN_TXDISABLEPHASE_MASK                0x0008
#define SGMII2_DIGITAL_MISC2_AN_TXDISABLEPHASE_ALIGN               0
#define SGMII2_DIGITAL_MISC2_AN_TXDISABLEPHASE_BITS                1
#define SGMII2_DIGITAL_MISC2_AN_TXDISABLEPHASE_SHIFT               3

/* SGMII2_Digital :: Misc2 :: reserved1 [02:00] */
#define SGMII2_DIGITAL_MISC2_RESERVED1_MASK                        0x0007
#define SGMII2_DIGITAL_MISC2_RESERVED1_ALIGN                       0
#define SGMII2_DIGITAL_MISC2_RESERVED1_BITS                        3
#define SGMII2_DIGITAL_MISC2_RESERVED1_SHIFT                       0


/****************************************************************************
 * SGMII2_Digital :: PatGenCtrl
 ***************************************************************************/
/* SGMII2_Digital :: PatGenCtrl :: patgen_lpi_en [15:15] */
#define Wr_SGMII2_Digital_PatGenCtrl_patgen_lpi_en(x) WriteRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x8000,15,x)
#define Rd_SGMII2_Digital_PatGenCtrl_patgen_lpi_en(x) ReadRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x8000,15)
#define SGMII2_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_MASK               0x8000
#define SGMII2_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_ALIGN              0
#define SGMII2_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_BITS               1
#define SGMII2_DIGITAL_PATGENCTRL_PATGEN_LPI_EN_SHIFT              15

/* SGMII2_Digital :: PatGenCtrl :: tx_err [14:14] */
#define Wr_SGMII2_Digital_PatGenCtrl_tx_err(x) WriteRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x4000,14,x)
#define Rd_SGMII2_Digital_PatGenCtrl_tx_err(x) ReadRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x4000,14)
#define SGMII2_DIGITAL_PATGENCTRL_TX_ERR_MASK                      0x4000
#define SGMII2_DIGITAL_PATGENCTRL_TX_ERR_ALIGN                     0
#define SGMII2_DIGITAL_PATGENCTRL_TX_ERR_BITS                      1
#define SGMII2_DIGITAL_PATGENCTRL_TX_ERR_SHIFT                     14

/* SGMII2_Digital :: PatGenCtrl :: skip_crc [13:13] */
#define Wr_SGMII2_Digital_PatGenCtrl_skip_crc(x) WriteRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x2000,13,x)
#define Rd_SGMII2_Digital_PatGenCtrl_skip_crc(x) ReadRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x2000,13)
#define SGMII2_DIGITAL_PATGENCTRL_SKIP_CRC_MASK                    0x2000
#define SGMII2_DIGITAL_PATGENCTRL_SKIP_CRC_ALIGN                   0
#define SGMII2_DIGITAL_PATGENCTRL_SKIP_CRC_BITS                    1
#define SGMII2_DIGITAL_PATGENCTRL_SKIP_CRC_SHIFT                   13

/* SGMII2_Digital :: PatGenCtrl :: en_crc_checker_fragment_err_det [12:12] */
#define Wr_SGMII2_Digital_PatGenCtrl_en_crc_checker_fragment_err_det(x) WriteRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x1000,12,x)
#define Rd_SGMII2_Digital_PatGenCtrl_en_crc_checker_fragment_err_det(x) ReadRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x1000,12)
#define SGMII2_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_MASK 0x1000
#define SGMII2_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_ALIGN 0
#define SGMII2_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_BITS 1
#define SGMII2_DIGITAL_PATGENCTRL_EN_CRC_CHECKER_FRAGMENT_ERR_DET_SHIFT 12

/* SGMII2_Digital :: PatGenCtrl :: ipg_select [11:09] */
#define Wr_SGMII2_Digital_PatGenCtrl_ipg_select(x) WriteRegBits16(SGMII2_DIGITAL_PATGENCTRL,0xe00,9,x)
#define Rd_SGMII2_Digital_PatGenCtrl_ipg_select(x) ReadRegBits16(SGMII2_DIGITAL_PATGENCTRL,0xe00,9)
#define SGMII2_DIGITAL_PATGENCTRL_IPG_SELECT_MASK                  0x0e00
#define SGMII2_DIGITAL_PATGENCTRL_IPG_SELECT_ALIGN                 0
#define SGMII2_DIGITAL_PATGENCTRL_IPG_SELECT_BITS                  3
#define SGMII2_DIGITAL_PATGENCTRL_IPG_SELECT_SHIFT                 9

/* SGMII2_Digital :: PatGenCtrl :: pkt_size [08:03] */
#define Wr_SGMII2_Digital_PatGenCtrl_pkt_size(x) WriteRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x1f8,3,x)
#define Rd_SGMII2_Digital_PatGenCtrl_pkt_size(x) ReadRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x1f8,3)
#define SGMII2_DIGITAL_PATGENCTRL_PKT_SIZE_MASK                    0x01f8
#define SGMII2_DIGITAL_PATGENCTRL_PKT_SIZE_ALIGN                   0
#define SGMII2_DIGITAL_PATGENCTRL_PKT_SIZE_BITS                    6
#define SGMII2_DIGITAL_PATGENCTRL_PKT_SIZE_SHIFT                   3

/* SGMII2_Digital :: PatGenCtrl :: single_pass_mode [02:02] */
#define Wr_SGMII2_Digital_PatGenCtrl_single_pass_mode(x) WriteRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x4,2,x)
#define Rd_SGMII2_Digital_PatGenCtrl_single_pass_mode(x) ReadRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x4,2)
#define SGMII2_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_MASK            0x0004
#define SGMII2_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_ALIGN           0
#define SGMII2_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_BITS            1
#define SGMII2_DIGITAL_PATGENCTRL_SINGLE_PASS_MODE_SHIFT           2

/* SGMII2_Digital :: PatGenCtrl :: run_pattern_gen [01:01] */
#define Wr_SGMII2_Digital_PatGenCtrl_run_pattern_gen(x) WriteRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x2,1,x)
#define Rd_SGMII2_Digital_PatGenCtrl_run_pattern_gen(x) ReadRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x2,1)
#define SGMII2_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_MASK             0x0002
#define SGMII2_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_ALIGN            0
#define SGMII2_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_BITS             1
#define SGMII2_DIGITAL_PATGENCTRL_RUN_PATTERN_GEN_SHIFT            1

/* SGMII2_Digital :: PatGenCtrl :: sel_pattern_gen_data [00:00] */
#define Wr_SGMII2_Digital_PatGenCtrl_sel_pattern_gen_data(x) WriteRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x1,0,x)
#define Rd_SGMII2_Digital_PatGenCtrl_sel_pattern_gen_data(x) ReadRegBits16(SGMII2_DIGITAL_PATGENCTRL,0x1,0)
#define SGMII2_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_MASK        0x0001
#define SGMII2_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_ALIGN       0
#define SGMII2_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_BITS        1
#define SGMII2_DIGITAL_PATGENCTRL_SEL_PATTERN_GEN_DATA_SHIFT       0


/****************************************************************************
 * SGMII2_Digital :: PatGenStat
 ***************************************************************************/
/* SGMII2_Digital :: PatGenStat :: reserved0 [15:04] */
#define SGMII2_DIGITAL_PATGENSTAT_RESERVED0_MASK                   0xfff0
#define SGMII2_DIGITAL_PATGENSTAT_RESERVED0_ALIGN                  0
#define SGMII2_DIGITAL_PATGENSTAT_RESERVED0_BITS                   12
#define SGMII2_DIGITAL_PATGENSTAT_RESERVED0_SHIFT                  4

/* SGMII2_Digital :: PatGenStat :: pattern_gen_active [03:03] */
#define Wr_SGMII2_Digital_PatGenStat_pattern_gen_active(x) WriteRegBits16(SGMII2_DIGITAL_PATGENSTAT,0x8,3,x)
#define Rd_SGMII2_Digital_PatGenStat_pattern_gen_active(x) ReadRegBits16(SGMII2_DIGITAL_PATGENSTAT,0x8,3)
#define SGMII2_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_MASK          0x0008
#define SGMII2_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_ALIGN         0
#define SGMII2_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_BITS          1
#define SGMII2_DIGITAL_PATGENSTAT_PATTERN_GEN_ACTIVE_SHIFT         3

/* SGMII2_Digital :: PatGenStat :: pattern_gen_fsm [02:00] */
#define Wr_SGMII2_Digital_PatGenStat_pattern_gen_fsm(x) WriteRegBits16(SGMII2_DIGITAL_PATGENSTAT,0x7,0,x)
#define Rd_SGMII2_Digital_PatGenStat_pattern_gen_fsm(x) ReadRegBits16(SGMII2_DIGITAL_PATGENSTAT,0x7,0)
#define SGMII2_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_MASK             0x0007
#define SGMII2_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_ALIGN            0
#define SGMII2_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_BITS             3
#define SGMII2_DIGITAL_PATGENSTAT_PATTERN_GEN_FSM_SHIFT            0


/****************************************************************************
 * SGMII2_Digital :: TestMode
 ***************************************************************************/
/* SGMII2_Digital :: TestMode :: disable_reset_cnt [15:15] */
#define Wr_SGMII2_Digital_TestMode_disable_reset_cnt(x) WriteRegBits16(SGMII2_DIGITAL_TESTMODE,0x8000,15,x)
#define Rd_SGMII2_Digital_TestMode_disable_reset_cnt(x) ReadRegBits16(SGMII2_DIGITAL_TESTMODE,0x8000,15)
#define SGMII2_DIGITAL_TESTMODE_DISABLE_RESET_CNT_MASK             0x8000
#define SGMII2_DIGITAL_TESTMODE_DISABLE_RESET_CNT_ALIGN            0
#define SGMII2_DIGITAL_TESTMODE_DISABLE_RESET_CNT_BITS             1
#define SGMII2_DIGITAL_TESTMODE_DISABLE_RESET_CNT_SHIFT            15

/* SGMII2_Digital :: TestMode :: clear_packet_counters [14:14] */
#define Wr_SGMII2_Digital_TestMode_clear_packet_counters(x) WriteRegBits16(SGMII2_DIGITAL_TESTMODE,0x4000,14,x)
#define Rd_SGMII2_Digital_TestMode_clear_packet_counters(x) ReadRegBits16(SGMII2_DIGITAL_TESTMODE,0x4000,14)
#define SGMII2_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_MASK         0x4000
#define SGMII2_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_ALIGN        0
#define SGMII2_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_BITS         1
#define SGMII2_DIGITAL_TESTMODE_CLEAR_PACKET_COUNTERS_SHIFT        14

/* SGMII2_Digital :: TestMode :: reserved0 [13:05] */
#define SGMII2_DIGITAL_TESTMODE_RESERVED0_MASK                     0x3fe0
#define SGMII2_DIGITAL_TESTMODE_RESERVED0_ALIGN                    0
#define SGMII2_DIGITAL_TESTMODE_RESERVED0_BITS                     9
#define SGMII2_DIGITAL_TESTMODE_RESERVED0_SHIFT                    5

/* SGMII2_Digital :: TestMode :: fifo_fsm_cya_rx [04:04] */
#define Wr_SGMII2_Digital_TestMode_fifo_fsm_cya_rx(x) WriteRegBits16(SGMII2_DIGITAL_TESTMODE,0x10,4,x)
#define Rd_SGMII2_Digital_TestMode_fifo_fsm_cya_rx(x) ReadRegBits16(SGMII2_DIGITAL_TESTMODE,0x10,4)
#define SGMII2_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_MASK               0x0010
#define SGMII2_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_ALIGN              0
#define SGMII2_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_BITS               1
#define SGMII2_DIGITAL_TESTMODE_FIFO_FSM_CYA_RX_SHIFT              4

/* SGMII2_Digital :: TestMode :: dig1000x_afrst_cya [03:03] */
#define Wr_SGMII2_Digital_TestMode_dig1000x_afrst_cya(x) WriteRegBits16(SGMII2_DIGITAL_TESTMODE,0x8,3,x)
#define Rd_SGMII2_Digital_TestMode_dig1000x_afrst_cya(x) ReadRegBits16(SGMII2_DIGITAL_TESTMODE,0x8,3)
#define SGMII2_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_MASK            0x0008
#define SGMII2_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_ALIGN           0
#define SGMII2_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_BITS            1
#define SGMII2_DIGITAL_TESTMODE_DIG1000X_AFRST_CYA_SHIFT           3

/* SGMII2_Digital :: TestMode :: fifo_elasticity_rx [02:01] */
#define Wr_SGMII2_Digital_TestMode_fifo_elasticity_rx(x) WriteRegBits16(SGMII2_DIGITAL_TESTMODE,0x6,1,x)
#define Rd_SGMII2_Digital_TestMode_fifo_elasticity_rx(x) ReadRegBits16(SGMII2_DIGITAL_TESTMODE,0x6,1)
#define SGMII2_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_MASK            0x0006
#define SGMII2_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_ALIGN           0
#define SGMII2_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_BITS            2
#define SGMII2_DIGITAL_TESTMODE_FIFO_ELASTICITY_RX_SHIFT           1

/* SGMII2_Digital :: TestMode :: fifo_ipg_rx_cya [00:00] */
#define Wr_SGMII2_Digital_TestMode_fifo_ipg_rx_cya(x) WriteRegBits16(SGMII2_DIGITAL_TESTMODE,0x1,0,x)
#define Rd_SGMII2_Digital_TestMode_fifo_ipg_rx_cya(x) ReadRegBits16(SGMII2_DIGITAL_TESTMODE,0x1,0)
#define SGMII2_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_MASK               0x0001
#define SGMII2_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_ALIGN              0
#define SGMII2_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_BITS               1
#define SGMII2_DIGITAL_TESTMODE_FIFO_IPG_RX_CYA_SHIFT              0


/****************************************************************************
 * SGMII2_Digital :: TxPktCnt
 ***************************************************************************/
/* SGMII2_Digital :: TxPktCnt :: TxPktCnt [15:00] */
#define Wr_SGMII2_Digital_TxPktCnt_TxPktCnt(x) WriteReg16(SGMII2_DIGITAL_TXPKTCNT,x)
#define Rd_SGMII2_Digital_TxPktCnt_TxPktCnt(x) ReadReg16(SGMII2_DIGITAL_TXPKTCNT)
#define SGMII2_DIGITAL_TXPKTCNT_TXPKTCNT_MASK                      0xffff
#define SGMII2_DIGITAL_TXPKTCNT_TXPKTCNT_ALIGN                     0
#define SGMII2_DIGITAL_TXPKTCNT_TXPKTCNT_BITS                      16
#define SGMII2_DIGITAL_TXPKTCNT_TXPKTCNT_SHIFT                     0


/****************************************************************************
 * SGMII2_Digital :: RxPktCnt
 ***************************************************************************/
/* SGMII2_Digital :: RxPktCnt :: RxPktCnt [15:00] */
#define Wr_SGMII2_Digital_RxPktCnt_RxPktCnt(x) WriteReg16(SGMII2_DIGITAL_RXPKTCNT,x)
#define Rd_SGMII2_Digital_RxPktCnt_RxPktCnt(x) ReadReg16(SGMII2_DIGITAL_RXPKTCNT)
#define SGMII2_DIGITAL_RXPKTCNT_RXPKTCNT_MASK                      0xffff
#define SGMII2_DIGITAL_RXPKTCNT_RXPKTCNT_ALIGN                     0
#define SGMII2_DIGITAL_RXPKTCNT_RXPKTCNT_BITS                      16
#define SGMII2_DIGITAL_RXPKTCNT_RXPKTCNT_SHIFT                     0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_serdesID
 ***************************************************************************/
/****************************************************************************
 * SGMII2_serdesID :: serdesID0
 ***************************************************************************/
/* SGMII2_serdesID :: serdesID0 :: rev_letter [15:14] */
#define Wr_SGMII2_serdesID_serdesID0_rev_letter(x) WriteRegBits16(SGMII2_SERDESID_SERDESID0,0xc000,14,x)
#define Rd_SGMII2_serdesID_serdesID0_rev_letter(x) ReadRegBits16(SGMII2_SERDESID_SERDESID0,0xc000,14)
#define SGMII2_SERDESID_SERDESID0_REV_LETTER_MASK                  0xc000
#define SGMII2_SERDESID_SERDESID0_REV_LETTER_ALIGN                 0
#define SGMII2_SERDESID_SERDESID0_REV_LETTER_BITS                  2
#define SGMII2_SERDESID_SERDESID0_REV_LETTER_SHIFT                 14

/* SGMII2_serdesID :: serdesID0 :: rev_number [13:11] */
#define Wr_SGMII2_serdesID_serdesID0_rev_number(x) WriteRegBits16(SGMII2_SERDESID_SERDESID0,0x3800,11,x)
#define Rd_SGMII2_serdesID_serdesID0_rev_number(x) ReadRegBits16(SGMII2_SERDESID_SERDESID0,0x3800,11)
#define SGMII2_SERDESID_SERDESID0_REV_NUMBER_MASK                  0x3800
#define SGMII2_SERDESID_SERDESID0_REV_NUMBER_ALIGN                 0
#define SGMII2_SERDESID_SERDESID0_REV_NUMBER_BITS                  3
#define SGMII2_SERDESID_SERDESID0_REV_NUMBER_SHIFT                 11

/* SGMII2_serdesID :: serdesID0 :: bonding [10:09] */
#define Wr_SGMII2_serdesID_serdesID0_bonding(x) WriteRegBits16(SGMII2_SERDESID_SERDESID0,0x600,9,x)
#define Rd_SGMII2_serdesID_serdesID0_bonding(x) ReadRegBits16(SGMII2_SERDESID_SERDESID0,0x600,9)
#define SGMII2_SERDESID_SERDESID0_BONDING_MASK                     0x0600
#define SGMII2_SERDESID_SERDESID0_BONDING_ALIGN                    0
#define SGMII2_SERDESID_SERDESID0_BONDING_BITS                     2
#define SGMII2_SERDESID_SERDESID0_BONDING_SHIFT                    9

/* SGMII2_serdesID :: serdesID0 :: tech_proc [08:06] */
#define Wr_SGMII2_serdesID_serdesID0_tech_proc(x) WriteRegBits16(SGMII2_SERDESID_SERDESID0,0x1c0,6,x)
#define Rd_SGMII2_serdesID_serdesID0_tech_proc(x) ReadRegBits16(SGMII2_SERDESID_SERDESID0,0x1c0,6)
#define SGMII2_SERDESID_SERDESID0_TECH_PROC_MASK                   0x01c0
#define SGMII2_SERDESID_SERDESID0_TECH_PROC_ALIGN                  0
#define SGMII2_SERDESID_SERDESID0_TECH_PROC_BITS                   3
#define SGMII2_SERDESID_SERDESID0_TECH_PROC_SHIFT                  6

/* SGMII2_serdesID :: serdesID0 :: model_number [05:00] */
#define Wr_SGMII2_serdesID_serdesID0_model_number(x) WriteRegBits16(SGMII2_SERDESID_SERDESID0,0x3f,0,x)
#define Rd_SGMII2_serdesID_serdesID0_model_number(x) ReadRegBits16(SGMII2_SERDESID_SERDESID0,0x3f,0)
#define SGMII2_SERDESID_SERDESID0_MODEL_NUMBER_MASK                0x003f
#define SGMII2_SERDESID_SERDESID0_MODEL_NUMBER_ALIGN               0
#define SGMII2_SERDESID_SERDESID0_MODEL_NUMBER_BITS                6
#define SGMII2_SERDESID_SERDESID0_MODEL_NUMBER_SHIFT               0


/****************************************************************************
 * SGMII2_serdesID :: serdesID1
 ***************************************************************************/
/* SGMII2_serdesID :: serdesID1 :: multiplicity [15:12] */
#define Wr_SGMII2_serdesID_serdesID1_multiplicity(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0xf000,12,x)
#define Rd_SGMII2_serdesID_serdesID1_multiplicity(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0xf000,12)
#define SGMII2_SERDESID_SERDESID1_MULTIPLICITY_MASK                0xf000
#define SGMII2_SERDESID_SERDESID1_MULTIPLICITY_ALIGN               0
#define SGMII2_SERDESID_SERDESID1_MULTIPLICITY_BITS                4
#define SGMII2_SERDESID_SERDESID1_MULTIPLICITY_SHIFT               12

/* SGMII2_serdesID :: serdesID1 :: CL37 [11:11] */
#define Wr_SGMII2_serdesID_serdesID1_CL37(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x800,11,x)
#define Rd_SGMII2_serdesID_serdesID1_CL37(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x800,11)
#define SGMII2_SERDESID_SERDESID1_CL37_MASK                        0x0800
#define SGMII2_SERDESID_SERDESID1_CL37_ALIGN                       0
#define SGMII2_SERDESID_SERDESID1_CL37_BITS                        1
#define SGMII2_SERDESID_SERDESID1_CL37_SHIFT                       11

/* SGMII2_serdesID :: serdesID1 :: CL73 [10:10] */
#define Wr_SGMII2_serdesID_serdesID1_CL73(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x400,10,x)
#define Rd_SGMII2_serdesID_serdesID1_CL73(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x400,10)
#define SGMII2_SERDESID_SERDESID1_CL73_MASK                        0x0400
#define SGMII2_SERDESID_SERDESID1_CL73_ALIGN                       0
#define SGMII2_SERDESID_SERDESID1_CL73_BITS                        1
#define SGMII2_SERDESID_SERDESID1_CL73_SHIFT                       10

/* SGMII2_serdesID :: serdesID1 :: CL36 [09:09] */
#define Wr_SGMII2_serdesID_serdesID1_CL36(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x200,9,x)
#define Rd_SGMII2_serdesID_serdesID1_CL36(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x200,9)
#define SGMII2_SERDESID_SERDESID1_CL36_MASK                        0x0200
#define SGMII2_SERDESID_SERDESID1_CL36_ALIGN                       0
#define SGMII2_SERDESID_SERDESID1_CL36_BITS                        1
#define SGMII2_SERDESID_SERDESID1_CL36_SHIFT                       9

/* SGMII2_serdesID :: serdesID1 :: CL48 [08:08] */
#define Wr_SGMII2_serdesID_serdesID1_CL48(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x100,8,x)
#define Rd_SGMII2_serdesID_serdesID1_CL48(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x100,8)
#define SGMII2_SERDESID_SERDESID1_CL48_MASK                        0x0100
#define SGMII2_SERDESID_SERDESID1_CL48_ALIGN                       0
#define SGMII2_SERDESID_SERDESID1_CL48_BITS                        1
#define SGMII2_SERDESID_SERDESID1_CL48_SHIFT                       8

/* SGMII2_serdesID :: serdesID1 :: HiGig [07:07] */
#define Wr_SGMII2_serdesID_serdesID1_HiGig(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x80,7,x)
#define Rd_SGMII2_serdesID_serdesID1_HiGig(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x80,7)
#define SGMII2_SERDESID_SERDESID1_HIGIG_MASK                       0x0080
#define SGMII2_SERDESID_SERDESID1_HIGIG_ALIGN                      0
#define SGMII2_SERDESID_SERDESID1_HIGIG_BITS                       1
#define SGMII2_SERDESID_SERDESID1_HIGIG_SHIFT                      7

/* SGMII2_serdesID :: serdesID1 :: HiGigII [06:06] */
#define Wr_SGMII2_serdesID_serdesID1_HiGigII(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x40,6,x)
#define Rd_SGMII2_serdesID_serdesID1_HiGigII(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x40,6)
#define SGMII2_SERDESID_SERDESID1_HIGIGII_MASK                     0x0040
#define SGMII2_SERDESID_SERDESID1_HIGIGII_ALIGN                    0
#define SGMII2_SERDESID_SERDESID1_HIGIGII_BITS                     1
#define SGMII2_SERDESID_SERDESID1_HIGIGII_SHIFT                    6

/* SGMII2_serdesID :: serdesID1 :: PCIE [05:05] */
#define Wr_SGMII2_serdesID_serdesID1_PCIE(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x20,5,x)
#define Rd_SGMII2_serdesID_serdesID1_PCIE(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x20,5)
#define SGMII2_SERDESID_SERDESID1_PCIE_MASK                        0x0020
#define SGMII2_SERDESID_SERDESID1_PCIE_ALIGN                       0
#define SGMII2_SERDESID_SERDESID1_PCIE_BITS                        1
#define SGMII2_SERDESID_SERDESID1_PCIE_SHIFT                       5

/* SGMII2_serdesID :: serdesID1 :: PCIE_II [04:04] */
#define Wr_SGMII2_serdesID_serdesID1_PCIE_II(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x10,4,x)
#define Rd_SGMII2_serdesID_serdesID1_PCIE_II(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x10,4)
#define SGMII2_SERDESID_SERDESID1_PCIE_II_MASK                     0x0010
#define SGMII2_SERDESID_SERDESID1_PCIE_II_ALIGN                    0
#define SGMII2_SERDESID_SERDESID1_PCIE_II_BITS                     1
#define SGMII2_SERDESID_SERDESID1_PCIE_II_SHIFT                    4

/* SGMII2_serdesID :: serdesID1 :: brcm_64B66B [03:03] */
#define Wr_SGMII2_serdesID_serdesID1_brcm_64B66B(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x8,3,x)
#define Rd_SGMII2_serdesID_serdesID1_brcm_64B66B(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x8,3)
#define SGMII2_SERDESID_SERDESID1_BRCM_64B66B_MASK                 0x0008
#define SGMII2_SERDESID_SERDESID1_BRCM_64B66B_ALIGN                0
#define SGMII2_SERDESID_SERDESID1_BRCM_64B66B_BITS                 1
#define SGMII2_SERDESID_SERDESID1_BRCM_64B66B_SHIFT                3

/* SGMII2_serdesID :: serdesID1 :: Scrambler [02:02] */
#define Wr_SGMII2_serdesID_serdesID1_Scrambler(x) WriteRegBits16(SGMII2_SERDESID_SERDESID1,0x4,2,x)
#define Rd_SGMII2_serdesID_serdesID1_Scrambler(x) ReadRegBits16(SGMII2_SERDESID_SERDESID1,0x4,2)
#define SGMII2_SERDESID_SERDESID1_SCRAMBLER_MASK                   0x0004
#define SGMII2_SERDESID_SERDESID1_SCRAMBLER_ALIGN                  0
#define SGMII2_SERDESID_SERDESID1_SCRAMBLER_BITS                   1
#define SGMII2_SERDESID_SERDESID1_SCRAMBLER_SHIFT                  2

/* SGMII2_serdesID :: serdesID1 :: reserved0 [01:00] */
#define SGMII2_SERDESID_SERDESID1_RESERVED0_MASK                   0x0003
#define SGMII2_SERDESID_SERDESID1_RESERVED0_ALIGN                  0
#define SGMII2_SERDESID_SERDESID1_RESERVED0_BITS                   2
#define SGMII2_SERDESID_SERDESID1_RESERVED0_SHIFT                  0


/****************************************************************************
 * SGMII2_serdesID :: serdesID2
 ***************************************************************************/
/* SGMII2_serdesID :: serdesID2 :: ID3present [15:15] */
#define Wr_SGMII2_serdesID_serdesID2_ID3present(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x8000,15,x)
#define Rd_SGMII2_serdesID_serdesID2_ID3present(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x8000,15)
#define SGMII2_SERDESID_SERDESID2_ID3PRESENT_MASK                  0x8000
#define SGMII2_SERDESID_SERDESID2_ID3PRESENT_ALIGN                 0
#define SGMII2_SERDESID_SERDESID2_ID3PRESENT_BITS                  1
#define SGMII2_SERDESID_SERDESID2_ID3PRESENT_SHIFT                 15

/* SGMII2_serdesID :: serdesID2 :: dr_25G_4L [14:14] */
#define Wr_SGMII2_serdesID_serdesID2_dr_25G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x4000,14,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_25G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x4000,14)
#define SGMII2_SERDESID_SERDESID2_DR_25G_4L_MASK                   0x4000
#define SGMII2_SERDESID_SERDESID2_DR_25G_4L_ALIGN                  0
#define SGMII2_SERDESID_SERDESID2_DR_25G_4L_BITS                   1
#define SGMII2_SERDESID_SERDESID2_DR_25G_4L_SHIFT                  14

/* SGMII2_serdesID :: serdesID2 :: dr_21G_4L [13:13] */
#define Wr_SGMII2_serdesID_serdesID2_dr_21G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x2000,13,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_21G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x2000,13)
#define SGMII2_SERDESID_SERDESID2_DR_21G_4L_MASK                   0x2000
#define SGMII2_SERDESID_SERDESID2_DR_21G_4L_ALIGN                  0
#define SGMII2_SERDESID_SERDESID2_DR_21G_4L_BITS                   1
#define SGMII2_SERDESID_SERDESID2_DR_21G_4L_SHIFT                  13

/* SGMII2_serdesID :: serdesID2 :: dr_20G_4L [12:12] */
#define Wr_SGMII2_serdesID_serdesID2_dr_20G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x1000,12,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_20G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x1000,12)
#define SGMII2_SERDESID_SERDESID2_DR_20G_4L_MASK                   0x1000
#define SGMII2_SERDESID_SERDESID2_DR_20G_4L_ALIGN                  0
#define SGMII2_SERDESID_SERDESID2_DR_20G_4L_BITS                   1
#define SGMII2_SERDESID_SERDESID2_DR_20G_4L_SHIFT                  12

/* SGMII2_serdesID :: serdesID2 :: dr_16G_4L [11:11] */
#define Wr_SGMII2_serdesID_serdesID2_dr_16G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x800,11,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_16G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x800,11)
#define SGMII2_SERDESID_SERDESID2_DR_16G_4L_MASK                   0x0800
#define SGMII2_SERDESID_SERDESID2_DR_16G_4L_ALIGN                  0
#define SGMII2_SERDESID_SERDESID2_DR_16G_4L_BITS                   1
#define SGMII2_SERDESID_SERDESID2_DR_16G_4L_SHIFT                  11

/* SGMII2_serdesID :: serdesID2 :: dr_15G_4L [10:10] */
#define Wr_SGMII2_serdesID_serdesID2_dr_15G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x400,10,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_15G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x400,10)
#define SGMII2_SERDESID_SERDESID2_DR_15G_4L_MASK                   0x0400
#define SGMII2_SERDESID_SERDESID2_DR_15G_4L_ALIGN                  0
#define SGMII2_SERDESID_SERDESID2_DR_15G_4L_BITS                   1
#define SGMII2_SERDESID_SERDESID2_DR_15G_4L_SHIFT                  10

/* SGMII2_serdesID :: serdesID2 :: dr_13G_4L [09:09] */
#define Wr_SGMII2_serdesID_serdesID2_dr_13G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x200,9,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_13G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x200,9)
#define SGMII2_SERDESID_SERDESID2_DR_13G_4L_MASK                   0x0200
#define SGMII2_SERDESID_SERDESID2_DR_13G_4L_ALIGN                  0
#define SGMII2_SERDESID_SERDESID2_DR_13G_4L_BITS                   1
#define SGMII2_SERDESID_SERDESID2_DR_13G_4L_SHIFT                  9

/* SGMII2_serdesID :: serdesID2 :: dr_12_5G_4L [08:08] */
#define Wr_SGMII2_serdesID_serdesID2_dr_12_5G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x100,8,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_12_5G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x100,8)
#define SGMII2_SERDESID_SERDESID2_DR_12_5G_4L_MASK                 0x0100
#define SGMII2_SERDESID_SERDESID2_DR_12_5G_4L_ALIGN                0
#define SGMII2_SERDESID_SERDESID2_DR_12_5G_4L_BITS                 1
#define SGMII2_SERDESID_SERDESID2_DR_12_5G_4L_SHIFT                8

/* SGMII2_serdesID :: serdesID2 :: dr_12G_4L [07:07] */
#define Wr_SGMII2_serdesID_serdesID2_dr_12G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x80,7,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_12G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x80,7)
#define SGMII2_SERDESID_SERDESID2_DR_12G_4L_MASK                   0x0080
#define SGMII2_SERDESID_SERDESID2_DR_12G_4L_ALIGN                  0
#define SGMII2_SERDESID_SERDESID2_DR_12G_4L_BITS                   1
#define SGMII2_SERDESID_SERDESID2_DR_12G_4L_SHIFT                  7

/* SGMII2_serdesID :: serdesID2 :: dr_10G_4L [06:06] */
#define Wr_SGMII2_serdesID_serdesID2_dr_10G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x40,6,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_10G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x40,6)
#define SGMII2_SERDESID_SERDESID2_DR_10G_4L_MASK                   0x0040
#define SGMII2_SERDESID_SERDESID2_DR_10G_4L_ALIGN                  0
#define SGMII2_SERDESID_SERDESID2_DR_10G_4L_BITS                   1
#define SGMII2_SERDESID_SERDESID2_DR_10G_4L_SHIFT                  6

/* SGMII2_serdesID :: serdesID2 :: dr_6G_4L [05:05] */
#define Wr_SGMII2_serdesID_serdesID2_dr_6G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x20,5,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_6G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x20,5)
#define SGMII2_SERDESID_SERDESID2_DR_6G_4L_MASK                    0x0020
#define SGMII2_SERDESID_SERDESID2_DR_6G_4L_ALIGN                   0
#define SGMII2_SERDESID_SERDESID2_DR_6G_4L_BITS                    1
#define SGMII2_SERDESID_SERDESID2_DR_6G_4L_SHIFT                   5

/* SGMII2_serdesID :: serdesID2 :: dr_5G_4L [04:04] */
#define Wr_SGMII2_serdesID_serdesID2_dr_5G_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x10,4,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_5G_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x10,4)
#define SGMII2_SERDESID_SERDESID2_DR_5G_4L_MASK                    0x0010
#define SGMII2_SERDESID_SERDESID2_DR_5G_4L_ALIGN                   0
#define SGMII2_SERDESID_SERDESID2_DR_5G_4L_BITS                    1
#define SGMII2_SERDESID_SERDESID2_DR_5G_4L_SHIFT                   4

/* SGMII2_serdesID :: serdesID2 :: dr_2p5G_SL [03:03] */
#define Wr_SGMII2_serdesID_serdesID2_dr_2p5G_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x8,3,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_2p5G_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x8,3)
#define SGMII2_SERDESID_SERDESID2_DR_2P5G_SL_MASK                  0x0008
#define SGMII2_SERDESID_SERDESID2_DR_2P5G_SL_ALIGN                 0
#define SGMII2_SERDESID_SERDESID2_DR_2P5G_SL_BITS                  1
#define SGMII2_SERDESID_SERDESID2_DR_2P5G_SL_SHIFT                 3

/* SGMII2_serdesID :: serdesID2 :: dr_1G_SL [02:02] */
#define Wr_SGMII2_serdesID_serdesID2_dr_1G_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x4,2,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_1G_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x4,2)
#define SGMII2_SERDESID_SERDESID2_DR_1G_SL_MASK                    0x0004
#define SGMII2_SERDESID_SERDESID2_DR_1G_SL_ALIGN                   0
#define SGMII2_SERDESID_SERDESID2_DR_1G_SL_BITS                    1
#define SGMII2_SERDESID_SERDESID2_DR_1G_SL_SHIFT                   2

/* SGMII2_serdesID :: serdesID2 :: dr_100M_SL [01:01] */
#define Wr_SGMII2_serdesID_serdesID2_dr_100M_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x2,1,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_100M_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x2,1)
#define SGMII2_SERDESID_SERDESID2_DR_100M_SL_MASK                  0x0002
#define SGMII2_SERDESID_SERDESID2_DR_100M_SL_ALIGN                 0
#define SGMII2_SERDESID_SERDESID2_DR_100M_SL_BITS                  1
#define SGMII2_SERDESID_SERDESID2_DR_100M_SL_SHIFT                 1

/* SGMII2_serdesID :: serdesID2 :: dr_10M_SL [00:00] */
#define Wr_SGMII2_serdesID_serdesID2_dr_10M_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID2,0x1,0,x)
#define Rd_SGMII2_serdesID_serdesID2_dr_10M_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID2,0x1,0)
#define SGMII2_SERDESID_SERDESID2_DR_10M_SL_MASK                   0x0001
#define SGMII2_SERDESID_SERDESID2_DR_10M_SL_ALIGN                  0
#define SGMII2_SERDESID_SERDESID2_DR_10M_SL_BITS                   1
#define SGMII2_SERDESID_SERDESID2_DR_10M_SL_SHIFT                  0


/****************************************************************************
 * SGMII2_serdesID :: serdesID3
 ***************************************************************************/
/* SGMII2_serdesID :: serdesID3 :: ID4present [15:15] */
#define Wr_SGMII2_serdesID_serdesID3_ID4present(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x8000,15,x)
#define Rd_SGMII2_serdesID_serdesID3_ID4present(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x8000,15)
#define SGMII2_SERDESID_SERDESID3_ID4PRESENT_MASK                  0x8000
#define SGMII2_SERDESID_SERDESID3_ID4PRESENT_ALIGN                 0
#define SGMII2_SERDESID_SERDESID3_ID4PRESENT_BITS                  1
#define SGMII2_SERDESID_SERDESID3_ID4PRESENT_SHIFT                 15

/* SGMII2_serdesID :: serdesID3 :: reserved0 [14:10] */
#define SGMII2_SERDESID_SERDESID3_RESERVED0_MASK                   0x7c00
#define SGMII2_SERDESID_SERDESID3_RESERVED0_ALIGN                  0
#define SGMII2_SERDESID_SERDESID3_RESERVED0_BITS                   5
#define SGMII2_SERDESID_SERDESID3_RESERVED0_SHIFT                  10

/* SGMII2_serdesID :: serdesID3 :: dr_40000_4L [09:09] */
#define Wr_SGMII2_serdesID_serdesID3_dr_40000_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x200,9,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_40000_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x200,9)
#define SGMII2_SERDESID_SERDESID3_DR_40000_4L_MASK                 0x0200
#define SGMII2_SERDESID_SERDESID3_DR_40000_4L_ALIGN                0
#define SGMII2_SERDESID_SERDESID3_DR_40000_4L_BITS                 1
#define SGMII2_SERDESID_SERDESID3_DR_40000_4L_SHIFT                9

/* SGMII2_serdesID :: serdesID3 :: dr_32700_4L [08:08] */
#define Wr_SGMII2_serdesID_serdesID3_dr_32700_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x100,8,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_32700_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x100,8)
#define SGMII2_SERDESID_SERDESID3_DR_32700_4L_MASK                 0x0100
#define SGMII2_SERDESID_SERDESID3_DR_32700_4L_ALIGN                0
#define SGMII2_SERDESID_SERDESID3_DR_32700_4L_BITS                 1
#define SGMII2_SERDESID_SERDESID3_DR_32700_4L_SHIFT                8

/* SGMII2_serdesID :: serdesID3 :: dr_31500_4L [07:07] */
#define Wr_SGMII2_serdesID_serdesID3_dr_31500_4L(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x80,7,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_31500_4L(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x80,7)
#define SGMII2_SERDESID_SERDESID3_DR_31500_4L_MASK                 0x0080
#define SGMII2_SERDESID_SERDESID3_DR_31500_4L_ALIGN                0
#define SGMII2_SERDESID_SERDESID3_DR_31500_4L_BITS                 1
#define SGMII2_SERDESID_SERDESID3_DR_31500_4L_SHIFT                7

/* SGMII2_serdesID :: serdesID3 :: dr_2400_SL [06:06] */
#define Wr_SGMII2_serdesID_serdesID3_dr_2400_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x40,6,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_2400_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x40,6)
#define SGMII2_SERDESID_SERDESID3_DR_2400_SL_MASK                  0x0040
#define SGMII2_SERDESID_SERDESID3_DR_2400_SL_ALIGN                 0
#define SGMII2_SERDESID_SERDESID3_DR_2400_SL_BITS                  1
#define SGMII2_SERDESID_SERDESID3_DR_2400_SL_SHIFT                 6

/* SGMII2_serdesID :: serdesID3 :: dr_1200_SL [05:05] */
#define Wr_SGMII2_serdesID_serdesID3_dr_1200_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x20,5,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_1200_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x20,5)
#define SGMII2_SERDESID_SERDESID3_DR_1200_SL_MASK                  0x0020
#define SGMII2_SERDESID_SERDESID3_DR_1200_SL_ALIGN                 0
#define SGMII2_SERDESID_SERDESID3_DR_1200_SL_BITS                  1
#define SGMII2_SERDESID_SERDESID3_DR_1200_SL_SHIFT                 5

/* SGMII2_serdesID :: serdesID3 :: dr_6400_SL [04:04] */
#define Wr_SGMII2_serdesID_serdesID3_dr_6400_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x10,4,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_6400_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x10,4)
#define SGMII2_SERDESID_SERDESID3_DR_6400_SL_MASK                  0x0010
#define SGMII2_SERDESID_SERDESID3_DR_6400_SL_ALIGN                 0
#define SGMII2_SERDESID_SERDESID3_DR_6400_SL_BITS                  1
#define SGMII2_SERDESID_SERDESID3_DR_6400_SL_SHIFT                 4

/* SGMII2_serdesID :: serdesID3 :: dr_5000_SL [03:03] */
#define Wr_SGMII2_serdesID_serdesID3_dr_5000_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x8,3,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_5000_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x8,3)
#define SGMII2_SERDESID_SERDESID3_DR_5000_SL_MASK                  0x0008
#define SGMII2_SERDESID_SERDESID3_DR_5000_SL_ALIGN                 0
#define SGMII2_SERDESID_SERDESID3_DR_5000_SL_BITS                  1
#define SGMII2_SERDESID_SERDESID3_DR_5000_SL_SHIFT                 3

/* SGMII2_serdesID :: serdesID3 :: dr_4000_SL [02:02] */
#define Wr_SGMII2_serdesID_serdesID3_dr_4000_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x4,2,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_4000_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x4,2)
#define SGMII2_SERDESID_SERDESID3_DR_4000_SL_MASK                  0x0004
#define SGMII2_SERDESID_SERDESID3_DR_4000_SL_ALIGN                 0
#define SGMII2_SERDESID_SERDESID3_DR_4000_SL_BITS                  1
#define SGMII2_SERDESID_SERDESID3_DR_4000_SL_SHIFT                 2

/* SGMII2_serdesID :: serdesID3 :: dr_2000_SL [01:01] */
#define Wr_SGMII2_serdesID_serdesID3_dr_2000_SL(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x2,1,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_2000_SL(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x2,1)
#define SGMII2_SERDESID_SERDESID3_DR_2000_SL_MASK                  0x0002
#define SGMII2_SERDESID_SERDESID3_DR_2000_SL_ALIGN                 0
#define SGMII2_SERDESID_SERDESID3_DR_2000_SL_BITS                  1
#define SGMII2_SERDESID_SERDESID3_DR_2000_SL_SHIFT                 1

/* SGMII2_serdesID :: serdesID3 :: dr_100FX [00:00] */
#define Wr_SGMII2_serdesID_serdesID3_dr_100FX(x) WriteRegBits16(SGMII2_SERDESID_SERDESID3,0x1,0,x)
#define Rd_SGMII2_serdesID_serdesID3_dr_100FX(x) ReadRegBits16(SGMII2_SERDESID_SERDESID3,0x1,0)
#define SGMII2_SERDESID_SERDESID3_DR_100FX_MASK                    0x0001
#define SGMII2_SERDESID_SERDESID3_DR_100FX_ALIGN                   0
#define SGMII2_SERDESID_SERDESID3_DR_100FX_BITS                    1
#define SGMII2_SERDESID_SERDESID3_DR_100FX_SHIFT                   0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_Digital3
 ***************************************************************************/
/****************************************************************************
 * SGMII2_Digital3 :: TPOUT_1
 ***************************************************************************/
/* SGMII2_Digital3 :: TPOUT_1 :: tpout1 [15:00] */
#define Wr_SGMII2_Digital3_TPOUT_1_tpout1(x) WriteReg16(SGMII2_DIGITAL3_TPOUT_1,x)
#define Rd_SGMII2_Digital3_TPOUT_1_tpout1(x) ReadReg16(SGMII2_DIGITAL3_TPOUT_1)
#define SGMII2_DIGITAL3_TPOUT_1_TPOUT1_MASK                        0xffff
#define SGMII2_DIGITAL3_TPOUT_1_TPOUT1_ALIGN                       0
#define SGMII2_DIGITAL3_TPOUT_1_TPOUT1_BITS                        16
#define SGMII2_DIGITAL3_TPOUT_1_TPOUT1_SHIFT                       0


/****************************************************************************
 * SGMII2_Digital3 :: TPOUT_2
 ***************************************************************************/
/* SGMII2_Digital3 :: TPOUT_2 :: tpout2 [15:00] */
#define Wr_SGMII2_Digital3_TPOUT_2_tpout2(x) WriteReg16(SGMII2_DIGITAL3_TPOUT_2,x)
#define Rd_SGMII2_Digital3_TPOUT_2_tpout2(x) ReadReg16(SGMII2_DIGITAL3_TPOUT_2)
#define SGMII2_DIGITAL3_TPOUT_2_TPOUT2_MASK                        0xffff
#define SGMII2_DIGITAL3_TPOUT_2_TPOUT2_ALIGN                       0
#define SGMII2_DIGITAL3_TPOUT_2_TPOUT2_BITS                        16
#define SGMII2_DIGITAL3_TPOUT_2_TPOUT2_SHIFT                       0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_Digital4
 ***************************************************************************/
/****************************************************************************
 * SGMII2_Digital4 :: Misc3
 ***************************************************************************/
/* SGMII2_Digital4 :: Misc3 :: reserved0 [15:10] */
#define SGMII2_DIGITAL4_MISC3_RESERVED0_MASK                       0xfc00
#define SGMII2_DIGITAL4_MISC3_RESERVED0_ALIGN                      0
#define SGMII2_DIGITAL4_MISC3_RESERVED0_BITS                       6
#define SGMII2_DIGITAL4_MISC3_RESERVED0_SHIFT                      10

/* SGMII2_Digital4 :: Misc3 :: fifo_ipg_cya [09:09] */
#define Wr_SGMII2_Digital4_Misc3_fifo_ipg_cya(x) WriteRegBits16(SGMII2_DIGITAL4_MISC3,0x200,9,x)
#define Rd_SGMII2_Digital4_Misc3_fifo_ipg_cya(x) ReadRegBits16(SGMII2_DIGITAL4_MISC3,0x200,9)
#define SGMII2_DIGITAL4_MISC3_FIFO_IPG_CYA_MASK                    0x0200
#define SGMII2_DIGITAL4_MISC3_FIFO_IPG_CYA_ALIGN                   0
#define SGMII2_DIGITAL4_MISC3_FIFO_IPG_CYA_BITS                    1
#define SGMII2_DIGITAL4_MISC3_FIFO_IPG_CYA_SHIFT                   9

/* SGMII2_Digital4 :: Misc3 :: reserved1 [08:07] */
#define SGMII2_DIGITAL4_MISC3_RESERVED1_MASK                       0x0180
#define SGMII2_DIGITAL4_MISC3_RESERVED1_ALIGN                      0
#define SGMII2_DIGITAL4_MISC3_RESERVED1_BITS                       2
#define SGMII2_DIGITAL4_MISC3_RESERVED1_SHIFT                      7

/* SGMII2_Digital4 :: Misc3 :: laneDisable [06:06] */
#define Wr_SGMII2_Digital4_Misc3_laneDisable(x) WriteRegBits16(SGMII2_DIGITAL4_MISC3,0x40,6,x)
#define Rd_SGMII2_Digital4_Misc3_laneDisable(x) ReadRegBits16(SGMII2_DIGITAL4_MISC3,0x40,6)
#define SGMII2_DIGITAL4_MISC3_LANEDISABLE_MASK                     0x0040
#define SGMII2_DIGITAL4_MISC3_LANEDISABLE_ALIGN                    0
#define SGMII2_DIGITAL4_MISC3_LANEDISABLE_BITS                     1
#define SGMII2_DIGITAL4_MISC3_LANEDISABLE_SHIFT                    6

/* SGMII2_Digital4 :: Misc3 :: reserved2 [05:00] */
#define SGMII2_DIGITAL4_MISC3_RESERVED2_MASK                       0x003f
#define SGMII2_DIGITAL4_MISC3_RESERVED2_ALIGN                      0
#define SGMII2_DIGITAL4_MISC3_RESERVED2_BITS                       6
#define SGMII2_DIGITAL4_MISC3_RESERVED2_SHIFT                      0


/****************************************************************************
 * SGMII2_Digital4 :: Misc5
 ***************************************************************************/
/* SGMII2_Digital4 :: Misc5 :: LPI_en_rx [15:15] */
#define Wr_SGMII2_Digital4_Misc5_LPI_en_rx(x) WriteRegBits16(SGMII2_DIGITAL4_MISC5,0x8000,15,x)
#define Rd_SGMII2_Digital4_Misc5_LPI_en_rx(x) ReadRegBits16(SGMII2_DIGITAL4_MISC5,0x8000,15)
#define SGMII2_DIGITAL4_MISC5_LPI_EN_RX_MASK                       0x8000
#define SGMII2_DIGITAL4_MISC5_LPI_EN_RX_ALIGN                      0
#define SGMII2_DIGITAL4_MISC5_LPI_EN_RX_BITS                       1
#define SGMII2_DIGITAL4_MISC5_LPI_EN_RX_SHIFT                      15

/* SGMII2_Digital4 :: Misc5 :: LPI_en_tx [14:14] */
#define Wr_SGMII2_Digital4_Misc5_LPI_en_tx(x) WriteRegBits16(SGMII2_DIGITAL4_MISC5,0x4000,14,x)
#define Rd_SGMII2_Digital4_Misc5_LPI_en_tx(x) ReadRegBits16(SGMII2_DIGITAL4_MISC5,0x4000,14)
#define SGMII2_DIGITAL4_MISC5_LPI_EN_TX_MASK                       0x4000
#define SGMII2_DIGITAL4_MISC5_LPI_EN_TX_ALIGN                      0
#define SGMII2_DIGITAL4_MISC5_LPI_EN_TX_BITS                       1
#define SGMII2_DIGITAL4_MISC5_LPI_EN_TX_SHIFT                      14

/* SGMII2_Digital4 :: Misc5 :: reserved0 [13:00] */
#define SGMII2_DIGITAL4_MISC5_RESERVED0_MASK                       0x3fff
#define SGMII2_DIGITAL4_MISC5_RESERVED0_ALIGN                      0
#define SGMII2_DIGITAL4_MISC5_RESERVED0_BITS                       14
#define SGMII2_DIGITAL4_MISC5_RESERVED0_SHIFT                      0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_FX100
 ***************************************************************************/
/****************************************************************************
 * SGMII2_FX100 :: Control1
 ***************************************************************************/
/* SGMII2_FX100 :: Control1 :: data_sampler_en [15:15] */
#define Wr_SGMII2_FX100_Control1_data_sampler_en(x) WriteRegBits16(SGMII2_FX100_CONTROL1,0x8000,15,x)
#define Rd_SGMII2_FX100_Control1_data_sampler_en(x) ReadRegBits16(SGMII2_FX100_CONTROL1,0x8000,15)
#define SGMII2_FX100_CONTROL1_DATA_SAMPLER_EN_MASK                 0x8000
#define SGMII2_FX100_CONTROL1_DATA_SAMPLER_EN_ALIGN                0
#define SGMII2_FX100_CONTROL1_DATA_SAMPLER_EN_BITS                 1
#define SGMII2_FX100_CONTROL1_DATA_SAMPLER_EN_SHIFT                15

/* SGMII2_FX100 :: Control1 :: reserved0 [14:10] */
#define SGMII2_FX100_CONTROL1_RESERVED0_MASK                       0x7c00
#define SGMII2_FX100_CONTROL1_RESERVED0_ALIGN                      0
#define SGMII2_FX100_CONTROL1_RESERVED0_BITS                       5
#define SGMII2_FX100_CONTROL1_RESERVED0_SHIFT                      10

/* SGMII2_FX100 :: Control1 :: rxdata_sel [09:06] */
#define Wr_SGMII2_FX100_Control1_rxdata_sel(x) WriteRegBits16(SGMII2_FX100_CONTROL1,0x3c0,6,x)
#define Rd_SGMII2_FX100_Control1_rxdata_sel(x) ReadRegBits16(SGMII2_FX100_CONTROL1,0x3c0,6)
#define SGMII2_FX100_CONTROL1_RXDATA_SEL_MASK                      0x03c0
#define SGMII2_FX100_CONTROL1_RXDATA_SEL_ALIGN                     0
#define SGMII2_FX100_CONTROL1_RXDATA_SEL_BITS                      4
#define SGMII2_FX100_CONTROL1_RXDATA_SEL_SHIFT                     6

/* SGMII2_FX100 :: Control1 :: disable_rx_qual [05:05] */
#define Wr_SGMII2_FX100_Control1_disable_rx_qual(x) WriteRegBits16(SGMII2_FX100_CONTROL1,0x20,5,x)
#define Rd_SGMII2_FX100_Control1_disable_rx_qual(x) ReadRegBits16(SGMII2_FX100_CONTROL1,0x20,5)
#define SGMII2_FX100_CONTROL1_DISABLE_RX_QUAL_MASK                 0x0020
#define SGMII2_FX100_CONTROL1_DISABLE_RX_QUAL_ALIGN                0
#define SGMII2_FX100_CONTROL1_DISABLE_RX_QUAL_BITS                 1
#define SGMII2_FX100_CONTROL1_DISABLE_RX_QUAL_SHIFT                5

/* SGMII2_FX100 :: Control1 :: force_rx_qual [04:04] */
#define Wr_SGMII2_FX100_Control1_force_rx_qual(x) WriteRegBits16(SGMII2_FX100_CONTROL1,0x10,4,x)
#define Rd_SGMII2_FX100_Control1_force_rx_qual(x) ReadRegBits16(SGMII2_FX100_CONTROL1,0x10,4)
#define SGMII2_FX100_CONTROL1_FORCE_RX_QUAL_MASK                   0x0010
#define SGMII2_FX100_CONTROL1_FORCE_RX_QUAL_ALIGN                  0
#define SGMII2_FX100_CONTROL1_FORCE_RX_QUAL_BITS                   1
#define SGMII2_FX100_CONTROL1_FORCE_RX_QUAL_SHIFT                  4

/* SGMII2_FX100 :: Control1 :: far_end_fault_en [03:03] */
#define Wr_SGMII2_FX100_Control1_far_end_fault_en(x) WriteRegBits16(SGMII2_FX100_CONTROL1,0x8,3,x)
#define Rd_SGMII2_FX100_Control1_far_end_fault_en(x) ReadRegBits16(SGMII2_FX100_CONTROL1,0x8,3)
#define SGMII2_FX100_CONTROL1_FAR_END_FAULT_EN_MASK                0x0008
#define SGMII2_FX100_CONTROL1_FAR_END_FAULT_EN_ALIGN               0
#define SGMII2_FX100_CONTROL1_FAR_END_FAULT_EN_BITS                1
#define SGMII2_FX100_CONTROL1_FAR_END_FAULT_EN_SHIFT               3

/* SGMII2_FX100 :: Control1 :: auto_detect_fx_mode [02:02] */
#define Wr_SGMII2_FX100_Control1_auto_detect_fx_mode(x) WriteRegBits16(SGMII2_FX100_CONTROL1,0x4,2,x)
#define Rd_SGMII2_FX100_Control1_auto_detect_fx_mode(x) ReadRegBits16(SGMII2_FX100_CONTROL1,0x4,2)
#define SGMII2_FX100_CONTROL1_AUTO_DETECT_FX_MODE_MASK             0x0004
#define SGMII2_FX100_CONTROL1_AUTO_DETECT_FX_MODE_ALIGN            0
#define SGMII2_FX100_CONTROL1_AUTO_DETECT_FX_MODE_BITS             1
#define SGMII2_FX100_CONTROL1_AUTO_DETECT_FX_MODE_SHIFT            2

/* SGMII2_FX100 :: Control1 :: full_duplex [01:01] */
#define Wr_SGMII2_FX100_Control1_full_duplex(x) WriteRegBits16(SGMII2_FX100_CONTROL1,0x2,1,x)
#define Rd_SGMII2_FX100_Control1_full_duplex(x) ReadRegBits16(SGMII2_FX100_CONTROL1,0x2,1)
#define SGMII2_FX100_CONTROL1_FULL_DUPLEX_MASK                     0x0002
#define SGMII2_FX100_CONTROL1_FULL_DUPLEX_ALIGN                    0
#define SGMII2_FX100_CONTROL1_FULL_DUPLEX_BITS                     1
#define SGMII2_FX100_CONTROL1_FULL_DUPLEX_SHIFT                    1

/* SGMII2_FX100 :: Control1 :: enable [00:00] */
#define Wr_SGMII2_FX100_Control1_enable(x) WriteRegBits16(SGMII2_FX100_CONTROL1,0x1,0,x)
#define Rd_SGMII2_FX100_Control1_enable(x) ReadRegBits16(SGMII2_FX100_CONTROL1,0x1,0)
#define SGMII2_FX100_CONTROL1_ENABLE_MASK                          0x0001
#define SGMII2_FX100_CONTROL1_ENABLE_ALIGN                         0
#define SGMII2_FX100_CONTROL1_ENABLE_BITS                          1
#define SGMII2_FX100_CONTROL1_ENABLE_SHIFT                         0


/****************************************************************************
 * SGMII2_FX100 :: Control2
 ***************************************************************************/
/* SGMII2_FX100 :: Control2 :: reserved0 [15:12] */
#define SGMII2_FX100_CONTROL2_RESERVED0_MASK                       0xf000
#define SGMII2_FX100_CONTROL2_RESERVED0_ALIGN                      0
#define SGMII2_FX100_CONTROL2_RESERVED0_BITS                       4
#define SGMII2_FX100_CONTROL2_RESERVED0_SHIFT                      12

/* SGMII2_FX100 :: Control2 :: ping_pong_disable [11:11] */
#define Wr_SGMII2_FX100_Control2_ping_pong_disable(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x800,11,x)
#define Rd_SGMII2_FX100_Control2_ping_pong_disable(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x800,11)
#define SGMII2_FX100_CONTROL2_PING_PONG_DISABLE_MASK               0x0800
#define SGMII2_FX100_CONTROL2_PING_PONG_DISABLE_ALIGN              0
#define SGMII2_FX100_CONTROL2_PING_PONG_DISABLE_BITS               1
#define SGMII2_FX100_CONTROL2_PING_PONG_DISABLE_SHIFT              11

/* SGMII2_FX100 :: Control2 :: pll_clk125_sw_ref [10:10] */
#define Wr_SGMII2_FX100_Control2_pll_clk125_sw_ref(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x400,10,x)
#define Rd_SGMII2_FX100_Control2_pll_clk125_sw_ref(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x400,10)
#define SGMII2_FX100_CONTROL2_PLL_CLK125_SW_REF_MASK               0x0400
#define SGMII2_FX100_CONTROL2_PLL_CLK125_SW_REF_ALIGN              0
#define SGMII2_FX100_CONTROL2_PLL_CLK125_SW_REF_BITS               1
#define SGMII2_FX100_CONTROL2_PLL_CLK125_SW_REF_SHIFT              10

/* SGMII2_FX100 :: Control2 :: pll_clk125_sw_en [09:09] */
#define Wr_SGMII2_FX100_Control2_pll_clk125_sw_en(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x200,9,x)
#define Rd_SGMII2_FX100_Control2_pll_clk125_sw_en(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x200,9)
#define SGMII2_FX100_CONTROL2_PLL_CLK125_SW_EN_MASK                0x0200
#define SGMII2_FX100_CONTROL2_PLL_CLK125_SW_EN_ALIGN               0
#define SGMII2_FX100_CONTROL2_PLL_CLK125_SW_EN_BITS                1
#define SGMII2_FX100_CONTROL2_PLL_CLK125_SW_EN_SHIFT               9

/* SGMII2_FX100 :: Control2 :: clk_out_1000_sw_def [08:08] */
#define Wr_SGMII2_FX100_Control2_clk_out_1000_sw_def(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x100,8,x)
#define Rd_SGMII2_FX100_Control2_clk_out_1000_sw_def(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x100,8)
#define SGMII2_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_MASK             0x0100
#define SGMII2_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_ALIGN            0
#define SGMII2_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_BITS             1
#define SGMII2_FX100_CONTROL2_CLK_OUT_1000_SW_DEF_SHIFT            8

/* SGMII2_FX100 :: Control2 :: clk_out_1000_sw_en [07:07] */
#define Wr_SGMII2_FX100_Control2_clk_out_1000_sw_en(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x80,7,x)
#define Rd_SGMII2_FX100_Control2_clk_out_1000_sw_en(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x80,7)
#define SGMII2_FX100_CONTROL2_CLK_OUT_1000_SW_EN_MASK              0x0080
#define SGMII2_FX100_CONTROL2_CLK_OUT_1000_SW_EN_ALIGN             0
#define SGMII2_FX100_CONTROL2_CLK_OUT_1000_SW_EN_BITS              1
#define SGMII2_FX100_CONTROL2_CLK_OUT_1000_SW_EN_SHIFT             7

/* SGMII2_FX100 :: Control2 :: mii_rxc_out_sw_ref [06:06] */
#define Wr_SGMII2_FX100_Control2_mii_rxc_out_sw_ref(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x40,6,x)
#define Rd_SGMII2_FX100_Control2_mii_rxc_out_sw_ref(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x40,6)
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SW_REF_MASK              0x0040
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SW_REF_ALIGN             0
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SW_REF_BITS              1
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SW_REF_SHIFT             6

/* SGMII2_FX100 :: Control2 :: mii_rxc_out_sw_en [05:05] */
#define Wr_SGMII2_FX100_Control2_mii_rxc_out_sw_en(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x20,5,x)
#define Rd_SGMII2_FX100_Control2_mii_rxc_out_sw_en(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x20,5)
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SW_EN_MASK               0x0020
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SW_EN_ALIGN              0
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SW_EN_BITS               1
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SW_EN_SHIFT              5

/* SGMII2_FX100 :: Control2 :: mii_rxc_out_sm_rst [04:04] */
#define Wr_SGMII2_FX100_Control2_mii_rxc_out_sm_rst(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x10,4,x)
#define Rd_SGMII2_FX100_Control2_mii_rxc_out_sm_rst(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x10,4)
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SM_RST_MASK              0x0010
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SM_RST_ALIGN             0
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SM_RST_BITS              1
#define SGMII2_FX100_CONTROL2_MII_RXC_OUT_SM_RST_SHIFT             4

/* SGMII2_FX100 :: Control2 :: mode_chg_nrst [03:03] */
#define Wr_SGMII2_FX100_Control2_mode_chg_nrst(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x8,3,x)
#define Rd_SGMII2_FX100_Control2_mode_chg_nrst(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x8,3)
#define SGMII2_FX100_CONTROL2_MODE_CHG_NRST_MASK                   0x0008
#define SGMII2_FX100_CONTROL2_MODE_CHG_NRST_ALIGN                  0
#define SGMII2_FX100_CONTROL2_MODE_CHG_NRST_BITS                   1
#define SGMII2_FX100_CONTROL2_MODE_CHG_NRST_SHIFT                  3

/* SGMII2_FX100 :: Control2 :: reset_rxfifo [02:02] */
#define Wr_SGMII2_FX100_Control2_reset_rxfifo(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x4,2,x)
#define Rd_SGMII2_FX100_Control2_reset_rxfifo(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x4,2)
#define SGMII2_FX100_CONTROL2_RESET_RXFIFO_MASK                    0x0004
#define SGMII2_FX100_CONTROL2_RESET_RXFIFO_ALIGN                   0
#define SGMII2_FX100_CONTROL2_RESET_RXFIFO_BITS                    1
#define SGMII2_FX100_CONTROL2_RESET_RXFIFO_SHIFT                   2

/* SGMII2_FX100 :: Control2 :: bypass_rxfifo [01:01] */
#define Wr_SGMII2_FX100_Control2_bypass_rxfifo(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x2,1,x)
#define Rd_SGMII2_FX100_Control2_bypass_rxfifo(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x2,1)
#define SGMII2_FX100_CONTROL2_BYPASS_RXFIFO_MASK                   0x0002
#define SGMII2_FX100_CONTROL2_BYPASS_RXFIFO_ALIGN                  0
#define SGMII2_FX100_CONTROL2_BYPASS_RXFIFO_BITS                   1
#define SGMII2_FX100_CONTROL2_BYPASS_RXFIFO_SHIFT                  1

/* SGMII2_FX100 :: Control2 :: extend_pkt_size [00:00] */
#define Wr_SGMII2_FX100_Control2_extend_pkt_size(x) WriteRegBits16(SGMII2_FX100_CONTROL2,0x1,0,x)
#define Rd_SGMII2_FX100_Control2_extend_pkt_size(x) ReadRegBits16(SGMII2_FX100_CONTROL2,0x1,0)
#define SGMII2_FX100_CONTROL2_EXTEND_PKT_SIZE_MASK                 0x0001
#define SGMII2_FX100_CONTROL2_EXTEND_PKT_SIZE_ALIGN                0
#define SGMII2_FX100_CONTROL2_EXTEND_PKT_SIZE_BITS                 1
#define SGMII2_FX100_CONTROL2_EXTEND_PKT_SIZE_SHIFT                0


/****************************************************************************
 * SGMII2_FX100 :: Control3
 ***************************************************************************/
/* SGMII2_FX100 :: Control3 :: number_of_idle [15:08] */
#define Wr_SGMII2_FX100_Control3_number_of_idle(x) WriteRegBits16(SGMII2_FX100_CONTROL3,0xff00,8,x)
#define Rd_SGMII2_FX100_Control3_number_of_idle(x) ReadRegBits16(SGMII2_FX100_CONTROL3,0xff00,8)
#define SGMII2_FX100_CONTROL3_NUMBER_OF_IDLE_MASK                  0xff00
#define SGMII2_FX100_CONTROL3_NUMBER_OF_IDLE_ALIGN                 0
#define SGMII2_FX100_CONTROL3_NUMBER_OF_IDLE_BITS                  8
#define SGMII2_FX100_CONTROL3_NUMBER_OF_IDLE_SHIFT                 8

/* SGMII2_FX100 :: Control3 :: correlator_disable [07:07] */
#define Wr_SGMII2_FX100_Control3_correlator_disable(x) WriteRegBits16(SGMII2_FX100_CONTROL3,0x80,7,x)
#define Rd_SGMII2_FX100_Control3_correlator_disable(x) ReadRegBits16(SGMII2_FX100_CONTROL3,0x80,7)
#define SGMII2_FX100_CONTROL3_CORRELATOR_DISABLE_MASK              0x0080
#define SGMII2_FX100_CONTROL3_CORRELATOR_DISABLE_ALIGN             0
#define SGMII2_FX100_CONTROL3_CORRELATOR_DISABLE_BITS              1
#define SGMII2_FX100_CONTROL3_CORRELATOR_DISABLE_SHIFT             7

/* SGMII2_FX100 :: Control3 :: bypass_nrz [06:06] */
#define Wr_SGMII2_FX100_Control3_bypass_nrz(x) WriteRegBits16(SGMII2_FX100_CONTROL3,0x40,6,x)
#define Rd_SGMII2_FX100_Control3_bypass_nrz(x) ReadRegBits16(SGMII2_FX100_CONTROL3,0x40,6)
#define SGMII2_FX100_CONTROL3_BYPASS_NRZ_MASK                      0x0040
#define SGMII2_FX100_CONTROL3_BYPASS_NRZ_ALIGN                     0
#define SGMII2_FX100_CONTROL3_BYPASS_NRZ_BITS                      1
#define SGMII2_FX100_CONTROL3_BYPASS_NRZ_SHIFT                     6

/* SGMII2_FX100 :: Control3 :: bypass_encoder [05:05] */
#define Wr_SGMII2_FX100_Control3_bypass_encoder(x) WriteRegBits16(SGMII2_FX100_CONTROL3,0x20,5,x)
#define Rd_SGMII2_FX100_Control3_bypass_encoder(x) ReadRegBits16(SGMII2_FX100_CONTROL3,0x20,5)
#define SGMII2_FX100_CONTROL3_BYPASS_ENCODER_MASK                  0x0020
#define SGMII2_FX100_CONTROL3_BYPASS_ENCODER_ALIGN                 0
#define SGMII2_FX100_CONTROL3_BYPASS_ENCODER_BITS                  1
#define SGMII2_FX100_CONTROL3_BYPASS_ENCODER_SHIFT                 5

/* SGMII2_FX100 :: Control3 :: bypass_alignment [04:04] */
#define Wr_SGMII2_FX100_Control3_bypass_alignment(x) WriteRegBits16(SGMII2_FX100_CONTROL3,0x10,4,x)
#define Rd_SGMII2_FX100_Control3_bypass_alignment(x) ReadRegBits16(SGMII2_FX100_CONTROL3,0x10,4)
#define SGMII2_FX100_CONTROL3_BYPASS_ALIGNMENT_MASK                0x0010
#define SGMII2_FX100_CONTROL3_BYPASS_ALIGNMENT_ALIGN               0
#define SGMII2_FX100_CONTROL3_BYPASS_ALIGNMENT_BITS                1
#define SGMII2_FX100_CONTROL3_BYPASS_ALIGNMENT_SHIFT               4

/* SGMII2_FX100 :: Control3 :: force_link [03:03] */
#define Wr_SGMII2_FX100_Control3_force_link(x) WriteRegBits16(SGMII2_FX100_CONTROL3,0x8,3,x)
#define Rd_SGMII2_FX100_Control3_force_link(x) ReadRegBits16(SGMII2_FX100_CONTROL3,0x8,3)
#define SGMII2_FX100_CONTROL3_FORCE_LINK_MASK                      0x0008
#define SGMII2_FX100_CONTROL3_FORCE_LINK_ALIGN                     0
#define SGMII2_FX100_CONTROL3_FORCE_LINK_BITS                      1
#define SGMII2_FX100_CONTROL3_FORCE_LINK_SHIFT                     3

/* SGMII2_FX100 :: Control3 :: force_lock [02:02] */
#define Wr_SGMII2_FX100_Control3_force_lock(x) WriteRegBits16(SGMII2_FX100_CONTROL3,0x4,2,x)
#define Rd_SGMII2_FX100_Control3_force_lock(x) ReadRegBits16(SGMII2_FX100_CONTROL3,0x4,2)
#define SGMII2_FX100_CONTROL3_FORCE_LOCK_MASK                      0x0004
#define SGMII2_FX100_CONTROL3_FORCE_LOCK_ALIGN                     0
#define SGMII2_FX100_CONTROL3_FORCE_LOCK_BITS                      1
#define SGMII2_FX100_CONTROL3_FORCE_LOCK_SHIFT                     2

/* SGMII2_FX100 :: Control3 :: fast_unlock_timer [01:01] */
#define Wr_SGMII2_FX100_Control3_fast_unlock_timer(x) WriteRegBits16(SGMII2_FX100_CONTROL3,0x2,1,x)
#define Rd_SGMII2_FX100_Control3_fast_unlock_timer(x) ReadRegBits16(SGMII2_FX100_CONTROL3,0x2,1)
#define SGMII2_FX100_CONTROL3_FAST_UNLOCK_TIMER_MASK               0x0002
#define SGMII2_FX100_CONTROL3_FAST_UNLOCK_TIMER_ALIGN              0
#define SGMII2_FX100_CONTROL3_FAST_UNLOCK_TIMER_BITS               1
#define SGMII2_FX100_CONTROL3_FAST_UNLOCK_TIMER_SHIFT              1

/* SGMII2_FX100 :: Control3 :: fast_timers [00:00] */
#define Wr_SGMII2_FX100_Control3_fast_timers(x) WriteRegBits16(SGMII2_FX100_CONTROL3,0x1,0,x)
#define Rd_SGMII2_FX100_Control3_fast_timers(x) ReadRegBits16(SGMII2_FX100_CONTROL3,0x1,0)
#define SGMII2_FX100_CONTROL3_FAST_TIMERS_MASK                     0x0001
#define SGMII2_FX100_CONTROL3_FAST_TIMERS_ALIGN                    0
#define SGMII2_FX100_CONTROL3_FAST_TIMERS_BITS                     1
#define SGMII2_FX100_CONTROL3_FAST_TIMERS_SHIFT                    0


/****************************************************************************
 * SGMII2_FX100 :: Status1
 ***************************************************************************/
/* SGMII2_FX100 :: Status1 :: mode_change [15:15] */
#define Wr_SGMII2_FX100_Status1_mode_change(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x8000,15,x)
#define Rd_SGMII2_FX100_Status1_mode_change(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x8000,15)
#define SGMII2_FX100_STATUS1_MODE_CHANGE_MASK                      0x8000
#define SGMII2_FX100_STATUS1_MODE_CHANGE_ALIGN                     0
#define SGMII2_FX100_STATUS1_MODE_CHANGE_BITS                      1
#define SGMII2_FX100_STATUS1_MODE_CHANGE_SHIFT                     15

/* SGMII2_FX100 :: Status1 :: reserved0 [14:12] */
#define SGMII2_FX100_STATUS1_RESERVED0_MASK                        0x7000
#define SGMII2_FX100_STATUS1_RESERVED0_ALIGN                       0
#define SGMII2_FX100_STATUS1_RESERVED0_BITS                        3
#define SGMII2_FX100_STATUS1_RESERVED0_SHIFT                       12

/* SGMII2_FX100 :: Status1 :: fiber_pwrdwn_status_chg [11:11] */
#define Wr_SGMII2_FX100_Status1_fiber_pwrdwn_status_chg(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x800,11,x)
#define Rd_SGMII2_FX100_Status1_fiber_pwrdwn_status_chg(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x800,11)
#define SGMII2_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_MASK          0x0800
#define SGMII2_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_ALIGN         0
#define SGMII2_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_BITS          1
#define SGMII2_FX100_STATUS1_FIBER_PWRDWN_STATUS_CHG_SHIFT         11

/* SGMII2_FX100 :: Status1 :: fiber_pwrdwn [10:10] */
#define Wr_SGMII2_FX100_Status1_fiber_pwrdwn(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x400,10,x)
#define Rd_SGMII2_FX100_Status1_fiber_pwrdwn(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x400,10)
#define SGMII2_FX100_STATUS1_FIBER_PWRDWN_MASK                     0x0400
#define SGMII2_FX100_STATUS1_FIBER_PWRDWN_ALIGN                    0
#define SGMII2_FX100_STATUS1_FIBER_PWRDWN_BITS                     1
#define SGMII2_FX100_STATUS1_FIBER_PWRDWN_SHIFT                    10

/* SGMII2_FX100 :: Status1 :: link_status_chg [09:09] */
#define Wr_SGMII2_FX100_Status1_link_status_chg(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x200,9,x)
#define Rd_SGMII2_FX100_Status1_link_status_chg(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x200,9)
#define SGMII2_FX100_STATUS1_LINK_STATUS_CHG_MASK                  0x0200
#define SGMII2_FX100_STATUS1_LINK_STATUS_CHG_ALIGN                 0
#define SGMII2_FX100_STATUS1_LINK_STATUS_CHG_BITS                  1
#define SGMII2_FX100_STATUS1_LINK_STATUS_CHG_SHIFT                 9

/* SGMII2_FX100 :: Status1 :: bad_esd_detected [08:08] */
#define Wr_SGMII2_FX100_Status1_bad_esd_detected(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x100,8,x)
#define Rd_SGMII2_FX100_Status1_bad_esd_detected(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x100,8)
#define SGMII2_FX100_STATUS1_BAD_ESD_DETECTED_MASK                 0x0100
#define SGMII2_FX100_STATUS1_BAD_ESD_DETECTED_ALIGN                0
#define SGMII2_FX100_STATUS1_BAD_ESD_DETECTED_BITS                 1
#define SGMII2_FX100_STATUS1_BAD_ESD_DETECTED_SHIFT                8

/* SGMII2_FX100 :: Status1 :: false_carrier_detected [07:07] */
#define Wr_SGMII2_FX100_Status1_false_carrier_detected(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x80,7,x)
#define Rd_SGMII2_FX100_Status1_false_carrier_detected(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x80,7)
#define SGMII2_FX100_STATUS1_FALSE_CARRIER_DETECTED_MASK           0x0080
#define SGMII2_FX100_STATUS1_FALSE_CARRIER_DETECTED_ALIGN          0
#define SGMII2_FX100_STATUS1_FALSE_CARRIER_DETECTED_BITS           1
#define SGMII2_FX100_STATUS1_FALSE_CARRIER_DETECTED_SHIFT          7

/* SGMII2_FX100 :: Status1 :: tx_err_detected [06:06] */
#define Wr_SGMII2_FX100_Status1_tx_err_detected(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x40,6,x)
#define Rd_SGMII2_FX100_Status1_tx_err_detected(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x40,6)
#define SGMII2_FX100_STATUS1_TX_ERR_DETECTED_MASK                  0x0040
#define SGMII2_FX100_STATUS1_TX_ERR_DETECTED_ALIGN                 0
#define SGMII2_FX100_STATUS1_TX_ERR_DETECTED_BITS                  1
#define SGMII2_FX100_STATUS1_TX_ERR_DETECTED_SHIFT                 6

/* SGMII2_FX100 :: Status1 :: rx_err_detected [05:05] */
#define Wr_SGMII2_FX100_Status1_rx_err_detected(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x20,5,x)
#define Rd_SGMII2_FX100_Status1_rx_err_detected(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x20,5)
#define SGMII2_FX100_STATUS1_RX_ERR_DETECTED_MASK                  0x0020
#define SGMII2_FX100_STATUS1_RX_ERR_DETECTED_ALIGN                 0
#define SGMII2_FX100_STATUS1_RX_ERR_DETECTED_BITS                  1
#define SGMII2_FX100_STATUS1_RX_ERR_DETECTED_SHIFT                 5

/* SGMII2_FX100 :: Status1 :: lock_timer_expired [04:04] */
#define Wr_SGMII2_FX100_Status1_lock_timer_expired(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x10,4,x)
#define Rd_SGMII2_FX100_Status1_lock_timer_expired(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x10,4)
#define SGMII2_FX100_STATUS1_LOCK_TIMER_EXPIRED_MASK               0x0010
#define SGMII2_FX100_STATUS1_LOCK_TIMER_EXPIRED_ALIGN              0
#define SGMII2_FX100_STATUS1_LOCK_TIMER_EXPIRED_BITS               1
#define SGMII2_FX100_STATUS1_LOCK_TIMER_EXPIRED_SHIFT              4

/* SGMII2_FX100 :: Status1 :: lost_lock [03:03] */
#define Wr_SGMII2_FX100_Status1_lost_lock(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x8,3,x)
#define Rd_SGMII2_FX100_Status1_lost_lock(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x8,3)
#define SGMII2_FX100_STATUS1_LOST_LOCK_MASK                        0x0008
#define SGMII2_FX100_STATUS1_LOST_LOCK_ALIGN                       0
#define SGMII2_FX100_STATUS1_LOST_LOCK_BITS                        1
#define SGMII2_FX100_STATUS1_LOST_LOCK_SHIFT                       3

/* SGMII2_FX100 :: Status1 :: faulting [02:02] */
#define Wr_SGMII2_FX100_Status1_faulting(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x4,2,x)
#define Rd_SGMII2_FX100_Status1_faulting(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x4,2)
#define SGMII2_FX100_STATUS1_FAULTING_MASK                         0x0004
#define SGMII2_FX100_STATUS1_FAULTING_ALIGN                        0
#define SGMII2_FX100_STATUS1_FAULTING_BITS                         1
#define SGMII2_FX100_STATUS1_FAULTING_SHIFT                        2

/* SGMII2_FX100 :: Status1 :: locked [01:01] */
#define Wr_SGMII2_FX100_Status1_locked(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x2,1,x)
#define Rd_SGMII2_FX100_Status1_locked(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x2,1)
#define SGMII2_FX100_STATUS1_LOCKED_MASK                           0x0002
#define SGMII2_FX100_STATUS1_LOCKED_ALIGN                          0
#define SGMII2_FX100_STATUS1_LOCKED_BITS                           1
#define SGMII2_FX100_STATUS1_LOCKED_SHIFT                          1

/* SGMII2_FX100 :: Status1 :: link [00:00] */
#define Wr_SGMII2_FX100_Status1_link(x) WriteRegBits16(SGMII2_FX100_STATUS1,0x1,0,x)
#define Rd_SGMII2_FX100_Status1_link(x) ReadRegBits16(SGMII2_FX100_STATUS1,0x1,0)
#define SGMII2_FX100_STATUS1_LINK_MASK                             0x0001
#define SGMII2_FX100_STATUS1_LINK_ALIGN                            0
#define SGMII2_FX100_STATUS1_LINK_BITS                             1
#define SGMII2_FX100_STATUS1_LINK_SHIFT                            0


/****************************************************************************
 * SGMII2_FX100 :: Status3
 ***************************************************************************/
/* SGMII2_FX100 :: Status3 :: linkmon_cntr [15:08] */
#define Wr_SGMII2_FX100_Status3_linkmon_cntr(x) WriteRegBits16(SGMII2_FX100_STATUS3,0xff00,8,x)
#define Rd_SGMII2_FX100_Status3_linkmon_cntr(x) ReadRegBits16(SGMII2_FX100_STATUS3,0xff00,8)
#define SGMII2_FX100_STATUS3_LINKMON_CNTR_MASK                     0xff00
#define SGMII2_FX100_STATUS3_LINKMON_CNTR_ALIGN                    0
#define SGMII2_FX100_STATUS3_LINKMON_CNTR_BITS                     8
#define SGMII2_FX100_STATUS3_LINKMON_CNTR_SHIFT                    8

/* SGMII2_FX100 :: Status3 :: reserved0 [07:07] */
#define SGMII2_FX100_STATUS3_RESERVED0_MASK                        0x0080
#define SGMII2_FX100_STATUS3_RESERVED0_ALIGN                       0
#define SGMII2_FX100_STATUS3_RESERVED0_BITS                        1
#define SGMII2_FX100_STATUS3_RESERVED0_SHIFT                       7

/* SGMII2_FX100 :: Status3 :: idles_detected_5b [06:06] */
#define Wr_SGMII2_FX100_Status3_idles_detected_5b(x) WriteRegBits16(SGMII2_FX100_STATUS3,0x40,6,x)
#define Rd_SGMII2_FX100_Status3_idles_detected_5b(x) ReadRegBits16(SGMII2_FX100_STATUS3,0x40,6)
#define SGMII2_FX100_STATUS3_IDLES_DETECTED_5B_MASK                0x0040
#define SGMII2_FX100_STATUS3_IDLES_DETECTED_5B_ALIGN               0
#define SGMII2_FX100_STATUS3_IDLES_DETECTED_5B_BITS                1
#define SGMII2_FX100_STATUS3_IDLES_DETECTED_5B_SHIFT               6

/* SGMII2_FX100 :: Status3 :: crs_ind_detected [05:05] */
#define Wr_SGMII2_FX100_Status3_crs_ind_detected(x) WriteRegBits16(SGMII2_FX100_STATUS3,0x20,5,x)
#define Rd_SGMII2_FX100_Status3_crs_ind_detected(x) ReadRegBits16(SGMII2_FX100_STATUS3,0x20,5)
#define SGMII2_FX100_STATUS3_CRS_IND_DETECTED_MASK                 0x0020
#define SGMII2_FX100_STATUS3_CRS_IND_DETECTED_ALIGN                0
#define SGMII2_FX100_STATUS3_CRS_IND_DETECTED_BITS                 1
#define SGMII2_FX100_STATUS3_CRS_IND_DETECTED_SHIFT                5

/* SGMII2_FX100 :: Status3 :: err_detected [04:04] */
#define Wr_SGMII2_FX100_Status3_err_detected(x) WriteRegBits16(SGMII2_FX100_STATUS3,0x10,4,x)
#define Rd_SGMII2_FX100_Status3_err_detected(x) ReadRegBits16(SGMII2_FX100_STATUS3,0x10,4)
#define SGMII2_FX100_STATUS3_ERR_DETECTED_MASK                     0x0010
#define SGMII2_FX100_STATUS3_ERR_DETECTED_ALIGN                    0
#define SGMII2_FX100_STATUS3_ERR_DETECTED_BITS                     1
#define SGMII2_FX100_STATUS3_ERR_DETECTED_SHIFT                    4

/* SGMII2_FX100 :: Status3 :: esd_detected [03:03] */
#define Wr_SGMII2_FX100_Status3_esd_detected(x) WriteRegBits16(SGMII2_FX100_STATUS3,0x8,3,x)
#define Rd_SGMII2_FX100_Status3_esd_detected(x) ReadRegBits16(SGMII2_FX100_STATUS3,0x8,3)
#define SGMII2_FX100_STATUS3_ESD_DETECTED_MASK                     0x0008
#define SGMII2_FX100_STATUS3_ESD_DETECTED_ALIGN                    0
#define SGMII2_FX100_STATUS3_ESD_DETECTED_BITS                     1
#define SGMII2_FX100_STATUS3_ESD_DETECTED_SHIFT                    3

/* SGMII2_FX100 :: Status3 :: ssd_detected [02:02] */
#define Wr_SGMII2_FX100_Status3_ssd_detected(x) WriteRegBits16(SGMII2_FX100_STATUS3,0x4,2,x)
#define Rd_SGMII2_FX100_Status3_ssd_detected(x) ReadRegBits16(SGMII2_FX100_STATUS3,0x4,2)
#define SGMII2_FX100_STATUS3_SSD_DETECTED_MASK                     0x0004
#define SGMII2_FX100_STATUS3_SSD_DETECTED_ALIGN                    0
#define SGMII2_FX100_STATUS3_SSD_DETECTED_BITS                     1
#define SGMII2_FX100_STATUS3_SSD_DETECTED_SHIFT                    2

/* SGMII2_FX100 :: Status3 :: ij_detected [01:01] */
#define Wr_SGMII2_FX100_Status3_ij_detected(x) WriteRegBits16(SGMII2_FX100_STATUS3,0x2,1,x)
#define Rd_SGMII2_FX100_Status3_ij_detected(x) ReadRegBits16(SGMII2_FX100_STATUS3,0x2,1)
#define SGMII2_FX100_STATUS3_IJ_DETECTED_MASK                      0x0002
#define SGMII2_FX100_STATUS3_IJ_DETECTED_ALIGN                     0
#define SGMII2_FX100_STATUS3_IJ_DETECTED_BITS                      1
#define SGMII2_FX100_STATUS3_IJ_DETECTED_SHIFT                     1

/* SGMII2_FX100 :: Status3 :: idles_detected [00:00] */
#define Wr_SGMII2_FX100_Status3_idles_detected(x) WriteRegBits16(SGMII2_FX100_STATUS3,0x1,0,x)
#define Rd_SGMII2_FX100_Status3_idles_detected(x) ReadRegBits16(SGMII2_FX100_STATUS3,0x1,0)
#define SGMII2_FX100_STATUS3_IDLES_DETECTED_MASK                   0x0001
#define SGMII2_FX100_STATUS3_IDLES_DETECTED_ALIGN                  0
#define SGMII2_FX100_STATUS3_IDLES_DETECTED_BITS                   1
#define SGMII2_FX100_STATUS3_IDLES_DETECTED_SHIFT                  0


/****************************************************************************
 * SGMII2_FX100 :: Status4
 ***************************************************************************/
/* SGMII2_FX100 :: Status4 :: reserved0 [15:15] */
#define SGMII2_FX100_STATUS4_RESERVED0_MASK                        0x8000
#define SGMII2_FX100_STATUS4_RESERVED0_ALIGN                       0
#define SGMII2_FX100_STATUS4_RESERVED0_BITS                        1
#define SGMII2_FX100_STATUS4_RESERVED0_SHIFT                       15

/* SGMII2_FX100 :: Status4 :: rx_badend [14:14] */
#define Wr_SGMII2_FX100_Status4_rx_badend(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x4000,14,x)
#define Rd_SGMII2_FX100_Status4_rx_badend(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x4000,14)
#define SGMII2_FX100_STATUS4_RX_BADEND_MASK                        0x4000
#define SGMII2_FX100_STATUS4_RX_BADEND_ALIGN                       0
#define SGMII2_FX100_STATUS4_RX_BADEND_BITS                        1
#define SGMII2_FX100_STATUS4_RX_BADEND_SHIFT                       14

/* SGMII2_FX100 :: Status4 :: rx_data [13:13] */
#define Wr_SGMII2_FX100_Status4_rx_data(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x2000,13,x)
#define Rd_SGMII2_FX100_Status4_rx_data(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x2000,13)
#define SGMII2_FX100_STATUS4_RX_DATA_MASK                          0x2000
#define SGMII2_FX100_STATUS4_RX_DATA_ALIGN                         0
#define SGMII2_FX100_STATUS4_RX_DATA_BITS                          1
#define SGMII2_FX100_STATUS4_RX_DATA_SHIFT                         13

/* SGMII2_FX100 :: Status4 :: rx_ssk [12:12] */
#define Wr_SGMII2_FX100_Status4_rx_ssk(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x1000,12,x)
#define Rd_SGMII2_FX100_Status4_rx_ssk(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x1000,12)
#define SGMII2_FX100_STATUS4_RX_SSK_MASK                           0x1000
#define SGMII2_FX100_STATUS4_RX_SSK_ALIGN                          0
#define SGMII2_FX100_STATUS4_RX_SSK_BITS                           1
#define SGMII2_FX100_STATUS4_RX_SSK_SHIFT                          12

/* SGMII2_FX100 :: Status4 :: rx_ssj [11:11] */
#define Wr_SGMII2_FX100_Status4_rx_ssj(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x800,11,x)
#define Rd_SGMII2_FX100_Status4_rx_ssj(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x800,11)
#define SGMII2_FX100_STATUS4_RX_SSJ_MASK                           0x0800
#define SGMII2_FX100_STATUS4_RX_SSJ_ALIGN                          0
#define SGMII2_FX100_STATUS4_RX_SSJ_BITS                           1
#define SGMII2_FX100_STATUS4_RX_SSJ_SHIFT                          11

/* SGMII2_FX100 :: Status4 :: rx_confirmk [10:10] */
#define Wr_SGMII2_FX100_Status4_rx_confirmk(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x400,10,x)
#define Rd_SGMII2_FX100_Status4_rx_confirmk(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x400,10)
#define SGMII2_FX100_STATUS4_RX_CONFIRMK_MASK                      0x0400
#define SGMII2_FX100_STATUS4_RX_CONFIRMK_ALIGN                     0
#define SGMII2_FX100_STATUS4_RX_CONFIRMK_BITS                      1
#define SGMII2_FX100_STATUS4_RX_CONFIRMK_SHIFT                     10

/* SGMII2_FX100 :: Status4 :: rx_badssd [09:09] */
#define Wr_SGMII2_FX100_Status4_rx_badssd(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x200,9,x)
#define Rd_SGMII2_FX100_Status4_rx_badssd(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x200,9)
#define SGMII2_FX100_STATUS4_RX_BADSSD_MASK                        0x0200
#define SGMII2_FX100_STATUS4_RX_BADSSD_ALIGN                       0
#define SGMII2_FX100_STATUS4_RX_BADSSD_BITS                        1
#define SGMII2_FX100_STATUS4_RX_BADSSD_SHIFT                       9

/* SGMII2_FX100 :: Status4 :: fx_linkfail [08:08] */
#define Wr_SGMII2_FX100_Status4_fx_linkfail(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x100,8,x)
#define Rd_SGMII2_FX100_Status4_fx_linkfail(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x100,8)
#define SGMII2_FX100_STATUS4_FX_LINKFAIL_MASK                      0x0100
#define SGMII2_FX100_STATUS4_FX_LINKFAIL_ALIGN                     0
#define SGMII2_FX100_STATUS4_FX_LINKFAIL_BITS                      1
#define SGMII2_FX100_STATUS4_FX_LINKFAIL_SHIFT                     8

/* SGMII2_FX100 :: Status4 :: tx_esr [07:07] */
#define Wr_SGMII2_FX100_Status4_tx_esr(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x80,7,x)
#define Rd_SGMII2_FX100_Status4_tx_esr(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x80,7)
#define SGMII2_FX100_STATUS4_TX_ESR_MASK                           0x0080
#define SGMII2_FX100_STATUS4_TX_ESR_ALIGN                          0
#define SGMII2_FX100_STATUS4_TX_ESR_BITS                           1
#define SGMII2_FX100_STATUS4_TX_ESR_SHIFT                          7

/* SGMII2_FX100 :: Status4 :: tx_est [06:06] */
#define Wr_SGMII2_FX100_Status4_tx_est(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x40,6,x)
#define Rd_SGMII2_FX100_Status4_tx_est(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x40,6)
#define SGMII2_FX100_STATUS4_TX_EST_MASK                           0x0040
#define SGMII2_FX100_STATUS4_TX_EST_ALIGN                          0
#define SGMII2_FX100_STATUS4_TX_EST_BITS                           1
#define SGMII2_FX100_STATUS4_TX_EST_SHIFT                          6

/* SGMII2_FX100 :: Status4 :: tx_terror [05:05] */
#define Wr_SGMII2_FX100_Status4_tx_terror(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x20,5,x)
#define Rd_SGMII2_FX100_Status4_tx_terror(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x20,5)
#define SGMII2_FX100_STATUS4_TX_TERROR_MASK                        0x0020
#define SGMII2_FX100_STATUS4_TX_TERROR_ALIGN                       0
#define SGMII2_FX100_STATUS4_TX_TERROR_BITS                        1
#define SGMII2_FX100_STATUS4_TX_TERROR_SHIFT                       5

/* SGMII2_FX100 :: Status4 :: tx_tdata [04:04] */
#define Wr_SGMII2_FX100_Status4_tx_tdata(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x10,4,x)
#define Rd_SGMII2_FX100_Status4_tx_tdata(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x10,4)
#define SGMII2_FX100_STATUS4_TX_TDATA_MASK                         0x0010
#define SGMII2_FX100_STATUS4_TX_TDATA_ALIGN                        0
#define SGMII2_FX100_STATUS4_TX_TDATA_BITS                         1
#define SGMII2_FX100_STATUS4_TX_TDATA_SHIFT                        4

/* SGMII2_FX100 :: Status4 :: tx_ssk [03:03] */
#define Wr_SGMII2_FX100_Status4_tx_ssk(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x8,3,x)
#define Rd_SGMII2_FX100_Status4_tx_ssk(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x8,3)
#define SGMII2_FX100_STATUS4_TX_SSK_MASK                           0x0008
#define SGMII2_FX100_STATUS4_TX_SSK_ALIGN                          0
#define SGMII2_FX100_STATUS4_TX_SSK_BITS                           1
#define SGMII2_FX100_STATUS4_TX_SSK_SHIFT                          3

/* SGMII2_FX100 :: Status4 :: tx_sek [02:02] */
#define Wr_SGMII2_FX100_Status4_tx_sek(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x4,2,x)
#define Rd_SGMII2_FX100_Status4_tx_sek(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x4,2)
#define SGMII2_FX100_STATUS4_TX_SEK_MASK                           0x0004
#define SGMII2_FX100_STATUS4_TX_SEK_ALIGN                          0
#define SGMII2_FX100_STATUS4_TX_SEK_BITS                           1
#define SGMII2_FX100_STATUS4_TX_SEK_SHIFT                          2

/* SGMII2_FX100 :: Status4 :: tx_ssj [01:01] */
#define Wr_SGMII2_FX100_Status4_tx_ssj(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x2,1,x)
#define Rd_SGMII2_FX100_Status4_tx_ssj(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x2,1)
#define SGMII2_FX100_STATUS4_TX_SSJ_MASK                           0x0002
#define SGMII2_FX100_STATUS4_TX_SSJ_ALIGN                          0
#define SGMII2_FX100_STATUS4_TX_SSJ_BITS                           1
#define SGMII2_FX100_STATUS4_TX_SSJ_SHIFT                          1

/* SGMII2_FX100 :: Status4 :: tx_sej [00:00] */
#define Wr_SGMII2_FX100_Status4_tx_sej(x) WriteRegBits16(SGMII2_FX100_STATUS4,0x1,0,x)
#define Rd_SGMII2_FX100_Status4_tx_sej(x) ReadRegBits16(SGMII2_FX100_STATUS4,0x1,0)
#define SGMII2_FX100_STATUS4_TX_SEJ_MASK                           0x0001
#define SGMII2_FX100_STATUS4_TX_SEJ_ALIGN                          0
#define SGMII2_FX100_STATUS4_TX_SEJ_BITS                           1
#define SGMII2_FX100_STATUS4_TX_SEJ_SHIFT                          0


/****************************************************************************
 * SGMII2_FX100 :: fx100Idle1
 ***************************************************************************/
/* SGMII2_FX100 :: fx100Idle1 :: reserved0 [15:10] */
#define SGMII2_FX100_FX100IDLE1_RESERVED0_MASK                     0xfc00
#define SGMII2_FX100_FX100IDLE1_RESERVED0_ALIGN                    0
#define SGMII2_FX100_FX100IDLE1_RESERVED0_BITS                     6
#define SGMII2_FX100_FX100IDLE1_RESERVED0_SHIFT                    10

/* SGMII2_FX100 :: fx100Idle1 :: fx100_idle1 [09:00] */
#define Wr_SGMII2_FX100_fx100Idle1_fx100_idle1(x) WriteRegBits16(SGMII2_FX100_FX100IDLE1,0x3ff,0,x)
#define Rd_SGMII2_FX100_fx100Idle1_fx100_idle1(x) ReadRegBits16(SGMII2_FX100_FX100IDLE1,0x3ff,0)
#define SGMII2_FX100_FX100IDLE1_FX100_IDLE1_MASK                   0x03ff
#define SGMII2_FX100_FX100IDLE1_FX100_IDLE1_ALIGN                  0
#define SGMII2_FX100_FX100IDLE1_FX100_IDLE1_BITS                   10
#define SGMII2_FX100_FX100IDLE1_FX100_IDLE1_SHIFT                  0


/****************************************************************************
 * SGMII2_FX100 :: fx100idle2
 ***************************************************************************/
/* SGMII2_FX100 :: fx100idle2 :: reserved0 [15:10] */
#define SGMII2_FX100_FX100IDLE2_RESERVED0_MASK                     0xfc00
#define SGMII2_FX100_FX100IDLE2_RESERVED0_ALIGN                    0
#define SGMII2_FX100_FX100IDLE2_RESERVED0_BITS                     6
#define SGMII2_FX100_FX100IDLE2_RESERVED0_SHIFT                    10

/* SGMII2_FX100 :: fx100idle2 :: fx100_idle2 [09:00] */
#define Wr_SGMII2_FX100_fx100idle2_fx100_idle2(x) WriteRegBits16(SGMII2_FX100_FX100IDLE2,0x3ff,0,x)
#define Rd_SGMII2_FX100_fx100idle2_fx100_idle2(x) ReadRegBits16(SGMII2_FX100_FX100IDLE2,0x3ff,0)
#define SGMII2_FX100_FX100IDLE2_FX100_IDLE2_MASK                   0x03ff
#define SGMII2_FX100_FX100IDLE2_FX100_IDLE2_ALIGN                  0
#define SGMII2_FX100_FX100IDLE2_FX100_IDLE2_BITS                   10
#define SGMII2_FX100_FX100IDLE2_FX100_IDLE2_SHIFT                  0


/****************************************************************************
 * SGMII2_FX100 :: fx100IdleStatus
 ***************************************************************************/
/* SGMII2_FX100 :: fx100IdleStatus :: reserved0 [15:07] */
#define SGMII2_FX100_FX100IDLESTATUS_RESERVED0_MASK                0xff80
#define SGMII2_FX100_FX100IDLESTATUS_RESERVED0_ALIGN               0
#define SGMII2_FX100_FX100IDLESTATUS_RESERVED0_BITS                9
#define SGMII2_FX100_FX100IDLESTATUS_RESERVED0_SHIFT               7

/* SGMII2_FX100 :: fx100IdleStatus :: fx100_idleCorr_cnt [06:00] */
#define Wr_SGMII2_FX100_fx100IdleStatus_fx100_idleCorr_cnt(x) WriteRegBits16(SGMII2_FX100_FX100IDLESTATUS,0x7f,0,x)
#define Rd_SGMII2_FX100_fx100IdleStatus_fx100_idleCorr_cnt(x) ReadRegBits16(SGMII2_FX100_FX100IDLESTATUS,0x7f,0)
#define SGMII2_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_MASK       0x007f
#define SGMII2_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_ALIGN      0
#define SGMII2_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_BITS       7
#define SGMII2_FX100_FX100IDLESTATUS_FX100_IDLECORR_CNT_SHIFT      0


/****************************************************************************
 * SGMII2_FX100 :: fx100IdleThres
 ***************************************************************************/
/* SGMII2_FX100 :: fx100IdleThres :: reserved0 [15:14] */
#define SGMII2_FX100_FX100IDLETHRES_RESERVED0_MASK                 0xc000
#define SGMII2_FX100_FX100IDLETHRES_RESERVED0_ALIGN                0
#define SGMII2_FX100_FX100IDLETHRES_RESERVED0_BITS                 2
#define SGMII2_FX100_FX100IDLETHRES_RESERVED0_SHIFT                14

/* SGMII2_FX100 :: fx100IdleThres :: fx100_idle_min_thres [13:07] */
#define Wr_SGMII2_FX100_fx100IdleThres_fx100_idle_min_thres(x) WriteRegBits16(SGMII2_FX100_FX100IDLETHRES,0x3f80,7,x)
#define Rd_SGMII2_FX100_fx100IdleThres_fx100_idle_min_thres(x) ReadRegBits16(SGMII2_FX100_FX100IDLETHRES,0x3f80,7)
#define SGMII2_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_MASK      0x3f80
#define SGMII2_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_ALIGN     0
#define SGMII2_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_BITS      7
#define SGMII2_FX100_FX100IDLETHRES_FX100_IDLE_MIN_THRES_SHIFT     7

/* SGMII2_FX100 :: fx100IdleThres :: fx100_idle_max_thres [06:00] */
#define Wr_SGMII2_FX100_fx100IdleThres_fx100_idle_max_thres(x) WriteRegBits16(SGMII2_FX100_FX100IDLETHRES,0x7f,0,x)
#define Rd_SGMII2_FX100_fx100IdleThres_fx100_idle_max_thres(x) ReadRegBits16(SGMII2_FX100_FX100IDLETHRES,0x7f,0)
#define SGMII2_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_MASK      0x007f
#define SGMII2_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_ALIGN     0
#define SGMII2_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_BITS      7
#define SGMII2_FX100_FX100IDLETHRES_FX100_IDLE_MAX_THRES_SHIFT     0


/****************************************************************************
 * SGMII2_FX100 :: fx100LockTmr
 ***************************************************************************/
/* SGMII2_FX100 :: fx100LockTmr :: fx100_lock_thres [15:12] */
#define Wr_SGMII2_FX100_fx100LockTmr_fx100_lock_thres(x) WriteRegBits16(SGMII2_FX100_FX100LOCKTMR,0xf000,12,x)
#define Rd_SGMII2_FX100_fx100LockTmr_fx100_lock_thres(x) ReadRegBits16(SGMII2_FX100_FX100LOCKTMR,0xf000,12)
#define SGMII2_FX100_FX100LOCKTMR_FX100_LOCK_THRES_MASK            0xf000
#define SGMII2_FX100_FX100LOCKTMR_FX100_LOCK_THRES_ALIGN           0
#define SGMII2_FX100_FX100LOCKTMR_FX100_LOCK_THRES_BITS            4
#define SGMII2_FX100_FX100LOCKTMR_FX100_LOCK_THRES_SHIFT           12

/* SGMII2_FX100 :: fx100LockTmr :: fx100_unlock_thres [11:08] */
#define Wr_SGMII2_FX100_fx100LockTmr_fx100_unlock_thres(x) WriteRegBits16(SGMII2_FX100_FX100LOCKTMR,0xf00,8,x)
#define Rd_SGMII2_FX100_fx100LockTmr_fx100_unlock_thres(x) ReadRegBits16(SGMII2_FX100_FX100LOCKTMR,0xf00,8)
#define SGMII2_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_MASK          0x0f00
#define SGMII2_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_ALIGN         0
#define SGMII2_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_BITS          4
#define SGMII2_FX100_FX100LOCKTMR_FX100_UNLOCK_THRES_SHIFT         8

/* SGMII2_FX100 :: fx100LockTmr :: fx100_lock_maxtime [07:00] */
#define Wr_SGMII2_FX100_fx100LockTmr_fx100_lock_maxtime(x) WriteRegBits16(SGMII2_FX100_FX100LOCKTMR,0xff,0,x)
#define Rd_SGMII2_FX100_fx100LockTmr_fx100_lock_maxtime(x) ReadRegBits16(SGMII2_FX100_FX100LOCKTMR,0xff,0)
#define SGMII2_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_MASK          0x00ff
#define SGMII2_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_ALIGN         0
#define SGMII2_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_BITS          8
#define SGMII2_FX100_FX100LOCKTMR_FX100_LOCK_MAXTIME_SHIFT         0


/****************************************************************************
 * SGMII2_FX100 :: fx100LinkTmr
 ***************************************************************************/
/* SGMII2_FX100 :: fx100LinkTmr :: fx100_linkup_count [15:08] */
#define Wr_SGMII2_FX100_fx100LinkTmr_fx100_linkup_count(x) WriteRegBits16(SGMII2_FX100_FX100LINKTMR,0xff00,8,x)
#define Rd_SGMII2_FX100_fx100LinkTmr_fx100_linkup_count(x) ReadRegBits16(SGMII2_FX100_FX100LINKTMR,0xff00,8)
#define SGMII2_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_MASK          0xff00
#define SGMII2_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_ALIGN         0
#define SGMII2_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_BITS          8
#define SGMII2_FX100_FX100LINKTMR_FX100_LINKUP_COUNT_SHIFT         8

/* SGMII2_FX100 :: fx100LinkTmr :: fx100_linkdn_count [07:00] */
#define Wr_SGMII2_FX100_fx100LinkTmr_fx100_linkdn_count(x) WriteRegBits16(SGMII2_FX100_FX100LINKTMR,0xff,0,x)
#define Rd_SGMII2_FX100_fx100LinkTmr_fx100_linkdn_count(x) ReadRegBits16(SGMII2_FX100_FX100LINKTMR,0xff,0)
#define SGMII2_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_MASK          0x00ff
#define SGMII2_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_ALIGN         0
#define SGMII2_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_BITS          8
#define SGMII2_FX100_FX100LINKTMR_FX100_LINKDN_COUNT_SHIFT         0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_RX2
 ***************************************************************************/
/****************************************************************************
 * SGMII2_RX2 :: rxseq0
 ***************************************************************************/
/* SGMII2_RX2 :: rxseq0 :: cdrLockTimeTrckNrml_SM [15:08] */
#define Wr_SGMII2_RX2_rxseq0_cdrLockTimeTrckNrml_SM(x) WriteRegBits16(SGMII2_RX2_RXSEQ0,0xff00,8,x)
#define Rd_SGMII2_RX2_rxseq0_cdrLockTimeTrckNrml_SM(x) ReadRegBits16(SGMII2_RX2_RXSEQ0,0xff00,8)
#define SGMII2_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_MASK              0xff00
#define SGMII2_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_ALIGN             0
#define SGMII2_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_BITS              8
#define SGMII2_RX2_RXSEQ0_CDRLOCKTIMETRCKNRML_SM_SHIFT             8

/* SGMII2_RX2 :: rxseq0 :: cdrLockTimeAcq_S1_SM [07:00] */
#define Wr_SGMII2_RX2_rxseq0_cdrLockTimeAcq_S1_SM(x) WriteRegBits16(SGMII2_RX2_RXSEQ0,0xff,0,x)
#define Rd_SGMII2_RX2_rxseq0_cdrLockTimeAcq_S1_SM(x) ReadRegBits16(SGMII2_RX2_RXSEQ0,0xff,0)
#define SGMII2_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_MASK                0x00ff
#define SGMII2_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_ALIGN               0
#define SGMII2_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_BITS                8
#define SGMII2_RX2_RXSEQ0_CDRLOCKTIMEACQ_S1_SM_SHIFT               0


/****************************************************************************
 * SGMII2_RX2 :: rxseq1
 ***************************************************************************/
/* SGMII2_RX2 :: rxseq1 :: cdrLockTimeAcq_S2_SM [15:08] */
#define Wr_SGMII2_RX2_rxseq1_cdrLockTimeAcq_S2_SM(x) WriteRegBits16(SGMII2_RX2_RXSEQ1,0xff00,8,x)
#define Rd_SGMII2_RX2_rxseq1_cdrLockTimeAcq_S2_SM(x) ReadRegBits16(SGMII2_RX2_RXSEQ1,0xff00,8)
#define SGMII2_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_MASK                0xff00
#define SGMII2_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_ALIGN               0
#define SGMII2_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_BITS                8
#define SGMII2_RX2_RXSEQ1_CDRLOCKTIMEACQ_S2_SM_SHIFT               8

/* SGMII2_RX2 :: rxseq1 :: cdrLockTimeAcq_S3_SM [07:00] */
#define Wr_SGMII2_RX2_rxseq1_cdrLockTimeAcq_S3_SM(x) WriteRegBits16(SGMII2_RX2_RXSEQ1,0xff,0,x)
#define Rd_SGMII2_RX2_rxseq1_cdrLockTimeAcq_S3_SM(x) ReadRegBits16(SGMII2_RX2_RXSEQ1,0xff,0)
#define SGMII2_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_MASK                0x00ff
#define SGMII2_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_ALIGN               0
#define SGMII2_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_BITS                8
#define SGMII2_RX2_RXSEQ1_CDRLOCKTIMEACQ_S3_SM_SHIFT               0


/****************************************************************************
 * SGMII2_RX2 :: rxcdr0
 ***************************************************************************/
/* SGMII2_RX2 :: rxcdr0 :: sigdetTime_SM [15:12] */
#define Wr_SGMII2_RX2_rxcdr0_sigdetTime_SM(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0xf000,12,x)
#define Rd_SGMII2_RX2_rxcdr0_sigdetTime_SM(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0xf000,12)
#define SGMII2_RX2_RXCDR0_SIGDETTIME_SM_MASK                       0xf000
#define SGMII2_RX2_RXCDR0_SIGDETTIME_SM_ALIGN                      0
#define SGMII2_RX2_RXCDR0_SIGDETTIME_SM_BITS                       4
#define SGMII2_RX2_RXCDR0_SIGDETTIME_SM_SHIFT                      12

/* SGMII2_RX2 :: rxcdr0 :: em_phase_shift_360_ovrd_val [11:11] */
#define Wr_SGMII2_RX2_rxcdr0_em_phase_shift_360_ovrd_val(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x800,11,x)
#define Rd_SGMII2_RX2_rxcdr0_em_phase_shift_360_ovrd_val(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x800,11)
#define SGMII2_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_MASK         0x0800
#define SGMII2_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_ALIGN        0
#define SGMII2_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_BITS         1
#define SGMII2_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_VAL_SHIFT        11

/* SGMII2_RX2 :: rxcdr0 :: em_phase_shift_360_ovrd [10:10] */
#define Wr_SGMII2_RX2_rxcdr0_em_phase_shift_360_ovrd(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x400,10,x)
#define Rd_SGMII2_RX2_rxcdr0_em_phase_shift_360_ovrd(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x400,10)
#define SGMII2_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_MASK             0x0400
#define SGMII2_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_ALIGN            0
#define SGMII2_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_BITS             1
#define SGMII2_RX2_RXCDR0_EM_PHASE_SHIFT_360_OVRD_SHIFT            10

/* SGMII2_RX2 :: rxcdr0 :: rx_interp_ctrl_cap [09:09] */
#define Wr_SGMII2_RX2_rxcdr0_rx_interp_ctrl_cap(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x200,9,x)
#define Rd_SGMII2_RX2_rxcdr0_rx_interp_ctrl_cap(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x200,9)
#define SGMII2_RX2_RXCDR0_RX_INTERP_CTRL_CAP_MASK                  0x0200
#define SGMII2_RX2_RXCDR0_RX_INTERP_CTRL_CAP_ALIGN                 0
#define SGMII2_RX2_RXCDR0_RX_INTERP_CTRL_CAP_BITS                  1
#define SGMII2_RX2_RXCDR0_RX_INTERP_CTRL_CAP_SHIFT                 9

/* SGMII2_RX2 :: rxcdr0 :: rx_interp_status_sel [08:06] */
#define Wr_SGMII2_RX2_rxcdr0_rx_interp_status_sel(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x1c0,6,x)
#define Rd_SGMII2_RX2_rxcdr0_rx_interp_status_sel(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x1c0,6)
#define SGMII2_RX2_RXCDR0_RX_INTERP_STATUS_SEL_MASK                0x01c0
#define SGMII2_RX2_RXCDR0_RX_INTERP_STATUS_SEL_ALIGN               0
#define SGMII2_RX2_RXCDR0_RX_INTERP_STATUS_SEL_BITS                3
#define SGMII2_RX2_RXCDR0_RX_INTERP_STATUS_SEL_SHIFT               6

/* SGMII2_RX2 :: rxcdr0 :: pi_clk90_offset_override [05:05] */
#define Wr_SGMII2_RX2_rxcdr0_pi_clk90_offset_override(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x20,5,x)
#define Rd_SGMII2_RX2_rxcdr0_pi_clk90_offset_override(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x20,5)
#define SGMII2_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_MASK            0x0020
#define SGMII2_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_ALIGN           0
#define SGMII2_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_BITS            1
#define SGMII2_RX2_RXCDR0_PI_CLK90_OFFSET_OVERRIDE_SHIFT           5

/* SGMII2_RX2 :: rxcdr0 :: pi_phase_rotate_override [04:04] */
#define Wr_SGMII2_RX2_rxcdr0_pi_phase_rotate_override(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x10,4,x)
#define Rd_SGMII2_RX2_rxcdr0_pi_phase_rotate_override(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x10,4)
#define SGMII2_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_MASK            0x0010
#define SGMII2_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_ALIGN           0
#define SGMII2_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_BITS            1
#define SGMII2_RX2_RXCDR0_PI_PHASE_ROTATE_OVERRIDE_SHIFT           4

/* SGMII2_RX2 :: rxcdr0 :: mdio_em_err_cnt_clr [03:03] */
#define Wr_SGMII2_RX2_rxcdr0_mdio_em_err_cnt_clr(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x8,3,x)
#define Rd_SGMII2_RX2_rxcdr0_mdio_em_err_cnt_clr(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x8,3)
#define SGMII2_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_MASK                 0x0008
#define SGMII2_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_ALIGN                0
#define SGMII2_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_BITS                 1
#define SGMII2_RX2_RXCDR0_MDIO_EM_ERR_CNT_CLR_SHIFT                3

/* SGMII2_RX2 :: rxcdr0 :: mdio_em_err_cnt_frz [02:02] */
#define Wr_SGMII2_RX2_rxcdr0_mdio_em_err_cnt_frz(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x4,2,x)
#define Rd_SGMII2_RX2_rxcdr0_mdio_em_err_cnt_frz(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x4,2)
#define SGMII2_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_MASK                 0x0004
#define SGMII2_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_ALIGN                0
#define SGMII2_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_BITS                 1
#define SGMII2_RX2_RXCDR0_MDIO_EM_ERR_CNT_FRZ_SHIFT                2

/* SGMII2_RX2 :: rxcdr0 :: mdio_em_pwrdn [01:01] */
#define Wr_SGMII2_RX2_rxcdr0_mdio_em_pwrdn(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x2,1,x)
#define Rd_SGMII2_RX2_rxcdr0_mdio_em_pwrdn(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x2,1)
#define SGMII2_RX2_RXCDR0_MDIO_EM_PWRDN_MASK                       0x0002
#define SGMII2_RX2_RXCDR0_MDIO_EM_PWRDN_ALIGN                      0
#define SGMII2_RX2_RXCDR0_MDIO_EM_PWRDN_BITS                       1
#define SGMII2_RX2_RXCDR0_MDIO_EM_PWRDN_SHIFT                      1

/* SGMII2_RX2 :: rxcdr0 :: pi_phase_invert [00:00] */
#define Wr_SGMII2_RX2_rxcdr0_pi_phase_invert(x) WriteRegBits16(SGMII2_RX2_RXCDR0,0x1,0,x)
#define Rd_SGMII2_RX2_rxcdr0_pi_phase_invert(x) ReadRegBits16(SGMII2_RX2_RXCDR0,0x1,0)
#define SGMII2_RX2_RXCDR0_PI_PHASE_INVERT_MASK                     0x0001
#define SGMII2_RX2_RXCDR0_PI_PHASE_INVERT_ALIGN                    0
#define SGMII2_RX2_RXCDR0_PI_PHASE_INVERT_BITS                     1
#define SGMII2_RX2_RXCDR0_PI_PHASE_INVERT_SHIFT                    0


/****************************************************************************
 * SGMII2_RX2 :: rxcdr1
 ***************************************************************************/
/* SGMII2_RX2 :: rxcdr1 :: reserved0 [15:13] */
#define SGMII2_RX2_RXCDR1_RESERVED0_MASK                           0xe000
#define SGMII2_RX2_RXCDR1_RESERVED0_ALIGN                          0
#define SGMII2_RX2_RXCDR1_RESERVED0_BITS                           3
#define SGMII2_RX2_RXCDR1_RESERVED0_SHIFT                          13

/* SGMII2_RX2 :: rxcdr1 :: step_two [12:11] */
#define Wr_SGMII2_RX2_rxcdr1_step_two(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x1800,11,x)
#define Rd_SGMII2_RX2_rxcdr1_step_two(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x1800,11)
#define SGMII2_RX2_RXCDR1_STEP_TWO_MASK                            0x1800
#define SGMII2_RX2_RXCDR1_STEP_TWO_ALIGN                           0
#define SGMII2_RX2_RXCDR1_STEP_TWO_BITS                            2
#define SGMII2_RX2_RXCDR1_STEP_TWO_SHIFT                           11

/* SGMII2_RX2 :: rxcdr1 :: step_one [10:09] */
#define Wr_SGMII2_RX2_rxcdr1_step_one(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x600,9,x)
#define Rd_SGMII2_RX2_rxcdr1_step_one(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x600,9)
#define SGMII2_RX2_RXCDR1_STEP_ONE_MASK                            0x0600
#define SGMII2_RX2_RXCDR1_STEP_ONE_ALIGN                           0
#define SGMII2_RX2_RXCDR1_STEP_ONE_BITS                            2
#define SGMII2_RX2_RXCDR1_STEP_ONE_SHIFT                           9

/* SGMII2_RX2 :: rxcdr1 :: flip_zero_polarity [08:08] */
#define Wr_SGMII2_RX2_rxcdr1_flip_zero_polarity(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x100,8,x)
#define Rd_SGMII2_RX2_rxcdr1_flip_zero_polarity(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x100,8)
#define SGMII2_RX2_RXCDR1_FLIP_ZERO_POLARITY_MASK                  0x0100
#define SGMII2_RX2_RXCDR1_FLIP_ZERO_POLARITY_ALIGN                 0
#define SGMII2_RX2_RXCDR1_FLIP_ZERO_POLARITY_BITS                  1
#define SGMII2_RX2_RXCDR1_FLIP_ZERO_POLARITY_SHIFT                 8

/* SGMII2_RX2 :: rxcdr1 :: flip_peak_polarity [07:07] */
#define Wr_SGMII2_RX2_rxcdr1_flip_peak_polarity(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x80,7,x)
#define Rd_SGMII2_RX2_rxcdr1_flip_peak_polarity(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x80,7)
#define SGMII2_RX2_RXCDR1_FLIP_PEAK_POLARITY_MASK                  0x0080
#define SGMII2_RX2_RXCDR1_FLIP_PEAK_POLARITY_ALIGN                 0
#define SGMII2_RX2_RXCDR1_FLIP_PEAK_POLARITY_BITS                  1
#define SGMII2_RX2_RXCDR1_FLIP_PEAK_POLARITY_SHIFT                 7

/* SGMII2_RX2 :: rxcdr1 :: rising_edge [06:06] */
#define Wr_SGMII2_RX2_rxcdr1_rising_edge(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x40,6,x)
#define Rd_SGMII2_RX2_rxcdr1_rising_edge(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x40,6)
#define SGMII2_RX2_RXCDR1_RISING_EDGE_MASK                         0x0040
#define SGMII2_RX2_RXCDR1_RISING_EDGE_ALIGN                        0
#define SGMII2_RX2_RXCDR1_RISING_EDGE_BITS                         1
#define SGMII2_RX2_RXCDR1_RISING_EDGE_SHIFT                        6

/* SGMII2_RX2 :: rxcdr1 :: falling_edge [05:05] */
#define Wr_SGMII2_RX2_rxcdr1_falling_edge(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x20,5,x)
#define Rd_SGMII2_RX2_rxcdr1_falling_edge(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x20,5)
#define SGMII2_RX2_RXCDR1_FALLING_EDGE_MASK                        0x0020
#define SGMII2_RX2_RXCDR1_FALLING_EDGE_ALIGN                       0
#define SGMII2_RX2_RXCDR1_FALLING_EDGE_BITS                        1
#define SGMII2_RX2_RXCDR1_FALLING_EDGE_SHIFT                       5

/* SGMII2_RX2 :: rxcdr1 :: freq_upd_en [04:04] */
#define Wr_SGMII2_RX2_rxcdr1_freq_upd_en(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x10,4,x)
#define Rd_SGMII2_RX2_rxcdr1_freq_upd_en(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x10,4)
#define SGMII2_RX2_RXCDR1_FREQ_UPD_EN_MASK                         0x0010
#define SGMII2_RX2_RXCDR1_FREQ_UPD_EN_ALIGN                        0
#define SGMII2_RX2_RXCDR1_FREQ_UPD_EN_BITS                         1
#define SGMII2_RX2_RXCDR1_FREQ_UPD_EN_SHIFT                        4

/* SGMII2_RX2 :: rxcdr1 :: phase_delta [03:03] */
#define Wr_SGMII2_RX2_rxcdr1_phase_delta(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x8,3,x)
#define Rd_SGMII2_RX2_rxcdr1_phase_delta(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x8,3)
#define SGMII2_RX2_RXCDR1_PHASE_DELTA_MASK                         0x0008
#define SGMII2_RX2_RXCDR1_PHASE_DELTA_ALIGN                        0
#define SGMII2_RX2_RXCDR1_PHASE_DELTA_BITS                         1
#define SGMII2_RX2_RXCDR1_PHASE_DELTA_SHIFT                        3

/* SGMII2_RX2 :: rxcdr1 :: phs_counter_clr [02:02] */
#define Wr_SGMII2_RX2_rxcdr1_phs_counter_clr(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x4,2,x)
#define Rd_SGMII2_RX2_rxcdr1_phs_counter_clr(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x4,2)
#define SGMII2_RX2_RXCDR1_PHS_COUNTER_CLR_MASK                     0x0004
#define SGMII2_RX2_RXCDR1_PHS_COUNTER_CLR_ALIGN                    0
#define SGMII2_RX2_RXCDR1_PHS_COUNTER_CLR_BITS                     1
#define SGMII2_RX2_RXCDR1_PHS_COUNTER_CLR_SHIFT                    2

/* SGMII2_RX2 :: rxcdr1 :: phase_sat_ctrl [01:00] */
#define Wr_SGMII2_RX2_rxcdr1_phase_sat_ctrl(x) WriteRegBits16(SGMII2_RX2_RXCDR1,0x3,0,x)
#define Rd_SGMII2_RX2_rxcdr1_phase_sat_ctrl(x) ReadRegBits16(SGMII2_RX2_RXCDR1,0x3,0)
#define SGMII2_RX2_RXCDR1_PHASE_SAT_CTRL_MASK                      0x0003
#define SGMII2_RX2_RXCDR1_PHASE_SAT_CTRL_ALIGN                     0
#define SGMII2_RX2_RXCDR1_PHASE_SAT_CTRL_BITS                      2
#define SGMII2_RX2_RXCDR1_PHASE_SAT_CTRL_SHIFT                     0


/****************************************************************************
 * SGMII2_RX2 :: rxcdr2
 ***************************************************************************/
/* SGMII2_RX2 :: rxcdr2 :: reserved0 [15:14] */
#define SGMII2_RX2_RXCDR2_RESERVED0_MASK                           0xc000
#define SGMII2_RX2_RXCDR2_RESERVED0_ALIGN                          0
#define SGMII2_RX2_RXCDR2_RESERVED0_BITS                           2
#define SGMII2_RX2_RXCDR2_RESERVED0_SHIFT                          14

/* SGMII2_RX2 :: rxcdr2 :: phsacq_enable [13:13] */
#define Wr_SGMII2_RX2_rxcdr2_phsacq_enable(x) WriteRegBits16(SGMII2_RX2_RXCDR2,0x2000,13,x)
#define Rd_SGMII2_RX2_rxcdr2_phsacq_enable(x) ReadRegBits16(SGMII2_RX2_RXCDR2,0x2000,13)
#define SGMII2_RX2_RXCDR2_PHSACQ_ENABLE_MASK                       0x2000
#define SGMII2_RX2_RXCDR2_PHSACQ_ENABLE_ALIGN                      0
#define SGMII2_RX2_RXCDR2_PHSACQ_ENABLE_BITS                       1
#define SGMII2_RX2_RXCDR2_PHSACQ_ENABLE_SHIFT                      13

/* SGMII2_RX2 :: rxcdr2 :: rate_select [12:12] */
#define Wr_SGMII2_RX2_rxcdr2_rate_select(x) WriteRegBits16(SGMII2_RX2_RXCDR2,0x1000,12,x)
#define Rd_SGMII2_RX2_rxcdr2_rate_select(x) ReadRegBits16(SGMII2_RX2_RXCDR2,0x1000,12)
#define SGMII2_RX2_RXCDR2_RATE_SELECT_MASK                         0x1000
#define SGMII2_RX2_RXCDR2_RATE_SELECT_ALIGN                        0
#define SGMII2_RX2_RXCDR2_RATE_SELECT_BITS                         1
#define SGMII2_RX2_RXCDR2_RATE_SELECT_SHIFT                        12

/* SGMII2_RX2 :: rxcdr2 :: phsacq_dir [11:11] */
#define Wr_SGMII2_RX2_rxcdr2_phsacq_dir(x) WriteRegBits16(SGMII2_RX2_RXCDR2,0x800,11,x)
#define Rd_SGMII2_RX2_rxcdr2_phsacq_dir(x) ReadRegBits16(SGMII2_RX2_RXCDR2,0x800,11)
#define SGMII2_RX2_RXCDR2_PHSACQ_DIR_MASK                          0x0800
#define SGMII2_RX2_RXCDR2_PHSACQ_DIR_ALIGN                         0
#define SGMII2_RX2_RXCDR2_PHSACQ_DIR_BITS                          1
#define SGMII2_RX2_RXCDR2_PHSACQ_DIR_SHIFT                         11

/* SGMII2_RX2 :: rxcdr2 :: reserved1 [10:10] */
#define SGMII2_RX2_RXCDR2_RESERVED1_MASK                           0x0400
#define SGMII2_RX2_RXCDR2_RESERVED1_ALIGN                          0
#define SGMII2_RX2_RXCDR2_RESERVED1_BITS                           1
#define SGMII2_RX2_RXCDR2_RESERVED1_SHIFT                          10

/* SGMII2_RX2 :: rxcdr2 :: phsacq_freq_sel [09:09] */
#define Wr_SGMII2_RX2_rxcdr2_phsacq_freq_sel(x) WriteRegBits16(SGMII2_RX2_RXCDR2,0x200,9,x)
#define Rd_SGMII2_RX2_rxcdr2_phsacq_freq_sel(x) ReadRegBits16(SGMII2_RX2_RXCDR2,0x200,9)
#define SGMII2_RX2_RXCDR2_PHSACQ_FREQ_SEL_MASK                     0x0200
#define SGMII2_RX2_RXCDR2_PHSACQ_FREQ_SEL_ALIGN                    0
#define SGMII2_RX2_RXCDR2_PHSACQ_FREQ_SEL_BITS                     1
#define SGMII2_RX2_RXCDR2_PHSACQ_FREQ_SEL_SHIFT                    9

/* SGMII2_RX2 :: rxcdr2 :: phsacq_step [08:08] */
#define Wr_SGMII2_RX2_rxcdr2_phsacq_step(x) WriteRegBits16(SGMII2_RX2_RXCDR2,0x100,8,x)
#define Rd_SGMII2_RX2_rxcdr2_phsacq_step(x) ReadRegBits16(SGMII2_RX2_RXCDR2,0x100,8)
#define SGMII2_RX2_RXCDR2_PHSACQ_STEP_MASK                         0x0100
#define SGMII2_RX2_RXCDR2_PHSACQ_STEP_ALIGN                        0
#define SGMII2_RX2_RXCDR2_PHSACQ_STEP_BITS                         1
#define SGMII2_RX2_RXCDR2_PHSACQ_STEP_SHIFT                        8

/* SGMII2_RX2 :: rxcdr2 :: phsacq_timeout [07:00] */
#define Wr_SGMII2_RX2_rxcdr2_phsacq_timeout(x) WriteRegBits16(SGMII2_RX2_RXCDR2,0xff,0,x)
#define Rd_SGMII2_RX2_rxcdr2_phsacq_timeout(x) ReadRegBits16(SGMII2_RX2_RXCDR2,0xff,0)
#define SGMII2_RX2_RXCDR2_PHSACQ_TIMEOUT_MASK                      0x00ff
#define SGMII2_RX2_RXCDR2_PHSACQ_TIMEOUT_ALIGN                     0
#define SGMII2_RX2_RXCDR2_PHSACQ_TIMEOUT_BITS                      8
#define SGMII2_RX2_RXCDR2_PHSACQ_TIMEOUT_SHIFT                     0


/****************************************************************************
 * SGMII2_RX2 :: rxcdr3
 ***************************************************************************/
/* SGMII2_RX2 :: rxcdr3 :: reserved0 [15:13] */
#define SGMII2_RX2_RXCDR3_RESERVED0_MASK                           0xe000
#define SGMII2_RX2_RXCDR3_RESERVED0_ALIGN                          0
#define SGMII2_RX2_RXCDR3_RESERVED0_BITS                           3
#define SGMII2_RX2_RXCDR3_RESERVED0_SHIFT                          13

/* SGMII2_RX2 :: rxcdr3 :: phase_step [12:11] */
#define Wr_SGMII2_RX2_rxcdr3_phase_step(x) WriteRegBits16(SGMII2_RX2_RXCDR3,0x1800,11,x)
#define Rd_SGMII2_RX2_rxcdr3_phase_step(x) ReadRegBits16(SGMII2_RX2_RXCDR3,0x1800,11)
#define SGMII2_RX2_RXCDR3_PHASE_STEP_MASK                          0x1800
#define SGMII2_RX2_RXCDR3_PHASE_STEP_ALIGN                         0
#define SGMII2_RX2_RXCDR3_PHASE_STEP_BITS                          2
#define SGMII2_RX2_RXCDR3_PHASE_STEP_SHIFT                         11

/* SGMII2_RX2 :: rxcdr3 :: phase_frz_1 [10:10] */
#define Wr_SGMII2_RX2_rxcdr3_phase_frz_1(x) WriteRegBits16(SGMII2_RX2_RXCDR3,0x400,10,x)
#define Rd_SGMII2_RX2_rxcdr3_phase_frz_1(x) ReadRegBits16(SGMII2_RX2_RXCDR3,0x400,10)
#define SGMII2_RX2_RXCDR3_PHASE_FRZ_1_MASK                         0x0400
#define SGMII2_RX2_RXCDR3_PHASE_FRZ_1_ALIGN                        0
#define SGMII2_RX2_RXCDR3_PHASE_FRZ_1_BITS                         1
#define SGMII2_RX2_RXCDR3_PHASE_FRZ_1_SHIFT                        10

/* SGMII2_RX2 :: rxcdr3 :: phase_frz_1_en [09:09] */
#define Wr_SGMII2_RX2_rxcdr3_phase_frz_1_en(x) WriteRegBits16(SGMII2_RX2_RXCDR3,0x200,9,x)
#define Rd_SGMII2_RX2_rxcdr3_phase_frz_1_en(x) ReadRegBits16(SGMII2_RX2_RXCDR3,0x200,9)
#define SGMII2_RX2_RXCDR3_PHASE_FRZ_1_EN_MASK                      0x0200
#define SGMII2_RX2_RXCDR3_PHASE_FRZ_1_EN_ALIGN                     0
#define SGMII2_RX2_RXCDR3_PHASE_FRZ_1_EN_BITS                      1
#define SGMII2_RX2_RXCDR3_PHASE_FRZ_1_EN_SHIFT                     9

/* SGMII2_RX2 :: rxcdr3 :: phase_override_SM [08:08] */
#define Wr_SGMII2_RX2_rxcdr3_phase_override_SM(x) WriteRegBits16(SGMII2_RX2_RXCDR3,0x100,8,x)
#define Rd_SGMII2_RX2_rxcdr3_phase_override_SM(x) ReadRegBits16(SGMII2_RX2_RXCDR3,0x100,8)
#define SGMII2_RX2_RXCDR3_PHASE_OVERRIDE_SM_MASK                   0x0100
#define SGMII2_RX2_RXCDR3_PHASE_OVERRIDE_SM_ALIGN                  0
#define SGMII2_RX2_RXCDR3_PHASE_OVERRIDE_SM_BITS                   1
#define SGMII2_RX2_RXCDR3_PHASE_OVERRIDE_SM_SHIFT                  8

/* SGMII2_RX2 :: rxcdr3 :: phase_inc_SM [07:07] */
#define Wr_SGMII2_RX2_rxcdr3_phase_inc_SM(x) WriteRegBits16(SGMII2_RX2_RXCDR3,0x80,7,x)
#define Rd_SGMII2_RX2_rxcdr3_phase_inc_SM(x) ReadRegBits16(SGMII2_RX2_RXCDR3,0x80,7)
#define SGMII2_RX2_RXCDR3_PHASE_INC_SM_MASK                        0x0080
#define SGMII2_RX2_RXCDR3_PHASE_INC_SM_ALIGN                       0
#define SGMII2_RX2_RXCDR3_PHASE_INC_SM_BITS                        1
#define SGMII2_RX2_RXCDR3_PHASE_INC_SM_SHIFT                       7

/* SGMII2_RX2 :: rxcdr3 :: phase_dec_SM [06:06] */
#define Wr_SGMII2_RX2_rxcdr3_phase_dec_SM(x) WriteRegBits16(SGMII2_RX2_RXCDR3,0x40,6,x)
#define Rd_SGMII2_RX2_rxcdr3_phase_dec_SM(x) ReadRegBits16(SGMII2_RX2_RXCDR3,0x40,6)
#define SGMII2_RX2_RXCDR3_PHASE_DEC_SM_MASK                        0x0040
#define SGMII2_RX2_RXCDR3_PHASE_DEC_SM_ALIGN                       0
#define SGMII2_RX2_RXCDR3_PHASE_DEC_SM_BITS                        1
#define SGMII2_RX2_RXCDR3_PHASE_DEC_SM_SHIFT                       6

/* SGMII2_RX2 :: rxcdr3 :: phase_strobe_SM [05:05] */
#define Wr_SGMII2_RX2_rxcdr3_phase_strobe_SM(x) WriteRegBits16(SGMII2_RX2_RXCDR3,0x20,5,x)
#define Rd_SGMII2_RX2_rxcdr3_phase_strobe_SM(x) ReadRegBits16(SGMII2_RX2_RXCDR3,0x20,5)
#define SGMII2_RX2_RXCDR3_PHASE_STROBE_SM_MASK                     0x0020
#define SGMII2_RX2_RXCDR3_PHASE_STROBE_SM_ALIGN                    0
#define SGMII2_RX2_RXCDR3_PHASE_STROBE_SM_BITS                     1
#define SGMII2_RX2_RXCDR3_PHASE_STROBE_SM_SHIFT                    5

/* SGMII2_RX2 :: rxcdr3 :: phase_delta_SM [04:00] */
#define Wr_SGMII2_RX2_rxcdr3_phase_delta_SM(x) WriteRegBits16(SGMII2_RX2_RXCDR3,0x1f,0,x)
#define Rd_SGMII2_RX2_rxcdr3_phase_delta_SM(x) ReadRegBits16(SGMII2_RX2_RXCDR3,0x1f,0)
#define SGMII2_RX2_RXCDR3_PHASE_DELTA_SM_MASK                      0x001f
#define SGMII2_RX2_RXCDR3_PHASE_DELTA_SM_ALIGN                     0
#define SGMII2_RX2_RXCDR3_PHASE_DELTA_SM_BITS                      5
#define SGMII2_RX2_RXCDR3_PHASE_DELTA_SM_SHIFT                     0


/****************************************************************************
 * SGMII2_RX2 :: rxcdr4
 ***************************************************************************/
/* SGMII2_RX2 :: rxcdr4 :: bwsel_integ [15:12] */
#define Wr_SGMII2_RX2_rxcdr4_bwsel_integ(x) WriteRegBits16(SGMII2_RX2_RXCDR4,0xf000,12,x)
#define Rd_SGMII2_RX2_rxcdr4_bwsel_integ(x) ReadRegBits16(SGMII2_RX2_RXCDR4,0xf000,12)
#define SGMII2_RX2_RXCDR4_BWSEL_INTEG_MASK                         0xf000
#define SGMII2_RX2_RXCDR4_BWSEL_INTEG_ALIGN                        0
#define SGMII2_RX2_RXCDR4_BWSEL_INTEG_BITS                         4
#define SGMII2_RX2_RXCDR4_BWSEL_INTEG_SHIFT                        12

/* SGMII2_RX2 :: rxcdr4 :: bwsel_prop [11:08] */
#define Wr_SGMII2_RX2_rxcdr4_bwsel_prop(x) WriteRegBits16(SGMII2_RX2_RXCDR4,0xf00,8,x)
#define Rd_SGMII2_RX2_rxcdr4_bwsel_prop(x) ReadRegBits16(SGMII2_RX2_RXCDR4,0xf00,8)
#define SGMII2_RX2_RXCDR4_BWSEL_PROP_MASK                          0x0f00
#define SGMII2_RX2_RXCDR4_BWSEL_PROP_ALIGN                         0
#define SGMII2_RX2_RXCDR4_BWSEL_PROP_BITS                          4
#define SGMII2_RX2_RXCDR4_BWSEL_PROP_SHIFT                         8

/* SGMII2_RX2 :: rxcdr4 :: integ_clr [07:07] */
#define Wr_SGMII2_RX2_rxcdr4_integ_clr(x) WriteRegBits16(SGMII2_RX2_RXCDR4,0x80,7,x)
#define Rd_SGMII2_RX2_rxcdr4_integ_clr(x) ReadRegBits16(SGMII2_RX2_RXCDR4,0x80,7)
#define SGMII2_RX2_RXCDR4_INTEG_CLR_MASK                           0x0080
#define SGMII2_RX2_RXCDR4_INTEG_CLR_ALIGN                          0
#define SGMII2_RX2_RXCDR4_INTEG_CLR_BITS                           1
#define SGMII2_RX2_RXCDR4_INTEG_CLR_SHIFT                          7

/* SGMII2_RX2 :: rxcdr4 :: freq_en [06:06] */
#define Wr_SGMII2_RX2_rxcdr4_freq_en(x) WriteRegBits16(SGMII2_RX2_RXCDR4,0x40,6,x)
#define Rd_SGMII2_RX2_rxcdr4_freq_en(x) ReadRegBits16(SGMII2_RX2_RXCDR4,0x40,6)
#define SGMII2_RX2_RXCDR4_FREQ_EN_MASK                             0x0040
#define SGMII2_RX2_RXCDR4_FREQ_EN_ALIGN                            0
#define SGMII2_RX2_RXCDR4_FREQ_EN_BITS                             1
#define SGMII2_RX2_RXCDR4_FREQ_EN_SHIFT                            6

/* SGMII2_RX2 :: rxcdr4 :: freq_override_en [05:05] */
#define Wr_SGMII2_RX2_rxcdr4_freq_override_en(x) WriteRegBits16(SGMII2_RX2_RXCDR4,0x20,5,x)
#define Rd_SGMII2_RX2_rxcdr4_freq_override_en(x) ReadRegBits16(SGMII2_RX2_RXCDR4,0x20,5)
#define SGMII2_RX2_RXCDR4_FREQ_OVERRIDE_EN_MASK                    0x0020
#define SGMII2_RX2_RXCDR4_FREQ_OVERRIDE_EN_ALIGN                   0
#define SGMII2_RX2_RXCDR4_FREQ_OVERRIDE_EN_BITS                    1
#define SGMII2_RX2_RXCDR4_FREQ_OVERRIDE_EN_SHIFT                   5

/* SGMII2_RX2 :: rxcdr4 :: freq_override_val [04:00] */
#define Wr_SGMII2_RX2_rxcdr4_freq_override_val(x) WriteRegBits16(SGMII2_RX2_RXCDR4,0x1f,0,x)
#define Rd_SGMII2_RX2_rxcdr4_freq_override_val(x) ReadRegBits16(SGMII2_RX2_RXCDR4,0x1f,0)
#define SGMII2_RX2_RXCDR4_FREQ_OVERRIDE_VAL_MASK                   0x001f
#define SGMII2_RX2_RXCDR4_FREQ_OVERRIDE_VAL_ALIGN                  0
#define SGMII2_RX2_RXCDR4_FREQ_OVERRIDE_VAL_BITS                   5
#define SGMII2_RX2_RXCDR4_FREQ_OVERRIDE_VAL_SHIFT                  0


/****************************************************************************
 * SGMII2_RX2 :: status0
 ***************************************************************************/
/* SGMII2_RX2 :: status0 :: reserved0 [15:10] */
#define SGMII2_RX2_STATUS0_RESERVED0_MASK                          0xfc00
#define SGMII2_RX2_STATUS0_RESERVED0_ALIGN                         0
#define SGMII2_RX2_STATUS0_RESERVED0_BITS                          6
#define SGMII2_RX2_STATUS0_RESERVED0_SHIFT                         10

/* SGMII2_RX2 :: status0 :: rx_lmtoff [09:04] */
#define Wr_SGMII2_RX2_status0_rx_lmtoff(x) WriteRegBits16(SGMII2_RX2_STATUS0,0x3f0,4,x)
#define Rd_SGMII2_RX2_status0_rx_lmtoff(x) ReadRegBits16(SGMII2_RX2_STATUS0,0x3f0,4)
#define SGMII2_RX2_STATUS0_RX_LMTOFF_MASK                          0x03f0
#define SGMII2_RX2_STATUS0_RX_LMTOFF_ALIGN                         0
#define SGMII2_RX2_STATUS0_RX_LMTOFF_BITS                          6
#define SGMII2_RX2_STATUS0_RX_LMTOFF_SHIFT                         4

/* SGMII2_RX2 :: status0 :: rx_slicer_cal_done [03:03] */
#define Wr_SGMII2_RX2_status0_rx_slicer_cal_done(x) WriteRegBits16(SGMII2_RX2_STATUS0,0x8,3,x)
#define Rd_SGMII2_RX2_status0_rx_slicer_cal_done(x) ReadRegBits16(SGMII2_RX2_STATUS0,0x8,3)
#define SGMII2_RX2_STATUS0_RX_SLICER_CAL_DONE_MASK                 0x0008
#define SGMII2_RX2_STATUS0_RX_SLICER_CAL_DONE_ALIGN                0
#define SGMII2_RX2_STATUS0_RX_SLICER_CAL_DONE_BITS                 1
#define SGMII2_RX2_STATUS0_RX_SLICER_CAL_DONE_SHIFT                3

/* SGMII2_RX2 :: status0 :: rx_sloff0_invalid [02:02] */
#define Wr_SGMII2_RX2_status0_rx_sloff0_invalid(x) WriteRegBits16(SGMII2_RX2_STATUS0,0x4,2,x)
#define Rd_SGMII2_RX2_status0_rx_sloff0_invalid(x) ReadRegBits16(SGMII2_RX2_STATUS0,0x4,2)
#define SGMII2_RX2_STATUS0_RX_SLOFF0_INVALID_MASK                  0x0004
#define SGMII2_RX2_STATUS0_RX_SLOFF0_INVALID_ALIGN                 0
#define SGMII2_RX2_STATUS0_RX_SLOFF0_INVALID_BITS                  1
#define SGMII2_RX2_STATUS0_RX_SLOFF0_INVALID_SHIFT                 2

/* SGMII2_RX2 :: status0 :: rx_sloff1_invalid [01:01] */
#define Wr_SGMII2_RX2_status0_rx_sloff1_invalid(x) WriteRegBits16(SGMII2_RX2_STATUS0,0x2,1,x)
#define Rd_SGMII2_RX2_status0_rx_sloff1_invalid(x) ReadRegBits16(SGMII2_RX2_STATUS0,0x2,1)
#define SGMII2_RX2_STATUS0_RX_SLOFF1_INVALID_MASK                  0x0002
#define SGMII2_RX2_STATUS0_RX_SLOFF1_INVALID_ALIGN                 0
#define SGMII2_RX2_STATUS0_RX_SLOFF1_INVALID_BITS                  1
#define SGMII2_RX2_STATUS0_RX_SLOFF1_INVALID_SHIFT                 1

/* SGMII2_RX2 :: status0 :: rx_sloff2_invalid [00:00] */
#define Wr_SGMII2_RX2_status0_rx_sloff2_invalid(x) WriteRegBits16(SGMII2_RX2_STATUS0,0x1,0,x)
#define Rd_SGMII2_RX2_status0_rx_sloff2_invalid(x) ReadRegBits16(SGMII2_RX2_STATUS0,0x1,0)
#define SGMII2_RX2_STATUS0_RX_SLOFF2_INVALID_MASK                  0x0001
#define SGMII2_RX2_STATUS0_RX_SLOFF2_INVALID_ALIGN                 0
#define SGMII2_RX2_STATUS0_RX_SLOFF2_INVALID_BITS                  1
#define SGMII2_RX2_STATUS0_RX_SLOFF2_INVALID_SHIFT                 0


/****************************************************************************
 * SGMII2_RX2 :: status1
 ***************************************************************************/
/* SGMII2_RX2 :: status1 :: reserved0 [15:15] */
#define SGMII2_RX2_STATUS1_RESERVED0_MASK                          0x8000
#define SGMII2_RX2_STATUS1_RESERVED0_ALIGN                         0
#define SGMII2_RX2_STATUS1_RESERVED0_BITS                          1
#define SGMII2_RX2_STATUS1_RESERVED0_SHIFT                         15

/* SGMII2_RX2 :: status1 :: up_sloffx_val [14:11] */
#define Wr_SGMII2_RX2_status1_up_sloffx_val(x) WriteRegBits16(SGMII2_RX2_STATUS1,0x7800,11,x)
#define Rd_SGMII2_RX2_status1_up_sloffx_val(x) ReadRegBits16(SGMII2_RX2_STATUS1,0x7800,11)
#define SGMII2_RX2_STATUS1_UP_SLOFFX_VAL_MASK                      0x7800
#define SGMII2_RX2_STATUS1_UP_SLOFFX_VAL_ALIGN                     0
#define SGMII2_RX2_STATUS1_UP_SLOFFX_VAL_BITS                      4
#define SGMII2_RX2_STATUS1_UP_SLOFFX_VAL_SHIFT                     11

/* SGMII2_RX2 :: status1 :: dn_sloffx_val [10:07] */
#define Wr_SGMII2_RX2_status1_dn_sloffx_val(x) WriteRegBits16(SGMII2_RX2_STATUS1,0x780,7,x)
#define Rd_SGMII2_RX2_status1_dn_sloffx_val(x) ReadRegBits16(SGMII2_RX2_STATUS1,0x780,7)
#define SGMII2_RX2_STATUS1_DN_SLOFFX_VAL_MASK                      0x0780
#define SGMII2_RX2_STATUS1_DN_SLOFFX_VAL_ALIGN                     0
#define SGMII2_RX2_STATUS1_DN_SLOFFX_VAL_BITS                      4
#define SGMII2_RX2_STATUS1_DN_SLOFFX_VAL_SHIFT                     7

/* SGMII2_RX2 :: status1 :: sloffx_val [06:03] */
#define Wr_SGMII2_RX2_status1_sloffx_val(x) WriteRegBits16(SGMII2_RX2_STATUS1,0x78,3,x)
#define Rd_SGMII2_RX2_status1_sloffx_val(x) ReadRegBits16(SGMII2_RX2_STATUS1,0x78,3)
#define SGMII2_RX2_STATUS1_SLOFFX_VAL_MASK                         0x0078
#define SGMII2_RX2_STATUS1_SLOFFX_VAL_ALIGN                        0
#define SGMII2_RX2_STATUS1_SLOFFX_VAL_BITS                         4
#define SGMII2_RX2_STATUS1_SLOFFX_VAL_SHIFT                        3

/* SGMII2_RX2 :: status1 :: slcal_state [02:00] */
#define Wr_SGMII2_RX2_status1_slcal_state(x) WriteRegBits16(SGMII2_RX2_STATUS1,0x7,0,x)
#define Rd_SGMII2_RX2_status1_slcal_state(x) ReadRegBits16(SGMII2_RX2_STATUS1,0x7,0)
#define SGMII2_RX2_STATUS1_SLCAL_STATE_MASK                        0x0007
#define SGMII2_RX2_STATUS1_SLCAL_STATE_ALIGN                       0
#define SGMII2_RX2_STATUS1_SLCAL_STATE_BITS                        3
#define SGMII2_RX2_STATUS1_SLCAL_STATE_SHIFT                       0


/****************************************************************************
 * SGMII2_RX2 :: status2
 ***************************************************************************/
/* SGMII2_RX2 :: status2 :: lmtcal_acc [15:00] */
#define Wr_SGMII2_RX2_status2_lmtcal_acc(x) WriteReg16(SGMII2_RX2_STATUS2,x)
#define Rd_SGMII2_RX2_status2_lmtcal_acc(x) ReadReg16(SGMII2_RX2_STATUS2)
#define SGMII2_RX2_STATUS2_LMTCAL_ACC_MASK                         0xffff
#define SGMII2_RX2_STATUS2_LMTCAL_ACC_ALIGN                        0
#define SGMII2_RX2_STATUS2_LMTCAL_ACC_BITS                         16
#define SGMII2_RX2_STATUS2_LMTCAL_ACC_SHIFT                        0


/****************************************************************************
 * SGMII2_RX2 :: status3
 ***************************************************************************/
/* SGMII2_RX2 :: status3 :: reserved0 [15:11] */
#define SGMII2_RX2_STATUS3_RESERVED0_MASK                          0xf800
#define SGMII2_RX2_STATUS3_RESERVED0_ALIGN                         0
#define SGMII2_RX2_STATUS3_RESERVED0_BITS                          5
#define SGMII2_RX2_STATUS3_RESERVED0_SHIFT                         11

/* SGMII2_RX2 :: status3 :: lmtcal_state [10:08] */
#define Wr_SGMII2_RX2_status3_lmtcal_state(x) WriteRegBits16(SGMII2_RX2_STATUS3,0x700,8,x)
#define Rd_SGMII2_RX2_status3_lmtcal_state(x) ReadRegBits16(SGMII2_RX2_STATUS3,0x700,8)
#define SGMII2_RX2_STATUS3_LMTCAL_STATE_MASK                       0x0700
#define SGMII2_RX2_STATUS3_LMTCAL_STATE_ALIGN                      0
#define SGMII2_RX2_STATUS3_LMTCAL_STATE_BITS                       3
#define SGMII2_RX2_STATUS3_LMTCAL_STATE_SHIFT                      8

/* SGMII2_RX2 :: status3 :: rx_LA_cal_done [07:07] */
#define Wr_SGMII2_RX2_status3_rx_LA_cal_done(x) WriteRegBits16(SGMII2_RX2_STATUS3,0x80,7,x)
#define Rd_SGMII2_RX2_status3_rx_LA_cal_done(x) ReadRegBits16(SGMII2_RX2_STATUS3,0x80,7)
#define SGMII2_RX2_STATUS3_RX_LA_CAL_DONE_MASK                     0x0080
#define SGMII2_RX2_STATUS3_RX_LA_CAL_DONE_ALIGN                    0
#define SGMII2_RX2_STATUS3_RX_LA_CAL_DONE_BITS                     1
#define SGMII2_RX2_STATUS3_RX_LA_CAL_DONE_SHIFT                    7

/* SGMII2_RX2 :: status3 :: lmtcal_valid [06:06] */
#define Wr_SGMII2_RX2_status3_lmtcal_valid(x) WriteRegBits16(SGMII2_RX2_STATUS3,0x40,6,x)
#define Rd_SGMII2_RX2_status3_lmtcal_valid(x) ReadRegBits16(SGMII2_RX2_STATUS3,0x40,6)
#define SGMII2_RX2_STATUS3_LMTCAL_VALID_MASK                       0x0040
#define SGMII2_RX2_STATUS3_LMTCAL_VALID_ALIGN                      0
#define SGMII2_RX2_STATUS3_LMTCAL_VALID_BITS                       1
#define SGMII2_RX2_STATUS3_LMTCAL_VALID_SHIFT                      6

/* SGMII2_RX2 :: status3 :: lmtcal_adj_cnt [05:01] */
#define Wr_SGMII2_RX2_status3_lmtcal_adj_cnt(x) WriteRegBits16(SGMII2_RX2_STATUS3,0x3e,1,x)
#define Rd_SGMII2_RX2_status3_lmtcal_adj_cnt(x) ReadRegBits16(SGMII2_RX2_STATUS3,0x3e,1)
#define SGMII2_RX2_STATUS3_LMTCAL_ADJ_CNT_MASK                     0x003e
#define SGMII2_RX2_STATUS3_LMTCAL_ADJ_CNT_ALIGN                    0
#define SGMII2_RX2_STATUS3_LMTCAL_ADJ_CNT_BITS                     5
#define SGMII2_RX2_STATUS3_LMTCAL_ADJ_CNT_SHIFT                    1

/* SGMII2_RX2 :: status3 :: recal_ind [00:00] */
#define Wr_SGMII2_RX2_status3_recal_ind(x) WriteRegBits16(SGMII2_RX2_STATUS3,0x1,0,x)
#define Rd_SGMII2_RX2_status3_recal_ind(x) ReadRegBits16(SGMII2_RX2_STATUS3,0x1,0)
#define SGMII2_RX2_STATUS3_RECAL_IND_MASK                          0x0001
#define SGMII2_RX2_STATUS3_RECAL_IND_ALIGN                         0
#define SGMII2_RX2_STATUS3_RECAL_IND_BITS                          1
#define SGMII2_RX2_STATUS3_RECAL_IND_SHIFT                         0


/****************************************************************************
 * SGMII2_RX2 :: status4
 ***************************************************************************/
/* SGMII2_RX2 :: status4 :: em_err_cnt_H [15:00] */
#define Wr_SGMII2_RX2_status4_em_err_cnt_H(x) WriteReg16(SGMII2_RX2_STATUS4,x)
#define Rd_SGMII2_RX2_status4_em_err_cnt_H(x) ReadReg16(SGMII2_RX2_STATUS4)
#define SGMII2_RX2_STATUS4_EM_ERR_CNT_H_MASK                       0xffff
#define SGMII2_RX2_STATUS4_EM_ERR_CNT_H_ALIGN                      0
#define SGMII2_RX2_STATUS4_EM_ERR_CNT_H_BITS                       16
#define SGMII2_RX2_STATUS4_EM_ERR_CNT_H_SHIFT                      0


/****************************************************************************
 * SGMII2_RX2 :: status5
 ***************************************************************************/
/* SGMII2_RX2 :: status5 :: em_err_cnt_L [15:00] */
#define Wr_SGMII2_RX2_status5_em_err_cnt_L(x) WriteReg16(SGMII2_RX2_STATUS5,x)
#define Rd_SGMII2_RX2_status5_em_err_cnt_L(x) ReadReg16(SGMII2_RX2_STATUS5)
#define SGMII2_RX2_STATUS5_EM_ERR_CNT_L_MASK                       0xffff
#define SGMII2_RX2_STATUS5_EM_ERR_CNT_L_ALIGN                      0
#define SGMII2_RX2_STATUS5_EM_ERR_CNT_L_BITS                       16
#define SGMII2_RX2_STATUS5_EM_ERR_CNT_L_SHIFT                      0


/****************************************************************************
 * SGMII2_RX2 :: status6
 ***************************************************************************/
/* SGMII2_RX2 :: status6 :: rx_phs_interp_status [15:00] */
#define Wr_SGMII2_RX2_status6_rx_phs_interp_status(x) WriteReg16(SGMII2_RX2_STATUS6,x)
#define Rd_SGMII2_RX2_status6_rx_phs_interp_status(x) ReadReg16(SGMII2_RX2_STATUS6)
#define SGMII2_RX2_STATUS6_RX_PHS_INTERP_STATUS_MASK               0xffff
#define SGMII2_RX2_STATUS6_RX_PHS_INTERP_STATUS_ALIGN              0
#define SGMII2_RX2_STATUS6_RX_PHS_INTERP_STATUS_BITS               16
#define SGMII2_RX2_STATUS6_RX_PHS_INTERP_STATUS_SHIFT              0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_RX3
 ***************************************************************************/
/****************************************************************************
 * SGMII2_RX3 :: control0
 ***************************************************************************/
/* SGMII2_RX3 :: control0 :: lmtcal_max_adj [15:11] */
#define Wr_SGMII2_RX3_control0_lmtcal_max_adj(x) WriteRegBits16(SGMII2_RX3_CONTROL0,0xf800,11,x)
#define Rd_SGMII2_RX3_control0_lmtcal_max_adj(x) ReadRegBits16(SGMII2_RX3_CONTROL0,0xf800,11)
#define SGMII2_RX3_CONTROL0_LMTCAL_MAX_ADJ_MASK                    0xf800
#define SGMII2_RX3_CONTROL0_LMTCAL_MAX_ADJ_ALIGN                   0
#define SGMII2_RX3_CONTROL0_LMTCAL_MAX_ADJ_BITS                    5
#define SGMII2_RX3_CONTROL0_LMTCAL_MAX_ADJ_SHIFT                   11

/* SGMII2_RX3 :: control0 :: lmtcal_intv_time [10:00] */
#define Wr_SGMII2_RX3_control0_lmtcal_intv_time(x) WriteRegBits16(SGMII2_RX3_CONTROL0,0x7ff,0,x)
#define Rd_SGMII2_RX3_control0_lmtcal_intv_time(x) ReadRegBits16(SGMII2_RX3_CONTROL0,0x7ff,0)
#define SGMII2_RX3_CONTROL0_LMTCAL_INTV_TIME_MASK                  0x07ff
#define SGMII2_RX3_CONTROL0_LMTCAL_INTV_TIME_ALIGN                 0
#define SGMII2_RX3_CONTROL0_LMTCAL_INTV_TIME_BITS                  11
#define SGMII2_RX3_CONTROL0_LMTCAL_INTV_TIME_SHIFT                 0


/****************************************************************************
 * SGMII2_RX3 :: control1
 ***************************************************************************/
/* SGMII2_RX3 :: control1 :: lmtcal_falling_edge_en [15:15] */
#define Wr_SGMII2_RX3_control1_lmtcal_falling_edge_en(x) WriteRegBits16(SGMII2_RX3_CONTROL1,0x8000,15,x)
#define Rd_SGMII2_RX3_control1_lmtcal_falling_edge_en(x) ReadRegBits16(SGMII2_RX3_CONTROL1,0x8000,15)
#define SGMII2_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_MASK            0x8000
#define SGMII2_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_ALIGN           0
#define SGMII2_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_BITS            1
#define SGMII2_RX3_CONTROL1_LMTCAL_FALLING_EDGE_EN_SHIFT           15

/* SGMII2_RX3 :: control1 :: lmtcal_rising_edge_en [14:14] */
#define Wr_SGMII2_RX3_control1_lmtcal_rising_edge_en(x) WriteRegBits16(SGMII2_RX3_CONTROL1,0x4000,14,x)
#define Rd_SGMII2_RX3_control1_lmtcal_rising_edge_en(x) ReadRegBits16(SGMII2_RX3_CONTROL1,0x4000,14)
#define SGMII2_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_MASK             0x4000
#define SGMII2_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_ALIGN            0
#define SGMII2_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_BITS             1
#define SGMII2_RX3_CONTROL1_LMTCAL_RISING_EDGE_EN_SHIFT            14

/* SGMII2_RX3 :: control1 :: lmtcal_kp [13:12] */
#define Wr_SGMII2_RX3_control1_lmtcal_kp(x) WriteRegBits16(SGMII2_RX3_CONTROL1,0x3000,12,x)
#define Rd_SGMII2_RX3_control1_lmtcal_kp(x) ReadRegBits16(SGMII2_RX3_CONTROL1,0x3000,12)
#define SGMII2_RX3_CONTROL1_LMTCAL_KP_MASK                         0x3000
#define SGMII2_RX3_CONTROL1_LMTCAL_KP_ALIGN                        0
#define SGMII2_RX3_CONTROL1_LMTCAL_KP_BITS                         2
#define SGMII2_RX3_CONTROL1_LMTCAL_KP_SHIFT                        12

/* SGMII2_RX3 :: control1 :: lmtcal_adj_dir [11:11] */
#define Wr_SGMII2_RX3_control1_lmtcal_adj_dir(x) WriteRegBits16(SGMII2_RX3_CONTROL1,0x800,11,x)
#define Rd_SGMII2_RX3_control1_lmtcal_adj_dir(x) ReadRegBits16(SGMII2_RX3_CONTROL1,0x800,11)
#define SGMII2_RX3_CONTROL1_LMTCAL_ADJ_DIR_MASK                    0x0800
#define SGMII2_RX3_CONTROL1_LMTCAL_ADJ_DIR_ALIGN                   0
#define SGMII2_RX3_CONTROL1_LMTCAL_ADJ_DIR_BITS                    1
#define SGMII2_RX3_CONTROL1_LMTCAL_ADJ_DIR_SHIFT                   11

/* SGMII2_RX3 :: control1 :: lmtcal_init_time [10:00] */
#define Wr_SGMII2_RX3_control1_lmtcal_init_time(x) WriteRegBits16(SGMII2_RX3_CONTROL1,0x7ff,0,x)
#define Rd_SGMII2_RX3_control1_lmtcal_init_time(x) ReadRegBits16(SGMII2_RX3_CONTROL1,0x7ff,0)
#define SGMII2_RX3_CONTROL1_LMTCAL_INIT_TIME_MASK                  0x07ff
#define SGMII2_RX3_CONTROL1_LMTCAL_INIT_TIME_ALIGN                 0
#define SGMII2_RX3_CONTROL1_LMTCAL_INIT_TIME_BITS                  11
#define SGMII2_RX3_CONTROL1_LMTCAL_INIT_TIME_SHIFT                 0


/****************************************************************************
 * SGMII2_RX3 :: control2
 ***************************************************************************/
/* SGMII2_RX3 :: control2 :: lmtcal_pd_polarity [15:15] */
#define Wr_SGMII2_RX3_control2_lmtcal_pd_polarity(x) WriteRegBits16(SGMII2_RX3_CONTROL2,0x8000,15,x)
#define Rd_SGMII2_RX3_control2_lmtcal_pd_polarity(x) ReadRegBits16(SGMII2_RX3_CONTROL2,0x8000,15)
#define SGMII2_RX3_CONTROL2_LMTCAL_PD_POLARITY_MASK                0x8000
#define SGMII2_RX3_CONTROL2_LMTCAL_PD_POLARITY_ALIGN               0
#define SGMII2_RX3_CONTROL2_LMTCAL_PD_POLARITY_BITS                1
#define SGMII2_RX3_CONTROL2_LMTCAL_PD_POLARITY_SHIFT               15

/* SGMII2_RX3 :: control2 :: lmtcal_acc_time [14:04] */
#define Wr_SGMII2_RX3_control2_lmtcal_acc_time(x) WriteRegBits16(SGMII2_RX3_CONTROL2,0x7ff0,4,x)
#define Rd_SGMII2_RX3_control2_lmtcal_acc_time(x) ReadRegBits16(SGMII2_RX3_CONTROL2,0x7ff0,4)
#define SGMII2_RX3_CONTROL2_LMTCAL_ACC_TIME_MASK                   0x7ff0
#define SGMII2_RX3_CONTROL2_LMTCAL_ACC_TIME_ALIGN                  0
#define SGMII2_RX3_CONTROL2_LMTCAL_ACC_TIME_BITS                   11
#define SGMII2_RX3_CONTROL2_LMTCAL_ACC_TIME_SHIFT                  4

/* SGMII2_RX3 :: control2 :: lmtcal_en_ovrd [03:03] */
#define Wr_SGMII2_RX3_control2_lmtcal_en_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL2,0x8,3,x)
#define Rd_SGMII2_RX3_control2_lmtcal_en_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL2,0x8,3)
#define SGMII2_RX3_CONTROL2_LMTCAL_EN_OVRD_MASK                    0x0008
#define SGMII2_RX3_CONTROL2_LMTCAL_EN_OVRD_ALIGN                   0
#define SGMII2_RX3_CONTROL2_LMTCAL_EN_OVRD_BITS                    1
#define SGMII2_RX3_CONTROL2_LMTCAL_EN_OVRD_SHIFT                   3

/* SGMII2_RX3 :: control2 :: lmtcal_en_ovrd_val [02:02] */
#define Wr_SGMII2_RX3_control2_lmtcal_en_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL2,0x4,2,x)
#define Rd_SGMII2_RX3_control2_lmtcal_en_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL2,0x4,2)
#define SGMII2_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_MASK                0x0004
#define SGMII2_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_ALIGN               0
#define SGMII2_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_BITS                1
#define SGMII2_RX3_CONTROL2_LMTCAL_EN_OVRD_VAL_SHIFT               2

/* SGMII2_RX3 :: control2 :: lmtcal_done_ovrd [01:01] */
#define Wr_SGMII2_RX3_control2_lmtcal_done_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL2,0x2,1,x)
#define Rd_SGMII2_RX3_control2_lmtcal_done_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL2,0x2,1)
#define SGMII2_RX3_CONTROL2_LMTCAL_DONE_OVRD_MASK                  0x0002
#define SGMII2_RX3_CONTROL2_LMTCAL_DONE_OVRD_ALIGN                 0
#define SGMII2_RX3_CONTROL2_LMTCAL_DONE_OVRD_BITS                  1
#define SGMII2_RX3_CONTROL2_LMTCAL_DONE_OVRD_SHIFT                 1

/* SGMII2_RX3 :: control2 :: lmtcal_done_ovrd_val [00:00] */
#define Wr_SGMII2_RX3_control2_lmtcal_done_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL2,0x1,0,x)
#define Rd_SGMII2_RX3_control2_lmtcal_done_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL2,0x1,0)
#define SGMII2_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_MASK              0x0001
#define SGMII2_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_ALIGN             0
#define SGMII2_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_BITS              1
#define SGMII2_RX3_CONTROL2_LMTCAL_DONE_OVRD_VAL_SHIFT             0


/****************************************************************************
 * SGMII2_RX3 :: control3
 ***************************************************************************/
/* SGMII2_RX3 :: control3 :: recal_pos_thres [15:00] */
#define Wr_SGMII2_RX3_control3_recal_pos_thres(x) WriteReg16(SGMII2_RX3_CONTROL3,x)
#define Rd_SGMII2_RX3_control3_recal_pos_thres(x) ReadReg16(SGMII2_RX3_CONTROL3)
#define SGMII2_RX3_CONTROL3_RECAL_POS_THRES_MASK                   0xffff
#define SGMII2_RX3_CONTROL3_RECAL_POS_THRES_ALIGN                  0
#define SGMII2_RX3_CONTROL3_RECAL_POS_THRES_BITS                   16
#define SGMII2_RX3_CONTROL3_RECAL_POS_THRES_SHIFT                  0


/****************************************************************************
 * SGMII2_RX3 :: control4
 ***************************************************************************/
/* SGMII2_RX3 :: control4 :: recal_neg_thres [15:00] */
#define Wr_SGMII2_RX3_control4_recal_neg_thres(x) WriteReg16(SGMII2_RX3_CONTROL4,x)
#define Rd_SGMII2_RX3_control4_recal_neg_thres(x) ReadReg16(SGMII2_RX3_CONTROL4)
#define SGMII2_RX3_CONTROL4_RECAL_NEG_THRES_MASK                   0xffff
#define SGMII2_RX3_CONTROL4_RECAL_NEG_THRES_ALIGN                  0
#define SGMII2_RX3_CONTROL4_RECAL_NEG_THRES_BITS                   16
#define SGMII2_RX3_CONTROL4_RECAL_NEG_THRES_SHIFT                  0


/****************************************************************************
 * SGMII2_RX3 :: control5
 ***************************************************************************/
/* SGMII2_RX3 :: control5 :: reserved0 [15:12] */
#define SGMII2_RX3_CONTROL5_RESERVED0_MASK                         0xf000
#define SGMII2_RX3_CONTROL5_RESERVED0_ALIGN                        0
#define SGMII2_RX3_CONTROL5_RESERVED0_BITS                         4
#define SGMII2_RX3_CONTROL5_RESERVED0_SHIFT                        12

/* SGMII2_RX3 :: control5 :: lmtcal_cont_acc_time [11:01] */
#define Wr_SGMII2_RX3_control5_lmtcal_cont_acc_time(x) WriteRegBits16(SGMII2_RX3_CONTROL5,0xffe,1,x)
#define Rd_SGMII2_RX3_control5_lmtcal_cont_acc_time(x) ReadRegBits16(SGMII2_RX3_CONTROL5,0xffe,1)
#define SGMII2_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_MASK              0x0ffe
#define SGMII2_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_ALIGN             0
#define SGMII2_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_BITS              11
#define SGMII2_RX3_CONTROL5_LMTCAL_CONT_ACC_TIME_SHIFT             1

/* SGMII2_RX3 :: control5 :: cont_lmtcal_en [00:00] */
#define Wr_SGMII2_RX3_control5_cont_lmtcal_en(x) WriteRegBits16(SGMII2_RX3_CONTROL5,0x1,0,x)
#define Rd_SGMII2_RX3_control5_cont_lmtcal_en(x) ReadRegBits16(SGMII2_RX3_CONTROL5,0x1,0)
#define SGMII2_RX3_CONTROL5_CONT_LMTCAL_EN_MASK                    0x0001
#define SGMII2_RX3_CONTROL5_CONT_LMTCAL_EN_ALIGN                   0
#define SGMII2_RX3_CONTROL5_CONT_LMTCAL_EN_BITS                    1
#define SGMII2_RX3_CONTROL5_CONT_LMTCAL_EN_SHIFT                   0


/****************************************************************************
 * SGMII2_RX3 :: control6
 ***************************************************************************/
/* SGMII2_RX3 :: control6 :: reserved0 [15:12] */
#define SGMII2_RX3_CONTROL6_RESERVED0_MASK                         0xf000
#define SGMII2_RX3_CONTROL6_RESERVED0_ALIGN                        0
#define SGMII2_RX3_CONTROL6_RESERVED0_BITS                         4
#define SGMII2_RX3_CONTROL6_RESERVED0_SHIFT                        12

/* SGMII2_RX3 :: control6 :: lmtcal_interval_time [11:07] */
#define Wr_SGMII2_RX3_control6_lmtcal_interval_time(x) WriteRegBits16(SGMII2_RX3_CONTROL6,0xf80,7,x)
#define Rd_SGMII2_RX3_control6_lmtcal_interval_time(x) ReadRegBits16(SGMII2_RX3_CONTROL6,0xf80,7)
#define SGMII2_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_MASK              0x0f80
#define SGMII2_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_ALIGN             0
#define SGMII2_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_BITS              5
#define SGMII2_RX3_CONTROL6_LMTCAL_INTERVAL_TIME_SHIFT             7

/* SGMII2_RX3 :: control6 :: rx_lmtoff_ovrd [06:06] */
#define Wr_SGMII2_RX3_control6_rx_lmtoff_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL6,0x40,6,x)
#define Rd_SGMII2_RX3_control6_rx_lmtoff_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL6,0x40,6)
#define SGMII2_RX3_CONTROL6_RX_LMTOFF_OVRD_MASK                    0x0040
#define SGMII2_RX3_CONTROL6_RX_LMTOFF_OVRD_ALIGN                   0
#define SGMII2_RX3_CONTROL6_RX_LMTOFF_OVRD_BITS                    1
#define SGMII2_RX3_CONTROL6_RX_LMTOFF_OVRD_SHIFT                   6

/* SGMII2_RX3 :: control6 :: rx_lmtoff_ovrd_val [05:00] */
#define Wr_SGMII2_RX3_control6_rx_lmtoff_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL6,0x3f,0,x)
#define Rd_SGMII2_RX3_control6_rx_lmtoff_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL6,0x3f,0)
#define SGMII2_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_MASK                0x003f
#define SGMII2_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_ALIGN               0
#define SGMII2_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_BITS                6
#define SGMII2_RX3_CONTROL6_RX_LMTOFF_OVRD_VAL_SHIFT               0


/****************************************************************************
 * SGMII2_RX3 :: control7
 ***************************************************************************/
/* SGMII2_RX3 :: control7 :: cal_state_ovrd [15:15] */
#define Wr_SGMII2_RX3_control7_cal_state_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL7,0x8000,15,x)
#define Rd_SGMII2_RX3_control7_cal_state_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL7,0x8000,15)
#define SGMII2_RX3_CONTROL7_CAL_STATE_OVRD_MASK                    0x8000
#define SGMII2_RX3_CONTROL7_CAL_STATE_OVRD_ALIGN                   0
#define SGMII2_RX3_CONTROL7_CAL_STATE_OVRD_BITS                    1
#define SGMII2_RX3_CONTROL7_CAL_STATE_OVRD_SHIFT                   15

/* SGMII2_RX3 :: control7 :: slcal_en_ovrd [14:14] */
#define Wr_SGMII2_RX3_control7_slcal_en_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL7,0x4000,14,x)
#define Rd_SGMII2_RX3_control7_slcal_en_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL7,0x4000,14)
#define SGMII2_RX3_CONTROL7_SLCAL_EN_OVRD_MASK                     0x4000
#define SGMII2_RX3_CONTROL7_SLCAL_EN_OVRD_ALIGN                    0
#define SGMII2_RX3_CONTROL7_SLCAL_EN_OVRD_BITS                     1
#define SGMII2_RX3_CONTROL7_SLCAL_EN_OVRD_SHIFT                    14

/* SGMII2_RX3 :: control7 :: slcal_en_ovrd_val [13:13] */
#define Wr_SGMII2_RX3_control7_slcal_en_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL7,0x2000,13,x)
#define Rd_SGMII2_RX3_control7_slcal_en_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL7,0x2000,13)
#define SGMII2_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_MASK                 0x2000
#define SGMII2_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_ALIGN                0
#define SGMII2_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_BITS                 1
#define SGMII2_RX3_CONTROL7_SLCAL_EN_OVRD_VAL_SHIFT                13

/* SGMII2_RX3 :: control7 :: slcal_acc_opt [12:11] */
#define Wr_SGMII2_RX3_control7_slcal_acc_opt(x) WriteRegBits16(SGMII2_RX3_CONTROL7,0x1800,11,x)
#define Rd_SGMII2_RX3_control7_slcal_acc_opt(x) ReadRegBits16(SGMII2_RX3_CONTROL7,0x1800,11)
#define SGMII2_RX3_CONTROL7_SLCAL_ACC_OPT_MASK                     0x1800
#define SGMII2_RX3_CONTROL7_SLCAL_ACC_OPT_ALIGN                    0
#define SGMII2_RX3_CONTROL7_SLCAL_ACC_OPT_BITS                     2
#define SGMII2_RX3_CONTROL7_SLCAL_ACC_OPT_SHIFT                    11

/* SGMII2_RX3 :: control7 :: slcal_pol [10:10] */
#define Wr_SGMII2_RX3_control7_slcal_pol(x) WriteRegBits16(SGMII2_RX3_CONTROL7,0x400,10,x)
#define Rd_SGMII2_RX3_control7_slcal_pol(x) ReadRegBits16(SGMII2_RX3_CONTROL7,0x400,10)
#define SGMII2_RX3_CONTROL7_SLCAL_POL_MASK                         0x0400
#define SGMII2_RX3_CONTROL7_SLCAL_POL_ALIGN                        0
#define SGMII2_RX3_CONTROL7_SLCAL_POL_BITS                         1
#define SGMII2_RX3_CONTROL7_SLCAL_POL_SHIFT                        10

/* SGMII2_RX3 :: control7 :: reserved0 [09:02] */
#define SGMII2_RX3_CONTROL7_RESERVED0_MASK                         0x03fc
#define SGMII2_RX3_CONTROL7_RESERVED0_ALIGN                        0
#define SGMII2_RX3_CONTROL7_RESERVED0_BITS                         8
#define SGMII2_RX3_CONTROL7_RESERVED0_SHIFT                        2

/* SGMII2_RX3 :: control7 :: slcal_valid_ovrd [01:01] */
#define Wr_SGMII2_RX3_control7_slcal_valid_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL7,0x2,1,x)
#define Rd_SGMII2_RX3_control7_slcal_valid_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL7,0x2,1)
#define SGMII2_RX3_CONTROL7_SLCAL_VALID_OVRD_MASK                  0x0002
#define SGMII2_RX3_CONTROL7_SLCAL_VALID_OVRD_ALIGN                 0
#define SGMII2_RX3_CONTROL7_SLCAL_VALID_OVRD_BITS                  1
#define SGMII2_RX3_CONTROL7_SLCAL_VALID_OVRD_SHIFT                 1

/* SGMII2_RX3 :: control7 :: slcal_valid_ovrd_val [00:00] */
#define Wr_SGMII2_RX3_control7_slcal_valid_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL7,0x1,0,x)
#define Rd_SGMII2_RX3_control7_slcal_valid_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL7,0x1,0)
#define SGMII2_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_MASK              0x0001
#define SGMII2_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_ALIGN             0
#define SGMII2_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_BITS              1
#define SGMII2_RX3_CONTROL7_SLCAL_VALID_OVRD_VAL_SHIFT             0


/****************************************************************************
 * SGMII2_RX3 :: control8
 ***************************************************************************/
/* SGMII2_RX3 :: control8 :: reserved0 [15:15] */
#define SGMII2_RX3_CONTROL8_RESERVED0_MASK                         0x8000
#define SGMII2_RX3_CONTROL8_RESERVED0_ALIGN                        0
#define SGMII2_RX3_CONTROL8_RESERVED0_BITS                         1
#define SGMII2_RX3_CONTROL8_RESERVED0_SHIFT                        15

/* SGMII2_RX3 :: control8 :: rx_sloff2_ovrd [14:14] */
#define Wr_SGMII2_RX3_control8_rx_sloff2_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL8,0x4000,14,x)
#define Rd_SGMII2_RX3_control8_rx_sloff2_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL8,0x4000,14)
#define SGMII2_RX3_CONTROL8_RX_SLOFF2_OVRD_MASK                    0x4000
#define SGMII2_RX3_CONTROL8_RX_SLOFF2_OVRD_ALIGN                   0
#define SGMII2_RX3_CONTROL8_RX_SLOFF2_OVRD_BITS                    1
#define SGMII2_RX3_CONTROL8_RX_SLOFF2_OVRD_SHIFT                   14

/* SGMII2_RX3 :: control8 :: rx_sloff2_ovrd_val [13:10] */
#define Wr_SGMII2_RX3_control8_rx_sloff2_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL8,0x3c00,10,x)
#define Rd_SGMII2_RX3_control8_rx_sloff2_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL8,0x3c00,10)
#define SGMII2_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_MASK                0x3c00
#define SGMII2_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_ALIGN               0
#define SGMII2_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_BITS                4
#define SGMII2_RX3_CONTROL8_RX_SLOFF2_OVRD_VAL_SHIFT               10

/* SGMII2_RX3 :: control8 :: rx_sloff1_ovrd [09:09] */
#define Wr_SGMII2_RX3_control8_rx_sloff1_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL8,0x200,9,x)
#define Rd_SGMII2_RX3_control8_rx_sloff1_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL8,0x200,9)
#define SGMII2_RX3_CONTROL8_RX_SLOFF1_OVRD_MASK                    0x0200
#define SGMII2_RX3_CONTROL8_RX_SLOFF1_OVRD_ALIGN                   0
#define SGMII2_RX3_CONTROL8_RX_SLOFF1_OVRD_BITS                    1
#define SGMII2_RX3_CONTROL8_RX_SLOFF1_OVRD_SHIFT                   9

/* SGMII2_RX3 :: control8 :: rx_sloff1_ovrd_val [08:05] */
#define Wr_SGMII2_RX3_control8_rx_sloff1_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL8,0x1e0,5,x)
#define Rd_SGMII2_RX3_control8_rx_sloff1_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL8,0x1e0,5)
#define SGMII2_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_MASK                0x01e0
#define SGMII2_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_ALIGN               0
#define SGMII2_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_BITS                4
#define SGMII2_RX3_CONTROL8_RX_SLOFF1_OVRD_VAL_SHIFT               5

/* SGMII2_RX3 :: control8 :: rx_sloff0_ovrd [04:04] */
#define Wr_SGMII2_RX3_control8_rx_sloff0_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL8,0x10,4,x)
#define Rd_SGMII2_RX3_control8_rx_sloff0_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL8,0x10,4)
#define SGMII2_RX3_CONTROL8_RX_SLOFF0_OVRD_MASK                    0x0010
#define SGMII2_RX3_CONTROL8_RX_SLOFF0_OVRD_ALIGN                   0
#define SGMII2_RX3_CONTROL8_RX_SLOFF0_OVRD_BITS                    1
#define SGMII2_RX3_CONTROL8_RX_SLOFF0_OVRD_SHIFT                   4

/* SGMII2_RX3 :: control8 :: rx_sloff0_ovrd_val [03:00] */
#define Wr_SGMII2_RX3_control8_rx_sloff0_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL8,0xf,0,x)
#define Rd_SGMII2_RX3_control8_rx_sloff0_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL8,0xf,0)
#define SGMII2_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_MASK                0x000f
#define SGMII2_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_ALIGN               0
#define SGMII2_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_BITS                4
#define SGMII2_RX3_CONTROL8_RX_SLOFF0_OVRD_VAL_SHIFT               0


/****************************************************************************
 * SGMII2_RX3 :: control9
 ***************************************************************************/
/* SGMII2_RX3 :: control9 :: cal_state_ovrd_val [15:13] */
#define Wr_SGMII2_RX3_control9_cal_state_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL9,0xe000,13,x)
#define Rd_SGMII2_RX3_control9_cal_state_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL9,0xe000,13)
#define SGMII2_RX3_CONTROL9_CAL_STATE_OVRD_VAL_MASK                0xe000
#define SGMII2_RX3_CONTROL9_CAL_STATE_OVRD_VAL_ALIGN               0
#define SGMII2_RX3_CONTROL9_CAL_STATE_OVRD_VAL_BITS                3
#define SGMII2_RX3_CONTROL9_CAL_STATE_OVRD_VAL_SHIFT               13

/* SGMII2_RX3 :: control9 :: rx_slicer_calvalid_ovrd [12:12] */
#define Wr_SGMII2_RX3_control9_rx_slicer_calvalid_ovrd(x) WriteRegBits16(SGMII2_RX3_CONTROL9,0x1000,12,x)
#define Rd_SGMII2_RX3_control9_rx_slicer_calvalid_ovrd(x) ReadRegBits16(SGMII2_RX3_CONTROL9,0x1000,12)
#define SGMII2_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_MASK           0x1000
#define SGMII2_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_ALIGN          0
#define SGMII2_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_BITS           1
#define SGMII2_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_SHIFT          12

/* SGMII2_RX3 :: control9 :: rx_slicer_calvalid_ovrd_val [11:11] */
#define Wr_SGMII2_RX3_control9_rx_slicer_calvalid_ovrd_val(x) WriteRegBits16(SGMII2_RX3_CONTROL9,0x800,11,x)
#define Rd_SGMII2_RX3_control9_rx_slicer_calvalid_ovrd_val(x) ReadRegBits16(SGMII2_RX3_CONTROL9,0x800,11)
#define SGMII2_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_MASK       0x0800
#define SGMII2_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_ALIGN      0
#define SGMII2_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_BITS       1
#define SGMII2_RX3_CONTROL9_RX_SLICER_CALVALID_OVRD_VAL_SHIFT      11

/* SGMII2_RX3 :: control9 :: slcal_up_thres [10:00] */
#define Wr_SGMII2_RX3_control9_slcal_up_thres(x) WriteRegBits16(SGMII2_RX3_CONTROL9,0x7ff,0,x)
#define Rd_SGMII2_RX3_control9_slcal_up_thres(x) ReadRegBits16(SGMII2_RX3_CONTROL9,0x7ff,0)
#define SGMII2_RX3_CONTROL9_SLCAL_UP_THRES_MASK                    0x07ff
#define SGMII2_RX3_CONTROL9_SLCAL_UP_THRES_ALIGN                   0
#define SGMII2_RX3_CONTROL9_SLCAL_UP_THRES_BITS                    11
#define SGMII2_RX3_CONTROL9_SLCAL_UP_THRES_SHIFT                   0


/****************************************************************************
 * SGMII2_RX3 :: control10
 ***************************************************************************/
/* SGMII2_RX3 :: control10 :: slicer_interval_time [15:11] */
#define Wr_SGMII2_RX3_control10_slicer_interval_time(x) WriteRegBits16(SGMII2_RX3_CONTROL10,0xf800,11,x)
#define Rd_SGMII2_RX3_control10_slicer_interval_time(x) ReadRegBits16(SGMII2_RX3_CONTROL10,0xf800,11)
#define SGMII2_RX3_CONTROL10_SLICER_INTERVAL_TIME_MASK             0xf800
#define SGMII2_RX3_CONTROL10_SLICER_INTERVAL_TIME_ALIGN            0
#define SGMII2_RX3_CONTROL10_SLICER_INTERVAL_TIME_BITS             5
#define SGMII2_RX3_CONTROL10_SLICER_INTERVAL_TIME_SHIFT            11

/* SGMII2_RX3 :: control10 :: slcal_dn_thres [10:00] */
#define Wr_SGMII2_RX3_control10_slcal_dn_thres(x) WriteRegBits16(SGMII2_RX3_CONTROL10,0x7ff,0,x)
#define Rd_SGMII2_RX3_control10_slcal_dn_thres(x) ReadRegBits16(SGMII2_RX3_CONTROL10,0x7ff,0)
#define SGMII2_RX3_CONTROL10_SLCAL_DN_THRES_MASK                   0x07ff
#define SGMII2_RX3_CONTROL10_SLCAL_DN_THRES_ALIGN                  0
#define SGMII2_RX3_CONTROL10_SLCAL_DN_THRES_BITS                   11
#define SGMII2_RX3_CONTROL10_SLCAL_DN_THRES_SHIFT                  0


/****************************************************************************
 * SGMII2_RX3 :: control11
 ***************************************************************************/
/* SGMII2_RX3 :: control11 :: recal_ind_clr [15:15] */
#define Wr_SGMII2_RX3_control11_recal_ind_clr(x) WriteRegBits16(SGMII2_RX3_CONTROL11,0x8000,15,x)
#define Rd_SGMII2_RX3_control11_recal_ind_clr(x) ReadRegBits16(SGMII2_RX3_CONTROL11,0x8000,15)
#define SGMII2_RX3_CONTROL11_RECAL_IND_CLR_MASK                    0x8000
#define SGMII2_RX3_CONTROL11_RECAL_IND_CLR_ALIGN                   0
#define SGMII2_RX3_CONTROL11_RECAL_IND_CLR_BITS                    1
#define SGMII2_RX3_CONTROL11_RECAL_IND_CLR_SHIFT                   15

/* SGMII2_RX3 :: control11 :: slcal_init_time [14:07] */
#define Wr_SGMII2_RX3_control11_slcal_init_time(x) WriteRegBits16(SGMII2_RX3_CONTROL11,0x7f80,7,x)
#define Rd_SGMII2_RX3_control11_slcal_init_time(x) ReadRegBits16(SGMII2_RX3_CONTROL11,0x7f80,7)
#define SGMII2_RX3_CONTROL11_SLCAL_INIT_TIME_MASK                  0x7f80
#define SGMII2_RX3_CONTROL11_SLCAL_INIT_TIME_ALIGN                 0
#define SGMII2_RX3_CONTROL11_SLCAL_INIT_TIME_BITS                  8
#define SGMII2_RX3_CONTROL11_SLCAL_INIT_TIME_SHIFT                 7

/* SGMII2_RX3 :: control11 :: reserved0 [06:02] */
#define SGMII2_RX3_CONTROL11_RESERVED0_MASK                        0x007c
#define SGMII2_RX3_CONTROL11_RESERVED0_ALIGN                       0
#define SGMII2_RX3_CONTROL11_RESERVED0_BITS                        5
#define SGMII2_RX3_CONTROL11_RESERVED0_SHIFT                       2

/* SGMII2_RX3 :: control11 :: pm_RxSlicerCalByp [01:01] */
#define Wr_SGMII2_RX3_control11_pm_RxSlicerCalByp(x) WriteRegBits16(SGMII2_RX3_CONTROL11,0x2,1,x)
#define Rd_SGMII2_RX3_control11_pm_RxSlicerCalByp(x) ReadRegBits16(SGMII2_RX3_CONTROL11,0x2,1)
#define SGMII2_RX3_CONTROL11_PM_RXSLICERCALBYP_MASK                0x0002
#define SGMII2_RX3_CONTROL11_PM_RXSLICERCALBYP_ALIGN               0
#define SGMII2_RX3_CONTROL11_PM_RXSLICERCALBYP_BITS                1
#define SGMII2_RX3_CONTROL11_PM_RXSLICERCALBYP_SHIFT               1

/* SGMII2_RX3 :: control11 :: pm_RxLimitAmpCalByp [00:00] */
#define Wr_SGMII2_RX3_control11_pm_RxLimitAmpCalByp(x) WriteRegBits16(SGMII2_RX3_CONTROL11,0x1,0,x)
#define Rd_SGMII2_RX3_control11_pm_RxLimitAmpCalByp(x) ReadRegBits16(SGMII2_RX3_CONTROL11,0x1,0)
#define SGMII2_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_MASK              0x0001
#define SGMII2_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_ALIGN             0
#define SGMII2_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_BITS              1
#define SGMII2_RX3_CONTROL11_PM_RXLIMITAMPCALBYP_SHIFT             0


/****************************************************************************
 * bcm89530_top_bridge_sgmii_x3_SGMII_LANE2_SGMII2_Combo_IEEE0
 ***************************************************************************/
/****************************************************************************
 * SGMII2_Combo_IEEE0 :: MIICntl
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: MIICntl :: rst_hw [15:15] */
#define Wr_SGMII2_Combo_IEEE0_MIICntl_rst_hw(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x8000,15,x)
#define Rd_SGMII2_Combo_IEEE0_MIICntl_rst_hw(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x8000,15)
#define SGMII2_COMBO_IEEE0_MIICNTL_RST_HW_MASK                     0x8000
#define SGMII2_COMBO_IEEE0_MIICNTL_RST_HW_ALIGN                    0
#define SGMII2_COMBO_IEEE0_MIICNTL_RST_HW_BITS                     1
#define SGMII2_COMBO_IEEE0_MIICNTL_RST_HW_SHIFT                    15

/* SGMII2_Combo_IEEE0 :: MIICntl :: gloopback [14:14] */
#define Wr_SGMII2_Combo_IEEE0_MIICntl_gloopback(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x4000,14,x)
#define Rd_SGMII2_Combo_IEEE0_MIICntl_gloopback(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x4000,14)
#define SGMII2_COMBO_IEEE0_MIICNTL_GLOOPBACK_MASK                  0x4000
#define SGMII2_COMBO_IEEE0_MIICNTL_GLOOPBACK_ALIGN                 0
#define SGMII2_COMBO_IEEE0_MIICNTL_GLOOPBACK_BITS                  1
#define SGMII2_COMBO_IEEE0_MIICNTL_GLOOPBACK_SHIFT                 14

/* SGMII2_Combo_IEEE0 :: MIICntl :: manual_speed0 [13:13] */
#define Wr_SGMII2_Combo_IEEE0_MIICntl_manual_speed0(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x2000,13,x)
#define Rd_SGMII2_Combo_IEEE0_MIICntl_manual_speed0(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x2000,13)
#define SGMII2_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_MASK              0x2000
#define SGMII2_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_ALIGN             0
#define SGMII2_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_BITS              1
#define SGMII2_COMBO_IEEE0_MIICNTL_MANUAL_SPEED0_SHIFT             13

/* SGMII2_Combo_IEEE0 :: MIICntl :: autoneg_enable [12:12] */
#define Wr_SGMII2_Combo_IEEE0_MIICntl_autoneg_enable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x1000,12,x)
#define Rd_SGMII2_Combo_IEEE0_MIICntl_autoneg_enable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x1000,12)
#define SGMII2_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_MASK             0x1000
#define SGMII2_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_ALIGN            0
#define SGMII2_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_BITS             1
#define SGMII2_COMBO_IEEE0_MIICNTL_AUTONEG_ENABLE_SHIFT            12

/* SGMII2_Combo_IEEE0 :: MIICntl :: pwrdwn_sw [11:11] */
#define Wr_SGMII2_Combo_IEEE0_MIICntl_pwrdwn_sw(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x800,11,x)
#define Rd_SGMII2_Combo_IEEE0_MIICntl_pwrdwn_sw(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x800,11)
#define SGMII2_COMBO_IEEE0_MIICNTL_PWRDWN_SW_MASK                  0x0800
#define SGMII2_COMBO_IEEE0_MIICNTL_PWRDWN_SW_ALIGN                 0
#define SGMII2_COMBO_IEEE0_MIICNTL_PWRDWN_SW_BITS                  1
#define SGMII2_COMBO_IEEE0_MIICNTL_PWRDWN_SW_SHIFT                 11

/* SGMII2_Combo_IEEE0 :: MIICntl :: reserved0 [10:10] */
#define SGMII2_COMBO_IEEE0_MIICNTL_RESERVED0_MASK                  0x0400
#define SGMII2_COMBO_IEEE0_MIICNTL_RESERVED0_ALIGN                 0
#define SGMII2_COMBO_IEEE0_MIICNTL_RESERVED0_BITS                  1
#define SGMII2_COMBO_IEEE0_MIICNTL_RESERVED0_SHIFT                 10

/* SGMII2_Combo_IEEE0 :: MIICntl :: restart_autoneg [09:09] */
#define Wr_SGMII2_Combo_IEEE0_MIICntl_restart_autoneg(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x200,9,x)
#define Rd_SGMII2_Combo_IEEE0_MIICntl_restart_autoneg(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x200,9)
#define SGMII2_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_MASK            0x0200
#define SGMII2_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_ALIGN           0
#define SGMII2_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_BITS            1
#define SGMII2_COMBO_IEEE0_MIICNTL_RESTART_AUTONEG_SHIFT           9

/* SGMII2_Combo_IEEE0 :: MIICntl :: full_duplex [08:08] */
#define Wr_SGMII2_Combo_IEEE0_MIICntl_full_duplex(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x100,8,x)
#define Rd_SGMII2_Combo_IEEE0_MIICntl_full_duplex(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x100,8)
#define SGMII2_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_MASK                0x0100
#define SGMII2_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_ALIGN               0
#define SGMII2_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_BITS                1
#define SGMII2_COMBO_IEEE0_MIICNTL_FULL_DUPLEX_SHIFT               8

/* SGMII2_Combo_IEEE0 :: MIICntl :: collision_test_en [07:07] */
#define Wr_SGMII2_Combo_IEEE0_MIICntl_collision_test_en(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x80,7,x)
#define Rd_SGMII2_Combo_IEEE0_MIICntl_collision_test_en(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x80,7)
#define SGMII2_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_MASK          0x0080
#define SGMII2_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_ALIGN         0
#define SGMII2_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_BITS          1
#define SGMII2_COMBO_IEEE0_MIICNTL_COLLISION_TEST_EN_SHIFT         7

/* SGMII2_Combo_IEEE0 :: MIICntl :: manual_speed1 [06:06] */
#define Wr_SGMII2_Combo_IEEE0_MIICntl_manual_speed1(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x40,6,x)
#define Rd_SGMII2_Combo_IEEE0_MIICntl_manual_speed1(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIICNTL,0x40,6)
#define SGMII2_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_MASK              0x0040
#define SGMII2_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_ALIGN             0
#define SGMII2_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_BITS              1
#define SGMII2_COMBO_IEEE0_MIICNTL_MANUAL_SPEED1_SHIFT             6

/* SGMII2_Combo_IEEE0 :: MIICntl :: reserved1 [05:00] */
#define SGMII2_COMBO_IEEE0_MIICNTL_RESERVED1_MASK                  0x003f
#define SGMII2_COMBO_IEEE0_MIICNTL_RESERVED1_ALIGN                 0
#define SGMII2_COMBO_IEEE0_MIICNTL_RESERVED1_BITS                  6
#define SGMII2_COMBO_IEEE0_MIICNTL_RESERVED1_SHIFT                 0


/****************************************************************************
 * SGMII2_Combo_IEEE0 :: MIIStat
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: MIIStat :: s100BASE_T4_capable [15:15] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_s100BASE_T4_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x8000,15,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_s100BASE_T4_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x8000,15)
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_MASK        0x8000
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_ALIGN       0
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_BITS        1
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T4_CAPABLE_SHIFT       15

/* SGMII2_Combo_IEEE0 :: MIIStat :: s100BASE_X_FULL_Duplex_capable [14:14] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x4000,14,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_s100BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x4000,14)
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 14

/* SGMII2_Combo_IEEE0 :: MIIStat :: s100BASE_X_HALF_Duplex_capable [13:13] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x2000,13,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_s100BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x2000,13)
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 13

/* SGMII2_Combo_IEEE0 :: MIIStat :: s10BASE_T_FULL_Duplex_capable [12:12] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x1000,12,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_s10BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x1000,12)
#define SGMII2_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x1000
#define SGMII2_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIISTAT_S10BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 12

/* SGMII2_Combo_IEEE0 :: MIIStat :: s10BASE_T_HALF_Duplex_capable [11:11] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x800,11,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_s10BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x800,11)
#define SGMII2_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x0800
#define SGMII2_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIISTAT_S10BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 11

/* SGMII2_Combo_IEEE0 :: MIIStat :: s100BASE_T2_FULL_Duplex_capable [10:10] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x400,10,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_s100BASE_T2_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x400,10)
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_MASK 0x0400
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T2_FULL_DUPLEX_CAPABLE_SHIFT 10

/* SGMII2_Combo_IEEE0 :: MIIStat :: s100BASE_T2_HALF_Duplex_capable [09:09] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x200,9,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_s100BASE_T2_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x200,9)
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_MASK 0x0200
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIISTAT_S100BASE_T2_HALF_DUPLEX_CAPABLE_SHIFT 9

/* SGMII2_Combo_IEEE0 :: MIIStat :: extended_status [08:08] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_extended_status(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x100,8,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_extended_status(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x100,8)
#define SGMII2_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_MASK            0x0100
#define SGMII2_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_ALIGN           0
#define SGMII2_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_BITS            1
#define SGMII2_COMBO_IEEE0_MIISTAT_EXTENDED_STATUS_SHIFT           8

/* SGMII2_Combo_IEEE0 :: MIIStat :: reserved0 [07:07] */
#define SGMII2_COMBO_IEEE0_MIISTAT_RESERVED0_MASK                  0x0080
#define SGMII2_COMBO_IEEE0_MIISTAT_RESERVED0_ALIGN                 0
#define SGMII2_COMBO_IEEE0_MIISTAT_RESERVED0_BITS                  1
#define SGMII2_COMBO_IEEE0_MIISTAT_RESERVED0_SHIFT                 7

/* SGMII2_Combo_IEEE0 :: MIIStat :: mf_preamble_supression [06:06] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_mf_preamble_supression(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x40,6,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_mf_preamble_supression(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x40,6)
#define SGMII2_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_MASK     0x0040
#define SGMII2_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_ALIGN    0
#define SGMII2_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_BITS     1
#define SGMII2_COMBO_IEEE0_MIISTAT_MF_PREAMBLE_SUPRESSION_SHIFT    6

/* SGMII2_Combo_IEEE0 :: MIIStat :: autoneg_complete [05:05] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_autoneg_complete(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x20,5,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_autoneg_complete(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x20,5)
#define SGMII2_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_MASK           0x0020
#define SGMII2_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_ALIGN          0
#define SGMII2_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_BITS           1
#define SGMII2_COMBO_IEEE0_MIISTAT_AUTONEG_COMPLETE_SHIFT          5

/* SGMII2_Combo_IEEE0 :: MIIStat :: remote_fault [04:04] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_remote_fault(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x10,4,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_remote_fault(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x10,4)
#define SGMII2_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_MASK               0x0010
#define SGMII2_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_ALIGN              0
#define SGMII2_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_BITS               1
#define SGMII2_COMBO_IEEE0_MIISTAT_REMOTE_FAULT_SHIFT              4

/* SGMII2_Combo_IEEE0 :: MIIStat :: autoneg_ability [03:03] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_autoneg_ability(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x8,3,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_autoneg_ability(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x8,3)
#define SGMII2_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_MASK            0x0008
#define SGMII2_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_ALIGN           0
#define SGMII2_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_BITS            1
#define SGMII2_COMBO_IEEE0_MIISTAT_AUTONEG_ABILITY_SHIFT           3

/* SGMII2_Combo_IEEE0 :: MIIStat :: link_status [02:02] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_link_status(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x4,2,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_link_status(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x4,2)
#define SGMII2_COMBO_IEEE0_MIISTAT_LINK_STATUS_MASK                0x0004
#define SGMII2_COMBO_IEEE0_MIISTAT_LINK_STATUS_ALIGN               0
#define SGMII2_COMBO_IEEE0_MIISTAT_LINK_STATUS_BITS                1
#define SGMII2_COMBO_IEEE0_MIISTAT_LINK_STATUS_SHIFT               2

/* SGMII2_Combo_IEEE0 :: MIIStat :: jabber_detect [01:01] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_jabber_detect(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x2,1,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_jabber_detect(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x2,1)
#define SGMII2_COMBO_IEEE0_MIISTAT_JABBER_DETECT_MASK              0x0002
#define SGMII2_COMBO_IEEE0_MIISTAT_JABBER_DETECT_ALIGN             0
#define SGMII2_COMBO_IEEE0_MIISTAT_JABBER_DETECT_BITS              1
#define SGMII2_COMBO_IEEE0_MIISTAT_JABBER_DETECT_SHIFT             1

/* SGMII2_Combo_IEEE0 :: MIIStat :: extended_capability [00:00] */
#define Wr_SGMII2_Combo_IEEE0_MIIStat_extended_capability(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x1,0,x)
#define Rd_SGMII2_Combo_IEEE0_MIIStat_extended_capability(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIISTAT,0x1,0)
#define SGMII2_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_MASK        0x0001
#define SGMII2_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_ALIGN       0
#define SGMII2_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_BITS        1
#define SGMII2_COMBO_IEEE0_MIISTAT_EXTENDED_CAPABILITY_SHIFT       0


/****************************************************************************
 * SGMII2_Combo_IEEE0 :: Id1
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: Id1 :: regid [15:00] */
#define Wr_SGMII2_Combo_IEEE0_Id1_regid(x) WriteReg16(SGMII2_COMBO_IEEE0_ID1,x)
#define Rd_SGMII2_Combo_IEEE0_Id1_regid(x) ReadReg16(SGMII2_COMBO_IEEE0_ID1)
#define SGMII2_COMBO_IEEE0_ID1_REGID_MASK                          0xffff
#define SGMII2_COMBO_IEEE0_ID1_REGID_ALIGN                         0
#define SGMII2_COMBO_IEEE0_ID1_REGID_BITS                          16
#define SGMII2_COMBO_IEEE0_ID1_REGID_SHIFT                         0


/****************************************************************************
 * SGMII2_Combo_IEEE0 :: Id2
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: Id2 :: regid [15:00] */
#define Wr_SGMII2_Combo_IEEE0_Id2_regid(x) WriteReg16(SGMII2_COMBO_IEEE0_ID2,x)
#define Rd_SGMII2_Combo_IEEE0_Id2_regid(x) ReadReg16(SGMII2_COMBO_IEEE0_ID2)
#define SGMII2_COMBO_IEEE0_ID2_REGID_MASK                          0xffff
#define SGMII2_COMBO_IEEE0_ID2_REGID_ALIGN                         0
#define SGMII2_COMBO_IEEE0_ID2_REGID_BITS                          16
#define SGMII2_COMBO_IEEE0_ID2_REGID_SHIFT                         0


/****************************************************************************
 * SGMII2_Combo_IEEE0 :: AutoNegAdv
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: AutoNegAdv :: next_page [15:15] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegAdv_next_page(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x8000,15,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegAdv_next_page(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x8000,15)
#define SGMII2_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_MASK               0x8000
#define SGMII2_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_ALIGN              0
#define SGMII2_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_BITS               1
#define SGMII2_COMBO_IEEE0_AUTONEGADV_NEXT_PAGE_SHIFT              15

/* SGMII2_Combo_IEEE0 :: AutoNegAdv :: reserved0 [14:14] */
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED0_MASK               0x4000
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED0_ALIGN              0
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED0_BITS               1
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED0_SHIFT              14

/* SGMII2_Combo_IEEE0 :: AutoNegAdv :: remote_fault [13:12] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegAdv_remote_fault(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x3000,12,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegAdv_remote_fault(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x3000,12)
#define SGMII2_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_MASK            0x3000
#define SGMII2_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_ALIGN           0
#define SGMII2_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_BITS            2
#define SGMII2_COMBO_IEEE0_AUTONEGADV_REMOTE_FAULT_SHIFT           12

/* SGMII2_Combo_IEEE0 :: AutoNegAdv :: reserved1 [11:09] */
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED1_MASK               0x0e00
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED1_ALIGN              0
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED1_BITS               3
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED1_SHIFT              9

/* SGMII2_Combo_IEEE0 :: AutoNegAdv :: pause [08:07] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegAdv_pause(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x180,7,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegAdv_pause(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x180,7)
#define SGMII2_COMBO_IEEE0_AUTONEGADV_PAUSE_MASK                   0x0180
#define SGMII2_COMBO_IEEE0_AUTONEGADV_PAUSE_ALIGN                  0
#define SGMII2_COMBO_IEEE0_AUTONEGADV_PAUSE_BITS                   2
#define SGMII2_COMBO_IEEE0_AUTONEGADV_PAUSE_SHIFT                  7

/* SGMII2_Combo_IEEE0 :: AutoNegAdv :: half_duplex [06:06] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegAdv_half_duplex(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x40,6,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegAdv_half_duplex(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x40,6)
#define SGMII2_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_MASK             0x0040
#define SGMII2_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_ALIGN            0
#define SGMII2_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_BITS             1
#define SGMII2_COMBO_IEEE0_AUTONEGADV_HALF_DUPLEX_SHIFT            6

/* SGMII2_Combo_IEEE0 :: AutoNegAdv :: full_duplex [05:05] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegAdv_full_duplex(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x20,5,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegAdv_full_duplex(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGADV,0x20,5)
#define SGMII2_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_MASK             0x0020
#define SGMII2_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_ALIGN            0
#define SGMII2_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_BITS             1
#define SGMII2_COMBO_IEEE0_AUTONEGADV_FULL_DUPLEX_SHIFT            5

/* SGMII2_Combo_IEEE0 :: AutoNegAdv :: reserved2 [04:00] */
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED2_MASK               0x001f
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED2_ALIGN              0
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED2_BITS               5
#define SGMII2_COMBO_IEEE0_AUTONEGADV_RESERVED2_SHIFT              0


/****************************************************************************
 * SGMII2_Combo_IEEE0 :: AutoNegLPAbil
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil :: next_page [15:15] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil_next_page(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x8000,15,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil_next_page(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x8000,15)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_MASK            0x8000
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_ALIGN           0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_BITS            1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_NEXT_PAGE_SHIFT           15

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil :: acknowledge [14:14] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil_acknowledge(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x4000,14,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil_acknowledge(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x4000,14)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_MASK          0x4000
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_ALIGN         0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_BITS          1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_ACKNOWLEDGE_SHIFT         14

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil :: remote_fault [13:12] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil_remote_fault(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x3000,12,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil_remote_fault(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x3000,12)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_MASK         0x3000
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_ALIGN        0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_BITS         2
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_REMOTE_FAULT_SHIFT        12

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil :: reserved0 [11:09] */
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_MASK            0x0e00
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_ALIGN           0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_BITS            3
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_RESERVED0_SHIFT           9

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil :: pause [08:07] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil_pause(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x180,7,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil_pause(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x180,7)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_MASK                0x0180
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_ALIGN               0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_BITS                2
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_PAUSE_SHIFT               7

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil :: half_duplex [06:06] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil_half_duplex(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x40,6,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil_half_duplex(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x40,6)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_MASK          0x0040
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_ALIGN         0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_BITS          1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_HALF_DUPLEX_SHIFT         6

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil :: full_duplex [05:05] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil_full_duplex(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x20,5,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil_full_duplex(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x20,5)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_MASK          0x0020
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_ALIGN         0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_BITS          1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_FULL_DUPLEX_SHIFT         5

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil :: reserved1 [04:01] */
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_MASK            0x001e
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_ALIGN           0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_BITS            4
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_RESERVED1_SHIFT           1

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil :: sgmii_mode [00:00] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil_sgmii_mode(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x1,0,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil_sgmii_mode(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL,0x1,0)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_MASK           0x0001
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_ALIGN          0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_BITS           1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL_SGMII_MODE_SHIFT          0


/****************************************************************************
 * SGMII2_Combo_IEEE0 :: AutoNegExp
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: AutoNegExp :: reserved0 [15:03] */
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_RESERVED0_MASK               0xfff8
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_RESERVED0_ALIGN              0
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_RESERVED0_BITS               13
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_RESERVED0_SHIFT              3

/* SGMII2_Combo_IEEE0 :: AutoNegExp :: next_page_ability [02:02] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegExp_next_page_ability(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGEXP,0x4,2,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegExp_next_page_ability(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGEXP,0x4,2)
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_MASK       0x0004
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_ALIGN      0
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_BITS       1
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_NEXT_PAGE_ABILITY_SHIFT      2

/* SGMII2_Combo_IEEE0 :: AutoNegExp :: page_received [01:01] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegExp_page_received(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGEXP,0x2,1,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegExp_page_received(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGEXP,0x2,1)
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_MASK           0x0002
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_ALIGN          0
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_BITS           1
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_PAGE_RECEIVED_SHIFT          1

/* SGMII2_Combo_IEEE0 :: AutoNegExp :: reserved1 [00:00] */
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_RESERVED1_MASK               0x0001
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_RESERVED1_ALIGN              0
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_RESERVED1_BITS               1
#define SGMII2_COMBO_IEEE0_AUTONEGEXP_RESERVED1_SHIFT              0


/****************************************************************************
 * SGMII2_Combo_IEEE0 :: AutoNegNP
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: AutoNegNP :: Next_Page [15:15] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegNP_Next_Page(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x8000,15,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegNP_Next_Page(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x8000,15)
#define SGMII2_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_MASK                0x8000
#define SGMII2_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_ALIGN               0
#define SGMII2_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_BITS                1
#define SGMII2_COMBO_IEEE0_AUTONEGNP_NEXT_PAGE_SHIFT               15

/* SGMII2_Combo_IEEE0 :: AutoNegNP :: Ack [14:14] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegNP_Ack(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x4000,14,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegNP_Ack(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x4000,14)
#define SGMII2_COMBO_IEEE0_AUTONEGNP_ACK_MASK                      0x4000
#define SGMII2_COMBO_IEEE0_AUTONEGNP_ACK_ALIGN                     0
#define SGMII2_COMBO_IEEE0_AUTONEGNP_ACK_BITS                      1
#define SGMII2_COMBO_IEEE0_AUTONEGNP_ACK_SHIFT                     14

/* SGMII2_Combo_IEEE0 :: AutoNegNP :: Message_Page [13:13] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegNP_Message_Page(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x2000,13,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegNP_Message_Page(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x2000,13)
#define SGMII2_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_MASK             0x2000
#define SGMII2_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_ALIGN            0
#define SGMII2_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_BITS             1
#define SGMII2_COMBO_IEEE0_AUTONEGNP_MESSAGE_PAGE_SHIFT            13

/* SGMII2_Combo_IEEE0 :: AutoNegNP :: Ack2 [12:12] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegNP_Ack2(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x1000,12,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegNP_Ack2(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x1000,12)
#define SGMII2_COMBO_IEEE0_AUTONEGNP_ACK2_MASK                     0x1000
#define SGMII2_COMBO_IEEE0_AUTONEGNP_ACK2_ALIGN                    0
#define SGMII2_COMBO_IEEE0_AUTONEGNP_ACK2_BITS                     1
#define SGMII2_COMBO_IEEE0_AUTONEGNP_ACK2_SHIFT                    12

/* SGMII2_Combo_IEEE0 :: AutoNegNP :: Toggle [11:11] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegNP_Toggle(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x800,11,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegNP_Toggle(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x800,11)
#define SGMII2_COMBO_IEEE0_AUTONEGNP_TOGGLE_MASK                   0x0800
#define SGMII2_COMBO_IEEE0_AUTONEGNP_TOGGLE_ALIGN                  0
#define SGMII2_COMBO_IEEE0_AUTONEGNP_TOGGLE_BITS                   1
#define SGMII2_COMBO_IEEE0_AUTONEGNP_TOGGLE_SHIFT                  11

/* SGMII2_Combo_IEEE0 :: AutoNegNP :: Message [10:00] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegNP_Message(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x7ff,0,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegNP_Message(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGNP,0x7ff,0)
#define SGMII2_COMBO_IEEE0_AUTONEGNP_MESSAGE_MASK                  0x07ff
#define SGMII2_COMBO_IEEE0_AUTONEGNP_MESSAGE_ALIGN                 0
#define SGMII2_COMBO_IEEE0_AUTONEGNP_MESSAGE_BITS                  11
#define SGMII2_COMBO_IEEE0_AUTONEGNP_MESSAGE_SHIFT                 0


/****************************************************************************
 * SGMII2_Combo_IEEE0 :: AutoNegLPAbil2
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil2 :: Next_Page [15:15] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Next_Page(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x8000,15,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Next_Page(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x8000,15)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_MASK           0x8000
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_ALIGN          0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_BITS           1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_NEXT_PAGE_SHIFT          15

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil2 :: Ack [14:14] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Ack(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x4000,14,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Ack(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x4000,14)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_ACK_MASK                 0x4000
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_ACK_ALIGN                0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_ACK_BITS                 1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_ACK_SHIFT                14

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil2 :: Message_Page [13:13] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Message_Page(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x2000,13,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Message_Page(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x2000,13)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_MASK        0x2000
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_ALIGN       0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_BITS        1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_PAGE_SHIFT       13

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil2 :: Ack2 [12:12] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Ack2(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x1000,12,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Ack2(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x1000,12)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_MASK                0x1000
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_ALIGN               0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_BITS                1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_ACK2_SHIFT               12

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil2 :: Toggle [11:11] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Toggle(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x800,11,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Toggle(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x800,11)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_MASK              0x0800
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_ALIGN             0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_BITS              1
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_TOGGLE_SHIFT             11

/* SGMII2_Combo_IEEE0 :: AutoNegLPAbil2 :: Message [10:00] */
#define Wr_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Message(x) WriteRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x7ff,0,x)
#define Rd_SGMII2_Combo_IEEE0_AutoNegLPAbil2_Message(x) ReadRegBits16(SGMII2_COMBO_IEEE0_AUTONEGLPABIL2,0x7ff,0)
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_MASK             0x07ff
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_ALIGN            0
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_BITS             11
#define SGMII2_COMBO_IEEE0_AUTONEGLPABIL2_MESSAGE_SHIFT            0


/****************************************************************************
 * SGMII2_Combo_IEEE0 :: MIIextStat
 ***************************************************************************/
/* SGMII2_Combo_IEEE0 :: MIIextStat :: s1000BASE_X_FULL_Duplex_capable [15:15] */
#define Wr_SGMII2_Combo_IEEE0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIIEXTSTAT,0x8000,15,x)
#define Rd_SGMII2_Combo_IEEE0_MIIextStat_s1000BASE_X_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIIEXTSTAT,0x8000,15)
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_MASK 0x8000
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_FULL_DUPLEX_CAPABLE_SHIFT 15

/* SGMII2_Combo_IEEE0 :: MIIextStat :: s1000BASE_X_HALF_Duplex_capable [14:14] */
#define Wr_SGMII2_Combo_IEEE0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIIEXTSTAT,0x4000,14,x)
#define Rd_SGMII2_Combo_IEEE0_MIIextStat_s1000BASE_X_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIIEXTSTAT,0x4000,14)
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_MASK 0x4000
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_X_HALF_DUPLEX_CAPABLE_SHIFT 14

/* SGMII2_Combo_IEEE0 :: MIIextStat :: s1000BASE_T_FULL_Duplex_capable [13:13] */
#define Wr_SGMII2_Combo_IEEE0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIIEXTSTAT,0x2000,13,x)
#define Rd_SGMII2_Combo_IEEE0_MIIextStat_s1000BASE_T_FULL_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIIEXTSTAT,0x2000,13)
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_MASK 0x2000
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_FULL_DUPLEX_CAPABLE_SHIFT 13

/* SGMII2_Combo_IEEE0 :: MIIextStat :: s1000BASE_T_HALF_Duplex_capable [12:12] */
#define Wr_SGMII2_Combo_IEEE0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) WriteRegBits16(SGMII2_COMBO_IEEE0_MIIEXTSTAT,0x1000,12,x)
#define Rd_SGMII2_Combo_IEEE0_MIIextStat_s1000BASE_T_HALF_Duplex_capable(x) ReadRegBits16(SGMII2_COMBO_IEEE0_MIIEXTSTAT,0x1000,12)
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_MASK 0x1000
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_ALIGN 0
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_BITS 1
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_S1000BASE_T_HALF_DUPLEX_CAPABLE_SHIFT 12

/* SGMII2_Combo_IEEE0 :: MIIextStat :: reserved0 [11:00] */
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_MASK               0x0fff
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_ALIGN              0
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_BITS               12
#define SGMII2_COMBO_IEEE0_MIIEXTSTAT_RESERVED0_SHIFT              0


/****************************************************************************
 * bcm89530_top_bridge_MISC
 ***************************************************************************/
/****************************************************************************
 * MISC :: model_rev_num
 ***************************************************************************/
/* MISC :: model_rev_num :: reserved0 [15:10] */
#define MISC_MODEL_REV_NUM_RESERVED0_MASK                          0xfc00
#define MISC_MODEL_REV_NUM_RESERVED0_ALIGN                         0
#define MISC_MODEL_REV_NUM_RESERVED0_BITS                          6
#define MISC_MODEL_REV_NUM_RESERVED0_SHIFT                         10

/* MISC :: model_rev_num :: model_num [09:04] */
#define Wr_MISC_model_rev_num_model_num(x) WriteRegBits16(MISC_MODEL_REV_NUM,0x3f0,4,x)
#define Rd_MISC_model_rev_num_model_num(x) ReadRegBits16(MISC_MODEL_REV_NUM,0x3f0,4)
#define MISC_MODEL_REV_NUM_MODEL_NUM_MASK                          0x03f0
#define MISC_MODEL_REV_NUM_MODEL_NUM_ALIGN                         0
#define MISC_MODEL_REV_NUM_MODEL_NUM_BITS                          6
#define MISC_MODEL_REV_NUM_MODEL_NUM_SHIFT                         4

/* MISC :: model_rev_num :: rev_num [03:00] */
#define Wr_MISC_model_rev_num_rev_num(x) WriteRegBits16(MISC_MODEL_REV_NUM,0xf,0,x)
#define Rd_MISC_model_rev_num_rev_num(x) ReadRegBits16(MISC_MODEL_REV_NUM,0xf,0)
#define MISC_MODEL_REV_NUM_REV_NUM_MASK                            0x000f
#define MISC_MODEL_REV_NUM_REV_NUM_ALIGN                           0
#define MISC_MODEL_REV_NUM_REV_NUM_BITS                            4
#define MISC_MODEL_REV_NUM_REV_NUM_SHIFT                           0


/****************************************************************************
 * MISC :: deviceid_lo
 ***************************************************************************/
/* MISC :: deviceid_lo :: reserved0 [15:12] */
#define MISC_DEVICEID_LO_RESERVED0_MASK                            0xf000
#define MISC_DEVICEID_LO_RESERVED0_ALIGN                           0
#define MISC_DEVICEID_LO_RESERVED0_BITS                            4
#define MISC_DEVICEID_LO_RESERVED0_SHIFT                           12

/* MISC :: deviceid_lo :: device_id_lo [11:00] */
#define Wr_MISC_deviceid_lo_device_id_lo(x) WriteRegBits16(MISC_DEVICEID_LO,0xfff,0,x)
#define Rd_MISC_deviceid_lo_device_id_lo(x) ReadRegBits16(MISC_DEVICEID_LO,0xfff,0)
#define MISC_DEVICEID_LO_DEVICE_ID_LO_MASK                         0x0fff
#define MISC_DEVICEID_LO_DEVICE_ID_LO_ALIGN                        0
#define MISC_DEVICEID_LO_DEVICE_ID_LO_BITS                         12
#define MISC_DEVICEID_LO_DEVICE_ID_LO_SHIFT                        0


/****************************************************************************
 * MISC :: deviceid_hi
 ***************************************************************************/
/* MISC :: deviceid_hi :: reserved0 [15:08] */
#define MISC_DEVICEID_HI_RESERVED0_MASK                            0xff00
#define MISC_DEVICEID_HI_RESERVED0_ALIGN                           0
#define MISC_DEVICEID_HI_RESERVED0_BITS                            8
#define MISC_DEVICEID_HI_RESERVED0_SHIFT                           8

/* MISC :: deviceid_hi :: device_id_hi [07:00] */
#define Wr_MISC_deviceid_hi_device_id_hi(x) WriteRegBits16(MISC_DEVICEID_HI,0xff,0,x)
#define Rd_MISC_deviceid_hi_device_id_hi(x) ReadRegBits16(MISC_DEVICEID_HI,0xff,0)
#define MISC_DEVICEID_HI_DEVICE_ID_HI_MASK                         0x00ff
#define MISC_DEVICEID_HI_DEVICE_ID_HI_ALIGN                        0
#define MISC_DEVICEID_HI_DEVICE_ID_HI_BITS                         8
#define MISC_DEVICEID_HI_DEVICE_ID_HI_SHIFT                        0


/****************************************************************************
 * MISC :: switch_misc_ctrl
 ***************************************************************************/
/* MISC :: switch_misc_ctrl :: pda_all_mem_for_switch [15:15] */
#define Wr_MISC_switch_misc_ctrl_pda_all_mem_for_switch(x) WriteRegBits16(MISC_SWITCH_MISC_CTRL,0x8000,15,x)
#define Rd_MISC_switch_misc_ctrl_pda_all_mem_for_switch(x) ReadRegBits16(MISC_SWITCH_MISC_CTRL,0x8000,15)
#define MISC_SWITCH_MISC_CTRL_PDA_ALL_MEM_FOR_SWITCH_MASK          0x8000
#define MISC_SWITCH_MISC_CTRL_PDA_ALL_MEM_FOR_SWITCH_ALIGN         0
#define MISC_SWITCH_MISC_CTRL_PDA_ALL_MEM_FOR_SWITCH_BITS          1
#define MISC_SWITCH_MISC_CTRL_PDA_ALL_MEM_FOR_SWITCH_SHIFT         15

/* MISC :: switch_misc_ctrl :: reserved0 [14:09] */
#define MISC_SWITCH_MISC_CTRL_RESERVED0_MASK                       0x7e00
#define MISC_SWITCH_MISC_CTRL_RESERVED0_ALIGN                      0
#define MISC_SWITCH_MISC_CTRL_RESERVED0_BITS                       6
#define MISC_SWITCH_MISC_CTRL_RESERVED0_SHIFT                      9

/* MISC :: switch_misc_ctrl :: direct_gate_port [08:00] */
#define Wr_MISC_switch_misc_ctrl_direct_gate_port(x) WriteRegBits16(MISC_SWITCH_MISC_CTRL,0x1ff,0,x)
#define Rd_MISC_switch_misc_ctrl_direct_gate_port(x) ReadRegBits16(MISC_SWITCH_MISC_CTRL,0x1ff,0)
#define MISC_SWITCH_MISC_CTRL_DIRECT_GATE_PORT_MASK                0x01ff
#define MISC_SWITCH_MISC_CTRL_DIRECT_GATE_PORT_ALIGN               0
#define MISC_SWITCH_MISC_CTRL_DIRECT_GATE_PORT_BITS                9
#define MISC_SWITCH_MISC_CTRL_DIRECT_GATE_PORT_SHIFT               0


/****************************************************************************
 * MISC :: ldo_pwrdn
 ***************************************************************************/
/* MISC :: ldo_pwrdn :: reserved0 [15:01] */
#define MISC_LDO_PWRDN_RESERVED0_MASK                              0xfffe
#define MISC_LDO_PWRDN_RESERVED0_ALIGN                             0
#define MISC_LDO_PWRDN_RESERVED0_BITS                              15
#define MISC_LDO_PWRDN_RESERVED0_SHIFT                             1

/* MISC :: ldo_pwrdn :: pwrdn [00:00] */
#define Wr_MISC_ldo_pwrdn_pwrdn(x) WriteRegBits16(MISC_LDO_PWRDN,0x1,0,x)
#define Rd_MISC_ldo_pwrdn_pwrdn(x) ReadRegBits16(MISC_LDO_PWRDN,0x1,0)
#define MISC_LDO_PWRDN_PWRDN_MASK                                  0x0001
#define MISC_LDO_PWRDN_PWRDN_ALIGN                                 0
#define MISC_LDO_PWRDN_PWRDN_BITS                                  1
#define MISC_LDO_PWRDN_PWRDN_SHIFT                                 0


/****************************************************************************
 * MISC :: ldo_vregcntl_1
 ***************************************************************************/
/* MISC :: ldo_vregcntl_1 :: reserved0 [15:15] */
#define MISC_LDO_VREGCNTL_1_RESERVED0_MASK                         0x8000
#define MISC_LDO_VREGCNTL_1_RESERVED0_ALIGN                        0
#define MISC_LDO_VREGCNTL_1_RESERVED0_BITS                         1
#define MISC_LDO_VREGCNTL_1_RESERVED0_SHIFT                        15

/* MISC :: ldo_vregcntl_1 :: BG_ref_voltage_trimming [14:11] */
#define Wr_MISC_ldo_vregcntl_1_BG_ref_voltage_trimming(x) WriteRegBits16(MISC_LDO_VREGCNTL_1,0x7800,11,x)
#define Rd_MISC_ldo_vregcntl_1_BG_ref_voltage_trimming(x) ReadRegBits16(MISC_LDO_VREGCNTL_1,0x7800,11)
#define MISC_LDO_VREGCNTL_1_BG_REF_VOLTAGE_TRIMMING_MASK           0x7800
#define MISC_LDO_VREGCNTL_1_BG_REF_VOLTAGE_TRIMMING_ALIGN          0
#define MISC_LDO_VREGCNTL_1_BG_REF_VOLTAGE_TRIMMING_BITS           4
#define MISC_LDO_VREGCNTL_1_BG_REF_VOLTAGE_TRIMMING_SHIFT          11

/* MISC :: ldo_vregcntl_1 :: Inrush_current_adjustment [10:10] */
#define Wr_MISC_ldo_vregcntl_1_Inrush_current_adjustment(x) WriteRegBits16(MISC_LDO_VREGCNTL_1,0x400,10,x)
#define Rd_MISC_ldo_vregcntl_1_Inrush_current_adjustment(x) ReadRegBits16(MISC_LDO_VREGCNTL_1,0x400,10)
#define MISC_LDO_VREGCNTL_1_INRUSH_CURRENT_ADJUSTMENT_MASK         0x0400
#define MISC_LDO_VREGCNTL_1_INRUSH_CURRENT_ADJUSTMENT_ALIGN        0
#define MISC_LDO_VREGCNTL_1_INRUSH_CURRENT_ADJUSTMENT_BITS         1
#define MISC_LDO_VREGCNTL_1_INRUSH_CURRENT_ADJUSTMENT_SHIFT        10

/* MISC :: ldo_vregcntl_1 :: Current_limit_adjustment [09:09] */
#define Wr_MISC_ldo_vregcntl_1_Current_limit_adjustment(x) WriteRegBits16(MISC_LDO_VREGCNTL_1,0x200,9,x)
#define Rd_MISC_ldo_vregcntl_1_Current_limit_adjustment(x) ReadRegBits16(MISC_LDO_VREGCNTL_1,0x200,9)
#define MISC_LDO_VREGCNTL_1_CURRENT_LIMIT_ADJUSTMENT_MASK          0x0200
#define MISC_LDO_VREGCNTL_1_CURRENT_LIMIT_ADJUSTMENT_ALIGN         0
#define MISC_LDO_VREGCNTL_1_CURRENT_LIMIT_ADJUSTMENT_BITS          1
#define MISC_LDO_VREGCNTL_1_CURRENT_LIMIT_ADJUSTMENT_SHIFT         9

/* MISC :: ldo_vregcntl_1 :: Leakage_sensing_control [08:08] */
#define Wr_MISC_ldo_vregcntl_1_Leakage_sensing_control(x) WriteRegBits16(MISC_LDO_VREGCNTL_1,0x100,8,x)
#define Rd_MISC_ldo_vregcntl_1_Leakage_sensing_control(x) ReadRegBits16(MISC_LDO_VREGCNTL_1,0x100,8)
#define MISC_LDO_VREGCNTL_1_LEAKAGE_SENSING_CONTROL_MASK           0x0100
#define MISC_LDO_VREGCNTL_1_LEAKAGE_SENSING_CONTROL_ALIGN          0
#define MISC_LDO_VREGCNTL_1_LEAKAGE_SENSING_CONTROL_BITS           1
#define MISC_LDO_VREGCNTL_1_LEAKAGE_SENSING_CONTROL_SHIFT          8

/* MISC :: ldo_vregcntl_1 :: Output_voltage_tuning [07:04] */
#define Wr_MISC_ldo_vregcntl_1_Output_voltage_tuning(x) WriteRegBits16(MISC_LDO_VREGCNTL_1,0xf0,4,x)
#define Rd_MISC_ldo_vregcntl_1_Output_voltage_tuning(x) ReadRegBits16(MISC_LDO_VREGCNTL_1,0xf0,4)
#define MISC_LDO_VREGCNTL_1_OUTPUT_VOLTAGE_TUNING_MASK             0x00f0
#define MISC_LDO_VREGCNTL_1_OUTPUT_VOLTAGE_TUNING_ALIGN            0
#define MISC_LDO_VREGCNTL_1_OUTPUT_VOLTAGE_TUNING_BITS             4
#define MISC_LDO_VREGCNTL_1_OUTPUT_VOLTAGE_TUNING_SHIFT            4

/* MISC :: ldo_vregcntl_1 :: Bandgap_temperature_coefficient_tuning [03:00] */
#define Wr_MISC_ldo_vregcntl_1_Bandgap_temperature_coefficient_tuning(x) WriteRegBits16(MISC_LDO_VREGCNTL_1,0xf,0,x)
#define Rd_MISC_ldo_vregcntl_1_Bandgap_temperature_coefficient_tuning(x) ReadRegBits16(MISC_LDO_VREGCNTL_1,0xf,0)
#define MISC_LDO_VREGCNTL_1_BANDGAP_TEMPERATURE_COEFFICIENT_TUNING_MASK 0x000f
#define MISC_LDO_VREGCNTL_1_BANDGAP_TEMPERATURE_COEFFICIENT_TUNING_ALIGN 0
#define MISC_LDO_VREGCNTL_1_BANDGAP_TEMPERATURE_COEFFICIENT_TUNING_BITS 4
#define MISC_LDO_VREGCNTL_1_BANDGAP_TEMPERATURE_COEFFICIENT_TUNING_SHIFT 0


/****************************************************************************
 * MISC :: ldo_vregcntl_2
 ***************************************************************************/
/* MISC :: ldo_vregcntl_2 :: reserved0 [15:04] */
#define MISC_LDO_VREGCNTL_2_RESERVED0_MASK                         0xfff0
#define MISC_LDO_VREGCNTL_2_RESERVED0_ALIGN                        0
#define MISC_LDO_VREGCNTL_2_RESERVED0_BITS                         12
#define MISC_LDO_VREGCNTL_2_RESERVED0_SHIFT                        4

/* MISC :: ldo_vregcntl_2 :: Zero_position_adjustment [03:02] */
#define Wr_MISC_ldo_vregcntl_2_Zero_position_adjustment(x) WriteRegBits16(MISC_LDO_VREGCNTL_2,0xc,2,x)
#define Rd_MISC_ldo_vregcntl_2_Zero_position_adjustment(x) ReadRegBits16(MISC_LDO_VREGCNTL_2,0xc,2)
#define MISC_LDO_VREGCNTL_2_ZERO_POSITION_ADJUSTMENT_MASK          0x000c
#define MISC_LDO_VREGCNTL_2_ZERO_POSITION_ADJUSTMENT_ALIGN         0
#define MISC_LDO_VREGCNTL_2_ZERO_POSITION_ADJUSTMENT_BITS          2
#define MISC_LDO_VREGCNTL_2_ZERO_POSITION_ADJUSTMENT_SHIFT         2

/* MISC :: ldo_vregcntl_2 :: Leakage_sensing_adjustment [01:00] */
#define Wr_MISC_ldo_vregcntl_2_Leakage_sensing_adjustment(x) WriteRegBits16(MISC_LDO_VREGCNTL_2,0x3,0,x)
#define Rd_MISC_ldo_vregcntl_2_Leakage_sensing_adjustment(x) ReadRegBits16(MISC_LDO_VREGCNTL_2,0x3,0)
#define MISC_LDO_VREGCNTL_2_LEAKAGE_SENSING_ADJUSTMENT_MASK        0x0003
#define MISC_LDO_VREGCNTL_2_LEAKAGE_SENSING_ADJUSTMENT_ALIGN       0
#define MISC_LDO_VREGCNTL_2_LEAKAGE_SENSING_ADJUSTMENT_BITS        2
#define MISC_LDO_VREGCNTL_2_LEAKAGE_SENSING_ADJUSTMENT_SHIFT       0


/****************************************************************************
 * MISC :: ldo_vregcntlen
 ***************************************************************************/
/* MISC :: ldo_vregcntlen :: reserved0 [15:01] */
#define MISC_LDO_VREGCNTLEN_RESERVED0_MASK                         0xfffe
#define MISC_LDO_VREGCNTLEN_RESERVED0_ALIGN                        0
#define MISC_LDO_VREGCNTLEN_RESERVED0_BITS                         15
#define MISC_LDO_VREGCNTLEN_RESERVED0_SHIFT                        1

/* MISC :: ldo_vregcntlen :: vregcntlen [00:00] */
#define Wr_MISC_ldo_vregcntlen_vregcntlen(x) WriteRegBits16(MISC_LDO_VREGCNTLEN,0x1,0,x)
#define Rd_MISC_ldo_vregcntlen_vregcntlen(x) ReadRegBits16(MISC_LDO_VREGCNTLEN,0x1,0)
#define MISC_LDO_VREGCNTLEN_VREGCNTLEN_MASK                        0x0001
#define MISC_LDO_VREGCNTLEN_VREGCNTLEN_ALIGN                       0
#define MISC_LDO_VREGCNTLEN_VREGCNTLEN_BITS                        1
#define MISC_LDO_VREGCNTLEN_VREGCNTLEN_SHIFT                       0


/****************************************************************************
 * MISC :: swreg_ctrl_reg0
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg0 :: jitterfilter_dis [15:15] */
#define Wr_MISC_swreg_ctrl_reg0_jitterfilter_dis(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x8000,15,x)
#define Rd_MISC_swreg_ctrl_reg0_jitterfilter_dis(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x8000,15)
#define MISC_SWREG_CTRL_REG0_JITTERFILTER_DIS_MASK                 0x8000
#define MISC_SWREG_CTRL_REG0_JITTERFILTER_DIS_ALIGN                0
#define MISC_SWREG_CTRL_REG0_JITTERFILTER_DIS_BITS                 1
#define MISC_SWREG_CTRL_REG0_JITTERFILTER_DIS_SHIFT                15

/* MISC :: swreg_ctrl_reg0 :: fault_ov_en [14:14] */
#define Wr_MISC_swreg_ctrl_reg0_fault_ov_en(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x4000,14,x)
#define Rd_MISC_swreg_ctrl_reg0_fault_ov_en(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x4000,14)
#define MISC_SWREG_CTRL_REG0_FAULT_OV_EN_MASK                      0x4000
#define MISC_SWREG_CTRL_REG0_FAULT_OV_EN_ALIGN                     0
#define MISC_SWREG_CTRL_REG0_FAULT_OV_EN_BITS                      1
#define MISC_SWREG_CTRL_REG0_FAULT_OV_EN_SHIFT                     14

/* MISC :: swreg_ctrl_reg0 :: fault_1_ilim_adcout_en [13:13] */
#define Wr_MISC_swreg_ctrl_reg0_fault_1_ilim_adcout_en(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x2000,13,x)
#define Rd_MISC_swreg_ctrl_reg0_fault_1_ilim_adcout_en(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x2000,13)
#define MISC_SWREG_CTRL_REG0_FAULT_1_ILIM_ADCOUT_EN_MASK           0x2000
#define MISC_SWREG_CTRL_REG0_FAULT_1_ILIM_ADCOUT_EN_ALIGN          0
#define MISC_SWREG_CTRL_REG0_FAULT_1_ILIM_ADCOUT_EN_BITS           1
#define MISC_SWREG_CTRL_REG0_FAULT_1_ILIM_ADCOUT_EN_SHIFT          13

/* MISC :: swreg_ctrl_reg0 :: fault_0_ilim_dutycycle_en [12:12] */
#define Wr_MISC_swreg_ctrl_reg0_fault_0_ilim_dutycycle_en(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x1000,12,x)
#define Rd_MISC_swreg_ctrl_reg0_fault_0_ilim_dutycycle_en(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x1000,12)
#define MISC_SWREG_CTRL_REG0_FAULT_0_ILIM_DUTYCYCLE_EN_MASK        0x1000
#define MISC_SWREG_CTRL_REG0_FAULT_0_ILIM_DUTYCYCLE_EN_ALIGN       0
#define MISC_SWREG_CTRL_REG0_FAULT_0_ILIM_DUTYCYCLE_EN_BITS        1
#define MISC_SWREG_CTRL_REG0_FAULT_0_ILIM_DUTYCYCLE_EN_SHIFT       12

/* MISC :: swreg_ctrl_reg0 :: sd_dither_dis [11:11] */
#define Wr_MISC_swreg_ctrl_reg0_sd_dither_dis(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x800,11,x)
#define Rd_MISC_swreg_ctrl_reg0_sd_dither_dis(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x800,11)
#define MISC_SWREG_CTRL_REG0_SD_DITHER_DIS_MASK                    0x0800
#define MISC_SWREG_CTRL_REG0_SD_DITHER_DIS_ALIGN                   0
#define MISC_SWREG_CTRL_REG0_SD_DITHER_DIS_BITS                    1
#define MISC_SWREG_CTRL_REG0_SD_DITHER_DIS_SHIFT                   11

/* MISC :: swreg_ctrl_reg0 :: burst_r_ctrl [10:09] */
#define Wr_MISC_swreg_ctrl_reg0_burst_r_ctrl(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x600,9,x)
#define Rd_MISC_swreg_ctrl_reg0_burst_r_ctrl(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x600,9)
#define MISC_SWREG_CTRL_REG0_BURST_R_CTRL_MASK                     0x0600
#define MISC_SWREG_CTRL_REG0_BURST_R_CTRL_ALIGN                    0
#define MISC_SWREG_CTRL_REG0_BURST_R_CTRL_BITS                     2
#define MISC_SWREG_CTRL_REG0_BURST_R_CTRL_SHIFT                    9

/* MISC :: swreg_ctrl_reg0 :: swreg_ctrl_reg0_reserved [08:07] */
#define MISC_SWREG_CTRL_REG0_SWREG_CTRL_REG0_RESERVED_MASK         0x0180
#define MISC_SWREG_CTRL_REG0_SWREG_CTRL_REG0_RESERVED_ALIGN        0
#define MISC_SWREG_CTRL_REG0_SWREG_CTRL_REG0_RESERVED_BITS         2
#define MISC_SWREG_CTRL_REG0_SWREG_CTRL_REG0_RESERVED_SHIFT        7

/* MISC :: swreg_ctrl_reg0 :: comp_loop_gain2_ctrl [06:04] */
#define Wr_MISC_swreg_ctrl_reg0_comp_loop_gain2_ctrl(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x70,4,x)
#define Rd_MISC_swreg_ctrl_reg0_comp_loop_gain2_ctrl(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x70,4)
#define MISC_SWREG_CTRL_REG0_COMP_LOOP_GAIN2_CTRL_MASK             0x0070
#define MISC_SWREG_CTRL_REG0_COMP_LOOP_GAIN2_CTRL_ALIGN            0
#define MISC_SWREG_CTRL_REG0_COMP_LOOP_GAIN2_CTRL_BITS             3
#define MISC_SWREG_CTRL_REG0_COMP_LOOP_GAIN2_CTRL_SHIFT            4

/* MISC :: swreg_ctrl_reg0 :: comp_loop_gain1_ctrl [03:03] */
#define Wr_MISC_swreg_ctrl_reg0_comp_loop_gain1_ctrl(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x8,3,x)
#define Rd_MISC_swreg_ctrl_reg0_comp_loop_gain1_ctrl(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x8,3)
#define MISC_SWREG_CTRL_REG0_COMP_LOOP_GAIN1_CTRL_MASK             0x0008
#define MISC_SWREG_CTRL_REG0_COMP_LOOP_GAIN1_CTRL_ALIGN            0
#define MISC_SWREG_CTRL_REG0_COMP_LOOP_GAIN1_CTRL_BITS             1
#define MISC_SWREG_CTRL_REG0_COMP_LOOP_GAIN1_CTRL_SHIFT            3

/* MISC :: swreg_ctrl_reg0 :: comp_lp_ctrl [02:02] */
#define Wr_MISC_swreg_ctrl_reg0_comp_lp_ctrl(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x4,2,x)
#define Rd_MISC_swreg_ctrl_reg0_comp_lp_ctrl(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x4,2)
#define MISC_SWREG_CTRL_REG0_COMP_LP_CTRL_MASK                     0x0004
#define MISC_SWREG_CTRL_REG0_COMP_LP_CTRL_ALIGN                    0
#define MISC_SWREG_CTRL_REG0_COMP_LP_CTRL_BITS                     1
#define MISC_SWREG_CTRL_REG0_COMP_LP_CTRL_SHIFT                    2

/* MISC :: swreg_ctrl_reg0 :: update_ctrl_reg_posedge [01:01] */
#define Wr_MISC_swreg_ctrl_reg0_update_ctrl_reg_posedge(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x2,1,x)
#define Rd_MISC_swreg_ctrl_reg0_update_ctrl_reg_posedge(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x2,1)
#define MISC_SWREG_CTRL_REG0_UPDATE_CTRL_REG_POSEDGE_MASK          0x0002
#define MISC_SWREG_CTRL_REG0_UPDATE_CTRL_REG_POSEDGE_ALIGN         0
#define MISC_SWREG_CTRL_REG0_UPDATE_CTRL_REG_POSEDGE_BITS          1
#define MISC_SWREG_CTRL_REG0_UPDATE_CTRL_REG_POSEDGE_SHIFT         1

/* MISC :: swreg_ctrl_reg0 :: swreg_softreset [00:00] */
#define Wr_MISC_swreg_ctrl_reg0_swreg_softreset(x) WriteRegBits16(MISC_SWREG_CTRL_REG0,0x1,0,x)
#define Rd_MISC_swreg_ctrl_reg0_swreg_softreset(x) ReadRegBits16(MISC_SWREG_CTRL_REG0,0x1,0)
#define MISC_SWREG_CTRL_REG0_SWREG_SOFTRESET_MASK                  0x0001
#define MISC_SWREG_CTRL_REG0_SWREG_SOFTRESET_ALIGN                 0
#define MISC_SWREG_CTRL_REG0_SWREG_SOFTRESET_BITS                  1
#define MISC_SWREG_CTRL_REG0_SWREG_SOFTRESET_SHIFT                 0


/****************************************************************************
 * MISC :: swreg_ctrl_reg1
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg1 :: comp_coef1_sel [15:08] */
#define Wr_MISC_swreg_ctrl_reg1_comp_coef1_sel(x) WriteRegBits16(MISC_SWREG_CTRL_REG1,0xff00,8,x)
#define Rd_MISC_swreg_ctrl_reg1_comp_coef1_sel(x) ReadRegBits16(MISC_SWREG_CTRL_REG1,0xff00,8)
#define MISC_SWREG_CTRL_REG1_COMP_COEF1_SEL_MASK                   0xff00
#define MISC_SWREG_CTRL_REG1_COMP_COEF1_SEL_ALIGN                  0
#define MISC_SWREG_CTRL_REG1_COMP_COEF1_SEL_BITS                   8
#define MISC_SWREG_CTRL_REG1_COMP_COEF1_SEL_SHIFT                  8

/* MISC :: swreg_ctrl_reg1 :: fault_adcout_ctrl [07:06] */
#define Wr_MISC_swreg_ctrl_reg1_fault_adcout_ctrl(x) WriteRegBits16(MISC_SWREG_CTRL_REG1,0xc0,6,x)
#define Rd_MISC_swreg_ctrl_reg1_fault_adcout_ctrl(x) ReadRegBits16(MISC_SWREG_CTRL_REG1,0xc0,6)
#define MISC_SWREG_CTRL_REG1_FAULT_ADCOUT_CTRL_MASK                0x00c0
#define MISC_SWREG_CTRL_REG1_FAULT_ADCOUT_CTRL_ALIGN               0
#define MISC_SWREG_CTRL_REG1_FAULT_ADCOUT_CTRL_BITS                2
#define MISC_SWREG_CTRL_REG1_FAULT_ADCOUT_CTRL_SHIFT               6

/* MISC :: swreg_ctrl_reg1 :: fault_dutycycle [05:04] */
#define Wr_MISC_swreg_ctrl_reg1_fault_dutycycle(x) WriteRegBits16(MISC_SWREG_CTRL_REG1,0x30,4,x)
#define Rd_MISC_swreg_ctrl_reg1_fault_dutycycle(x) ReadRegBits16(MISC_SWREG_CTRL_REG1,0x30,4)
#define MISC_SWREG_CTRL_REG1_FAULT_DUTYCYCLE_MASK                  0x0030
#define MISC_SWREG_CTRL_REG1_FAULT_DUTYCYCLE_ALIGN                 0
#define MISC_SWREG_CTRL_REG1_FAULT_DUTYCYCLE_BITS                  2
#define MISC_SWREG_CTRL_REG1_FAULT_DUTYCYCLE_SHIFT                 4

/* MISC :: swreg_ctrl_reg1 :: sd_freq_ctrl [03:02] */
#define Wr_MISC_swreg_ctrl_reg1_sd_freq_ctrl(x) WriteRegBits16(MISC_SWREG_CTRL_REG1,0xc,2,x)
#define Rd_MISC_swreg_ctrl_reg1_sd_freq_ctrl(x) ReadRegBits16(MISC_SWREG_CTRL_REG1,0xc,2)
#define MISC_SWREG_CTRL_REG1_SD_FREQ_CTRL_MASK                     0x000c
#define MISC_SWREG_CTRL_REG1_SD_FREQ_CTRL_ALIGN                    0
#define MISC_SWREG_CTRL_REG1_SD_FREQ_CTRL_BITS                     2
#define MISC_SWREG_CTRL_REG1_SD_FREQ_CTRL_SHIFT                    2

/* MISC :: swreg_ctrl_reg1 :: comp_ss_ctrl [01:00] */
#define Wr_MISC_swreg_ctrl_reg1_comp_ss_ctrl(x) WriteRegBits16(MISC_SWREG_CTRL_REG1,0x3,0,x)
#define Rd_MISC_swreg_ctrl_reg1_comp_ss_ctrl(x) ReadRegBits16(MISC_SWREG_CTRL_REG1,0x3,0)
#define MISC_SWREG_CTRL_REG1_COMP_SS_CTRL_MASK                     0x0003
#define MISC_SWREG_CTRL_REG1_COMP_SS_CTRL_ALIGN                    0
#define MISC_SWREG_CTRL_REG1_COMP_SS_CTRL_BITS                     2
#define MISC_SWREG_CTRL_REG1_COMP_SS_CTRL_SHIFT                    0


/****************************************************************************
 * MISC :: swreg_ctrl_reg2
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg2 :: sd_dutymin_3_0 [15:12] */
#define Wr_MISC_swreg_ctrl_reg2_sd_dutymin_3_0(x) WriteRegBits16(MISC_SWREG_CTRL_REG2,0xf000,12,x)
#define Rd_MISC_swreg_ctrl_reg2_sd_dutymin_3_0(x) ReadRegBits16(MISC_SWREG_CTRL_REG2,0xf000,12)
#define MISC_SWREG_CTRL_REG2_SD_DUTYMIN_3_0_MASK                   0xf000
#define MISC_SWREG_CTRL_REG2_SD_DUTYMIN_3_0_ALIGN                  0
#define MISC_SWREG_CTRL_REG2_SD_DUTYMIN_3_0_BITS                   4
#define MISC_SWREG_CTRL_REG2_SD_DUTYMIN_3_0_SHIFT                  12

/* MISC :: swreg_ctrl_reg2 :: comp_coef2_sel [11:02] */
#define Wr_MISC_swreg_ctrl_reg2_comp_coef2_sel(x) WriteRegBits16(MISC_SWREG_CTRL_REG2,0xffc,2,x)
#define Rd_MISC_swreg_ctrl_reg2_comp_coef2_sel(x) ReadRegBits16(MISC_SWREG_CTRL_REG2,0xffc,2)
#define MISC_SWREG_CTRL_REG2_COMP_COEF2_SEL_MASK                   0x0ffc
#define MISC_SWREG_CTRL_REG2_COMP_COEF2_SEL_ALIGN                  0
#define MISC_SWREG_CTRL_REG2_COMP_COEF2_SEL_BITS                   10
#define MISC_SWREG_CTRL_REG2_COMP_COEF2_SEL_SHIFT                  2

/* MISC :: swreg_ctrl_reg2 :: comp_coef1_sel [01:00] */
#define Wr_MISC_swreg_ctrl_reg2_comp_coef1_sel(x) WriteRegBits16(MISC_SWREG_CTRL_REG2,0x3,0,x)
#define Rd_MISC_swreg_ctrl_reg2_comp_coef1_sel(x) ReadRegBits16(MISC_SWREG_CTRL_REG2,0x3,0)
#define MISC_SWREG_CTRL_REG2_COMP_COEF1_SEL_MASK                   0x0003
#define MISC_SWREG_CTRL_REG2_COMP_COEF1_SEL_ALIGN                  0
#define MISC_SWREG_CTRL_REG2_COMP_COEF1_SEL_BITS                   2
#define MISC_SWREG_CTRL_REG2_COMP_COEF1_SEL_SHIFT                  0


/****************************************************************************
 * MISC :: swreg_ctrl_reg3
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg3 :: fault_adcout_ref_3_0 [15:12] */
#define Wr_MISC_swreg_ctrl_reg3_fault_adcout_ref_3_0(x) WriteRegBits16(MISC_SWREG_CTRL_REG3,0xf000,12,x)
#define Rd_MISC_swreg_ctrl_reg3_fault_adcout_ref_3_0(x) ReadRegBits16(MISC_SWREG_CTRL_REG3,0xf000,12)
#define MISC_SWREG_CTRL_REG3_FAULT_ADCOUT_REF_3_0_MASK             0xf000
#define MISC_SWREG_CTRL_REG3_FAULT_ADCOUT_REF_3_0_ALIGN            0
#define MISC_SWREG_CTRL_REG3_FAULT_ADCOUT_REF_3_0_BITS             4
#define MISC_SWREG_CTRL_REG3_FAULT_ADCOUT_REF_3_0_SHIFT            12

/* MISC :: swreg_ctrl_reg3 :: sd_dutymax [11:03] */
#define Wr_MISC_swreg_ctrl_reg3_sd_dutymax(x) WriteRegBits16(MISC_SWREG_CTRL_REG3,0xff8,3,x)
#define Rd_MISC_swreg_ctrl_reg3_sd_dutymax(x) ReadRegBits16(MISC_SWREG_CTRL_REG3,0xff8,3)
#define MISC_SWREG_CTRL_REG3_SD_DUTYMAX_MASK                       0x0ff8
#define MISC_SWREG_CTRL_REG3_SD_DUTYMAX_ALIGN                      0
#define MISC_SWREG_CTRL_REG3_SD_DUTYMAX_BITS                       9
#define MISC_SWREG_CTRL_REG3_SD_DUTYMAX_SHIFT                      3

/* MISC :: swreg_ctrl_reg3 :: sd_dutymin_6_4 [02:00] */
#define Wr_MISC_swreg_ctrl_reg3_sd_dutymin_6_4(x) WriteRegBits16(MISC_SWREG_CTRL_REG3,0x7,0,x)
#define Rd_MISC_swreg_ctrl_reg3_sd_dutymin_6_4(x) ReadRegBits16(MISC_SWREG_CTRL_REG3,0x7,0)
#define MISC_SWREG_CTRL_REG3_SD_DUTYMIN_6_4_MASK                   0x0007
#define MISC_SWREG_CTRL_REG3_SD_DUTYMIN_6_4_ALIGN                  0
#define MISC_SWREG_CTRL_REG3_SD_DUTYMIN_6_4_BITS                   3
#define MISC_SWREG_CTRL_REG3_SD_DUTYMIN_6_4_SHIFT                  0


/****************************************************************************
 * MISC :: swreg_ctrl_reg4
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg4 :: ilim_dutycycle_ref [15:06] */
#define Wr_MISC_swreg_ctrl_reg4_ilim_dutycycle_ref(x) WriteRegBits16(MISC_SWREG_CTRL_REG4,0xffc0,6,x)
#define Rd_MISC_swreg_ctrl_reg4_ilim_dutycycle_ref(x) ReadRegBits16(MISC_SWREG_CTRL_REG4,0xffc0,6)
#define MISC_SWREG_CTRL_REG4_ILIM_DUTYCYCLE_REF_MASK               0xffc0
#define MISC_SWREG_CTRL_REG4_ILIM_DUTYCYCLE_REF_ALIGN              0
#define MISC_SWREG_CTRL_REG4_ILIM_DUTYCYCLE_REF_BITS               10
#define MISC_SWREG_CTRL_REG4_ILIM_DUTYCYCLE_REF_SHIFT              6

/* MISC :: swreg_ctrl_reg4 :: fault_adcout_ref_9_4 [05:00] */
#define Wr_MISC_swreg_ctrl_reg4_fault_adcout_ref_9_4(x) WriteRegBits16(MISC_SWREG_CTRL_REG4,0x3f,0,x)
#define Rd_MISC_swreg_ctrl_reg4_fault_adcout_ref_9_4(x) ReadRegBits16(MISC_SWREG_CTRL_REG4,0x3f,0)
#define MISC_SWREG_CTRL_REG4_FAULT_ADCOUT_REF_9_4_MASK             0x003f
#define MISC_SWREG_CTRL_REG4_FAULT_ADCOUT_REF_9_4_ALIGN            0
#define MISC_SWREG_CTRL_REG4_FAULT_ADCOUT_REF_9_4_BITS             6
#define MISC_SWREG_CTRL_REG4_FAULT_ADCOUT_REF_9_4_SHIFT            0


/****************************************************************************
 * MISC :: swreg_ctrl_reg5
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg5 :: burst_d_ctrl_2_0 [15:13] */
#define Wr_MISC_swreg_ctrl_reg5_burst_d_ctrl_2_0(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0xe000,13,x)
#define Rd_MISC_swreg_ctrl_reg5_burst_d_ctrl_2_0(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0xe000,13)
#define MISC_SWREG_CTRL_REG5_BURST_D_CTRL_2_0_MASK                 0xe000
#define MISC_SWREG_CTRL_REG5_BURST_D_CTRL_2_0_ALIGN                0
#define MISC_SWREG_CTRL_REG5_BURST_D_CTRL_2_0_BITS                 3
#define MISC_SWREG_CTRL_REG5_BURST_D_CTRL_2_0_SHIFT                13

/* MISC :: swreg_ctrl_reg5 :: BURST_MODE_EN [12:12] */
#define Wr_MISC_swreg_ctrl_reg5_BURST_MODE_EN(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0x1000,12,x)
#define Rd_MISC_swreg_ctrl_reg5_BURST_MODE_EN(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0x1000,12)
#define MISC_SWREG_CTRL_REG5_BURST_MODE_EN_MASK                    0x1000
#define MISC_SWREG_CTRL_REG5_BURST_MODE_EN_ALIGN                   0
#define MISC_SWREG_CTRL_REG5_BURST_MODE_EN_BITS                    1
#define MISC_SWREG_CTRL_REG5_BURST_MODE_EN_SHIFT                   12

/* MISC :: swreg_ctrl_reg5 :: PLL_EN [11:11] */
#define Wr_MISC_swreg_ctrl_reg5_PLL_EN(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0x800,11,x)
#define Rd_MISC_swreg_ctrl_reg5_PLL_EN(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0x800,11)
#define MISC_SWREG_CTRL_REG5_PLL_EN_MASK                           0x0800
#define MISC_SWREG_CTRL_REG5_PLL_EN_ALIGN                          0
#define MISC_SWREG_CTRL_REG5_PLL_EN_BITS                           1
#define MISC_SWREG_CTRL_REG5_PLL_EN_SHIFT                          11

/* MISC :: swreg_ctrl_reg5 :: OV_fault_mask [10:10] */
#define Wr_MISC_swreg_ctrl_reg5_OV_fault_mask(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0x400,10,x)
#define Rd_MISC_swreg_ctrl_reg5_OV_fault_mask(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0x400,10)
#define MISC_SWREG_CTRL_REG5_OV_FAULT_MASK_MASK                    0x0400
#define MISC_SWREG_CTRL_REG5_OV_FAULT_MASK_ALIGN                   0
#define MISC_SWREG_CTRL_REG5_OV_FAULT_MASK_BITS                    1
#define MISC_SWREG_CTRL_REG5_OV_FAULT_MASK_SHIFT                   10

/* MISC :: swreg_ctrl_reg5 :: analog_comp_ilim_fault2_mask [09:09] */
#define Wr_MISC_swreg_ctrl_reg5_analog_comp_ilim_fault2_mask(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0x200,9,x)
#define Rd_MISC_swreg_ctrl_reg5_analog_comp_ilim_fault2_mask(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0x200,9)
#define MISC_SWREG_CTRL_REG5_ANALOG_COMP_ILIM_FAULT2_MASK_MASK     0x0200
#define MISC_SWREG_CTRL_REG5_ANALOG_COMP_ILIM_FAULT2_MASK_ALIGN    0
#define MISC_SWREG_CTRL_REG5_ANALOG_COMP_ILIM_FAULT2_MASK_BITS     1
#define MISC_SWREG_CTRL_REG5_ANALOG_COMP_ILIM_FAULT2_MASK_SHIFT    9

/* MISC :: swreg_ctrl_reg5 :: adcout_ilim_fault_1_mask [08:08] */
#define Wr_MISC_swreg_ctrl_reg5_adcout_ilim_fault_1_mask(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0x100,8,x)
#define Rd_MISC_swreg_ctrl_reg5_adcout_ilim_fault_1_mask(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0x100,8)
#define MISC_SWREG_CTRL_REG5_ADCOUT_ILIM_FAULT_1_MASK_MASK         0x0100
#define MISC_SWREG_CTRL_REG5_ADCOUT_ILIM_FAULT_1_MASK_ALIGN        0
#define MISC_SWREG_CTRL_REG5_ADCOUT_ILIM_FAULT_1_MASK_BITS         1
#define MISC_SWREG_CTRL_REG5_ADCOUT_ILIM_FAULT_1_MASK_SHIFT        8

/* MISC :: swreg_ctrl_reg5 :: dutycycle_ilim_fault_0_mask [07:07] */
#define Wr_MISC_swreg_ctrl_reg5_dutycycle_ilim_fault_0_mask(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0x80,7,x)
#define Rd_MISC_swreg_ctrl_reg5_dutycycle_ilim_fault_0_mask(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0x80,7)
#define MISC_SWREG_CTRL_REG5_DUTYCYCLE_ILIM_FAULT_0_MASK_MASK      0x0080
#define MISC_SWREG_CTRL_REG5_DUTYCYCLE_ILIM_FAULT_0_MASK_ALIGN     0
#define MISC_SWREG_CTRL_REG5_DUTYCYCLE_ILIM_FAULT_0_MASK_BITS      1
#define MISC_SWREG_CTRL_REG5_DUTYCYCLE_ILIM_FAULT_0_MASK_SHIFT     7

/* MISC :: swreg_ctrl_reg5 :: NOVL_CTRL [06:04] */
#define Wr_MISC_swreg_ctrl_reg5_NOVL_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0x70,4,x)
#define Rd_MISC_swreg_ctrl_reg5_NOVL_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0x70,4)
#define MISC_SWREG_CTRL_REG5_NOVL_CTRL_MASK                        0x0070
#define MISC_SWREG_CTRL_REG5_NOVL_CTRL_ALIGN                       0
#define MISC_SWREG_CTRL_REG5_NOVL_CTRL_BITS                        3
#define MISC_SWREG_CTRL_REG5_NOVL_CTRL_SHIFT                       4

/* MISC :: swreg_ctrl_reg5 :: FETS_ENB_DELAY_CTRL [03:02] */
#define Wr_MISC_swreg_ctrl_reg5_FETS_ENB_DELAY_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0xc,2,x)
#define Rd_MISC_swreg_ctrl_reg5_FETS_ENB_DELAY_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0xc,2)
#define MISC_SWREG_CTRL_REG5_FETS_ENB_DELAY_CTRL_MASK              0x000c
#define MISC_SWREG_CTRL_REG5_FETS_ENB_DELAY_CTRL_ALIGN             0
#define MISC_SWREG_CTRL_REG5_FETS_ENB_DELAY_CTRL_BITS              2
#define MISC_SWREG_CTRL_REG5_FETS_ENB_DELAY_CTRL_SHIFT             2

/* MISC :: swreg_ctrl_reg5 :: swreg_ctrl_reg5_reserved [01:01] */
#define MISC_SWREG_CTRL_REG5_SWREG_CTRL_REG5_RESERVED_MASK         0x0002
#define MISC_SWREG_CTRL_REG5_SWREG_CTRL_REG5_RESERVED_ALIGN        0
#define MISC_SWREG_CTRL_REG5_SWREG_CTRL_REG5_RESERVED_BITS         1
#define MISC_SWREG_CTRL_REG5_SWREG_CTRL_REG5_RESERVED_SHIFT        1

/* MISC :: swreg_ctrl_reg5 :: pmu_stable_override_bsti [00:00] */
#define Wr_MISC_swreg_ctrl_reg5_pmu_stable_override_bsti(x) WriteRegBits16(MISC_SWREG_CTRL_REG5,0x1,0,x)
#define Rd_MISC_swreg_ctrl_reg5_pmu_stable_override_bsti(x) ReadRegBits16(MISC_SWREG_CTRL_REG5,0x1,0)
#define MISC_SWREG_CTRL_REG5_PMU_STABLE_OVERRIDE_BSTI_MASK         0x0001
#define MISC_SWREG_CTRL_REG5_PMU_STABLE_OVERRIDE_BSTI_ALIGN        0
#define MISC_SWREG_CTRL_REG5_PMU_STABLE_OVERRIDE_BSTI_BITS         1
#define MISC_SWREG_CTRL_REG5_PMU_STABLE_OVERRIDE_BSTI_SHIFT        0


/****************************************************************************
 * MISC :: swreg_ctrl_reg6
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg6 :: REF_CTRL [15:08] */
#define Wr_MISC_swreg_ctrl_reg6_REF_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG6,0xff00,8,x)
#define Rd_MISC_swreg_ctrl_reg6_REF_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG6,0xff00,8)
#define MISC_SWREG_CTRL_REG6_REF_CTRL_MASK                         0xff00
#define MISC_SWREG_CTRL_REG6_REF_CTRL_ALIGN                        0
#define MISC_SWREG_CTRL_REG6_REF_CTRL_BITS                         8
#define MISC_SWREG_CTRL_REG6_REF_CTRL_SHIFT                        8

/* MISC :: swreg_ctrl_reg6 :: BG_TRIM_CTRL [07:02] */
#define Wr_MISC_swreg_ctrl_reg6_BG_TRIM_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG6,0xfc,2,x)
#define Rd_MISC_swreg_ctrl_reg6_BG_TRIM_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG6,0xfc,2)
#define MISC_SWREG_CTRL_REG6_BG_TRIM_CTRL_MASK                     0x00fc
#define MISC_SWREG_CTRL_REG6_BG_TRIM_CTRL_ALIGN                    0
#define MISC_SWREG_CTRL_REG6_BG_TRIM_CTRL_BITS                     6
#define MISC_SWREG_CTRL_REG6_BG_TRIM_CTRL_SHIFT                    2

/* MISC :: swreg_ctrl_reg6 :: DVDD_CTRL [01:00] */
#define Wr_MISC_swreg_ctrl_reg6_DVDD_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG6,0x3,0,x)
#define Rd_MISC_swreg_ctrl_reg6_DVDD_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG6,0x3,0)
#define MISC_SWREG_CTRL_REG6_DVDD_CTRL_MASK                        0x0003
#define MISC_SWREG_CTRL_REG6_DVDD_CTRL_ALIGN                       0
#define MISC_SWREG_CTRL_REG6_DVDD_CTRL_BITS                        2
#define MISC_SWREG_CTRL_REG6_DVDD_CTRL_SHIFT                       0


/****************************************************************************
 * MISC :: swreg_ctrl_reg7
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg7 :: pulse_width_limit [15:14] */
#define Wr_MISC_swreg_ctrl_reg7_pulse_width_limit(x) WriteRegBits16(MISC_SWREG_CTRL_REG7,0xc000,14,x)
#define Rd_MISC_swreg_ctrl_reg7_pulse_width_limit(x) ReadRegBits16(MISC_SWREG_CTRL_REG7,0xc000,14)
#define MISC_SWREG_CTRL_REG7_PULSE_WIDTH_LIMIT_MASK                0xc000
#define MISC_SWREG_CTRL_REG7_PULSE_WIDTH_LIMIT_ALIGN               0
#define MISC_SWREG_CTRL_REG7_PULSE_WIDTH_LIMIT_BITS                2
#define MISC_SWREG_CTRL_REG7_PULSE_WIDTH_LIMIT_SHIFT               14

/* MISC :: swreg_ctrl_reg7 :: adapt_novl [13:12] */
#define Wr_MISC_swreg_ctrl_reg7_adapt_novl(x) WriteRegBits16(MISC_SWREG_CTRL_REG7,0x3000,12,x)
#define Rd_MISC_swreg_ctrl_reg7_adapt_novl(x) ReadRegBits16(MISC_SWREG_CTRL_REG7,0x3000,12)
#define MISC_SWREG_CTRL_REG7_ADAPT_NOVL_MASK                       0x3000
#define MISC_SWREG_CTRL_REG7_ADAPT_NOVL_ALIGN                      0
#define MISC_SWREG_CTRL_REG7_ADAPT_NOVL_BITS                       2
#define MISC_SWREG_CTRL_REG7_ADAPT_NOVL_SHIFT                      12

/* MISC :: swreg_ctrl_reg7 :: PDRIVE_Nfet [11:09] */
#define Wr_MISC_swreg_ctrl_reg7_PDRIVE_Nfet(x) WriteRegBits16(MISC_SWREG_CTRL_REG7,0xe00,9,x)
#define Rd_MISC_swreg_ctrl_reg7_PDRIVE_Nfet(x) ReadRegBits16(MISC_SWREG_CTRL_REG7,0xe00,9)
#define MISC_SWREG_CTRL_REG7_PDRIVE_NFET_MASK                      0x0e00
#define MISC_SWREG_CTRL_REG7_PDRIVE_NFET_ALIGN                     0
#define MISC_SWREG_CTRL_REG7_PDRIVE_NFET_BITS                      3
#define MISC_SWREG_CTRL_REG7_PDRIVE_NFET_SHIFT                     9

/* MISC :: swreg_ctrl_reg7 :: PDRIVE_Pfet [08:06] */
#define Wr_MISC_swreg_ctrl_reg7_PDRIVE_Pfet(x) WriteRegBits16(MISC_SWREG_CTRL_REG7,0x1c0,6,x)
#define Rd_MISC_swreg_ctrl_reg7_PDRIVE_Pfet(x) ReadRegBits16(MISC_SWREG_CTRL_REG7,0x1c0,6)
#define MISC_SWREG_CTRL_REG7_PDRIVE_PFET_MASK                      0x01c0
#define MISC_SWREG_CTRL_REG7_PDRIVE_PFET_ALIGN                     0
#define MISC_SWREG_CTRL_REG7_PDRIVE_PFET_BITS                      3
#define MISC_SWREG_CTRL_REG7_PDRIVE_PFET_SHIFT                     6

/* MISC :: swreg_ctrl_reg7 :: NDRIVE_Nfet [05:03] */
#define Wr_MISC_swreg_ctrl_reg7_NDRIVE_Nfet(x) WriteRegBits16(MISC_SWREG_CTRL_REG7,0x38,3,x)
#define Rd_MISC_swreg_ctrl_reg7_NDRIVE_Nfet(x) ReadRegBits16(MISC_SWREG_CTRL_REG7,0x38,3)
#define MISC_SWREG_CTRL_REG7_NDRIVE_NFET_MASK                      0x0038
#define MISC_SWREG_CTRL_REG7_NDRIVE_NFET_ALIGN                     0
#define MISC_SWREG_CTRL_REG7_NDRIVE_NFET_BITS                      3
#define MISC_SWREG_CTRL_REG7_NDRIVE_NFET_SHIFT                     3

/* MISC :: swreg_ctrl_reg7 :: NDRIVE_Pfet [02:00] */
#define Wr_MISC_swreg_ctrl_reg7_NDRIVE_Pfet(x) WriteRegBits16(MISC_SWREG_CTRL_REG7,0x7,0,x)
#define Rd_MISC_swreg_ctrl_reg7_NDRIVE_Pfet(x) ReadRegBits16(MISC_SWREG_CTRL_REG7,0x7,0)
#define MISC_SWREG_CTRL_REG7_NDRIVE_PFET_MASK                      0x0007
#define MISC_SWREG_CTRL_REG7_NDRIVE_PFET_ALIGN                     0
#define MISC_SWREG_CTRL_REG7_NDRIVE_PFET_BITS                      3
#define MISC_SWREG_CTRL_REG7_NDRIVE_PFET_SHIFT                     0


/****************************************************************************
 * MISC :: swreg_ctrl_reg8
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg8 :: burst_d_ctrl_6_3 [15:12] */
#define Wr_MISC_swreg_ctrl_reg8_burst_d_ctrl_6_3(x) WriteRegBits16(MISC_SWREG_CTRL_REG8,0xf000,12,x)
#define Rd_MISC_swreg_ctrl_reg8_burst_d_ctrl_6_3(x) ReadRegBits16(MISC_SWREG_CTRL_REG8,0xf000,12)
#define MISC_SWREG_CTRL_REG8_BURST_D_CTRL_6_3_MASK                 0xf000
#define MISC_SWREG_CTRL_REG8_BURST_D_CTRL_6_3_ALIGN                0
#define MISC_SWREG_CTRL_REG8_BURST_D_CTRL_6_3_BITS                 4
#define MISC_SWREG_CTRL_REG8_BURST_D_CTRL_6_3_SHIFT                12

/* MISC :: swreg_ctrl_reg8 :: IVCO_CTRL [11:09] */
#define Wr_MISC_swreg_ctrl_reg8_IVCO_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG8,0xe00,9,x)
#define Rd_MISC_swreg_ctrl_reg8_IVCO_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG8,0xe00,9)
#define MISC_SWREG_CTRL_REG8_IVCO_CTRL_MASK                        0x0e00
#define MISC_SWREG_CTRL_REG8_IVCO_CTRL_ALIGN                       0
#define MISC_SWREG_CTRL_REG8_IVCO_CTRL_BITS                        3
#define MISC_SWREG_CTRL_REG8_IVCO_CTRL_SHIFT                       9

/* MISC :: swreg_ctrl_reg8 :: phase_cntrl_comp_width [08:08] */
#define Wr_MISC_swreg_ctrl_reg8_phase_cntrl_comp_width(x) WriteRegBits16(MISC_SWREG_CTRL_REG8,0x100,8,x)
#define Rd_MISC_swreg_ctrl_reg8_phase_cntrl_comp_width(x) ReadRegBits16(MISC_SWREG_CTRL_REG8,0x100,8)
#define MISC_SWREG_CTRL_REG8_PHASE_CNTRL_COMP_WIDTH_MASK           0x0100
#define MISC_SWREG_CTRL_REG8_PHASE_CNTRL_COMP_WIDTH_ALIGN          0
#define MISC_SWREG_CTRL_REG8_PHASE_CNTRL_COMP_WIDTH_BITS           1
#define MISC_SWREG_CTRL_REG8_PHASE_CNTRL_COMP_WIDTH_SHIFT          8

/* MISC :: swreg_ctrl_reg8 :: GMBIAS_CTRL [07:07] */
#define Wr_MISC_swreg_ctrl_reg8_GMBIAS_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG8,0x80,7,x)
#define Rd_MISC_swreg_ctrl_reg8_GMBIAS_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG8,0x80,7)
#define MISC_SWREG_CTRL_REG8_GMBIAS_CTRL_MASK                      0x0080
#define MISC_SWREG_CTRL_REG8_GMBIAS_CTRL_ALIGN                     0
#define MISC_SWREG_CTRL_REG8_GMBIAS_CTRL_BITS                      1
#define MISC_SWREG_CTRL_REG8_GMBIAS_CTRL_SHIFT                     7

/* MISC :: swreg_ctrl_reg8 :: phase_cntrl_en [06:06] */
#define Wr_MISC_swreg_ctrl_reg8_phase_cntrl_en(x) WriteRegBits16(MISC_SWREG_CTRL_REG8,0x40,6,x)
#define Rd_MISC_swreg_ctrl_reg8_phase_cntrl_en(x) ReadRegBits16(MISC_SWREG_CTRL_REG8,0x40,6)
#define MISC_SWREG_CTRL_REG8_PHASE_CNTRL_EN_MASK                   0x0040
#define MISC_SWREG_CTRL_REG8_PHASE_CNTRL_EN_ALIGN                  0
#define MISC_SWREG_CTRL_REG8_PHASE_CNTRL_EN_BITS                   1
#define MISC_SWREG_CTRL_REG8_PHASE_CNTRL_EN_SHIFT                  6

/* MISC :: swreg_ctrl_reg8 :: OSC_ADJ [05:03] */
#define Wr_MISC_swreg_ctrl_reg8_OSC_ADJ(x) WriteRegBits16(MISC_SWREG_CTRL_REG8,0x38,3,x)
#define Rd_MISC_swreg_ctrl_reg8_OSC_ADJ(x) ReadRegBits16(MISC_SWREG_CTRL_REG8,0x38,3)
#define MISC_SWREG_CTRL_REG8_OSC_ADJ_MASK                          0x0038
#define MISC_SWREG_CTRL_REG8_OSC_ADJ_ALIGN                         0
#define MISC_SWREG_CTRL_REG8_OSC_ADJ_BITS                          3
#define MISC_SWREG_CTRL_REG8_OSC_ADJ_SHIFT                         3

/* MISC :: swreg_ctrl_reg8 :: RGM_CTRL [02:00] */
#define Wr_MISC_swreg_ctrl_reg8_RGM_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG8,0x7,0,x)
#define Rd_MISC_swreg_ctrl_reg8_RGM_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG8,0x7,0)
#define MISC_SWREG_CTRL_REG8_RGM_CTRL_MASK                         0x0007
#define MISC_SWREG_CTRL_REG8_RGM_CTRL_ALIGN                        0
#define MISC_SWREG_CTRL_REG8_RGM_CTRL_BITS                         3
#define MISC_SWREG_CTRL_REG8_RGM_CTRL_SHIFT                        0


/****************************************************************************
 * MISC :: swreg_ctrl_reg9
 ***************************************************************************/
/* MISC :: swreg_ctrl_reg9 :: adc_freq [15:14] */
#define Wr_MISC_swreg_ctrl_reg9_adc_freq(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0xc000,14,x)
#define Rd_MISC_swreg_ctrl_reg9_adc_freq(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0xc000,14)
#define MISC_SWREG_CTRL_REG9_ADC_FREQ_MASK                         0xc000
#define MISC_SWREG_CTRL_REG9_ADC_FREQ_ALIGN                        0
#define MISC_SWREG_CTRL_REG9_ADC_FREQ_BITS                         2
#define MISC_SWREG_CTRL_REG9_ADC_FREQ_SHIFT                        14

/* MISC :: swreg_ctrl_reg9 :: sys_clk_freq [13:12] */
#define Wr_MISC_swreg_ctrl_reg9_sys_clk_freq(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0x3000,12,x)
#define Rd_MISC_swreg_ctrl_reg9_sys_clk_freq(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0x3000,12)
#define MISC_SWREG_CTRL_REG9_SYS_CLK_FREQ_MASK                     0x3000
#define MISC_SWREG_CTRL_REG9_SYS_CLK_FREQ_ALIGN                    0
#define MISC_SWREG_CTRL_REG9_SYS_CLK_FREQ_BITS                     2
#define MISC_SWREG_CTRL_REG9_SYS_CLK_FREQ_SHIFT                    12

/* MISC :: swreg_ctrl_reg9 :: adc_gain [11:10] */
#define Wr_MISC_swreg_ctrl_reg9_adc_gain(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0xc00,10,x)
#define Rd_MISC_swreg_ctrl_reg9_adc_gain(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0xc00,10)
#define MISC_SWREG_CTRL_REG9_ADC_GAIN_MASK                         0x0c00
#define MISC_SWREG_CTRL_REG9_ADC_GAIN_ALIGN                        0
#define MISC_SWREG_CTRL_REG9_ADC_GAIN_BITS                         2
#define MISC_SWREG_CTRL_REG9_ADC_GAIN_SHIFT                        10

/* MISC :: swreg_ctrl_reg9 :: non_linear_gain_en [09:09] */
#define Wr_MISC_swreg_ctrl_reg9_non_linear_gain_en(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0x200,9,x)
#define Rd_MISC_swreg_ctrl_reg9_non_linear_gain_en(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0x200,9)
#define MISC_SWREG_CTRL_REG9_NON_LINEAR_GAIN_EN_MASK               0x0200
#define MISC_SWREG_CTRL_REG9_NON_LINEAR_GAIN_EN_ALIGN              0
#define MISC_SWREG_CTRL_REG9_NON_LINEAR_GAIN_EN_BITS               1
#define MISC_SWREG_CTRL_REG9_NON_LINEAR_GAIN_EN_SHIFT              9

/* MISC :: swreg_ctrl_reg9 :: non_linear_gain [08:08] */
#define Wr_MISC_swreg_ctrl_reg9_non_linear_gain(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0x100,8,x)
#define Rd_MISC_swreg_ctrl_reg9_non_linear_gain(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0x100,8)
#define MISC_SWREG_CTRL_REG9_NON_LINEAR_GAIN_MASK                  0x0100
#define MISC_SWREG_CTRL_REG9_NON_LINEAR_GAIN_ALIGN                 0
#define MISC_SWREG_CTRL_REG9_NON_LINEAR_GAIN_BITS                  1
#define MISC_SWREG_CTRL_REG9_NON_LINEAR_GAIN_SHIFT                 8

/* MISC :: swreg_ctrl_reg9 :: swreg_ctrl_reg9_reserved [07:07] */
#define MISC_SWREG_CTRL_REG9_SWREG_CTRL_REG9_RESERVED_MASK         0x0080
#define MISC_SWREG_CTRL_REG9_SWREG_CTRL_REG9_RESERVED_ALIGN        0
#define MISC_SWREG_CTRL_REG9_SWREG_CTRL_REG9_RESERVED_BITS         1
#define MISC_SWREG_CTRL_REG9_SWREG_CTRL_REG9_RESERVED_SHIFT        7

/* MISC :: swreg_ctrl_reg9 :: adaptive_deadtime_CTRL [06:05] */
#define Wr_MISC_swreg_ctrl_reg9_adaptive_deadtime_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0x60,5,x)
#define Rd_MISC_swreg_ctrl_reg9_adaptive_deadtime_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0x60,5)
#define MISC_SWREG_CTRL_REG9_ADAPTIVE_DEADTIME_CTRL_MASK           0x0060
#define MISC_SWREG_CTRL_REG9_ADAPTIVE_DEADTIME_CTRL_ALIGN          0
#define MISC_SWREG_CTRL_REG9_ADAPTIVE_DEADTIME_CTRL_BITS           2
#define MISC_SWREG_CTRL_REG9_ADAPTIVE_DEADTIME_CTRL_SHIFT          5

/* MISC :: swreg_ctrl_reg9 :: adaptive_deadtime_dis [04:04] */
#define Wr_MISC_swreg_ctrl_reg9_adaptive_deadtime_dis(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0x10,4,x)
#define Rd_MISC_swreg_ctrl_reg9_adaptive_deadtime_dis(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0x10,4)
#define MISC_SWREG_CTRL_REG9_ADAPTIVE_DEADTIME_DIS_MASK            0x0010
#define MISC_SWREG_CTRL_REG9_ADAPTIVE_DEADTIME_DIS_ALIGN           0
#define MISC_SWREG_CTRL_REG9_ADAPTIVE_DEADTIME_DIS_BITS            1
#define MISC_SWREG_CTRL_REG9_ADAPTIVE_DEADTIME_DIS_SHIFT           4

/* MISC :: swreg_ctrl_reg9 :: OVERCUR_REF_CTRL [03:02] */
#define Wr_MISC_swreg_ctrl_reg9_OVERCUR_REF_CTRL(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0xc,2,x)
#define Rd_MISC_swreg_ctrl_reg9_OVERCUR_REF_CTRL(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0xc,2)
#define MISC_SWREG_CTRL_REG9_OVERCUR_REF_CTRL_MASK                 0x000c
#define MISC_SWREG_CTRL_REG9_OVERCUR_REF_CTRL_ALIGN                0
#define MISC_SWREG_CTRL_REG9_OVERCUR_REF_CTRL_BITS                 2
#define MISC_SWREG_CTRL_REG9_OVERCUR_REF_CTRL_SHIFT                2

/* MISC :: swreg_ctrl_reg9 :: Test_mode_Vbg [01:01] */
#define Wr_MISC_swreg_ctrl_reg9_Test_mode_Vbg(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0x2,1,x)
#define Rd_MISC_swreg_ctrl_reg9_Test_mode_Vbg(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0x2,1)
#define MISC_SWREG_CTRL_REG9_TEST_MODE_VBG_MASK                    0x0002
#define MISC_SWREG_CTRL_REG9_TEST_MODE_VBG_ALIGN                   0
#define MISC_SWREG_CTRL_REG9_TEST_MODE_VBG_BITS                    1
#define MISC_SWREG_CTRL_REG9_TEST_MODE_VBG_SHIFT                   1

/* MISC :: swreg_ctrl_reg9 :: Test_mode_ADC [00:00] */
#define Wr_MISC_swreg_ctrl_reg9_Test_mode_ADC(x) WriteRegBits16(MISC_SWREG_CTRL_REG9,0x1,0,x)
#define Rd_MISC_swreg_ctrl_reg9_Test_mode_ADC(x) ReadRegBits16(MISC_SWREG_CTRL_REG9,0x1,0)
#define MISC_SWREG_CTRL_REG9_TEST_MODE_ADC_MASK                    0x0001
#define MISC_SWREG_CTRL_REG9_TEST_MODE_ADC_ALIGN                   0
#define MISC_SWREG_CTRL_REG9_TEST_MODE_ADC_BITS                    1
#define MISC_SWREG_CTRL_REG9_TEST_MODE_ADC_SHIFT                   0


/****************************************************************************
 * MISC :: swreg_stat_reg12
 ***************************************************************************/
/* MISC :: swreg_stat_reg12 :: swreg_stat_reg12_reserved_1 [15:12] */
#define MISC_SWREG_STAT_REG12_SWREG_STAT_REG12_RESERVED_1_MASK     0xf000
#define MISC_SWREG_STAT_REG12_SWREG_STAT_REG12_RESERVED_1_ALIGN    0
#define MISC_SWREG_STAT_REG12_SWREG_STAT_REG12_RESERVED_1_BITS     4
#define MISC_SWREG_STAT_REG12_SWREG_STAT_REG12_RESERVED_1_SHIFT    12

/* MISC :: swreg_stat_reg12 :: overvoltage_fault [11:11] */
#define Wr_MISC_swreg_stat_reg12_overvoltage_fault(x) WriteRegBits16(MISC_SWREG_STAT_REG12,0x800,11,x)
#define Rd_MISC_swreg_stat_reg12_overvoltage_fault(x) ReadRegBits16(MISC_SWREG_STAT_REG12,0x800,11)
#define MISC_SWREG_STAT_REG12_OVERVOLTAGE_FAULT_MASK               0x0800
#define MISC_SWREG_STAT_REG12_OVERVOLTAGE_FAULT_ALIGN              0
#define MISC_SWREG_STAT_REG12_OVERVOLTAGE_FAULT_BITS               1
#define MISC_SWREG_STAT_REG12_OVERVOLTAGE_FAULT_SHIFT              11

/* MISC :: swreg_stat_reg12 :: swreg_stat_reg12_reserved_2 [10:10] */
#define MISC_SWREG_STAT_REG12_SWREG_STAT_REG12_RESERVED_2_MASK     0x0400
#define MISC_SWREG_STAT_REG12_SWREG_STAT_REG12_RESERVED_2_ALIGN    0
#define MISC_SWREG_STAT_REG12_SWREG_STAT_REG12_RESERVED_2_BITS     1
#define MISC_SWREG_STAT_REG12_SWREG_STAT_REG12_RESERVED_2_SHIFT    10

/* MISC :: swreg_stat_reg12 :: undervoltage_fault [09:09] */
#define Wr_MISC_swreg_stat_reg12_undervoltage_fault(x) WriteRegBits16(MISC_SWREG_STAT_REG12,0x200,9,x)
#define Rd_MISC_swreg_stat_reg12_undervoltage_fault(x) ReadRegBits16(MISC_SWREG_STAT_REG12,0x200,9)
#define MISC_SWREG_STAT_REG12_UNDERVOLTAGE_FAULT_MASK              0x0200
#define MISC_SWREG_STAT_REG12_UNDERVOLTAGE_FAULT_ALIGN             0
#define MISC_SWREG_STAT_REG12_UNDERVOLTAGE_FAULT_BITS              1
#define MISC_SWREG_STAT_REG12_UNDERVOLTAGE_FAULT_SHIFT             9

/* MISC :: swreg_stat_reg12 :: duty_cycle [08:08] */
#define Wr_MISC_swreg_stat_reg12_duty_cycle(x) WriteRegBits16(MISC_SWREG_STAT_REG12,0x100,8,x)
#define Rd_MISC_swreg_stat_reg12_duty_cycle(x) ReadRegBits16(MISC_SWREG_STAT_REG12,0x100,8)
#define MISC_SWREG_STAT_REG12_DUTY_CYCLE_MASK                      0x0100
#define MISC_SWREG_STAT_REG12_DUTY_CYCLE_ALIGN                     0
#define MISC_SWREG_STAT_REG12_DUTY_CYCLE_BITS                      1
#define MISC_SWREG_STAT_REG12_DUTY_CYCLE_SHIFT                     8

/* MISC :: swreg_stat_reg12 :: adc_comp_in [07:00] */
#define Wr_MISC_swreg_stat_reg12_adc_comp_in(x) WriteRegBits16(MISC_SWREG_STAT_REG12,0xff,0,x)
#define Rd_MISC_swreg_stat_reg12_adc_comp_in(x) ReadRegBits16(MISC_SWREG_STAT_REG12,0xff,0)
#define MISC_SWREG_STAT_REG12_ADC_COMP_IN_MASK                     0x00ff
#define MISC_SWREG_STAT_REG12_ADC_COMP_IN_ALIGN                    0
#define MISC_SWREG_STAT_REG12_ADC_COMP_IN_BITS                     8
#define MISC_SWREG_STAT_REG12_ADC_COMP_IN_SHIFT                    0


/****************************************************************************
 * MISC :: swreg_stat_reg13
 ***************************************************************************/
/* MISC :: swreg_stat_reg13 :: swreg_stat_reg13_reserved [15:10] */
#define MISC_SWREG_STAT_REG13_SWREG_STAT_REG13_RESERVED_MASK       0xfc00
#define MISC_SWREG_STAT_REG13_SWREG_STAT_REG13_RESERVED_ALIGN      0
#define MISC_SWREG_STAT_REG13_SWREG_STAT_REG13_RESERVED_BITS       6
#define MISC_SWREG_STAT_REG13_SWREG_STAT_REG13_RESERVED_SHIFT      10

/* MISC :: swreg_stat_reg13 :: ilim_dutycycle [09:00] */
#define Wr_MISC_swreg_stat_reg13_ilim_dutycycle(x) WriteRegBits16(MISC_SWREG_STAT_REG13,0x3ff,0,x)
#define Rd_MISC_swreg_stat_reg13_ilim_dutycycle(x) ReadRegBits16(MISC_SWREG_STAT_REG13,0x3ff,0)
#define MISC_SWREG_STAT_REG13_ILIM_DUTYCYCLE_MASK                  0x03ff
#define MISC_SWREG_STAT_REG13_ILIM_DUTYCYCLE_ALIGN                 0
#define MISC_SWREG_STAT_REG13_ILIM_DUTYCYCLE_BITS                  10
#define MISC_SWREG_STAT_REG13_ILIM_DUTYCYCLE_SHIFT                 0


/****************************************************************************
 * MISC :: swreg_stat_reg14
 ***************************************************************************/
/* MISC :: swreg_stat_reg14 :: swreg_stat_reg14_reserved [15:11] */
#define MISC_SWREG_STAT_REG14_SWREG_STAT_REG14_RESERVED_MASK       0xf800
#define MISC_SWREG_STAT_REG14_SWREG_STAT_REG14_RESERVED_ALIGN      0
#define MISC_SWREG_STAT_REG14_SWREG_STAT_REG14_RESERVED_BITS       5
#define MISC_SWREG_STAT_REG14_SWREG_STAT_REG14_RESERVED_SHIFT      11

/* MISC :: swreg_stat_reg14 :: ilim_adcout [10:00] */
#define Wr_MISC_swreg_stat_reg14_ilim_adcout(x) WriteRegBits16(MISC_SWREG_STAT_REG14,0x7ff,0,x)
#define Rd_MISC_swreg_stat_reg14_ilim_adcout(x) ReadRegBits16(MISC_SWREG_STAT_REG14,0x7ff,0)
#define MISC_SWREG_STAT_REG14_ILIM_ADCOUT_MASK                     0x07ff
#define MISC_SWREG_STAT_REG14_ILIM_ADCOUT_ALIGN                    0
#define MISC_SWREG_STAT_REG14_ILIM_ADCOUT_BITS                     11
#define MISC_SWREG_STAT_REG14_ILIM_ADCOUT_SHIFT                    0


/****************************************************************************
 * MISC :: swreg_stat_reg15
 ***************************************************************************/
/* MISC :: swreg_stat_reg15 :: dig_ov_fault [15:15] */
#define Wr_MISC_swreg_stat_reg15_dig_ov_fault(x) WriteRegBits16(MISC_SWREG_STAT_REG15,0x8000,15,x)
#define Rd_MISC_swreg_stat_reg15_dig_ov_fault(x) ReadRegBits16(MISC_SWREG_STAT_REG15,0x8000,15)
#define MISC_SWREG_STAT_REG15_DIG_OV_FAULT_MASK                    0x8000
#define MISC_SWREG_STAT_REG15_DIG_OV_FAULT_ALIGN                   0
#define MISC_SWREG_STAT_REG15_DIG_OV_FAULT_BITS                    1
#define MISC_SWREG_STAT_REG15_DIG_OV_FAULT_SHIFT                   15

/* MISC :: swreg_stat_reg15 :: dig_uv_fault [14:14] */
#define Wr_MISC_swreg_stat_reg15_dig_uv_fault(x) WriteRegBits16(MISC_SWREG_STAT_REG15,0x4000,14,x)
#define Rd_MISC_swreg_stat_reg15_dig_uv_fault(x) ReadRegBits16(MISC_SWREG_STAT_REG15,0x4000,14)
#define MISC_SWREG_STAT_REG15_DIG_UV_FAULT_MASK                    0x4000
#define MISC_SWREG_STAT_REG15_DIG_UV_FAULT_ALIGN                   0
#define MISC_SWREG_STAT_REG15_DIG_UV_FAULT_BITS                    1
#define MISC_SWREG_STAT_REG15_DIG_UV_FAULT_SHIFT                   14

/* MISC :: swreg_stat_reg15 :: dig_duty_cycle_curr_limit_fault [13:13] */
#define Wr_MISC_swreg_stat_reg15_dig_duty_cycle_curr_limit_fault(x) WriteRegBits16(MISC_SWREG_STAT_REG15,0x2000,13,x)
#define Rd_MISC_swreg_stat_reg15_dig_duty_cycle_curr_limit_fault(x) ReadRegBits16(MISC_SWREG_STAT_REG15,0x2000,13)
#define MISC_SWREG_STAT_REG15_DIG_DUTY_CYCLE_CURR_LIMIT_FAULT_MASK 0x2000
#define MISC_SWREG_STAT_REG15_DIG_DUTY_CYCLE_CURR_LIMIT_FAULT_ALIGN 0
#define MISC_SWREG_STAT_REG15_DIG_DUTY_CYCLE_CURR_LIMIT_FAULT_BITS 1
#define MISC_SWREG_STAT_REG15_DIG_DUTY_CYCLE_CURR_LIMIT_FAULT_SHIFT 13

/* MISC :: swreg_stat_reg15 :: swreg_stat_reg15_reserved [12:05] */
#define MISC_SWREG_STAT_REG15_SWREG_STAT_REG15_RESERVED_MASK       0x1fe0
#define MISC_SWREG_STAT_REG15_SWREG_STAT_REG15_RESERVED_ALIGN      0
#define MISC_SWREG_STAT_REG15_SWREG_STAT_REG15_RESERVED_BITS       8
#define MISC_SWREG_STAT_REG15_SWREG_STAT_REG15_RESERVED_SHIFT      5

/* MISC :: swreg_stat_reg15 :: vin_select_1P5 [04:03] */
#define Wr_MISC_swreg_stat_reg15_vin_select_1P5(x) WriteRegBits16(MISC_SWREG_STAT_REG15,0x18,3,x)
#define Rd_MISC_swreg_stat_reg15_vin_select_1P5(x) ReadRegBits16(MISC_SWREG_STAT_REG15,0x18,3)
#define MISC_SWREG_STAT_REG15_VIN_SELECT_1P5_MASK                  0x0018
#define MISC_SWREG_STAT_REG15_VIN_SELECT_1P5_ALIGN                 0
#define MISC_SWREG_STAT_REG15_VIN_SELECT_1P5_BITS                  2
#define MISC_SWREG_STAT_REG15_VIN_SELECT_1P5_SHIFT                 3

/* MISC :: swreg_stat_reg15 :: pvin_select_1P5 [02:01] */
#define Wr_MISC_swreg_stat_reg15_pvin_select_1P5(x) WriteRegBits16(MISC_SWREG_STAT_REG15,0x6,1,x)
#define Rd_MISC_swreg_stat_reg15_pvin_select_1P5(x) ReadRegBits16(MISC_SWREG_STAT_REG15,0x6,1)
#define MISC_SWREG_STAT_REG15_PVIN_SELECT_1P5_MASK                 0x0006
#define MISC_SWREG_STAT_REG15_PVIN_SELECT_1P5_ALIGN                0
#define MISC_SWREG_STAT_REG15_PVIN_SELECT_1P5_BITS                 2
#define MISC_SWREG_STAT_REG15_PVIN_SELECT_1P5_SHIFT                1

/* MISC :: swreg_stat_reg15 :: ana_curr_limit [00:00] */
#define Wr_MISC_swreg_stat_reg15_ana_curr_limit(x) WriteRegBits16(MISC_SWREG_STAT_REG15,0x1,0,x)
#define Rd_MISC_swreg_stat_reg15_ana_curr_limit(x) ReadRegBits16(MISC_SWREG_STAT_REG15,0x1,0)
#define MISC_SWREG_STAT_REG15_ANA_CURR_LIMIT_MASK                  0x0001
#define MISC_SWREG_STAT_REG15_ANA_CURR_LIMIT_ALIGN                 0
#define MISC_SWREG_STAT_REG15_ANA_CURR_LIMIT_BITS                  1
#define MISC_SWREG_STAT_REG15_ANA_CURR_LIMIT_SHIFT                 0


/****************************************************************************
 * MISC :: swreg_access_ctrl_1
 ***************************************************************************/
/* MISC :: swreg_access_ctrl_1 :: swreg_access_ctrl_1_reserved [15:10] */
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_ACCESS_CTRL_1_RESERVED_MASK 0xfc00
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_ACCESS_CTRL_1_RESERVED_ALIGN 0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_ACCESS_CTRL_1_RESERVED_BITS 6
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_ACCESS_CTRL_1_RESERVED_SHIFT 10

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_9 [09:09] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_9(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x200,9,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_9(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x200,9)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_9_MASK           0x0200
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_9_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_9_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_9_SHIFT          9

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_8 [08:08] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_8(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x100,8,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_8(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x100,8)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_8_MASK           0x0100
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_8_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_8_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_8_SHIFT          8

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_7 [07:07] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_7(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x80,7,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_7(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x80,7)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_7_MASK           0x0080
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_7_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_7_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_7_SHIFT          7

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_6 [06:06] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_6(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x40,6,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_6(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x40,6)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_6_MASK           0x0040
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_6_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_6_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_6_SHIFT          6

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_5 [05:05] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_5(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x20,5,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_5(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x20,5)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_5_MASK           0x0020
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_5_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_5_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_5_SHIFT          5

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_4 [04:04] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_4(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x10,4,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_4(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x10,4)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_4_MASK           0x0010
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_4_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_4_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_4_SHIFT          4

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_3 [03:03] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_3(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x8,3,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_3(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x8,3)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_3_MASK           0x0008
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_3_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_3_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_3_SHIFT          3

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_2 [02:02] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_2(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x4,2,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_2(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x4,2)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_2_MASK           0x0004
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_2_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_2_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_2_SHIFT          2

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_1 [01:01] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_1(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x2,1,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_1(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x2,1)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_1_MASK           0x0002
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_1_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_1_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_1_SHIFT          1

/* MISC :: swreg_access_ctrl_1 :: swreg_write_ctrl_0 [00:00] */
#define Wr_MISC_swreg_access_ctrl_1_swreg_write_ctrl_0(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x1,0,x)
#define Rd_MISC_swreg_access_ctrl_1_swreg_write_ctrl_0(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_1,0x1,0)
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_0_MASK           0x0001
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_0_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_0_BITS           1
#define MISC_SWREG_ACCESS_CTRL_1_SWREG_WRITE_CTRL_0_SHIFT          0


/****************************************************************************
 * MISC :: swreg_access_ctrl_2
 ***************************************************************************/
/* MISC :: swreg_access_ctrl_2 :: swreg_read_stat_15 [15:15] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_stat_15(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x8000,15,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_stat_15(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x8000,15)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_15_MASK           0x8000
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_15_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_15_BITS           1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_15_SHIFT          15

/* MISC :: swreg_access_ctrl_2 :: swreg_read_stat_14 [14:14] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_stat_14(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x4000,14,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_stat_14(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x4000,14)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_14_MASK           0x4000
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_14_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_14_BITS           1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_14_SHIFT          14

/* MISC :: swreg_access_ctrl_2 :: swreg_read_stat_13 [13:13] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_stat_13(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x2000,13,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_stat_13(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x2000,13)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_13_MASK           0x2000
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_13_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_13_BITS           1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_13_SHIFT          13

/* MISC :: swreg_access_ctrl_2 :: swreg_read_stat_12 [12:12] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_stat_12(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x1000,12,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_stat_12(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x1000,12)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_12_MASK           0x1000
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_12_ALIGN          0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_12_BITS           1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_STAT_12_SHIFT          12

/* MISC :: swreg_access_ctrl_2 :: swreg_access_ctrl_2_reserved [11:10] */
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_ACCESS_CTRL_2_RESERVED_MASK 0x0c00
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_ACCESS_CTRL_2_RESERVED_ALIGN 0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_ACCESS_CTRL_2_RESERVED_BITS 2
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_ACCESS_CTRL_2_RESERVED_SHIFT 10

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_9 [09:09] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_9(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x200,9,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_9(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x200,9)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_9_MASK            0x0200
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_9_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_9_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_9_SHIFT           9

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_8 [08:08] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_8(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x100,8,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_8(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x100,8)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_8_MASK            0x0100
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_8_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_8_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_8_SHIFT           8

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_7 [07:07] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_7(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x80,7,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_7(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x80,7)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_7_MASK            0x0080
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_7_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_7_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_7_SHIFT           7

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_6 [06:06] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_6(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x40,6,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_6(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x40,6)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_6_MASK            0x0040
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_6_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_6_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_6_SHIFT           6

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_5 [05:05] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_5(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x20,5,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_5(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x20,5)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_5_MASK            0x0020
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_5_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_5_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_5_SHIFT           5

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_4 [04:04] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_4(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x10,4,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_4(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x10,4)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_4_MASK            0x0010
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_4_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_4_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_4_SHIFT           4

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_3 [03:03] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_3(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x8,3,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_3(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x8,3)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_3_MASK            0x0008
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_3_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_3_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_3_SHIFT           3

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_2 [02:02] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_2(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x4,2,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_2(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x4,2)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_2_MASK            0x0004
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_2_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_2_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_2_SHIFT           2

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_1 [01:01] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_1(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x2,1,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_1(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x2,1)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_1_MASK            0x0002
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_1_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_1_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_1_SHIFT           1

/* MISC :: swreg_access_ctrl_2 :: swreg_read_ctrl_0 [00:00] */
#define Wr_MISC_swreg_access_ctrl_2_swreg_read_ctrl_0(x) WriteRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x1,0,x)
#define Rd_MISC_swreg_access_ctrl_2_swreg_read_ctrl_0(x) ReadRegBits16(MISC_SWREG_ACCESS_CTRL_2,0x1,0)
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_0_MASK            0x0001
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_0_ALIGN           0
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_0_BITS            1
#define MISC_SWREG_ACCESS_CTRL_2_SWREG_READ_CTRL_0_SHIFT           0


/****************************************************************************
 * MISC :: swreg_control_status
 ***************************************************************************/
/* MISC :: swreg_control_status :: swreg_control_status_reserved [15:02] */
#define MISC_SWREG_CONTROL_STATUS_SWREG_CONTROL_STATUS_RESERVED_MASK 0xfffc
#define MISC_SWREG_CONTROL_STATUS_SWREG_CONTROL_STATUS_RESERVED_ALIGN 0
#define MISC_SWREG_CONTROL_STATUS_SWREG_CONTROL_STATUS_RESERVED_BITS 14
#define MISC_SWREG_CONTROL_STATUS_SWREG_CONTROL_STATUS_RESERVED_SHIFT 2

/* MISC :: swreg_control_status :: swreg_ext_pllclk_en [01:01] */
#define Wr_MISC_swreg_control_status_swreg_ext_pllclk_en(x) WriteRegBits16(MISC_SWREG_CONTROL_STATUS,0x2,1,x)
#define Rd_MISC_swreg_control_status_swreg_ext_pllclk_en(x) ReadRegBits16(MISC_SWREG_CONTROL_STATUS,0x2,1)
#define MISC_SWREG_CONTROL_STATUS_SWREG_EXT_PLLCLK_EN_MASK         0x0002
#define MISC_SWREG_CONTROL_STATUS_SWREG_EXT_PLLCLK_EN_ALIGN        0
#define MISC_SWREG_CONTROL_STATUS_SWREG_EXT_PLLCLK_EN_BITS         1
#define MISC_SWREG_CONTROL_STATUS_SWREG_EXT_PLLCLK_EN_SHIFT        1

/* MISC :: swreg_control_status :: swreg_pmu_stable_status [00:00] */
#define Wr_MISC_swreg_control_status_swreg_pmu_stable_status(x) WriteRegBits16(MISC_SWREG_CONTROL_STATUS,0x1,0,x)
#define Rd_MISC_swreg_control_status_swreg_pmu_stable_status(x) ReadRegBits16(MISC_SWREG_CONTROL_STATUS,0x1,0)
#define MISC_SWREG_CONTROL_STATUS_SWREG_PMU_STABLE_STATUS_MASK     0x0001
#define MISC_SWREG_CONTROL_STATUS_SWREG_PMU_STABLE_STATUS_ALIGN    0
#define MISC_SWREG_CONTROL_STATUS_SWREG_PMU_STABLE_STATUS_BITS     1
#define MISC_SWREG_CONTROL_STATUS_SWREG_PMU_STABLE_STATUS_SHIFT    0


/****************************************************************************
 * MISC :: sgmii_pwrdwn
 ***************************************************************************/
/* MISC :: sgmii_pwrdwn :: reserved0 [15:01] */
#define MISC_SGMII_PWRDWN_RESERVED0_MASK                           0xfffe
#define MISC_SGMII_PWRDWN_RESERVED0_ALIGN                          0
#define MISC_SGMII_PWRDWN_RESERVED0_BITS                           15
#define MISC_SGMII_PWRDWN_RESERVED0_SHIFT                          1

/* MISC :: sgmii_pwrdwn :: pwrdwn [00:00] */
#define Wr_MISC_sgmii_pwrdwn_pwrdwn(x) WriteRegBits16(MISC_SGMII_PWRDWN,0x1,0,x)
#define Rd_MISC_sgmii_pwrdwn_pwrdwn(x) ReadRegBits16(MISC_SGMII_PWRDWN,0x1,0)
#define MISC_SGMII_PWRDWN_PWRDWN_MASK                              0x0001
#define MISC_SGMII_PWRDWN_PWRDWN_ALIGN                             0
#define MISC_SGMII_PWRDWN_PWRDWN_BITS                              1
#define MISC_SGMII_PWRDWN_PWRDWN_SHIFT                             0


/****************************************************************************
 * MISC :: sgmii_hw_rst_dly_val
 ***************************************************************************/
/* MISC :: sgmii_hw_rst_dly_val :: reserved0 [15:15] */
#define MISC_SGMII_HW_RST_DLY_VAL_RESERVED0_MASK                   0x8000
#define MISC_SGMII_HW_RST_DLY_VAL_RESERVED0_ALIGN                  0
#define MISC_SGMII_HW_RST_DLY_VAL_RESERVED0_BITS                   1
#define MISC_SGMII_HW_RST_DLY_VAL_RESERVED0_SHIFT                  15

/* MISC :: sgmii_hw_rst_dly_val :: hw_rst_dly_val [14:00] */
#define Wr_MISC_sgmii_hw_rst_dly_val_hw_rst_dly_val(x) WriteRegBits16(MISC_SGMII_HW_RST_DLY_VAL,0x7fff,0,x)
#define Rd_MISC_sgmii_hw_rst_dly_val_hw_rst_dly_val(x) ReadRegBits16(MISC_SGMII_HW_RST_DLY_VAL,0x7fff,0)
#define MISC_SGMII_HW_RST_DLY_VAL_HW_RST_DLY_VAL_MASK              0x7fff
#define MISC_SGMII_HW_RST_DLY_VAL_HW_RST_DLY_VAL_ALIGN             0
#define MISC_SGMII_HW_RST_DLY_VAL_HW_RST_DLY_VAL_BITS              15
#define MISC_SGMII_HW_RST_DLY_VAL_HW_RST_DLY_VAL_SHIFT             0


/****************************************************************************
 * MISC :: sgmii_mdio_rst_dly_val
 ***************************************************************************/
/* MISC :: sgmii_mdio_rst_dly_val :: reserved0 [15:15] */
#define MISC_SGMII_MDIO_RST_DLY_VAL_RESERVED0_MASK                 0x8000
#define MISC_SGMII_MDIO_RST_DLY_VAL_RESERVED0_ALIGN                0
#define MISC_SGMII_MDIO_RST_DLY_VAL_RESERVED0_BITS                 1
#define MISC_SGMII_MDIO_RST_DLY_VAL_RESERVED0_SHIFT                15

/* MISC :: sgmii_mdio_rst_dly_val :: pcb_rd_ack_pos_sel [14:14] */
#define Wr_MISC_sgmii_mdio_rst_dly_val_pcb_rd_ack_pos_sel(x) WriteRegBits16(MISC_SGMII_MDIO_RST_DLY_VAL,0x4000,14,x)
#define Rd_MISC_sgmii_mdio_rst_dly_val_pcb_rd_ack_pos_sel(x) ReadRegBits16(MISC_SGMII_MDIO_RST_DLY_VAL,0x4000,14)
#define MISC_SGMII_MDIO_RST_DLY_VAL_PCB_RD_ACK_POS_SEL_MASK        0x4000
#define MISC_SGMII_MDIO_RST_DLY_VAL_PCB_RD_ACK_POS_SEL_ALIGN       0
#define MISC_SGMII_MDIO_RST_DLY_VAL_PCB_RD_ACK_POS_SEL_BITS        1
#define MISC_SGMII_MDIO_RST_DLY_VAL_PCB_RD_ACK_POS_SEL_SHIFT       14

/* MISC :: sgmii_mdio_rst_dly_val :: pcb_rd_cycle_len_sel [13:13] */
#define Wr_MISC_sgmii_mdio_rst_dly_val_pcb_rd_cycle_len_sel(x) WriteRegBits16(MISC_SGMII_MDIO_RST_DLY_VAL,0x2000,13,x)
#define Rd_MISC_sgmii_mdio_rst_dly_val_pcb_rd_cycle_len_sel(x) ReadRegBits16(MISC_SGMII_MDIO_RST_DLY_VAL,0x2000,13)
#define MISC_SGMII_MDIO_RST_DLY_VAL_PCB_RD_CYCLE_LEN_SEL_MASK      0x2000
#define MISC_SGMII_MDIO_RST_DLY_VAL_PCB_RD_CYCLE_LEN_SEL_ALIGN     0
#define MISC_SGMII_MDIO_RST_DLY_VAL_PCB_RD_CYCLE_LEN_SEL_BITS      1
#define MISC_SGMII_MDIO_RST_DLY_VAL_PCB_RD_CYCLE_LEN_SEL_SHIFT     13

/* MISC :: sgmii_mdio_rst_dly_val :: mdio_rst_dly_val [12:00] */
#define Wr_MISC_sgmii_mdio_rst_dly_val_mdio_rst_dly_val(x) WriteRegBits16(MISC_SGMII_MDIO_RST_DLY_VAL,0x1fff,0,x)
#define Rd_MISC_sgmii_mdio_rst_dly_val_mdio_rst_dly_val(x) ReadRegBits16(MISC_SGMII_MDIO_RST_DLY_VAL,0x1fff,0)
#define MISC_SGMII_MDIO_RST_DLY_VAL_MDIO_RST_DLY_VAL_MASK          0x1fff
#define MISC_SGMII_MDIO_RST_DLY_VAL_MDIO_RST_DLY_VAL_ALIGN         0
#define MISC_SGMII_MDIO_RST_DLY_VAL_MDIO_RST_DLY_VAL_BITS          13
#define MISC_SGMII_MDIO_RST_DLY_VAL_MDIO_RST_DLY_VAL_SHIFT         0


/****************************************************************************
 * MISC :: sgmii_pll_rst_dly_val
 ***************************************************************************/
/* MISC :: sgmii_pll_rst_dly_val :: reserved0 [15:15] */
#define MISC_SGMII_PLL_RST_DLY_VAL_RESERVED0_MASK                  0x8000
#define MISC_SGMII_PLL_RST_DLY_VAL_RESERVED0_ALIGN                 0
#define MISC_SGMII_PLL_RST_DLY_VAL_RESERVED0_BITS                  1
#define MISC_SGMII_PLL_RST_DLY_VAL_RESERVED0_SHIFT                 15

/* MISC :: sgmii_pll_rst_dly_val :: pcb_wr_ack_pos_sel [14:14] */
#define Wr_MISC_sgmii_pll_rst_dly_val_pcb_wr_ack_pos_sel(x) WriteRegBits16(MISC_SGMII_PLL_RST_DLY_VAL,0x4000,14,x)
#define Rd_MISC_sgmii_pll_rst_dly_val_pcb_wr_ack_pos_sel(x) ReadRegBits16(MISC_SGMII_PLL_RST_DLY_VAL,0x4000,14)
#define MISC_SGMII_PLL_RST_DLY_VAL_PCB_WR_ACK_POS_SEL_MASK         0x4000
#define MISC_SGMII_PLL_RST_DLY_VAL_PCB_WR_ACK_POS_SEL_ALIGN        0
#define MISC_SGMII_PLL_RST_DLY_VAL_PCB_WR_ACK_POS_SEL_BITS         1
#define MISC_SGMII_PLL_RST_DLY_VAL_PCB_WR_ACK_POS_SEL_SHIFT        14

/* MISC :: sgmii_pll_rst_dly_val :: pcb_wr_cycle_len_sel [13:12] */
#define Wr_MISC_sgmii_pll_rst_dly_val_pcb_wr_cycle_len_sel(x) WriteRegBits16(MISC_SGMII_PLL_RST_DLY_VAL,0x3000,12,x)
#define Rd_MISC_sgmii_pll_rst_dly_val_pcb_wr_cycle_len_sel(x) ReadRegBits16(MISC_SGMII_PLL_RST_DLY_VAL,0x3000,12)
#define MISC_SGMII_PLL_RST_DLY_VAL_PCB_WR_CYCLE_LEN_SEL_MASK       0x3000
#define MISC_SGMII_PLL_RST_DLY_VAL_PCB_WR_CYCLE_LEN_SEL_ALIGN      0
#define MISC_SGMII_PLL_RST_DLY_VAL_PCB_WR_CYCLE_LEN_SEL_BITS       2
#define MISC_SGMII_PLL_RST_DLY_VAL_PCB_WR_CYCLE_LEN_SEL_SHIFT      12

/* MISC :: sgmii_pll_rst_dly_val :: pll_rst_dly_val [11:00] */
#define Wr_MISC_sgmii_pll_rst_dly_val_pll_rst_dly_val(x) WriteRegBits16(MISC_SGMII_PLL_RST_DLY_VAL,0xfff,0,x)
#define Rd_MISC_sgmii_pll_rst_dly_val_pll_rst_dly_val(x) ReadRegBits16(MISC_SGMII_PLL_RST_DLY_VAL,0xfff,0)
#define MISC_SGMII_PLL_RST_DLY_VAL_PLL_RST_DLY_VAL_MASK            0x0fff
#define MISC_SGMII_PLL_RST_DLY_VAL_PLL_RST_DLY_VAL_ALIGN           0
#define MISC_SGMII_PLL_RST_DLY_VAL_PLL_RST_DLY_VAL_BITS            12
#define MISC_SGMII_PLL_RST_DLY_VAL_PLL_RST_DLY_VAL_SHIFT           0


/****************************************************************************
 * MISC :: sgmii_ext_ctl
 ***************************************************************************/
/* MISC :: sgmii_ext_ctl :: reserved0 [15:08] */
#define MISC_SGMII_EXT_CTL_RESERVED0_MASK                          0xff00
#define MISC_SGMII_EXT_CTL_RESERVED0_ALIGN                         0
#define MISC_SGMII_EXT_CTL_RESERVED0_BITS                          8
#define MISC_SGMII_EXT_CTL_RESERVED0_SHIFT                         8

/* MISC :: sgmii_ext_ctl :: rescal [07:04] */
#define Wr_MISC_sgmii_ext_ctl_rescal(x) WriteRegBits16(MISC_SGMII_EXT_CTL,0xf0,4,x)
#define Rd_MISC_sgmii_ext_ctl_rescal(x) ReadRegBits16(MISC_SGMII_EXT_CTL,0xf0,4)
#define MISC_SGMII_EXT_CTL_RESCAL_MASK                             0x00f0
#define MISC_SGMII_EXT_CTL_RESCAL_ALIGN                            0
#define MISC_SGMII_EXT_CTL_RESCAL_BITS                             4
#define MISC_SGMII_EXT_CTL_RESCAL_SHIFT                            4

/* MISC :: sgmii_ext_ctl :: reserved1 [03:01] */
#define MISC_SGMII_EXT_CTL_RESERVED1_MASK                          0x000e
#define MISC_SGMII_EXT_CTL_RESERVED1_ALIGN                         0
#define MISC_SGMII_EXT_CTL_RESERVED1_BITS                          3
#define MISC_SGMII_EXT_CTL_RESERVED1_SHIFT                         1

/* MISC :: sgmii_ext_ctl :: sgmii_ext_def [00:00] */
#define Wr_MISC_sgmii_ext_ctl_sgmii_ext_def(x) WriteRegBits16(MISC_SGMII_EXT_CTL,0x1,0,x)
#define Rd_MISC_sgmii_ext_ctl_sgmii_ext_def(x) ReadRegBits16(MISC_SGMII_EXT_CTL,0x1,0)
#define MISC_SGMII_EXT_CTL_SGMII_EXT_DEF_MASK                      0x0001
#define MISC_SGMII_EXT_CTL_SGMII_EXT_DEF_ALIGN                     0
#define MISC_SGMII_EXT_CTL_SGMII_EXT_DEF_BITS                      1
#define MISC_SGMII_EXT_CTL_SGMII_EXT_DEF_SHIFT                     0


/****************************************************************************
 * MISC :: sgmii_an0
 ***************************************************************************/
/* MISC :: sgmii_an0 :: reserved0 [15:02] */
#define MISC_SGMII_AN0_RESERVED0_MASK                              0xfffc
#define MISC_SGMII_AN0_RESERVED0_ALIGN                             0
#define MISC_SGMII_AN0_RESERVED0_BITS                              14
#define MISC_SGMII_AN0_RESERVED0_SHIFT                             2

/* MISC :: sgmii_an0 :: cu_link [01:01] */
#define Wr_MISC_sgmii_an0_cu_link(x) WriteRegBits16(MISC_SGMII_AN0,0x2,1,x)
#define Rd_MISC_sgmii_an0_cu_link(x) ReadRegBits16(MISC_SGMII_AN0,0x2,1)
#define MISC_SGMII_AN0_CU_LINK_MASK                                0x0002
#define MISC_SGMII_AN0_CU_LINK_ALIGN                               0
#define MISC_SGMII_AN0_CU_LINK_BITS                                1
#define MISC_SGMII_AN0_CU_LINK_SHIFT                               1

/* MISC :: sgmii_an0 :: restart_AN [00:00] */
#define Wr_MISC_sgmii_an0_restart_AN(x) WriteRegBits16(MISC_SGMII_AN0,0x1,0,x)
#define Rd_MISC_sgmii_an0_restart_AN(x) ReadRegBits16(MISC_SGMII_AN0,0x1,0)
#define MISC_SGMII_AN0_RESTART_AN_MASK                             0x0001
#define MISC_SGMII_AN0_RESTART_AN_ALIGN                            0
#define MISC_SGMII_AN0_RESTART_AN_BITS                             1
#define MISC_SGMII_AN0_RESTART_AN_SHIFT                            0


/****************************************************************************
 * MISC :: sgmii_base_page0
 ***************************************************************************/
/* MISC :: sgmii_base_page0 :: base_page [15:00] */
#define Wr_MISC_sgmii_base_page0_base_page(x) WriteReg16(MISC_SGMII_BASE_PAGE0,x)
#define Rd_MISC_sgmii_base_page0_base_page(x) ReadReg16(MISC_SGMII_BASE_PAGE0)
#define MISC_SGMII_BASE_PAGE0_BASE_PAGE_MASK                       0xffff
#define MISC_SGMII_BASE_PAGE0_BASE_PAGE_ALIGN                      0
#define MISC_SGMII_BASE_PAGE0_BASE_PAGE_BITS                       16
#define MISC_SGMII_BASE_PAGE0_BASE_PAGE_SHIFT                      0


/****************************************************************************
 * MISC :: sgmii_an1
 ***************************************************************************/
/* MISC :: sgmii_an1 :: reserved0 [15:02] */
#define MISC_SGMII_AN1_RESERVED0_MASK                              0xfffc
#define MISC_SGMII_AN1_RESERVED0_ALIGN                             0
#define MISC_SGMII_AN1_RESERVED0_BITS                              14
#define MISC_SGMII_AN1_RESERVED0_SHIFT                             2

/* MISC :: sgmii_an1 :: cu_link [01:01] */
#define Wr_MISC_sgmii_an1_cu_link(x) WriteRegBits16(MISC_SGMII_AN1,0x2,1,x)
#define Rd_MISC_sgmii_an1_cu_link(x) ReadRegBits16(MISC_SGMII_AN1,0x2,1)
#define MISC_SGMII_AN1_CU_LINK_MASK                                0x0002
#define MISC_SGMII_AN1_CU_LINK_ALIGN                               0
#define MISC_SGMII_AN1_CU_LINK_BITS                                1
#define MISC_SGMII_AN1_CU_LINK_SHIFT                               1

/* MISC :: sgmii_an1 :: restart_AN [00:00] */
#define Wr_MISC_sgmii_an1_restart_AN(x) WriteRegBits16(MISC_SGMII_AN1,0x1,0,x)
#define Rd_MISC_sgmii_an1_restart_AN(x) ReadRegBits16(MISC_SGMII_AN1,0x1,0)
#define MISC_SGMII_AN1_RESTART_AN_MASK                             0x0001
#define MISC_SGMII_AN1_RESTART_AN_ALIGN                            0
#define MISC_SGMII_AN1_RESTART_AN_BITS                             1
#define MISC_SGMII_AN1_RESTART_AN_SHIFT                            0


/****************************************************************************
 * MISC :: sgmii_base_page1
 ***************************************************************************/
/* MISC :: sgmii_base_page1 :: base_page [15:00] */
#define Wr_MISC_sgmii_base_page1_base_page(x) WriteReg16(MISC_SGMII_BASE_PAGE1,x)
#define Rd_MISC_sgmii_base_page1_base_page(x) ReadReg16(MISC_SGMII_BASE_PAGE1)
#define MISC_SGMII_BASE_PAGE1_BASE_PAGE_MASK                       0xffff
#define MISC_SGMII_BASE_PAGE1_BASE_PAGE_ALIGN                      0
#define MISC_SGMII_BASE_PAGE1_BASE_PAGE_BITS                       16
#define MISC_SGMII_BASE_PAGE1_BASE_PAGE_SHIFT                      0


/****************************************************************************
 * MISC :: sgmii_an2
 ***************************************************************************/
/* MISC :: sgmii_an2 :: reserved0 [15:02] */
#define MISC_SGMII_AN2_RESERVED0_MASK                              0xfffc
#define MISC_SGMII_AN2_RESERVED0_ALIGN                             0
#define MISC_SGMII_AN2_RESERVED0_BITS                              14
#define MISC_SGMII_AN2_RESERVED0_SHIFT                             2

/* MISC :: sgmii_an2 :: cu_link [01:01] */
#define Wr_MISC_sgmii_an2_cu_link(x) WriteRegBits16(MISC_SGMII_AN2,0x2,1,x)
#define Rd_MISC_sgmii_an2_cu_link(x) ReadRegBits16(MISC_SGMII_AN2,0x2,1)
#define MISC_SGMII_AN2_CU_LINK_MASK                                0x0002
#define MISC_SGMII_AN2_CU_LINK_ALIGN                               0
#define MISC_SGMII_AN2_CU_LINK_BITS                                1
#define MISC_SGMII_AN2_CU_LINK_SHIFT                               1

/* MISC :: sgmii_an2 :: restart_AN [00:00] */
#define Wr_MISC_sgmii_an2_restart_AN(x) WriteRegBits16(MISC_SGMII_AN2,0x1,0,x)
#define Rd_MISC_sgmii_an2_restart_AN(x) ReadRegBits16(MISC_SGMII_AN2,0x1,0)
#define MISC_SGMII_AN2_RESTART_AN_MASK                             0x0001
#define MISC_SGMII_AN2_RESTART_AN_ALIGN                            0
#define MISC_SGMII_AN2_RESTART_AN_BITS                             1
#define MISC_SGMII_AN2_RESTART_AN_SHIFT                            0


/****************************************************************************
 * MISC :: sgmii_base_page2
 ***************************************************************************/
/* MISC :: sgmii_base_page2 :: base_page [15:00] */
#define Wr_MISC_sgmii_base_page2_base_page(x) WriteReg16(MISC_SGMII_BASE_PAGE2,x)
#define Rd_MISC_sgmii_base_page2_base_page(x) ReadReg16(MISC_SGMII_BASE_PAGE2)
#define MISC_SGMII_BASE_PAGE2_BASE_PAGE_MASK                       0xffff
#define MISC_SGMII_BASE_PAGE2_BASE_PAGE_ALIGN                      0
#define MISC_SGMII_BASE_PAGE2_BASE_PAGE_BITS                       16
#define MISC_SGMII_BASE_PAGE2_BASE_PAGE_SHIFT                      0


/****************************************************************************
 * MISC :: sgmii_mdio_ctl
 ***************************************************************************/
/* MISC :: sgmii_mdio_ctl :: reserved0 [15:09] */
#define MISC_SGMII_MDIO_CTL_RESERVED0_MASK                         0xfe00
#define MISC_SGMII_MDIO_CTL_RESERVED0_ALIGN                        0
#define MISC_SGMII_MDIO_CTL_RESERVED0_BITS                         7
#define MISC_SGMII_MDIO_CTL_RESERVED0_SHIFT                        9

/* MISC :: sgmii_mdio_ctl :: md_clause_sel [08:08] */
#define Wr_MISC_sgmii_mdio_ctl_md_clause_sel(x) WriteRegBits16(MISC_SGMII_MDIO_CTL,0x100,8,x)
#define Rd_MISC_sgmii_mdio_ctl_md_clause_sel(x) ReadRegBits16(MISC_SGMII_MDIO_CTL,0x100,8)
#define MISC_SGMII_MDIO_CTL_MD_CLAUSE_SEL_MASK                     0x0100
#define MISC_SGMII_MDIO_CTL_MD_CLAUSE_SEL_ALIGN                    0
#define MISC_SGMII_MDIO_CTL_MD_CLAUSE_SEL_BITS                     1
#define MISC_SGMII_MDIO_CTL_MD_CLAUSE_SEL_SHIFT                    8

/* MISC :: sgmii_mdio_ctl :: reserved1 [07:05] */
#define MISC_SGMII_MDIO_CTL_RESERVED1_MASK                         0x00e0
#define MISC_SGMII_MDIO_CTL_RESERVED1_ALIGN                        0
#define MISC_SGMII_MDIO_CTL_RESERVED1_BITS                         3
#define MISC_SGMII_MDIO_CTL_RESERVED1_SHIFT                        5

/* MISC :: sgmii_mdio_ctl :: md_devad [04:00] */
#define Wr_MISC_sgmii_mdio_ctl_md_devad(x) WriteRegBits16(MISC_SGMII_MDIO_CTL,0x1f,0,x)
#define Rd_MISC_sgmii_mdio_ctl_md_devad(x) ReadRegBits16(MISC_SGMII_MDIO_CTL,0x1f,0)
#define MISC_SGMII_MDIO_CTL_MD_DEVAD_MASK                          0x001f
#define MISC_SGMII_MDIO_CTL_MD_DEVAD_ALIGN                         0
#define MISC_SGMII_MDIO_CTL_MD_DEVAD_BITS                          5
#define MISC_SGMII_MDIO_CTL_MD_DEVAD_SHIFT                         0


/****************************************************************************
 * MISC :: OTP_CPU_COMMAND
 ***************************************************************************/
/* MISC :: OTP_CPU_COMMAND :: reserved0 [15:06] */
#define MISC_OTP_CPU_COMMAND_RESERVED0_MASK                        0xffc0
#define MISC_OTP_CPU_COMMAND_RESERVED0_ALIGN                       0
#define MISC_OTP_CPU_COMMAND_RESERVED0_BITS                        10
#define MISC_OTP_CPU_COMMAND_RESERVED0_SHIFT                       6

/* MISC :: OTP_CPU_COMMAND :: OPCODE [05:00] */
#define Wr_MISC_OTP_CPU_COMMAND_OPCODE(x) WriteRegBits16(MISC_OTP_CPU_COMMAND,0x3f,0,x)
#define Rd_MISC_OTP_CPU_COMMAND_OPCODE(x) ReadRegBits16(MISC_OTP_CPU_COMMAND,0x3f,0)
#define MISC_OTP_CPU_COMMAND_OPCODE_MASK                           0x003f
#define MISC_OTP_CPU_COMMAND_OPCODE_ALIGN                          0
#define MISC_OTP_CPU_COMMAND_OPCODE_BITS                           6
#define MISC_OTP_CPU_COMMAND_OPCODE_SHIFT                          0


/****************************************************************************
 * MISC :: OTP_CPU_WRDATA_H
 ***************************************************************************/
/* MISC :: OTP_CPU_WRDATA_H :: CPU_WRDATA [15:00] */
#define Wr_MISC_OTP_CPU_WRDATA_H_CPU_WRDATA(x) WriteReg16(MISC_OTP_CPU_WRDATA_H,x)
#define Rd_MISC_OTP_CPU_WRDATA_H_CPU_WRDATA(x) ReadReg16(MISC_OTP_CPU_WRDATA_H)
#define MISC_OTP_CPU_WRDATA_H_CPU_WRDATA_MASK                      0xffff
#define MISC_OTP_CPU_WRDATA_H_CPU_WRDATA_ALIGN                     0
#define MISC_OTP_CPU_WRDATA_H_CPU_WRDATA_BITS                      16
#define MISC_OTP_CPU_WRDATA_H_CPU_WRDATA_SHIFT                     0


/****************************************************************************
 * MISC :: OTP_CPU_WRDATA_L
 ***************************************************************************/
/* MISC :: OTP_CPU_WRDATA_L :: CPU_WRDATA [15:00] */
#define Wr_MISC_OTP_CPU_WRDATA_L_CPU_WRDATA(x) WriteReg16(MISC_OTP_CPU_WRDATA_L,x)
#define Rd_MISC_OTP_CPU_WRDATA_L_CPU_WRDATA(x) ReadReg16(MISC_OTP_CPU_WRDATA_L)
#define MISC_OTP_CPU_WRDATA_L_CPU_WRDATA_MASK                      0xffff
#define MISC_OTP_CPU_WRDATA_L_CPU_WRDATA_ALIGN                     0
#define MISC_OTP_CPU_WRDATA_L_CPU_WRDATA_BITS                      16
#define MISC_OTP_CPU_WRDATA_L_CPU_WRDATA_SHIFT                     0


/****************************************************************************
 * MISC :: OTP_CONFIG
 ***************************************************************************/
/* MISC :: OTP_CONFIG :: HARD_RESET [15:15] */
#define Wr_MISC_OTP_CONFIG_HARD_RESET(x) WriteRegBits16(MISC_OTP_CONFIG,0x8000,15,x)
#define Rd_MISC_OTP_CONFIG_HARD_RESET(x) ReadRegBits16(MISC_OTP_CONFIG,0x8000,15)
#define MISC_OTP_CONFIG_HARD_RESET_MASK                            0x8000
#define MISC_OTP_CONFIG_HARD_RESET_ALIGN                           0
#define MISC_OTP_CONFIG_HARD_RESET_BITS                            1
#define MISC_OTP_CONFIG_HARD_RESET_SHIFT                           15

/* MISC :: OTP_CONFIG :: SOFT_RESET [14:14] */
#define Wr_MISC_OTP_CONFIG_SOFT_RESET(x) WriteRegBits16(MISC_OTP_CONFIG,0x4000,14,x)
#define Rd_MISC_OTP_CONFIG_SOFT_RESET(x) ReadRegBits16(MISC_OTP_CONFIG,0x4000,14)
#define MISC_OTP_CONFIG_SOFT_RESET_MASK                            0x4000
#define MISC_OTP_CONFIG_SOFT_RESET_ALIGN                           0
#define MISC_OTP_CONFIG_SOFT_RESET_BITS                            1
#define MISC_OTP_CONFIG_SOFT_RESET_SHIFT                           14

/* MISC :: OTP_CONFIG :: reserved0 [13:03] */
#define MISC_OTP_CONFIG_RESERVED0_MASK                             0x3ff8
#define MISC_OTP_CONFIG_RESERVED0_ALIGN                            0
#define MISC_OTP_CONFIG_RESERVED0_BITS                             11
#define MISC_OTP_CONFIG_RESERVED0_SHIFT                            3

/* MISC :: OTP_CONFIG :: CPU_CMD_WR [02:02] */
#define Wr_MISC_OTP_CONFIG_CPU_CMD_WR(x) WriteRegBits16(MISC_OTP_CONFIG,0x4,2,x)
#define Rd_MISC_OTP_CONFIG_CPU_CMD_WR(x) ReadRegBits16(MISC_OTP_CONFIG,0x4,2)
#define MISC_OTP_CONFIG_CPU_CMD_WR_MASK                            0x0004
#define MISC_OTP_CONFIG_CPU_CMD_WR_ALIGN                           0
#define MISC_OTP_CONFIG_CPU_CMD_WR_BITS                            1
#define MISC_OTP_CONFIG_CPU_CMD_WR_SHIFT                           2

/* MISC :: OTP_CONFIG :: CPU_MODE [01:01] */
#define Wr_MISC_OTP_CONFIG_CPU_MODE(x) WriteRegBits16(MISC_OTP_CONFIG,0x2,1,x)
#define Rd_MISC_OTP_CONFIG_CPU_MODE(x) ReadRegBits16(MISC_OTP_CONFIG,0x2,1)
#define MISC_OTP_CONFIG_CPU_MODE_MASK                              0x0002
#define MISC_OTP_CONFIG_CPU_MODE_ALIGN                             0
#define MISC_OTP_CONFIG_CPU_MODE_BITS                              1
#define MISC_OTP_CONFIG_CPU_MODE_SHIFT                             1

/* MISC :: OTP_CONFIG :: DIS_OTP_ACC [00:00] */
#define Wr_MISC_OTP_CONFIG_DIS_OTP_ACC(x) WriteRegBits16(MISC_OTP_CONFIG,0x1,0,x)
#define Rd_MISC_OTP_CONFIG_DIS_OTP_ACC(x) ReadRegBits16(MISC_OTP_CONFIG,0x1,0)
#define MISC_OTP_CONFIG_DIS_OTP_ACC_MASK                           0x0001
#define MISC_OTP_CONFIG_DIS_OTP_ACC_ALIGN                          0
#define MISC_OTP_CONFIG_DIS_OTP_ACC_BITS                           1
#define MISC_OTP_CONFIG_DIS_OTP_ACC_SHIFT                          0


/****************************************************************************
 * MISC :: OTP_ADDRESS
 ***************************************************************************/
/* MISC :: OTP_ADDRESS :: reserved0 [15:09] */
#define MISC_OTP_ADDRESS_RESERVED0_MASK                            0xfe00
#define MISC_OTP_ADDRESS_RESERVED0_ALIGN                           0
#define MISC_OTP_ADDRESS_RESERVED0_BITS                            7
#define MISC_OTP_ADDRESS_RESERVED0_SHIFT                           9

/* MISC :: OTP_ADDRESS :: ADDRESS [08:00] */
#define Wr_MISC_OTP_ADDRESS_ADDRESS(x) WriteRegBits16(MISC_OTP_ADDRESS,0x1ff,0,x)
#define Rd_MISC_OTP_ADDRESS_ADDRESS(x) ReadRegBits16(MISC_OTP_ADDRESS,0x1ff,0)
#define MISC_OTP_ADDRESS_ADDRESS_MASK                              0x01ff
#define MISC_OTP_ADDRESS_ADDRESS_ALIGN                             0
#define MISC_OTP_ADDRESS_ADDRESS_BITS                              9
#define MISC_OTP_ADDRESS_ADDRESS_SHIFT                             0


/****************************************************************************
 * MISC :: OTP_STATUS_1
 ***************************************************************************/
/* MISC :: OTP_STATUS_1 :: reserved0 [15:04] */
#define MISC_OTP_STATUS_1_RESERVED0_MASK                           0xfff0
#define MISC_OTP_STATUS_1_RESERVED0_ALIGN                          0
#define MISC_OTP_STATUS_1_RESERVED0_BITS                           12
#define MISC_OTP_STATUS_1_RESERVED0_SHIFT                          4

/* MISC :: OTP_STATUS_1 :: ILLEGAL_ADDR [03:03] */
#define Wr_MISC_OTP_STATUS_1_ILLEGAL_ADDR(x) WriteRegBits16(MISC_OTP_STATUS_1,0x8,3,x)
#define Rd_MISC_OTP_STATUS_1_ILLEGAL_ADDR(x) ReadRegBits16(MISC_OTP_STATUS_1,0x8,3)
#define MISC_OTP_STATUS_1_ILLEGAL_ADDR_MASK                        0x0008
#define MISC_OTP_STATUS_1_ILLEGAL_ADDR_ALIGN                       0
#define MISC_OTP_STATUS_1_ILLEGAL_ADDR_BITS                        1
#define MISC_OTP_STATUS_1_ILLEGAL_ADDR_SHIFT                       3

/* MISC :: OTP_STATUS_1 :: MAX_SW [02:02] */
#define Wr_MISC_OTP_STATUS_1_MAX_SW(x) WriteRegBits16(MISC_OTP_STATUS_1,0x4,2,x)
#define Rd_MISC_OTP_STATUS_1_MAX_SW(x) ReadRegBits16(MISC_OTP_STATUS_1,0x4,2)
#define MISC_OTP_STATUS_1_MAX_SW_MASK                              0x0004
#define MISC_OTP_STATUS_1_MAX_SW_ALIGN                             0
#define MISC_OTP_STATUS_1_MAX_SW_BITS                              1
#define MISC_OTP_STATUS_1_MAX_SW_SHIFT                             2

/* MISC :: OTP_STATUS_1 :: AUTO_RW_MAX [01:01] */
#define Wr_MISC_OTP_STATUS_1_AUTO_RW_MAX(x) WriteRegBits16(MISC_OTP_STATUS_1,0x2,1,x)
#define Rd_MISC_OTP_STATUS_1_AUTO_RW_MAX(x) ReadRegBits16(MISC_OTP_STATUS_1,0x2,1)
#define MISC_OTP_STATUS_1_AUTO_RW_MAX_MASK                         0x0002
#define MISC_OTP_STATUS_1_AUTO_RW_MAX_ALIGN                        0
#define MISC_OTP_STATUS_1_AUTO_RW_MAX_BITS                         1
#define MISC_OTP_STATUS_1_AUTO_RW_MAX_SHIFT                        1

/* MISC :: OTP_STATUS_1 :: MAX_RWP [00:00] */
#define Wr_MISC_OTP_STATUS_1_MAX_RWP(x) WriteRegBits16(MISC_OTP_STATUS_1,0x1,0,x)
#define Rd_MISC_OTP_STATUS_1_MAX_RWP(x) ReadRegBits16(MISC_OTP_STATUS_1,0x1,0)
#define MISC_OTP_STATUS_1_MAX_RWP_MASK                             0x0001
#define MISC_OTP_STATUS_1_MAX_RWP_ALIGN                            0
#define MISC_OTP_STATUS_1_MAX_RWP_BITS                             1
#define MISC_OTP_STATUS_1_MAX_RWP_SHIFT                            0


/****************************************************************************
 * MISC :: OTP_STATUS_0
 ***************************************************************************/
/* MISC :: OTP_STATUS_0 :: MAX_RW [15:15] */
#define Wr_MISC_OTP_STATUS_0_MAX_RW(x) WriteRegBits16(MISC_OTP_STATUS_0,0x8000,15,x)
#define Rd_MISC_OTP_STATUS_0_MAX_RW(x) ReadRegBits16(MISC_OTP_STATUS_0,0x8000,15)
#define MISC_OTP_STATUS_0_MAX_RW_MASK                              0x8000
#define MISC_OTP_STATUS_0_MAX_RW_ALIGN                             0
#define MISC_OTP_STATUS_0_MAX_RW_BITS                              1
#define MISC_OTP_STATUS_0_MAX_RW_SHIFT                             15

/* MISC :: OTP_STATUS_0 :: PGM_WD_FP_FAIL [14:14] */
#define Wr_MISC_OTP_STATUS_0_PGM_WD_FP_FAIL(x) WriteRegBits16(MISC_OTP_STATUS_0,0x4000,14,x)
#define Rd_MISC_OTP_STATUS_0_PGM_WD_FP_FAIL(x) ReadRegBits16(MISC_OTP_STATUS_0,0x4000,14)
#define MISC_OTP_STATUS_0_PGM_WD_FP_FAIL_MASK                      0x4000
#define MISC_OTP_STATUS_0_PGM_WD_FP_FAIL_ALIGN                     0
#define MISC_OTP_STATUS_0_PGM_WD_FP_FAIL_BITS                      1
#define MISC_OTP_STATUS_0_PGM_WD_FP_FAIL_SHIFT                     14

/* MISC :: OTP_STATUS_0 :: PROG_EN [13:13] */
#define Wr_MISC_OTP_STATUS_0_PROG_EN(x) WriteRegBits16(MISC_OTP_STATUS_0,0x2000,13,x)
#define Rd_MISC_OTP_STATUS_0_PROG_EN(x) ReadRegBits16(MISC_OTP_STATUS_0,0x2000,13)
#define MISC_OTP_STATUS_0_PROG_EN_MASK                             0x2000
#define MISC_OTP_STATUS_0_PROG_EN_ALIGN                            0
#define MISC_OTP_STATUS_0_PROG_EN_BITS                             1
#define MISC_OTP_STATUS_0_PROG_EN_SHIFT                            13

/* MISC :: OTP_STATUS_0 :: PROG_BLK_CMD [12:12] */
#define Wr_MISC_OTP_STATUS_0_PROG_BLK_CMD(x) WriteRegBits16(MISC_OTP_STATUS_0,0x1000,12,x)
#define Rd_MISC_OTP_STATUS_0_PROG_BLK_CMD(x) ReadRegBits16(MISC_OTP_STATUS_0,0x1000,12)
#define MISC_OTP_STATUS_0_PROG_BLK_CMD_MASK                        0x1000
#define MISC_OTP_STATUS_0_PROG_BLK_CMD_ALIGN                       0
#define MISC_OTP_STATUS_0_PROG_BLK_CMD_BITS                        1
#define MISC_OTP_STATUS_0_PROG_BLK_CMD_SHIFT                       12

/* MISC :: OTP_STATUS_0 :: PROG_SCR_FAIL [11:11] */
#define Wr_MISC_OTP_STATUS_0_PROG_SCR_FAIL(x) WriteRegBits16(MISC_OTP_STATUS_0,0x800,11,x)
#define Rd_MISC_OTP_STATUS_0_PROG_SCR_FAIL(x) ReadRegBits16(MISC_OTP_STATUS_0,0x800,11)
#define MISC_OTP_STATUS_0_PROG_SCR_FAIL_MASK                       0x0800
#define MISC_OTP_STATUS_0_PROG_SCR_FAIL_ALIGN                      0
#define MISC_OTP_STATUS_0_PROG_SCR_FAIL_BITS                       1
#define MISC_OTP_STATUS_0_PROG_SCR_FAIL_SHIFT                      11

/* MISC :: OTP_STATUS_0 :: PROG_WORD_FAIL [10:10] */
#define Wr_MISC_OTP_STATUS_0_PROG_WORD_FAIL(x) WriteRegBits16(MISC_OTP_STATUS_0,0x400,10,x)
#define Rd_MISC_OTP_STATUS_0_PROG_WORD_FAIL(x) ReadRegBits16(MISC_OTP_STATUS_0,0x400,10)
#define MISC_OTP_STATUS_0_PROG_WORD_FAIL_MASK                      0x0400
#define MISC_OTP_STATUS_0_PROG_WORD_FAIL_ALIGN                     0
#define MISC_OTP_STATUS_0_PROG_WORD_FAIL_BITS                      1
#define MISC_OTP_STATUS_0_PROG_WORD_FAIL_SHIFT                     10

/* MISC :: OTP_STATUS_0 :: INVALID_ADDR [09:09] */
#define Wr_MISC_OTP_STATUS_0_INVALID_ADDR(x) WriteRegBits16(MISC_OTP_STATUS_0,0x200,9,x)
#define Rd_MISC_OTP_STATUS_0_INVALID_ADDR(x) ReadRegBits16(MISC_OTP_STATUS_0,0x200,9)
#define MISC_OTP_STATUS_0_INVALID_ADDR_MASK                        0x0200
#define MISC_OTP_STATUS_0_INVALID_ADDR_ALIGN                       0
#define MISC_OTP_STATUS_0_INVALID_ADDR_BITS                        1
#define MISC_OTP_STATUS_0_INVALID_ADDR_SHIFT                       9

/* MISC :: OTP_STATUS_0 :: DEBUG_MODE [08:08] */
#define Wr_MISC_OTP_STATUS_0_DEBUG_MODE(x) WriteRegBits16(MISC_OTP_STATUS_0,0x100,8,x)
#define Rd_MISC_OTP_STATUS_0_DEBUG_MODE(x) ReadRegBits16(MISC_OTP_STATUS_0,0x100,8)
#define MISC_OTP_STATUS_0_DEBUG_MODE_MASK                          0x0100
#define MISC_OTP_STATUS_0_DEBUG_MODE_ALIGN                         0
#define MISC_OTP_STATUS_0_DEBUG_MODE_BITS                          1
#define MISC_OTP_STATUS_0_DEBUG_MODE_SHIFT                         8

/* MISC :: OTP_STATUS_0 :: MST_FSM_ERROR [07:07] */
#define Wr_MISC_OTP_STATUS_0_MST_FSM_ERROR(x) WriteRegBits16(MISC_OTP_STATUS_0,0x80,7,x)
#define Rd_MISC_OTP_STATUS_0_MST_FSM_ERROR(x) ReadRegBits16(MISC_OTP_STATUS_0,0x80,7)
#define MISC_OTP_STATUS_0_MST_FSM_ERROR_MASK                       0x0080
#define MISC_OTP_STATUS_0_MST_FSM_ERROR_ALIGN                      0
#define MISC_OTP_STATUS_0_MST_FSM_ERROR_BITS                       1
#define MISC_OTP_STATUS_0_MST_FSM_ERROR_SHIFT                      7

/* MISC :: OTP_STATUS_0 :: DEBUG_MODE_SET [06:06] */
#define Wr_MISC_OTP_STATUS_0_DEBUG_MODE_SET(x) WriteRegBits16(MISC_OTP_STATUS_0,0x40,6,x)
#define Rd_MISC_OTP_STATUS_0_DEBUG_MODE_SET(x) ReadRegBits16(MISC_OTP_STATUS_0,0x40,6)
#define MISC_OTP_STATUS_0_DEBUG_MODE_SET_MASK                      0x0040
#define MISC_OTP_STATUS_0_DEBUG_MODE_SET_ALIGN                     0
#define MISC_OTP_STATUS_0_DEBUG_MODE_SET_BITS                      1
#define MISC_OTP_STATUS_0_DEBUG_MODE_SET_SHIFT                     6

/* MISC :: OTP_STATUS_0 :: REF_OK [05:05] */
#define Wr_MISC_OTP_STATUS_0_REF_OK(x) WriteRegBits16(MISC_OTP_STATUS_0,0x20,5,x)
#define Rd_MISC_OTP_STATUS_0_REF_OK(x) ReadRegBits16(MISC_OTP_STATUS_0,0x20,5)
#define MISC_OTP_STATUS_0_REF_OK_MASK                              0x0020
#define MISC_OTP_STATUS_0_REF_OK_ALIGN                             0
#define MISC_OTP_STATUS_0_REF_OK_BITS                              1
#define MISC_OTP_STATUS_0_REF_OK_SHIFT                             5

/* MISC :: OTP_STATUS_0 :: CMD_FAIL [04:04] */
#define Wr_MISC_OTP_STATUS_0_CMD_FAIL(x) WriteRegBits16(MISC_OTP_STATUS_0,0x10,4,x)
#define Rd_MISC_OTP_STATUS_0_CMD_FAIL(x) ReadRegBits16(MISC_OTP_STATUS_0,0x10,4)
#define MISC_OTP_STATUS_0_CMD_FAIL_MASK                            0x0010
#define MISC_OTP_STATUS_0_CMD_FAIL_ALIGN                           0
#define MISC_OTP_STATUS_0_CMD_FAIL_BITS                            1
#define MISC_OTP_STATUS_0_CMD_FAIL_SHIFT                           4

/* MISC :: OTP_STATUS_0 :: FDONE [03:03] */
#define Wr_MISC_OTP_STATUS_0_FDONE(x) WriteRegBits16(MISC_OTP_STATUS_0,0x8,3,x)
#define Rd_MISC_OTP_STATUS_0_FDONE(x) ReadRegBits16(MISC_OTP_STATUS_0,0x8,3)
#define MISC_OTP_STATUS_0_FDONE_MASK                               0x0008
#define MISC_OTP_STATUS_0_FDONE_ALIGN                              0
#define MISC_OTP_STATUS_0_FDONE_BITS                               1
#define MISC_OTP_STATUS_0_FDONE_SHIFT                              3

/* MISC :: OTP_STATUS_0 :: PROG_OK [02:02] */
#define Wr_MISC_OTP_STATUS_0_PROG_OK(x) WriteRegBits16(MISC_OTP_STATUS_0,0x4,2,x)
#define Rd_MISC_OTP_STATUS_0_PROG_OK(x) ReadRegBits16(MISC_OTP_STATUS_0,0x4,2)
#define MISC_OTP_STATUS_0_PROG_OK_MASK                             0x0004
#define MISC_OTP_STATUS_0_PROG_OK_ALIGN                            0
#define MISC_OTP_STATUS_0_PROG_OK_BITS                             1
#define MISC_OTP_STATUS_0_PROG_OK_SHIFT                            2

/* MISC :: OTP_STATUS_0 :: CMD_DONE [01:01] */
#define Wr_MISC_OTP_STATUS_0_CMD_DONE(x) WriteRegBits16(MISC_OTP_STATUS_0,0x2,1,x)
#define Rd_MISC_OTP_STATUS_0_CMD_DONE(x) ReadRegBits16(MISC_OTP_STATUS_0,0x2,1)
#define MISC_OTP_STATUS_0_CMD_DONE_MASK                            0x0002
#define MISC_OTP_STATUS_0_CMD_DONE_ALIGN                           0
#define MISC_OTP_STATUS_0_CMD_DONE_BITS                            1
#define MISC_OTP_STATUS_0_CMD_DONE_SHIFT                           1

/* MISC :: OTP_STATUS_0 :: DATA_VALID [00:00] */
#define Wr_MISC_OTP_STATUS_0_DATA_VALID(x) WriteRegBits16(MISC_OTP_STATUS_0,0x1,0,x)
#define Rd_MISC_OTP_STATUS_0_DATA_VALID(x) ReadRegBits16(MISC_OTP_STATUS_0,0x1,0)
#define MISC_OTP_STATUS_0_DATA_VALID_MASK                          0x0001
#define MISC_OTP_STATUS_0_DATA_VALID_ALIGN                         0
#define MISC_OTP_STATUS_0_DATA_VALID_BITS                          1
#define MISC_OTP_STATUS_0_DATA_VALID_SHIFT                         0


/****************************************************************************
 * MISC :: OTP_RDATA_H
 ***************************************************************************/
/* MISC :: OTP_RDATA_H :: RDATA [15:00] */
#define Wr_MISC_OTP_RDATA_H_RDATA(x) WriteReg16(MISC_OTP_RDATA_H,x)
#define Rd_MISC_OTP_RDATA_H_RDATA(x) ReadReg16(MISC_OTP_RDATA_H)
#define MISC_OTP_RDATA_H_RDATA_MASK                                0xffff
#define MISC_OTP_RDATA_H_RDATA_ALIGN                               0
#define MISC_OTP_RDATA_H_RDATA_BITS                                16
#define MISC_OTP_RDATA_H_RDATA_SHIFT                               0


/****************************************************************************
 * MISC :: OTP_RDATA_L
 ***************************************************************************/
/* MISC :: OTP_RDATA_L :: RDATA [15:00] */
#define Wr_MISC_OTP_RDATA_L_RDATA(x) WriteReg16(MISC_OTP_RDATA_L,x)
#define Rd_MISC_OTP_RDATA_L_RDATA(x) ReadReg16(MISC_OTP_RDATA_L)
#define MISC_OTP_RDATA_L_RDATA_MASK                                0xffff
#define MISC_OTP_RDATA_L_RDATA_ALIGN                               0
#define MISC_OTP_RDATA_L_RDATA_BITS                                16
#define MISC_OTP_RDATA_L_RDATA_SHIFT                               0


/****************************************************************************
 * MISC :: BISR_STATUS
 ***************************************************************************/
/* MISC :: BISR_STATUS :: BISR_STATUS [15:00] */
#define Wr_MISC_BISR_STATUS_BISR_STATUS(x) WriteReg16(MISC_BISR_STATUS,x)
#define Rd_MISC_BISR_STATUS_BISR_STATUS(x) ReadReg16(MISC_BISR_STATUS)
#define MISC_BISR_STATUS_BISR_STATUS_MASK                          0xffff
#define MISC_BISR_STATUS_BISR_STATUS_ALIGN                         0
#define MISC_BISR_STATUS_BISR_STATUS_BITS                          16
#define MISC_BISR_STATUS_BISR_STATUS_SHIFT                         0


/****************************************************************************
 * MISC :: pvtmon_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_ctrl :: vmon_3p3_en [15:15] */
#define Wr_MISC_pvtmon_ctrl_vmon_3p3_en(x) WriteRegBits16(MISC_PVTMON_CTRL,0x8000,15,x)
#define Rd_MISC_pvtmon_ctrl_vmon_3p3_en(x) ReadRegBits16(MISC_PVTMON_CTRL,0x8000,15)
#define MISC_PVTMON_CTRL_VMON_3P3_EN_MASK                          0x8000
#define MISC_PVTMON_CTRL_VMON_3P3_EN_ALIGN                         0
#define MISC_PVTMON_CTRL_VMON_3P3_EN_BITS                          1
#define MISC_PVTMON_CTRL_VMON_3P3_EN_SHIFT                         15

/* MISC :: pvtmon_ctrl :: vmon_1p8_en [14:14] */
#define Wr_MISC_pvtmon_ctrl_vmon_1p8_en(x) WriteRegBits16(MISC_PVTMON_CTRL,0x4000,14,x)
#define Rd_MISC_pvtmon_ctrl_vmon_1p8_en(x) ReadRegBits16(MISC_PVTMON_CTRL,0x4000,14)
#define MISC_PVTMON_CTRL_VMON_1P8_EN_MASK                          0x4000
#define MISC_PVTMON_CTRL_VMON_1P8_EN_ALIGN                         0
#define MISC_PVTMON_CTRL_VMON_1P8_EN_BITS                          1
#define MISC_PVTMON_CTRL_VMON_1P8_EN_SHIFT                         14

/* MISC :: pvtmon_ctrl :: vmon_1v_en [13:13] */
#define Wr_MISC_pvtmon_ctrl_vmon_1v_en(x) WriteRegBits16(MISC_PVTMON_CTRL,0x2000,13,x)
#define Rd_MISC_pvtmon_ctrl_vmon_1v_en(x) ReadRegBits16(MISC_PVTMON_CTRL,0x2000,13)
#define MISC_PVTMON_CTRL_VMON_1V_EN_MASK                           0x2000
#define MISC_PVTMON_CTRL_VMON_1V_EN_ALIGN                          0
#define MISC_PVTMON_CTRL_VMON_1V_EN_BITS                           1
#define MISC_PVTMON_CTRL_VMON_1V_EN_SHIFT                          13

/* MISC :: pvtmon_ctrl :: tmon_en [12:12] */
#define Wr_MISC_pvtmon_ctrl_tmon_en(x) WriteRegBits16(MISC_PVTMON_CTRL,0x1000,12,x)
#define Rd_MISC_pvtmon_ctrl_tmon_en(x) ReadRegBits16(MISC_PVTMON_CTRL,0x1000,12)
#define MISC_PVTMON_CTRL_TMON_EN_MASK                              0x1000
#define MISC_PVTMON_CTRL_TMON_EN_ALIGN                             0
#define MISC_PVTMON_CTRL_TMON_EN_BITS                              1
#define MISC_PVTMON_CTRL_TMON_EN_SHIFT                             12

/* MISC :: pvtmon_ctrl :: pvtmon_ext_intr_en [11:11] */
#define Wr_MISC_pvtmon_ctrl_pvtmon_ext_intr_en(x) WriteRegBits16(MISC_PVTMON_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_ctrl_pvtmon_ext_intr_en(x) ReadRegBits16(MISC_PVTMON_CTRL,0x800,11)
#define MISC_PVTMON_CTRL_PVTMON_EXT_INTR_EN_MASK                   0x0800
#define MISC_PVTMON_CTRL_PVTMON_EXT_INTR_EN_ALIGN                  0
#define MISC_PVTMON_CTRL_PVTMON_EXT_INTR_EN_BITS                   1
#define MISC_PVTMON_CTRL_PVTMON_EXT_INTR_EN_SHIFT                  11

/* MISC :: pvtmon_ctrl :: pvtmon_intr_en [10:10] */
#define Wr_MISC_pvtmon_ctrl_pvtmon_intr_en(x) WriteRegBits16(MISC_PVTMON_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_ctrl_pvtmon_intr_en(x) ReadRegBits16(MISC_PVTMON_CTRL,0x400,10)
#define MISC_PVTMON_CTRL_PVTMON_INTR_EN_MASK                       0x0400
#define MISC_PVTMON_CTRL_PVTMON_INTR_EN_ALIGN                      0
#define MISC_PVTMON_CTRL_PVTMON_INTR_EN_BITS                       1
#define MISC_PVTMON_CTRL_PVTMON_INTR_EN_SHIFT                      10

/* MISC :: pvtmon_ctrl :: clksel [09:08] */
#define Wr_MISC_pvtmon_ctrl_clksel(x) WriteRegBits16(MISC_PVTMON_CTRL,0x300,8,x)
#define Rd_MISC_pvtmon_ctrl_clksel(x) ReadRegBits16(MISC_PVTMON_CTRL,0x300,8)
#define MISC_PVTMON_CTRL_CLKSEL_MASK                               0x0300
#define MISC_PVTMON_CTRL_CLKSEL_ALIGN                              0
#define MISC_PVTMON_CTRL_CLKSEL_BITS                               2
#define MISC_PVTMON_CTRL_CLKSEL_SHIFT                              8

/* MISC :: pvtmon_ctrl :: reserved0 [07:07] */
#define MISC_PVTMON_CTRL_RESERVED0_MASK                            0x0080
#define MISC_PVTMON_CTRL_RESERVED0_ALIGN                           0
#define MISC_PVTMON_CTRL_RESERVED0_BITS                            1
#define MISC_PVTMON_CTRL_RESERVED0_SHIFT                           7

/* MISC :: pvtmon_ctrl :: i_PVTMON_sel [06:04] */
#define Wr_MISC_pvtmon_ctrl_i_PVTMON_sel(x) WriteRegBits16(MISC_PVTMON_CTRL,0x70,4,x)
#define Rd_MISC_pvtmon_ctrl_i_PVTMON_sel(x) ReadRegBits16(MISC_PVTMON_CTRL,0x70,4)
#define MISC_PVTMON_CTRL_I_PVTMON_SEL_MASK                         0x0070
#define MISC_PVTMON_CTRL_I_PVTMON_SEL_ALIGN                        0
#define MISC_PVTMON_CTRL_I_PVTMON_SEL_BITS                         3
#define MISC_PVTMON_CTRL_I_PVTMON_SEL_SHIFT                        4

/* MISC :: pvtmon_ctrl :: reserved1 [03:02] */
#define MISC_PVTMON_CTRL_RESERVED1_MASK                            0x000c
#define MISC_PVTMON_CTRL_RESERVED1_ALIGN                           0
#define MISC_PVTMON_CTRL_RESERVED1_BITS                            2
#define MISC_PVTMON_CTRL_RESERVED1_SHIFT                           2

/* MISC :: pvtmon_ctrl :: auto_mode [01:01] */
#define Wr_MISC_pvtmon_ctrl_auto_mode(x) WriteRegBits16(MISC_PVTMON_CTRL,0x2,1,x)
#define Rd_MISC_pvtmon_ctrl_auto_mode(x) ReadRegBits16(MISC_PVTMON_CTRL,0x2,1)
#define MISC_PVTMON_CTRL_AUTO_MODE_MASK                            0x0002
#define MISC_PVTMON_CTRL_AUTO_MODE_ALIGN                           0
#define MISC_PVTMON_CTRL_AUTO_MODE_BITS                            1
#define MISC_PVTMON_CTRL_AUTO_MODE_SHIFT                           1

/* MISC :: pvtmon_ctrl :: i_pwrdn [00:00] */
#define Wr_MISC_pvtmon_ctrl_i_pwrdn(x) WriteRegBits16(MISC_PVTMON_CTRL,0x1,0,x)
#define Rd_MISC_pvtmon_ctrl_i_pwrdn(x) ReadRegBits16(MISC_PVTMON_CTRL,0x1,0)
#define MISC_PVTMON_CTRL_I_PWRDN_MASK                              0x0001
#define MISC_PVTMON_CTRL_I_PWRDN_ALIGN                             0
#define MISC_PVTMON_CTRL_I_PWRDN_BITS                              1
#define MISC_PVTMON_CTRL_I_PWRDN_SHIFT                             0


/****************************************************************************
 * MISC :: pvtmon_sample_num
 ***************************************************************************/
/* MISC :: pvtmon_sample_num :: reserved0 [15:08] */
#define MISC_PVTMON_SAMPLE_NUM_RESERVED0_MASK                      0xff00
#define MISC_PVTMON_SAMPLE_NUM_RESERVED0_ALIGN                     0
#define MISC_PVTMON_SAMPLE_NUM_RESERVED0_BITS                      8
#define MISC_PVTMON_SAMPLE_NUM_RESERVED0_SHIFT                     8

/* MISC :: pvtmon_sample_num :: vmon_sample_num [07:04] */
#define Wr_MISC_pvtmon_sample_num_vmon_sample_num(x) WriteRegBits16(MISC_PVTMON_SAMPLE_NUM,0xf0,4,x)
#define Rd_MISC_pvtmon_sample_num_vmon_sample_num(x) ReadRegBits16(MISC_PVTMON_SAMPLE_NUM,0xf0,4)
#define MISC_PVTMON_SAMPLE_NUM_VMON_SAMPLE_NUM_MASK                0x00f0
#define MISC_PVTMON_SAMPLE_NUM_VMON_SAMPLE_NUM_ALIGN               0
#define MISC_PVTMON_SAMPLE_NUM_VMON_SAMPLE_NUM_BITS                4
#define MISC_PVTMON_SAMPLE_NUM_VMON_SAMPLE_NUM_SHIFT               4

/* MISC :: pvtmon_sample_num :: tmon_sample_num [03:00] */
#define Wr_MISC_pvtmon_sample_num_tmon_sample_num(x) WriteRegBits16(MISC_PVTMON_SAMPLE_NUM,0xf,0,x)
#define Rd_MISC_pvtmon_sample_num_tmon_sample_num(x) ReadRegBits16(MISC_PVTMON_SAMPLE_NUM,0xf,0)
#define MISC_PVTMON_SAMPLE_NUM_TMON_SAMPLE_NUM_MASK                0x000f
#define MISC_PVTMON_SAMPLE_NUM_TMON_SAMPLE_NUM_ALIGN               0
#define MISC_PVTMON_SAMPLE_NUM_TMON_SAMPLE_NUM_BITS                4
#define MISC_PVTMON_SAMPLE_NUM_TMON_SAMPLE_NUM_SHIFT               0


/****************************************************************************
 * MISC :: pvtmon_tmon_period
 ***************************************************************************/
/* MISC :: pvtmon_tmon_period :: reserved0 [15:04] */
#define MISC_PVTMON_TMON_PERIOD_RESERVED0_MASK                     0xfff0
#define MISC_PVTMON_TMON_PERIOD_RESERVED0_ALIGN                    0
#define MISC_PVTMON_TMON_PERIOD_RESERVED0_BITS                     12
#define MISC_PVTMON_TMON_PERIOD_RESERVED0_SHIFT                    4

/* MISC :: pvtmon_tmon_period :: tmon_period [03:00] */
#define Wr_MISC_pvtmon_tmon_period_tmon_period(x) WriteRegBits16(MISC_PVTMON_TMON_PERIOD,0xf,0,x)
#define Rd_MISC_pvtmon_tmon_period_tmon_period(x) ReadRegBits16(MISC_PVTMON_TMON_PERIOD,0xf,0)
#define MISC_PVTMON_TMON_PERIOD_TMON_PERIOD_MASK                   0x000f
#define MISC_PVTMON_TMON_PERIOD_TMON_PERIOD_ALIGN                  0
#define MISC_PVTMON_TMON_PERIOD_TMON_PERIOD_BITS                   4
#define MISC_PVTMON_TMON_PERIOD_TMON_PERIOD_SHIFT                  0


/****************************************************************************
 * MISC :: pvtmon_i_ctrl_31_16
 ***************************************************************************/
/* MISC :: pvtmon_i_ctrl_31_16 :: i_ctrl_31_16 [15:00] */
#define Wr_MISC_pvtmon_i_ctrl_31_16_i_ctrl_31_16(x) WriteReg16(MISC_PVTMON_I_CTRL_31_16,x)
#define Rd_MISC_pvtmon_i_ctrl_31_16_i_ctrl_31_16(x) ReadReg16(MISC_PVTMON_I_CTRL_31_16)
#define MISC_PVTMON_I_CTRL_31_16_I_CTRL_31_16_MASK                 0xffff
#define MISC_PVTMON_I_CTRL_31_16_I_CTRL_31_16_ALIGN                0
#define MISC_PVTMON_I_CTRL_31_16_I_CTRL_31_16_BITS                 16
#define MISC_PVTMON_I_CTRL_31_16_I_CTRL_31_16_SHIFT                0


/****************************************************************************
 * MISC :: pvtmon_i_ctrl_15_0
 ***************************************************************************/
/* MISC :: pvtmon_i_ctrl_15_0 :: i_ctrl_15_0 [15:00] */
#define Wr_MISC_pvtmon_i_ctrl_15_0_i_ctrl_15_0(x) WriteReg16(MISC_PVTMON_I_CTRL_15_0,x)
#define Rd_MISC_pvtmon_i_ctrl_15_0_i_ctrl_15_0(x) ReadReg16(MISC_PVTMON_I_CTRL_15_0)
#define MISC_PVTMON_I_CTRL_15_0_I_CTRL_15_0_MASK                   0xffff
#define MISC_PVTMON_I_CTRL_15_0_I_CTRL_15_0_ALIGN                  0
#define MISC_PVTMON_I_CTRL_15_0_I_CTRL_15_0_BITS                   16
#define MISC_PVTMON_I_CTRL_15_0_I_CTRL_15_0_SHIFT                  0


/****************************************************************************
 * MISC :: pvtmon_adc_data
 ***************************************************************************/
/* MISC :: pvtmon_adc_data :: reserved0 [15:10] */
#define MISC_PVTMON_ADC_DATA_RESERVED0_MASK                        0xfc00
#define MISC_PVTMON_ADC_DATA_RESERVED0_ALIGN                       0
#define MISC_PVTMON_ADC_DATA_RESERVED0_BITS                        6
#define MISC_PVTMON_ADC_DATA_RESERVED0_SHIFT                       10

/* MISC :: pvtmon_adc_data :: ADC_data [09:00] */
#define Wr_MISC_pvtmon_adc_data_ADC_data(x) WriteRegBits16(MISC_PVTMON_ADC_DATA,0x3ff,0,x)
#define Rd_MISC_pvtmon_adc_data_ADC_data(x) ReadRegBits16(MISC_PVTMON_ADC_DATA,0x3ff,0)
#define MISC_PVTMON_ADC_DATA_ADC_DATA_MASK                         0x03ff
#define MISC_PVTMON_ADC_DATA_ADC_DATA_ALIGN                        0
#define MISC_PVTMON_ADC_DATA_ADC_DATA_BITS                         10
#define MISC_PVTMON_ADC_DATA_ADC_DATA_SHIFT                        0


/****************************************************************************
 * MISC :: pvtmon_dac_data
 ***************************************************************************/
/* MISC :: pvtmon_dac_data :: reserved0 [15:10] */
#define MISC_PVTMON_DAC_DATA_RESERVED0_MASK                        0xfc00
#define MISC_PVTMON_DAC_DATA_RESERVED0_ALIGN                       0
#define MISC_PVTMON_DAC_DATA_RESERVED0_BITS                        6
#define MISC_PVTMON_DAC_DATA_RESERVED0_SHIFT                       10

/* MISC :: pvtmon_dac_data :: DAC_data [09:00] */
#define Wr_MISC_pvtmon_dac_data_DAC_data(x) WriteRegBits16(MISC_PVTMON_DAC_DATA,0x3ff,0,x)
#define Rd_MISC_pvtmon_dac_data_DAC_data(x) ReadRegBits16(MISC_PVTMON_DAC_DATA,0x3ff,0)
#define MISC_PVTMON_DAC_DATA_DAC_DATA_MASK                         0x03ff
#define MISC_PVTMON_DAC_DATA_DAC_DATA_ALIGN                        0
#define MISC_PVTMON_DAC_DATA_DAC_DATA_BITS                         10
#define MISC_PVTMON_DAC_DATA_DAC_DATA_SHIFT                        0


/****************************************************************************
 * MISC :: pvtmon_tmon_thresh1_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_tmon_thresh1_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_TMON_THRESH1_CTRL_RESERVED0_MASK               0xf000
#define MISC_PVTMON_TMON_THRESH1_CTRL_RESERVED0_ALIGN              0
#define MISC_PVTMON_TMON_THRESH1_CTRL_RESERVED0_BITS               4
#define MISC_PVTMON_TMON_THRESH1_CTRL_RESERVED0_SHIFT              12

/* MISC :: pvtmon_tmon_thresh1_ctrl :: tmon_thresh1_reset_en [11:11] */
#define Wr_MISC_pvtmon_tmon_thresh1_ctrl_tmon_thresh1_reset_en(x) WriteRegBits16(MISC_PVTMON_TMON_THRESH1_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_tmon_thresh1_ctrl_tmon_thresh1_reset_en(x) ReadRegBits16(MISC_PVTMON_TMON_THRESH1_CTRL,0x800,11)
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_RESET_EN_MASK   0x0800
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_RESET_EN_ALIGN  0
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_RESET_EN_BITS   1
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_RESET_EN_SHIFT  11

/* MISC :: pvtmon_tmon_thresh1_ctrl :: tmon_thresh1_intr_en [10:10] */
#define Wr_MISC_pvtmon_tmon_thresh1_ctrl_tmon_thresh1_intr_en(x) WriteRegBits16(MISC_PVTMON_TMON_THRESH1_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_tmon_thresh1_ctrl_tmon_thresh1_intr_en(x) ReadRegBits16(MISC_PVTMON_TMON_THRESH1_CTRL,0x400,10)
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_INTR_EN_MASK    0x0400
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_INTR_EN_ALIGN   0
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_INTR_EN_BITS    1
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_INTR_EN_SHIFT   10

/* MISC :: pvtmon_tmon_thresh1_ctrl :: tmon_thresh1 [09:00] */
#define Wr_MISC_pvtmon_tmon_thresh1_ctrl_tmon_thresh1(x) WriteRegBits16(MISC_PVTMON_TMON_THRESH1_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_tmon_thresh1_ctrl_tmon_thresh1(x) ReadRegBits16(MISC_PVTMON_TMON_THRESH1_CTRL,0x3ff,0)
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_MASK            0x03ff
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_ALIGN           0
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_BITS            10
#define MISC_PVTMON_TMON_THRESH1_CTRL_TMON_THRESH1_SHIFT           0


/****************************************************************************
 * MISC :: pvtmon_tmon_thresh2_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_tmon_thresh2_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_TMON_THRESH2_CTRL_RESERVED0_MASK               0xf000
#define MISC_PVTMON_TMON_THRESH2_CTRL_RESERVED0_ALIGN              0
#define MISC_PVTMON_TMON_THRESH2_CTRL_RESERVED0_BITS               4
#define MISC_PVTMON_TMON_THRESH2_CTRL_RESERVED0_SHIFT              12

/* MISC :: pvtmon_tmon_thresh2_ctrl :: tmon_thresh2_reset_en [11:11] */
#define Wr_MISC_pvtmon_tmon_thresh2_ctrl_tmon_thresh2_reset_en(x) WriteRegBits16(MISC_PVTMON_TMON_THRESH2_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_tmon_thresh2_ctrl_tmon_thresh2_reset_en(x) ReadRegBits16(MISC_PVTMON_TMON_THRESH2_CTRL,0x800,11)
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_RESET_EN_MASK   0x0800
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_RESET_EN_ALIGN  0
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_RESET_EN_BITS   1
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_RESET_EN_SHIFT  11

/* MISC :: pvtmon_tmon_thresh2_ctrl :: tmon_thresh2_intr_en [10:10] */
#define Wr_MISC_pvtmon_tmon_thresh2_ctrl_tmon_thresh2_intr_en(x) WriteRegBits16(MISC_PVTMON_TMON_THRESH2_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_tmon_thresh2_ctrl_tmon_thresh2_intr_en(x) ReadRegBits16(MISC_PVTMON_TMON_THRESH2_CTRL,0x400,10)
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_INTR_EN_MASK    0x0400
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_INTR_EN_ALIGN   0
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_INTR_EN_BITS    1
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_INTR_EN_SHIFT   10

/* MISC :: pvtmon_tmon_thresh2_ctrl :: tmon_thresh2 [09:00] */
#define Wr_MISC_pvtmon_tmon_thresh2_ctrl_tmon_thresh2(x) WriteRegBits16(MISC_PVTMON_TMON_THRESH2_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_tmon_thresh2_ctrl_tmon_thresh2(x) ReadRegBits16(MISC_PVTMON_TMON_THRESH2_CTRL,0x3ff,0)
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_MASK            0x03ff
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_ALIGN           0
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_BITS            10
#define MISC_PVTMON_TMON_THRESH2_CTRL_TMON_THRESH2_SHIFT           0


/****************************************************************************
 * MISC :: pvtmon_vmon_1v_h_thresh1_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1v_h_thresh1_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_RESERVED0_MASK          0xf000
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_RESERVED0_ALIGN         0
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_RESERVED0_BITS          4
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_RESERVED0_SHIFT         12

/* MISC :: pvtmon_vmon_1v_h_thresh1_ctrl :: vmon_1v_h_thresh1_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_1v_h_thresh1_ctrl_vmon_1v_h_thresh1_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_1V_H_THRESH1_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_1v_h_thresh1_ctrl_vmon_1v_h_thresh1_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_1V_H_THRESH1_CTRL,0x800,11)
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_1v_h_thresh1_ctrl :: vmon_1v_h_thresh1_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_1v_h_thresh1_ctrl_vmon_1v_h_thresh1_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_1V_H_THRESH1_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_1v_h_thresh1_ctrl_vmon_1v_h_thresh1_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_1V_H_THRESH1_CTRL,0x400,10)
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_1v_h_thresh1_ctrl :: vmon_1v_h_thresh1 [09:00] */
#define Wr_MISC_pvtmon_vmon_1v_h_thresh1_ctrl_vmon_1v_h_thresh1(x) WriteRegBits16(MISC_PVTMON_VMON_1V_H_THRESH1_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1v_h_thresh1_ctrl_vmon_1v_h_thresh1(x) ReadRegBits16(MISC_PVTMON_VMON_1V_H_THRESH1_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_MASK  0x03ff
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_ALIGN 0
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_BITS  10
#define MISC_PVTMON_VMON_1V_H_THRESH1_CTRL_VMON_1V_H_THRESH1_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_1v_h_thresh2_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1v_h_thresh2_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_RESERVED0_MASK          0xf000
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_RESERVED0_ALIGN         0
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_RESERVED0_BITS          4
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_RESERVED0_SHIFT         12

/* MISC :: pvtmon_vmon_1v_h_thresh2_ctrl :: vmon_1v_h_thresh2_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_1v_h_thresh2_ctrl_vmon_1v_h_thresh2_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_1V_H_THRESH2_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_1v_h_thresh2_ctrl_vmon_1v_h_thresh2_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_1V_H_THRESH2_CTRL,0x800,11)
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_1v_h_thresh2_ctrl :: vmon_1v_h_thresh2_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_1v_h_thresh2_ctrl_vmon_1v_h_thresh2_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_1V_H_THRESH2_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_1v_h_thresh2_ctrl_vmon_1v_h_thresh2_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_1V_H_THRESH2_CTRL,0x400,10)
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_1v_h_thresh2_ctrl :: vmon_1v_h_thresh2 [09:00] */
#define Wr_MISC_pvtmon_vmon_1v_h_thresh2_ctrl_vmon_1v_h_thresh2(x) WriteRegBits16(MISC_PVTMON_VMON_1V_H_THRESH2_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1v_h_thresh2_ctrl_vmon_1v_h_thresh2(x) ReadRegBits16(MISC_PVTMON_VMON_1V_H_THRESH2_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_MASK  0x03ff
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_ALIGN 0
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_BITS  10
#define MISC_PVTMON_VMON_1V_H_THRESH2_CTRL_VMON_1V_H_THRESH2_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_1v_l_thresh1_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1v_l_thresh1_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_RESERVED0_MASK          0xf000
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_RESERVED0_ALIGN         0
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_RESERVED0_BITS          4
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_RESERVED0_SHIFT         12

/* MISC :: pvtmon_vmon_1v_l_thresh1_ctrl :: vmon_1v_l_thresh1_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_1v_l_thresh1_ctrl_vmon_1v_l_thresh1_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_1V_L_THRESH1_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_1v_l_thresh1_ctrl_vmon_1v_l_thresh1_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_1V_L_THRESH1_CTRL,0x800,11)
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_1v_l_thresh1_ctrl :: vmon_1v_l_thresh1_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_1v_l_thresh1_ctrl_vmon_1v_l_thresh1_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_1V_L_THRESH1_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_1v_l_thresh1_ctrl_vmon_1v_l_thresh1_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_1V_L_THRESH1_CTRL,0x400,10)
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_1v_l_thresh1_ctrl :: vmon_1v_l_thresh1 [09:00] */
#define Wr_MISC_pvtmon_vmon_1v_l_thresh1_ctrl_vmon_1v_l_thresh1(x) WriteRegBits16(MISC_PVTMON_VMON_1V_L_THRESH1_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1v_l_thresh1_ctrl_vmon_1v_l_thresh1(x) ReadRegBits16(MISC_PVTMON_VMON_1V_L_THRESH1_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_MASK  0x03ff
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_ALIGN 0
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_BITS  10
#define MISC_PVTMON_VMON_1V_L_THRESH1_CTRL_VMON_1V_L_THRESH1_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_1v_l_thresh2_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1v_l_thresh2_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_RESERVED0_MASK          0xf000
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_RESERVED0_ALIGN         0
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_RESERVED0_BITS          4
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_RESERVED0_SHIFT         12

/* MISC :: pvtmon_vmon_1v_l_thresh2_ctrl :: vmon_1v_l_thresh2_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_1v_l_thresh2_ctrl_vmon_1v_l_thresh2_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_1V_L_THRESH2_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_1v_l_thresh2_ctrl_vmon_1v_l_thresh2_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_1V_L_THRESH2_CTRL,0x800,11)
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_1v_l_thresh2_ctrl :: vmon_1v_l_thresh2_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_1v_l_thresh2_ctrl_vmon_1v_l_thresh2_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_1V_L_THRESH2_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_1v_l_thresh2_ctrl_vmon_1v_l_thresh2_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_1V_L_THRESH2_CTRL,0x400,10)
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_1v_l_thresh2_ctrl :: vmon_1v_l_thresh2 [09:00] */
#define Wr_MISC_pvtmon_vmon_1v_l_thresh2_ctrl_vmon_1v_l_thresh2(x) WriteRegBits16(MISC_PVTMON_VMON_1V_L_THRESH2_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1v_l_thresh2_ctrl_vmon_1v_l_thresh2(x) ReadRegBits16(MISC_PVTMON_VMON_1V_L_THRESH2_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_MASK  0x03ff
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_ALIGN 0
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_BITS  10
#define MISC_PVTMON_VMON_1V_L_THRESH2_CTRL_VMON_1V_L_THRESH2_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_1p8v_h_thresh1_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1p8v_h_thresh1_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_RESERVED0_MASK        0xf000
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_RESERVED0_ALIGN       0
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_RESERVED0_BITS        4
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_RESERVED0_SHIFT       12

/* MISC :: pvtmon_vmon_1p8v_h_thresh1_ctrl :: vmon_1p8v_h_thresh1_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_1p8v_h_thresh1_ctrl_vmon_1p8v_h_thresh1_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_1p8v_h_thresh1_ctrl_vmon_1p8v_h_thresh1_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL,0x800,11)
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_1p8v_h_thresh1_ctrl :: vmon_1p8v_h_thresh1_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_1p8v_h_thresh1_ctrl_vmon_1p8v_h_thresh1_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_1p8v_h_thresh1_ctrl_vmon_1p8v_h_thresh1_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL,0x400,10)
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_1p8v_h_thresh1_ctrl :: vmon_1p8v_h_thresh1 [09:00] */
#define Wr_MISC_pvtmon_vmon_1p8v_h_thresh1_ctrl_vmon_1p8v_h_thresh1(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1p8v_h_thresh1_ctrl_vmon_1p8v_h_thresh1(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_MASK 0x03ff
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_BITS 10
#define MISC_PVTMON_VMON_1P8V_H_THRESH1_CTRL_VMON_1P8V_H_THRESH1_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_1p8v_h_thresh2_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1p8v_h_thresh2_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_RESERVED0_MASK        0xf000
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_RESERVED0_ALIGN       0
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_RESERVED0_BITS        4
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_RESERVED0_SHIFT       12

/* MISC :: pvtmon_vmon_1p8v_h_thresh2_ctrl :: vmon_1p8v_h_thresh2_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_1p8v_h_thresh2_ctrl_vmon_1p8v_h_thresh2_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_1p8v_h_thresh2_ctrl_vmon_1p8v_h_thresh2_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL,0x800,11)
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_1p8v_h_thresh2_ctrl :: vmon_1p8v_h_thresh2_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_1p8v_h_thresh2_ctrl_vmon_1p8v_h_thresh2_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_1p8v_h_thresh2_ctrl_vmon_1p8v_h_thresh2_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL,0x400,10)
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_1p8v_h_thresh2_ctrl :: vmon_1p8v_h_thresh2 [09:00] */
#define Wr_MISC_pvtmon_vmon_1p8v_h_thresh2_ctrl_vmon_1p8v_h_thresh2(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1p8v_h_thresh2_ctrl_vmon_1p8v_h_thresh2(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_MASK 0x03ff
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_BITS 10
#define MISC_PVTMON_VMON_1P8V_H_THRESH2_CTRL_VMON_1P8V_H_THRESH2_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_1p8v_l_thresh1_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1p8v_l_thresh1_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_RESERVED0_MASK        0xf000
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_RESERVED0_ALIGN       0
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_RESERVED0_BITS        4
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_RESERVED0_SHIFT       12

/* MISC :: pvtmon_vmon_1p8v_l_thresh1_ctrl :: vmon_1p8v_l_thresh1_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_1p8v_l_thresh1_ctrl_vmon_1p8v_l_thresh1_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_1p8v_l_thresh1_ctrl_vmon_1p8v_l_thresh1_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL,0x800,11)
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_1p8v_l_thresh1_ctrl :: vmon_1p8v_l_thresh1_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_1p8v_l_thresh1_ctrl_vmon_1p8v_l_thresh1_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_1p8v_l_thresh1_ctrl_vmon_1p8v_l_thresh1_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL,0x400,10)
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_1p8v_l_thresh1_ctrl :: vmon_1p8v_l_thresh1 [09:00] */
#define Wr_MISC_pvtmon_vmon_1p8v_l_thresh1_ctrl_vmon_1p8v_l_thresh1(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1p8v_l_thresh1_ctrl_vmon_1p8v_l_thresh1(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_MASK 0x03ff
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_BITS 10
#define MISC_PVTMON_VMON_1P8V_L_THRESH1_CTRL_VMON_1P8V_L_THRESH1_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_1p8v_l_thresh2_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1p8v_l_thresh2_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_RESERVED0_MASK        0xf000
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_RESERVED0_ALIGN       0
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_RESERVED0_BITS        4
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_RESERVED0_SHIFT       12

/* MISC :: pvtmon_vmon_1p8v_l_thresh2_ctrl :: vmon_1p8v_l_thresh2_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_1p8v_l_thresh2_ctrl_vmon_1p8v_l_thresh2_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_1p8v_l_thresh2_ctrl_vmon_1p8v_l_thresh2_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL,0x800,11)
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_1p8v_l_thresh2_ctrl :: vmon_1p8v_l_thresh2_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_1p8v_l_thresh2_ctrl_vmon_1p8v_l_thresh2_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_1p8v_l_thresh2_ctrl_vmon_1p8v_l_thresh2_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL,0x400,10)
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_1p8v_l_thresh2_ctrl :: vmon_1p8v_l_thresh2 [09:00] */
#define Wr_MISC_pvtmon_vmon_1p8v_l_thresh2_ctrl_vmon_1p8v_l_thresh2(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1p8v_l_thresh2_ctrl_vmon_1p8v_l_thresh2(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_MASK 0x03ff
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_ALIGN 0
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_BITS 10
#define MISC_PVTMON_VMON_1P8V_L_THRESH2_CTRL_VMON_1P8V_L_THRESH2_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_3p3v_h_thresh1_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_3p3v_h_thresh1_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_RESERVED0_MASK        0xf000
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_RESERVED0_ALIGN       0
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_RESERVED0_BITS        4
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_RESERVED0_SHIFT       12

/* MISC :: pvtmon_vmon_3p3v_h_thresh1_ctrl :: vmon_3p3v_h_thresh1_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_3p3v_h_thresh1_ctrl_vmon_3p3v_h_thresh1_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_3p3v_h_thresh1_ctrl_vmon_3p3v_h_thresh1_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL,0x800,11)
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_3p3v_h_thresh1_ctrl :: vmon_3p3v_h_thresh1_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_3p3v_h_thresh1_ctrl_vmon_3p3v_h_thresh1_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_3p3v_h_thresh1_ctrl_vmon_3p3v_h_thresh1_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL,0x400,10)
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_3p3v_h_thresh1_ctrl :: vmon_3p3v_h_thresh1 [09:00] */
#define Wr_MISC_pvtmon_vmon_3p3v_h_thresh1_ctrl_vmon_3p3v_h_thresh1(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_3p3v_h_thresh1_ctrl_vmon_3p3v_h_thresh1(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_MASK 0x03ff
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_BITS 10
#define MISC_PVTMON_VMON_3P3V_H_THRESH1_CTRL_VMON_3P3V_H_THRESH1_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_3p3v_h_thresh2_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_3p3v_h_thresh2_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_RESERVED0_MASK        0xf000
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_RESERVED0_ALIGN       0
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_RESERVED0_BITS        4
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_RESERVED0_SHIFT       12

/* MISC :: pvtmon_vmon_3p3v_h_thresh2_ctrl :: vmon_3p3v_h_thresh2_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_3p3v_h_thresh2_ctrl_vmon_3p3v_h_thresh2_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_3p3v_h_thresh2_ctrl_vmon_3p3v_h_thresh2_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL,0x800,11)
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_3p3v_h_thresh2_ctrl :: vmon_3p3v_h_thresh2_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_3p3v_h_thresh2_ctrl_vmon_3p3v_h_thresh2_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_3p3v_h_thresh2_ctrl_vmon_3p3v_h_thresh2_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL,0x400,10)
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_3p3v_h_thresh2_ctrl :: vmon_3p3v_h_thresh2 [09:00] */
#define Wr_MISC_pvtmon_vmon_3p3v_h_thresh2_ctrl_vmon_3p3v_h_thresh2(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_3p3v_h_thresh2_ctrl_vmon_3p3v_h_thresh2(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_MASK 0x03ff
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_BITS 10
#define MISC_PVTMON_VMON_3P3V_H_THRESH2_CTRL_VMON_3P3V_H_THRESH2_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_3p3v_l_thresh1_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_3p3v_l_thresh1_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_RESERVED0_MASK        0xf000
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_RESERVED0_ALIGN       0
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_RESERVED0_BITS        4
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_RESERVED0_SHIFT       12

/* MISC :: pvtmon_vmon_3p3v_l_thresh1_ctrl :: vmon_3p3v_l_thresh1_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_3p3v_l_thresh1_ctrl_vmon_3p3v_l_thresh1_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_3p3v_l_thresh1_ctrl_vmon_3p3v_l_thresh1_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL,0x800,11)
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_3p3v_l_thresh1_ctrl :: vmon_3p3v_l_thresh1_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_3p3v_l_thresh1_ctrl_vmon_3p3v_l_thresh1_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_3p3v_l_thresh1_ctrl_vmon_3p3v_l_thresh1_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL,0x400,10)
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_3p3v_l_thresh1_ctrl :: vmon_3p3v_l_thresh1 [09:00] */
#define Wr_MISC_pvtmon_vmon_3p3v_l_thresh1_ctrl_vmon_3p3v_l_thresh1(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_3p3v_l_thresh1_ctrl_vmon_3p3v_l_thresh1(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_MASK 0x03ff
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_BITS 10
#define MISC_PVTMON_VMON_3P3V_L_THRESH1_CTRL_VMON_3P3V_L_THRESH1_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_vmon_3p3v_l_thresh2_ctrl
 ***************************************************************************/
/* MISC :: pvtmon_vmon_3p3v_l_thresh2_ctrl :: reserved0 [15:12] */
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_RESERVED0_MASK        0xf000
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_RESERVED0_ALIGN       0
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_RESERVED0_BITS        4
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_RESERVED0_SHIFT       12

/* MISC :: pvtmon_vmon_3p3v_l_thresh2_ctrl :: vmon_3p3v_l_thresh2_reset_en [11:11] */
#define Wr_MISC_pvtmon_vmon_3p3v_l_thresh2_ctrl_vmon_3p3v_l_thresh2_reset_en(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL,0x800,11,x)
#define Rd_MISC_pvtmon_vmon_3p3v_l_thresh2_ctrl_vmon_3p3v_l_thresh2_reset_en(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL,0x800,11)
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_RESET_EN_MASK 0x0800
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_RESET_EN_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_RESET_EN_BITS 1
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_RESET_EN_SHIFT 11

/* MISC :: pvtmon_vmon_3p3v_l_thresh2_ctrl :: vmon_3p3v_l_thresh2_intr_en [10:10] */
#define Wr_MISC_pvtmon_vmon_3p3v_l_thresh2_ctrl_vmon_3p3v_l_thresh2_intr_en(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL,0x400,10,x)
#define Rd_MISC_pvtmon_vmon_3p3v_l_thresh2_ctrl_vmon_3p3v_l_thresh2_intr_en(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL,0x400,10)
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_INTR_EN_MASK 0x0400
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_INTR_EN_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_INTR_EN_BITS 1
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_INTR_EN_SHIFT 10

/* MISC :: pvtmon_vmon_3p3v_l_thresh2_ctrl :: vmon_3p3v_l_thresh2 [09:00] */
#define Wr_MISC_pvtmon_vmon_3p3v_l_thresh2_ctrl_vmon_3p3v_l_thresh2(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_3p3v_l_thresh2_ctrl_vmon_3p3v_l_thresh2(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL,0x3ff,0)
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_MASK 0x03ff
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_ALIGN 0
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_BITS 10
#define MISC_PVTMON_VMON_3P3V_L_THRESH2_CTRL_VMON_3P3V_L_THRESH2_SHIFT 0


/****************************************************************************
 * MISC :: pvtmon_threshold_filter
 ***************************************************************************/
/* MISC :: pvtmon_threshold_filter :: reserved0 [15:08] */
#define MISC_PVTMON_THRESHOLD_FILTER_RESERVED0_MASK                0xff00
#define MISC_PVTMON_THRESHOLD_FILTER_RESERVED0_ALIGN               0
#define MISC_PVTMON_THRESHOLD_FILTER_RESERVED0_BITS                8
#define MISC_PVTMON_THRESHOLD_FILTER_RESERVED0_SHIFT               8

/* MISC :: pvtmon_threshold_filter :: threshold_filter [07:00] */
#define Wr_MISC_pvtmon_threshold_filter_threshold_filter(x) WriteRegBits16(MISC_PVTMON_THRESHOLD_FILTER,0xff,0,x)
#define Rd_MISC_pvtmon_threshold_filter_threshold_filter(x) ReadRegBits16(MISC_PVTMON_THRESHOLD_FILTER,0xff,0)
#define MISC_PVTMON_THRESHOLD_FILTER_THRESHOLD_FILTER_MASK         0x00ff
#define MISC_PVTMON_THRESHOLD_FILTER_THRESHOLD_FILTER_ALIGN        0
#define MISC_PVTMON_THRESHOLD_FILTER_THRESHOLD_FILTER_BITS         8
#define MISC_PVTMON_THRESHOLD_FILTER_THRESHOLD_FILTER_SHIFT        0


/****************************************************************************
 * MISC :: pvtmon_viol_rawsts
 ***************************************************************************/
/* MISC :: pvtmon_viol_rawsts :: reserved0 [15:14] */
#define MISC_PVTMON_VIOL_RAWSTS_RESERVED0_MASK                     0xc000
#define MISC_PVTMON_VIOL_RAWSTS_RESERVED0_ALIGN                    0
#define MISC_PVTMON_VIOL_RAWSTS_RESERVED0_BITS                     2
#define MISC_PVTMON_VIOL_RAWSTS_RESERVED0_SHIFT                    14

/* MISC :: pvtmon_viol_rawsts :: vmon_3p3v_l_thresh2_viol [13:13] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_3p3v_l_thresh2_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x2000,13,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_3p3v_l_thresh2_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x2000,13)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_L_THRESH2_VIOL_MASK      0x2000
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_L_THRESH2_VIOL_ALIGN     0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_L_THRESH2_VIOL_BITS      1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_L_THRESH2_VIOL_SHIFT     13

/* MISC :: pvtmon_viol_rawsts :: vmon_3p3v_l_thresh1_viol [12:12] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_3p3v_l_thresh1_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x1000,12,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_3p3v_l_thresh1_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x1000,12)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_L_THRESH1_VIOL_MASK      0x1000
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_L_THRESH1_VIOL_ALIGN     0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_L_THRESH1_VIOL_BITS      1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_L_THRESH1_VIOL_SHIFT     12

/* MISC :: pvtmon_viol_rawsts :: vmon_3p3v_h_thresh2_viol [11:11] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_3p3v_h_thresh2_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x800,11,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_3p3v_h_thresh2_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x800,11)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_H_THRESH2_VIOL_MASK      0x0800
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_H_THRESH2_VIOL_ALIGN     0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_H_THRESH2_VIOL_BITS      1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_H_THRESH2_VIOL_SHIFT     11

/* MISC :: pvtmon_viol_rawsts :: vmon_3p3v_h_thresh1_viol [10:10] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_3p3v_h_thresh1_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x400,10,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_3p3v_h_thresh1_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x400,10)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_H_THRESH1_VIOL_MASK      0x0400
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_H_THRESH1_VIOL_ALIGN     0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_H_THRESH1_VIOL_BITS      1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_3P3V_H_THRESH1_VIOL_SHIFT     10

/* MISC :: pvtmon_viol_rawsts :: vmon_1p8v_l_thresh2_viol [09:09] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_1p8v_l_thresh2_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x200,9,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_1p8v_l_thresh2_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x200,9)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_L_THRESH2_VIOL_MASK      0x0200
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_L_THRESH2_VIOL_ALIGN     0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_L_THRESH2_VIOL_BITS      1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_L_THRESH2_VIOL_SHIFT     9

/* MISC :: pvtmon_viol_rawsts :: vmon_1p8v_l_thresh1_viol [08:08] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_1p8v_l_thresh1_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x100,8,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_1p8v_l_thresh1_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x100,8)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_L_THRESH1_VIOL_MASK      0x0100
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_L_THRESH1_VIOL_ALIGN     0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_L_THRESH1_VIOL_BITS      1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_L_THRESH1_VIOL_SHIFT     8

/* MISC :: pvtmon_viol_rawsts :: vmon_1p8v_h_thresh2_viol [07:07] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_1p8v_h_thresh2_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x80,7,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_1p8v_h_thresh2_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x80,7)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_H_THRESH2_VIOL_MASK      0x0080
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_H_THRESH2_VIOL_ALIGN     0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_H_THRESH2_VIOL_BITS      1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_H_THRESH2_VIOL_SHIFT     7

/* MISC :: pvtmon_viol_rawsts :: vmon_1p8v_h_thresh1_viol [06:06] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_1p8v_h_thresh1_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x40,6,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_1p8v_h_thresh1_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x40,6)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_H_THRESH1_VIOL_MASK      0x0040
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_H_THRESH1_VIOL_ALIGN     0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_H_THRESH1_VIOL_BITS      1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1P8V_H_THRESH1_VIOL_SHIFT     6

/* MISC :: pvtmon_viol_rawsts :: vmon_1v_l_thresh2_viol [05:05] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_1v_l_thresh2_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x20,5,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_1v_l_thresh2_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x20,5)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_L_THRESH2_VIOL_MASK        0x0020
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_L_THRESH2_VIOL_ALIGN       0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_L_THRESH2_VIOL_BITS        1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_L_THRESH2_VIOL_SHIFT       5

/* MISC :: pvtmon_viol_rawsts :: vmon_1v_l_thresh1_viol [04:04] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_1v_l_thresh1_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x10,4,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_1v_l_thresh1_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x10,4)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_L_THRESH1_VIOL_MASK        0x0010
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_L_THRESH1_VIOL_ALIGN       0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_L_THRESH1_VIOL_BITS        1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_L_THRESH1_VIOL_SHIFT       4

/* MISC :: pvtmon_viol_rawsts :: vmon_1v_h_thresh2_viol [03:03] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_1v_h_thresh2_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x8,3,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_1v_h_thresh2_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x8,3)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_H_THRESH2_VIOL_MASK        0x0008
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_H_THRESH2_VIOL_ALIGN       0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_H_THRESH2_VIOL_BITS        1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_H_THRESH2_VIOL_SHIFT       3

/* MISC :: pvtmon_viol_rawsts :: vmon_1v_h_thresh1_viol [02:02] */
#define Wr_MISC_pvtmon_viol_rawsts_vmon_1v_h_thresh1_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x4,2,x)
#define Rd_MISC_pvtmon_viol_rawsts_vmon_1v_h_thresh1_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x4,2)
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_H_THRESH1_VIOL_MASK        0x0004
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_H_THRESH1_VIOL_ALIGN       0
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_H_THRESH1_VIOL_BITS        1
#define MISC_PVTMON_VIOL_RAWSTS_VMON_1V_H_THRESH1_VIOL_SHIFT       2

/* MISC :: pvtmon_viol_rawsts :: tmon_thresh2_viol [01:01] */
#define Wr_MISC_pvtmon_viol_rawsts_tmon_thresh2_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x2,1,x)
#define Rd_MISC_pvtmon_viol_rawsts_tmon_thresh2_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x2,1)
#define MISC_PVTMON_VIOL_RAWSTS_TMON_THRESH2_VIOL_MASK             0x0002
#define MISC_PVTMON_VIOL_RAWSTS_TMON_THRESH2_VIOL_ALIGN            0
#define MISC_PVTMON_VIOL_RAWSTS_TMON_THRESH2_VIOL_BITS             1
#define MISC_PVTMON_VIOL_RAWSTS_TMON_THRESH2_VIOL_SHIFT            1

/* MISC :: pvtmon_viol_rawsts :: tmon_thresh1_viol [00:00] */
#define Wr_MISC_pvtmon_viol_rawsts_tmon_thresh1_viol(x) WriteRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x1,0,x)
#define Rd_MISC_pvtmon_viol_rawsts_tmon_thresh1_viol(x) ReadRegBits16(MISC_PVTMON_VIOL_RAWSTS,0x1,0)
#define MISC_PVTMON_VIOL_RAWSTS_TMON_THRESH1_VIOL_MASK             0x0001
#define MISC_PVTMON_VIOL_RAWSTS_TMON_THRESH1_VIOL_ALIGN            0
#define MISC_PVTMON_VIOL_RAWSTS_TMON_THRESH1_VIOL_BITS             1
#define MISC_PVTMON_VIOL_RAWSTS_TMON_THRESH1_VIOL_SHIFT            0


/****************************************************************************
 * MISC :: pvtmon_intr_status
 ***************************************************************************/
/* MISC :: pvtmon_intr_status :: reserved0 [15:14] */
#define MISC_PVTMON_INTR_STATUS_RESERVED0_MASK                     0xc000
#define MISC_PVTMON_INTR_STATUS_RESERVED0_ALIGN                    0
#define MISC_PVTMON_INTR_STATUS_RESERVED0_BITS                     2
#define MISC_PVTMON_INTR_STATUS_RESERVED0_SHIFT                    14

/* MISC :: pvtmon_intr_status :: vmon_3p3v_l_thresh2_intr [13:13] */
#define Wr_MISC_pvtmon_intr_status_vmon_3p3v_l_thresh2_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x2000,13,x)
#define Rd_MISC_pvtmon_intr_status_vmon_3p3v_l_thresh2_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x2000,13)
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_L_THRESH2_INTR_MASK      0x2000
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_L_THRESH2_INTR_ALIGN     0
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_L_THRESH2_INTR_BITS      1
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_L_THRESH2_INTR_SHIFT     13

/* MISC :: pvtmon_intr_status :: vmon_3p3v_l_thresh1_intr [12:12] */
#define Wr_MISC_pvtmon_intr_status_vmon_3p3v_l_thresh1_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x1000,12,x)
#define Rd_MISC_pvtmon_intr_status_vmon_3p3v_l_thresh1_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x1000,12)
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_L_THRESH1_INTR_MASK      0x1000
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_L_THRESH1_INTR_ALIGN     0
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_L_THRESH1_INTR_BITS      1
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_L_THRESH1_INTR_SHIFT     12

/* MISC :: pvtmon_intr_status :: vmon_3p3v_h_thresh2_intr [11:11] */
#define Wr_MISC_pvtmon_intr_status_vmon_3p3v_h_thresh2_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x800,11,x)
#define Rd_MISC_pvtmon_intr_status_vmon_3p3v_h_thresh2_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x800,11)
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_H_THRESH2_INTR_MASK      0x0800
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_H_THRESH2_INTR_ALIGN     0
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_H_THRESH2_INTR_BITS      1
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_H_THRESH2_INTR_SHIFT     11

/* MISC :: pvtmon_intr_status :: vmon_3p3v_h_thresh1_intr [10:10] */
#define Wr_MISC_pvtmon_intr_status_vmon_3p3v_h_thresh1_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x400,10,x)
#define Rd_MISC_pvtmon_intr_status_vmon_3p3v_h_thresh1_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x400,10)
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_H_THRESH1_INTR_MASK      0x0400
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_H_THRESH1_INTR_ALIGN     0
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_H_THRESH1_INTR_BITS      1
#define MISC_PVTMON_INTR_STATUS_VMON_3P3V_H_THRESH1_INTR_SHIFT     10

/* MISC :: pvtmon_intr_status :: vmon_1p8v_l_thresh2_intr [09:09] */
#define Wr_MISC_pvtmon_intr_status_vmon_1p8v_l_thresh2_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x200,9,x)
#define Rd_MISC_pvtmon_intr_status_vmon_1p8v_l_thresh2_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x200,9)
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_L_THRESH2_INTR_MASK      0x0200
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_L_THRESH2_INTR_ALIGN     0
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_L_THRESH2_INTR_BITS      1
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_L_THRESH2_INTR_SHIFT     9

/* MISC :: pvtmon_intr_status :: vmon_1p8v_l_thresh1_intr [08:08] */
#define Wr_MISC_pvtmon_intr_status_vmon_1p8v_l_thresh1_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x100,8,x)
#define Rd_MISC_pvtmon_intr_status_vmon_1p8v_l_thresh1_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x100,8)
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_L_THRESH1_INTR_MASK      0x0100
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_L_THRESH1_INTR_ALIGN     0
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_L_THRESH1_INTR_BITS      1
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_L_THRESH1_INTR_SHIFT     8

/* MISC :: pvtmon_intr_status :: vmon_1p8v_h_thresh2_intr [07:07] */
#define Wr_MISC_pvtmon_intr_status_vmon_1p8v_h_thresh2_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x80,7,x)
#define Rd_MISC_pvtmon_intr_status_vmon_1p8v_h_thresh2_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x80,7)
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_H_THRESH2_INTR_MASK      0x0080
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_H_THRESH2_INTR_ALIGN     0
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_H_THRESH2_INTR_BITS      1
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_H_THRESH2_INTR_SHIFT     7

/* MISC :: pvtmon_intr_status :: vmon_1p8v_h_thresh1_intr [06:06] */
#define Wr_MISC_pvtmon_intr_status_vmon_1p8v_h_thresh1_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x40,6,x)
#define Rd_MISC_pvtmon_intr_status_vmon_1p8v_h_thresh1_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x40,6)
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_H_THRESH1_INTR_MASK      0x0040
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_H_THRESH1_INTR_ALIGN     0
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_H_THRESH1_INTR_BITS      1
#define MISC_PVTMON_INTR_STATUS_VMON_1P8V_H_THRESH1_INTR_SHIFT     6

/* MISC :: pvtmon_intr_status :: vmon_1v_l_thresh2_intr [05:05] */
#define Wr_MISC_pvtmon_intr_status_vmon_1v_l_thresh2_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x20,5,x)
#define Rd_MISC_pvtmon_intr_status_vmon_1v_l_thresh2_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x20,5)
#define MISC_PVTMON_INTR_STATUS_VMON_1V_L_THRESH2_INTR_MASK        0x0020
#define MISC_PVTMON_INTR_STATUS_VMON_1V_L_THRESH2_INTR_ALIGN       0
#define MISC_PVTMON_INTR_STATUS_VMON_1V_L_THRESH2_INTR_BITS        1
#define MISC_PVTMON_INTR_STATUS_VMON_1V_L_THRESH2_INTR_SHIFT       5

/* MISC :: pvtmon_intr_status :: vmon_1v_l_thresh1_intr [04:04] */
#define Wr_MISC_pvtmon_intr_status_vmon_1v_l_thresh1_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x10,4,x)
#define Rd_MISC_pvtmon_intr_status_vmon_1v_l_thresh1_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x10,4)
#define MISC_PVTMON_INTR_STATUS_VMON_1V_L_THRESH1_INTR_MASK        0x0010
#define MISC_PVTMON_INTR_STATUS_VMON_1V_L_THRESH1_INTR_ALIGN       0
#define MISC_PVTMON_INTR_STATUS_VMON_1V_L_THRESH1_INTR_BITS        1
#define MISC_PVTMON_INTR_STATUS_VMON_1V_L_THRESH1_INTR_SHIFT       4

/* MISC :: pvtmon_intr_status :: vmon_1v_h_thresh2_intr [03:03] */
#define Wr_MISC_pvtmon_intr_status_vmon_1v_h_thresh2_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x8,3,x)
#define Rd_MISC_pvtmon_intr_status_vmon_1v_h_thresh2_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x8,3)
#define MISC_PVTMON_INTR_STATUS_VMON_1V_H_THRESH2_INTR_MASK        0x0008
#define MISC_PVTMON_INTR_STATUS_VMON_1V_H_THRESH2_INTR_ALIGN       0
#define MISC_PVTMON_INTR_STATUS_VMON_1V_H_THRESH2_INTR_BITS        1
#define MISC_PVTMON_INTR_STATUS_VMON_1V_H_THRESH2_INTR_SHIFT       3

/* MISC :: pvtmon_intr_status :: vmon_1v_h_thresh1_intr [02:02] */
#define Wr_MISC_pvtmon_intr_status_vmon_1v_h_thresh1_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x4,2,x)
#define Rd_MISC_pvtmon_intr_status_vmon_1v_h_thresh1_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x4,2)
#define MISC_PVTMON_INTR_STATUS_VMON_1V_H_THRESH1_INTR_MASK        0x0004
#define MISC_PVTMON_INTR_STATUS_VMON_1V_H_THRESH1_INTR_ALIGN       0
#define MISC_PVTMON_INTR_STATUS_VMON_1V_H_THRESH1_INTR_BITS        1
#define MISC_PVTMON_INTR_STATUS_VMON_1V_H_THRESH1_INTR_SHIFT       2

/* MISC :: pvtmon_intr_status :: tmon_thresh2_intr [01:01] */
#define Wr_MISC_pvtmon_intr_status_tmon_thresh2_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x2,1,x)
#define Rd_MISC_pvtmon_intr_status_tmon_thresh2_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x2,1)
#define MISC_PVTMON_INTR_STATUS_TMON_THRESH2_INTR_MASK             0x0002
#define MISC_PVTMON_INTR_STATUS_TMON_THRESH2_INTR_ALIGN            0
#define MISC_PVTMON_INTR_STATUS_TMON_THRESH2_INTR_BITS             1
#define MISC_PVTMON_INTR_STATUS_TMON_THRESH2_INTR_SHIFT            1

/* MISC :: pvtmon_intr_status :: tmon_thresh1_intr [00:00] */
#define Wr_MISC_pvtmon_intr_status_tmon_thresh1_intr(x) WriteRegBits16(MISC_PVTMON_INTR_STATUS,0x1,0,x)
#define Rd_MISC_pvtmon_intr_status_tmon_thresh1_intr(x) ReadRegBits16(MISC_PVTMON_INTR_STATUS,0x1,0)
#define MISC_PVTMON_INTR_STATUS_TMON_THRESH1_INTR_MASK             0x0001
#define MISC_PVTMON_INTR_STATUS_TMON_THRESH1_INTR_ALIGN            0
#define MISC_PVTMON_INTR_STATUS_TMON_THRESH1_INTR_BITS             1
#define MISC_PVTMON_INTR_STATUS_TMON_THRESH1_INTR_SHIFT            0


/****************************************************************************
 * MISC :: pvtmon_intsts_clear
 ***************************************************************************/
/* MISC :: pvtmon_intsts_clear :: reserved0 [15:14] */
#define MISC_PVTMON_INTSTS_CLEAR_RESERVED0_MASK                    0xc000
#define MISC_PVTMON_INTSTS_CLEAR_RESERVED0_ALIGN                   0
#define MISC_PVTMON_INTSTS_CLEAR_RESERVED0_BITS                    2
#define MISC_PVTMON_INTSTS_CLEAR_RESERVED0_SHIFT                   14

/* MISC :: pvtmon_intsts_clear :: vmon_3p3v_l_thresh2_intsts_clear [13:13] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_3p3v_l_thresh2_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x2000,13,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_3p3v_l_thresh2_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x2000,13)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_L_THRESH2_INTSTS_CLEAR_MASK 0x2000
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_L_THRESH2_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_L_THRESH2_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_L_THRESH2_INTSTS_CLEAR_SHIFT 13

/* MISC :: pvtmon_intsts_clear :: vmon_3p3v_l_thresh1_intsts_clear [12:12] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_3p3v_l_thresh1_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x1000,12,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_3p3v_l_thresh1_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x1000,12)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_L_THRESH1_INTSTS_CLEAR_MASK 0x1000
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_L_THRESH1_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_L_THRESH1_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_L_THRESH1_INTSTS_CLEAR_SHIFT 12

/* MISC :: pvtmon_intsts_clear :: vmon_3p3v_h_thresh2_intsts_clear [11:11] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_3p3v_h_thresh2_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x800,11,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_3p3v_h_thresh2_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x800,11)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_H_THRESH2_INTSTS_CLEAR_MASK 0x0800
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_H_THRESH2_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_H_THRESH2_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_H_THRESH2_INTSTS_CLEAR_SHIFT 11

/* MISC :: pvtmon_intsts_clear :: vmon_3p3v_h_thresh1_intsts_clear [10:10] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_3p3v_h_thresh1_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x400,10,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_3p3v_h_thresh1_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x400,10)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_H_THRESH1_INTSTS_CLEAR_MASK 0x0400
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_H_THRESH1_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_H_THRESH1_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_3P3V_H_THRESH1_INTSTS_CLEAR_SHIFT 10

/* MISC :: pvtmon_intsts_clear :: vmon_1p8v_l_thresh2_intsts_clear [09:09] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_1p8v_l_thresh2_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x200,9,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_1p8v_l_thresh2_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x200,9)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_L_THRESH2_INTSTS_CLEAR_MASK 0x0200
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_L_THRESH2_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_L_THRESH2_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_L_THRESH2_INTSTS_CLEAR_SHIFT 9

/* MISC :: pvtmon_intsts_clear :: vmon_1p8v_l_thresh1_intsts_clear [08:08] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_1p8v_l_thresh1_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x100,8,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_1p8v_l_thresh1_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x100,8)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_L_THRESH1_INTSTS_CLEAR_MASK 0x0100
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_L_THRESH1_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_L_THRESH1_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_L_THRESH1_INTSTS_CLEAR_SHIFT 8

/* MISC :: pvtmon_intsts_clear :: vmon_1p8v_h_thresh2_intsts_clear [07:07] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_1p8v_h_thresh2_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x80,7,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_1p8v_h_thresh2_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x80,7)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_H_THRESH2_INTSTS_CLEAR_MASK 0x0080
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_H_THRESH2_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_H_THRESH2_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_H_THRESH2_INTSTS_CLEAR_SHIFT 7

/* MISC :: pvtmon_intsts_clear :: vmon_1p8v_h_thresh1_intsts_clear [06:06] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_1p8v_h_thresh1_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x40,6,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_1p8v_h_thresh1_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x40,6)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_H_THRESH1_INTSTS_CLEAR_MASK 0x0040
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_H_THRESH1_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_H_THRESH1_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1P8V_H_THRESH1_INTSTS_CLEAR_SHIFT 6

/* MISC :: pvtmon_intsts_clear :: vmon_1v_l_thresh2_intsts_clear [05:05] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_1v_l_thresh2_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x20,5,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_1v_l_thresh2_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x20,5)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_L_THRESH2_INTSTS_CLEAR_MASK 0x0020
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_L_THRESH2_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_L_THRESH2_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_L_THRESH2_INTSTS_CLEAR_SHIFT 5

/* MISC :: pvtmon_intsts_clear :: vmon_1v_l_thresh1_intsts_clear [04:04] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_1v_l_thresh1_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x10,4,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_1v_l_thresh1_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x10,4)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_L_THRESH1_INTSTS_CLEAR_MASK 0x0010
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_L_THRESH1_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_L_THRESH1_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_L_THRESH1_INTSTS_CLEAR_SHIFT 4

/* MISC :: pvtmon_intsts_clear :: vmon_1v_h_thresh2_intsts_clear [03:03] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_1v_h_thresh2_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x8,3,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_1v_h_thresh2_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x8,3)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_H_THRESH2_INTSTS_CLEAR_MASK 0x0008
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_H_THRESH2_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_H_THRESH2_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_H_THRESH2_INTSTS_CLEAR_SHIFT 3

/* MISC :: pvtmon_intsts_clear :: vmon_1v_h_thresh1_intsts_clear [02:02] */
#define Wr_MISC_pvtmon_intsts_clear_vmon_1v_h_thresh1_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x4,2,x)
#define Rd_MISC_pvtmon_intsts_clear_vmon_1v_h_thresh1_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x4,2)
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_H_THRESH1_INTSTS_CLEAR_MASK 0x0004
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_H_THRESH1_INTSTS_CLEAR_ALIGN 0
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_H_THRESH1_INTSTS_CLEAR_BITS 1
#define MISC_PVTMON_INTSTS_CLEAR_VMON_1V_H_THRESH1_INTSTS_CLEAR_SHIFT 2

/* MISC :: pvtmon_intsts_clear :: tmon_thresh2_intsts_clear [01:01] */
#define Wr_MISC_pvtmon_intsts_clear_tmon_thresh2_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x2,1,x)
#define Rd_MISC_pvtmon_intsts_clear_tmon_thresh2_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x2,1)
#define MISC_PVTMON_INTSTS_CLEAR_TMON_THRESH2_INTSTS_CLEAR_MASK    0x0002
#define MISC_PVTMON_INTSTS_CLEAR_TMON_THRESH2_INTSTS_CLEAR_ALIGN   0
#define MISC_PVTMON_INTSTS_CLEAR_TMON_THRESH2_INTSTS_CLEAR_BITS    1
#define MISC_PVTMON_INTSTS_CLEAR_TMON_THRESH2_INTSTS_CLEAR_SHIFT   1

/* MISC :: pvtmon_intsts_clear :: tmon_thresh1_intsts_clear [00:00] */
#define Wr_MISC_pvtmon_intsts_clear_tmon_thresh1_intsts_clear(x) WriteRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x1,0,x)
#define Rd_MISC_pvtmon_intsts_clear_tmon_thresh1_intsts_clear(x) ReadRegBits16(MISC_PVTMON_INTSTS_CLEAR,0x1,0)
#define MISC_PVTMON_INTSTS_CLEAR_TMON_THRESH1_INTSTS_CLEAR_MASK    0x0001
#define MISC_PVTMON_INTSTS_CLEAR_TMON_THRESH1_INTSTS_CLEAR_ALIGN   0
#define MISC_PVTMON_INTSTS_CLEAR_TMON_THRESH1_INTSTS_CLEAR_BITS    1
#define MISC_PVTMON_INTSTS_CLEAR_TMON_THRESH1_INTSTS_CLEAR_SHIFT   0


/****************************************************************************
 * MISC :: pvtmon_interrupt_count
 ***************************************************************************/
/* MISC :: pvtmon_interrupt_count :: interrupt_count [15:00] */
#define Wr_MISC_pvtmon_interrupt_count_interrupt_count(x) WriteReg16(MISC_PVTMON_INTERRUPT_COUNT,x)
#define Rd_MISC_pvtmon_interrupt_count_interrupt_count(x) ReadReg16(MISC_PVTMON_INTERRUPT_COUNT)
#define MISC_PVTMON_INTERRUPT_COUNT_INTERRUPT_COUNT_MASK           0xffff
#define MISC_PVTMON_INTERRUPT_COUNT_INTERRUPT_COUNT_ALIGN          0
#define MISC_PVTMON_INTERRUPT_COUNT_INTERRUPT_COUNT_BITS           16
#define MISC_PVTMON_INTERRUPT_COUNT_INTERRUPT_COUNT_SHIFT          0


/****************************************************************************
 * MISC :: pvtmon_tmon_sample
 ***************************************************************************/
/* MISC :: pvtmon_tmon_sample :: reserved0 [15:10] */
#define MISC_PVTMON_TMON_SAMPLE_RESERVED0_MASK                     0xfc00
#define MISC_PVTMON_TMON_SAMPLE_RESERVED0_ALIGN                    0
#define MISC_PVTMON_TMON_SAMPLE_RESERVED0_BITS                     6
#define MISC_PVTMON_TMON_SAMPLE_RESERVED0_SHIFT                    10

/* MISC :: pvtmon_tmon_sample :: tmon_sample [09:00] */
#define Wr_MISC_pvtmon_tmon_sample_tmon_sample(x) WriteRegBits16(MISC_PVTMON_TMON_SAMPLE,0x3ff,0,x)
#define Rd_MISC_pvtmon_tmon_sample_tmon_sample(x) ReadRegBits16(MISC_PVTMON_TMON_SAMPLE,0x3ff,0)
#define MISC_PVTMON_TMON_SAMPLE_TMON_SAMPLE_MASK                   0x03ff
#define MISC_PVTMON_TMON_SAMPLE_TMON_SAMPLE_ALIGN                  0
#define MISC_PVTMON_TMON_SAMPLE_TMON_SAMPLE_BITS                   10
#define MISC_PVTMON_TMON_SAMPLE_TMON_SAMPLE_SHIFT                  0


/****************************************************************************
 * MISC :: pvtmon_vmon_1v_sample
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1v_sample :: reserved0 [15:10] */
#define MISC_PVTMON_VMON_1V_SAMPLE_RESERVED0_MASK                  0xfc00
#define MISC_PVTMON_VMON_1V_SAMPLE_RESERVED0_ALIGN                 0
#define MISC_PVTMON_VMON_1V_SAMPLE_RESERVED0_BITS                  6
#define MISC_PVTMON_VMON_1V_SAMPLE_RESERVED0_SHIFT                 10

/* MISC :: pvtmon_vmon_1v_sample :: vmon_1v_sample [09:00] */
#define Wr_MISC_pvtmon_vmon_1v_sample_vmon_1v_sample(x) WriteRegBits16(MISC_PVTMON_VMON_1V_SAMPLE,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1v_sample_vmon_1v_sample(x) ReadRegBits16(MISC_PVTMON_VMON_1V_SAMPLE,0x3ff,0)
#define MISC_PVTMON_VMON_1V_SAMPLE_VMON_1V_SAMPLE_MASK             0x03ff
#define MISC_PVTMON_VMON_1V_SAMPLE_VMON_1V_SAMPLE_ALIGN            0
#define MISC_PVTMON_VMON_1V_SAMPLE_VMON_1V_SAMPLE_BITS             10
#define MISC_PVTMON_VMON_1V_SAMPLE_VMON_1V_SAMPLE_SHIFT            0


/****************************************************************************
 * MISC :: pvtmon_vmon_1p8v_sample
 ***************************************************************************/
/* MISC :: pvtmon_vmon_1p8v_sample :: reserved0 [15:10] */
#define MISC_PVTMON_VMON_1P8V_SAMPLE_RESERVED0_MASK                0xfc00
#define MISC_PVTMON_VMON_1P8V_SAMPLE_RESERVED0_ALIGN               0
#define MISC_PVTMON_VMON_1P8V_SAMPLE_RESERVED0_BITS                6
#define MISC_PVTMON_VMON_1P8V_SAMPLE_RESERVED0_SHIFT               10

/* MISC :: pvtmon_vmon_1p8v_sample :: vmon_1p8v_sample [09:00] */
#define Wr_MISC_pvtmon_vmon_1p8v_sample_vmon_1p8v_sample(x) WriteRegBits16(MISC_PVTMON_VMON_1P8V_SAMPLE,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_1p8v_sample_vmon_1p8v_sample(x) ReadRegBits16(MISC_PVTMON_VMON_1P8V_SAMPLE,0x3ff,0)
#define MISC_PVTMON_VMON_1P8V_SAMPLE_VMON_1P8V_SAMPLE_MASK         0x03ff
#define MISC_PVTMON_VMON_1P8V_SAMPLE_VMON_1P8V_SAMPLE_ALIGN        0
#define MISC_PVTMON_VMON_1P8V_SAMPLE_VMON_1P8V_SAMPLE_BITS         10
#define MISC_PVTMON_VMON_1P8V_SAMPLE_VMON_1P8V_SAMPLE_SHIFT        0


/****************************************************************************
 * MISC :: pvtmon_vmon_3p3v_sample
 ***************************************************************************/
/* MISC :: pvtmon_vmon_3p3v_sample :: reserved0 [15:10] */
#define MISC_PVTMON_VMON_3P3V_SAMPLE_RESERVED0_MASK                0xfc00
#define MISC_PVTMON_VMON_3P3V_SAMPLE_RESERVED0_ALIGN               0
#define MISC_PVTMON_VMON_3P3V_SAMPLE_RESERVED0_BITS                6
#define MISC_PVTMON_VMON_3P3V_SAMPLE_RESERVED0_SHIFT               10

/* MISC :: pvtmon_vmon_3p3v_sample :: vmon_3p3v_sample [09:00] */
#define Wr_MISC_pvtmon_vmon_3p3v_sample_vmon_3p3v_sample(x) WriteRegBits16(MISC_PVTMON_VMON_3P3V_SAMPLE,0x3ff,0,x)
#define Rd_MISC_pvtmon_vmon_3p3v_sample_vmon_3p3v_sample(x) ReadRegBits16(MISC_PVTMON_VMON_3P3V_SAMPLE,0x3ff,0)
#define MISC_PVTMON_VMON_3P3V_SAMPLE_VMON_3P3V_SAMPLE_MASK         0x03ff
#define MISC_PVTMON_VMON_3P3V_SAMPLE_VMON_3P3V_SAMPLE_ALIGN        0
#define MISC_PVTMON_VMON_3P3V_SAMPLE_VMON_3P3V_SAMPLE_BITS         10
#define MISC_PVTMON_VMON_3P3V_SAMPLE_VMON_3P3V_SAMPLE_SHIFT        0


/****************************************************************************
 * MISC :: F1_Image_status
 ***************************************************************************/
/* MISC :: F1_Image_status :: firmware_executed [15:15] */
#define Wr_MISC_F1_Image_status_firmware_executed(x) WriteRegBits16(MISC_F1_IMAGE_STATUS,0x8000,15,x)
#define Rd_MISC_F1_Image_status_firmware_executed(x) ReadRegBits16(MISC_F1_IMAGE_STATUS,0x8000,15)
#define MISC_F1_IMAGE_STATUS_FIRMWARE_EXECUTED_MASK                0x8000
#define MISC_F1_IMAGE_STATUS_FIRMWARE_EXECUTED_ALIGN               0
#define MISC_F1_IMAGE_STATUS_FIRMWARE_EXECUTED_BITS                1
#define MISC_F1_IMAGE_STATUS_FIRMWARE_EXECUTED_SHIFT               15

/* MISC :: F1_Image_status :: bootrom_loaded [14:14] */
#define Wr_MISC_F1_Image_status_bootrom_loaded(x) WriteRegBits16(MISC_F1_IMAGE_STATUS,0x4000,14,x)
#define Rd_MISC_F1_Image_status_bootrom_loaded(x) ReadRegBits16(MISC_F1_IMAGE_STATUS,0x4000,14)
#define MISC_F1_IMAGE_STATUS_BOOTROM_LOADED_MASK                   0x4000
#define MISC_F1_IMAGE_STATUS_BOOTROM_LOADED_ALIGN                  0
#define MISC_F1_IMAGE_STATUS_BOOTROM_LOADED_BITS                   1
#define MISC_F1_IMAGE_STATUS_BOOTROM_LOADED_SHIFT                  14

/* MISC :: F1_Image_status :: spare [13:10] */
#define Wr_MISC_F1_Image_status_spare(x) WriteRegBits16(MISC_F1_IMAGE_STATUS,0x3c00,10,x)
#define Rd_MISC_F1_Image_status_spare(x) ReadRegBits16(MISC_F1_IMAGE_STATUS,0x3c00,10)
#define MISC_F1_IMAGE_STATUS_SPARE_MASK                            0x3c00
#define MISC_F1_IMAGE_STATUS_SPARE_ALIGN                           0
#define MISC_F1_IMAGE_STATUS_SPARE_BITS                            4
#define MISC_F1_IMAGE_STATUS_SPARE_SHIFT                           10

/* MISC :: F1_Image_status :: CRC_status [09:09] */
#define Wr_MISC_F1_Image_status_CRC_status(x) WriteRegBits16(MISC_F1_IMAGE_STATUS,0x200,9,x)
#define Rd_MISC_F1_Image_status_CRC_status(x) ReadRegBits16(MISC_F1_IMAGE_STATUS,0x200,9)
#define MISC_F1_IMAGE_STATUS_CRC_STATUS_MASK                       0x0200
#define MISC_F1_IMAGE_STATUS_CRC_STATUS_ALIGN                      0
#define MISC_F1_IMAGE_STATUS_CRC_STATUS_BITS                       1
#define MISC_F1_IMAGE_STATUS_CRC_STATUS_SHIFT                      9

/* MISC :: F1_Image_status :: Image_Key [08:08] */
#define Wr_MISC_F1_Image_status_Image_Key(x) WriteRegBits16(MISC_F1_IMAGE_STATUS,0x100,8,x)
#define Rd_MISC_F1_Image_status_Image_Key(x) ReadRegBits16(MISC_F1_IMAGE_STATUS,0x100,8)
#define MISC_F1_IMAGE_STATUS_IMAGE_KEY_MASK                        0x0100
#define MISC_F1_IMAGE_STATUS_IMAGE_KEY_ALIGN                       0
#define MISC_F1_IMAGE_STATUS_IMAGE_KEY_BITS                        1
#define MISC_F1_IMAGE_STATUS_IMAGE_KEY_SHIFT                       8

/* MISC :: F1_Image_status :: Image_Type [07:06] */
#define Wr_MISC_F1_Image_status_Image_Type(x) WriteRegBits16(MISC_F1_IMAGE_STATUS,0xc0,6,x)
#define Rd_MISC_F1_Image_status_Image_Type(x) ReadRegBits16(MISC_F1_IMAGE_STATUS,0xc0,6)
#define MISC_F1_IMAGE_STATUS_IMAGE_TYPE_MASK                       0x00c0
#define MISC_F1_IMAGE_STATUS_IMAGE_TYPE_ALIGN                      0
#define MISC_F1_IMAGE_STATUS_IMAGE_TYPE_BITS                       2
#define MISC_F1_IMAGE_STATUS_IMAGE_TYPE_SHIFT                      6

/* MISC :: F1_Image_status :: Image_Count [05:02] */
#define Wr_MISC_F1_Image_status_Image_Count(x) WriteRegBits16(MISC_F1_IMAGE_STATUS,0x3c,2,x)
#define Rd_MISC_F1_Image_status_Image_Count(x) ReadRegBits16(MISC_F1_IMAGE_STATUS,0x3c,2)
#define MISC_F1_IMAGE_STATUS_IMAGE_COUNT_MASK                      0x003c
#define MISC_F1_IMAGE_STATUS_IMAGE_COUNT_ALIGN                     0
#define MISC_F1_IMAGE_STATUS_IMAGE_COUNT_BITS                      4
#define MISC_F1_IMAGE_STATUS_IMAGE_COUNT_SHIFT                     2

/* MISC :: F1_Image_status :: Final_Image [01:01] */
#define Wr_MISC_F1_Image_status_Final_Image(x) WriteRegBits16(MISC_F1_IMAGE_STATUS,0x2,1,x)
#define Rd_MISC_F1_Image_status_Final_Image(x) ReadRegBits16(MISC_F1_IMAGE_STATUS,0x2,1)
#define MISC_F1_IMAGE_STATUS_FINAL_IMAGE_MASK                      0x0002
#define MISC_F1_IMAGE_STATUS_FINAL_IMAGE_ALIGN                     0
#define MISC_F1_IMAGE_STATUS_FINAL_IMAGE_BITS                      1
#define MISC_F1_IMAGE_STATUS_FINAL_IMAGE_SHIFT                     1

/* MISC :: F1_Image_status :: CRC_Check_Enable [00:00] */
#define Wr_MISC_F1_Image_status_CRC_Check_Enable(x) WriteRegBits16(MISC_F1_IMAGE_STATUS,0x1,0,x)
#define Rd_MISC_F1_Image_status_CRC_Check_Enable(x) ReadRegBits16(MISC_F1_IMAGE_STATUS,0x1,0)
#define MISC_F1_IMAGE_STATUS_CRC_CHECK_ENABLE_MASK                 0x0001
#define MISC_F1_IMAGE_STATUS_CRC_CHECK_ENABLE_ALIGN                0
#define MISC_F1_IMAGE_STATUS_CRC_CHECK_ENABLE_BITS                 1
#define MISC_F1_IMAGE_STATUS_CRC_CHECK_ENABLE_SHIFT                0


/****************************************************************************
 * MISC :: F1_Image_version
 ***************************************************************************/
/* MISC :: F1_Image_version :: firmware_version [15:13] */
#define Wr_MISC_F1_Image_version_firmware_version(x) WriteRegBits16(MISC_F1_IMAGE_VERSION,0xe000,13,x)
#define Rd_MISC_F1_Image_version_firmware_version(x) ReadRegBits16(MISC_F1_IMAGE_VERSION,0xe000,13)
#define MISC_F1_IMAGE_VERSION_FIRMWARE_VERSION_MASK                0xe000
#define MISC_F1_IMAGE_VERSION_FIRMWARE_VERSION_ALIGN               0
#define MISC_F1_IMAGE_VERSION_FIRMWARE_VERSION_BITS                3
#define MISC_F1_IMAGE_VERSION_FIRMWARE_VERSION_SHIFT               13

/* MISC :: F1_Image_version :: Month [12:09] */
#define Wr_MISC_F1_Image_version_Month(x) WriteRegBits16(MISC_F1_IMAGE_VERSION,0x1e00,9,x)
#define Rd_MISC_F1_Image_version_Month(x) ReadRegBits16(MISC_F1_IMAGE_VERSION,0x1e00,9)
#define MISC_F1_IMAGE_VERSION_MONTH_MASK                           0x1e00
#define MISC_F1_IMAGE_VERSION_MONTH_ALIGN                          0
#define MISC_F1_IMAGE_VERSION_MONTH_BITS                           4
#define MISC_F1_IMAGE_VERSION_MONTH_SHIFT                          9

/* MISC :: F1_Image_version :: day [08:04] */
#define Wr_MISC_F1_Image_version_day(x) WriteRegBits16(MISC_F1_IMAGE_VERSION,0x1f0,4,x)
#define Rd_MISC_F1_Image_version_day(x) ReadRegBits16(MISC_F1_IMAGE_VERSION,0x1f0,4)
#define MISC_F1_IMAGE_VERSION_DAY_MASK                             0x01f0
#define MISC_F1_IMAGE_VERSION_DAY_ALIGN                            0
#define MISC_F1_IMAGE_VERSION_DAY_BITS                             5
#define MISC_F1_IMAGE_VERSION_DAY_SHIFT                            4

/* MISC :: F1_Image_version :: year [03:00] */
#define Wr_MISC_F1_Image_version_year(x) WriteRegBits16(MISC_F1_IMAGE_VERSION,0xf,0,x)
#define Rd_MISC_F1_Image_version_year(x) ReadRegBits16(MISC_F1_IMAGE_VERSION,0xf,0)
#define MISC_F1_IMAGE_VERSION_YEAR_MASK                            0x000f
#define MISC_F1_IMAGE_VERSION_YEAR_ALIGN                           0
#define MISC_F1_IMAGE_VERSION_YEAR_BITS                            4
#define MISC_F1_IMAGE_VERSION_YEAR_SHIFT                           0


/****************************************************************************
 * MISC :: F2_Image_status
 ***************************************************************************/
/* MISC :: F2_Image_status :: firmware_executed [15:15] */
#define Wr_MISC_F2_Image_status_firmware_executed(x) WriteRegBits16(MISC_F2_IMAGE_STATUS,0x8000,15,x)
#define Rd_MISC_F2_Image_status_firmware_executed(x) ReadRegBits16(MISC_F2_IMAGE_STATUS,0x8000,15)
#define MISC_F2_IMAGE_STATUS_FIRMWARE_EXECUTED_MASK                0x8000
#define MISC_F2_IMAGE_STATUS_FIRMWARE_EXECUTED_ALIGN               0
#define MISC_F2_IMAGE_STATUS_FIRMWARE_EXECUTED_BITS                1
#define MISC_F2_IMAGE_STATUS_FIRMWARE_EXECUTED_SHIFT               15

/* MISC :: F2_Image_status :: bootrom_loaded [14:14] */
#define Wr_MISC_F2_Image_status_bootrom_loaded(x) WriteRegBits16(MISC_F2_IMAGE_STATUS,0x4000,14,x)
#define Rd_MISC_F2_Image_status_bootrom_loaded(x) ReadRegBits16(MISC_F2_IMAGE_STATUS,0x4000,14)
#define MISC_F2_IMAGE_STATUS_BOOTROM_LOADED_MASK                   0x4000
#define MISC_F2_IMAGE_STATUS_BOOTROM_LOADED_ALIGN                  0
#define MISC_F2_IMAGE_STATUS_BOOTROM_LOADED_BITS                   1
#define MISC_F2_IMAGE_STATUS_BOOTROM_LOADED_SHIFT                  14

/* MISC :: F2_Image_status :: spare [13:10] */
#define Wr_MISC_F2_Image_status_spare(x) WriteRegBits16(MISC_F2_IMAGE_STATUS,0x3c00,10,x)
#define Rd_MISC_F2_Image_status_spare(x) ReadRegBits16(MISC_F2_IMAGE_STATUS,0x3c00,10)
#define MISC_F2_IMAGE_STATUS_SPARE_MASK                            0x3c00
#define MISC_F2_IMAGE_STATUS_SPARE_ALIGN                           0
#define MISC_F2_IMAGE_STATUS_SPARE_BITS                            4
#define MISC_F2_IMAGE_STATUS_SPARE_SHIFT                           10

/* MISC :: F2_Image_status :: CRC_status [09:09] */
#define Wr_MISC_F2_Image_status_CRC_status(x) WriteRegBits16(MISC_F2_IMAGE_STATUS,0x200,9,x)
#define Rd_MISC_F2_Image_status_CRC_status(x) ReadRegBits16(MISC_F2_IMAGE_STATUS,0x200,9)
#define MISC_F2_IMAGE_STATUS_CRC_STATUS_MASK                       0x0200
#define MISC_F2_IMAGE_STATUS_CRC_STATUS_ALIGN                      0
#define MISC_F2_IMAGE_STATUS_CRC_STATUS_BITS                       1
#define MISC_F2_IMAGE_STATUS_CRC_STATUS_SHIFT                      9

/* MISC :: F2_Image_status :: Image_Key [08:08] */
#define Wr_MISC_F2_Image_status_Image_Key(x) WriteRegBits16(MISC_F2_IMAGE_STATUS,0x100,8,x)
#define Rd_MISC_F2_Image_status_Image_Key(x) ReadRegBits16(MISC_F2_IMAGE_STATUS,0x100,8)
#define MISC_F2_IMAGE_STATUS_IMAGE_KEY_MASK                        0x0100
#define MISC_F2_IMAGE_STATUS_IMAGE_KEY_ALIGN                       0
#define MISC_F2_IMAGE_STATUS_IMAGE_KEY_BITS                        1
#define MISC_F2_IMAGE_STATUS_IMAGE_KEY_SHIFT                       8

/* MISC :: F2_Image_status :: Image_Type [07:06] */
#define Wr_MISC_F2_Image_status_Image_Type(x) WriteRegBits16(MISC_F2_IMAGE_STATUS,0xc0,6,x)
#define Rd_MISC_F2_Image_status_Image_Type(x) ReadRegBits16(MISC_F2_IMAGE_STATUS,0xc0,6)
#define MISC_F2_IMAGE_STATUS_IMAGE_TYPE_MASK                       0x00c0
#define MISC_F2_IMAGE_STATUS_IMAGE_TYPE_ALIGN                      0
#define MISC_F2_IMAGE_STATUS_IMAGE_TYPE_BITS                       2
#define MISC_F2_IMAGE_STATUS_IMAGE_TYPE_SHIFT                      6

/* MISC :: F2_Image_status :: Image_Count [05:02] */
#define Wr_MISC_F2_Image_status_Image_Count(x) WriteRegBits16(MISC_F2_IMAGE_STATUS,0x3c,2,x)
#define Rd_MISC_F2_Image_status_Image_Count(x) ReadRegBits16(MISC_F2_IMAGE_STATUS,0x3c,2)
#define MISC_F2_IMAGE_STATUS_IMAGE_COUNT_MASK                      0x003c
#define MISC_F2_IMAGE_STATUS_IMAGE_COUNT_ALIGN                     0
#define MISC_F2_IMAGE_STATUS_IMAGE_COUNT_BITS                      4
#define MISC_F2_IMAGE_STATUS_IMAGE_COUNT_SHIFT                     2

/* MISC :: F2_Image_status :: Final_Image [01:01] */
#define Wr_MISC_F2_Image_status_Final_Image(x) WriteRegBits16(MISC_F2_IMAGE_STATUS,0x2,1,x)
#define Rd_MISC_F2_Image_status_Final_Image(x) ReadRegBits16(MISC_F2_IMAGE_STATUS,0x2,1)
#define MISC_F2_IMAGE_STATUS_FINAL_IMAGE_MASK                      0x0002
#define MISC_F2_IMAGE_STATUS_FINAL_IMAGE_ALIGN                     0
#define MISC_F2_IMAGE_STATUS_FINAL_IMAGE_BITS                      1
#define MISC_F2_IMAGE_STATUS_FINAL_IMAGE_SHIFT                     1

/* MISC :: F2_Image_status :: CRC_Check_Enable [00:00] */
#define Wr_MISC_F2_Image_status_CRC_Check_Enable(x) WriteRegBits16(MISC_F2_IMAGE_STATUS,0x1,0,x)
#define Rd_MISC_F2_Image_status_CRC_Check_Enable(x) ReadRegBits16(MISC_F2_IMAGE_STATUS,0x1,0)
#define MISC_F2_IMAGE_STATUS_CRC_CHECK_ENABLE_MASK                 0x0001
#define MISC_F2_IMAGE_STATUS_CRC_CHECK_ENABLE_ALIGN                0
#define MISC_F2_IMAGE_STATUS_CRC_CHECK_ENABLE_BITS                 1
#define MISC_F2_IMAGE_STATUS_CRC_CHECK_ENABLE_SHIFT                0


/****************************************************************************
 * MISC :: F2_Image_version
 ***************************************************************************/
/* MISC :: F2_Image_version :: firmware_version [15:13] */
#define Wr_MISC_F2_Image_version_firmware_version(x) WriteRegBits16(MISC_F2_IMAGE_VERSION,0xe000,13,x)
#define Rd_MISC_F2_Image_version_firmware_version(x) ReadRegBits16(MISC_F2_IMAGE_VERSION,0xe000,13)
#define MISC_F2_IMAGE_VERSION_FIRMWARE_VERSION_MASK                0xe000
#define MISC_F2_IMAGE_VERSION_FIRMWARE_VERSION_ALIGN               0
#define MISC_F2_IMAGE_VERSION_FIRMWARE_VERSION_BITS                3
#define MISC_F2_IMAGE_VERSION_FIRMWARE_VERSION_SHIFT               13

/* MISC :: F2_Image_version :: Month [12:09] */
#define Wr_MISC_F2_Image_version_Month(x) WriteRegBits16(MISC_F2_IMAGE_VERSION,0x1e00,9,x)
#define Rd_MISC_F2_Image_version_Month(x) ReadRegBits16(MISC_F2_IMAGE_VERSION,0x1e00,9)
#define MISC_F2_IMAGE_VERSION_MONTH_MASK                           0x1e00
#define MISC_F2_IMAGE_VERSION_MONTH_ALIGN                          0
#define MISC_F2_IMAGE_VERSION_MONTH_BITS                           4
#define MISC_F2_IMAGE_VERSION_MONTH_SHIFT                          9

/* MISC :: F2_Image_version :: day [08:04] */
#define Wr_MISC_F2_Image_version_day(x) WriteRegBits16(MISC_F2_IMAGE_VERSION,0x1f0,4,x)
#define Rd_MISC_F2_Image_version_day(x) ReadRegBits16(MISC_F2_IMAGE_VERSION,0x1f0,4)
#define MISC_F2_IMAGE_VERSION_DAY_MASK                             0x01f0
#define MISC_F2_IMAGE_VERSION_DAY_ALIGN                            0
#define MISC_F2_IMAGE_VERSION_DAY_BITS                             5
#define MISC_F2_IMAGE_VERSION_DAY_SHIFT                            4

/* MISC :: F2_Image_version :: year [03:00] */
#define Wr_MISC_F2_Image_version_year(x) WriteRegBits16(MISC_F2_IMAGE_VERSION,0xf,0,x)
#define Rd_MISC_F2_Image_version_year(x) ReadRegBits16(MISC_F2_IMAGE_VERSION,0xf,0)
#define MISC_F2_IMAGE_VERSION_YEAR_MASK                            0x000f
#define MISC_F2_IMAGE_VERSION_YEAR_ALIGN                           0
#define MISC_F2_IMAGE_VERSION_YEAR_BITS                            4
#define MISC_F2_IMAGE_VERSION_YEAR_SHIFT                           0


/****************************************************************************
 * MISC :: SPARE_HW_REG4
 ***************************************************************************/
/* MISC :: SPARE_HW_REG4 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG4_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG4,x)
#define Rd_MISC_SPARE_HW_REG4_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG4)
#define MISC_SPARE_HW_REG4_SPARE_HW_REG_MASK                       0xffff
#define MISC_SPARE_HW_REG4_SPARE_HW_REG_ALIGN                      0
#define MISC_SPARE_HW_REG4_SPARE_HW_REG_BITS                       16
#define MISC_SPARE_HW_REG4_SPARE_HW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_HW_REG5
 ***************************************************************************/
/* MISC :: SPARE_HW_REG5 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG5_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG5,x)
#define Rd_MISC_SPARE_HW_REG5_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG5)
#define MISC_SPARE_HW_REG5_SPARE_HW_REG_MASK                       0xffff
#define MISC_SPARE_HW_REG5_SPARE_HW_REG_ALIGN                      0
#define MISC_SPARE_HW_REG5_SPARE_HW_REG_BITS                       16
#define MISC_SPARE_HW_REG5_SPARE_HW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_HW_REG6
 ***************************************************************************/
/* MISC :: SPARE_HW_REG6 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG6_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG6,x)
#define Rd_MISC_SPARE_HW_REG6_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG6)
#define MISC_SPARE_HW_REG6_SPARE_HW_REG_MASK                       0xffff
#define MISC_SPARE_HW_REG6_SPARE_HW_REG_ALIGN                      0
#define MISC_SPARE_HW_REG6_SPARE_HW_REG_BITS                       16
#define MISC_SPARE_HW_REG6_SPARE_HW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_HW_REG7
 ***************************************************************************/
/* MISC :: SPARE_HW_REG7 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG7_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG7,x)
#define Rd_MISC_SPARE_HW_REG7_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG7)
#define MISC_SPARE_HW_REG7_SPARE_HW_REG_MASK                       0xffff
#define MISC_SPARE_HW_REG7_SPARE_HW_REG_ALIGN                      0
#define MISC_SPARE_HW_REG7_SPARE_HW_REG_BITS                       16
#define MISC_SPARE_HW_REG7_SPARE_HW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_HW_REG8
 ***************************************************************************/
/* MISC :: SPARE_HW_REG8 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG8_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG8,x)
#define Rd_MISC_SPARE_HW_REG8_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG8)
#define MISC_SPARE_HW_REG8_SPARE_HW_REG_MASK                       0xffff
#define MISC_SPARE_HW_REG8_SPARE_HW_REG_ALIGN                      0
#define MISC_SPARE_HW_REG8_SPARE_HW_REG_BITS                       16
#define MISC_SPARE_HW_REG8_SPARE_HW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_HW_REG9
 ***************************************************************************/
/* MISC :: SPARE_HW_REG9 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG9_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG9,x)
#define Rd_MISC_SPARE_HW_REG9_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG9)
#define MISC_SPARE_HW_REG9_SPARE_HW_REG_MASK                       0xffff
#define MISC_SPARE_HW_REG9_SPARE_HW_REG_ALIGN                      0
#define MISC_SPARE_HW_REG9_SPARE_HW_REG_BITS                       16
#define MISC_SPARE_HW_REG9_SPARE_HW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_HW_REG10
 ***************************************************************************/
/* MISC :: SPARE_HW_REG10 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG10_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG10,x)
#define Rd_MISC_SPARE_HW_REG10_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG10)
#define MISC_SPARE_HW_REG10_SPARE_HW_REG_MASK                      0xffff
#define MISC_SPARE_HW_REG10_SPARE_HW_REG_ALIGN                     0
#define MISC_SPARE_HW_REG10_SPARE_HW_REG_BITS                      16
#define MISC_SPARE_HW_REG10_SPARE_HW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_HW_REG11
 ***************************************************************************/
/* MISC :: SPARE_HW_REG11 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG11_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG11,x)
#define Rd_MISC_SPARE_HW_REG11_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG11)
#define MISC_SPARE_HW_REG11_SPARE_HW_REG_MASK                      0xffff
#define MISC_SPARE_HW_REG11_SPARE_HW_REG_ALIGN                     0
#define MISC_SPARE_HW_REG11_SPARE_HW_REG_BITS                      16
#define MISC_SPARE_HW_REG11_SPARE_HW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_HW_REG12
 ***************************************************************************/
/* MISC :: SPARE_HW_REG12 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG12_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG12,x)
#define Rd_MISC_SPARE_HW_REG12_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG12)
#define MISC_SPARE_HW_REG12_SPARE_HW_REG_MASK                      0xffff
#define MISC_SPARE_HW_REG12_SPARE_HW_REG_ALIGN                     0
#define MISC_SPARE_HW_REG12_SPARE_HW_REG_BITS                      16
#define MISC_SPARE_HW_REG12_SPARE_HW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_HW_REG13
 ***************************************************************************/
/* MISC :: SPARE_HW_REG13 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG13_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG13,x)
#define Rd_MISC_SPARE_HW_REG13_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG13)
#define MISC_SPARE_HW_REG13_SPARE_HW_REG_MASK                      0xffff
#define MISC_SPARE_HW_REG13_SPARE_HW_REG_ALIGN                     0
#define MISC_SPARE_HW_REG13_SPARE_HW_REG_BITS                      16
#define MISC_SPARE_HW_REG13_SPARE_HW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_HW_REG14
 ***************************************************************************/
/* MISC :: SPARE_HW_REG14 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG14_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG14,x)
#define Rd_MISC_SPARE_HW_REG14_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG14)
#define MISC_SPARE_HW_REG14_SPARE_HW_REG_MASK                      0xffff
#define MISC_SPARE_HW_REG14_SPARE_HW_REG_ALIGN                     0
#define MISC_SPARE_HW_REG14_SPARE_HW_REG_BITS                      16
#define MISC_SPARE_HW_REG14_SPARE_HW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_HW_REG15
 ***************************************************************************/
/* MISC :: SPARE_HW_REG15 :: spare_hw_reg [15:00] */
#define Wr_MISC_SPARE_HW_REG15_spare_hw_reg(x) WriteReg16(MISC_SPARE_HW_REG15,x)
#define Rd_MISC_SPARE_HW_REG15_spare_hw_reg(x) ReadReg16(MISC_SPARE_HW_REG15)
#define MISC_SPARE_HW_REG15_SPARE_HW_REG_MASK                      0xffff
#define MISC_SPARE_HW_REG15_SPARE_HW_REG_ALIGN                     0
#define MISC_SPARE_HW_REG15_SPARE_HW_REG_BITS                      16
#define MISC_SPARE_HW_REG15_SPARE_HW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_SW_REG0
 ***************************************************************************/
/* MISC :: SPARE_SW_REG0 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG0_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG0,x)
#define Rd_MISC_SPARE_SW_REG0_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG0)
#define MISC_SPARE_SW_REG0_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG0_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG0_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG0_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG1
 ***************************************************************************/
/* MISC :: SPARE_SW_REG1 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG1_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG1,x)
#define Rd_MISC_SPARE_SW_REG1_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG1)
#define MISC_SPARE_SW_REG1_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG1_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG1_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG1_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG2
 ***************************************************************************/
/* MISC :: SPARE_SW_REG2 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG2_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG2,x)
#define Rd_MISC_SPARE_SW_REG2_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG2)
#define MISC_SPARE_SW_REG2_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG2_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG2_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG2_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG3
 ***************************************************************************/
/* MISC :: SPARE_SW_REG3 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG3_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG3,x)
#define Rd_MISC_SPARE_SW_REG3_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG3)
#define MISC_SPARE_SW_REG3_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG3_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG3_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG3_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG4
 ***************************************************************************/
/* MISC :: SPARE_SW_REG4 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG4_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG4,x)
#define Rd_MISC_SPARE_SW_REG4_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG4)
#define MISC_SPARE_SW_REG4_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG4_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG4_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG4_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG5
 ***************************************************************************/
/* MISC :: SPARE_SW_REG5 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG5_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG5,x)
#define Rd_MISC_SPARE_SW_REG5_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG5)
#define MISC_SPARE_SW_REG5_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG5_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG5_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG5_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG6
 ***************************************************************************/
/* MISC :: SPARE_SW_REG6 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG6_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG6,x)
#define Rd_MISC_SPARE_SW_REG6_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG6)
#define MISC_SPARE_SW_REG6_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG6_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG6_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG6_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG7
 ***************************************************************************/
/* MISC :: SPARE_SW_REG7 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG7_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG7,x)
#define Rd_MISC_SPARE_SW_REG7_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG7)
#define MISC_SPARE_SW_REG7_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG7_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG7_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG7_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG8
 ***************************************************************************/
/* MISC :: SPARE_SW_REG8 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG8_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG8,x)
#define Rd_MISC_SPARE_SW_REG8_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG8)
#define MISC_SPARE_SW_REG8_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG8_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG8_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG8_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG9
 ***************************************************************************/
/* MISC :: SPARE_SW_REG9 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG9_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG9,x)
#define Rd_MISC_SPARE_SW_REG9_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG9)
#define MISC_SPARE_SW_REG9_SPARE_SW_REG_MASK                       0xffff
#define MISC_SPARE_SW_REG9_SPARE_SW_REG_ALIGN                      0
#define MISC_SPARE_SW_REG9_SPARE_SW_REG_BITS                       16
#define MISC_SPARE_SW_REG9_SPARE_SW_REG_SHIFT                      0


/****************************************************************************
 * MISC :: SPARE_SW_REG10
 ***************************************************************************/
/* MISC :: SPARE_SW_REG10 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG10_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG10,x)
#define Rd_MISC_SPARE_SW_REG10_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG10)
#define MISC_SPARE_SW_REG10_SPARE_SW_REG_MASK                      0xffff
#define MISC_SPARE_SW_REG10_SPARE_SW_REG_ALIGN                     0
#define MISC_SPARE_SW_REG10_SPARE_SW_REG_BITS                      16
#define MISC_SPARE_SW_REG10_SPARE_SW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_SW_REG11
 ***************************************************************************/
/* MISC :: SPARE_SW_REG11 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG11_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG11,x)
#define Rd_MISC_SPARE_SW_REG11_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG11)
#define MISC_SPARE_SW_REG11_SPARE_SW_REG_MASK                      0xffff
#define MISC_SPARE_SW_REG11_SPARE_SW_REG_ALIGN                     0
#define MISC_SPARE_SW_REG11_SPARE_SW_REG_BITS                      16
#define MISC_SPARE_SW_REG11_SPARE_SW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_SW_REG12
 ***************************************************************************/
/* MISC :: SPARE_SW_REG12 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG12_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG12,x)
#define Rd_MISC_SPARE_SW_REG12_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG12)
#define MISC_SPARE_SW_REG12_SPARE_SW_REG_MASK                      0xffff
#define MISC_SPARE_SW_REG12_SPARE_SW_REG_ALIGN                     0
#define MISC_SPARE_SW_REG12_SPARE_SW_REG_BITS                      16
#define MISC_SPARE_SW_REG12_SPARE_SW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_SW_REG13
 ***************************************************************************/
/* MISC :: SPARE_SW_REG13 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG13_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG13,x)
#define Rd_MISC_SPARE_SW_REG13_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG13)
#define MISC_SPARE_SW_REG13_SPARE_SW_REG_MASK                      0xffff
#define MISC_SPARE_SW_REG13_SPARE_SW_REG_ALIGN                     0
#define MISC_SPARE_SW_REG13_SPARE_SW_REG_BITS                      16
#define MISC_SPARE_SW_REG13_SPARE_SW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_SW_REG14
 ***************************************************************************/
/* MISC :: SPARE_SW_REG14 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG14_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG14,x)
#define Rd_MISC_SPARE_SW_REG14_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG14)
#define MISC_SPARE_SW_REG14_SPARE_SW_REG_MASK                      0xffff
#define MISC_SPARE_SW_REG14_SPARE_SW_REG_ALIGN                     0
#define MISC_SPARE_SW_REG14_SPARE_SW_REG_BITS                      16
#define MISC_SPARE_SW_REG14_SPARE_SW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: SPARE_SW_REG15
 ***************************************************************************/
/* MISC :: SPARE_SW_REG15 :: spare_sw_reg [15:00] */
#define Wr_MISC_SPARE_SW_REG15_spare_sw_reg(x) WriteReg16(MISC_SPARE_SW_REG15,x)
#define Rd_MISC_SPARE_SW_REG15_spare_sw_reg(x) ReadReg16(MISC_SPARE_SW_REG15)
#define MISC_SPARE_SW_REG15_SPARE_SW_REG_MASK                      0xffff
#define MISC_SPARE_SW_REG15_SPARE_SW_REG_ALIGN                     0
#define MISC_SPARE_SW_REG15_SPARE_SW_REG_BITS                      16
#define MISC_SPARE_SW_REG15_SPARE_SW_REG_SHIFT                     0


/****************************************************************************
 * MISC :: CPUSYS_MISC
 ***************************************************************************/
/* MISC :: CPUSYS_MISC :: reserved0 [15:01] */
#define MISC_CPUSYS_MISC_RESERVED0_MASK                            0xfffe
#define MISC_CPUSYS_MISC_RESERVED0_ALIGN                           0
#define MISC_CPUSYS_MISC_RESERVED0_BITS                            15
#define MISC_CPUSYS_MISC_RESERVED0_SHIFT                           1

/* MISC :: CPUSYS_MISC :: soft_intr [00:00] */
#define Wr_MISC_CPUSYS_MISC_soft_intr(x) WriteRegBits16(MISC_CPUSYS_MISC,0x1,0,x)
#define Rd_MISC_CPUSYS_MISC_soft_intr(x) ReadRegBits16(MISC_CPUSYS_MISC,0x1,0)
#define MISC_CPUSYS_MISC_SOFT_INTR_MASK                            0x0001
#define MISC_CPUSYS_MISC_SOFT_INTR_ALIGN                           0
#define MISC_CPUSYS_MISC_SOFT_INTR_BITS                            1
#define MISC_CPUSYS_MISC_SOFT_INTR_SHIFT                           0


/****************************************************************************
 * MISC :: BRPHYS_CLEAR_ON_READ_REG
 ***************************************************************************/
/* MISC :: BRPHYS_CLEAR_ON_READ_REG :: reserved0 [15:01] */
#define MISC_BRPHYS_CLEAR_ON_READ_REG_RESERVED0_MASK               0xfffe
#define MISC_BRPHYS_CLEAR_ON_READ_REG_RESERVED0_ALIGN              0
#define MISC_BRPHYS_CLEAR_ON_READ_REG_RESERVED0_BITS               15
#define MISC_BRPHYS_CLEAR_ON_READ_REG_RESERVED0_SHIFT              1

/* MISC :: BRPHYS_CLEAR_ON_READ_REG :: clear_on_read_en [00:00] */
#define Wr_MISC_BRPHYS_CLEAR_ON_READ_REG_clear_on_read_en(x) WriteRegBits16(MISC_BRPHYS_CLEAR_ON_READ_REG,0x1,0,x)
#define Rd_MISC_BRPHYS_CLEAR_ON_READ_REG_clear_on_read_en(x) ReadRegBits16(MISC_BRPHYS_CLEAR_ON_READ_REG,0x1,0)
#define MISC_BRPHYS_CLEAR_ON_READ_REG_CLEAR_ON_READ_EN_MASK        0x0001
#define MISC_BRPHYS_CLEAR_ON_READ_REG_CLEAR_ON_READ_EN_ALIGN       0
#define MISC_BRPHYS_CLEAR_ON_READ_REG_CLEAR_ON_READ_EN_BITS        1
#define MISC_BRPHYS_CLEAR_ON_READ_REG_CLEAR_ON_READ_EN_SHIFT       0


/****************************************************************************
 * MISC :: SCRATCH_REG
 ***************************************************************************/
/* MISC :: SCRATCH_REG :: scratch [15:00] */
#define Wr_MISC_SCRATCH_REG_scratch(x) WriteReg16(MISC_SCRATCH_REG,x)
#define Rd_MISC_SCRATCH_REG_scratch(x) ReadReg16(MISC_SCRATCH_REG)
#define MISC_SCRATCH_REG_SCRATCH_MASK                              0xffff
#define MISC_SCRATCH_REG_SCRATCH_ALIGN                             0
#define MISC_SCRATCH_REG_SCRATCH_BITS                              16
#define MISC_SCRATCH_REG_SCRATCH_SHIFT                             0


/****************************************************************************
 * bcm89530_top_bridge_CRG
 ***************************************************************************/
/****************************************************************************
 * CRG :: XTAL_CONFIG
 ***************************************************************************/
/* CRG :: XTAL_CONFIG :: reserved0 [15:12] */
#define CRG_XTAL_CONFIG_RESERVED0_MASK                             0xf000
#define CRG_XTAL_CONFIG_RESERVED0_ALIGN                            0
#define CRG_XTAL_CONFIG_RESERVED0_BITS                             4
#define CRG_XTAL_CONFIG_RESERVED0_SHIFT                            12

/* CRG :: XTAL_CONFIG :: xcore_CM_sel [11:11] */
#define Wr_CRG_XTAL_CONFIG_xcore_CM_sel(x) WriteRegBits16(CRG_XTAL_CONFIG,0x800,11,x)
#define Rd_CRG_XTAL_CONFIG_xcore_CM_sel(x) ReadRegBits16(CRG_XTAL_CONFIG,0x800,11)
#define CRG_XTAL_CONFIG_XCORE_CM_SEL_MASK                          0x0800
#define CRG_XTAL_CONFIG_XCORE_CM_SEL_ALIGN                         0
#define CRG_XTAL_CONFIG_XCORE_CM_SEL_BITS                          1
#define CRG_XTAL_CONFIG_XCORE_CM_SEL_SHIFT                         11

/* CRG :: XTAL_CONFIG :: xtal_bias [10:08] */
#define Wr_CRG_XTAL_CONFIG_xtal_bias(x) WriteRegBits16(CRG_XTAL_CONFIG,0x700,8,x)
#define Rd_CRG_XTAL_CONFIG_xtal_bias(x) ReadRegBits16(CRG_XTAL_CONFIG,0x700,8)
#define CRG_XTAL_CONFIG_XTAL_BIAS_MASK                             0x0700
#define CRG_XTAL_CONFIG_XTAL_BIAS_ALIGN                            0
#define CRG_XTAL_CONFIG_XTAL_BIAS_BITS                             3
#define CRG_XTAL_CONFIG_XTAL_BIAS_SHIFT                            8

/* CRG :: XTAL_CONFIG :: cmos_en_ch [07:06] */
#define Wr_CRG_XTAL_CONFIG_cmos_en_ch(x) WriteRegBits16(CRG_XTAL_CONFIG,0xc0,6,x)
#define Rd_CRG_XTAL_CONFIG_cmos_en_ch(x) ReadRegBits16(CRG_XTAL_CONFIG,0xc0,6)
#define CRG_XTAL_CONFIG_CMOS_EN_CH_MASK                            0x00c0
#define CRG_XTAL_CONFIG_CMOS_EN_CH_ALIGN                           0
#define CRG_XTAL_CONFIG_CMOS_EN_CH_BITS                            2
#define CRG_XTAL_CONFIG_CMOS_EN_CH_SHIFT                           6

/* CRG :: XTAL_CONFIG :: cmos_en_all [05:05] */
#define Wr_CRG_XTAL_CONFIG_cmos_en_all(x) WriteRegBits16(CRG_XTAL_CONFIG,0x20,5,x)
#define Rd_CRG_XTAL_CONFIG_cmos_en_all(x) ReadRegBits16(CRG_XTAL_CONFIG,0x20,5)
#define CRG_XTAL_CONFIG_CMOS_EN_ALL_MASK                           0x0020
#define CRG_XTAL_CONFIG_CMOS_EN_ALL_ALIGN                          0
#define CRG_XTAL_CONFIG_CMOS_EN_ALL_BITS                           1
#define CRG_XTAL_CONFIG_CMOS_EN_ALL_SHIFT                          5

/* CRG :: XTAL_CONFIG :: cml_cur [04:04] */
#define Wr_CRG_XTAL_CONFIG_cml_cur(x) WriteRegBits16(CRG_XTAL_CONFIG,0x10,4,x)
#define Rd_CRG_XTAL_CONFIG_cml_cur(x) ReadRegBits16(CRG_XTAL_CONFIG,0x10,4)
#define CRG_XTAL_CONFIG_CML_CUR_MASK                               0x0010
#define CRG_XTAL_CONFIG_CML_CUR_ALIGN                              0
#define CRG_XTAL_CONFIG_CML_CUR_BITS                               1
#define CRG_XTAL_CONFIG_CML_CUR_SHIFT                              4

/* CRG :: XTAL_CONFIG :: cml_pd_ch [03:03] */
#define Wr_CRG_XTAL_CONFIG_cml_pd_ch(x) WriteRegBits16(CRG_XTAL_CONFIG,0x8,3,x)
#define Rd_CRG_XTAL_CONFIG_cml_pd_ch(x) ReadRegBits16(CRG_XTAL_CONFIG,0x8,3)
#define CRG_XTAL_CONFIG_CML_PD_CH_MASK                             0x0008
#define CRG_XTAL_CONFIG_CML_PD_CH_ALIGN                            0
#define CRG_XTAL_CONFIG_CML_PD_CH_BITS                             1
#define CRG_XTAL_CONFIG_CML_PD_CH_SHIFT                            3

/* CRG :: XTAL_CONFIG :: d2c_bias [02:00] */
#define Wr_CRG_XTAL_CONFIG_d2c_bias(x) WriteRegBits16(CRG_XTAL_CONFIG,0x7,0,x)
#define Rd_CRG_XTAL_CONFIG_d2c_bias(x) ReadRegBits16(CRG_XTAL_CONFIG,0x7,0)
#define CRG_XTAL_CONFIG_D2C_BIAS_MASK                              0x0007
#define CRG_XTAL_CONFIG_D2C_BIAS_ALIGN                             0
#define CRG_XTAL_CONFIG_D2C_BIAS_BITS                              3
#define CRG_XTAL_CONFIG_D2C_BIAS_SHIFT                             0


/****************************************************************************
 * CRG :: PLL_CONFIG1
 ***************************************************************************/
/* CRG :: PLL_CONFIG1 :: pdiv [15:12] */
#define Wr_CRG_PLL_CONFIG1_pdiv(x) WriteRegBits16(CRG_PLL_CONFIG1,0xf000,12,x)
#define Rd_CRG_PLL_CONFIG1_pdiv(x) ReadRegBits16(CRG_PLL_CONFIG1,0xf000,12)
#define CRG_PLL_CONFIG1_PDIV_MASK                                  0xf000
#define CRG_PLL_CONFIG1_PDIV_ALIGN                                 0
#define CRG_PLL_CONFIG1_PDIV_BITS                                  4
#define CRG_PLL_CONFIG1_PDIV_SHIFT                                 12

/* CRG :: PLL_CONFIG1 :: reserved0 [11:10] */
#define CRG_PLL_CONFIG1_RESERVED0_MASK                             0x0c00
#define CRG_PLL_CONFIG1_RESERVED0_ALIGN                            0
#define CRG_PLL_CONFIG1_RESERVED0_BITS                             2
#define CRG_PLL_CONFIG1_RESERVED0_SHIFT                            10

/* CRG :: PLL_CONFIG1 :: ka [09:07] */
#define Wr_CRG_PLL_CONFIG1_ka(x) WriteRegBits16(CRG_PLL_CONFIG1,0x380,7,x)
#define Rd_CRG_PLL_CONFIG1_ka(x) ReadRegBits16(CRG_PLL_CONFIG1,0x380,7)
#define CRG_PLL_CONFIG1_KA_MASK                                    0x0380
#define CRG_PLL_CONFIG1_KA_ALIGN                                   0
#define CRG_PLL_CONFIG1_KA_BITS                                    3
#define CRG_PLL_CONFIG1_KA_SHIFT                                   7

/* CRG :: PLL_CONFIG1 :: ki [06:04] */
#define Wr_CRG_PLL_CONFIG1_ki(x) WriteRegBits16(CRG_PLL_CONFIG1,0x70,4,x)
#define Rd_CRG_PLL_CONFIG1_ki(x) ReadRegBits16(CRG_PLL_CONFIG1,0x70,4)
#define CRG_PLL_CONFIG1_KI_MASK                                    0x0070
#define CRG_PLL_CONFIG1_KI_ALIGN                                   0
#define CRG_PLL_CONFIG1_KI_BITS                                    3
#define CRG_PLL_CONFIG1_KI_SHIFT                                   4

/* CRG :: PLL_CONFIG1 :: kp [03:00] */
#define Wr_CRG_PLL_CONFIG1_kp(x) WriteRegBits16(CRG_PLL_CONFIG1,0xf,0,x)
#define Rd_CRG_PLL_CONFIG1_kp(x) ReadRegBits16(CRG_PLL_CONFIG1,0xf,0)
#define CRG_PLL_CONFIG1_KP_MASK                                    0x000f
#define CRG_PLL_CONFIG1_KP_ALIGN                                   0
#define CRG_PLL_CONFIG1_KP_BITS                                    4
#define CRG_PLL_CONFIG1_KP_SHIFT                                   0


/****************************************************************************
 * CRG :: PLL_CONFIG2
 ***************************************************************************/
/* CRG :: PLL_CONFIG2 :: bypass_en [15:12] */
#define Wr_CRG_PLL_CONFIG2_bypass_en(x) WriteRegBits16(CRG_PLL_CONFIG2,0xf000,12,x)
#define Rd_CRG_PLL_CONFIG2_bypass_en(x) ReadRegBits16(CRG_PLL_CONFIG2,0xf000,12)
#define CRG_PLL_CONFIG2_BYPASS_EN_MASK                             0xf000
#define CRG_PLL_CONFIG2_BYPASS_EN_ALIGN                            0
#define CRG_PLL_CONFIG2_BYPASS_EN_BITS                             4
#define CRG_PLL_CONFIG2_BYPASS_EN_SHIFT                            12

/* CRG :: PLL_CONFIG2 :: pll_ch_delay [11:08] */
#define Wr_CRG_PLL_CONFIG2_pll_ch_delay(x) WriteRegBits16(CRG_PLL_CONFIG2,0xf00,8,x)
#define Rd_CRG_PLL_CONFIG2_pll_ch_delay(x) ReadRegBits16(CRG_PLL_CONFIG2,0xf00,8)
#define CRG_PLL_CONFIG2_PLL_CH_DELAY_MASK                          0x0f00
#define CRG_PLL_CONFIG2_PLL_CH_DELAY_ALIGN                         0
#define CRG_PLL_CONFIG2_PLL_CH_DELAY_BITS                          4
#define CRG_PLL_CONFIG2_PLL_CH_DELAY_SHIFT                         8

/* CRG :: PLL_CONFIG2 :: pll_ch_hold [07:04] */
#define Wr_CRG_PLL_CONFIG2_pll_ch_hold(x) WriteRegBits16(CRG_PLL_CONFIG2,0xf0,4,x)
#define Rd_CRG_PLL_CONFIG2_pll_ch_hold(x) ReadRegBits16(CRG_PLL_CONFIG2,0xf0,4)
#define CRG_PLL_CONFIG2_PLL_CH_HOLD_MASK                           0x00f0
#define CRG_PLL_CONFIG2_PLL_CH_HOLD_ALIGN                          0
#define CRG_PLL_CONFIG2_PLL_CH_HOLD_BITS                           4
#define CRG_PLL_CONFIG2_PLL_CH_HOLD_SHIFT                          4

/* CRG :: PLL_CONFIG2 :: pll_ch_en_n [03:00] */
#define Wr_CRG_PLL_CONFIG2_pll_ch_en_n(x) WriteRegBits16(CRG_PLL_CONFIG2,0xf,0,x)
#define Rd_CRG_PLL_CONFIG2_pll_ch_en_n(x) ReadRegBits16(CRG_PLL_CONFIG2,0xf,0)
#define CRG_PLL_CONFIG2_PLL_CH_EN_N_MASK                           0x000f
#define CRG_PLL_CONFIG2_PLL_CH_EN_N_ALIGN                          0
#define CRG_PLL_CONFIG2_PLL_CH_EN_N_BITS                           4
#define CRG_PLL_CONFIG2_PLL_CH_EN_N_SHIFT                          0


/****************************************************************************
 * CRG :: PLL_NDIV
 ***************************************************************************/
/* CRG :: PLL_NDIV :: reserved0 [15:10] */
#define CRG_PLL_NDIV_RESERVED0_MASK                                0xfc00
#define CRG_PLL_NDIV_RESERVED0_ALIGN                               0
#define CRG_PLL_NDIV_RESERVED0_BITS                                6
#define CRG_PLL_NDIV_RESERVED0_SHIFT                               10

/* CRG :: PLL_NDIV :: NDIV_INT [09:00] */
#define Wr_CRG_PLL_NDIV_NDIV_INT(x) WriteRegBits16(CRG_PLL_NDIV,0x3ff,0,x)
#define Rd_CRG_PLL_NDIV_NDIV_INT(x) ReadRegBits16(CRG_PLL_NDIV,0x3ff,0)
#define CRG_PLL_NDIV_NDIV_INT_MASK                                 0x03ff
#define CRG_PLL_NDIV_NDIV_INT_ALIGN                                0
#define CRG_PLL_NDIV_NDIV_INT_BITS                                 10
#define CRG_PLL_NDIV_NDIV_INT_SHIFT                                0


/****************************************************************************
 * CRG :: PLL_CTRL0
 ***************************************************************************/
/* CRG :: PLL_CTRL0 :: pll_ctrl0 [15:00] */
#define Wr_CRG_PLL_CTRL0_pll_ctrl0(x) WriteReg16(CRG_PLL_CTRL0,x)
#define Rd_CRG_PLL_CTRL0_pll_ctrl0(x) ReadReg16(CRG_PLL_CTRL0)
#define CRG_PLL_CTRL0_PLL_CTRL0_MASK                               0xffff
#define CRG_PLL_CTRL0_PLL_CTRL0_ALIGN                              0
#define CRG_PLL_CTRL0_PLL_CTRL0_BITS                               16
#define CRG_PLL_CTRL0_PLL_CTRL0_SHIFT                              0


/****************************************************************************
 * CRG :: PLL_CTRL1
 ***************************************************************************/
/* CRG :: PLL_CTRL1 :: pll_ctrl1 [15:00] */
#define Wr_CRG_PLL_CTRL1_pll_ctrl1(x) WriteReg16(CRG_PLL_CTRL1,x)
#define Rd_CRG_PLL_CTRL1_pll_ctrl1(x) ReadReg16(CRG_PLL_CTRL1)
#define CRG_PLL_CTRL1_PLL_CTRL1_MASK                               0xffff
#define CRG_PLL_CTRL1_PLL_CTRL1_ALIGN                              0
#define CRG_PLL_CTRL1_PLL_CTRL1_BITS                               16
#define CRG_PLL_CTRL1_PLL_CTRL1_SHIFT                              0


/****************************************************************************
 * CRG :: PLL_CTRL2
 ***************************************************************************/
/* CRG :: PLL_CTRL2 :: pll_ctrl2 [15:00] */
#define Wr_CRG_PLL_CTRL2_pll_ctrl2(x) WriteReg16(CRG_PLL_CTRL2,x)
#define Rd_CRG_PLL_CTRL2_pll_ctrl2(x) ReadReg16(CRG_PLL_CTRL2)
#define CRG_PLL_CTRL2_PLL_CTRL2_MASK                               0xffff
#define CRG_PLL_CTRL2_PLL_CTRL2_ALIGN                              0
#define CRG_PLL_CTRL2_PLL_CTRL2_BITS                               16
#define CRG_PLL_CTRL2_PLL_CTRL2_SHIFT                              0


/****************************************************************************
 * CRG :: PLL_CTRL3
 ***************************************************************************/
/* CRG :: PLL_CTRL3 :: pll_ctrl3 [15:00] */
#define Wr_CRG_PLL_CTRL3_pll_ctrl3(x) WriteReg16(CRG_PLL_CTRL3,x)
#define Rd_CRG_PLL_CTRL3_pll_ctrl3(x) ReadReg16(CRG_PLL_CTRL3)
#define CRG_PLL_CTRL3_PLL_CTRL3_MASK                               0xffff
#define CRG_PLL_CTRL3_PLL_CTRL3_ALIGN                              0
#define CRG_PLL_CTRL3_PLL_CTRL3_BITS                               16
#define CRG_PLL_CTRL3_PLL_CTRL3_SHIFT                              0


/****************************************************************************
 * CRG :: PLL_MDIV_CH01
 ***************************************************************************/
/* CRG :: PLL_MDIV_CH01 :: mdiv_ch1 [15:08] */
#define Wr_CRG_PLL_MDIV_CH01_mdiv_ch1(x) WriteRegBits16(CRG_PLL_MDIV_CH01,0xff00,8,x)
#define Rd_CRG_PLL_MDIV_CH01_mdiv_ch1(x) ReadRegBits16(CRG_PLL_MDIV_CH01,0xff00,8)
#define CRG_PLL_MDIV_CH01_MDIV_CH1_MASK                            0xff00
#define CRG_PLL_MDIV_CH01_MDIV_CH1_ALIGN                           0
#define CRG_PLL_MDIV_CH01_MDIV_CH1_BITS                            8
#define CRG_PLL_MDIV_CH01_MDIV_CH1_SHIFT                           8

/* CRG :: PLL_MDIV_CH01 :: mdiv_ch0 [07:00] */
#define Wr_CRG_PLL_MDIV_CH01_mdiv_ch0(x) WriteRegBits16(CRG_PLL_MDIV_CH01,0xff,0,x)
#define Rd_CRG_PLL_MDIV_CH01_mdiv_ch0(x) ReadRegBits16(CRG_PLL_MDIV_CH01,0xff,0)
#define CRG_PLL_MDIV_CH01_MDIV_CH0_MASK                            0x00ff
#define CRG_PLL_MDIV_CH01_MDIV_CH0_ALIGN                           0
#define CRG_PLL_MDIV_CH01_MDIV_CH0_BITS                            8
#define CRG_PLL_MDIV_CH01_MDIV_CH0_SHIFT                           0


/****************************************************************************
 * CRG :: PLL_MDIV_CH23
 ***************************************************************************/
/* CRG :: PLL_MDIV_CH23 :: mdiv_ch3 [15:08] */
#define Wr_CRG_PLL_MDIV_CH23_mdiv_ch3(x) WriteRegBits16(CRG_PLL_MDIV_CH23,0xff00,8,x)
#define Rd_CRG_PLL_MDIV_CH23_mdiv_ch3(x) ReadRegBits16(CRG_PLL_MDIV_CH23,0xff00,8)
#define CRG_PLL_MDIV_CH23_MDIV_CH3_MASK                            0xff00
#define CRG_PLL_MDIV_CH23_MDIV_CH3_ALIGN                           0
#define CRG_PLL_MDIV_CH23_MDIV_CH3_BITS                            8
#define CRG_PLL_MDIV_CH23_MDIV_CH3_SHIFT                           8

/* CRG :: PLL_MDIV_CH23 :: mdiv_ch2 [07:00] */
#define Wr_CRG_PLL_MDIV_CH23_mdiv_ch2(x) WriteRegBits16(CRG_PLL_MDIV_CH23,0xff,0,x)
#define Rd_CRG_PLL_MDIV_CH23_mdiv_ch2(x) ReadRegBits16(CRG_PLL_MDIV_CH23,0xff,0)
#define CRG_PLL_MDIV_CH23_MDIV_CH2_MASK                            0x00ff
#define CRG_PLL_MDIV_CH23_MDIV_CH2_ALIGN                           0
#define CRG_PLL_MDIV_CH23_MDIV_CH2_BITS                            8
#define CRG_PLL_MDIV_CH23_MDIV_CH2_SHIFT                           0


/****************************************************************************
 * CRG :: PLL_SSC_CONFIG1
 ***************************************************************************/
/* CRG :: PLL_SSC_CONFIG1 :: reserved0 [15:14] */
#define CRG_PLL_SSC_CONFIG1_RESERVED0_MASK                         0xc000
#define CRG_PLL_SSC_CONFIG1_RESERVED0_ALIGN                        0
#define CRG_PLL_SSC_CONFIG1_RESERVED0_BITS                         2
#define CRG_PLL_SSC_CONFIG1_RESERVED0_SHIFT                        14

/* CRG :: PLL_SSC_CONFIG1 :: scc_limit_hi [13:08] */
#define Wr_CRG_PLL_SSC_CONFIG1_scc_limit_hi(x) WriteRegBits16(CRG_PLL_SSC_CONFIG1,0x3f00,8,x)
#define Rd_CRG_PLL_SSC_CONFIG1_scc_limit_hi(x) ReadRegBits16(CRG_PLL_SSC_CONFIG1,0x3f00,8)
#define CRG_PLL_SSC_CONFIG1_SCC_LIMIT_HI_MASK                      0x3f00
#define CRG_PLL_SSC_CONFIG1_SCC_LIMIT_HI_ALIGN                     0
#define CRG_PLL_SSC_CONFIG1_SCC_LIMIT_HI_BITS                      6
#define CRG_PLL_SSC_CONFIG1_SCC_LIMIT_HI_SHIFT                     8

/* CRG :: PLL_SSC_CONFIG1 :: reserved1 [07:01] */
#define CRG_PLL_SSC_CONFIG1_RESERVED1_MASK                         0x00fe
#define CRG_PLL_SSC_CONFIG1_RESERVED1_ALIGN                        0
#define CRG_PLL_SSC_CONFIG1_RESERVED1_BITS                         7
#define CRG_PLL_SSC_CONFIG1_RESERVED1_SHIFT                        1

/* CRG :: PLL_SSC_CONFIG1 :: SSC_mode [00:00] */
#define Wr_CRG_PLL_SSC_CONFIG1_SSC_mode(x) WriteRegBits16(CRG_PLL_SSC_CONFIG1,0x1,0,x)
#define Rd_CRG_PLL_SSC_CONFIG1_SSC_mode(x) ReadRegBits16(CRG_PLL_SSC_CONFIG1,0x1,0)
#define CRG_PLL_SSC_CONFIG1_SSC_MODE_MASK                          0x0001
#define CRG_PLL_SSC_CONFIG1_SSC_MODE_ALIGN                         0
#define CRG_PLL_SSC_CONFIG1_SSC_MODE_BITS                          1
#define CRG_PLL_SSC_CONFIG1_SSC_MODE_SHIFT                         0


/****************************************************************************
 * CRG :: PLL_SSC_CONFIG2
 ***************************************************************************/
/* CRG :: PLL_SSC_CONFIG2 :: scc_limit_low [15:00] */
#define Wr_CRG_PLL_SSC_CONFIG2_scc_limit_low(x) WriteReg16(CRG_PLL_SSC_CONFIG2,x)
#define Rd_CRG_PLL_SSC_CONFIG2_scc_limit_low(x) ReadReg16(CRG_PLL_SSC_CONFIG2)
#define CRG_PLL_SSC_CONFIG2_SCC_LIMIT_LOW_MASK                     0xffff
#define CRG_PLL_SSC_CONFIG2_SCC_LIMIT_LOW_ALIGN                    0
#define CRG_PLL_SSC_CONFIG2_SCC_LIMIT_LOW_BITS                     16
#define CRG_PLL_SSC_CONFIG2_SCC_LIMIT_LOW_SHIFT                    0


/****************************************************************************
 * CRG :: PLL_SSC_STEP
 ***************************************************************************/
/* CRG :: PLL_SSC_STEP :: SCC_step [15:00] */
#define Wr_CRG_PLL_SSC_STEP_SCC_step(x) WriteReg16(CRG_PLL_SSC_STEP,x)
#define Rd_CRG_PLL_SSC_STEP_SCC_step(x) ReadReg16(CRG_PLL_SSC_STEP)
#define CRG_PLL_SSC_STEP_SCC_STEP_MASK                             0xffff
#define CRG_PLL_SSC_STEP_SCC_STEP_ALIGN                            0
#define CRG_PLL_SSC_STEP_SCC_STEP_BITS                             16
#define CRG_PLL_SSC_STEP_SCC_STEP_SHIFT                            0


/****************************************************************************
 * CRG :: PLL_STATUS
 ***************************************************************************/
/* CRG :: PLL_STATUS :: reserved0 [15:14] */
#define CRG_PLL_STATUS_RESERVED0_MASK                              0xc000
#define CRG_PLL_STATUS_RESERVED0_ALIGN                             0
#define CRG_PLL_STATUS_RESERVED0_BITS                              2
#define CRG_PLL_STATUS_RESERVED0_SHIFT                             14

/* CRG :: PLL_STATUS :: pll_lock [13:13] */
#define Wr_CRG_PLL_STATUS_pll_lock(x) WriteRegBits16(CRG_PLL_STATUS,0x2000,13,x)
#define Rd_CRG_PLL_STATUS_pll_lock(x) ReadRegBits16(CRG_PLL_STATUS,0x2000,13)
#define CRG_PLL_STATUS_PLL_LOCK_MASK                               0x2000
#define CRG_PLL_STATUS_PLL_LOCK_ALIGN                              0
#define CRG_PLL_STATUS_PLL_LOCK_BITS                               1
#define CRG_PLL_STATUS_PLL_LOCK_SHIFT                              13

/* CRG :: PLL_STATUS :: pll_lock_lost [12:12] */
#define Wr_CRG_PLL_STATUS_pll_lock_lost(x) WriteRegBits16(CRG_PLL_STATUS,0x1000,12,x)
#define Rd_CRG_PLL_STATUS_pll_lock_lost(x) ReadRegBits16(CRG_PLL_STATUS,0x1000,12)
#define CRG_PLL_STATUS_PLL_LOCK_LOST_MASK                          0x1000
#define CRG_PLL_STATUS_PLL_LOCK_LOST_ALIGN                         0
#define CRG_PLL_STATUS_PLL_LOCK_LOST_BITS                          1
#define CRG_PLL_STATUS_PLL_LOCK_LOST_SHIFT                         12

/* CRG :: PLL_STATUS :: pll_status [11:00] */
#define Wr_CRG_PLL_STATUS_pll_status(x) WriteRegBits16(CRG_PLL_STATUS,0xfff,0,x)
#define Rd_CRG_PLL_STATUS_pll_status(x) ReadRegBits16(CRG_PLL_STATUS,0xfff,0)
#define CRG_PLL_STATUS_PLL_STATUS_MASK                             0x0fff
#define CRG_PLL_STATUS_PLL_STATUS_ALIGN                            0
#define CRG_PLL_STATUS_PLL_STATUS_BITS                             12
#define CRG_PLL_STATUS_PLL_STATUS_SHIFT                            0


/****************************************************************************
 * CRG :: CLOCK_CONFIG1
 ***************************************************************************/
/* CRG :: CLOCK_CONFIG1 :: reserved0 [15:04] */
#define CRG_CLOCK_CONFIG1_RESERVED0_MASK                           0xfff0
#define CRG_CLOCK_CONFIG1_RESERVED0_ALIGN                          0
#define CRG_CLOCK_CONFIG1_RESERVED0_BITS                           12
#define CRG_CLOCK_CONFIG1_RESERVED0_SHIFT                          4

/* CRG :: CLOCK_CONFIG1 :: sysclk_dis [03:03] */
#define Wr_CRG_CLOCK_CONFIG1_sysclk_dis(x) WriteRegBits16(CRG_CLOCK_CONFIG1,0x8,3,x)
#define Rd_CRG_CLOCK_CONFIG1_sysclk_dis(x) ReadRegBits16(CRG_CLOCK_CONFIG1,0x8,3)
#define CRG_CLOCK_CONFIG1_SYSCLK_DIS_MASK                          0x0008
#define CRG_CLOCK_CONFIG1_SYSCLK_DIS_ALIGN                         0
#define CRG_CLOCK_CONFIG1_SYSCLK_DIS_BITS                          1
#define CRG_CLOCK_CONFIG1_SYSCLK_DIS_SHIFT                         3

/* CRG :: CLOCK_CONFIG1 :: mii2_gmiiclk_dis [02:02] */
#define Wr_CRG_CLOCK_CONFIG1_mii2_gmiiclk_dis(x) WriteRegBits16(CRG_CLOCK_CONFIG1,0x4,2,x)
#define Rd_CRG_CLOCK_CONFIG1_mii2_gmiiclk_dis(x) ReadRegBits16(CRG_CLOCK_CONFIG1,0x4,2)
#define CRG_CLOCK_CONFIG1_MII2_GMIICLK_DIS_MASK                    0x0004
#define CRG_CLOCK_CONFIG1_MII2_GMIICLK_DIS_ALIGN                   0
#define CRG_CLOCK_CONFIG1_MII2_GMIICLK_DIS_BITS                    1
#define CRG_CLOCK_CONFIG1_MII2_GMIICLK_DIS_SHIFT                   2

/* CRG :: CLOCK_CONFIG1 :: mii1_gmiiclk_dis [01:01] */
#define Wr_CRG_CLOCK_CONFIG1_mii1_gmiiclk_dis(x) WriteRegBits16(CRG_CLOCK_CONFIG1,0x2,1,x)
#define Rd_CRG_CLOCK_CONFIG1_mii1_gmiiclk_dis(x) ReadRegBits16(CRG_CLOCK_CONFIG1,0x2,1)
#define CRG_CLOCK_CONFIG1_MII1_GMIICLK_DIS_MASK                    0x0002
#define CRG_CLOCK_CONFIG1_MII1_GMIICLK_DIS_ALIGN                   0
#define CRG_CLOCK_CONFIG1_MII1_GMIICLK_DIS_BITS                    1
#define CRG_CLOCK_CONFIG1_MII1_GMIICLK_DIS_SHIFT                   1

/* CRG :: CLOCK_CONFIG1 :: p7_gmiiclk_dis [00:00] */
#define Wr_CRG_CLOCK_CONFIG1_p7_gmiiclk_dis(x) WriteRegBits16(CRG_CLOCK_CONFIG1,0x1,0,x)
#define Rd_CRG_CLOCK_CONFIG1_p7_gmiiclk_dis(x) ReadRegBits16(CRG_CLOCK_CONFIG1,0x1,0)
#define CRG_CLOCK_CONFIG1_P7_GMIICLK_DIS_MASK                      0x0001
#define CRG_CLOCK_CONFIG1_P7_GMIICLK_DIS_ALIGN                     0
#define CRG_CLOCK_CONFIG1_P7_GMIICLK_DIS_BITS                      1
#define CRG_CLOCK_CONFIG1_P7_GMIICLK_DIS_SHIFT                     0


/****************************************************************************
 * CRG :: IDDQ_CHIP
 ***************************************************************************/
/* CRG :: IDDQ_CHIP :: iddq_chip [15:00] */
#define Wr_CRG_IDDQ_CHIP_iddq_chip(x) WriteReg16(CRG_IDDQ_CHIP,x)
#define Rd_CRG_IDDQ_CHIP_iddq_chip(x) ReadReg16(CRG_IDDQ_CHIP)
#define CRG_IDDQ_CHIP_IDDQ_CHIP_MASK                               0xffff
#define CRG_IDDQ_CHIP_IDDQ_CHIP_ALIGN                              0
#define CRG_IDDQ_CHIP_IDDQ_CHIP_BITS                               16
#define CRG_IDDQ_CHIP_IDDQ_CHIP_SHIFT                              0


/****************************************************************************
 * CRG :: IDDQ_CONFIG
 ***************************************************************************/
/* CRG :: IDDQ_CONFIG :: reserved0 [15:08] */
#define CRG_IDDQ_CONFIG_RESERVED0_MASK                             0xff00
#define CRG_IDDQ_CONFIG_RESERVED0_ALIGN                            0
#define CRG_IDDQ_CONFIG_RESERVED0_BITS                             8
#define CRG_IDDQ_CONFIG_RESERVED0_SHIFT                            8

/* CRG :: IDDQ_CONFIG :: iddq_rgmii2 [07:07] */
#define Wr_CRG_IDDQ_CONFIG_iddq_rgmii2(x) WriteRegBits16(CRG_IDDQ_CONFIG,0x80,7,x)
#define Rd_CRG_IDDQ_CONFIG_iddq_rgmii2(x) ReadRegBits16(CRG_IDDQ_CONFIG,0x80,7)
#define CRG_IDDQ_CONFIG_IDDQ_RGMII2_MASK                           0x0080
#define CRG_IDDQ_CONFIG_IDDQ_RGMII2_ALIGN                          0
#define CRG_IDDQ_CONFIG_IDDQ_RGMII2_BITS                           1
#define CRG_IDDQ_CONFIG_IDDQ_RGMII2_SHIFT                          7

/* CRG :: IDDQ_CONFIG :: iddq_rgmii1 [06:06] */
#define Wr_CRG_IDDQ_CONFIG_iddq_rgmii1(x) WriteRegBits16(CRG_IDDQ_CONFIG,0x40,6,x)
#define Rd_CRG_IDDQ_CONFIG_iddq_rgmii1(x) ReadRegBits16(CRG_IDDQ_CONFIG,0x40,6)
#define CRG_IDDQ_CONFIG_IDDQ_RGMII1_MASK                           0x0040
#define CRG_IDDQ_CONFIG_IDDQ_RGMII1_ALIGN                          0
#define CRG_IDDQ_CONFIG_IDDQ_RGMII1_BITS                           1
#define CRG_IDDQ_CONFIG_IDDQ_RGMII1_SHIFT                          6

/* CRG :: IDDQ_CONFIG :: iddq_sgmii [05:05] */
#define Wr_CRG_IDDQ_CONFIG_iddq_sgmii(x) WriteRegBits16(CRG_IDDQ_CONFIG,0x20,5,x)
#define Rd_CRG_IDDQ_CONFIG_iddq_sgmii(x) ReadRegBits16(CRG_IDDQ_CONFIG,0x20,5)
#define CRG_IDDQ_CONFIG_IDDQ_SGMII_MASK                            0x0020
#define CRG_IDDQ_CONFIG_IDDQ_SGMII_ALIGN                           0
#define CRG_IDDQ_CONFIG_IDDQ_SGMII_BITS                            1
#define CRG_IDDQ_CONFIG_IDDQ_SGMII_SHIFT                           5

/* CRG :: IDDQ_CONFIG :: iddq_brphy4 [04:04] */
#define Wr_CRG_IDDQ_CONFIG_iddq_brphy4(x) WriteRegBits16(CRG_IDDQ_CONFIG,0x10,4,x)
#define Rd_CRG_IDDQ_CONFIG_iddq_brphy4(x) ReadRegBits16(CRG_IDDQ_CONFIG,0x10,4)
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY4_MASK                           0x0010
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY4_ALIGN                          0
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY4_BITS                           1
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY4_SHIFT                          4

/* CRG :: IDDQ_CONFIG :: iddq_brphy3 [03:03] */
#define Wr_CRG_IDDQ_CONFIG_iddq_brphy3(x) WriteRegBits16(CRG_IDDQ_CONFIG,0x8,3,x)
#define Rd_CRG_IDDQ_CONFIG_iddq_brphy3(x) ReadRegBits16(CRG_IDDQ_CONFIG,0x8,3)
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY3_MASK                           0x0008
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY3_ALIGN                          0
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY3_BITS                           1
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY3_SHIFT                          3

/* CRG :: IDDQ_CONFIG :: iddq_brphy2 [02:02] */
#define Wr_CRG_IDDQ_CONFIG_iddq_brphy2(x) WriteRegBits16(CRG_IDDQ_CONFIG,0x4,2,x)
#define Rd_CRG_IDDQ_CONFIG_iddq_brphy2(x) ReadRegBits16(CRG_IDDQ_CONFIG,0x4,2)
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY2_MASK                           0x0004
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY2_ALIGN                          0
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY2_BITS                           1
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY2_SHIFT                          2

/* CRG :: IDDQ_CONFIG :: iddq_brphy1 [01:01] */
#define Wr_CRG_IDDQ_CONFIG_iddq_brphy1(x) WriteRegBits16(CRG_IDDQ_CONFIG,0x2,1,x)
#define Rd_CRG_IDDQ_CONFIG_iddq_brphy1(x) ReadRegBits16(CRG_IDDQ_CONFIG,0x2,1)
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY1_MASK                           0x0002
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY1_ALIGN                          0
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY1_BITS                           1
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY1_SHIFT                          1

/* CRG :: IDDQ_CONFIG :: iddq_brphy0 [00:00] */
#define Wr_CRG_IDDQ_CONFIG_iddq_brphy0(x) WriteRegBits16(CRG_IDDQ_CONFIG,0x1,0,x)
#define Rd_CRG_IDDQ_CONFIG_iddq_brphy0(x) ReadRegBits16(CRG_IDDQ_CONFIG,0x1,0)
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY0_MASK                           0x0001
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY0_ALIGN                          0
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY0_BITS                           1
#define CRG_IDDQ_CONFIG_IDDQ_BRPHY0_SHIFT                          0


/****************************************************************************
 * CRG :: RESET_CONFIG
 ***************************************************************************/
/* CRG :: RESET_CONFIG :: global_srst_en [15:15] */
#define Wr_CRG_RESET_CONFIG_global_srst_en(x) WriteRegBits16(CRG_RESET_CONFIG,0x8000,15,x)
#define Rd_CRG_RESET_CONFIG_global_srst_en(x) ReadRegBits16(CRG_RESET_CONFIG,0x8000,15)
#define CRG_RESET_CONFIG_GLOBAL_SRST_EN_MASK                       0x8000
#define CRG_RESET_CONFIG_GLOBAL_SRST_EN_ALIGN                      0
#define CRG_RESET_CONFIG_GLOBAL_SRST_EN_BITS                       1
#define CRG_RESET_CONFIG_GLOBAL_SRST_EN_SHIFT                      15

/* CRG :: RESET_CONFIG :: reserved0 [14:09] */
#define CRG_RESET_CONFIG_RESERVED0_MASK                            0x7e00
#define CRG_RESET_CONFIG_RESERVED0_ALIGN                           0
#define CRG_RESET_CONFIG_RESERVED0_BITS                            6
#define CRG_RESET_CONFIG_RESERVED0_SHIFT                           9

/* CRG :: RESET_CONFIG :: pvtmon_rst_en [08:08] */
#define Wr_CRG_RESET_CONFIG_pvtmon_rst_en(x) WriteRegBits16(CRG_RESET_CONFIG,0x100,8,x)
#define Rd_CRG_RESET_CONFIG_pvtmon_rst_en(x) ReadRegBits16(CRG_RESET_CONFIG,0x100,8)
#define CRG_RESET_CONFIG_PVTMON_RST_EN_MASK                        0x0100
#define CRG_RESET_CONFIG_PVTMON_RST_EN_ALIGN                       0
#define CRG_RESET_CONFIG_PVTMON_RST_EN_BITS                        1
#define CRG_RESET_CONFIG_PVTMON_RST_EN_SHIFT                       8

/* CRG :: RESET_CONFIG :: reserved1 [07:07] */
#define CRG_RESET_CONFIG_RESERVED1_MASK                            0x0080
#define CRG_RESET_CONFIG_RESERVED1_ALIGN                           0
#define CRG_RESET_CONFIG_RESERVED1_BITS                            1
#define CRG_RESET_CONFIG_RESERVED1_SHIFT                           7

/* CRG :: RESET_CONFIG :: srst_gmii2 [06:06] */
#define Wr_CRG_RESET_CONFIG_srst_gmii2(x) WriteRegBits16(CRG_RESET_CONFIG,0x40,6,x)
#define Rd_CRG_RESET_CONFIG_srst_gmii2(x) ReadRegBits16(CRG_RESET_CONFIG,0x40,6)
#define CRG_RESET_CONFIG_SRST_GMII2_MASK                           0x0040
#define CRG_RESET_CONFIG_SRST_GMII2_ALIGN                          0
#define CRG_RESET_CONFIG_SRST_GMII2_BITS                           1
#define CRG_RESET_CONFIG_SRST_GMII2_SHIFT                          6

/* CRG :: RESET_CONFIG :: srst_gmii1 [05:05] */
#define Wr_CRG_RESET_CONFIG_srst_gmii1(x) WriteRegBits16(CRG_RESET_CONFIG,0x20,5,x)
#define Rd_CRG_RESET_CONFIG_srst_gmii1(x) ReadRegBits16(CRG_RESET_CONFIG,0x20,5)
#define CRG_RESET_CONFIG_SRST_GMII1_MASK                           0x0020
#define CRG_RESET_CONFIG_SRST_GMII1_ALIGN                          0
#define CRG_RESET_CONFIG_SRST_GMII1_BITS                           1
#define CRG_RESET_CONFIG_SRST_GMII1_SHIFT                          5

/* CRG :: RESET_CONFIG :: srst_sgmii [04:04] */
#define Wr_CRG_RESET_CONFIG_srst_sgmii(x) WriteRegBits16(CRG_RESET_CONFIG,0x10,4,x)
#define Rd_CRG_RESET_CONFIG_srst_sgmii(x) ReadRegBits16(CRG_RESET_CONFIG,0x10,4)
#define CRG_RESET_CONFIG_SRST_SGMII_MASK                           0x0010
#define CRG_RESET_CONFIG_SRST_SGMII_ALIGN                          0
#define CRG_RESET_CONFIG_SRST_SGMII_BITS                           1
#define CRG_RESET_CONFIG_SRST_SGMII_SHIFT                          4

/* CRG :: RESET_CONFIG :: srst_soc [03:03] */
#define Wr_CRG_RESET_CONFIG_srst_soc(x) WriteRegBits16(CRG_RESET_CONFIG,0x8,3,x)
#define Rd_CRG_RESET_CONFIG_srst_soc(x) ReadRegBits16(CRG_RESET_CONFIG,0x8,3)
#define CRG_RESET_CONFIG_SRST_SOC_MASK                             0x0008
#define CRG_RESET_CONFIG_SRST_SOC_ALIGN                            0
#define CRG_RESET_CONFIG_SRST_SOC_BITS                             1
#define CRG_RESET_CONFIG_SRST_SOC_SHIFT                            3

/* CRG :: RESET_CONFIG :: srst_switch [02:02] */
#define Wr_CRG_RESET_CONFIG_srst_switch(x) WriteRegBits16(CRG_RESET_CONFIG,0x4,2,x)
#define Rd_CRG_RESET_CONFIG_srst_switch(x) ReadRegBits16(CRG_RESET_CONFIG,0x4,2)
#define CRG_RESET_CONFIG_SRST_SWITCH_MASK                          0x0004
#define CRG_RESET_CONFIG_SRST_SWITCH_ALIGN                         0
#define CRG_RESET_CONFIG_SRST_SWITCH_BITS                          1
#define CRG_RESET_CONFIG_SRST_SWITCH_SHIFT                         2

/* CRG :: RESET_CONFIG :: srst_brphys [01:01] */
#define Wr_CRG_RESET_CONFIG_srst_brphys(x) WriteRegBits16(CRG_RESET_CONFIG,0x2,1,x)
#define Rd_CRG_RESET_CONFIG_srst_brphys(x) ReadRegBits16(CRG_RESET_CONFIG,0x2,1)
#define CRG_RESET_CONFIG_SRST_BRPHYS_MASK                          0x0002
#define CRG_RESET_CONFIG_SRST_BRPHYS_ALIGN                         0
#define CRG_RESET_CONFIG_SRST_BRPHYS_BITS                          1
#define CRG_RESET_CONFIG_SRST_BRPHYS_SHIFT                         1

/* CRG :: RESET_CONFIG :: srst_chip [00:00] */
#define Wr_CRG_RESET_CONFIG_srst_chip(x) WriteRegBits16(CRG_RESET_CONFIG,0x1,0,x)
#define Rd_CRG_RESET_CONFIG_srst_chip(x) ReadRegBits16(CRG_RESET_CONFIG,0x1,0)
#define CRG_RESET_CONFIG_SRST_CHIP_MASK                            0x0001
#define CRG_RESET_CONFIG_SRST_CHIP_ALIGN                           0
#define CRG_RESET_CONFIG_SRST_CHIP_BITS                            1
#define CRG_RESET_CONFIG_SRST_CHIP_SHIFT                           0


/****************************************************************************
 * CRG :: SCRATCH_REG
 ***************************************************************************/
/* CRG :: SCRATCH_REG :: scratch [15:00] */
#define Wr_CRG_SCRATCH_REG_scratch(x) WriteReg16(CRG_SCRATCH_REG,x)
#define Rd_CRG_SCRATCH_REG_scratch(x) ReadReg16(CRG_SCRATCH_REG)
#define CRG_SCRATCH_REG_SCRATCH_MASK                               0xffff
#define CRG_SCRATCH_REG_SCRATCH_ALIGN                              0
#define CRG_SCRATCH_REG_SCRATCH_BITS                               16
#define CRG_SCRATCH_REG_SCRATCH_SHIFT                              0


/****************************************************************************
 * bcm89530_top_bridge_IO
 ***************************************************************************/
/****************************************************************************
 * IO :: MII1_CONFIG
 ***************************************************************************/
/* IO :: MII1_CONFIG :: clock_en_mii1 [15:15] */
#define Wr_IO_MII1_CONFIG_clock_en_mii1(x) WriteRegBits16(IO_MII1_CONFIG,0x8000,15,x)
#define Rd_IO_MII1_CONFIG_clock_en_mii1(x) ReadRegBits16(IO_MII1_CONFIG,0x8000,15)
#define IO_MII1_CONFIG_CLOCK_EN_MII1_MASK                          0x8000
#define IO_MII1_CONFIG_CLOCK_EN_MII1_ALIGN                         0
#define IO_MII1_CONFIG_CLOCK_EN_MII1_BITS                          1
#define IO_MII1_CONFIG_CLOCK_EN_MII1_SHIFT                         15

/* IO :: MII1_CONFIG :: reserved0 [14:07] */
#define IO_MII1_CONFIG_RESERVED0_MASK                              0x7f80
#define IO_MII1_CONFIG_RESERVED0_ALIGN                             0
#define IO_MII1_CONFIG_RESERVED0_BITS                              8
#define IO_MII1_CONFIG_RESERVED0_SHIFT                             7

/* IO :: MII1_CONFIG :: src_mii1 [06:05] */
#define Wr_IO_MII1_CONFIG_src_mii1(x) WriteRegBits16(IO_MII1_CONFIG,0x60,5,x)
#define Rd_IO_MII1_CONFIG_src_mii1(x) ReadRegBits16(IO_MII1_CONFIG,0x60,5)
#define IO_MII1_CONFIG_SRC_MII1_MASK                               0x0060
#define IO_MII1_CONFIG_SRC_MII1_ALIGN                              0
#define IO_MII1_CONFIG_SRC_MII1_BITS                               2
#define IO_MII1_CONFIG_SRC_MII1_SHIFT                              5

/* IO :: MII1_CONFIG :: amp_enable_mii1 [04:04] */
#define Wr_IO_MII1_CONFIG_amp_enable_mii1(x) WriteRegBits16(IO_MII1_CONFIG,0x10,4,x)
#define Rd_IO_MII1_CONFIG_amp_enable_mii1(x) ReadRegBits16(IO_MII1_CONFIG,0x10,4)
#define IO_MII1_CONFIG_AMP_ENABLE_MII1_MASK                        0x0010
#define IO_MII1_CONFIG_AMP_ENABLE_MII1_ALIGN                       0
#define IO_MII1_CONFIG_AMP_ENABLE_MII1_BITS                        1
#define IO_MII1_CONFIG_AMP_ENABLE_MII1_SHIFT                       4

/* IO :: MII1_CONFIG :: sel_mii1 [03:01] */
#define Wr_IO_MII1_CONFIG_sel_mii1(x) WriteRegBits16(IO_MII1_CONFIG,0xe,1,x)
#define Rd_IO_MII1_CONFIG_sel_mii1(x) ReadRegBits16(IO_MII1_CONFIG,0xe,1)
#define IO_MII1_CONFIG_SEL_MII1_MASK                               0x000e
#define IO_MII1_CONFIG_SEL_MII1_ALIGN                              0
#define IO_MII1_CONFIG_SEL_MII1_BITS                               3
#define IO_MII1_CONFIG_SEL_MII1_SHIFT                              1

/* IO :: MII1_CONFIG :: spare [00:00] */
#define Wr_IO_MII1_CONFIG_spare(x) WriteRegBits16(IO_MII1_CONFIG,0x1,0,x)
#define Rd_IO_MII1_CONFIG_spare(x) ReadRegBits16(IO_MII1_CONFIG,0x1,0)
#define IO_MII1_CONFIG_SPARE_MASK                                  0x0001
#define IO_MII1_CONFIG_SPARE_ALIGN                                 0
#define IO_MII1_CONFIG_SPARE_BITS                                  1
#define IO_MII1_CONFIG_SPARE_SHIFT                                 0


/****************************************************************************
 * IO :: MII2_CONFIG
 ***************************************************************************/
/* IO :: MII2_CONFIG :: clock_en_mii2 [15:15] */
#define Wr_IO_MII2_CONFIG_clock_en_mii2(x) WriteRegBits16(IO_MII2_CONFIG,0x8000,15,x)
#define Rd_IO_MII2_CONFIG_clock_en_mii2(x) ReadRegBits16(IO_MII2_CONFIG,0x8000,15)
#define IO_MII2_CONFIG_CLOCK_EN_MII2_MASK                          0x8000
#define IO_MII2_CONFIG_CLOCK_EN_MII2_ALIGN                         0
#define IO_MII2_CONFIG_CLOCK_EN_MII2_BITS                          1
#define IO_MII2_CONFIG_CLOCK_EN_MII2_SHIFT                         15

/* IO :: MII2_CONFIG :: reserved0 [14:07] */
#define IO_MII2_CONFIG_RESERVED0_MASK                              0x7f80
#define IO_MII2_CONFIG_RESERVED0_ALIGN                             0
#define IO_MII2_CONFIG_RESERVED0_BITS                              8
#define IO_MII2_CONFIG_RESERVED0_SHIFT                             7

/* IO :: MII2_CONFIG :: src_mii2 [06:05] */
#define Wr_IO_MII2_CONFIG_src_mii2(x) WriteRegBits16(IO_MII2_CONFIG,0x60,5,x)
#define Rd_IO_MII2_CONFIG_src_mii2(x) ReadRegBits16(IO_MII2_CONFIG,0x60,5)
#define IO_MII2_CONFIG_SRC_MII2_MASK                               0x0060
#define IO_MII2_CONFIG_SRC_MII2_ALIGN                              0
#define IO_MII2_CONFIG_SRC_MII2_BITS                               2
#define IO_MII2_CONFIG_SRC_MII2_SHIFT                              5

/* IO :: MII2_CONFIG :: amp_enable_mii2 [04:04] */
#define Wr_IO_MII2_CONFIG_amp_enable_mii2(x) WriteRegBits16(IO_MII2_CONFIG,0x10,4,x)
#define Rd_IO_MII2_CONFIG_amp_enable_mii2(x) ReadRegBits16(IO_MII2_CONFIG,0x10,4)
#define IO_MII2_CONFIG_AMP_ENABLE_MII2_MASK                        0x0010
#define IO_MII2_CONFIG_AMP_ENABLE_MII2_ALIGN                       0
#define IO_MII2_CONFIG_AMP_ENABLE_MII2_BITS                        1
#define IO_MII2_CONFIG_AMP_ENABLE_MII2_SHIFT                       4

/* IO :: MII2_CONFIG :: sel_mii2 [03:01] */
#define Wr_IO_MII2_CONFIG_sel_mii2(x) WriteRegBits16(IO_MII2_CONFIG,0xe,1,x)
#define Rd_IO_MII2_CONFIG_sel_mii2(x) ReadRegBits16(IO_MII2_CONFIG,0xe,1)
#define IO_MII2_CONFIG_SEL_MII2_MASK                               0x000e
#define IO_MII2_CONFIG_SEL_MII2_ALIGN                              0
#define IO_MII2_CONFIG_SEL_MII2_BITS                               3
#define IO_MII2_CONFIG_SEL_MII2_SHIFT                              1

/* IO :: MII2_CONFIG :: spare [00:00] */
#define Wr_IO_MII2_CONFIG_spare(x) WriteRegBits16(IO_MII2_CONFIG,0x1,0,x)
#define Rd_IO_MII2_CONFIG_spare(x) ReadRegBits16(IO_MII2_CONFIG,0x1,0)
#define IO_MII2_CONFIG_SPARE_MASK                                  0x0001
#define IO_MII2_CONFIG_SPARE_ALIGN                                 0
#define IO_MII2_CONFIG_SPARE_BITS                                  1
#define IO_MII2_CONFIG_SPARE_SHIFT                                 0


/****************************************************************************
 * IO :: IO_HYSTERESIS
 ***************************************************************************/
/* IO :: IO_HYSTERESIS :: reserved0 [15:05] */
#define IO_IO_HYSTERESIS_RESERVED0_MASK                            0xffe0
#define IO_IO_HYSTERESIS_RESERVED0_ALIGN                           0
#define IO_IO_HYSTERESIS_RESERVED0_BITS                            11
#define IO_IO_HYSTERESIS_RESERVED0_SHIFT                           5

/* IO :: IO_HYSTERESIS :: io_hys [04:00] */
#define Wr_IO_IO_HYSTERESIS_io_hys(x) WriteRegBits16(IO_IO_HYSTERESIS,0x1f,0,x)
#define Rd_IO_IO_HYSTERESIS_io_hys(x) ReadRegBits16(IO_IO_HYSTERESIS,0x1f,0)
#define IO_IO_HYSTERESIS_IO_HYS_MASK                               0x001f
#define IO_IO_HYSTERESIS_IO_HYS_ALIGN                              0
#define IO_IO_HYSTERESIS_IO_HYS_BITS                               5
#define IO_IO_HYSTERESIS_IO_HYS_SHIFT                              0


/****************************************************************************
 * IO :: IO_SOURCE
 ***************************************************************************/
/* IO :: IO_SOURCE :: reserved0 [15:05] */
#define IO_IO_SOURCE_RESERVED0_MASK                                0xffe0
#define IO_IO_SOURCE_RESERVED0_ALIGN                               0
#define IO_IO_SOURCE_RESERVED0_BITS                                11
#define IO_IO_SOURCE_RESERVED0_SHIFT                               5

/* IO :: IO_SOURCE :: io_src [04:00] */
#define Wr_IO_IO_SOURCE_io_src(x) WriteRegBits16(IO_IO_SOURCE,0x1f,0,x)
#define Rd_IO_IO_SOURCE_io_src(x) ReadRegBits16(IO_IO_SOURCE,0x1f,0)
#define IO_IO_SOURCE_IO_SRC_MASK                                   0x001f
#define IO_IO_SOURCE_IO_SRC_ALIGN                                  0
#define IO_IO_SOURCE_IO_SRC_BITS                                   5
#define IO_IO_SOURCE_IO_SRC_SHIFT                                  0


/****************************************************************************
 * IO :: IO_SEL
 ***************************************************************************/
/* IO :: IO_SEL :: reserved0 [15:15] */
#define IO_IO_SEL_RESERVED0_MASK                                   0x8000
#define IO_IO_SEL_RESERVED0_ALIGN                                  0
#define IO_IO_SEL_RESERVED0_BITS                                   1
#define IO_IO_SEL_RESERVED0_SHIFT                                  15

/* IO :: IO_SEL :: io_sel_flash [14:12] */
#define Wr_IO_IO_SEL_io_sel_flash(x) WriteRegBits16(IO_IO_SEL,0x7000,12,x)
#define Rd_IO_IO_SEL_io_sel_flash(x) ReadRegBits16(IO_IO_SEL,0x7000,12)
#define IO_IO_SEL_IO_SEL_FLASH_MASK                                0x7000
#define IO_IO_SEL_IO_SEL_FLASH_ALIGN                               0
#define IO_IO_SEL_IO_SEL_FLASH_BITS                                3
#define IO_IO_SEL_IO_SEL_FLASH_SHIFT                               12

/* IO :: IO_SEL :: io_sel_misc [11:09] */
#define Wr_IO_IO_SEL_io_sel_misc(x) WriteRegBits16(IO_IO_SEL,0xe00,9,x)
#define Rd_IO_IO_SEL_io_sel_misc(x) ReadRegBits16(IO_IO_SEL,0xe00,9)
#define IO_IO_SEL_IO_SEL_MISC_MASK                                 0x0e00
#define IO_IO_SEL_IO_SEL_MISC_ALIGN                                0
#define IO_IO_SEL_IO_SEL_MISC_BITS                                 3
#define IO_IO_SEL_IO_SEL_MISC_SHIFT                                9

/* IO :: IO_SEL :: io_sel_i2c [08:06] */
#define Wr_IO_IO_SEL_io_sel_i2c(x) WriteRegBits16(IO_IO_SEL,0x1c0,6,x)
#define Rd_IO_IO_SEL_io_sel_i2c(x) ReadRegBits16(IO_IO_SEL,0x1c0,6)
#define IO_IO_SEL_IO_SEL_I2C_MASK                                  0x01c0
#define IO_IO_SEL_IO_SEL_I2C_ALIGN                                 0
#define IO_IO_SEL_IO_SEL_I2C_BITS                                  3
#define IO_IO_SEL_IO_SEL_I2C_SHIFT                                 6

/* IO :: IO_SEL :: io_sel_gpio [05:03] */
#define Wr_IO_IO_SEL_io_sel_gpio(x) WriteRegBits16(IO_IO_SEL,0x38,3,x)
#define Rd_IO_IO_SEL_io_sel_gpio(x) ReadRegBits16(IO_IO_SEL,0x38,3)
#define IO_IO_SEL_IO_SEL_GPIO_MASK                                 0x0038
#define IO_IO_SEL_IO_SEL_GPIO_ALIGN                                0
#define IO_IO_SEL_IO_SEL_GPIO_BITS                                 3
#define IO_IO_SEL_IO_SEL_GPIO_SHIFT                                3

/* IO :: IO_SEL :: io_sel_spi_slv [02:00] */
#define Wr_IO_IO_SEL_io_sel_spi_slv(x) WriteRegBits16(IO_IO_SEL,0x7,0,x)
#define Rd_IO_IO_SEL_io_sel_spi_slv(x) ReadRegBits16(IO_IO_SEL,0x7,0)
#define IO_IO_SEL_IO_SEL_SPI_SLV_MASK                              0x0007
#define IO_IO_SEL_IO_SEL_SPI_SLV_ALIGN                             0
#define IO_IO_SEL_IO_SEL_SPI_SLV_BITS                              3
#define IO_IO_SEL_IO_SEL_SPI_SLV_SHIFT                             0


/****************************************************************************
 * IO :: IO_MII1_MODEHV
 ***************************************************************************/
/* IO :: IO_MII1_MODEHV :: reserved0 [15:01] */
#define IO_IO_MII1_MODEHV_RESERVED0_MASK                           0xfffe
#define IO_IO_MII1_MODEHV_RESERVED0_ALIGN                          0
#define IO_IO_MII1_MODEHV_RESERVED0_BITS                           15
#define IO_IO_MII1_MODEHV_RESERVED0_SHIFT                          1

/* IO :: IO_MII1_MODEHV :: MII1_MODEHV [00:00] */
#define Wr_IO_IO_MII1_MODEHV_MII1_MODEHV(x) WriteRegBits16(IO_IO_MII1_MODEHV,0x1,0,x)
#define Rd_IO_IO_MII1_MODEHV_MII1_MODEHV(x) ReadRegBits16(IO_IO_MII1_MODEHV,0x1,0)
#define IO_IO_MII1_MODEHV_MII1_MODEHV_MASK                         0x0001
#define IO_IO_MII1_MODEHV_MII1_MODEHV_ALIGN                        0
#define IO_IO_MII1_MODEHV_MII1_MODEHV_BITS                         1
#define IO_IO_MII1_MODEHV_MII1_MODEHV_SHIFT                        0


/****************************************************************************
 * IO :: IO_MII2_MODEHV
 ***************************************************************************/
/* IO :: IO_MII2_MODEHV :: reserved0 [15:01] */
#define IO_IO_MII2_MODEHV_RESERVED0_MASK                           0xfffe
#define IO_IO_MII2_MODEHV_RESERVED0_ALIGN                          0
#define IO_IO_MII2_MODEHV_RESERVED0_BITS                           15
#define IO_IO_MII2_MODEHV_RESERVED0_SHIFT                          1

/* IO :: IO_MII2_MODEHV :: MII1_MODEHV [00:00] */
#define Wr_IO_IO_MII2_MODEHV_MII1_MODEHV(x) WriteRegBits16(IO_IO_MII2_MODEHV,0x1,0,x)
#define Rd_IO_IO_MII2_MODEHV_MII1_MODEHV(x) ReadRegBits16(IO_IO_MII2_MODEHV,0x1,0)
#define IO_IO_MII2_MODEHV_MII1_MODEHV_MASK                         0x0001
#define IO_IO_MII2_MODEHV_MII1_MODEHV_ALIGN                        0
#define IO_IO_MII2_MODEHV_MII1_MODEHV_BITS                         1
#define IO_IO_MII2_MODEHV_MII1_MODEHV_SHIFT                        0


/****************************************************************************
 * IO :: RGMII1_CTL
 ***************************************************************************/
/* IO :: RGMII1_CTL :: dis_imp [15:15] */
#define Wr_IO_RGMII1_CTL_dis_imp(x) WriteRegBits16(IO_RGMII1_CTL,0x8000,15,x)
#define Rd_IO_RGMII1_CTL_dis_imp(x) ReadRegBits16(IO_RGMII1_CTL,0x8000,15)
#define IO_RGMII1_CTL_DIS_IMP_MASK                                 0x8000
#define IO_RGMII1_CTL_DIS_IMP_ALIGN                                0
#define IO_RGMII1_CTL_DIS_IMP_BITS                                 1
#define IO_RGMII1_CTL_DIS_IMP_SHIFT                                15

/* IO :: RGMII1_CTL :: reserved0 [14:04] */
#define IO_RGMII1_CTL_RESERVED0_MASK                               0x7ff0
#define IO_RGMII1_CTL_RESERVED0_ALIGN                              0
#define IO_RGMII1_CTL_RESERVED0_BITS                               11
#define IO_RGMII1_CTL_RESERVED0_SHIFT                              4

/* IO :: RGMII1_CTL :: rmii_clock_direction [03:03] */
#define Wr_IO_RGMII1_CTL_rmii_clock_direction(x) WriteRegBits16(IO_RGMII1_CTL,0x8,3,x)
#define Rd_IO_RGMII1_CTL_rmii_clock_direction(x) ReadRegBits16(IO_RGMII1_CTL,0x8,3)
#define IO_RGMII1_CTL_RMII_CLOCK_DIRECTION_MASK                    0x0008
#define IO_RGMII1_CTL_RMII_CLOCK_DIRECTION_ALIGN                   0
#define IO_RGMII1_CTL_RMII_CLOCK_DIRECTION_BITS                    1
#define IO_RGMII1_CTL_RMII_CLOCK_DIRECTION_SHIFT                   3

/* IO :: RGMII1_CTL :: rgmii1_ctl [02:01] */
#define Wr_IO_RGMII1_CTL_rgmii1_ctl(x) WriteRegBits16(IO_RGMII1_CTL,0x6,1,x)
#define Rd_IO_RGMII1_CTL_rgmii1_ctl(x) ReadRegBits16(IO_RGMII1_CTL,0x6,1)
#define IO_RGMII1_CTL_RGMII1_CTL_MASK                              0x0006
#define IO_RGMII1_CTL_RGMII1_CTL_ALIGN                             0
#define IO_RGMII1_CTL_RGMII1_CTL_BITS                              2
#define IO_RGMII1_CTL_RGMII1_CTL_SHIFT                             1

/* IO :: RGMII1_CTL :: rgmii1_bypass_imp_2ns_del [00:00] */
#define Wr_IO_RGMII1_CTL_rgmii1_bypass_imp_2ns_del(x) WriteRegBits16(IO_RGMII1_CTL,0x1,0,x)
#define Rd_IO_RGMII1_CTL_rgmii1_bypass_imp_2ns_del(x) ReadRegBits16(IO_RGMII1_CTL,0x1,0)
#define IO_RGMII1_CTL_RGMII1_BYPASS_IMP_2NS_DEL_MASK               0x0001
#define IO_RGMII1_CTL_RGMII1_BYPASS_IMP_2NS_DEL_ALIGN              0
#define IO_RGMII1_CTL_RGMII1_BYPASS_IMP_2NS_DEL_BITS               1
#define IO_RGMII1_CTL_RGMII1_BYPASS_IMP_2NS_DEL_SHIFT              0


/****************************************************************************
 * IO :: RGMII2_CTL
 ***************************************************************************/
/* IO :: RGMII2_CTL :: dis_imp [15:15] */
#define Wr_IO_RGMII2_CTL_dis_imp(x) WriteRegBits16(IO_RGMII2_CTL,0x8000,15,x)
#define Rd_IO_RGMII2_CTL_dis_imp(x) ReadRegBits16(IO_RGMII2_CTL,0x8000,15)
#define IO_RGMII2_CTL_DIS_IMP_MASK                                 0x8000
#define IO_RGMII2_CTL_DIS_IMP_ALIGN                                0
#define IO_RGMII2_CTL_DIS_IMP_BITS                                 1
#define IO_RGMII2_CTL_DIS_IMP_SHIFT                                15

/* IO :: RGMII2_CTL :: reserved0 [14:04] */
#define IO_RGMII2_CTL_RESERVED0_MASK                               0x7ff0
#define IO_RGMII2_CTL_RESERVED0_ALIGN                              0
#define IO_RGMII2_CTL_RESERVED0_BITS                               11
#define IO_RGMII2_CTL_RESERVED0_SHIFT                              4

/* IO :: RGMII2_CTL :: rmii_clock_direction [03:03] */
#define Wr_IO_RGMII2_CTL_rmii_clock_direction(x) WriteRegBits16(IO_RGMII2_CTL,0x8,3,x)
#define Rd_IO_RGMII2_CTL_rmii_clock_direction(x) ReadRegBits16(IO_RGMII2_CTL,0x8,3)
#define IO_RGMII2_CTL_RMII_CLOCK_DIRECTION_MASK                    0x0008
#define IO_RGMII2_CTL_RMII_CLOCK_DIRECTION_ALIGN                   0
#define IO_RGMII2_CTL_RMII_CLOCK_DIRECTION_BITS                    1
#define IO_RGMII2_CTL_RMII_CLOCK_DIRECTION_SHIFT                   3

/* IO :: RGMII2_CTL :: rgmii2_ctl [02:01] */
#define Wr_IO_RGMII2_CTL_rgmii2_ctl(x) WriteRegBits16(IO_RGMII2_CTL,0x6,1,x)
#define Rd_IO_RGMII2_CTL_rgmii2_ctl(x) ReadRegBits16(IO_RGMII2_CTL,0x6,1)
#define IO_RGMII2_CTL_RGMII2_CTL_MASK                              0x0006
#define IO_RGMII2_CTL_RGMII2_CTL_ALIGN                             0
#define IO_RGMII2_CTL_RGMII2_CTL_BITS                              2
#define IO_RGMII2_CTL_RGMII2_CTL_SHIFT                             1

/* IO :: RGMII2_CTL :: rgmii2_bypass_imp_2ns_del [00:00] */
#define Wr_IO_RGMII2_CTL_rgmii2_bypass_imp_2ns_del(x) WriteRegBits16(IO_RGMII2_CTL,0x1,0,x)
#define Rd_IO_RGMII2_CTL_rgmii2_bypass_imp_2ns_del(x) ReadRegBits16(IO_RGMII2_CTL,0x1,0)
#define IO_RGMII2_CTL_RGMII2_BYPASS_IMP_2NS_DEL_MASK               0x0001
#define IO_RGMII2_CTL_RGMII2_BYPASS_IMP_2NS_DEL_ALIGN              0
#define IO_RGMII2_CTL_RGMII2_BYPASS_IMP_2NS_DEL_BITS               1
#define IO_RGMII2_CTL_RGMII2_BYPASS_IMP_2NS_DEL_SHIFT              0


/****************************************************************************
 * IO :: SGMII_RGMII_CTL
 ***************************************************************************/
/* IO :: SGMII_RGMII_CTL :: reserved0 [15:02] */
#define IO_SGMII_RGMII_CTL_RESERVED0_MASK                          0xfffc
#define IO_SGMII_RGMII_CTL_RESERVED0_ALIGN                         0
#define IO_SGMII_RGMII_CTL_RESERVED0_BITS                          14
#define IO_SGMII_RGMII_CTL_RESERVED0_SHIFT                         2

/* IO :: SGMII_RGMII_CTL :: sel_sgmii_rgmii1 [01:01] */
#define Wr_IO_SGMII_RGMII_CTL_sel_sgmii_rgmii1(x) WriteRegBits16(IO_SGMII_RGMII_CTL,0x2,1,x)
#define Rd_IO_SGMII_RGMII_CTL_sel_sgmii_rgmii1(x) ReadRegBits16(IO_SGMII_RGMII_CTL,0x2,1)
#define IO_SGMII_RGMII_CTL_SEL_SGMII_RGMII1_MASK                   0x0002
#define IO_SGMII_RGMII_CTL_SEL_SGMII_RGMII1_ALIGN                  0
#define IO_SGMII_RGMII_CTL_SEL_SGMII_RGMII1_BITS                   1
#define IO_SGMII_RGMII_CTL_SEL_SGMII_RGMII1_SHIFT                  1

/* IO :: SGMII_RGMII_CTL :: sel_sgmii_rgmii2 [00:00] */
#define Wr_IO_SGMII_RGMII_CTL_sel_sgmii_rgmii2(x) WriteRegBits16(IO_SGMII_RGMII_CTL,0x1,0,x)
#define Rd_IO_SGMII_RGMII_CTL_sel_sgmii_rgmii2(x) ReadRegBits16(IO_SGMII_RGMII_CTL,0x1,0)
#define IO_SGMII_RGMII_CTL_SEL_SGMII_RGMII2_MASK                   0x0001
#define IO_SGMII_RGMII_CTL_SEL_SGMII_RGMII2_ALIGN                  0
#define IO_SGMII_RGMII_CTL_SEL_SGMII_RGMII2_BITS                   1
#define IO_SGMII_RGMII_CTL_SEL_SGMII_RGMII2_SHIFT                  0


/****************************************************************************
 * IO :: RGMII1_GMII_CTL
 ***************************************************************************/
/* IO :: RGMII1_GMII_CTL :: reserved0 [15:05] */
#define IO_RGMII1_GMII_CTL_RESERVED0_MASK                          0xffe0
#define IO_RGMII1_GMII_CTL_RESERVED0_ALIGN                         0
#define IO_RGMII1_GMII_CTL_RESERVED0_BITS                          11
#define IO_RGMII1_GMII_CTL_RESERVED0_SHIFT                         5

/* IO :: RGMII1_GMII_CTL :: rgmii_rx_pause [04:04] */
#define Wr_IO_RGMII1_GMII_CTL_rgmii_rx_pause(x) WriteRegBits16(IO_RGMII1_GMII_CTL,0x10,4,x)
#define Rd_IO_RGMII1_GMII_CTL_rgmii_rx_pause(x) ReadRegBits16(IO_RGMII1_GMII_CTL,0x10,4)
#define IO_RGMII1_GMII_CTL_RGMII_RX_PAUSE_MASK                     0x0010
#define IO_RGMII1_GMII_CTL_RGMII_RX_PAUSE_ALIGN                    0
#define IO_RGMII1_GMII_CTL_RGMII_RX_PAUSE_BITS                     1
#define IO_RGMII1_GMII_CTL_RGMII_RX_PAUSE_SHIFT                    4

/* IO :: RGMII1_GMII_CTL :: rgmii_tx_pause [03:03] */
#define Wr_IO_RGMII1_GMII_CTL_rgmii_tx_pause(x) WriteRegBits16(IO_RGMII1_GMII_CTL,0x8,3,x)
#define Rd_IO_RGMII1_GMII_CTL_rgmii_tx_pause(x) ReadRegBits16(IO_RGMII1_GMII_CTL,0x8,3)
#define IO_RGMII1_GMII_CTL_RGMII_TX_PAUSE_MASK                     0x0008
#define IO_RGMII1_GMII_CTL_RGMII_TX_PAUSE_ALIGN                    0
#define IO_RGMII1_GMII_CTL_RGMII_TX_PAUSE_BITS                     1
#define IO_RGMII1_GMII_CTL_RGMII_TX_PAUSE_SHIFT                    3

/* IO :: RGMII1_GMII_CTL :: rgmii_link [02:02] */
#define Wr_IO_RGMII1_GMII_CTL_rgmii_link(x) WriteRegBits16(IO_RGMII1_GMII_CTL,0x4,2,x)
#define Rd_IO_RGMII1_GMII_CTL_rgmii_link(x) ReadRegBits16(IO_RGMII1_GMII_CTL,0x4,2)
#define IO_RGMII1_GMII_CTL_RGMII_LINK_MASK                         0x0004
#define IO_RGMII1_GMII_CTL_RGMII_LINK_ALIGN                        0
#define IO_RGMII1_GMII_CTL_RGMII_LINK_BITS                         1
#define IO_RGMII1_GMII_CTL_RGMII_LINK_SHIFT                        2

/* IO :: RGMII1_GMII_CTL :: rgmii_spd [01:00] */
#define Wr_IO_RGMII1_GMII_CTL_rgmii_spd(x) WriteRegBits16(IO_RGMII1_GMII_CTL,0x3,0,x)
#define Rd_IO_RGMII1_GMII_CTL_rgmii_spd(x) ReadRegBits16(IO_RGMII1_GMII_CTL,0x3,0)
#define IO_RGMII1_GMII_CTL_RGMII_SPD_MASK                          0x0003
#define IO_RGMII1_GMII_CTL_RGMII_SPD_ALIGN                         0
#define IO_RGMII1_GMII_CTL_RGMII_SPD_BITS                          2
#define IO_RGMII1_GMII_CTL_RGMII_SPD_SHIFT                         0


/****************************************************************************
 * IO :: RGMII2_GMII_CTL
 ***************************************************************************/
/* IO :: RGMII2_GMII_CTL :: reserved0 [15:05] */
#define IO_RGMII2_GMII_CTL_RESERVED0_MASK                          0xffe0
#define IO_RGMII2_GMII_CTL_RESERVED0_ALIGN                         0
#define IO_RGMII2_GMII_CTL_RESERVED0_BITS                          11
#define IO_RGMII2_GMII_CTL_RESERVED0_SHIFT                         5

/* IO :: RGMII2_GMII_CTL :: rgmii_rx_pause [04:04] */
#define Wr_IO_RGMII2_GMII_CTL_rgmii_rx_pause(x) WriteRegBits16(IO_RGMII2_GMII_CTL,0x10,4,x)
#define Rd_IO_RGMII2_GMII_CTL_rgmii_rx_pause(x) ReadRegBits16(IO_RGMII2_GMII_CTL,0x10,4)
#define IO_RGMII2_GMII_CTL_RGMII_RX_PAUSE_MASK                     0x0010
#define IO_RGMII2_GMII_CTL_RGMII_RX_PAUSE_ALIGN                    0
#define IO_RGMII2_GMII_CTL_RGMII_RX_PAUSE_BITS                     1
#define IO_RGMII2_GMII_CTL_RGMII_RX_PAUSE_SHIFT                    4

/* IO :: RGMII2_GMII_CTL :: rgmii_tx_pause [03:03] */
#define Wr_IO_RGMII2_GMII_CTL_rgmii_tx_pause(x) WriteRegBits16(IO_RGMII2_GMII_CTL,0x8,3,x)
#define Rd_IO_RGMII2_GMII_CTL_rgmii_tx_pause(x) ReadRegBits16(IO_RGMII2_GMII_CTL,0x8,3)
#define IO_RGMII2_GMII_CTL_RGMII_TX_PAUSE_MASK                     0x0008
#define IO_RGMII2_GMII_CTL_RGMII_TX_PAUSE_ALIGN                    0
#define IO_RGMII2_GMII_CTL_RGMII_TX_PAUSE_BITS                     1
#define IO_RGMII2_GMII_CTL_RGMII_TX_PAUSE_SHIFT                    3

/* IO :: RGMII2_GMII_CTL :: rgmii_link [02:02] */
#define Wr_IO_RGMII2_GMII_CTL_rgmii_link(x) WriteRegBits16(IO_RGMII2_GMII_CTL,0x4,2,x)
#define Rd_IO_RGMII2_GMII_CTL_rgmii_link(x) ReadRegBits16(IO_RGMII2_GMII_CTL,0x4,2)
#define IO_RGMII2_GMII_CTL_RGMII_LINK_MASK                         0x0004
#define IO_RGMII2_GMII_CTL_RGMII_LINK_ALIGN                        0
#define IO_RGMII2_GMII_CTL_RGMII_LINK_BITS                         1
#define IO_RGMII2_GMII_CTL_RGMII_LINK_SHIFT                        2

/* IO :: RGMII2_GMII_CTL :: rgmii_spd [01:00] */
#define Wr_IO_RGMII2_GMII_CTL_rgmii_spd(x) WriteRegBits16(IO_RGMII2_GMII_CTL,0x3,0,x)
#define Rd_IO_RGMII2_GMII_CTL_rgmii_spd(x) ReadRegBits16(IO_RGMII2_GMII_CTL,0x3,0)
#define IO_RGMII2_GMII_CTL_RGMII_SPD_MASK                          0x0003
#define IO_RGMII2_GMII_CTL_RGMII_SPD_ALIGN                         0
#define IO_RGMII2_GMII_CTL_RGMII_SPD_BITS                          2
#define IO_RGMII2_GMII_CTL_RGMII_SPD_SHIFT                         0


/****************************************************************************
 * IO :: CPU_GMII_CTL
 ***************************************************************************/
/* IO :: CPU_GMII_CTL :: reserved0 [15:09] */
#define IO_CPU_GMII_CTL_RESERVED0_MASK                             0xfe00
#define IO_CPU_GMII_CTL_RESERVED0_ALIGN                            0
#define IO_CPU_GMII_CTL_RESERVED0_BITS                             7
#define IO_CPU_GMII_CTL_RESERVED0_SHIFT                            9

/* IO :: CPU_GMII_CTL :: cpu_lpbk_sel [08:08] */
#define Wr_IO_CPU_GMII_CTL_cpu_lpbk_sel(x) WriteRegBits16(IO_CPU_GMII_CTL,0x100,8,x)
#define Rd_IO_CPU_GMII_CTL_cpu_lpbk_sel(x) ReadRegBits16(IO_CPU_GMII_CTL,0x100,8)
#define IO_CPU_GMII_CTL_CPU_LPBK_SEL_MASK                          0x0100
#define IO_CPU_GMII_CTL_CPU_LPBK_SEL_ALIGN                         0
#define IO_CPU_GMII_CTL_CPU_LPBK_SEL_BITS                          1
#define IO_CPU_GMII_CTL_CPU_LPBK_SEL_SHIFT                         8

/* IO :: CPU_GMII_CTL :: reserved1 [07:05] */
#define IO_CPU_GMII_CTL_RESERVED1_MASK                             0x00e0
#define IO_CPU_GMII_CTL_RESERVED1_ALIGN                            0
#define IO_CPU_GMII_CTL_RESERVED1_BITS                             3
#define IO_CPU_GMII_CTL_RESERVED1_SHIFT                            5

/* IO :: CPU_GMII_CTL :: cpu_rx_pause [04:04] */
#define Wr_IO_CPU_GMII_CTL_cpu_rx_pause(x) WriteRegBits16(IO_CPU_GMII_CTL,0x10,4,x)
#define Rd_IO_CPU_GMII_CTL_cpu_rx_pause(x) ReadRegBits16(IO_CPU_GMII_CTL,0x10,4)
#define IO_CPU_GMII_CTL_CPU_RX_PAUSE_MASK                          0x0010
#define IO_CPU_GMII_CTL_CPU_RX_PAUSE_ALIGN                         0
#define IO_CPU_GMII_CTL_CPU_RX_PAUSE_BITS                          1
#define IO_CPU_GMII_CTL_CPU_RX_PAUSE_SHIFT                         4

/* IO :: CPU_GMII_CTL :: cpu_tx_pause [03:03] */
#define Wr_IO_CPU_GMII_CTL_cpu_tx_pause(x) WriteRegBits16(IO_CPU_GMII_CTL,0x8,3,x)
#define Rd_IO_CPU_GMII_CTL_cpu_tx_pause(x) ReadRegBits16(IO_CPU_GMII_CTL,0x8,3)
#define IO_CPU_GMII_CTL_CPU_TX_PAUSE_MASK                          0x0008
#define IO_CPU_GMII_CTL_CPU_TX_PAUSE_ALIGN                         0
#define IO_CPU_GMII_CTL_CPU_TX_PAUSE_BITS                          1
#define IO_CPU_GMII_CTL_CPU_TX_PAUSE_SHIFT                         3

/* IO :: CPU_GMII_CTL :: cpu_link [02:02] */
#define Wr_IO_CPU_GMII_CTL_cpu_link(x) WriteRegBits16(IO_CPU_GMII_CTL,0x4,2,x)
#define Rd_IO_CPU_GMII_CTL_cpu_link(x) ReadRegBits16(IO_CPU_GMII_CTL,0x4,2)
#define IO_CPU_GMII_CTL_CPU_LINK_MASK                              0x0004
#define IO_CPU_GMII_CTL_CPU_LINK_ALIGN                             0
#define IO_CPU_GMII_CTL_CPU_LINK_BITS                              1
#define IO_CPU_GMII_CTL_CPU_LINK_SHIFT                             2

/* IO :: CPU_GMII_CTL :: cpu_spd [01:00] */
#define Wr_IO_CPU_GMII_CTL_cpu_spd(x) WriteRegBits16(IO_CPU_GMII_CTL,0x3,0,x)
#define Rd_IO_CPU_GMII_CTL_cpu_spd(x) ReadRegBits16(IO_CPU_GMII_CTL,0x3,0)
#define IO_CPU_GMII_CTL_CPU_SPD_MASK                               0x0003
#define IO_CPU_GMII_CTL_CPU_SPD_ALIGN                              0
#define IO_CPU_GMII_CTL_CPU_SPD_BITS                               2
#define IO_CPU_GMII_CTL_CPU_SPD_SHIFT                              0


/****************************************************************************
 * IO :: STRAPS_RAW
 ***************************************************************************/
/* IO :: STRAPS_RAW :: STRAP15_RAW [15:15] */
#define Wr_IO_STRAPS_RAW_STRAP15_RAW(x) WriteRegBits16(IO_STRAPS_RAW,0x8000,15,x)
#define Rd_IO_STRAPS_RAW_STRAP15_RAW(x) ReadRegBits16(IO_STRAPS_RAW,0x8000,15)
#define IO_STRAPS_RAW_STRAP15_RAW_MASK                             0x8000
#define IO_STRAPS_RAW_STRAP15_RAW_ALIGN                            0
#define IO_STRAPS_RAW_STRAP15_RAW_BITS                             1
#define IO_STRAPS_RAW_STRAP15_RAW_SHIFT                            15

/* IO :: STRAPS_RAW :: STRAP14_RAW [14:14] */
#define Wr_IO_STRAPS_RAW_STRAP14_RAW(x) WriteRegBits16(IO_STRAPS_RAW,0x4000,14,x)
#define Rd_IO_STRAPS_RAW_STRAP14_RAW(x) ReadRegBits16(IO_STRAPS_RAW,0x4000,14)
#define IO_STRAPS_RAW_STRAP14_RAW_MASK                             0x4000
#define IO_STRAPS_RAW_STRAP14_RAW_ALIGN                            0
#define IO_STRAPS_RAW_STRAP14_RAW_BITS                             1
#define IO_STRAPS_RAW_STRAP14_RAW_SHIFT                            14

/* IO :: STRAPS_RAW :: STRAP13_RAW [13:13] */
#define Wr_IO_STRAPS_RAW_STRAP13_RAW(x) WriteRegBits16(IO_STRAPS_RAW,0x2000,13,x)
#define Rd_IO_STRAPS_RAW_STRAP13_RAW(x) ReadRegBits16(IO_STRAPS_RAW,0x2000,13)
#define IO_STRAPS_RAW_STRAP13_RAW_MASK                             0x2000
#define IO_STRAPS_RAW_STRAP13_RAW_ALIGN                            0
#define IO_STRAPS_RAW_STRAP13_RAW_BITS                             1
#define IO_STRAPS_RAW_STRAP13_RAW_SHIFT                            13

/* IO :: STRAPS_RAW :: STRAP12_RAW [12:12] */
#define Wr_IO_STRAPS_RAW_STRAP12_RAW(x) WriteRegBits16(IO_STRAPS_RAW,0x1000,12,x)
#define Rd_IO_STRAPS_RAW_STRAP12_RAW(x) ReadRegBits16(IO_STRAPS_RAW,0x1000,12)
#define IO_STRAPS_RAW_STRAP12_RAW_MASK                             0x1000
#define IO_STRAPS_RAW_STRAP12_RAW_ALIGN                            0
#define IO_STRAPS_RAW_STRAP12_RAW_BITS                             1
#define IO_STRAPS_RAW_STRAP12_RAW_SHIFT                            12

/* IO :: STRAPS_RAW :: STRAP11_RAW [11:11] */
#define Wr_IO_STRAPS_RAW_STRAP11_RAW(x) WriteRegBits16(IO_STRAPS_RAW,0x800,11,x)
#define Rd_IO_STRAPS_RAW_STRAP11_RAW(x) ReadRegBits16(IO_STRAPS_RAW,0x800,11)
#define IO_STRAPS_RAW_STRAP11_RAW_MASK                             0x0800
#define IO_STRAPS_RAW_STRAP11_RAW_ALIGN                            0
#define IO_STRAPS_RAW_STRAP11_RAW_BITS                             1
#define IO_STRAPS_RAW_STRAP11_RAW_SHIFT                            11

/* IO :: STRAPS_RAW :: MII2_MODE_2 [10:10] */
#define Wr_IO_STRAPS_RAW_MII2_MODE_2(x) WriteRegBits16(IO_STRAPS_RAW,0x400,10,x)
#define Rd_IO_STRAPS_RAW_MII2_MODE_2(x) ReadRegBits16(IO_STRAPS_RAW,0x400,10)
#define IO_STRAPS_RAW_MII2_MODE_2_MASK                             0x0400
#define IO_STRAPS_RAW_MII2_MODE_2_ALIGN                            0
#define IO_STRAPS_RAW_MII2_MODE_2_BITS                             1
#define IO_STRAPS_RAW_MII2_MODE_2_SHIFT                            10

/* IO :: STRAPS_RAW :: MII1_MODE_2 [09:09] */
#define Wr_IO_STRAPS_RAW_MII1_MODE_2(x) WriteRegBits16(IO_STRAPS_RAW,0x200,9,x)
#define Rd_IO_STRAPS_RAW_MII1_MODE_2(x) ReadRegBits16(IO_STRAPS_RAW,0x200,9)
#define IO_STRAPS_RAW_MII1_MODE_2_MASK                             0x0200
#define IO_STRAPS_RAW_MII1_MODE_2_ALIGN                            0
#define IO_STRAPS_RAW_MII1_MODE_2_BITS                             1
#define IO_STRAPS_RAW_MII1_MODE_2_SHIFT                            9

/* IO :: STRAPS_RAW :: HW_FWDG_EN [08:08] */
#define Wr_IO_STRAPS_RAW_HW_FWDG_EN(x) WriteRegBits16(IO_STRAPS_RAW,0x100,8,x)
#define Rd_IO_STRAPS_RAW_HW_FWDG_EN(x) ReadRegBits16(IO_STRAPS_RAW,0x100,8)
#define IO_STRAPS_RAW_HW_FWDG_EN_MASK                              0x0100
#define IO_STRAPS_RAW_HW_FWDG_EN_ALIGN                             0
#define IO_STRAPS_RAW_HW_FWDG_EN_BITS                              1
#define IO_STRAPS_RAW_HW_FWDG_EN_SHIFT                             8

/* IO :: STRAPS_RAW :: MII2_MODE_1 [07:07] */
#define Wr_IO_STRAPS_RAW_MII2_MODE_1(x) WriteRegBits16(IO_STRAPS_RAW,0x80,7,x)
#define Rd_IO_STRAPS_RAW_MII2_MODE_1(x) ReadRegBits16(IO_STRAPS_RAW,0x80,7)
#define IO_STRAPS_RAW_MII2_MODE_1_MASK                             0x0080
#define IO_STRAPS_RAW_MII2_MODE_1_ALIGN                            0
#define IO_STRAPS_RAW_MII2_MODE_1_BITS                             1
#define IO_STRAPS_RAW_MII2_MODE_1_SHIFT                            7

/* IO :: STRAPS_RAW :: MII2_MODE_0 [06:06] */
#define Wr_IO_STRAPS_RAW_MII2_MODE_0(x) WriteRegBits16(IO_STRAPS_RAW,0x40,6,x)
#define Rd_IO_STRAPS_RAW_MII2_MODE_0(x) ReadRegBits16(IO_STRAPS_RAW,0x40,6)
#define IO_STRAPS_RAW_MII2_MODE_0_MASK                             0x0040
#define IO_STRAPS_RAW_MII2_MODE_0_ALIGN                            0
#define IO_STRAPS_RAW_MII2_MODE_0_BITS                             1
#define IO_STRAPS_RAW_MII2_MODE_0_SHIFT                            6

/* IO :: STRAPS_RAW :: MII1_MODE_1 [05:05] */
#define Wr_IO_STRAPS_RAW_MII1_MODE_1(x) WriteRegBits16(IO_STRAPS_RAW,0x20,5,x)
#define Rd_IO_STRAPS_RAW_MII1_MODE_1(x) ReadRegBits16(IO_STRAPS_RAW,0x20,5)
#define IO_STRAPS_RAW_MII1_MODE_1_MASK                             0x0020
#define IO_STRAPS_RAW_MII1_MODE_1_ALIGN                            0
#define IO_STRAPS_RAW_MII1_MODE_1_BITS                             1
#define IO_STRAPS_RAW_MII1_MODE_1_SHIFT                            5

/* IO :: STRAPS_RAW :: MII1_MODE_0 [04:04] */
#define Wr_IO_STRAPS_RAW_MII1_MODE_0(x) WriteRegBits16(IO_STRAPS_RAW,0x10,4,x)
#define Rd_IO_STRAPS_RAW_MII1_MODE_0(x) ReadRegBits16(IO_STRAPS_RAW,0x10,4)
#define IO_STRAPS_RAW_MII1_MODE_0_MASK                             0x0010
#define IO_STRAPS_RAW_MII1_MODE_0_ALIGN                            0
#define IO_STRAPS_RAW_MII1_MODE_0_BITS                             1
#define IO_STRAPS_RAW_MII1_MODE_0_SHIFT                            4

/* IO :: STRAPS_RAW :: JTCE_STRAP [03:03] */
#define Wr_IO_STRAPS_RAW_JTCE_STRAP(x) WriteRegBits16(IO_STRAPS_RAW,0x8,3,x)
#define Rd_IO_STRAPS_RAW_JTCE_STRAP(x) ReadRegBits16(IO_STRAPS_RAW,0x8,3)
#define IO_STRAPS_RAW_JTCE_STRAP_MASK                              0x0008
#define IO_STRAPS_RAW_JTCE_STRAP_ALIGN                             0
#define IO_STRAPS_RAW_JTCE_STRAP_BITS                              1
#define IO_STRAPS_RAW_JTCE_STRAP_SHIFT                             3

/* IO :: STRAPS_RAW :: QSPI_MODE_STRAP [02:02] */
#define Wr_IO_STRAPS_RAW_QSPI_MODE_STRAP(x) WriteRegBits16(IO_STRAPS_RAW,0x4,2,x)
#define Rd_IO_STRAPS_RAW_QSPI_MODE_STRAP(x) ReadRegBits16(IO_STRAPS_RAW,0x4,2)
#define IO_STRAPS_RAW_QSPI_MODE_STRAP_MASK                         0x0004
#define IO_STRAPS_RAW_QSPI_MODE_STRAP_ALIGN                        0
#define IO_STRAPS_RAW_QSPI_MODE_STRAP_BITS                         1
#define IO_STRAPS_RAW_QSPI_MODE_STRAP_SHIFT                        2

/* IO :: STRAPS_RAW :: BRPHY_MS_STRAP [01:01] */
#define Wr_IO_STRAPS_RAW_BRPHY_MS_STRAP(x) WriteRegBits16(IO_STRAPS_RAW,0x2,1,x)
#define Rd_IO_STRAPS_RAW_BRPHY_MS_STRAP(x) ReadRegBits16(IO_STRAPS_RAW,0x2,1)
#define IO_STRAPS_RAW_BRPHY_MS_STRAP_MASK                          0x0002
#define IO_STRAPS_RAW_BRPHY_MS_STRAP_ALIGN                         0
#define IO_STRAPS_RAW_BRPHY_MS_STRAP_BITS                          1
#define IO_STRAPS_RAW_BRPHY_MS_STRAP_SHIFT                         1

/* IO :: STRAPS_RAW :: STRAP_ENEXTCK [00:00] */
#define Wr_IO_STRAPS_RAW_STRAP_ENEXTCK(x) WriteRegBits16(IO_STRAPS_RAW,0x1,0,x)
#define Rd_IO_STRAPS_RAW_STRAP_ENEXTCK(x) ReadRegBits16(IO_STRAPS_RAW,0x1,0)
#define IO_STRAPS_RAW_STRAP_ENEXTCK_MASK                           0x0001
#define IO_STRAPS_RAW_STRAP_ENEXTCK_ALIGN                          0
#define IO_STRAPS_RAW_STRAP_ENEXTCK_BITS                           1
#define IO_STRAPS_RAW_STRAP_ENEXTCK_SHIFT                          0


/****************************************************************************
 * IO :: STRAPS_OV
 ***************************************************************************/
/* IO :: STRAPS_OV :: STRAP15 [15:15] */
#define Wr_IO_STRAPS_OV_STRAP15(x) WriteRegBits16(IO_STRAPS_OV,0x8000,15,x)
#define Rd_IO_STRAPS_OV_STRAP15(x) ReadRegBits16(IO_STRAPS_OV,0x8000,15)
#define IO_STRAPS_OV_STRAP15_MASK                                  0x8000
#define IO_STRAPS_OV_STRAP15_ALIGN                                 0
#define IO_STRAPS_OV_STRAP15_BITS                                  1
#define IO_STRAPS_OV_STRAP15_SHIFT                                 15

/* IO :: STRAPS_OV :: STRAP14 [14:14] */
#define Wr_IO_STRAPS_OV_STRAP14(x) WriteRegBits16(IO_STRAPS_OV,0x4000,14,x)
#define Rd_IO_STRAPS_OV_STRAP14(x) ReadRegBits16(IO_STRAPS_OV,0x4000,14)
#define IO_STRAPS_OV_STRAP14_MASK                                  0x4000
#define IO_STRAPS_OV_STRAP14_ALIGN                                 0
#define IO_STRAPS_OV_STRAP14_BITS                                  1
#define IO_STRAPS_OV_STRAP14_SHIFT                                 14

/* IO :: STRAPS_OV :: STRAP13 [13:13] */
#define Wr_IO_STRAPS_OV_STRAP13(x) WriteRegBits16(IO_STRAPS_OV,0x2000,13,x)
#define Rd_IO_STRAPS_OV_STRAP13(x) ReadRegBits16(IO_STRAPS_OV,0x2000,13)
#define IO_STRAPS_OV_STRAP13_MASK                                  0x2000
#define IO_STRAPS_OV_STRAP13_ALIGN                                 0
#define IO_STRAPS_OV_STRAP13_BITS                                  1
#define IO_STRAPS_OV_STRAP13_SHIFT                                 13

/* IO :: STRAPS_OV :: STRAP12 [12:12] */
#define Wr_IO_STRAPS_OV_STRAP12(x) WriteRegBits16(IO_STRAPS_OV,0x1000,12,x)
#define Rd_IO_STRAPS_OV_STRAP12(x) ReadRegBits16(IO_STRAPS_OV,0x1000,12)
#define IO_STRAPS_OV_STRAP12_MASK                                  0x1000
#define IO_STRAPS_OV_STRAP12_ALIGN                                 0
#define IO_STRAPS_OV_STRAP12_BITS                                  1
#define IO_STRAPS_OV_STRAP12_SHIFT                                 12

/* IO :: STRAPS_OV :: STRAP11 [11:11] */
#define Wr_IO_STRAPS_OV_STRAP11(x) WriteRegBits16(IO_STRAPS_OV,0x800,11,x)
#define Rd_IO_STRAPS_OV_STRAP11(x) ReadRegBits16(IO_STRAPS_OV,0x800,11)
#define IO_STRAPS_OV_STRAP11_MASK                                  0x0800
#define IO_STRAPS_OV_STRAP11_ALIGN                                 0
#define IO_STRAPS_OV_STRAP11_BITS                                  1
#define IO_STRAPS_OV_STRAP11_SHIFT                                 11

/* IO :: STRAPS_OV :: STRAP10 [10:10] */
#define Wr_IO_STRAPS_OV_STRAP10(x) WriteRegBits16(IO_STRAPS_OV,0x400,10,x)
#define Rd_IO_STRAPS_OV_STRAP10(x) ReadRegBits16(IO_STRAPS_OV,0x400,10)
#define IO_STRAPS_OV_STRAP10_MASK                                  0x0400
#define IO_STRAPS_OV_STRAP10_ALIGN                                 0
#define IO_STRAPS_OV_STRAP10_BITS                                  1
#define IO_STRAPS_OV_STRAP10_SHIFT                                 10

/* IO :: STRAPS_OV :: STRAP09 [09:09] */
#define Wr_IO_STRAPS_OV_STRAP09(x) WriteRegBits16(IO_STRAPS_OV,0x200,9,x)
#define Rd_IO_STRAPS_OV_STRAP09(x) ReadRegBits16(IO_STRAPS_OV,0x200,9)
#define IO_STRAPS_OV_STRAP09_MASK                                  0x0200
#define IO_STRAPS_OV_STRAP09_ALIGN                                 0
#define IO_STRAPS_OV_STRAP09_BITS                                  1
#define IO_STRAPS_OV_STRAP09_SHIFT                                 9

/* IO :: STRAPS_OV :: HW_FWDG_EN [08:08] */
#define Wr_IO_STRAPS_OV_HW_FWDG_EN(x) WriteRegBits16(IO_STRAPS_OV,0x100,8,x)
#define Rd_IO_STRAPS_OV_HW_FWDG_EN(x) ReadRegBits16(IO_STRAPS_OV,0x100,8)
#define IO_STRAPS_OV_HW_FWDG_EN_MASK                               0x0100
#define IO_STRAPS_OV_HW_FWDG_EN_ALIGN                              0
#define IO_STRAPS_OV_HW_FWDG_EN_BITS                               1
#define IO_STRAPS_OV_HW_FWDG_EN_SHIFT                              8

/* IO :: STRAPS_OV :: MII2_MODE_1 [07:07] */
#define Wr_IO_STRAPS_OV_MII2_MODE_1(x) WriteRegBits16(IO_STRAPS_OV,0x80,7,x)
#define Rd_IO_STRAPS_OV_MII2_MODE_1(x) ReadRegBits16(IO_STRAPS_OV,0x80,7)
#define IO_STRAPS_OV_MII2_MODE_1_MASK                              0x0080
#define IO_STRAPS_OV_MII2_MODE_1_ALIGN                             0
#define IO_STRAPS_OV_MII2_MODE_1_BITS                              1
#define IO_STRAPS_OV_MII2_MODE_1_SHIFT                             7

/* IO :: STRAPS_OV :: MII2_MODE_0 [06:06] */
#define Wr_IO_STRAPS_OV_MII2_MODE_0(x) WriteRegBits16(IO_STRAPS_OV,0x40,6,x)
#define Rd_IO_STRAPS_OV_MII2_MODE_0(x) ReadRegBits16(IO_STRAPS_OV,0x40,6)
#define IO_STRAPS_OV_MII2_MODE_0_MASK                              0x0040
#define IO_STRAPS_OV_MII2_MODE_0_ALIGN                             0
#define IO_STRAPS_OV_MII2_MODE_0_BITS                              1
#define IO_STRAPS_OV_MII2_MODE_0_SHIFT                             6

/* IO :: STRAPS_OV :: MII1_MODE_1 [05:05] */
#define Wr_IO_STRAPS_OV_MII1_MODE_1(x) WriteRegBits16(IO_STRAPS_OV,0x20,5,x)
#define Rd_IO_STRAPS_OV_MII1_MODE_1(x) ReadRegBits16(IO_STRAPS_OV,0x20,5)
#define IO_STRAPS_OV_MII1_MODE_1_MASK                              0x0020
#define IO_STRAPS_OV_MII1_MODE_1_ALIGN                             0
#define IO_STRAPS_OV_MII1_MODE_1_BITS                              1
#define IO_STRAPS_OV_MII1_MODE_1_SHIFT                             5

/* IO :: STRAPS_OV :: MII1_MODE_0 [04:04] */
#define Wr_IO_STRAPS_OV_MII1_MODE_0(x) WriteRegBits16(IO_STRAPS_OV,0x10,4,x)
#define Rd_IO_STRAPS_OV_MII1_MODE_0(x) ReadRegBits16(IO_STRAPS_OV,0x10,4)
#define IO_STRAPS_OV_MII1_MODE_0_MASK                              0x0010
#define IO_STRAPS_OV_MII1_MODE_0_ALIGN                             0
#define IO_STRAPS_OV_MII1_MODE_0_BITS                              1
#define IO_STRAPS_OV_MII1_MODE_0_SHIFT                             4

/* IO :: STRAPS_OV :: JTCE_STRAP [03:03] */
#define Wr_IO_STRAPS_OV_JTCE_STRAP(x) WriteRegBits16(IO_STRAPS_OV,0x8,3,x)
#define Rd_IO_STRAPS_OV_JTCE_STRAP(x) ReadRegBits16(IO_STRAPS_OV,0x8,3)
#define IO_STRAPS_OV_JTCE_STRAP_MASK                               0x0008
#define IO_STRAPS_OV_JTCE_STRAP_ALIGN                              0
#define IO_STRAPS_OV_JTCE_STRAP_BITS                               1
#define IO_STRAPS_OV_JTCE_STRAP_SHIFT                              3

/* IO :: STRAPS_OV :: QSPI_MODE_STRAP [02:02] */
#define Wr_IO_STRAPS_OV_QSPI_MODE_STRAP(x) WriteRegBits16(IO_STRAPS_OV,0x4,2,x)
#define Rd_IO_STRAPS_OV_QSPI_MODE_STRAP(x) ReadRegBits16(IO_STRAPS_OV,0x4,2)
#define IO_STRAPS_OV_QSPI_MODE_STRAP_MASK                          0x0004
#define IO_STRAPS_OV_QSPI_MODE_STRAP_ALIGN                         0
#define IO_STRAPS_OV_QSPI_MODE_STRAP_BITS                          1
#define IO_STRAPS_OV_QSPI_MODE_STRAP_SHIFT                         2

/* IO :: STRAPS_OV :: BRPHY_MS_STRAP [01:01] */
#define Wr_IO_STRAPS_OV_BRPHY_MS_STRAP(x) WriteRegBits16(IO_STRAPS_OV,0x2,1,x)
#define Rd_IO_STRAPS_OV_BRPHY_MS_STRAP(x) ReadRegBits16(IO_STRAPS_OV,0x2,1)
#define IO_STRAPS_OV_BRPHY_MS_STRAP_MASK                           0x0002
#define IO_STRAPS_OV_BRPHY_MS_STRAP_ALIGN                          0
#define IO_STRAPS_OV_BRPHY_MS_STRAP_BITS                           1
#define IO_STRAPS_OV_BRPHY_MS_STRAP_SHIFT                          1

/* IO :: STRAPS_OV :: STRAP_ENEXTCK [00:00] */
#define Wr_IO_STRAPS_OV_STRAP_ENEXTCK(x) WriteRegBits16(IO_STRAPS_OV,0x1,0,x)
#define Rd_IO_STRAPS_OV_STRAP_ENEXTCK(x) ReadRegBits16(IO_STRAPS_OV,0x1,0)
#define IO_STRAPS_OV_STRAP_ENEXTCK_MASK                            0x0001
#define IO_STRAPS_OV_STRAP_ENEXTCK_ALIGN                           0
#define IO_STRAPS_OV_STRAP_ENEXTCK_BITS                            1
#define IO_STRAPS_OV_STRAP_ENEXTCK_SHIFT                           0


/****************************************************************************
 * IO :: SW_OVRD0
 ***************************************************************************/
/* IO :: SW_OVRD0 :: reserved0 [15:12] */
#define IO_SW_OVRD0_RESERVED0_MASK                                 0xf000
#define IO_SW_OVRD0_RESERVED0_ALIGN                                0
#define IO_SW_OVRD0_RESERVED0_BITS                                 4
#define IO_SW_OVRD0_RESERVED0_SHIFT                                12

/* IO :: SW_OVRD0 :: ovrd_rx_pause_sel [11:11] */
#define Wr_IO_SW_OVRD0_ovrd_rx_pause_sel(x) WriteRegBits16(IO_SW_OVRD0,0x800,11,x)
#define Rd_IO_SW_OVRD0_ovrd_rx_pause_sel(x) ReadRegBits16(IO_SW_OVRD0,0x800,11)
#define IO_SW_OVRD0_OVRD_RX_PAUSE_SEL_MASK                         0x0800
#define IO_SW_OVRD0_OVRD_RX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD0_OVRD_RX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD0_OVRD_RX_PAUSE_SEL_SHIFT                        11

/* IO :: SW_OVRD0 :: ovrd_tx_pause_sel [10:10] */
#define Wr_IO_SW_OVRD0_ovrd_tx_pause_sel(x) WriteRegBits16(IO_SW_OVRD0,0x400,10,x)
#define Rd_IO_SW_OVRD0_ovrd_tx_pause_sel(x) ReadRegBits16(IO_SW_OVRD0,0x400,10)
#define IO_SW_OVRD0_OVRD_TX_PAUSE_SEL_MASK                         0x0400
#define IO_SW_OVRD0_OVRD_TX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD0_OVRD_TX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD0_OVRD_TX_PAUSE_SEL_SHIFT                        10

/* IO :: SW_OVRD0 :: ovrd_link_sel [09:09] */
#define Wr_IO_SW_OVRD0_ovrd_link_sel(x) WriteRegBits16(IO_SW_OVRD0,0x200,9,x)
#define Rd_IO_SW_OVRD0_ovrd_link_sel(x) ReadRegBits16(IO_SW_OVRD0,0x200,9)
#define IO_SW_OVRD0_OVRD_LINK_SEL_MASK                             0x0200
#define IO_SW_OVRD0_OVRD_LINK_SEL_ALIGN                            0
#define IO_SW_OVRD0_OVRD_LINK_SEL_BITS                             1
#define IO_SW_OVRD0_OVRD_LINK_SEL_SHIFT                            9

/* IO :: SW_OVRD0 :: ovrd_spd_sel [08:08] */
#define Wr_IO_SW_OVRD0_ovrd_spd_sel(x) WriteRegBits16(IO_SW_OVRD0,0x100,8,x)
#define Rd_IO_SW_OVRD0_ovrd_spd_sel(x) ReadRegBits16(IO_SW_OVRD0,0x100,8)
#define IO_SW_OVRD0_OVRD_SPD_SEL_MASK                              0x0100
#define IO_SW_OVRD0_OVRD_SPD_SEL_ALIGN                             0
#define IO_SW_OVRD0_OVRD_SPD_SEL_BITS                              1
#define IO_SW_OVRD0_OVRD_SPD_SEL_SHIFT                             8

/* IO :: SW_OVRD0 :: reserved1 [07:05] */
#define IO_SW_OVRD0_RESERVED1_MASK                                 0x00e0
#define IO_SW_OVRD0_RESERVED1_ALIGN                                0
#define IO_SW_OVRD0_RESERVED1_BITS                                 3
#define IO_SW_OVRD0_RESERVED1_SHIFT                                5

/* IO :: SW_OVRD0 :: ovrd_rx_pause_val [04:04] */
#define Wr_IO_SW_OVRD0_ovrd_rx_pause_val(x) WriteRegBits16(IO_SW_OVRD0,0x10,4,x)
#define Rd_IO_SW_OVRD0_ovrd_rx_pause_val(x) ReadRegBits16(IO_SW_OVRD0,0x10,4)
#define IO_SW_OVRD0_OVRD_RX_PAUSE_VAL_MASK                         0x0010
#define IO_SW_OVRD0_OVRD_RX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD0_OVRD_RX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD0_OVRD_RX_PAUSE_VAL_SHIFT                        4

/* IO :: SW_OVRD0 :: ovrd_tx_pause_val [03:03] */
#define Wr_IO_SW_OVRD0_ovrd_tx_pause_val(x) WriteRegBits16(IO_SW_OVRD0,0x8,3,x)
#define Rd_IO_SW_OVRD0_ovrd_tx_pause_val(x) ReadRegBits16(IO_SW_OVRD0,0x8,3)
#define IO_SW_OVRD0_OVRD_TX_PAUSE_VAL_MASK                         0x0008
#define IO_SW_OVRD0_OVRD_TX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD0_OVRD_TX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD0_OVRD_TX_PAUSE_VAL_SHIFT                        3

/* IO :: SW_OVRD0 :: ovrd_link_val [02:02] */
#define Wr_IO_SW_OVRD0_ovrd_link_val(x) WriteRegBits16(IO_SW_OVRD0,0x4,2,x)
#define Rd_IO_SW_OVRD0_ovrd_link_val(x) ReadRegBits16(IO_SW_OVRD0,0x4,2)
#define IO_SW_OVRD0_OVRD_LINK_VAL_MASK                             0x0004
#define IO_SW_OVRD0_OVRD_LINK_VAL_ALIGN                            0
#define IO_SW_OVRD0_OVRD_LINK_VAL_BITS                             1
#define IO_SW_OVRD0_OVRD_LINK_VAL_SHIFT                            2

/* IO :: SW_OVRD0 :: ovrd_spd_val [01:00] */
#define Wr_IO_SW_OVRD0_ovrd_spd_val(x) WriteRegBits16(IO_SW_OVRD0,0x3,0,x)
#define Rd_IO_SW_OVRD0_ovrd_spd_val(x) ReadRegBits16(IO_SW_OVRD0,0x3,0)
#define IO_SW_OVRD0_OVRD_SPD_VAL_MASK                              0x0003
#define IO_SW_OVRD0_OVRD_SPD_VAL_ALIGN                             0
#define IO_SW_OVRD0_OVRD_SPD_VAL_BITS                              2
#define IO_SW_OVRD0_OVRD_SPD_VAL_SHIFT                             0


/****************************************************************************
 * IO :: SW_OVRD1
 ***************************************************************************/
/* IO :: SW_OVRD1 :: reserved0 [15:12] */
#define IO_SW_OVRD1_RESERVED0_MASK                                 0xf000
#define IO_SW_OVRD1_RESERVED0_ALIGN                                0
#define IO_SW_OVRD1_RESERVED0_BITS                                 4
#define IO_SW_OVRD1_RESERVED0_SHIFT                                12

/* IO :: SW_OVRD1 :: ovrd_rx_pause_sel [11:11] */
#define Wr_IO_SW_OVRD1_ovrd_rx_pause_sel(x) WriteRegBits16(IO_SW_OVRD1,0x800,11,x)
#define Rd_IO_SW_OVRD1_ovrd_rx_pause_sel(x) ReadRegBits16(IO_SW_OVRD1,0x800,11)
#define IO_SW_OVRD1_OVRD_RX_PAUSE_SEL_MASK                         0x0800
#define IO_SW_OVRD1_OVRD_RX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD1_OVRD_RX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD1_OVRD_RX_PAUSE_SEL_SHIFT                        11

/* IO :: SW_OVRD1 :: ovrd_tx_pause_sel [10:10] */
#define Wr_IO_SW_OVRD1_ovrd_tx_pause_sel(x) WriteRegBits16(IO_SW_OVRD1,0x400,10,x)
#define Rd_IO_SW_OVRD1_ovrd_tx_pause_sel(x) ReadRegBits16(IO_SW_OVRD1,0x400,10)
#define IO_SW_OVRD1_OVRD_TX_PAUSE_SEL_MASK                         0x0400
#define IO_SW_OVRD1_OVRD_TX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD1_OVRD_TX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD1_OVRD_TX_PAUSE_SEL_SHIFT                        10

/* IO :: SW_OVRD1 :: ovrd_link_sel [09:09] */
#define Wr_IO_SW_OVRD1_ovrd_link_sel(x) WriteRegBits16(IO_SW_OVRD1,0x200,9,x)
#define Rd_IO_SW_OVRD1_ovrd_link_sel(x) ReadRegBits16(IO_SW_OVRD1,0x200,9)
#define IO_SW_OVRD1_OVRD_LINK_SEL_MASK                             0x0200
#define IO_SW_OVRD1_OVRD_LINK_SEL_ALIGN                            0
#define IO_SW_OVRD1_OVRD_LINK_SEL_BITS                             1
#define IO_SW_OVRD1_OVRD_LINK_SEL_SHIFT                            9

/* IO :: SW_OVRD1 :: ovrd_spd_sel [08:08] */
#define Wr_IO_SW_OVRD1_ovrd_spd_sel(x) WriteRegBits16(IO_SW_OVRD1,0x100,8,x)
#define Rd_IO_SW_OVRD1_ovrd_spd_sel(x) ReadRegBits16(IO_SW_OVRD1,0x100,8)
#define IO_SW_OVRD1_OVRD_SPD_SEL_MASK                              0x0100
#define IO_SW_OVRD1_OVRD_SPD_SEL_ALIGN                             0
#define IO_SW_OVRD1_OVRD_SPD_SEL_BITS                              1
#define IO_SW_OVRD1_OVRD_SPD_SEL_SHIFT                             8

/* IO :: SW_OVRD1 :: reserved1 [07:05] */
#define IO_SW_OVRD1_RESERVED1_MASK                                 0x00e0
#define IO_SW_OVRD1_RESERVED1_ALIGN                                0
#define IO_SW_OVRD1_RESERVED1_BITS                                 3
#define IO_SW_OVRD1_RESERVED1_SHIFT                                5

/* IO :: SW_OVRD1 :: ovrd_rx_pause_val [04:04] */
#define Wr_IO_SW_OVRD1_ovrd_rx_pause_val(x) WriteRegBits16(IO_SW_OVRD1,0x10,4,x)
#define Rd_IO_SW_OVRD1_ovrd_rx_pause_val(x) ReadRegBits16(IO_SW_OVRD1,0x10,4)
#define IO_SW_OVRD1_OVRD_RX_PAUSE_VAL_MASK                         0x0010
#define IO_SW_OVRD1_OVRD_RX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD1_OVRD_RX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD1_OVRD_RX_PAUSE_VAL_SHIFT                        4

/* IO :: SW_OVRD1 :: ovrd_tx_pause_val [03:03] */
#define Wr_IO_SW_OVRD1_ovrd_tx_pause_val(x) WriteRegBits16(IO_SW_OVRD1,0x8,3,x)
#define Rd_IO_SW_OVRD1_ovrd_tx_pause_val(x) ReadRegBits16(IO_SW_OVRD1,0x8,3)
#define IO_SW_OVRD1_OVRD_TX_PAUSE_VAL_MASK                         0x0008
#define IO_SW_OVRD1_OVRD_TX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD1_OVRD_TX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD1_OVRD_TX_PAUSE_VAL_SHIFT                        3

/* IO :: SW_OVRD1 :: ovrd_link_val [02:02] */
#define Wr_IO_SW_OVRD1_ovrd_link_val(x) WriteRegBits16(IO_SW_OVRD1,0x4,2,x)
#define Rd_IO_SW_OVRD1_ovrd_link_val(x) ReadRegBits16(IO_SW_OVRD1,0x4,2)
#define IO_SW_OVRD1_OVRD_LINK_VAL_MASK                             0x0004
#define IO_SW_OVRD1_OVRD_LINK_VAL_ALIGN                            0
#define IO_SW_OVRD1_OVRD_LINK_VAL_BITS                             1
#define IO_SW_OVRD1_OVRD_LINK_VAL_SHIFT                            2

/* IO :: SW_OVRD1 :: ovrd_spd_val [01:00] */
#define Wr_IO_SW_OVRD1_ovrd_spd_val(x) WriteRegBits16(IO_SW_OVRD1,0x3,0,x)
#define Rd_IO_SW_OVRD1_ovrd_spd_val(x) ReadRegBits16(IO_SW_OVRD1,0x3,0)
#define IO_SW_OVRD1_OVRD_SPD_VAL_MASK                              0x0003
#define IO_SW_OVRD1_OVRD_SPD_VAL_ALIGN                             0
#define IO_SW_OVRD1_OVRD_SPD_VAL_BITS                              2
#define IO_SW_OVRD1_OVRD_SPD_VAL_SHIFT                             0


/****************************************************************************
 * IO :: SW_OVRD2
 ***************************************************************************/
/* IO :: SW_OVRD2 :: reserved0 [15:12] */
#define IO_SW_OVRD2_RESERVED0_MASK                                 0xf000
#define IO_SW_OVRD2_RESERVED0_ALIGN                                0
#define IO_SW_OVRD2_RESERVED0_BITS                                 4
#define IO_SW_OVRD2_RESERVED0_SHIFT                                12

/* IO :: SW_OVRD2 :: ovrd_rx_pause_sel [11:11] */
#define Wr_IO_SW_OVRD2_ovrd_rx_pause_sel(x) WriteRegBits16(IO_SW_OVRD2,0x800,11,x)
#define Rd_IO_SW_OVRD2_ovrd_rx_pause_sel(x) ReadRegBits16(IO_SW_OVRD2,0x800,11)
#define IO_SW_OVRD2_OVRD_RX_PAUSE_SEL_MASK                         0x0800
#define IO_SW_OVRD2_OVRD_RX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD2_OVRD_RX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD2_OVRD_RX_PAUSE_SEL_SHIFT                        11

/* IO :: SW_OVRD2 :: ovrd_tx_pause_sel [10:10] */
#define Wr_IO_SW_OVRD2_ovrd_tx_pause_sel(x) WriteRegBits16(IO_SW_OVRD2,0x400,10,x)
#define Rd_IO_SW_OVRD2_ovrd_tx_pause_sel(x) ReadRegBits16(IO_SW_OVRD2,0x400,10)
#define IO_SW_OVRD2_OVRD_TX_PAUSE_SEL_MASK                         0x0400
#define IO_SW_OVRD2_OVRD_TX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD2_OVRD_TX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD2_OVRD_TX_PAUSE_SEL_SHIFT                        10

/* IO :: SW_OVRD2 :: ovrd_link_sel [09:09] */
#define Wr_IO_SW_OVRD2_ovrd_link_sel(x) WriteRegBits16(IO_SW_OVRD2,0x200,9,x)
#define Rd_IO_SW_OVRD2_ovrd_link_sel(x) ReadRegBits16(IO_SW_OVRD2,0x200,9)
#define IO_SW_OVRD2_OVRD_LINK_SEL_MASK                             0x0200
#define IO_SW_OVRD2_OVRD_LINK_SEL_ALIGN                            0
#define IO_SW_OVRD2_OVRD_LINK_SEL_BITS                             1
#define IO_SW_OVRD2_OVRD_LINK_SEL_SHIFT                            9

/* IO :: SW_OVRD2 :: ovrd_spd_sel [08:08] */
#define Wr_IO_SW_OVRD2_ovrd_spd_sel(x) WriteRegBits16(IO_SW_OVRD2,0x100,8,x)
#define Rd_IO_SW_OVRD2_ovrd_spd_sel(x) ReadRegBits16(IO_SW_OVRD2,0x100,8)
#define IO_SW_OVRD2_OVRD_SPD_SEL_MASK                              0x0100
#define IO_SW_OVRD2_OVRD_SPD_SEL_ALIGN                             0
#define IO_SW_OVRD2_OVRD_SPD_SEL_BITS                              1
#define IO_SW_OVRD2_OVRD_SPD_SEL_SHIFT                             8

/* IO :: SW_OVRD2 :: reserved1 [07:05] */
#define IO_SW_OVRD2_RESERVED1_MASK                                 0x00e0
#define IO_SW_OVRD2_RESERVED1_ALIGN                                0
#define IO_SW_OVRD2_RESERVED1_BITS                                 3
#define IO_SW_OVRD2_RESERVED1_SHIFT                                5

/* IO :: SW_OVRD2 :: ovrd_rx_pause_val [04:04] */
#define Wr_IO_SW_OVRD2_ovrd_rx_pause_val(x) WriteRegBits16(IO_SW_OVRD2,0x10,4,x)
#define Rd_IO_SW_OVRD2_ovrd_rx_pause_val(x) ReadRegBits16(IO_SW_OVRD2,0x10,4)
#define IO_SW_OVRD2_OVRD_RX_PAUSE_VAL_MASK                         0x0010
#define IO_SW_OVRD2_OVRD_RX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD2_OVRD_RX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD2_OVRD_RX_PAUSE_VAL_SHIFT                        4

/* IO :: SW_OVRD2 :: ovrd_tx_pause_val [03:03] */
#define Wr_IO_SW_OVRD2_ovrd_tx_pause_val(x) WriteRegBits16(IO_SW_OVRD2,0x8,3,x)
#define Rd_IO_SW_OVRD2_ovrd_tx_pause_val(x) ReadRegBits16(IO_SW_OVRD2,0x8,3)
#define IO_SW_OVRD2_OVRD_TX_PAUSE_VAL_MASK                         0x0008
#define IO_SW_OVRD2_OVRD_TX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD2_OVRD_TX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD2_OVRD_TX_PAUSE_VAL_SHIFT                        3

/* IO :: SW_OVRD2 :: ovrd_link_val [02:02] */
#define Wr_IO_SW_OVRD2_ovrd_link_val(x) WriteRegBits16(IO_SW_OVRD2,0x4,2,x)
#define Rd_IO_SW_OVRD2_ovrd_link_val(x) ReadRegBits16(IO_SW_OVRD2,0x4,2)
#define IO_SW_OVRD2_OVRD_LINK_VAL_MASK                             0x0004
#define IO_SW_OVRD2_OVRD_LINK_VAL_ALIGN                            0
#define IO_SW_OVRD2_OVRD_LINK_VAL_BITS                             1
#define IO_SW_OVRD2_OVRD_LINK_VAL_SHIFT                            2

/* IO :: SW_OVRD2 :: ovrd_spd_val [01:00] */
#define Wr_IO_SW_OVRD2_ovrd_spd_val(x) WriteRegBits16(IO_SW_OVRD2,0x3,0,x)
#define Rd_IO_SW_OVRD2_ovrd_spd_val(x) ReadRegBits16(IO_SW_OVRD2,0x3,0)
#define IO_SW_OVRD2_OVRD_SPD_VAL_MASK                              0x0003
#define IO_SW_OVRD2_OVRD_SPD_VAL_ALIGN                             0
#define IO_SW_OVRD2_OVRD_SPD_VAL_BITS                              2
#define IO_SW_OVRD2_OVRD_SPD_VAL_SHIFT                             0


/****************************************************************************
 * IO :: SW_OVRD3
 ***************************************************************************/
/* IO :: SW_OVRD3 :: reserved0 [15:12] */
#define IO_SW_OVRD3_RESERVED0_MASK                                 0xf000
#define IO_SW_OVRD3_RESERVED0_ALIGN                                0
#define IO_SW_OVRD3_RESERVED0_BITS                                 4
#define IO_SW_OVRD3_RESERVED0_SHIFT                                12

/* IO :: SW_OVRD3 :: ovrd_rx_pause_sel [11:11] */
#define Wr_IO_SW_OVRD3_ovrd_rx_pause_sel(x) WriteRegBits16(IO_SW_OVRD3,0x800,11,x)
#define Rd_IO_SW_OVRD3_ovrd_rx_pause_sel(x) ReadRegBits16(IO_SW_OVRD3,0x800,11)
#define IO_SW_OVRD3_OVRD_RX_PAUSE_SEL_MASK                         0x0800
#define IO_SW_OVRD3_OVRD_RX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD3_OVRD_RX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD3_OVRD_RX_PAUSE_SEL_SHIFT                        11

/* IO :: SW_OVRD3 :: ovrd_tx_pause_sel [10:10] */
#define Wr_IO_SW_OVRD3_ovrd_tx_pause_sel(x) WriteRegBits16(IO_SW_OVRD3,0x400,10,x)
#define Rd_IO_SW_OVRD3_ovrd_tx_pause_sel(x) ReadRegBits16(IO_SW_OVRD3,0x400,10)
#define IO_SW_OVRD3_OVRD_TX_PAUSE_SEL_MASK                         0x0400
#define IO_SW_OVRD3_OVRD_TX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD3_OVRD_TX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD3_OVRD_TX_PAUSE_SEL_SHIFT                        10

/* IO :: SW_OVRD3 :: ovrd_link_sel [09:09] */
#define Wr_IO_SW_OVRD3_ovrd_link_sel(x) WriteRegBits16(IO_SW_OVRD3,0x200,9,x)
#define Rd_IO_SW_OVRD3_ovrd_link_sel(x) ReadRegBits16(IO_SW_OVRD3,0x200,9)
#define IO_SW_OVRD3_OVRD_LINK_SEL_MASK                             0x0200
#define IO_SW_OVRD3_OVRD_LINK_SEL_ALIGN                            0
#define IO_SW_OVRD3_OVRD_LINK_SEL_BITS                             1
#define IO_SW_OVRD3_OVRD_LINK_SEL_SHIFT                            9

/* IO :: SW_OVRD3 :: ovrd_spd_sel [08:08] */
#define Wr_IO_SW_OVRD3_ovrd_spd_sel(x) WriteRegBits16(IO_SW_OVRD3,0x100,8,x)
#define Rd_IO_SW_OVRD3_ovrd_spd_sel(x) ReadRegBits16(IO_SW_OVRD3,0x100,8)
#define IO_SW_OVRD3_OVRD_SPD_SEL_MASK                              0x0100
#define IO_SW_OVRD3_OVRD_SPD_SEL_ALIGN                             0
#define IO_SW_OVRD3_OVRD_SPD_SEL_BITS                              1
#define IO_SW_OVRD3_OVRD_SPD_SEL_SHIFT                             8

/* IO :: SW_OVRD3 :: reserved1 [07:05] */
#define IO_SW_OVRD3_RESERVED1_MASK                                 0x00e0
#define IO_SW_OVRD3_RESERVED1_ALIGN                                0
#define IO_SW_OVRD3_RESERVED1_BITS                                 3
#define IO_SW_OVRD3_RESERVED1_SHIFT                                5

/* IO :: SW_OVRD3 :: ovrd_rx_pause_val [04:04] */
#define Wr_IO_SW_OVRD3_ovrd_rx_pause_val(x) WriteRegBits16(IO_SW_OVRD3,0x10,4,x)
#define Rd_IO_SW_OVRD3_ovrd_rx_pause_val(x) ReadRegBits16(IO_SW_OVRD3,0x10,4)
#define IO_SW_OVRD3_OVRD_RX_PAUSE_VAL_MASK                         0x0010
#define IO_SW_OVRD3_OVRD_RX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD3_OVRD_RX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD3_OVRD_RX_PAUSE_VAL_SHIFT                        4

/* IO :: SW_OVRD3 :: ovrd_tx_pause_val [03:03] */
#define Wr_IO_SW_OVRD3_ovrd_tx_pause_val(x) WriteRegBits16(IO_SW_OVRD3,0x8,3,x)
#define Rd_IO_SW_OVRD3_ovrd_tx_pause_val(x) ReadRegBits16(IO_SW_OVRD3,0x8,3)
#define IO_SW_OVRD3_OVRD_TX_PAUSE_VAL_MASK                         0x0008
#define IO_SW_OVRD3_OVRD_TX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD3_OVRD_TX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD3_OVRD_TX_PAUSE_VAL_SHIFT                        3

/* IO :: SW_OVRD3 :: ovrd_link_val [02:02] */
#define Wr_IO_SW_OVRD3_ovrd_link_val(x) WriteRegBits16(IO_SW_OVRD3,0x4,2,x)
#define Rd_IO_SW_OVRD3_ovrd_link_val(x) ReadRegBits16(IO_SW_OVRD3,0x4,2)
#define IO_SW_OVRD3_OVRD_LINK_VAL_MASK                             0x0004
#define IO_SW_OVRD3_OVRD_LINK_VAL_ALIGN                            0
#define IO_SW_OVRD3_OVRD_LINK_VAL_BITS                             1
#define IO_SW_OVRD3_OVRD_LINK_VAL_SHIFT                            2

/* IO :: SW_OVRD3 :: ovrd_spd_val [01:00] */
#define Wr_IO_SW_OVRD3_ovrd_spd_val(x) WriteRegBits16(IO_SW_OVRD3,0x3,0,x)
#define Rd_IO_SW_OVRD3_ovrd_spd_val(x) ReadRegBits16(IO_SW_OVRD3,0x3,0)
#define IO_SW_OVRD3_OVRD_SPD_VAL_MASK                              0x0003
#define IO_SW_OVRD3_OVRD_SPD_VAL_ALIGN                             0
#define IO_SW_OVRD3_OVRD_SPD_VAL_BITS                              2
#define IO_SW_OVRD3_OVRD_SPD_VAL_SHIFT                             0


/****************************************************************************
 * IO :: SW_OVRD4
 ***************************************************************************/
/* IO :: SW_OVRD4 :: reserved0 [15:12] */
#define IO_SW_OVRD4_RESERVED0_MASK                                 0xf000
#define IO_SW_OVRD4_RESERVED0_ALIGN                                0
#define IO_SW_OVRD4_RESERVED0_BITS                                 4
#define IO_SW_OVRD4_RESERVED0_SHIFT                                12

/* IO :: SW_OVRD4 :: ovrd_rx_pause_sel [11:11] */
#define Wr_IO_SW_OVRD4_ovrd_rx_pause_sel(x) WriteRegBits16(IO_SW_OVRD4,0x800,11,x)
#define Rd_IO_SW_OVRD4_ovrd_rx_pause_sel(x) ReadRegBits16(IO_SW_OVRD4,0x800,11)
#define IO_SW_OVRD4_OVRD_RX_PAUSE_SEL_MASK                         0x0800
#define IO_SW_OVRD4_OVRD_RX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD4_OVRD_RX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD4_OVRD_RX_PAUSE_SEL_SHIFT                        11

/* IO :: SW_OVRD4 :: ovrd_tx_pause_sel [10:10] */
#define Wr_IO_SW_OVRD4_ovrd_tx_pause_sel(x) WriteRegBits16(IO_SW_OVRD4,0x400,10,x)
#define Rd_IO_SW_OVRD4_ovrd_tx_pause_sel(x) ReadRegBits16(IO_SW_OVRD4,0x400,10)
#define IO_SW_OVRD4_OVRD_TX_PAUSE_SEL_MASK                         0x0400
#define IO_SW_OVRD4_OVRD_TX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD4_OVRD_TX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD4_OVRD_TX_PAUSE_SEL_SHIFT                        10

/* IO :: SW_OVRD4 :: ovrd_link_sel [09:09] */
#define Wr_IO_SW_OVRD4_ovrd_link_sel(x) WriteRegBits16(IO_SW_OVRD4,0x200,9,x)
#define Rd_IO_SW_OVRD4_ovrd_link_sel(x) ReadRegBits16(IO_SW_OVRD4,0x200,9)
#define IO_SW_OVRD4_OVRD_LINK_SEL_MASK                             0x0200
#define IO_SW_OVRD4_OVRD_LINK_SEL_ALIGN                            0
#define IO_SW_OVRD4_OVRD_LINK_SEL_BITS                             1
#define IO_SW_OVRD4_OVRD_LINK_SEL_SHIFT                            9

/* IO :: SW_OVRD4 :: ovrd_spd_sel [08:08] */
#define Wr_IO_SW_OVRD4_ovrd_spd_sel(x) WriteRegBits16(IO_SW_OVRD4,0x100,8,x)
#define Rd_IO_SW_OVRD4_ovrd_spd_sel(x) ReadRegBits16(IO_SW_OVRD4,0x100,8)
#define IO_SW_OVRD4_OVRD_SPD_SEL_MASK                              0x0100
#define IO_SW_OVRD4_OVRD_SPD_SEL_ALIGN                             0
#define IO_SW_OVRD4_OVRD_SPD_SEL_BITS                              1
#define IO_SW_OVRD4_OVRD_SPD_SEL_SHIFT                             8

/* IO :: SW_OVRD4 :: reserved1 [07:05] */
#define IO_SW_OVRD4_RESERVED1_MASK                                 0x00e0
#define IO_SW_OVRD4_RESERVED1_ALIGN                                0
#define IO_SW_OVRD4_RESERVED1_BITS                                 3
#define IO_SW_OVRD4_RESERVED1_SHIFT                                5

/* IO :: SW_OVRD4 :: ovrd_rx_pause_val [04:04] */
#define Wr_IO_SW_OVRD4_ovrd_rx_pause_val(x) WriteRegBits16(IO_SW_OVRD4,0x10,4,x)
#define Rd_IO_SW_OVRD4_ovrd_rx_pause_val(x) ReadRegBits16(IO_SW_OVRD4,0x10,4)
#define IO_SW_OVRD4_OVRD_RX_PAUSE_VAL_MASK                         0x0010
#define IO_SW_OVRD4_OVRD_RX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD4_OVRD_RX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD4_OVRD_RX_PAUSE_VAL_SHIFT                        4

/* IO :: SW_OVRD4 :: ovrd_tx_pause_val [03:03] */
#define Wr_IO_SW_OVRD4_ovrd_tx_pause_val(x) WriteRegBits16(IO_SW_OVRD4,0x8,3,x)
#define Rd_IO_SW_OVRD4_ovrd_tx_pause_val(x) ReadRegBits16(IO_SW_OVRD4,0x8,3)
#define IO_SW_OVRD4_OVRD_TX_PAUSE_VAL_MASK                         0x0008
#define IO_SW_OVRD4_OVRD_TX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD4_OVRD_TX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD4_OVRD_TX_PAUSE_VAL_SHIFT                        3

/* IO :: SW_OVRD4 :: ovrd_link_val [02:02] */
#define Wr_IO_SW_OVRD4_ovrd_link_val(x) WriteRegBits16(IO_SW_OVRD4,0x4,2,x)
#define Rd_IO_SW_OVRD4_ovrd_link_val(x) ReadRegBits16(IO_SW_OVRD4,0x4,2)
#define IO_SW_OVRD4_OVRD_LINK_VAL_MASK                             0x0004
#define IO_SW_OVRD4_OVRD_LINK_VAL_ALIGN                            0
#define IO_SW_OVRD4_OVRD_LINK_VAL_BITS                             1
#define IO_SW_OVRD4_OVRD_LINK_VAL_SHIFT                            2

/* IO :: SW_OVRD4 :: ovrd_spd_val [01:00] */
#define Wr_IO_SW_OVRD4_ovrd_spd_val(x) WriteRegBits16(IO_SW_OVRD4,0x3,0,x)
#define Rd_IO_SW_OVRD4_ovrd_spd_val(x) ReadRegBits16(IO_SW_OVRD4,0x3,0)
#define IO_SW_OVRD4_OVRD_SPD_VAL_MASK                              0x0003
#define IO_SW_OVRD4_OVRD_SPD_VAL_ALIGN                             0
#define IO_SW_OVRD4_OVRD_SPD_VAL_BITS                              2
#define IO_SW_OVRD4_OVRD_SPD_VAL_SHIFT                             0


/****************************************************************************
 * IO :: SW_OVRD5
 ***************************************************************************/
/* IO :: SW_OVRD5 :: reserved0 [15:12] */
#define IO_SW_OVRD5_RESERVED0_MASK                                 0xf000
#define IO_SW_OVRD5_RESERVED0_ALIGN                                0
#define IO_SW_OVRD5_RESERVED0_BITS                                 4
#define IO_SW_OVRD5_RESERVED0_SHIFT                                12

/* IO :: SW_OVRD5 :: ovrd_rx_pause_sel [11:11] */
#define Wr_IO_SW_OVRD5_ovrd_rx_pause_sel(x) WriteRegBits16(IO_SW_OVRD5,0x800,11,x)
#define Rd_IO_SW_OVRD5_ovrd_rx_pause_sel(x) ReadRegBits16(IO_SW_OVRD5,0x800,11)
#define IO_SW_OVRD5_OVRD_RX_PAUSE_SEL_MASK                         0x0800
#define IO_SW_OVRD5_OVRD_RX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD5_OVRD_RX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD5_OVRD_RX_PAUSE_SEL_SHIFT                        11

/* IO :: SW_OVRD5 :: ovrd_tx_pause_sel [10:10] */
#define Wr_IO_SW_OVRD5_ovrd_tx_pause_sel(x) WriteRegBits16(IO_SW_OVRD5,0x400,10,x)
#define Rd_IO_SW_OVRD5_ovrd_tx_pause_sel(x) ReadRegBits16(IO_SW_OVRD5,0x400,10)
#define IO_SW_OVRD5_OVRD_TX_PAUSE_SEL_MASK                         0x0400
#define IO_SW_OVRD5_OVRD_TX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD5_OVRD_TX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD5_OVRD_TX_PAUSE_SEL_SHIFT                        10

/* IO :: SW_OVRD5 :: ovrd_link_sel [09:09] */
#define Wr_IO_SW_OVRD5_ovrd_link_sel(x) WriteRegBits16(IO_SW_OVRD5,0x200,9,x)
#define Rd_IO_SW_OVRD5_ovrd_link_sel(x) ReadRegBits16(IO_SW_OVRD5,0x200,9)
#define IO_SW_OVRD5_OVRD_LINK_SEL_MASK                             0x0200
#define IO_SW_OVRD5_OVRD_LINK_SEL_ALIGN                            0
#define IO_SW_OVRD5_OVRD_LINK_SEL_BITS                             1
#define IO_SW_OVRD5_OVRD_LINK_SEL_SHIFT                            9

/* IO :: SW_OVRD5 :: ovrd_spd_sel [08:08] */
#define Wr_IO_SW_OVRD5_ovrd_spd_sel(x) WriteRegBits16(IO_SW_OVRD5,0x100,8,x)
#define Rd_IO_SW_OVRD5_ovrd_spd_sel(x) ReadRegBits16(IO_SW_OVRD5,0x100,8)
#define IO_SW_OVRD5_OVRD_SPD_SEL_MASK                              0x0100
#define IO_SW_OVRD5_OVRD_SPD_SEL_ALIGN                             0
#define IO_SW_OVRD5_OVRD_SPD_SEL_BITS                              1
#define IO_SW_OVRD5_OVRD_SPD_SEL_SHIFT                             8

/* IO :: SW_OVRD5 :: reserved1 [07:05] */
#define IO_SW_OVRD5_RESERVED1_MASK                                 0x00e0
#define IO_SW_OVRD5_RESERVED1_ALIGN                                0
#define IO_SW_OVRD5_RESERVED1_BITS                                 3
#define IO_SW_OVRD5_RESERVED1_SHIFT                                5

/* IO :: SW_OVRD5 :: ovrd_rx_pause_val [04:04] */
#define Wr_IO_SW_OVRD5_ovrd_rx_pause_val(x) WriteRegBits16(IO_SW_OVRD5,0x10,4,x)
#define Rd_IO_SW_OVRD5_ovrd_rx_pause_val(x) ReadRegBits16(IO_SW_OVRD5,0x10,4)
#define IO_SW_OVRD5_OVRD_RX_PAUSE_VAL_MASK                         0x0010
#define IO_SW_OVRD5_OVRD_RX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD5_OVRD_RX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD5_OVRD_RX_PAUSE_VAL_SHIFT                        4

/* IO :: SW_OVRD5 :: ovrd_tx_pause_val [03:03] */
#define Wr_IO_SW_OVRD5_ovrd_tx_pause_val(x) WriteRegBits16(IO_SW_OVRD5,0x8,3,x)
#define Rd_IO_SW_OVRD5_ovrd_tx_pause_val(x) ReadRegBits16(IO_SW_OVRD5,0x8,3)
#define IO_SW_OVRD5_OVRD_TX_PAUSE_VAL_MASK                         0x0008
#define IO_SW_OVRD5_OVRD_TX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD5_OVRD_TX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD5_OVRD_TX_PAUSE_VAL_SHIFT                        3

/* IO :: SW_OVRD5 :: ovrd_link_val [02:02] */
#define Wr_IO_SW_OVRD5_ovrd_link_val(x) WriteRegBits16(IO_SW_OVRD5,0x4,2,x)
#define Rd_IO_SW_OVRD5_ovrd_link_val(x) ReadRegBits16(IO_SW_OVRD5,0x4,2)
#define IO_SW_OVRD5_OVRD_LINK_VAL_MASK                             0x0004
#define IO_SW_OVRD5_OVRD_LINK_VAL_ALIGN                            0
#define IO_SW_OVRD5_OVRD_LINK_VAL_BITS                             1
#define IO_SW_OVRD5_OVRD_LINK_VAL_SHIFT                            2

/* IO :: SW_OVRD5 :: ovrd_spd_val [01:00] */
#define Wr_IO_SW_OVRD5_ovrd_spd_val(x) WriteRegBits16(IO_SW_OVRD5,0x3,0,x)
#define Rd_IO_SW_OVRD5_ovrd_spd_val(x) ReadRegBits16(IO_SW_OVRD5,0x3,0)
#define IO_SW_OVRD5_OVRD_SPD_VAL_MASK                              0x0003
#define IO_SW_OVRD5_OVRD_SPD_VAL_ALIGN                             0
#define IO_SW_OVRD5_OVRD_SPD_VAL_BITS                              2
#define IO_SW_OVRD5_OVRD_SPD_VAL_SHIFT                             0


/****************************************************************************
 * IO :: SW_OVRD6
 ***************************************************************************/
/* IO :: SW_OVRD6 :: reserved0 [15:12] */
#define IO_SW_OVRD6_RESERVED0_MASK                                 0xf000
#define IO_SW_OVRD6_RESERVED0_ALIGN                                0
#define IO_SW_OVRD6_RESERVED0_BITS                                 4
#define IO_SW_OVRD6_RESERVED0_SHIFT                                12

/* IO :: SW_OVRD6 :: ovrd_rx_pause_sel [11:11] */
#define Wr_IO_SW_OVRD6_ovrd_rx_pause_sel(x) WriteRegBits16(IO_SW_OVRD6,0x800,11,x)
#define Rd_IO_SW_OVRD6_ovrd_rx_pause_sel(x) ReadRegBits16(IO_SW_OVRD6,0x800,11)
#define IO_SW_OVRD6_OVRD_RX_PAUSE_SEL_MASK                         0x0800
#define IO_SW_OVRD6_OVRD_RX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD6_OVRD_RX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD6_OVRD_RX_PAUSE_SEL_SHIFT                        11

/* IO :: SW_OVRD6 :: ovrd_tx_pause_sel [10:10] */
#define Wr_IO_SW_OVRD6_ovrd_tx_pause_sel(x) WriteRegBits16(IO_SW_OVRD6,0x400,10,x)
#define Rd_IO_SW_OVRD6_ovrd_tx_pause_sel(x) ReadRegBits16(IO_SW_OVRD6,0x400,10)
#define IO_SW_OVRD6_OVRD_TX_PAUSE_SEL_MASK                         0x0400
#define IO_SW_OVRD6_OVRD_TX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD6_OVRD_TX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD6_OVRD_TX_PAUSE_SEL_SHIFT                        10

/* IO :: SW_OVRD6 :: ovrd_link_sel [09:09] */
#define Wr_IO_SW_OVRD6_ovrd_link_sel(x) WriteRegBits16(IO_SW_OVRD6,0x200,9,x)
#define Rd_IO_SW_OVRD6_ovrd_link_sel(x) ReadRegBits16(IO_SW_OVRD6,0x200,9)
#define IO_SW_OVRD6_OVRD_LINK_SEL_MASK                             0x0200
#define IO_SW_OVRD6_OVRD_LINK_SEL_ALIGN                            0
#define IO_SW_OVRD6_OVRD_LINK_SEL_BITS                             1
#define IO_SW_OVRD6_OVRD_LINK_SEL_SHIFT                            9

/* IO :: SW_OVRD6 :: ovrd_spd_sel [08:08] */
#define Wr_IO_SW_OVRD6_ovrd_spd_sel(x) WriteRegBits16(IO_SW_OVRD6,0x100,8,x)
#define Rd_IO_SW_OVRD6_ovrd_spd_sel(x) ReadRegBits16(IO_SW_OVRD6,0x100,8)
#define IO_SW_OVRD6_OVRD_SPD_SEL_MASK                              0x0100
#define IO_SW_OVRD6_OVRD_SPD_SEL_ALIGN                             0
#define IO_SW_OVRD6_OVRD_SPD_SEL_BITS                              1
#define IO_SW_OVRD6_OVRD_SPD_SEL_SHIFT                             8

/* IO :: SW_OVRD6 :: reserved1 [07:05] */
#define IO_SW_OVRD6_RESERVED1_MASK                                 0x00e0
#define IO_SW_OVRD6_RESERVED1_ALIGN                                0
#define IO_SW_OVRD6_RESERVED1_BITS                                 3
#define IO_SW_OVRD6_RESERVED1_SHIFT                                5

/* IO :: SW_OVRD6 :: ovrd_rx_pause_val [04:04] */
#define Wr_IO_SW_OVRD6_ovrd_rx_pause_val(x) WriteRegBits16(IO_SW_OVRD6,0x10,4,x)
#define Rd_IO_SW_OVRD6_ovrd_rx_pause_val(x) ReadRegBits16(IO_SW_OVRD6,0x10,4)
#define IO_SW_OVRD6_OVRD_RX_PAUSE_VAL_MASK                         0x0010
#define IO_SW_OVRD6_OVRD_RX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD6_OVRD_RX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD6_OVRD_RX_PAUSE_VAL_SHIFT                        4

/* IO :: SW_OVRD6 :: ovrd_tx_pause_val [03:03] */
#define Wr_IO_SW_OVRD6_ovrd_tx_pause_val(x) WriteRegBits16(IO_SW_OVRD6,0x8,3,x)
#define Rd_IO_SW_OVRD6_ovrd_tx_pause_val(x) ReadRegBits16(IO_SW_OVRD6,0x8,3)
#define IO_SW_OVRD6_OVRD_TX_PAUSE_VAL_MASK                         0x0008
#define IO_SW_OVRD6_OVRD_TX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD6_OVRD_TX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD6_OVRD_TX_PAUSE_VAL_SHIFT                        3

/* IO :: SW_OVRD6 :: ovrd_link_val [02:02] */
#define Wr_IO_SW_OVRD6_ovrd_link_val(x) WriteRegBits16(IO_SW_OVRD6,0x4,2,x)
#define Rd_IO_SW_OVRD6_ovrd_link_val(x) ReadRegBits16(IO_SW_OVRD6,0x4,2)
#define IO_SW_OVRD6_OVRD_LINK_VAL_MASK                             0x0004
#define IO_SW_OVRD6_OVRD_LINK_VAL_ALIGN                            0
#define IO_SW_OVRD6_OVRD_LINK_VAL_BITS                             1
#define IO_SW_OVRD6_OVRD_LINK_VAL_SHIFT                            2

/* IO :: SW_OVRD6 :: ovrd_spd_val [01:00] */
#define Wr_IO_SW_OVRD6_ovrd_spd_val(x) WriteRegBits16(IO_SW_OVRD6,0x3,0,x)
#define Rd_IO_SW_OVRD6_ovrd_spd_val(x) ReadRegBits16(IO_SW_OVRD6,0x3,0)
#define IO_SW_OVRD6_OVRD_SPD_VAL_MASK                              0x0003
#define IO_SW_OVRD6_OVRD_SPD_VAL_ALIGN                             0
#define IO_SW_OVRD6_OVRD_SPD_VAL_BITS                              2
#define IO_SW_OVRD6_OVRD_SPD_VAL_SHIFT                             0


/****************************************************************************
 * IO :: SW_OVRD7
 ***************************************************************************/
/* IO :: SW_OVRD7 :: reserved0 [15:12] */
#define IO_SW_OVRD7_RESERVED0_MASK                                 0xf000
#define IO_SW_OVRD7_RESERVED0_ALIGN                                0
#define IO_SW_OVRD7_RESERVED0_BITS                                 4
#define IO_SW_OVRD7_RESERVED0_SHIFT                                12

/* IO :: SW_OVRD7 :: ovrd_rx_pause_sel [11:11] */
#define Wr_IO_SW_OVRD7_ovrd_rx_pause_sel(x) WriteRegBits16(IO_SW_OVRD7,0x800,11,x)
#define Rd_IO_SW_OVRD7_ovrd_rx_pause_sel(x) ReadRegBits16(IO_SW_OVRD7,0x800,11)
#define IO_SW_OVRD7_OVRD_RX_PAUSE_SEL_MASK                         0x0800
#define IO_SW_OVRD7_OVRD_RX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD7_OVRD_RX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD7_OVRD_RX_PAUSE_SEL_SHIFT                        11

/* IO :: SW_OVRD7 :: ovrd_tx_pause_sel [10:10] */
#define Wr_IO_SW_OVRD7_ovrd_tx_pause_sel(x) WriteRegBits16(IO_SW_OVRD7,0x400,10,x)
#define Rd_IO_SW_OVRD7_ovrd_tx_pause_sel(x) ReadRegBits16(IO_SW_OVRD7,0x400,10)
#define IO_SW_OVRD7_OVRD_TX_PAUSE_SEL_MASK                         0x0400
#define IO_SW_OVRD7_OVRD_TX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD7_OVRD_TX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD7_OVRD_TX_PAUSE_SEL_SHIFT                        10

/* IO :: SW_OVRD7 :: ovrd_link_sel [09:09] */
#define Wr_IO_SW_OVRD7_ovrd_link_sel(x) WriteRegBits16(IO_SW_OVRD7,0x200,9,x)
#define Rd_IO_SW_OVRD7_ovrd_link_sel(x) ReadRegBits16(IO_SW_OVRD7,0x200,9)
#define IO_SW_OVRD7_OVRD_LINK_SEL_MASK                             0x0200
#define IO_SW_OVRD7_OVRD_LINK_SEL_ALIGN                            0
#define IO_SW_OVRD7_OVRD_LINK_SEL_BITS                             1
#define IO_SW_OVRD7_OVRD_LINK_SEL_SHIFT                            9

/* IO :: SW_OVRD7 :: ovrd_spd_sel [08:08] */
#define Wr_IO_SW_OVRD7_ovrd_spd_sel(x) WriteRegBits16(IO_SW_OVRD7,0x100,8,x)
#define Rd_IO_SW_OVRD7_ovrd_spd_sel(x) ReadRegBits16(IO_SW_OVRD7,0x100,8)
#define IO_SW_OVRD7_OVRD_SPD_SEL_MASK                              0x0100
#define IO_SW_OVRD7_OVRD_SPD_SEL_ALIGN                             0
#define IO_SW_OVRD7_OVRD_SPD_SEL_BITS                              1
#define IO_SW_OVRD7_OVRD_SPD_SEL_SHIFT                             8

/* IO :: SW_OVRD7 :: reserved1 [07:05] */
#define IO_SW_OVRD7_RESERVED1_MASK                                 0x00e0
#define IO_SW_OVRD7_RESERVED1_ALIGN                                0
#define IO_SW_OVRD7_RESERVED1_BITS                                 3
#define IO_SW_OVRD7_RESERVED1_SHIFT                                5

/* IO :: SW_OVRD7 :: ovrd_rx_pause_val [04:04] */
#define Wr_IO_SW_OVRD7_ovrd_rx_pause_val(x) WriteRegBits16(IO_SW_OVRD7,0x10,4,x)
#define Rd_IO_SW_OVRD7_ovrd_rx_pause_val(x) ReadRegBits16(IO_SW_OVRD7,0x10,4)
#define IO_SW_OVRD7_OVRD_RX_PAUSE_VAL_MASK                         0x0010
#define IO_SW_OVRD7_OVRD_RX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD7_OVRD_RX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD7_OVRD_RX_PAUSE_VAL_SHIFT                        4

/* IO :: SW_OVRD7 :: ovrd_tx_pause_val [03:03] */
#define Wr_IO_SW_OVRD7_ovrd_tx_pause_val(x) WriteRegBits16(IO_SW_OVRD7,0x8,3,x)
#define Rd_IO_SW_OVRD7_ovrd_tx_pause_val(x) ReadRegBits16(IO_SW_OVRD7,0x8,3)
#define IO_SW_OVRD7_OVRD_TX_PAUSE_VAL_MASK                         0x0008
#define IO_SW_OVRD7_OVRD_TX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD7_OVRD_TX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD7_OVRD_TX_PAUSE_VAL_SHIFT                        3

/* IO :: SW_OVRD7 :: ovrd_link_val [02:02] */
#define Wr_IO_SW_OVRD7_ovrd_link_val(x) WriteRegBits16(IO_SW_OVRD7,0x4,2,x)
#define Rd_IO_SW_OVRD7_ovrd_link_val(x) ReadRegBits16(IO_SW_OVRD7,0x4,2)
#define IO_SW_OVRD7_OVRD_LINK_VAL_MASK                             0x0004
#define IO_SW_OVRD7_OVRD_LINK_VAL_ALIGN                            0
#define IO_SW_OVRD7_OVRD_LINK_VAL_BITS                             1
#define IO_SW_OVRD7_OVRD_LINK_VAL_SHIFT                            2

/* IO :: SW_OVRD7 :: ovrd_spd_val [01:00] */
#define Wr_IO_SW_OVRD7_ovrd_spd_val(x) WriteRegBits16(IO_SW_OVRD7,0x3,0,x)
#define Rd_IO_SW_OVRD7_ovrd_spd_val(x) ReadRegBits16(IO_SW_OVRD7,0x3,0)
#define IO_SW_OVRD7_OVRD_SPD_VAL_MASK                              0x0003
#define IO_SW_OVRD7_OVRD_SPD_VAL_ALIGN                             0
#define IO_SW_OVRD7_OVRD_SPD_VAL_BITS                              2
#define IO_SW_OVRD7_OVRD_SPD_VAL_SHIFT                             0


/****************************************************************************
 * IO :: SW_OVRD8
 ***************************************************************************/
/* IO :: SW_OVRD8 :: reserved0 [15:12] */
#define IO_SW_OVRD8_RESERVED0_MASK                                 0xf000
#define IO_SW_OVRD8_RESERVED0_ALIGN                                0
#define IO_SW_OVRD8_RESERVED0_BITS                                 4
#define IO_SW_OVRD8_RESERVED0_SHIFT                                12

/* IO :: SW_OVRD8 :: ovrd_rx_pause_sel [11:11] */
#define Wr_IO_SW_OVRD8_ovrd_rx_pause_sel(x) WriteRegBits16(IO_SW_OVRD8,0x800,11,x)
#define Rd_IO_SW_OVRD8_ovrd_rx_pause_sel(x) ReadRegBits16(IO_SW_OVRD8,0x800,11)
#define IO_SW_OVRD8_OVRD_RX_PAUSE_SEL_MASK                         0x0800
#define IO_SW_OVRD8_OVRD_RX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD8_OVRD_RX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD8_OVRD_RX_PAUSE_SEL_SHIFT                        11

/* IO :: SW_OVRD8 :: ovrd_tx_pause_sel [10:10] */
#define Wr_IO_SW_OVRD8_ovrd_tx_pause_sel(x) WriteRegBits16(IO_SW_OVRD8,0x400,10,x)
#define Rd_IO_SW_OVRD8_ovrd_tx_pause_sel(x) ReadRegBits16(IO_SW_OVRD8,0x400,10)
#define IO_SW_OVRD8_OVRD_TX_PAUSE_SEL_MASK                         0x0400
#define IO_SW_OVRD8_OVRD_TX_PAUSE_SEL_ALIGN                        0
#define IO_SW_OVRD8_OVRD_TX_PAUSE_SEL_BITS                         1
#define IO_SW_OVRD8_OVRD_TX_PAUSE_SEL_SHIFT                        10

/* IO :: SW_OVRD8 :: ovrd_link_sel [09:09] */
#define Wr_IO_SW_OVRD8_ovrd_link_sel(x) WriteRegBits16(IO_SW_OVRD8,0x200,9,x)
#define Rd_IO_SW_OVRD8_ovrd_link_sel(x) ReadRegBits16(IO_SW_OVRD8,0x200,9)
#define IO_SW_OVRD8_OVRD_LINK_SEL_MASK                             0x0200
#define IO_SW_OVRD8_OVRD_LINK_SEL_ALIGN                            0
#define IO_SW_OVRD8_OVRD_LINK_SEL_BITS                             1
#define IO_SW_OVRD8_OVRD_LINK_SEL_SHIFT                            9

/* IO :: SW_OVRD8 :: ovrd_spd_sel [08:08] */
#define Wr_IO_SW_OVRD8_ovrd_spd_sel(x) WriteRegBits16(IO_SW_OVRD8,0x100,8,x)
#define Rd_IO_SW_OVRD8_ovrd_spd_sel(x) ReadRegBits16(IO_SW_OVRD8,0x100,8)
#define IO_SW_OVRD8_OVRD_SPD_SEL_MASK                              0x0100
#define IO_SW_OVRD8_OVRD_SPD_SEL_ALIGN                             0
#define IO_SW_OVRD8_OVRD_SPD_SEL_BITS                              1
#define IO_SW_OVRD8_OVRD_SPD_SEL_SHIFT                             8

/* IO :: SW_OVRD8 :: reserved1 [07:05] */
#define IO_SW_OVRD8_RESERVED1_MASK                                 0x00e0
#define IO_SW_OVRD8_RESERVED1_ALIGN                                0
#define IO_SW_OVRD8_RESERVED1_BITS                                 3
#define IO_SW_OVRD8_RESERVED1_SHIFT                                5

/* IO :: SW_OVRD8 :: ovrd_rx_pause_val [04:04] */
#define Wr_IO_SW_OVRD8_ovrd_rx_pause_val(x) WriteRegBits16(IO_SW_OVRD8,0x10,4,x)
#define Rd_IO_SW_OVRD8_ovrd_rx_pause_val(x) ReadRegBits16(IO_SW_OVRD8,0x10,4)
#define IO_SW_OVRD8_OVRD_RX_PAUSE_VAL_MASK                         0x0010
#define IO_SW_OVRD8_OVRD_RX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD8_OVRD_RX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD8_OVRD_RX_PAUSE_VAL_SHIFT                        4

/* IO :: SW_OVRD8 :: ovrd_tx_pause_val [03:03] */
#define Wr_IO_SW_OVRD8_ovrd_tx_pause_val(x) WriteRegBits16(IO_SW_OVRD8,0x8,3,x)
#define Rd_IO_SW_OVRD8_ovrd_tx_pause_val(x) ReadRegBits16(IO_SW_OVRD8,0x8,3)
#define IO_SW_OVRD8_OVRD_TX_PAUSE_VAL_MASK                         0x0008
#define IO_SW_OVRD8_OVRD_TX_PAUSE_VAL_ALIGN                        0
#define IO_SW_OVRD8_OVRD_TX_PAUSE_VAL_BITS                         1
#define IO_SW_OVRD8_OVRD_TX_PAUSE_VAL_SHIFT                        3

/* IO :: SW_OVRD8 :: ovrd_link_val [02:02] */
#define Wr_IO_SW_OVRD8_ovrd_link_val(x) WriteRegBits16(IO_SW_OVRD8,0x4,2,x)
#define Rd_IO_SW_OVRD8_ovrd_link_val(x) ReadRegBits16(IO_SW_OVRD8,0x4,2)
#define IO_SW_OVRD8_OVRD_LINK_VAL_MASK                             0x0004
#define IO_SW_OVRD8_OVRD_LINK_VAL_ALIGN                            0
#define IO_SW_OVRD8_OVRD_LINK_VAL_BITS                             1
#define IO_SW_OVRD8_OVRD_LINK_VAL_SHIFT                            2

/* IO :: SW_OVRD8 :: ovrd_spd_val [01:00] */
#define Wr_IO_SW_OVRD8_ovrd_spd_val(x) WriteRegBits16(IO_SW_OVRD8,0x3,0,x)
#define Rd_IO_SW_OVRD8_ovrd_spd_val(x) ReadRegBits16(IO_SW_OVRD8,0x3,0)
#define IO_SW_OVRD8_OVRD_SPD_VAL_MASK                              0x0003
#define IO_SW_OVRD8_OVRD_SPD_VAL_ALIGN                             0
#define IO_SW_OVRD8_OVRD_SPD_VAL_BITS                              2
#define IO_SW_OVRD8_OVRD_SPD_VAL_SHIFT                             0


/****************************************************************************
 * IO :: TEST_BUS_SELECT
 ***************************************************************************/
/* IO :: TEST_BUS_SELECT :: ovstb [15:15] */
#define Wr_IO_TEST_BUS_SELECT_ovstb(x) WriteRegBits16(IO_TEST_BUS_SELECT,0x8000,15,x)
#define Rd_IO_TEST_BUS_SELECT_ovstb(x) ReadRegBits16(IO_TEST_BUS_SELECT,0x8000,15)
#define IO_TEST_BUS_SELECT_OVSTB_MASK                              0x8000
#define IO_TEST_BUS_SELECT_OVSTB_ALIGN                             0
#define IO_TEST_BUS_SELECT_OVSTB_BITS                              1
#define IO_TEST_BUS_SELECT_OVSTB_SHIFT                             15

/* IO :: TEST_BUS_SELECT :: burnin_en [14:14] */
#define Wr_IO_TEST_BUS_SELECT_burnin_en(x) WriteRegBits16(IO_TEST_BUS_SELECT,0x4000,14,x)
#define Rd_IO_TEST_BUS_SELECT_burnin_en(x) ReadRegBits16(IO_TEST_BUS_SELECT,0x4000,14)
#define IO_TEST_BUS_SELECT_BURNIN_EN_MASK                          0x4000
#define IO_TEST_BUS_SELECT_BURNIN_EN_ALIGN                         0
#define IO_TEST_BUS_SELECT_BURNIN_EN_BITS                          1
#define IO_TEST_BUS_SELECT_BURNIN_EN_SHIFT                         14

/* IO :: TEST_BUS_SELECT :: reserved0 [13:03] */
#define IO_TEST_BUS_SELECT_RESERVED0_MASK                          0x3ff8
#define IO_TEST_BUS_SELECT_RESERVED0_ALIGN                         0
#define IO_TEST_BUS_SELECT_RESERVED0_BITS                          11
#define IO_TEST_BUS_SELECT_RESERVED0_SHIFT                         3

/* IO :: TEST_BUS_SELECT :: select_test_bus [02:00] */
#define Wr_IO_TEST_BUS_SELECT_select_test_bus(x) WriteRegBits16(IO_TEST_BUS_SELECT,0x7,0,x)
#define Rd_IO_TEST_BUS_SELECT_select_test_bus(x) ReadRegBits16(IO_TEST_BUS_SELECT,0x7,0)
#define IO_TEST_BUS_SELECT_SELECT_TEST_BUS_MASK                    0x0007
#define IO_TEST_BUS_SELECT_SELECT_TEST_BUS_ALIGN                   0
#define IO_TEST_BUS_SELECT_SELECT_TEST_BUS_BITS                    3
#define IO_TEST_BUS_SELECT_SELECT_TEST_BUS_SHIFT                   0


/****************************************************************************
 * IO :: P1588_CONFIG
 ***************************************************************************/
/* IO :: P1588_CONFIG :: reserved0 [15:01] */
#define IO_P1588_CONFIG_RESERVED0_MASK                             0xfffe
#define IO_P1588_CONFIG_RESERVED0_ALIGN                            0
#define IO_P1588_CONFIG_RESERVED0_BITS                             15
#define IO_P1588_CONFIG_RESERVED0_SHIFT                            1

/* IO :: P1588_CONFIG :: p1588_sync_out_sel [00:00] */
#define Wr_IO_P1588_CONFIG_p1588_sync_out_sel(x) WriteRegBits16(IO_P1588_CONFIG,0x1,0,x)
#define Rd_IO_P1588_CONFIG_p1588_sync_out_sel(x) ReadRegBits16(IO_P1588_CONFIG,0x1,0)
#define IO_P1588_CONFIG_P1588_SYNC_OUT_SEL_MASK                    0x0001
#define IO_P1588_CONFIG_P1588_SYNC_OUT_SEL_ALIGN                   0
#define IO_P1588_CONFIG_P1588_SYNC_OUT_SEL_BITS                    1
#define IO_P1588_CONFIG_P1588_SYNC_OUT_SEL_SHIFT                   0


/****************************************************************************
 * IO :: P1588_SYNC_GEN
 ***************************************************************************/
/* IO :: P1588_SYNC_GEN :: reserved0 [15:04] */
#define IO_P1588_SYNC_GEN_RESERVED0_MASK                           0xfff0
#define IO_P1588_SYNC_GEN_RESERVED0_ALIGN                          0
#define IO_P1588_SYNC_GEN_RESERVED0_BITS                           12
#define IO_P1588_SYNC_GEN_RESERVED0_SHIFT                          4

/* IO :: P1588_SYNC_GEN :: io_sync_in1 [03:03] */
#define Wr_IO_P1588_SYNC_GEN_io_sync_in1(x) WriteRegBits16(IO_P1588_SYNC_GEN,0x8,3,x)
#define Rd_IO_P1588_SYNC_GEN_io_sync_in1(x) ReadRegBits16(IO_P1588_SYNC_GEN,0x8,3)
#define IO_P1588_SYNC_GEN_IO_SYNC_IN1_MASK                         0x0008
#define IO_P1588_SYNC_GEN_IO_SYNC_IN1_ALIGN                        0
#define IO_P1588_SYNC_GEN_IO_SYNC_IN1_BITS                         1
#define IO_P1588_SYNC_GEN_IO_SYNC_IN1_SHIFT                        3

/* IO :: P1588_SYNC_GEN :: io_sync_in0 [02:02] */
#define Wr_IO_P1588_SYNC_GEN_io_sync_in0(x) WriteRegBits16(IO_P1588_SYNC_GEN,0x4,2,x)
#define Rd_IO_P1588_SYNC_GEN_io_sync_in0(x) ReadRegBits16(IO_P1588_SYNC_GEN,0x4,2)
#define IO_P1588_SYNC_GEN_IO_SYNC_IN0_MASK                         0x0004
#define IO_P1588_SYNC_GEN_IO_SYNC_IN0_ALIGN                        0
#define IO_P1588_SYNC_GEN_IO_SYNC_IN0_BITS                         1
#define IO_P1588_SYNC_GEN_IO_SYNC_IN0_SHIFT                        2

/* IO :: P1588_SYNC_GEN :: brphy_sync_in1 [01:01] */
#define Wr_IO_P1588_SYNC_GEN_brphy_sync_in1(x) WriteRegBits16(IO_P1588_SYNC_GEN,0x2,1,x)
#define Rd_IO_P1588_SYNC_GEN_brphy_sync_in1(x) ReadRegBits16(IO_P1588_SYNC_GEN,0x2,1)
#define IO_P1588_SYNC_GEN_BRPHY_SYNC_IN1_MASK                      0x0002
#define IO_P1588_SYNC_GEN_BRPHY_SYNC_IN1_ALIGN                     0
#define IO_P1588_SYNC_GEN_BRPHY_SYNC_IN1_BITS                      1
#define IO_P1588_SYNC_GEN_BRPHY_SYNC_IN1_SHIFT                     1

/* IO :: P1588_SYNC_GEN :: brphy_sync_in0 [00:00] */
#define Wr_IO_P1588_SYNC_GEN_brphy_sync_in0(x) WriteRegBits16(IO_P1588_SYNC_GEN,0x1,0,x)
#define Rd_IO_P1588_SYNC_GEN_brphy_sync_in0(x) ReadRegBits16(IO_P1588_SYNC_GEN,0x1,0)
#define IO_P1588_SYNC_GEN_BRPHY_SYNC_IN0_MASK                      0x0001
#define IO_P1588_SYNC_GEN_BRPHY_SYNC_IN0_ALIGN                     0
#define IO_P1588_SYNC_GEN_BRPHY_SYNC_IN0_BITS                      1
#define IO_P1588_SYNC_GEN_BRPHY_SYNC_IN0_SHIFT                     0


/****************************************************************************
 * IO :: IOFF
 ***************************************************************************/
/* IO :: IOFF :: IOFF [15:00] */
#define Wr_IO_IOFF_IOFF(x) WriteReg16(IO_IOFF,x)
#define Rd_IO_IOFF_IOFF(x) ReadReg16(IO_IOFF)
#define IO_IOFF_IOFF_MASK                                          0xffff
#define IO_IOFF_IOFF_ALIGN                                         0
#define IO_IOFF_IOFF_BITS                                          16
#define IO_IOFF_IOFF_SHIFT                                         0


/****************************************************************************
 * bcm89530_top_bridge_TOP_1588
 ***************************************************************************/
/****************************************************************************
 * TOP_1588 :: SLICE_ENABLE
 ***************************************************************************/
/* TOP_1588 :: SLICE_ENABLE :: RX_SLICE_1588_EN [15:08] */
#define Wr_TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN(x) WriteRegBits16(TOP_1588_SLICE_ENABLE,0xff00,8,x)
#define Rd_TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN(x) ReadRegBits16(TOP_1588_SLICE_ENABLE,0xff00,8)
#define TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN_MASK                0xff00
#define TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN_ALIGN               0
#define TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN_BITS                8
#define TOP_1588_SLICE_ENABLE_RX_SLICE_1588_EN_SHIFT               8

/* TOP_1588 :: SLICE_ENABLE :: TX_SLICE_1588_EN [07:00] */
#define Wr_TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN(x) WriteRegBits16(TOP_1588_SLICE_ENABLE,0xff,0,x)
#define Rd_TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN(x) ReadRegBits16(TOP_1588_SLICE_ENABLE,0xff,0)
#define TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN_MASK                0x00ff
#define TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN_ALIGN               0
#define TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN_BITS                8
#define TOP_1588_SLICE_ENABLE_TX_SLICE_1588_EN_SHIFT               0


/****************************************************************************
 * TOP_1588 :: TX_MODE_PORT_0
 ***************************************************************************/
/* TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE2 [15:08] */
#define Wr_TOP_1588_TX_MODE_PORT_0_TX_MODE2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_0,0xff00,8,x)
#define Rd_TOP_1588_TX_MODE_PORT_0_TX_MODE2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_0,0xff00,8)
#define TOP_1588_TX_MODE_PORT_0_TX_MODE2_MASK                      0xff00
#define TOP_1588_TX_MODE_PORT_0_TX_MODE2_ALIGN                     0
#define TOP_1588_TX_MODE_PORT_0_TX_MODE2_BITS                      8
#define TOP_1588_TX_MODE_PORT_0_TX_MODE2_SHIFT                     8

/* TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_0,0xc0,6,x)
#define Rd_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_0,0xc0,6)
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3_BITS                   2
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_0,0x30,4,x)
#define Rd_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_0,0x30,4)
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2_MASK                   0x0030
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2_BITS                   2
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_0,0xc,2,x)
#define Rd_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_0,0xc,2)
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1_MASK                   0x000c
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1_BITS                   2
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: TX_MODE_PORT_0 :: TX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_0,0x3,0,x)
#define Rd_TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_0,0x3,0)
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0_MASK                   0x0003
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0_BITS                   2
#define TOP_1588_TX_MODE_PORT_0_TX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: TX_MODE_PORT_1
 ***************************************************************************/
/* TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE2 [15:08] */
#define Wr_TOP_1588_TX_MODE_PORT_1_TX_MODE2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_1,0xff00,8,x)
#define Rd_TOP_1588_TX_MODE_PORT_1_TX_MODE2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_1,0xff00,8)
#define TOP_1588_TX_MODE_PORT_1_TX_MODE2_MASK                      0xff00
#define TOP_1588_TX_MODE_PORT_1_TX_MODE2_ALIGN                     0
#define TOP_1588_TX_MODE_PORT_1_TX_MODE2_BITS                      8
#define TOP_1588_TX_MODE_PORT_1_TX_MODE2_SHIFT                     8

/* TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_1,0xc0,6,x)
#define Rd_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_1,0xc0,6)
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3_BITS                   2
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_1,0x30,4,x)
#define Rd_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_1,0x30,4)
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2_MASK                   0x0030
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2_BITS                   2
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_1,0xc,2,x)
#define Rd_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_1,0xc,2)
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1_MASK                   0x000c
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1_BITS                   2
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: TX_MODE_PORT_1 :: TX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_1,0x3,0,x)
#define Rd_TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_1,0x3,0)
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0_MASK                   0x0003
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0_BITS                   2
#define TOP_1588_TX_MODE_PORT_1_TX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: TX_MODE_PORT_2
 ***************************************************************************/
/* TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE2 [15:08] */
#define Wr_TOP_1588_TX_MODE_PORT_2_TX_MODE2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_2,0xff00,8,x)
#define Rd_TOP_1588_TX_MODE_PORT_2_TX_MODE2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_2,0xff00,8)
#define TOP_1588_TX_MODE_PORT_2_TX_MODE2_MASK                      0xff00
#define TOP_1588_TX_MODE_PORT_2_TX_MODE2_ALIGN                     0
#define TOP_1588_TX_MODE_PORT_2_TX_MODE2_BITS                      8
#define TOP_1588_TX_MODE_PORT_2_TX_MODE2_SHIFT                     8

/* TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_2,0xc0,6,x)
#define Rd_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_2,0xc0,6)
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3_BITS                   2
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_2,0x30,4,x)
#define Rd_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_2,0x30,4)
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2_MASK                   0x0030
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2_BITS                   2
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_2,0xc,2,x)
#define Rd_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_2,0xc,2)
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1_MASK                   0x000c
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1_BITS                   2
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: TX_MODE_PORT_2 :: TX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_2,0x3,0,x)
#define Rd_TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_2,0x3,0)
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0_MASK                   0x0003
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0_BITS                   2
#define TOP_1588_TX_MODE_PORT_2_TX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: TX_MODE_PORT_3
 ***************************************************************************/
/* TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE2 [15:08] */
#define Wr_TOP_1588_TX_MODE_PORT_3_TX_MODE2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_3,0xff00,8,x)
#define Rd_TOP_1588_TX_MODE_PORT_3_TX_MODE2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_3,0xff00,8)
#define TOP_1588_TX_MODE_PORT_3_TX_MODE2_MASK                      0xff00
#define TOP_1588_TX_MODE_PORT_3_TX_MODE2_ALIGN                     0
#define TOP_1588_TX_MODE_PORT_3_TX_MODE2_BITS                      8
#define TOP_1588_TX_MODE_PORT_3_TX_MODE2_SHIFT                     8

/* TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_3,0xc0,6,x)
#define Rd_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_3,0xc0,6)
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3_BITS                   2
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_3,0x30,4,x)
#define Rd_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_3,0x30,4)
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2_MASK                   0x0030
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2_BITS                   2
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_3,0xc,2,x)
#define Rd_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_3,0xc,2)
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1_MASK                   0x000c
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1_BITS                   2
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: TX_MODE_PORT_3 :: TX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_3,0x3,0,x)
#define Rd_TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_3,0x3,0)
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0_MASK                   0x0003
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0_BITS                   2
#define TOP_1588_TX_MODE_PORT_3_TX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: TX_MODE_PORT_4
 ***************************************************************************/
/* TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE2 [15:08] */
#define Wr_TOP_1588_TX_MODE_PORT_4_TX_MODE2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_4,0xff00,8,x)
#define Rd_TOP_1588_TX_MODE_PORT_4_TX_MODE2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_4,0xff00,8)
#define TOP_1588_TX_MODE_PORT_4_TX_MODE2_MASK                      0xff00
#define TOP_1588_TX_MODE_PORT_4_TX_MODE2_ALIGN                     0
#define TOP_1588_TX_MODE_PORT_4_TX_MODE2_BITS                      8
#define TOP_1588_TX_MODE_PORT_4_TX_MODE2_SHIFT                     8

/* TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_4,0xc0,6,x)
#define Rd_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_4,0xc0,6)
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3_BITS                   2
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_4,0x30,4,x)
#define Rd_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_4,0x30,4)
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2_MASK                   0x0030
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2_BITS                   2
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_4,0xc,2,x)
#define Rd_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_4,0xc,2)
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1_MASK                   0x000c
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1_BITS                   2
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: TX_MODE_PORT_4 :: TX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_4,0x3,0,x)
#define Rd_TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_4,0x3,0)
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0_MASK                   0x0003
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0_BITS                   2
#define TOP_1588_TX_MODE_PORT_4_TX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: TX_MODE_PORT_5
 ***************************************************************************/
/* TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE2 [15:08] */
#define Wr_TOP_1588_TX_MODE_PORT_5_TX_MODE2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_5,0xff00,8,x)
#define Rd_TOP_1588_TX_MODE_PORT_5_TX_MODE2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_5,0xff00,8)
#define TOP_1588_TX_MODE_PORT_5_TX_MODE2_MASK                      0xff00
#define TOP_1588_TX_MODE_PORT_5_TX_MODE2_ALIGN                     0
#define TOP_1588_TX_MODE_PORT_5_TX_MODE2_BITS                      8
#define TOP_1588_TX_MODE_PORT_5_TX_MODE2_SHIFT                     8

/* TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_5,0xc0,6,x)
#define Rd_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_5,0xc0,6)
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3_BITS                   2
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_5,0x30,4,x)
#define Rd_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_5,0x30,4)
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2_MASK                   0x0030
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2_BITS                   2
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_5,0xc,2,x)
#define Rd_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_5,0xc,2)
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1_MASK                   0x000c
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1_BITS                   2
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: TX_MODE_PORT_5 :: TX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_5,0x3,0,x)
#define Rd_TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_5,0x3,0)
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0_MASK                   0x0003
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0_BITS                   2
#define TOP_1588_TX_MODE_PORT_5_TX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: TX_MODE_PORT_6
 ***************************************************************************/
/* TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE2 [15:08] */
#define Wr_TOP_1588_TX_MODE_PORT_6_TX_MODE2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_6,0xff00,8,x)
#define Rd_TOP_1588_TX_MODE_PORT_6_TX_MODE2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_6,0xff00,8)
#define TOP_1588_TX_MODE_PORT_6_TX_MODE2_MASK                      0xff00
#define TOP_1588_TX_MODE_PORT_6_TX_MODE2_ALIGN                     0
#define TOP_1588_TX_MODE_PORT_6_TX_MODE2_BITS                      8
#define TOP_1588_TX_MODE_PORT_6_TX_MODE2_SHIFT                     8

/* TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_6,0xc0,6,x)
#define Rd_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_6,0xc0,6)
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3_BITS                   2
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_6,0x30,4,x)
#define Rd_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_6,0x30,4)
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2_MASK                   0x0030
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2_BITS                   2
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_6,0xc,2,x)
#define Rd_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_6,0xc,2)
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1_MASK                   0x000c
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1_BITS                   2
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: TX_MODE_PORT_6 :: TX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_6,0x3,0,x)
#define Rd_TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_6,0x3,0)
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0_MASK                   0x0003
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0_BITS                   2
#define TOP_1588_TX_MODE_PORT_6_TX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: TX_MODE_PORT_7
 ***************************************************************************/
/* TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE2 [15:08] */
#define Wr_TOP_1588_TX_MODE_PORT_7_TX_MODE2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_7,0xff00,8,x)
#define Rd_TOP_1588_TX_MODE_PORT_7_TX_MODE2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_7,0xff00,8)
#define TOP_1588_TX_MODE_PORT_7_TX_MODE2_MASK                      0xff00
#define TOP_1588_TX_MODE_PORT_7_TX_MODE2_ALIGN                     0
#define TOP_1588_TX_MODE_PORT_7_TX_MODE2_BITS                      8
#define TOP_1588_TX_MODE_PORT_7_TX_MODE2_SHIFT                     8

/* TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_7,0xc0,6,x)
#define Rd_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_7,0xc0,6)
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3_BITS                   2
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_7,0x30,4,x)
#define Rd_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_7,0x30,4)
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2_MASK                   0x0030
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2_BITS                   2
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_7,0xc,2,x)
#define Rd_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_7,0xc,2)
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1_MASK                   0x000c
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1_BITS                   2
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: TX_MODE_PORT_7 :: TX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0(x) WriteRegBits16(TOP_1588_TX_MODE_PORT_7,0x3,0,x)
#define Rd_TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0(x) ReadRegBits16(TOP_1588_TX_MODE_PORT_7,0x3,0)
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0_MASK                   0x0003
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0_ALIGN                  0
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0_BITS                   2
#define TOP_1588_TX_MODE_PORT_7_TX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: RX_MODE_PORT_0
 ***************************************************************************/
/* TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE2 [15:08] */
#define Wr_TOP_1588_RX_MODE_PORT_0_RX_MODE2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_0,0xff00,8,x)
#define Rd_TOP_1588_RX_MODE_PORT_0_RX_MODE2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_0,0xff00,8)
#define TOP_1588_RX_MODE_PORT_0_RX_MODE2_MASK                      0xff00
#define TOP_1588_RX_MODE_PORT_0_RX_MODE2_ALIGN                     0
#define TOP_1588_RX_MODE_PORT_0_RX_MODE2_BITS                      8
#define TOP_1588_RX_MODE_PORT_0_RX_MODE2_SHIFT                     8

/* TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_0,0xc0,6,x)
#define Rd_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_0,0xc0,6)
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3_BITS                   2
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_0,0x30,4,x)
#define Rd_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_0,0x30,4)
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2_MASK                   0x0030
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2_BITS                   2
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_0,0xc,2,x)
#define Rd_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_0,0xc,2)
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1_MASK                   0x000c
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1_BITS                   2
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: RX_MODE_PORT_0 :: RX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_0,0x3,0,x)
#define Rd_TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_0,0x3,0)
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0_MASK                   0x0003
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0_BITS                   2
#define TOP_1588_RX_MODE_PORT_0_RX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: RX_MODE_PORT_1
 ***************************************************************************/
/* TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE2 [15:08] */
#define Wr_TOP_1588_RX_MODE_PORT_1_RX_MODE2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_1,0xff00,8,x)
#define Rd_TOP_1588_RX_MODE_PORT_1_RX_MODE2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_1,0xff00,8)
#define TOP_1588_RX_MODE_PORT_1_RX_MODE2_MASK                      0xff00
#define TOP_1588_RX_MODE_PORT_1_RX_MODE2_ALIGN                     0
#define TOP_1588_RX_MODE_PORT_1_RX_MODE2_BITS                      8
#define TOP_1588_RX_MODE_PORT_1_RX_MODE2_SHIFT                     8

/* TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_1,0xc0,6,x)
#define Rd_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_1,0xc0,6)
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3_BITS                   2
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_1,0x30,4,x)
#define Rd_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_1,0x30,4)
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2_MASK                   0x0030
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2_BITS                   2
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_1,0xc,2,x)
#define Rd_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_1,0xc,2)
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1_MASK                   0x000c
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1_BITS                   2
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: RX_MODE_PORT_1 :: RX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_1,0x3,0,x)
#define Rd_TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_1,0x3,0)
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0_MASK                   0x0003
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0_BITS                   2
#define TOP_1588_RX_MODE_PORT_1_RX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: RX_MODE_PORT_2
 ***************************************************************************/
/* TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE2 [15:08] */
#define Wr_TOP_1588_RX_MODE_PORT_2_RX_MODE2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_2,0xff00,8,x)
#define Rd_TOP_1588_RX_MODE_PORT_2_RX_MODE2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_2,0xff00,8)
#define TOP_1588_RX_MODE_PORT_2_RX_MODE2_MASK                      0xff00
#define TOP_1588_RX_MODE_PORT_2_RX_MODE2_ALIGN                     0
#define TOP_1588_RX_MODE_PORT_2_RX_MODE2_BITS                      8
#define TOP_1588_RX_MODE_PORT_2_RX_MODE2_SHIFT                     8

/* TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_2,0xc0,6,x)
#define Rd_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_2,0xc0,6)
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3_BITS                   2
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_2,0x30,4,x)
#define Rd_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_2,0x30,4)
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2_MASK                   0x0030
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2_BITS                   2
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_2,0xc,2,x)
#define Rd_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_2,0xc,2)
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1_MASK                   0x000c
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1_BITS                   2
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: RX_MODE_PORT_2 :: RX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_2,0x3,0,x)
#define Rd_TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_2,0x3,0)
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0_MASK                   0x0003
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0_BITS                   2
#define TOP_1588_RX_MODE_PORT_2_RX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: RX_MODE_PORT_3
 ***************************************************************************/
/* TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE2 [15:08] */
#define Wr_TOP_1588_RX_MODE_PORT_3_RX_MODE2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_3,0xff00,8,x)
#define Rd_TOP_1588_RX_MODE_PORT_3_RX_MODE2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_3,0xff00,8)
#define TOP_1588_RX_MODE_PORT_3_RX_MODE2_MASK                      0xff00
#define TOP_1588_RX_MODE_PORT_3_RX_MODE2_ALIGN                     0
#define TOP_1588_RX_MODE_PORT_3_RX_MODE2_BITS                      8
#define TOP_1588_RX_MODE_PORT_3_RX_MODE2_SHIFT                     8

/* TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_3,0xc0,6,x)
#define Rd_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_3,0xc0,6)
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3_BITS                   2
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_3,0x30,4,x)
#define Rd_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_3,0x30,4)
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2_MASK                   0x0030
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2_BITS                   2
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_3,0xc,2,x)
#define Rd_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_3,0xc,2)
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1_MASK                   0x000c
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1_BITS                   2
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: RX_MODE_PORT_3 :: RX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_3,0x3,0,x)
#define Rd_TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_3,0x3,0)
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0_MASK                   0x0003
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0_BITS                   2
#define TOP_1588_RX_MODE_PORT_3_RX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: RX_MODE_PORT_4
 ***************************************************************************/
/* TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE2 [15:08] */
#define Wr_TOP_1588_RX_MODE_PORT_4_RX_MODE2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_4,0xff00,8,x)
#define Rd_TOP_1588_RX_MODE_PORT_4_RX_MODE2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_4,0xff00,8)
#define TOP_1588_RX_MODE_PORT_4_RX_MODE2_MASK                      0xff00
#define TOP_1588_RX_MODE_PORT_4_RX_MODE2_ALIGN                     0
#define TOP_1588_RX_MODE_PORT_4_RX_MODE2_BITS                      8
#define TOP_1588_RX_MODE_PORT_4_RX_MODE2_SHIFT                     8

/* TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_4,0xc0,6,x)
#define Rd_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_4,0xc0,6)
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3_BITS                   2
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_4,0x30,4,x)
#define Rd_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_4,0x30,4)
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2_MASK                   0x0030
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2_BITS                   2
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_4,0xc,2,x)
#define Rd_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_4,0xc,2)
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1_MASK                   0x000c
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1_BITS                   2
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: RX_MODE_PORT_4 :: RX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_4,0x3,0,x)
#define Rd_TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_4,0x3,0)
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0_MASK                   0x0003
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0_BITS                   2
#define TOP_1588_RX_MODE_PORT_4_RX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: RX_MODE_PORT_5
 ***************************************************************************/
/* TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE2 [15:08] */
#define Wr_TOP_1588_RX_MODE_PORT_5_RX_MODE2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_5,0xff00,8,x)
#define Rd_TOP_1588_RX_MODE_PORT_5_RX_MODE2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_5,0xff00,8)
#define TOP_1588_RX_MODE_PORT_5_RX_MODE2_MASK                      0xff00
#define TOP_1588_RX_MODE_PORT_5_RX_MODE2_ALIGN                     0
#define TOP_1588_RX_MODE_PORT_5_RX_MODE2_BITS                      8
#define TOP_1588_RX_MODE_PORT_5_RX_MODE2_SHIFT                     8

/* TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_5,0xc0,6,x)
#define Rd_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_5,0xc0,6)
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3_BITS                   2
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_5,0x30,4,x)
#define Rd_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_5,0x30,4)
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2_MASK                   0x0030
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2_BITS                   2
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_5,0xc,2,x)
#define Rd_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_5,0xc,2)
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1_MASK                   0x000c
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1_BITS                   2
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: RX_MODE_PORT_5 :: RX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_5,0x3,0,x)
#define Rd_TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_5,0x3,0)
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0_MASK                   0x0003
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0_BITS                   2
#define TOP_1588_RX_MODE_PORT_5_RX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: RX_MODE_PORT_6
 ***************************************************************************/
/* TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE2 [15:08] */
#define Wr_TOP_1588_RX_MODE_PORT_6_RX_MODE2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_6,0xff00,8,x)
#define Rd_TOP_1588_RX_MODE_PORT_6_RX_MODE2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_6,0xff00,8)
#define TOP_1588_RX_MODE_PORT_6_RX_MODE2_MASK                      0xff00
#define TOP_1588_RX_MODE_PORT_6_RX_MODE2_ALIGN                     0
#define TOP_1588_RX_MODE_PORT_6_RX_MODE2_BITS                      8
#define TOP_1588_RX_MODE_PORT_6_RX_MODE2_SHIFT                     8

/* TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_6,0xc0,6,x)
#define Rd_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_6,0xc0,6)
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3_BITS                   2
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_6,0x30,4,x)
#define Rd_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_6,0x30,4)
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2_MASK                   0x0030
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2_BITS                   2
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_6,0xc,2,x)
#define Rd_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_6,0xc,2)
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1_MASK                   0x000c
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1_BITS                   2
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: RX_MODE_PORT_6 :: RX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_6,0x3,0,x)
#define Rd_TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_6,0x3,0)
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0_MASK                   0x0003
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0_BITS                   2
#define TOP_1588_RX_MODE_PORT_6_RX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: RX_MODE_PORT_7
 ***************************************************************************/
/* TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE2 [15:08] */
#define Wr_TOP_1588_RX_MODE_PORT_7_RX_MODE2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_7,0xff00,8,x)
#define Rd_TOP_1588_RX_MODE_PORT_7_RX_MODE2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_7,0xff00,8)
#define TOP_1588_RX_MODE_PORT_7_RX_MODE2_MASK                      0xff00
#define TOP_1588_RX_MODE_PORT_7_RX_MODE2_ALIGN                     0
#define TOP_1588_RX_MODE_PORT_7_RX_MODE2_BITS                      8
#define TOP_1588_RX_MODE_PORT_7_RX_MODE2_SHIFT                     8

/* TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE1_M3 [07:06] */
#define Wr_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_7,0xc0,6,x)
#define Rd_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_7,0xc0,6)
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3_MASK                   0x00c0
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3_BITS                   2
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M3_SHIFT                  6

/* TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE1_M2 [05:04] */
#define Wr_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_7,0x30,4,x)
#define Rd_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_7,0x30,4)
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2_MASK                   0x0030
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2_BITS                   2
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M2_SHIFT                  4

/* TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE1_M1 [03:02] */
#define Wr_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_7,0xc,2,x)
#define Rd_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_7,0xc,2)
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1_MASK                   0x000c
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1_BITS                   2
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M1_SHIFT                  2

/* TOP_1588 :: RX_MODE_PORT_7 :: RX_MODE1_M0 [01:00] */
#define Wr_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0(x) WriteRegBits16(TOP_1588_RX_MODE_PORT_7,0x3,0,x)
#define Rd_TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0(x) ReadRegBits16(TOP_1588_RX_MODE_PORT_7,0x3,0)
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0_MASK                   0x0003
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0_ALIGN                  0
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0_BITS                   2
#define TOP_1588_RX_MODE_PORT_7_RX_MODE1_M0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: TX_TS_CAP
 ***************************************************************************/
/* TOP_1588 :: TX_TS_CAP :: TX_CS_DIS [15:08] */
#define Wr_TOP_1588_TX_TS_CAP_TX_CS_DIS(x) WriteRegBits16(TOP_1588_TX_TS_CAP,0xff00,8,x)
#define Rd_TOP_1588_TX_TS_CAP_TX_CS_DIS(x) ReadRegBits16(TOP_1588_TX_TS_CAP,0xff00,8)
#define TOP_1588_TX_TS_CAP_TX_CS_DIS_MASK                          0xff00
#define TOP_1588_TX_TS_CAP_TX_CS_DIS_ALIGN                         0
#define TOP_1588_TX_TS_CAP_TX_CS_DIS_BITS                          8
#define TOP_1588_TX_TS_CAP_TX_CS_DIS_SHIFT                         8

/* TOP_1588 :: TX_TS_CAP :: TX_TS_CAP [07:00] */
#define Wr_TOP_1588_TX_TS_CAP_TX_TS_CAP(x) WriteRegBits16(TOP_1588_TX_TS_CAP,0xff,0,x)
#define Rd_TOP_1588_TX_TS_CAP_TX_TS_CAP(x) ReadRegBits16(TOP_1588_TX_TS_CAP,0xff,0)
#define TOP_1588_TX_TS_CAP_TX_TS_CAP_MASK                          0x00ff
#define TOP_1588_TX_TS_CAP_TX_TS_CAP_ALIGN                         0
#define TOP_1588_TX_TS_CAP_TX_TS_CAP_BITS                          8
#define TOP_1588_TX_TS_CAP_TX_TS_CAP_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: RX_TS_CAP
 ***************************************************************************/
/* TOP_1588 :: RX_TS_CAP :: RX_CS_DIS [15:08] */
#define Wr_TOP_1588_RX_TS_CAP_RX_CS_DIS(x) WriteRegBits16(TOP_1588_RX_TS_CAP,0xff00,8,x)
#define Rd_TOP_1588_RX_TS_CAP_RX_CS_DIS(x) ReadRegBits16(TOP_1588_RX_TS_CAP,0xff00,8)
#define TOP_1588_RX_TS_CAP_RX_CS_DIS_MASK                          0xff00
#define TOP_1588_RX_TS_CAP_RX_CS_DIS_ALIGN                         0
#define TOP_1588_RX_TS_CAP_RX_CS_DIS_BITS                          8
#define TOP_1588_RX_TS_CAP_RX_CS_DIS_SHIFT                         8

/* TOP_1588 :: RX_TS_CAP :: RX_TS_CAP [07:00] */
#define Wr_TOP_1588_RX_TS_CAP_RX_TS_CAP(x) WriteRegBits16(TOP_1588_RX_TS_CAP,0xff,0,x)
#define Rd_TOP_1588_RX_TS_CAP_RX_TS_CAP(x) ReadRegBits16(TOP_1588_RX_TS_CAP,0xff,0)
#define TOP_1588_RX_TS_CAP_RX_TS_CAP_MASK                          0x00ff
#define TOP_1588_RX_TS_CAP_RX_TS_CAP_ALIGN                         0
#define TOP_1588_RX_TS_CAP_RX_TS_CAP_BITS                          8
#define TOP_1588_RX_TS_CAP_RX_TS_CAP_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: RX_TX_OPTION
 ***************************************************************************/
/* TOP_1588 :: RX_TX_OPTION :: SPARE_REG1 [15:11] */
#define Wr_TOP_1588_RX_TX_OPTION_SPARE_REG1(x) WriteRegBits16(TOP_1588_RX_TX_OPTION,0xf800,11,x)
#define Rd_TOP_1588_RX_TX_OPTION_SPARE_REG1(x) ReadRegBits16(TOP_1588_RX_TX_OPTION,0xf800,11)
#define TOP_1588_RX_TX_OPTION_SPARE_REG1_MASK                      0xf800
#define TOP_1588_RX_TX_OPTION_SPARE_REG1_ALIGN                     0
#define TOP_1588_RX_TX_OPTION_SPARE_REG1_BITS                      5
#define TOP_1588_RX_TX_OPTION_SPARE_REG1_SHIFT                     11

/* TOP_1588 :: RX_TX_OPTION :: RX_PTP_VER_DIS [10:10] */
#define Wr_TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS(x) WriteRegBits16(TOP_1588_RX_TX_OPTION,0x400,10,x)
#define Rd_TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS(x) ReadRegBits16(TOP_1588_RX_TX_OPTION,0x400,10)
#define TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS_MASK                  0x0400
#define TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS_ALIGN                 0
#define TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS_BITS                  1
#define TOP_1588_RX_TX_OPTION_RX_PTP_VER_DIS_SHIFT                 10

/* TOP_1588 :: RX_TX_OPTION :: RX_TIMECODE_ADD_IN [09:09] */
#define Wr_TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN(x) WriteRegBits16(TOP_1588_RX_TX_OPTION,0x200,9,x)
#define Rd_TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN(x) ReadRegBits16(TOP_1588_RX_TX_OPTION,0x200,9)
#define TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN_MASK              0x0200
#define TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN_ALIGN             0
#define TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN_BITS              1
#define TOP_1588_RX_TX_OPTION_RX_TIMECODE_ADD_IN_SHIFT             9

/* TOP_1588 :: RX_TX_OPTION :: RX_CRC_KEEP [08:08] */
#define Wr_TOP_1588_RX_TX_OPTION_RX_CRC_KEEP(x) WriteRegBits16(TOP_1588_RX_TX_OPTION,0x100,8,x)
#define Rd_TOP_1588_RX_TX_OPTION_RX_CRC_KEEP(x) ReadRegBits16(TOP_1588_RX_TX_OPTION,0x100,8)
#define TOP_1588_RX_TX_OPTION_RX_CRC_KEEP_MASK                     0x0100
#define TOP_1588_RX_TX_OPTION_RX_CRC_KEEP_ALIGN                    0
#define TOP_1588_RX_TX_OPTION_RX_CRC_KEEP_BITS                     1
#define TOP_1588_RX_TX_OPTION_RX_CRC_KEEP_SHIFT                    8

/* TOP_1588 :: RX_TX_OPTION :: SPARE_REG0 [07:03] */
#define Wr_TOP_1588_RX_TX_OPTION_SPARE_REG0(x) WriteRegBits16(TOP_1588_RX_TX_OPTION,0xf8,3,x)
#define Rd_TOP_1588_RX_TX_OPTION_SPARE_REG0(x) ReadRegBits16(TOP_1588_RX_TX_OPTION,0xf8,3)
#define TOP_1588_RX_TX_OPTION_SPARE_REG0_MASK                      0x00f8
#define TOP_1588_RX_TX_OPTION_SPARE_REG0_ALIGN                     0
#define TOP_1588_RX_TX_OPTION_SPARE_REG0_BITS                      5
#define TOP_1588_RX_TX_OPTION_SPARE_REG0_SHIFT                     3

/* TOP_1588 :: RX_TX_OPTION :: TX_PTP_VER_DIS [02:02] */
#define Wr_TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS(x) WriteRegBits16(TOP_1588_RX_TX_OPTION,0x4,2,x)
#define Rd_TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS(x) ReadRegBits16(TOP_1588_RX_TX_OPTION,0x4,2)
#define TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS_MASK                  0x0004
#define TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS_ALIGN                 0
#define TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS_BITS                  1
#define TOP_1588_RX_TX_OPTION_TX_PTP_VER_DIS_SHIFT                 2

/* TOP_1588 :: RX_TX_OPTION :: TX_TIMECODE_ADD_IN [01:01] */
#define Wr_TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN(x) WriteRegBits16(TOP_1588_RX_TX_OPTION,0x2,1,x)
#define Rd_TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN(x) ReadRegBits16(TOP_1588_RX_TX_OPTION,0x2,1)
#define TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN_MASK              0x0002
#define TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN_ALIGN             0
#define TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN_BITS              1
#define TOP_1588_RX_TX_OPTION_TX_TIMECODE_ADD_IN_SHIFT             1

/* TOP_1588 :: RX_TX_OPTION :: TX_CRC_KEEP [00:00] */
#define Wr_TOP_1588_RX_TX_OPTION_TX_CRC_KEEP(x) WriteRegBits16(TOP_1588_RX_TX_OPTION,0x1,0,x)
#define Rd_TOP_1588_RX_TX_OPTION_TX_CRC_KEEP(x) ReadRegBits16(TOP_1588_RX_TX_OPTION,0x1,0)
#define TOP_1588_RX_TX_OPTION_TX_CRC_KEEP_MASK                     0x0001
#define TOP_1588_RX_TX_OPTION_TX_CRC_KEEP_ALIGN                    0
#define TOP_1588_RX_TX_OPTION_TX_CRC_KEEP_BITS                     1
#define TOP_1588_RX_TX_OPTION_TX_CRC_KEEP_SHIFT                    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_0_LINK_DELAY_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_0_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(TOP_1588_RX_PORT_0_LINK_DELAY_LSB,x)
#define Rd_TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(TOP_1588_RX_PORT_0_LINK_DELAY_LSB)
#define TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK   0xffff
#define TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN  0
#define TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS   16
#define TOP_1588_RX_PORT_0_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_0_LINK_DELAY_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_0_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(TOP_1588_RX_PORT_0_LINK_DELAY_MSB,x)
#define Rd_TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(TOP_1588_RX_PORT_0_LINK_DELAY_MSB)
#define TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK   0xffff
#define TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN  0
#define TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS   16
#define TOP_1588_RX_PORT_0_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_1_LINK_DELAY_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_1_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(TOP_1588_RX_PORT_1_LINK_DELAY_LSB,x)
#define Rd_TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(TOP_1588_RX_PORT_1_LINK_DELAY_LSB)
#define TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK   0xffff
#define TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN  0
#define TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS   16
#define TOP_1588_RX_PORT_1_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_1_LINK_DELAY_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_1_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(TOP_1588_RX_PORT_1_LINK_DELAY_MSB,x)
#define Rd_TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(TOP_1588_RX_PORT_1_LINK_DELAY_MSB)
#define TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK   0xffff
#define TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN  0
#define TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS   16
#define TOP_1588_RX_PORT_1_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_2_LINK_DELAY_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_2_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(TOP_1588_RX_PORT_2_LINK_DELAY_LSB,x)
#define Rd_TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(TOP_1588_RX_PORT_2_LINK_DELAY_LSB)
#define TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK   0xffff
#define TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN  0
#define TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS   16
#define TOP_1588_RX_PORT_2_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_2_LINK_DELAY_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_2_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(TOP_1588_RX_PORT_2_LINK_DELAY_MSB,x)
#define Rd_TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(TOP_1588_RX_PORT_2_LINK_DELAY_MSB)
#define TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK   0xffff
#define TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN  0
#define TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS   16
#define TOP_1588_RX_PORT_2_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_3_LINK_DELAY_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_3_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(TOP_1588_RX_PORT_3_LINK_DELAY_LSB,x)
#define Rd_TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(TOP_1588_RX_PORT_3_LINK_DELAY_LSB)
#define TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK   0xffff
#define TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN  0
#define TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS   16
#define TOP_1588_RX_PORT_3_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_3_LINK_DELAY_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_3_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(TOP_1588_RX_PORT_3_LINK_DELAY_MSB,x)
#define Rd_TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(TOP_1588_RX_PORT_3_LINK_DELAY_MSB)
#define TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK   0xffff
#define TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN  0
#define TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS   16
#define TOP_1588_RX_PORT_3_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_4_LINK_DELAY_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_4_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(TOP_1588_RX_PORT_4_LINK_DELAY_LSB,x)
#define Rd_TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(TOP_1588_RX_PORT_4_LINK_DELAY_LSB)
#define TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK   0xffff
#define TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN  0
#define TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS   16
#define TOP_1588_RX_PORT_4_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_4_LINK_DELAY_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_4_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(TOP_1588_RX_PORT_4_LINK_DELAY_MSB,x)
#define Rd_TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(TOP_1588_RX_PORT_4_LINK_DELAY_MSB)
#define TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK   0xffff
#define TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN  0
#define TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS   16
#define TOP_1588_RX_PORT_4_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_5_LINK_DELAY_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_5_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(TOP_1588_RX_PORT_5_LINK_DELAY_LSB,x)
#define Rd_TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(TOP_1588_RX_PORT_5_LINK_DELAY_LSB)
#define TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK   0xffff
#define TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN  0
#define TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS   16
#define TOP_1588_RX_PORT_5_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_5_LINK_DELAY_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_5_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(TOP_1588_RX_PORT_5_LINK_DELAY_MSB,x)
#define Rd_TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(TOP_1588_RX_PORT_5_LINK_DELAY_MSB)
#define TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK   0xffff
#define TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN  0
#define TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS   16
#define TOP_1588_RX_PORT_5_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_6_LINK_DELAY_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_6_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(TOP_1588_RX_PORT_6_LINK_DELAY_LSB,x)
#define Rd_TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(TOP_1588_RX_PORT_6_LINK_DELAY_LSB)
#define TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK   0xffff
#define TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN  0
#define TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS   16
#define TOP_1588_RX_PORT_6_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_6_LINK_DELAY_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_6_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(TOP_1588_RX_PORT_6_LINK_DELAY_MSB,x)
#define Rd_TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(TOP_1588_RX_PORT_6_LINK_DELAY_MSB)
#define TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK   0xffff
#define TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN  0
#define TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS   16
#define TOP_1588_RX_PORT_6_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_7_LINK_DELAY_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_7_LINK_DELAY_LSB :: RX_LINK_DELAY_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) WriteReg16(TOP_1588_RX_PORT_7_LINK_DELAY_LSB,x)
#define Rd_TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB(x) ReadReg16(TOP_1588_RX_PORT_7_LINK_DELAY_LSB)
#define TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_MASK   0xffff
#define TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_ALIGN  0
#define TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_BITS   16
#define TOP_1588_RX_PORT_7_LINK_DELAY_LSB_RX_LINK_DELAY_LSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: RX_PORT_7_LINK_DELAY_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_7_LINK_DELAY_MSB :: RX_LINK_DELAY_MSB [15:00] */
#define Wr_TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) WriteReg16(TOP_1588_RX_PORT_7_LINK_DELAY_MSB,x)
#define Rd_TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB(x) ReadReg16(TOP_1588_RX_PORT_7_LINK_DELAY_MSB)
#define TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_MASK   0xffff
#define TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_ALIGN  0
#define TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_BITS   16
#define TOP_1588_RX_PORT_7_LINK_DELAY_MSB_RX_LINK_DELAY_MSB_SHIFT  0


/****************************************************************************
 * TOP_1588 :: TX_PORT_0_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_0_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(TOP_1588_TX_PORT_0_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(TOP_1588_TX_PORT_0_TS_OFFSET_LSB)
#define TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK     0xffff
#define TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN    0
#define TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS     16
#define TOP_1588_TX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_0_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_0_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: TX_PORT_0_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: TX_PORT_0_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(TOP_1588_TX_PORT_0_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK     0x000f
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN    0
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS     4
#define TOP_1588_TX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_1_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_1_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(TOP_1588_TX_PORT_1_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(TOP_1588_TX_PORT_1_TS_OFFSET_LSB)
#define TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK     0xffff
#define TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN    0
#define TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS     16
#define TOP_1588_TX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_1_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_1_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: TX_PORT_1_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: TX_PORT_1_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(TOP_1588_TX_PORT_1_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK     0x000f
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN    0
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS     4
#define TOP_1588_TX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_2_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_2_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(TOP_1588_TX_PORT_2_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(TOP_1588_TX_PORT_2_TS_OFFSET_LSB)
#define TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK     0xffff
#define TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN    0
#define TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS     16
#define TOP_1588_TX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_2_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_2_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: TX_PORT_2_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: TX_PORT_2_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(TOP_1588_TX_PORT_2_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK     0x000f
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN    0
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS     4
#define TOP_1588_TX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_3_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_3_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(TOP_1588_TX_PORT_3_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(TOP_1588_TX_PORT_3_TS_OFFSET_LSB)
#define TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK     0xffff
#define TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN    0
#define TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS     16
#define TOP_1588_TX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_3_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_3_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: TX_PORT_3_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: TX_PORT_3_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(TOP_1588_TX_PORT_3_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK     0x000f
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN    0
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS     4
#define TOP_1588_TX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_4_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_4_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(TOP_1588_TX_PORT_4_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(TOP_1588_TX_PORT_4_TS_OFFSET_LSB)
#define TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK     0xffff
#define TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN    0
#define TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS     16
#define TOP_1588_TX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_4_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_4_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: TX_PORT_4_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: TX_PORT_4_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(TOP_1588_TX_PORT_4_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK     0x000f
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN    0
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS     4
#define TOP_1588_TX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_5_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_5_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(TOP_1588_TX_PORT_5_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(TOP_1588_TX_PORT_5_TS_OFFSET_LSB)
#define TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK     0xffff
#define TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN    0
#define TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS     16
#define TOP_1588_TX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_5_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_5_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: TX_PORT_5_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: TX_PORT_5_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(TOP_1588_TX_PORT_5_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK     0x000f
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN    0
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS     4
#define TOP_1588_TX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_6_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_6_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(TOP_1588_TX_PORT_6_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(TOP_1588_TX_PORT_6_TS_OFFSET_LSB)
#define TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK     0xffff
#define TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN    0
#define TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS     16
#define TOP_1588_TX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_6_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_6_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: TX_PORT_6_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: TX_PORT_6_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(TOP_1588_TX_PORT_6_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK     0x000f
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN    0
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS     4
#define TOP_1588_TX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_7_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_7_TS_OFFSET_LSB :: TS_OFFSET_TX_LSB [15:00] */
#define Wr_TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) WriteReg16(TOP_1588_TX_PORT_7_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB(x) ReadReg16(TOP_1588_TX_PORT_7_TS_OFFSET_LSB)
#define TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_MASK     0xffff
#define TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_ALIGN    0
#define TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_BITS     16
#define TOP_1588_TX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_TX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TX_PORT_7_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: TX_PORT_7_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: TX_PORT_7_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: TX_PORT_7_TS_OFFSET_MSB :: TS_OFFSET_TX_MSB [03:00] */
#define Wr_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) WriteRegBits16(TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB(x) ReadRegBits16(TOP_1588_TX_PORT_7_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_MASK     0x000f
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_ALIGN    0
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_BITS     4
#define TOP_1588_TX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_TX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_0_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_0_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(TOP_1588_RX_PORT_0_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(TOP_1588_RX_PORT_0_TS_OFFSET_LSB)
#define TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK     0xffff
#define TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN    0
#define TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS     16
#define TOP_1588_RX_PORT_0_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_0_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_0_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: RX_PORT_0_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: RX_PORT_0_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(TOP_1588_RX_PORT_0_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK     0x000f
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN    0
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS     4
#define TOP_1588_RX_PORT_0_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_1_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_1_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(TOP_1588_RX_PORT_1_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(TOP_1588_RX_PORT_1_TS_OFFSET_LSB)
#define TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK     0xffff
#define TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN    0
#define TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS     16
#define TOP_1588_RX_PORT_1_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_1_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_1_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: RX_PORT_1_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: RX_PORT_1_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(TOP_1588_RX_PORT_1_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK     0x000f
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN    0
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS     4
#define TOP_1588_RX_PORT_1_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_2_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_2_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(TOP_1588_RX_PORT_2_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(TOP_1588_RX_PORT_2_TS_OFFSET_LSB)
#define TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK     0xffff
#define TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN    0
#define TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS     16
#define TOP_1588_RX_PORT_2_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_2_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_2_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: RX_PORT_2_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: RX_PORT_2_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(TOP_1588_RX_PORT_2_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK     0x000f
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN    0
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS     4
#define TOP_1588_RX_PORT_2_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_3_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_3_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(TOP_1588_RX_PORT_3_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(TOP_1588_RX_PORT_3_TS_OFFSET_LSB)
#define TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK     0xffff
#define TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN    0
#define TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS     16
#define TOP_1588_RX_PORT_3_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_3_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_3_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: RX_PORT_3_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: RX_PORT_3_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(TOP_1588_RX_PORT_3_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK     0x000f
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN    0
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS     4
#define TOP_1588_RX_PORT_3_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_4_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_4_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(TOP_1588_RX_PORT_4_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(TOP_1588_RX_PORT_4_TS_OFFSET_LSB)
#define TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK     0xffff
#define TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN    0
#define TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS     16
#define TOP_1588_RX_PORT_4_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_4_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_4_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: RX_PORT_4_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: RX_PORT_4_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(TOP_1588_RX_PORT_4_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK     0x000f
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN    0
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS     4
#define TOP_1588_RX_PORT_4_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_5_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_5_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(TOP_1588_RX_PORT_5_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(TOP_1588_RX_PORT_5_TS_OFFSET_LSB)
#define TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK     0xffff
#define TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN    0
#define TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS     16
#define TOP_1588_RX_PORT_5_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_5_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_5_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: RX_PORT_5_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: RX_PORT_5_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(TOP_1588_RX_PORT_5_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK     0x000f
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN    0
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS     4
#define TOP_1588_RX_PORT_5_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_6_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_6_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(TOP_1588_RX_PORT_6_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(TOP_1588_RX_PORT_6_TS_OFFSET_LSB)
#define TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK     0xffff
#define TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN    0
#define TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS     16
#define TOP_1588_RX_PORT_6_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_6_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_6_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: RX_PORT_6_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: RX_PORT_6_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(TOP_1588_RX_PORT_6_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK     0x000f
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN    0
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS     4
#define TOP_1588_RX_PORT_6_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_7_TS_OFFSET_LSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_7_TS_OFFSET_LSB :: TS_OFFSET_RX_LSB [15:00] */
#define Wr_TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) WriteReg16(TOP_1588_RX_PORT_7_TS_OFFSET_LSB,x)
#define Rd_TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB(x) ReadReg16(TOP_1588_RX_PORT_7_TS_OFFSET_LSB)
#define TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_MASK     0xffff
#define TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_ALIGN    0
#define TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_BITS     16
#define TOP_1588_RX_PORT_7_TS_OFFSET_LSB_TS_OFFSET_RX_LSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: RX_PORT_7_TS_OFFSET_MSB
 ***************************************************************************/
/* TOP_1588 :: RX_PORT_7_TS_OFFSET_MSB :: TS_CAP [15:08] */
#define Wr_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP(x) WriteRegBits16(TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xff00,8,x)
#define Rd_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP(x) ReadRegBits16(TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xff00,8)
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP_MASK               0xff00
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP_ALIGN              0
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP_BITS               8
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_CAP_SHIFT              8

/* TOP_1588 :: RX_PORT_7_TS_OFFSET_MSB :: TS_LD [07:04] */
#define Wr_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD(x) WriteRegBits16(TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xf0,4,x)
#define Rd_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD(x) ReadRegBits16(TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xf0,4)
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD_MASK                0x00f0
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD_ALIGN               0
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD_BITS                4
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_LD_SHIFT               4

/* TOP_1588 :: RX_PORT_7_TS_OFFSET_MSB :: TS_OFFSET_RX_MSB [03:00] */
#define Wr_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) WriteRegBits16(TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xf,0,x)
#define Rd_TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB(x) ReadRegBits16(TOP_1588_RX_PORT_7_TS_OFFSET_MSB,0xf,0)
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_MASK     0x000f
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_ALIGN    0
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_BITS     4
#define TOP_1588_RX_PORT_7_TS_OFFSET_MSB_TS_OFFSET_RX_MSB_SHIFT    0


/****************************************************************************
 * TOP_1588 :: TIME_CODE_0
 ***************************************************************************/
/* TOP_1588 :: TIME_CODE_0 :: TIME_CODE_0 [15:00] */
#define Wr_TOP_1588_TIME_CODE_0_TIME_CODE_0(x) WriteReg16(TOP_1588_TIME_CODE_0,x)
#define Rd_TOP_1588_TIME_CODE_0_TIME_CODE_0(x) ReadReg16(TOP_1588_TIME_CODE_0)
#define TOP_1588_TIME_CODE_0_TIME_CODE_0_MASK                      0xffff
#define TOP_1588_TIME_CODE_0_TIME_CODE_0_ALIGN                     0
#define TOP_1588_TIME_CODE_0_TIME_CODE_0_BITS                      16
#define TOP_1588_TIME_CODE_0_TIME_CODE_0_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: TIME_CODE_1
 ***************************************************************************/
/* TOP_1588 :: TIME_CODE_1 :: TIME_CODE_1 [15:00] */
#define Wr_TOP_1588_TIME_CODE_1_TIME_CODE_1(x) WriteReg16(TOP_1588_TIME_CODE_1,x)
#define Rd_TOP_1588_TIME_CODE_1_TIME_CODE_1(x) ReadReg16(TOP_1588_TIME_CODE_1)
#define TOP_1588_TIME_CODE_1_TIME_CODE_1_MASK                      0xffff
#define TOP_1588_TIME_CODE_1_TIME_CODE_1_ALIGN                     0
#define TOP_1588_TIME_CODE_1_TIME_CODE_1_BITS                      16
#define TOP_1588_TIME_CODE_1_TIME_CODE_1_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: TIME_CODE_2
 ***************************************************************************/
/* TOP_1588 :: TIME_CODE_2 :: TIME_CODE_2 [15:00] */
#define Wr_TOP_1588_TIME_CODE_2_TIME_CODE_2(x) WriteReg16(TOP_1588_TIME_CODE_2,x)
#define Rd_TOP_1588_TIME_CODE_2_TIME_CODE_2(x) ReadReg16(TOP_1588_TIME_CODE_2)
#define TOP_1588_TIME_CODE_2_TIME_CODE_2_MASK                      0xffff
#define TOP_1588_TIME_CODE_2_TIME_CODE_2_ALIGN                     0
#define TOP_1588_TIME_CODE_2_TIME_CODE_2_BITS                      16
#define TOP_1588_TIME_CODE_2_TIME_CODE_2_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: TIME_CODE_3
 ***************************************************************************/
/* TOP_1588 :: TIME_CODE_3 :: TIME_CODE_3 [15:00] */
#define Wr_TOP_1588_TIME_CODE_3_TIME_CODE_3(x) WriteReg16(TOP_1588_TIME_CODE_3,x)
#define Rd_TOP_1588_TIME_CODE_3_TIME_CODE_3(x) ReadReg16(TOP_1588_TIME_CODE_3)
#define TOP_1588_TIME_CODE_3_TIME_CODE_3_MASK                      0xffff
#define TOP_1588_TIME_CODE_3_TIME_CODE_3_ALIGN                     0
#define TOP_1588_TIME_CODE_3_TIME_CODE_3_BITS                      16
#define TOP_1588_TIME_CODE_3_TIME_CODE_3_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: TIME_CODE_4
 ***************************************************************************/
/* TOP_1588 :: TIME_CODE_4 :: TIME_CODE_4 [15:00] */
#define Wr_TOP_1588_TIME_CODE_4_TIME_CODE_4(x) WriteReg16(TOP_1588_TIME_CODE_4,x)
#define Rd_TOP_1588_TIME_CODE_4_TIME_CODE_4(x) ReadReg16(TOP_1588_TIME_CODE_4)
#define TOP_1588_TIME_CODE_4_TIME_CODE_4_MASK                      0xffff
#define TOP_1588_TIME_CODE_4_TIME_CODE_4_ALIGN                     0
#define TOP_1588_TIME_CODE_4_TIME_CODE_4_BITS                      16
#define TOP_1588_TIME_CODE_4_TIME_CODE_4_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DPLL_DB_LSB
 ***************************************************************************/
/* TOP_1588 :: DPLL_DB_LSB :: DPLL_DB_LSB [15:00] */
#define Wr_TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB(x) WriteReg16(TOP_1588_DPLL_DB_LSB,x)
#define Rd_TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB(x) ReadReg16(TOP_1588_DPLL_DB_LSB)
#define TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB_MASK                      0xffff
#define TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB_ALIGN                     0
#define TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB_BITS                      16
#define TOP_1588_DPLL_DB_LSB_DPLL_DB_LSB_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DPLL_DB_MSB
 ***************************************************************************/
/* TOP_1588 :: DPLL_DB_MSB :: DPLL_DB_MSB [15:00] */
#define Wr_TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB(x) WriteReg16(TOP_1588_DPLL_DB_MSB,x)
#define Rd_TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB(x) ReadReg16(TOP_1588_DPLL_DB_MSB)
#define TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB_MASK                      0xffff
#define TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB_ALIGN                     0
#define TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB_BITS                      16
#define TOP_1588_DPLL_DB_MSB_DPLL_DB_MSB_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DPLL_DB_SEL
 ***************************************************************************/
/* TOP_1588 :: DPLL_DB_SEL :: SPARE_REG [15:01] */
#define Wr_TOP_1588_DPLL_DB_SEL_SPARE_REG(x) WriteRegBits16(TOP_1588_DPLL_DB_SEL,0xfffe,1,x)
#define Rd_TOP_1588_DPLL_DB_SEL_SPARE_REG(x) ReadRegBits16(TOP_1588_DPLL_DB_SEL,0xfffe,1)
#define TOP_1588_DPLL_DB_SEL_SPARE_REG_MASK                        0xfffe
#define TOP_1588_DPLL_DB_SEL_SPARE_REG_ALIGN                       0
#define TOP_1588_DPLL_DB_SEL_SPARE_REG_BITS                        15
#define TOP_1588_DPLL_DB_SEL_SPARE_REG_SHIFT                       1

/* TOP_1588 :: DPLL_DB_SEL :: DPLL_DB_SEL [00:00] */
#define Wr_TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL(x) WriteRegBits16(TOP_1588_DPLL_DB_SEL,0x1,0,x)
#define Rd_TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL(x) ReadRegBits16(TOP_1588_DPLL_DB_SEL,0x1,0)
#define TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL_MASK                      0x0001
#define TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL_ALIGN                     0
#define TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL_BITS                      1
#define TOP_1588_DPLL_DB_SEL_DPLL_DB_SEL_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: SHD_CTL
 ***************************************************************************/
/* TOP_1588 :: SHD_CTL :: F16_C [15:15] */
#define Wr_TOP_1588_SHD_CTL_F16_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x8000,15,x)
#define Rd_TOP_1588_SHD_CTL_F16_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x8000,15)
#define TOP_1588_SHD_CTL_F16_C_MASK                                0x8000
#define TOP_1588_SHD_CTL_F16_C_ALIGN                               0
#define TOP_1588_SHD_CTL_F16_C_BITS                                1
#define TOP_1588_SHD_CTL_F16_C_SHIFT                               15

/* TOP_1588 :: SHD_CTL :: F15_C [14:14] */
#define Wr_TOP_1588_SHD_CTL_F15_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x4000,14,x)
#define Rd_TOP_1588_SHD_CTL_F15_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x4000,14)
#define TOP_1588_SHD_CTL_F15_C_MASK                                0x4000
#define TOP_1588_SHD_CTL_F15_C_ALIGN                               0
#define TOP_1588_SHD_CTL_F15_C_BITS                                1
#define TOP_1588_SHD_CTL_F15_C_SHIFT                               14

/* TOP_1588 :: SHD_CTL :: F14_C [13:13] */
#define Wr_TOP_1588_SHD_CTL_F14_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x2000,13,x)
#define Rd_TOP_1588_SHD_CTL_F14_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x2000,13)
#define TOP_1588_SHD_CTL_F14_C_MASK                                0x2000
#define TOP_1588_SHD_CTL_F14_C_ALIGN                               0
#define TOP_1588_SHD_CTL_F14_C_BITS                                1
#define TOP_1588_SHD_CTL_F14_C_SHIFT                               13

/* TOP_1588 :: SHD_CTL :: F13_C [12:12] */
#define Wr_TOP_1588_SHD_CTL_F13_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x1000,12,x)
#define Rd_TOP_1588_SHD_CTL_F13_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x1000,12)
#define TOP_1588_SHD_CTL_F13_C_MASK                                0x1000
#define TOP_1588_SHD_CTL_F13_C_ALIGN                               0
#define TOP_1588_SHD_CTL_F13_C_BITS                                1
#define TOP_1588_SHD_CTL_F13_C_SHIFT                               12

/* TOP_1588 :: SHD_CTL :: F12_C [11:11] */
#define Wr_TOP_1588_SHD_CTL_F12_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x800,11,x)
#define Rd_TOP_1588_SHD_CTL_F12_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x800,11)
#define TOP_1588_SHD_CTL_F12_C_MASK                                0x0800
#define TOP_1588_SHD_CTL_F12_C_ALIGN                               0
#define TOP_1588_SHD_CTL_F12_C_BITS                                1
#define TOP_1588_SHD_CTL_F12_C_SHIFT                               11

/* TOP_1588 :: SHD_CTL :: F11_C [10:10] */
#define Wr_TOP_1588_SHD_CTL_F11_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x400,10,x)
#define Rd_TOP_1588_SHD_CTL_F11_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x400,10)
#define TOP_1588_SHD_CTL_F11_C_MASK                                0x0400
#define TOP_1588_SHD_CTL_F11_C_ALIGN                               0
#define TOP_1588_SHD_CTL_F11_C_BITS                                1
#define TOP_1588_SHD_CTL_F11_C_SHIFT                               10

/* TOP_1588 :: SHD_CTL :: F10_C [09:09] */
#define Wr_TOP_1588_SHD_CTL_F10_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x200,9,x)
#define Rd_TOP_1588_SHD_CTL_F10_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x200,9)
#define TOP_1588_SHD_CTL_F10_C_MASK                                0x0200
#define TOP_1588_SHD_CTL_F10_C_ALIGN                               0
#define TOP_1588_SHD_CTL_F10_C_BITS                                1
#define TOP_1588_SHD_CTL_F10_C_SHIFT                               9

/* TOP_1588 :: SHD_CTL :: F9_C [08:08] */
#define Wr_TOP_1588_SHD_CTL_F9_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x100,8,x)
#define Rd_TOP_1588_SHD_CTL_F9_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x100,8)
#define TOP_1588_SHD_CTL_F9_C_MASK                                 0x0100
#define TOP_1588_SHD_CTL_F9_C_ALIGN                                0
#define TOP_1588_SHD_CTL_F9_C_BITS                                 1
#define TOP_1588_SHD_CTL_F9_C_SHIFT                                8

/* TOP_1588 :: SHD_CTL :: F8_C [07:07] */
#define Wr_TOP_1588_SHD_CTL_F8_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x80,7,x)
#define Rd_TOP_1588_SHD_CTL_F8_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x80,7)
#define TOP_1588_SHD_CTL_F8_C_MASK                                 0x0080
#define TOP_1588_SHD_CTL_F8_C_ALIGN                                0
#define TOP_1588_SHD_CTL_F8_C_BITS                                 1
#define TOP_1588_SHD_CTL_F8_C_SHIFT                                7

/* TOP_1588 :: SHD_CTL :: F7_C [06:06] */
#define Wr_TOP_1588_SHD_CTL_F7_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x40,6,x)
#define Rd_TOP_1588_SHD_CTL_F7_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x40,6)
#define TOP_1588_SHD_CTL_F7_C_MASK                                 0x0040
#define TOP_1588_SHD_CTL_F7_C_ALIGN                                0
#define TOP_1588_SHD_CTL_F7_C_BITS                                 1
#define TOP_1588_SHD_CTL_F7_C_SHIFT                                6

/* TOP_1588 :: SHD_CTL :: F6_C [05:05] */
#define Wr_TOP_1588_SHD_CTL_F6_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x20,5,x)
#define Rd_TOP_1588_SHD_CTL_F6_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x20,5)
#define TOP_1588_SHD_CTL_F6_C_MASK                                 0x0020
#define TOP_1588_SHD_CTL_F6_C_ALIGN                                0
#define TOP_1588_SHD_CTL_F6_C_BITS                                 1
#define TOP_1588_SHD_CTL_F6_C_SHIFT                                5

/* TOP_1588 :: SHD_CTL :: F5_C [04:04] */
#define Wr_TOP_1588_SHD_CTL_F5_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x10,4,x)
#define Rd_TOP_1588_SHD_CTL_F5_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x10,4)
#define TOP_1588_SHD_CTL_F5_C_MASK                                 0x0010
#define TOP_1588_SHD_CTL_F5_C_ALIGN                                0
#define TOP_1588_SHD_CTL_F5_C_BITS                                 1
#define TOP_1588_SHD_CTL_F5_C_SHIFT                                4

/* TOP_1588 :: SHD_CTL :: F4_C [03:03] */
#define Wr_TOP_1588_SHD_CTL_F4_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x8,3,x)
#define Rd_TOP_1588_SHD_CTL_F4_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x8,3)
#define TOP_1588_SHD_CTL_F4_C_MASK                                 0x0008
#define TOP_1588_SHD_CTL_F4_C_ALIGN                                0
#define TOP_1588_SHD_CTL_F4_C_BITS                                 1
#define TOP_1588_SHD_CTL_F4_C_SHIFT                                3

/* TOP_1588 :: SHD_CTL :: F3_C [02:02] */
#define Wr_TOP_1588_SHD_CTL_F3_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x4,2,x)
#define Rd_TOP_1588_SHD_CTL_F3_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x4,2)
#define TOP_1588_SHD_CTL_F3_C_MASK                                 0x0004
#define TOP_1588_SHD_CTL_F3_C_ALIGN                                0
#define TOP_1588_SHD_CTL_F3_C_BITS                                 1
#define TOP_1588_SHD_CTL_F3_C_SHIFT                                2

/* TOP_1588 :: SHD_CTL :: F2_C [01:01] */
#define Wr_TOP_1588_SHD_CTL_F2_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x2,1,x)
#define Rd_TOP_1588_SHD_CTL_F2_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x2,1)
#define TOP_1588_SHD_CTL_F2_C_MASK                                 0x0002
#define TOP_1588_SHD_CTL_F2_C_ALIGN                                0
#define TOP_1588_SHD_CTL_F2_C_BITS                                 1
#define TOP_1588_SHD_CTL_F2_C_SHIFT                                1

/* TOP_1588 :: SHD_CTL :: F1_C [00:00] */
#define Wr_TOP_1588_SHD_CTL_F1_C(x) WriteRegBits16(TOP_1588_SHD_CTL,0x1,0,x)
#define Rd_TOP_1588_SHD_CTL_F1_C(x) ReadRegBits16(TOP_1588_SHD_CTL,0x1,0)
#define TOP_1588_SHD_CTL_F1_C_MASK                                 0x0001
#define TOP_1588_SHD_CTL_F1_C_ALIGN                                0
#define TOP_1588_SHD_CTL_F1_C_BITS                                 1
#define TOP_1588_SHD_CTL_F1_C_SHIFT                                0


/****************************************************************************
 * TOP_1588 :: SHD_LD
 ***************************************************************************/
/* TOP_1588 :: SHD_LD :: F16_L [15:15] */
#define Wr_TOP_1588_SHD_LD_F16_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x8000,15,x)
#define Rd_TOP_1588_SHD_LD_F16_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x8000,15)
#define TOP_1588_SHD_LD_F16_L_MASK                                 0x8000
#define TOP_1588_SHD_LD_F16_L_ALIGN                                0
#define TOP_1588_SHD_LD_F16_L_BITS                                 1
#define TOP_1588_SHD_LD_F16_L_SHIFT                                15

/* TOP_1588 :: SHD_LD :: F15_L [14:14] */
#define Wr_TOP_1588_SHD_LD_F15_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x4000,14,x)
#define Rd_TOP_1588_SHD_LD_F15_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x4000,14)
#define TOP_1588_SHD_LD_F15_L_MASK                                 0x4000
#define TOP_1588_SHD_LD_F15_L_ALIGN                                0
#define TOP_1588_SHD_LD_F15_L_BITS                                 1
#define TOP_1588_SHD_LD_F15_L_SHIFT                                14

/* TOP_1588 :: SHD_LD :: F14_L [13:13] */
#define Wr_TOP_1588_SHD_LD_F14_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x2000,13,x)
#define Rd_TOP_1588_SHD_LD_F14_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x2000,13)
#define TOP_1588_SHD_LD_F14_L_MASK                                 0x2000
#define TOP_1588_SHD_LD_F14_L_ALIGN                                0
#define TOP_1588_SHD_LD_F14_L_BITS                                 1
#define TOP_1588_SHD_LD_F14_L_SHIFT                                13

/* TOP_1588 :: SHD_LD :: F13_L [12:12] */
#define Wr_TOP_1588_SHD_LD_F13_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x1000,12,x)
#define Rd_TOP_1588_SHD_LD_F13_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x1000,12)
#define TOP_1588_SHD_LD_F13_L_MASK                                 0x1000
#define TOP_1588_SHD_LD_F13_L_ALIGN                                0
#define TOP_1588_SHD_LD_F13_L_BITS                                 1
#define TOP_1588_SHD_LD_F13_L_SHIFT                                12

/* TOP_1588 :: SHD_LD :: F12_L [11:11] */
#define Wr_TOP_1588_SHD_LD_F12_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x800,11,x)
#define Rd_TOP_1588_SHD_LD_F12_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x800,11)
#define TOP_1588_SHD_LD_F12_L_MASK                                 0x0800
#define TOP_1588_SHD_LD_F12_L_ALIGN                                0
#define TOP_1588_SHD_LD_F12_L_BITS                                 1
#define TOP_1588_SHD_LD_F12_L_SHIFT                                11

/* TOP_1588 :: SHD_LD :: F11_L [10:10] */
#define Wr_TOP_1588_SHD_LD_F11_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x400,10,x)
#define Rd_TOP_1588_SHD_LD_F11_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x400,10)
#define TOP_1588_SHD_LD_F11_L_MASK                                 0x0400
#define TOP_1588_SHD_LD_F11_L_ALIGN                                0
#define TOP_1588_SHD_LD_F11_L_BITS                                 1
#define TOP_1588_SHD_LD_F11_L_SHIFT                                10

/* TOP_1588 :: SHD_LD :: F10_L [09:09] */
#define Wr_TOP_1588_SHD_LD_F10_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x200,9,x)
#define Rd_TOP_1588_SHD_LD_F10_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x200,9)
#define TOP_1588_SHD_LD_F10_L_MASK                                 0x0200
#define TOP_1588_SHD_LD_F10_L_ALIGN                                0
#define TOP_1588_SHD_LD_F10_L_BITS                                 1
#define TOP_1588_SHD_LD_F10_L_SHIFT                                9

/* TOP_1588 :: SHD_LD :: F9_L [08:08] */
#define Wr_TOP_1588_SHD_LD_F9_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x100,8,x)
#define Rd_TOP_1588_SHD_LD_F9_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x100,8)
#define TOP_1588_SHD_LD_F9_L_MASK                                  0x0100
#define TOP_1588_SHD_LD_F9_L_ALIGN                                 0
#define TOP_1588_SHD_LD_F9_L_BITS                                  1
#define TOP_1588_SHD_LD_F9_L_SHIFT                                 8

/* TOP_1588 :: SHD_LD :: F8_L [07:07] */
#define Wr_TOP_1588_SHD_LD_F8_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x80,7,x)
#define Rd_TOP_1588_SHD_LD_F8_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x80,7)
#define TOP_1588_SHD_LD_F8_L_MASK                                  0x0080
#define TOP_1588_SHD_LD_F8_L_ALIGN                                 0
#define TOP_1588_SHD_LD_F8_L_BITS                                  1
#define TOP_1588_SHD_LD_F8_L_SHIFT                                 7

/* TOP_1588 :: SHD_LD :: F7_L [06:06] */
#define Wr_TOP_1588_SHD_LD_F7_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x40,6,x)
#define Rd_TOP_1588_SHD_LD_F7_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x40,6)
#define TOP_1588_SHD_LD_F7_L_MASK                                  0x0040
#define TOP_1588_SHD_LD_F7_L_ALIGN                                 0
#define TOP_1588_SHD_LD_F7_L_BITS                                  1
#define TOP_1588_SHD_LD_F7_L_SHIFT                                 6

/* TOP_1588 :: SHD_LD :: F6_L [05:05] */
#define Wr_TOP_1588_SHD_LD_F6_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x20,5,x)
#define Rd_TOP_1588_SHD_LD_F6_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x20,5)
#define TOP_1588_SHD_LD_F6_L_MASK                                  0x0020
#define TOP_1588_SHD_LD_F6_L_ALIGN                                 0
#define TOP_1588_SHD_LD_F6_L_BITS                                  1
#define TOP_1588_SHD_LD_F6_L_SHIFT                                 5

/* TOP_1588 :: SHD_LD :: F5_L [04:04] */
#define Wr_TOP_1588_SHD_LD_F5_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x10,4,x)
#define Rd_TOP_1588_SHD_LD_F5_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x10,4)
#define TOP_1588_SHD_LD_F5_L_MASK                                  0x0010
#define TOP_1588_SHD_LD_F5_L_ALIGN                                 0
#define TOP_1588_SHD_LD_F5_L_BITS                                  1
#define TOP_1588_SHD_LD_F5_L_SHIFT                                 4

/* TOP_1588 :: SHD_LD :: F4_L [03:03] */
#define Wr_TOP_1588_SHD_LD_F4_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x8,3,x)
#define Rd_TOP_1588_SHD_LD_F4_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x8,3)
#define TOP_1588_SHD_LD_F4_L_MASK                                  0x0008
#define TOP_1588_SHD_LD_F4_L_ALIGN                                 0
#define TOP_1588_SHD_LD_F4_L_BITS                                  1
#define TOP_1588_SHD_LD_F4_L_SHIFT                                 3

/* TOP_1588 :: SHD_LD :: F3_L [02:02] */
#define Wr_TOP_1588_SHD_LD_F3_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x4,2,x)
#define Rd_TOP_1588_SHD_LD_F3_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x4,2)
#define TOP_1588_SHD_LD_F3_L_MASK                                  0x0004
#define TOP_1588_SHD_LD_F3_L_ALIGN                                 0
#define TOP_1588_SHD_LD_F3_L_BITS                                  1
#define TOP_1588_SHD_LD_F3_L_SHIFT                                 2

/* TOP_1588 :: SHD_LD :: F2_L [01:01] */
#define Wr_TOP_1588_SHD_LD_F2_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x2,1,x)
#define Rd_TOP_1588_SHD_LD_F2_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x2,1)
#define TOP_1588_SHD_LD_F2_L_MASK                                  0x0002
#define TOP_1588_SHD_LD_F2_L_ALIGN                                 0
#define TOP_1588_SHD_LD_F2_L_BITS                                  1
#define TOP_1588_SHD_LD_F2_L_SHIFT                                 1

/* TOP_1588 :: SHD_LD :: F1_L [00:00] */
#define Wr_TOP_1588_SHD_LD_F1_L(x) WriteRegBits16(TOP_1588_SHD_LD,0x1,0,x)
#define Rd_TOP_1588_SHD_LD_F1_L(x) ReadRegBits16(TOP_1588_SHD_LD,0x1,0)
#define TOP_1588_SHD_LD_F1_L_MASK                                  0x0001
#define TOP_1588_SHD_LD_F1_L_ALIGN                                 0
#define TOP_1588_SHD_LD_F1_L_BITS                                  1
#define TOP_1588_SHD_LD_F1_L_SHIFT                                 0


/****************************************************************************
 * TOP_1588 :: INT_MASK
 ***************************************************************************/
/* TOP_1588 :: INT_MASK :: reserved0 [15:11] */
#define TOP_1588_INT_MASK_RESERVED0_MASK                           0xf800
#define TOP_1588_INT_MASK_RESERVED0_ALIGN                          0
#define TOP_1588_INT_MASK_RESERVED0_BITS                           5
#define TOP_1588_INT_MASK_RESERVED0_SHIFT                          11

/* TOP_1588 :: INT_MASK :: SPARE_REG [10:09] */
#define Wr_TOP_1588_INT_MASK_SPARE_REG(x) WriteRegBits16(TOP_1588_INT_MASK,0x600,9,x)
#define Rd_TOP_1588_INT_MASK_SPARE_REG(x) ReadRegBits16(TOP_1588_INT_MASK,0x600,9)
#define TOP_1588_INT_MASK_SPARE_REG_MASK                           0x0600
#define TOP_1588_INT_MASK_SPARE_REG_ALIGN                          0
#define TOP_1588_INT_MASK_SPARE_REG_BITS                           2
#define TOP_1588_INT_MASK_SPARE_REG_SHIFT                          9

/* TOP_1588 :: INT_MASK :: INTC_SOP_MASK [08:01] */
#define Wr_TOP_1588_INT_MASK_INTC_SOP_MASK(x) WriteRegBits16(TOP_1588_INT_MASK,0x1fe,1,x)
#define Rd_TOP_1588_INT_MASK_INTC_SOP_MASK(x) ReadRegBits16(TOP_1588_INT_MASK,0x1fe,1)
#define TOP_1588_INT_MASK_INTC_SOP_MASK_MASK                       0x01fe
#define TOP_1588_INT_MASK_INTC_SOP_MASK_ALIGN                      0
#define TOP_1588_INT_MASK_INTC_SOP_MASK_BITS                       8
#define TOP_1588_INT_MASK_INTC_SOP_MASK_SHIFT                      1

/* TOP_1588 :: INT_MASK :: INTC_FSYNC_MASK [00:00] */
#define Wr_TOP_1588_INT_MASK_INTC_FSYNC_MASK(x) WriteRegBits16(TOP_1588_INT_MASK,0x1,0,x)
#define Rd_TOP_1588_INT_MASK_INTC_FSYNC_MASK(x) ReadRegBits16(TOP_1588_INT_MASK,0x1,0)
#define TOP_1588_INT_MASK_INTC_FSYNC_MASK_MASK                     0x0001
#define TOP_1588_INT_MASK_INTC_FSYNC_MASK_ALIGN                    0
#define TOP_1588_INT_MASK_INTC_FSYNC_MASK_BITS                     1
#define TOP_1588_INT_MASK_INTC_FSYNC_MASK_SHIFT                    0


/****************************************************************************
 * TOP_1588 :: INT_STAT
 ***************************************************************************/
/* TOP_1588 :: INT_STAT :: reserved0 [15:11] */
#define TOP_1588_INT_STAT_RESERVED0_MASK                           0xf800
#define TOP_1588_INT_STAT_RESERVED0_ALIGN                          0
#define TOP_1588_INT_STAT_RESERVED0_BITS                           5
#define TOP_1588_INT_STAT_RESERVED0_SHIFT                          11

/* TOP_1588 :: INT_STAT :: INTC_RESERVED [10:09] */
#define Wr_TOP_1588_INT_STAT_INTC_RESERVED(x) WriteRegBits16(TOP_1588_INT_STAT,0x600,9,x)
#define Rd_TOP_1588_INT_STAT_INTC_RESERVED(x) ReadRegBits16(TOP_1588_INT_STAT,0x600,9)
#define TOP_1588_INT_STAT_INTC_RESERVED_MASK                       0x0600
#define TOP_1588_INT_STAT_INTC_RESERVED_ALIGN                      0
#define TOP_1588_INT_STAT_INTC_RESERVED_BITS                       2
#define TOP_1588_INT_STAT_INTC_RESERVED_SHIFT                      9

/* TOP_1588 :: INT_STAT :: INTC_SOP [08:01] */
#define Wr_TOP_1588_INT_STAT_INTC_SOP(x) WriteRegBits16(TOP_1588_INT_STAT,0x1fe,1,x)
#define Rd_TOP_1588_INT_STAT_INTC_SOP(x) ReadRegBits16(TOP_1588_INT_STAT,0x1fe,1)
#define TOP_1588_INT_STAT_INTC_SOP_MASK                            0x01fe
#define TOP_1588_INT_STAT_INTC_SOP_ALIGN                           0
#define TOP_1588_INT_STAT_INTC_SOP_BITS                            8
#define TOP_1588_INT_STAT_INTC_SOP_SHIFT                           1

/* TOP_1588 :: INT_STAT :: INTC_FSYNC [00:00] */
#define Wr_TOP_1588_INT_STAT_INTC_FSYNC(x) WriteRegBits16(TOP_1588_INT_STAT,0x1,0,x)
#define Rd_TOP_1588_INT_STAT_INTC_FSYNC(x) ReadRegBits16(TOP_1588_INT_STAT,0x1,0)
#define TOP_1588_INT_STAT_INTC_FSYNC_MASK                          0x0001
#define TOP_1588_INT_STAT_INTC_FSYNC_ALIGN                         0
#define TOP_1588_INT_STAT_INTC_FSYNC_BITS                          1
#define TOP_1588_INT_STAT_INTC_FSYNC_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: TX_CTL
 ***************************************************************************/
/* TOP_1588 :: TX_CTL :: TX_OFFSET [15:08] */
#define Wr_TOP_1588_TX_CTL_TX_OFFSET(x) WriteRegBits16(TOP_1588_TX_CTL,0xff00,8,x)
#define Rd_TOP_1588_TX_CTL_TX_OFFSET(x) ReadRegBits16(TOP_1588_TX_CTL,0xff00,8)
#define TOP_1588_TX_CTL_TX_OFFSET_MASK                             0xff00
#define TOP_1588_TX_CTL_TX_OFFSET_ALIGN                            0
#define TOP_1588_TX_CTL_TX_OFFSET_BITS                             8
#define TOP_1588_TX_CTL_TX_OFFSET_SHIFT                            8

/* TOP_1588 :: TX_CTL :: TX_AS_DS_EN [07:07] */
#define Wr_TOP_1588_TX_CTL_TX_AS_DS_EN(x) WriteRegBits16(TOP_1588_TX_CTL,0x80,7,x)
#define Rd_TOP_1588_TX_CTL_TX_AS_DS_EN(x) ReadRegBits16(TOP_1588_TX_CTL,0x80,7)
#define TOP_1588_TX_CTL_TX_AS_DS_EN_MASK                           0x0080
#define TOP_1588_TX_CTL_TX_AS_DS_EN_ALIGN                          0
#define TOP_1588_TX_CTL_TX_AS_DS_EN_BITS                           1
#define TOP_1588_TX_CTL_TX_AS_DS_EN_SHIFT                          7

/* TOP_1588 :: TX_CTL :: TX_L2_DS_EN [06:06] */
#define Wr_TOP_1588_TX_CTL_TX_L2_DS_EN(x) WriteRegBits16(TOP_1588_TX_CTL,0x40,6,x)
#define Rd_TOP_1588_TX_CTL_TX_L2_DS_EN(x) ReadRegBits16(TOP_1588_TX_CTL,0x40,6)
#define TOP_1588_TX_CTL_TX_L2_DS_EN_MASK                           0x0040
#define TOP_1588_TX_CTL_TX_L2_DS_EN_ALIGN                          0
#define TOP_1588_TX_CTL_TX_L2_DS_EN_BITS                           1
#define TOP_1588_TX_CTL_TX_L2_DS_EN_SHIFT                          6

/* TOP_1588 :: TX_CTL :: TX_L4_IP_ADDRESS_EN [05:05] */
#define Wr_TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN(x) WriteRegBits16(TOP_1588_TX_CTL,0x20,5,x)
#define Rd_TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN(x) ReadRegBits16(TOP_1588_TX_CTL,0x20,5)
#define TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN_MASK                   0x0020
#define TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN_ALIGN                  0
#define TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN_BITS                   1
#define TOP_1588_TX_CTL_TX_L4_IP_ADDRESS_EN_SHIFT                  5

/* TOP_1588 :: TX_CTL :: TX_L4_IPV6_ADDRESS_EN [04:04] */
#define Wr_TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN(x) WriteRegBits16(TOP_1588_TX_CTL,0x10,4,x)
#define Rd_TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN(x) ReadRegBits16(TOP_1588_TX_CTL,0x10,4)
#define TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN_MASK                 0x0010
#define TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN_ALIGN                0
#define TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN_BITS                 1
#define TOP_1588_TX_CTL_TX_L4_IPV6_ADDRESS_EN_SHIFT                4

/* TOP_1588 :: TX_CTL :: TX_AS_EN [03:03] */
#define Wr_TOP_1588_TX_CTL_TX_AS_EN(x) WriteRegBits16(TOP_1588_TX_CTL,0x8,3,x)
#define Rd_TOP_1588_TX_CTL_TX_AS_EN(x) ReadRegBits16(TOP_1588_TX_CTL,0x8,3)
#define TOP_1588_TX_CTL_TX_AS_EN_MASK                              0x0008
#define TOP_1588_TX_CTL_TX_AS_EN_ALIGN                             0
#define TOP_1588_TX_CTL_TX_AS_EN_BITS                              1
#define TOP_1588_TX_CTL_TX_AS_EN_SHIFT                             3

/* TOP_1588 :: TX_CTL :: TX_L2_EN [02:02] */
#define Wr_TOP_1588_TX_CTL_TX_L2_EN(x) WriteRegBits16(TOP_1588_TX_CTL,0x4,2,x)
#define Rd_TOP_1588_TX_CTL_TX_L2_EN(x) ReadRegBits16(TOP_1588_TX_CTL,0x4,2)
#define TOP_1588_TX_CTL_TX_L2_EN_MASK                              0x0004
#define TOP_1588_TX_CTL_TX_L2_EN_ALIGN                             0
#define TOP_1588_TX_CTL_TX_L2_EN_BITS                              1
#define TOP_1588_TX_CTL_TX_L2_EN_SHIFT                             2

/* TOP_1588 :: TX_CTL :: TX_IPV4_UDP_EN [01:01] */
#define Wr_TOP_1588_TX_CTL_TX_IPV4_UDP_EN(x) WriteRegBits16(TOP_1588_TX_CTL,0x2,1,x)
#define Rd_TOP_1588_TX_CTL_TX_IPV4_UDP_EN(x) ReadRegBits16(TOP_1588_TX_CTL,0x2,1)
#define TOP_1588_TX_CTL_TX_IPV4_UDP_EN_MASK                        0x0002
#define TOP_1588_TX_CTL_TX_IPV4_UDP_EN_ALIGN                       0
#define TOP_1588_TX_CTL_TX_IPV4_UDP_EN_BITS                        1
#define TOP_1588_TX_CTL_TX_IPV4_UDP_EN_SHIFT                       1

/* TOP_1588 :: TX_CTL :: TX_IPV6_UDP_EN [00:00] */
#define Wr_TOP_1588_TX_CTL_TX_IPV6_UDP_EN(x) WriteRegBits16(TOP_1588_TX_CTL,0x1,0,x)
#define Rd_TOP_1588_TX_CTL_TX_IPV6_UDP_EN(x) ReadRegBits16(TOP_1588_TX_CTL,0x1,0)
#define TOP_1588_TX_CTL_TX_IPV6_UDP_EN_MASK                        0x0001
#define TOP_1588_TX_CTL_TX_IPV6_UDP_EN_ALIGN                       0
#define TOP_1588_TX_CTL_TX_IPV6_UDP_EN_BITS                        1
#define TOP_1588_TX_CTL_TX_IPV6_UDP_EN_SHIFT                       0


/****************************************************************************
 * TOP_1588 :: RX_CTL
 ***************************************************************************/
/* TOP_1588 :: RX_CTL :: RX_OFFSET [15:08] */
#define Wr_TOP_1588_RX_CTL_RX_OFFSET(x) WriteRegBits16(TOP_1588_RX_CTL,0xff00,8,x)
#define Rd_TOP_1588_RX_CTL_RX_OFFSET(x) ReadRegBits16(TOP_1588_RX_CTL,0xff00,8)
#define TOP_1588_RX_CTL_RX_OFFSET_MASK                             0xff00
#define TOP_1588_RX_CTL_RX_OFFSET_ALIGN                            0
#define TOP_1588_RX_CTL_RX_OFFSET_BITS                             8
#define TOP_1588_RX_CTL_RX_OFFSET_SHIFT                            8

/* TOP_1588 :: RX_CTL :: RX_AS_DS_EN [07:07] */
#define Wr_TOP_1588_RX_CTL_RX_AS_DS_EN(x) WriteRegBits16(TOP_1588_RX_CTL,0x80,7,x)
#define Rd_TOP_1588_RX_CTL_RX_AS_DS_EN(x) ReadRegBits16(TOP_1588_RX_CTL,0x80,7)
#define TOP_1588_RX_CTL_RX_AS_DS_EN_MASK                           0x0080
#define TOP_1588_RX_CTL_RX_AS_DS_EN_ALIGN                          0
#define TOP_1588_RX_CTL_RX_AS_DS_EN_BITS                           1
#define TOP_1588_RX_CTL_RX_AS_DS_EN_SHIFT                          7

/* TOP_1588 :: RX_CTL :: RX_L2_DS_EN [06:06] */
#define Wr_TOP_1588_RX_CTL_RX_L2_DS_EN(x) WriteRegBits16(TOP_1588_RX_CTL,0x40,6,x)
#define Rd_TOP_1588_RX_CTL_RX_L2_DS_EN(x) ReadRegBits16(TOP_1588_RX_CTL,0x40,6)
#define TOP_1588_RX_CTL_RX_L2_DS_EN_MASK                           0x0040
#define TOP_1588_RX_CTL_RX_L2_DS_EN_ALIGN                          0
#define TOP_1588_RX_CTL_RX_L2_DS_EN_BITS                           1
#define TOP_1588_RX_CTL_RX_L2_DS_EN_SHIFT                          6

/* TOP_1588 :: RX_CTL :: RX_L4_IP_ADDRESS_EN [05:05] */
#define Wr_TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN(x) WriteRegBits16(TOP_1588_RX_CTL,0x20,5,x)
#define Rd_TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN(x) ReadRegBits16(TOP_1588_RX_CTL,0x20,5)
#define TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN_MASK                   0x0020
#define TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN_ALIGN                  0
#define TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN_BITS                   1
#define TOP_1588_RX_CTL_RX_L4_IP_ADDRESS_EN_SHIFT                  5

/* TOP_1588 :: RX_CTL :: RX_L4_IPV6_ADDRESS_EN [04:04] */
#define Wr_TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN(x) WriteRegBits16(TOP_1588_RX_CTL,0x10,4,x)
#define Rd_TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN(x) ReadRegBits16(TOP_1588_RX_CTL,0x10,4)
#define TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN_MASK                 0x0010
#define TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN_ALIGN                0
#define TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN_BITS                 1
#define TOP_1588_RX_CTL_RX_L4_IPV6_ADDRESS_EN_SHIFT                4

/* TOP_1588 :: RX_CTL :: RX_AS_EN [03:03] */
#define Wr_TOP_1588_RX_CTL_RX_AS_EN(x) WriteRegBits16(TOP_1588_RX_CTL,0x8,3,x)
#define Rd_TOP_1588_RX_CTL_RX_AS_EN(x) ReadRegBits16(TOP_1588_RX_CTL,0x8,3)
#define TOP_1588_RX_CTL_RX_AS_EN_MASK                              0x0008
#define TOP_1588_RX_CTL_RX_AS_EN_ALIGN                             0
#define TOP_1588_RX_CTL_RX_AS_EN_BITS                              1
#define TOP_1588_RX_CTL_RX_AS_EN_SHIFT                             3

/* TOP_1588 :: RX_CTL :: RX_L2_EN [02:02] */
#define Wr_TOP_1588_RX_CTL_RX_L2_EN(x) WriteRegBits16(TOP_1588_RX_CTL,0x4,2,x)
#define Rd_TOP_1588_RX_CTL_RX_L2_EN(x) ReadRegBits16(TOP_1588_RX_CTL,0x4,2)
#define TOP_1588_RX_CTL_RX_L2_EN_MASK                              0x0004
#define TOP_1588_RX_CTL_RX_L2_EN_ALIGN                             0
#define TOP_1588_RX_CTL_RX_L2_EN_BITS                              1
#define TOP_1588_RX_CTL_RX_L2_EN_SHIFT                             2

/* TOP_1588 :: RX_CTL :: RX_IPV4_UDP_EN [01:01] */
#define Wr_TOP_1588_RX_CTL_RX_IPV4_UDP_EN(x) WriteRegBits16(TOP_1588_RX_CTL,0x2,1,x)
#define Rd_TOP_1588_RX_CTL_RX_IPV4_UDP_EN(x) ReadRegBits16(TOP_1588_RX_CTL,0x2,1)
#define TOP_1588_RX_CTL_RX_IPV4_UDP_EN_MASK                        0x0002
#define TOP_1588_RX_CTL_RX_IPV4_UDP_EN_ALIGN                       0
#define TOP_1588_RX_CTL_RX_IPV4_UDP_EN_BITS                        1
#define TOP_1588_RX_CTL_RX_IPV4_UDP_EN_SHIFT                       1

/* TOP_1588 :: RX_CTL :: RX_IPV6_UDP_EN [00:00] */
#define Wr_TOP_1588_RX_CTL_RX_IPV6_UDP_EN(x) WriteRegBits16(TOP_1588_RX_CTL,0x1,0,x)
#define Rd_TOP_1588_RX_CTL_RX_IPV6_UDP_EN(x) ReadRegBits16(TOP_1588_RX_CTL,0x1,0)
#define TOP_1588_RX_CTL_RX_IPV6_UDP_EN_MASK                        0x0001
#define TOP_1588_RX_CTL_RX_IPV6_UDP_EN_ALIGN                       0
#define TOP_1588_RX_CTL_RX_IPV6_UDP_EN_BITS                        1
#define TOP_1588_RX_CTL_RX_IPV6_UDP_EN_SHIFT                       0


/****************************************************************************
 * TOP_1588 :: RX_TX_CTL
 ***************************************************************************/
/* TOP_1588 :: RX_TX_CTL :: reserved0 [15:08] */
#define TOP_1588_RX_TX_CTL_RESERVED0_MASK                          0xff00
#define TOP_1588_RX_TX_CTL_RESERVED0_ALIGN                         0
#define TOP_1588_RX_TX_CTL_RESERVED0_BITS                          8
#define TOP_1588_RX_TX_CTL_RESERVED0_SHIFT                         8

/* TOP_1588 :: RX_TX_CTL :: TX_CRC_EN [07:07] */
#define Wr_TOP_1588_RX_TX_CTL_TX_CRC_EN(x) WriteRegBits16(TOP_1588_RX_TX_CTL,0x80,7,x)
#define Rd_TOP_1588_RX_TX_CTL_TX_CRC_EN(x) ReadRegBits16(TOP_1588_RX_TX_CTL,0x80,7)
#define TOP_1588_RX_TX_CTL_TX_CRC_EN_MASK                          0x0080
#define TOP_1588_RX_TX_CTL_TX_CRC_EN_ALIGN                         0
#define TOP_1588_RX_TX_CTL_TX_CRC_EN_BITS                          1
#define TOP_1588_RX_TX_CTL_TX_CRC_EN_SHIFT                         7

/* TOP_1588 :: RX_TX_CTL :: TX_L4_IP_ADDRESS_SEL [06:04] */
#define Wr_TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL(x) WriteRegBits16(TOP_1588_RX_TX_CTL,0x70,4,x)
#define Rd_TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL(x) ReadRegBits16(TOP_1588_RX_TX_CTL,0x70,4)
#define TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL_MASK               0x0070
#define TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL_ALIGN              0
#define TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL_BITS               3
#define TOP_1588_RX_TX_CTL_TX_L4_IP_ADDRESS_SEL_SHIFT              4

/* TOP_1588 :: RX_TX_CTL :: RX_CRC_EN [03:03] */
#define Wr_TOP_1588_RX_TX_CTL_RX_CRC_EN(x) WriteRegBits16(TOP_1588_RX_TX_CTL,0x8,3,x)
#define Rd_TOP_1588_RX_TX_CTL_RX_CRC_EN(x) ReadRegBits16(TOP_1588_RX_TX_CTL,0x8,3)
#define TOP_1588_RX_TX_CTL_RX_CRC_EN_MASK                          0x0008
#define TOP_1588_RX_TX_CTL_RX_CRC_EN_ALIGN                         0
#define TOP_1588_RX_TX_CTL_RX_CRC_EN_BITS                          1
#define TOP_1588_RX_TX_CTL_RX_CRC_EN_SHIFT                         3

/* TOP_1588 :: RX_TX_CTL :: RX_L4_IP_ADDRESS_SEL [02:00] */
#define Wr_TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL(x) WriteRegBits16(TOP_1588_RX_TX_CTL,0x7,0,x)
#define Rd_TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL(x) ReadRegBits16(TOP_1588_RX_TX_CTL,0x7,0)
#define TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL_MASK               0x0007
#define TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL_ALIGN              0
#define TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL_BITS               3
#define TOP_1588_RX_TX_CTL_RX_L4_IP_ADDRESS_SEL_SHIFT              0


/****************************************************************************
 * TOP_1588 :: VLAN_ITPID
 ***************************************************************************/
/* TOP_1588 :: VLAN_ITPID :: ITPID [15:00] */
#define Wr_TOP_1588_VLAN_ITPID_ITPID(x) WriteReg16(TOP_1588_VLAN_ITPID,x)
#define Rd_TOP_1588_VLAN_ITPID_ITPID(x) ReadReg16(TOP_1588_VLAN_ITPID)
#define TOP_1588_VLAN_ITPID_ITPID_MASK                             0xffff
#define TOP_1588_VLAN_ITPID_ITPID_ALIGN                            0
#define TOP_1588_VLAN_ITPID_ITPID_BITS                             16
#define TOP_1588_VLAN_ITPID_ITPID_SHIFT                            0


/****************************************************************************
 * TOP_1588 :: VLAN_OTPID
 ***************************************************************************/
/* TOP_1588 :: VLAN_OTPID :: OTPID [15:00] */
#define Wr_TOP_1588_VLAN_OTPID_OTPID(x) WriteReg16(TOP_1588_VLAN_OTPID,x)
#define Rd_TOP_1588_VLAN_OTPID_OTPID(x) ReadReg16(TOP_1588_VLAN_OTPID)
#define TOP_1588_VLAN_OTPID_OTPID_MASK                             0xffff
#define TOP_1588_VLAN_OTPID_OTPID_ALIGN                            0
#define TOP_1588_VLAN_OTPID_OTPID_BITS                             16
#define TOP_1588_VLAN_OTPID_OTPID_SHIFT                            0


/****************************************************************************
 * TOP_1588 :: OTHER_OTPID
 ***************************************************************************/
/* TOP_1588 :: OTHER_OTPID :: OTPID_2 [15:00] */
#define Wr_TOP_1588_OTHER_OTPID_OTPID_2(x) WriteReg16(TOP_1588_OTHER_OTPID,x)
#define Rd_TOP_1588_OTHER_OTPID_OTPID_2(x) ReadReg16(TOP_1588_OTHER_OTPID)
#define TOP_1588_OTHER_OTPID_OTPID_2_MASK                          0xffff
#define TOP_1588_OTHER_OTPID_OTPID_2_ALIGN                         0
#define TOP_1588_OTHER_OTPID_OTPID_2_BITS                          16
#define TOP_1588_OTHER_OTPID_OTPID_2_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_1
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_1 :: SPARE_REG1 [15:12] */
#define Wr_TOP_1588_NSE_DPLL_1_SPARE_REG1(x) WriteRegBits16(TOP_1588_NSE_DPLL_1,0xf000,12,x)
#define Rd_TOP_1588_NSE_DPLL_1_SPARE_REG1(x) ReadRegBits16(TOP_1588_NSE_DPLL_1,0xf000,12)
#define TOP_1588_NSE_DPLL_1_SPARE_REG1_MASK                        0xf000
#define TOP_1588_NSE_DPLL_1_SPARE_REG1_ALIGN                       0
#define TOP_1588_NSE_DPLL_1_SPARE_REG1_BITS                        4
#define TOP_1588_NSE_DPLL_1_SPARE_REG1_SHIFT                       12

/* TOP_1588 :: NSE_DPLL_1 :: TS_DEBUG [11:09] */
#define Wr_TOP_1588_NSE_DPLL_1_TS_DEBUG(x) WriteRegBits16(TOP_1588_NSE_DPLL_1,0xe00,9,x)
#define Rd_TOP_1588_NSE_DPLL_1_TS_DEBUG(x) ReadRegBits16(TOP_1588_NSE_DPLL_1,0xe00,9)
#define TOP_1588_NSE_DPLL_1_TS_DEBUG_MASK                          0x0e00
#define TOP_1588_NSE_DPLL_1_TS_DEBUG_ALIGN                         0
#define TOP_1588_NSE_DPLL_1_TS_DEBUG_BITS                          3
#define TOP_1588_NSE_DPLL_1_TS_DEBUG_SHIFT                         9

/* TOP_1588 :: NSE_DPLL_1 :: TS_DEBUG_EN [08:08] */
#define Wr_TOP_1588_NSE_DPLL_1_TS_DEBUG_EN(x) WriteRegBits16(TOP_1588_NSE_DPLL_1,0x100,8,x)
#define Rd_TOP_1588_NSE_DPLL_1_TS_DEBUG_EN(x) ReadRegBits16(TOP_1588_NSE_DPLL_1,0x100,8)
#define TOP_1588_NSE_DPLL_1_TS_DEBUG_EN_MASK                       0x0100
#define TOP_1588_NSE_DPLL_1_TS_DEBUG_EN_ALIGN                      0
#define TOP_1588_NSE_DPLL_1_TS_DEBUG_EN_BITS                       1
#define TOP_1588_NSE_DPLL_1_TS_DEBUG_EN_SHIFT                      8

/* TOP_1588 :: NSE_DPLL_1 :: RX_TEST_SEL [07:07] */
#define Wr_TOP_1588_NSE_DPLL_1_RX_TEST_SEL(x) WriteRegBits16(TOP_1588_NSE_DPLL_1,0x80,7,x)
#define Rd_TOP_1588_NSE_DPLL_1_RX_TEST_SEL(x) ReadRegBits16(TOP_1588_NSE_DPLL_1,0x80,7)
#define TOP_1588_NSE_DPLL_1_RX_TEST_SEL_MASK                       0x0080
#define TOP_1588_NSE_DPLL_1_RX_TEST_SEL_ALIGN                      0
#define TOP_1588_NSE_DPLL_1_RX_TEST_SEL_BITS                       1
#define TOP_1588_NSE_DPLL_1_RX_TEST_SEL_SHIFT                      7

/* TOP_1588 :: NSE_DPLL_1 :: SPARE_REG0 [06:06] */
#define Wr_TOP_1588_NSE_DPLL_1_SPARE_REG0(x) WriteRegBits16(TOP_1588_NSE_DPLL_1,0x40,6,x)
#define Rd_TOP_1588_NSE_DPLL_1_SPARE_REG0(x) ReadRegBits16(TOP_1588_NSE_DPLL_1,0x40,6)
#define TOP_1588_NSE_DPLL_1_SPARE_REG0_MASK                        0x0040
#define TOP_1588_NSE_DPLL_1_SPARE_REG0_ALIGN                       0
#define TOP_1588_NSE_DPLL_1_SPARE_REG0_BITS                        1
#define TOP_1588_NSE_DPLL_1_SPARE_REG0_SHIFT                       6

/* TOP_1588 :: NSE_DPLL_1 :: TEST_BUS_SEL [05:01] */
#define Wr_TOP_1588_NSE_DPLL_1_TEST_BUS_SEL(x) WriteRegBits16(TOP_1588_NSE_DPLL_1,0x3e,1,x)
#define Rd_TOP_1588_NSE_DPLL_1_TEST_BUS_SEL(x) ReadRegBits16(TOP_1588_NSE_DPLL_1,0x3e,1)
#define TOP_1588_NSE_DPLL_1_TEST_BUS_SEL_MASK                      0x003e
#define TOP_1588_NSE_DPLL_1_TEST_BUS_SEL_ALIGN                     0
#define TOP_1588_NSE_DPLL_1_TEST_BUS_SEL_BITS                      5
#define TOP_1588_NSE_DPLL_1_TEST_BUS_SEL_SHIFT                     1

/* TOP_1588 :: NSE_DPLL_1 :: DPLL_SELECT_MODE [00:00] */
#define Wr_TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE(x) WriteRegBits16(TOP_1588_NSE_DPLL_1,0x1,0,x)
#define Rd_TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE(x) ReadRegBits16(TOP_1588_NSE_DPLL_1,0x1,0)
#define TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE_MASK                  0x0001
#define TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE_ALIGN                 0
#define TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE_BITS                  1
#define TOP_1588_NSE_DPLL_1_DPLL_SELECT_MODE_SHIFT                 0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_2_0
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_2_0 :: REF_PHASE_0 [15:00] */
#define Wr_TOP_1588_NSE_DPLL_2_0_REF_PHASE_0(x) WriteReg16(TOP_1588_NSE_DPLL_2_0,x)
#define Rd_TOP_1588_NSE_DPLL_2_0_REF_PHASE_0(x) ReadReg16(TOP_1588_NSE_DPLL_2_0)
#define TOP_1588_NSE_DPLL_2_0_REF_PHASE_0_MASK                     0xffff
#define TOP_1588_NSE_DPLL_2_0_REF_PHASE_0_ALIGN                    0
#define TOP_1588_NSE_DPLL_2_0_REF_PHASE_0_BITS                     16
#define TOP_1588_NSE_DPLL_2_0_REF_PHASE_0_SHIFT                    0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_2_1
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_2_1 :: REF_PHASE_1 [15:00] */
#define Wr_TOP_1588_NSE_DPLL_2_1_REF_PHASE_1(x) WriteReg16(TOP_1588_NSE_DPLL_2_1,x)
#define Rd_TOP_1588_NSE_DPLL_2_1_REF_PHASE_1(x) ReadReg16(TOP_1588_NSE_DPLL_2_1)
#define TOP_1588_NSE_DPLL_2_1_REF_PHASE_1_MASK                     0xffff
#define TOP_1588_NSE_DPLL_2_1_REF_PHASE_1_ALIGN                    0
#define TOP_1588_NSE_DPLL_2_1_REF_PHASE_1_BITS                     16
#define TOP_1588_NSE_DPLL_2_1_REF_PHASE_1_SHIFT                    0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_2_2
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_2_2 :: REF_PHASE_2 [15:00] */
#define Wr_TOP_1588_NSE_DPLL_2_2_REF_PHASE_2(x) WriteReg16(TOP_1588_NSE_DPLL_2_2,x)
#define Rd_TOP_1588_NSE_DPLL_2_2_REF_PHASE_2(x) ReadReg16(TOP_1588_NSE_DPLL_2_2)
#define TOP_1588_NSE_DPLL_2_2_REF_PHASE_2_MASK                     0xffff
#define TOP_1588_NSE_DPLL_2_2_REF_PHASE_2_ALIGN                    0
#define TOP_1588_NSE_DPLL_2_2_REF_PHASE_2_BITS                     16
#define TOP_1588_NSE_DPLL_2_2_REF_PHASE_2_SHIFT                    0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_3_LSB
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_3_LSB :: REF_PHASE_DELTA_LSB [15:00] */
#define Wr_TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB(x) WriteReg16(TOP_1588_NSE_DPLL_3_LSB,x)
#define Rd_TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB(x) ReadReg16(TOP_1588_NSE_DPLL_3_LSB)
#define TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB_MASK           0xffff
#define TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB_ALIGN          0
#define TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB_BITS           16
#define TOP_1588_NSE_DPLL_3_LSB_REF_PHASE_DELTA_LSB_SHIFT          0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_3_MSB
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_3_MSB :: REF_PHASE_DELTA_MSB [15:00] */
#define Wr_TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB(x) WriteReg16(TOP_1588_NSE_DPLL_3_MSB,x)
#define Rd_TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB(x) ReadReg16(TOP_1588_NSE_DPLL_3_MSB)
#define TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB_MASK           0xffff
#define TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB_ALIGN          0
#define TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB_BITS           16
#define TOP_1588_NSE_DPLL_3_MSB_REF_PHASE_DELTA_MSB_SHIFT          0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_4
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_4 :: reserved0 [15:08] */
#define TOP_1588_NSE_DPLL_4_RESERVED0_MASK                         0xff00
#define TOP_1588_NSE_DPLL_4_RESERVED0_ALIGN                        0
#define TOP_1588_NSE_DPLL_4_RESERVED0_BITS                         8
#define TOP_1588_NSE_DPLL_4_RESERVED0_SHIFT                        8

/* TOP_1588 :: NSE_DPLL_4 :: DPLL_K1 [07:00] */
#define Wr_TOP_1588_NSE_DPLL_4_DPLL_K1(x) WriteRegBits16(TOP_1588_NSE_DPLL_4,0xff,0,x)
#define Rd_TOP_1588_NSE_DPLL_4_DPLL_K1(x) ReadRegBits16(TOP_1588_NSE_DPLL_4,0xff,0)
#define TOP_1588_NSE_DPLL_4_DPLL_K1_MASK                           0x00ff
#define TOP_1588_NSE_DPLL_4_DPLL_K1_ALIGN                          0
#define TOP_1588_NSE_DPLL_4_DPLL_K1_BITS                           8
#define TOP_1588_NSE_DPLL_4_DPLL_K1_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_5
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_5 :: reserved0 [15:08] */
#define TOP_1588_NSE_DPLL_5_RESERVED0_MASK                         0xff00
#define TOP_1588_NSE_DPLL_5_RESERVED0_ALIGN                        0
#define TOP_1588_NSE_DPLL_5_RESERVED0_BITS                         8
#define TOP_1588_NSE_DPLL_5_RESERVED0_SHIFT                        8

/* TOP_1588 :: NSE_DPLL_5 :: DPLL_K2 [07:00] */
#define Wr_TOP_1588_NSE_DPLL_5_DPLL_K2(x) WriteRegBits16(TOP_1588_NSE_DPLL_5,0xff,0,x)
#define Rd_TOP_1588_NSE_DPLL_5_DPLL_K2(x) ReadRegBits16(TOP_1588_NSE_DPLL_5,0xff,0)
#define TOP_1588_NSE_DPLL_5_DPLL_K2_MASK                           0x00ff
#define TOP_1588_NSE_DPLL_5_DPLL_K2_ALIGN                          0
#define TOP_1588_NSE_DPLL_5_DPLL_K2_BITS                           8
#define TOP_1588_NSE_DPLL_5_DPLL_K2_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_6
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_6 :: reserved0 [15:08] */
#define TOP_1588_NSE_DPLL_6_RESERVED0_MASK                         0xff00
#define TOP_1588_NSE_DPLL_6_RESERVED0_ALIGN                        0
#define TOP_1588_NSE_DPLL_6_RESERVED0_BITS                         8
#define TOP_1588_NSE_DPLL_6_RESERVED0_SHIFT                        8

/* TOP_1588 :: NSE_DPLL_6 :: DPLL_K3 [07:00] */
#define Wr_TOP_1588_NSE_DPLL_6_DPLL_K3(x) WriteRegBits16(TOP_1588_NSE_DPLL_6,0xff,0,x)
#define Rd_TOP_1588_NSE_DPLL_6_DPLL_K3(x) ReadRegBits16(TOP_1588_NSE_DPLL_6,0xff,0)
#define TOP_1588_NSE_DPLL_6_DPLL_K3_MASK                           0x00ff
#define TOP_1588_NSE_DPLL_6_DPLL_K3_ALIGN                          0
#define TOP_1588_NSE_DPLL_6_DPLL_K3_BITS                           8
#define TOP_1588_NSE_DPLL_6_DPLL_K3_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_7_0
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_7_0 :: LOOP_FILTER_0 [15:00] */
#define Wr_TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0(x) WriteReg16(TOP_1588_NSE_DPLL_7_0,x)
#define Rd_TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0(x) ReadReg16(TOP_1588_NSE_DPLL_7_0)
#define TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0_MASK                   0xffff
#define TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0_ALIGN                  0
#define TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0_BITS                   16
#define TOP_1588_NSE_DPLL_7_0_LOOP_FILTER_0_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_7_1
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_7_1 :: LOOP_FILTER_1 [15:00] */
#define Wr_TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1(x) WriteReg16(TOP_1588_NSE_DPLL_7_1,x)
#define Rd_TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1(x) ReadReg16(TOP_1588_NSE_DPLL_7_1)
#define TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1_MASK                   0xffff
#define TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1_ALIGN                  0
#define TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1_BITS                   16
#define TOP_1588_NSE_DPLL_7_1_LOOP_FILTER_1_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_7_2
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_7_2 :: LOOP_FILTER_2 [15:00] */
#define Wr_TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2(x) WriteReg16(TOP_1588_NSE_DPLL_7_2,x)
#define Rd_TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2(x) ReadReg16(TOP_1588_NSE_DPLL_7_2)
#define TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2_MASK                   0xffff
#define TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2_ALIGN                  0
#define TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2_BITS                   16
#define TOP_1588_NSE_DPLL_7_2_LOOP_FILTER_2_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: NSE_DPLL_7_3
 ***************************************************************************/
/* TOP_1588 :: NSE_DPLL_7_3 :: LOOP_FILTER_3 [15:00] */
#define Wr_TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3(x) WriteReg16(TOP_1588_NSE_DPLL_7_3,x)
#define Rd_TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3(x) ReadReg16(TOP_1588_NSE_DPLL_7_3)
#define TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3_MASK                   0xffff
#define TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3_ALIGN                  0
#define TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3_BITS                   16
#define TOP_1588_NSE_DPLL_7_3_LOOP_FILTER_3_SHIFT                  0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_1_LSB
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_1_LSB :: NSE_REG_NCO_FREQCNTRL_LSB [15:00] */
#define Wr_TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB(x) WriteReg16(TOP_1588_NSE_NCO_1_LSB,x)
#define Rd_TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB(x) ReadReg16(TOP_1588_NSE_NCO_1_LSB)
#define TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB_MASK      0xffff
#define TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB_ALIGN     0
#define TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB_BITS      16
#define TOP_1588_NSE_NCO_1_LSB_NSE_REG_NCO_FREQCNTRL_LSB_SHIFT     0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_1_MSB
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_1_MSB :: NSE_REG_NCO_FREQCNTRL_MSB [15:00] */
#define Wr_TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB(x) WriteReg16(TOP_1588_NSE_NCO_1_MSB,x)
#define Rd_TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB(x) ReadReg16(TOP_1588_NSE_NCO_1_MSB)
#define TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB_MASK      0xffff
#define TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB_ALIGN     0
#define TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB_BITS      16
#define TOP_1588_NSE_NCO_1_MSB_NSE_REG_NCO_FREQCNTRL_MSB_SHIFT     0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_2_0
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_2_0 :: LOCAL_TIME_UP_0 [15:00] */
#define Wr_TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0(x) WriteReg16(TOP_1588_NSE_NCO_2_0,x)
#define Rd_TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0(x) ReadReg16(TOP_1588_NSE_NCO_2_0)
#define TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0_MASK                  0xffff
#define TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0_ALIGN                 0
#define TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0_BITS                  16
#define TOP_1588_NSE_NCO_2_0_LOCAL_TIME_UP_0_SHIFT                 0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_2_1
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_2_1 :: LOCAL_TIME_UP_1 [15:00] */
#define Wr_TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1(x) WriteReg16(TOP_1588_NSE_NCO_2_1,x)
#define Rd_TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1(x) ReadReg16(TOP_1588_NSE_NCO_2_1)
#define TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1_MASK                  0xffff
#define TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1_ALIGN                 0
#define TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1_BITS                  16
#define TOP_1588_NSE_NCO_2_1_LOCAL_TIME_UP_1_SHIFT                 0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_2_2
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_2_2 :: SPARE_REG2 [15:15] */
#define Wr_TOP_1588_NSE_NCO_2_2_SPARE_REG2(x) WriteRegBits16(TOP_1588_NSE_NCO_2_2,0x8000,15,x)
#define Rd_TOP_1588_NSE_NCO_2_2_SPARE_REG2(x) ReadRegBits16(TOP_1588_NSE_NCO_2_2,0x8000,15)
#define TOP_1588_NSE_NCO_2_2_SPARE_REG2_MASK                       0x8000
#define TOP_1588_NSE_NCO_2_2_SPARE_REG2_ALIGN                      0
#define TOP_1588_NSE_NCO_2_2_SPARE_REG2_BITS                       1
#define TOP_1588_NSE_NCO_2_2_SPARE_REG2_SHIFT                      15

/* TOP_1588 :: NSE_NCO_2_2 :: FREQ_MDIO_SEL [14:14] */
#define Wr_TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL(x) WriteRegBits16(TOP_1588_NSE_NCO_2_2,0x4000,14,x)
#define Rd_TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL(x) ReadRegBits16(TOP_1588_NSE_NCO_2_2,0x4000,14)
#define TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL_MASK                    0x4000
#define TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL_ALIGN                   0
#define TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL_BITS                    1
#define TOP_1588_NSE_NCO_2_2_FREQ_MDIO_SEL_SHIFT                   14

/* TOP_1588 :: NSE_NCO_2_2 :: SPARE_REG1 [13:12] */
#define Wr_TOP_1588_NSE_NCO_2_2_SPARE_REG1(x) WriteRegBits16(TOP_1588_NSE_NCO_2_2,0x3000,12,x)
#define Rd_TOP_1588_NSE_NCO_2_2_SPARE_REG1(x) ReadRegBits16(TOP_1588_NSE_NCO_2_2,0x3000,12)
#define TOP_1588_NSE_NCO_2_2_SPARE_REG1_MASK                       0x3000
#define TOP_1588_NSE_NCO_2_2_SPARE_REG1_ALIGN                      0
#define TOP_1588_NSE_NCO_2_2_SPARE_REG1_BITS                       2
#define TOP_1588_NSE_NCO_2_2_SPARE_REG1_SHIFT                      12

/* TOP_1588 :: NSE_NCO_2_2 :: LOCAL_TIME_UP_2 [11:00] */
#define Wr_TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2(x) WriteRegBits16(TOP_1588_NSE_NCO_2_2,0xfff,0,x)
#define Rd_TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2(x) ReadRegBits16(TOP_1588_NSE_NCO_2_2,0xfff,0)
#define TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2_MASK                  0x0fff
#define TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2_ALIGN                 0
#define TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2_BITS                  12
#define TOP_1588_NSE_NCO_2_2_LOCAL_TIME_UP_2_SHIFT                 0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_3_0
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_3_0 :: INTERVAL_LENGTH_0 [15:00] */
#define Wr_TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0(x) WriteReg16(TOP_1588_NSE_NCO_3_0,x)
#define Rd_TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0(x) ReadReg16(TOP_1588_NSE_NCO_3_0)
#define TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0_MASK                0xffff
#define TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0_ALIGN               0
#define TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0_BITS                16
#define TOP_1588_NSE_NCO_3_0_INTERVAL_LENGTH_0_SHIFT               0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_3_1
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_3_1 :: PULSE_TRAIN_LENGTH_0 [15:14] */
#define Wr_TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0(x) WriteRegBits16(TOP_1588_NSE_NCO_3_1,0xc000,14,x)
#define Rd_TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0(x) ReadRegBits16(TOP_1588_NSE_NCO_3_1,0xc000,14)
#define TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0_MASK             0xc000
#define TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0_ALIGN            0
#define TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0_BITS             2
#define TOP_1588_NSE_NCO_3_1_PULSE_TRAIN_LENGTH_0_SHIFT            14

/* TOP_1588 :: NSE_NCO_3_1 :: INTERVAL_LENGTH_1 [13:00] */
#define Wr_TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1(x) WriteRegBits16(TOP_1588_NSE_NCO_3_1,0x3fff,0,x)
#define Rd_TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1(x) ReadRegBits16(TOP_1588_NSE_NCO_3_1,0x3fff,0)
#define TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1_MASK                0x3fff
#define TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1_ALIGN               0
#define TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1_BITS                14
#define TOP_1588_NSE_NCO_3_1_INTERVAL_LENGTH_1_SHIFT               0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_3_2
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_3_2 :: FRMSYNC_PULSE_LENGTH [15:07] */
#define Wr_TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH(x) WriteRegBits16(TOP_1588_NSE_NCO_3_2,0xff80,7,x)
#define Rd_TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH(x) ReadRegBits16(TOP_1588_NSE_NCO_3_2,0xff80,7)
#define TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH_MASK             0xff80
#define TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH_ALIGN            0
#define TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH_BITS             9
#define TOP_1588_NSE_NCO_3_2_FRMSYNC_PULSE_LENGTH_SHIFT            7

/* TOP_1588 :: NSE_NCO_3_2 :: PULSE_TRAIN_LENGTH_1 [06:00] */
#define Wr_TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1(x) WriteRegBits16(TOP_1588_NSE_NCO_3_2,0x7f,0,x)
#define Rd_TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1(x) ReadRegBits16(TOP_1588_NSE_NCO_3_2,0x7f,0)
#define TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1_MASK             0x007f
#define TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1_ALIGN            0
#define TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1_BITS             7
#define TOP_1588_NSE_NCO_3_2_PULSE_TRAIN_LENGTH_1_SHIFT            0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_4
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_4 :: reserved0 [15:12] */
#define TOP_1588_NSE_NCO_4_RESERVED0_MASK                          0xf000
#define TOP_1588_NSE_NCO_4_RESERVED0_ALIGN                         0
#define TOP_1588_NSE_NCO_4_RESERVED0_BITS                          4
#define TOP_1588_NSE_NCO_4_RESERVED0_SHIFT                         12

/* TOP_1588 :: NSE_NCO_4 :: NSE_REG_TS_DIVIDER [11:00] */
#define Wr_TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER(x) WriteRegBits16(TOP_1588_NSE_NCO_4,0xfff,0,x)
#define Rd_TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER(x) ReadRegBits16(TOP_1588_NSE_NCO_4,0xfff,0)
#define TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER_MASK                 0x0fff
#define TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER_ALIGN                0
#define TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER_BITS                 12
#define TOP_1588_NSE_NCO_4_NSE_REG_TS_DIVIDER_SHIFT                0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_5_0
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_5_0 :: SYNOUT_TS_REG_0 [15:04] */
#define Wr_TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0(x) WriteRegBits16(TOP_1588_NSE_NCO_5_0,0xfff0,4,x)
#define Rd_TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0(x) ReadRegBits16(TOP_1588_NSE_NCO_5_0,0xfff0,4)
#define TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0_MASK                  0xfff0
#define TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0_ALIGN                 0
#define TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0_BITS                  12
#define TOP_1588_NSE_NCO_5_0_SYNOUT_TS_REG_0_SHIFT                 4

/* TOP_1588 :: NSE_NCO_5_0 :: SPARE_REG [03:00] */
#define Wr_TOP_1588_NSE_NCO_5_0_SPARE_REG(x) WriteRegBits16(TOP_1588_NSE_NCO_5_0,0xf,0,x)
#define Rd_TOP_1588_NSE_NCO_5_0_SPARE_REG(x) ReadRegBits16(TOP_1588_NSE_NCO_5_0,0xf,0)
#define TOP_1588_NSE_NCO_5_0_SPARE_REG_MASK                        0x000f
#define TOP_1588_NSE_NCO_5_0_SPARE_REG_ALIGN                       0
#define TOP_1588_NSE_NCO_5_0_SPARE_REG_BITS                        4
#define TOP_1588_NSE_NCO_5_0_SPARE_REG_SHIFT                       0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_5_1
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_5_1 :: SYNOUT_TS_REG_1 [15:00] */
#define Wr_TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1(x) WriteReg16(TOP_1588_NSE_NCO_5_1,x)
#define Rd_TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1(x) ReadReg16(TOP_1588_NSE_NCO_5_1)
#define TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1_MASK                  0xffff
#define TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1_ALIGN                 0
#define TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1_BITS                  16
#define TOP_1588_NSE_NCO_5_1_SYNOUT_TS_REG_1_SHIFT                 0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_5_2
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_5_2 :: SYNOUT_TS_REG_2 [15:00] */
#define Wr_TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2(x) WriteReg16(TOP_1588_NSE_NCO_5_2,x)
#define Rd_TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2(x) ReadReg16(TOP_1588_NSE_NCO_5_2)
#define TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2_MASK                  0xffff
#define TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2_ALIGN                 0
#define TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2_BITS                  16
#define TOP_1588_NSE_NCO_5_2_SYNOUT_TS_REG_2_SHIFT                 0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_6
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_6 :: GMODE [15:14] */
#define Wr_TOP_1588_NSE_NCO_6_GMODE(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0xc000,14,x)
#define Rd_TOP_1588_NSE_NCO_6_GMODE(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0xc000,14)
#define TOP_1588_NSE_NCO_6_GMODE_MASK                              0xc000
#define TOP_1588_NSE_NCO_6_GMODE_ALIGN                             0
#define TOP_1588_NSE_NCO_6_GMODE_BITS                              2
#define TOP_1588_NSE_NCO_6_GMODE_SHIFT                             14

/* TOP_1588 :: NSE_NCO_6 :: TS_CAPTURE [13:13] */
#define Wr_TOP_1588_NSE_NCO_6_TS_CAPTURE(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x2000,13,x)
#define Rd_TOP_1588_NSE_NCO_6_TS_CAPTURE(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x2000,13)
#define TOP_1588_NSE_NCO_6_TS_CAPTURE_MASK                         0x2000
#define TOP_1588_NSE_NCO_6_TS_CAPTURE_ALIGN                        0
#define TOP_1588_NSE_NCO_6_TS_CAPTURE_BITS                         1
#define TOP_1588_NSE_NCO_6_TS_CAPTURE_SHIFT                        13

/* TOP_1588 :: NSE_NCO_6 :: NSE_INIT [12:12] */
#define Wr_TOP_1588_NSE_NCO_6_NSE_INIT(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x1000,12,x)
#define Rd_TOP_1588_NSE_NCO_6_NSE_INIT(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x1000,12)
#define TOP_1588_NSE_NCO_6_NSE_INIT_MASK                           0x1000
#define TOP_1588_NSE_NCO_6_NSE_INIT_ALIGN                          0
#define TOP_1588_NSE_NCO_6_NSE_INIT_BITS                           1
#define TOP_1588_NSE_NCO_6_NSE_INIT_SHIFT                          12

/* TOP_1588 :: NSE_NCO_6 :: M34_LOCAL_SYNC_DIS [11:11] */
#define Wr_TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x800,11,x)
#define Rd_TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x800,11)
#define TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS_MASK                 0x0800
#define TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS_ALIGN                0
#define TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS_BITS                 1
#define TOP_1588_NSE_NCO_6_M34_LOCAL_SYNC_DIS_SHIFT                11

/* TOP_1588 :: NSE_NCO_6 :: SPARE_REG1 [10:10] */
#define Wr_TOP_1588_NSE_NCO_6_SPARE_REG1(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x400,10,x)
#define Rd_TOP_1588_NSE_NCO_6_SPARE_REG1(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x400,10)
#define TOP_1588_NSE_NCO_6_SPARE_REG1_MASK                         0x0400
#define TOP_1588_NSE_NCO_6_SPARE_REG1_ALIGN                        0
#define TOP_1588_NSE_NCO_6_SPARE_REG1_BITS                         1
#define TOP_1588_NSE_NCO_6_SPARE_REG1_SHIFT                        10

/* TOP_1588 :: NSE_NCO_6 :: RESET_LOCK_STATE [09:09] */
#define Wr_TOP_1588_NSE_NCO_6_RESET_LOCK_STATE(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x200,9,x)
#define Rd_TOP_1588_NSE_NCO_6_RESET_LOCK_STATE(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x200,9)
#define TOP_1588_NSE_NCO_6_RESET_LOCK_STATE_MASK                   0x0200
#define TOP_1588_NSE_NCO_6_RESET_LOCK_STATE_ALIGN                  0
#define TOP_1588_NSE_NCO_6_RESET_LOCK_STATE_BITS                   1
#define TOP_1588_NSE_NCO_6_RESET_LOCK_STATE_SHIFT                  9

/* TOP_1588 :: NSE_NCO_6 :: RESET_SYNCIN_STATE [08:08] */
#define Wr_TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x100,8,x)
#define Rd_TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x100,8)
#define TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE_MASK                 0x0100
#define TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE_ALIGN                0
#define TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE_BITS                 1
#define TOP_1588_NSE_NCO_6_RESET_SYNCIN_STATE_SHIFT                8

/* TOP_1588 :: NSE_NCO_6 :: RESET_SYNC_STATE [07:07] */
#define Wr_TOP_1588_NSE_NCO_6_RESET_SYNC_STATE(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x80,7,x)
#define Rd_TOP_1588_NSE_NCO_6_RESET_SYNC_STATE(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x80,7)
#define TOP_1588_NSE_NCO_6_RESET_SYNC_STATE_MASK                   0x0080
#define TOP_1588_NSE_NCO_6_RESET_SYNC_STATE_ALIGN                  0
#define TOP_1588_NSE_NCO_6_RESET_SYNC_STATE_BITS                   1
#define TOP_1588_NSE_NCO_6_RESET_SYNC_STATE_SHIFT                  7

/* TOP_1588 :: NSE_NCO_6 :: SPARE_REG0 [06:06] */
#define Wr_TOP_1588_NSE_NCO_6_SPARE_REG0(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x40,6,x)
#define Rd_TOP_1588_NSE_NCO_6_SPARE_REG0(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x40,6)
#define TOP_1588_NSE_NCO_6_SPARE_REG0_MASK                         0x0040
#define TOP_1588_NSE_NCO_6_SPARE_REG0_ALIGN                        0
#define TOP_1588_NSE_NCO_6_SPARE_REG0_BITS                         1
#define TOP_1588_NSE_NCO_6_SPARE_REG0_SHIFT                        6

/* TOP_1588 :: NSE_NCO_6 :: FRAMESYN_MODE [05:02] */
#define Wr_TOP_1588_NSE_NCO_6_FRAMESYN_MODE(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x3c,2,x)
#define Rd_TOP_1588_NSE_NCO_6_FRAMESYN_MODE(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x3c,2)
#define TOP_1588_NSE_NCO_6_FRAMESYN_MODE_MASK                      0x003c
#define TOP_1588_NSE_NCO_6_FRAMESYN_MODE_ALIGN                     0
#define TOP_1588_NSE_NCO_6_FRAMESYN_MODE_BITS                      4
#define TOP_1588_NSE_NCO_6_FRAMESYN_MODE_SHIFT                     2

/* TOP_1588 :: NSE_NCO_6 :: SYNOUT_MODE [01:00] */
#define Wr_TOP_1588_NSE_NCO_6_SYNOUT_MODE(x) WriteRegBits16(TOP_1588_NSE_NCO_6,0x3,0,x)
#define Rd_TOP_1588_NSE_NCO_6_SYNOUT_MODE(x) ReadRegBits16(TOP_1588_NSE_NCO_6,0x3,0)
#define TOP_1588_NSE_NCO_6_SYNOUT_MODE_MASK                        0x0003
#define TOP_1588_NSE_NCO_6_SYNOUT_MODE_ALIGN                       0
#define TOP_1588_NSE_NCO_6_SYNOUT_MODE_BITS                        2
#define TOP_1588_NSE_NCO_6_SYNOUT_MODE_SHIFT                       0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_7_0
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_7_0 :: LENGTH_THRESHOLD [15:00] */
#define Wr_TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD(x) WriteReg16(TOP_1588_NSE_NCO_7_0,x)
#define Rd_TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD(x) ReadReg16(TOP_1588_NSE_NCO_7_0)
#define TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD_MASK                 0xffff
#define TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD_ALIGN                0
#define TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD_BITS                 16
#define TOP_1588_NSE_NCO_7_0_LENGTH_THRESHOLD_SHIFT                0


/****************************************************************************
 * TOP_1588 :: NSE_NCO_7_1
 ***************************************************************************/
/* TOP_1588 :: NSE_NCO_7_1 :: EVENT_OFFSET [15:00] */
#define Wr_TOP_1588_NSE_NCO_7_1_EVENT_OFFSET(x) WriteReg16(TOP_1588_NSE_NCO_7_1,x)
#define Rd_TOP_1588_NSE_NCO_7_1_EVENT_OFFSET(x) ReadReg16(TOP_1588_NSE_NCO_7_1)
#define TOP_1588_NSE_NCO_7_1_EVENT_OFFSET_MASK                     0xffff
#define TOP_1588_NSE_NCO_7_1_EVENT_OFFSET_ALIGN                    0
#define TOP_1588_NSE_NCO_7_1_EVENT_OFFSET_BITS                     16
#define TOP_1588_NSE_NCO_7_1_EVENT_OFFSET_SHIFT                    0


/****************************************************************************
 * TOP_1588 :: TX_COUNTER
 ***************************************************************************/
/* TOP_1588 :: TX_COUNTER :: TX_COUNTER [15:00] */
#define Wr_TOP_1588_TX_COUNTER_TX_COUNTER(x) WriteReg16(TOP_1588_TX_COUNTER,x)
#define Rd_TOP_1588_TX_COUNTER_TX_COUNTER(x) ReadReg16(TOP_1588_TX_COUNTER)
#define TOP_1588_TX_COUNTER_TX_COUNTER_MASK                        0xffff
#define TOP_1588_TX_COUNTER_TX_COUNTER_ALIGN                       0
#define TOP_1588_TX_COUNTER_TX_COUNTER_BITS                        16
#define TOP_1588_TX_COUNTER_TX_COUNTER_SHIFT                       0


/****************************************************************************
 * TOP_1588 :: RX_COUNTER
 ***************************************************************************/
/* TOP_1588 :: RX_COUNTER :: RX_COUNTER [15:00] */
#define Wr_TOP_1588_RX_COUNTER_RX_COUNTER(x) WriteReg16(TOP_1588_RX_COUNTER,x)
#define Rd_TOP_1588_RX_COUNTER_RX_COUNTER(x) ReadReg16(TOP_1588_RX_COUNTER)
#define TOP_1588_RX_COUNTER_RX_COUNTER_MASK                        0xffff
#define TOP_1588_RX_COUNTER_RX_COUNTER_ALIGN                       0
#define TOP_1588_RX_COUNTER_RX_COUNTER_BITS                        16
#define TOP_1588_RX_COUNTER_RX_COUNTER_SHIFT                       0


/****************************************************************************
 * TOP_1588 :: RX_TX_1588_COUNTER
 ***************************************************************************/
/* TOP_1588 :: RX_TX_1588_COUNTER :: RX_1588_COUNTER [15:08] */
#define Wr_TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER(x) WriteRegBits16(TOP_1588_RX_TX_1588_COUNTER,0xff00,8,x)
#define Rd_TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER(x) ReadRegBits16(TOP_1588_RX_TX_1588_COUNTER,0xff00,8)
#define TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER_MASK           0xff00
#define TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER_ALIGN          0
#define TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER_BITS           8
#define TOP_1588_RX_TX_1588_COUNTER_RX_1588_COUNTER_SHIFT          8

/* TOP_1588 :: RX_TX_1588_COUNTER :: TX_1588_COUNTER [07:00] */
#define Wr_TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER(x) WriteRegBits16(TOP_1588_RX_TX_1588_COUNTER,0xff,0,x)
#define Rd_TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER(x) ReadRegBits16(TOP_1588_RX_TX_1588_COUNTER,0xff,0)
#define TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER_MASK           0x00ff
#define TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER_ALIGN          0
#define TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER_BITS           8
#define TOP_1588_RX_TX_1588_COUNTER_TX_1588_COUNTER_SHIFT          0


/****************************************************************************
 * TOP_1588 :: TS_READ_START_END
 ***************************************************************************/
/* TOP_1588 :: TS_READ_START_END :: TS [15:00] */
#define Wr_TOP_1588_TS_READ_START_END_TS(x) WriteReg16(TOP_1588_TS_READ_START_END,x)
#define Rd_TOP_1588_TS_READ_START_END_TS(x) ReadReg16(TOP_1588_TS_READ_START_END)
#define TOP_1588_TS_READ_START_END_TS_MASK                         0xffff
#define TOP_1588_TS_READ_START_END_TS_ALIGN                        0
#define TOP_1588_TS_READ_START_END_TS_BITS                         16
#define TOP_1588_TS_READ_START_END_TS_SHIFT                        0


/****************************************************************************
 * TOP_1588 :: HEARTBEAT_0
 ***************************************************************************/
/* TOP_1588 :: HEARTBEAT_0 :: HEARTBEAT_0 [15:00] */
#define Wr_TOP_1588_HEARTBEAT_0_HEARTBEAT_0(x) WriteReg16(TOP_1588_HEARTBEAT_0,x)
#define Rd_TOP_1588_HEARTBEAT_0_HEARTBEAT_0(x) ReadReg16(TOP_1588_HEARTBEAT_0)
#define TOP_1588_HEARTBEAT_0_HEARTBEAT_0_MASK                      0xffff
#define TOP_1588_HEARTBEAT_0_HEARTBEAT_0_ALIGN                     0
#define TOP_1588_HEARTBEAT_0_HEARTBEAT_0_BITS                      16
#define TOP_1588_HEARTBEAT_0_HEARTBEAT_0_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: HEARTBEAT_1
 ***************************************************************************/
/* TOP_1588 :: HEARTBEAT_1 :: HEARTBEAT_1 [15:00] */
#define Wr_TOP_1588_HEARTBEAT_1_HEARTBEAT_1(x) WriteReg16(TOP_1588_HEARTBEAT_1,x)
#define Rd_TOP_1588_HEARTBEAT_1_HEARTBEAT_1(x) ReadReg16(TOP_1588_HEARTBEAT_1)
#define TOP_1588_HEARTBEAT_1_HEARTBEAT_1_MASK                      0xffff
#define TOP_1588_HEARTBEAT_1_HEARTBEAT_1_ALIGN                     0
#define TOP_1588_HEARTBEAT_1_HEARTBEAT_1_BITS                      16
#define TOP_1588_HEARTBEAT_1_HEARTBEAT_1_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: HEARTBEAT_2
 ***************************************************************************/
/* TOP_1588 :: HEARTBEAT_2 :: HEARTBEAT_2 [15:00] */
#define Wr_TOP_1588_HEARTBEAT_2_HEARTBEAT_2(x) WriteReg16(TOP_1588_HEARTBEAT_2,x)
#define Rd_TOP_1588_HEARTBEAT_2_HEARTBEAT_2(x) ReadReg16(TOP_1588_HEARTBEAT_2)
#define TOP_1588_HEARTBEAT_2_HEARTBEAT_2_MASK                      0xffff
#define TOP_1588_HEARTBEAT_2_HEARTBEAT_2_ALIGN                     0
#define TOP_1588_HEARTBEAT_2_HEARTBEAT_2_BITS                      16
#define TOP_1588_HEARTBEAT_2_HEARTBEAT_2_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_0
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_0 :: TIME_STAMP_0 [15:00] */
#define Wr_TOP_1588_TIME_STAMP_0_TIME_STAMP_0(x) WriteReg16(TOP_1588_TIME_STAMP_0,x)
#define Rd_TOP_1588_TIME_STAMP_0_TIME_STAMP_0(x) ReadReg16(TOP_1588_TIME_STAMP_0)
#define TOP_1588_TIME_STAMP_0_TIME_STAMP_0_MASK                    0xffff
#define TOP_1588_TIME_STAMP_0_TIME_STAMP_0_ALIGN                   0
#define TOP_1588_TIME_STAMP_0_TIME_STAMP_0_BITS                    16
#define TOP_1588_TIME_STAMP_0_TIME_STAMP_0_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_1
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_1 :: TIME_STAMP_1 [15:00] */
#define Wr_TOP_1588_TIME_STAMP_1_TIME_STAMP_1(x) WriteReg16(TOP_1588_TIME_STAMP_1,x)
#define Rd_TOP_1588_TIME_STAMP_1_TIME_STAMP_1(x) ReadReg16(TOP_1588_TIME_STAMP_1)
#define TOP_1588_TIME_STAMP_1_TIME_STAMP_1_MASK                    0xffff
#define TOP_1588_TIME_STAMP_1_TIME_STAMP_1_ALIGN                   0
#define TOP_1588_TIME_STAMP_1_TIME_STAMP_1_BITS                    16
#define TOP_1588_TIME_STAMP_1_TIME_STAMP_1_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_2
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_2 :: TIME_STAMP_2 [15:00] */
#define Wr_TOP_1588_TIME_STAMP_2_TIME_STAMP_2(x) WriteReg16(TOP_1588_TIME_STAMP_2,x)
#define Rd_TOP_1588_TIME_STAMP_2_TIME_STAMP_2(x) ReadReg16(TOP_1588_TIME_STAMP_2)
#define TOP_1588_TIME_STAMP_2_TIME_STAMP_2_MASK                    0xffff
#define TOP_1588_TIME_STAMP_2_TIME_STAMP_2_ALIGN                   0
#define TOP_1588_TIME_STAMP_2_TIME_STAMP_2_BITS                    16
#define TOP_1588_TIME_STAMP_2_TIME_STAMP_2_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_INFO_1
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_INFO_1 :: TIME_STAMP_INFO [15:00] */
#define Wr_TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO(x) WriteReg16(TOP_1588_TIME_STAMP_INFO_1,x)
#define Rd_TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO(x) ReadReg16(TOP_1588_TIME_STAMP_INFO_1)
#define TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO_MASK            0xffff
#define TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO_ALIGN           0
#define TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO_BITS            16
#define TOP_1588_TIME_STAMP_INFO_1_TIME_STAMP_INFO_SHIFT           0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_INFO_2
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_INFO_2 :: TIME_STAMP_INFO [15:00] */
#define Wr_TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO(x) WriteReg16(TOP_1588_TIME_STAMP_INFO_2,x)
#define Rd_TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO(x) ReadReg16(TOP_1588_TIME_STAMP_INFO_2)
#define TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO_MASK            0xffff
#define TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO_ALIGN           0
#define TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO_BITS            16
#define TOP_1588_TIME_STAMP_INFO_2_TIME_STAMP_INFO_SHIFT           0


/****************************************************************************
 * TOP_1588 :: CNTR_DBG
 ***************************************************************************/
/* TOP_1588 :: CNTR_DBG :: SPARE_REG [15:14] */
#define Wr_TOP_1588_CNTR_DBG_SPARE_REG(x) WriteRegBits16(TOP_1588_CNTR_DBG,0xc000,14,x)
#define Rd_TOP_1588_CNTR_DBG_SPARE_REG(x) ReadRegBits16(TOP_1588_CNTR_DBG,0xc000,14)
#define TOP_1588_CNTR_DBG_SPARE_REG_MASK                           0xc000
#define TOP_1588_CNTR_DBG_SPARE_REG_ALIGN                          0
#define TOP_1588_CNTR_DBG_SPARE_REG_BITS                           2
#define TOP_1588_CNTR_DBG_SPARE_REG_SHIFT                          14

/* TOP_1588 :: CNTR_DBG :: TC_64_LEAP [13:12] */
#define Wr_TOP_1588_CNTR_DBG_TC_64_LEAP(x) WriteRegBits16(TOP_1588_CNTR_DBG,0x3000,12,x)
#define Rd_TOP_1588_CNTR_DBG_TC_64_LEAP(x) ReadRegBits16(TOP_1588_CNTR_DBG,0x3000,12)
#define TOP_1588_CNTR_DBG_TC_64_LEAP_MASK                          0x3000
#define TOP_1588_CNTR_DBG_TC_64_LEAP_ALIGN                         0
#define TOP_1588_CNTR_DBG_TC_64_LEAP_BITS                          2
#define TOP_1588_CNTR_DBG_TC_64_LEAP_SHIFT                         12

/* TOP_1588 :: CNTR_DBG :: HB_CNTL [11:10] */
#define Wr_TOP_1588_CNTR_DBG_HB_CNTL(x) WriteRegBits16(TOP_1588_CNTR_DBG,0xc00,10,x)
#define Rd_TOP_1588_CNTR_DBG_HB_CNTL(x) ReadRegBits16(TOP_1588_CNTR_DBG,0xc00,10)
#define TOP_1588_CNTR_DBG_HB_CNTL_MASK                             0x0c00
#define TOP_1588_CNTR_DBG_HB_CNTL_ALIGN                            0
#define TOP_1588_CNTR_DBG_HB_CNTL_BITS                             2
#define TOP_1588_CNTR_DBG_HB_CNTL_SHIFT                            10

/* TOP_1588 :: CNTR_DBG :: TS_SLICE_SEL [09:07] */
#define Wr_TOP_1588_CNTR_DBG_TS_SLICE_SEL(x) WriteRegBits16(TOP_1588_CNTR_DBG,0x380,7,x)
#define Rd_TOP_1588_CNTR_DBG_TS_SLICE_SEL(x) ReadRegBits16(TOP_1588_CNTR_DBG,0x380,7)
#define TOP_1588_CNTR_DBG_TS_SLICE_SEL_MASK                        0x0380
#define TOP_1588_CNTR_DBG_TS_SLICE_SEL_ALIGN                       0
#define TOP_1588_CNTR_DBG_TS_SLICE_SEL_BITS                        3
#define TOP_1588_CNTR_DBG_TS_SLICE_SEL_SHIFT                       7

/* TOP_1588 :: CNTR_DBG :: TC_80_LEAP [06:05] */
#define Wr_TOP_1588_CNTR_DBG_TC_80_LEAP(x) WriteRegBits16(TOP_1588_CNTR_DBG,0x60,5,x)
#define Rd_TOP_1588_CNTR_DBG_TC_80_LEAP(x) ReadRegBits16(TOP_1588_CNTR_DBG,0x60,5)
#define TOP_1588_CNTR_DBG_TC_80_LEAP_MASK                          0x0060
#define TOP_1588_CNTR_DBG_TC_80_LEAP_ALIGN                         0
#define TOP_1588_CNTR_DBG_TC_80_LEAP_BITS                          2
#define TOP_1588_CNTR_DBG_TC_80_LEAP_SHIFT                         5

/* TOP_1588 :: CNTR_DBG :: CNTR_SLICE_SEL [04:02] */
#define Wr_TOP_1588_CNTR_DBG_CNTR_SLICE_SEL(x) WriteRegBits16(TOP_1588_CNTR_DBG,0x1c,2,x)
#define Rd_TOP_1588_CNTR_DBG_CNTR_SLICE_SEL(x) ReadRegBits16(TOP_1588_CNTR_DBG,0x1c,2)
#define TOP_1588_CNTR_DBG_CNTR_SLICE_SEL_MASK                      0x001c
#define TOP_1588_CNTR_DBG_CNTR_SLICE_SEL_ALIGN                     0
#define TOP_1588_CNTR_DBG_CNTR_SLICE_SEL_BITS                      3
#define TOP_1588_CNTR_DBG_CNTR_SLICE_SEL_SHIFT                     2

/* TOP_1588 :: CNTR_DBG :: RST_RX_CNTR [01:01] */
#define Wr_TOP_1588_CNTR_DBG_RST_RX_CNTR(x) WriteRegBits16(TOP_1588_CNTR_DBG,0x2,1,x)
#define Rd_TOP_1588_CNTR_DBG_RST_RX_CNTR(x) ReadRegBits16(TOP_1588_CNTR_DBG,0x2,1)
#define TOP_1588_CNTR_DBG_RST_RX_CNTR_MASK                         0x0002
#define TOP_1588_CNTR_DBG_RST_RX_CNTR_ALIGN                        0
#define TOP_1588_CNTR_DBG_RST_RX_CNTR_BITS                         1
#define TOP_1588_CNTR_DBG_RST_RX_CNTR_SHIFT                        1

/* TOP_1588 :: CNTR_DBG :: RST_TX_CNTR [00:00] */
#define Wr_TOP_1588_CNTR_DBG_RST_TX_CNTR(x) WriteRegBits16(TOP_1588_CNTR_DBG,0x1,0,x)
#define Rd_TOP_1588_CNTR_DBG_RST_TX_CNTR(x) ReadRegBits16(TOP_1588_CNTR_DBG,0x1,0)
#define TOP_1588_CNTR_DBG_RST_TX_CNTR_MASK                         0x0001
#define TOP_1588_CNTR_DBG_RST_TX_CNTR_ALIGN                        0
#define TOP_1588_CNTR_DBG_RST_TX_CNTR_BITS                         1
#define TOP_1588_CNTR_DBG_RST_TX_CNTR_SHIFT                        0


/****************************************************************************
 * TOP_1588 :: MPLS_SPARE1
 ***************************************************************************/
/* TOP_1588 :: MPLS_SPARE1 :: CPU_MODE_PORT_ENABLE [15:00] */
#define Wr_TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE(x) WriteReg16(TOP_1588_MPLS_SPARE1,x)
#define Rd_TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE(x) ReadReg16(TOP_1588_MPLS_SPARE1)
#define TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE_MASK             0xffff
#define TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE_ALIGN            0
#define TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE_BITS             16
#define TOP_1588_MPLS_SPARE1_CPU_MODE_PORT_ENABLE_SHIFT            0


/****************************************************************************
 * TOP_1588 :: MPLS_SPARE2
 ***************************************************************************/
/* TOP_1588 :: MPLS_SPARE2 :: CPU_DA1 [15:00] */
#define Wr_TOP_1588_MPLS_SPARE2_CPU_DA1(x) WriteReg16(TOP_1588_MPLS_SPARE2,x)
#define Rd_TOP_1588_MPLS_SPARE2_CPU_DA1(x) ReadReg16(TOP_1588_MPLS_SPARE2)
#define TOP_1588_MPLS_SPARE2_CPU_DA1_MASK                          0xffff
#define TOP_1588_MPLS_SPARE2_CPU_DA1_ALIGN                         0
#define TOP_1588_MPLS_SPARE2_CPU_DA1_BITS                          16
#define TOP_1588_MPLS_SPARE2_CPU_DA1_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: MPLS_SPARE3
 ***************************************************************************/
/* TOP_1588 :: MPLS_SPARE3 :: CPU_DA2 [15:00] */
#define Wr_TOP_1588_MPLS_SPARE3_CPU_DA2(x) WriteReg16(TOP_1588_MPLS_SPARE3,x)
#define Rd_TOP_1588_MPLS_SPARE3_CPU_DA2(x) ReadReg16(TOP_1588_MPLS_SPARE3)
#define TOP_1588_MPLS_SPARE3_CPU_DA2_MASK                          0xffff
#define TOP_1588_MPLS_SPARE3_CPU_DA2_ALIGN                         0
#define TOP_1588_MPLS_SPARE3_CPU_DA2_BITS                          16
#define TOP_1588_MPLS_SPARE3_CPU_DA2_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: MPLS_SPARE4
 ***************************************************************************/
/* TOP_1588 :: MPLS_SPARE4 :: CPU_DA3 [15:00] */
#define Wr_TOP_1588_MPLS_SPARE4_CPU_DA3(x) WriteReg16(TOP_1588_MPLS_SPARE4,x)
#define Rd_TOP_1588_MPLS_SPARE4_CPU_DA3(x) ReadReg16(TOP_1588_MPLS_SPARE4)
#define TOP_1588_MPLS_SPARE4_CPU_DA3_MASK                          0xffff
#define TOP_1588_MPLS_SPARE4_CPU_DA3_ALIGN                         0
#define TOP_1588_MPLS_SPARE4_CPU_DA3_BITS                          16
#define TOP_1588_MPLS_SPARE4_CPU_DA3_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: MPLS_SPARE5
 ***************************************************************************/
/* TOP_1588 :: MPLS_SPARE5 :: MPLS_SPEC_LABEL1 [15:00] */
#define Wr_TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1(x) WriteReg16(TOP_1588_MPLS_SPARE5,x)
#define Rd_TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1(x) ReadReg16(TOP_1588_MPLS_SPARE5)
#define TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1_MASK                 0xffff
#define TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1_ALIGN                0
#define TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1_BITS                 16
#define TOP_1588_MPLS_SPARE5_MPLS_SPEC_LABEL1_SHIFT                0


/****************************************************************************
 * TOP_1588 :: MPLS_SPARE6
 ***************************************************************************/
/* TOP_1588 :: MPLS_SPARE6 :: MPLS_SPEC_LABEL2 [15:00] */
#define Wr_TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2(x) WriteReg16(TOP_1588_MPLS_SPARE6,x)
#define Rd_TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2(x) ReadReg16(TOP_1588_MPLS_SPARE6)
#define TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2_MASK                 0xffff
#define TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2_ALIGN                0
#define TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2_BITS                 16
#define TOP_1588_MPLS_SPARE6_MPLS_SPEC_LABEL2_SHIFT                0


/****************************************************************************
 * TOP_1588 :: MPLS_TX_CNTL
 ***************************************************************************/
/* TOP_1588 :: MPLS_TX_CNTL :: MPLS_CNTL [15:00] */
#define Wr_TOP_1588_MPLS_TX_CNTL_MPLS_CNTL(x) WriteReg16(TOP_1588_MPLS_TX_CNTL,x)
#define Rd_TOP_1588_MPLS_TX_CNTL_MPLS_CNTL(x) ReadReg16(TOP_1588_MPLS_TX_CNTL)
#define TOP_1588_MPLS_TX_CNTL_MPLS_CNTL_MASK                       0xffff
#define TOP_1588_MPLS_TX_CNTL_MPLS_CNTL_ALIGN                      0
#define TOP_1588_MPLS_TX_CNTL_MPLS_CNTL_BITS                       16
#define TOP_1588_MPLS_TX_CNTL_MPLS_CNTL_SHIFT                      0


/****************************************************************************
 * TOP_1588 :: MPLS_RX_CNTL
 ***************************************************************************/
/* TOP_1588 :: MPLS_RX_CNTL :: MPLS_CNTL [15:00] */
#define Wr_TOP_1588_MPLS_RX_CNTL_MPLS_CNTL(x) WriteReg16(TOP_1588_MPLS_RX_CNTL,x)
#define Rd_TOP_1588_MPLS_RX_CNTL_MPLS_CNTL(x) ReadReg16(TOP_1588_MPLS_RX_CNTL)
#define TOP_1588_MPLS_RX_CNTL_MPLS_CNTL_MASK                       0xffff
#define TOP_1588_MPLS_RX_CNTL_MPLS_CNTL_ALIGN                      0
#define TOP_1588_MPLS_RX_CNTL_MPLS_CNTL_BITS                       16
#define TOP_1588_MPLS_RX_CNTL_MPLS_CNTL_SHIFT                      0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL1_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL1_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL1_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL1_LSB_MASK)
#define TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK     0xffff
#define TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS     16
#define TOP_1588_MPLS_LABEL1_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL1_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL1_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL1_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL1_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK    0xfff0
#define TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN   0
#define TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS    12
#define TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT   4

/* TOP_1588 :: MPLS_LABEL1_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL1_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL1_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK     0x000f
#define TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS     4
#define TOP_1588_MPLS_LABEL1_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL1_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL1_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL1_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL1_LSB_VALUE)
#define TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK   0xffff
#define TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS   16
#define TOP_1588_MPLS_LABEL1_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL1_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL1_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL1_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL1_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL1_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL1_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL1_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK   0x000f
#define TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS   4
#define TOP_1588_MPLS_LABEL1_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL2_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL2_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL2_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL2_LSB_MASK)
#define TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK     0xffff
#define TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS     16
#define TOP_1588_MPLS_LABEL2_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL2_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL2_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL2_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL2_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK    0xfff0
#define TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN   0
#define TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS    12
#define TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT   4

/* TOP_1588 :: MPLS_LABEL2_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL2_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL2_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK     0x000f
#define TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS     4
#define TOP_1588_MPLS_LABEL2_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL2_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL2_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL2_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL2_LSB_VALUE)
#define TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK   0xffff
#define TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS   16
#define TOP_1588_MPLS_LABEL2_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL2_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL2_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL2_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL2_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL2_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL2_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL2_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK   0x000f
#define TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS   4
#define TOP_1588_MPLS_LABEL2_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL3_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL3_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL3_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL3_LSB_MASK)
#define TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK     0xffff
#define TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS     16
#define TOP_1588_MPLS_LABEL3_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL3_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL3_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL3_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL3_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK    0xfff0
#define TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN   0
#define TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS    12
#define TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT   4

/* TOP_1588 :: MPLS_LABEL3_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL3_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL3_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK     0x000f
#define TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS     4
#define TOP_1588_MPLS_LABEL3_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL3_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL3_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL3_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL3_LSB_VALUE)
#define TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK   0xffff
#define TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS   16
#define TOP_1588_MPLS_LABEL3_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL3_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL3_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL3_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL3_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL3_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL3_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL3_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK   0x000f
#define TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS   4
#define TOP_1588_MPLS_LABEL3_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL4_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL4_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL4_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL4_LSB_MASK)
#define TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK     0xffff
#define TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS     16
#define TOP_1588_MPLS_LABEL4_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL4_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL4_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL4_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL4_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK    0xfff0
#define TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN   0
#define TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS    12
#define TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT   4

/* TOP_1588 :: MPLS_LABEL4_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL4_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL4_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK     0x000f
#define TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS     4
#define TOP_1588_MPLS_LABEL4_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL4_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL4_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL4_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL4_LSB_VALUE)
#define TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK   0xffff
#define TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS   16
#define TOP_1588_MPLS_LABEL4_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL4_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL4_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL4_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL4_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL4_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL4_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL4_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK   0x000f
#define TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS   4
#define TOP_1588_MPLS_LABEL4_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL5_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL5_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL5_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL5_LSB_MASK)
#define TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK     0xffff
#define TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS     16
#define TOP_1588_MPLS_LABEL5_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL5_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL5_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL5_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL5_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK    0xfff0
#define TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN   0
#define TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS    12
#define TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT   4

/* TOP_1588 :: MPLS_LABEL5_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL5_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL5_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK     0x000f
#define TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS     4
#define TOP_1588_MPLS_LABEL5_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL5_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL5_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL5_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL5_LSB_VALUE)
#define TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK   0xffff
#define TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS   16
#define TOP_1588_MPLS_LABEL5_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL5_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL5_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL5_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL5_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL5_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL5_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL5_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK   0x000f
#define TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS   4
#define TOP_1588_MPLS_LABEL5_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL6_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL6_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL6_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL6_LSB_MASK)
#define TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK     0xffff
#define TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS     16
#define TOP_1588_MPLS_LABEL6_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL6_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL6_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL6_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL6_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK    0xfff0
#define TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN   0
#define TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS    12
#define TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT   4

/* TOP_1588 :: MPLS_LABEL6_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL6_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL6_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK     0x000f
#define TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS     4
#define TOP_1588_MPLS_LABEL6_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL6_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL6_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL6_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL6_LSB_VALUE)
#define TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK   0xffff
#define TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS   16
#define TOP_1588_MPLS_LABEL6_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL6_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL6_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL6_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL6_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL6_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL6_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL6_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK   0x000f
#define TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS   4
#define TOP_1588_MPLS_LABEL6_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL7_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL7_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL7_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL7_LSB_MASK)
#define TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK     0xffff
#define TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS     16
#define TOP_1588_MPLS_LABEL7_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL7_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL7_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL7_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL7_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK    0xfff0
#define TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN   0
#define TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS    12
#define TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT   4

/* TOP_1588 :: MPLS_LABEL7_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL7_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL7_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK     0x000f
#define TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS     4
#define TOP_1588_MPLS_LABEL7_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL7_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL7_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL7_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL7_LSB_VALUE)
#define TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK   0xffff
#define TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS   16
#define TOP_1588_MPLS_LABEL7_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL7_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL7_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL7_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL7_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL7_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL7_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL7_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK   0x000f
#define TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS   4
#define TOP_1588_MPLS_LABEL7_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL8_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL8_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL8_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL8_LSB_MASK)
#define TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK     0xffff
#define TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS     16
#define TOP_1588_MPLS_LABEL8_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL8_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL8_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL8_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL8_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK    0xfff0
#define TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN   0
#define TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS    12
#define TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT   4

/* TOP_1588 :: MPLS_LABEL8_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL8_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL8_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK     0x000f
#define TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS     4
#define TOP_1588_MPLS_LABEL8_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL8_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL8_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL8_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL8_LSB_VALUE)
#define TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK   0xffff
#define TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS   16
#define TOP_1588_MPLS_LABEL8_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL8_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL8_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL8_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL8_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL8_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL8_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL8_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK   0x000f
#define TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS   4
#define TOP_1588_MPLS_LABEL8_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL9_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL9_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL9_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL9_LSB_MASK)
#define TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK     0xffff
#define TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS     16
#define TOP_1588_MPLS_LABEL9_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL9_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL9_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL9_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL9_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK    0xfff0
#define TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN   0
#define TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS    12
#define TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT   4

/* TOP_1588 :: MPLS_LABEL9_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL9_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL9_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK     0x000f
#define TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN    0
#define TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS     4
#define TOP_1588_MPLS_LABEL9_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT    0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL9_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL9_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL9_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL9_LSB_VALUE)
#define TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK   0xffff
#define TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS   16
#define TOP_1588_MPLS_LABEL9_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL9_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL9_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL9_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL9_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL9_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL9_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL9_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK   0x000f
#define TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN  0
#define TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS   4
#define TOP_1588_MPLS_LABEL9_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT  0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL10_LSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL10_LSB_MASK :: MPLS_LABEL_LSB_MASK [15:00] */
#define Wr_TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK(x) WriteReg16(TOP_1588_MPLS_LABEL10_LSB_MASK,x)
#define Rd_TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK(x) ReadReg16(TOP_1588_MPLS_LABEL10_LSB_MASK)
#define TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK_MASK    0xffff
#define TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK_ALIGN   0
#define TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK_BITS    16
#define TOP_1588_MPLS_LABEL10_LSB_MASK_MPLS_LABEL_LSB_MASK_SHIFT   0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL10_MSB_MASK
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL10_MSB_MASK :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL10_MSB_MASK,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL10_MSB_MASK,0xfff0,4)
#define TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE_MASK   0xfff0
#define TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE_ALIGN  0
#define TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE_BITS   12
#define TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_SPARE_SHIFT  4

/* TOP_1588 :: MPLS_LABEL10_MSB_MASK :: MPLS_LABEL_MSB_MASK [03:00] */
#define Wr_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK(x) WriteRegBits16(TOP_1588_MPLS_LABEL10_MSB_MASK,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK(x) ReadRegBits16(TOP_1588_MPLS_LABEL10_MSB_MASK,0xf,0)
#define TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK_MASK    0x000f
#define TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK_ALIGN   0
#define TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK_BITS    4
#define TOP_1588_MPLS_LABEL10_MSB_MASK_MPLS_LABEL_MSB_MASK_SHIFT   0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL10_LSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL10_LSB_VALUE :: MPLS_LABEL_LSB_VALUE [15:00] */
#define Wr_TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) WriteReg16(TOP_1588_MPLS_LABEL10_LSB_VALUE,x)
#define Rd_TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE(x) ReadReg16(TOP_1588_MPLS_LABEL10_LSB_VALUE)
#define TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE_MASK  0xffff
#define TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE_ALIGN 0
#define TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE_BITS  16
#define TOP_1588_MPLS_LABEL10_LSB_VALUE_MPLS_LABEL_LSB_VALUE_SHIFT 0


/****************************************************************************
 * TOP_1588 :: MPLS_LABEL10_MSB_VALUE
 ***************************************************************************/
/* TOP_1588 :: MPLS_LABEL10_MSB_VALUE :: MPLS_LABEL_MSB_SPARE [15:04] */
#define Wr_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) WriteRegBits16(TOP_1588_MPLS_LABEL10_MSB_VALUE,0xfff0,4,x)
#define Rd_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE(x) ReadRegBits16(TOP_1588_MPLS_LABEL10_MSB_VALUE,0xfff0,4)
#define TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE_MASK  0xfff0
#define TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE_ALIGN 0
#define TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE_BITS  12
#define TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_SPARE_SHIFT 4

/* TOP_1588 :: MPLS_LABEL10_MSB_VALUE :: MPLS_LABEL_MSB_VALUE [03:00] */
#define Wr_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) WriteRegBits16(TOP_1588_MPLS_LABEL10_MSB_VALUE,0xf,0,x)
#define Rd_TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE(x) ReadRegBits16(TOP_1588_MPLS_LABEL10_MSB_VALUE,0xf,0)
#define TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE_MASK  0x000f
#define TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE_ALIGN 0
#define TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE_BITS  4
#define TOP_1588_MPLS_LABEL10_MSB_VALUE_MPLS_LABEL_MSB_VALUE_SHIFT 0


/****************************************************************************
 * TOP_1588 :: RX_TX_1588_COUNTER1
 ***************************************************************************/
/* TOP_1588 :: RX_TX_1588_COUNTER1 :: RX_1588_COUNTER1 [15:08] */
#define Wr_TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1(x) WriteRegBits16(TOP_1588_RX_TX_1588_COUNTER1,0xff00,8,x)
#define Rd_TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1(x) ReadRegBits16(TOP_1588_RX_TX_1588_COUNTER1,0xff00,8)
#define TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1_MASK         0xff00
#define TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1_ALIGN        0
#define TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1_BITS         8
#define TOP_1588_RX_TX_1588_COUNTER1_RX_1588_COUNTER1_SHIFT        8

/* TOP_1588 :: RX_TX_1588_COUNTER1 :: TX_1588_COUNTER1 [07:00] */
#define Wr_TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1(x) WriteRegBits16(TOP_1588_RX_TX_1588_COUNTER1,0xff,0,x)
#define Rd_TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1(x) ReadRegBits16(TOP_1588_RX_TX_1588_COUNTER1,0xff,0)
#define TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1_MASK         0x00ff
#define TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1_ALIGN        0
#define TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1_BITS         8
#define TOP_1588_RX_TX_1588_COUNTER1_TX_1588_COUNTER1_SHIFT        0


/****************************************************************************
 * TOP_1588 :: RX_CF_SPEC
 ***************************************************************************/
/* TOP_1588 :: RX_CF_SPEC :: RX_CF_SPEC [15:00] */
#define Wr_TOP_1588_RX_CF_SPEC_RX_CF_SPEC(x) WriteReg16(TOP_1588_RX_CF_SPEC,x)
#define Rd_TOP_1588_RX_CF_SPEC_RX_CF_SPEC(x) ReadReg16(TOP_1588_RX_CF_SPEC)
#define TOP_1588_RX_CF_SPEC_RX_CF_SPEC_MASK                        0xffff
#define TOP_1588_RX_CF_SPEC_RX_CF_SPEC_ALIGN                       0
#define TOP_1588_RX_CF_SPEC_RX_CF_SPEC_BITS                        16
#define TOP_1588_RX_CF_SPEC_RX_CF_SPEC_SHIFT                       0


/****************************************************************************
 * TOP_1588 :: TX_CF_SPEC
 ***************************************************************************/
/* TOP_1588 :: TX_CF_SPEC :: TX_CF_SPEC [15:00] */
#define Wr_TOP_1588_TX_CF_SPEC_TX_CF_SPEC(x) WriteReg16(TOP_1588_TX_CF_SPEC,x)
#define Rd_TOP_1588_TX_CF_SPEC_TX_CF_SPEC(x) ReadReg16(TOP_1588_TX_CF_SPEC)
#define TOP_1588_TX_CF_SPEC_TX_CF_SPEC_MASK                        0xffff
#define TOP_1588_TX_CF_SPEC_TX_CF_SPEC_ALIGN                       0
#define TOP_1588_TX_CF_SPEC_TX_CF_SPEC_BITS                        16
#define TOP_1588_TX_CF_SPEC_TX_CF_SPEC_SHIFT                       0


/****************************************************************************
 * TOP_1588 :: MPLS_PACKET_ENABLE
 ***************************************************************************/
/* TOP_1588 :: MPLS_PACKET_ENABLE :: MPLS_PACKET_ENABLE [15:00] */
#define Wr_TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE(x) WriteReg16(TOP_1588_MPLS_PACKET_ENABLE,x)
#define Rd_TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE(x) ReadReg16(TOP_1588_MPLS_PACKET_ENABLE)
#define TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE_MASK        0xffff
#define TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE_ALIGN       0
#define TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE_BITS        16
#define TOP_1588_MPLS_PACKET_ENABLE_MPLS_PACKET_ENABLE_SHIFT       0


/****************************************************************************
 * TOP_1588 :: TIMECODE_SEL
 ***************************************************************************/
/* TOP_1588 :: TIMECODE_SEL :: TIMECODE_SEL [15:00] */
#define Wr_TOP_1588_TIMECODE_SEL_TIMECODE_SEL(x) WriteReg16(TOP_1588_TIMECODE_SEL,x)
#define Rd_TOP_1588_TIMECODE_SEL_TIMECODE_SEL(x) ReadReg16(TOP_1588_TIMECODE_SEL)
#define TOP_1588_TIMECODE_SEL_TIMECODE_SEL_MASK                    0xffff
#define TOP_1588_TIMECODE_SEL_TIMECODE_SEL_ALIGN                   0
#define TOP_1588_TIMECODE_SEL_TIMECODE_SEL_BITS                    16
#define TOP_1588_TIMECODE_SEL_TIMECODE_SEL_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_3
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_3 :: TIME_STAMP_3 [15:00] */
#define Wr_TOP_1588_TIME_STAMP_3_TIME_STAMP_3(x) WriteReg16(TOP_1588_TIME_STAMP_3,x)
#define Rd_TOP_1588_TIME_STAMP_3_TIME_STAMP_3(x) ReadReg16(TOP_1588_TIME_STAMP_3)
#define TOP_1588_TIME_STAMP_3_TIME_STAMP_3_MASK                    0xffff
#define TOP_1588_TIME_STAMP_3_TIME_STAMP_3_ALIGN                   0
#define TOP_1588_TIME_STAMP_3_TIME_STAMP_3_BITS                    16
#define TOP_1588_TIME_STAMP_3_TIME_STAMP_3_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP :: TIME_STAMP [15:00] */
#define Wr_TOP_1588_TIME_STAMP_TIME_STAMP(x) WriteReg16(TOP_1588_TIME_STAMP,x)
#define Rd_TOP_1588_TIME_STAMP_TIME_STAMP(x) ReadReg16(TOP_1588_TIME_STAMP)
#define TOP_1588_TIME_STAMP_TIME_STAMP_MASK                        0xffff
#define TOP_1588_TIME_STAMP_TIME_STAMP_ALIGN                       0
#define TOP_1588_TIME_STAMP_TIME_STAMP_BITS                        16
#define TOP_1588_TIME_STAMP_TIME_STAMP_SHIFT                       0


/****************************************************************************
 * TOP_1588 :: DM_TX_CNTL
 ***************************************************************************/
/* TOP_1588 :: DM_TX_CNTL :: SPARE_REG [15:10] */
#define Wr_TOP_1588_DM_TX_CNTL_SPARE_REG(x) WriteRegBits16(TOP_1588_DM_TX_CNTL,0xfc00,10,x)
#define Rd_TOP_1588_DM_TX_CNTL_SPARE_REG(x) ReadRegBits16(TOP_1588_DM_TX_CNTL,0xfc00,10)
#define TOP_1588_DM_TX_CNTL_SPARE_REG_MASK                         0xfc00
#define TOP_1588_DM_TX_CNTL_SPARE_REG_ALIGN                        0
#define TOP_1588_DM_TX_CNTL_SPARE_REG_BITS                         6
#define TOP_1588_DM_TX_CNTL_SPARE_REG_SHIFT                        10

/* TOP_1588 :: DM_TX_CNTL :: IETF_SEL [09:06] */
#define Wr_TOP_1588_DM_TX_CNTL_IETF_SEL(x) WriteRegBits16(TOP_1588_DM_TX_CNTL,0x3c0,6,x)
#define Rd_TOP_1588_DM_TX_CNTL_IETF_SEL(x) ReadRegBits16(TOP_1588_DM_TX_CNTL,0x3c0,6)
#define TOP_1588_DM_TX_CNTL_IETF_SEL_MASK                          0x03c0
#define TOP_1588_DM_TX_CNTL_IETF_SEL_ALIGN                         0
#define TOP_1588_DM_TX_CNTL_IETF_SEL_BITS                          4
#define TOP_1588_DM_TX_CNTL_IETF_SEL_SHIFT                         6

/* TOP_1588 :: DM_TX_CNTL :: BHH_TS_SEL [05:05] */
#define Wr_TOP_1588_DM_TX_CNTL_BHH_TS_SEL(x) WriteRegBits16(TOP_1588_DM_TX_CNTL,0x20,5,x)
#define Rd_TOP_1588_DM_TX_CNTL_BHH_TS_SEL(x) ReadRegBits16(TOP_1588_DM_TX_CNTL,0x20,5)
#define TOP_1588_DM_TX_CNTL_BHH_TS_SEL_MASK                        0x0020
#define TOP_1588_DM_TX_CNTL_BHH_TS_SEL_ALIGN                       0
#define TOP_1588_DM_TX_CNTL_BHH_TS_SEL_BITS                        1
#define TOP_1588_DM_TX_CNTL_BHH_TS_SEL_SHIFT                       5

/* TOP_1588 :: DM_TX_CNTL :: Y1731_TS_SEL [04:04] */
#define Wr_TOP_1588_DM_TX_CNTL_Y1731_TS_SEL(x) WriteRegBits16(TOP_1588_DM_TX_CNTL,0x10,4,x)
#define Rd_TOP_1588_DM_TX_CNTL_Y1731_TS_SEL(x) ReadRegBits16(TOP_1588_DM_TX_CNTL,0x10,4)
#define TOP_1588_DM_TX_CNTL_Y1731_TS_SEL_MASK                      0x0010
#define TOP_1588_DM_TX_CNTL_Y1731_TS_SEL_ALIGN                     0
#define TOP_1588_DM_TX_CNTL_Y1731_TS_SEL_BITS                      1
#define TOP_1588_DM_TX_CNTL_Y1731_TS_SEL_SHIFT                     4

/* TOP_1588 :: DM_TX_CNTL :: ENTROPY_EN [03:03] */
#define Wr_TOP_1588_DM_TX_CNTL_ENTROPY_EN(x) WriteRegBits16(TOP_1588_DM_TX_CNTL,0x8,3,x)
#define Rd_TOP_1588_DM_TX_CNTL_ENTROPY_EN(x) ReadRegBits16(TOP_1588_DM_TX_CNTL,0x8,3)
#define TOP_1588_DM_TX_CNTL_ENTROPY_EN_MASK                        0x0008
#define TOP_1588_DM_TX_CNTL_ENTROPY_EN_ALIGN                       0
#define TOP_1588_DM_TX_CNTL_ENTROPY_EN_BITS                        1
#define TOP_1588_DM_TX_CNTL_ENTROPY_EN_SHIFT                       3

/* TOP_1588 :: DM_TX_CNTL :: CW_EN [02:02] */
#define Wr_TOP_1588_DM_TX_CNTL_CW_EN(x) WriteRegBits16(TOP_1588_DM_TX_CNTL,0x4,2,x)
#define Rd_TOP_1588_DM_TX_CNTL_CW_EN(x) ReadRegBits16(TOP_1588_DM_TX_CNTL,0x4,2)
#define TOP_1588_DM_TX_CNTL_CW_EN_MASK                             0x0004
#define TOP_1588_DM_TX_CNTL_CW_EN_ALIGN                            0
#define TOP_1588_DM_TX_CNTL_CW_EN_BITS                             1
#define TOP_1588_DM_TX_CNTL_CW_EN_SHIFT                            2

/* TOP_1588 :: DM_TX_CNTL :: MAC_EN [01:01] */
#define Wr_TOP_1588_DM_TX_CNTL_MAC_EN(x) WriteRegBits16(TOP_1588_DM_TX_CNTL,0x2,1,x)
#define Rd_TOP_1588_DM_TX_CNTL_MAC_EN(x) ReadRegBits16(TOP_1588_DM_TX_CNTL,0x2,1)
#define TOP_1588_DM_TX_CNTL_MAC_EN_MASK                            0x0002
#define TOP_1588_DM_TX_CNTL_MAC_EN_ALIGN                           0
#define TOP_1588_DM_TX_CNTL_MAC_EN_BITS                            1
#define TOP_1588_DM_TX_CNTL_MAC_EN_SHIFT                           1

/* TOP_1588 :: DM_TX_CNTL :: EN [00:00] */
#define Wr_TOP_1588_DM_TX_CNTL_EN(x) WriteRegBits16(TOP_1588_DM_TX_CNTL,0x1,0,x)
#define Rd_TOP_1588_DM_TX_CNTL_EN(x) ReadRegBits16(TOP_1588_DM_TX_CNTL,0x1,0)
#define TOP_1588_DM_TX_CNTL_EN_MASK                                0x0001
#define TOP_1588_DM_TX_CNTL_EN_ALIGN                               0
#define TOP_1588_DM_TX_CNTL_EN_BITS                                1
#define TOP_1588_DM_TX_CNTL_EN_SHIFT                               0


/****************************************************************************
 * TOP_1588 :: DM_RX_CNTL
 ***************************************************************************/
/* TOP_1588 :: DM_RX_CNTL :: SPARE_REG [15:10] */
#define Wr_TOP_1588_DM_RX_CNTL_SPARE_REG(x) WriteRegBits16(TOP_1588_DM_RX_CNTL,0xfc00,10,x)
#define Rd_TOP_1588_DM_RX_CNTL_SPARE_REG(x) ReadRegBits16(TOP_1588_DM_RX_CNTL,0xfc00,10)
#define TOP_1588_DM_RX_CNTL_SPARE_REG_MASK                         0xfc00
#define TOP_1588_DM_RX_CNTL_SPARE_REG_ALIGN                        0
#define TOP_1588_DM_RX_CNTL_SPARE_REG_BITS                         6
#define TOP_1588_DM_RX_CNTL_SPARE_REG_SHIFT                        10

/* TOP_1588 :: DM_RX_CNTL :: IETF_SEL [09:06] */
#define Wr_TOP_1588_DM_RX_CNTL_IETF_SEL(x) WriteRegBits16(TOP_1588_DM_RX_CNTL,0x3c0,6,x)
#define Rd_TOP_1588_DM_RX_CNTL_IETF_SEL(x) ReadRegBits16(TOP_1588_DM_RX_CNTL,0x3c0,6)
#define TOP_1588_DM_RX_CNTL_IETF_SEL_MASK                          0x03c0
#define TOP_1588_DM_RX_CNTL_IETF_SEL_ALIGN                         0
#define TOP_1588_DM_RX_CNTL_IETF_SEL_BITS                          4
#define TOP_1588_DM_RX_CNTL_IETF_SEL_SHIFT                         6

/* TOP_1588 :: DM_RX_CNTL :: BHH_TS_SEL [05:05] */
#define Wr_TOP_1588_DM_RX_CNTL_BHH_TS_SEL(x) WriteRegBits16(TOP_1588_DM_RX_CNTL,0x20,5,x)
#define Rd_TOP_1588_DM_RX_CNTL_BHH_TS_SEL(x) ReadRegBits16(TOP_1588_DM_RX_CNTL,0x20,5)
#define TOP_1588_DM_RX_CNTL_BHH_TS_SEL_MASK                        0x0020
#define TOP_1588_DM_RX_CNTL_BHH_TS_SEL_ALIGN                       0
#define TOP_1588_DM_RX_CNTL_BHH_TS_SEL_BITS                        1
#define TOP_1588_DM_RX_CNTL_BHH_TS_SEL_SHIFT                       5

/* TOP_1588 :: DM_RX_CNTL :: Y1731_TS_SEL [04:04] */
#define Wr_TOP_1588_DM_RX_CNTL_Y1731_TS_SEL(x) WriteRegBits16(TOP_1588_DM_RX_CNTL,0x10,4,x)
#define Rd_TOP_1588_DM_RX_CNTL_Y1731_TS_SEL(x) ReadRegBits16(TOP_1588_DM_RX_CNTL,0x10,4)
#define TOP_1588_DM_RX_CNTL_Y1731_TS_SEL_MASK                      0x0010
#define TOP_1588_DM_RX_CNTL_Y1731_TS_SEL_ALIGN                     0
#define TOP_1588_DM_RX_CNTL_Y1731_TS_SEL_BITS                      1
#define TOP_1588_DM_RX_CNTL_Y1731_TS_SEL_SHIFT                     4

/* TOP_1588 :: DM_RX_CNTL :: ENTROPY_EN [03:03] */
#define Wr_TOP_1588_DM_RX_CNTL_ENTROPY_EN(x) WriteRegBits16(TOP_1588_DM_RX_CNTL,0x8,3,x)
#define Rd_TOP_1588_DM_RX_CNTL_ENTROPY_EN(x) ReadRegBits16(TOP_1588_DM_RX_CNTL,0x8,3)
#define TOP_1588_DM_RX_CNTL_ENTROPY_EN_MASK                        0x0008
#define TOP_1588_DM_RX_CNTL_ENTROPY_EN_ALIGN                       0
#define TOP_1588_DM_RX_CNTL_ENTROPY_EN_BITS                        1
#define TOP_1588_DM_RX_CNTL_ENTROPY_EN_SHIFT                       3

/* TOP_1588 :: DM_RX_CNTL :: CW_EN [02:02] */
#define Wr_TOP_1588_DM_RX_CNTL_CW_EN(x) WriteRegBits16(TOP_1588_DM_RX_CNTL,0x4,2,x)
#define Rd_TOP_1588_DM_RX_CNTL_CW_EN(x) ReadRegBits16(TOP_1588_DM_RX_CNTL,0x4,2)
#define TOP_1588_DM_RX_CNTL_CW_EN_MASK                             0x0004
#define TOP_1588_DM_RX_CNTL_CW_EN_ALIGN                            0
#define TOP_1588_DM_RX_CNTL_CW_EN_BITS                             1
#define TOP_1588_DM_RX_CNTL_CW_EN_SHIFT                            2

/* TOP_1588 :: DM_RX_CNTL :: MAC_EN [01:01] */
#define Wr_TOP_1588_DM_RX_CNTL_MAC_EN(x) WriteRegBits16(TOP_1588_DM_RX_CNTL,0x2,1,x)
#define Rd_TOP_1588_DM_RX_CNTL_MAC_EN(x) ReadRegBits16(TOP_1588_DM_RX_CNTL,0x2,1)
#define TOP_1588_DM_RX_CNTL_MAC_EN_MASK                            0x0002
#define TOP_1588_DM_RX_CNTL_MAC_EN_ALIGN                           0
#define TOP_1588_DM_RX_CNTL_MAC_EN_BITS                            1
#define TOP_1588_DM_RX_CNTL_MAC_EN_SHIFT                           1

/* TOP_1588 :: DM_RX_CNTL :: EN [00:00] */
#define Wr_TOP_1588_DM_RX_CNTL_EN(x) WriteRegBits16(TOP_1588_DM_RX_CNTL,0x1,0,x)
#define Rd_TOP_1588_DM_RX_CNTL_EN(x) ReadRegBits16(TOP_1588_DM_RX_CNTL,0x1,0)
#define TOP_1588_DM_RX_CNTL_EN_MASK                                0x0001
#define TOP_1588_DM_RX_CNTL_EN_ALIGN                               0
#define TOP_1588_DM_RX_CNTL_EN_BITS                                1
#define TOP_1588_DM_RX_CNTL_EN_SHIFT                               0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE1
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE1 :: DM_ETHTYPE1 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1(x) WriteReg16(TOP_1588_DM_ETHTYPE1,x)
#define Rd_TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1(x) ReadReg16(TOP_1588_DM_ETHTYPE1)
#define TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1_MASK                      0xffff
#define TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1_ALIGN                     0
#define TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1_BITS                      16
#define TOP_1588_DM_ETHTYPE1_DM_ETHTYPE1_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE2
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE2 :: DM_ETHTYPE2 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2(x) WriteReg16(TOP_1588_DM_ETHTYPE2,x)
#define Rd_TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2(x) ReadReg16(TOP_1588_DM_ETHTYPE2)
#define TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2_MASK                      0xffff
#define TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2_ALIGN                     0
#define TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2_BITS                      16
#define TOP_1588_DM_ETHTYPE2_DM_ETHTYPE2_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE3
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE3 :: DM_ETHTYPE3 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3(x) WriteReg16(TOP_1588_DM_ETHTYPE3,x)
#define Rd_TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3(x) ReadReg16(TOP_1588_DM_ETHTYPE3)
#define TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3_MASK                      0xffff
#define TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3_ALIGN                     0
#define TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3_BITS                      16
#define TOP_1588_DM_ETHTYPE3_DM_ETHTYPE3_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE4
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE4 :: DM_ETHTYPE4 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4(x) WriteReg16(TOP_1588_DM_ETHTYPE4,x)
#define Rd_TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4(x) ReadReg16(TOP_1588_DM_ETHTYPE4)
#define TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4_MASK                      0xffff
#define TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4_ALIGN                     0
#define TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4_BITS                      16
#define TOP_1588_DM_ETHTYPE4_DM_ETHTYPE4_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE5
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE5 :: DM_ETHTYPE5 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5(x) WriteReg16(TOP_1588_DM_ETHTYPE5,x)
#define Rd_TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5(x) ReadReg16(TOP_1588_DM_ETHTYPE5)
#define TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5_MASK                      0xffff
#define TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5_ALIGN                     0
#define TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5_BITS                      16
#define TOP_1588_DM_ETHTYPE5_DM_ETHTYPE5_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE6
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE6 :: DM_ETHTYPE6 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6(x) WriteReg16(TOP_1588_DM_ETHTYPE6,x)
#define Rd_TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6(x) ReadReg16(TOP_1588_DM_ETHTYPE6)
#define TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6_MASK                      0xffff
#define TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6_ALIGN                     0
#define TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6_BITS                      16
#define TOP_1588_DM_ETHTYPE6_DM_ETHTYPE6_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE7
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE7 :: DM_ETHTYPE7 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7(x) WriteReg16(TOP_1588_DM_ETHTYPE7,x)
#define Rd_TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7(x) ReadReg16(TOP_1588_DM_ETHTYPE7)
#define TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7_MASK                      0xffff
#define TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7_ALIGN                     0
#define TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7_BITS                      16
#define TOP_1588_DM_ETHTYPE7_DM_ETHTYPE7_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE8
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE8 :: DM_ETHTYPE8 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8(x) WriteReg16(TOP_1588_DM_ETHTYPE8,x)
#define Rd_TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8(x) ReadReg16(TOP_1588_DM_ETHTYPE8)
#define TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8_MASK                      0xffff
#define TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8_ALIGN                     0
#define TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8_BITS                      16
#define TOP_1588_DM_ETHTYPE8_DM_ETHTYPE8_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE9
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE9 :: DM_ETHTYPE9 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9(x) WriteReg16(TOP_1588_DM_ETHTYPE9,x)
#define Rd_TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9(x) ReadReg16(TOP_1588_DM_ETHTYPE9)
#define TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9_MASK                      0xffff
#define TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9_ALIGN                     0
#define TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9_BITS                      16
#define TOP_1588_DM_ETHTYPE9_DM_ETHTYPE9_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE10
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE10 :: DM_ETHTYPE10 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10(x) WriteReg16(TOP_1588_DM_ETHTYPE10,x)
#define Rd_TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10(x) ReadReg16(TOP_1588_DM_ETHTYPE10)
#define TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10_MASK                    0xffff
#define TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10_ALIGN                   0
#define TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10_BITS                    16
#define TOP_1588_DM_ETHTYPE10_DM_ETHTYPE10_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE11
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE11 :: DM_ETHTYPE11 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11(x) WriteReg16(TOP_1588_DM_ETHTYPE11,x)
#define Rd_TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11(x) ReadReg16(TOP_1588_DM_ETHTYPE11)
#define TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11_MASK                    0xffff
#define TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11_ALIGN                   0
#define TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11_BITS                    16
#define TOP_1588_DM_ETHTYPE11_DM_ETHTYPE11_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE12
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE12 :: DM_ETHTYPE12 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12(x) WriteReg16(TOP_1588_DM_ETHTYPE12,x)
#define Rd_TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12(x) ReadReg16(TOP_1588_DM_ETHTYPE12)
#define TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12_MASK                    0xffff
#define TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12_ALIGN                   0
#define TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12_BITS                    16
#define TOP_1588_DM_ETHTYPE12_DM_ETHTYPE12_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: DM_ETHTYPE13
 ***************************************************************************/
/* TOP_1588 :: DM_ETHTYPE13 :: DM_ETHTYPE13 [15:00] */
#define Wr_TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13(x) WriteReg16(TOP_1588_DM_ETHTYPE13,x)
#define Rd_TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13(x) ReadReg16(TOP_1588_DM_ETHTYPE13)
#define TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13_MASK                    0xffff
#define TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13_ALIGN                   0
#define TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13_BITS                    16
#define TOP_1588_DM_ETHTYPE13_DM_ETHTYPE13_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: DM_IETF_OFFSET
 ***************************************************************************/
/* TOP_1588 :: DM_IETF_OFFSET :: RX_OFFSET [15:08] */
#define Wr_TOP_1588_DM_IETF_OFFSET_RX_OFFSET(x) WriteRegBits16(TOP_1588_DM_IETF_OFFSET,0xff00,8,x)
#define Rd_TOP_1588_DM_IETF_OFFSET_RX_OFFSET(x) ReadRegBits16(TOP_1588_DM_IETF_OFFSET,0xff00,8)
#define TOP_1588_DM_IETF_OFFSET_RX_OFFSET_MASK                     0xff00
#define TOP_1588_DM_IETF_OFFSET_RX_OFFSET_ALIGN                    0
#define TOP_1588_DM_IETF_OFFSET_RX_OFFSET_BITS                     8
#define TOP_1588_DM_IETF_OFFSET_RX_OFFSET_SHIFT                    8

/* TOP_1588 :: DM_IETF_OFFSET :: TX_OFFSET [07:00] */
#define Wr_TOP_1588_DM_IETF_OFFSET_TX_OFFSET(x) WriteRegBits16(TOP_1588_DM_IETF_OFFSET,0xff,0,x)
#define Rd_TOP_1588_DM_IETF_OFFSET_TX_OFFSET(x) ReadRegBits16(TOP_1588_DM_IETF_OFFSET,0xff,0)
#define TOP_1588_DM_IETF_OFFSET_TX_OFFSET_MASK                     0x00ff
#define TOP_1588_DM_IETF_OFFSET_TX_OFFSET_ALIGN                    0
#define TOP_1588_DM_IETF_OFFSET_TX_OFFSET_BITS                     8
#define TOP_1588_DM_IETF_OFFSET_TX_OFFSET_SHIFT                    0


/****************************************************************************
 * TOP_1588 :: NTP_TIME_STAMP_0
 ***************************************************************************/
/* TOP_1588 :: NTP_TIME_STAMP_0 :: NTP_TIME_STAMP_0 [15:00] */
#define Wr_TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0(x) WriteReg16(TOP_1588_NTP_TIME_STAMP_0,x)
#define Rd_TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0(x) ReadReg16(TOP_1588_NTP_TIME_STAMP_0)
#define TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0_MASK            0xffff
#define TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0_ALIGN           0
#define TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0_BITS            16
#define TOP_1588_NTP_TIME_STAMP_0_NTP_TIME_STAMP_0_SHIFT           0


/****************************************************************************
 * TOP_1588 :: NTP_TIME_STAMP_1
 ***************************************************************************/
/* TOP_1588 :: NTP_TIME_STAMP_1 :: NTP_TIME_STAMP_1 [15:00] */
#define Wr_TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1(x) WriteReg16(TOP_1588_NTP_TIME_STAMP_1,x)
#define Rd_TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1(x) ReadReg16(TOP_1588_NTP_TIME_STAMP_1)
#define TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1_MASK            0xffff
#define TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1_ALIGN           0
#define TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1_BITS            16
#define TOP_1588_NTP_TIME_STAMP_1_NTP_TIME_STAMP_1_SHIFT           0


/****************************************************************************
 * TOP_1588 :: NTP_TIME_STAMP_2
 ***************************************************************************/
/* TOP_1588 :: NTP_TIME_STAMP_2 :: NTP_TIME_STAMP_2 [15:00] */
#define Wr_TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2(x) WriteReg16(TOP_1588_NTP_TIME_STAMP_2,x)
#define Rd_TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2(x) ReadReg16(TOP_1588_NTP_TIME_STAMP_2)
#define TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2_MASK            0xffff
#define TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2_ALIGN           0
#define TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2_BITS            16
#define TOP_1588_NTP_TIME_STAMP_2_NTP_TIME_STAMP_2_SHIFT           0


/****************************************************************************
 * TOP_1588 :: NTP_TIME_STAMP_3
 ***************************************************************************/
/* TOP_1588 :: NTP_TIME_STAMP_3 :: NTP_TIME_STAMP_3 [15:00] */
#define Wr_TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3(x) WriteReg16(TOP_1588_NTP_TIME_STAMP_3,x)
#define Rd_TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3(x) ReadReg16(TOP_1588_NTP_TIME_STAMP_3)
#define TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3_MASK            0xffff
#define TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3_ALIGN           0
#define TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3_BITS            16
#define TOP_1588_NTP_TIME_STAMP_3_NTP_TIME_STAMP_3_SHIFT           0


/****************************************************************************
 * TOP_1588 :: NTP_NCO_FREQ_0
 ***************************************************************************/
/* TOP_1588 :: NTP_NCO_FREQ_0 :: NTP_NCO_FREQ_0 [15:00] */
#define Wr_TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0(x) WriteReg16(TOP_1588_NTP_NCO_FREQ_0,x)
#define Rd_TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0(x) ReadReg16(TOP_1588_NTP_NCO_FREQ_0)
#define TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0_MASK                0xffff
#define TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0_ALIGN               0
#define TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0_BITS                16
#define TOP_1588_NTP_NCO_FREQ_0_NTP_NCO_FREQ_0_SHIFT               0


/****************************************************************************
 * TOP_1588 :: NTP_NCO_FREQ_1
 ***************************************************************************/
/* TOP_1588 :: NTP_NCO_FREQ_1 :: NTP_NCO_FREQ_1 [15:00] */
#define Wr_TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1(x) WriteReg16(TOP_1588_NTP_NCO_FREQ_1,x)
#define Rd_TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1(x) ReadReg16(TOP_1588_NTP_NCO_FREQ_1)
#define TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1_MASK                0xffff
#define TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1_ALIGN               0
#define TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1_BITS                16
#define TOP_1588_NTP_NCO_FREQ_1_NTP_NCO_FREQ_1_SHIFT               0


/****************************************************************************
 * TOP_1588 :: NTP_DOWN_CNTER_0
 ***************************************************************************/
/* TOP_1588 :: NTP_DOWN_CNTER_0 :: NTP_DOWN_CNTER_0 [15:00] */
#define Wr_TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0(x) WriteReg16(TOP_1588_NTP_DOWN_CNTER_0,x)
#define Rd_TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0(x) ReadReg16(TOP_1588_NTP_DOWN_CNTER_0)
#define TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0_MASK            0xffff
#define TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0_ALIGN           0
#define TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0_BITS            16
#define TOP_1588_NTP_DOWN_CNTER_0_NTP_DOWN_CNTER_0_SHIFT           0


/****************************************************************************
 * TOP_1588 :: NTP_DOWN_CNTER_1
 ***************************************************************************/
/* TOP_1588 :: NTP_DOWN_CNTER_1 :: NTP_DOWN_CNTER_1 [15:00] */
#define Wr_TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1(x) WriteReg16(TOP_1588_NTP_DOWN_CNTER_1,x)
#define Rd_TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1(x) ReadReg16(TOP_1588_NTP_DOWN_CNTER_1)
#define TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1_MASK            0xffff
#define TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1_ALIGN           0
#define TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1_BITS            16
#define TOP_1588_NTP_DOWN_CNTER_1_NTP_DOWN_CNTER_1_SHIFT           0


/****************************************************************************
 * TOP_1588 :: NTP_ERR_LSB
 ***************************************************************************/
/* TOP_1588 :: NTP_ERR_LSB :: NTP_ERR_LSB [15:00] */
#define Wr_TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB(x) WriteReg16(TOP_1588_NTP_ERR_LSB,x)
#define Rd_TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB(x) ReadReg16(TOP_1588_NTP_ERR_LSB)
#define TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB_MASK                      0xffff
#define TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB_ALIGN                     0
#define TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB_BITS                      16
#define TOP_1588_NTP_ERR_LSB_NTP_ERR_LSB_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: NTP_ERR_MSB
 ***************************************************************************/
/* TOP_1588 :: NTP_ERR_MSB :: NTP_ERR_MSB [15:00] */
#define Wr_TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB(x) WriteReg16(TOP_1588_NTP_ERR_MSB,x)
#define Rd_TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB(x) ReadReg16(TOP_1588_NTP_ERR_MSB)
#define TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB_MASK                      0xffff
#define TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB_ALIGN                     0
#define TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB_BITS                      16
#define TOP_1588_NTP_ERR_MSB_NTP_ERR_MSB_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: DM_MAC_L1_0
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_L1_0 :: DM_DA1 [15:00] */
#define Wr_TOP_1588_DM_MAC_L1_0_DM_DA1(x) WriteReg16(TOP_1588_DM_MAC_L1_0,x)
#define Rd_TOP_1588_DM_MAC_L1_0_DM_DA1(x) ReadReg16(TOP_1588_DM_MAC_L1_0)
#define TOP_1588_DM_MAC_L1_0_DM_DA1_MASK                           0xffff
#define TOP_1588_DM_MAC_L1_0_DM_DA1_ALIGN                          0
#define TOP_1588_DM_MAC_L1_0_DM_DA1_BITS                           16
#define TOP_1588_DM_MAC_L1_0_DM_DA1_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: DM_MAC_L1_1
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_L1_1 :: DM_DA2 [15:00] */
#define Wr_TOP_1588_DM_MAC_L1_1_DM_DA2(x) WriteReg16(TOP_1588_DM_MAC_L1_1,x)
#define Rd_TOP_1588_DM_MAC_L1_1_DM_DA2(x) ReadReg16(TOP_1588_DM_MAC_L1_1)
#define TOP_1588_DM_MAC_L1_1_DM_DA2_MASK                           0xffff
#define TOP_1588_DM_MAC_L1_1_DM_DA2_ALIGN                          0
#define TOP_1588_DM_MAC_L1_1_DM_DA2_BITS                           16
#define TOP_1588_DM_MAC_L1_1_DM_DA2_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: DM_MAC_L1_2
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_L1_2 :: DM_DA3 [15:00] */
#define Wr_TOP_1588_DM_MAC_L1_2_DM_DA3(x) WriteReg16(TOP_1588_DM_MAC_L1_2,x)
#define Rd_TOP_1588_DM_MAC_L1_2_DM_DA3(x) ReadReg16(TOP_1588_DM_MAC_L1_2)
#define TOP_1588_DM_MAC_L1_2_DM_DA3_MASK                           0xffff
#define TOP_1588_DM_MAC_L1_2_DM_DA3_ALIGN                          0
#define TOP_1588_DM_MAC_L1_2_DM_DA3_BITS                           16
#define TOP_1588_DM_MAC_L1_2_DM_DA3_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: DM_MAC_L2_0
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_L2_0 :: DM_DA1 [15:00] */
#define Wr_TOP_1588_DM_MAC_L2_0_DM_DA1(x) WriteReg16(TOP_1588_DM_MAC_L2_0,x)
#define Rd_TOP_1588_DM_MAC_L2_0_DM_DA1(x) ReadReg16(TOP_1588_DM_MAC_L2_0)
#define TOP_1588_DM_MAC_L2_0_DM_DA1_MASK                           0xffff
#define TOP_1588_DM_MAC_L2_0_DM_DA1_ALIGN                          0
#define TOP_1588_DM_MAC_L2_0_DM_DA1_BITS                           16
#define TOP_1588_DM_MAC_L2_0_DM_DA1_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: DM_MAC_L2_1
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_L2_1 :: DM_DA2 [15:00] */
#define Wr_TOP_1588_DM_MAC_L2_1_DM_DA2(x) WriteReg16(TOP_1588_DM_MAC_L2_1,x)
#define Rd_TOP_1588_DM_MAC_L2_1_DM_DA2(x) ReadReg16(TOP_1588_DM_MAC_L2_1)
#define TOP_1588_DM_MAC_L2_1_DM_DA2_MASK                           0xffff
#define TOP_1588_DM_MAC_L2_1_DM_DA2_ALIGN                          0
#define TOP_1588_DM_MAC_L2_1_DM_DA2_BITS                           16
#define TOP_1588_DM_MAC_L2_1_DM_DA2_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: DM_MAC_L2_2
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_L2_2 :: DM_DA3 [15:00] */
#define Wr_TOP_1588_DM_MAC_L2_2_DM_DA3(x) WriteReg16(TOP_1588_DM_MAC_L2_2,x)
#define Rd_TOP_1588_DM_MAC_L2_2_DM_DA3(x) ReadReg16(TOP_1588_DM_MAC_L2_2)
#define TOP_1588_DM_MAC_L2_2_DM_DA3_MASK                           0xffff
#define TOP_1588_DM_MAC_L2_2_DM_DA3_ALIGN                          0
#define TOP_1588_DM_MAC_L2_2_DM_DA3_BITS                           16
#define TOP_1588_DM_MAC_L2_2_DM_DA3_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: DM_MAC_L3_0
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_L3_0 :: DM_DA1 [15:00] */
#define Wr_TOP_1588_DM_MAC_L3_0_DM_DA1(x) WriteReg16(TOP_1588_DM_MAC_L3_0,x)
#define Rd_TOP_1588_DM_MAC_L3_0_DM_DA1(x) ReadReg16(TOP_1588_DM_MAC_L3_0)
#define TOP_1588_DM_MAC_L3_0_DM_DA1_MASK                           0xffff
#define TOP_1588_DM_MAC_L3_0_DM_DA1_ALIGN                          0
#define TOP_1588_DM_MAC_L3_0_DM_DA1_BITS                           16
#define TOP_1588_DM_MAC_L3_0_DM_DA1_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: DM_MAC_L3_1
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_L3_1 :: DM_DA2 [15:00] */
#define Wr_TOP_1588_DM_MAC_L3_1_DM_DA2(x) WriteReg16(TOP_1588_DM_MAC_L3_1,x)
#define Rd_TOP_1588_DM_MAC_L3_1_DM_DA2(x) ReadReg16(TOP_1588_DM_MAC_L3_1)
#define TOP_1588_DM_MAC_L3_1_DM_DA2_MASK                           0xffff
#define TOP_1588_DM_MAC_L3_1_DM_DA2_ALIGN                          0
#define TOP_1588_DM_MAC_L3_1_DM_DA2_BITS                           16
#define TOP_1588_DM_MAC_L3_1_DM_DA2_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: DM_MAC_L3_2
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_L3_2 :: DM_DA3 [15:00] */
#define Wr_TOP_1588_DM_MAC_L3_2_DM_DA3(x) WriteReg16(TOP_1588_DM_MAC_L3_2,x)
#define Rd_TOP_1588_DM_MAC_L3_2_DM_DA3(x) ReadReg16(TOP_1588_DM_MAC_L3_2)
#define TOP_1588_DM_MAC_L3_2_DM_DA3_MASK                           0xffff
#define TOP_1588_DM_MAC_L3_2_DM_DA3_ALIGN                          0
#define TOP_1588_DM_MAC_L3_2_DM_DA3_BITS                           16
#define TOP_1588_DM_MAC_L3_2_DM_DA3_SHIFT                          0


/****************************************************************************
 * TOP_1588 :: DM_MAC_CTL_0
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_CTL_0 :: DM_DA1 [15:00] */
#define Wr_TOP_1588_DM_MAC_CTL_0_DM_DA1(x) WriteReg16(TOP_1588_DM_MAC_CTL_0,x)
#define Rd_TOP_1588_DM_MAC_CTL_0_DM_DA1(x) ReadReg16(TOP_1588_DM_MAC_CTL_0)
#define TOP_1588_DM_MAC_CTL_0_DM_DA1_MASK                          0xffff
#define TOP_1588_DM_MAC_CTL_0_DM_DA1_ALIGN                         0
#define TOP_1588_DM_MAC_CTL_0_DM_DA1_BITS                          16
#define TOP_1588_DM_MAC_CTL_0_DM_DA1_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: DM_MAC_CTL_1
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_CTL_1 :: DM_DA2 [15:00] */
#define Wr_TOP_1588_DM_MAC_CTL_1_DM_DA2(x) WriteReg16(TOP_1588_DM_MAC_CTL_1,x)
#define Rd_TOP_1588_DM_MAC_CTL_1_DM_DA2(x) ReadReg16(TOP_1588_DM_MAC_CTL_1)
#define TOP_1588_DM_MAC_CTL_1_DM_DA2_MASK                          0xffff
#define TOP_1588_DM_MAC_CTL_1_DM_DA2_ALIGN                         0
#define TOP_1588_DM_MAC_CTL_1_DM_DA2_BITS                          16
#define TOP_1588_DM_MAC_CTL_1_DM_DA2_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: DM_MAC_CTL_2
 ***************************************************************************/
/* TOP_1588 :: DM_MAC_CTL_2 :: DM_DA3 [15:00] */
#define Wr_TOP_1588_DM_MAC_CTL_2_DM_DA3(x) WriteReg16(TOP_1588_DM_MAC_CTL_2,x)
#define Rd_TOP_1588_DM_MAC_CTL_2_DM_DA3(x) ReadReg16(TOP_1588_DM_MAC_CTL_2)
#define TOP_1588_DM_MAC_CTL_2_DM_DA3_MASK                          0xffff
#define TOP_1588_DM_MAC_CTL_2_DM_DA3_ALIGN                         0
#define TOP_1588_DM_MAC_CTL_2_DM_DA3_BITS                          16
#define TOP_1588_DM_MAC_CTL_2_DM_DA3_SHIFT                         0


/****************************************************************************
 * TOP_1588 :: HEARTBEAT_3
 ***************************************************************************/
/* TOP_1588 :: HEARTBEAT_3 :: HEARTBEAT_3 [15:00] */
#define Wr_TOP_1588_HEARTBEAT_3_HEARTBEAT_3(x) WriteReg16(TOP_1588_HEARTBEAT_3,x)
#define Rd_TOP_1588_HEARTBEAT_3_HEARTBEAT_3(x) ReadReg16(TOP_1588_HEARTBEAT_3)
#define TOP_1588_HEARTBEAT_3_HEARTBEAT_3_MASK                      0xffff
#define TOP_1588_HEARTBEAT_3_HEARTBEAT_3_ALIGN                     0
#define TOP_1588_HEARTBEAT_3_HEARTBEAT_3_BITS                      16
#define TOP_1588_HEARTBEAT_3_HEARTBEAT_3_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: HEARTBEAT_4
 ***************************************************************************/
/* TOP_1588 :: HEARTBEAT_4 :: HEARTBEAT_4 [15:00] */
#define Wr_TOP_1588_HEARTBEAT_4_HEARTBEAT_4(x) WriteReg16(TOP_1588_HEARTBEAT_4,x)
#define Rd_TOP_1588_HEARTBEAT_4_HEARTBEAT_4(x) ReadReg16(TOP_1588_HEARTBEAT_4)
#define TOP_1588_HEARTBEAT_4_HEARTBEAT_4_MASK                      0xffff
#define TOP_1588_HEARTBEAT_4_HEARTBEAT_4_ALIGN                     0
#define TOP_1588_HEARTBEAT_4_HEARTBEAT_4_BITS                      16
#define TOP_1588_HEARTBEAT_4_HEARTBEAT_4_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: INBAND_CNTL_0
 ***************************************************************************/
/* TOP_1588 :: INBAND_CNTL_0 :: INBAND_CNTL [15:00] */
#define Wr_TOP_1588_INBAND_CNTL_0_INBAND_CNTL(x) WriteReg16(TOP_1588_INBAND_CNTL_0,x)
#define Rd_TOP_1588_INBAND_CNTL_0_INBAND_CNTL(x) ReadReg16(TOP_1588_INBAND_CNTL_0)
#define TOP_1588_INBAND_CNTL_0_INBAND_CNTL_MASK                    0xffff
#define TOP_1588_INBAND_CNTL_0_INBAND_CNTL_ALIGN                   0
#define TOP_1588_INBAND_CNTL_0_INBAND_CNTL_BITS                    16
#define TOP_1588_INBAND_CNTL_0_INBAND_CNTL_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: INBAND_CNTL_1
 ***************************************************************************/
/* TOP_1588 :: INBAND_CNTL_1 :: INBAND_CNTL [15:00] */
#define Wr_TOP_1588_INBAND_CNTL_1_INBAND_CNTL(x) WriteReg16(TOP_1588_INBAND_CNTL_1,x)
#define Rd_TOP_1588_INBAND_CNTL_1_INBAND_CNTL(x) ReadReg16(TOP_1588_INBAND_CNTL_1)
#define TOP_1588_INBAND_CNTL_1_INBAND_CNTL_MASK                    0xffff
#define TOP_1588_INBAND_CNTL_1_INBAND_CNTL_ALIGN                   0
#define TOP_1588_INBAND_CNTL_1_INBAND_CNTL_BITS                    16
#define TOP_1588_INBAND_CNTL_1_INBAND_CNTL_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: INBAND_CNTL_2
 ***************************************************************************/
/* TOP_1588 :: INBAND_CNTL_2 :: INBAND_CNTL [15:00] */
#define Wr_TOP_1588_INBAND_CNTL_2_INBAND_CNTL(x) WriteReg16(TOP_1588_INBAND_CNTL_2,x)
#define Rd_TOP_1588_INBAND_CNTL_2_INBAND_CNTL(x) ReadReg16(TOP_1588_INBAND_CNTL_2)
#define TOP_1588_INBAND_CNTL_2_INBAND_CNTL_MASK                    0xffff
#define TOP_1588_INBAND_CNTL_2_INBAND_CNTL_ALIGN                   0
#define TOP_1588_INBAND_CNTL_2_INBAND_CNTL_BITS                    16
#define TOP_1588_INBAND_CNTL_2_INBAND_CNTL_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: INBAND_CNTL_3
 ***************************************************************************/
/* TOP_1588 :: INBAND_CNTL_3 :: INBAND_CNTL [15:00] */
#define Wr_TOP_1588_INBAND_CNTL_3_INBAND_CNTL(x) WriteReg16(TOP_1588_INBAND_CNTL_3,x)
#define Rd_TOP_1588_INBAND_CNTL_3_INBAND_CNTL(x) ReadReg16(TOP_1588_INBAND_CNTL_3)
#define TOP_1588_INBAND_CNTL_3_INBAND_CNTL_MASK                    0xffff
#define TOP_1588_INBAND_CNTL_3_INBAND_CNTL_ALIGN                   0
#define TOP_1588_INBAND_CNTL_3_INBAND_CNTL_BITS                    16
#define TOP_1588_INBAND_CNTL_3_INBAND_CNTL_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: INBAND_CNTL_4
 ***************************************************************************/
/* TOP_1588 :: INBAND_CNTL_4 :: INBAND_CNTL [15:00] */
#define Wr_TOP_1588_INBAND_CNTL_4_INBAND_CNTL(x) WriteReg16(TOP_1588_INBAND_CNTL_4,x)
#define Rd_TOP_1588_INBAND_CNTL_4_INBAND_CNTL(x) ReadReg16(TOP_1588_INBAND_CNTL_4)
#define TOP_1588_INBAND_CNTL_4_INBAND_CNTL_MASK                    0xffff
#define TOP_1588_INBAND_CNTL_4_INBAND_CNTL_ALIGN                   0
#define TOP_1588_INBAND_CNTL_4_INBAND_CNTL_BITS                    16
#define TOP_1588_INBAND_CNTL_4_INBAND_CNTL_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: INBAND_CNTL_5
 ***************************************************************************/
/* TOP_1588 :: INBAND_CNTL_5 :: INBAND_CNTL [15:00] */
#define Wr_TOP_1588_INBAND_CNTL_5_INBAND_CNTL(x) WriteReg16(TOP_1588_INBAND_CNTL_5,x)
#define Rd_TOP_1588_INBAND_CNTL_5_INBAND_CNTL(x) ReadReg16(TOP_1588_INBAND_CNTL_5)
#define TOP_1588_INBAND_CNTL_5_INBAND_CNTL_MASK                    0xffff
#define TOP_1588_INBAND_CNTL_5_INBAND_CNTL_ALIGN                   0
#define TOP_1588_INBAND_CNTL_5_INBAND_CNTL_BITS                    16
#define TOP_1588_INBAND_CNTL_5_INBAND_CNTL_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: INBAND_CNTL_6
 ***************************************************************************/
/* TOP_1588 :: INBAND_CNTL_6 :: INBAND_CNTL [15:00] */
#define Wr_TOP_1588_INBAND_CNTL_6_INBAND_CNTL(x) WriteReg16(TOP_1588_INBAND_CNTL_6,x)
#define Rd_TOP_1588_INBAND_CNTL_6_INBAND_CNTL(x) ReadReg16(TOP_1588_INBAND_CNTL_6)
#define TOP_1588_INBAND_CNTL_6_INBAND_CNTL_MASK                    0xffff
#define TOP_1588_INBAND_CNTL_6_INBAND_CNTL_ALIGN                   0
#define TOP_1588_INBAND_CNTL_6_INBAND_CNTL_BITS                    16
#define TOP_1588_INBAND_CNTL_6_INBAND_CNTL_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: INBAND_CNTL_7
 ***************************************************************************/
/* TOP_1588 :: INBAND_CNTL_7 :: INBAND_CNTL [15:00] */
#define Wr_TOP_1588_INBAND_CNTL_7_INBAND_CNTL(x) WriteReg16(TOP_1588_INBAND_CNTL_7,x)
#define Rd_TOP_1588_INBAND_CNTL_7_INBAND_CNTL(x) ReadReg16(TOP_1588_INBAND_CNTL_7)
#define TOP_1588_INBAND_CNTL_7_INBAND_CNTL_MASK                    0xffff
#define TOP_1588_INBAND_CNTL_7_INBAND_CNTL_ALIGN                   0
#define TOP_1588_INBAND_CNTL_7_INBAND_CNTL_BITS                    16
#define TOP_1588_INBAND_CNTL_7_INBAND_CNTL_SHIFT                   0


/****************************************************************************
 * TOP_1588 :: MEM_COUNTER
 ***************************************************************************/
/* TOP_1588 :: MEM_COUNTER :: MEM_COUNTER [15:00] */
#define Wr_TOP_1588_MEM_COUNTER_MEM_COUNTER(x) WriteReg16(TOP_1588_MEM_COUNTER,x)
#define Rd_TOP_1588_MEM_COUNTER_MEM_COUNTER(x) ReadReg16(TOP_1588_MEM_COUNTER)
#define TOP_1588_MEM_COUNTER_MEM_COUNTER_MASK                      0xffff
#define TOP_1588_MEM_COUNTER_MEM_COUNTER_ALIGN                     0
#define TOP_1588_MEM_COUNTER_MEM_COUNTER_BITS                      16
#define TOP_1588_MEM_COUNTER_MEM_COUNTER_SHIFT                     0


/****************************************************************************
 * TOP_1588 :: TIMESTAMP_DELTA
 ***************************************************************************/
/* TOP_1588 :: TIMESTAMP_DELTA :: TIMESTAMP_DELTA1 [15:15] */
#define Wr_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1(x) WriteRegBits16(TOP_1588_TIMESTAMP_DELTA,0x8000,15,x)
#define Rd_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1(x) ReadRegBits16(TOP_1588_TIMESTAMP_DELTA,0x8000,15)
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1_MASK             0x8000
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1_ALIGN            0
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1_BITS             1
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA1_SHIFT            15

/* TOP_1588 :: TIMESTAMP_DELTA :: TIMESTAMP_DELTA2 [14:14] */
#define Wr_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2(x) WriteRegBits16(TOP_1588_TIMESTAMP_DELTA,0x4000,14,x)
#define Rd_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2(x) ReadRegBits16(TOP_1588_TIMESTAMP_DELTA,0x4000,14)
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2_MASK             0x4000
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2_ALIGN            0
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2_BITS             1
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA2_SHIFT            14

/* TOP_1588 :: TIMESTAMP_DELTA :: TIMESTAMP_DELTA3 [13:00] */
#define Wr_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3(x) WriteRegBits16(TOP_1588_TIMESTAMP_DELTA,0x3fff,0,x)
#define Rd_TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3(x) ReadRegBits16(TOP_1588_TIMESTAMP_DELTA,0x3fff,0)
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3_MASK             0x3fff
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3_ALIGN            0
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3_BITS             14
#define TOP_1588_TIMESTAMP_DELTA_TIMESTAMP_DELTA3_SHIFT            0


/****************************************************************************
 * TOP_1588 :: SOP_SEL
 ***************************************************************************/
/* TOP_1588 :: SOP_SEL :: SOP_SEL [15:00] */
#define Wr_TOP_1588_SOP_SEL_SOP_SEL(x) WriteReg16(TOP_1588_SOP_SEL,x)
#define Rd_TOP_1588_SOP_SEL_SOP_SEL(x) ReadReg16(TOP_1588_SOP_SEL)
#define TOP_1588_SOP_SEL_SOP_SEL_MASK                              0xffff
#define TOP_1588_SOP_SEL_SOP_SEL_ALIGN                             0
#define TOP_1588_SOP_SEL_SOP_SEL_BITS                              16
#define TOP_1588_SOP_SEL_SOP_SEL_SHIFT                             0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_INFO_3
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_INFO_3 :: TIME_STAMP_INFO [15:00] */
#define Wr_TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO(x) WriteReg16(TOP_1588_TIME_STAMP_INFO_3,x)
#define Rd_TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO(x) ReadReg16(TOP_1588_TIME_STAMP_INFO_3)
#define TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO_MASK            0xffff
#define TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO_ALIGN           0
#define TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO_BITS            16
#define TOP_1588_TIME_STAMP_INFO_3_TIME_STAMP_INFO_SHIFT           0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_INFO_4
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_INFO_4 :: TIME_STAMP_INFO [15:00] */
#define Wr_TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO(x) WriteReg16(TOP_1588_TIME_STAMP_INFO_4,x)
#define Rd_TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO(x) ReadReg16(TOP_1588_TIME_STAMP_INFO_4)
#define TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO_MASK            0xffff
#define TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO_ALIGN           0
#define TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO_BITS            16
#define TOP_1588_TIME_STAMP_INFO_4_TIME_STAMP_INFO_SHIFT           0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_INFO_5
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_INFO_5 :: TIME_STAMP_INFO [15:00] */
#define Wr_TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO(x) WriteReg16(TOP_1588_TIME_STAMP_INFO_5,x)
#define Rd_TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO(x) ReadReg16(TOP_1588_TIME_STAMP_INFO_5)
#define TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO_MASK            0xffff
#define TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO_ALIGN           0
#define TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO_BITS            16
#define TOP_1588_TIME_STAMP_INFO_5_TIME_STAMP_INFO_SHIFT           0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_INFO_6
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_INFO_6 :: TIME_STAMP_INFO [15:00] */
#define Wr_TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO(x) WriteReg16(TOP_1588_TIME_STAMP_INFO_6,x)
#define Rd_TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO(x) ReadReg16(TOP_1588_TIME_STAMP_INFO_6)
#define TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO_MASK            0xffff
#define TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO_ALIGN           0
#define TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO_BITS            16
#define TOP_1588_TIME_STAMP_INFO_6_TIME_STAMP_INFO_SHIFT           0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_INFO_7
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_INFO_7 :: TIME_STAMP_INFO [15:00] */
#define Wr_TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO(x) WriteReg16(TOP_1588_TIME_STAMP_INFO_7,x)
#define Rd_TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO(x) ReadReg16(TOP_1588_TIME_STAMP_INFO_7)
#define TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO_MASK            0xffff
#define TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO_ALIGN           0
#define TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO_BITS            16
#define TOP_1588_TIME_STAMP_INFO_7_TIME_STAMP_INFO_SHIFT           0


/****************************************************************************
 * TOP_1588 :: TIME_STAMP_INFO_8
 ***************************************************************************/
/* TOP_1588 :: TIME_STAMP_INFO_8 :: TIME_STAMP_INFO [15:00] */
#define Wr_TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO(x) WriteReg16(TOP_1588_TIME_STAMP_INFO_8,x)
#define Rd_TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO(x) ReadReg16(TOP_1588_TIME_STAMP_INFO_8)
#define TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO_MASK            0xffff
#define TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO_ALIGN           0
#define TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO_BITS            16
#define TOP_1588_TIME_STAMP_INFO_8_TIME_STAMP_INFO_SHIFT           0


/****************************************************************************
 * TOP_1588 :: INBAND_SPARE1
 ***************************************************************************/
/* TOP_1588 :: INBAND_SPARE1 :: INBAND_SPARE [15:00] */
#define Wr_TOP_1588_INBAND_SPARE1_INBAND_SPARE(x) WriteReg16(TOP_1588_INBAND_SPARE1,x)
#define Rd_TOP_1588_INBAND_SPARE1_INBAND_SPARE(x) ReadReg16(TOP_1588_INBAND_SPARE1)
#define TOP_1588_INBAND_SPARE1_INBAND_SPARE_MASK                   0xffff
#define TOP_1588_INBAND_SPARE1_INBAND_SPARE_ALIGN                  0
#define TOP_1588_INBAND_SPARE1_INBAND_SPARE_BITS                   16
#define TOP_1588_INBAND_SPARE1_INBAND_SPARE_SHIFT                  0


/****************************************************************************
 * bcm89530_swsys_switch
 ***************************************************************************/
/****************************************************************************
 * switch :: PAGE_00_G_PCTL0
 ***************************************************************************/
/* switch :: PAGE_00_G_PCTL0 :: PAGE_00_G_PCTL0_G_MISTP_STATE [07:05] */
#define Wr_switch_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_G_MISTP_STATE(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL0,0xe0,5,x)
#define Rd_switch_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_G_MISTP_STATE(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL0,0xe0,5)
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_G_MISTP_STATE_MASK  0xe0
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_G_MISTP_STATE_ALIGN 0
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_G_MISTP_STATE_BITS  3
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_G_MISTP_STATE_SHIFT 5

/* switch :: PAGE_00_G_PCTL0 :: PAGE_00_G_PCTL0_RESERVED [04:02] */
#define Wr_switch_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL0,0x1c,2,x)
#define Rd_switch_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL0,0x1c,2)
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RESERVED_MASK       0x1c
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RESERVED_ALIGN      0
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RESERVED_BITS       3
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RESERVED_SHIFT      2

/* switch :: PAGE_00_G_PCTL0 :: PAGE_00_G_PCTL0_TX_DIS [01:01] */
#define Wr_switch_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_TX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL0,0x2,1,x)
#define Rd_switch_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_TX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL0,0x2,1)
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_TX_DIS_MASK         0x02
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_TX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_TX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_TX_DIS_SHIFT        1

/* switch :: PAGE_00_G_PCTL0 :: PAGE_00_G_PCTL0_RX_DIS [00:00] */
#define Wr_switch_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL0,0x1,0,x)
#define Rd_switch_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL0,0x1,0)
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RX_DIS_MASK         0x01
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL0_PAGE_00_G_PCTL0_RX_DIS_SHIFT        0


/****************************************************************************
 * switch :: PAGE_00_G_PCTL1
 ***************************************************************************/
/* switch :: PAGE_00_G_PCTL1 :: PAGE_00_G_PCTL1_G_MISTP_STATE [07:05] */
#define Wr_switch_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_G_MISTP_STATE(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL1,0xe0,5,x)
#define Rd_switch_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_G_MISTP_STATE(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL1,0xe0,5)
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_G_MISTP_STATE_MASK  0xe0
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_G_MISTP_STATE_ALIGN 0
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_G_MISTP_STATE_BITS  3
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_G_MISTP_STATE_SHIFT 5

/* switch :: PAGE_00_G_PCTL1 :: PAGE_00_G_PCTL1_RESERVED [04:02] */
#define Wr_switch_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL1,0x1c,2,x)
#define Rd_switch_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL1,0x1c,2)
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RESERVED_MASK       0x1c
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RESERVED_ALIGN      0
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RESERVED_BITS       3
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RESERVED_SHIFT      2

/* switch :: PAGE_00_G_PCTL1 :: PAGE_00_G_PCTL1_TX_DIS [01:01] */
#define Wr_switch_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_TX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL1,0x2,1,x)
#define Rd_switch_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_TX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL1,0x2,1)
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_TX_DIS_MASK         0x02
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_TX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_TX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_TX_DIS_SHIFT        1

/* switch :: PAGE_00_G_PCTL1 :: PAGE_00_G_PCTL1_RX_DIS [00:00] */
#define Wr_switch_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL1,0x1,0,x)
#define Rd_switch_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL1,0x1,0)
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RX_DIS_MASK         0x01
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL1_PAGE_00_G_PCTL1_RX_DIS_SHIFT        0


/****************************************************************************
 * switch :: PAGE_00_G_PCTL2
 ***************************************************************************/
/* switch :: PAGE_00_G_PCTL2 :: PAGE_00_G_PCTL2_G_MISTP_STATE [07:05] */
#define Wr_switch_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_G_MISTP_STATE(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL2,0xe0,5,x)
#define Rd_switch_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_G_MISTP_STATE(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL2,0xe0,5)
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_G_MISTP_STATE_MASK  0xe0
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_G_MISTP_STATE_ALIGN 0
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_G_MISTP_STATE_BITS  3
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_G_MISTP_STATE_SHIFT 5

/* switch :: PAGE_00_G_PCTL2 :: PAGE_00_G_PCTL2_RESERVED [04:02] */
#define Wr_switch_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL2,0x1c,2,x)
#define Rd_switch_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL2,0x1c,2)
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RESERVED_MASK       0x1c
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RESERVED_ALIGN      0
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RESERVED_BITS       3
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RESERVED_SHIFT      2

/* switch :: PAGE_00_G_PCTL2 :: PAGE_00_G_PCTL2_TX_DIS [01:01] */
#define Wr_switch_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_TX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL2,0x2,1,x)
#define Rd_switch_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_TX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL2,0x2,1)
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_TX_DIS_MASK         0x02
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_TX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_TX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_TX_DIS_SHIFT        1

/* switch :: PAGE_00_G_PCTL2 :: PAGE_00_G_PCTL2_RX_DIS [00:00] */
#define Wr_switch_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL2,0x1,0,x)
#define Rd_switch_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL2,0x1,0)
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RX_DIS_MASK         0x01
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL2_PAGE_00_G_PCTL2_RX_DIS_SHIFT        0


/****************************************************************************
 * switch :: PAGE_00_G_PCTL3
 ***************************************************************************/
/* switch :: PAGE_00_G_PCTL3 :: PAGE_00_G_PCTL3_G_MISTP_STATE [07:05] */
#define Wr_switch_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_G_MISTP_STATE(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL3,0xe0,5,x)
#define Rd_switch_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_G_MISTP_STATE(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL3,0xe0,5)
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_G_MISTP_STATE_MASK  0xe0
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_G_MISTP_STATE_ALIGN 0
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_G_MISTP_STATE_BITS  3
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_G_MISTP_STATE_SHIFT 5

/* switch :: PAGE_00_G_PCTL3 :: PAGE_00_G_PCTL3_RESERVED [04:02] */
#define Wr_switch_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL3,0x1c,2,x)
#define Rd_switch_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL3,0x1c,2)
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RESERVED_MASK       0x1c
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RESERVED_ALIGN      0
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RESERVED_BITS       3
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RESERVED_SHIFT      2

/* switch :: PAGE_00_G_PCTL3 :: PAGE_00_G_PCTL3_TX_DIS [01:01] */
#define Wr_switch_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_TX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL3,0x2,1,x)
#define Rd_switch_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_TX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL3,0x2,1)
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_TX_DIS_MASK         0x02
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_TX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_TX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_TX_DIS_SHIFT        1

/* switch :: PAGE_00_G_PCTL3 :: PAGE_00_G_PCTL3_RX_DIS [00:00] */
#define Wr_switch_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL3,0x1,0,x)
#define Rd_switch_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL3,0x1,0)
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RX_DIS_MASK         0x01
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL3_PAGE_00_G_PCTL3_RX_DIS_SHIFT        0


/****************************************************************************
 * switch :: PAGE_00_G_PCTL4
 ***************************************************************************/
/* switch :: PAGE_00_G_PCTL4 :: PAGE_00_G_PCTL4_G_MISTP_STATE [07:05] */
#define Wr_switch_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_G_MISTP_STATE(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL4,0xe0,5,x)
#define Rd_switch_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_G_MISTP_STATE(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL4,0xe0,5)
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_G_MISTP_STATE_MASK  0xe0
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_G_MISTP_STATE_ALIGN 0
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_G_MISTP_STATE_BITS  3
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_G_MISTP_STATE_SHIFT 5

/* switch :: PAGE_00_G_PCTL4 :: PAGE_00_G_PCTL4_RESERVED [04:02] */
#define Wr_switch_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL4,0x1c,2,x)
#define Rd_switch_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL4,0x1c,2)
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RESERVED_MASK       0x1c
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RESERVED_ALIGN      0
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RESERVED_BITS       3
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RESERVED_SHIFT      2

/* switch :: PAGE_00_G_PCTL4 :: PAGE_00_G_PCTL4_TX_DIS [01:01] */
#define Wr_switch_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_TX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL4,0x2,1,x)
#define Rd_switch_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_TX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL4,0x2,1)
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_TX_DIS_MASK         0x02
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_TX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_TX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_TX_DIS_SHIFT        1

/* switch :: PAGE_00_G_PCTL4 :: PAGE_00_G_PCTL4_RX_DIS [00:00] */
#define Wr_switch_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL4,0x1,0,x)
#define Rd_switch_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL4,0x1,0)
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RX_DIS_MASK         0x01
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL4_PAGE_00_G_PCTL4_RX_DIS_SHIFT        0


/****************************************************************************
 * switch :: PAGE_00_G_PCTL5
 ***************************************************************************/
/* switch :: PAGE_00_G_PCTL5 :: PAGE_00_G_PCTL5_G_MISTP_STATE [07:05] */
#define Wr_switch_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_G_MISTP_STATE(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL5,0xe0,5,x)
#define Rd_switch_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_G_MISTP_STATE(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL5,0xe0,5)
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_G_MISTP_STATE_MASK  0xe0
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_G_MISTP_STATE_ALIGN 0
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_G_MISTP_STATE_BITS  3
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_G_MISTP_STATE_SHIFT 5

/* switch :: PAGE_00_G_PCTL5 :: PAGE_00_G_PCTL5_RESERVED [04:02] */
#define Wr_switch_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL5,0x1c,2,x)
#define Rd_switch_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL5,0x1c,2)
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RESERVED_MASK       0x1c
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RESERVED_ALIGN      0
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RESERVED_BITS       3
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RESERVED_SHIFT      2

/* switch :: PAGE_00_G_PCTL5 :: PAGE_00_G_PCTL5_TX_DIS [01:01] */
#define Wr_switch_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_TX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL5,0x2,1,x)
#define Rd_switch_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_TX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL5,0x2,1)
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_TX_DIS_MASK         0x02
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_TX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_TX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_TX_DIS_SHIFT        1

/* switch :: PAGE_00_G_PCTL5 :: PAGE_00_G_PCTL5_RX_DIS [00:00] */
#define Wr_switch_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL5,0x1,0,x)
#define Rd_switch_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL5,0x1,0)
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RX_DIS_MASK         0x01
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL5_PAGE_00_G_PCTL5_RX_DIS_SHIFT        0


/****************************************************************************
 * switch :: PAGE_00_G_PCTL6
 ***************************************************************************/
/* switch :: PAGE_00_G_PCTL6 :: PAGE_00_G_PCTL6_G_MISTP_STATE [07:05] */
#define Wr_switch_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_G_MISTP_STATE(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL6,0xe0,5,x)
#define Rd_switch_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_G_MISTP_STATE(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL6,0xe0,5)
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_G_MISTP_STATE_MASK  0xe0
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_G_MISTP_STATE_ALIGN 0
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_G_MISTP_STATE_BITS  3
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_G_MISTP_STATE_SHIFT 5

/* switch :: PAGE_00_G_PCTL6 :: PAGE_00_G_PCTL6_RESERVED [04:02] */
#define Wr_switch_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL6,0x1c,2,x)
#define Rd_switch_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL6,0x1c,2)
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RESERVED_MASK       0x1c
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RESERVED_ALIGN      0
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RESERVED_BITS       3
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RESERVED_SHIFT      2

/* switch :: PAGE_00_G_PCTL6 :: PAGE_00_G_PCTL6_TX_DIS [01:01] */
#define Wr_switch_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_TX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL6,0x2,1,x)
#define Rd_switch_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_TX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL6,0x2,1)
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_TX_DIS_MASK         0x02
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_TX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_TX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_TX_DIS_SHIFT        1

/* switch :: PAGE_00_G_PCTL6 :: PAGE_00_G_PCTL6_RX_DIS [00:00] */
#define Wr_switch_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RX_DIS(x) WriteRegBits(SWITCH_PAGE_00_G_PCTL6,0x1,0,x)
#define Rd_switch_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RX_DIS(x) ReadRegBits(SWITCH_PAGE_00_G_PCTL6,0x1,0)
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RX_DIS_MASK         0x01
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RX_DIS_ALIGN        0
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RX_DIS_BITS         1
#define SWITCH_PAGE_00_G_PCTL6_PAGE_00_G_PCTL6_RX_DIS_SHIFT        0


/****************************************************************************
 * switch :: PAGE_00_P7_CTL
 ***************************************************************************/
/* switch :: PAGE_00_P7_CTL :: PAGE_00_P7_CTL_G_MISTP_STATE [07:05] */
#define Wr_switch_PAGE_00_P7_CTL_PAGE_00_P7_CTL_G_MISTP_STATE(x) WriteRegBits(SWITCH_PAGE_00_P7_CTL,0xe0,5,x)
#define Rd_switch_PAGE_00_P7_CTL_PAGE_00_P7_CTL_G_MISTP_STATE(x) ReadRegBits(SWITCH_PAGE_00_P7_CTL,0xe0,5)
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_G_MISTP_STATE_MASK    0xe0
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_G_MISTP_STATE_ALIGN   0
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_G_MISTP_STATE_BITS    3
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_G_MISTP_STATE_SHIFT   5

/* switch :: PAGE_00_P7_CTL :: PAGE_00_P7_CTL_RESERVED [04:02] */
#define Wr_switch_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_P7_CTL,0x1c,2,x)
#define Rd_switch_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_P7_CTL,0x1c,2)
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RESERVED_MASK         0x1c
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RESERVED_ALIGN        0
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RESERVED_BITS         3
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RESERVED_SHIFT        2

/* switch :: PAGE_00_P7_CTL :: PAGE_00_P7_CTL_TX_DIS [01:01] */
#define Wr_switch_PAGE_00_P7_CTL_PAGE_00_P7_CTL_TX_DIS(x) WriteRegBits(SWITCH_PAGE_00_P7_CTL,0x2,1,x)
#define Rd_switch_PAGE_00_P7_CTL_PAGE_00_P7_CTL_TX_DIS(x) ReadRegBits(SWITCH_PAGE_00_P7_CTL,0x2,1)
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_TX_DIS_MASK           0x02
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_TX_DIS_ALIGN          0
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_TX_DIS_BITS           1
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_TX_DIS_SHIFT          1

/* switch :: PAGE_00_P7_CTL :: PAGE_00_P7_CTL_RX_DIS [00:00] */
#define Wr_switch_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RX_DIS(x) WriteRegBits(SWITCH_PAGE_00_P7_CTL,0x1,0,x)
#define Rd_switch_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RX_DIS(x) ReadRegBits(SWITCH_PAGE_00_P7_CTL,0x1,0)
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RX_DIS_MASK           0x01
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RX_DIS_ALIGN          0
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RX_DIS_BITS           1
#define SWITCH_PAGE_00_P7_CTL_PAGE_00_P7_CTL_RX_DIS_SHIFT          0


/****************************************************************************
 * switch :: PAGE_00_IMP_CTL
 ***************************************************************************/
/* switch :: PAGE_00_IMP_CTL :: PAGE_00_IMP_CTL_RESERVED [07:05] */
#define Wr_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_IMP_CTL,0xe0,5,x)
#define Rd_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_IMP_CTL,0xe0,5)
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RESERVED_MASK       0xe0
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RESERVED_ALIGN      0
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RESERVED_BITS       3
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RESERVED_SHIFT      5

/* switch :: PAGE_00_IMP_CTL :: PAGE_00_IMP_CTL_RX_UCST_EN [04:04] */
#define Wr_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_UCST_EN(x) WriteRegBits(SWITCH_PAGE_00_IMP_CTL,0x10,4,x)
#define Rd_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_UCST_EN(x) ReadRegBits(SWITCH_PAGE_00_IMP_CTL,0x10,4)
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_UCST_EN_MASK     0x10
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_UCST_EN_ALIGN    0
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_UCST_EN_BITS     1
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_UCST_EN_SHIFT    4

/* switch :: PAGE_00_IMP_CTL :: PAGE_00_IMP_CTL_RX_MCST_EN [03:03] */
#define Wr_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_MCST_EN(x) WriteRegBits(SWITCH_PAGE_00_IMP_CTL,0x8,3,x)
#define Rd_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_MCST_EN(x) ReadRegBits(SWITCH_PAGE_00_IMP_CTL,0x8,3)
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_MCST_EN_MASK     0x08
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_MCST_EN_ALIGN    0
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_MCST_EN_BITS     1
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_MCST_EN_SHIFT    3

/* switch :: PAGE_00_IMP_CTL :: PAGE_00_IMP_CTL_RX_BCST_EN [02:02] */
#define Wr_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_BCST_EN(x) WriteRegBits(SWITCH_PAGE_00_IMP_CTL,0x4,2,x)
#define Rd_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_BCST_EN(x) ReadRegBits(SWITCH_PAGE_00_IMP_CTL,0x4,2)
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_BCST_EN_MASK     0x04
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_BCST_EN_ALIGN    0
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_BCST_EN_BITS     1
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_BCST_EN_SHIFT    2

/* switch :: PAGE_00_IMP_CTL :: PAGE_00_IMP_CTL_TX_DIS [01:01] */
#define Wr_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_TX_DIS(x) WriteRegBits(SWITCH_PAGE_00_IMP_CTL,0x2,1,x)
#define Rd_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_TX_DIS(x) ReadRegBits(SWITCH_PAGE_00_IMP_CTL,0x2,1)
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_TX_DIS_MASK         0x02
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_TX_DIS_ALIGN        0
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_TX_DIS_BITS         1
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_TX_DIS_SHIFT        1

/* switch :: PAGE_00_IMP_CTL :: PAGE_00_IMP_CTL_RX_DIS [00:00] */
#define Wr_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_DIS(x) WriteRegBits(SWITCH_PAGE_00_IMP_CTL,0x1,0,x)
#define Rd_switch_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_DIS(x) ReadRegBits(SWITCH_PAGE_00_IMP_CTL,0x1,0)
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_DIS_MASK         0x01
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_DIS_ALIGN        0
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_DIS_BITS         1
#define SWITCH_PAGE_00_IMP_CTL_PAGE_00_IMP_CTL_RX_DIS_SHIFT        0


/****************************************************************************
 * switch :: PAGE_00_RX_GLOBAL_CTL
 ***************************************************************************/
/* switch :: PAGE_00_RX_GLOBAL_CTL :: PAGE_00_RX_GLOBAL_CTL_RESERVED [07:07] */
#define Wr_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0x80,7,x)
#define Rd_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0x80,7)
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_RESERVED_MASK 0x80
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_RESERVED_BITS 1
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_RESERVED_SHIFT 7

/* switch :: PAGE_00_RX_GLOBAL_CTL :: PAGE_00_RX_GLOBAL_CTL_DIS_RX_MASK [06:06] */
#define Wr_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_RX_MASK(x) WriteRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0x40,6,x)
#define Rd_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_RX_MASK(x) ReadRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0x40,6)
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_RX_MASK_MASK 0x40
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_RX_MASK_ALIGN 0
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_RX_MASK_BITS 1
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_RX_MASK_SHIFT 6

/* switch :: PAGE_00_RX_GLOBAL_CTL :: PAGE_00_RX_GLOBAL_CTL_DIS_ECC_CHK [05:05] */
#define Wr_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_ECC_CHK(x) WriteRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0x20,5,x)
#define Rd_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_ECC_CHK(x) ReadRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0x20,5)
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_ECC_CHK_MASK 0x20
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_ECC_CHK_ALIGN 0
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_ECC_CHK_BITS 1
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_ECC_CHK_SHIFT 5

/* switch :: PAGE_00_RX_GLOBAL_CTL :: PAGE_00_RX_GLOBAL_CTL_DIS_CRC_CHK [04:04] */
#define Wr_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_CRC_CHK(x) WriteRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0x10,4,x)
#define Rd_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_CRC_CHK(x) ReadRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0x10,4)
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_CRC_CHK_MASK 0x10
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_CRC_CHK_ALIGN 0
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_CRC_CHK_BITS 1
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_DIS_CRC_CHK_SHIFT 4

/* switch :: PAGE_00_RX_GLOBAL_CTL :: PAGE_00_RX_GLOBAL_CTL_FMOK_LATENCY_CNT [03:00] */
#define Wr_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_FMOK_LATENCY_CNT(x) WriteRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0xf,0,x)
#define Rd_switch_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_FMOK_LATENCY_CNT(x) ReadRegBits(SWITCH_PAGE_00_RX_GLOBAL_CTL,0xf,0)
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_MASK 0x0f
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_ALIGN 0
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_BITS 4
#define SWITCH_PAGE_00_RX_GLOBAL_CTL_PAGE_00_RX_GLOBAL_CTL_FMOK_LATENCY_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_SWMODE
 ***************************************************************************/
/* switch :: PAGE_00_SWMODE :: PAGE_00_SWMODE_RESERVED [07:05] */
#define Wr_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_SWMODE,0xe0,5,x)
#define Rd_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_SWMODE,0xe0,5)
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_RESERVED_MASK         0xe0
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_RESERVED_ALIGN        0
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_RESERVED_BITS         3
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_RESERVED_SHIFT        5

/* switch :: PAGE_00_SWMODE :: PAGE_00_SWMODE_NOBLKCD [04:04] */
#define Wr_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_NOBLKCD(x) WriteRegBits(SWITCH_PAGE_00_SWMODE,0x10,4,x)
#define Rd_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_NOBLKCD(x) ReadRegBits(SWITCH_PAGE_00_SWMODE,0x10,4)
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_NOBLKCD_MASK          0x10
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_NOBLKCD_ALIGN         0
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_NOBLKCD_BITS          1
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_NOBLKCD_SHIFT         4

/* switch :: PAGE_00_SWMODE :: PAGE_00_SWMODE_FAST_TXDESC_RERURN [03:03] */
#define Wr_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_FAST_TXDESC_RERURN(x) WriteRegBits(SWITCH_PAGE_00_SWMODE,0x8,3,x)
#define Rd_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_FAST_TXDESC_RERURN(x) ReadRegBits(SWITCH_PAGE_00_SWMODE,0x8,3)
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_FAST_TXDESC_RERURN_MASK 0x08
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_FAST_TXDESC_RERURN_ALIGN 0
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_FAST_TXDESC_RERURN_BITS 1
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_FAST_TXDESC_RERURN_SHIFT 3

/* switch :: PAGE_00_SWMODE :: PAGE_00_SWMODE_RTRY_LMT_DIS [02:02] */
#define Wr_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_RTRY_LMT_DIS(x) WriteRegBits(SWITCH_PAGE_00_SWMODE,0x4,2,x)
#define Rd_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_RTRY_LMT_DIS(x) ReadRegBits(SWITCH_PAGE_00_SWMODE,0x4,2)
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_RTRY_LMT_DIS_MASK     0x04
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_RTRY_LMT_DIS_ALIGN    0
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_RTRY_LMT_DIS_BITS     1
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_RTRY_LMT_DIS_SHIFT    2

/* switch :: PAGE_00_SWMODE :: PAGE_00_SWMODE_SW_FWDG_EN [01:01] */
#define Wr_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_EN(x) WriteRegBits(SWITCH_PAGE_00_SWMODE,0x2,1,x)
#define Rd_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_EN(x) ReadRegBits(SWITCH_PAGE_00_SWMODE,0x2,1)
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_EN_MASK       0x02
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_EN_ALIGN      0
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_EN_BITS       1
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_EN_SHIFT      1

/* switch :: PAGE_00_SWMODE :: PAGE_00_SWMODE_SW_FWDG_MODE [00:00] */
#define Wr_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_MODE(x) WriteRegBits(SWITCH_PAGE_00_SWMODE,0x1,0,x)
#define Rd_switch_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_MODE(x) ReadRegBits(SWITCH_PAGE_00_SWMODE,0x1,0)
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_MODE_MASK     0x01
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_MODE_ALIGN    0
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_MODE_BITS     1
#define SWITCH_PAGE_00_SWMODE_PAGE_00_SWMODE_SW_FWDG_MODE_SHIFT    0


/****************************************************************************
 * switch :: PAGE_00_LED_REFLSH_CTL
 ***************************************************************************/
/* switch :: PAGE_00_LED_REFLSH_CTL :: PAGE_00_LED_REFLSH_CTL_LED_EN [07:07] */
#define Wr_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_EN(x) WriteRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x80,7,x)
#define Rd_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_EN(x) ReadRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x80,7)
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_EN_MASK 0x80
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_EN_ALIGN 0
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_EN_BITS 1
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_EN_SHIFT 7

/* switch :: PAGE_00_LED_REFLSH_CTL :: PAGE_00_LED_REFLSH_CTL_LED_POST_EXEC [06:06] */
#define Wr_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_EXEC(x) WriteRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x40,6,x)
#define Rd_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_EXEC(x) ReadRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x40,6)
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_EXEC_MASK 0x40
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_EXEC_ALIGN 0
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_EXEC_BITS 1
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_EXEC_SHIFT 6

/* switch :: PAGE_00_LED_REFLSH_CTL :: PAGE_00_LED_REFLSH_CTL_LED_PSCAN_EN [05:05] */
#define Wr_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_PSCAN_EN(x) WriteRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x20,5,x)
#define Rd_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_PSCAN_EN(x) ReadRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x20,5)
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_PSCAN_EN_MASK 0x20
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_PSCAN_EN_ALIGN 0
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_PSCAN_EN_BITS 1
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_PSCAN_EN_SHIFT 5

/* switch :: PAGE_00_LED_REFLSH_CTL :: PAGE_00_LED_REFLSH_CTL_LED_POST_CD_EN [04:04] */
#define Wr_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_CD_EN(x) WriteRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x10,4,x)
#define Rd_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_CD_EN(x) ReadRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x10,4)
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_CD_EN_MASK 0x10
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_CD_EN_ALIGN 0
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_CD_EN_BITS 1
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_POST_CD_EN_SHIFT 4

/* switch :: PAGE_00_LED_REFLSH_CTL :: PAGE_00_LED_REFLSH_CTL_LED_NORM_CD_EN [03:03] */
#define Wr_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_NORM_CD_EN(x) WriteRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x8,3,x)
#define Rd_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_NORM_CD_EN(x) ReadRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x8,3)
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_NORM_CD_EN_MASK 0x08
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_NORM_CD_EN_ALIGN 0
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_NORM_CD_EN_BITS 1
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_NORM_CD_EN_SHIFT 3

/* switch :: PAGE_00_LED_REFLSH_CTL :: PAGE_00_LED_REFLSH_CTL_LED_RFS_STOP [02:00] */
#define Wr_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_RFS_STOP(x) WriteRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x7,0,x)
#define Rd_switch_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_RFS_STOP(x) ReadRegBits(SWITCH_PAGE_00_LED_REFLSH_CTL,0x7,0)
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_RFS_STOP_MASK 0x07
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_RFS_STOP_ALIGN 0
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_RFS_STOP_BITS 3
#define SWITCH_PAGE_00_LED_REFLSH_CTL_PAGE_00_LED_REFLSH_CTL_LED_RFS_STOP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LED_FUNC0_CTL
 ***************************************************************************/
/* switch :: PAGE_00_LED_FUNC0_CTL :: PAGE_00_LED_FUNC0_CTL_LED_FUNC0 [15:00] */
#define Wr_switch_PAGE_00_LED_FUNC0_CTL_PAGE_00_LED_FUNC0_CTL_LED_FUNC0(x) WriteReg16(SWITCH_PAGE_00_LED_FUNC0_CTL,x)
#define Rd_switch_PAGE_00_LED_FUNC0_CTL_PAGE_00_LED_FUNC0_CTL_LED_FUNC0(x) ReadReg16(SWITCH_PAGE_00_LED_FUNC0_CTL)
#define SWITCH_PAGE_00_LED_FUNC0_CTL_PAGE_00_LED_FUNC0_CTL_LED_FUNC0_MASK 0xffff
#define SWITCH_PAGE_00_LED_FUNC0_CTL_PAGE_00_LED_FUNC0_CTL_LED_FUNC0_ALIGN 0
#define SWITCH_PAGE_00_LED_FUNC0_CTL_PAGE_00_LED_FUNC0_CTL_LED_FUNC0_BITS 16
#define SWITCH_PAGE_00_LED_FUNC0_CTL_PAGE_00_LED_FUNC0_CTL_LED_FUNC0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LED_FUNC1_CTL
 ***************************************************************************/
/* switch :: PAGE_00_LED_FUNC1_CTL :: PAGE_00_LED_FUNC1_CTL_LED_FUNC1 [15:00] */
#define Wr_switch_PAGE_00_LED_FUNC1_CTL_PAGE_00_LED_FUNC1_CTL_LED_FUNC1(x) WriteReg16(SWITCH_PAGE_00_LED_FUNC1_CTL,x)
#define Rd_switch_PAGE_00_LED_FUNC1_CTL_PAGE_00_LED_FUNC1_CTL_LED_FUNC1(x) ReadReg16(SWITCH_PAGE_00_LED_FUNC1_CTL)
#define SWITCH_PAGE_00_LED_FUNC1_CTL_PAGE_00_LED_FUNC1_CTL_LED_FUNC1_MASK 0xffff
#define SWITCH_PAGE_00_LED_FUNC1_CTL_PAGE_00_LED_FUNC1_CTL_LED_FUNC1_ALIGN 0
#define SWITCH_PAGE_00_LED_FUNC1_CTL_PAGE_00_LED_FUNC1_CTL_LED_FUNC1_BITS 16
#define SWITCH_PAGE_00_LED_FUNC1_CTL_PAGE_00_LED_FUNC1_CTL_LED_FUNC1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LED_FUNC_MAP
 ***************************************************************************/
/* switch :: PAGE_00_LED_FUNC_MAP :: PAGE_00_LED_FUNC_MAP_RESERVED [15:09] */
#define Wr_switch_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_LED_FUNC_MAP,0xfe00,9,x)
#define Rd_switch_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_LED_FUNC_MAP,0xfe00,9)
#define SWITCH_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_RESERVED_BITS 7
#define SWITCH_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_RESERVED_SHIFT 9

/* switch :: PAGE_00_LED_FUNC_MAP :: PAGE_00_LED_FUNC_MAP_LED_FUNC_MAP [08:00] */
#define Wr_switch_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_LED_FUNC_MAP(x) WriteRegBits16(SWITCH_PAGE_00_LED_FUNC_MAP,0x1ff,0,x)
#define Rd_switch_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_LED_FUNC_MAP(x) ReadRegBits16(SWITCH_PAGE_00_LED_FUNC_MAP,0x1ff,0)
#define SWITCH_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_LED_FUNC_MAP_MASK 0x01ff
#define SWITCH_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_LED_FUNC_MAP_ALIGN 0
#define SWITCH_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_LED_FUNC_MAP_BITS 9
#define SWITCH_PAGE_00_LED_FUNC_MAP_PAGE_00_LED_FUNC_MAP_LED_FUNC_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LED_EN_MAP
 ***************************************************************************/
/* switch :: PAGE_00_LED_EN_MAP :: PAGE_00_LED_EN_MAP_RESERVED [15:09] */
#define Wr_switch_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_LED_EN_MAP,0xfe00,9,x)
#define Rd_switch_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_LED_EN_MAP,0xfe00,9)
#define SWITCH_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_RESERVED_BITS 7
#define SWITCH_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_RESERVED_SHIFT 9

/* switch :: PAGE_00_LED_EN_MAP :: PAGE_00_LED_EN_MAP_LED_EN_MAP [08:00] */
#define Wr_switch_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_LED_EN_MAP(x) WriteRegBits16(SWITCH_PAGE_00_LED_EN_MAP,0x1ff,0,x)
#define Rd_switch_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_LED_EN_MAP(x) ReadRegBits16(SWITCH_PAGE_00_LED_EN_MAP,0x1ff,0)
#define SWITCH_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_LED_EN_MAP_MASK 0x01ff
#define SWITCH_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_LED_EN_MAP_ALIGN 0
#define SWITCH_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_LED_EN_MAP_BITS 9
#define SWITCH_PAGE_00_LED_EN_MAP_PAGE_00_LED_EN_MAP_LED_EN_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LED_MODE_MAP_0
 ***************************************************************************/
/* switch :: PAGE_00_LED_MODE_MAP_0 :: PAGE_00_LED_MODE_MAP_0_RESERVED [15:09] */
#define Wr_switch_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_LED_MODE_MAP_0,0xfe00,9,x)
#define Rd_switch_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_LED_MODE_MAP_0,0xfe00,9)
#define SWITCH_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_RESERVED_BITS 7
#define SWITCH_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_RESERVED_SHIFT 9

/* switch :: PAGE_00_LED_MODE_MAP_0 :: PAGE_00_LED_MODE_MAP_0_LED_MODE_MAP0 [08:00] */
#define Wr_switch_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_LED_MODE_MAP0(x) WriteRegBits16(SWITCH_PAGE_00_LED_MODE_MAP_0,0x1ff,0,x)
#define Rd_switch_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_LED_MODE_MAP0(x) ReadRegBits16(SWITCH_PAGE_00_LED_MODE_MAP_0,0x1ff,0)
#define SWITCH_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_LED_MODE_MAP0_MASK 0x01ff
#define SWITCH_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_LED_MODE_MAP0_ALIGN 0
#define SWITCH_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_LED_MODE_MAP0_BITS 9
#define SWITCH_PAGE_00_LED_MODE_MAP_0_PAGE_00_LED_MODE_MAP_0_LED_MODE_MAP0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LED_MODE_MAP_1
 ***************************************************************************/
/* switch :: PAGE_00_LED_MODE_MAP_1 :: PAGE_00_LED_MODE_MAP_1_RESERVED [15:09] */
#define Wr_switch_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_LED_MODE_MAP_1,0xfe00,9,x)
#define Rd_switch_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_LED_MODE_MAP_1,0xfe00,9)
#define SWITCH_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_RESERVED_BITS 7
#define SWITCH_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_RESERVED_SHIFT 9

/* switch :: PAGE_00_LED_MODE_MAP_1 :: PAGE_00_LED_MODE_MAP_1_LED_MODE_MAP1 [08:00] */
#define Wr_switch_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_LED_MODE_MAP1(x) WriteRegBits16(SWITCH_PAGE_00_LED_MODE_MAP_1,0x1ff,0,x)
#define Rd_switch_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_LED_MODE_MAP1(x) ReadRegBits16(SWITCH_PAGE_00_LED_MODE_MAP_1,0x1ff,0)
#define SWITCH_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_LED_MODE_MAP1_MASK 0x01ff
#define SWITCH_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_LED_MODE_MAP1_ALIGN 0
#define SWITCH_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_LED_MODE_MAP1_BITS 9
#define SWITCH_PAGE_00_LED_MODE_MAP_1_PAGE_00_LED_MODE_MAP_1_LED_MODE_MAP1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_POST_LED_CTRL
 ***************************************************************************/
/* switch :: PAGE_00_POST_LED_CTRL :: PAGE_00_POST_LED_CTRL_ACT_LED_TRIGGER [07:07] */
#define Wr_switch_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_ACT_LED_TRIGGER(x) WriteRegBits(SWITCH_PAGE_00_POST_LED_CTRL,0x80,7,x)
#define Rd_switch_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_ACT_LED_TRIGGER(x) ReadRegBits(SWITCH_PAGE_00_POST_LED_CTRL,0x80,7)
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_ACT_LED_TRIGGER_MASK 0x80
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_ACT_LED_TRIGGER_ALIGN 0
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_ACT_LED_TRIGGER_BITS 1
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_ACT_LED_TRIGGER_SHIFT 7

/* switch :: PAGE_00_POST_LED_CTRL :: PAGE_00_POST_LED_CTRL_RESERVED [06:04] */
#define Wr_switch_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_POST_LED_CTRL,0x70,4,x)
#define Rd_switch_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_POST_LED_CTRL,0x70,4)
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_RESERVED_MASK 0x70
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_RESERVED_BITS 3
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_RESERVED_SHIFT 4

/* switch :: PAGE_00_POST_LED_CTRL :: PAGE_00_POST_LED_CTRL_POST_LED_TRIGGER [03:00] */
#define Wr_switch_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_POST_LED_TRIGGER(x) WriteRegBits(SWITCH_PAGE_00_POST_LED_CTRL,0xf,0,x)
#define Rd_switch_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_POST_LED_TRIGGER(x) ReadRegBits(SWITCH_PAGE_00_POST_LED_CTRL,0xf,0)
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_POST_LED_TRIGGER_MASK 0x0f
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_POST_LED_TRIGGER_ALIGN 0
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_POST_LED_TRIGGER_BITS 4
#define SWITCH_PAGE_00_POST_LED_CTRL_PAGE_00_POST_LED_CTRL_POST_LED_TRIGGER_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_DEBUG_REG
 ***************************************************************************/
/* switch :: PAGE_00_DEBUG_REG :: PAGE_00_DEBUG_REG_PROBE_SOC_DMU_CLK [07:07] */
#define Wr_switch_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_PROBE_SOC_DMU_CLK(x) WriteRegBits(SWITCH_PAGE_00_DEBUG_REG,0x80,7,x)
#define Rd_switch_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_PROBE_SOC_DMU_CLK(x) ReadRegBits(SWITCH_PAGE_00_DEBUG_REG,0x80,7)
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_PROBE_SOC_DMU_CLK_MASK 0x80
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_PROBE_SOC_DMU_CLK_ALIGN 0
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_PROBE_SOC_DMU_CLK_BITS 1
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_PROBE_SOC_DMU_CLK_SHIFT 7

/* switch :: PAGE_00_DEBUG_REG :: PAGE_00_DEBUG_REG_DEBUG_SEL [06:01] */
#define Wr_switch_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_DEBUG_SEL(x) WriteRegBits(SWITCH_PAGE_00_DEBUG_REG,0x7e,1,x)
#define Rd_switch_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_DEBUG_SEL(x) ReadRegBits(SWITCH_PAGE_00_DEBUG_REG,0x7e,1)
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_DEBUG_SEL_MASK  0x7e
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_DEBUG_SEL_ALIGN 0
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_DEBUG_SEL_BITS  6
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_DEBUG_SEL_SHIFT 1

/* switch :: PAGE_00_DEBUG_REG :: PAGE_00_DEBUG_REG_EN_DEBUG [00:00] */
#define Wr_switch_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_EN_DEBUG(x) WriteRegBits(SWITCH_PAGE_00_DEBUG_REG,0x1,0,x)
#define Rd_switch_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_EN_DEBUG(x) ReadRegBits(SWITCH_PAGE_00_DEBUG_REG,0x1,0)
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_EN_DEBUG_MASK   0x01
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_EN_DEBUG_ALIGN  0
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_EN_DEBUG_BITS   1
#define SWITCH_PAGE_00_DEBUG_REG_PAGE_00_DEBUG_REG_EN_DEBUG_SHIFT  0


/****************************************************************************
 * switch :: PAGE_00_NEW_CTRL
 ***************************************************************************/
/* switch :: PAGE_00_NEW_CTRL :: PAGE_00_NEW_CTRL_MC_FWD_EN [07:07] */
#define Wr_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_MC_FWD_EN(x) WriteRegBits(SWITCH_PAGE_00_NEW_CTRL,0x80,7,x)
#define Rd_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_MC_FWD_EN(x) ReadRegBits(SWITCH_PAGE_00_NEW_CTRL,0x80,7)
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_MC_FWD_EN_MASK    0x80
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_MC_FWD_EN_ALIGN   0
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_MC_FWD_EN_BITS    1
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_MC_FWD_EN_SHIFT   7

/* switch :: PAGE_00_NEW_CTRL :: PAGE_00_NEW_CTRL_UC_FWD_EN [06:06] */
#define Wr_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_UC_FWD_EN(x) WriteRegBits(SWITCH_PAGE_00_NEW_CTRL,0x40,6,x)
#define Rd_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_UC_FWD_EN(x) ReadRegBits(SWITCH_PAGE_00_NEW_CTRL,0x40,6)
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_UC_FWD_EN_MASK    0x40
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_UC_FWD_EN_ALIGN   0
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_UC_FWD_EN_BITS    1
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_UC_FWD_EN_SHIFT   6

/* switch :: PAGE_00_NEW_CTRL :: PAGE_00_NEW_CTRL_EN_AUTO_PD_WAR [05:05] */
#define Wr_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_EN_AUTO_PD_WAR(x) WriteRegBits(SWITCH_PAGE_00_NEW_CTRL,0x20,5,x)
#define Rd_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_EN_AUTO_PD_WAR(x) ReadRegBits(SWITCH_PAGE_00_NEW_CTRL,0x20,5)
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_EN_AUTO_PD_WAR_MASK 0x20
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_EN_AUTO_PD_WAR_ALIGN 0
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_EN_AUTO_PD_WAR_BITS 1
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_EN_AUTO_PD_WAR_SHIFT 5

/* switch :: PAGE_00_NEW_CTRL :: PAGE_00_NEW_CTRL_OVERRIDE_AUTO_PD_WAR [04:04] */
#define Wr_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OVERRIDE_AUTO_PD_WAR(x) WriteRegBits(SWITCH_PAGE_00_NEW_CTRL,0x10,4,x)
#define Rd_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OVERRIDE_AUTO_PD_WAR(x) ReadRegBits(SWITCH_PAGE_00_NEW_CTRL,0x10,4)
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_MASK 0x10
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_ALIGN 0
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_BITS 1
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OVERRIDE_AUTO_PD_WAR_SHIFT 4

/* switch :: PAGE_00_NEW_CTRL :: PAGE_00_NEW_CTRL_CABLE_DIAG_LEN [03:03] */
#define Wr_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_CABLE_DIAG_LEN(x) WriteRegBits(SWITCH_PAGE_00_NEW_CTRL,0x8,3,x)
#define Rd_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_CABLE_DIAG_LEN(x) ReadRegBits(SWITCH_PAGE_00_NEW_CTRL,0x8,3)
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_CABLE_DIAG_LEN_MASK 0x08
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_CABLE_DIAG_LEN_ALIGN 0
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_CABLE_DIAG_LEN_BITS 1
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_CABLE_DIAG_LEN_SHIFT 3

/* switch :: PAGE_00_NEW_CTRL :: PAGE_00_NEW_CTRL_INRANGEERR_DISCARD [02:02] */
#define Wr_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_INRANGEERR_DISCARD(x) WriteRegBits(SWITCH_PAGE_00_NEW_CTRL,0x4,2,x)
#define Rd_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_INRANGEERR_DISCARD(x) ReadRegBits(SWITCH_PAGE_00_NEW_CTRL,0x4,2)
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_INRANGEERR_DISCARD_MASK 0x04
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_INRANGEERR_DISCARD_ALIGN 0
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_INRANGEERR_DISCARD_BITS 1
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_INRANGEERR_DISCARD_SHIFT 2

/* switch :: PAGE_00_NEW_CTRL :: PAGE_00_NEW_CTRL_OUTRANGEERR_DISCARD [01:01] */
#define Wr_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OUTRANGEERR_DISCARD(x) WriteRegBits(SWITCH_PAGE_00_NEW_CTRL,0x2,1,x)
#define Rd_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OUTRANGEERR_DISCARD(x) ReadRegBits(SWITCH_PAGE_00_NEW_CTRL,0x2,1)
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OUTRANGEERR_DISCARD_MASK 0x02
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OUTRANGEERR_DISCARD_ALIGN 0
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OUTRANGEERR_DISCARD_BITS 1
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_OUTRANGEERR_DISCARD_SHIFT 1

/* switch :: PAGE_00_NEW_CTRL :: PAGE_00_NEW_CTRL_IP_MC [00:00] */
#define Wr_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_IP_MC(x) WriteRegBits(SWITCH_PAGE_00_NEW_CTRL,0x1,0,x)
#define Rd_switch_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_IP_MC(x) ReadRegBits(SWITCH_PAGE_00_NEW_CTRL,0x1,0)
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_IP_MC_MASK        0x01
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_IP_MC_ALIGN       0
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_IP_MC_BITS        1
#define SWITCH_PAGE_00_NEW_CTRL_PAGE_00_NEW_CTRL_IP_MC_SHIFT       0


/****************************************************************************
 * switch :: PAGE_00_SWITCH_CTRL
 ***************************************************************************/
/* switch :: PAGE_00_SWITCH_CTRL :: PAGE_00_SWITCH_CTRL_RESERVED_1 [15:07] */
#define Wr_switch_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_00_SWITCH_CTRL,0xff80,7,x)
#define Rd_switch_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_00_SWITCH_CTRL,0xff80,7)
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_1_MASK 0xff80
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_1_BITS 9
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_1_SHIFT 7

/* switch :: PAGE_00_SWITCH_CTRL :: PAGE_00_SWITCH_CTRL_MII_DUMB_FWDG_EN [06:06] */
#define Wr_switch_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_MII_DUMB_FWDG_EN(x) WriteRegBits16(SWITCH_PAGE_00_SWITCH_CTRL,0x40,6,x)
#define Rd_switch_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_MII_DUMB_FWDG_EN(x) ReadRegBits16(SWITCH_PAGE_00_SWITCH_CTRL,0x40,6)
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_MII_DUMB_FWDG_EN_MASK 0x0040
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_MII_DUMB_FWDG_EN_ALIGN 0
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_MII_DUMB_FWDG_EN_BITS 1
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_MII_DUMB_FWDG_EN_SHIFT 6

/* switch :: PAGE_00_SWITCH_CTRL :: PAGE_00_SWITCH_CTRL_RESERVED_0 [05:00] */
#define Wr_switch_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_00_SWITCH_CTRL,0x3f,0,x)
#define Rd_switch_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_00_SWITCH_CTRL,0x3f,0)
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_0_MASK 0x003f
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_0_BITS 6
#define SWITCH_PAGE_00_SWITCH_CTRL_PAGE_00_SWITCH_CTRL_RESERVED_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_PROTECTED_SEL
 ***************************************************************************/
/* switch :: PAGE_00_PROTECTED_SEL :: PAGE_00_PROTECTED_SEL_RESERVED [15:09] */
#define Wr_switch_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_PROTECTED_SEL,0xfe00,9,x)
#define Rd_switch_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_PROTECTED_SEL,0xfe00,9)
#define SWITCH_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_RESERVED_BITS 7
#define SWITCH_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_RESERVED_SHIFT 9

/* switch :: PAGE_00_PROTECTED_SEL :: PAGE_00_PROTECTED_SEL_PORT_SEL [08:00] */
#define Wr_switch_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_PORT_SEL(x) WriteRegBits16(SWITCH_PAGE_00_PROTECTED_SEL,0x1ff,0,x)
#define Rd_switch_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_PORT_SEL(x) ReadRegBits16(SWITCH_PAGE_00_PROTECTED_SEL,0x1ff,0)
#define SWITCH_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_PORT_SEL_MASK 0x01ff
#define SWITCH_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_PORT_SEL_ALIGN 0
#define SWITCH_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_PORT_SEL_BITS 9
#define SWITCH_PAGE_00_PROTECTED_SEL_PAGE_00_PROTECTED_SEL_PORT_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_WAN_PORT_SEL
 ***************************************************************************/
/* switch :: PAGE_00_WAN_PORT_SEL :: PAGE_00_WAN_PORT_SEL_RESERVED_1 [15:10] */
#define Wr_switch_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_00_WAN_PORT_SEL,0xfc00,10,x)
#define Rd_switch_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_00_WAN_PORT_SEL,0xfc00,10)
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_1_MASK 0xfc00
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_1_BITS 6
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_1_SHIFT 10

/* switch :: PAGE_00_WAN_PORT_SEL :: PAGE_00_WAN_PORT_SEL_EN_MAN2WAN [09:09] */
#define Wr_switch_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_EN_MAN2WAN(x) WriteRegBits16(SWITCH_PAGE_00_WAN_PORT_SEL,0x200,9,x)
#define Rd_switch_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_EN_MAN2WAN(x) ReadRegBits16(SWITCH_PAGE_00_WAN_PORT_SEL,0x200,9)
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_EN_MAN2WAN_MASK 0x0200
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_EN_MAN2WAN_ALIGN 0
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_EN_MAN2WAN_BITS 1
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_EN_MAN2WAN_SHIFT 9

/* switch :: PAGE_00_WAN_PORT_SEL :: PAGE_00_WAN_PORT_SEL_RESERVED_0 [08:08] */
#define Wr_switch_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_00_WAN_PORT_SEL,0x100,8,x)
#define Rd_switch_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_00_WAN_PORT_SEL,0x100,8)
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_0_MASK 0x0100
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_0_BITS 1
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_RESERVED_0_SHIFT 8

/* switch :: PAGE_00_WAN_PORT_SEL :: PAGE_00_WAN_PORT_SEL_WAN_SELECT [07:00] */
#define Wr_switch_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_WAN_SELECT(x) WriteRegBits16(SWITCH_PAGE_00_WAN_PORT_SEL,0xff,0,x)
#define Rd_switch_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_WAN_SELECT(x) ReadRegBits16(SWITCH_PAGE_00_WAN_PORT_SEL,0xff,0)
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_WAN_SELECT_MASK 0x00ff
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_WAN_SELECT_ALIGN 0
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_WAN_SELECT_BITS 8
#define SWITCH_PAGE_00_WAN_PORT_SEL_PAGE_00_WAN_PORT_SEL_WAN_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_RSV_MCAST_CTRL
 ***************************************************************************/
/* switch :: PAGE_00_RSV_MCAST_CTRL :: PAGE_00_RSV_MCAST_CTRL_EN_RES_MUL_LEARN [07:07] */
#define Wr_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_RES_MUL_LEARN(x) WriteRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x80,7,x)
#define Rd_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_RES_MUL_LEARN(x) ReadRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x80,7)
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_MASK 0x80
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_ALIGN 0
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_BITS 1
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_RES_MUL_LEARN_SHIFT 7

/* switch :: PAGE_00_RSV_MCAST_CTRL :: PAGE_00_RSV_MCAST_CTRL_RESERVED [06:05] */
#define Wr_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x60,5,x)
#define Rd_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x60,5)
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_RESERVED_MASK 0x60
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_RESERVED_BITS 2
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_RESERVED_SHIFT 5

/* switch :: PAGE_00_RSV_MCAST_CTRL :: PAGE_00_RSV_MCAST_CTRL_EN_MUL_4 [04:04] */
#define Wr_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_4(x) WriteRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x10,4,x)
#define Rd_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_4(x) ReadRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x10,4)
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_4_MASK 0x10
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_4_ALIGN 0
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_4_BITS 1
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_4_SHIFT 4

/* switch :: PAGE_00_RSV_MCAST_CTRL :: PAGE_00_RSV_MCAST_CTRL_EN_MUL_3 [03:03] */
#define Wr_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_3(x) WriteRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x8,3,x)
#define Rd_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_3(x) ReadRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x8,3)
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_3_MASK 0x08
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_3_ALIGN 0
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_3_BITS 1
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_3_SHIFT 3

/* switch :: PAGE_00_RSV_MCAST_CTRL :: PAGE_00_RSV_MCAST_CTRL_EN_MUL_2 [02:02] */
#define Wr_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_2(x) WriteRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x4,2,x)
#define Rd_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_2(x) ReadRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x4,2)
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_2_MASK 0x04
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_2_ALIGN 0
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_2_BITS 1
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_2_SHIFT 2

/* switch :: PAGE_00_RSV_MCAST_CTRL :: PAGE_00_RSV_MCAST_CTRL_EN_MUL_1 [01:01] */
#define Wr_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_1(x) WriteRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x2,1,x)
#define Rd_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_1(x) ReadRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x2,1)
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_1_MASK 0x02
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_1_ALIGN 0
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_1_BITS 1
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_1_SHIFT 1

/* switch :: PAGE_00_RSV_MCAST_CTRL :: PAGE_00_RSV_MCAST_CTRL_EN_MUL_0 [00:00] */
#define Wr_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_0(x) WriteRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x1,0,x)
#define Rd_switch_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_0(x) ReadRegBits(SWITCH_PAGE_00_RSV_MCAST_CTRL,0x1,0)
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_0_MASK 0x01
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_0_ALIGN 0
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_0_BITS 1
#define SWITCH_PAGE_00_RSV_MCAST_CTRL_PAGE_00_RSV_MCAST_CTRL_EN_MUL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_TXQ_FLUSH_MODE
 ***************************************************************************/
/* switch :: PAGE_00_TXQ_FLUSH_MODE :: PAGE_00_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED [07:07] */
#define Wr_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED(x) WriteRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x80,7,x)
#define Rd_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED(x) ReadRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x80,7)
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_MASK 0x80
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_ALIGN 0
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_BITS 1
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_NEW_BOFF_SEED_SHIFT 7

/* switch :: PAGE_00_TXQ_FLUSH_MODE :: PAGE_00_TXQ_FLUSH_MODE_EN_LATECOl65_DROP [06:06] */
#define Wr_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LATECOl65_DROP(x) WriteRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x40,6,x)
#define Rd_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LATECOl65_DROP(x) ReadRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x40,6)
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LATECOL65_DROP_MASK 0x40
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LATECOL65_DROP_ALIGN 0
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LATECOL65_DROP_BITS 1
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LATECOL65_DROP_SHIFT 6

/* switch :: PAGE_00_TXQ_FLUSH_MODE :: PAGE_00_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK [05:05] */
#define Wr_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK(x) WriteRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x20,5,x)
#define Rd_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK(x) ReadRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x20,5)
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_MASK 0x20
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_ALIGN 0
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_BITS 1
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_ECOL_TXFM_MASK_SHIFT 5

/* switch :: PAGE_00_TXQ_FLUSH_MODE :: PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK [04:04] */
#define Wr_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK(x) WriteRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x10,4,x)
#define Rd_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK(x) ReadRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x10,4)
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_MASK 0x10
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_ALIGN 0
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_BITS 1
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_TXFM_MASK_SHIFT 4

/* switch :: PAGE_00_TXQ_FLUSH_MODE :: PAGE_00_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH [03:03] */
#define Wr_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH(x) WriteRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x8,3,x)
#define Rd_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH(x) ReadRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x8,3)
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_MASK 0x08
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_ALIGN 0
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_BITS 1
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_RELOAD_ERR_PATH_SHIFT 3

/* switch :: PAGE_00_TXQ_FLUSH_MODE :: PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_FLUSH [02:02] */
#define Wr_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_FLUSH(x) WriteRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x4,2,x)
#define Rd_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_FLUSH(x) ReadRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x4,2)
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_MASK 0x04
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_ALIGN 0
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_BITS 1
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_EN_LCOL_FLUSH_SHIFT 2

/* switch :: PAGE_00_TXQ_FLUSH_MODE :: PAGE_00_TXQ_FLUSH_MODE_DIS_NEW_TXDIS [01:01] */
#define Wr_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_DIS_NEW_TXDIS(x) WriteRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x2,1,x)
#define Rd_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_DIS_NEW_TXDIS(x) ReadRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x2,1)
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_MASK 0x02
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_ALIGN 0
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_BITS 1
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_DIS_NEW_TXDIS_SHIFT 1

/* switch :: PAGE_00_TXQ_FLUSH_MODE :: PAGE_00_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH [00:00] */
#define Wr_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH(x) WriteRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x1,0,x)
#define Rd_switch_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH(x) ReadRegBits(SWITCH_PAGE_00_TXQ_FLUSH_MODE,0x1,0)
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_MASK 0x01
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_ALIGN 0
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_BITS 1
#define SWITCH_PAGE_00_TXQ_FLUSH_MODE_PAGE_00_TXQ_FLUSH_MODE_BYPASS_FASTTXDSC_PATH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_ULF_DROP_MAP
 ***************************************************************************/
/* switch :: PAGE_00_ULF_DROP_MAP :: PAGE_00_ULF_DROP_MAP_RESERVED [15:09] */
#define Wr_switch_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_ULF_DROP_MAP,0xfe00,9,x)
#define Rd_switch_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_ULF_DROP_MAP,0xfe00,9)
#define SWITCH_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_RESERVED_BITS 7
#define SWITCH_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_RESERVED_SHIFT 9

/* switch :: PAGE_00_ULF_DROP_MAP :: PAGE_00_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP [08:00] */
#define Wr_switch_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP(x) WriteRegBits16(SWITCH_PAGE_00_ULF_DROP_MAP,0x1ff,0,x)
#define Rd_switch_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP(x) ReadRegBits16(SWITCH_PAGE_00_ULF_DROP_MAP,0x1ff,0)
#define SWITCH_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_MASK 0x01ff
#define SWITCH_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_ALIGN 0
#define SWITCH_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_BITS 9
#define SWITCH_PAGE_00_ULF_DROP_MAP_PAGE_00_ULF_DROP_MAP_UNI_LOOKUP_FAIL_FWD_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_MLF_DROP_MAP
 ***************************************************************************/
/* switch :: PAGE_00_MLF_DROP_MAP :: PAGE_00_MLF_DROP_MAP_RESERVED [15:09] */
#define Wr_switch_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_MLF_DROP_MAP,0xfe00,9,x)
#define Rd_switch_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_MLF_DROP_MAP,0xfe00,9)
#define SWITCH_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_RESERVED_BITS 7
#define SWITCH_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_RESERVED_SHIFT 9

/* switch :: PAGE_00_MLF_DROP_MAP :: PAGE_00_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP [08:00] */
#define Wr_switch_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP(x) WriteRegBits16(SWITCH_PAGE_00_MLF_DROP_MAP,0x1ff,0,x)
#define Rd_switch_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP(x) ReadRegBits16(SWITCH_PAGE_00_MLF_DROP_MAP,0x1ff,0)
#define SWITCH_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_MASK 0x01ff
#define SWITCH_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_ALIGN 0
#define SWITCH_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_BITS 9
#define SWITCH_PAGE_00_MLF_DROP_MAP_PAGE_00_MLF_DROP_MAP_MUL_LOOKUP_FAIL_FRW_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_MLF_IPMC_FWD_MAP
 ***************************************************************************/
/* switch :: PAGE_00_MLF_IPMC_FWD_MAP :: PAGE_00_MLF_IPMC_FWD_MAP_RESERVED [15:09] */
#define Wr_switch_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_MLF_IPMC_FWD_MAP,0xfe00,9,x)
#define Rd_switch_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_MLF_IPMC_FWD_MAP,0xfe00,9)
#define SWITCH_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_RESERVED_BITS 7
#define SWITCH_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_RESERVED_SHIFT 9

/* switch :: PAGE_00_MLF_IPMC_FWD_MAP :: PAGE_00_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP [08:00] */
#define Wr_switch_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP(x) WriteRegBits16(SWITCH_PAGE_00_MLF_IPMC_FWD_MAP,0x1ff,0,x)
#define Rd_switch_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP(x) ReadRegBits16(SWITCH_PAGE_00_MLF_IPMC_FWD_MAP,0x1ff,0)
#define SWITCH_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_MASK 0x01ff
#define SWITCH_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_ALIGN 0
#define SWITCH_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_BITS 9
#define SWITCH_PAGE_00_MLF_IPMC_FWD_MAP_PAGE_00_MLF_IPMC_FWD_MAP_MLF_IPMC_FWD_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_RX_PAUSE_PASS
 ***************************************************************************/
/* switch :: PAGE_00_RX_PAUSE_PASS :: PAGE_00_RX_PAUSE_PASS_RESERVED_1 [15:09] */
#define Wr_switch_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_00_RX_PAUSE_PASS,0xfe00,9,x)
#define Rd_switch_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_00_RX_PAUSE_PASS,0xfe00,9)
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_1_MASK 0xfe00
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_1_BITS 7
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_1_SHIFT 9

/* switch :: PAGE_00_RX_PAUSE_PASS :: PAGE_00_RX_PAUSE_PASS_RESERVED_0 [08:08] */
#define Wr_switch_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_00_RX_PAUSE_PASS,0x100,8,x)
#define Rd_switch_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_00_RX_PAUSE_PASS,0x100,8)
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_0_MASK 0x0100
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_0_BITS 1
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RESERVED_0_SHIFT 8

/* switch :: PAGE_00_RX_PAUSE_PASS :: PAGE_00_RX_PAUSE_PASS_RX_PAUSE_PASS [07:00] */
#define Wr_switch_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RX_PAUSE_PASS(x) WriteRegBits16(SWITCH_PAGE_00_RX_PAUSE_PASS,0xff,0,x)
#define Rd_switch_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RX_PAUSE_PASS(x) ReadRegBits16(SWITCH_PAGE_00_RX_PAUSE_PASS,0xff,0)
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RX_PAUSE_PASS_MASK 0x00ff
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RX_PAUSE_PASS_ALIGN 0
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RX_PAUSE_PASS_BITS 8
#define SWITCH_PAGE_00_RX_PAUSE_PASS_PAGE_00_RX_PAUSE_PASS_RX_PAUSE_PASS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_TX_PAUSE_PASS
 ***************************************************************************/
/* switch :: PAGE_00_TX_PAUSE_PASS :: PAGE_00_TX_PAUSE_PASS_RESERVED [15:09] */
#define Wr_switch_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_TX_PAUSE_PASS,0xfe00,9,x)
#define Rd_switch_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_TX_PAUSE_PASS,0xfe00,9)
#define SWITCH_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_RESERVED_BITS 7
#define SWITCH_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_RESERVED_SHIFT 9

/* switch :: PAGE_00_TX_PAUSE_PASS :: PAGE_00_TX_PAUSE_PASS_TX_PAUSE_PASS [08:00] */
#define Wr_switch_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_TX_PAUSE_PASS(x) WriteRegBits16(SWITCH_PAGE_00_TX_PAUSE_PASS,0x1ff,0,x)
#define Rd_switch_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_TX_PAUSE_PASS(x) ReadRegBits16(SWITCH_PAGE_00_TX_PAUSE_PASS,0x1ff,0)
#define SWITCH_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_TX_PAUSE_PASS_MASK 0x01ff
#define SWITCH_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_TX_PAUSE_PASS_ALIGN 0
#define SWITCH_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_TX_PAUSE_PASS_BITS 9
#define SWITCH_PAGE_00_TX_PAUSE_PASS_PAGE_00_TX_PAUSE_PASS_TX_PAUSE_PASS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_DIS_LEARN
 ***************************************************************************/
/* switch :: PAGE_00_DIS_LEARN :: PAGE_00_DIS_LEARN_RESERVED [15:09] */
#define Wr_switch_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_DIS_LEARN,0xfe00,9,x)
#define Rd_switch_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_DIS_LEARN,0xfe00,9)
#define SWITCH_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_RESERVED_MASK   0xfe00
#define SWITCH_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_RESERVED_ALIGN  0
#define SWITCH_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_RESERVED_BITS   7
#define SWITCH_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_RESERVED_SHIFT  9

/* switch :: PAGE_00_DIS_LEARN :: PAGE_00_DIS_LEARN_DIS_LEARN [08:00] */
#define Wr_switch_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_DIS_LEARN(x) WriteRegBits16(SWITCH_PAGE_00_DIS_LEARN,0x1ff,0,x)
#define Rd_switch_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_DIS_LEARN(x) ReadRegBits16(SWITCH_PAGE_00_DIS_LEARN,0x1ff,0)
#define SWITCH_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_DIS_LEARN_MASK  0x01ff
#define SWITCH_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_DIS_LEARN_ALIGN 0
#define SWITCH_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_DIS_LEARN_BITS  9
#define SWITCH_PAGE_00_DIS_LEARN_PAGE_00_DIS_LEARN_DIS_LEARN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_SFT_LRN_CTL
 ***************************************************************************/
/* switch :: PAGE_00_SFT_LRN_CTL :: PAGE_00_SFT_LRN_CTL_RESERVED [15:09] */
#define Wr_switch_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_SFT_LRN_CTL,0xfe00,9,x)
#define Rd_switch_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_SFT_LRN_CTL,0xfe00,9)
#define SWITCH_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_RESERVED_BITS 7
#define SWITCH_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_RESERVED_SHIFT 9

/* switch :: PAGE_00_SFT_LRN_CTL :: PAGE_00_SFT_LRN_CTL_SW_LEARN_CNTL [08:00] */
#define Wr_switch_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_SW_LEARN_CNTL(x) WriteRegBits16(SWITCH_PAGE_00_SFT_LRN_CTL,0x1ff,0,x)
#define Rd_switch_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_SW_LEARN_CNTL(x) ReadRegBits16(SWITCH_PAGE_00_SFT_LRN_CTL,0x1ff,0)
#define SWITCH_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_SW_LEARN_CNTL_MASK 0x01ff
#define SWITCH_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_SW_LEARN_CNTL_ALIGN 0
#define SWITCH_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_SW_LEARN_CNTL_BITS 9
#define SWITCH_PAGE_00_SFT_LRN_CTL_PAGE_00_SFT_LRN_CTL_SW_LEARN_CNTL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LOW_POWER_EXP1
 ***************************************************************************/
/* switch :: PAGE_00_LOW_POWER_EXP1 :: PAGE_00_LOW_POWER_EXP1_RESERVED_1 [31:25] */
#define Wr_switch_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_00_LOW_POWER_EXP1,0xfe000000,25,x)
#define Rd_switch_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_00_LOW_POWER_EXP1,0xfe000000,25)
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_1_MASK 0xfe000000
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_1_BITS 7
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_1_SHIFT 25

/* switch :: PAGE_00_LOW_POWER_EXP1 :: PAGE_00_LOW_POWER_EXP1_SLEEP_MACCLK_PORT [24:16] */
#define Wr_switch_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_MACCLK_PORT(x) WriteRegBits(SWITCH_PAGE_00_LOW_POWER_EXP1,0x1ff0000,16,x)
#define Rd_switch_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_MACCLK_PORT(x) ReadRegBits(SWITCH_PAGE_00_LOW_POWER_EXP1,0x1ff0000,16)
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_MASK 0x01ff0000
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_ALIGN 0
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_BITS 9
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_MACCLK_PORT_SHIFT 16

/* switch :: PAGE_00_LOW_POWER_EXP1 :: PAGE_00_LOW_POWER_EXP1_RESERVED_0 [15:09] */
#define Wr_switch_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_00_LOW_POWER_EXP1,0xfe00,9,x)
#define Rd_switch_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_00_LOW_POWER_EXP1,0xfe00,9)
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_0_MASK 0x0000fe00
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_0_BITS 7
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_RESERVED_0_SHIFT 9

/* switch :: PAGE_00_LOW_POWER_EXP1 :: PAGE_00_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT [08:00] */
#define Wr_switch_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT(x) WriteRegBits(SWITCH_PAGE_00_LOW_POWER_EXP1,0x1ff,0,x)
#define Rd_switch_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT(x) ReadRegBits(SWITCH_PAGE_00_LOW_POWER_EXP1,0x1ff,0)
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_MASK 0x000001ff
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_ALIGN 0
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_BITS 9
#define SWITCH_PAGE_00_LOW_POWER_EXP1_PAGE_00_LOW_POWER_EXP1_SLEEP_SYSCLK_PORT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_PHY_INT_STS
 ***************************************************************************/
/* switch :: PAGE_00_PHY_INT_STS :: PAGE_00_PHY_INT_STS_CFP_TCAM_CHKSUM_ERR_MIR [15:15] */
#define Wr_switch_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_CFP_TCAM_CHKSUM_ERR_MIR(x) WriteRegBits16(SWITCH_PAGE_00_PHY_INT_STS,0x8000,15,x)
#define Rd_switch_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_CFP_TCAM_CHKSUM_ERR_MIR(x) ReadRegBits16(SWITCH_PAGE_00_PHY_INT_STS,0x8000,15)
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_CFP_TCAM_CHKSUM_ERR_MIR_MASK 0x8000
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_CFP_TCAM_CHKSUM_ERR_MIR_ALIGN 0
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_CFP_TCAM_CHKSUM_ERR_MIR_BITS 1
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_CFP_TCAM_CHKSUM_ERR_MIR_SHIFT 15

/* switch :: PAGE_00_PHY_INT_STS :: PAGE_00_PHY_INT_STS_RESERVED [14:01] */
#define Wr_switch_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_PHY_INT_STS,0x7ffe,1,x)
#define Rd_switch_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_PHY_INT_STS,0x7ffe,1)
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_RESERVED_MASK 0x7ffe
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_RESERVED_BITS 14
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_RESERVED_SHIFT 1

/* switch :: PAGE_00_PHY_INT_STS :: PAGE_00_PHY_INT_STS_ALL_PHY_INT_STS [00:00] */
#define Wr_switch_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_ALL_PHY_INT_STS(x) WriteRegBits16(SWITCH_PAGE_00_PHY_INT_STS,0x1,0,x)
#define Rd_switch_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_ALL_PHY_INT_STS(x) ReadRegBits16(SWITCH_PAGE_00_PHY_INT_STS,0x1,0)
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_ALL_PHY_INT_STS_MASK 0x0001
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_ALL_PHY_INT_STS_ALIGN 0
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_ALL_PHY_INT_STS_BITS 1
#define SWITCH_PAGE_00_PHY_INT_STS_PAGE_00_PHY_INT_STS_ALL_PHY_INT_STS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_CTLREG_REG_SPARE
 ***************************************************************************/
/* switch :: PAGE_00_CTLREG_REG_SPARE :: PAGE_00_CTLREG_REG_SPARE_CTLREG_REG_SPARE [31:00] */
#define Wr_switch_PAGE_00_CTLREG_REG_SPARE_PAGE_00_CTLREG_REG_SPARE_CTLREG_REG_SPARE(x) WriteReg(SWITCH_PAGE_00_CTLREG_REG_SPARE,x)
#define Rd_switch_PAGE_00_CTLREG_REG_SPARE_PAGE_00_CTLREG_REG_SPARE_CTLREG_REG_SPARE(x) ReadReg(SWITCH_PAGE_00_CTLREG_REG_SPARE)
#define SWITCH_PAGE_00_CTLREG_REG_SPARE_PAGE_00_CTLREG_REG_SPARE_CTLREG_REG_SPARE_MASK 0xffffffff
#define SWITCH_PAGE_00_CTLREG_REG_SPARE_PAGE_00_CTLREG_REG_SPARE_CTLREG_REG_SPARE_ALIGN 0
#define SWITCH_PAGE_00_CTLREG_REG_SPARE_PAGE_00_CTLREG_REG_SPARE_CTLREG_REG_SPARE_BITS 32
#define SWITCH_PAGE_00_CTLREG_REG_SPARE_PAGE_00_CTLREG_REG_SPARE_CTLREG_REG_SPARE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_WATCH_DOG_RPT1
 ***************************************************************************/
/* switch :: PAGE_00_WATCH_DOG_RPT1 :: PAGE_00_WATCH_DOG_RPT1_RESERVED [15:09] */
#define Wr_switch_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT1,0xfe00,9,x)
#define Rd_switch_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT1,0xfe00,9)
#define SWITCH_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_RESERVED_BITS 7
#define SWITCH_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_RESERVED_SHIFT 9

/* switch :: PAGE_00_WATCH_DOG_RPT1 :: PAGE_00_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR [08:00] */
#define Wr_switch_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR(x) WriteRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT1,0x1ff,0,x)
#define Rd_switch_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR(x) ReadRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT1,0x1ff,0)
#define SWITCH_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_MASK 0x01ff
#define SWITCH_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_ALIGN 0
#define SWITCH_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_BITS 9
#define SWITCH_PAGE_00_WATCH_DOG_RPT1_PAGE_00_WATCH_DOG_RPT1_TX_PORT_HUNG_INDICATOR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_WATCH_DOG_RPT2
 ***************************************************************************/
/* switch :: PAGE_00_WATCH_DOG_RPT2 :: PAGE_00_WATCH_DOG_RPT2_RESERVED [15:09] */
#define Wr_switch_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT2,0xfe00,9,x)
#define Rd_switch_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT2,0xfe00,9)
#define SWITCH_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RESERVED_BITS 7
#define SWITCH_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RESERVED_SHIFT 9

/* switch :: PAGE_00_WATCH_DOG_RPT2 :: PAGE_00_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR [08:00] */
#define Wr_switch_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR(x) WriteRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT2,0x1ff,0,x)
#define Rd_switch_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR(x) ReadRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT2,0x1ff,0)
#define SWITCH_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_MASK 0x01ff
#define SWITCH_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_ALIGN 0
#define SWITCH_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_BITS 9
#define SWITCH_PAGE_00_WATCH_DOG_RPT2_PAGE_00_WATCH_DOG_RPT2_RX_PORT_HUNG_INDICATOR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_WATCH_DOG_RPT3
 ***************************************************************************/
/* switch :: PAGE_00_WATCH_DOG_RPT3 :: PAGE_00_WATCH_DOG_RPT3_RESERVED [15:09] */
#define Wr_switch_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT3,0xfe00,9,x)
#define Rd_switch_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT3,0xfe00,9)
#define SWITCH_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_RESERVED_BITS 7
#define SWITCH_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_RESERVED_SHIFT 9

/* switch :: PAGE_00_WATCH_DOG_RPT3 :: PAGE_00_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR [08:00] */
#define Wr_switch_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR(x) WriteRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT3,0x1ff,0,x)
#define Rd_switch_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR(x) ReadRegBits16(SWITCH_PAGE_00_WATCH_DOG_RPT3,0x1ff,0)
#define SWITCH_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_MASK 0x01ff
#define SWITCH_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_ALIGN 0
#define SWITCH_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_BITS 9
#define SWITCH_PAGE_00_WATCH_DOG_RPT3_PAGE_00_WATCH_DOG_RPT3_ARL_HUNG_INDICATOR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_PAUSE_FRM_CTRL
 ***************************************************************************/
/* switch :: PAGE_00_PAUSE_FRM_CTRL :: PAGE_00_PAUSE_FRM_CTRL_RESERVED_2 [07:03] */
#define Wr_switch_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_00_PAUSE_FRM_CTRL,0xf8,3,x)
#define Rd_switch_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_00_PAUSE_FRM_CTRL,0xf8,3)
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_2_MASK 0xf8
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_2_BITS 5
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_2_SHIFT 3

/* switch :: PAGE_00_PAUSE_FRM_CTRL :: PAGE_00_PAUSE_FRM_CTRL_RESERVED_1 [02:01] */
#define Wr_switch_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_00_PAUSE_FRM_CTRL,0x6,1,x)
#define Rd_switch_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_00_PAUSE_FRM_CTRL,0x6,1)
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_1_MASK 0x06
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_1_BITS 2
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_RESERVED_1_SHIFT 1

/* switch :: PAGE_00_PAUSE_FRM_CTRL :: PAGE_00_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA [00:00] */
#define Wr_switch_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA(x) WriteRegBits(SWITCH_PAGE_00_PAUSE_FRM_CTRL,0x1,0,x)
#define Rd_switch_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA(x) ReadRegBits(SWITCH_PAGE_00_PAUSE_FRM_CTRL,0x1,0)
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_MASK 0x01
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_ALIGN 0
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_BITS 1
#define SWITCH_PAGE_00_PAUSE_FRM_CTRL_PAGE_00_PAUSE_FRM_CTRL_PAUSE_IGNORE_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_PAUSE_ST_ADDR
 ***************************************************************************/
/* switch :: PAGE_00_PAUSE_ST_ADDR :: reserved0 [63:48] */
#define SWITCH_PAGE_00_PAUSE_ST_ADDR_RESERVED0_MASK                0xffff000000000000
#define SWITCH_PAGE_00_PAUSE_ST_ADDR_RESERVED0_ALIGN               0
#define SWITCH_PAGE_00_PAUSE_ST_ADDR_RESERVED0_BITS                16
#define SWITCH_PAGE_00_PAUSE_ST_ADDR_RESERVED0_SHIFT               48

/* switch :: PAGE_00_PAUSE_ST_ADDR :: PAGE_00_PAUSE_ST_ADDR_PAUSE_ST_ADDR [47:00] */
#define Wr_switch_PAGE_00_PAUSE_ST_ADDR_PAGE_00_PAUSE_ST_ADDR_PAUSE_ST_ADDR(x) WriteRegBits(SWITCH_PAGE_00_PAUSE_ST_ADDR,0xffffffffffff,0,x)
#define Rd_switch_PAGE_00_PAUSE_ST_ADDR_PAGE_00_PAUSE_ST_ADDR_PAUSE_ST_ADDR(x) ReadRegBits(SWITCH_PAGE_00_PAUSE_ST_ADDR,0xffffffffffff,0)
#define SWITCH_PAGE_00_PAUSE_ST_ADDR_PAGE_00_PAUSE_ST_ADDR_PAUSE_ST_ADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_00_PAUSE_ST_ADDR_PAGE_00_PAUSE_ST_ADDR_PAUSE_ST_ADDR_ALIGN 0
#define SWITCH_PAGE_00_PAUSE_ST_ADDR_PAGE_00_PAUSE_ST_ADDR_PAUSE_ST_ADDR_BITS 48
#define SWITCH_PAGE_00_PAUSE_ST_ADDR_PAGE_00_PAUSE_ST_ADDR_PAUSE_ST_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_FAST_AGE_CTRL
 ***************************************************************************/
/* switch :: PAGE_00_FAST_AGE_CTRL :: PAGE_00_FAST_AGE_CTRL_FAST_AGE_STR_DONE [07:07] */
#define Wr_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_FAST_AGE_STR_DONE(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x80,7,x)
#define Rd_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_FAST_AGE_STR_DONE(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x80,7)
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_FAST_AGE_STR_DONE_MASK 0x80
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_FAST_AGE_STR_DONE_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_FAST_AGE_STR_DONE_BITS 1
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_FAST_AGE_STR_DONE_SHIFT 7

/* switch :: PAGE_00_FAST_AGE_CTRL :: PAGE_00_FAST_AGE_CTRL_RESERVED [06:06] */
#define Wr_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x40,6,x)
#define Rd_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x40,6)
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_RESERVED_MASK 0x40
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_RESERVED_BITS 1
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_RESERVED_SHIFT 6

/* switch :: PAGE_00_FAST_AGE_CTRL :: PAGE_00_FAST_AGE_CTRL_EN_AGE_MCAST [05:05] */
#define Wr_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_MCAST(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x20,5,x)
#define Rd_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_MCAST(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x20,5)
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_MCAST_MASK 0x20
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_MCAST_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_MCAST_BITS 1
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_MCAST_SHIFT 5

/* switch :: PAGE_00_FAST_AGE_CTRL :: PAGE_00_FAST_AGE_CTRL_EN_AGE_SPT [04:04] */
#define Wr_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_SPT(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x10,4,x)
#define Rd_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_SPT(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x10,4)
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_SPT_MASK 0x10
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_SPT_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_SPT_BITS 1
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_SPT_SHIFT 4

/* switch :: PAGE_00_FAST_AGE_CTRL :: PAGE_00_FAST_AGE_CTRL_EN_AGE_VLAN [03:03] */
#define Wr_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_VLAN(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x8,3,x)
#define Rd_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_VLAN(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x8,3)
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_VLAN_MASK 0x08
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_VLAN_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_VLAN_BITS 1
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_VLAN_SHIFT 3

/* switch :: PAGE_00_FAST_AGE_CTRL :: PAGE_00_FAST_AGE_CTRL_EN_AGE_PORT [02:02] */
#define Wr_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_PORT(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x4,2,x)
#define Rd_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_PORT(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x4,2)
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_PORT_MASK 0x04
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_PORT_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_PORT_BITS 1
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_PORT_SHIFT 2

/* switch :: PAGE_00_FAST_AGE_CTRL :: PAGE_00_FAST_AGE_CTRL_EN_AGE_DYNAMIC [01:01] */
#define Wr_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_DYNAMIC(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x2,1,x)
#define Rd_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_DYNAMIC(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x2,1)
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_DYNAMIC_MASK 0x02
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_DYNAMIC_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_DYNAMIC_BITS 1
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_AGE_DYNAMIC_SHIFT 1

/* switch :: PAGE_00_FAST_AGE_CTRL :: PAGE_00_FAST_AGE_CTRL_EN_FAST_AGE_STATIC [00:00] */
#define Wr_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_FAST_AGE_STATIC(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x1,0,x)
#define Rd_switch_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_FAST_AGE_STATIC(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_CTRL,0x1,0)
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_MASK 0x01
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_BITS 1
#define SWITCH_PAGE_00_FAST_AGE_CTRL_PAGE_00_FAST_AGE_CTRL_EN_FAST_AGE_STATIC_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_FAST_AGE_PORT
 ***************************************************************************/
/* switch :: PAGE_00_FAST_AGE_PORT :: PAGE_00_FAST_AGE_PORT_RESERVED [07:04] */
#define Wr_switch_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_PORT,0xf0,4,x)
#define Rd_switch_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_PORT,0xf0,4)
#define SWITCH_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_RESERVED_MASK 0xf0
#define SWITCH_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_RESERVED_BITS 4
#define SWITCH_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_RESERVED_SHIFT 4

/* switch :: PAGE_00_FAST_AGE_PORT :: PAGE_00_FAST_AGE_PORT_AGE_PORT [03:00] */
#define Wr_switch_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_AGE_PORT(x) WriteRegBits(SWITCH_PAGE_00_FAST_AGE_PORT,0xf,0,x)
#define Rd_switch_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_AGE_PORT(x) ReadRegBits(SWITCH_PAGE_00_FAST_AGE_PORT,0xf,0)
#define SWITCH_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_AGE_PORT_MASK 0x0f
#define SWITCH_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_AGE_PORT_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_AGE_PORT_BITS 4
#define SWITCH_PAGE_00_FAST_AGE_PORT_PAGE_00_FAST_AGE_PORT_AGE_PORT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_FAST_AGE_VID
 ***************************************************************************/
/* switch :: PAGE_00_FAST_AGE_VID :: PAGE_00_FAST_AGE_VID_RESERVED [15:12] */
#define Wr_switch_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_FAST_AGE_VID,0xf000,12,x)
#define Rd_switch_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_FAST_AGE_VID,0xf000,12)
#define SWITCH_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_RESERVED_MASK 0xf000
#define SWITCH_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_RESERVED_BITS 4
#define SWITCH_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_RESERVED_SHIFT 12

/* switch :: PAGE_00_FAST_AGE_VID :: PAGE_00_FAST_AGE_VID_AGE_VID [11:00] */
#define Wr_switch_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_AGE_VID(x) WriteRegBits16(SWITCH_PAGE_00_FAST_AGE_VID,0xfff,0,x)
#define Rd_switch_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_AGE_VID(x) ReadRegBits16(SWITCH_PAGE_00_FAST_AGE_VID,0xfff,0)
#define SWITCH_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_AGE_VID_MASK 0x0fff
#define SWITCH_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_AGE_VID_ALIGN 0
#define SWITCH_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_AGE_VID_BITS 12
#define SWITCH_PAGE_00_FAST_AGE_VID_PAGE_00_FAST_AGE_VID_AGE_VID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LED_FUNC0_EXTD_CTL
 ***************************************************************************/
/* switch :: PAGE_00_LED_FUNC0_EXTD_CTL :: PAGE_00_LED_FUNC0_EXTD_CTL_RESERVED [15:02] */
#define Wr_switch_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL,0xfffc,2,x)
#define Rd_switch_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL,0xfffc,2)
#define SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_RESERVED_MASK 0xfffc
#define SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_RESERVED_BITS 14
#define SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_RESERVED_SHIFT 2

/* switch :: PAGE_00_LED_FUNC0_EXTD_CTL :: PAGE_00_LED_FUNC0_EXTD_CTL_LED_FUNC0_EXTD [01:00] */
#define Wr_switch_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_LED_FUNC0_EXTD(x) WriteRegBits16(SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL,0x3,0,x)
#define Rd_switch_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_LED_FUNC0_EXTD(x) ReadRegBits16(SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL,0x3,0)
#define SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_LED_FUNC0_EXTD_MASK 0x0003
#define SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_LED_FUNC0_EXTD_ALIGN 0
#define SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_LED_FUNC0_EXTD_BITS 2
#define SWITCH_PAGE_00_LED_FUNC0_EXTD_CTL_PAGE_00_LED_FUNC0_EXTD_CTL_LED_FUNC0_EXTD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LED_FUNC1_EXTD_CTL
 ***************************************************************************/
/* switch :: PAGE_00_LED_FUNC1_EXTD_CTL :: PAGE_00_LED_FUNC1_EXTD_CTL_RESERVED [15:02] */
#define Wr_switch_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL,0xfffc,2,x)
#define Rd_switch_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL,0xfffc,2)
#define SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_RESERVED_MASK 0xfffc
#define SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_RESERVED_BITS 14
#define SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_RESERVED_SHIFT 2

/* switch :: PAGE_00_LED_FUNC1_EXTD_CTL :: PAGE_00_LED_FUNC1_EXTD_CTL_LED_FUNC1_EXTD [01:00] */
#define Wr_switch_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_LED_FUNC1_EXTD(x) WriteRegBits16(SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL,0x3,0,x)
#define Rd_switch_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_LED_FUNC1_EXTD(x) ReadRegBits16(SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL,0x3,0)
#define SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_LED_FUNC1_EXTD_MASK 0x0003
#define SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_LED_FUNC1_EXTD_ALIGN 0
#define SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_LED_FUNC1_EXTD_BITS 2
#define SWITCH_PAGE_00_LED_FUNC1_EXTD_CTL_PAGE_00_LED_FUNC1_EXTD_CTL_LED_FUNC1_EXTD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LOW_POWER_CTRL
 ***************************************************************************/
/* switch :: PAGE_00_LOW_POWER_CTRL :: PAGE_00_LOW_POWER_CTRL_RESERVED_1 [15:07] */
#define Wr_switch_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_00_LOW_POWER_CTRL,0xff80,7,x)
#define Rd_switch_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_00_LOW_POWER_CTRL,0xff80,7)
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_1_MASK 0xff80
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_1_BITS 9
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_1_SHIFT 7

/* switch :: PAGE_00_LOW_POWER_CTRL :: PAGE_00_LOW_POWER_CTRL_SLEEP_SYS [06:06] */
#define Wr_switch_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_SLEEP_SYS(x) WriteRegBits16(SWITCH_PAGE_00_LOW_POWER_CTRL,0x40,6,x)
#define Rd_switch_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_SLEEP_SYS(x) ReadRegBits16(SWITCH_PAGE_00_LOW_POWER_CTRL,0x40,6)
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_SLEEP_SYS_MASK 0x0040
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_SLEEP_SYS_ALIGN 0
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_SLEEP_SYS_BITS 1
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_SLEEP_SYS_SHIFT 6

/* switch :: PAGE_00_LOW_POWER_CTRL :: PAGE_00_LOW_POWER_CTRL_TIMER_DISABLE [05:05] */
#define Wr_switch_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_TIMER_DISABLE(x) WriteRegBits16(SWITCH_PAGE_00_LOW_POWER_CTRL,0x20,5,x)
#define Rd_switch_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_TIMER_DISABLE(x) ReadRegBits16(SWITCH_PAGE_00_LOW_POWER_CTRL,0x20,5)
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_TIMER_DISABLE_MASK 0x0020
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_TIMER_DISABLE_ALIGN 0
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_TIMER_DISABLE_BITS 1
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_TIMER_DISABLE_SHIFT 5

/* switch :: PAGE_00_LOW_POWER_CTRL :: PAGE_00_LOW_POWER_CTRL_RESERVED_0 [04:00] */
#define Wr_switch_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_00_LOW_POWER_CTRL,0x1f,0,x)
#define Rd_switch_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_00_LOW_POWER_CTRL,0x1f,0)
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_0_MASK 0x001f
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_0_BITS 5
#define SWITCH_PAGE_00_LOW_POWER_CTRL_PAGE_00_LOW_POWER_CTRL_RESERVED_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_TCAM_CTRL
 ***************************************************************************/
/* switch :: PAGE_00_TCAM_CTRL :: PAGE_00_TCAM_CTRL_EN_TCAM_CHKSUM [07:07] */
#define Wr_switch_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_EN_TCAM_CHKSUM(x) WriteRegBits(SWITCH_PAGE_00_TCAM_CTRL,0x80,7,x)
#define Rd_switch_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_EN_TCAM_CHKSUM(x) ReadRegBits(SWITCH_PAGE_00_TCAM_CTRL,0x80,7)
#define SWITCH_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_EN_TCAM_CHKSUM_MASK 0x80
#define SWITCH_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_EN_TCAM_CHKSUM_ALIGN 0
#define SWITCH_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_EN_TCAM_CHKSUM_BITS 1
#define SWITCH_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_EN_TCAM_CHKSUM_SHIFT 7

/* switch :: PAGE_00_TCAM_CTRL :: PAGE_00_TCAM_CTRL_RESERVED [06:00] */
#define Wr_switch_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_TCAM_CTRL,0x7f,0,x)
#define Rd_switch_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_TCAM_CTRL,0x7f,0)
#define SWITCH_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_RESERVED_MASK   0x7f
#define SWITCH_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_RESERVED_ALIGN  0
#define SWITCH_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_RESERVED_BITS   7
#define SWITCH_PAGE_00_TCAM_CTRL_PAGE_00_TCAM_CTRL_RESERVED_SHIFT  0


/****************************************************************************
 * switch :: PAGE_00_TCAM_CHKSUM_STS
 ***************************************************************************/
/* switch :: PAGE_00_TCAM_CHKSUM_STS :: PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR [15:15] */
#define Wr_switch_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR(x) WriteRegBits16(SWITCH_PAGE_00_TCAM_CHKSUM_STS,0x8000,15,x)
#define Rd_switch_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR(x) ReadRegBits16(SWITCH_PAGE_00_TCAM_CHKSUM_STS,0x8000,15)
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_MASK 0x8000
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_ALIGN 0
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_BITS 1
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ERR_SHIFT 15

/* switch :: PAGE_00_TCAM_CHKSUM_STS :: PAGE_00_TCAM_CHKSUM_STS_RESERVED [14:08] */
#define Wr_switch_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_00_TCAM_CHKSUM_STS,0x7f00,8,x)
#define Rd_switch_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_00_TCAM_CHKSUM_STS,0x7f00,8)
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_RESERVED_MASK 0x7f00
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_RESERVED_BITS 7
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_RESERVED_SHIFT 8

/* switch :: PAGE_00_TCAM_CHKSUM_STS :: PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR [07:00] */
#define Wr_switch_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR(x) WriteRegBits16(SWITCH_PAGE_00_TCAM_CHKSUM_STS,0xff,0,x)
#define Rd_switch_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR(x) ReadRegBits16(SWITCH_PAGE_00_TCAM_CHKSUM_STS,0xff,0)
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_MASK 0x00ff
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_ALIGN 0
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_BITS 8
#define SWITCH_PAGE_00_TCAM_CHKSUM_STS_PAGE_00_TCAM_CHKSUM_STS_CFP_TCAM_CHKSUM_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_00_LIGHTSTACK_CTRL
 ***************************************************************************/
/* switch :: PAGE_00_LIGHTSTACK_CTRL :: PAGE_00_LIGHTSTACK_CTRL_RESERVED [31:11] */
#define Wr_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0xfffff800,11,x)
#define Rd_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0xfffff800,11)
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED_MASK 0xfffff800
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED_BITS 21
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED_SHIFT 11

/* switch :: PAGE_00_LIGHTSTACK_CTRL :: PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT0 [10:08] */
#define Wr_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT0(x) WriteRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x700,8,x)
#define Rd_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT0(x) ReadRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x700,8)
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT0_MASK 0x00000700
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT0_ALIGN 0
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT0_BITS 3
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT0_SHIFT 8

/* switch :: PAGE_00_LIGHTSTACK_CTRL :: PAGE_00_LIGHTSTACK_CTRL_RESERVED1 [07:07] */
#define Wr_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED1(x) WriteRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x80,7,x)
#define Rd_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED1(x) ReadRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x80,7)
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED1_MASK 0x00000080
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED1_ALIGN 0
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED1_BITS 1
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED1_SHIFT 7

/* switch :: PAGE_00_LIGHTSTACK_CTRL :: PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1 [06:04] */
#define Wr_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1(x) WriteRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x70,4,x)
#define Rd_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1(x) ReadRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x70,4)
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_MASK 0x00000070
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_ALIGN 0
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_BITS 3
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_SHIFT 4

/* switch :: PAGE_00_LIGHTSTACK_CTRL :: PAGE_00_LIGHTSTACK_CTRL_RESERVED2 [03:03] */
#define Wr_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED2(x) WriteRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x8,3,x)
#define Rd_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED2(x) ReadRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x8,3)
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED2_MASK 0x00000008
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED2_ALIGN 0
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED2_BITS 1
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_RESERVED2_SHIFT 3

/* switch :: PAGE_00_LIGHTSTACK_CTRL :: PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_EN [02:02] */
#define Wr_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_EN(x) WriteRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x4,2,x)
#define Rd_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_EN(x) ReadRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x4,2)
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_EN_MASK 0x00000004
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_EN_ALIGN 0
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_EN_BITS 1
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_PORT1_EN_SHIFT 2

/* switch :: PAGE_00_LIGHTSTACK_CTRL :: PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_MASTER [01:01] */
#define Wr_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_MASTER(x) WriteRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x2,1,x)
#define Rd_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_MASTER(x) ReadRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x2,1)
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_MASTER_MASK 0x00000002
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_MASTER_ALIGN 0
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_MASTER_BITS 1
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_MASTER_SHIFT 1

/* switch :: PAGE_00_LIGHTSTACK_CTRL :: PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_EN [00:00] */
#define Wr_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_EN(x) WriteRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x1,0,x)
#define Rd_switch_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_EN(x) ReadRegBits(SWITCH_PAGE_00_LIGHTSTACK_CTRL,0x1,0)
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_EN_MASK 0x00000001
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_EN_ALIGN 0
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_EN_BITS 1
#define SWITCH_PAGE_00_LIGHTSTACK_CTRL_PAGE_00_LIGHTSTACK_CTRL_LIGHTSTACK_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_LNKSTS
 ***************************************************************************/
/* switch :: PAGE_01_LNKSTS :: PAGE_01_LNKSTS_RESERVED [15:09] */
#define Wr_switch_PAGE_01_LNKSTS_PAGE_01_LNKSTS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_01_LNKSTS,0xfe00,9,x)
#define Rd_switch_PAGE_01_LNKSTS_PAGE_01_LNKSTS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_01_LNKSTS,0xfe00,9)
#define SWITCH_PAGE_01_LNKSTS_PAGE_01_LNKSTS_RESERVED_MASK         0xfe00
#define SWITCH_PAGE_01_LNKSTS_PAGE_01_LNKSTS_RESERVED_ALIGN        0
#define SWITCH_PAGE_01_LNKSTS_PAGE_01_LNKSTS_RESERVED_BITS         7
#define SWITCH_PAGE_01_LNKSTS_PAGE_01_LNKSTS_RESERVED_SHIFT        9

/* switch :: PAGE_01_LNKSTS :: PAGE_01_LNKSTS_LNK_STS [08:00] */
#define Wr_switch_PAGE_01_LNKSTS_PAGE_01_LNKSTS_LNK_STS(x) WriteRegBits16(SWITCH_PAGE_01_LNKSTS,0x1ff,0,x)
#define Rd_switch_PAGE_01_LNKSTS_PAGE_01_LNKSTS_LNK_STS(x) ReadRegBits16(SWITCH_PAGE_01_LNKSTS,0x1ff,0)
#define SWITCH_PAGE_01_LNKSTS_PAGE_01_LNKSTS_LNK_STS_MASK          0x01ff
#define SWITCH_PAGE_01_LNKSTS_PAGE_01_LNKSTS_LNK_STS_ALIGN         0
#define SWITCH_PAGE_01_LNKSTS_PAGE_01_LNKSTS_LNK_STS_BITS          9
#define SWITCH_PAGE_01_LNKSTS_PAGE_01_LNKSTS_LNK_STS_SHIFT         0


/****************************************************************************
 * switch :: PAGE_01_LNKSTSCHG
 ***************************************************************************/
/* switch :: PAGE_01_LNKSTSCHG :: PAGE_01_LNKSTSCHG_RESERVED [15:09] */
#define Wr_switch_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_RESERVED(x) WriteRegBits16(SWITCH_PAGE_01_LNKSTSCHG,0xfe00,9,x)
#define Rd_switch_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_RESERVED(x) ReadRegBits16(SWITCH_PAGE_01_LNKSTSCHG,0xfe00,9)
#define SWITCH_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_RESERVED_MASK   0xfe00
#define SWITCH_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_RESERVED_ALIGN  0
#define SWITCH_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_RESERVED_BITS   7
#define SWITCH_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_RESERVED_SHIFT  9

/* switch :: PAGE_01_LNKSTSCHG :: PAGE_01_LNKSTSCHG_LNK_STS_CHG [08:00] */
#define Wr_switch_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_LNK_STS_CHG(x) WriteRegBits16(SWITCH_PAGE_01_LNKSTSCHG,0x1ff,0,x)
#define Rd_switch_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_LNK_STS_CHG(x) ReadRegBits16(SWITCH_PAGE_01_LNKSTSCHG,0x1ff,0)
#define SWITCH_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_LNK_STS_CHG_MASK 0x01ff
#define SWITCH_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_LNK_STS_CHG_ALIGN 0
#define SWITCH_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_LNK_STS_CHG_BITS 9
#define SWITCH_PAGE_01_LNKSTSCHG_PAGE_01_LNKSTSCHG_LNK_STS_CHG_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_SPDSTS
 ***************************************************************************/
/* switch :: PAGE_01_SPDSTS :: PAGE_01_SPDSTS_RESERVED [31:18] */
#define Wr_switch_PAGE_01_SPDSTS_PAGE_01_SPDSTS_RESERVED(x) WriteRegBits(SWITCH_PAGE_01_SPDSTS,0xfffc0000,18,x)
#define Rd_switch_PAGE_01_SPDSTS_PAGE_01_SPDSTS_RESERVED(x) ReadRegBits(SWITCH_PAGE_01_SPDSTS,0xfffc0000,18)
#define SWITCH_PAGE_01_SPDSTS_PAGE_01_SPDSTS_RESERVED_MASK         0xfffc0000
#define SWITCH_PAGE_01_SPDSTS_PAGE_01_SPDSTS_RESERVED_ALIGN        0
#define SWITCH_PAGE_01_SPDSTS_PAGE_01_SPDSTS_RESERVED_BITS         14
#define SWITCH_PAGE_01_SPDSTS_PAGE_01_SPDSTS_RESERVED_SHIFT        18

/* switch :: PAGE_01_SPDSTS :: PAGE_01_SPDSTS_PORT_SPD [17:00] */
#define Wr_switch_PAGE_01_SPDSTS_PAGE_01_SPDSTS_PORT_SPD(x) WriteRegBits(SWITCH_PAGE_01_SPDSTS,0x3ffff,0,x)
#define Rd_switch_PAGE_01_SPDSTS_PAGE_01_SPDSTS_PORT_SPD(x) ReadRegBits(SWITCH_PAGE_01_SPDSTS,0x3ffff,0)
#define SWITCH_PAGE_01_SPDSTS_PAGE_01_SPDSTS_PORT_SPD_MASK         0x0003ffff
#define SWITCH_PAGE_01_SPDSTS_PAGE_01_SPDSTS_PORT_SPD_ALIGN        0
#define SWITCH_PAGE_01_SPDSTS_PAGE_01_SPDSTS_PORT_SPD_BITS         18
#define SWITCH_PAGE_01_SPDSTS_PAGE_01_SPDSTS_PORT_SPD_SHIFT        0


/****************************************************************************
 * switch :: PAGE_01_DUPSTS
 ***************************************************************************/
/* switch :: PAGE_01_DUPSTS :: PAGE_01_DUPSTS_RESERVED [15:09] */
#define Wr_switch_PAGE_01_DUPSTS_PAGE_01_DUPSTS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_01_DUPSTS,0xfe00,9,x)
#define Rd_switch_PAGE_01_DUPSTS_PAGE_01_DUPSTS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_01_DUPSTS,0xfe00,9)
#define SWITCH_PAGE_01_DUPSTS_PAGE_01_DUPSTS_RESERVED_MASK         0xfe00
#define SWITCH_PAGE_01_DUPSTS_PAGE_01_DUPSTS_RESERVED_ALIGN        0
#define SWITCH_PAGE_01_DUPSTS_PAGE_01_DUPSTS_RESERVED_BITS         7
#define SWITCH_PAGE_01_DUPSTS_PAGE_01_DUPSTS_RESERVED_SHIFT        9

/* switch :: PAGE_01_DUPSTS :: PAGE_01_DUPSTS_DUP_STS [08:00] */
#define Wr_switch_PAGE_01_DUPSTS_PAGE_01_DUPSTS_DUP_STS(x) WriteRegBits16(SWITCH_PAGE_01_DUPSTS,0x1ff,0,x)
#define Rd_switch_PAGE_01_DUPSTS_PAGE_01_DUPSTS_DUP_STS(x) ReadRegBits16(SWITCH_PAGE_01_DUPSTS,0x1ff,0)
#define SWITCH_PAGE_01_DUPSTS_PAGE_01_DUPSTS_DUP_STS_MASK          0x01ff
#define SWITCH_PAGE_01_DUPSTS_PAGE_01_DUPSTS_DUP_STS_ALIGN         0
#define SWITCH_PAGE_01_DUPSTS_PAGE_01_DUPSTS_DUP_STS_BITS          9
#define SWITCH_PAGE_01_DUPSTS_PAGE_01_DUPSTS_DUP_STS_SHIFT         0


/****************************************************************************
 * switch :: PAGE_01_PAUSESTS
 ***************************************************************************/
/* switch :: PAGE_01_PAUSESTS :: PAGE_01_PAUSESTS_RESERVED [31:18] */
#define Wr_switch_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_RESERVED(x) WriteRegBits(SWITCH_PAGE_01_PAUSESTS,0xfffc0000,18,x)
#define Rd_switch_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_RESERVED(x) ReadRegBits(SWITCH_PAGE_01_PAUSESTS,0xfffc0000,18)
#define SWITCH_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_RESERVED_MASK     0xfffc0000
#define SWITCH_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_RESERVED_ALIGN    0
#define SWITCH_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_RESERVED_BITS     14
#define SWITCH_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_RESERVED_SHIFT    18

/* switch :: PAGE_01_PAUSESTS :: PAGE_01_PAUSESTS_PAUSE_STS [17:00] */
#define Wr_switch_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_PAUSE_STS(x) WriteRegBits(SWITCH_PAGE_01_PAUSESTS,0x3ffff,0,x)
#define Rd_switch_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_PAUSE_STS(x) ReadRegBits(SWITCH_PAGE_01_PAUSESTS,0x3ffff,0)
#define SWITCH_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_PAUSE_STS_MASK    0x0003ffff
#define SWITCH_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_PAUSE_STS_ALIGN   0
#define SWITCH_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_PAUSE_STS_BITS    18
#define SWITCH_PAGE_01_PAUSESTS_PAGE_01_PAUSESTS_PAUSE_STS_SHIFT   0


/****************************************************************************
 * switch :: PAGE_01_SRCADRCHG
 ***************************************************************************/
/* switch :: PAGE_01_SRCADRCHG :: PAGE_01_SRCADRCHG_RESERVED [15:09] */
#define Wr_switch_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_RESERVED(x) WriteRegBits16(SWITCH_PAGE_01_SRCADRCHG,0xfe00,9,x)
#define Rd_switch_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_RESERVED(x) ReadRegBits16(SWITCH_PAGE_01_SRCADRCHG,0xfe00,9)
#define SWITCH_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_RESERVED_MASK   0xfe00
#define SWITCH_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_RESERVED_ALIGN  0
#define SWITCH_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_RESERVED_BITS   7
#define SWITCH_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_RESERVED_SHIFT  9

/* switch :: PAGE_01_SRCADRCHG :: PAGE_01_SRCADRCHG_SRC_ADDR_CHANGE [08:00] */
#define Wr_switch_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_SRC_ADDR_CHANGE(x) WriteRegBits16(SWITCH_PAGE_01_SRCADRCHG,0x1ff,0,x)
#define Rd_switch_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_SRC_ADDR_CHANGE(x) ReadRegBits16(SWITCH_PAGE_01_SRCADRCHG,0x1ff,0)
#define SWITCH_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_SRC_ADDR_CHANGE_MASK 0x01ff
#define SWITCH_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_SRC_ADDR_CHANGE_ALIGN 0
#define SWITCH_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_SRC_ADDR_CHANGE_BITS 9
#define SWITCH_PAGE_01_SRCADRCHG_PAGE_01_SRCADRCHG_SRC_ADDR_CHANGE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_LSA_PORT0
 ***************************************************************************/
/* switch :: PAGE_01_LSA_PORT0 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_LSA_PORT0_RESERVED0_MASK                    0xffff000000000000
#define SWITCH_PAGE_01_LSA_PORT0_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_01_LSA_PORT0_RESERVED0_BITS                    16
#define SWITCH_PAGE_01_LSA_PORT0_RESERVED0_SHIFT                   48

/* switch :: PAGE_01_LSA_PORT0 :: PAGE_01_LSA_PORT0_LST_ADDR [47:00] */
#define Wr_switch_PAGE_01_LSA_PORT0_PAGE_01_LSA_PORT0_LST_ADDR(x) WriteRegBits(SWITCH_PAGE_01_LSA_PORT0,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_LSA_PORT0_PAGE_01_LSA_PORT0_LST_ADDR(x) ReadRegBits(SWITCH_PAGE_01_LSA_PORT0,0xffffffffffff,0)
#define SWITCH_PAGE_01_LSA_PORT0_PAGE_01_LSA_PORT0_LST_ADDR_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_01_LSA_PORT0_PAGE_01_LSA_PORT0_LST_ADDR_ALIGN  0
#define SWITCH_PAGE_01_LSA_PORT0_PAGE_01_LSA_PORT0_LST_ADDR_BITS   48
#define SWITCH_PAGE_01_LSA_PORT0_PAGE_01_LSA_PORT0_LST_ADDR_SHIFT  0


/****************************************************************************
 * switch :: PAGE_01_LSA_PORT1
 ***************************************************************************/
/* switch :: PAGE_01_LSA_PORT1 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_LSA_PORT1_RESERVED0_MASK                    0xffff000000000000
#define SWITCH_PAGE_01_LSA_PORT1_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_01_LSA_PORT1_RESERVED0_BITS                    16
#define SWITCH_PAGE_01_LSA_PORT1_RESERVED0_SHIFT                   48

/* switch :: PAGE_01_LSA_PORT1 :: PAGE_01_LSA_PORT1_LST_ADDR [47:00] */
#define Wr_switch_PAGE_01_LSA_PORT1_PAGE_01_LSA_PORT1_LST_ADDR(x) WriteRegBits(SWITCH_PAGE_01_LSA_PORT1,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_LSA_PORT1_PAGE_01_LSA_PORT1_LST_ADDR(x) ReadRegBits(SWITCH_PAGE_01_LSA_PORT1,0xffffffffffff,0)
#define SWITCH_PAGE_01_LSA_PORT1_PAGE_01_LSA_PORT1_LST_ADDR_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_01_LSA_PORT1_PAGE_01_LSA_PORT1_LST_ADDR_ALIGN  0
#define SWITCH_PAGE_01_LSA_PORT1_PAGE_01_LSA_PORT1_LST_ADDR_BITS   48
#define SWITCH_PAGE_01_LSA_PORT1_PAGE_01_LSA_PORT1_LST_ADDR_SHIFT  0


/****************************************************************************
 * switch :: PAGE_01_LSA_PORT2
 ***************************************************************************/
/* switch :: PAGE_01_LSA_PORT2 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_LSA_PORT2_RESERVED0_MASK                    0xffff000000000000
#define SWITCH_PAGE_01_LSA_PORT2_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_01_LSA_PORT2_RESERVED0_BITS                    16
#define SWITCH_PAGE_01_LSA_PORT2_RESERVED0_SHIFT                   48

/* switch :: PAGE_01_LSA_PORT2 :: PAGE_01_LSA_PORT2_LST_ADDR [47:00] */
#define Wr_switch_PAGE_01_LSA_PORT2_PAGE_01_LSA_PORT2_LST_ADDR(x) WriteRegBits(SWITCH_PAGE_01_LSA_PORT2,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_LSA_PORT2_PAGE_01_LSA_PORT2_LST_ADDR(x) ReadRegBits(SWITCH_PAGE_01_LSA_PORT2,0xffffffffffff,0)
#define SWITCH_PAGE_01_LSA_PORT2_PAGE_01_LSA_PORT2_LST_ADDR_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_01_LSA_PORT2_PAGE_01_LSA_PORT2_LST_ADDR_ALIGN  0
#define SWITCH_PAGE_01_LSA_PORT2_PAGE_01_LSA_PORT2_LST_ADDR_BITS   48
#define SWITCH_PAGE_01_LSA_PORT2_PAGE_01_LSA_PORT2_LST_ADDR_SHIFT  0


/****************************************************************************
 * switch :: PAGE_01_LSA_PORT3
 ***************************************************************************/
/* switch :: PAGE_01_LSA_PORT3 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_LSA_PORT3_RESERVED0_MASK                    0xffff000000000000
#define SWITCH_PAGE_01_LSA_PORT3_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_01_LSA_PORT3_RESERVED0_BITS                    16
#define SWITCH_PAGE_01_LSA_PORT3_RESERVED0_SHIFT                   48

/* switch :: PAGE_01_LSA_PORT3 :: PAGE_01_LSA_PORT3_LST_ADDR [47:00] */
#define Wr_switch_PAGE_01_LSA_PORT3_PAGE_01_LSA_PORT3_LST_ADDR(x) WriteRegBits(SWITCH_PAGE_01_LSA_PORT3,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_LSA_PORT3_PAGE_01_LSA_PORT3_LST_ADDR(x) ReadRegBits(SWITCH_PAGE_01_LSA_PORT3,0xffffffffffff,0)
#define SWITCH_PAGE_01_LSA_PORT3_PAGE_01_LSA_PORT3_LST_ADDR_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_01_LSA_PORT3_PAGE_01_LSA_PORT3_LST_ADDR_ALIGN  0
#define SWITCH_PAGE_01_LSA_PORT3_PAGE_01_LSA_PORT3_LST_ADDR_BITS   48
#define SWITCH_PAGE_01_LSA_PORT3_PAGE_01_LSA_PORT3_LST_ADDR_SHIFT  0


/****************************************************************************
 * switch :: PAGE_01_LSA_PORT4
 ***************************************************************************/
/* switch :: PAGE_01_LSA_PORT4 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_LSA_PORT4_RESERVED0_MASK                    0xffff000000000000
#define SWITCH_PAGE_01_LSA_PORT4_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_01_LSA_PORT4_RESERVED0_BITS                    16
#define SWITCH_PAGE_01_LSA_PORT4_RESERVED0_SHIFT                   48

/* switch :: PAGE_01_LSA_PORT4 :: PAGE_01_LSA_PORT4_LST_ADDR [47:00] */
#define Wr_switch_PAGE_01_LSA_PORT4_PAGE_01_LSA_PORT4_LST_ADDR(x) WriteRegBits(SWITCH_PAGE_01_LSA_PORT4,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_LSA_PORT4_PAGE_01_LSA_PORT4_LST_ADDR(x) ReadRegBits(SWITCH_PAGE_01_LSA_PORT4,0xffffffffffff,0)
#define SWITCH_PAGE_01_LSA_PORT4_PAGE_01_LSA_PORT4_LST_ADDR_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_01_LSA_PORT4_PAGE_01_LSA_PORT4_LST_ADDR_ALIGN  0
#define SWITCH_PAGE_01_LSA_PORT4_PAGE_01_LSA_PORT4_LST_ADDR_BITS   48
#define SWITCH_PAGE_01_LSA_PORT4_PAGE_01_LSA_PORT4_LST_ADDR_SHIFT  0


/****************************************************************************
 * switch :: PAGE_01_LSA_PORT5
 ***************************************************************************/
/* switch :: PAGE_01_LSA_PORT5 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_LSA_PORT5_RESERVED0_MASK                    0xffff000000000000
#define SWITCH_PAGE_01_LSA_PORT5_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_01_LSA_PORT5_RESERVED0_BITS                    16
#define SWITCH_PAGE_01_LSA_PORT5_RESERVED0_SHIFT                   48

/* switch :: PAGE_01_LSA_PORT5 :: PAGE_01_LSA_PORT5_LST_ADDR [47:00] */
#define Wr_switch_PAGE_01_LSA_PORT5_PAGE_01_LSA_PORT5_LST_ADDR(x) WriteRegBits(SWITCH_PAGE_01_LSA_PORT5,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_LSA_PORT5_PAGE_01_LSA_PORT5_LST_ADDR(x) ReadRegBits(SWITCH_PAGE_01_LSA_PORT5,0xffffffffffff,0)
#define SWITCH_PAGE_01_LSA_PORT5_PAGE_01_LSA_PORT5_LST_ADDR_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_01_LSA_PORT5_PAGE_01_LSA_PORT5_LST_ADDR_ALIGN  0
#define SWITCH_PAGE_01_LSA_PORT5_PAGE_01_LSA_PORT5_LST_ADDR_BITS   48
#define SWITCH_PAGE_01_LSA_PORT5_PAGE_01_LSA_PORT5_LST_ADDR_SHIFT  0


/****************************************************************************
 * switch :: PAGE_01_LSA_PORT6
 ***************************************************************************/
/* switch :: PAGE_01_LSA_PORT6 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_LSA_PORT6_RESERVED0_MASK                    0xffff000000000000
#define SWITCH_PAGE_01_LSA_PORT6_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_01_LSA_PORT6_RESERVED0_BITS                    16
#define SWITCH_PAGE_01_LSA_PORT6_RESERVED0_SHIFT                   48

/* switch :: PAGE_01_LSA_PORT6 :: PAGE_01_LSA_PORT6_LST_ADDR [47:00] */
#define Wr_switch_PAGE_01_LSA_PORT6_PAGE_01_LSA_PORT6_LST_ADDR(x) WriteRegBits(SWITCH_PAGE_01_LSA_PORT6,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_LSA_PORT6_PAGE_01_LSA_PORT6_LST_ADDR(x) ReadRegBits(SWITCH_PAGE_01_LSA_PORT6,0xffffffffffff,0)
#define SWITCH_PAGE_01_LSA_PORT6_PAGE_01_LSA_PORT6_LST_ADDR_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_01_LSA_PORT6_PAGE_01_LSA_PORT6_LST_ADDR_ALIGN  0
#define SWITCH_PAGE_01_LSA_PORT6_PAGE_01_LSA_PORT6_LST_ADDR_BITS   48
#define SWITCH_PAGE_01_LSA_PORT6_PAGE_01_LSA_PORT6_LST_ADDR_SHIFT  0


/****************************************************************************
 * switch :: PAGE_01_LSA_PORT7
 ***************************************************************************/
/* switch :: PAGE_01_LSA_PORT7 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_LSA_PORT7_RESERVED0_MASK                    0xffff000000000000
#define SWITCH_PAGE_01_LSA_PORT7_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_01_LSA_PORT7_RESERVED0_BITS                    16
#define SWITCH_PAGE_01_LSA_PORT7_RESERVED0_SHIFT                   48

/* switch :: PAGE_01_LSA_PORT7 :: PAGE_01_LSA_PORT7_LST_ADDR [47:00] */
#define Wr_switch_PAGE_01_LSA_PORT7_PAGE_01_LSA_PORT7_LST_ADDR(x) WriteRegBits(SWITCH_PAGE_01_LSA_PORT7,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_LSA_PORT7_PAGE_01_LSA_PORT7_LST_ADDR(x) ReadRegBits(SWITCH_PAGE_01_LSA_PORT7,0xffffffffffff,0)
#define SWITCH_PAGE_01_LSA_PORT7_PAGE_01_LSA_PORT7_LST_ADDR_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_01_LSA_PORT7_PAGE_01_LSA_PORT7_LST_ADDR_ALIGN  0
#define SWITCH_PAGE_01_LSA_PORT7_PAGE_01_LSA_PORT7_LST_ADDR_BITS   48
#define SWITCH_PAGE_01_LSA_PORT7_PAGE_01_LSA_PORT7_LST_ADDR_SHIFT  0


/****************************************************************************
 * switch :: PAGE_01_LSA_MII_PORT
 ***************************************************************************/
/* switch :: PAGE_01_LSA_MII_PORT :: reserved0 [63:48] */
#define SWITCH_PAGE_01_LSA_MII_PORT_RESERVED0_MASK                 0xffff000000000000
#define SWITCH_PAGE_01_LSA_MII_PORT_RESERVED0_ALIGN                0
#define SWITCH_PAGE_01_LSA_MII_PORT_RESERVED0_BITS                 16
#define SWITCH_PAGE_01_LSA_MII_PORT_RESERVED0_SHIFT                48

/* switch :: PAGE_01_LSA_MII_PORT :: PAGE_01_LSA_MII_PORT_LST_ADDR [47:00] */
#define Wr_switch_PAGE_01_LSA_MII_PORT_PAGE_01_LSA_MII_PORT_LST_ADDR(x) WriteRegBits(SWITCH_PAGE_01_LSA_MII_PORT,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_LSA_MII_PORT_PAGE_01_LSA_MII_PORT_LST_ADDR(x) ReadRegBits(SWITCH_PAGE_01_LSA_MII_PORT,0xffffffffffff,0)
#define SWITCH_PAGE_01_LSA_MII_PORT_PAGE_01_LSA_MII_PORT_LST_ADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_01_LSA_MII_PORT_PAGE_01_LSA_MII_PORT_LST_ADDR_ALIGN 0
#define SWITCH_PAGE_01_LSA_MII_PORT_PAGE_01_LSA_MII_PORT_LST_ADDR_BITS 48
#define SWITCH_PAGE_01_LSA_MII_PORT_PAGE_01_LSA_MII_PORT_LST_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_BIST_STS0
 ***************************************************************************/
/* switch :: PAGE_01_BIST_STS0 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_BIST_STS0_RESERVED0_MASK                    0xffff000000000000
#define SWITCH_PAGE_01_BIST_STS0_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_01_BIST_STS0_RESERVED0_BITS                    16
#define SWITCH_PAGE_01_BIST_STS0_RESERVED0_SHIFT                   48

/* switch :: PAGE_01_BIST_STS0 :: PAGE_01_BIST_STS0_BIST_STS0 [47:00] */
#define Wr_switch_PAGE_01_BIST_STS0_PAGE_01_BIST_STS0_BIST_STS0(x) WriteRegBits(SWITCH_PAGE_01_BIST_STS0,0xffffffffffff,0,x)
#define Rd_switch_PAGE_01_BIST_STS0_PAGE_01_BIST_STS0_BIST_STS0(x) ReadRegBits(SWITCH_PAGE_01_BIST_STS0,0xffffffffffff,0)
#define SWITCH_PAGE_01_BIST_STS0_PAGE_01_BIST_STS0_BIST_STS0_MASK  0x0000ffffffffffff
#define SWITCH_PAGE_01_BIST_STS0_PAGE_01_BIST_STS0_BIST_STS0_ALIGN 0
#define SWITCH_PAGE_01_BIST_STS0_PAGE_01_BIST_STS0_BIST_STS0_BITS  48
#define SWITCH_PAGE_01_BIST_STS0_PAGE_01_BIST_STS0_BIST_STS0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_BIST_STS1
 ***************************************************************************/
/* switch :: PAGE_01_BIST_STS1 :: PAGE_01_BIST_STS1_BIST_STS1 [15:00] */
#define Wr_switch_PAGE_01_BIST_STS1_PAGE_01_BIST_STS1_BIST_STS1(x) WriteReg16(SWITCH_PAGE_01_BIST_STS1,x)
#define Rd_switch_PAGE_01_BIST_STS1_PAGE_01_BIST_STS1_BIST_STS1(x) ReadReg16(SWITCH_PAGE_01_BIST_STS1)
#define SWITCH_PAGE_01_BIST_STS1_PAGE_01_BIST_STS1_BIST_STS1_MASK  0xffff
#define SWITCH_PAGE_01_BIST_STS1_PAGE_01_BIST_STS1_BIST_STS1_ALIGN 0
#define SWITCH_PAGE_01_BIST_STS1_PAGE_01_BIST_STS1_BIST_STS1_BITS  16
#define SWITCH_PAGE_01_BIST_STS1_PAGE_01_BIST_STS1_BIST_STS1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_PBPTRFIFO_0
 ***************************************************************************/
/* switch :: PAGE_01_PBPTRFIFO_0 :: reserved0 [63:48] */
#define SWITCH_PAGE_01_PBPTRFIFO_0_RESERVED0_MASK                  0xffff000000000000
#define SWITCH_PAGE_01_PBPTRFIFO_0_RESERVED0_ALIGN                 0
#define SWITCH_PAGE_01_PBPTRFIFO_0_RESERVED0_BITS                  16
#define SWITCH_PAGE_01_PBPTRFIFO_0_RESERVED0_SHIFT                 48

/* switch :: PAGE_01_PBPTRFIFO_0 :: PAGE_01_PBPTRFIFO_0_VALID_CNT_P5 [47:40] */
#define Wr_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P5(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff0000000000,40,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P5(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff0000000000,40)
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P5_MASK 0x0000ff0000000000
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P5_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P5_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P5_SHIFT 40

/* switch :: PAGE_01_PBPTRFIFO_0 :: PAGE_01_PBPTRFIFO_0_VALID_CNT_P4 [39:32] */
#define Wr_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P4(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff00000000,32,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P4(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff00000000,32)
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P4_MASK 0x000000ff00000000
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P4_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P4_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P4_SHIFT 32

/* switch :: PAGE_01_PBPTRFIFO_0 :: PAGE_01_PBPTRFIFO_0_VALID_CNT_P3 [31:24] */
#define Wr_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P3(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff000000,24,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P3(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff000000,24)
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P3_MASK 0x00000000ff000000
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P3_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P3_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P3_SHIFT 24

/* switch :: PAGE_01_PBPTRFIFO_0 :: PAGE_01_PBPTRFIFO_0_VALID_CNT_P2 [23:16] */
#define Wr_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P2(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff0000,16,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P2(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff0000,16)
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P2_MASK 0x0000000000ff0000
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P2_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P2_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P2_SHIFT 16

/* switch :: PAGE_01_PBPTRFIFO_0 :: PAGE_01_PBPTRFIFO_0_VALID_CNT_P1 [15:08] */
#define Wr_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P1(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff00,8,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P1(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff00,8)
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P1_MASK 0x000000000000ff00
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P1_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P1_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P1_SHIFT 8

/* switch :: PAGE_01_PBPTRFIFO_0 :: PAGE_01_PBPTRFIFO_0_VALID_CNT_P0 [07:00] */
#define Wr_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P0(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff,0,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P0(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_0,0xff,0)
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P0_MASK 0x00000000000000ff
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P0_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P0_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_0_PAGE_01_PBPTRFIFO_0_VALID_CNT_P0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_PBPTRFIFO_1
 ***************************************************************************/
/* switch :: PAGE_01_PBPTRFIFO_1 :: PAGE_01_PBPTRFIFO_1_RESERVED_1 [31:24] */
#define Wr_switch_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_1,0xff000000,24,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_1,0xff000000,24)
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_RESERVED_1_MASK 0xff000000
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_RESERVED_1_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_RESERVED_1_SHIFT 24

/* switch :: PAGE_01_PBPTRFIFO_1 :: PAGE_01_PBPTRFIFO_1_VALID_CNT_P8 [23:16] */
#define Wr_switch_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P8(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_1,0xff0000,16,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P8(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_1,0xff0000,16)
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P8_MASK 0x00ff0000
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P8_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P8_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P8_SHIFT 16

/* switch :: PAGE_01_PBPTRFIFO_1 :: PAGE_01_PBPTRFIFO_1_VALID_CNT_P7 [15:08] */
#define Wr_switch_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P7(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_1,0xff00,8,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P7(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_1,0xff00,8)
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P7_MASK 0x0000ff00
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P7_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P7_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P7_SHIFT 8

/* switch :: PAGE_01_PBPTRFIFO_1 :: PAGE_01_PBPTRFIFO_1_VALID_CNT_P6 [07:00] */
#define Wr_switch_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P6(x) WriteRegBits(SWITCH_PAGE_01_PBPTRFIFO_1,0xff,0,x)
#define Rd_switch_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P6(x) ReadRegBits(SWITCH_PAGE_01_PBPTRFIFO_1,0xff,0)
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P6_MASK 0x000000ff
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P6_ALIGN 0
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P6_BITS 8
#define SWITCH_PAGE_01_PBPTRFIFO_1_PAGE_01_PBPTRFIFO_1_VALID_CNT_P6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_RESET_STATUS
 ***************************************************************************/
/* switch :: PAGE_01_RESET_STATUS :: PAGE_01_RESET_STATUS_RESERVED_1 [15:10] */
#define Wr_switch_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_01_RESET_STATUS,0xfc00,10,x)
#define Rd_switch_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_01_RESET_STATUS,0xfc00,10)
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_1_MASK 0xfc00
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_1_BITS 6
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_1_SHIFT 10

/* switch :: PAGE_01_RESET_STATUS :: PAGE_01_RESET_STATUS_SW_CORE_RST_STS [09:09] */
#define Wr_switch_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_CORE_RST_STS(x) WriteRegBits16(SWITCH_PAGE_01_RESET_STATUS,0x200,9,x)
#define Rd_switch_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_CORE_RST_STS(x) ReadRegBits16(SWITCH_PAGE_01_RESET_STATUS,0x200,9)
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_CORE_RST_STS_MASK 0x0200
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_CORE_RST_STS_ALIGN 0
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_CORE_RST_STS_BITS 1
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_CORE_RST_STS_SHIFT 9

/* switch :: PAGE_01_RESET_STATUS :: PAGE_01_RESET_STATUS_SW_REG_RST_STS [08:08] */
#define Wr_switch_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_REG_RST_STS(x) WriteRegBits16(SWITCH_PAGE_01_RESET_STATUS,0x100,8,x)
#define Rd_switch_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_REG_RST_STS(x) ReadRegBits16(SWITCH_PAGE_01_RESET_STATUS,0x100,8)
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_REG_RST_STS_MASK 0x0100
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_REG_RST_STS_ALIGN 0
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_REG_RST_STS_BITS 1
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_SW_REG_RST_STS_SHIFT 8

/* switch :: PAGE_01_RESET_STATUS :: PAGE_01_RESET_STATUS_RESERVED_0 [07:00] */
#define Wr_switch_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_01_RESET_STATUS,0xff,0,x)
#define Rd_switch_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_01_RESET_STATUS,0xff,0)
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_0_MASK 0x00ff
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_0_BITS 8
#define SWITCH_PAGE_01_RESET_STATUS_PAGE_01_RESET_STATUS_RESERVED_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_STREG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_01_STREG_REG_SPARE0 :: PAGE_01_STREG_REG_SPARE0_STREG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_01_STREG_REG_SPARE0_PAGE_01_STREG_REG_SPARE0_STREG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_01_STREG_REG_SPARE0,x)
#define Rd_switch_PAGE_01_STREG_REG_SPARE0_PAGE_01_STREG_REG_SPARE0_STREG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_01_STREG_REG_SPARE0)
#define SWITCH_PAGE_01_STREG_REG_SPARE0_PAGE_01_STREG_REG_SPARE0_STREG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_01_STREG_REG_SPARE0_PAGE_01_STREG_REG_SPARE0_STREG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_01_STREG_REG_SPARE0_PAGE_01_STREG_REG_SPARE0_STREG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_01_STREG_REG_SPARE0_PAGE_01_STREG_REG_SPARE0_STREG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_01_STREG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_01_STREG_REG_SPARE1 :: PAGE_01_STREG_REG_SPARE1_STREG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_01_STREG_REG_SPARE1_PAGE_01_STREG_REG_SPARE1_STREG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_01_STREG_REG_SPARE1,x)
#define Rd_switch_PAGE_01_STREG_REG_SPARE1_PAGE_01_STREG_REG_SPARE1_STREG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_01_STREG_REG_SPARE1)
#define SWITCH_PAGE_01_STREG_REG_SPARE1_PAGE_01_STREG_REG_SPARE1_STREG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_01_STREG_REG_SPARE1_PAGE_01_STREG_REG_SPARE1_STREG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_01_STREG_REG_SPARE1_PAGE_01_STREG_REG_SPARE1_STREG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_01_STREG_REG_SPARE1_PAGE_01_STREG_REG_SPARE1_STREG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_GMNGCFG
 ***************************************************************************/
/* switch :: PAGE_02_GMNGCFG :: PAGE_02_GMNGCFG_FRM_MNGP [07:06] */
#define Wr_switch_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_FRM_MNGP(x) WriteRegBits(SWITCH_PAGE_02_GMNGCFG,0xc0,6,x)
#define Rd_switch_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_FRM_MNGP(x) ReadRegBits(SWITCH_PAGE_02_GMNGCFG,0xc0,6)
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_FRM_MNGP_MASK       0xc0
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_FRM_MNGP_ALIGN      0
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_FRM_MNGP_BITS       2
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_FRM_MNGP_SHIFT      6

/* switch :: PAGE_02_GMNGCFG :: PAGE_02_GMNGCFG_RESERVED [05:02] */
#define Wr_switch_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RESERVED(x) WriteRegBits(SWITCH_PAGE_02_GMNGCFG,0x3c,2,x)
#define Rd_switch_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RESERVED(x) ReadRegBits(SWITCH_PAGE_02_GMNGCFG,0x3c,2)
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RESERVED_MASK       0x3c
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RESERVED_ALIGN      0
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RESERVED_BITS       4
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RESERVED_SHIFT      2

/* switch :: PAGE_02_GMNGCFG :: PAGE_02_GMNGCFG_RXBPDU_EN [01:01] */
#define Wr_switch_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RXBPDU_EN(x) WriteRegBits(SWITCH_PAGE_02_GMNGCFG,0x2,1,x)
#define Rd_switch_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RXBPDU_EN(x) ReadRegBits(SWITCH_PAGE_02_GMNGCFG,0x2,1)
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RXBPDU_EN_MASK      0x02
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RXBPDU_EN_ALIGN     0
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RXBPDU_EN_BITS      1
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RXBPDU_EN_SHIFT     1

/* switch :: PAGE_02_GMNGCFG :: PAGE_02_GMNGCFG_RST_MIB_CNT [00:00] */
#define Wr_switch_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RST_MIB_CNT(x) WriteRegBits(SWITCH_PAGE_02_GMNGCFG,0x1,0,x)
#define Rd_switch_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RST_MIB_CNT(x) ReadRegBits(SWITCH_PAGE_02_GMNGCFG,0x1,0)
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RST_MIB_CNT_MASK    0x01
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RST_MIB_CNT_ALIGN   0
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RST_MIB_CNT_BITS    1
#define SWITCH_PAGE_02_GMNGCFG_PAGE_02_GMNGCFG_RST_MIB_CNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_02_IMP0_PRT_ID
 ***************************************************************************/
/* switch :: PAGE_02_IMP0_PRT_ID :: PAGE_02_IMP0_PRT_ID_RESERVED [07:04] */
#define Wr_switch_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_RESERVED(x) WriteRegBits(SWITCH_PAGE_02_IMP0_PRT_ID,0xf0,4,x)
#define Rd_switch_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_RESERVED(x) ReadRegBits(SWITCH_PAGE_02_IMP0_PRT_ID,0xf0,4)
#define SWITCH_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_RESERVED_MASK 0xf0
#define SWITCH_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_RESERVED_ALIGN 0
#define SWITCH_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_RESERVED_BITS 4
#define SWITCH_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_RESERVED_SHIFT 4

/* switch :: PAGE_02_IMP0_PRT_ID :: PAGE_02_IMP0_PRT_ID_IMP0_PRT_ID [03:00] */
#define Wr_switch_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_IMP0_PRT_ID(x) WriteRegBits(SWITCH_PAGE_02_IMP0_PRT_ID,0xf,0,x)
#define Rd_switch_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_IMP0_PRT_ID(x) ReadRegBits(SWITCH_PAGE_02_IMP0_PRT_ID,0xf,0)
#define SWITCH_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_IMP0_PRT_ID_MASK 0x0f
#define SWITCH_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_IMP0_PRT_ID_ALIGN 0
#define SWITCH_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_IMP0_PRT_ID_BITS 4
#define SWITCH_PAGE_02_IMP0_PRT_ID_PAGE_02_IMP0_PRT_ID_IMP0_PRT_ID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_IMP1_PRT_ID
 ***************************************************************************/
/* switch :: PAGE_02_IMP1_PRT_ID :: PAGE_02_IMP1_PRT_ID_RESERVED [07:04] */
#define Wr_switch_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_RESERVED(x) WriteRegBits(SWITCH_PAGE_02_IMP1_PRT_ID,0xf0,4,x)
#define Rd_switch_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_RESERVED(x) ReadRegBits(SWITCH_PAGE_02_IMP1_PRT_ID,0xf0,4)
#define SWITCH_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_RESERVED_MASK 0xf0
#define SWITCH_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_RESERVED_ALIGN 0
#define SWITCH_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_RESERVED_BITS 4
#define SWITCH_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_RESERVED_SHIFT 4

/* switch :: PAGE_02_IMP1_PRT_ID :: PAGE_02_IMP1_PRT_ID_IMP1_PRT_ID [03:00] */
#define Wr_switch_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_IMP1_PRT_ID(x) WriteRegBits(SWITCH_PAGE_02_IMP1_PRT_ID,0xf,0,x)
#define Rd_switch_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_IMP1_PRT_ID(x) ReadRegBits(SWITCH_PAGE_02_IMP1_PRT_ID,0xf,0)
#define SWITCH_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_IMP1_PRT_ID_MASK 0x0f
#define SWITCH_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_IMP1_PRT_ID_ALIGN 0
#define SWITCH_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_IMP1_PRT_ID_BITS 4
#define SWITCH_PAGE_02_IMP1_PRT_ID_PAGE_02_IMP1_PRT_ID_IMP1_PRT_ID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_BRCM_HDR_CTRL
 ***************************************************************************/
/* switch :: PAGE_02_BRCM_HDR_CTRL :: PAGE_02_BRCM_HDR_CTRL_RESERVED [07:03] */
#define Wr_switch_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_02_BRCM_HDR_CTRL,0xf8,3,x)
#define Rd_switch_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_02_BRCM_HDR_CTRL,0xf8,3)
#define SWITCH_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_RESERVED_MASK 0xf8
#define SWITCH_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_RESERVED_BITS 5
#define SWITCH_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_RESERVED_SHIFT 3

/* switch :: PAGE_02_BRCM_HDR_CTRL :: PAGE_02_BRCM_HDR_CTRL_BRCM_HDR_EN [02:00] */
#define Wr_switch_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_BRCM_HDR_EN(x) WriteRegBits(SWITCH_PAGE_02_BRCM_HDR_CTRL,0x7,0,x)
#define Rd_switch_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_BRCM_HDR_EN(x) ReadRegBits(SWITCH_PAGE_02_BRCM_HDR_CTRL,0x7,0)
#define SWITCH_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_BRCM_HDR_EN_MASK 0x07
#define SWITCH_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_BRCM_HDR_EN_ALIGN 0
#define SWITCH_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_BRCM_HDR_EN_BITS 3
#define SWITCH_PAGE_02_BRCM_HDR_CTRL_PAGE_02_BRCM_HDR_CTRL_BRCM_HDR_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_SPTAGT
 ***************************************************************************/
/* switch :: PAGE_02_SPTAGT :: PAGE_02_SPTAGT_RESERVED [31:21] */
#define Wr_switch_PAGE_02_SPTAGT_PAGE_02_SPTAGT_RESERVED(x) WriteRegBits(SWITCH_PAGE_02_SPTAGT,0xffe00000,21,x)
#define Rd_switch_PAGE_02_SPTAGT_PAGE_02_SPTAGT_RESERVED(x) ReadRegBits(SWITCH_PAGE_02_SPTAGT,0xffe00000,21)
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_RESERVED_MASK         0xffe00000
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_RESERVED_ALIGN        0
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_RESERVED_BITS         11
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_RESERVED_SHIFT        21

/* switch :: PAGE_02_SPTAGT :: PAGE_02_SPTAGT_AGE_CHANGE_EN [20:20] */
#define Wr_switch_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_CHANGE_EN(x) WriteRegBits(SWITCH_PAGE_02_SPTAGT,0x100000,20,x)
#define Rd_switch_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_CHANGE_EN(x) ReadRegBits(SWITCH_PAGE_02_SPTAGT,0x100000,20)
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_CHANGE_EN_MASK    0x00100000
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_CHANGE_EN_ALIGN   0
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_CHANGE_EN_BITS    1
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_CHANGE_EN_SHIFT   20

/* switch :: PAGE_02_SPTAGT :: PAGE_02_SPTAGT_AGE_TIME [19:00] */
#define Wr_switch_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_TIME(x) WriteRegBits(SWITCH_PAGE_02_SPTAGT,0xfffff,0,x)
#define Rd_switch_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_TIME(x) ReadRegBits(SWITCH_PAGE_02_SPTAGT,0xfffff,0)
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_TIME_MASK         0x000fffff
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_TIME_ALIGN        0
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_TIME_BITS         20
#define SWITCH_PAGE_02_SPTAGT_PAGE_02_SPTAGT_AGE_TIME_SHIFT        0


/****************************************************************************
 * switch :: PAGE_02_BRCM_HDR_CTRL2
 ***************************************************************************/
/* switch :: PAGE_02_BRCM_HDR_CTRL2 :: PAGE_02_BRCM_HDR_CTRL2_RESERVED_1 [15:09] */
#define Wr_switch_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_02_BRCM_HDR_CTRL2,0xfe00,9,x)
#define Rd_switch_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_02_BRCM_HDR_CTRL2,0xfe00,9)
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_1_MASK 0xfe00
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_1_BITS 7
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_1_SHIFT 9

/* switch :: PAGE_02_BRCM_HDR_CTRL2 :: PAGE_02_BRCM_HDR_CTRL2_RESERVED_0 [08:07] */
#define Wr_switch_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_02_BRCM_HDR_CTRL2,0x180,7,x)
#define Rd_switch_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_02_BRCM_HDR_CTRL2,0x180,7)
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_0_MASK 0x0180
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_0_BITS 2
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_RESERVED_0_SHIFT 7

/* switch :: PAGE_02_BRCM_HDR_CTRL2 :: PAGE_02_BRCM_HDR_CTRL2_BRCM_HDR_EN [06:00] */
#define Wr_switch_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_BRCM_HDR_EN(x) WriteRegBits16(SWITCH_PAGE_02_BRCM_HDR_CTRL2,0x7f,0,x)
#define Rd_switch_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_BRCM_HDR_EN(x) ReadRegBits16(SWITCH_PAGE_02_BRCM_HDR_CTRL2,0x7f,0)
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_BRCM_HDR_EN_MASK 0x007f
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_BRCM_HDR_EN_ALIGN 0
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_BRCM_HDR_EN_BITS 7
#define SWITCH_PAGE_02_BRCM_HDR_CTRL2_PAGE_02_BRCM_HDR_CTRL2_BRCM_HDR_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_IPG_SHRNK_CTRL
 ***************************************************************************/
/* switch :: PAGE_02_IPG_SHRNK_CTRL :: PAGE_02_IPG_SHRNK_CTRL_RESERVED [31:18] */
#define Wr_switch_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_02_IPG_SHRNK_CTRL,0xfffc0000,18,x)
#define Rd_switch_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_02_IPG_SHRNK_CTRL,0xfffc0000,18)
#define SWITCH_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_RESERVED_BITS 14
#define SWITCH_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_RESERVED_SHIFT 18

/* switch :: PAGE_02_IPG_SHRNK_CTRL :: PAGE_02_IPG_SHRNK_CTRL_IPG_SHKCTRL [17:00] */
#define Wr_switch_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_IPG_SHKCTRL(x) WriteRegBits(SWITCH_PAGE_02_IPG_SHRNK_CTRL,0x3ffff,0,x)
#define Rd_switch_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_IPG_SHKCTRL(x) ReadRegBits(SWITCH_PAGE_02_IPG_SHRNK_CTRL,0x3ffff,0)
#define SWITCH_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_IPG_SHKCTRL_MASK 0x0003ffff
#define SWITCH_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_IPG_SHKCTRL_ALIGN 0
#define SWITCH_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_IPG_SHKCTRL_BITS 18
#define SWITCH_PAGE_02_IPG_SHRNK_CTRL_PAGE_02_IPG_SHRNK_CTRL_IPG_SHKCTRL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_MIRCAPCTL
 ***************************************************************************/
/* switch :: PAGE_02_MIRCAPCTL :: PAGE_02_MIRCAPCTL_MIR_EN [15:15] */
#define Wr_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_MIR_EN(x) WriteRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0x8000,15,x)
#define Rd_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_MIR_EN(x) ReadRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0x8000,15)
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_MIR_EN_MASK     0x8000
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_MIR_EN_ALIGN    0
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_MIR_EN_BITS     1
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_MIR_EN_SHIFT    15

/* switch :: PAGE_02_MIRCAPCTL :: PAGE_02_MIRCAPCTL_BLK_NOT_MIR [14:14] */
#define Wr_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_BLK_NOT_MIR(x) WriteRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0x4000,14,x)
#define Rd_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_BLK_NOT_MIR(x) ReadRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0x4000,14)
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_BLK_NOT_MIR_MASK 0x4000
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_BLK_NOT_MIR_ALIGN 0
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_BLK_NOT_MIR_BITS 1
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_BLK_NOT_MIR_SHIFT 14

/* switch :: PAGE_02_MIRCAPCTL :: PAGE_02_MIRCAPCTL_RESERVED_1 [13:06] */
#define Wr_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0x3fc0,6,x)
#define Rd_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0x3fc0,6)
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_1_MASK 0x3fc0
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_1_BITS 8
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_1_SHIFT 6

/* switch :: PAGE_02_MIRCAPCTL :: PAGE_02_MIRCAPCTL_RESERVED_0 [05:04] */
#define Wr_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0x30,4,x)
#define Rd_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0x30,4)
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_0_MASK 0x0030
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_0_BITS 2
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_RESERVED_0_SHIFT 4

/* switch :: PAGE_02_MIRCAPCTL :: PAGE_02_MIRCAPCTL_SMIR_CAP_PORT [03:00] */
#define Wr_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_SMIR_CAP_PORT(x) WriteRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0xf,0,x)
#define Rd_switch_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_SMIR_CAP_PORT(x) ReadRegBits16(SWITCH_PAGE_02_MIRCAPCTL,0xf,0)
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_SMIR_CAP_PORT_MASK 0x000f
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_SMIR_CAP_PORT_ALIGN 0
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_SMIR_CAP_PORT_BITS 4
#define SWITCH_PAGE_02_MIRCAPCTL_PAGE_02_MIRCAPCTL_SMIR_CAP_PORT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_IGMIRCTL
 ***************************************************************************/
/* switch :: PAGE_02_IGMIRCTL :: PAGE_02_IGMIRCTL_IN_MIR_FLTR [15:14] */
#define Wr_switch_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_FLTR(x) WriteRegBits16(SWITCH_PAGE_02_IGMIRCTL,0xc000,14,x)
#define Rd_switch_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_FLTR(x) ReadRegBits16(SWITCH_PAGE_02_IGMIRCTL,0xc000,14)
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_FLTR_MASK  0xc000
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_FLTR_ALIGN 0
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_FLTR_BITS  2
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_FLTR_SHIFT 14

/* switch :: PAGE_02_IGMIRCTL :: PAGE_02_IGMIRCTL_IN_DIV_EN [13:13] */
#define Wr_switch_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_DIV_EN(x) WriteRegBits16(SWITCH_PAGE_02_IGMIRCTL,0x2000,13,x)
#define Rd_switch_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_DIV_EN(x) ReadRegBits16(SWITCH_PAGE_02_IGMIRCTL,0x2000,13)
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_DIV_EN_MASK    0x2000
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_DIV_EN_ALIGN   0
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_DIV_EN_BITS    1
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_DIV_EN_SHIFT   13

/* switch :: PAGE_02_IGMIRCTL :: PAGE_02_IGMIRCTL_RESERVED [12:09] */
#define Wr_switch_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_02_IGMIRCTL,0x1e00,9,x)
#define Rd_switch_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_02_IGMIRCTL,0x1e00,9)
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_RESERVED_MASK     0x1e00
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_RESERVED_ALIGN    0
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_RESERVED_BITS     4
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_RESERVED_SHIFT    9

/* switch :: PAGE_02_IGMIRCTL :: PAGE_02_IGMIRCTL_IN_MIR_MSK [08:00] */
#define Wr_switch_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_MSK(x) WriteRegBits16(SWITCH_PAGE_02_IGMIRCTL,0x1ff,0,x)
#define Rd_switch_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_MSK(x) ReadRegBits16(SWITCH_PAGE_02_IGMIRCTL,0x1ff,0)
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_MSK_MASK   0x01ff
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_MSK_ALIGN  0
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_MSK_BITS   9
#define SWITCH_PAGE_02_IGMIRCTL_PAGE_02_IGMIRCTL_IN_MIR_MSK_SHIFT  0


/****************************************************************************
 * switch :: PAGE_02_IGMIRDIV
 ***************************************************************************/
/* switch :: PAGE_02_IGMIRDIV :: PAGE_02_IGMIRDIV_RESERVED [15:10] */
#define Wr_switch_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_RESERVED(x) WriteRegBits16(SWITCH_PAGE_02_IGMIRDIV,0xfc00,10,x)
#define Rd_switch_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_RESERVED(x) ReadRegBits16(SWITCH_PAGE_02_IGMIRDIV,0xfc00,10)
#define SWITCH_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_RESERVED_MASK     0xfc00
#define SWITCH_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_RESERVED_ALIGN    0
#define SWITCH_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_RESERVED_BITS     6
#define SWITCH_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_RESERVED_SHIFT    10

/* switch :: PAGE_02_IGMIRDIV :: PAGE_02_IGMIRDIV_IN_MIR_DIV [09:00] */
#define Wr_switch_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_IN_MIR_DIV(x) WriteRegBits16(SWITCH_PAGE_02_IGMIRDIV,0x3ff,0,x)
#define Rd_switch_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_IN_MIR_DIV(x) ReadRegBits16(SWITCH_PAGE_02_IGMIRDIV,0x3ff,0)
#define SWITCH_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_IN_MIR_DIV_MASK   0x03ff
#define SWITCH_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_IN_MIR_DIV_ALIGN  0
#define SWITCH_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_IN_MIR_DIV_BITS   10
#define SWITCH_PAGE_02_IGMIRDIV_PAGE_02_IGMIRDIV_IN_MIR_DIV_SHIFT  0


/****************************************************************************
 * switch :: PAGE_02_IGMIRMAC
 ***************************************************************************/
/* switch :: PAGE_02_IGMIRMAC :: reserved0 [63:48] */
#define SWITCH_PAGE_02_IGMIRMAC_RESERVED0_MASK                     0xffff000000000000
#define SWITCH_PAGE_02_IGMIRMAC_RESERVED0_ALIGN                    0
#define SWITCH_PAGE_02_IGMIRMAC_RESERVED0_BITS                     16
#define SWITCH_PAGE_02_IGMIRMAC_RESERVED0_SHIFT                    48

/* switch :: PAGE_02_IGMIRMAC :: PAGE_02_IGMIRMAC_IN_MIR_MAC [47:00] */
#define Wr_switch_PAGE_02_IGMIRMAC_PAGE_02_IGMIRMAC_IN_MIR_MAC(x) WriteRegBits(SWITCH_PAGE_02_IGMIRMAC,0xffffffffffff,0,x)
#define Rd_switch_PAGE_02_IGMIRMAC_PAGE_02_IGMIRMAC_IN_MIR_MAC(x) ReadRegBits(SWITCH_PAGE_02_IGMIRMAC,0xffffffffffff,0)
#define SWITCH_PAGE_02_IGMIRMAC_PAGE_02_IGMIRMAC_IN_MIR_MAC_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_02_IGMIRMAC_PAGE_02_IGMIRMAC_IN_MIR_MAC_ALIGN  0
#define SWITCH_PAGE_02_IGMIRMAC_PAGE_02_IGMIRMAC_IN_MIR_MAC_BITS   48
#define SWITCH_PAGE_02_IGMIRMAC_PAGE_02_IGMIRMAC_IN_MIR_MAC_SHIFT  0


/****************************************************************************
 * switch :: PAGE_02_EGMIRCTL
 ***************************************************************************/
/* switch :: PAGE_02_EGMIRCTL :: PAGE_02_EGMIRCTL_OUT_MIR_FLTR [15:14] */
#define Wr_switch_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_FLTR(x) WriteRegBits16(SWITCH_PAGE_02_EGMIRCTL,0xc000,14,x)
#define Rd_switch_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_FLTR(x) ReadRegBits16(SWITCH_PAGE_02_EGMIRCTL,0xc000,14)
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_FLTR_MASK 0xc000
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_FLTR_ALIGN 0
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_FLTR_BITS 2
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_FLTR_SHIFT 14

/* switch :: PAGE_02_EGMIRCTL :: PAGE_02_EGMIRCTL_OUT_DIV_EN [13:13] */
#define Wr_switch_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_DIV_EN(x) WriteRegBits16(SWITCH_PAGE_02_EGMIRCTL,0x2000,13,x)
#define Rd_switch_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_DIV_EN(x) ReadRegBits16(SWITCH_PAGE_02_EGMIRCTL,0x2000,13)
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_DIV_EN_MASK   0x2000
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_DIV_EN_ALIGN  0
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_DIV_EN_BITS   1
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_DIV_EN_SHIFT  13

/* switch :: PAGE_02_EGMIRCTL :: PAGE_02_EGMIRCTL_RESERVED [12:09] */
#define Wr_switch_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_02_EGMIRCTL,0x1e00,9,x)
#define Rd_switch_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_02_EGMIRCTL,0x1e00,9)
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_RESERVED_MASK     0x1e00
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_RESERVED_ALIGN    0
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_RESERVED_BITS     4
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_RESERVED_SHIFT    9

/* switch :: PAGE_02_EGMIRCTL :: PAGE_02_EGMIRCTL_OUT_MIR_MSK [08:00] */
#define Wr_switch_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_MSK(x) WriteRegBits16(SWITCH_PAGE_02_EGMIRCTL,0x1ff,0,x)
#define Rd_switch_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_MSK(x) ReadRegBits16(SWITCH_PAGE_02_EGMIRCTL,0x1ff,0)
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_MSK_MASK  0x01ff
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_MSK_ALIGN 0
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_MSK_BITS  9
#define SWITCH_PAGE_02_EGMIRCTL_PAGE_02_EGMIRCTL_OUT_MIR_MSK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_EGMIRDIV
 ***************************************************************************/
/* switch :: PAGE_02_EGMIRDIV :: PAGE_02_EGMIRDIV_RESERVED [15:10] */
#define Wr_switch_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_RESERVED(x) WriteRegBits16(SWITCH_PAGE_02_EGMIRDIV,0xfc00,10,x)
#define Rd_switch_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_RESERVED(x) ReadRegBits16(SWITCH_PAGE_02_EGMIRDIV,0xfc00,10)
#define SWITCH_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_RESERVED_MASK     0xfc00
#define SWITCH_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_RESERVED_ALIGN    0
#define SWITCH_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_RESERVED_BITS     6
#define SWITCH_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_RESERVED_SHIFT    10

/* switch :: PAGE_02_EGMIRDIV :: PAGE_02_EGMIRDIV_OUT_MIR_DIV [09:00] */
#define Wr_switch_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_OUT_MIR_DIV(x) WriteRegBits16(SWITCH_PAGE_02_EGMIRDIV,0x3ff,0,x)
#define Rd_switch_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_OUT_MIR_DIV(x) ReadRegBits16(SWITCH_PAGE_02_EGMIRDIV,0x3ff,0)
#define SWITCH_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_OUT_MIR_DIV_MASK  0x03ff
#define SWITCH_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_OUT_MIR_DIV_ALIGN 0
#define SWITCH_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_OUT_MIR_DIV_BITS  10
#define SWITCH_PAGE_02_EGMIRDIV_PAGE_02_EGMIRDIV_OUT_MIR_DIV_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_EGMIRMAC
 ***************************************************************************/
/* switch :: PAGE_02_EGMIRMAC :: reserved0 [63:48] */
#define SWITCH_PAGE_02_EGMIRMAC_RESERVED0_MASK                     0xffff000000000000
#define SWITCH_PAGE_02_EGMIRMAC_RESERVED0_ALIGN                    0
#define SWITCH_PAGE_02_EGMIRMAC_RESERVED0_BITS                     16
#define SWITCH_PAGE_02_EGMIRMAC_RESERVED0_SHIFT                    48

/* switch :: PAGE_02_EGMIRMAC :: PAGE_02_EGMIRMAC_OUT_MIR_MAC [47:00] */
#define Wr_switch_PAGE_02_EGMIRMAC_PAGE_02_EGMIRMAC_OUT_MIR_MAC(x) WriteRegBits(SWITCH_PAGE_02_EGMIRMAC,0xffffffffffff,0,x)
#define Rd_switch_PAGE_02_EGMIRMAC_PAGE_02_EGMIRMAC_OUT_MIR_MAC(x) ReadRegBits(SWITCH_PAGE_02_EGMIRMAC,0xffffffffffff,0)
#define SWITCH_PAGE_02_EGMIRMAC_PAGE_02_EGMIRMAC_OUT_MIR_MAC_MASK  0x0000ffffffffffff
#define SWITCH_PAGE_02_EGMIRMAC_PAGE_02_EGMIRMAC_OUT_MIR_MAC_ALIGN 0
#define SWITCH_PAGE_02_EGMIRMAC_PAGE_02_EGMIRMAC_OUT_MIR_MAC_BITS  48
#define SWITCH_PAGE_02_EGMIRMAC_PAGE_02_EGMIRMAC_OUT_MIR_MAC_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_SPANCTL
 ***************************************************************************/
/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_SPAN_CTL [31:30] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_CTL(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0xc0000000,30,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_CTL(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0xc0000000,30)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_CTL_MASK       0xc0000000
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_CTL_ALIGN      0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_CTL_BITS       2
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_CTL_SHIFT      30

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_SPAN_SRC_TYPE_SELECT [29:28] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_TYPE_SELECT(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0x30000000,28,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_TYPE_SELECT(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0x30000000,28)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_TYPE_SELECT_MASK 0x30000000
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_TYPE_SELECT_ALIGN 0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_TYPE_SELECT_BITS 2
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_TYPE_SELECT_SHIFT 28

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_BLK_DST_PORT [27:27] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_BLK_DST_PORT(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0x8000000,27,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_BLK_DST_PORT(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0x8000000,27)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_BLK_DST_PORT_MASK   0x08000000
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_BLK_DST_PORT_ALIGN  0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_BLK_DST_PORT_BITS   1
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_BLK_DST_PORT_SHIFT  27

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_REF_PORT_EN [26:26] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_EN(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0x4000000,26,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_EN(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0x4000000,26)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_EN_MASK    0x04000000
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_EN_ALIGN   0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_EN_BITS    1
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_EN_SHIFT   26

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_REF_PORT [25:22] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0x3c00000,22,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0x3c00000,22)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_MASK       0x03c00000
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_ALIGN      0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_BITS       4
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_REF_PORT_SHIFT      22

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_INTER_SW [21:21] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_INTER_SW(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0x200000,21,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_INTER_SW(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0x200000,21)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_INTER_SW_MASK       0x00200000
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_INTER_SW_ALIGN      0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_INTER_SW_BITS       1
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_INTER_SW_SHIFT      21

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_SPT_DROP_EN [20:20] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPT_DROP_EN(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0x100000,20,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPT_DROP_EN(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0x100000,20)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPT_DROP_EN_MASK    0x00100000
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPT_DROP_EN_ALIGN   0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPT_DROP_EN_BITS    1
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPT_DROP_EN_SHIFT   20

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_EAP_DROP_EN [19:19] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_EAP_DROP_EN(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0x80000,19,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_EAP_DROP_EN(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0x80000,19)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_EAP_DROP_EN_MASK    0x00080000
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_EAP_DROP_EN_ALIGN   0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_EAP_DROP_EN_BITS    1
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_EAP_DROP_EN_SHIFT   19

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_RESERVED [18:16] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_RESERVED(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0x70000,16,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_RESERVED(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0x70000,16)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_RESERVED_MASK       0x00070000
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_RESERVED_ALIGN      0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_RESERVED_BITS       3
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_RESERVED_SHIFT      16

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_SPAN_SRC [15:04] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0xfff0,4,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0xfff0,4)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_MASK       0x0000fff0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_ALIGN      0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_BITS       12
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_SRC_SHIFT      4

/* switch :: PAGE_02_SPANCTL :: PAGE_02_SPANCTL_SPAN_DST_PORT_ID [03:00] */
#define Wr_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_DST_PORT_ID(x) WriteRegBits(SWITCH_PAGE_02_SPANCTL,0xf,0,x)
#define Rd_switch_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_DST_PORT_ID(x) ReadRegBits(SWITCH_PAGE_02_SPANCTL,0xf,0)
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_DST_PORT_ID_MASK 0x0000000f
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_DST_PORT_ID_ALIGN 0
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_DST_PORT_ID_BITS 4
#define SWITCH_PAGE_02_SPANCTL_PAGE_02_SPANCTL_SPAN_DST_PORT_ID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_RSPANVLAN
 ***************************************************************************/
/* switch :: PAGE_02_RSPANVLAN :: PAGE_02_RSPANVLAN_RESERVED [15:12] */
#define Wr_switch_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_02_RSPANVLAN,0xf000,12,x)
#define Rd_switch_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_02_RSPANVLAN,0xf000,12)
#define SWITCH_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RESERVED_MASK   0xf000
#define SWITCH_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RESERVED_ALIGN  0
#define SWITCH_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RESERVED_BITS   4
#define SWITCH_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RESERVED_SHIFT  12

/* switch :: PAGE_02_RSPANVLAN :: PAGE_02_RSPANVLAN_RSPAN_VLAN [11:00] */
#define Wr_switch_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RSPAN_VLAN(x) WriteRegBits16(SWITCH_PAGE_02_RSPANVLAN,0xfff,0,x)
#define Rd_switch_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RSPAN_VLAN(x) ReadRegBits16(SWITCH_PAGE_02_RSPANVLAN,0xfff,0)
#define SWITCH_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RSPAN_VLAN_MASK 0x0fff
#define SWITCH_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RSPAN_VLAN_ALIGN 0
#define SWITCH_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RSPAN_VLAN_BITS 12
#define SWITCH_PAGE_02_RSPANVLAN_PAGE_02_RSPANVLAN_RSPAN_VLAN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_MODEL_ID
 ***************************************************************************/
/* switch :: PAGE_02_MODEL_ID :: PAGE_02_MODEL_ID_MODELID [31:00] */
#define Wr_switch_PAGE_02_MODEL_ID_PAGE_02_MODEL_ID_MODELID(x) WriteReg(SWITCH_PAGE_02_MODEL_ID,x)
#define Rd_switch_PAGE_02_MODEL_ID_PAGE_02_MODEL_ID_MODELID(x) ReadReg(SWITCH_PAGE_02_MODEL_ID)
#define SWITCH_PAGE_02_MODEL_ID_PAGE_02_MODEL_ID_MODELID_MASK      0xffffffff
#define SWITCH_PAGE_02_MODEL_ID_PAGE_02_MODEL_ID_MODELID_ALIGN     0
#define SWITCH_PAGE_02_MODEL_ID_PAGE_02_MODEL_ID_MODELID_BITS      32
#define SWITCH_PAGE_02_MODEL_ID_PAGE_02_MODEL_ID_MODELID_SHIFT     0


/****************************************************************************
 * switch :: PAGE_02_CHIP_REVID
 ***************************************************************************/
/* switch :: PAGE_02_CHIP_REVID :: PAGE_02_CHIP_REVID_REVID [07:00] */
#define Wr_switch_PAGE_02_CHIP_REVID_PAGE_02_CHIP_REVID_REVID(x) WriteReg(SWITCH_PAGE_02_CHIP_REVID,x)
#define Rd_switch_PAGE_02_CHIP_REVID_PAGE_02_CHIP_REVID_REVID(x) ReadReg(SWITCH_PAGE_02_CHIP_REVID)
#define SWITCH_PAGE_02_CHIP_REVID_PAGE_02_CHIP_REVID_REVID_MASK    0xff
#define SWITCH_PAGE_02_CHIP_REVID_PAGE_02_CHIP_REVID_REVID_ALIGN   0
#define SWITCH_PAGE_02_CHIP_REVID_PAGE_02_CHIP_REVID_REVID_BITS    8
#define SWITCH_PAGE_02_CHIP_REVID_PAGE_02_CHIP_REVID_REVID_SHIFT   0


/****************************************************************************
 * switch :: PAGE_02_HL_PRTC_CTRL
 ***************************************************************************/
/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_RESERVED_1 [31:19] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0xfff80000,19,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0xfff80000,19)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_1_MASK 0xfff80000
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_1_BITS 13
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_1_SHIFT 19

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_MLD_QRY_FWD_MODE [18:18] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_FWD_MODE(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x40000,18,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_FWD_MODE(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x40000,18)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_MASK 0x00040000
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_FWD_MODE_SHIFT 18

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_MLD_QRY_EN [17:17] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x20000,17,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x20000,17)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_EN_MASK 0x00020000
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_QRY_EN_SHIFT 17

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE [16:16] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x10000,16,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x10000,16)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_MASK 0x00010000
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_FWD_MODE_SHIFT 16

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_EN [15:15] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x8000,15,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x8000,15)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_EN_MASK 0x00008000
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_MLD_RPTDONE_EN_SHIFT 15

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE [14:14] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x4000,14,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x4000,14)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_MASK 0x00004000
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_FWD_MODE_SHIFT 14

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_IGMP_UKN_EN [13:13] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x2000,13,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x2000,13)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_EN_MASK 0x00002000
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_UKN_EN_SHIFT 13

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE [12:12] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x1000,12,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x1000,12)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_MASK 0x00001000
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_FWD_MODE_SHIFT 12

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_IGMP_QRY_EN [11:11] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x800,11,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x800,11)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_EN_MASK 0x00000800
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_QRY_EN_SHIFT 11

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE [10:10] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x400,10,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x400,10)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_MASK 0x00000400
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_FWD_MODE_SHIFT 10

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_EN [09:09] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x200,9,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x200,9)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_EN_MASK 0x00000200
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_RPTLVE_EN_SHIFT 9

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_IGMP_DIP_EN [08:08] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_DIP_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x100,8,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_DIP_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x100,8)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_DIP_EN_MASK 0x00000100
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_DIP_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_DIP_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_IGMP_DIP_EN_SHIFT 8

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_RESERVED_0 [07:06] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0xc0,6,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0xc0,6)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_0_MASK 0x000000c0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_0_BITS 2
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RESERVED_0_SHIFT 6

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_ICMPv6_FWD_MODE [05:05] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPv6_FWD_MODE(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x20,5,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPv6_FWD_MODE(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x20,5)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_FWD_MODE_MASK 0x00000020
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_FWD_MODE_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_FWD_MODE_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_FWD_MODE_SHIFT 5

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_ICMPV6_EN [04:04] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x10,4,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x10,4)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_EN_MASK 0x00000010
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV6_EN_SHIFT 4

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_ICMPV4_EN [03:03] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV4_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x8,3,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV4_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x8,3)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV4_EN_MASK 0x00000008
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV4_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV4_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ICMPV4_EN_SHIFT 3

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_DHCP_EN [02:02] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_DHCP_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x4,2,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_DHCP_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x4,2)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_DHCP_EN_MASK 0x00000004
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_DHCP_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_DHCP_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_DHCP_EN_SHIFT 2

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_RARP_EN [01:01] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RARP_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x2,1,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RARP_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x2,1)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RARP_EN_MASK 0x00000002
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RARP_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RARP_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_RARP_EN_SHIFT 1

/* switch :: PAGE_02_HL_PRTC_CTRL :: PAGE_02_HL_PRTC_CTRL_ARP_EN [00:00] */
#define Wr_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ARP_EN(x) WriteRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x1,0,x)
#define Rd_switch_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ARP_EN(x) ReadRegBits(SWITCH_PAGE_02_HL_PRTC_CTRL,0x1,0)
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ARP_EN_MASK 0x00000001
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ARP_EN_ALIGN 0
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ARP_EN_BITS 1
#define SWITCH_PAGE_02_HL_PRTC_CTRL_PAGE_02_HL_PRTC_CTRL_ARP_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_RST_MIB_CNT_EN
 ***************************************************************************/
/* switch :: PAGE_02_RST_MIB_CNT_EN :: PAGE_02_RST_MIB_CNT_EN_RESERVED [15:09] */
#define Wr_switch_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_02_RST_MIB_CNT_EN,0xfe00,9,x)
#define Rd_switch_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_02_RST_MIB_CNT_EN,0xfe00,9)
#define SWITCH_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RESERVED_ALIGN 0
#define SWITCH_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RESERVED_BITS 7
#define SWITCH_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RESERVED_SHIFT 9

/* switch :: PAGE_02_RST_MIB_CNT_EN :: PAGE_02_RST_MIB_CNT_EN_RST_MIB_CNT_EN [08:00] */
#define Wr_switch_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RST_MIB_CNT_EN(x) WriteRegBits16(SWITCH_PAGE_02_RST_MIB_CNT_EN,0x1ff,0,x)
#define Rd_switch_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RST_MIB_CNT_EN(x) ReadRegBits16(SWITCH_PAGE_02_RST_MIB_CNT_EN,0x1ff,0)
#define SWITCH_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RST_MIB_CNT_EN_MASK 0x01ff
#define SWITCH_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RST_MIB_CNT_EN_ALIGN 0
#define SWITCH_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RST_MIB_CNT_EN_BITS 9
#define SWITCH_PAGE_02_RST_MIB_CNT_EN_PAGE_02_RST_MIB_CNT_EN_RST_MIB_CNT_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_IPG_SHRINK_2G_WA
 ***************************************************************************/
/* switch :: PAGE_02_IPG_SHRINK_2G_WA :: PAGE_02_IPG_SHRINK_2G_WA_RESERVED [15:09] */
#define Wr_switch_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_RESERVED(x) WriteRegBits16(SWITCH_PAGE_02_IPG_SHRINK_2G_WA,0xfe00,9,x)
#define Rd_switch_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_RESERVED(x) ReadRegBits16(SWITCH_PAGE_02_IPG_SHRINK_2G_WA,0xfe00,9)
#define SWITCH_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_RESERVED_ALIGN 0
#define SWITCH_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_RESERVED_BITS 7
#define SWITCH_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_RESERVED_SHIFT 9

/* switch :: PAGE_02_IPG_SHRINK_2G_WA :: PAGE_02_IPG_SHRINK_2G_WA_VLD2_COND_DIS [08:00] */
#define Wr_switch_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_VLD2_COND_DIS(x) WriteRegBits16(SWITCH_PAGE_02_IPG_SHRINK_2G_WA,0x1ff,0,x)
#define Rd_switch_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_VLD2_COND_DIS(x) ReadRegBits16(SWITCH_PAGE_02_IPG_SHRINK_2G_WA,0x1ff,0)
#define SWITCH_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_VLD2_COND_DIS_MASK 0x01ff
#define SWITCH_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_VLD2_COND_DIS_ALIGN 0
#define SWITCH_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_VLD2_COND_DIS_BITS 9
#define SWITCH_PAGE_02_IPG_SHRINK_2G_WA_PAGE_02_IPG_SHRINK_2G_WA_VLD2_COND_DIS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_MNGMODE_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_02_MNGMODE_REG_SPARE0 :: PAGE_02_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_02_MNGMODE_REG_SPARE0_PAGE_02_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0(x) WriteReg(SWITCH_PAGE_02_MNGMODE_REG_SPARE0,x)
#define Rd_switch_PAGE_02_MNGMODE_REG_SPARE0_PAGE_02_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0(x) ReadReg(SWITCH_PAGE_02_MNGMODE_REG_SPARE0)
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE0_PAGE_02_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE0_PAGE_02_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE0_PAGE_02_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_BITS 32
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE0_PAGE_02_MNGMODE_REG_SPARE0_MNGMODE_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_02_MNGMODE_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_02_MNGMODE_REG_SPARE1 :: PAGE_02_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_02_MNGMODE_REG_SPARE1_PAGE_02_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1(x) WriteReg(SWITCH_PAGE_02_MNGMODE_REG_SPARE1,x)
#define Rd_switch_PAGE_02_MNGMODE_REG_SPARE1_PAGE_02_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1(x) ReadReg(SWITCH_PAGE_02_MNGMODE_REG_SPARE1)
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE1_PAGE_02_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE1_PAGE_02_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE1_PAGE_02_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_BITS 32
#define SWITCH_PAGE_02_MNGMODE_REG_SPARE1_PAGE_02_MNGMODE_REG_SPARE1_MNGMODE_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_INT_STS
 ***************************************************************************/
/* switch :: PAGE_03_INT_STS :: PAGE_03_INT_STS_INT_STS [31:00] */
#define Wr_switch_PAGE_03_INT_STS_PAGE_03_INT_STS_INT_STS(x) WriteReg(SWITCH_PAGE_03_INT_STS,x)
#define Rd_switch_PAGE_03_INT_STS_PAGE_03_INT_STS_INT_STS(x) ReadReg(SWITCH_PAGE_03_INT_STS)
#define SWITCH_PAGE_03_INT_STS_PAGE_03_INT_STS_INT_STS_MASK        0xffffffff
#define SWITCH_PAGE_03_INT_STS_PAGE_03_INT_STS_INT_STS_ALIGN       0
#define SWITCH_PAGE_03_INT_STS_PAGE_03_INT_STS_INT_STS_BITS        32
#define SWITCH_PAGE_03_INT_STS_PAGE_03_INT_STS_INT_STS_SHIFT       0


/****************************************************************************
 * switch :: PAGE_03_INT_EN
 ***************************************************************************/
/* switch :: PAGE_03_INT_EN :: PAGE_03_INT_EN_INT_EN [31:00] */
#define Wr_switch_PAGE_03_INT_EN_PAGE_03_INT_EN_INT_EN(x) WriteReg(SWITCH_PAGE_03_INT_EN,x)
#define Rd_switch_PAGE_03_INT_EN_PAGE_03_INT_EN_INT_EN(x) ReadReg(SWITCH_PAGE_03_INT_EN)
#define SWITCH_PAGE_03_INT_EN_PAGE_03_INT_EN_INT_EN_MASK           0xffffffff
#define SWITCH_PAGE_03_INT_EN_PAGE_03_INT_EN_INT_EN_ALIGN          0
#define SWITCH_PAGE_03_INT_EN_PAGE_03_INT_EN_INT_EN_BITS           32
#define SWITCH_PAGE_03_INT_EN_PAGE_03_INT_EN_INT_EN_SHIFT          0


/****************************************************************************
 * switch :: PAGE_03_IMP_SLEEP_TIMER
 ***************************************************************************/
/* switch :: PAGE_03_IMP_SLEEP_TIMER :: PAGE_03_IMP_SLEEP_TIMER_RESERVED [15:13] */
#define Wr_switch_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_IMP_SLEEP_TIMER,0xe000,13,x)
#define Rd_switch_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_IMP_SLEEP_TIMER,0xe000,13)
#define SWITCH_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_RESERVED_MASK 0xe000
#define SWITCH_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_RESERVED_BITS 3
#define SWITCH_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_RESERVED_SHIFT 13

/* switch :: PAGE_03_IMP_SLEEP_TIMER :: PAGE_03_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER [12:00] */
#define Wr_switch_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER(x) WriteRegBits16(SWITCH_PAGE_03_IMP_SLEEP_TIMER,0x1fff,0,x)
#define Rd_switch_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER(x) ReadRegBits16(SWITCH_PAGE_03_IMP_SLEEP_TIMER,0x1fff,0)
#define SWITCH_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_MASK 0x1fff
#define SWITCH_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_ALIGN 0
#define SWITCH_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_BITS 13
#define SWITCH_PAGE_03_IMP_SLEEP_TIMER_PAGE_03_IMP_SLEEP_TIMER_IMP_SLEEP_TIMER_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_PORT7_SLEEP_TIMER
 ***************************************************************************/
/* switch :: PAGE_03_PORT7_SLEEP_TIMER :: PAGE_03_PORT7_SLEEP_TIMER_RESERVED [15:13] */
#define Wr_switch_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_PORT7_SLEEP_TIMER,0xe000,13,x)
#define Rd_switch_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_PORT7_SLEEP_TIMER,0xe000,13)
#define SWITCH_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_RESERVED_MASK 0xe000
#define SWITCH_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_RESERVED_BITS 3
#define SWITCH_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_RESERVED_SHIFT 13

/* switch :: PAGE_03_PORT7_SLEEP_TIMER :: PAGE_03_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER [12:00] */
#define Wr_switch_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER(x) WriteRegBits16(SWITCH_PAGE_03_PORT7_SLEEP_TIMER,0x1fff,0,x)
#define Rd_switch_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER(x) ReadRegBits16(SWITCH_PAGE_03_PORT7_SLEEP_TIMER,0x1fff,0)
#define SWITCH_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_MASK 0x1fff
#define SWITCH_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_ALIGN 0
#define SWITCH_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_BITS 13
#define SWITCH_PAGE_03_PORT7_SLEEP_TIMER_PAGE_03_PORT7_SLEEP_TIMER_PORT7_SLEEP_TIMER_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_WAN_SLEEP_TIMER
 ***************************************************************************/
/* switch :: PAGE_03_WAN_SLEEP_TIMER :: PAGE_03_WAN_SLEEP_TIMER_RESERVED [15:13] */
#define Wr_switch_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_WAN_SLEEP_TIMER,0xe000,13,x)
#define Rd_switch_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_WAN_SLEEP_TIMER,0xe000,13)
#define SWITCH_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_RESERVED_MASK 0xe000
#define SWITCH_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_RESERVED_BITS 3
#define SWITCH_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_RESERVED_SHIFT 13

/* switch :: PAGE_03_WAN_SLEEP_TIMER :: PAGE_03_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER [12:00] */
#define Wr_switch_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER(x) WriteRegBits16(SWITCH_PAGE_03_WAN_SLEEP_TIMER,0x1fff,0,x)
#define Rd_switch_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER(x) ReadRegBits16(SWITCH_PAGE_03_WAN_SLEEP_TIMER,0x1fff,0)
#define SWITCH_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_MASK 0x1fff
#define SWITCH_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_ALIGN 0
#define SWITCH_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_BITS 13
#define SWITCH_PAGE_03_WAN_SLEEP_TIMER_PAGE_03_WAN_SLEEP_TIMER_WAN_SLEEP_TIMER_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_PORT_SLEEP_STS
 ***************************************************************************/
/* switch :: PAGE_03_PORT_SLEEP_STS :: PAGE_03_PORT_SLEEP_STS_RESERVED [07:03] */
#define Wr_switch_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_03_PORT_SLEEP_STS,0xf8,3,x)
#define Rd_switch_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_03_PORT_SLEEP_STS,0xf8,3)
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_RESERVED_MASK 0xf8
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_RESERVED_BITS 5
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_RESERVED_SHIFT 3

/* switch :: PAGE_03_PORT_SLEEP_STS :: PAGE_03_PORT_SLEEP_STS_PORT7_SLEEP_STS [02:02] */
#define Wr_switch_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_PORT7_SLEEP_STS(x) WriteRegBits(SWITCH_PAGE_03_PORT_SLEEP_STS,0x4,2,x)
#define Rd_switch_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_PORT7_SLEEP_STS(x) ReadRegBits(SWITCH_PAGE_03_PORT_SLEEP_STS,0x4,2)
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_PORT7_SLEEP_STS_MASK 0x04
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_PORT7_SLEEP_STS_ALIGN 0
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_PORT7_SLEEP_STS_BITS 1
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_PORT7_SLEEP_STS_SHIFT 2

/* switch :: PAGE_03_PORT_SLEEP_STS :: PAGE_03_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS [01:01] */
#define Wr_switch_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS(x) WriteRegBits(SWITCH_PAGE_03_PORT_SLEEP_STS,0x2,1,x)
#define Rd_switch_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS(x) ReadRegBits(SWITCH_PAGE_03_PORT_SLEEP_STS,0x2,1)
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_MASK 0x02
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_ALIGN 0
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_BITS 1
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_WAN_PORT_SLEEP_STS_SHIFT 1

/* switch :: PAGE_03_PORT_SLEEP_STS :: PAGE_03_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS [00:00] */
#define Wr_switch_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS(x) WriteRegBits(SWITCH_PAGE_03_PORT_SLEEP_STS,0x1,0,x)
#define Rd_switch_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS(x) ReadRegBits(SWITCH_PAGE_03_PORT_SLEEP_STS,0x1,0)
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_MASK 0x01
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_ALIGN 0
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_BITS 1
#define SWITCH_PAGE_03_PORT_SLEEP_STS_PAGE_03_PORT_SLEEP_STS_IMP_PORT_SLEEP_STS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_INT_TRIGGER
 ***************************************************************************/
/* switch :: PAGE_03_INT_TRIGGER :: PAGE_03_INT_TRIGGER_RESERVED [31:03] */
#define Wr_switch_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_RESERVED(x) WriteRegBits(SWITCH_PAGE_03_INT_TRIGGER,0xfffffff8,3,x)
#define Rd_switch_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_RESERVED(x) ReadRegBits(SWITCH_PAGE_03_INT_TRIGGER,0xfffffff8,3)
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_RESERVED_MASK 0xfffffff8
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_RESERVED_BITS 29
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_RESERVED_SHIFT 3

/* switch :: PAGE_03_INT_TRIGGER :: PAGE_03_INT_TRIGGER_INT_CPU_DOORBELL [02:02] */
#define Wr_switch_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_INT_CPU_DOORBELL(x) WriteRegBits(SWITCH_PAGE_03_INT_TRIGGER,0x4,2,x)
#define Rd_switch_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_INT_CPU_DOORBELL(x) ReadRegBits(SWITCH_PAGE_03_INT_TRIGGER,0x4,2)
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_INT_CPU_DOORBELL_MASK 0x00000004
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_INT_CPU_DOORBELL_ALIGN 0
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_INT_CPU_DOORBELL_BITS 1
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_INT_CPU_DOORBELL_SHIFT 2

/* switch :: PAGE_03_INT_TRIGGER :: PAGE_03_INT_TRIGGER_EXT_CPU_DOORBELL [01:01] */
#define Wr_switch_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_DOORBELL(x) WriteRegBits(SWITCH_PAGE_03_INT_TRIGGER,0x2,1,x)
#define Rd_switch_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_DOORBELL(x) ReadRegBits(SWITCH_PAGE_03_INT_TRIGGER,0x2,1)
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_DOORBELL_MASK 0x00000002
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_DOORBELL_ALIGN 0
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_DOORBELL_BITS 1
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_DOORBELL_SHIFT 1

/* switch :: PAGE_03_INT_TRIGGER :: PAGE_03_INT_TRIGGER_EXT_CPU_INT [00:00] */
#define Wr_switch_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_INT(x) WriteRegBits(SWITCH_PAGE_03_INT_TRIGGER,0x1,0,x)
#define Rd_switch_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_INT(x) ReadRegBits(SWITCH_PAGE_03_INT_TRIGGER,0x1,0)
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_INT_MASK 0x00000001
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_INT_ALIGN 0
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_INT_BITS 1
#define SWITCH_PAGE_03_INT_TRIGGER_PAGE_03_INT_TRIGGER_EXT_CPU_INT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_LINK_STS_INT_EN
 ***************************************************************************/
/* switch :: PAGE_03_LINK_STS_INT_EN :: PAGE_03_LINK_STS_INT_EN_RESERVED [15:09] */
#define Wr_switch_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_LINK_STS_INT_EN,0xfe00,9,x)
#define Rd_switch_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_LINK_STS_INT_EN,0xfe00,9)
#define SWITCH_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_RESERVED_BITS 7
#define SWITCH_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_RESERVED_SHIFT 9

/* switch :: PAGE_03_LINK_STS_INT_EN :: PAGE_03_LINK_STS_INT_EN_LINK_STS_INT_EN [08:00] */
#define Wr_switch_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_LINK_STS_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_LINK_STS_INT_EN,0x1ff,0,x)
#define Rd_switch_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_LINK_STS_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_LINK_STS_INT_EN,0x1ff,0)
#define SWITCH_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_LINK_STS_INT_EN_MASK 0x01ff
#define SWITCH_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_LINK_STS_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_LINK_STS_INT_EN_BITS 9
#define SWITCH_PAGE_03_LINK_STS_INT_EN_PAGE_03_LINK_STS_INT_EN_LINK_STS_INT_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_ENG_DET_INT_EN
 ***************************************************************************/
/* switch :: PAGE_03_ENG_DET_INT_EN :: PAGE_03_ENG_DET_INT_EN_RESERVED_1 [15:09] */
#define Wr_switch_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_03_ENG_DET_INT_EN,0xfe00,9,x)
#define Rd_switch_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_03_ENG_DET_INT_EN,0xfe00,9)
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_1_MASK 0xfe00
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_1_BITS 7
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_1_SHIFT 9

/* switch :: PAGE_03_ENG_DET_INT_EN :: PAGE_03_ENG_DET_INT_EN_RESERVED_0 [08:07] */
#define Wr_switch_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_03_ENG_DET_INT_EN,0x180,7,x)
#define Rd_switch_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_03_ENG_DET_INT_EN,0x180,7)
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_0_MASK 0x0180
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_0_BITS 2
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_RESERVED_0_SHIFT 7

/* switch :: PAGE_03_ENG_DET_INT_EN :: PAGE_03_ENG_DET_INT_EN_ENG_DET_INT_EN [06:00] */
#define Wr_switch_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_ENG_DET_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_ENG_DET_INT_EN,0x7f,0,x)
#define Rd_switch_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_ENG_DET_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_ENG_DET_INT_EN,0x7f,0)
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_ENG_DET_INT_EN_MASK 0x007f
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_ENG_DET_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_ENG_DET_INT_EN_BITS 7
#define SWITCH_PAGE_03_ENG_DET_INT_EN_PAGE_03_ENG_DET_INT_EN_ENG_DET_INT_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_LPI_STS_CHG_INT_EN
 ***************************************************************************/
/* switch :: PAGE_03_LPI_STS_CHG_INT_EN :: PAGE_03_LPI_STS_CHG_INT_EN_RESERVED [15:09] */
#define Wr_switch_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_LPI_STS_CHG_INT_EN,0xfe00,9,x)
#define Rd_switch_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_LPI_STS_CHG_INT_EN,0xfe00,9)
#define SWITCH_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_RESERVED_BITS 7
#define SWITCH_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_RESERVED_SHIFT 9

/* switch :: PAGE_03_LPI_STS_CHG_INT_EN :: PAGE_03_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN [08:00] */
#define Wr_switch_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_LPI_STS_CHG_INT_EN,0x1ff,0,x)
#define Rd_switch_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_LPI_STS_CHG_INT_EN,0x1ff,0)
#define SWITCH_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_MASK 0x01ff
#define SWITCH_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_BITS 9
#define SWITCH_PAGE_03_LPI_STS_CHG_INT_EN_PAGE_03_LPI_STS_CHG_INT_EN_LPI_STS_CHG_INT_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_CPU_RESOURCE_ARBITER
 ***************************************************************************/
/* switch :: PAGE_03_CPU_RESOURCE_ARBITER :: PAGE_03_CPU_RESOURCE_ARBITER_RESERVED [07:02] */
#define Wr_switch_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_RESERVED(x) WriteRegBits(SWITCH_PAGE_03_CPU_RESOURCE_ARBITER,0xfc,2,x)
#define Rd_switch_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_RESERVED(x) ReadRegBits(SWITCH_PAGE_03_CPU_RESOURCE_ARBITER,0xfc,2)
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_RESERVED_MASK 0xfc
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_RESERVED_BITS 6
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_RESERVED_SHIFT 2

/* switch :: PAGE_03_CPU_RESOURCE_ARBITER :: PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_REQ [01:01] */
#define Wr_switch_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_REQ(x) WriteRegBits(SWITCH_PAGE_03_CPU_RESOURCE_ARBITER,0x2,1,x)
#define Rd_switch_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_REQ(x) ReadRegBits(SWITCH_PAGE_03_CPU_RESOURCE_ARBITER,0x2,1)
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_MASK 0x02
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_ALIGN 0
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_BITS 1
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_REQ_SHIFT 1

/* switch :: PAGE_03_CPU_RESOURCE_ARBITER :: PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_GNT [00:00] */
#define Wr_switch_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_GNT(x) WriteRegBits(SWITCH_PAGE_03_CPU_RESOURCE_ARBITER,0x1,0,x)
#define Rd_switch_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_GNT(x) ReadRegBits(SWITCH_PAGE_03_CPU_RESOURCE_ARBITER,0x1,0)
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_MASK 0x01
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_ALIGN 0
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_BITS 1
#define SWITCH_PAGE_03_CPU_RESOURCE_ARBITER_PAGE_03_CPU_RESOURCE_ARBITER_EXT_CPU_GNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_CPU_DATA_SHARE
 ***************************************************************************/
/* switch :: PAGE_03_CPU_DATA_SHARE :: PAGE_03_CPU_DATA_SHARE_CPU_DATA_SHARE [63:00] */
#define Wr_switch_PAGE_03_CPU_DATA_SHARE_PAGE_03_CPU_DATA_SHARE_CPU_DATA_SHARE(x) WriteReg(SWITCH_PAGE_03_CPU_DATA_SHARE,x)
#define Rd_switch_PAGE_03_CPU_DATA_SHARE_PAGE_03_CPU_DATA_SHARE_CPU_DATA_SHARE(x) ReadReg(SWITCH_PAGE_03_CPU_DATA_SHARE)
#define SWITCH_PAGE_03_CPU_DATA_SHARE_PAGE_03_CPU_DATA_SHARE_CPU_DATA_SHARE_MASK 0xffffffffffffffff
#define SWITCH_PAGE_03_CPU_DATA_SHARE_PAGE_03_CPU_DATA_SHARE_CPU_DATA_SHARE_ALIGN 0
#define SWITCH_PAGE_03_CPU_DATA_SHARE_PAGE_03_CPU_DATA_SHARE_CPU_DATA_SHARE_BITS 64
#define SWITCH_PAGE_03_CPU_DATA_SHARE_PAGE_03_CPU_DATA_SHARE_CPU_DATA_SHARE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_CPU_DATA_SHARE_1
 ***************************************************************************/
/* switch :: PAGE_03_CPU_DATA_SHARE_1 :: PAGE_03_CPU_DATA_SHARE_1_CPU_DATA_SHARE [63:00] */
#define Wr_switch_PAGE_03_CPU_DATA_SHARE_1_PAGE_03_CPU_DATA_SHARE_1_CPU_DATA_SHARE(x) WriteReg(SWITCH_PAGE_03_CPU_DATA_SHARE_1,x)
#define Rd_switch_PAGE_03_CPU_DATA_SHARE_1_PAGE_03_CPU_DATA_SHARE_1_CPU_DATA_SHARE(x) ReadReg(SWITCH_PAGE_03_CPU_DATA_SHARE_1)
#define SWITCH_PAGE_03_CPU_DATA_SHARE_1_PAGE_03_CPU_DATA_SHARE_1_CPU_DATA_SHARE_MASK 0xffffffffffffffff
#define SWITCH_PAGE_03_CPU_DATA_SHARE_1_PAGE_03_CPU_DATA_SHARE_1_CPU_DATA_SHARE_ALIGN 0
#define SWITCH_PAGE_03_CPU_DATA_SHARE_1_PAGE_03_CPU_DATA_SHARE_1_CPU_DATA_SHARE_BITS 64
#define SWITCH_PAGE_03_CPU_DATA_SHARE_1_PAGE_03_CPU_DATA_SHARE_1_CPU_DATA_SHARE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_MEM_ECC_ERR_INT_STS
 ***************************************************************************/
/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_RESERVED [15:13] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0xe000,13,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0xe000,13)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_RESERVED_MASK 0xe000
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_RESERVED_BITS 3
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_RESERVED_SHIFT 13

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_ARL_TCAM_ECC_ERR_INT_STS [12:12] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_TCAM_ECC_ERR_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x1000,12,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_TCAM_ECC_ERR_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x1000,12)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_TCAM_ECC_ERR_INT_STS_MASK 0x1000
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_TCAM_ECC_ERR_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_TCAM_ECC_ERR_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_TCAM_ECC_ERR_INT_STS_SHIFT 12

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SEC_ECC_DED_INT_STS [11:11] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SEC_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x800,11,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SEC_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x800,11)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SEC_ECC_DED_INT_STS_MASK 0x0800
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SEC_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SEC_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SEC_ECC_DED_INT_STS_SHIFT 11

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS [10:10] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x400,10,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x400,10)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_MASK 0x0400
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TXQ_ECC_DED_INT_STS_SHIFT 10

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS [09:09] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x200,9,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x200,9)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_MASK 0x0200
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_MIB_ECC_DED_INT_STS_SHIFT 9

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS [08:08] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x100,8,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x100,8)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_MASK 0x0100
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_EVT_ECC_DED_INT_STS_SHIFT 8

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS [07:07] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x80,7,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x80,7)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_MASK 0x0080
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_STS_ECC_DED_INT_STS_SHIFT 7

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS [06:06] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x40,6,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x40,6)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_MASK 0x0040
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ACTRAT_ECC_DED_INT_STS_SHIFT 6

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS [05:05] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x20,5,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x20,5)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_MASK 0x0020
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_TCS_ECC_DED_INT_STS_SHIFT 5

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS [04:04] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x10,4,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x10,4)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_MASK 0x0010
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_FM_ECC_DED_INT_STS_SHIFT 4

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS [03:03] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x8,3,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x8,3)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_MASK 0x0008
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_BT_ECC_DED_INT_STS_SHIFT 3

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS [02:02] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x4,2,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x4,2)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_MASK 0x0004
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_VL_ECC_DED_INT_STS_SHIFT 2

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS [01:01] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x2,1,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x2,1)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_MASK 0x0002
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_SCON_ECC_DED_INT_STS_SHIFT 1

/* switch :: PAGE_03_MEM_ECC_ERR_INT_STS :: PAGE_03_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS [00:00] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x1,0,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS,0x1,0)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_MASK 0x0001
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_STS_PAGE_03_MEM_ECC_ERR_INT_STS_ARL_ATMU_ECC_DED_INT_STS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_MEM_ECC_ERR_INT_EN
 ***************************************************************************/
/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_RESERVED [15:13] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0xe000,13,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0xe000,13)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_RESERVED_MASK 0xe000
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_RESERVED_BITS 3
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_RESERVED_SHIFT 13

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_ARL_TCAM_ECC_ERR_INT_EN [12:12] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_TCAM_ECC_ERR_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x1000,12,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_TCAM_ECC_ERR_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x1000,12)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_TCAM_ECC_ERR_INT_EN_MASK 0x1000
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_TCAM_ECC_ERR_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_TCAM_ECC_ERR_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_TCAM_ECC_ERR_INT_EN_SHIFT 12

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SEC_ECC_DED_INT_EN [11:11] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SEC_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x800,11,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SEC_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x800,11)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SEC_ECC_DED_INT_EN_MASK 0x0800
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SEC_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SEC_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SEC_ECC_DED_INT_EN_SHIFT 11

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN [10:10] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x400,10,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x400,10)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_MASK 0x0400
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TXQ_ECC_DED_INT_EN_SHIFT 10

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN [09:09] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x200,9,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x200,9)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_MASK 0x0200
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_MIB_ECC_DED_INT_EN_SHIFT 9

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN [08:08] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x100,8,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x100,8)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_MASK 0x0100
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_EVT_ECC_DED_INT_EN_SHIFT 8

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN [07:07] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x80,7,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x80,7)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_MASK 0x0080
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_STS_ECC_DED_INT_EN_SHIFT 7

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN [06:06] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x40,6,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x40,6)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_MASK 0x0040
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ACTRAT_ECC_DED_INT_EN_SHIFT 6

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN [05:05] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x20,5,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x20,5)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_MASK 0x0020
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_TCS_ECC_DED_INT_EN_SHIFT 5

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN [04:04] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x10,4,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x10,4)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_MASK 0x0010
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_FM_ECC_DED_INT_EN_SHIFT 4

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN [03:03] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x8,3,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x8,3)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_MASK 0x0008
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_BT_ECC_DED_INT_EN_SHIFT 3

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN [02:02] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x4,2,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x4,2)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_MASK 0x0004
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_VL_ECC_DED_INT_EN_SHIFT 2

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN [01:01] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x2,1,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x2,1)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_MASK 0x0002
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_SCON_ECC_DED_INT_EN_SHIFT 1

/* switch :: PAGE_03_MEM_ECC_ERR_INT_EN :: PAGE_03_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN [00:00] */
#define Wr_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN(x) WriteRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x1,0,x)
#define Rd_switch_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN(x) ReadRegBits16(SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN,0x1,0)
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_MASK 0x0001
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_ALIGN 0
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_BITS 1
#define SWITCH_PAGE_03_MEM_ECC_ERR_INT_EN_PAGE_03_MEM_ECC_ERR_INT_EN_ARL_ATMU_ECC_DED_INT_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_PORT_EVT_ECC_ERR_STS
 ***************************************************************************/
/* switch :: PAGE_03_PORT_EVT_ECC_ERR_STS :: PAGE_03_PORT_EVT_ECC_ERR_STS_RESERVED [15:09] */
#define Wr_switch_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS,0xfe00,9,x)
#define Rd_switch_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS,0xfe00,9)
#define SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_RESERVED_BITS 7
#define SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_RESERVED_SHIFT 9

/* switch :: PAGE_03_PORT_EVT_ECC_ERR_STS :: PAGE_03_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS [08:00] */
#define Wr_switch_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS(x) WriteRegBits16(SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS,0x1ff,0,x)
#define Rd_switch_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS(x) ReadRegBits16(SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS,0x1ff,0)
#define SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_MASK 0x01ff
#define SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_ALIGN 0
#define SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_BITS 9
#define SWITCH_PAGE_03_PORT_EVT_ECC_ERR_STS_PAGE_03_PORT_EVT_ECC_ERR_STS_EVT_ECC_ERR_STS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_PORT_MIB_ECC_ERR_STS
 ***************************************************************************/
/* switch :: PAGE_03_PORT_MIB_ECC_ERR_STS :: PAGE_03_PORT_MIB_ECC_ERR_STS_RESERVED [15:10] */
#define Wr_switch_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS,0xfc00,10,x)
#define Rd_switch_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS,0xfc00,10)
#define SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_RESERVED_MASK 0xfc00
#define SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_RESERVED_BITS 6
#define SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_RESERVED_SHIFT 10

/* switch :: PAGE_03_PORT_MIB_ECC_ERR_STS :: PAGE_03_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS [09:00] */
#define Wr_switch_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS(x) WriteRegBits16(SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS,0x3ff,0,x)
#define Rd_switch_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS(x) ReadRegBits16(SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS,0x3ff,0)
#define SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_MASK 0x03ff
#define SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_ALIGN 0
#define SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_BITS 10
#define SWITCH_PAGE_03_PORT_MIB_ECC_ERR_STS_PAGE_03_PORT_MIB_ECC_ERR_STS_MIB_ECC_ERR_STS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_PORT_TXQ_ECC_ERR_STS
 ***************************************************************************/
/* switch :: PAGE_03_PORT_TXQ_ECC_ERR_STS :: PAGE_03_PORT_TXQ_ECC_ERR_STS_RESERVED [15:09] */
#define Wr_switch_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS,0xfe00,9,x)
#define Rd_switch_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS,0xfe00,9)
#define SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_RESERVED_BITS 7
#define SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_RESERVED_SHIFT 9

/* switch :: PAGE_03_PORT_TXQ_ECC_ERR_STS :: PAGE_03_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS [08:00] */
#define Wr_switch_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS(x) WriteRegBits16(SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS,0x1ff,0,x)
#define Rd_switch_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS(x) ReadRegBits16(SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS,0x1ff,0)
#define SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_MASK 0x01ff
#define SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_ALIGN 0
#define SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_BITS 9
#define SWITCH_PAGE_03_PORT_TXQ_ECC_ERR_STS_PAGE_03_PORT_TXQ_ECC_ERR_STS_TXQ_ECC_ERR_STS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_PROBE_BUS_CTL
 ***************************************************************************/
/* switch :: PAGE_03_PROBE_BUS_CTL :: PAGE_03_PROBE_BUS_CTL_PROBE_DEBUG_CTL [31:24] */
#define Wr_switch_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_DEBUG_CTL(x) WriteRegBits(SWITCH_PAGE_03_PROBE_BUS_CTL,0xff000000,24,x)
#define Rd_switch_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_DEBUG_CTL(x) ReadRegBits(SWITCH_PAGE_03_PROBE_BUS_CTL,0xff000000,24)
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_DEBUG_CTL_MASK 0xff000000
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_DEBUG_CTL_ALIGN 0
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_DEBUG_CTL_BITS 8
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_DEBUG_CTL_SHIFT 24

/* switch :: PAGE_03_PROBE_BUS_CTL :: PAGE_03_PROBE_BUS_CTL_PROBE_CLK_SEL [23:16] */
#define Wr_switch_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_CLK_SEL(x) WriteRegBits(SWITCH_PAGE_03_PROBE_BUS_CTL,0xff0000,16,x)
#define Rd_switch_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_CLK_SEL(x) ReadRegBits(SWITCH_PAGE_03_PROBE_BUS_CTL,0xff0000,16)
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_CLK_SEL_MASK 0x00ff0000
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_CLK_SEL_ALIGN 0
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_CLK_SEL_BITS 8
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PROBE_CLK_SEL_SHIFT 16

/* switch :: PAGE_03_PROBE_BUS_CTL :: PAGE_03_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL [15:08] */
#define Wr_switch_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL(x) WriteRegBits(SWITCH_PAGE_03_PROBE_BUS_CTL,0xff00,8,x)
#define Rd_switch_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL(x) ReadRegBits(SWITCH_PAGE_03_PROBE_BUS_CTL,0xff00,8)
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_MASK 0x0000ff00
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_ALIGN 0
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_BITS 8
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_DEBUG_SEL_SHIFT 8

/* switch :: PAGE_03_PROBE_BUS_CTL :: PAGE_03_PROBE_BUS_CTL_PER_PORT_PROBE_SEL [07:00] */
#define Wr_switch_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_PROBE_SEL(x) WriteRegBits(SWITCH_PAGE_03_PROBE_BUS_CTL,0xff,0,x)
#define Rd_switch_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_PROBE_SEL(x) ReadRegBits(SWITCH_PAGE_03_PROBE_BUS_CTL,0xff,0)
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_MASK 0x000000ff
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_ALIGN 0
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_BITS 8
#define SWITCH_PAGE_03_PROBE_BUS_CTL_PAGE_03_PROBE_BUS_CTL_PER_PORT_PROBE_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_MDC_EXTEND_CTRL
 ***************************************************************************/
/* switch :: PAGE_03_MDC_EXTEND_CTRL :: PAGE_03_MDC_EXTEND_CTRL_RESERVED [07:01] */
#define Wr_switch_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_03_MDC_EXTEND_CTRL,0xfe,1,x)
#define Rd_switch_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_03_MDC_EXTEND_CTRL,0xfe,1)
#define SWITCH_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_RESERVED_MASK 0xfe
#define SWITCH_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_RESERVED_BITS 7
#define SWITCH_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_RESERVED_SHIFT 1

/* switch :: PAGE_03_MDC_EXTEND_CTRL :: PAGE_03_MDC_EXTEND_CTRL_EXTENDED_MDC_EN [00:00] */
#define Wr_switch_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_EXTENDED_MDC_EN(x) WriteRegBits(SWITCH_PAGE_03_MDC_EXTEND_CTRL,0x1,0,x)
#define Rd_switch_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_EXTENDED_MDC_EN(x) ReadRegBits(SWITCH_PAGE_03_MDC_EXTEND_CTRL,0x1,0)
#define SWITCH_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_MASK 0x01
#define SWITCH_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_ALIGN 0
#define SWITCH_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_BITS 1
#define SWITCH_PAGE_03_MDC_EXTEND_CTRL_PAGE_03_MDC_EXTEND_CTRL_EXTENDED_MDC_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_PPPOE_SESSION_PARSE_EN
 ***************************************************************************/
/* switch :: PAGE_03_PPPOE_SESSION_PARSE_EN :: PAGE_03_PPPOE_SESSION_PARSE_EN_RESERVED [31:25] */
#define Wr_switch_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_RESERVED(x) WriteRegBits(SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN,0xfe000000,25,x)
#define Rd_switch_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_RESERVED(x) ReadRegBits(SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN,0xfe000000,25)
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_RESERVED_MASK 0xfe000000
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_RESERVED_ALIGN 0
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_RESERVED_BITS 7
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_RESERVED_SHIFT 25

/* switch :: PAGE_03_PPPOE_SESSION_PARSE_EN :: PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN [24:16] */
#define Wr_switch_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN(x) WriteRegBits(SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN,0x1ff0000,16,x)
#define Rd_switch_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN(x) ReadRegBits(SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN,0x1ff0000,16)
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_MASK 0x01ff0000
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_ALIGN 0
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_BITS 9
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_PARSE_EN_SHIFT 16

/* switch :: PAGE_03_PPPOE_SESSION_PARSE_EN :: PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE [15:00] */
#define Wr_switch_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE(x) WriteRegBits(SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN,0xffff,0,x)
#define Rd_switch_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE(x) ReadRegBits(SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN,0xffff,0)
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_MASK 0x0000ffff
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_ALIGN 0
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_BITS 16
#define SWITCH_PAGE_03_PPPOE_SESSION_PARSE_EN_PAGE_03_PPPOE_SESSION_PARSE_EN_PPPOE_SESSION_ETYPE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_CTLREG_1_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_03_CTLREG_1_REG_SPARE0 :: PAGE_03_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_03_CTLREG_1_REG_SPARE0_PAGE_03_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0(x) WriteReg(SWITCH_PAGE_03_CTLREG_1_REG_SPARE0,x)
#define Rd_switch_PAGE_03_CTLREG_1_REG_SPARE0_PAGE_03_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0(x) ReadReg(SWITCH_PAGE_03_CTLREG_1_REG_SPARE0)
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE0_PAGE_03_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE0_PAGE_03_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE0_PAGE_03_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_BITS 32
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE0_PAGE_03_CTLREG_1_REG_SPARE0_CTLREG_1_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_03_CTLREG_1_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_03_CTLREG_1_REG_SPARE1 :: PAGE_03_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_03_CTLREG_1_REG_SPARE1_PAGE_03_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1(x) WriteReg(SWITCH_PAGE_03_CTLREG_1_REG_SPARE1,x)
#define Rd_switch_PAGE_03_CTLREG_1_REG_SPARE1_PAGE_03_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1(x) ReadReg(SWITCH_PAGE_03_CTLREG_1_REG_SPARE1)
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE1_PAGE_03_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE1_PAGE_03_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE1_PAGE_03_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_BITS 32
#define SWITCH_PAGE_03_CTLREG_1_REG_SPARE1_PAGE_03_CTLREG_1_REG_SPARE1_CTLREG_1_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_GARLCFG
 ***************************************************************************/
/* switch :: PAGE_04_GARLCFG :: PAGE_04_GARLCFG_RESERVED_1 [07:03] */
#define Wr_switch_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_04_GARLCFG,0xf8,3,x)
#define Rd_switch_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_04_GARLCFG,0xf8,3)
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_1_MASK     0xf8
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_1_ALIGN    0
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_1_BITS     5
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_1_SHIFT    3

/* switch :: PAGE_04_GARLCFG :: PAGE_04_GARLCFG_AGE_ACC [02:02] */
#define Wr_switch_PAGE_04_GARLCFG_PAGE_04_GARLCFG_AGE_ACC(x) WriteRegBits(SWITCH_PAGE_04_GARLCFG,0x4,2,x)
#define Rd_switch_PAGE_04_GARLCFG_PAGE_04_GARLCFG_AGE_ACC(x) ReadRegBits(SWITCH_PAGE_04_GARLCFG,0x4,2)
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_AGE_ACC_MASK        0x04
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_AGE_ACC_ALIGN       0
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_AGE_ACC_BITS        1
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_AGE_ACC_SHIFT       2

/* switch :: PAGE_04_GARLCFG :: PAGE_04_GARLCFG_RESERVED_0 [01:01] */
#define Wr_switch_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_04_GARLCFG,0x2,1,x)
#define Rd_switch_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_04_GARLCFG,0x2,1)
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_0_MASK     0x02
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_0_ALIGN    0
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_0_BITS     1
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_RESERVED_0_SHIFT    1

/* switch :: PAGE_04_GARLCFG :: PAGE_04_GARLCFG_HASH_DISABLE [00:00] */
#define Wr_switch_PAGE_04_GARLCFG_PAGE_04_GARLCFG_HASH_DISABLE(x) WriteRegBits(SWITCH_PAGE_04_GARLCFG,0x1,0,x)
#define Rd_switch_PAGE_04_GARLCFG_PAGE_04_GARLCFG_HASH_DISABLE(x) ReadRegBits(SWITCH_PAGE_04_GARLCFG,0x1,0)
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_HASH_DISABLE_MASK   0x01
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_HASH_DISABLE_ALIGN  0
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_HASH_DISABLE_BITS   1
#define SWITCH_PAGE_04_GARLCFG_PAGE_04_GARLCFG_HASH_DISABLE_SHIFT  0


/****************************************************************************
 * switch :: PAGE_04_BPDU_MCADDR
 ***************************************************************************/
/* switch :: PAGE_04_BPDU_MCADDR :: reserved0 [63:48] */
#define SWITCH_PAGE_04_BPDU_MCADDR_RESERVED0_MASK                  0xffff000000000000
#define SWITCH_PAGE_04_BPDU_MCADDR_RESERVED0_ALIGN                 0
#define SWITCH_PAGE_04_BPDU_MCADDR_RESERVED0_BITS                  16
#define SWITCH_PAGE_04_BPDU_MCADDR_RESERVED0_SHIFT                 48

/* switch :: PAGE_04_BPDU_MCADDR :: PAGE_04_BPDU_MCADDR_BPDU_MC_ADDR [47:00] */
#define Wr_switch_PAGE_04_BPDU_MCADDR_PAGE_04_BPDU_MCADDR_BPDU_MC_ADDR(x) WriteRegBits(SWITCH_PAGE_04_BPDU_MCADDR,0xffffffffffff,0,x)
#define Rd_switch_PAGE_04_BPDU_MCADDR_PAGE_04_BPDU_MCADDR_BPDU_MC_ADDR(x) ReadRegBits(SWITCH_PAGE_04_BPDU_MCADDR,0xffffffffffff,0)
#define SWITCH_PAGE_04_BPDU_MCADDR_PAGE_04_BPDU_MCADDR_BPDU_MC_ADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_04_BPDU_MCADDR_PAGE_04_BPDU_MCADDR_BPDU_MC_ADDR_ALIGN 0
#define SWITCH_PAGE_04_BPDU_MCADDR_PAGE_04_BPDU_MCADDR_BPDU_MC_ADDR_BITS 48
#define SWITCH_PAGE_04_BPDU_MCADDR_PAGE_04_BPDU_MCADDR_BPDU_MC_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MULTI_PORT_CTL
 ***************************************************************************/
/* switch :: PAGE_04_MULTI_PORT_CTL :: PAGE_04_MULTI_PORT_CTL_MPORT0_TS_EN [15:15] */
#define Wr_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT0_TS_EN(x) WriteRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x8000,15,x)
#define Rd_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT0_TS_EN(x) ReadRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x8000,15)
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT0_TS_EN_MASK 0x8000
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT0_TS_EN_ALIGN 0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT0_TS_EN_BITS 1
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT0_TS_EN_SHIFT 15

/* switch :: PAGE_04_MULTI_PORT_CTL :: PAGE_04_MULTI_PORT_CTL_MPORT_DA_HIT_EN [14:14] */
#define Wr_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_DA_HIT_EN(x) WriteRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x4000,14,x)
#define Rd_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_DA_HIT_EN(x) ReadRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x4000,14)
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_DA_HIT_EN_MASK 0x4000
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_DA_HIT_EN_ALIGN 0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_DA_HIT_EN_BITS 1
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_DA_HIT_EN_SHIFT 14

/* switch :: PAGE_04_MULTI_PORT_CTL :: PAGE_04_MULTI_PORT_CTL_RESERVED [13:12] */
#define Wr_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x3000,12,x)
#define Rd_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x3000,12)
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_RESERVED_MASK 0x3000
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_RESERVED_BITS 2
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_RESERVED_SHIFT 12

/* switch :: PAGE_04_MULTI_PORT_CTL :: PAGE_04_MULTI_PORT_CTL_MPORT_CTRL5 [11:10] */
#define Wr_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL5(x) WriteRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0xc00,10,x)
#define Rd_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL5(x) ReadRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0xc00,10)
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL5_MASK 0x0c00
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL5_ALIGN 0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL5_BITS 2
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL5_SHIFT 10

/* switch :: PAGE_04_MULTI_PORT_CTL :: PAGE_04_MULTI_PORT_CTL_MPORT_CTRL4 [09:08] */
#define Wr_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL4(x) WriteRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x300,8,x)
#define Rd_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL4(x) ReadRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x300,8)
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL4_MASK 0x0300
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL4_ALIGN 0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL4_BITS 2
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL4_SHIFT 8

/* switch :: PAGE_04_MULTI_PORT_CTL :: PAGE_04_MULTI_PORT_CTL_MPORT_CTRL3 [07:06] */
#define Wr_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL3(x) WriteRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0xc0,6,x)
#define Rd_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL3(x) ReadRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0xc0,6)
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL3_MASK 0x00c0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL3_ALIGN 0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL3_BITS 2
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL3_SHIFT 6

/* switch :: PAGE_04_MULTI_PORT_CTL :: PAGE_04_MULTI_PORT_CTL_MPORT_CTRL2 [05:04] */
#define Wr_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL2(x) WriteRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x30,4,x)
#define Rd_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL2(x) ReadRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x30,4)
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL2_MASK 0x0030
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL2_ALIGN 0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL2_BITS 2
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL2_SHIFT 4

/* switch :: PAGE_04_MULTI_PORT_CTL :: PAGE_04_MULTI_PORT_CTL_MPORT_CTRL1 [03:02] */
#define Wr_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL1(x) WriteRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0xc,2,x)
#define Rd_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL1(x) ReadRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0xc,2)
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL1_MASK 0x000c
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL1_ALIGN 0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL1_BITS 2
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL1_SHIFT 2

/* switch :: PAGE_04_MULTI_PORT_CTL :: PAGE_04_MULTI_PORT_CTL_MPORT_CTRL0 [01:00] */
#define Wr_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL0(x) WriteRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x3,0,x)
#define Rd_switch_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL0(x) ReadRegBits16(SWITCH_PAGE_04_MULTI_PORT_CTL,0x3,0)
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL0_MASK 0x0003
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL0_ALIGN 0
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL0_BITS 2
#define SWITCH_PAGE_04_MULTI_PORT_CTL_PAGE_04_MULTI_PORT_CTL_MPORT_CTRL0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MULTIPORT_ADDR0
 ***************************************************************************/
/* switch :: PAGE_04_MULTIPORT_ADDR0 :: PAGE_04_MULTIPORT_ADDR0_MPORT_E_TYPE [63:48] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_E_TYPE(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR0,0xffff000000000000,48,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_E_TYPE(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR0,0xffff000000000000,48)
#define SWITCH_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_E_TYPE_MASK 0xffff000000000000
#define SWITCH_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_E_TYPE_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_E_TYPE_BITS 16
#define SWITCH_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_E_TYPE_SHIFT 48

/* switch :: PAGE_04_MULTIPORT_ADDR0 :: PAGE_04_MULTIPORT_ADDR0_MPORT_ADDR [47:00] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_ADDR(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR0,0xffffffffffff,0,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_ADDR(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR0,0xffffffffffff,0)
#define SWITCH_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_ADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_ADDR_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_ADDR_BITS 48
#define SWITCH_PAGE_04_MULTIPORT_ADDR0_PAGE_04_MULTIPORT_ADDR0_MPORT_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MPORTVEC0
 ***************************************************************************/
/* switch :: PAGE_04_MPORTVEC0 :: PAGE_04_MPORTVEC0_RESERVED [31:09] */
#define Wr_switch_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_RESERVED(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC0,0xfffffe00,9,x)
#define Rd_switch_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_RESERVED(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC0,0xfffffe00,9)
#define SWITCH_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_RESERVED_MASK   0xfffffe00
#define SWITCH_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_RESERVED_ALIGN  0
#define SWITCH_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_RESERVED_BITS   23
#define SWITCH_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_RESERVED_SHIFT  9

/* switch :: PAGE_04_MPORTVEC0 :: PAGE_04_MPORTVEC0_PORT_VCTR [08:00] */
#define Wr_switch_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_PORT_VCTR(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC0,0x1ff,0,x)
#define Rd_switch_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_PORT_VCTR(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC0,0x1ff,0)
#define SWITCH_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_PORT_VCTR_MASK  0x000001ff
#define SWITCH_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_PORT_VCTR_ALIGN 0
#define SWITCH_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_PORT_VCTR_BITS  9
#define SWITCH_PAGE_04_MPORTVEC0_PAGE_04_MPORTVEC0_PORT_VCTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MULTIPORT_ADDR1
 ***************************************************************************/
/* switch :: PAGE_04_MULTIPORT_ADDR1 :: PAGE_04_MULTIPORT_ADDR1_MPORT_E_TYPE [63:48] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_E_TYPE(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR1,0xffff000000000000,48,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_E_TYPE(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR1,0xffff000000000000,48)
#define SWITCH_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_E_TYPE_MASK 0xffff000000000000
#define SWITCH_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_E_TYPE_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_E_TYPE_BITS 16
#define SWITCH_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_E_TYPE_SHIFT 48

/* switch :: PAGE_04_MULTIPORT_ADDR1 :: PAGE_04_MULTIPORT_ADDR1_MPORT_ADDR [47:00] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_ADDR(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR1,0xffffffffffff,0,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_ADDR(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR1,0xffffffffffff,0)
#define SWITCH_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_ADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_ADDR_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_ADDR_BITS 48
#define SWITCH_PAGE_04_MULTIPORT_ADDR1_PAGE_04_MULTIPORT_ADDR1_MPORT_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MPORTVEC1
 ***************************************************************************/
/* switch :: PAGE_04_MPORTVEC1 :: PAGE_04_MPORTVEC1_RESERVED [31:09] */
#define Wr_switch_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_RESERVED(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC1,0xfffffe00,9,x)
#define Rd_switch_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_RESERVED(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC1,0xfffffe00,9)
#define SWITCH_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_RESERVED_MASK   0xfffffe00
#define SWITCH_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_RESERVED_ALIGN  0
#define SWITCH_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_RESERVED_BITS   23
#define SWITCH_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_RESERVED_SHIFT  9

/* switch :: PAGE_04_MPORTVEC1 :: PAGE_04_MPORTVEC1_PORT_VCTR [08:00] */
#define Wr_switch_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_PORT_VCTR(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC1,0x1ff,0,x)
#define Rd_switch_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_PORT_VCTR(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC1,0x1ff,0)
#define SWITCH_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_PORT_VCTR_MASK  0x000001ff
#define SWITCH_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_PORT_VCTR_ALIGN 0
#define SWITCH_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_PORT_VCTR_BITS  9
#define SWITCH_PAGE_04_MPORTVEC1_PAGE_04_MPORTVEC1_PORT_VCTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MULTIPORT_ADDR2
 ***************************************************************************/
/* switch :: PAGE_04_MULTIPORT_ADDR2 :: PAGE_04_MULTIPORT_ADDR2_MPORT_E_TYPE [63:48] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_E_TYPE(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR2,0xffff000000000000,48,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_E_TYPE(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR2,0xffff000000000000,48)
#define SWITCH_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_E_TYPE_MASK 0xffff000000000000
#define SWITCH_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_E_TYPE_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_E_TYPE_BITS 16
#define SWITCH_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_E_TYPE_SHIFT 48

/* switch :: PAGE_04_MULTIPORT_ADDR2 :: PAGE_04_MULTIPORT_ADDR2_MPORT_ADDR [47:00] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_ADDR(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR2,0xffffffffffff,0,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_ADDR(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR2,0xffffffffffff,0)
#define SWITCH_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_ADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_ADDR_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_ADDR_BITS 48
#define SWITCH_PAGE_04_MULTIPORT_ADDR2_PAGE_04_MULTIPORT_ADDR2_MPORT_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MPORTVEC2
 ***************************************************************************/
/* switch :: PAGE_04_MPORTVEC2 :: PAGE_04_MPORTVEC2_RESERVED [31:09] */
#define Wr_switch_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_RESERVED(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC2,0xfffffe00,9,x)
#define Rd_switch_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_RESERVED(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC2,0xfffffe00,9)
#define SWITCH_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_RESERVED_MASK   0xfffffe00
#define SWITCH_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_RESERVED_ALIGN  0
#define SWITCH_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_RESERVED_BITS   23
#define SWITCH_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_RESERVED_SHIFT  9

/* switch :: PAGE_04_MPORTVEC2 :: PAGE_04_MPORTVEC2_PORT_VCTR [08:00] */
#define Wr_switch_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_PORT_VCTR(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC2,0x1ff,0,x)
#define Rd_switch_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_PORT_VCTR(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC2,0x1ff,0)
#define SWITCH_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_PORT_VCTR_MASK  0x000001ff
#define SWITCH_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_PORT_VCTR_ALIGN 0
#define SWITCH_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_PORT_VCTR_BITS  9
#define SWITCH_PAGE_04_MPORTVEC2_PAGE_04_MPORTVEC2_PORT_VCTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MULTIPORT_ADDR3
 ***************************************************************************/
/* switch :: PAGE_04_MULTIPORT_ADDR3 :: PAGE_04_MULTIPORT_ADDR3_MPORT_E_TYPE [63:48] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_E_TYPE(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR3,0xffff000000000000,48,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_E_TYPE(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR3,0xffff000000000000,48)
#define SWITCH_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_E_TYPE_MASK 0xffff000000000000
#define SWITCH_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_E_TYPE_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_E_TYPE_BITS 16
#define SWITCH_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_E_TYPE_SHIFT 48

/* switch :: PAGE_04_MULTIPORT_ADDR3 :: PAGE_04_MULTIPORT_ADDR3_MPORT_ADDR [47:00] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_ADDR(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR3,0xffffffffffff,0,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_ADDR(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR3,0xffffffffffff,0)
#define SWITCH_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_ADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_ADDR_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_ADDR_BITS 48
#define SWITCH_PAGE_04_MULTIPORT_ADDR3_PAGE_04_MULTIPORT_ADDR3_MPORT_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MPORTVEC3
 ***************************************************************************/
/* switch :: PAGE_04_MPORTVEC3 :: PAGE_04_MPORTVEC3_RESERVED [31:09] */
#define Wr_switch_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_RESERVED(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC3,0xfffffe00,9,x)
#define Rd_switch_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_RESERVED(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC3,0xfffffe00,9)
#define SWITCH_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_RESERVED_MASK   0xfffffe00
#define SWITCH_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_RESERVED_ALIGN  0
#define SWITCH_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_RESERVED_BITS   23
#define SWITCH_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_RESERVED_SHIFT  9

/* switch :: PAGE_04_MPORTVEC3 :: PAGE_04_MPORTVEC3_PORT_VCTR [08:00] */
#define Wr_switch_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_PORT_VCTR(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC3,0x1ff,0,x)
#define Rd_switch_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_PORT_VCTR(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC3,0x1ff,0)
#define SWITCH_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_PORT_VCTR_MASK  0x000001ff
#define SWITCH_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_PORT_VCTR_ALIGN 0
#define SWITCH_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_PORT_VCTR_BITS  9
#define SWITCH_PAGE_04_MPORTVEC3_PAGE_04_MPORTVEC3_PORT_VCTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MULTIPORT_ADDR4
 ***************************************************************************/
/* switch :: PAGE_04_MULTIPORT_ADDR4 :: PAGE_04_MULTIPORT_ADDR4_MPORT_E_TYPE [63:48] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_E_TYPE(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR4,0xffff000000000000,48,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_E_TYPE(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR4,0xffff000000000000,48)
#define SWITCH_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_E_TYPE_MASK 0xffff000000000000
#define SWITCH_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_E_TYPE_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_E_TYPE_BITS 16
#define SWITCH_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_E_TYPE_SHIFT 48

/* switch :: PAGE_04_MULTIPORT_ADDR4 :: PAGE_04_MULTIPORT_ADDR4_MPORT_ADDR [47:00] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_ADDR(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR4,0xffffffffffff,0,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_ADDR(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR4,0xffffffffffff,0)
#define SWITCH_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_ADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_ADDR_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_ADDR_BITS 48
#define SWITCH_PAGE_04_MULTIPORT_ADDR4_PAGE_04_MULTIPORT_ADDR4_MPORT_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MPORTVEC4
 ***************************************************************************/
/* switch :: PAGE_04_MPORTVEC4 :: PAGE_04_MPORTVEC4_RESERVED [31:09] */
#define Wr_switch_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_RESERVED(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC4,0xfffffe00,9,x)
#define Rd_switch_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_RESERVED(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC4,0xfffffe00,9)
#define SWITCH_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_RESERVED_MASK   0xfffffe00
#define SWITCH_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_RESERVED_ALIGN  0
#define SWITCH_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_RESERVED_BITS   23
#define SWITCH_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_RESERVED_SHIFT  9

/* switch :: PAGE_04_MPORTVEC4 :: PAGE_04_MPORTVEC4_PORT_VCTR [08:00] */
#define Wr_switch_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_PORT_VCTR(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC4,0x1ff,0,x)
#define Rd_switch_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_PORT_VCTR(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC4,0x1ff,0)
#define SWITCH_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_PORT_VCTR_MASK  0x000001ff
#define SWITCH_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_PORT_VCTR_ALIGN 0
#define SWITCH_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_PORT_VCTR_BITS  9
#define SWITCH_PAGE_04_MPORTVEC4_PAGE_04_MPORTVEC4_PORT_VCTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MULTIPORT_ADDR5
 ***************************************************************************/
/* switch :: PAGE_04_MULTIPORT_ADDR5 :: PAGE_04_MULTIPORT_ADDR5_MPORT_E_TYPE [63:48] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_E_TYPE(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR5,0xffff000000000000,48,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_E_TYPE(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR5,0xffff000000000000,48)
#define SWITCH_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_E_TYPE_MASK 0xffff000000000000
#define SWITCH_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_E_TYPE_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_E_TYPE_BITS 16
#define SWITCH_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_E_TYPE_SHIFT 48

/* switch :: PAGE_04_MULTIPORT_ADDR5 :: PAGE_04_MULTIPORT_ADDR5_MPORT_ADDR [47:00] */
#define Wr_switch_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_ADDR(x) WriteRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR5,0xffffffffffff,0,x)
#define Rd_switch_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_ADDR(x) ReadRegBits(SWITCH_PAGE_04_MULTIPORT_ADDR5,0xffffffffffff,0)
#define SWITCH_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_ADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_ADDR_ALIGN 0
#define SWITCH_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_ADDR_BITS 48
#define SWITCH_PAGE_04_MULTIPORT_ADDR5_PAGE_04_MULTIPORT_ADDR5_MPORT_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_MPORTVEC5
 ***************************************************************************/
/* switch :: PAGE_04_MPORTVEC5 :: PAGE_04_MPORTVEC5_RESERVED [31:09] */
#define Wr_switch_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_RESERVED(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC5,0xfffffe00,9,x)
#define Rd_switch_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_RESERVED(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC5,0xfffffe00,9)
#define SWITCH_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_RESERVED_MASK   0xfffffe00
#define SWITCH_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_RESERVED_ALIGN  0
#define SWITCH_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_RESERVED_BITS   23
#define SWITCH_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_RESERVED_SHIFT  9

/* switch :: PAGE_04_MPORTVEC5 :: PAGE_04_MPORTVEC5_PORT_VCTR [08:00] */
#define Wr_switch_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_PORT_VCTR(x) WriteRegBits(SWITCH_PAGE_04_MPORTVEC5,0x1ff,0,x)
#define Rd_switch_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_PORT_VCTR(x) ReadRegBits(SWITCH_PAGE_04_MPORTVEC5,0x1ff,0)
#define SWITCH_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_PORT_VCTR_MASK  0x000001ff
#define SWITCH_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_PORT_VCTR_ALIGN 0
#define SWITCH_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_PORT_VCTR_BITS  9
#define SWITCH_PAGE_04_MPORTVEC5_PAGE_04_MPORTVEC5_PORT_VCTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_ARL_BIN_FULL_CNTR
 ***************************************************************************/
/* switch :: PAGE_04_ARL_BIN_FULL_CNTR :: PAGE_04_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR [31:00] */
#define Wr_switch_PAGE_04_ARL_BIN_FULL_CNTR_PAGE_04_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR(x) WriteReg(SWITCH_PAGE_04_ARL_BIN_FULL_CNTR,x)
#define Rd_switch_PAGE_04_ARL_BIN_FULL_CNTR_PAGE_04_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR(x) ReadReg(SWITCH_PAGE_04_ARL_BIN_FULL_CNTR)
#define SWITCH_PAGE_04_ARL_BIN_FULL_CNTR_PAGE_04_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_MASK 0xffffffff
#define SWITCH_PAGE_04_ARL_BIN_FULL_CNTR_PAGE_04_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_ALIGN 0
#define SWITCH_PAGE_04_ARL_BIN_FULL_CNTR_PAGE_04_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_BITS 32
#define SWITCH_PAGE_04_ARL_BIN_FULL_CNTR_PAGE_04_ARL_BIN_FULL_CNTR_ARL_BIN_FUL_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_ARL_BIN_FULL_FWD
 ***************************************************************************/
/* switch :: PAGE_04_ARL_BIN_FULL_FWD :: PAGE_04_ARL_BIN_FULL_FWD_Reserved [15:01] */
#define Wr_switch_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_Reserved(x) WriteRegBits16(SWITCH_PAGE_04_ARL_BIN_FULL_FWD,0xfffe,1,x)
#define Rd_switch_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_Reserved(x) ReadRegBits16(SWITCH_PAGE_04_ARL_BIN_FULL_FWD,0xfffe,1)
#define SWITCH_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_RESERVED_MASK 0xfffe
#define SWITCH_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_RESERVED_ALIGN 0
#define SWITCH_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_RESERVED_BITS 15
#define SWITCH_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_RESERVED_SHIFT 1

/* switch :: PAGE_04_ARL_BIN_FULL_FWD :: PAGE_04_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN [00:00] */
#define Wr_switch_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN(x) WriteRegBits16(SWITCH_PAGE_04_ARL_BIN_FULL_FWD,0x1,0,x)
#define Rd_switch_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN(x) ReadRegBits16(SWITCH_PAGE_04_ARL_BIN_FULL_FWD,0x1,0)
#define SWITCH_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_MASK 0x0001
#define SWITCH_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_ALIGN 0
#define SWITCH_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_BITS 1
#define SWITCH_PAGE_04_ARL_BIN_FULL_FWD_PAGE_04_ARL_BIN_FULL_FWD_ARL_BIN_FULL_FWD_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_ARL_SEED
 ***************************************************************************/
/* switch :: PAGE_04_ARL_SEED :: PAGE_04_ARL_SEED_Reserved [63:60] */
#define Wr_switch_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_Reserved(x) WriteRegBits(SWITCH_PAGE_04_ARL_SEED,0xf000000000000000,60,x)
#define Rd_switch_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_Reserved(x) ReadRegBits(SWITCH_PAGE_04_ARL_SEED,0xf000000000000000,60)
#define SWITCH_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_RESERVED_MASK     0xf000000000000000
#define SWITCH_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_RESERVED_ALIGN    0
#define SWITCH_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_RESERVED_BITS     4
#define SWITCH_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_RESERVED_SHIFT    60

/* switch :: PAGE_04_ARL_SEED :: PAGE_04_ARL_SEED_ARL_SEED [59:00] */
#define Wr_switch_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_ARL_SEED(x) WriteRegBits(SWITCH_PAGE_04_ARL_SEED,0x1000000000000000,0,x)
#define Rd_switch_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_ARL_SEED(x) ReadRegBits(SWITCH_PAGE_04_ARL_SEED,0x1000000000000000,0)
#define SWITCH_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_ARL_SEED_MASK     0x1000000000000000
#define SWITCH_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_ARL_SEED_ALIGN    0
#define SWITCH_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_ARL_SEED_BITS     60
#define SWITCH_PAGE_04_ARL_SEED_PAGE_04_ARL_SEED_ARL_SEED_SHIFT    0


/****************************************************************************
 * switch :: PAGE_04_ARLCTL_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_04_ARLCTL_REG_SPARE0 :: PAGE_04_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_04_ARLCTL_REG_SPARE0_PAGE_04_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0(x) WriteReg(SWITCH_PAGE_04_ARLCTL_REG_SPARE0,x)
#define Rd_switch_PAGE_04_ARLCTL_REG_SPARE0_PAGE_04_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0(x) ReadReg(SWITCH_PAGE_04_ARLCTL_REG_SPARE0)
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE0_PAGE_04_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE0_PAGE_04_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE0_PAGE_04_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_BITS 32
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE0_PAGE_04_ARLCTL_REG_SPARE0_ARLCTL_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_ARLCTL_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_04_ARLCTL_REG_SPARE1 :: PAGE_04_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_04_ARLCTL_REG_SPARE1_PAGE_04_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1(x) WriteReg(SWITCH_PAGE_04_ARLCTL_REG_SPARE1,x)
#define Rd_switch_PAGE_04_ARLCTL_REG_SPARE1_PAGE_04_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1(x) ReadReg(SWITCH_PAGE_04_ARLCTL_REG_SPARE1)
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE1_PAGE_04_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE1_PAGE_04_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE1_PAGE_04_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_BITS 32
#define SWITCH_PAGE_04_ARLCTL_REG_SPARE1_PAGE_04_ARLCTL_REG_SPARE1_ARLCTL_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_ARL_TCAM_CTRL
 ***************************************************************************/
/* switch :: PAGE_04_ARL_TCAM_CTRL :: PAGE_04_ARL_TCAM_CTRL_RESERVED [31:03] */
#define Wr_switch_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_04_ARL_TCAM_CTRL,0xfffffff8,3,x)
#define Rd_switch_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_04_ARL_TCAM_CTRL,0xfffffff8,3)
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_RESERVED_MASK 0xfffffff8
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_RESERVED_BITS 29
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_RESERVED_SHIFT 3

/* switch :: PAGE_04_ARL_TCAM_CTRL :: PAGE_04_ARL_TCAM_CTRL_TCAM_ENC_DIS [02:02] */
#define Wr_switch_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_ENC_DIS(x) WriteRegBits(SWITCH_PAGE_04_ARL_TCAM_CTRL,0x4,2,x)
#define Rd_switch_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_ENC_DIS(x) ReadRegBits(SWITCH_PAGE_04_ARL_TCAM_CTRL,0x4,2)
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_ENC_DIS_MASK 0x00000004
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_ENC_DIS_ALIGN 0
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_ENC_DIS_BITS 1
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_ENC_DIS_SHIFT 2

/* switch :: PAGE_04_ARL_TCAM_CTRL :: PAGE_04_ARL_TCAM_CTRL_TCAM_CHK_EN [01:01] */
#define Wr_switch_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_CHK_EN(x) WriteRegBits(SWITCH_PAGE_04_ARL_TCAM_CTRL,0x2,1,x)
#define Rd_switch_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_CHK_EN(x) ReadRegBits(SWITCH_PAGE_04_ARL_TCAM_CTRL,0x2,1)
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_CHK_EN_MASK 0x00000002
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_CHK_EN_ALIGN 0
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_CHK_EN_BITS 1
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_CHK_EN_SHIFT 1

/* switch :: PAGE_04_ARL_TCAM_CTRL :: PAGE_04_ARL_TCAM_CTRL_TCAM_EN [00:00] */
#define Wr_switch_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_EN(x) WriteRegBits(SWITCH_PAGE_04_ARL_TCAM_CTRL,0x1,0,x)
#define Rd_switch_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_EN(x) ReadRegBits(SWITCH_PAGE_04_ARL_TCAM_CTRL,0x1,0)
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_EN_MASK 0x00000001
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_EN_ALIGN 0
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_EN_BITS 1
#define SWITCH_PAGE_04_ARL_TCAM_CTRL_PAGE_04_ARL_TCAM_CTRL_TCAM_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_ARL_TCAM_STS
 ***************************************************************************/
/* switch :: PAGE_04_ARL_TCAM_STS :: PAGE_04_ARL_TCAM_STS_TCAM_ERR_FLAG [31:31] */
#define Wr_switch_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_ERR_FLAG(x) WriteRegBits(SWITCH_PAGE_04_ARL_TCAM_STS,0x80000000,31,x)
#define Rd_switch_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_ERR_FLAG(x) ReadRegBits(SWITCH_PAGE_04_ARL_TCAM_STS,0x80000000,31)
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_ERR_FLAG_MASK 0x80000000
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_ERR_FLAG_ALIGN 0
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_ERR_FLAG_BITS 1
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_ERR_FLAG_SHIFT 31

/* switch :: PAGE_04_ARL_TCAM_STS :: PAGE_04_ARL_TCAM_STS_RESERVED_0 [30:30] */
#define Wr_switch_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_04_ARL_TCAM_STS,0x40000000,30,x)
#define Rd_switch_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_04_ARL_TCAM_STS,0x40000000,30)
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_0_MASK 0x40000000
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_0_BITS 1
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_0_SHIFT 30

/* switch :: PAGE_04_ARL_TCAM_STS :: PAGE_04_ARL_TCAM_STS_TCAM_CHK_ADDR [29:22] */
#define Wr_switch_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_CHK_ADDR(x) WriteRegBits(SWITCH_PAGE_04_ARL_TCAM_STS,0x3fc00000,22,x)
#define Rd_switch_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_CHK_ADDR(x) ReadRegBits(SWITCH_PAGE_04_ARL_TCAM_STS,0x3fc00000,22)
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_CHK_ADDR_MASK 0x3fc00000
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_CHK_ADDR_ALIGN 0
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_CHK_ADDR_BITS 8
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_TCAM_CHK_ADDR_SHIFT 22

/* switch :: PAGE_04_ARL_TCAM_STS :: PAGE_04_ARL_TCAM_STS_RESERVED [21:00] */
#define Wr_switch_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_04_ARL_TCAM_STS,0x3fffff,0,x)
#define Rd_switch_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_04_ARL_TCAM_STS,0x3fffff,0)
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_MASK 0x003fffff
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_BITS 22
#define SWITCH_PAGE_04_ARL_TCAM_STS_PAGE_04_ARL_TCAM_STS_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_04_ARL_TCAM_FULL_CNTR
 ***************************************************************************/
/* switch :: PAGE_04_ARL_TCAM_FULL_CNTR :: PAGE_04_ARL_TCAM_FULL_CNTR_ARL_TCAM_FUL_CNTR [31:00] */
#define Wr_switch_PAGE_04_ARL_TCAM_FULL_CNTR_PAGE_04_ARL_TCAM_FULL_CNTR_ARL_TCAM_FUL_CNTR(x) WriteReg(SWITCH_PAGE_04_ARL_TCAM_FULL_CNTR,x)
#define Rd_switch_PAGE_04_ARL_TCAM_FULL_CNTR_PAGE_04_ARL_TCAM_FULL_CNTR_ARL_TCAM_FUL_CNTR(x) ReadReg(SWITCH_PAGE_04_ARL_TCAM_FULL_CNTR)
#define SWITCH_PAGE_04_ARL_TCAM_FULL_CNTR_PAGE_04_ARL_TCAM_FULL_CNTR_ARL_TCAM_FUL_CNTR_MASK 0xffffffff
#define SWITCH_PAGE_04_ARL_TCAM_FULL_CNTR_PAGE_04_ARL_TCAM_FULL_CNTR_ARL_TCAM_FUL_CNTR_ALIGN 0
#define SWITCH_PAGE_04_ARL_TCAM_FULL_CNTR_PAGE_04_ARL_TCAM_FULL_CNTR_ARL_TCAM_FUL_CNTR_BITS 32
#define SWITCH_PAGE_04_ARL_TCAM_FULL_CNTR_PAGE_04_ARL_TCAM_FULL_CNTR_ARL_TCAM_FUL_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_RWCTL
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_RWCTL :: PAGE_05_ARLA_RWCTL_ARL_STRTDN [07:07] */
#define Wr_switch_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_STRTDN(x) WriteRegBits(SWITCH_PAGE_05_ARLA_RWCTL,0x80,7,x)
#define Rd_switch_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_STRTDN(x) ReadRegBits(SWITCH_PAGE_05_ARLA_RWCTL,0x80,7)
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_STRTDN_MASK 0x80
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_STRTDN_ALIGN 0
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_STRTDN_BITS 1
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_STRTDN_SHIFT 7

/* switch :: PAGE_05_ARLA_RWCTL :: PAGE_05_ARLA_RWCTL_IVL_SVL_SELECT [06:06] */
#define Wr_switch_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_IVL_SVL_SELECT(x) WriteRegBits(SWITCH_PAGE_05_ARLA_RWCTL,0x40,6,x)
#define Rd_switch_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_IVL_SVL_SELECT(x) ReadRegBits(SWITCH_PAGE_05_ARLA_RWCTL,0x40,6)
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_IVL_SVL_SELECT_MASK 0x40
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_IVL_SVL_SELECT_ALIGN 0
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_IVL_SVL_SELECT_BITS 1
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_IVL_SVL_SELECT_SHIFT 6

/* switch :: PAGE_05_ARLA_RWCTL :: PAGE_05_ARLA_RWCTL_RESERVED [05:01] */
#define Wr_switch_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_RWCTL,0x3e,1,x)
#define Rd_switch_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_RWCTL,0x3e,1)
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_RESERVED_MASK 0x3e
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_RESERVED_BITS 5
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_RESERVED_SHIFT 1

/* switch :: PAGE_05_ARLA_RWCTL :: PAGE_05_ARLA_RWCTL_ARL_RW [00:00] */
#define Wr_switch_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_RW(x) WriteRegBits(SWITCH_PAGE_05_ARLA_RWCTL,0x1,0,x)
#define Rd_switch_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_RW(x) ReadRegBits(SWITCH_PAGE_05_ARLA_RWCTL,0x1,0)
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_RW_MASK   0x01
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_RW_ALIGN  0
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_RW_BITS   1
#define SWITCH_PAGE_05_ARLA_RWCTL_PAGE_05_ARLA_RWCTL_ARL_RW_SHIFT  0


/****************************************************************************
 * switch :: PAGE_05_ARLA_MAC
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_MAC :: reserved0 [63:48] */
#define SWITCH_PAGE_05_ARLA_MAC_RESERVED0_MASK                     0xffff000000000000
#define SWITCH_PAGE_05_ARLA_MAC_RESERVED0_ALIGN                    0
#define SWITCH_PAGE_05_ARLA_MAC_RESERVED0_BITS                     16
#define SWITCH_PAGE_05_ARLA_MAC_RESERVED0_SHIFT                    48

/* switch :: PAGE_05_ARLA_MAC :: PAGE_05_ARLA_MAC_MAC_ADDR_INDX [47:00] */
#define Wr_switch_PAGE_05_ARLA_MAC_PAGE_05_ARLA_MAC_MAC_ADDR_INDX(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MAC,0xffffffffffff,0,x)
#define Rd_switch_PAGE_05_ARLA_MAC_PAGE_05_ARLA_MAC_MAC_ADDR_INDX(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MAC,0xffffffffffff,0)
#define SWITCH_PAGE_05_ARLA_MAC_PAGE_05_ARLA_MAC_MAC_ADDR_INDX_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_05_ARLA_MAC_PAGE_05_ARLA_MAC_MAC_ADDR_INDX_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MAC_PAGE_05_ARLA_MAC_MAC_ADDR_INDX_BITS 48
#define SWITCH_PAGE_05_ARLA_MAC_PAGE_05_ARLA_MAC_MAC_ADDR_INDX_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_VID
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_VID :: PAGE_05_ARLA_VID_ARLA_VIDTAB_RSRV0 [15:12] */
#define Wr_switch_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_RSRV0(x) WriteRegBits16(SWITCH_PAGE_05_ARLA_VID,0xf000,12,x)
#define Rd_switch_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_RSRV0(x) ReadRegBits16(SWITCH_PAGE_05_ARLA_VID,0xf000,12)
#define SWITCH_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_RSRV0_MASK 0xf000
#define SWITCH_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_RSRV0_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_RSRV0_BITS 4
#define SWITCH_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_RSRV0_SHIFT 12

/* switch :: PAGE_05_ARLA_VID :: PAGE_05_ARLA_VID_ARLA_VIDTAB_INDX [11:00] */
#define Wr_switch_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_INDX(x) WriteRegBits16(SWITCH_PAGE_05_ARLA_VID,0xfff,0,x)
#define Rd_switch_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_INDX(x) ReadRegBits16(SWITCH_PAGE_05_ARLA_VID,0xfff,0)
#define SWITCH_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_INDX_MASK 0x0fff
#define SWITCH_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_INDX_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_INDX_BITS 12
#define SWITCH_PAGE_05_ARLA_VID_PAGE_05_ARLA_VID_ARLA_VIDTAB_INDX_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_MACVID_ENTRY0
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_MACVID_ENTRY0 :: PAGE_05_ARLA_MACVID_ENTRY0_RESERVED [63:60] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY0,0xf000000000000000,60,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY0,0xf000000000000000,60)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_RESERVED_MASK 0xf000000000000000
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_RESERVED_BITS 4
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_RESERVED_SHIFT 60

/* switch :: PAGE_05_ARLA_MACVID_ENTRY0 :: PAGE_05_ARLA_MACVID_ENTRY0_VID [59:48] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_VID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY0,0xfff000000000000,48,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_VID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY0,0xfff000000000000,48)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_VID_MASK 0x0fff000000000000
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_VID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_VID_BITS 12
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_VID_SHIFT 48

/* switch :: PAGE_05_ARLA_MACVID_ENTRY0 :: PAGE_05_ARLA_MACVID_ENTRY0_ARL_MACADDR [47:00] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_ARL_MACADDR(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY0,0xffffffffffff,0,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_ARL_MACADDR(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY0,0xffffffffffff,0)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_ARL_MACADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_ARL_MACADDR_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_ARL_MACADDR_BITS 48
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY0_PAGE_05_ARLA_MACVID_ENTRY0_ARL_MACADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_FWD_ENTRY0
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_FWD_ENTRY0 :: PAGE_05_ARLA_FWD_ENTRY0_RESERVED [31:17] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0xfffe0000,17,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0xfffe0000,17)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_RESERVED_MASK 0xfffe0000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_RESERVED_BITS 15
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_RESERVED_SHIFT 17

/* switch :: PAGE_05_ARLA_FWD_ENTRY0 :: PAGE_05_ARLA_FWD_ENTRY0_ARL_VALID [16:16] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_VALID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x10000,16,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_VALID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x10000,16)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_VALID_MASK 0x00010000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_VALID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_VALID_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_VALID_SHIFT 16

/* switch :: PAGE_05_ARLA_FWD_ENTRY0 :: PAGE_05_ARLA_FWD_ENTRY0_ARL_STATIC [15:15] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_STATIC(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x8000,15,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_STATIC(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x8000,15)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_STATIC_MASK 0x00008000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_STATIC_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_STATIC_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_STATIC_SHIFT 15

/* switch :: PAGE_05_ARLA_FWD_ENTRY0 :: PAGE_05_ARLA_FWD_ENTRY0_ARL_AGE [14:14] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_AGE(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x4000,14,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_AGE(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x4000,14)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_AGE_MASK 0x00004000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_AGE_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_AGE_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_AGE_SHIFT 14

/* switch :: PAGE_05_ARLA_FWD_ENTRY0 :: PAGE_05_ARLA_FWD_ENTRY0_ARL_PRI [13:11] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_PRI(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x3800,11,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_PRI(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x3800,11)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_PRI_MASK 0x00003800
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_PRI_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_PRI_BITS 3
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_PRI_SHIFT 11

/* switch :: PAGE_05_ARLA_FWD_ENTRY0 :: PAGE_05_ARLA_FWD_ENTRY0_ARL_CON [10:09] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_CON(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x600,9,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_CON(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x600,9)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_CON_MASK 0x00000600
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_CON_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_CON_BITS 2
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_ARL_CON_SHIFT 9

/* switch :: PAGE_05_ARLA_FWD_ENTRY0 :: PAGE_05_ARLA_FWD_ENTRY0_PORTID [08:00] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_PORTID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x1ff,0,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_PORTID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY0,0x1ff,0)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_PORTID_MASK 0x000001ff
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_PORTID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_PORTID_BITS 9
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY0_PAGE_05_ARLA_FWD_ENTRY0_PORTID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_MACVID_ENTRY1
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_MACVID_ENTRY1 :: PAGE_05_ARLA_MACVID_ENTRY1_RESERVED [63:60] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY1,0xf000000000000000,60,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY1,0xf000000000000000,60)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_RESERVED_MASK 0xf000000000000000
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_RESERVED_BITS 4
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_RESERVED_SHIFT 60

/* switch :: PAGE_05_ARLA_MACVID_ENTRY1 :: PAGE_05_ARLA_MACVID_ENTRY1_VID [59:48] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_VID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY1,0xfff000000000000,48,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_VID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY1,0xfff000000000000,48)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_VID_MASK 0x0fff000000000000
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_VID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_VID_BITS 12
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_VID_SHIFT 48

/* switch :: PAGE_05_ARLA_MACVID_ENTRY1 :: PAGE_05_ARLA_MACVID_ENTRY1_ARL_MACADDR [47:00] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_ARL_MACADDR(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY1,0xffffffffffff,0,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_ARL_MACADDR(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY1,0xffffffffffff,0)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_ARL_MACADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_ARL_MACADDR_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_ARL_MACADDR_BITS 48
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY1_PAGE_05_ARLA_MACVID_ENTRY1_ARL_MACADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_FWD_ENTRY1
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_FWD_ENTRY1 :: PAGE_05_ARLA_FWD_ENTRY1_RESERVED [31:17] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0xfffe0000,17,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0xfffe0000,17)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_RESERVED_MASK 0xfffe0000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_RESERVED_BITS 15
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_RESERVED_SHIFT 17

/* switch :: PAGE_05_ARLA_FWD_ENTRY1 :: PAGE_05_ARLA_FWD_ENTRY1_ARL_VALID [16:16] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_VALID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x10000,16,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_VALID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x10000,16)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_VALID_MASK 0x00010000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_VALID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_VALID_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_VALID_SHIFT 16

/* switch :: PAGE_05_ARLA_FWD_ENTRY1 :: PAGE_05_ARLA_FWD_ENTRY1_ARL_STATIC [15:15] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_STATIC(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x8000,15,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_STATIC(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x8000,15)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_STATIC_MASK 0x00008000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_STATIC_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_STATIC_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_STATIC_SHIFT 15

/* switch :: PAGE_05_ARLA_FWD_ENTRY1 :: PAGE_05_ARLA_FWD_ENTRY1_ARL_AGE [14:14] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_AGE(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x4000,14,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_AGE(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x4000,14)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_AGE_MASK 0x00004000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_AGE_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_AGE_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_AGE_SHIFT 14

/* switch :: PAGE_05_ARLA_FWD_ENTRY1 :: PAGE_05_ARLA_FWD_ENTRY1_ARL_PRI [13:11] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_PRI(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x3800,11,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_PRI(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x3800,11)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_PRI_MASK 0x00003800
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_PRI_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_PRI_BITS 3
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_PRI_SHIFT 11

/* switch :: PAGE_05_ARLA_FWD_ENTRY1 :: PAGE_05_ARLA_FWD_ENTRY1_ARL_CON [10:09] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_CON(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x600,9,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_CON(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x600,9)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_CON_MASK 0x00000600
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_CON_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_CON_BITS 2
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_ARL_CON_SHIFT 9

/* switch :: PAGE_05_ARLA_FWD_ENTRY1 :: PAGE_05_ARLA_FWD_ENTRY1_PORTID [08:00] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_PORTID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x1ff,0,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_PORTID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY1,0x1ff,0)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_PORTID_MASK 0x000001ff
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_PORTID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_PORTID_BITS 9
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY1_PAGE_05_ARLA_FWD_ENTRY1_PORTID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_MACVID_ENTRY2
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_MACVID_ENTRY2 :: PAGE_05_ARLA_MACVID_ENTRY2_RESERVED [63:60] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY2,0xf000000000000000,60,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY2,0xf000000000000000,60)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_RESERVED_MASK 0xf000000000000000
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_RESERVED_BITS 4
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_RESERVED_SHIFT 60

/* switch :: PAGE_05_ARLA_MACVID_ENTRY2 :: PAGE_05_ARLA_MACVID_ENTRY2_VID [59:48] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_VID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY2,0xfff000000000000,48,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_VID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY2,0xfff000000000000,48)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_VID_MASK 0x0fff000000000000
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_VID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_VID_BITS 12
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_VID_SHIFT 48

/* switch :: PAGE_05_ARLA_MACVID_ENTRY2 :: PAGE_05_ARLA_MACVID_ENTRY2_ARL_MACADDR [47:00] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_ARL_MACADDR(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY2,0xffffffffffff,0,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_ARL_MACADDR(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY2,0xffffffffffff,0)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_ARL_MACADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_ARL_MACADDR_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_ARL_MACADDR_BITS 48
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY2_PAGE_05_ARLA_MACVID_ENTRY2_ARL_MACADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_FWD_ENTRY2
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_FWD_ENTRY2 :: PAGE_05_ARLA_FWD_ENTRY2_RESERVED [31:17] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0xfffe0000,17,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0xfffe0000,17)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_RESERVED_MASK 0xfffe0000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_RESERVED_BITS 15
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_RESERVED_SHIFT 17

/* switch :: PAGE_05_ARLA_FWD_ENTRY2 :: PAGE_05_ARLA_FWD_ENTRY2_ARL_VALID [16:16] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_VALID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x10000,16,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_VALID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x10000,16)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_VALID_MASK 0x00010000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_VALID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_VALID_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_VALID_SHIFT 16

/* switch :: PAGE_05_ARLA_FWD_ENTRY2 :: PAGE_05_ARLA_FWD_ENTRY2_ARL_STATIC [15:15] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_STATIC(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x8000,15,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_STATIC(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x8000,15)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_STATIC_MASK 0x00008000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_STATIC_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_STATIC_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_STATIC_SHIFT 15

/* switch :: PAGE_05_ARLA_FWD_ENTRY2 :: PAGE_05_ARLA_FWD_ENTRY2_ARL_AGE [14:14] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_AGE(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x4000,14,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_AGE(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x4000,14)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_AGE_MASK 0x00004000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_AGE_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_AGE_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_AGE_SHIFT 14

/* switch :: PAGE_05_ARLA_FWD_ENTRY2 :: PAGE_05_ARLA_FWD_ENTRY2_ARL_PRI [13:11] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_PRI(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x3800,11,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_PRI(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x3800,11)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_PRI_MASK 0x00003800
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_PRI_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_PRI_BITS 3
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_PRI_SHIFT 11

/* switch :: PAGE_05_ARLA_FWD_ENTRY2 :: PAGE_05_ARLA_FWD_ENTRY2_ARL_CON [10:09] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_CON(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x600,9,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_CON(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x600,9)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_CON_MASK 0x00000600
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_CON_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_CON_BITS 2
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_ARL_CON_SHIFT 9

/* switch :: PAGE_05_ARLA_FWD_ENTRY2 :: PAGE_05_ARLA_FWD_ENTRY2_PORTID [08:00] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_PORTID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x1ff,0,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_PORTID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY2,0x1ff,0)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_PORTID_MASK 0x000001ff
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_PORTID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_PORTID_BITS 9
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY2_PAGE_05_ARLA_FWD_ENTRY2_PORTID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_MACVID_ENTRY3
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_MACVID_ENTRY3 :: PAGE_05_ARLA_MACVID_ENTRY3_RESERVED [63:60] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY3,0xf000000000000000,60,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY3,0xf000000000000000,60)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_RESERVED_MASK 0xf000000000000000
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_RESERVED_BITS 4
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_RESERVED_SHIFT 60

/* switch :: PAGE_05_ARLA_MACVID_ENTRY3 :: PAGE_05_ARLA_MACVID_ENTRY3_VID [59:48] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_VID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY3,0xfff000000000000,48,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_VID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY3,0xfff000000000000,48)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_VID_MASK 0x0fff000000000000
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_VID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_VID_BITS 12
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_VID_SHIFT 48

/* switch :: PAGE_05_ARLA_MACVID_ENTRY3 :: PAGE_05_ARLA_MACVID_ENTRY3_ARL_MACADDR [47:00] */
#define Wr_switch_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_ARL_MACADDR(x) WriteRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY3,0xffffffffffff,0,x)
#define Rd_switch_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_ARL_MACADDR(x) ReadRegBits(SWITCH_PAGE_05_ARLA_MACVID_ENTRY3,0xffffffffffff,0)
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_ARL_MACADDR_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_ARL_MACADDR_ALIGN 0
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_ARL_MACADDR_BITS 48
#define SWITCH_PAGE_05_ARLA_MACVID_ENTRY3_PAGE_05_ARLA_MACVID_ENTRY3_ARL_MACADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_FWD_ENTRY3
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_FWD_ENTRY3 :: PAGE_05_ARLA_FWD_ENTRY3_RESERVED [31:17] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0xfffe0000,17,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0xfffe0000,17)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_RESERVED_MASK 0xfffe0000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_RESERVED_BITS 15
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_RESERVED_SHIFT 17

/* switch :: PAGE_05_ARLA_FWD_ENTRY3 :: PAGE_05_ARLA_FWD_ENTRY3_ARL_VALID [16:16] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_VALID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x10000,16,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_VALID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x10000,16)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_VALID_MASK 0x00010000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_VALID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_VALID_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_VALID_SHIFT 16

/* switch :: PAGE_05_ARLA_FWD_ENTRY3 :: PAGE_05_ARLA_FWD_ENTRY3_ARL_STATIC [15:15] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_STATIC(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x8000,15,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_STATIC(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x8000,15)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_STATIC_MASK 0x00008000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_STATIC_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_STATIC_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_STATIC_SHIFT 15

/* switch :: PAGE_05_ARLA_FWD_ENTRY3 :: PAGE_05_ARLA_FWD_ENTRY3_ARL_AGE [14:14] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_AGE(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x4000,14,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_AGE(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x4000,14)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_AGE_MASK 0x00004000
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_AGE_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_AGE_BITS 1
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_AGE_SHIFT 14

/* switch :: PAGE_05_ARLA_FWD_ENTRY3 :: PAGE_05_ARLA_FWD_ENTRY3_ARL_PRI [13:11] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_PRI(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x3800,11,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_PRI(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x3800,11)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_PRI_MASK 0x00003800
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_PRI_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_PRI_BITS 3
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_PRI_SHIFT 11

/* switch :: PAGE_05_ARLA_FWD_ENTRY3 :: PAGE_05_ARLA_FWD_ENTRY3_ARL_CON [10:09] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_CON(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x600,9,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_CON(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x600,9)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_CON_MASK 0x00000600
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_CON_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_CON_BITS 2
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_ARL_CON_SHIFT 9

/* switch :: PAGE_05_ARLA_FWD_ENTRY3 :: PAGE_05_ARLA_FWD_ENTRY3_PORTID [08:00] */
#define Wr_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_PORTID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x1ff,0,x)
#define Rd_switch_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_PORTID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_FWD_ENTRY3,0x1ff,0)
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_PORTID_MASK 0x000001ff
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_PORTID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_PORTID_BITS 9
#define SWITCH_PAGE_05_ARLA_FWD_ENTRY3_PAGE_05_ARLA_FWD_ENTRY3_PORTID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_SRCH_CTL
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_SRCH_CTL :: PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_STDN [07:07] */
#define Wr_switch_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_STDN(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_CTL,0x80,7,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_STDN(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_CTL,0x80,7)
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_STDN_MASK 0x80
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_STDN_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_STDN_BITS 1
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_STDN_SHIFT 7

/* switch :: PAGE_05_ARLA_SRCH_CTL :: PAGE_05_ARLA_SRCH_CTL_RESERVED [06:01] */
#define Wr_switch_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_CTL,0x7e,1,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_CTL,0x7e,1)
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_RESERVED_MASK 0x7e
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_RESERVED_BITS 6
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_RESERVED_SHIFT 1

/* switch :: PAGE_05_ARLA_SRCH_CTL :: PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_VLID [00:00] */
#define Wr_switch_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_VLID(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_CTL,0x1,0,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_VLID(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_CTL,0x1,0)
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_VLID_MASK 0x01
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_VLID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_VLID_BITS 1
#define SWITCH_PAGE_05_ARLA_SRCH_CTL_PAGE_05_ARLA_SRCH_CTL_ARLA_SRCH_VLID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_SRCH_ADR
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_SRCH_ADR :: PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID [15:15] */
#define Wr_switch_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID(x) WriteRegBits16(SWITCH_PAGE_05_ARLA_SRCH_ADR,0x8000,15,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID(x) ReadRegBits16(SWITCH_PAGE_05_ARLA_SRCH_ADR,0x8000,15)
#define SWITCH_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_MASK 0x8000
#define SWITCH_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_BITS 1
#define SWITCH_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADR_VALID_SHIFT 15

/* switch :: PAGE_05_ARLA_SRCH_ADR :: PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS [14:00] */
#define Wr_switch_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS(x) WriteRegBits16(SWITCH_PAGE_05_ARLA_SRCH_ADR,0x7fff,0,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS(x) ReadRegBits16(SWITCH_PAGE_05_ARLA_SRCH_ADR,0x7fff,0)
#define SWITCH_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_MASK 0x7fff
#define SWITCH_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_BITS 15
#define SWITCH_PAGE_05_ARLA_SRCH_ADR_PAGE_05_ARLA_SRCH_ADR_ARLA_SRCH_ADDRESS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_SRCH_RSLT_0_MACVID
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_SRCH_RSLT_0_MACVID :: PAGE_05_ARLA_SRCH_RSLT_0_MACVID_RESERVED [63:60] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID,0xf000000000000000,60,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID,0xf000000000000000,60)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_RESERVED_MASK 0xf000000000000000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_RESERVED_BITS 4
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_RESERVED_SHIFT 60

/* switch :: PAGE_05_ARLA_SRCH_RSLT_0_MACVID :: PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0 [59:48] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID,0xfff000000000000,48,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID,0xfff000000000000,48)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_MASK 0x0fff000000000000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_BITS 12
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_RSLT_VID_0_SHIFT 48

/* switch :: PAGE_05_ARLA_SRCH_RSLT_0_MACVID :: PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0 [47:00] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID,0xffffffffffff,0,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID,0xffffffffffff,0)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_BITS 48
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_PAGE_05_ARLA_SRCH_RSLT_0_MACVID_ARLA_SRCH_MACADDR_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_SRCH_RSLT_0
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_SRCH_RSLT_0 :: PAGE_05_ARLA_SRCH_RSLT_0_RESERVED [31:17] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0xfffe0000,17,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0xfffe0000,17)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_RESERVED_MASK 0xfffe0000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_RESERVED_BITS 15
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_RESERVED_SHIFT 17

/* switch :: PAGE_05_ARLA_SRCH_RSLT_0 :: PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0 [16:16] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x10000,16,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x10000,16)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_MASK 0x00010000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_BITS 1
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_VLID_0_SHIFT 16

/* switch :: PAGE_05_ARLA_SRCH_RSLT_0 :: PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0 [15:15] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x8000,15,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x8000,15)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_MASK 0x00008000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_BITS 1
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_STATIC_0_SHIFT 15

/* switch :: PAGE_05_ARLA_SRCH_RSLT_0 :: PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0 [14:14] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x4000,14,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x4000,14)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_MASK 0x00004000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_BITS 1
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_AGE_0_SHIFT 14

/* switch :: PAGE_05_ARLA_SRCH_RSLT_0 :: PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0 [13:11] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x3800,11,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x3800,11)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_MASK 0x00003800
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_BITS 3
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARLA_SRCH_RSLT_PRI_0_SHIFT 11

/* switch :: PAGE_05_ARLA_SRCH_RSLT_0 :: PAGE_05_ARLA_SRCH_RSLT_0_ARL_CON_0 [10:09] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARL_CON_0(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x600,9,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARL_CON_0(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x600,9)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARL_CON_0_MASK 0x00000600
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARL_CON_0_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARL_CON_0_BITS 2
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_ARL_CON_0_SHIFT 9

/* switch :: PAGE_05_ARLA_SRCH_RSLT_0 :: PAGE_05_ARLA_SRCH_RSLT_0_PORTID_0 [08:00] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_PORTID_0(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x1ff,0,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_PORTID_0(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_0,0x1ff,0)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_PORTID_0_MASK 0x000001ff
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_PORTID_0_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_PORTID_0_BITS 9
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_0_PAGE_05_ARLA_SRCH_RSLT_0_PORTID_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_SRCH_RSLT_1_MACVID
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_SRCH_RSLT_1_MACVID :: PAGE_05_ARLA_SRCH_RSLT_1_MACVID_RESERVED [63:60] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID,0xf000000000000000,60,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID,0xf000000000000000,60)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_RESERVED_MASK 0xf000000000000000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_RESERVED_BITS 4
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_RESERVED_SHIFT 60

/* switch :: PAGE_05_ARLA_SRCH_RSLT_1_MACVID :: PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1 [59:48] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID,0xfff000000000000,48,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID,0xfff000000000000,48)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_MASK 0x0fff000000000000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_BITS 12
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_RSLT_VID_1_SHIFT 48

/* switch :: PAGE_05_ARLA_SRCH_RSLT_1_MACVID :: PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1 [47:00] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID,0xffffffffffff,0,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID,0xffffffffffff,0)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_BITS 48
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_PAGE_05_ARLA_SRCH_RSLT_1_MACVID_ARLA_SRCH_MACADDR_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_SRCH_RSLT_1
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_SRCH_RSLT_1 :: PAGE_05_ARLA_SRCH_RSLT_1_RESERVED [31:17] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0xfffe0000,17,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0xfffe0000,17)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_RESERVED_MASK 0xfffe0000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_RESERVED_BITS 15
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_RESERVED_SHIFT 17

/* switch :: PAGE_05_ARLA_SRCH_RSLT_1 :: PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1 [16:16] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x10000,16,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x10000,16)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_MASK 0x00010000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_BITS 1
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_VLID_1_SHIFT 16

/* switch :: PAGE_05_ARLA_SRCH_RSLT_1 :: PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1 [15:15] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x8000,15,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x8000,15)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_MASK 0x00008000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_BITS 1
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_STATIC_1_SHIFT 15

/* switch :: PAGE_05_ARLA_SRCH_RSLT_1 :: PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1 [14:14] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x4000,14,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x4000,14)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_MASK 0x00004000
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_BITS 1
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_AGE_1_SHIFT 14

/* switch :: PAGE_05_ARLA_SRCH_RSLT_1 :: PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1 [13:11] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x3800,11,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x3800,11)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_MASK 0x00003800
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_BITS 3
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARLA_SRCH_RSLT_PRI_1_SHIFT 11

/* switch :: PAGE_05_ARLA_SRCH_RSLT_1 :: PAGE_05_ARLA_SRCH_RSLT_1_ARL_CON_1 [10:09] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARL_CON_1(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x600,9,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARL_CON_1(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x600,9)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARL_CON_1_MASK 0x00000600
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARL_CON_1_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARL_CON_1_BITS 2
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_ARL_CON_1_SHIFT 9

/* switch :: PAGE_05_ARLA_SRCH_RSLT_1 :: PAGE_05_ARLA_SRCH_RSLT_1_PORTID_1 [08:00] */
#define Wr_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_PORTID_1(x) WriteRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x1ff,0,x)
#define Rd_switch_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_PORTID_1(x) ReadRegBits(SWITCH_PAGE_05_ARLA_SRCH_RSLT_1,0x1ff,0)
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_PORTID_1_MASK 0x000001ff
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_PORTID_1_ALIGN 0
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_PORTID_1_BITS 9
#define SWITCH_PAGE_05_ARLA_SRCH_RSLT_1_PAGE_05_ARLA_SRCH_RSLT_1_PORTID_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_VTBL_RWCTRL
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_VTBL_RWCTRL :: PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN [07:07] */
#define Wr_switch_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN(x) WriteRegBits(SWITCH_PAGE_05_ARLA_VTBL_RWCTRL,0x80,7,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN(x) ReadRegBits(SWITCH_PAGE_05_ARLA_VTBL_RWCTRL,0x80,7)
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_MASK 0x80
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_BITS 1
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_STDN_SHIFT 7

/* switch :: PAGE_05_ARLA_VTBL_RWCTRL :: PAGE_05_ARLA_VTBL_RWCTRL_RESERVED [06:02] */
#define Wr_switch_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_VTBL_RWCTRL,0x7c,2,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_VTBL_RWCTRL,0x7c,2)
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_RESERVED_MASK 0x7c
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_RESERVED_BITS 5
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_RESERVED_SHIFT 2

/* switch :: PAGE_05_ARLA_VTBL_RWCTRL :: PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR [01:00] */
#define Wr_switch_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR(x) WriteRegBits(SWITCH_PAGE_05_ARLA_VTBL_RWCTRL,0x3,0,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR(x) ReadRegBits(SWITCH_PAGE_05_ARLA_VTBL_RWCTRL,0x3,0)
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_MASK 0x03
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_BITS 2
#define SWITCH_PAGE_05_ARLA_VTBL_RWCTRL_PAGE_05_ARLA_VTBL_RWCTRL_ARLA_VTBL_RW_CLR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_VTBL_ADDR
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_VTBL_ADDR :: PAGE_05_ARLA_VTBL_ADDR_RESERVED [15:12] */
#define Wr_switch_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_RESERVED(x) WriteRegBits16(SWITCH_PAGE_05_ARLA_VTBL_ADDR,0xf000,12,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_RESERVED(x) ReadRegBits16(SWITCH_PAGE_05_ARLA_VTBL_ADDR,0xf000,12)
#define SWITCH_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_RESERVED_MASK 0xf000
#define SWITCH_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_RESERVED_BITS 4
#define SWITCH_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_RESERVED_SHIFT 12

/* switch :: PAGE_05_ARLA_VTBL_ADDR :: PAGE_05_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX [11:00] */
#define Wr_switch_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX(x) WriteRegBits16(SWITCH_PAGE_05_ARLA_VTBL_ADDR,0xfff,0,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX(x) ReadRegBits16(SWITCH_PAGE_05_ARLA_VTBL_ADDR,0xfff,0)
#define SWITCH_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_MASK 0x0fff
#define SWITCH_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_BITS 12
#define SWITCH_PAGE_05_ARLA_VTBL_ADDR_PAGE_05_ARLA_VTBL_ADDR_VTBL_ADDR_INDEX_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLA_VTBL_ENTRY
 ***************************************************************************/
/* switch :: PAGE_05_ARLA_VTBL_ENTRY :: PAGE_05_ARLA_VTBL_ENTRY_RESERVED [31:22] */
#define Wr_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_RESERVED(x) WriteRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0xffc00000,22,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_RESERVED(x) ReadRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0xffc00000,22)
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_RESERVED_MASK 0xffc00000
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_RESERVED_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_RESERVED_BITS 10
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_RESERVED_SHIFT 22

/* switch :: PAGE_05_ARLA_VTBL_ENTRY :: PAGE_05_ARLA_VTBL_ENTRY_FWD_MODE [21:21] */
#define Wr_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MODE(x) WriteRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0x200000,21,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MODE(x) ReadRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0x200000,21)
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MODE_MASK 0x00200000
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MODE_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MODE_BITS 1
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MODE_SHIFT 21

/* switch :: PAGE_05_ARLA_VTBL_ENTRY :: PAGE_05_ARLA_VTBL_ENTRY_MSPT_INDEX [20:18] */
#define Wr_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_MSPT_INDEX(x) WriteRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0x1c0000,18,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_MSPT_INDEX(x) ReadRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0x1c0000,18)
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_MSPT_INDEX_MASK 0x001c0000
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_MSPT_INDEX_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_MSPT_INDEX_BITS 3
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_MSPT_INDEX_SHIFT 18

/* switch :: PAGE_05_ARLA_VTBL_ENTRY :: PAGE_05_ARLA_VTBL_ENTRY_UNTAG_MAP [17:09] */
#define Wr_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_UNTAG_MAP(x) WriteRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0x3fe00,9,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_UNTAG_MAP(x) ReadRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0x3fe00,9)
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_UNTAG_MAP_MASK 0x0003fe00
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_UNTAG_MAP_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_UNTAG_MAP_BITS 9
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_UNTAG_MAP_SHIFT 9

/* switch :: PAGE_05_ARLA_VTBL_ENTRY :: PAGE_05_ARLA_VTBL_ENTRY_FWD_MAP [08:00] */
#define Wr_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MAP(x) WriteRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0x1ff,0,x)
#define Rd_switch_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MAP(x) ReadRegBits(SWITCH_PAGE_05_ARLA_VTBL_ENTRY,0x1ff,0)
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MAP_MASK 0x000001ff
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MAP_ALIGN 0
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MAP_BITS 9
#define SWITCH_PAGE_05_ARLA_VTBL_ENTRY_PAGE_05_ARLA_VTBL_ENTRY_FWD_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLACCS_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_05_ARLACCS_REG_SPARE0 :: PAGE_05_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_05_ARLACCS_REG_SPARE0_PAGE_05_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0(x) WriteReg(SWITCH_PAGE_05_ARLACCS_REG_SPARE0,x)
#define Rd_switch_PAGE_05_ARLACCS_REG_SPARE0_PAGE_05_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0(x) ReadReg(SWITCH_PAGE_05_ARLACCS_REG_SPARE0)
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE0_PAGE_05_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE0_PAGE_05_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE0_PAGE_05_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_BITS 32
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE0_PAGE_05_ARLACCS_REG_SPARE0_ARLACCS_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_05_ARLACCS_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_05_ARLACCS_REG_SPARE1 :: PAGE_05_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_05_ARLACCS_REG_SPARE1_PAGE_05_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1(x) WriteReg(SWITCH_PAGE_05_ARLACCS_REG_SPARE1,x)
#define Rd_switch_PAGE_05_ARLACCS_REG_SPARE1_PAGE_05_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1(x) ReadReg(SWITCH_PAGE_05_ARLACCS_REG_SPARE1)
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE1_PAGE_05_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE1_PAGE_05_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE1_PAGE_05_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_BITS 32
#define SWITCH_PAGE_05_ARLACCS_REG_SPARE1_PAGE_05_ARLACCS_REG_SPARE1_ARLACCS_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_CTRL
 ***************************************************************************/
/* switch :: PAGE_08_MEM_CTRL :: PAGE_08_MEM_CTRL_MEM_TYPE [07:06] */
#define Wr_switch_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_MEM_TYPE(x) WriteRegBits(SWITCH_PAGE_08_MEM_CTRL,0xc0,6,x)
#define Rd_switch_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_MEM_TYPE(x) ReadRegBits(SWITCH_PAGE_08_MEM_CTRL,0xc0,6)
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_MEM_TYPE_MASK     0xc0
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_MEM_TYPE_ALIGN    0
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_MEM_TYPE_BITS     2
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_MEM_TYPE_SHIFT    6

/* switch :: PAGE_08_MEM_CTRL :: PAGE_08_MEM_CTRL_RESERVED_1 [05:04] */
#define Wr_switch_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_08_MEM_CTRL,0x30,4,x)
#define Rd_switch_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_08_MEM_CTRL,0x30,4)
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_1_MASK   0x30
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_1_ALIGN  0
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_1_BITS   2
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_1_SHIFT  4

/* switch :: PAGE_08_MEM_CTRL :: PAGE_08_MEM_CTRL_RESERVED_0 [03:00] */
#define Wr_switch_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_08_MEM_CTRL,0xf,0,x)
#define Rd_switch_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_08_MEM_CTRL,0xf,0)
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_0_MASK   0x0f
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_0_ALIGN  0
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_0_BITS   4
#define SWITCH_PAGE_08_MEM_CTRL_PAGE_08_MEM_CTRL_RESERVED_0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_08_MEM_ADDR
 ***************************************************************************/
/* switch :: PAGE_08_MEM_ADDR :: PAGE_08_MEM_ADDR_MEM_STDN [15:15] */
#define Wr_switch_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_STDN(x) WriteRegBits16(SWITCH_PAGE_08_MEM_ADDR,0x8000,15,x)
#define Rd_switch_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_STDN(x) ReadRegBits16(SWITCH_PAGE_08_MEM_ADDR,0x8000,15)
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_STDN_MASK     0x8000
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_STDN_ALIGN    0
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_STDN_BITS     1
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_STDN_SHIFT    15

/* switch :: PAGE_08_MEM_ADDR :: PAGE_08_MEM_ADDR_MEM_RW [14:14] */
#define Wr_switch_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_RW(x) WriteRegBits16(SWITCH_PAGE_08_MEM_ADDR,0x4000,14,x)
#define Rd_switch_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_RW(x) ReadRegBits16(SWITCH_PAGE_08_MEM_ADDR,0x4000,14)
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_RW_MASK       0x4000
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_RW_ALIGN      0
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_RW_BITS       1
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_RW_SHIFT      14

/* switch :: PAGE_08_MEM_ADDR :: PAGE_08_MEM_ADDR_MEM_ADR [13:00] */
#define Wr_switch_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_ADR(x) WriteRegBits16(SWITCH_PAGE_08_MEM_ADDR,0x3fff,0,x)
#define Rd_switch_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_ADR(x) ReadRegBits16(SWITCH_PAGE_08_MEM_ADDR,0x3fff,0)
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_ADR_MASK      0x3fff
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_ADR_ALIGN     0
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_ADR_BITS      14
#define SWITCH_PAGE_08_MEM_ADDR_PAGE_08_MEM_ADDR_MEM_ADR_SHIFT     0


/****************************************************************************
 * switch :: PAGE_08_MEM_DEBUG_DATA_0_0
 ***************************************************************************/
/* switch :: PAGE_08_MEM_DEBUG_DATA_0_0 :: PAGE_08_MEM_DEBUG_DATA_0_0_MEM_DAT [63:00] */
#define Wr_switch_PAGE_08_MEM_DEBUG_DATA_0_0_PAGE_08_MEM_DEBUG_DATA_0_0_MEM_DAT(x) WriteReg(SWITCH_PAGE_08_MEM_DEBUG_DATA_0_0,x)
#define Rd_switch_PAGE_08_MEM_DEBUG_DATA_0_0_PAGE_08_MEM_DEBUG_DATA_0_0_MEM_DAT(x) ReadReg(SWITCH_PAGE_08_MEM_DEBUG_DATA_0_0)
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_0_PAGE_08_MEM_DEBUG_DATA_0_0_MEM_DAT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_0_PAGE_08_MEM_DEBUG_DATA_0_0_MEM_DAT_ALIGN 0
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_0_PAGE_08_MEM_DEBUG_DATA_0_0_MEM_DAT_BITS 64
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_0_PAGE_08_MEM_DEBUG_DATA_0_0_MEM_DAT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_DEBUG_DATA_0_1
 ***************************************************************************/
/* switch :: PAGE_08_MEM_DEBUG_DATA_0_1 :: PAGE_08_MEM_DEBUG_DATA_0_1_MEM_DAT [15:00] */
#define Wr_switch_PAGE_08_MEM_DEBUG_DATA_0_1_PAGE_08_MEM_DEBUG_DATA_0_1_MEM_DAT(x) WriteReg16(SWITCH_PAGE_08_MEM_DEBUG_DATA_0_1,x)
#define Rd_switch_PAGE_08_MEM_DEBUG_DATA_0_1_PAGE_08_MEM_DEBUG_DATA_0_1_MEM_DAT(x) ReadReg16(SWITCH_PAGE_08_MEM_DEBUG_DATA_0_1)
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_1_PAGE_08_MEM_DEBUG_DATA_0_1_MEM_DAT_MASK 0xffff
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_1_PAGE_08_MEM_DEBUG_DATA_0_1_MEM_DAT_ALIGN 0
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_1_PAGE_08_MEM_DEBUG_DATA_0_1_MEM_DAT_BITS 16
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_0_1_PAGE_08_MEM_DEBUG_DATA_0_1_MEM_DAT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_DEBUG_DATA_1_0
 ***************************************************************************/
/* switch :: PAGE_08_MEM_DEBUG_DATA_1_0 :: PAGE_08_MEM_DEBUG_DATA_1_0_MEM_DAT [63:00] */
#define Wr_switch_PAGE_08_MEM_DEBUG_DATA_1_0_PAGE_08_MEM_DEBUG_DATA_1_0_MEM_DAT(x) WriteReg(SWITCH_PAGE_08_MEM_DEBUG_DATA_1_0,x)
#define Rd_switch_PAGE_08_MEM_DEBUG_DATA_1_0_PAGE_08_MEM_DEBUG_DATA_1_0_MEM_DAT(x) ReadReg(SWITCH_PAGE_08_MEM_DEBUG_DATA_1_0)
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_0_PAGE_08_MEM_DEBUG_DATA_1_0_MEM_DAT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_0_PAGE_08_MEM_DEBUG_DATA_1_0_MEM_DAT_ALIGN 0
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_0_PAGE_08_MEM_DEBUG_DATA_1_0_MEM_DAT_BITS 64
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_0_PAGE_08_MEM_DEBUG_DATA_1_0_MEM_DAT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_DEBUG_DATA_1_1
 ***************************************************************************/
/* switch :: PAGE_08_MEM_DEBUG_DATA_1_1 :: PAGE_08_MEM_DEBUG_DATA_1_1_MEM_DAT [15:00] */
#define Wr_switch_PAGE_08_MEM_DEBUG_DATA_1_1_PAGE_08_MEM_DEBUG_DATA_1_1_MEM_DAT(x) WriteReg16(SWITCH_PAGE_08_MEM_DEBUG_DATA_1_1,x)
#define Rd_switch_PAGE_08_MEM_DEBUG_DATA_1_1_PAGE_08_MEM_DEBUG_DATA_1_1_MEM_DAT(x) ReadReg16(SWITCH_PAGE_08_MEM_DEBUG_DATA_1_1)
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_1_PAGE_08_MEM_DEBUG_DATA_1_1_MEM_DAT_MASK 0xffff
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_1_PAGE_08_MEM_DEBUG_DATA_1_1_MEM_DAT_ALIGN 0
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_1_PAGE_08_MEM_DEBUG_DATA_1_1_MEM_DAT_BITS 16
#define SWITCH_PAGE_08_MEM_DEBUG_DATA_1_1_PAGE_08_MEM_DEBUG_DATA_1_1_MEM_DAT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_FRM_ADDR
 ***************************************************************************/
/* switch :: PAGE_08_MEM_FRM_ADDR :: PAGE_08_MEM_FRM_ADDR_MEM_STDN [15:15] */
#define Wr_switch_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_STDN(x) WriteRegBits16(SWITCH_PAGE_08_MEM_FRM_ADDR,0x8000,15,x)
#define Rd_switch_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_STDN(x) ReadRegBits16(SWITCH_PAGE_08_MEM_FRM_ADDR,0x8000,15)
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_STDN_MASK 0x8000
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_STDN_ALIGN 0
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_STDN_BITS 1
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_STDN_SHIFT 15

/* switch :: PAGE_08_MEM_FRM_ADDR :: PAGE_08_MEM_FRM_ADDR_MEM_RW [14:14] */
#define Wr_switch_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_RW(x) WriteRegBits16(SWITCH_PAGE_08_MEM_FRM_ADDR,0x4000,14,x)
#define Rd_switch_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_RW(x) ReadRegBits16(SWITCH_PAGE_08_MEM_FRM_ADDR,0x4000,14)
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_RW_MASK 0x4000
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_RW_ALIGN 0
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_RW_BITS 1
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_RW_SHIFT 14

/* switch :: PAGE_08_MEM_FRM_ADDR :: PAGE_08_MEM_FRM_ADDR_MEM_ADR [13:00] */
#define Wr_switch_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_ADR(x) WriteRegBits16(SWITCH_PAGE_08_MEM_FRM_ADDR,0x3fff,0,x)
#define Rd_switch_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_ADR(x) ReadRegBits16(SWITCH_PAGE_08_MEM_FRM_ADDR,0x3fff,0)
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_ADR_MASK 0x3fff
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_ADR_ALIGN 0
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_ADR_BITS 14
#define SWITCH_PAGE_08_MEM_FRM_ADDR_PAGE_08_MEM_FRM_ADDR_MEM_ADR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_FRM_DATA0
 ***************************************************************************/
/* switch :: PAGE_08_MEM_FRM_DATA0 :: PAGE_08_MEM_FRM_DATA0_MEM_DATA [63:00] */
#define Wr_switch_PAGE_08_MEM_FRM_DATA0_PAGE_08_MEM_FRM_DATA0_MEM_DATA(x) WriteReg(SWITCH_PAGE_08_MEM_FRM_DATA0,x)
#define Rd_switch_PAGE_08_MEM_FRM_DATA0_PAGE_08_MEM_FRM_DATA0_MEM_DATA(x) ReadReg(SWITCH_PAGE_08_MEM_FRM_DATA0)
#define SWITCH_PAGE_08_MEM_FRM_DATA0_PAGE_08_MEM_FRM_DATA0_MEM_DATA_MASK 0xffffffffffffffff
#define SWITCH_PAGE_08_MEM_FRM_DATA0_PAGE_08_MEM_FRM_DATA0_MEM_DATA_ALIGN 0
#define SWITCH_PAGE_08_MEM_FRM_DATA0_PAGE_08_MEM_FRM_DATA0_MEM_DATA_BITS 64
#define SWITCH_PAGE_08_MEM_FRM_DATA0_PAGE_08_MEM_FRM_DATA0_MEM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_FRM_DATA1
 ***************************************************************************/
/* switch :: PAGE_08_MEM_FRM_DATA1 :: PAGE_08_MEM_FRM_DATA1_MEM_DATA [63:00] */
#define Wr_switch_PAGE_08_MEM_FRM_DATA1_PAGE_08_MEM_FRM_DATA1_MEM_DATA(x) WriteReg(SWITCH_PAGE_08_MEM_FRM_DATA1,x)
#define Rd_switch_PAGE_08_MEM_FRM_DATA1_PAGE_08_MEM_FRM_DATA1_MEM_DATA(x) ReadReg(SWITCH_PAGE_08_MEM_FRM_DATA1)
#define SWITCH_PAGE_08_MEM_FRM_DATA1_PAGE_08_MEM_FRM_DATA1_MEM_DATA_MASK 0xffffffffffffffff
#define SWITCH_PAGE_08_MEM_FRM_DATA1_PAGE_08_MEM_FRM_DATA1_MEM_DATA_ALIGN 0
#define SWITCH_PAGE_08_MEM_FRM_DATA1_PAGE_08_MEM_FRM_DATA1_MEM_DATA_BITS 64
#define SWITCH_PAGE_08_MEM_FRM_DATA1_PAGE_08_MEM_FRM_DATA1_MEM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_FRM_DATA2
 ***************************************************************************/
/* switch :: PAGE_08_MEM_FRM_DATA2 :: PAGE_08_MEM_FRM_DATA2_MEM_DATA [63:00] */
#define Wr_switch_PAGE_08_MEM_FRM_DATA2_PAGE_08_MEM_FRM_DATA2_MEM_DATA(x) WriteReg(SWITCH_PAGE_08_MEM_FRM_DATA2,x)
#define Rd_switch_PAGE_08_MEM_FRM_DATA2_PAGE_08_MEM_FRM_DATA2_MEM_DATA(x) ReadReg(SWITCH_PAGE_08_MEM_FRM_DATA2)
#define SWITCH_PAGE_08_MEM_FRM_DATA2_PAGE_08_MEM_FRM_DATA2_MEM_DATA_MASK 0xffffffffffffffff
#define SWITCH_PAGE_08_MEM_FRM_DATA2_PAGE_08_MEM_FRM_DATA2_MEM_DATA_ALIGN 0
#define SWITCH_PAGE_08_MEM_FRM_DATA2_PAGE_08_MEM_FRM_DATA2_MEM_DATA_BITS 64
#define SWITCH_PAGE_08_MEM_FRM_DATA2_PAGE_08_MEM_FRM_DATA2_MEM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_FRM_DATA3
 ***************************************************************************/
/* switch :: PAGE_08_MEM_FRM_DATA3 :: PAGE_08_MEM_FRM_DATA3_MEM_DATA [63:00] */
#define Wr_switch_PAGE_08_MEM_FRM_DATA3_PAGE_08_MEM_FRM_DATA3_MEM_DATA(x) WriteReg(SWITCH_PAGE_08_MEM_FRM_DATA3,x)
#define Rd_switch_PAGE_08_MEM_FRM_DATA3_PAGE_08_MEM_FRM_DATA3_MEM_DATA(x) ReadReg(SWITCH_PAGE_08_MEM_FRM_DATA3)
#define SWITCH_PAGE_08_MEM_FRM_DATA3_PAGE_08_MEM_FRM_DATA3_MEM_DATA_MASK 0xffffffffffffffff
#define SWITCH_PAGE_08_MEM_FRM_DATA3_PAGE_08_MEM_FRM_DATA3_MEM_DATA_ALIGN 0
#define SWITCH_PAGE_08_MEM_FRM_DATA3_PAGE_08_MEM_FRM_DATA3_MEM_DATA_BITS 64
#define SWITCH_PAGE_08_MEM_FRM_DATA3_PAGE_08_MEM_FRM_DATA3_MEM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_BTM_DATA0
 ***************************************************************************/
/* switch :: PAGE_08_MEM_BTM_DATA0 :: PAGE_08_MEM_BTM_DATA0_MEM_DATA [63:00] */
#define Wr_switch_PAGE_08_MEM_BTM_DATA0_PAGE_08_MEM_BTM_DATA0_MEM_DATA(x) WriteReg(SWITCH_PAGE_08_MEM_BTM_DATA0,x)
#define Rd_switch_PAGE_08_MEM_BTM_DATA0_PAGE_08_MEM_BTM_DATA0_MEM_DATA(x) ReadReg(SWITCH_PAGE_08_MEM_BTM_DATA0)
#define SWITCH_PAGE_08_MEM_BTM_DATA0_PAGE_08_MEM_BTM_DATA0_MEM_DATA_MASK 0xffffffffffffffff
#define SWITCH_PAGE_08_MEM_BTM_DATA0_PAGE_08_MEM_BTM_DATA0_MEM_DATA_ALIGN 0
#define SWITCH_PAGE_08_MEM_BTM_DATA0_PAGE_08_MEM_BTM_DATA0_MEM_DATA_BITS 64
#define SWITCH_PAGE_08_MEM_BTM_DATA0_PAGE_08_MEM_BTM_DATA0_MEM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_BTM_DATA1
 ***************************************************************************/
/* switch :: PAGE_08_MEM_BTM_DATA1 :: reserved0 [63:48] */
#define SWITCH_PAGE_08_MEM_BTM_DATA1_RESERVED0_MASK                0xffff000000000000
#define SWITCH_PAGE_08_MEM_BTM_DATA1_RESERVED0_ALIGN               0
#define SWITCH_PAGE_08_MEM_BTM_DATA1_RESERVED0_BITS                16
#define SWITCH_PAGE_08_MEM_BTM_DATA1_RESERVED0_SHIFT               48

/* switch :: PAGE_08_MEM_BTM_DATA1 :: PAGE_08_MEM_BTM_DATA1_MEM_DATA [47:00] */
#define Wr_switch_PAGE_08_MEM_BTM_DATA1_PAGE_08_MEM_BTM_DATA1_MEM_DATA(x) WriteRegBits(SWITCH_PAGE_08_MEM_BTM_DATA1,0xffffffffffff,0,x)
#define Rd_switch_PAGE_08_MEM_BTM_DATA1_PAGE_08_MEM_BTM_DATA1_MEM_DATA(x) ReadRegBits(SWITCH_PAGE_08_MEM_BTM_DATA1,0xffffffffffff,0)
#define SWITCH_PAGE_08_MEM_BTM_DATA1_PAGE_08_MEM_BTM_DATA1_MEM_DATA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_08_MEM_BTM_DATA1_PAGE_08_MEM_BTM_DATA1_MEM_DATA_ALIGN 0
#define SWITCH_PAGE_08_MEM_BTM_DATA1_PAGE_08_MEM_BTM_DATA1_MEM_DATA_BITS 48
#define SWITCH_PAGE_08_MEM_BTM_DATA1_PAGE_08_MEM_BTM_DATA1_MEM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_BFC_ADDR
 ***************************************************************************/
/* switch :: PAGE_08_MEM_BFC_ADDR :: PAGE_08_MEM_BFC_ADDR_MEM_REQ [15:15] */
#define Wr_switch_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_MEM_REQ(x) WriteRegBits16(SWITCH_PAGE_08_MEM_BFC_ADDR,0x8000,15,x)
#define Rd_switch_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_MEM_REQ(x) ReadRegBits16(SWITCH_PAGE_08_MEM_BFC_ADDR,0x8000,15)
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_MEM_REQ_MASK 0x8000
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_MEM_REQ_ALIGN 0
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_MEM_REQ_BITS 1
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_MEM_REQ_SHIFT 15

/* switch :: PAGE_08_MEM_BFC_ADDR :: PAGE_08_MEM_BFC_ADDR_RW_CTRL [14:14] */
#define Wr_switch_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_RW_CTRL(x) WriteRegBits16(SWITCH_PAGE_08_MEM_BFC_ADDR,0x4000,14,x)
#define Rd_switch_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_RW_CTRL(x) ReadRegBits16(SWITCH_PAGE_08_MEM_BFC_ADDR,0x4000,14)
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_RW_CTRL_MASK 0x4000
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_RW_CTRL_ALIGN 0
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_RW_CTRL_BITS 1
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_RW_CTRL_SHIFT 14

/* switch :: PAGE_08_MEM_BFC_ADDR :: PAGE_08_MEM_BFC_ADDR_BFC_ADDR [13:00] */
#define Wr_switch_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_BFC_ADDR(x) WriteRegBits16(SWITCH_PAGE_08_MEM_BFC_ADDR,0x3fff,0,x)
#define Rd_switch_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_BFC_ADDR(x) ReadRegBits16(SWITCH_PAGE_08_MEM_BFC_ADDR,0x3fff,0)
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_BFC_ADDR_MASK 0x3fff
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_BFC_ADDR_ALIGN 0
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_BFC_ADDR_BITS 14
#define SWITCH_PAGE_08_MEM_BFC_ADDR_PAGE_08_MEM_BFC_ADDR_BFC_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_BFC_DATA
 ***************************************************************************/
/* switch :: PAGE_08_MEM_BFC_DATA :: PAGE_08_MEM_BFC_DATA_BFC_DATA [63:00] */
#define Wr_switch_PAGE_08_MEM_BFC_DATA_PAGE_08_MEM_BFC_DATA_BFC_DATA(x) WriteReg(SWITCH_PAGE_08_MEM_BFC_DATA,x)
#define Rd_switch_PAGE_08_MEM_BFC_DATA_PAGE_08_MEM_BFC_DATA_BFC_DATA(x) ReadReg(SWITCH_PAGE_08_MEM_BFC_DATA)
#define SWITCH_PAGE_08_MEM_BFC_DATA_PAGE_08_MEM_BFC_DATA_BFC_DATA_MASK 0xffffffffffffffff
#define SWITCH_PAGE_08_MEM_BFC_DATA_PAGE_08_MEM_BFC_DATA_BFC_DATA_ALIGN 0
#define SWITCH_PAGE_08_MEM_BFC_DATA_PAGE_08_MEM_BFC_DATA_BFC_DATA_BITS 64
#define SWITCH_PAGE_08_MEM_BFC_DATA_PAGE_08_MEM_BFC_DATA_BFC_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_PRS_FIFO_DEBUG_CTRL
 ***************************************************************************/
/* switch :: PAGE_08_PRS_FIFO_DEBUG_CTRL :: PAGE_08_PRS_FIFO_DEBUG_CTRL_RESERVED [07:04] */
#define Wr_switch_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL,0xf0,4,x)
#define Rd_switch_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL,0xf0,4)
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_RESERVED_MASK 0xf0
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_RESERVED_BITS 4
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_RESERVED_SHIFT 4

/* switch :: PAGE_08_PRS_FIFO_DEBUG_CTRL :: PAGE_08_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL [03:00] */
#define Wr_switch_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL(x) WriteRegBits(SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL,0xf,0,x)
#define Rd_switch_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL(x) ReadRegBits(SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL,0xf,0)
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_MASK 0x0f
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_ALIGN 0
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_BITS 4
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_CTRL_PAGE_08_PRS_FIFO_DEBUG_CTRL_PRS_FIFO_DBG_CTRL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_PRS_FIFO_DEBUG_DATA
 ***************************************************************************/
/* switch :: PAGE_08_PRS_FIFO_DEBUG_DATA :: PAGE_08_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA [63:00] */
#define Wr_switch_PAGE_08_PRS_FIFO_DEBUG_DATA_PAGE_08_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA(x) WriteReg(SWITCH_PAGE_08_PRS_FIFO_DEBUG_DATA,x)
#define Rd_switch_PAGE_08_PRS_FIFO_DEBUG_DATA_PAGE_08_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA(x) ReadReg(SWITCH_PAGE_08_PRS_FIFO_DEBUG_DATA)
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_DATA_PAGE_08_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_MASK 0xffffffffffffffff
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_DATA_PAGE_08_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_ALIGN 0
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_DATA_PAGE_08_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_BITS 64
#define SWITCH_PAGE_08_PRS_FIFO_DEBUG_DATA_PAGE_08_PRS_FIFO_DEBUG_DATA_PRS_FIFO_DBG_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_08_MEM_REG_SPARE0 :: PAGE_08_MEM_REG_SPARE0_MEM_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_08_MEM_REG_SPARE0_PAGE_08_MEM_REG_SPARE0_MEM_REG_SPARE0(x) WriteReg(SWITCH_PAGE_08_MEM_REG_SPARE0,x)
#define Rd_switch_PAGE_08_MEM_REG_SPARE0_PAGE_08_MEM_REG_SPARE0_MEM_REG_SPARE0(x) ReadReg(SWITCH_PAGE_08_MEM_REG_SPARE0)
#define SWITCH_PAGE_08_MEM_REG_SPARE0_PAGE_08_MEM_REG_SPARE0_MEM_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_08_MEM_REG_SPARE0_PAGE_08_MEM_REG_SPARE0_MEM_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_08_MEM_REG_SPARE0_PAGE_08_MEM_REG_SPARE0_MEM_REG_SPARE0_BITS 32
#define SWITCH_PAGE_08_MEM_REG_SPARE0_PAGE_08_MEM_REG_SPARE0_MEM_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_08_MEM_REG_SPARE1 :: PAGE_08_MEM_REG_SPARE1_MEM_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_08_MEM_REG_SPARE1_PAGE_08_MEM_REG_SPARE1_MEM_REG_SPARE1(x) WriteReg(SWITCH_PAGE_08_MEM_REG_SPARE1,x)
#define Rd_switch_PAGE_08_MEM_REG_SPARE1_PAGE_08_MEM_REG_SPARE1_MEM_REG_SPARE1(x) ReadReg(SWITCH_PAGE_08_MEM_REG_SPARE1)
#define SWITCH_PAGE_08_MEM_REG_SPARE1_PAGE_08_MEM_REG_SPARE1_MEM_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_08_MEM_REG_SPARE1_PAGE_08_MEM_REG_SPARE1_MEM_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_08_MEM_REG_SPARE1_PAGE_08_MEM_REG_SPARE1_MEM_REG_SPARE1_BITS 32
#define SWITCH_PAGE_08_MEM_REG_SPARE1_PAGE_08_MEM_REG_SPARE1_MEM_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_MISC_CTRL
 ***************************************************************************/
/* switch :: PAGE_08_MEM_MISC_CTRL :: PAGE_08_MEM_MISC_CTRL_RESERVED [31:05] */
#define Wr_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0xffffffe0,5,x)
#define Rd_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0xffffffe0,5)
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_RESERVED_MASK 0xffffffe0
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_RESERVED_BITS 27
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_RESERVED_SHIFT 5

/* switch :: PAGE_08_MEM_MISC_CTRL :: PAGE_08_MEM_MISC_CTRL_TXQ_DCM [04:04] */
#define Wr_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_TXQ_DCM(x) WriteRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x10,4,x)
#define Rd_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_TXQ_DCM(x) ReadRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x10,4)
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_TXQ_DCM_MASK 0x00000010
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_TXQ_DCM_ALIGN 0
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_TXQ_DCM_BITS 1
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_TXQ_DCM_SHIFT 4

/* switch :: PAGE_08_MEM_MISC_CTRL :: PAGE_08_MEM_MISC_CTRL_PB_DCM [03:03] */
#define Wr_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_PB_DCM(x) WriteRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x8,3,x)
#define Rd_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_PB_DCM(x) ReadRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x8,3)
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_PB_DCM_MASK 0x00000008
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_PB_DCM_ALIGN 0
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_PB_DCM_BITS 1
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_PB_DCM_SHIFT 3

/* switch :: PAGE_08_MEM_MISC_CTRL :: PAGE_08_MEM_MISC_CTRL_BT_DCM [02:02] */
#define Wr_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_BT_DCM(x) WriteRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x4,2,x)
#define Rd_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_BT_DCM(x) ReadRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x4,2)
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_BT_DCM_MASK 0x00000004
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_BT_DCM_ALIGN 0
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_BT_DCM_BITS 1
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_BT_DCM_SHIFT 2

/* switch :: PAGE_08_MEM_MISC_CTRL :: PAGE_08_MEM_MISC_CTRL_ARL_DCM [01:01] */
#define Wr_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_ARL_DCM(x) WriteRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x2,1,x)
#define Rd_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_ARL_DCM(x) ReadRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x2,1)
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_ARL_DCM_MASK 0x00000002
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_ARL_DCM_ALIGN 0
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_ARL_DCM_BITS 1
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_ARL_DCM_SHIFT 1

/* switch :: PAGE_08_MEM_MISC_CTRL :: PAGE_08_MEM_MISC_CTRL_CK_AON [00:00] */
#define Wr_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_CK_AON(x) WriteRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x1,0,x)
#define Rd_switch_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_CK_AON(x) ReadRegBits(SWITCH_PAGE_08_MEM_MISC_CTRL,0x1,0)
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_CK_AON_MASK 0x00000001
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_CK_AON_ALIGN 0
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_CK_AON_BITS 1
#define SWITCH_PAGE_08_MEM_MISC_CTRL_PAGE_08_MEM_MISC_CTRL_CK_AON_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_TEST_CTRL0
 ***************************************************************************/
/* switch :: PAGE_08_MEM_TEST_CTRL0 :: PAGE_08_MEM_TEST_CTRL0_RESERVED_0 [31:31] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x80000000,31,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x80000000,31)
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_0_MASK 0x80000000
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_0_BITS 1
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_0_SHIFT 31

/* switch :: PAGE_08_MEM_TEST_CTRL0 :: PAGE_08_MEM_TEST_CTRL0_RESERVED_1 [30:27] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x78000000,27,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x78000000,27)
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_1_MASK 0x78000000
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_1_BITS 4
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_1_SHIFT 27

/* switch :: PAGE_08_MEM_TEST_CTRL0 :: PAGE_08_MEM_TEST_CTRL0_VL_TM [26:17] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_VL_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x7fe0000,17,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_VL_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x7fe0000,17)
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_VL_TM_MASK 0x07fe0000
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_VL_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_VL_TM_BITS 10
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_VL_TM_SHIFT 17

/* switch :: PAGE_08_MEM_TEST_CTRL0 :: PAGE_08_MEM_TEST_CTRL0_RESERVED_2 [16:13] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x1e000,13,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x1e000,13)
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_2_MASK 0x0001e000
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_2_BITS 4
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_RESERVED_2_SHIFT 13

/* switch :: PAGE_08_MEM_TEST_CTRL0 :: PAGE_08_MEM_TEST_CTRL0_ARL_TM [12:00] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_ARL_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x1fff,0,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_ARL_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL0,0x1fff,0)
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_ARL_TM_MASK 0x00001fff
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_ARL_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_ARL_TM_BITS 13
#define SWITCH_PAGE_08_MEM_TEST_CTRL0_PAGE_08_MEM_TEST_CTRL0_ARL_TM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_TEST_CTRL1
 ***************************************************************************/
/* switch :: PAGE_08_MEM_TEST_CTRL1 :: PAGE_08_MEM_TEST_CTRL1_RESERVED_0 [31:31] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x80000000,31,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x80000000,31)
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_0_MASK 0x80000000
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_0_BITS 1
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_0_SHIFT 31

/* switch :: PAGE_08_MEM_TEST_CTRL1 :: PAGE_08_MEM_TEST_CTRL1_RESERVED_1 [30:27] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x78000000,27,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x78000000,27)
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_1_MASK 0x78000000
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_1_BITS 4
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_1_SHIFT 27

/* switch :: PAGE_08_MEM_TEST_CTRL1 :: PAGE_08_MEM_TEST_CTRL1_ACTRAT_TM [26:17] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_ACTRAT_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x7fe0000,17,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_ACTRAT_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x7fe0000,17)
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_ACTRAT_TM_MASK 0x07fe0000
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_ACTRAT_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_ACTRAT_TM_BITS 10
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_ACTRAT_TM_SHIFT 17

/* switch :: PAGE_08_MEM_TEST_CTRL1 :: PAGE_08_MEM_TEST_CTRL1_RESERVED_2 [16:13] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x1e000,13,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x1e000,13)
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_2_MASK 0x0001e000
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_2_BITS 4
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_RESERVED_2_SHIFT 13

/* switch :: PAGE_08_MEM_TEST_CTRL1 :: PAGE_08_MEM_TEST_CTRL1_BT_TM [12:00] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_BT_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x1fff,0,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_BT_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL1,0x1fff,0)
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_BT_TM_MASK 0x00001fff
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_BT_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_BT_TM_BITS 13
#define SWITCH_PAGE_08_MEM_TEST_CTRL1_PAGE_08_MEM_TEST_CTRL1_BT_TM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_TEST_CTRL2
 ***************************************************************************/
/* switch :: PAGE_08_MEM_TEST_CTRL2 :: PAGE_08_MEM_TEST_CTRL2_RESERVED_0 [31:31] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x80000000,31,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x80000000,31)
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_0_MASK 0x80000000
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_0_BITS 1
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_0_SHIFT 31

/* switch :: PAGE_08_MEM_TEST_CTRL2 :: PAGE_08_MEM_TEST_CTRL2_RESERVED_1 [30:27] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x78000000,27,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x78000000,27)
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_1_MASK 0x78000000
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_1_BITS 4
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_1_SHIFT 27

/* switch :: PAGE_08_MEM_TEST_CTRL2 :: PAGE_08_MEM_TEST_CTRL2_STS_TM [26:17] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_STS_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x7fe0000,17,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_STS_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x7fe0000,17)
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_STS_TM_MASK 0x07fe0000
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_STS_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_STS_TM_BITS 10
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_STS_TM_SHIFT 17

/* switch :: PAGE_08_MEM_TEST_CTRL2 :: PAGE_08_MEM_TEST_CTRL2_RESERVED_2 [16:13] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x1e000,13,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x1e000,13)
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_2_MASK 0x0001e000
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_2_BITS 4
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_RESERVED_2_SHIFT 13

/* switch :: PAGE_08_MEM_TEST_CTRL2 :: PAGE_08_MEM_TEST_CTRL2_PB_TM [12:00] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_PB_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x1fff,0,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_PB_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL2,0x1fff,0)
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_PB_TM_MASK 0x00001fff
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_PB_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_PB_TM_BITS 13
#define SWITCH_PAGE_08_MEM_TEST_CTRL2_PAGE_08_MEM_TEST_CTRL2_PB_TM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_TEST_CTRL3
 ***************************************************************************/
/* switch :: PAGE_08_MEM_TEST_CTRL3 :: PAGE_08_MEM_TEST_CTRL3_RESERVED_0 [31:31] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x80000000,31,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x80000000,31)
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_0_MASK 0x80000000
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_0_BITS 1
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_0_SHIFT 31

/* switch :: PAGE_08_MEM_TEST_CTRL3 :: PAGE_08_MEM_TEST_CTRL3_RESERVED_1 [30:27] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x78000000,27,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x78000000,27)
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_1_MASK 0x78000000
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_1_BITS 4
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_1_SHIFT 27

/* switch :: PAGE_08_MEM_TEST_CTRL3 :: PAGE_08_MEM_TEST_CTRL3_EVT_TM [26:17] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_EVT_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x7fe0000,17,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_EVT_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x7fe0000,17)
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_EVT_TM_MASK 0x07fe0000
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_EVT_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_EVT_TM_BITS 10
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_EVT_TM_SHIFT 17

/* switch :: PAGE_08_MEM_TEST_CTRL3 :: PAGE_08_MEM_TEST_CTRL3_RESERVED_2 [16:13] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x1e000,13,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x1e000,13)
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_2_MASK 0x0001e000
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_2_BITS 4
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_RESERVED_2_SHIFT 13

/* switch :: PAGE_08_MEM_TEST_CTRL3 :: PAGE_08_MEM_TEST_CTRL3_TXQ_TM [12:00] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_TXQ_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x1fff,0,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_TXQ_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL3,0x1fff,0)
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_TXQ_TM_MASK 0x00001fff
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_TXQ_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_TXQ_TM_BITS 13
#define SWITCH_PAGE_08_MEM_TEST_CTRL3_PAGE_08_MEM_TEST_CTRL3_TXQ_TM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_TEST_CTRL4
 ***************************************************************************/
/* switch :: PAGE_08_MEM_TEST_CTRL4 :: PAGE_08_MEM_TEST_CTRL4_ARL_TCAM_TM [31:16] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_ARL_TCAM_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL4,0xffff0000,16,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_ARL_TCAM_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL4,0xffff0000,16)
#define SWITCH_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_ARL_TCAM_TM_MASK 0xffff0000
#define SWITCH_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_ARL_TCAM_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_ARL_TCAM_TM_BITS 16
#define SWITCH_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_ARL_TCAM_TM_SHIFT 16

/* switch :: PAGE_08_MEM_TEST_CTRL4 :: PAGE_08_MEM_TEST_CTRL4_TCAM_TM [15:00] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_TCAM_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL4,0xffff,0,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_TCAM_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL4,0xffff,0)
#define SWITCH_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_TCAM_TM_MASK 0x0000ffff
#define SWITCH_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_TCAM_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_TCAM_TM_BITS 16
#define SWITCH_PAGE_08_MEM_TEST_CTRL4_PAGE_08_MEM_TEST_CTRL4_TCAM_TM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_TEST_CTRL5
 ***************************************************************************/
/* switch :: PAGE_08_MEM_TEST_CTRL5 :: PAGE_08_MEM_TEST_CTRL5_RESERVED_2 [31:30] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0xc0000000,30,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0xc0000000,30)
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_2_MASK 0xc0000000
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_2_BITS 2
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_2_SHIFT 30

/* switch :: PAGE_08_MEM_TEST_CTRL5 :: PAGE_08_MEM_TEST_CTRL5_RESERVED_1 [29:23] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0x3f800000,23,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0x3f800000,23)
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_1_MASK 0x3f800000
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_1_BITS 7
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_1_SHIFT 23

/* switch :: PAGE_08_MEM_TEST_CTRL5 :: PAGE_08_MEM_TEST_CTRL5_TCAM_CHKSUM_TM [22:16] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_TCAM_CHKSUM_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0x7f0000,16,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_TCAM_CHKSUM_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0x7f0000,16)
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_TCAM_CHKSUM_TM_MASK 0x007f0000
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_TCAM_CHKSUM_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_TCAM_CHKSUM_TM_BITS 7
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_TCAM_CHKSUM_TM_SHIFT 16

/* switch :: PAGE_08_MEM_TEST_CTRL5 :: PAGE_08_MEM_TEST_CTRL5_ARL_SEC_TM [15:06] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_ARL_SEC_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0xffc0,6,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_ARL_SEC_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0xffc0,6)
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_ARL_SEC_TM_MASK 0x0000ffc0
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_ARL_SEC_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_ARL_SEC_TM_BITS 10
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_ARL_SEC_TM_SHIFT 6

/* switch :: PAGE_08_MEM_TEST_CTRL5 :: PAGE_08_MEM_TEST_CTRL5_RESERVED_0 [05:03] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0x38,3,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0x38,3)
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_0_MASK 0x00000038
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_0_BITS 3
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_RESERVED_0_SHIFT 3

/* switch :: PAGE_08_MEM_TEST_CTRL5 :: PAGE_08_MEM_TEST_CTRL5_MIB_TM [02:00] */
#define Wr_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_MIB_TM(x) WriteRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0x7,0,x)
#define Rd_switch_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_MIB_TM(x) ReadRegBits(SWITCH_PAGE_08_MEM_TEST_CTRL5,0x7,0)
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_MIB_TM_MASK 0x00000007
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_MIB_TM_ALIGN 0
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_MIB_TM_BITS 3
#define SWITCH_PAGE_08_MEM_TEST_CTRL5_PAGE_08_MEM_TEST_CTRL5_MIB_TM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_08_MEM_PSM_VDD_CTRL
 ***************************************************************************/
/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED [31:22] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0xffc00000,22,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0xffc00000,22)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_MASK 0xffc00000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_BITS 10
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_SHIFT 22

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_21 [21:21] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_21(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x200000,21,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_21(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x200000,21)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_21_MASK 0x00200000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_21_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_21_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_21_SHIFT 21

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_STS_PDA [20:20] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_STS_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x100000,20,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_STS_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x100000,20)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_STS_PDA_MASK 0x00100000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_STS_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_STS_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_STS_PDA_SHIFT 20

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_19 [19:19] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_19(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x80000,19,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_19(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x80000,19)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_19_MASK 0x00080000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_19_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_19_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_19_SHIFT 19

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_ACTRAT_PDA [18:18] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_ACTRAT_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x40000,18,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_ACTRAT_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x40000,18)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_ACTRAT_PDA_MASK 0x00040000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_ACTRAT_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_ACTRAT_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_ACTRAT_PDA_SHIFT 18

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_17 [17:17] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_17(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x20000,17,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_17(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x20000,17)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_17_MASK 0x00020000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_17_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_17_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_17_SHIFT 17

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_IMP_TXQ_PDA [16:16] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_IMP_TXQ_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x10000,16,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_IMP_TXQ_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x10000,16)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_IMP_TXQ_PDA_MASK 0x00010000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_IMP_TXQ_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_IMP_TXQ_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_IMP_TXQ_PDA_SHIFT 16

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_15 [15:15] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_15(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x8000,15,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_15(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x8000,15)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_15_MASK 0x00008000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_15_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_15_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_15_SHIFT 15

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_P7_TXQ_PDA [14:14] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P7_TXQ_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x4000,14,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P7_TXQ_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x4000,14)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P7_TXQ_PDA_MASK 0x00004000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P7_TXQ_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P7_TXQ_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P7_TXQ_PDA_SHIFT 14

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_13 [13:13] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_13(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x2000,13,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_13(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x2000,13)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_13_MASK 0x00002000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_13_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_13_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_13_SHIFT 13

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_P6_TXQ_PDA [12:12] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P6_TXQ_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x1000,12,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P6_TXQ_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x1000,12)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P6_TXQ_PDA_MASK 0x00001000
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P6_TXQ_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P6_TXQ_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P6_TXQ_PDA_SHIFT 12

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_11 [11:11] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_11(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x800,11,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_11(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x800,11)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_11_MASK 0x00000800
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_11_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_11_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_11_SHIFT 11

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_P5_TXQ_PDA [10:10] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P5_TXQ_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x400,10,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P5_TXQ_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x400,10)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P5_TXQ_PDA_MASK 0x00000400
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P5_TXQ_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P5_TXQ_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P5_TXQ_PDA_SHIFT 10

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_9 [09:09] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_9(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x200,9,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_9(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x200,9)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_9_MASK 0x00000200
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_9_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_9_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_9_SHIFT 9

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_P4_TXQ_PDA [08:08] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P4_TXQ_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x100,8,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P4_TXQ_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x100,8)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P4_TXQ_PDA_MASK 0x00000100
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P4_TXQ_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P4_TXQ_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P4_TXQ_PDA_SHIFT 8

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_7 [07:07] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_7(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x80,7,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_7(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x80,7)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_7_MASK 0x00000080
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_7_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_7_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_7_SHIFT 7

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_P3_TXQ_PDA [06:06] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P3_TXQ_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x40,6,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P3_TXQ_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x40,6)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P3_TXQ_PDA_MASK 0x00000040
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P3_TXQ_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P3_TXQ_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P3_TXQ_PDA_SHIFT 6

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_5 [05:05] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x20,5,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x20,5)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_5_MASK 0x00000020
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_5_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_5_SHIFT 5

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_P2_TXQ_PDA [04:04] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P2_TXQ_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x10,4,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P2_TXQ_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x10,4)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P2_TXQ_PDA_MASK 0x00000010
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P2_TXQ_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P2_TXQ_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P2_TXQ_PDA_SHIFT 4

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_3 [03:03] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x8,3,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x8,3)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_3_MASK 0x00000008
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_3_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_3_SHIFT 3

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_P1_TXQ_PDA [02:02] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P1_TXQ_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x4,2,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P1_TXQ_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x4,2)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P1_TXQ_PDA_MASK 0x00000004
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P1_TXQ_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P1_TXQ_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P1_TXQ_PDA_SHIFT 2

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_1 [01:01] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x2,1,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x2,1)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_1_MASK 0x00000002
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_1_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_RESERVED_1_SHIFT 1

/* switch :: PAGE_08_MEM_PSM_VDD_CTRL :: PAGE_08_MEM_PSM_VDD_CTRL_P0_TXQ_PDA [00:00] */
#define Wr_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P0_TXQ_PDA(x) WriteRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x1,0,x)
#define Rd_switch_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P0_TXQ_PDA(x) ReadRegBits(SWITCH_PAGE_08_MEM_PSM_VDD_CTRL,0x1,0)
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P0_TXQ_PDA_MASK 0x00000001
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P0_TXQ_PDA_ALIGN 0
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P0_TXQ_PDA_BITS 1
#define SWITCH_PAGE_08_MEM_PSM_VDD_CTRL_PAGE_08_MEM_PSM_VDD_CTRL_P0_TXQ_PDA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_09_PORT0_DEBUG
 ***************************************************************************/
/* switch :: PAGE_09_PORT0_DEBUG :: PAGE_09_PORT0_DEBUG_RESERVED [31:00] */
#define Wr_switch_PAGE_09_PORT0_DEBUG_PAGE_09_PORT0_DEBUG_RESERVED(x) WriteReg(SWITCH_PAGE_09_PORT0_DEBUG,x)
#define Rd_switch_PAGE_09_PORT0_DEBUG_PAGE_09_PORT0_DEBUG_RESERVED(x) ReadReg(SWITCH_PAGE_09_PORT0_DEBUG)
#define SWITCH_PAGE_09_PORT0_DEBUG_PAGE_09_PORT0_DEBUG_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_09_PORT0_DEBUG_PAGE_09_PORT0_DEBUG_RESERVED_ALIGN 0
#define SWITCH_PAGE_09_PORT0_DEBUG_PAGE_09_PORT0_DEBUG_RESERVED_BITS 32
#define SWITCH_PAGE_09_PORT0_DEBUG_PAGE_09_PORT0_DEBUG_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_09_PORT1_DEBUG
 ***************************************************************************/
/* switch :: PAGE_09_PORT1_DEBUG :: PAGE_09_PORT1_DEBUG_RESERVED [31:00] */
#define Wr_switch_PAGE_09_PORT1_DEBUG_PAGE_09_PORT1_DEBUG_RESERVED(x) WriteReg(SWITCH_PAGE_09_PORT1_DEBUG,x)
#define Rd_switch_PAGE_09_PORT1_DEBUG_PAGE_09_PORT1_DEBUG_RESERVED(x) ReadReg(SWITCH_PAGE_09_PORT1_DEBUG)
#define SWITCH_PAGE_09_PORT1_DEBUG_PAGE_09_PORT1_DEBUG_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_09_PORT1_DEBUG_PAGE_09_PORT1_DEBUG_RESERVED_ALIGN 0
#define SWITCH_PAGE_09_PORT1_DEBUG_PAGE_09_PORT1_DEBUG_RESERVED_BITS 32
#define SWITCH_PAGE_09_PORT1_DEBUG_PAGE_09_PORT1_DEBUG_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_09_PORT2_DEBUG
 ***************************************************************************/
/* switch :: PAGE_09_PORT2_DEBUG :: PAGE_09_PORT2_DEBUG_RESERVED [31:00] */
#define Wr_switch_PAGE_09_PORT2_DEBUG_PAGE_09_PORT2_DEBUG_RESERVED(x) WriteReg(SWITCH_PAGE_09_PORT2_DEBUG,x)
#define Rd_switch_PAGE_09_PORT2_DEBUG_PAGE_09_PORT2_DEBUG_RESERVED(x) ReadReg(SWITCH_PAGE_09_PORT2_DEBUG)
#define SWITCH_PAGE_09_PORT2_DEBUG_PAGE_09_PORT2_DEBUG_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_09_PORT2_DEBUG_PAGE_09_PORT2_DEBUG_RESERVED_ALIGN 0
#define SWITCH_PAGE_09_PORT2_DEBUG_PAGE_09_PORT2_DEBUG_RESERVED_BITS 32
#define SWITCH_PAGE_09_PORT2_DEBUG_PAGE_09_PORT2_DEBUG_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_09_PORT3_DEBUG
 ***************************************************************************/
/* switch :: PAGE_09_PORT3_DEBUG :: PAGE_09_PORT3_DEBUG_RESERVED [31:00] */
#define Wr_switch_PAGE_09_PORT3_DEBUG_PAGE_09_PORT3_DEBUG_RESERVED(x) WriteReg(SWITCH_PAGE_09_PORT3_DEBUG,x)
#define Rd_switch_PAGE_09_PORT3_DEBUG_PAGE_09_PORT3_DEBUG_RESERVED(x) ReadReg(SWITCH_PAGE_09_PORT3_DEBUG)
#define SWITCH_PAGE_09_PORT3_DEBUG_PAGE_09_PORT3_DEBUG_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_09_PORT3_DEBUG_PAGE_09_PORT3_DEBUG_RESERVED_ALIGN 0
#define SWITCH_PAGE_09_PORT3_DEBUG_PAGE_09_PORT3_DEBUG_RESERVED_BITS 32
#define SWITCH_PAGE_09_PORT3_DEBUG_PAGE_09_PORT3_DEBUG_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_09_PORT4_DEBUG
 ***************************************************************************/
/* switch :: PAGE_09_PORT4_DEBUG :: PAGE_09_PORT4_DEBUG_RESERVED [31:00] */
#define Wr_switch_PAGE_09_PORT4_DEBUG_PAGE_09_PORT4_DEBUG_RESERVED(x) WriteReg(SWITCH_PAGE_09_PORT4_DEBUG,x)
#define Rd_switch_PAGE_09_PORT4_DEBUG_PAGE_09_PORT4_DEBUG_RESERVED(x) ReadReg(SWITCH_PAGE_09_PORT4_DEBUG)
#define SWITCH_PAGE_09_PORT4_DEBUG_PAGE_09_PORT4_DEBUG_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_09_PORT4_DEBUG_PAGE_09_PORT4_DEBUG_RESERVED_ALIGN 0
#define SWITCH_PAGE_09_PORT4_DEBUG_PAGE_09_PORT4_DEBUG_RESERVED_BITS 32
#define SWITCH_PAGE_09_PORT4_DEBUG_PAGE_09_PORT4_DEBUG_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_09_PORT5_DEBUG
 ***************************************************************************/
/* switch :: PAGE_09_PORT5_DEBUG :: PAGE_09_PORT5_DEBUG_RESERVED [31:00] */
#define Wr_switch_PAGE_09_PORT5_DEBUG_PAGE_09_PORT5_DEBUG_RESERVED(x) WriteReg(SWITCH_PAGE_09_PORT5_DEBUG,x)
#define Rd_switch_PAGE_09_PORT5_DEBUG_PAGE_09_PORT5_DEBUG_RESERVED(x) ReadReg(SWITCH_PAGE_09_PORT5_DEBUG)
#define SWITCH_PAGE_09_PORT5_DEBUG_PAGE_09_PORT5_DEBUG_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_09_PORT5_DEBUG_PAGE_09_PORT5_DEBUG_RESERVED_ALIGN 0
#define SWITCH_PAGE_09_PORT5_DEBUG_PAGE_09_PORT5_DEBUG_RESERVED_BITS 32
#define SWITCH_PAGE_09_PORT5_DEBUG_PAGE_09_PORT5_DEBUG_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_09_PORT6_DEBUG
 ***************************************************************************/
/* switch :: PAGE_09_PORT6_DEBUG :: PAGE_09_PORT6_DEBUG_RESERVED [31:00] */
#define Wr_switch_PAGE_09_PORT6_DEBUG_PAGE_09_PORT6_DEBUG_RESERVED(x) WriteReg(SWITCH_PAGE_09_PORT6_DEBUG,x)
#define Rd_switch_PAGE_09_PORT6_DEBUG_PAGE_09_PORT6_DEBUG_RESERVED(x) ReadReg(SWITCH_PAGE_09_PORT6_DEBUG)
#define SWITCH_PAGE_09_PORT6_DEBUG_PAGE_09_PORT6_DEBUG_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_09_PORT6_DEBUG_PAGE_09_PORT6_DEBUG_RESERVED_ALIGN 0
#define SWITCH_PAGE_09_PORT6_DEBUG_PAGE_09_PORT6_DEBUG_RESERVED_BITS 32
#define SWITCH_PAGE_09_PORT6_DEBUG_PAGE_09_PORT6_DEBUG_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_09_PORT7_DEBUG
 ***************************************************************************/
/* switch :: PAGE_09_PORT7_DEBUG :: PAGE_09_PORT7_DEBUG_RESERVED [31:00] */
#define Wr_switch_PAGE_09_PORT7_DEBUG_PAGE_09_PORT7_DEBUG_RESERVED(x) WriteReg(SWITCH_PAGE_09_PORT7_DEBUG,x)
#define Rd_switch_PAGE_09_PORT7_DEBUG_PAGE_09_PORT7_DEBUG_RESERVED(x) ReadReg(SWITCH_PAGE_09_PORT7_DEBUG)
#define SWITCH_PAGE_09_PORT7_DEBUG_PAGE_09_PORT7_DEBUG_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_09_PORT7_DEBUG_PAGE_09_PORT7_DEBUG_RESERVED_ALIGN 0
#define SWITCH_PAGE_09_PORT7_DEBUG_PAGE_09_PORT7_DEBUG_RESERVED_BITS 32
#define SWITCH_PAGE_09_PORT7_DEBUG_PAGE_09_PORT7_DEBUG_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_09_PORT8_DEBUG
 ***************************************************************************/
/* switch :: PAGE_09_PORT8_DEBUG :: PAGE_09_PORT8_DEBUG_RESERVED [31:00] */
#define Wr_switch_PAGE_09_PORT8_DEBUG_PAGE_09_PORT8_DEBUG_RESERVED(x) WriteReg(SWITCH_PAGE_09_PORT8_DEBUG,x)
#define Rd_switch_PAGE_09_PORT8_DEBUG_PAGE_09_PORT8_DEBUG_RESERVED(x) ReadReg(SWITCH_PAGE_09_PORT8_DEBUG)
#define SWITCH_PAGE_09_PORT8_DEBUG_PAGE_09_PORT8_DEBUG_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_09_PORT8_DEBUG_PAGE_09_PORT8_DEBUG_RESERVED_ALIGN 0
#define SWITCH_PAGE_09_PORT8_DEBUG_PAGE_09_PORT8_DEBUG_RESERVED_BITS 32
#define SWITCH_PAGE_09_PORT8_DEBUG_PAGE_09_PORT8_DEBUG_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_DIAG_CTRL
 ***************************************************************************/
/* switch :: PAGE_0A_FC_DIAG_CTRL :: PAGE_0A_FC_DIAG_CTRL_RESERVED [15:04] */
#define Wr_switch_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_DIAG_CTRL,0xfff0,4,x)
#define Rd_switch_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_DIAG_CTRL,0xfff0,4)
#define SWITCH_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_RESERVED_MASK 0xfff0
#define SWITCH_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_RESERVED_BITS 12
#define SWITCH_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_RESERVED_SHIFT 4

/* switch :: PAGE_0A_FC_DIAG_CTRL :: PAGE_0A_FC_DIAG_CTRL_DIAG_FLOWCON_PORT [03:00] */
#define Wr_switch_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_DIAG_FLOWCON_PORT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_DIAG_CTRL,0xf,0,x)
#define Rd_switch_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_DIAG_FLOWCON_PORT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_DIAG_CTRL,0xf,0)
#define SWITCH_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_MASK 0x000f
#define SWITCH_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_ALIGN 0
#define SWITCH_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_BITS 4
#define SWITCH_PAGE_0A_FC_DIAG_CTRL_PAGE_0A_FC_DIAG_CTRL_DIAG_FLOWCON_PORT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CTRL_MODE
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CTRL_MODE :: PAGE_0A_FC_CTRL_MODE_RESERVED [07:01] */
#define Wr_switch_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_RESERVED(x) WriteRegBits(SWITCH_PAGE_0A_FC_CTRL_MODE,0xfe,1,x)
#define Rd_switch_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_RESERVED(x) ReadRegBits(SWITCH_PAGE_0A_FC_CTRL_MODE,0xfe,1)
#define SWITCH_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_RESERVED_MASK 0xfe
#define SWITCH_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_RESERVED_SHIFT 1

/* switch :: PAGE_0A_FC_CTRL_MODE :: PAGE_0A_FC_CTRL_MODE_FC_MODE [00:00] */
#define Wr_switch_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_FC_MODE(x) WriteRegBits(SWITCH_PAGE_0A_FC_CTRL_MODE,0x1,0,x)
#define Rd_switch_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_FC_MODE(x) ReadRegBits(SWITCH_PAGE_0A_FC_CTRL_MODE,0x1,0)
#define SWITCH_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_FC_MODE_MASK 0x01
#define SWITCH_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_FC_MODE_ALIGN 0
#define SWITCH_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_FC_MODE_BITS 1
#define SWITCH_PAGE_0A_FC_CTRL_MODE_PAGE_0A_FC_CTRL_MODE_FC_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CTRL_PORT
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CTRL_PORT :: PAGE_0A_FC_CTRL_PORT_RESERVED [07:04] */
#define Wr_switch_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_RESERVED(x) WriteRegBits(SWITCH_PAGE_0A_FC_CTRL_PORT,0xf0,4,x)
#define Rd_switch_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_RESERVED(x) ReadRegBits(SWITCH_PAGE_0A_FC_CTRL_PORT,0xf0,4)
#define SWITCH_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_RESERVED_MASK 0xf0
#define SWITCH_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_RESERVED_BITS 4
#define SWITCH_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_RESERVED_SHIFT 4

/* switch :: PAGE_0A_FC_CTRL_PORT :: PAGE_0A_FC_CTRL_PORT_FC_PORT_SEL [03:00] */
#define Wr_switch_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_FC_PORT_SEL(x) WriteRegBits(SWITCH_PAGE_0A_FC_CTRL_PORT,0xf,0,x)
#define Rd_switch_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_FC_PORT_SEL(x) ReadRegBits(SWITCH_PAGE_0A_FC_CTRL_PORT,0xf,0)
#define SWITCH_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_FC_PORT_SEL_MASK 0x0f
#define SWITCH_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_FC_PORT_SEL_ALIGN 0
#define SWITCH_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_FC_PORT_SEL_BITS 4
#define SWITCH_PAGE_0A_FC_CTRL_PORT_PAGE_0A_FC_CTRL_PORT_FC_PORT_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_OOB_PAUSE_EN
 ***************************************************************************/
/* switch :: PAGE_0A_FC_OOB_PAUSE_EN :: PAGE_0A_FC_OOB_PAUSE_EN_RESERVED [15:09] */
#define Wr_switch_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_OOB_PAUSE_EN,0xfe00,9,x)
#define Rd_switch_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_OOB_PAUSE_EN,0xfe00,9)
#define SWITCH_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_RESERVED_BITS 7
#define SWITCH_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_RESERVED_SHIFT 9

/* switch :: PAGE_0A_FC_OOB_PAUSE_EN :: PAGE_0A_FC_OOB_PAUSE_EN_OOB_PAUSE_EN [08:00] */
#define Wr_switch_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_OOB_PAUSE_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_OOB_PAUSE_EN,0x1ff,0,x)
#define Rd_switch_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_OOB_PAUSE_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_OOB_PAUSE_EN,0x1ff,0)
#define SWITCH_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_MASK 0x01ff
#define SWITCH_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_BITS 9
#define SWITCH_PAGE_0A_FC_OOB_PAUSE_EN_PAGE_0A_FC_OOB_PAUSE_EN_OOB_PAUSE_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_PAUSE_TIME_MAX
 ***************************************************************************/
/* switch :: PAGE_0A_PAUSE_TIME_MAX :: PAGE_0A_PAUSE_TIME_MAX_PAUSE_TIME_MAX [15:00] */
#define Wr_switch_PAGE_0A_PAUSE_TIME_MAX_PAGE_0A_PAUSE_TIME_MAX_PAUSE_TIME_MAX(x) WriteReg16(SWITCH_PAGE_0A_PAUSE_TIME_MAX,x)
#define Rd_switch_PAGE_0A_PAUSE_TIME_MAX_PAGE_0A_PAUSE_TIME_MAX_PAUSE_TIME_MAX(x) ReadReg16(SWITCH_PAGE_0A_PAUSE_TIME_MAX)
#define SWITCH_PAGE_0A_PAUSE_TIME_MAX_PAGE_0A_PAUSE_TIME_MAX_PAUSE_TIME_MAX_MASK 0xffff
#define SWITCH_PAGE_0A_PAUSE_TIME_MAX_PAGE_0A_PAUSE_TIME_MAX_PAUSE_TIME_MAX_ALIGN 0
#define SWITCH_PAGE_0A_PAUSE_TIME_MAX_PAGE_0A_PAUSE_TIME_MAX_PAUSE_TIME_MAX_BITS 16
#define SWITCH_PAGE_0A_PAUSE_TIME_MAX_PAGE_0A_PAUSE_TIME_MAX_PAUSE_TIME_MAX_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_PAUSE_TIME_MIN
 ***************************************************************************/
/* switch :: PAGE_0A_PAUSE_TIME_MIN :: PAGE_0A_PAUSE_TIME_MIN_PAUSE_TIME_MIN [15:00] */
#define Wr_switch_PAGE_0A_PAUSE_TIME_MIN_PAGE_0A_PAUSE_TIME_MIN_PAUSE_TIME_MIN(x) WriteReg16(SWITCH_PAGE_0A_PAUSE_TIME_MIN,x)
#define Rd_switch_PAGE_0A_PAUSE_TIME_MIN_PAGE_0A_PAUSE_TIME_MIN_PAUSE_TIME_MIN(x) ReadReg16(SWITCH_PAGE_0A_PAUSE_TIME_MIN)
#define SWITCH_PAGE_0A_PAUSE_TIME_MIN_PAGE_0A_PAUSE_TIME_MIN_PAUSE_TIME_MIN_MASK 0xffff
#define SWITCH_PAGE_0A_PAUSE_TIME_MIN_PAGE_0A_PAUSE_TIME_MIN_PAUSE_TIME_MIN_ALIGN 0
#define SWITCH_PAGE_0A_PAUSE_TIME_MIN_PAGE_0A_PAUSE_TIME_MIN_PAUSE_TIME_MIN_BITS 16
#define SWITCH_PAGE_0A_PAUSE_TIME_MIN_PAGE_0A_PAUSE_TIME_MIN_PAUSE_TIME_MIN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_PAUSE_TIME_RESET_THD
 ***************************************************************************/
/* switch :: PAGE_0A_PAUSE_TIME_RESET_THD :: PAGE_0A_PAUSE_TIME_RESET_THD_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD,0xf800,11,x)
#define Rd_switch_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD,0xf800,11)
#define SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_RESERVED_BITS 5
#define SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_RESERVED_SHIFT 11

/* switch :: PAGE_0A_PAUSE_TIME_RESET_THD :: PAGE_0A_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD [10:00] */
#define Wr_switch_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD(x) WriteRegBits16(SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD,0x7ff,0,x)
#define Rd_switch_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD(x) ReadRegBits16(SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD,0x7ff,0)
#define SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_MASK 0x07ff
#define SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_ALIGN 0
#define SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_BITS 11
#define SWITCH_PAGE_0A_PAUSE_TIME_RESET_THD_PAGE_0A_PAUSE_TIME_RESET_THD_PAUSE_TIME_RESET_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_PAUSE_TIME_UPDATE_PERIOD
 ***************************************************************************/
/* switch :: PAGE_0A_PAUSE_TIME_UPDATE_PERIOD :: PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD [15:00] */
#define Wr_switch_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD(x) WriteReg16(SWITCH_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD,x)
#define Rd_switch_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD(x) ReadReg16(SWITCH_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD)
#define SWITCH_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_MASK 0xffff
#define SWITCH_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_ALIGN 0
#define SWITCH_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_BITS 16
#define SWITCH_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAGE_0A_PAUSE_TIME_UPDATE_PERIOD_PAUSE_TIME_UPDATE_PERIOD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_PAUSE_TIME_DEFAULT
 ***************************************************************************/
/* switch :: PAGE_0A_PAUSE_TIME_DEFAULT :: PAGE_0A_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT [15:00] */
#define Wr_switch_PAGE_0A_PAUSE_TIME_DEFAULT_PAGE_0A_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT(x) WriteReg16(SWITCH_PAGE_0A_PAUSE_TIME_DEFAULT,x)
#define Rd_switch_PAGE_0A_PAUSE_TIME_DEFAULT_PAGE_0A_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT(x) ReadReg16(SWITCH_PAGE_0A_PAUSE_TIME_DEFAULT)
#define SWITCH_PAGE_0A_PAUSE_TIME_DEFAULT_PAGE_0A_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_MASK 0xffff
#define SWITCH_PAGE_0A_PAUSE_TIME_DEFAULT_PAGE_0A_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_ALIGN 0
#define SWITCH_PAGE_0A_PAUSE_TIME_DEFAULT_PAGE_0A_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_BITS 16
#define SWITCH_PAGE_0A_PAUSE_TIME_DEFAULT_PAGE_0A_PAUSE_TIME_DEFAULT_PAUSE_TIME_DEFAULT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_MCAST_DROP_CTRL
 ***************************************************************************/
/* switch :: PAGE_0A_FC_MCAST_DROP_CTRL :: PAGE_0A_FC_MCAST_DROP_CTRL_RESERVED [15:09] */
#define Wr_switch_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL,0xfe00,9,x)
#define Rd_switch_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL,0xfe00,9)
#define SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_RESERVED_BITS 7
#define SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_RESERVED_SHIFT 9

/* switch :: PAGE_0A_FC_MCAST_DROP_CTRL :: PAGE_0A_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN [08:00] */
#define Wr_switch_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL,0x1ff,0,x)
#define Rd_switch_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL,0x1ff,0)
#define SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_MASK 0x01ff
#define SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_BITS 9
#define SWITCH_PAGE_0A_FC_MCAST_DROP_CTRL_PAGE_0A_FC_MCAST_DROP_CTRL_MCAST_PARTIAL_DROP_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PAUSE_DROP_CTRL
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_RESERVED [15:13] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0xe000,13,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0xe000,13)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RESERVED_MASK 0xe000
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RESERVED_BITS 3
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RESERVED_SHIFT 13

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN [12:12] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x1000,12,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x1000,12)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_MASK 0x1000
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_QUEUE_BASED_PAUSE_EN_SHIFT 12

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN [11:11] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x800,11,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x800,11)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_MASK 0x0800
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TOTAL_PAUSE_EN_SHIFT 11

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN [10:10] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x400,10,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x400,10)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_MASK 0x0400
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP0_TXQ_PAUSE_EN_SHIFT 10

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN [09:09] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x200,9,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x200,9)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_MASK 0x0200
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TOTAL_PAUSE_EN_SHIFT 9

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN [08:08] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x100,8,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x100,8)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_MASK 0x0100
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_IMP1_TXQ_PAUSE_EN_SHIFT 8

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN [07:07] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x80,7,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x80,7)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_MASK 0x0080
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_PAUSE_EN_SHIFT 7

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN [06:06] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x40,6,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x40,6)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_MASK 0x0040
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_PAUSE_EN_SHIFT 6

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_RX_DROP_EN [05:05] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_DROP_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x20,5,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_DROP_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x20,5)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_DROP_EN_MASK 0x0020
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_DROP_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_DROP_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_DROP_EN_SHIFT 5

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN [04:04] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x10,4,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x10,4)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_MASK 0x0010
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TOTAL_DROP_EN_SHIFT 4

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN [03:03] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x8,3,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x8,3)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_MASK 0x0008
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_TXQ_DROP_EN_SHIFT 3

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN [02:02] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x4,2,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x4,2)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_MASK 0x0004
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_RX_BASED_CTRL_EN_SHIFT 2

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN [01:01] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x2,1,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x2,1)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_MASK 0x0002
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_QUANTUM_CTRL_EN_SHIFT 1

/* switch :: PAGE_0A_FC_PAUSE_DROP_CTRL :: PAGE_0A_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN [00:00] */
#define Wr_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x1,0,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL,0x1,0)
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_MASK 0x0001
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_BITS 1
#define SWITCH_PAGE_0A_FC_PAUSE_DROP_CTRL_PAGE_0A_FC_PAUSE_DROP_CTRL_TX_BASED_CTRL_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_THD_PAUSE_OFF
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_THD_PAUSE_OFF :: PAGE_0A_FC_TXQ_THD_PAUSE_OFF_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF,0xf800,11)
#define SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_TXQ_THD_PAUSE_OFF :: PAGE_0A_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF [10:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF(x) WriteRegBits16(SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF(x) ReadRegBits16(SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF,0x7ff,0)
#define SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_BITS 11
#define SWITCH_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_PAGE_0A_FC_TXQ_THD_PAUSE_OFF_TXQ_THD_PAUSE_OFF_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_RX_RUNOFF
 ***************************************************************************/
/* switch :: PAGE_0A_FC_RX_RUNOFF :: PAGE_0A_FC_RX_RUNOFF_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_RUNOFF,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_RUNOFF,0xf800,11)
#define SWITCH_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_RX_RUNOFF :: PAGE_0A_FC_RX_RUNOFF_RX_RUN_OFF_THD [10:00] */
#define Wr_switch_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RX_RUN_OFF_THD(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_RUNOFF,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RX_RUN_OFF_THD(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_RUNOFF,0x7ff,0)
#define SWITCH_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RX_RUN_OFF_THD_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RX_RUN_OFF_THD_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RX_RUN_OFF_THD_BITS 11
#define SWITCH_PAGE_0A_FC_RX_RUNOFF_PAGE_0A_FC_RX_RUNOFF_RX_RUN_OFF_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_RX_RSV_THD
 ***************************************************************************/
/* switch :: PAGE_0A_FC_RX_RSV_THD :: PAGE_0A_FC_RX_RSV_THD_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_RSV_THD,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_RSV_THD,0xf800,11)
#define SWITCH_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_RX_RSV_THD :: PAGE_0A_FC_RX_RSV_THD_RX_RSV_THD [10:00] */
#define Wr_switch_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RX_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_RSV_THD,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RX_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_RSV_THD,0x7ff,0)
#define SWITCH_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RX_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RX_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RX_RSV_THD_BITS 11
#define SWITCH_PAGE_0A_FC_RX_RSV_THD_PAGE_0A_FC_RX_RSV_THD_RX_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_RX_HYST_THD
 ***************************************************************************/
/* switch :: PAGE_0A_FC_RX_HYST_THD :: PAGE_0A_FC_RX_HYST_THD_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_HYST_THD,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_HYST_THD,0xf800,11)
#define SWITCH_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_RX_HYST_THD :: PAGE_0A_FC_RX_HYST_THD_RX_HYST_THD [10:00] */
#define Wr_switch_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RX_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_HYST_THD,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RX_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_HYST_THD,0x7ff,0)
#define SWITCH_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RX_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RX_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RX_HYST_THD_BITS 11
#define SWITCH_PAGE_0A_FC_RX_HYST_THD_PAGE_0A_FC_RX_HYST_THD_RX_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_RX_MAX_PTR
 ***************************************************************************/
/* switch :: PAGE_0A_FC_RX_MAX_PTR :: PAGE_0A_FC_RX_MAX_PTR_EN_REMAP [15:15] */
#define Wr_switch_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_EN_REMAP(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_MAX_PTR,0x8000,15,x)
#define Rd_switch_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_EN_REMAP(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_MAX_PTR,0x8000,15)
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_EN_REMAP_MASK 0x8000
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_EN_REMAP_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_EN_REMAP_BITS 1
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_EN_REMAP_SHIFT 15

/* switch :: PAGE_0A_FC_RX_MAX_PTR :: PAGE_0A_FC_RX_MAX_PTR_RESERVED [14:11] */
#define Wr_switch_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_MAX_PTR,0x7800,11,x)
#define Rd_switch_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_MAX_PTR,0x7800,11)
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_RESERVED_MASK 0x7800
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_RESERVED_BITS 4
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_RX_MAX_PTR :: PAGE_0A_FC_RX_MAX_PTR_MAXBUF_REMAP_THD [10:00] */
#define Wr_switch_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_MAXBUF_REMAP_THD(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_MAX_PTR,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_MAXBUF_REMAP_THD(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_MAX_PTR,0x7ff,0)
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_BITS 11
#define SWITCH_PAGE_0A_FC_RX_MAX_PTR_PAGE_0A_FC_RX_MAX_PTR_MAXBUF_REMAP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_SPARE_ZERO_REG
 ***************************************************************************/
/* switch :: PAGE_0A_FC_SPARE_ZERO_REG :: PAGE_0A_FC_SPARE_ZERO_REG_SPARE_ZERO [15:00] */
#define Wr_switch_PAGE_0A_FC_SPARE_ZERO_REG_PAGE_0A_FC_SPARE_ZERO_REG_SPARE_ZERO(x) WriteReg16(SWITCH_PAGE_0A_FC_SPARE_ZERO_REG,x)
#define Rd_switch_PAGE_0A_FC_SPARE_ZERO_REG_PAGE_0A_FC_SPARE_ZERO_REG_SPARE_ZERO(x) ReadReg16(SWITCH_PAGE_0A_FC_SPARE_ZERO_REG)
#define SWITCH_PAGE_0A_FC_SPARE_ZERO_REG_PAGE_0A_FC_SPARE_ZERO_REG_SPARE_ZERO_MASK 0xffff
#define SWITCH_PAGE_0A_FC_SPARE_ZERO_REG_PAGE_0A_FC_SPARE_ZERO_REG_SPARE_ZERO_ALIGN 0
#define SWITCH_PAGE_0A_FC_SPARE_ZERO_REG_PAGE_0A_FC_SPARE_ZERO_REG_SPARE_ZERO_BITS 16
#define SWITCH_PAGE_0A_FC_SPARE_ZERO_REG_PAGE_0A_FC_SPARE_ZERO_REG_SPARE_ZERO_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_SPARE_ONE_REG
 ***************************************************************************/
/* switch :: PAGE_0A_FC_SPARE_ONE_REG :: PAGE_0A_FC_SPARE_ONE_REG_SPARE_ONE [15:00] */
#define Wr_switch_PAGE_0A_FC_SPARE_ONE_REG_PAGE_0A_FC_SPARE_ONE_REG_SPARE_ONE(x) WriteReg16(SWITCH_PAGE_0A_FC_SPARE_ONE_REG,x)
#define Rd_switch_PAGE_0A_FC_SPARE_ONE_REG_PAGE_0A_FC_SPARE_ONE_REG_SPARE_ONE(x) ReadReg16(SWITCH_PAGE_0A_FC_SPARE_ONE_REG)
#define SWITCH_PAGE_0A_FC_SPARE_ONE_REG_PAGE_0A_FC_SPARE_ONE_REG_SPARE_ONE_MASK 0xffff
#define SWITCH_PAGE_0A_FC_SPARE_ONE_REG_PAGE_0A_FC_SPARE_ONE_REG_SPARE_ONE_ALIGN 0
#define SWITCH_PAGE_0A_FC_SPARE_ONE_REG_PAGE_0A_FC_SPARE_ONE_REG_SPARE_ONE_BITS 16
#define SWITCH_PAGE_0A_FC_SPARE_ONE_REG_PAGE_0A_FC_SPARE_ONE_REG_SPARE_ONE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_MON_TXQ0
 ***************************************************************************/
/* switch :: PAGE_0A_FC_MON_TXQ0 :: PAGE_0A_FC_MON_TXQ0_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ0,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ0,0xf800,11)
#define SWITCH_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_MON_TXQ0 :: PAGE_0A_FC_MON_TXQ0_MONITORED_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_MONITORED_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ0,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_MONITORED_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ0,0x7ff,0)
#define SWITCH_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_MONITORED_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_MONITORED_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_MONITORED_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_MON_TXQ0_PAGE_0A_FC_MON_TXQ0_MONITORED_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_MON_TXQ1
 ***************************************************************************/
/* switch :: PAGE_0A_FC_MON_TXQ1 :: PAGE_0A_FC_MON_TXQ1_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ1,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ1,0xf800,11)
#define SWITCH_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_MON_TXQ1 :: PAGE_0A_FC_MON_TXQ1_MONITORED_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_MONITORED_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ1,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_MONITORED_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ1,0x7ff,0)
#define SWITCH_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_MONITORED_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_MONITORED_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_MONITORED_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_MON_TXQ1_PAGE_0A_FC_MON_TXQ1_MONITORED_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_MON_TXQ2
 ***************************************************************************/
/* switch :: PAGE_0A_FC_MON_TXQ2 :: PAGE_0A_FC_MON_TXQ2_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ2,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ2,0xf800,11)
#define SWITCH_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_MON_TXQ2 :: PAGE_0A_FC_MON_TXQ2_MONITORED_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_MONITORED_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ2,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_MONITORED_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ2,0x7ff,0)
#define SWITCH_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_MONITORED_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_MONITORED_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_MONITORED_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_MON_TXQ2_PAGE_0A_FC_MON_TXQ2_MONITORED_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_MON_TXQ3
 ***************************************************************************/
/* switch :: PAGE_0A_FC_MON_TXQ3 :: PAGE_0A_FC_MON_TXQ3_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ3,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ3,0xf800,11)
#define SWITCH_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_MON_TXQ3 :: PAGE_0A_FC_MON_TXQ3_MONITORED_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_MONITORED_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ3,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_MONITORED_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ3,0x7ff,0)
#define SWITCH_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_MONITORED_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_MONITORED_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_MONITORED_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_MON_TXQ3_PAGE_0A_FC_MON_TXQ3_MONITORED_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_MON_TXQ4
 ***************************************************************************/
/* switch :: PAGE_0A_FC_MON_TXQ4 :: PAGE_0A_FC_MON_TXQ4_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ4,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ4,0xf800,11)
#define SWITCH_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_MON_TXQ4 :: PAGE_0A_FC_MON_TXQ4_MONITORED_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_MONITORED_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ4,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_MONITORED_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ4,0x7ff,0)
#define SWITCH_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_MONITORED_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_MONITORED_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_MONITORED_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_MON_TXQ4_PAGE_0A_FC_MON_TXQ4_MONITORED_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_MON_TXQ5
 ***************************************************************************/
/* switch :: PAGE_0A_FC_MON_TXQ5 :: PAGE_0A_FC_MON_TXQ5_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ5,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ5,0xf800,11)
#define SWITCH_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_MON_TXQ5 :: PAGE_0A_FC_MON_TXQ5_MONITORED_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_MONITORED_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ5,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_MONITORED_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ5,0x7ff,0)
#define SWITCH_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_MONITORED_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_MONITORED_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_MONITORED_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_MON_TXQ5_PAGE_0A_FC_MON_TXQ5_MONITORED_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_MON_TXQ6
 ***************************************************************************/
/* switch :: PAGE_0A_FC_MON_TXQ6 :: PAGE_0A_FC_MON_TXQ6_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ6,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ6,0xf800,11)
#define SWITCH_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_MON_TXQ6 :: PAGE_0A_FC_MON_TXQ6_MONITORED_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_MONITORED_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ6,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_MONITORED_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ6,0x7ff,0)
#define SWITCH_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_MONITORED_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_MONITORED_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_MONITORED_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_MON_TXQ6_PAGE_0A_FC_MON_TXQ6_MONITORED_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_MON_TXQ7
 ***************************************************************************/
/* switch :: PAGE_0A_FC_MON_TXQ7 :: PAGE_0A_FC_MON_TXQ7_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ7,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ7,0xf800,11)
#define SWITCH_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_MON_TXQ7 :: PAGE_0A_FC_MON_TXQ7_MONITORED_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_MONITORED_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ7,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_MONITORED_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_MON_TXQ7,0x7ff,0)
#define SWITCH_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_MONITORED_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_MONITORED_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_MONITORED_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_MON_TXQ7_PAGE_0A_FC_MON_TXQ7_MONITORED_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_TXQ0
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_TXQ0 :: PAGE_0A_FC_PEAK_TXQ0_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ0,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ0,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_TXQ0 :: PAGE_0A_FC_PEAK_TXQ0_PEAK_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_PEAK_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ0,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_PEAK_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ0,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_PEAK_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_PEAK_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_PEAK_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_TXQ0_PAGE_0A_FC_PEAK_TXQ0_PEAK_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_TXQ1
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_TXQ1 :: PAGE_0A_FC_PEAK_TXQ1_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ1,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ1,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_TXQ1 :: PAGE_0A_FC_PEAK_TXQ1_PEAK_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_PEAK_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ1,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_PEAK_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ1,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_PEAK_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_PEAK_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_PEAK_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_TXQ1_PAGE_0A_FC_PEAK_TXQ1_PEAK_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_TXQ2
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_TXQ2 :: PAGE_0A_FC_PEAK_TXQ2_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ2,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ2,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_TXQ2 :: PAGE_0A_FC_PEAK_TXQ2_PEAK_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_PEAK_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ2,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_PEAK_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ2,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_PEAK_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_PEAK_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_PEAK_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_TXQ2_PAGE_0A_FC_PEAK_TXQ2_PEAK_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_TXQ3
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_TXQ3 :: PAGE_0A_FC_PEAK_TXQ3_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ3,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ3,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_TXQ3 :: PAGE_0A_FC_PEAK_TXQ3_PEAK_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_PEAK_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ3,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_PEAK_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ3,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_PEAK_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_PEAK_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_PEAK_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_TXQ3_PAGE_0A_FC_PEAK_TXQ3_PEAK_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_TXQ4
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_TXQ4 :: PAGE_0A_FC_PEAK_TXQ4_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ4,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ4,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_TXQ4 :: PAGE_0A_FC_PEAK_TXQ4_PEAK_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_PEAK_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ4,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_PEAK_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ4,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_PEAK_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_PEAK_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_PEAK_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_TXQ4_PAGE_0A_FC_PEAK_TXQ4_PEAK_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_TXQ5
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_TXQ5 :: PAGE_0A_FC_PEAK_TXQ5_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ5,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ5,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_TXQ5 :: PAGE_0A_FC_PEAK_TXQ5_PEAK_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_PEAK_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ5,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_PEAK_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ5,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_PEAK_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_PEAK_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_PEAK_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_TXQ5_PAGE_0A_FC_PEAK_TXQ5_PEAK_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_TXQ6
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_TXQ6 :: PAGE_0A_FC_PEAK_TXQ6_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ6,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ6,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_TXQ6 :: PAGE_0A_FC_PEAK_TXQ6_PEAK_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_PEAK_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ6,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_PEAK_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ6,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_PEAK_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_PEAK_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_PEAK_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_TXQ6_PAGE_0A_FC_PEAK_TXQ6_PEAK_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_TXQ7
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_TXQ7 :: PAGE_0A_FC_PEAK_TXQ7_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ7,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ7,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_TXQ7 :: PAGE_0A_FC_PEAK_TXQ7_PEAK_TXQ_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_PEAK_TXQ_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ7,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_PEAK_TXQ_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TXQ7,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_PEAK_TXQ_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_PEAK_TXQ_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_PEAK_TXQ_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_TXQ7_PAGE_0A_FC_PEAK_TXQ7_PEAK_TXQ_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_TOTAL_USED
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_TOTAL_USED :: PAGE_0A_FC_PEAK_TOTAL_USED_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_TOTAL_USED :: PAGE_0A_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_TOTAL_USED_PAGE_0A_FC_PEAK_TOTAL_USED_PEAK_TOTAL_USE_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_USED
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_USED :: PAGE_0A_FC_TOTAL_USED_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_TOTAL_USED,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_TOTAL_USED,0xf800,11)
#define SWITCH_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_TOTAL_USED :: PAGE_0A_FC_TOTAL_USED_TOTAL_USE_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_TOTAL_USE_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_TOTAL_USED,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_TOTAL_USE_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_TOTAL_USED,0x7ff,0)
#define SWITCH_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_TOTAL_USE_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_TOTAL_USE_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_TOTAL_USE_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_TOTAL_USED_PAGE_0A_FC_TOTAL_USED_TOTAL_USE_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PEAK_RX_CNT
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PEAK_RX_CNT :: PAGE_0A_FC_PEAK_RX_CNT_RESERVED [15:11] */
#define Wr_switch_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_RX_CNT,0xf800,11,x)
#define Rd_switch_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_RX_CNT,0xf800,11)
#define SWITCH_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_RESERVED_BITS 5
#define SWITCH_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_RESERVED_SHIFT 11

/* switch :: PAGE_0A_FC_PEAK_RX_CNT :: PAGE_0A_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT [10:00] */
#define Wr_switch_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PEAK_RX_CNT,0x7ff,0,x)
#define Rd_switch_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PEAK_RX_CNT,0x7ff,0)
#define SWITCH_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_MASK 0x07ff
#define SWITCH_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_ALIGN 0
#define SWITCH_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_BITS 11
#define SWITCH_PAGE_0A_FC_PEAK_RX_CNT_PAGE_0A_FC_PEAK_RX_CNT_PEAK_RXBUF_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_LINK_PORTMAP
 ***************************************************************************/
/* switch :: PAGE_0A_FC_LINK_PORTMAP :: PAGE_0A_FC_LINK_PORTMAP_RESERVED [15:09] */
#define Wr_switch_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_LINK_PORTMAP,0xfe00,9,x)
#define Rd_switch_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_LINK_PORTMAP,0xfe00,9)
#define SWITCH_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_RESERVED_BITS 7
#define SWITCH_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_RESERVED_SHIFT 9

/* switch :: PAGE_0A_FC_LINK_PORTMAP :: PAGE_0A_FC_LINK_PORTMAP_LINK_PORTMAP [08:00] */
#define Wr_switch_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_LINK_PORTMAP(x) WriteRegBits16(SWITCH_PAGE_0A_FC_LINK_PORTMAP,0x1ff,0,x)
#define Rd_switch_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_LINK_PORTMAP(x) ReadRegBits16(SWITCH_PAGE_0A_FC_LINK_PORTMAP,0x1ff,0)
#define SWITCH_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_LINK_PORTMAP_MASK 0x01ff
#define SWITCH_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_LINK_PORTMAP_ALIGN 0
#define SWITCH_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_LINK_PORTMAP_BITS 9
#define SWITCH_PAGE_0A_FC_LINK_PORTMAP_PAGE_0A_FC_LINK_PORTMAP_LINK_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_GIGA_PORTMAP
 ***************************************************************************/
/* switch :: PAGE_0A_FC_GIGA_PORTMAP :: PAGE_0A_FC_GIGA_PORTMAP_RESERVED [15:09] */
#define Wr_switch_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_GIGA_PORTMAP,0xfe00,9,x)
#define Rd_switch_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_GIGA_PORTMAP,0xfe00,9)
#define SWITCH_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_RESERVED_BITS 7
#define SWITCH_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_RESERVED_SHIFT 9

/* switch :: PAGE_0A_FC_GIGA_PORTMAP :: PAGE_0A_FC_GIGA_PORTMAP_GIGA_PORTMAP [08:00] */
#define Wr_switch_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_GIGA_PORTMAP(x) WriteRegBits16(SWITCH_PAGE_0A_FC_GIGA_PORTMAP,0x1ff,0,x)
#define Rd_switch_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_GIGA_PORTMAP(x) ReadRegBits16(SWITCH_PAGE_0A_FC_GIGA_PORTMAP,0x1ff,0)
#define SWITCH_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_GIGA_PORTMAP_MASK 0x01ff
#define SWITCH_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_GIGA_PORTMAP_ALIGN 0
#define SWITCH_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_GIGA_PORTMAP_BITS 9
#define SWITCH_PAGE_0A_FC_GIGA_PORTMAP_PAGE_0A_FC_GIGA_PORTMAP_GIGA_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port0
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port0 :: PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_0 [15:00] */
#define Wr_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port0_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_0(x) WriteReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT0,x)
#define Rd_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port0_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_0(x) ReadReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT0)
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_0_MASK 0xffff
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_0_ALIGN 0
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_0_BITS 16
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port1
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port1 :: PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_1 [15:00] */
#define Wr_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port1_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_1(x) WriteReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT1,x)
#define Rd_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port1_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_1(x) ReadReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT1)
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_1_MASK 0xffff
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_1_ALIGN 0
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_1_BITS 16
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port2
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port2 :: PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_2 [15:00] */
#define Wr_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port2_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_2(x) WriteReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT2,x)
#define Rd_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port2_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_2(x) ReadReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT2)
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_2_MASK 0xffff
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_2_ALIGN 0
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_2_BITS 16
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port3
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port3 :: PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_3 [15:00] */
#define Wr_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port3_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_3(x) WriteReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT3,x)
#define Rd_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port3_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_3(x) ReadReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT3)
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_3_MASK 0xffff
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_3_ALIGN 0
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_3_BITS 16
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port4
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port4 :: PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_4 [15:00] */
#define Wr_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port4_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_4(x) WriteReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT4,x)
#define Rd_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port4_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_4(x) ReadReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT4)
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_4_MASK 0xffff
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_4_ALIGN 0
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_4_BITS 16
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port5
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port5 :: PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_5 [15:00] */
#define Wr_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port5_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_5(x) WriteReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT5,x)
#define Rd_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port5_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_5(x) ReadReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT5)
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_5_MASK 0xffff
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_5_ALIGN 0
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_5_BITS 16
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port6
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CONG_PORTMAP_PN_port6 :: PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_6 [15:00] */
#define Wr_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port6_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_6(x) WriteReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT6,x)
#define Rd_switch_PAGE_0A_FC_CONG_PORTMAP_PN_port6_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_6(x) ReadReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT6)
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_6_MASK 0xffff
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_6_ALIGN 0
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_6_BITS 16
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_CONG_PORTMAP_PN_CONGEST_PORTMAP_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CONG_PORTMAP_P7
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CONG_PORTMAP_P7 :: PAGE_0A_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP [15:00] */
#define Wr_switch_PAGE_0A_FC_CONG_PORTMAP_P7_PAGE_0A_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP(x) WriteReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_P7,x)
#define Rd_switch_PAGE_0A_FC_CONG_PORTMAP_P7_PAGE_0A_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP(x) ReadReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_P7)
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P7_PAGE_0A_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_MASK 0xffff
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P7_PAGE_0A_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_ALIGN 0
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P7_PAGE_0A_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_BITS 16
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P7_PAGE_0A_FC_CONG_PORTMAP_P7_CONGEST_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_CONG_PORTMAP_P8
 ***************************************************************************/
/* switch :: PAGE_0A_FC_CONG_PORTMAP_P8 :: PAGE_0A_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP [15:00] */
#define Wr_switch_PAGE_0A_FC_CONG_PORTMAP_P8_PAGE_0A_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP(x) WriteReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_P8,x)
#define Rd_switch_PAGE_0A_FC_CONG_PORTMAP_P8_PAGE_0A_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP(x) ReadReg16(SWITCH_PAGE_0A_FC_CONG_PORTMAP_P8)
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P8_PAGE_0A_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_MASK 0xffff
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P8_PAGE_0A_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_ALIGN 0
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P8_PAGE_0A_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_BITS 16
#define SWITCH_PAGE_0A_FC_CONG_PORTMAP_P8_PAGE_0A_FC_CONG_PORTMAP_P8_CONGEST_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_PAUSE_HIS
 ***************************************************************************/
/* switch :: PAGE_0A_FC_PAUSE_HIS :: PAGE_0A_FC_PAUSE_HIS_RESERVED [15:09] */
#define Wr_switch_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_HIS,0xfe00,9,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_HIS,0xfe00,9)
#define SWITCH_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_RESERVED_BITS 7
#define SWITCH_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_RESERVED_SHIFT 9

/* switch :: PAGE_0A_FC_PAUSE_HIS :: PAGE_0A_FC_PAUSE_HIS_PAUSE_HIS [08:00] */
#define Wr_switch_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_PAUSE_HIS(x) WriteRegBits16(SWITCH_PAGE_0A_FC_PAUSE_HIS,0x1ff,0,x)
#define Rd_switch_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_PAUSE_HIS(x) ReadRegBits16(SWITCH_PAGE_0A_FC_PAUSE_HIS,0x1ff,0)
#define SWITCH_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_PAUSE_HIS_MASK 0x01ff
#define SWITCH_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_PAUSE_HIS_ALIGN 0
#define SWITCH_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_PAUSE_HIS_BITS 9
#define SWITCH_PAGE_0A_FC_PAUSE_HIS_PAGE_0A_FC_PAUSE_HIS_PAUSE_HIS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS :: PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_RESERVED [15:09] */
#define Wr_switch_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS,0xfe00,9,x)
#define Rd_switch_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS,0xfe00,9)
#define SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_RESERVED_BITS 7
#define SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_RESERVED_SHIFT 9

/* switch :: PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS :: PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS [08:00] */
#define Wr_switch_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS(x) WriteRegBits16(SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS,0x1ff,0,x)
#define Rd_switch_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS(x) ReadRegBits16(SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS,0x1ff,0)
#define SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_MASK 0x01ff
#define SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_ALIGN 0
#define SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_BITS 9
#define SWITCH_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_PAGE_0A_FC_TX_QUANTUM_PAUSE_HIS_TX_QUANTUM_PAUSE_HIS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_RX_PAUSE_HIS
 ***************************************************************************/
/* switch :: PAGE_0A_FC_RX_PAUSE_HIS :: PAGE_0A_FC_RX_PAUSE_HIS_RESERVED [15:09] */
#define Wr_switch_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_PAUSE_HIS,0xfe00,9,x)
#define Rd_switch_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_PAUSE_HIS,0xfe00,9)
#define SWITCH_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RESERVED_BITS 7
#define SWITCH_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RESERVED_SHIFT 9

/* switch :: PAGE_0A_FC_RX_PAUSE_HIS :: PAGE_0A_FC_RX_PAUSE_HIS_RX_PAUSE_HIS [08:00] */
#define Wr_switch_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RX_PAUSE_HIS(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RX_PAUSE_HIS,0x1ff,0,x)
#define Rd_switch_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RX_PAUSE_HIS(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RX_PAUSE_HIS,0x1ff,0)
#define SWITCH_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_MASK 0x01ff
#define SWITCH_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_ALIGN 0
#define SWITCH_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_BITS 9
#define SWITCH_PAGE_0A_FC_RX_PAUSE_HIS_PAGE_0A_FC_RX_PAUSE_HIS_RX_PAUSE_HIS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_RXBUF_ERR_HIS
 ***************************************************************************/
/* switch :: PAGE_0A_FC_RXBUF_ERR_HIS :: PAGE_0A_FC_RXBUF_ERR_HIS_RESERVED [15:09] */
#define Wr_switch_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS,0xfe00,9,x)
#define Rd_switch_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS,0xfe00,9)
#define SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RESERVED_ALIGN 0
#define SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RESERVED_BITS 7
#define SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RESERVED_SHIFT 9

/* switch :: PAGE_0A_FC_RXBUF_ERR_HIS :: PAGE_0A_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS [08:00] */
#define Wr_switch_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS(x) WriteRegBits16(SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS,0x1ff,0,x)
#define Rd_switch_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS(x) ReadRegBits16(SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS,0x1ff,0)
#define SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_MASK 0x01ff
#define SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_ALIGN 0
#define SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_BITS 9
#define SWITCH_PAGE_0A_FC_RXBUF_ERR_HIS_PAGE_0A_FC_RXBUF_ERR_HIS_RXBUF_ERR_HIS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port0
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port0 :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_0 [15:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port0_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_0(x) WriteReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT0,x)
#define Rd_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port0_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_0(x) ReadReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT0)
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_0_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_0_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_0_BITS 16
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port1
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port1 :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_1 [15:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port1_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_1(x) WriteReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT1,x)
#define Rd_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port1_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_1(x) ReadReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT1)
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_1_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_1_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_1_BITS 16
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port2
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port2 :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_2 [15:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port2_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_2(x) WriteReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT2,x)
#define Rd_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port2_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_2(x) ReadReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT2)
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_2_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_2_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_2_BITS 16
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port3
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port3 :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_3 [15:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port3_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_3(x) WriteReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT3,x)
#define Rd_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port3_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_3(x) ReadReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT3)
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_3_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_3_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_3_BITS 16
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port4
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port4 :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_4 [15:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port4_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_4(x) WriteReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT4,x)
#define Rd_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port4_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_4(x) ReadReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT4)
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_4_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_4_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_4_BITS 16
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port5
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port5 :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_5 [15:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port5_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_5(x) WriteReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT5,x)
#define Rd_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port5_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_5(x) ReadReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT5)
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_5_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_5_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_5_BITS 16
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port6
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port6 :: PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_6 [15:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port6_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_6(x) WriteReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT6,x)
#define Rd_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_port6_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_6(x) ReadReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT6)
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_6_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_6_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_6_BITS 16
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_TXQ_CONG_PORTMAP_PN_TXQ_CONGEST_PORTMAP_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_P7
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_P7 :: PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP [15:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP(x) WriteReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7,x)
#define Rd_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP(x) ReadReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7)
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_BITS 16
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_PAGE_0A_FC_TXQ_CONG_PORTMAP_P7_TXQ_CONGEST_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_P8
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TXQ_CONG_PORTMAP_P8 :: PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP [15:00] */
#define Wr_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP(x) WriteReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8,x)
#define Rd_switch_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP(x) ReadReg16(SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8)
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_ALIGN 0
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_BITS 16
#define SWITCH_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_PAGE_0A_FC_TXQ_CONG_PORTMAP_P8_TXQ_CONGEST_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port0
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port0 :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_0 [15:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port0_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_0(x) WriteReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT0,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port0_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_0(x) ReadReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT0)
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_0_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_0_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_0_BITS 16
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT0_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port1
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port1 :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_1 [15:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port1_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_1(x) WriteReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT1,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port1_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_1(x) ReadReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT1)
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_1_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_1_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_1_BITS 16
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT1_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port2
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port2 :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_2 [15:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port2_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_2(x) WriteReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT2,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port2_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_2(x) ReadReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT2)
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_2_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_2_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_2_BITS 16
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT2_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port3
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port3 :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_3 [15:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port3_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_3(x) WriteReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT3,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port3_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_3(x) ReadReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT3)
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_3_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_3_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_3_BITS 16
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT3_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port4
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port4 :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_4 [15:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port4_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_4(x) WriteReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT4,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port4_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_4(x) ReadReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT4)
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_4_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_4_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_4_BITS 16
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT4_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port5
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port5 :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_5 [15:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port5_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_5(x) WriteReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT5,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port5_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_5(x) ReadReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT5)
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_5_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_5_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_5_BITS 16
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT5_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port6
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port6 :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_6 [15:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port6_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_6(x) WriteReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT6,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_port6_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_6(x) ReadReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT6)
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_6_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_6_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_6_BITS 16
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_PORT6_PAGE_0A_FC_TOTAL_CONG_PORTMAP_PN_TOTAL_CONGEST_PORTMAP_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7 :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP [15:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP(x) WriteReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP(x) ReadReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7)
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_BITS 16
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P7_TOTAL_CONGEST_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8
 ***************************************************************************/
/* switch :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8 :: PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP [15:00] */
#define Wr_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP(x) WriteReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8,x)
#define Rd_switch_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP(x) ReadReg16(SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8)
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_MASK 0xffff
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_ALIGN 0
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_BITS 16
#define SWITCH_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_PAGE_0A_FC_TOTAL_CONG_PORTMAP_P8_TOTAL_CONGEST_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q0_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q1_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q2_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q3_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q4_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q5_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q6_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7 :: PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_PAGE_0B_FC_LAN_TXQ_THD_RSV_Q7_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q0_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q1_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q2_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q3_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q4_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q5_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q6_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7 :: PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_PAGE_0B_FC_LAN_TXQ_THD_HYST_Q7_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7 :: PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q0_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q1_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q2_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q3_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q4_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q5_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q6_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7 :: PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_PAGE_0B_FC_LAN_TXQ_THD_DROP_Q7_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7 :: PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_PAGE_0B_FC_LAN_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7 :: PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_PAGE_0B_FC_LAN_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7
 ***************************************************************************/
/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7,0xf800,11)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7 :: PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7,0x7ff,0)
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_PAGE_0B_FC_LAN_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_P0_DEBUG_MUX
 ***************************************************************************/
/* switch :: PAGE_0C_P0_DEBUG_MUX :: PAGE_0C_P0_DEBUG_MUX_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_P0_DEBUG_MUX_PAGE_0C_P0_DEBUG_MUX_RESERVED(x) WriteReg(SWITCH_PAGE_0C_P0_DEBUG_MUX,x)
#define Rd_switch_PAGE_0C_P0_DEBUG_MUX_PAGE_0C_P0_DEBUG_MUX_RESERVED(x) ReadReg(SWITCH_PAGE_0C_P0_DEBUG_MUX)
#define SWITCH_PAGE_0C_P0_DEBUG_MUX_PAGE_0C_P0_DEBUG_MUX_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_P0_DEBUG_MUX_PAGE_0C_P0_DEBUG_MUX_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_P0_DEBUG_MUX_PAGE_0C_P0_DEBUG_MUX_RESERVED_BITS 32
#define SWITCH_PAGE_0C_P0_DEBUG_MUX_PAGE_0C_P0_DEBUG_MUX_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_P1_DEBUG_MUX
 ***************************************************************************/
/* switch :: PAGE_0C_P1_DEBUG_MUX :: PAGE_0C_P1_DEBUG_MUX_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_P1_DEBUG_MUX_PAGE_0C_P1_DEBUG_MUX_RESERVED(x) WriteReg(SWITCH_PAGE_0C_P1_DEBUG_MUX,x)
#define Rd_switch_PAGE_0C_P1_DEBUG_MUX_PAGE_0C_P1_DEBUG_MUX_RESERVED(x) ReadReg(SWITCH_PAGE_0C_P1_DEBUG_MUX)
#define SWITCH_PAGE_0C_P1_DEBUG_MUX_PAGE_0C_P1_DEBUG_MUX_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_P1_DEBUG_MUX_PAGE_0C_P1_DEBUG_MUX_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_P1_DEBUG_MUX_PAGE_0C_P1_DEBUG_MUX_RESERVED_BITS 32
#define SWITCH_PAGE_0C_P1_DEBUG_MUX_PAGE_0C_P1_DEBUG_MUX_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_P2_DEBUG_MUX
 ***************************************************************************/
/* switch :: PAGE_0C_P2_DEBUG_MUX :: PAGE_0C_P2_DEBUG_MUX_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_P2_DEBUG_MUX_PAGE_0C_P2_DEBUG_MUX_RESERVED(x) WriteReg(SWITCH_PAGE_0C_P2_DEBUG_MUX,x)
#define Rd_switch_PAGE_0C_P2_DEBUG_MUX_PAGE_0C_P2_DEBUG_MUX_RESERVED(x) ReadReg(SWITCH_PAGE_0C_P2_DEBUG_MUX)
#define SWITCH_PAGE_0C_P2_DEBUG_MUX_PAGE_0C_P2_DEBUG_MUX_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_P2_DEBUG_MUX_PAGE_0C_P2_DEBUG_MUX_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_P2_DEBUG_MUX_PAGE_0C_P2_DEBUG_MUX_RESERVED_BITS 32
#define SWITCH_PAGE_0C_P2_DEBUG_MUX_PAGE_0C_P2_DEBUG_MUX_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_P3_DEBUG_MUX
 ***************************************************************************/
/* switch :: PAGE_0C_P3_DEBUG_MUX :: PAGE_0C_P3_DEBUG_MUX_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_P3_DEBUG_MUX_PAGE_0C_P3_DEBUG_MUX_RESERVED(x) WriteReg(SWITCH_PAGE_0C_P3_DEBUG_MUX,x)
#define Rd_switch_PAGE_0C_P3_DEBUG_MUX_PAGE_0C_P3_DEBUG_MUX_RESERVED(x) ReadReg(SWITCH_PAGE_0C_P3_DEBUG_MUX)
#define SWITCH_PAGE_0C_P3_DEBUG_MUX_PAGE_0C_P3_DEBUG_MUX_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_P3_DEBUG_MUX_PAGE_0C_P3_DEBUG_MUX_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_P3_DEBUG_MUX_PAGE_0C_P3_DEBUG_MUX_RESERVED_BITS 32
#define SWITCH_PAGE_0C_P3_DEBUG_MUX_PAGE_0C_P3_DEBUG_MUX_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_P4_DEBUG_MUX
 ***************************************************************************/
/* switch :: PAGE_0C_P4_DEBUG_MUX :: PAGE_0C_P4_DEBUG_MUX_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_P4_DEBUG_MUX_PAGE_0C_P4_DEBUG_MUX_RESERVED(x) WriteReg(SWITCH_PAGE_0C_P4_DEBUG_MUX,x)
#define Rd_switch_PAGE_0C_P4_DEBUG_MUX_PAGE_0C_P4_DEBUG_MUX_RESERVED(x) ReadReg(SWITCH_PAGE_0C_P4_DEBUG_MUX)
#define SWITCH_PAGE_0C_P4_DEBUG_MUX_PAGE_0C_P4_DEBUG_MUX_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_P4_DEBUG_MUX_PAGE_0C_P4_DEBUG_MUX_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_P4_DEBUG_MUX_PAGE_0C_P4_DEBUG_MUX_RESERVED_BITS 32
#define SWITCH_PAGE_0C_P4_DEBUG_MUX_PAGE_0C_P4_DEBUG_MUX_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_P5_DEBUG_MUX
 ***************************************************************************/
/* switch :: PAGE_0C_P5_DEBUG_MUX :: PAGE_0C_P5_DEBUG_MUX_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_P5_DEBUG_MUX_PAGE_0C_P5_DEBUG_MUX_RESERVED(x) WriteReg(SWITCH_PAGE_0C_P5_DEBUG_MUX,x)
#define Rd_switch_PAGE_0C_P5_DEBUG_MUX_PAGE_0C_P5_DEBUG_MUX_RESERVED(x) ReadReg(SWITCH_PAGE_0C_P5_DEBUG_MUX)
#define SWITCH_PAGE_0C_P5_DEBUG_MUX_PAGE_0C_P5_DEBUG_MUX_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_P5_DEBUG_MUX_PAGE_0C_P5_DEBUG_MUX_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_P5_DEBUG_MUX_PAGE_0C_P5_DEBUG_MUX_RESERVED_BITS 32
#define SWITCH_PAGE_0C_P5_DEBUG_MUX_PAGE_0C_P5_DEBUG_MUX_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_P6_DEBUG_MUX
 ***************************************************************************/
/* switch :: PAGE_0C_P6_DEBUG_MUX :: PAGE_0C_P6_DEBUG_MUX_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_P6_DEBUG_MUX_PAGE_0C_P6_DEBUG_MUX_RESERVED(x) WriteReg(SWITCH_PAGE_0C_P6_DEBUG_MUX,x)
#define Rd_switch_PAGE_0C_P6_DEBUG_MUX_PAGE_0C_P6_DEBUG_MUX_RESERVED(x) ReadReg(SWITCH_PAGE_0C_P6_DEBUG_MUX)
#define SWITCH_PAGE_0C_P6_DEBUG_MUX_PAGE_0C_P6_DEBUG_MUX_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_P6_DEBUG_MUX_PAGE_0C_P6_DEBUG_MUX_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_P6_DEBUG_MUX_PAGE_0C_P6_DEBUG_MUX_RESERVED_BITS 32
#define SWITCH_PAGE_0C_P6_DEBUG_MUX_PAGE_0C_P6_DEBUG_MUX_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_P7_DEBUG_MUX
 ***************************************************************************/
/* switch :: PAGE_0C_P7_DEBUG_MUX :: PAGE_0C_P7_DEBUG_MUX_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_P7_DEBUG_MUX_PAGE_0C_P7_DEBUG_MUX_RESERVED(x) WriteReg(SWITCH_PAGE_0C_P7_DEBUG_MUX,x)
#define Rd_switch_PAGE_0C_P7_DEBUG_MUX_PAGE_0C_P7_DEBUG_MUX_RESERVED(x) ReadReg(SWITCH_PAGE_0C_P7_DEBUG_MUX)
#define SWITCH_PAGE_0C_P7_DEBUG_MUX_PAGE_0C_P7_DEBUG_MUX_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_P7_DEBUG_MUX_PAGE_0C_P7_DEBUG_MUX_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_P7_DEBUG_MUX_PAGE_0C_P7_DEBUG_MUX_RESERVED_BITS 32
#define SWITCH_PAGE_0C_P7_DEBUG_MUX_PAGE_0C_P7_DEBUG_MUX_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_IMP_DEBUG_MUX
 ***************************************************************************/
/* switch :: PAGE_0C_IMP_DEBUG_MUX :: PAGE_0C_IMP_DEBUG_MUX_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_IMP_DEBUG_MUX_PAGE_0C_IMP_DEBUG_MUX_RESERVED(x) WriteReg(SWITCH_PAGE_0C_IMP_DEBUG_MUX,x)
#define Rd_switch_PAGE_0C_IMP_DEBUG_MUX_PAGE_0C_IMP_DEBUG_MUX_RESERVED(x) ReadReg(SWITCH_PAGE_0C_IMP_DEBUG_MUX)
#define SWITCH_PAGE_0C_IMP_DEBUG_MUX_PAGE_0C_IMP_DEBUG_MUX_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_IMP_DEBUG_MUX_PAGE_0C_IMP_DEBUG_MUX_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_IMP_DEBUG_MUX_PAGE_0C_IMP_DEBUG_MUX_RESERVED_BITS 32
#define SWITCH_PAGE_0C_IMP_DEBUG_MUX_PAGE_0C_IMP_DEBUG_MUX_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_CFP_DEBUG_BUS_0
 ***************************************************************************/
/* switch :: PAGE_0C_CFP_DEBUG_BUS_0 :: PAGE_0C_CFP_DEBUG_BUS_0_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_CFP_DEBUG_BUS_0_PAGE_0C_CFP_DEBUG_BUS_0_RESERVED(x) WriteReg(SWITCH_PAGE_0C_CFP_DEBUG_BUS_0,x)
#define Rd_switch_PAGE_0C_CFP_DEBUG_BUS_0_PAGE_0C_CFP_DEBUG_BUS_0_RESERVED(x) ReadReg(SWITCH_PAGE_0C_CFP_DEBUG_BUS_0)
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_0_PAGE_0C_CFP_DEBUG_BUS_0_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_0_PAGE_0C_CFP_DEBUG_BUS_0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_0_PAGE_0C_CFP_DEBUG_BUS_0_RESERVED_BITS 32
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_0_PAGE_0C_CFP_DEBUG_BUS_0_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_CFP_DEBUG_BUS_1
 ***************************************************************************/
/* switch :: PAGE_0C_CFP_DEBUG_BUS_1 :: PAGE_0C_CFP_DEBUG_BUS_1_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_CFP_DEBUG_BUS_1_PAGE_0C_CFP_DEBUG_BUS_1_RESERVED(x) WriteReg(SWITCH_PAGE_0C_CFP_DEBUG_BUS_1,x)
#define Rd_switch_PAGE_0C_CFP_DEBUG_BUS_1_PAGE_0C_CFP_DEBUG_BUS_1_RESERVED(x) ReadReg(SWITCH_PAGE_0C_CFP_DEBUG_BUS_1)
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_1_PAGE_0C_CFP_DEBUG_BUS_1_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_1_PAGE_0C_CFP_DEBUG_BUS_1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_1_PAGE_0C_CFP_DEBUG_BUS_1_RESERVED_BITS 32
#define SWITCH_PAGE_0C_CFP_DEBUG_BUS_1_PAGE_0C_CFP_DEBUG_BUS_1_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_WRED_DEBUG_0
 ***************************************************************************/
/* switch :: PAGE_0C_WRED_DEBUG_0 :: PAGE_0C_WRED_DEBUG_0_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_WRED_DEBUG_0_PAGE_0C_WRED_DEBUG_0_RESERVED(x) WriteReg(SWITCH_PAGE_0C_WRED_DEBUG_0,x)
#define Rd_switch_PAGE_0C_WRED_DEBUG_0_PAGE_0C_WRED_DEBUG_0_RESERVED(x) ReadReg(SWITCH_PAGE_0C_WRED_DEBUG_0)
#define SWITCH_PAGE_0C_WRED_DEBUG_0_PAGE_0C_WRED_DEBUG_0_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_WRED_DEBUG_0_PAGE_0C_WRED_DEBUG_0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_WRED_DEBUG_0_PAGE_0C_WRED_DEBUG_0_RESERVED_BITS 32
#define SWITCH_PAGE_0C_WRED_DEBUG_0_PAGE_0C_WRED_DEBUG_0_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_WRED_DEBUG_1
 ***************************************************************************/
/* switch :: PAGE_0C_WRED_DEBUG_1 :: PAGE_0C_WRED_DEBUG_1_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_WRED_DEBUG_1_PAGE_0C_WRED_DEBUG_1_RESERVED(x) WriteReg(SWITCH_PAGE_0C_WRED_DEBUG_1,x)
#define Rd_switch_PAGE_0C_WRED_DEBUG_1_PAGE_0C_WRED_DEBUG_1_RESERVED(x) ReadReg(SWITCH_PAGE_0C_WRED_DEBUG_1)
#define SWITCH_PAGE_0C_WRED_DEBUG_1_PAGE_0C_WRED_DEBUG_1_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_WRED_DEBUG_1_PAGE_0C_WRED_DEBUG_1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_WRED_DEBUG_1_PAGE_0C_WRED_DEBUG_1_RESERVED_BITS 32
#define SWITCH_PAGE_0C_WRED_DEBUG_1_PAGE_0C_WRED_DEBUG_1_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_TOP_MISC_DEBUG_0
 ***************************************************************************/
/* switch :: PAGE_0C_TOP_MISC_DEBUG_0 :: PAGE_0C_TOP_MISC_DEBUG_0_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_TOP_MISC_DEBUG_0_PAGE_0C_TOP_MISC_DEBUG_0_RESERVED(x) WriteReg(SWITCH_PAGE_0C_TOP_MISC_DEBUG_0,x)
#define Rd_switch_PAGE_0C_TOP_MISC_DEBUG_0_PAGE_0C_TOP_MISC_DEBUG_0_RESERVED(x) ReadReg(SWITCH_PAGE_0C_TOP_MISC_DEBUG_0)
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_0_PAGE_0C_TOP_MISC_DEBUG_0_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_0_PAGE_0C_TOP_MISC_DEBUG_0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_0_PAGE_0C_TOP_MISC_DEBUG_0_RESERVED_BITS 32
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_0_PAGE_0C_TOP_MISC_DEBUG_0_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_TOP_MISC_DEBUG_1
 ***************************************************************************/
/* switch :: PAGE_0C_TOP_MISC_DEBUG_1 :: PAGE_0C_TOP_MISC_DEBUG_1_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_TOP_MISC_DEBUG_1_PAGE_0C_TOP_MISC_DEBUG_1_RESERVED(x) WriteReg(SWITCH_PAGE_0C_TOP_MISC_DEBUG_1,x)
#define Rd_switch_PAGE_0C_TOP_MISC_DEBUG_1_PAGE_0C_TOP_MISC_DEBUG_1_RESERVED(x) ReadReg(SWITCH_PAGE_0C_TOP_MISC_DEBUG_1)
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_1_PAGE_0C_TOP_MISC_DEBUG_1_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_1_PAGE_0C_TOP_MISC_DEBUG_1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_1_PAGE_0C_TOP_MISC_DEBUG_1_RESERVED_BITS 32
#define SWITCH_PAGE_0C_TOP_MISC_DEBUG_1_PAGE_0C_TOP_MISC_DEBUG_1_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_DIAGREG_BUFCON
 ***************************************************************************/
/* switch :: PAGE_0C_DIAGREG_BUFCON :: PAGE_0C_DIAGREG_BUFCON_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_DIAGREG_BUFCON_PAGE_0C_DIAGREG_BUFCON_RESERVED(x) WriteReg(SWITCH_PAGE_0C_DIAGREG_BUFCON,x)
#define Rd_switch_PAGE_0C_DIAGREG_BUFCON_PAGE_0C_DIAGREG_BUFCON_RESERVED(x) ReadReg(SWITCH_PAGE_0C_DIAGREG_BUFCON)
#define SWITCH_PAGE_0C_DIAGREG_BUFCON_PAGE_0C_DIAGREG_BUFCON_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_DIAGREG_BUFCON_PAGE_0C_DIAGREG_BUFCON_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_DIAGREG_BUFCON_PAGE_0C_DIAGREG_BUFCON_RESERVED_BITS 32
#define SWITCH_PAGE_0C_DIAGREG_BUFCON_PAGE_0C_DIAGREG_BUFCON_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_TESTBUS_P1588
 ***************************************************************************/
/* switch :: PAGE_0C_TESTBUS_P1588 :: PAGE_0C_TESTBUS_P1588_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_TESTBUS_P1588_PAGE_0C_TESTBUS_P1588_RESERVED(x) WriteReg(SWITCH_PAGE_0C_TESTBUS_P1588,x)
#define Rd_switch_PAGE_0C_TESTBUS_P1588_PAGE_0C_TESTBUS_P1588_RESERVED(x) ReadReg(SWITCH_PAGE_0C_TESTBUS_P1588)
#define SWITCH_PAGE_0C_TESTBUS_P1588_PAGE_0C_TESTBUS_P1588_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_TESTBUS_P1588_PAGE_0C_TESTBUS_P1588_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_TESTBUS_P1588_PAGE_0C_TESTBUS_P1588_RESERVED_BITS 32
#define SWITCH_PAGE_0C_TESTBUS_P1588_PAGE_0C_TESTBUS_P1588_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0C_FLOWCON_DEBUG_BUS
 ***************************************************************************/
/* switch :: PAGE_0C_FLOWCON_DEBUG_BUS :: PAGE_0C_FLOWCON_DEBUG_BUS_RESERVED [31:00] */
#define Wr_switch_PAGE_0C_FLOWCON_DEBUG_BUS_PAGE_0C_FLOWCON_DEBUG_BUS_RESERVED(x) WriteReg(SWITCH_PAGE_0C_FLOWCON_DEBUG_BUS,x)
#define Rd_switch_PAGE_0C_FLOWCON_DEBUG_BUS_PAGE_0C_FLOWCON_DEBUG_BUS_RESERVED(x) ReadReg(SWITCH_PAGE_0C_FLOWCON_DEBUG_BUS)
#define SWITCH_PAGE_0C_FLOWCON_DEBUG_BUS_PAGE_0C_FLOWCON_DEBUG_BUS_RESERVED_MASK 0xffffffff
#define SWITCH_PAGE_0C_FLOWCON_DEBUG_BUS_PAGE_0C_FLOWCON_DEBUG_BUS_RESERVED_ALIGN 0
#define SWITCH_PAGE_0C_FLOWCON_DEBUG_BUS_PAGE_0C_FLOWCON_DEBUG_BUS_RESERVED_BITS 32
#define SWITCH_PAGE_0C_FLOWCON_DEBUG_BUS_PAGE_0C_FLOWCON_DEBUG_BUS_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q0_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q1_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q2_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q3_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q4_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q5_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q6_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7 :: PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_PAGE_0D_FC_IMP0_TXQ_THD_RSV_Q7_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q0_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q1_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q2_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q3_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q4_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q5_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q6_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7 :: PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_PAGE_0D_FC_IMP0_TXQ_THD_HYST_Q7_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7 :: PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q0_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q1_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q2_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q3_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q4_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q5_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q6_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7 :: PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_PAGE_0D_FC_IMP0_TXQ_THD_DROP_Q7_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7 :: PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7 :: PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7,0xf800,11)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7 :: PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7,0x7ff,0)
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_PAGE_0D_FC_IMP0_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_REG_SPARE0 :: PAGE_0D_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0 [15:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_REG_SPARE0_PAGE_0D_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0(x) WriteReg16(SWITCH_PAGE_0D_FC_IMP0_REG_SPARE0,x)
#define Rd_switch_PAGE_0D_FC_IMP0_REG_SPARE0_PAGE_0D_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0(x) ReadReg16(SWITCH_PAGE_0D_FC_IMP0_REG_SPARE0)
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE0_PAGE_0D_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_MASK 0xffff
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE0_PAGE_0D_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE0_PAGE_0D_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_BITS 16
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE0_PAGE_0D_FC_IMP0_REG_SPARE0_FC_IMP0_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0D_FC_IMP0_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_0D_FC_IMP0_REG_SPARE1 :: PAGE_0D_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1 [15:00] */
#define Wr_switch_PAGE_0D_FC_IMP0_REG_SPARE1_PAGE_0D_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1(x) WriteReg16(SWITCH_PAGE_0D_FC_IMP0_REG_SPARE1,x)
#define Rd_switch_PAGE_0D_FC_IMP0_REG_SPARE1_PAGE_0D_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1(x) ReadReg16(SWITCH_PAGE_0D_FC_IMP0_REG_SPARE1)
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE1_PAGE_0D_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_MASK 0xffff
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE1_PAGE_0D_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE1_PAGE_0D_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_BITS 16
#define SWITCH_PAGE_0D_FC_IMP0_REG_SPARE1_PAGE_0D_FC_IMP0_REG_SPARE1_FC_IMP0_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q0_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q1_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q2_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q3_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q4_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q5_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q6_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_RSV_Q7_TXQ_RSV_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q0_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q1_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q2_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q3_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q4_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q5_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q6_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_HYST_Q7_TXQ_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q0_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q1_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q2_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q3_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q4_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q5_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q6_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_PAUSE_Q7_TXQ_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q0_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q1_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q2_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q3_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q4_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q5_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q6_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7 :: PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TXQ_THD_DROP_Q7_TXQ_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q0_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q1_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q2_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q3_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q4_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q5_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q6_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_HYST_Q7_TOTAL_HYST_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q0_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q1_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q2_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q3_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q4_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q5_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q6_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_PAUSE_Q7_TOTAL_PAUSE_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q0_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q1_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q2_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q3_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q4_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q5_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q6_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_RESERVED [15:11] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7,0xf800,11,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7,0xf800,11)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_RESERVED_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_RESERVED_BITS 5
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_RESERVED_SHIFT 11

/* switch :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7 :: PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD [10:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD(x) WriteRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7,0x7ff,0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD(x) ReadRegBits16(SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7,0x7ff,0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_MASK 0x07ff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_BITS 11
#define SWITCH_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_PAGE_0E_FC_WAN_IMP1_TOTAL_THD_DROP_Q7_TOTAL_DROP_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_REG_SPARE0 :: PAGE_0E_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0 [15:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0(x) WriteReg16(SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE0,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0(x) ReadReg16(SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE0)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_MASK 0xffff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_BITS 16
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_PAGE_0E_FC_WAN_IMP1_REG_SPARE0_FC_WAN_IMP1_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_0E_FC_WAN_IMP1_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_0E_FC_WAN_IMP1_REG_SPARE1 :: PAGE_0E_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1 [15:00] */
#define Wr_switch_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1(x) WriteReg16(SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE1,x)
#define Rd_switch_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1(x) ReadReg16(SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE1)
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_MASK 0xffff
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_BITS 16
#define SWITCH_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_PAGE_0E_FC_WAN_IMP1_REG_SPARE1_FC_WAN_IMP1_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxOctets
 ***************************************************************************/
/* switch :: PAGE_20_TxOctets :: PAGE_20_TxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_20_TxOctets_PAGE_20_TxOctets_COUNT(x) WriteReg(SWITCH_PAGE_20_TXOCTETS,x)
#define Rd_switch_PAGE_20_TxOctets_PAGE_20_TxOctets_COUNT(x) ReadReg(SWITCH_PAGE_20_TXOCTETS)
#define SWITCH_PAGE_20_TXOCTETS_PAGE_20_TXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_20_TXOCTETS_PAGE_20_TXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_20_TXOCTETS_PAGE_20_TXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_20_TXOCTETS_PAGE_20_TXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_TxDropPkts
 ***************************************************************************/
/* switch :: PAGE_20_TxDropPkts :: PAGE_20_TxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxDropPkts_PAGE_20_TxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_20_TXDROPPKTS,x)
#define Rd_switch_PAGE_20_TxDropPkts_PAGE_20_TxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_20_TXDROPPKTS)
#define SWITCH_PAGE_20_TXDROPPKTS_PAGE_20_TXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_20_TXDROPPKTS_PAGE_20_TXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_20_TXDROPPKTS_PAGE_20_TXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_20_TXDROPPKTS_PAGE_20_TXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_20_TxQPKTQ0
 ***************************************************************************/
/* switch :: PAGE_20_TxQPKTQ0 :: PAGE_20_TxQPKTQ0_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxQPKTQ0_PAGE_20_TxQPKTQ0_COUNT(x) WriteReg(SWITCH_PAGE_20_TXQPKTQ0,x)
#define Rd_switch_PAGE_20_TxQPKTQ0_PAGE_20_TxQPKTQ0_COUNT(x) ReadReg(SWITCH_PAGE_20_TXQPKTQ0)
#define SWITCH_PAGE_20_TXQPKTQ0_PAGE_20_TXQPKTQ0_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_20_TXQPKTQ0_PAGE_20_TXQPKTQ0_COUNT_ALIGN       0
#define SWITCH_PAGE_20_TXQPKTQ0_PAGE_20_TXQPKTQ0_COUNT_BITS        32
#define SWITCH_PAGE_20_TXQPKTQ0_PAGE_20_TXQPKTQ0_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_TxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_20_TxBroadcastPkts :: PAGE_20_TxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxBroadcastPkts_PAGE_20_TxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_20_TXBROADCASTPKTS,x)
#define Rd_switch_PAGE_20_TxBroadcastPkts_PAGE_20_TxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_20_TXBROADCASTPKTS)
#define SWITCH_PAGE_20_TXBROADCASTPKTS_PAGE_20_TXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXBROADCASTPKTS_PAGE_20_TXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXBROADCASTPKTS_PAGE_20_TXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXBROADCASTPKTS_PAGE_20_TXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_20_TxMulticastPkts :: PAGE_20_TxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxMulticastPkts_PAGE_20_TxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_20_TXMULTICASTPKTS,x)
#define Rd_switch_PAGE_20_TxMulticastPkts_PAGE_20_TxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_20_TXMULTICASTPKTS)
#define SWITCH_PAGE_20_TXMULTICASTPKTS_PAGE_20_TXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXMULTICASTPKTS_PAGE_20_TXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXMULTICASTPKTS_PAGE_20_TXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXMULTICASTPKTS_PAGE_20_TXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_20_TxUnicastPkts :: PAGE_20_TxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxUnicastPkts_PAGE_20_TxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_20_TXUNICASTPKTS,x)
#define Rd_switch_PAGE_20_TxUnicastPkts_PAGE_20_TxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_20_TXUNICASTPKTS)
#define SWITCH_PAGE_20_TXUNICASTPKTS_PAGE_20_TXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXUNICASTPKTS_PAGE_20_TXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXUNICASTPKTS_PAGE_20_TXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXUNICASTPKTS_PAGE_20_TXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxCollisions
 ***************************************************************************/
/* switch :: PAGE_20_TxCollisions :: PAGE_20_TxCollisions_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxCollisions_PAGE_20_TxCollisions_COUNT(x) WriteReg(SWITCH_PAGE_20_TXCOLLISIONS,x)
#define Rd_switch_PAGE_20_TxCollisions_PAGE_20_TxCollisions_COUNT(x) ReadReg(SWITCH_PAGE_20_TXCOLLISIONS)
#define SWITCH_PAGE_20_TXCOLLISIONS_PAGE_20_TXCOLLISIONS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXCOLLISIONS_PAGE_20_TXCOLLISIONS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXCOLLISIONS_PAGE_20_TXCOLLISIONS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXCOLLISIONS_PAGE_20_TXCOLLISIONS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxSingleCollision
 ***************************************************************************/
/* switch :: PAGE_20_TxSingleCollision :: PAGE_20_TxSingleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxSingleCollision_PAGE_20_TxSingleCollision_COUNT(x) WriteReg(SWITCH_PAGE_20_TXSINGLECOLLISION,x)
#define Rd_switch_PAGE_20_TxSingleCollision_PAGE_20_TxSingleCollision_COUNT(x) ReadReg(SWITCH_PAGE_20_TXSINGLECOLLISION)
#define SWITCH_PAGE_20_TXSINGLECOLLISION_PAGE_20_TXSINGLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXSINGLECOLLISION_PAGE_20_TXSINGLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXSINGLECOLLISION_PAGE_20_TXSINGLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_20_TXSINGLECOLLISION_PAGE_20_TXSINGLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxMultipleCollision
 ***************************************************************************/
/* switch :: PAGE_20_TxMultipleCollision :: PAGE_20_TxMultipleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxMultipleCollision_PAGE_20_TxMultipleCollision_COUNT(x) WriteReg(SWITCH_PAGE_20_TXMULTIPLECOLLISION,x)
#define Rd_switch_PAGE_20_TxMultipleCollision_PAGE_20_TxMultipleCollision_COUNT(x) ReadReg(SWITCH_PAGE_20_TXMULTIPLECOLLISION)
#define SWITCH_PAGE_20_TXMULTIPLECOLLISION_PAGE_20_TXMULTIPLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXMULTIPLECOLLISION_PAGE_20_TXMULTIPLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXMULTIPLECOLLISION_PAGE_20_TXMULTIPLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_20_TXMULTIPLECOLLISION_PAGE_20_TXMULTIPLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxDeferredTransmit
 ***************************************************************************/
/* switch :: PAGE_20_TxDeferredTransmit :: PAGE_20_TxDeferredTransmit_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxDeferredTransmit_PAGE_20_TxDeferredTransmit_COUNT(x) WriteReg(SWITCH_PAGE_20_TXDEFERREDTRANSMIT,x)
#define Rd_switch_PAGE_20_TxDeferredTransmit_PAGE_20_TxDeferredTransmit_COUNT(x) ReadReg(SWITCH_PAGE_20_TXDEFERREDTRANSMIT)
#define SWITCH_PAGE_20_TXDEFERREDTRANSMIT_PAGE_20_TXDEFERREDTRANSMIT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXDEFERREDTRANSMIT_PAGE_20_TXDEFERREDTRANSMIT_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXDEFERREDTRANSMIT_PAGE_20_TXDEFERREDTRANSMIT_COUNT_BITS 32
#define SWITCH_PAGE_20_TXDEFERREDTRANSMIT_PAGE_20_TXDEFERREDTRANSMIT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxLateCollision
 ***************************************************************************/
/* switch :: PAGE_20_TxLateCollision :: PAGE_20_TxLateCollision_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxLateCollision_PAGE_20_TxLateCollision_COUNT(x) WriteReg(SWITCH_PAGE_20_TXLATECOLLISION,x)
#define Rd_switch_PAGE_20_TxLateCollision_PAGE_20_TxLateCollision_COUNT(x) ReadReg(SWITCH_PAGE_20_TXLATECOLLISION)
#define SWITCH_PAGE_20_TXLATECOLLISION_PAGE_20_TXLATECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXLATECOLLISION_PAGE_20_TXLATECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXLATECOLLISION_PAGE_20_TXLATECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_20_TXLATECOLLISION_PAGE_20_TXLATECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxExcessiveCollision
 ***************************************************************************/
/* switch :: PAGE_20_TxExcessiveCollision :: PAGE_20_TxExcessiveCollision_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxExcessiveCollision_PAGE_20_TxExcessiveCollision_COUNT(x) WriteReg(SWITCH_PAGE_20_TXEXCESSIVECOLLISION,x)
#define Rd_switch_PAGE_20_TxExcessiveCollision_PAGE_20_TxExcessiveCollision_COUNT(x) ReadReg(SWITCH_PAGE_20_TXEXCESSIVECOLLISION)
#define SWITCH_PAGE_20_TXEXCESSIVECOLLISION_PAGE_20_TXEXCESSIVECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXEXCESSIVECOLLISION_PAGE_20_TXEXCESSIVECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXEXCESSIVECOLLISION_PAGE_20_TXEXCESSIVECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_20_TXEXCESSIVECOLLISION_PAGE_20_TXEXCESSIVECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxFrameInDisc
 ***************************************************************************/
/* switch :: PAGE_20_TxFrameInDisc :: PAGE_20_TxFrameInDisc_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxFrameInDisc_PAGE_20_TxFrameInDisc_COUNT(x) WriteReg(SWITCH_PAGE_20_TXFRAMEINDISC,x)
#define Rd_switch_PAGE_20_TxFrameInDisc_PAGE_20_TxFrameInDisc_COUNT(x) ReadReg(SWITCH_PAGE_20_TXFRAMEINDISC)
#define SWITCH_PAGE_20_TXFRAMEINDISC_PAGE_20_TXFRAMEINDISC_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXFRAMEINDISC_PAGE_20_TXFRAMEINDISC_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXFRAMEINDISC_PAGE_20_TXFRAMEINDISC_COUNT_BITS 32
#define SWITCH_PAGE_20_TXFRAMEINDISC_PAGE_20_TXFRAMEINDISC_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxPausePkts
 ***************************************************************************/
/* switch :: PAGE_20_TxPausePkts :: PAGE_20_TxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxPausePkts_PAGE_20_TxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_20_TXPAUSEPKTS,x)
#define Rd_switch_PAGE_20_TxPausePkts_PAGE_20_TxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_20_TXPAUSEPKTS)
#define SWITCH_PAGE_20_TXPAUSEPKTS_PAGE_20_TXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_20_TXPAUSEPKTS_PAGE_20_TXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXPAUSEPKTS_PAGE_20_TXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_20_TXPAUSEPKTS_PAGE_20_TXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxQPKTQ1
 ***************************************************************************/
/* switch :: PAGE_20_TxQPKTQ1 :: PAGE_20_TxQPKTQ1_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxQPKTQ1_PAGE_20_TxQPKTQ1_COUNT(x) WriteReg(SWITCH_PAGE_20_TXQPKTQ1,x)
#define Rd_switch_PAGE_20_TxQPKTQ1_PAGE_20_TxQPKTQ1_COUNT(x) ReadReg(SWITCH_PAGE_20_TXQPKTQ1)
#define SWITCH_PAGE_20_TXQPKTQ1_PAGE_20_TXQPKTQ1_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_20_TXQPKTQ1_PAGE_20_TXQPKTQ1_COUNT_ALIGN       0
#define SWITCH_PAGE_20_TXQPKTQ1_PAGE_20_TXQPKTQ1_COUNT_BITS        32
#define SWITCH_PAGE_20_TXQPKTQ1_PAGE_20_TXQPKTQ1_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_TxQPKTQ2
 ***************************************************************************/
/* switch :: PAGE_20_TxQPKTQ2 :: PAGE_20_TxQPKTQ2_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxQPKTQ2_PAGE_20_TxQPKTQ2_COUNT(x) WriteReg(SWITCH_PAGE_20_TXQPKTQ2,x)
#define Rd_switch_PAGE_20_TxQPKTQ2_PAGE_20_TxQPKTQ2_COUNT(x) ReadReg(SWITCH_PAGE_20_TXQPKTQ2)
#define SWITCH_PAGE_20_TXQPKTQ2_PAGE_20_TXQPKTQ2_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_20_TXQPKTQ2_PAGE_20_TXQPKTQ2_COUNT_ALIGN       0
#define SWITCH_PAGE_20_TXQPKTQ2_PAGE_20_TXQPKTQ2_COUNT_BITS        32
#define SWITCH_PAGE_20_TXQPKTQ2_PAGE_20_TXQPKTQ2_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_TxQPKTQ3
 ***************************************************************************/
/* switch :: PAGE_20_TxQPKTQ3 :: PAGE_20_TxQPKTQ3_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxQPKTQ3_PAGE_20_TxQPKTQ3_COUNT(x) WriteReg(SWITCH_PAGE_20_TXQPKTQ3,x)
#define Rd_switch_PAGE_20_TxQPKTQ3_PAGE_20_TxQPKTQ3_COUNT(x) ReadReg(SWITCH_PAGE_20_TXQPKTQ3)
#define SWITCH_PAGE_20_TXQPKTQ3_PAGE_20_TXQPKTQ3_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_20_TXQPKTQ3_PAGE_20_TXQPKTQ3_COUNT_ALIGN       0
#define SWITCH_PAGE_20_TXQPKTQ3_PAGE_20_TXQPKTQ3_COUNT_BITS        32
#define SWITCH_PAGE_20_TXQPKTQ3_PAGE_20_TXQPKTQ3_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_TxQPKTQ4
 ***************************************************************************/
/* switch :: PAGE_20_TxQPKTQ4 :: PAGE_20_TxQPKTQ4_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxQPKTQ4_PAGE_20_TxQPKTQ4_COUNT(x) WriteReg(SWITCH_PAGE_20_TXQPKTQ4,x)
#define Rd_switch_PAGE_20_TxQPKTQ4_PAGE_20_TxQPKTQ4_COUNT(x) ReadReg(SWITCH_PAGE_20_TXQPKTQ4)
#define SWITCH_PAGE_20_TXQPKTQ4_PAGE_20_TXQPKTQ4_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_20_TXQPKTQ4_PAGE_20_TXQPKTQ4_COUNT_ALIGN       0
#define SWITCH_PAGE_20_TXQPKTQ4_PAGE_20_TXQPKTQ4_COUNT_BITS        32
#define SWITCH_PAGE_20_TXQPKTQ4_PAGE_20_TXQPKTQ4_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_TxQPKTQ5
 ***************************************************************************/
/* switch :: PAGE_20_TxQPKTQ5 :: PAGE_20_TxQPKTQ5_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxQPKTQ5_PAGE_20_TxQPKTQ5_COUNT(x) WriteReg(SWITCH_PAGE_20_TXQPKTQ5,x)
#define Rd_switch_PAGE_20_TxQPKTQ5_PAGE_20_TxQPKTQ5_COUNT(x) ReadReg(SWITCH_PAGE_20_TXQPKTQ5)
#define SWITCH_PAGE_20_TXQPKTQ5_PAGE_20_TXQPKTQ5_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_20_TXQPKTQ5_PAGE_20_TXQPKTQ5_COUNT_ALIGN       0
#define SWITCH_PAGE_20_TXQPKTQ5_PAGE_20_TXQPKTQ5_COUNT_BITS        32
#define SWITCH_PAGE_20_TXQPKTQ5_PAGE_20_TXQPKTQ5_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_RxOctets
 ***************************************************************************/
/* switch :: PAGE_20_RxOctets :: PAGE_20_RxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_20_RxOctets_PAGE_20_RxOctets_COUNT(x) WriteReg(SWITCH_PAGE_20_RXOCTETS,x)
#define Rd_switch_PAGE_20_RxOctets_PAGE_20_RxOctets_COUNT(x) ReadReg(SWITCH_PAGE_20_RXOCTETS)
#define SWITCH_PAGE_20_RXOCTETS_PAGE_20_RXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_20_RXOCTETS_PAGE_20_RXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_20_RXOCTETS_PAGE_20_RXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_20_RXOCTETS_PAGE_20_RXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_RxUndersizePkts
 ***************************************************************************/
/* switch :: PAGE_20_RxUndersizePkts :: PAGE_20_RxUndersizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxUndersizePkts_PAGE_20_RxUndersizePkts_COUNT(x) WriteReg(SWITCH_PAGE_20_RXUNDERSIZEPKTS,x)
#define Rd_switch_PAGE_20_RxUndersizePkts_PAGE_20_RxUndersizePkts_COUNT(x) ReadReg(SWITCH_PAGE_20_RXUNDERSIZEPKTS)
#define SWITCH_PAGE_20_RXUNDERSIZEPKTS_PAGE_20_RXUNDERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXUNDERSIZEPKTS_PAGE_20_RXUNDERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXUNDERSIZEPKTS_PAGE_20_RXUNDERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXUNDERSIZEPKTS_PAGE_20_RXUNDERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxPausePkts
 ***************************************************************************/
/* switch :: PAGE_20_RxPausePkts :: PAGE_20_RxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxPausePkts_PAGE_20_RxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_20_RXPAUSEPKTS,x)
#define Rd_switch_PAGE_20_RxPausePkts_PAGE_20_RxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_20_RXPAUSEPKTS)
#define SWITCH_PAGE_20_RXPAUSEPKTS_PAGE_20_RXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_20_RXPAUSEPKTS_PAGE_20_RXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXPAUSEPKTS_PAGE_20_RXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_20_RXPAUSEPKTS_PAGE_20_RXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_20_RxPkts64Octets :: PAGE_20_RxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxPkts64Octets_PAGE_20_RxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_RXPKTS64OCTETS,x)
#define Rd_switch_PAGE_20_RxPkts64Octets_PAGE_20_RxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_RXPKTS64OCTETS)
#define SWITCH_PAGE_20_RXPKTS64OCTETS_PAGE_20_RXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXPKTS64OCTETS_PAGE_20_RXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXPKTS64OCTETS_PAGE_20_RXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXPKTS64OCTETS_PAGE_20_RXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_20_RxPkts65to127Octets :: PAGE_20_RxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxPkts65to127Octets_PAGE_20_RxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_RXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_20_RxPkts65to127Octets_PAGE_20_RxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_RXPKTS65TO127OCTETS)
#define SWITCH_PAGE_20_RXPKTS65TO127OCTETS_PAGE_20_RXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXPKTS65TO127OCTETS_PAGE_20_RXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXPKTS65TO127OCTETS_PAGE_20_RXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXPKTS65TO127OCTETS_PAGE_20_RXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_20_RxPkts128to255Octets :: PAGE_20_RxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxPkts128to255Octets_PAGE_20_RxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_RXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_20_RxPkts128to255Octets_PAGE_20_RxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_RXPKTS128TO255OCTETS)
#define SWITCH_PAGE_20_RXPKTS128TO255OCTETS_PAGE_20_RXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXPKTS128TO255OCTETS_PAGE_20_RXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXPKTS128TO255OCTETS_PAGE_20_RXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXPKTS128TO255OCTETS_PAGE_20_RXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_20_RxPkts256to511Octets :: PAGE_20_RxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxPkts256to511Octets_PAGE_20_RxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_RXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_20_RxPkts256to511Octets_PAGE_20_RxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_RXPKTS256TO511OCTETS)
#define SWITCH_PAGE_20_RXPKTS256TO511OCTETS_PAGE_20_RXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXPKTS256TO511OCTETS_PAGE_20_RXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXPKTS256TO511OCTETS_PAGE_20_RXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXPKTS256TO511OCTETS_PAGE_20_RXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_20_RxPkts512to1023Octets :: PAGE_20_RxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxPkts512to1023Octets_PAGE_20_RxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_RXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_20_RxPkts512to1023Octets_PAGE_20_RxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_RXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_20_RXPKTS512TO1023OCTETS_PAGE_20_RXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXPKTS512TO1023OCTETS_PAGE_20_RXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXPKTS512TO1023OCTETS_PAGE_20_RXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXPKTS512TO1023OCTETS_PAGE_20_RXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_20_RxPkts1024toMaxPktOctets :: PAGE_20_RxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxPkts1024toMaxPktOctets_PAGE_20_RxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_20_RXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_20_RxPkts1024toMaxPktOctets_PAGE_20_RxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_20_RXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_20_RXPKTS1024TOMAXPKTOCTETS_PAGE_20_RXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXPKTS1024TOMAXPKTOCTETS_PAGE_20_RXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXPKTS1024TOMAXPKTOCTETS_PAGE_20_RXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXPKTS1024TOMAXPKTOCTETS_PAGE_20_RXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxOversizePkts
 ***************************************************************************/
/* switch :: PAGE_20_RxOversizePkts :: PAGE_20_RxOversizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxOversizePkts_PAGE_20_RxOversizePkts_COUNT(x) WriteReg(SWITCH_PAGE_20_RXOVERSIZEPKTS,x)
#define Rd_switch_PAGE_20_RxOversizePkts_PAGE_20_RxOversizePkts_COUNT(x) ReadReg(SWITCH_PAGE_20_RXOVERSIZEPKTS)
#define SWITCH_PAGE_20_RXOVERSIZEPKTS_PAGE_20_RXOVERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXOVERSIZEPKTS_PAGE_20_RXOVERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXOVERSIZEPKTS_PAGE_20_RXOVERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXOVERSIZEPKTS_PAGE_20_RXOVERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxJabbers
 ***************************************************************************/
/* switch :: PAGE_20_RxJabbers :: PAGE_20_RxJabbers_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxJabbers_PAGE_20_RxJabbers_COUNT(x) WriteReg(SWITCH_PAGE_20_RXJABBERS,x)
#define Rd_switch_PAGE_20_RxJabbers_PAGE_20_RxJabbers_COUNT(x) ReadReg(SWITCH_PAGE_20_RXJABBERS)
#define SWITCH_PAGE_20_RXJABBERS_PAGE_20_RXJABBERS_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_20_RXJABBERS_PAGE_20_RXJABBERS_COUNT_ALIGN     0
#define SWITCH_PAGE_20_RXJABBERS_PAGE_20_RXJABBERS_COUNT_BITS      32
#define SWITCH_PAGE_20_RXJABBERS_PAGE_20_RXJABBERS_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_20_RxAlignmentErrors
 ***************************************************************************/
/* switch :: PAGE_20_RxAlignmentErrors :: PAGE_20_RxAlignmentErrors_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxAlignmentErrors_PAGE_20_RxAlignmentErrors_COUNT(x) WriteReg(SWITCH_PAGE_20_RXALIGNMENTERRORS,x)
#define Rd_switch_PAGE_20_RxAlignmentErrors_PAGE_20_RxAlignmentErrors_COUNT(x) ReadReg(SWITCH_PAGE_20_RXALIGNMENTERRORS)
#define SWITCH_PAGE_20_RXALIGNMENTERRORS_PAGE_20_RXALIGNMENTERRORS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXALIGNMENTERRORS_PAGE_20_RXALIGNMENTERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXALIGNMENTERRORS_PAGE_20_RXALIGNMENTERRORS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXALIGNMENTERRORS_PAGE_20_RXALIGNMENTERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxFCSErrors
 ***************************************************************************/
/* switch :: PAGE_20_RxFCSErrors :: PAGE_20_RxFCSErrors_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxFCSErrors_PAGE_20_RxFCSErrors_COUNT(x) WriteReg(SWITCH_PAGE_20_RXFCSERRORS,x)
#define Rd_switch_PAGE_20_RxFCSErrors_PAGE_20_RxFCSErrors_COUNT(x) ReadReg(SWITCH_PAGE_20_RXFCSERRORS)
#define SWITCH_PAGE_20_RXFCSERRORS_PAGE_20_RXFCSERRORS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_20_RXFCSERRORS_PAGE_20_RXFCSERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXFCSERRORS_PAGE_20_RXFCSERRORS_COUNT_BITS  32
#define SWITCH_PAGE_20_RXFCSERRORS_PAGE_20_RXFCSERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxGoodOctets
 ***************************************************************************/
/* switch :: PAGE_20_RxGoodOctets :: PAGE_20_RxGoodOctets_COUNT [63:00] */
#define Wr_switch_PAGE_20_RxGoodOctets_PAGE_20_RxGoodOctets_COUNT(x) WriteReg(SWITCH_PAGE_20_RXGOODOCTETS,x)
#define Rd_switch_PAGE_20_RxGoodOctets_PAGE_20_RxGoodOctets_COUNT(x) ReadReg(SWITCH_PAGE_20_RXGOODOCTETS)
#define SWITCH_PAGE_20_RXGOODOCTETS_PAGE_20_RXGOODOCTETS_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_20_RXGOODOCTETS_PAGE_20_RXGOODOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXGOODOCTETS_PAGE_20_RXGOODOCTETS_COUNT_BITS 64
#define SWITCH_PAGE_20_RXGOODOCTETS_PAGE_20_RXGOODOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxDropPkts
 ***************************************************************************/
/* switch :: PAGE_20_RxDropPkts :: PAGE_20_RxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxDropPkts_PAGE_20_RxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_20_RXDROPPKTS,x)
#define Rd_switch_PAGE_20_RxDropPkts_PAGE_20_RxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_20_RXDROPPKTS)
#define SWITCH_PAGE_20_RXDROPPKTS_PAGE_20_RXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_20_RXDROPPKTS_PAGE_20_RXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_20_RXDROPPKTS_PAGE_20_RXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_20_RXDROPPKTS_PAGE_20_RXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_20_RxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_20_RxUnicastPkts :: PAGE_20_RxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxUnicastPkts_PAGE_20_RxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_20_RXUNICASTPKTS,x)
#define Rd_switch_PAGE_20_RxUnicastPkts_PAGE_20_RxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_20_RXUNICASTPKTS)
#define SWITCH_PAGE_20_RXUNICASTPKTS_PAGE_20_RXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXUNICASTPKTS_PAGE_20_RXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXUNICASTPKTS_PAGE_20_RXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXUNICASTPKTS_PAGE_20_RXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_20_RxMulticastPkts :: PAGE_20_RxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxMulticastPkts_PAGE_20_RxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_20_RXMULTICASTPKTS,x)
#define Rd_switch_PAGE_20_RxMulticastPkts_PAGE_20_RxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_20_RXMULTICASTPKTS)
#define SWITCH_PAGE_20_RXMULTICASTPKTS_PAGE_20_RXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXMULTICASTPKTS_PAGE_20_RXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXMULTICASTPKTS_PAGE_20_RXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXMULTICASTPKTS_PAGE_20_RXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_20_RxBroadcastPkts :: PAGE_20_RxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxBroadcastPkts_PAGE_20_RxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_20_RXBROADCASTPKTS,x)
#define Rd_switch_PAGE_20_RxBroadcastPkts_PAGE_20_RxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_20_RXBROADCASTPKTS)
#define SWITCH_PAGE_20_RXBROADCASTPKTS_PAGE_20_RXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_RXBROADCASTPKTS_PAGE_20_RXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXBROADCASTPKTS_PAGE_20_RXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_20_RXBROADCASTPKTS_PAGE_20_RXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxSAChanges
 ***************************************************************************/
/* switch :: PAGE_20_RxSAChanges :: PAGE_20_RxSAChanges_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxSAChanges_PAGE_20_RxSAChanges_COUNT(x) WriteReg(SWITCH_PAGE_20_RXSACHANGES,x)
#define Rd_switch_PAGE_20_RxSAChanges_PAGE_20_RxSAChanges_COUNT(x) ReadReg(SWITCH_PAGE_20_RXSACHANGES)
#define SWITCH_PAGE_20_RXSACHANGES_PAGE_20_RXSACHANGES_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_20_RXSACHANGES_PAGE_20_RXSACHANGES_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXSACHANGES_PAGE_20_RXSACHANGES_COUNT_BITS  32
#define SWITCH_PAGE_20_RXSACHANGES_PAGE_20_RXSACHANGES_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxFragments
 ***************************************************************************/
/* switch :: PAGE_20_RxFragments :: PAGE_20_RxFragments_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxFragments_PAGE_20_RxFragments_COUNT(x) WriteReg(SWITCH_PAGE_20_RXFRAGMENTS,x)
#define Rd_switch_PAGE_20_RxFragments_PAGE_20_RxFragments_COUNT(x) ReadReg(SWITCH_PAGE_20_RXFRAGMENTS)
#define SWITCH_PAGE_20_RXFRAGMENTS_PAGE_20_RXFRAGMENTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_20_RXFRAGMENTS_PAGE_20_RXFRAGMENTS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_RXFRAGMENTS_PAGE_20_RXFRAGMENTS_COUNT_BITS  32
#define SWITCH_PAGE_20_RXFRAGMENTS_PAGE_20_RXFRAGMENTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxJumboPkt
 ***************************************************************************/
/* switch :: PAGE_20_RxJumboPkt :: PAGE_20_RxJumboPkt_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxJumboPkt_PAGE_20_RxJumboPkt_COUNT(x) WriteReg(SWITCH_PAGE_20_RXJUMBOPKT,x)
#define Rd_switch_PAGE_20_RxJumboPkt_PAGE_20_RxJumboPkt_COUNT(x) ReadReg(SWITCH_PAGE_20_RXJUMBOPKT)
#define SWITCH_PAGE_20_RXJUMBOPKT_PAGE_20_RXJUMBOPKT_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_20_RXJUMBOPKT_PAGE_20_RXJUMBOPKT_COUNT_ALIGN   0
#define SWITCH_PAGE_20_RXJUMBOPKT_PAGE_20_RXJUMBOPKT_COUNT_BITS    32
#define SWITCH_PAGE_20_RXJUMBOPKT_PAGE_20_RXJUMBOPKT_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_20_RxSymblErr
 ***************************************************************************/
/* switch :: PAGE_20_RxSymblErr :: PAGE_20_RxSymblErr_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxSymblErr_PAGE_20_RxSymblErr_COUNT(x) WriteReg(SWITCH_PAGE_20_RXSYMBLERR,x)
#define Rd_switch_PAGE_20_RxSymblErr_PAGE_20_RxSymblErr_COUNT(x) ReadReg(SWITCH_PAGE_20_RXSYMBLERR)
#define SWITCH_PAGE_20_RXSYMBLERR_PAGE_20_RXSYMBLERR_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_20_RXSYMBLERR_PAGE_20_RXSYMBLERR_COUNT_ALIGN   0
#define SWITCH_PAGE_20_RXSYMBLERR_PAGE_20_RXSYMBLERR_COUNT_BITS    32
#define SWITCH_PAGE_20_RXSYMBLERR_PAGE_20_RXSYMBLERR_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_20_InRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_20_InRangeErrCount :: PAGE_20_InRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_20_InRangeErrCount_PAGE_20_InRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_20_INRANGEERRCOUNT,x)
#define Rd_switch_PAGE_20_InRangeErrCount_PAGE_20_InRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_20_INRANGEERRCOUNT)
#define SWITCH_PAGE_20_INRANGEERRCOUNT_PAGE_20_INRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_INRANGEERRCOUNT_PAGE_20_INRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_20_INRANGEERRCOUNT_PAGE_20_INRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_20_INRANGEERRCOUNT_PAGE_20_INRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_OutRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_20_OutRangeErrCount :: PAGE_20_OutRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_20_OutRangeErrCount_PAGE_20_OutRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_20_OUTRANGEERRCOUNT,x)
#define Rd_switch_PAGE_20_OutRangeErrCount_PAGE_20_OutRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_20_OUTRANGEERRCOUNT)
#define SWITCH_PAGE_20_OUTRANGEERRCOUNT_PAGE_20_OUTRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_OUTRANGEERRCOUNT_PAGE_20_OUTRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_20_OUTRANGEERRCOUNT_PAGE_20_OUTRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_20_OUTRANGEERRCOUNT_PAGE_20_OUTRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_EEE_LPI_EVENT
 ***************************************************************************/
/* switch :: PAGE_20_EEE_LPI_EVENT :: PAGE_20_EEE_LPI_EVENT_COUNT [31:00] */
#define Wr_switch_PAGE_20_EEE_LPI_EVENT_PAGE_20_EEE_LPI_EVENT_COUNT(x) WriteReg(SWITCH_PAGE_20_EEE_LPI_EVENT,x)
#define Rd_switch_PAGE_20_EEE_LPI_EVENT_PAGE_20_EEE_LPI_EVENT_COUNT(x) ReadReg(SWITCH_PAGE_20_EEE_LPI_EVENT)
#define SWITCH_PAGE_20_EEE_LPI_EVENT_PAGE_20_EEE_LPI_EVENT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_EEE_LPI_EVENT_PAGE_20_EEE_LPI_EVENT_COUNT_ALIGN 0
#define SWITCH_PAGE_20_EEE_LPI_EVENT_PAGE_20_EEE_LPI_EVENT_COUNT_BITS 32
#define SWITCH_PAGE_20_EEE_LPI_EVENT_PAGE_20_EEE_LPI_EVENT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_EEE_LPI_DURATION
 ***************************************************************************/
/* switch :: PAGE_20_EEE_LPI_DURATION :: PAGE_20_EEE_LPI_DURATION_COUNT [31:00] */
#define Wr_switch_PAGE_20_EEE_LPI_DURATION_PAGE_20_EEE_LPI_DURATION_COUNT(x) WriteReg(SWITCH_PAGE_20_EEE_LPI_DURATION,x)
#define Rd_switch_PAGE_20_EEE_LPI_DURATION_PAGE_20_EEE_LPI_DURATION_COUNT(x) ReadReg(SWITCH_PAGE_20_EEE_LPI_DURATION)
#define SWITCH_PAGE_20_EEE_LPI_DURATION_PAGE_20_EEE_LPI_DURATION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_EEE_LPI_DURATION_PAGE_20_EEE_LPI_DURATION_COUNT_ALIGN 0
#define SWITCH_PAGE_20_EEE_LPI_DURATION_PAGE_20_EEE_LPI_DURATION_COUNT_BITS 32
#define SWITCH_PAGE_20_EEE_LPI_DURATION_PAGE_20_EEE_LPI_DURATION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_RxDiscard
 ***************************************************************************/
/* switch :: PAGE_20_RxDiscard :: PAGE_20_RxDiscard_COUNT [31:00] */
#define Wr_switch_PAGE_20_RxDiscard_PAGE_20_RxDiscard_COUNT(x) WriteReg(SWITCH_PAGE_20_RXDISCARD,x)
#define Rd_switch_PAGE_20_RxDiscard_PAGE_20_RxDiscard_COUNT(x) ReadReg(SWITCH_PAGE_20_RXDISCARD)
#define SWITCH_PAGE_20_RXDISCARD_PAGE_20_RXDISCARD_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_20_RXDISCARD_PAGE_20_RXDISCARD_COUNT_ALIGN     0
#define SWITCH_PAGE_20_RXDISCARD_PAGE_20_RXDISCARD_COUNT_BITS      32
#define SWITCH_PAGE_20_RXDISCARD_PAGE_20_RXDISCARD_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_20_TxQPKTQ6
 ***************************************************************************/
/* switch :: PAGE_20_TxQPKTQ6 :: PAGE_20_TxQPKTQ6_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxQPKTQ6_PAGE_20_TxQPKTQ6_COUNT(x) WriteReg(SWITCH_PAGE_20_TXQPKTQ6,x)
#define Rd_switch_PAGE_20_TxQPKTQ6_PAGE_20_TxQPKTQ6_COUNT(x) ReadReg(SWITCH_PAGE_20_TXQPKTQ6)
#define SWITCH_PAGE_20_TXQPKTQ6_PAGE_20_TXQPKTQ6_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_20_TXQPKTQ6_PAGE_20_TXQPKTQ6_COUNT_ALIGN       0
#define SWITCH_PAGE_20_TXQPKTQ6_PAGE_20_TXQPKTQ6_COUNT_BITS        32
#define SWITCH_PAGE_20_TXQPKTQ6_PAGE_20_TXQPKTQ6_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_TxQPKTQ7
 ***************************************************************************/
/* switch :: PAGE_20_TxQPKTQ7 :: PAGE_20_TxQPKTQ7_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxQPKTQ7_PAGE_20_TxQPKTQ7_COUNT(x) WriteReg(SWITCH_PAGE_20_TXQPKTQ7,x)
#define Rd_switch_PAGE_20_TxQPKTQ7_PAGE_20_TxQPKTQ7_COUNT(x) ReadReg(SWITCH_PAGE_20_TXQPKTQ7)
#define SWITCH_PAGE_20_TXQPKTQ7_PAGE_20_TXQPKTQ7_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_20_TXQPKTQ7_PAGE_20_TXQPKTQ7_COUNT_ALIGN       0
#define SWITCH_PAGE_20_TXQPKTQ7_PAGE_20_TXQPKTQ7_COUNT_BITS        32
#define SWITCH_PAGE_20_TXQPKTQ7_PAGE_20_TXQPKTQ7_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_20_TxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_20_TxPkts64Octets :: PAGE_20_TxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxPkts64Octets_PAGE_20_TxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_TXPKTS64OCTETS,x)
#define Rd_switch_PAGE_20_TxPkts64Octets_PAGE_20_TxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_TXPKTS64OCTETS)
#define SWITCH_PAGE_20_TXPKTS64OCTETS_PAGE_20_TXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXPKTS64OCTETS_PAGE_20_TXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXPKTS64OCTETS_PAGE_20_TXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXPKTS64OCTETS_PAGE_20_TXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_20_TxPkts65to127Octets :: PAGE_20_TxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxPkts65to127Octets_PAGE_20_TxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_TXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_20_TxPkts65to127Octets_PAGE_20_TxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_TXPKTS65TO127OCTETS)
#define SWITCH_PAGE_20_TXPKTS65TO127OCTETS_PAGE_20_TXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXPKTS65TO127OCTETS_PAGE_20_TXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXPKTS65TO127OCTETS_PAGE_20_TXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXPKTS65TO127OCTETS_PAGE_20_TXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_20_TxPkts128to255Octets :: PAGE_20_TxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxPkts128to255Octets_PAGE_20_TxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_TXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_20_TxPkts128to255Octets_PAGE_20_TxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_TXPKTS128TO255OCTETS)
#define SWITCH_PAGE_20_TXPKTS128TO255OCTETS_PAGE_20_TXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXPKTS128TO255OCTETS_PAGE_20_TXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXPKTS128TO255OCTETS_PAGE_20_TXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXPKTS128TO255OCTETS_PAGE_20_TXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_20_TxPkts256to511Octets :: PAGE_20_TxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxPkts256to511Octets_PAGE_20_TxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_TXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_20_TxPkts256to511Octets_PAGE_20_TxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_TXPKTS256TO511OCTETS)
#define SWITCH_PAGE_20_TXPKTS256TO511OCTETS_PAGE_20_TXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXPKTS256TO511OCTETS_PAGE_20_TXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXPKTS256TO511OCTETS_PAGE_20_TXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXPKTS256TO511OCTETS_PAGE_20_TXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_20_TxPkts512to1023Octets :: PAGE_20_TxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxPkts512to1023Octets_PAGE_20_TxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_20_TXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_20_TxPkts512to1023Octets_PAGE_20_TxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_20_TXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_20_TXPKTS512TO1023OCTETS_PAGE_20_TXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXPKTS512TO1023OCTETS_PAGE_20_TXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXPKTS512TO1023OCTETS_PAGE_20_TXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXPKTS512TO1023OCTETS_PAGE_20_TXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_20_TxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_20_TxPkts1024toMaxPktOctets :: PAGE_20_TxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_20_TxPkts1024toMaxPktOctets_PAGE_20_TxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_20_TXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_20_TxPkts1024toMaxPktOctets_PAGE_20_TxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_20_TXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_20_TXPKTS1024TOMAXPKTOCTETS_PAGE_20_TXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_20_TXPKTS1024TOMAXPKTOCTETS_PAGE_20_TXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_20_TXPKTS1024TOMAXPKTOCTETS_PAGE_20_TXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_20_TXPKTS1024TOMAXPKTOCTETS_PAGE_20_TXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxOctets
 ***************************************************************************/
/* switch :: PAGE_21_TxOctets :: PAGE_21_TxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_21_TxOctets_PAGE_21_TxOctets_COUNT(x) WriteReg(SWITCH_PAGE_21_TXOCTETS,x)
#define Rd_switch_PAGE_21_TxOctets_PAGE_21_TxOctets_COUNT(x) ReadReg(SWITCH_PAGE_21_TXOCTETS)
#define SWITCH_PAGE_21_TXOCTETS_PAGE_21_TXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_21_TXOCTETS_PAGE_21_TXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_21_TXOCTETS_PAGE_21_TXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_21_TXOCTETS_PAGE_21_TXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_TxDropPkts
 ***************************************************************************/
/* switch :: PAGE_21_TxDropPkts :: PAGE_21_TxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxDropPkts_PAGE_21_TxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_21_TXDROPPKTS,x)
#define Rd_switch_PAGE_21_TxDropPkts_PAGE_21_TxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_21_TXDROPPKTS)
#define SWITCH_PAGE_21_TXDROPPKTS_PAGE_21_TXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_21_TXDROPPKTS_PAGE_21_TXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_21_TXDROPPKTS_PAGE_21_TXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_21_TXDROPPKTS_PAGE_21_TXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_21_TxQPKTQ0
 ***************************************************************************/
/* switch :: PAGE_21_TxQPKTQ0 :: PAGE_21_TxQPKTQ0_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxQPKTQ0_PAGE_21_TxQPKTQ0_COUNT(x) WriteReg(SWITCH_PAGE_21_TXQPKTQ0,x)
#define Rd_switch_PAGE_21_TxQPKTQ0_PAGE_21_TxQPKTQ0_COUNT(x) ReadReg(SWITCH_PAGE_21_TXQPKTQ0)
#define SWITCH_PAGE_21_TXQPKTQ0_PAGE_21_TXQPKTQ0_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_21_TXQPKTQ0_PAGE_21_TXQPKTQ0_COUNT_ALIGN       0
#define SWITCH_PAGE_21_TXQPKTQ0_PAGE_21_TXQPKTQ0_COUNT_BITS        32
#define SWITCH_PAGE_21_TXQPKTQ0_PAGE_21_TXQPKTQ0_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_TxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_21_TxBroadcastPkts :: PAGE_21_TxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxBroadcastPkts_PAGE_21_TxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_21_TXBROADCASTPKTS,x)
#define Rd_switch_PAGE_21_TxBroadcastPkts_PAGE_21_TxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_21_TXBROADCASTPKTS)
#define SWITCH_PAGE_21_TXBROADCASTPKTS_PAGE_21_TXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXBROADCASTPKTS_PAGE_21_TXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXBROADCASTPKTS_PAGE_21_TXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXBROADCASTPKTS_PAGE_21_TXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_21_TxMulticastPkts :: PAGE_21_TxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxMulticastPkts_PAGE_21_TxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_21_TXMULTICASTPKTS,x)
#define Rd_switch_PAGE_21_TxMulticastPkts_PAGE_21_TxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_21_TXMULTICASTPKTS)
#define SWITCH_PAGE_21_TXMULTICASTPKTS_PAGE_21_TXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXMULTICASTPKTS_PAGE_21_TXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXMULTICASTPKTS_PAGE_21_TXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXMULTICASTPKTS_PAGE_21_TXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_21_TxUnicastPkts :: PAGE_21_TxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxUnicastPkts_PAGE_21_TxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_21_TXUNICASTPKTS,x)
#define Rd_switch_PAGE_21_TxUnicastPkts_PAGE_21_TxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_21_TXUNICASTPKTS)
#define SWITCH_PAGE_21_TXUNICASTPKTS_PAGE_21_TXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXUNICASTPKTS_PAGE_21_TXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXUNICASTPKTS_PAGE_21_TXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXUNICASTPKTS_PAGE_21_TXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxCollisions
 ***************************************************************************/
/* switch :: PAGE_21_TxCollisions :: PAGE_21_TxCollisions_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxCollisions_PAGE_21_TxCollisions_COUNT(x) WriteReg(SWITCH_PAGE_21_TXCOLLISIONS,x)
#define Rd_switch_PAGE_21_TxCollisions_PAGE_21_TxCollisions_COUNT(x) ReadReg(SWITCH_PAGE_21_TXCOLLISIONS)
#define SWITCH_PAGE_21_TXCOLLISIONS_PAGE_21_TXCOLLISIONS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXCOLLISIONS_PAGE_21_TXCOLLISIONS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXCOLLISIONS_PAGE_21_TXCOLLISIONS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXCOLLISIONS_PAGE_21_TXCOLLISIONS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxSingleCollision
 ***************************************************************************/
/* switch :: PAGE_21_TxSingleCollision :: PAGE_21_TxSingleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxSingleCollision_PAGE_21_TxSingleCollision_COUNT(x) WriteReg(SWITCH_PAGE_21_TXSINGLECOLLISION,x)
#define Rd_switch_PAGE_21_TxSingleCollision_PAGE_21_TxSingleCollision_COUNT(x) ReadReg(SWITCH_PAGE_21_TXSINGLECOLLISION)
#define SWITCH_PAGE_21_TXSINGLECOLLISION_PAGE_21_TXSINGLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXSINGLECOLLISION_PAGE_21_TXSINGLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXSINGLECOLLISION_PAGE_21_TXSINGLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_21_TXSINGLECOLLISION_PAGE_21_TXSINGLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxMultipleCollision
 ***************************************************************************/
/* switch :: PAGE_21_TxMultipleCollision :: PAGE_21_TxMultipleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxMultipleCollision_PAGE_21_TxMultipleCollision_COUNT(x) WriteReg(SWITCH_PAGE_21_TXMULTIPLECOLLISION,x)
#define Rd_switch_PAGE_21_TxMultipleCollision_PAGE_21_TxMultipleCollision_COUNT(x) ReadReg(SWITCH_PAGE_21_TXMULTIPLECOLLISION)
#define SWITCH_PAGE_21_TXMULTIPLECOLLISION_PAGE_21_TXMULTIPLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXMULTIPLECOLLISION_PAGE_21_TXMULTIPLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXMULTIPLECOLLISION_PAGE_21_TXMULTIPLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_21_TXMULTIPLECOLLISION_PAGE_21_TXMULTIPLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxDeferredTransmit
 ***************************************************************************/
/* switch :: PAGE_21_TxDeferredTransmit :: PAGE_21_TxDeferredTransmit_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxDeferredTransmit_PAGE_21_TxDeferredTransmit_COUNT(x) WriteReg(SWITCH_PAGE_21_TXDEFERREDTRANSMIT,x)
#define Rd_switch_PAGE_21_TxDeferredTransmit_PAGE_21_TxDeferredTransmit_COUNT(x) ReadReg(SWITCH_PAGE_21_TXDEFERREDTRANSMIT)
#define SWITCH_PAGE_21_TXDEFERREDTRANSMIT_PAGE_21_TXDEFERREDTRANSMIT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXDEFERREDTRANSMIT_PAGE_21_TXDEFERREDTRANSMIT_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXDEFERREDTRANSMIT_PAGE_21_TXDEFERREDTRANSMIT_COUNT_BITS 32
#define SWITCH_PAGE_21_TXDEFERREDTRANSMIT_PAGE_21_TXDEFERREDTRANSMIT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxLateCollision
 ***************************************************************************/
/* switch :: PAGE_21_TxLateCollision :: PAGE_21_TxLateCollision_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxLateCollision_PAGE_21_TxLateCollision_COUNT(x) WriteReg(SWITCH_PAGE_21_TXLATECOLLISION,x)
#define Rd_switch_PAGE_21_TxLateCollision_PAGE_21_TxLateCollision_COUNT(x) ReadReg(SWITCH_PAGE_21_TXLATECOLLISION)
#define SWITCH_PAGE_21_TXLATECOLLISION_PAGE_21_TXLATECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXLATECOLLISION_PAGE_21_TXLATECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXLATECOLLISION_PAGE_21_TXLATECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_21_TXLATECOLLISION_PAGE_21_TXLATECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxExcessiveCollision
 ***************************************************************************/
/* switch :: PAGE_21_TxExcessiveCollision :: PAGE_21_TxExcessiveCollision_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxExcessiveCollision_PAGE_21_TxExcessiveCollision_COUNT(x) WriteReg(SWITCH_PAGE_21_TXEXCESSIVECOLLISION,x)
#define Rd_switch_PAGE_21_TxExcessiveCollision_PAGE_21_TxExcessiveCollision_COUNT(x) ReadReg(SWITCH_PAGE_21_TXEXCESSIVECOLLISION)
#define SWITCH_PAGE_21_TXEXCESSIVECOLLISION_PAGE_21_TXEXCESSIVECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXEXCESSIVECOLLISION_PAGE_21_TXEXCESSIVECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXEXCESSIVECOLLISION_PAGE_21_TXEXCESSIVECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_21_TXEXCESSIVECOLLISION_PAGE_21_TXEXCESSIVECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxFrameInDisc
 ***************************************************************************/
/* switch :: PAGE_21_TxFrameInDisc :: PAGE_21_TxFrameInDisc_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxFrameInDisc_PAGE_21_TxFrameInDisc_COUNT(x) WriteReg(SWITCH_PAGE_21_TXFRAMEINDISC,x)
#define Rd_switch_PAGE_21_TxFrameInDisc_PAGE_21_TxFrameInDisc_COUNT(x) ReadReg(SWITCH_PAGE_21_TXFRAMEINDISC)
#define SWITCH_PAGE_21_TXFRAMEINDISC_PAGE_21_TXFRAMEINDISC_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXFRAMEINDISC_PAGE_21_TXFRAMEINDISC_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXFRAMEINDISC_PAGE_21_TXFRAMEINDISC_COUNT_BITS 32
#define SWITCH_PAGE_21_TXFRAMEINDISC_PAGE_21_TXFRAMEINDISC_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxPausePkts
 ***************************************************************************/
/* switch :: PAGE_21_TxPausePkts :: PAGE_21_TxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxPausePkts_PAGE_21_TxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_21_TXPAUSEPKTS,x)
#define Rd_switch_PAGE_21_TxPausePkts_PAGE_21_TxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_21_TXPAUSEPKTS)
#define SWITCH_PAGE_21_TXPAUSEPKTS_PAGE_21_TXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_21_TXPAUSEPKTS_PAGE_21_TXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXPAUSEPKTS_PAGE_21_TXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_21_TXPAUSEPKTS_PAGE_21_TXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxQPKTQ1
 ***************************************************************************/
/* switch :: PAGE_21_TxQPKTQ1 :: PAGE_21_TxQPKTQ1_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxQPKTQ1_PAGE_21_TxQPKTQ1_COUNT(x) WriteReg(SWITCH_PAGE_21_TXQPKTQ1,x)
#define Rd_switch_PAGE_21_TxQPKTQ1_PAGE_21_TxQPKTQ1_COUNT(x) ReadReg(SWITCH_PAGE_21_TXQPKTQ1)
#define SWITCH_PAGE_21_TXQPKTQ1_PAGE_21_TXQPKTQ1_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_21_TXQPKTQ1_PAGE_21_TXQPKTQ1_COUNT_ALIGN       0
#define SWITCH_PAGE_21_TXQPKTQ1_PAGE_21_TXQPKTQ1_COUNT_BITS        32
#define SWITCH_PAGE_21_TXQPKTQ1_PAGE_21_TXQPKTQ1_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_TxQPKTQ2
 ***************************************************************************/
/* switch :: PAGE_21_TxQPKTQ2 :: PAGE_21_TxQPKTQ2_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxQPKTQ2_PAGE_21_TxQPKTQ2_COUNT(x) WriteReg(SWITCH_PAGE_21_TXQPKTQ2,x)
#define Rd_switch_PAGE_21_TxQPKTQ2_PAGE_21_TxQPKTQ2_COUNT(x) ReadReg(SWITCH_PAGE_21_TXQPKTQ2)
#define SWITCH_PAGE_21_TXQPKTQ2_PAGE_21_TXQPKTQ2_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_21_TXQPKTQ2_PAGE_21_TXQPKTQ2_COUNT_ALIGN       0
#define SWITCH_PAGE_21_TXQPKTQ2_PAGE_21_TXQPKTQ2_COUNT_BITS        32
#define SWITCH_PAGE_21_TXQPKTQ2_PAGE_21_TXQPKTQ2_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_TxQPKTQ3
 ***************************************************************************/
/* switch :: PAGE_21_TxQPKTQ3 :: PAGE_21_TxQPKTQ3_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxQPKTQ3_PAGE_21_TxQPKTQ3_COUNT(x) WriteReg(SWITCH_PAGE_21_TXQPKTQ3,x)
#define Rd_switch_PAGE_21_TxQPKTQ3_PAGE_21_TxQPKTQ3_COUNT(x) ReadReg(SWITCH_PAGE_21_TXQPKTQ3)
#define SWITCH_PAGE_21_TXQPKTQ3_PAGE_21_TXQPKTQ3_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_21_TXQPKTQ3_PAGE_21_TXQPKTQ3_COUNT_ALIGN       0
#define SWITCH_PAGE_21_TXQPKTQ3_PAGE_21_TXQPKTQ3_COUNT_BITS        32
#define SWITCH_PAGE_21_TXQPKTQ3_PAGE_21_TXQPKTQ3_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_TxQPKTQ4
 ***************************************************************************/
/* switch :: PAGE_21_TxQPKTQ4 :: PAGE_21_TxQPKTQ4_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxQPKTQ4_PAGE_21_TxQPKTQ4_COUNT(x) WriteReg(SWITCH_PAGE_21_TXQPKTQ4,x)
#define Rd_switch_PAGE_21_TxQPKTQ4_PAGE_21_TxQPKTQ4_COUNT(x) ReadReg(SWITCH_PAGE_21_TXQPKTQ4)
#define SWITCH_PAGE_21_TXQPKTQ4_PAGE_21_TXQPKTQ4_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_21_TXQPKTQ4_PAGE_21_TXQPKTQ4_COUNT_ALIGN       0
#define SWITCH_PAGE_21_TXQPKTQ4_PAGE_21_TXQPKTQ4_COUNT_BITS        32
#define SWITCH_PAGE_21_TXQPKTQ4_PAGE_21_TXQPKTQ4_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_TxQPKTQ5
 ***************************************************************************/
/* switch :: PAGE_21_TxQPKTQ5 :: PAGE_21_TxQPKTQ5_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxQPKTQ5_PAGE_21_TxQPKTQ5_COUNT(x) WriteReg(SWITCH_PAGE_21_TXQPKTQ5,x)
#define Rd_switch_PAGE_21_TxQPKTQ5_PAGE_21_TxQPKTQ5_COUNT(x) ReadReg(SWITCH_PAGE_21_TXQPKTQ5)
#define SWITCH_PAGE_21_TXQPKTQ5_PAGE_21_TXQPKTQ5_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_21_TXQPKTQ5_PAGE_21_TXQPKTQ5_COUNT_ALIGN       0
#define SWITCH_PAGE_21_TXQPKTQ5_PAGE_21_TXQPKTQ5_COUNT_BITS        32
#define SWITCH_PAGE_21_TXQPKTQ5_PAGE_21_TXQPKTQ5_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_RxOctets
 ***************************************************************************/
/* switch :: PAGE_21_RxOctets :: PAGE_21_RxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_21_RxOctets_PAGE_21_RxOctets_COUNT(x) WriteReg(SWITCH_PAGE_21_RXOCTETS,x)
#define Rd_switch_PAGE_21_RxOctets_PAGE_21_RxOctets_COUNT(x) ReadReg(SWITCH_PAGE_21_RXOCTETS)
#define SWITCH_PAGE_21_RXOCTETS_PAGE_21_RXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_21_RXOCTETS_PAGE_21_RXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_21_RXOCTETS_PAGE_21_RXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_21_RXOCTETS_PAGE_21_RXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_RxUndersizePkts
 ***************************************************************************/
/* switch :: PAGE_21_RxUndersizePkts :: PAGE_21_RxUndersizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxUndersizePkts_PAGE_21_RxUndersizePkts_COUNT(x) WriteReg(SWITCH_PAGE_21_RXUNDERSIZEPKTS,x)
#define Rd_switch_PAGE_21_RxUndersizePkts_PAGE_21_RxUndersizePkts_COUNT(x) ReadReg(SWITCH_PAGE_21_RXUNDERSIZEPKTS)
#define SWITCH_PAGE_21_RXUNDERSIZEPKTS_PAGE_21_RXUNDERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXUNDERSIZEPKTS_PAGE_21_RXUNDERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXUNDERSIZEPKTS_PAGE_21_RXUNDERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXUNDERSIZEPKTS_PAGE_21_RXUNDERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxPausePkts
 ***************************************************************************/
/* switch :: PAGE_21_RxPausePkts :: PAGE_21_RxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxPausePkts_PAGE_21_RxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_21_RXPAUSEPKTS,x)
#define Rd_switch_PAGE_21_RxPausePkts_PAGE_21_RxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_21_RXPAUSEPKTS)
#define SWITCH_PAGE_21_RXPAUSEPKTS_PAGE_21_RXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_21_RXPAUSEPKTS_PAGE_21_RXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXPAUSEPKTS_PAGE_21_RXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_21_RXPAUSEPKTS_PAGE_21_RXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_21_RxPkts64Octets :: PAGE_21_RxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxPkts64Octets_PAGE_21_RxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_RXPKTS64OCTETS,x)
#define Rd_switch_PAGE_21_RxPkts64Octets_PAGE_21_RxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_RXPKTS64OCTETS)
#define SWITCH_PAGE_21_RXPKTS64OCTETS_PAGE_21_RXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXPKTS64OCTETS_PAGE_21_RXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXPKTS64OCTETS_PAGE_21_RXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXPKTS64OCTETS_PAGE_21_RXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_21_RxPkts65to127Octets :: PAGE_21_RxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxPkts65to127Octets_PAGE_21_RxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_RXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_21_RxPkts65to127Octets_PAGE_21_RxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_RXPKTS65TO127OCTETS)
#define SWITCH_PAGE_21_RXPKTS65TO127OCTETS_PAGE_21_RXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXPKTS65TO127OCTETS_PAGE_21_RXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXPKTS65TO127OCTETS_PAGE_21_RXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXPKTS65TO127OCTETS_PAGE_21_RXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_21_RxPkts128to255Octets :: PAGE_21_RxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxPkts128to255Octets_PAGE_21_RxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_RXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_21_RxPkts128to255Octets_PAGE_21_RxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_RXPKTS128TO255OCTETS)
#define SWITCH_PAGE_21_RXPKTS128TO255OCTETS_PAGE_21_RXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXPKTS128TO255OCTETS_PAGE_21_RXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXPKTS128TO255OCTETS_PAGE_21_RXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXPKTS128TO255OCTETS_PAGE_21_RXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_21_RxPkts256to511Octets :: PAGE_21_RxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxPkts256to511Octets_PAGE_21_RxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_RXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_21_RxPkts256to511Octets_PAGE_21_RxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_RXPKTS256TO511OCTETS)
#define SWITCH_PAGE_21_RXPKTS256TO511OCTETS_PAGE_21_RXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXPKTS256TO511OCTETS_PAGE_21_RXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXPKTS256TO511OCTETS_PAGE_21_RXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXPKTS256TO511OCTETS_PAGE_21_RXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_21_RxPkts512to1023Octets :: PAGE_21_RxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxPkts512to1023Octets_PAGE_21_RxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_RXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_21_RxPkts512to1023Octets_PAGE_21_RxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_RXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_21_RXPKTS512TO1023OCTETS_PAGE_21_RXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXPKTS512TO1023OCTETS_PAGE_21_RXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXPKTS512TO1023OCTETS_PAGE_21_RXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXPKTS512TO1023OCTETS_PAGE_21_RXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_21_RxPkts1024toMaxPktOctets :: PAGE_21_RxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxPkts1024toMaxPktOctets_PAGE_21_RxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_21_RXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_21_RxPkts1024toMaxPktOctets_PAGE_21_RxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_21_RXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_21_RXPKTS1024TOMAXPKTOCTETS_PAGE_21_RXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXPKTS1024TOMAXPKTOCTETS_PAGE_21_RXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXPKTS1024TOMAXPKTOCTETS_PAGE_21_RXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXPKTS1024TOMAXPKTOCTETS_PAGE_21_RXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxOversizePkts
 ***************************************************************************/
/* switch :: PAGE_21_RxOversizePkts :: PAGE_21_RxOversizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxOversizePkts_PAGE_21_RxOversizePkts_COUNT(x) WriteReg(SWITCH_PAGE_21_RXOVERSIZEPKTS,x)
#define Rd_switch_PAGE_21_RxOversizePkts_PAGE_21_RxOversizePkts_COUNT(x) ReadReg(SWITCH_PAGE_21_RXOVERSIZEPKTS)
#define SWITCH_PAGE_21_RXOVERSIZEPKTS_PAGE_21_RXOVERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXOVERSIZEPKTS_PAGE_21_RXOVERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXOVERSIZEPKTS_PAGE_21_RXOVERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXOVERSIZEPKTS_PAGE_21_RXOVERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxJabbers
 ***************************************************************************/
/* switch :: PAGE_21_RxJabbers :: PAGE_21_RxJabbers_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxJabbers_PAGE_21_RxJabbers_COUNT(x) WriteReg(SWITCH_PAGE_21_RXJABBERS,x)
#define Rd_switch_PAGE_21_RxJabbers_PAGE_21_RxJabbers_COUNT(x) ReadReg(SWITCH_PAGE_21_RXJABBERS)
#define SWITCH_PAGE_21_RXJABBERS_PAGE_21_RXJABBERS_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_21_RXJABBERS_PAGE_21_RXJABBERS_COUNT_ALIGN     0
#define SWITCH_PAGE_21_RXJABBERS_PAGE_21_RXJABBERS_COUNT_BITS      32
#define SWITCH_PAGE_21_RXJABBERS_PAGE_21_RXJABBERS_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_21_RxAlignmentErrors
 ***************************************************************************/
/* switch :: PAGE_21_RxAlignmentErrors :: PAGE_21_RxAlignmentErrors_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxAlignmentErrors_PAGE_21_RxAlignmentErrors_COUNT(x) WriteReg(SWITCH_PAGE_21_RXALIGNMENTERRORS,x)
#define Rd_switch_PAGE_21_RxAlignmentErrors_PAGE_21_RxAlignmentErrors_COUNT(x) ReadReg(SWITCH_PAGE_21_RXALIGNMENTERRORS)
#define SWITCH_PAGE_21_RXALIGNMENTERRORS_PAGE_21_RXALIGNMENTERRORS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXALIGNMENTERRORS_PAGE_21_RXALIGNMENTERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXALIGNMENTERRORS_PAGE_21_RXALIGNMENTERRORS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXALIGNMENTERRORS_PAGE_21_RXALIGNMENTERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxFCSErrors
 ***************************************************************************/
/* switch :: PAGE_21_RxFCSErrors :: PAGE_21_RxFCSErrors_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxFCSErrors_PAGE_21_RxFCSErrors_COUNT(x) WriteReg(SWITCH_PAGE_21_RXFCSERRORS,x)
#define Rd_switch_PAGE_21_RxFCSErrors_PAGE_21_RxFCSErrors_COUNT(x) ReadReg(SWITCH_PAGE_21_RXFCSERRORS)
#define SWITCH_PAGE_21_RXFCSERRORS_PAGE_21_RXFCSERRORS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_21_RXFCSERRORS_PAGE_21_RXFCSERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXFCSERRORS_PAGE_21_RXFCSERRORS_COUNT_BITS  32
#define SWITCH_PAGE_21_RXFCSERRORS_PAGE_21_RXFCSERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxGoodOctets
 ***************************************************************************/
/* switch :: PAGE_21_RxGoodOctets :: PAGE_21_RxGoodOctets_COUNT [63:00] */
#define Wr_switch_PAGE_21_RxGoodOctets_PAGE_21_RxGoodOctets_COUNT(x) WriteReg(SWITCH_PAGE_21_RXGOODOCTETS,x)
#define Rd_switch_PAGE_21_RxGoodOctets_PAGE_21_RxGoodOctets_COUNT(x) ReadReg(SWITCH_PAGE_21_RXGOODOCTETS)
#define SWITCH_PAGE_21_RXGOODOCTETS_PAGE_21_RXGOODOCTETS_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_21_RXGOODOCTETS_PAGE_21_RXGOODOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXGOODOCTETS_PAGE_21_RXGOODOCTETS_COUNT_BITS 64
#define SWITCH_PAGE_21_RXGOODOCTETS_PAGE_21_RXGOODOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxDropPkts
 ***************************************************************************/
/* switch :: PAGE_21_RxDropPkts :: PAGE_21_RxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxDropPkts_PAGE_21_RxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_21_RXDROPPKTS,x)
#define Rd_switch_PAGE_21_RxDropPkts_PAGE_21_RxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_21_RXDROPPKTS)
#define SWITCH_PAGE_21_RXDROPPKTS_PAGE_21_RXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_21_RXDROPPKTS_PAGE_21_RXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_21_RXDROPPKTS_PAGE_21_RXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_21_RXDROPPKTS_PAGE_21_RXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_21_RxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_21_RxUnicastPkts :: PAGE_21_RxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxUnicastPkts_PAGE_21_RxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_21_RXUNICASTPKTS,x)
#define Rd_switch_PAGE_21_RxUnicastPkts_PAGE_21_RxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_21_RXUNICASTPKTS)
#define SWITCH_PAGE_21_RXUNICASTPKTS_PAGE_21_RXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXUNICASTPKTS_PAGE_21_RXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXUNICASTPKTS_PAGE_21_RXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXUNICASTPKTS_PAGE_21_RXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_21_RxMulticastPkts :: PAGE_21_RxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxMulticastPkts_PAGE_21_RxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_21_RXMULTICASTPKTS,x)
#define Rd_switch_PAGE_21_RxMulticastPkts_PAGE_21_RxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_21_RXMULTICASTPKTS)
#define SWITCH_PAGE_21_RXMULTICASTPKTS_PAGE_21_RXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXMULTICASTPKTS_PAGE_21_RXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXMULTICASTPKTS_PAGE_21_RXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXMULTICASTPKTS_PAGE_21_RXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_21_RxBroadcastPkts :: PAGE_21_RxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxBroadcastPkts_PAGE_21_RxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_21_RXBROADCASTPKTS,x)
#define Rd_switch_PAGE_21_RxBroadcastPkts_PAGE_21_RxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_21_RXBROADCASTPKTS)
#define SWITCH_PAGE_21_RXBROADCASTPKTS_PAGE_21_RXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_RXBROADCASTPKTS_PAGE_21_RXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXBROADCASTPKTS_PAGE_21_RXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_21_RXBROADCASTPKTS_PAGE_21_RXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxSAChanges
 ***************************************************************************/
/* switch :: PAGE_21_RxSAChanges :: PAGE_21_RxSAChanges_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxSAChanges_PAGE_21_RxSAChanges_COUNT(x) WriteReg(SWITCH_PAGE_21_RXSACHANGES,x)
#define Rd_switch_PAGE_21_RxSAChanges_PAGE_21_RxSAChanges_COUNT(x) ReadReg(SWITCH_PAGE_21_RXSACHANGES)
#define SWITCH_PAGE_21_RXSACHANGES_PAGE_21_RXSACHANGES_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_21_RXSACHANGES_PAGE_21_RXSACHANGES_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXSACHANGES_PAGE_21_RXSACHANGES_COUNT_BITS  32
#define SWITCH_PAGE_21_RXSACHANGES_PAGE_21_RXSACHANGES_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxFragments
 ***************************************************************************/
/* switch :: PAGE_21_RxFragments :: PAGE_21_RxFragments_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxFragments_PAGE_21_RxFragments_COUNT(x) WriteReg(SWITCH_PAGE_21_RXFRAGMENTS,x)
#define Rd_switch_PAGE_21_RxFragments_PAGE_21_RxFragments_COUNT(x) ReadReg(SWITCH_PAGE_21_RXFRAGMENTS)
#define SWITCH_PAGE_21_RXFRAGMENTS_PAGE_21_RXFRAGMENTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_21_RXFRAGMENTS_PAGE_21_RXFRAGMENTS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_RXFRAGMENTS_PAGE_21_RXFRAGMENTS_COUNT_BITS  32
#define SWITCH_PAGE_21_RXFRAGMENTS_PAGE_21_RXFRAGMENTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxJumboPkt
 ***************************************************************************/
/* switch :: PAGE_21_RxJumboPkt :: PAGE_21_RxJumboPkt_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxJumboPkt_PAGE_21_RxJumboPkt_COUNT(x) WriteReg(SWITCH_PAGE_21_RXJUMBOPKT,x)
#define Rd_switch_PAGE_21_RxJumboPkt_PAGE_21_RxJumboPkt_COUNT(x) ReadReg(SWITCH_PAGE_21_RXJUMBOPKT)
#define SWITCH_PAGE_21_RXJUMBOPKT_PAGE_21_RXJUMBOPKT_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_21_RXJUMBOPKT_PAGE_21_RXJUMBOPKT_COUNT_ALIGN   0
#define SWITCH_PAGE_21_RXJUMBOPKT_PAGE_21_RXJUMBOPKT_COUNT_BITS    32
#define SWITCH_PAGE_21_RXJUMBOPKT_PAGE_21_RXJUMBOPKT_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_21_RxSymblErr
 ***************************************************************************/
/* switch :: PAGE_21_RxSymblErr :: PAGE_21_RxSymblErr_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxSymblErr_PAGE_21_RxSymblErr_COUNT(x) WriteReg(SWITCH_PAGE_21_RXSYMBLERR,x)
#define Rd_switch_PAGE_21_RxSymblErr_PAGE_21_RxSymblErr_COUNT(x) ReadReg(SWITCH_PAGE_21_RXSYMBLERR)
#define SWITCH_PAGE_21_RXSYMBLERR_PAGE_21_RXSYMBLERR_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_21_RXSYMBLERR_PAGE_21_RXSYMBLERR_COUNT_ALIGN   0
#define SWITCH_PAGE_21_RXSYMBLERR_PAGE_21_RXSYMBLERR_COUNT_BITS    32
#define SWITCH_PAGE_21_RXSYMBLERR_PAGE_21_RXSYMBLERR_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_21_InRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_21_InRangeErrCount :: PAGE_21_InRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_21_InRangeErrCount_PAGE_21_InRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_21_INRANGEERRCOUNT,x)
#define Rd_switch_PAGE_21_InRangeErrCount_PAGE_21_InRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_21_INRANGEERRCOUNT)
#define SWITCH_PAGE_21_INRANGEERRCOUNT_PAGE_21_INRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_INRANGEERRCOUNT_PAGE_21_INRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_21_INRANGEERRCOUNT_PAGE_21_INRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_21_INRANGEERRCOUNT_PAGE_21_INRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_OutRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_21_OutRangeErrCount :: PAGE_21_OutRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_21_OutRangeErrCount_PAGE_21_OutRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_21_OUTRANGEERRCOUNT,x)
#define Rd_switch_PAGE_21_OutRangeErrCount_PAGE_21_OutRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_21_OUTRANGEERRCOUNT)
#define SWITCH_PAGE_21_OUTRANGEERRCOUNT_PAGE_21_OUTRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_OUTRANGEERRCOUNT_PAGE_21_OUTRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_21_OUTRANGEERRCOUNT_PAGE_21_OUTRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_21_OUTRANGEERRCOUNT_PAGE_21_OUTRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_EEE_LPI_EVENT
 ***************************************************************************/
/* switch :: PAGE_21_EEE_LPI_EVENT :: PAGE_21_EEE_LPI_EVENT_COUNT [31:00] */
#define Wr_switch_PAGE_21_EEE_LPI_EVENT_PAGE_21_EEE_LPI_EVENT_COUNT(x) WriteReg(SWITCH_PAGE_21_EEE_LPI_EVENT,x)
#define Rd_switch_PAGE_21_EEE_LPI_EVENT_PAGE_21_EEE_LPI_EVENT_COUNT(x) ReadReg(SWITCH_PAGE_21_EEE_LPI_EVENT)
#define SWITCH_PAGE_21_EEE_LPI_EVENT_PAGE_21_EEE_LPI_EVENT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_EEE_LPI_EVENT_PAGE_21_EEE_LPI_EVENT_COUNT_ALIGN 0
#define SWITCH_PAGE_21_EEE_LPI_EVENT_PAGE_21_EEE_LPI_EVENT_COUNT_BITS 32
#define SWITCH_PAGE_21_EEE_LPI_EVENT_PAGE_21_EEE_LPI_EVENT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_EEE_LPI_DURATION
 ***************************************************************************/
/* switch :: PAGE_21_EEE_LPI_DURATION :: PAGE_21_EEE_LPI_DURATION_COUNT [31:00] */
#define Wr_switch_PAGE_21_EEE_LPI_DURATION_PAGE_21_EEE_LPI_DURATION_COUNT(x) WriteReg(SWITCH_PAGE_21_EEE_LPI_DURATION,x)
#define Rd_switch_PAGE_21_EEE_LPI_DURATION_PAGE_21_EEE_LPI_DURATION_COUNT(x) ReadReg(SWITCH_PAGE_21_EEE_LPI_DURATION)
#define SWITCH_PAGE_21_EEE_LPI_DURATION_PAGE_21_EEE_LPI_DURATION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_EEE_LPI_DURATION_PAGE_21_EEE_LPI_DURATION_COUNT_ALIGN 0
#define SWITCH_PAGE_21_EEE_LPI_DURATION_PAGE_21_EEE_LPI_DURATION_COUNT_BITS 32
#define SWITCH_PAGE_21_EEE_LPI_DURATION_PAGE_21_EEE_LPI_DURATION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_RxDiscard
 ***************************************************************************/
/* switch :: PAGE_21_RxDiscard :: PAGE_21_RxDiscard_COUNT [31:00] */
#define Wr_switch_PAGE_21_RxDiscard_PAGE_21_RxDiscard_COUNT(x) WriteReg(SWITCH_PAGE_21_RXDISCARD,x)
#define Rd_switch_PAGE_21_RxDiscard_PAGE_21_RxDiscard_COUNT(x) ReadReg(SWITCH_PAGE_21_RXDISCARD)
#define SWITCH_PAGE_21_RXDISCARD_PAGE_21_RXDISCARD_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_21_RXDISCARD_PAGE_21_RXDISCARD_COUNT_ALIGN     0
#define SWITCH_PAGE_21_RXDISCARD_PAGE_21_RXDISCARD_COUNT_BITS      32
#define SWITCH_PAGE_21_RXDISCARD_PAGE_21_RXDISCARD_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_21_TxQPKTQ6
 ***************************************************************************/
/* switch :: PAGE_21_TxQPKTQ6 :: PAGE_21_TxQPKTQ6_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxQPKTQ6_PAGE_21_TxQPKTQ6_COUNT(x) WriteReg(SWITCH_PAGE_21_TXQPKTQ6,x)
#define Rd_switch_PAGE_21_TxQPKTQ6_PAGE_21_TxQPKTQ6_COUNT(x) ReadReg(SWITCH_PAGE_21_TXQPKTQ6)
#define SWITCH_PAGE_21_TXQPKTQ6_PAGE_21_TXQPKTQ6_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_21_TXQPKTQ6_PAGE_21_TXQPKTQ6_COUNT_ALIGN       0
#define SWITCH_PAGE_21_TXQPKTQ6_PAGE_21_TXQPKTQ6_COUNT_BITS        32
#define SWITCH_PAGE_21_TXQPKTQ6_PAGE_21_TXQPKTQ6_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_TxQPKTQ7
 ***************************************************************************/
/* switch :: PAGE_21_TxQPKTQ7 :: PAGE_21_TxQPKTQ7_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxQPKTQ7_PAGE_21_TxQPKTQ7_COUNT(x) WriteReg(SWITCH_PAGE_21_TXQPKTQ7,x)
#define Rd_switch_PAGE_21_TxQPKTQ7_PAGE_21_TxQPKTQ7_COUNT(x) ReadReg(SWITCH_PAGE_21_TXQPKTQ7)
#define SWITCH_PAGE_21_TXQPKTQ7_PAGE_21_TXQPKTQ7_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_21_TXQPKTQ7_PAGE_21_TXQPKTQ7_COUNT_ALIGN       0
#define SWITCH_PAGE_21_TXQPKTQ7_PAGE_21_TXQPKTQ7_COUNT_BITS        32
#define SWITCH_PAGE_21_TXQPKTQ7_PAGE_21_TXQPKTQ7_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_21_TxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_21_TxPkts64Octets :: PAGE_21_TxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxPkts64Octets_PAGE_21_TxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_TXPKTS64OCTETS,x)
#define Rd_switch_PAGE_21_TxPkts64Octets_PAGE_21_TxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_TXPKTS64OCTETS)
#define SWITCH_PAGE_21_TXPKTS64OCTETS_PAGE_21_TXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXPKTS64OCTETS_PAGE_21_TXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXPKTS64OCTETS_PAGE_21_TXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXPKTS64OCTETS_PAGE_21_TXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_21_TxPkts65to127Octets :: PAGE_21_TxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxPkts65to127Octets_PAGE_21_TxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_TXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_21_TxPkts65to127Octets_PAGE_21_TxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_TXPKTS65TO127OCTETS)
#define SWITCH_PAGE_21_TXPKTS65TO127OCTETS_PAGE_21_TXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXPKTS65TO127OCTETS_PAGE_21_TXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXPKTS65TO127OCTETS_PAGE_21_TXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXPKTS65TO127OCTETS_PAGE_21_TXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_21_TxPkts128to255Octets :: PAGE_21_TxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxPkts128to255Octets_PAGE_21_TxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_TXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_21_TxPkts128to255Octets_PAGE_21_TxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_TXPKTS128TO255OCTETS)
#define SWITCH_PAGE_21_TXPKTS128TO255OCTETS_PAGE_21_TXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXPKTS128TO255OCTETS_PAGE_21_TXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXPKTS128TO255OCTETS_PAGE_21_TXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXPKTS128TO255OCTETS_PAGE_21_TXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_21_TxPkts256to511Octets :: PAGE_21_TxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxPkts256to511Octets_PAGE_21_TxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_TXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_21_TxPkts256to511Octets_PAGE_21_TxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_TXPKTS256TO511OCTETS)
#define SWITCH_PAGE_21_TXPKTS256TO511OCTETS_PAGE_21_TXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXPKTS256TO511OCTETS_PAGE_21_TXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXPKTS256TO511OCTETS_PAGE_21_TXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXPKTS256TO511OCTETS_PAGE_21_TXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_21_TxPkts512to1023Octets :: PAGE_21_TxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxPkts512to1023Octets_PAGE_21_TxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_21_TXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_21_TxPkts512to1023Octets_PAGE_21_TxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_21_TXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_21_TXPKTS512TO1023OCTETS_PAGE_21_TXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXPKTS512TO1023OCTETS_PAGE_21_TXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXPKTS512TO1023OCTETS_PAGE_21_TXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXPKTS512TO1023OCTETS_PAGE_21_TXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_21_TxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_21_TxPkts1024toMaxPktOctets :: PAGE_21_TxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_21_TxPkts1024toMaxPktOctets_PAGE_21_TxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_21_TXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_21_TxPkts1024toMaxPktOctets_PAGE_21_TxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_21_TXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_21_TXPKTS1024TOMAXPKTOCTETS_PAGE_21_TXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_21_TXPKTS1024TOMAXPKTOCTETS_PAGE_21_TXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_21_TXPKTS1024TOMAXPKTOCTETS_PAGE_21_TXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_21_TXPKTS1024TOMAXPKTOCTETS_PAGE_21_TXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxOctets
 ***************************************************************************/
/* switch :: PAGE_22_TxOctets :: PAGE_22_TxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_22_TxOctets_PAGE_22_TxOctets_COUNT(x) WriteReg(SWITCH_PAGE_22_TXOCTETS,x)
#define Rd_switch_PAGE_22_TxOctets_PAGE_22_TxOctets_COUNT(x) ReadReg(SWITCH_PAGE_22_TXOCTETS)
#define SWITCH_PAGE_22_TXOCTETS_PAGE_22_TXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_22_TXOCTETS_PAGE_22_TXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_22_TXOCTETS_PAGE_22_TXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_22_TXOCTETS_PAGE_22_TXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_TxDropPkts
 ***************************************************************************/
/* switch :: PAGE_22_TxDropPkts :: PAGE_22_TxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxDropPkts_PAGE_22_TxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_22_TXDROPPKTS,x)
#define Rd_switch_PAGE_22_TxDropPkts_PAGE_22_TxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_22_TXDROPPKTS)
#define SWITCH_PAGE_22_TXDROPPKTS_PAGE_22_TXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_22_TXDROPPKTS_PAGE_22_TXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_22_TXDROPPKTS_PAGE_22_TXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_22_TXDROPPKTS_PAGE_22_TXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_22_TxQPKTQ0
 ***************************************************************************/
/* switch :: PAGE_22_TxQPKTQ0 :: PAGE_22_TxQPKTQ0_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxQPKTQ0_PAGE_22_TxQPKTQ0_COUNT(x) WriteReg(SWITCH_PAGE_22_TXQPKTQ0,x)
#define Rd_switch_PAGE_22_TxQPKTQ0_PAGE_22_TxQPKTQ0_COUNT(x) ReadReg(SWITCH_PAGE_22_TXQPKTQ0)
#define SWITCH_PAGE_22_TXQPKTQ0_PAGE_22_TXQPKTQ0_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_22_TXQPKTQ0_PAGE_22_TXQPKTQ0_COUNT_ALIGN       0
#define SWITCH_PAGE_22_TXQPKTQ0_PAGE_22_TXQPKTQ0_COUNT_BITS        32
#define SWITCH_PAGE_22_TXQPKTQ0_PAGE_22_TXQPKTQ0_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_TxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_22_TxBroadcastPkts :: PAGE_22_TxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxBroadcastPkts_PAGE_22_TxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_22_TXBROADCASTPKTS,x)
#define Rd_switch_PAGE_22_TxBroadcastPkts_PAGE_22_TxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_22_TXBROADCASTPKTS)
#define SWITCH_PAGE_22_TXBROADCASTPKTS_PAGE_22_TXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXBROADCASTPKTS_PAGE_22_TXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXBROADCASTPKTS_PAGE_22_TXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXBROADCASTPKTS_PAGE_22_TXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_22_TxMulticastPkts :: PAGE_22_TxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxMulticastPkts_PAGE_22_TxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_22_TXMULTICASTPKTS,x)
#define Rd_switch_PAGE_22_TxMulticastPkts_PAGE_22_TxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_22_TXMULTICASTPKTS)
#define SWITCH_PAGE_22_TXMULTICASTPKTS_PAGE_22_TXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXMULTICASTPKTS_PAGE_22_TXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXMULTICASTPKTS_PAGE_22_TXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXMULTICASTPKTS_PAGE_22_TXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_22_TxUnicastPkts :: PAGE_22_TxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxUnicastPkts_PAGE_22_TxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_22_TXUNICASTPKTS,x)
#define Rd_switch_PAGE_22_TxUnicastPkts_PAGE_22_TxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_22_TXUNICASTPKTS)
#define SWITCH_PAGE_22_TXUNICASTPKTS_PAGE_22_TXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXUNICASTPKTS_PAGE_22_TXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXUNICASTPKTS_PAGE_22_TXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXUNICASTPKTS_PAGE_22_TXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxCollisions
 ***************************************************************************/
/* switch :: PAGE_22_TxCollisions :: PAGE_22_TxCollisions_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxCollisions_PAGE_22_TxCollisions_COUNT(x) WriteReg(SWITCH_PAGE_22_TXCOLLISIONS,x)
#define Rd_switch_PAGE_22_TxCollisions_PAGE_22_TxCollisions_COUNT(x) ReadReg(SWITCH_PAGE_22_TXCOLLISIONS)
#define SWITCH_PAGE_22_TXCOLLISIONS_PAGE_22_TXCOLLISIONS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXCOLLISIONS_PAGE_22_TXCOLLISIONS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXCOLLISIONS_PAGE_22_TXCOLLISIONS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXCOLLISIONS_PAGE_22_TXCOLLISIONS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxSingleCollision
 ***************************************************************************/
/* switch :: PAGE_22_TxSingleCollision :: PAGE_22_TxSingleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxSingleCollision_PAGE_22_TxSingleCollision_COUNT(x) WriteReg(SWITCH_PAGE_22_TXSINGLECOLLISION,x)
#define Rd_switch_PAGE_22_TxSingleCollision_PAGE_22_TxSingleCollision_COUNT(x) ReadReg(SWITCH_PAGE_22_TXSINGLECOLLISION)
#define SWITCH_PAGE_22_TXSINGLECOLLISION_PAGE_22_TXSINGLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXSINGLECOLLISION_PAGE_22_TXSINGLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXSINGLECOLLISION_PAGE_22_TXSINGLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_22_TXSINGLECOLLISION_PAGE_22_TXSINGLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxMultipleCollision
 ***************************************************************************/
/* switch :: PAGE_22_TxMultipleCollision :: PAGE_22_TxMultipleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxMultipleCollision_PAGE_22_TxMultipleCollision_COUNT(x) WriteReg(SWITCH_PAGE_22_TXMULTIPLECOLLISION,x)
#define Rd_switch_PAGE_22_TxMultipleCollision_PAGE_22_TxMultipleCollision_COUNT(x) ReadReg(SWITCH_PAGE_22_TXMULTIPLECOLLISION)
#define SWITCH_PAGE_22_TXMULTIPLECOLLISION_PAGE_22_TXMULTIPLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXMULTIPLECOLLISION_PAGE_22_TXMULTIPLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXMULTIPLECOLLISION_PAGE_22_TXMULTIPLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_22_TXMULTIPLECOLLISION_PAGE_22_TXMULTIPLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxDeferredTransmit
 ***************************************************************************/
/* switch :: PAGE_22_TxDeferredTransmit :: PAGE_22_TxDeferredTransmit_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxDeferredTransmit_PAGE_22_TxDeferredTransmit_COUNT(x) WriteReg(SWITCH_PAGE_22_TXDEFERREDTRANSMIT,x)
#define Rd_switch_PAGE_22_TxDeferredTransmit_PAGE_22_TxDeferredTransmit_COUNT(x) ReadReg(SWITCH_PAGE_22_TXDEFERREDTRANSMIT)
#define SWITCH_PAGE_22_TXDEFERREDTRANSMIT_PAGE_22_TXDEFERREDTRANSMIT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXDEFERREDTRANSMIT_PAGE_22_TXDEFERREDTRANSMIT_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXDEFERREDTRANSMIT_PAGE_22_TXDEFERREDTRANSMIT_COUNT_BITS 32
#define SWITCH_PAGE_22_TXDEFERREDTRANSMIT_PAGE_22_TXDEFERREDTRANSMIT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxLateCollision
 ***************************************************************************/
/* switch :: PAGE_22_TxLateCollision :: PAGE_22_TxLateCollision_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxLateCollision_PAGE_22_TxLateCollision_COUNT(x) WriteReg(SWITCH_PAGE_22_TXLATECOLLISION,x)
#define Rd_switch_PAGE_22_TxLateCollision_PAGE_22_TxLateCollision_COUNT(x) ReadReg(SWITCH_PAGE_22_TXLATECOLLISION)
#define SWITCH_PAGE_22_TXLATECOLLISION_PAGE_22_TXLATECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXLATECOLLISION_PAGE_22_TXLATECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXLATECOLLISION_PAGE_22_TXLATECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_22_TXLATECOLLISION_PAGE_22_TXLATECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxExcessiveCollision
 ***************************************************************************/
/* switch :: PAGE_22_TxExcessiveCollision :: PAGE_22_TxExcessiveCollision_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxExcessiveCollision_PAGE_22_TxExcessiveCollision_COUNT(x) WriteReg(SWITCH_PAGE_22_TXEXCESSIVECOLLISION,x)
#define Rd_switch_PAGE_22_TxExcessiveCollision_PAGE_22_TxExcessiveCollision_COUNT(x) ReadReg(SWITCH_PAGE_22_TXEXCESSIVECOLLISION)
#define SWITCH_PAGE_22_TXEXCESSIVECOLLISION_PAGE_22_TXEXCESSIVECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXEXCESSIVECOLLISION_PAGE_22_TXEXCESSIVECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXEXCESSIVECOLLISION_PAGE_22_TXEXCESSIVECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_22_TXEXCESSIVECOLLISION_PAGE_22_TXEXCESSIVECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxFrameInDisc
 ***************************************************************************/
/* switch :: PAGE_22_TxFrameInDisc :: PAGE_22_TxFrameInDisc_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxFrameInDisc_PAGE_22_TxFrameInDisc_COUNT(x) WriteReg(SWITCH_PAGE_22_TXFRAMEINDISC,x)
#define Rd_switch_PAGE_22_TxFrameInDisc_PAGE_22_TxFrameInDisc_COUNT(x) ReadReg(SWITCH_PAGE_22_TXFRAMEINDISC)
#define SWITCH_PAGE_22_TXFRAMEINDISC_PAGE_22_TXFRAMEINDISC_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXFRAMEINDISC_PAGE_22_TXFRAMEINDISC_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXFRAMEINDISC_PAGE_22_TXFRAMEINDISC_COUNT_BITS 32
#define SWITCH_PAGE_22_TXFRAMEINDISC_PAGE_22_TXFRAMEINDISC_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxPausePkts
 ***************************************************************************/
/* switch :: PAGE_22_TxPausePkts :: PAGE_22_TxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxPausePkts_PAGE_22_TxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_22_TXPAUSEPKTS,x)
#define Rd_switch_PAGE_22_TxPausePkts_PAGE_22_TxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_22_TXPAUSEPKTS)
#define SWITCH_PAGE_22_TXPAUSEPKTS_PAGE_22_TXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_22_TXPAUSEPKTS_PAGE_22_TXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXPAUSEPKTS_PAGE_22_TXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_22_TXPAUSEPKTS_PAGE_22_TXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxQPKTQ1
 ***************************************************************************/
/* switch :: PAGE_22_TxQPKTQ1 :: PAGE_22_TxQPKTQ1_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxQPKTQ1_PAGE_22_TxQPKTQ1_COUNT(x) WriteReg(SWITCH_PAGE_22_TXQPKTQ1,x)
#define Rd_switch_PAGE_22_TxQPKTQ1_PAGE_22_TxQPKTQ1_COUNT(x) ReadReg(SWITCH_PAGE_22_TXQPKTQ1)
#define SWITCH_PAGE_22_TXQPKTQ1_PAGE_22_TXQPKTQ1_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_22_TXQPKTQ1_PAGE_22_TXQPKTQ1_COUNT_ALIGN       0
#define SWITCH_PAGE_22_TXQPKTQ1_PAGE_22_TXQPKTQ1_COUNT_BITS        32
#define SWITCH_PAGE_22_TXQPKTQ1_PAGE_22_TXQPKTQ1_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_TxQPKTQ2
 ***************************************************************************/
/* switch :: PAGE_22_TxQPKTQ2 :: PAGE_22_TxQPKTQ2_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxQPKTQ2_PAGE_22_TxQPKTQ2_COUNT(x) WriteReg(SWITCH_PAGE_22_TXQPKTQ2,x)
#define Rd_switch_PAGE_22_TxQPKTQ2_PAGE_22_TxQPKTQ2_COUNT(x) ReadReg(SWITCH_PAGE_22_TXQPKTQ2)
#define SWITCH_PAGE_22_TXQPKTQ2_PAGE_22_TXQPKTQ2_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_22_TXQPKTQ2_PAGE_22_TXQPKTQ2_COUNT_ALIGN       0
#define SWITCH_PAGE_22_TXQPKTQ2_PAGE_22_TXQPKTQ2_COUNT_BITS        32
#define SWITCH_PAGE_22_TXQPKTQ2_PAGE_22_TXQPKTQ2_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_TxQPKTQ3
 ***************************************************************************/
/* switch :: PAGE_22_TxQPKTQ3 :: PAGE_22_TxQPKTQ3_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxQPKTQ3_PAGE_22_TxQPKTQ3_COUNT(x) WriteReg(SWITCH_PAGE_22_TXQPKTQ3,x)
#define Rd_switch_PAGE_22_TxQPKTQ3_PAGE_22_TxQPKTQ3_COUNT(x) ReadReg(SWITCH_PAGE_22_TXQPKTQ3)
#define SWITCH_PAGE_22_TXQPKTQ3_PAGE_22_TXQPKTQ3_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_22_TXQPKTQ3_PAGE_22_TXQPKTQ3_COUNT_ALIGN       0
#define SWITCH_PAGE_22_TXQPKTQ3_PAGE_22_TXQPKTQ3_COUNT_BITS        32
#define SWITCH_PAGE_22_TXQPKTQ3_PAGE_22_TXQPKTQ3_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_TxQPKTQ4
 ***************************************************************************/
/* switch :: PAGE_22_TxQPKTQ4 :: PAGE_22_TxQPKTQ4_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxQPKTQ4_PAGE_22_TxQPKTQ4_COUNT(x) WriteReg(SWITCH_PAGE_22_TXQPKTQ4,x)
#define Rd_switch_PAGE_22_TxQPKTQ4_PAGE_22_TxQPKTQ4_COUNT(x) ReadReg(SWITCH_PAGE_22_TXQPKTQ4)
#define SWITCH_PAGE_22_TXQPKTQ4_PAGE_22_TXQPKTQ4_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_22_TXQPKTQ4_PAGE_22_TXQPKTQ4_COUNT_ALIGN       0
#define SWITCH_PAGE_22_TXQPKTQ4_PAGE_22_TXQPKTQ4_COUNT_BITS        32
#define SWITCH_PAGE_22_TXQPKTQ4_PAGE_22_TXQPKTQ4_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_TxQPKTQ5
 ***************************************************************************/
/* switch :: PAGE_22_TxQPKTQ5 :: PAGE_22_TxQPKTQ5_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxQPKTQ5_PAGE_22_TxQPKTQ5_COUNT(x) WriteReg(SWITCH_PAGE_22_TXQPKTQ5,x)
#define Rd_switch_PAGE_22_TxQPKTQ5_PAGE_22_TxQPKTQ5_COUNT(x) ReadReg(SWITCH_PAGE_22_TXQPKTQ5)
#define SWITCH_PAGE_22_TXQPKTQ5_PAGE_22_TXQPKTQ5_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_22_TXQPKTQ5_PAGE_22_TXQPKTQ5_COUNT_ALIGN       0
#define SWITCH_PAGE_22_TXQPKTQ5_PAGE_22_TXQPKTQ5_COUNT_BITS        32
#define SWITCH_PAGE_22_TXQPKTQ5_PAGE_22_TXQPKTQ5_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_RxOctets
 ***************************************************************************/
/* switch :: PAGE_22_RxOctets :: PAGE_22_RxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_22_RxOctets_PAGE_22_RxOctets_COUNT(x) WriteReg(SWITCH_PAGE_22_RXOCTETS,x)
#define Rd_switch_PAGE_22_RxOctets_PAGE_22_RxOctets_COUNT(x) ReadReg(SWITCH_PAGE_22_RXOCTETS)
#define SWITCH_PAGE_22_RXOCTETS_PAGE_22_RXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_22_RXOCTETS_PAGE_22_RXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_22_RXOCTETS_PAGE_22_RXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_22_RXOCTETS_PAGE_22_RXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_RxUndersizePkts
 ***************************************************************************/
/* switch :: PAGE_22_RxUndersizePkts :: PAGE_22_RxUndersizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxUndersizePkts_PAGE_22_RxUndersizePkts_COUNT(x) WriteReg(SWITCH_PAGE_22_RXUNDERSIZEPKTS,x)
#define Rd_switch_PAGE_22_RxUndersizePkts_PAGE_22_RxUndersizePkts_COUNT(x) ReadReg(SWITCH_PAGE_22_RXUNDERSIZEPKTS)
#define SWITCH_PAGE_22_RXUNDERSIZEPKTS_PAGE_22_RXUNDERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXUNDERSIZEPKTS_PAGE_22_RXUNDERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXUNDERSIZEPKTS_PAGE_22_RXUNDERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXUNDERSIZEPKTS_PAGE_22_RXUNDERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxPausePkts
 ***************************************************************************/
/* switch :: PAGE_22_RxPausePkts :: PAGE_22_RxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxPausePkts_PAGE_22_RxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_22_RXPAUSEPKTS,x)
#define Rd_switch_PAGE_22_RxPausePkts_PAGE_22_RxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_22_RXPAUSEPKTS)
#define SWITCH_PAGE_22_RXPAUSEPKTS_PAGE_22_RXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_22_RXPAUSEPKTS_PAGE_22_RXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXPAUSEPKTS_PAGE_22_RXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_22_RXPAUSEPKTS_PAGE_22_RXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_22_RxPkts64Octets :: PAGE_22_RxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxPkts64Octets_PAGE_22_RxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_RXPKTS64OCTETS,x)
#define Rd_switch_PAGE_22_RxPkts64Octets_PAGE_22_RxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_RXPKTS64OCTETS)
#define SWITCH_PAGE_22_RXPKTS64OCTETS_PAGE_22_RXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXPKTS64OCTETS_PAGE_22_RXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXPKTS64OCTETS_PAGE_22_RXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXPKTS64OCTETS_PAGE_22_RXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_22_RxPkts65to127Octets :: PAGE_22_RxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxPkts65to127Octets_PAGE_22_RxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_RXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_22_RxPkts65to127Octets_PAGE_22_RxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_RXPKTS65TO127OCTETS)
#define SWITCH_PAGE_22_RXPKTS65TO127OCTETS_PAGE_22_RXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXPKTS65TO127OCTETS_PAGE_22_RXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXPKTS65TO127OCTETS_PAGE_22_RXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXPKTS65TO127OCTETS_PAGE_22_RXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_22_RxPkts128to255Octets :: PAGE_22_RxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxPkts128to255Octets_PAGE_22_RxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_RXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_22_RxPkts128to255Octets_PAGE_22_RxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_RXPKTS128TO255OCTETS)
#define SWITCH_PAGE_22_RXPKTS128TO255OCTETS_PAGE_22_RXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXPKTS128TO255OCTETS_PAGE_22_RXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXPKTS128TO255OCTETS_PAGE_22_RXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXPKTS128TO255OCTETS_PAGE_22_RXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_22_RxPkts256to511Octets :: PAGE_22_RxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxPkts256to511Octets_PAGE_22_RxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_RXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_22_RxPkts256to511Octets_PAGE_22_RxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_RXPKTS256TO511OCTETS)
#define SWITCH_PAGE_22_RXPKTS256TO511OCTETS_PAGE_22_RXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXPKTS256TO511OCTETS_PAGE_22_RXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXPKTS256TO511OCTETS_PAGE_22_RXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXPKTS256TO511OCTETS_PAGE_22_RXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_22_RxPkts512to1023Octets :: PAGE_22_RxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxPkts512to1023Octets_PAGE_22_RxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_RXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_22_RxPkts512to1023Octets_PAGE_22_RxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_RXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_22_RXPKTS512TO1023OCTETS_PAGE_22_RXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXPKTS512TO1023OCTETS_PAGE_22_RXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXPKTS512TO1023OCTETS_PAGE_22_RXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXPKTS512TO1023OCTETS_PAGE_22_RXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_22_RxPkts1024toMaxPktOctets :: PAGE_22_RxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxPkts1024toMaxPktOctets_PAGE_22_RxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_22_RXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_22_RxPkts1024toMaxPktOctets_PAGE_22_RxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_22_RXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_22_RXPKTS1024TOMAXPKTOCTETS_PAGE_22_RXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXPKTS1024TOMAXPKTOCTETS_PAGE_22_RXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXPKTS1024TOMAXPKTOCTETS_PAGE_22_RXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXPKTS1024TOMAXPKTOCTETS_PAGE_22_RXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxOversizePkts
 ***************************************************************************/
/* switch :: PAGE_22_RxOversizePkts :: PAGE_22_RxOversizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxOversizePkts_PAGE_22_RxOversizePkts_COUNT(x) WriteReg(SWITCH_PAGE_22_RXOVERSIZEPKTS,x)
#define Rd_switch_PAGE_22_RxOversizePkts_PAGE_22_RxOversizePkts_COUNT(x) ReadReg(SWITCH_PAGE_22_RXOVERSIZEPKTS)
#define SWITCH_PAGE_22_RXOVERSIZEPKTS_PAGE_22_RXOVERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXOVERSIZEPKTS_PAGE_22_RXOVERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXOVERSIZEPKTS_PAGE_22_RXOVERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXOVERSIZEPKTS_PAGE_22_RXOVERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxJabbers
 ***************************************************************************/
/* switch :: PAGE_22_RxJabbers :: PAGE_22_RxJabbers_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxJabbers_PAGE_22_RxJabbers_COUNT(x) WriteReg(SWITCH_PAGE_22_RXJABBERS,x)
#define Rd_switch_PAGE_22_RxJabbers_PAGE_22_RxJabbers_COUNT(x) ReadReg(SWITCH_PAGE_22_RXJABBERS)
#define SWITCH_PAGE_22_RXJABBERS_PAGE_22_RXJABBERS_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_22_RXJABBERS_PAGE_22_RXJABBERS_COUNT_ALIGN     0
#define SWITCH_PAGE_22_RXJABBERS_PAGE_22_RXJABBERS_COUNT_BITS      32
#define SWITCH_PAGE_22_RXJABBERS_PAGE_22_RXJABBERS_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_22_RxAlignmentErrors
 ***************************************************************************/
/* switch :: PAGE_22_RxAlignmentErrors :: PAGE_22_RxAlignmentErrors_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxAlignmentErrors_PAGE_22_RxAlignmentErrors_COUNT(x) WriteReg(SWITCH_PAGE_22_RXALIGNMENTERRORS,x)
#define Rd_switch_PAGE_22_RxAlignmentErrors_PAGE_22_RxAlignmentErrors_COUNT(x) ReadReg(SWITCH_PAGE_22_RXALIGNMENTERRORS)
#define SWITCH_PAGE_22_RXALIGNMENTERRORS_PAGE_22_RXALIGNMENTERRORS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXALIGNMENTERRORS_PAGE_22_RXALIGNMENTERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXALIGNMENTERRORS_PAGE_22_RXALIGNMENTERRORS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXALIGNMENTERRORS_PAGE_22_RXALIGNMENTERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxFCSErrors
 ***************************************************************************/
/* switch :: PAGE_22_RxFCSErrors :: PAGE_22_RxFCSErrors_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxFCSErrors_PAGE_22_RxFCSErrors_COUNT(x) WriteReg(SWITCH_PAGE_22_RXFCSERRORS,x)
#define Rd_switch_PAGE_22_RxFCSErrors_PAGE_22_RxFCSErrors_COUNT(x) ReadReg(SWITCH_PAGE_22_RXFCSERRORS)
#define SWITCH_PAGE_22_RXFCSERRORS_PAGE_22_RXFCSERRORS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_22_RXFCSERRORS_PAGE_22_RXFCSERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXFCSERRORS_PAGE_22_RXFCSERRORS_COUNT_BITS  32
#define SWITCH_PAGE_22_RXFCSERRORS_PAGE_22_RXFCSERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxGoodOctets
 ***************************************************************************/
/* switch :: PAGE_22_RxGoodOctets :: PAGE_22_RxGoodOctets_COUNT [63:00] */
#define Wr_switch_PAGE_22_RxGoodOctets_PAGE_22_RxGoodOctets_COUNT(x) WriteReg(SWITCH_PAGE_22_RXGOODOCTETS,x)
#define Rd_switch_PAGE_22_RxGoodOctets_PAGE_22_RxGoodOctets_COUNT(x) ReadReg(SWITCH_PAGE_22_RXGOODOCTETS)
#define SWITCH_PAGE_22_RXGOODOCTETS_PAGE_22_RXGOODOCTETS_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_22_RXGOODOCTETS_PAGE_22_RXGOODOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXGOODOCTETS_PAGE_22_RXGOODOCTETS_COUNT_BITS 64
#define SWITCH_PAGE_22_RXGOODOCTETS_PAGE_22_RXGOODOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxDropPkts
 ***************************************************************************/
/* switch :: PAGE_22_RxDropPkts :: PAGE_22_RxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxDropPkts_PAGE_22_RxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_22_RXDROPPKTS,x)
#define Rd_switch_PAGE_22_RxDropPkts_PAGE_22_RxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_22_RXDROPPKTS)
#define SWITCH_PAGE_22_RXDROPPKTS_PAGE_22_RXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_22_RXDROPPKTS_PAGE_22_RXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_22_RXDROPPKTS_PAGE_22_RXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_22_RXDROPPKTS_PAGE_22_RXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_22_RxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_22_RxUnicastPkts :: PAGE_22_RxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxUnicastPkts_PAGE_22_RxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_22_RXUNICASTPKTS,x)
#define Rd_switch_PAGE_22_RxUnicastPkts_PAGE_22_RxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_22_RXUNICASTPKTS)
#define SWITCH_PAGE_22_RXUNICASTPKTS_PAGE_22_RXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXUNICASTPKTS_PAGE_22_RXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXUNICASTPKTS_PAGE_22_RXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXUNICASTPKTS_PAGE_22_RXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_22_RxMulticastPkts :: PAGE_22_RxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxMulticastPkts_PAGE_22_RxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_22_RXMULTICASTPKTS,x)
#define Rd_switch_PAGE_22_RxMulticastPkts_PAGE_22_RxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_22_RXMULTICASTPKTS)
#define SWITCH_PAGE_22_RXMULTICASTPKTS_PAGE_22_RXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXMULTICASTPKTS_PAGE_22_RXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXMULTICASTPKTS_PAGE_22_RXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXMULTICASTPKTS_PAGE_22_RXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_22_RxBroadcastPkts :: PAGE_22_RxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxBroadcastPkts_PAGE_22_RxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_22_RXBROADCASTPKTS,x)
#define Rd_switch_PAGE_22_RxBroadcastPkts_PAGE_22_RxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_22_RXBROADCASTPKTS)
#define SWITCH_PAGE_22_RXBROADCASTPKTS_PAGE_22_RXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_RXBROADCASTPKTS_PAGE_22_RXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXBROADCASTPKTS_PAGE_22_RXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_22_RXBROADCASTPKTS_PAGE_22_RXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxSAChanges
 ***************************************************************************/
/* switch :: PAGE_22_RxSAChanges :: PAGE_22_RxSAChanges_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxSAChanges_PAGE_22_RxSAChanges_COUNT(x) WriteReg(SWITCH_PAGE_22_RXSACHANGES,x)
#define Rd_switch_PAGE_22_RxSAChanges_PAGE_22_RxSAChanges_COUNT(x) ReadReg(SWITCH_PAGE_22_RXSACHANGES)
#define SWITCH_PAGE_22_RXSACHANGES_PAGE_22_RXSACHANGES_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_22_RXSACHANGES_PAGE_22_RXSACHANGES_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXSACHANGES_PAGE_22_RXSACHANGES_COUNT_BITS  32
#define SWITCH_PAGE_22_RXSACHANGES_PAGE_22_RXSACHANGES_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxFragments
 ***************************************************************************/
/* switch :: PAGE_22_RxFragments :: PAGE_22_RxFragments_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxFragments_PAGE_22_RxFragments_COUNT(x) WriteReg(SWITCH_PAGE_22_RXFRAGMENTS,x)
#define Rd_switch_PAGE_22_RxFragments_PAGE_22_RxFragments_COUNT(x) ReadReg(SWITCH_PAGE_22_RXFRAGMENTS)
#define SWITCH_PAGE_22_RXFRAGMENTS_PAGE_22_RXFRAGMENTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_22_RXFRAGMENTS_PAGE_22_RXFRAGMENTS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_RXFRAGMENTS_PAGE_22_RXFRAGMENTS_COUNT_BITS  32
#define SWITCH_PAGE_22_RXFRAGMENTS_PAGE_22_RXFRAGMENTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxJumboPkt
 ***************************************************************************/
/* switch :: PAGE_22_RxJumboPkt :: PAGE_22_RxJumboPkt_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxJumboPkt_PAGE_22_RxJumboPkt_COUNT(x) WriteReg(SWITCH_PAGE_22_RXJUMBOPKT,x)
#define Rd_switch_PAGE_22_RxJumboPkt_PAGE_22_RxJumboPkt_COUNT(x) ReadReg(SWITCH_PAGE_22_RXJUMBOPKT)
#define SWITCH_PAGE_22_RXJUMBOPKT_PAGE_22_RXJUMBOPKT_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_22_RXJUMBOPKT_PAGE_22_RXJUMBOPKT_COUNT_ALIGN   0
#define SWITCH_PAGE_22_RXJUMBOPKT_PAGE_22_RXJUMBOPKT_COUNT_BITS    32
#define SWITCH_PAGE_22_RXJUMBOPKT_PAGE_22_RXJUMBOPKT_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_22_RxSymblErr
 ***************************************************************************/
/* switch :: PAGE_22_RxSymblErr :: PAGE_22_RxSymblErr_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxSymblErr_PAGE_22_RxSymblErr_COUNT(x) WriteReg(SWITCH_PAGE_22_RXSYMBLERR,x)
#define Rd_switch_PAGE_22_RxSymblErr_PAGE_22_RxSymblErr_COUNT(x) ReadReg(SWITCH_PAGE_22_RXSYMBLERR)
#define SWITCH_PAGE_22_RXSYMBLERR_PAGE_22_RXSYMBLERR_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_22_RXSYMBLERR_PAGE_22_RXSYMBLERR_COUNT_ALIGN   0
#define SWITCH_PAGE_22_RXSYMBLERR_PAGE_22_RXSYMBLERR_COUNT_BITS    32
#define SWITCH_PAGE_22_RXSYMBLERR_PAGE_22_RXSYMBLERR_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_22_InRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_22_InRangeErrCount :: PAGE_22_InRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_22_InRangeErrCount_PAGE_22_InRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_22_INRANGEERRCOUNT,x)
#define Rd_switch_PAGE_22_InRangeErrCount_PAGE_22_InRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_22_INRANGEERRCOUNT)
#define SWITCH_PAGE_22_INRANGEERRCOUNT_PAGE_22_INRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_INRANGEERRCOUNT_PAGE_22_INRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_22_INRANGEERRCOUNT_PAGE_22_INRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_22_INRANGEERRCOUNT_PAGE_22_INRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_OutRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_22_OutRangeErrCount :: PAGE_22_OutRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_22_OutRangeErrCount_PAGE_22_OutRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_22_OUTRANGEERRCOUNT,x)
#define Rd_switch_PAGE_22_OutRangeErrCount_PAGE_22_OutRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_22_OUTRANGEERRCOUNT)
#define SWITCH_PAGE_22_OUTRANGEERRCOUNT_PAGE_22_OUTRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_OUTRANGEERRCOUNT_PAGE_22_OUTRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_22_OUTRANGEERRCOUNT_PAGE_22_OUTRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_22_OUTRANGEERRCOUNT_PAGE_22_OUTRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_EEE_LPI_EVENT
 ***************************************************************************/
/* switch :: PAGE_22_EEE_LPI_EVENT :: PAGE_22_EEE_LPI_EVENT_COUNT [31:00] */
#define Wr_switch_PAGE_22_EEE_LPI_EVENT_PAGE_22_EEE_LPI_EVENT_COUNT(x) WriteReg(SWITCH_PAGE_22_EEE_LPI_EVENT,x)
#define Rd_switch_PAGE_22_EEE_LPI_EVENT_PAGE_22_EEE_LPI_EVENT_COUNT(x) ReadReg(SWITCH_PAGE_22_EEE_LPI_EVENT)
#define SWITCH_PAGE_22_EEE_LPI_EVENT_PAGE_22_EEE_LPI_EVENT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_EEE_LPI_EVENT_PAGE_22_EEE_LPI_EVENT_COUNT_ALIGN 0
#define SWITCH_PAGE_22_EEE_LPI_EVENT_PAGE_22_EEE_LPI_EVENT_COUNT_BITS 32
#define SWITCH_PAGE_22_EEE_LPI_EVENT_PAGE_22_EEE_LPI_EVENT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_EEE_LPI_DURATION
 ***************************************************************************/
/* switch :: PAGE_22_EEE_LPI_DURATION :: PAGE_22_EEE_LPI_DURATION_COUNT [31:00] */
#define Wr_switch_PAGE_22_EEE_LPI_DURATION_PAGE_22_EEE_LPI_DURATION_COUNT(x) WriteReg(SWITCH_PAGE_22_EEE_LPI_DURATION,x)
#define Rd_switch_PAGE_22_EEE_LPI_DURATION_PAGE_22_EEE_LPI_DURATION_COUNT(x) ReadReg(SWITCH_PAGE_22_EEE_LPI_DURATION)
#define SWITCH_PAGE_22_EEE_LPI_DURATION_PAGE_22_EEE_LPI_DURATION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_EEE_LPI_DURATION_PAGE_22_EEE_LPI_DURATION_COUNT_ALIGN 0
#define SWITCH_PAGE_22_EEE_LPI_DURATION_PAGE_22_EEE_LPI_DURATION_COUNT_BITS 32
#define SWITCH_PAGE_22_EEE_LPI_DURATION_PAGE_22_EEE_LPI_DURATION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_RxDiscard
 ***************************************************************************/
/* switch :: PAGE_22_RxDiscard :: PAGE_22_RxDiscard_COUNT [31:00] */
#define Wr_switch_PAGE_22_RxDiscard_PAGE_22_RxDiscard_COUNT(x) WriteReg(SWITCH_PAGE_22_RXDISCARD,x)
#define Rd_switch_PAGE_22_RxDiscard_PAGE_22_RxDiscard_COUNT(x) ReadReg(SWITCH_PAGE_22_RXDISCARD)
#define SWITCH_PAGE_22_RXDISCARD_PAGE_22_RXDISCARD_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_22_RXDISCARD_PAGE_22_RXDISCARD_COUNT_ALIGN     0
#define SWITCH_PAGE_22_RXDISCARD_PAGE_22_RXDISCARD_COUNT_BITS      32
#define SWITCH_PAGE_22_RXDISCARD_PAGE_22_RXDISCARD_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_22_TxQPKTQ6
 ***************************************************************************/
/* switch :: PAGE_22_TxQPKTQ6 :: PAGE_22_TxQPKTQ6_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxQPKTQ6_PAGE_22_TxQPKTQ6_COUNT(x) WriteReg(SWITCH_PAGE_22_TXQPKTQ6,x)
#define Rd_switch_PAGE_22_TxQPKTQ6_PAGE_22_TxQPKTQ6_COUNT(x) ReadReg(SWITCH_PAGE_22_TXQPKTQ6)
#define SWITCH_PAGE_22_TXQPKTQ6_PAGE_22_TXQPKTQ6_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_22_TXQPKTQ6_PAGE_22_TXQPKTQ6_COUNT_ALIGN       0
#define SWITCH_PAGE_22_TXQPKTQ6_PAGE_22_TXQPKTQ6_COUNT_BITS        32
#define SWITCH_PAGE_22_TXQPKTQ6_PAGE_22_TXQPKTQ6_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_TxQPKTQ7
 ***************************************************************************/
/* switch :: PAGE_22_TxQPKTQ7 :: PAGE_22_TxQPKTQ7_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxQPKTQ7_PAGE_22_TxQPKTQ7_COUNT(x) WriteReg(SWITCH_PAGE_22_TXQPKTQ7,x)
#define Rd_switch_PAGE_22_TxQPKTQ7_PAGE_22_TxQPKTQ7_COUNT(x) ReadReg(SWITCH_PAGE_22_TXQPKTQ7)
#define SWITCH_PAGE_22_TXQPKTQ7_PAGE_22_TXQPKTQ7_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_22_TXQPKTQ7_PAGE_22_TXQPKTQ7_COUNT_ALIGN       0
#define SWITCH_PAGE_22_TXQPKTQ7_PAGE_22_TXQPKTQ7_COUNT_BITS        32
#define SWITCH_PAGE_22_TXQPKTQ7_PAGE_22_TXQPKTQ7_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_22_TxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_22_TxPkts64Octets :: PAGE_22_TxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxPkts64Octets_PAGE_22_TxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_TXPKTS64OCTETS,x)
#define Rd_switch_PAGE_22_TxPkts64Octets_PAGE_22_TxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_TXPKTS64OCTETS)
#define SWITCH_PAGE_22_TXPKTS64OCTETS_PAGE_22_TXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXPKTS64OCTETS_PAGE_22_TXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXPKTS64OCTETS_PAGE_22_TXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXPKTS64OCTETS_PAGE_22_TXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_22_TxPkts65to127Octets :: PAGE_22_TxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxPkts65to127Octets_PAGE_22_TxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_TXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_22_TxPkts65to127Octets_PAGE_22_TxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_TXPKTS65TO127OCTETS)
#define SWITCH_PAGE_22_TXPKTS65TO127OCTETS_PAGE_22_TXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXPKTS65TO127OCTETS_PAGE_22_TXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXPKTS65TO127OCTETS_PAGE_22_TXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXPKTS65TO127OCTETS_PAGE_22_TXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_22_TxPkts128to255Octets :: PAGE_22_TxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxPkts128to255Octets_PAGE_22_TxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_TXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_22_TxPkts128to255Octets_PAGE_22_TxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_TXPKTS128TO255OCTETS)
#define SWITCH_PAGE_22_TXPKTS128TO255OCTETS_PAGE_22_TXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXPKTS128TO255OCTETS_PAGE_22_TXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXPKTS128TO255OCTETS_PAGE_22_TXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXPKTS128TO255OCTETS_PAGE_22_TXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_22_TxPkts256to511Octets :: PAGE_22_TxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxPkts256to511Octets_PAGE_22_TxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_TXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_22_TxPkts256to511Octets_PAGE_22_TxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_TXPKTS256TO511OCTETS)
#define SWITCH_PAGE_22_TXPKTS256TO511OCTETS_PAGE_22_TXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXPKTS256TO511OCTETS_PAGE_22_TXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXPKTS256TO511OCTETS_PAGE_22_TXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXPKTS256TO511OCTETS_PAGE_22_TXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_22_TxPkts512to1023Octets :: PAGE_22_TxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxPkts512to1023Octets_PAGE_22_TxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_22_TXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_22_TxPkts512to1023Octets_PAGE_22_TxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_22_TXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_22_TXPKTS512TO1023OCTETS_PAGE_22_TXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXPKTS512TO1023OCTETS_PAGE_22_TXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXPKTS512TO1023OCTETS_PAGE_22_TXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXPKTS512TO1023OCTETS_PAGE_22_TXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_22_TxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_22_TxPkts1024toMaxPktOctets :: PAGE_22_TxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_22_TxPkts1024toMaxPktOctets_PAGE_22_TxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_22_TXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_22_TxPkts1024toMaxPktOctets_PAGE_22_TxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_22_TXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_22_TXPKTS1024TOMAXPKTOCTETS_PAGE_22_TXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_22_TXPKTS1024TOMAXPKTOCTETS_PAGE_22_TXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_22_TXPKTS1024TOMAXPKTOCTETS_PAGE_22_TXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_22_TXPKTS1024TOMAXPKTOCTETS_PAGE_22_TXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxOctets
 ***************************************************************************/
/* switch :: PAGE_23_TxOctets :: PAGE_23_TxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_23_TxOctets_PAGE_23_TxOctets_COUNT(x) WriteReg(SWITCH_PAGE_23_TXOCTETS,x)
#define Rd_switch_PAGE_23_TxOctets_PAGE_23_TxOctets_COUNT(x) ReadReg(SWITCH_PAGE_23_TXOCTETS)
#define SWITCH_PAGE_23_TXOCTETS_PAGE_23_TXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_23_TXOCTETS_PAGE_23_TXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_23_TXOCTETS_PAGE_23_TXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_23_TXOCTETS_PAGE_23_TXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_TxDropPkts
 ***************************************************************************/
/* switch :: PAGE_23_TxDropPkts :: PAGE_23_TxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxDropPkts_PAGE_23_TxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_23_TXDROPPKTS,x)
#define Rd_switch_PAGE_23_TxDropPkts_PAGE_23_TxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_23_TXDROPPKTS)
#define SWITCH_PAGE_23_TXDROPPKTS_PAGE_23_TXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_23_TXDROPPKTS_PAGE_23_TXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_23_TXDROPPKTS_PAGE_23_TXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_23_TXDROPPKTS_PAGE_23_TXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_23_TxQPKTQ0
 ***************************************************************************/
/* switch :: PAGE_23_TxQPKTQ0 :: PAGE_23_TxQPKTQ0_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxQPKTQ0_PAGE_23_TxQPKTQ0_COUNT(x) WriteReg(SWITCH_PAGE_23_TXQPKTQ0,x)
#define Rd_switch_PAGE_23_TxQPKTQ0_PAGE_23_TxQPKTQ0_COUNT(x) ReadReg(SWITCH_PAGE_23_TXQPKTQ0)
#define SWITCH_PAGE_23_TXQPKTQ0_PAGE_23_TXQPKTQ0_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_23_TXQPKTQ0_PAGE_23_TXQPKTQ0_COUNT_ALIGN       0
#define SWITCH_PAGE_23_TXQPKTQ0_PAGE_23_TXQPKTQ0_COUNT_BITS        32
#define SWITCH_PAGE_23_TXQPKTQ0_PAGE_23_TXQPKTQ0_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_TxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_23_TxBroadcastPkts :: PAGE_23_TxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxBroadcastPkts_PAGE_23_TxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_23_TXBROADCASTPKTS,x)
#define Rd_switch_PAGE_23_TxBroadcastPkts_PAGE_23_TxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_23_TXBROADCASTPKTS)
#define SWITCH_PAGE_23_TXBROADCASTPKTS_PAGE_23_TXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXBROADCASTPKTS_PAGE_23_TXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXBROADCASTPKTS_PAGE_23_TXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXBROADCASTPKTS_PAGE_23_TXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_23_TxMulticastPkts :: PAGE_23_TxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxMulticastPkts_PAGE_23_TxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_23_TXMULTICASTPKTS,x)
#define Rd_switch_PAGE_23_TxMulticastPkts_PAGE_23_TxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_23_TXMULTICASTPKTS)
#define SWITCH_PAGE_23_TXMULTICASTPKTS_PAGE_23_TXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXMULTICASTPKTS_PAGE_23_TXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXMULTICASTPKTS_PAGE_23_TXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXMULTICASTPKTS_PAGE_23_TXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_23_TxUnicastPkts :: PAGE_23_TxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxUnicastPkts_PAGE_23_TxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_23_TXUNICASTPKTS,x)
#define Rd_switch_PAGE_23_TxUnicastPkts_PAGE_23_TxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_23_TXUNICASTPKTS)
#define SWITCH_PAGE_23_TXUNICASTPKTS_PAGE_23_TXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXUNICASTPKTS_PAGE_23_TXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXUNICASTPKTS_PAGE_23_TXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXUNICASTPKTS_PAGE_23_TXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxCollisions
 ***************************************************************************/
/* switch :: PAGE_23_TxCollisions :: PAGE_23_TxCollisions_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxCollisions_PAGE_23_TxCollisions_COUNT(x) WriteReg(SWITCH_PAGE_23_TXCOLLISIONS,x)
#define Rd_switch_PAGE_23_TxCollisions_PAGE_23_TxCollisions_COUNT(x) ReadReg(SWITCH_PAGE_23_TXCOLLISIONS)
#define SWITCH_PAGE_23_TXCOLLISIONS_PAGE_23_TXCOLLISIONS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXCOLLISIONS_PAGE_23_TXCOLLISIONS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXCOLLISIONS_PAGE_23_TXCOLLISIONS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXCOLLISIONS_PAGE_23_TXCOLLISIONS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxSingleCollision
 ***************************************************************************/
/* switch :: PAGE_23_TxSingleCollision :: PAGE_23_TxSingleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxSingleCollision_PAGE_23_TxSingleCollision_COUNT(x) WriteReg(SWITCH_PAGE_23_TXSINGLECOLLISION,x)
#define Rd_switch_PAGE_23_TxSingleCollision_PAGE_23_TxSingleCollision_COUNT(x) ReadReg(SWITCH_PAGE_23_TXSINGLECOLLISION)
#define SWITCH_PAGE_23_TXSINGLECOLLISION_PAGE_23_TXSINGLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXSINGLECOLLISION_PAGE_23_TXSINGLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXSINGLECOLLISION_PAGE_23_TXSINGLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_23_TXSINGLECOLLISION_PAGE_23_TXSINGLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxMultipleCollision
 ***************************************************************************/
/* switch :: PAGE_23_TxMultipleCollision :: PAGE_23_TxMultipleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxMultipleCollision_PAGE_23_TxMultipleCollision_COUNT(x) WriteReg(SWITCH_PAGE_23_TXMULTIPLECOLLISION,x)
#define Rd_switch_PAGE_23_TxMultipleCollision_PAGE_23_TxMultipleCollision_COUNT(x) ReadReg(SWITCH_PAGE_23_TXMULTIPLECOLLISION)
#define SWITCH_PAGE_23_TXMULTIPLECOLLISION_PAGE_23_TXMULTIPLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXMULTIPLECOLLISION_PAGE_23_TXMULTIPLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXMULTIPLECOLLISION_PAGE_23_TXMULTIPLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_23_TXMULTIPLECOLLISION_PAGE_23_TXMULTIPLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxDeferredTransmit
 ***************************************************************************/
/* switch :: PAGE_23_TxDeferredTransmit :: PAGE_23_TxDeferredTransmit_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxDeferredTransmit_PAGE_23_TxDeferredTransmit_COUNT(x) WriteReg(SWITCH_PAGE_23_TXDEFERREDTRANSMIT,x)
#define Rd_switch_PAGE_23_TxDeferredTransmit_PAGE_23_TxDeferredTransmit_COUNT(x) ReadReg(SWITCH_PAGE_23_TXDEFERREDTRANSMIT)
#define SWITCH_PAGE_23_TXDEFERREDTRANSMIT_PAGE_23_TXDEFERREDTRANSMIT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXDEFERREDTRANSMIT_PAGE_23_TXDEFERREDTRANSMIT_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXDEFERREDTRANSMIT_PAGE_23_TXDEFERREDTRANSMIT_COUNT_BITS 32
#define SWITCH_PAGE_23_TXDEFERREDTRANSMIT_PAGE_23_TXDEFERREDTRANSMIT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxLateCollision
 ***************************************************************************/
/* switch :: PAGE_23_TxLateCollision :: PAGE_23_TxLateCollision_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxLateCollision_PAGE_23_TxLateCollision_COUNT(x) WriteReg(SWITCH_PAGE_23_TXLATECOLLISION,x)
#define Rd_switch_PAGE_23_TxLateCollision_PAGE_23_TxLateCollision_COUNT(x) ReadReg(SWITCH_PAGE_23_TXLATECOLLISION)
#define SWITCH_PAGE_23_TXLATECOLLISION_PAGE_23_TXLATECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXLATECOLLISION_PAGE_23_TXLATECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXLATECOLLISION_PAGE_23_TXLATECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_23_TXLATECOLLISION_PAGE_23_TXLATECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxExcessiveCollision
 ***************************************************************************/
/* switch :: PAGE_23_TxExcessiveCollision :: PAGE_23_TxExcessiveCollision_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxExcessiveCollision_PAGE_23_TxExcessiveCollision_COUNT(x) WriteReg(SWITCH_PAGE_23_TXEXCESSIVECOLLISION,x)
#define Rd_switch_PAGE_23_TxExcessiveCollision_PAGE_23_TxExcessiveCollision_COUNT(x) ReadReg(SWITCH_PAGE_23_TXEXCESSIVECOLLISION)
#define SWITCH_PAGE_23_TXEXCESSIVECOLLISION_PAGE_23_TXEXCESSIVECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXEXCESSIVECOLLISION_PAGE_23_TXEXCESSIVECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXEXCESSIVECOLLISION_PAGE_23_TXEXCESSIVECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_23_TXEXCESSIVECOLLISION_PAGE_23_TXEXCESSIVECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxFrameInDisc
 ***************************************************************************/
/* switch :: PAGE_23_TxFrameInDisc :: PAGE_23_TxFrameInDisc_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxFrameInDisc_PAGE_23_TxFrameInDisc_COUNT(x) WriteReg(SWITCH_PAGE_23_TXFRAMEINDISC,x)
#define Rd_switch_PAGE_23_TxFrameInDisc_PAGE_23_TxFrameInDisc_COUNT(x) ReadReg(SWITCH_PAGE_23_TXFRAMEINDISC)
#define SWITCH_PAGE_23_TXFRAMEINDISC_PAGE_23_TXFRAMEINDISC_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXFRAMEINDISC_PAGE_23_TXFRAMEINDISC_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXFRAMEINDISC_PAGE_23_TXFRAMEINDISC_COUNT_BITS 32
#define SWITCH_PAGE_23_TXFRAMEINDISC_PAGE_23_TXFRAMEINDISC_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxPausePkts
 ***************************************************************************/
/* switch :: PAGE_23_TxPausePkts :: PAGE_23_TxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxPausePkts_PAGE_23_TxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_23_TXPAUSEPKTS,x)
#define Rd_switch_PAGE_23_TxPausePkts_PAGE_23_TxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_23_TXPAUSEPKTS)
#define SWITCH_PAGE_23_TXPAUSEPKTS_PAGE_23_TXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_23_TXPAUSEPKTS_PAGE_23_TXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXPAUSEPKTS_PAGE_23_TXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_23_TXPAUSEPKTS_PAGE_23_TXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxQPKTQ1
 ***************************************************************************/
/* switch :: PAGE_23_TxQPKTQ1 :: PAGE_23_TxQPKTQ1_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxQPKTQ1_PAGE_23_TxQPKTQ1_COUNT(x) WriteReg(SWITCH_PAGE_23_TXQPKTQ1,x)
#define Rd_switch_PAGE_23_TxQPKTQ1_PAGE_23_TxQPKTQ1_COUNT(x) ReadReg(SWITCH_PAGE_23_TXQPKTQ1)
#define SWITCH_PAGE_23_TXQPKTQ1_PAGE_23_TXQPKTQ1_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_23_TXQPKTQ1_PAGE_23_TXQPKTQ1_COUNT_ALIGN       0
#define SWITCH_PAGE_23_TXQPKTQ1_PAGE_23_TXQPKTQ1_COUNT_BITS        32
#define SWITCH_PAGE_23_TXQPKTQ1_PAGE_23_TXQPKTQ1_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_TxQPKTQ2
 ***************************************************************************/
/* switch :: PAGE_23_TxQPKTQ2 :: PAGE_23_TxQPKTQ2_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxQPKTQ2_PAGE_23_TxQPKTQ2_COUNT(x) WriteReg(SWITCH_PAGE_23_TXQPKTQ2,x)
#define Rd_switch_PAGE_23_TxQPKTQ2_PAGE_23_TxQPKTQ2_COUNT(x) ReadReg(SWITCH_PAGE_23_TXQPKTQ2)
#define SWITCH_PAGE_23_TXQPKTQ2_PAGE_23_TXQPKTQ2_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_23_TXQPKTQ2_PAGE_23_TXQPKTQ2_COUNT_ALIGN       0
#define SWITCH_PAGE_23_TXQPKTQ2_PAGE_23_TXQPKTQ2_COUNT_BITS        32
#define SWITCH_PAGE_23_TXQPKTQ2_PAGE_23_TXQPKTQ2_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_TxQPKTQ3
 ***************************************************************************/
/* switch :: PAGE_23_TxQPKTQ3 :: PAGE_23_TxQPKTQ3_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxQPKTQ3_PAGE_23_TxQPKTQ3_COUNT(x) WriteReg(SWITCH_PAGE_23_TXQPKTQ3,x)
#define Rd_switch_PAGE_23_TxQPKTQ3_PAGE_23_TxQPKTQ3_COUNT(x) ReadReg(SWITCH_PAGE_23_TXQPKTQ3)
#define SWITCH_PAGE_23_TXQPKTQ3_PAGE_23_TXQPKTQ3_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_23_TXQPKTQ3_PAGE_23_TXQPKTQ3_COUNT_ALIGN       0
#define SWITCH_PAGE_23_TXQPKTQ3_PAGE_23_TXQPKTQ3_COUNT_BITS        32
#define SWITCH_PAGE_23_TXQPKTQ3_PAGE_23_TXQPKTQ3_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_TxQPKTQ4
 ***************************************************************************/
/* switch :: PAGE_23_TxQPKTQ4 :: PAGE_23_TxQPKTQ4_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxQPKTQ4_PAGE_23_TxQPKTQ4_COUNT(x) WriteReg(SWITCH_PAGE_23_TXQPKTQ4,x)
#define Rd_switch_PAGE_23_TxQPKTQ4_PAGE_23_TxQPKTQ4_COUNT(x) ReadReg(SWITCH_PAGE_23_TXQPKTQ4)
#define SWITCH_PAGE_23_TXQPKTQ4_PAGE_23_TXQPKTQ4_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_23_TXQPKTQ4_PAGE_23_TXQPKTQ4_COUNT_ALIGN       0
#define SWITCH_PAGE_23_TXQPKTQ4_PAGE_23_TXQPKTQ4_COUNT_BITS        32
#define SWITCH_PAGE_23_TXQPKTQ4_PAGE_23_TXQPKTQ4_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_TxQPKTQ5
 ***************************************************************************/
/* switch :: PAGE_23_TxQPKTQ5 :: PAGE_23_TxQPKTQ5_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxQPKTQ5_PAGE_23_TxQPKTQ5_COUNT(x) WriteReg(SWITCH_PAGE_23_TXQPKTQ5,x)
#define Rd_switch_PAGE_23_TxQPKTQ5_PAGE_23_TxQPKTQ5_COUNT(x) ReadReg(SWITCH_PAGE_23_TXQPKTQ5)
#define SWITCH_PAGE_23_TXQPKTQ5_PAGE_23_TXQPKTQ5_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_23_TXQPKTQ5_PAGE_23_TXQPKTQ5_COUNT_ALIGN       0
#define SWITCH_PAGE_23_TXQPKTQ5_PAGE_23_TXQPKTQ5_COUNT_BITS        32
#define SWITCH_PAGE_23_TXQPKTQ5_PAGE_23_TXQPKTQ5_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_RxOctets
 ***************************************************************************/
/* switch :: PAGE_23_RxOctets :: PAGE_23_RxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_23_RxOctets_PAGE_23_RxOctets_COUNT(x) WriteReg(SWITCH_PAGE_23_RXOCTETS,x)
#define Rd_switch_PAGE_23_RxOctets_PAGE_23_RxOctets_COUNT(x) ReadReg(SWITCH_PAGE_23_RXOCTETS)
#define SWITCH_PAGE_23_RXOCTETS_PAGE_23_RXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_23_RXOCTETS_PAGE_23_RXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_23_RXOCTETS_PAGE_23_RXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_23_RXOCTETS_PAGE_23_RXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_RxUndersizePkts
 ***************************************************************************/
/* switch :: PAGE_23_RxUndersizePkts :: PAGE_23_RxUndersizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxUndersizePkts_PAGE_23_RxUndersizePkts_COUNT(x) WriteReg(SWITCH_PAGE_23_RXUNDERSIZEPKTS,x)
#define Rd_switch_PAGE_23_RxUndersizePkts_PAGE_23_RxUndersizePkts_COUNT(x) ReadReg(SWITCH_PAGE_23_RXUNDERSIZEPKTS)
#define SWITCH_PAGE_23_RXUNDERSIZEPKTS_PAGE_23_RXUNDERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXUNDERSIZEPKTS_PAGE_23_RXUNDERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXUNDERSIZEPKTS_PAGE_23_RXUNDERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXUNDERSIZEPKTS_PAGE_23_RXUNDERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxPausePkts
 ***************************************************************************/
/* switch :: PAGE_23_RxPausePkts :: PAGE_23_RxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxPausePkts_PAGE_23_RxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_23_RXPAUSEPKTS,x)
#define Rd_switch_PAGE_23_RxPausePkts_PAGE_23_RxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_23_RXPAUSEPKTS)
#define SWITCH_PAGE_23_RXPAUSEPKTS_PAGE_23_RXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_23_RXPAUSEPKTS_PAGE_23_RXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXPAUSEPKTS_PAGE_23_RXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_23_RXPAUSEPKTS_PAGE_23_RXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_23_RxPkts64Octets :: PAGE_23_RxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxPkts64Octets_PAGE_23_RxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_RXPKTS64OCTETS,x)
#define Rd_switch_PAGE_23_RxPkts64Octets_PAGE_23_RxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_RXPKTS64OCTETS)
#define SWITCH_PAGE_23_RXPKTS64OCTETS_PAGE_23_RXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXPKTS64OCTETS_PAGE_23_RXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXPKTS64OCTETS_PAGE_23_RXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXPKTS64OCTETS_PAGE_23_RXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_23_RxPkts65to127Octets :: PAGE_23_RxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxPkts65to127Octets_PAGE_23_RxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_RXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_23_RxPkts65to127Octets_PAGE_23_RxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_RXPKTS65TO127OCTETS)
#define SWITCH_PAGE_23_RXPKTS65TO127OCTETS_PAGE_23_RXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXPKTS65TO127OCTETS_PAGE_23_RXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXPKTS65TO127OCTETS_PAGE_23_RXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXPKTS65TO127OCTETS_PAGE_23_RXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_23_RxPkts128to255Octets :: PAGE_23_RxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxPkts128to255Octets_PAGE_23_RxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_RXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_23_RxPkts128to255Octets_PAGE_23_RxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_RXPKTS128TO255OCTETS)
#define SWITCH_PAGE_23_RXPKTS128TO255OCTETS_PAGE_23_RXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXPKTS128TO255OCTETS_PAGE_23_RXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXPKTS128TO255OCTETS_PAGE_23_RXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXPKTS128TO255OCTETS_PAGE_23_RXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_23_RxPkts256to511Octets :: PAGE_23_RxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxPkts256to511Octets_PAGE_23_RxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_RXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_23_RxPkts256to511Octets_PAGE_23_RxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_RXPKTS256TO511OCTETS)
#define SWITCH_PAGE_23_RXPKTS256TO511OCTETS_PAGE_23_RXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXPKTS256TO511OCTETS_PAGE_23_RXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXPKTS256TO511OCTETS_PAGE_23_RXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXPKTS256TO511OCTETS_PAGE_23_RXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_23_RxPkts512to1023Octets :: PAGE_23_RxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxPkts512to1023Octets_PAGE_23_RxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_RXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_23_RxPkts512to1023Octets_PAGE_23_RxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_RXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_23_RXPKTS512TO1023OCTETS_PAGE_23_RXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXPKTS512TO1023OCTETS_PAGE_23_RXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXPKTS512TO1023OCTETS_PAGE_23_RXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXPKTS512TO1023OCTETS_PAGE_23_RXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_23_RxPkts1024toMaxPktOctets :: PAGE_23_RxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxPkts1024toMaxPktOctets_PAGE_23_RxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_23_RXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_23_RxPkts1024toMaxPktOctets_PAGE_23_RxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_23_RXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_23_RXPKTS1024TOMAXPKTOCTETS_PAGE_23_RXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXPKTS1024TOMAXPKTOCTETS_PAGE_23_RXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXPKTS1024TOMAXPKTOCTETS_PAGE_23_RXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXPKTS1024TOMAXPKTOCTETS_PAGE_23_RXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxOversizePkts
 ***************************************************************************/
/* switch :: PAGE_23_RxOversizePkts :: PAGE_23_RxOversizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxOversizePkts_PAGE_23_RxOversizePkts_COUNT(x) WriteReg(SWITCH_PAGE_23_RXOVERSIZEPKTS,x)
#define Rd_switch_PAGE_23_RxOversizePkts_PAGE_23_RxOversizePkts_COUNT(x) ReadReg(SWITCH_PAGE_23_RXOVERSIZEPKTS)
#define SWITCH_PAGE_23_RXOVERSIZEPKTS_PAGE_23_RXOVERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXOVERSIZEPKTS_PAGE_23_RXOVERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXOVERSIZEPKTS_PAGE_23_RXOVERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXOVERSIZEPKTS_PAGE_23_RXOVERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxJabbers
 ***************************************************************************/
/* switch :: PAGE_23_RxJabbers :: PAGE_23_RxJabbers_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxJabbers_PAGE_23_RxJabbers_COUNT(x) WriteReg(SWITCH_PAGE_23_RXJABBERS,x)
#define Rd_switch_PAGE_23_RxJabbers_PAGE_23_RxJabbers_COUNT(x) ReadReg(SWITCH_PAGE_23_RXJABBERS)
#define SWITCH_PAGE_23_RXJABBERS_PAGE_23_RXJABBERS_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_23_RXJABBERS_PAGE_23_RXJABBERS_COUNT_ALIGN     0
#define SWITCH_PAGE_23_RXJABBERS_PAGE_23_RXJABBERS_COUNT_BITS      32
#define SWITCH_PAGE_23_RXJABBERS_PAGE_23_RXJABBERS_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_23_RxAlignmentErrors
 ***************************************************************************/
/* switch :: PAGE_23_RxAlignmentErrors :: PAGE_23_RxAlignmentErrors_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxAlignmentErrors_PAGE_23_RxAlignmentErrors_COUNT(x) WriteReg(SWITCH_PAGE_23_RXALIGNMENTERRORS,x)
#define Rd_switch_PAGE_23_RxAlignmentErrors_PAGE_23_RxAlignmentErrors_COUNT(x) ReadReg(SWITCH_PAGE_23_RXALIGNMENTERRORS)
#define SWITCH_PAGE_23_RXALIGNMENTERRORS_PAGE_23_RXALIGNMENTERRORS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXALIGNMENTERRORS_PAGE_23_RXALIGNMENTERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXALIGNMENTERRORS_PAGE_23_RXALIGNMENTERRORS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXALIGNMENTERRORS_PAGE_23_RXALIGNMENTERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxFCSErrors
 ***************************************************************************/
/* switch :: PAGE_23_RxFCSErrors :: PAGE_23_RxFCSErrors_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxFCSErrors_PAGE_23_RxFCSErrors_COUNT(x) WriteReg(SWITCH_PAGE_23_RXFCSERRORS,x)
#define Rd_switch_PAGE_23_RxFCSErrors_PAGE_23_RxFCSErrors_COUNT(x) ReadReg(SWITCH_PAGE_23_RXFCSERRORS)
#define SWITCH_PAGE_23_RXFCSERRORS_PAGE_23_RXFCSERRORS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_23_RXFCSERRORS_PAGE_23_RXFCSERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXFCSERRORS_PAGE_23_RXFCSERRORS_COUNT_BITS  32
#define SWITCH_PAGE_23_RXFCSERRORS_PAGE_23_RXFCSERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxGoodOctets
 ***************************************************************************/
/* switch :: PAGE_23_RxGoodOctets :: PAGE_23_RxGoodOctets_COUNT [63:00] */
#define Wr_switch_PAGE_23_RxGoodOctets_PAGE_23_RxGoodOctets_COUNT(x) WriteReg(SWITCH_PAGE_23_RXGOODOCTETS,x)
#define Rd_switch_PAGE_23_RxGoodOctets_PAGE_23_RxGoodOctets_COUNT(x) ReadReg(SWITCH_PAGE_23_RXGOODOCTETS)
#define SWITCH_PAGE_23_RXGOODOCTETS_PAGE_23_RXGOODOCTETS_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_23_RXGOODOCTETS_PAGE_23_RXGOODOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXGOODOCTETS_PAGE_23_RXGOODOCTETS_COUNT_BITS 64
#define SWITCH_PAGE_23_RXGOODOCTETS_PAGE_23_RXGOODOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxDropPkts
 ***************************************************************************/
/* switch :: PAGE_23_RxDropPkts :: PAGE_23_RxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxDropPkts_PAGE_23_RxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_23_RXDROPPKTS,x)
#define Rd_switch_PAGE_23_RxDropPkts_PAGE_23_RxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_23_RXDROPPKTS)
#define SWITCH_PAGE_23_RXDROPPKTS_PAGE_23_RXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_23_RXDROPPKTS_PAGE_23_RXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_23_RXDROPPKTS_PAGE_23_RXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_23_RXDROPPKTS_PAGE_23_RXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_23_RxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_23_RxUnicastPkts :: PAGE_23_RxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxUnicastPkts_PAGE_23_RxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_23_RXUNICASTPKTS,x)
#define Rd_switch_PAGE_23_RxUnicastPkts_PAGE_23_RxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_23_RXUNICASTPKTS)
#define SWITCH_PAGE_23_RXUNICASTPKTS_PAGE_23_RXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXUNICASTPKTS_PAGE_23_RXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXUNICASTPKTS_PAGE_23_RXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXUNICASTPKTS_PAGE_23_RXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_23_RxMulticastPkts :: PAGE_23_RxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxMulticastPkts_PAGE_23_RxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_23_RXMULTICASTPKTS,x)
#define Rd_switch_PAGE_23_RxMulticastPkts_PAGE_23_RxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_23_RXMULTICASTPKTS)
#define SWITCH_PAGE_23_RXMULTICASTPKTS_PAGE_23_RXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXMULTICASTPKTS_PAGE_23_RXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXMULTICASTPKTS_PAGE_23_RXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXMULTICASTPKTS_PAGE_23_RXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_23_RxBroadcastPkts :: PAGE_23_RxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxBroadcastPkts_PAGE_23_RxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_23_RXBROADCASTPKTS,x)
#define Rd_switch_PAGE_23_RxBroadcastPkts_PAGE_23_RxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_23_RXBROADCASTPKTS)
#define SWITCH_PAGE_23_RXBROADCASTPKTS_PAGE_23_RXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_RXBROADCASTPKTS_PAGE_23_RXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXBROADCASTPKTS_PAGE_23_RXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_23_RXBROADCASTPKTS_PAGE_23_RXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxSAChanges
 ***************************************************************************/
/* switch :: PAGE_23_RxSAChanges :: PAGE_23_RxSAChanges_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxSAChanges_PAGE_23_RxSAChanges_COUNT(x) WriteReg(SWITCH_PAGE_23_RXSACHANGES,x)
#define Rd_switch_PAGE_23_RxSAChanges_PAGE_23_RxSAChanges_COUNT(x) ReadReg(SWITCH_PAGE_23_RXSACHANGES)
#define SWITCH_PAGE_23_RXSACHANGES_PAGE_23_RXSACHANGES_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_23_RXSACHANGES_PAGE_23_RXSACHANGES_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXSACHANGES_PAGE_23_RXSACHANGES_COUNT_BITS  32
#define SWITCH_PAGE_23_RXSACHANGES_PAGE_23_RXSACHANGES_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxFragments
 ***************************************************************************/
/* switch :: PAGE_23_RxFragments :: PAGE_23_RxFragments_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxFragments_PAGE_23_RxFragments_COUNT(x) WriteReg(SWITCH_PAGE_23_RXFRAGMENTS,x)
#define Rd_switch_PAGE_23_RxFragments_PAGE_23_RxFragments_COUNT(x) ReadReg(SWITCH_PAGE_23_RXFRAGMENTS)
#define SWITCH_PAGE_23_RXFRAGMENTS_PAGE_23_RXFRAGMENTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_23_RXFRAGMENTS_PAGE_23_RXFRAGMENTS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_RXFRAGMENTS_PAGE_23_RXFRAGMENTS_COUNT_BITS  32
#define SWITCH_PAGE_23_RXFRAGMENTS_PAGE_23_RXFRAGMENTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxJumboPkt
 ***************************************************************************/
/* switch :: PAGE_23_RxJumboPkt :: PAGE_23_RxJumboPkt_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxJumboPkt_PAGE_23_RxJumboPkt_COUNT(x) WriteReg(SWITCH_PAGE_23_RXJUMBOPKT,x)
#define Rd_switch_PAGE_23_RxJumboPkt_PAGE_23_RxJumboPkt_COUNT(x) ReadReg(SWITCH_PAGE_23_RXJUMBOPKT)
#define SWITCH_PAGE_23_RXJUMBOPKT_PAGE_23_RXJUMBOPKT_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_23_RXJUMBOPKT_PAGE_23_RXJUMBOPKT_COUNT_ALIGN   0
#define SWITCH_PAGE_23_RXJUMBOPKT_PAGE_23_RXJUMBOPKT_COUNT_BITS    32
#define SWITCH_PAGE_23_RXJUMBOPKT_PAGE_23_RXJUMBOPKT_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_23_RxSymblErr
 ***************************************************************************/
/* switch :: PAGE_23_RxSymblErr :: PAGE_23_RxSymblErr_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxSymblErr_PAGE_23_RxSymblErr_COUNT(x) WriteReg(SWITCH_PAGE_23_RXSYMBLERR,x)
#define Rd_switch_PAGE_23_RxSymblErr_PAGE_23_RxSymblErr_COUNT(x) ReadReg(SWITCH_PAGE_23_RXSYMBLERR)
#define SWITCH_PAGE_23_RXSYMBLERR_PAGE_23_RXSYMBLERR_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_23_RXSYMBLERR_PAGE_23_RXSYMBLERR_COUNT_ALIGN   0
#define SWITCH_PAGE_23_RXSYMBLERR_PAGE_23_RXSYMBLERR_COUNT_BITS    32
#define SWITCH_PAGE_23_RXSYMBLERR_PAGE_23_RXSYMBLERR_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_23_InRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_23_InRangeErrCount :: PAGE_23_InRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_23_InRangeErrCount_PAGE_23_InRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_23_INRANGEERRCOUNT,x)
#define Rd_switch_PAGE_23_InRangeErrCount_PAGE_23_InRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_23_INRANGEERRCOUNT)
#define SWITCH_PAGE_23_INRANGEERRCOUNT_PAGE_23_INRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_INRANGEERRCOUNT_PAGE_23_INRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_23_INRANGEERRCOUNT_PAGE_23_INRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_23_INRANGEERRCOUNT_PAGE_23_INRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_OutRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_23_OutRangeErrCount :: PAGE_23_OutRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_23_OutRangeErrCount_PAGE_23_OutRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_23_OUTRANGEERRCOUNT,x)
#define Rd_switch_PAGE_23_OutRangeErrCount_PAGE_23_OutRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_23_OUTRANGEERRCOUNT)
#define SWITCH_PAGE_23_OUTRANGEERRCOUNT_PAGE_23_OUTRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_OUTRANGEERRCOUNT_PAGE_23_OUTRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_23_OUTRANGEERRCOUNT_PAGE_23_OUTRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_23_OUTRANGEERRCOUNT_PAGE_23_OUTRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_EEE_LPI_EVENT
 ***************************************************************************/
/* switch :: PAGE_23_EEE_LPI_EVENT :: PAGE_23_EEE_LPI_EVENT_COUNT [31:00] */
#define Wr_switch_PAGE_23_EEE_LPI_EVENT_PAGE_23_EEE_LPI_EVENT_COUNT(x) WriteReg(SWITCH_PAGE_23_EEE_LPI_EVENT,x)
#define Rd_switch_PAGE_23_EEE_LPI_EVENT_PAGE_23_EEE_LPI_EVENT_COUNT(x) ReadReg(SWITCH_PAGE_23_EEE_LPI_EVENT)
#define SWITCH_PAGE_23_EEE_LPI_EVENT_PAGE_23_EEE_LPI_EVENT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_EEE_LPI_EVENT_PAGE_23_EEE_LPI_EVENT_COUNT_ALIGN 0
#define SWITCH_PAGE_23_EEE_LPI_EVENT_PAGE_23_EEE_LPI_EVENT_COUNT_BITS 32
#define SWITCH_PAGE_23_EEE_LPI_EVENT_PAGE_23_EEE_LPI_EVENT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_EEE_LPI_DURATION
 ***************************************************************************/
/* switch :: PAGE_23_EEE_LPI_DURATION :: PAGE_23_EEE_LPI_DURATION_COUNT [31:00] */
#define Wr_switch_PAGE_23_EEE_LPI_DURATION_PAGE_23_EEE_LPI_DURATION_COUNT(x) WriteReg(SWITCH_PAGE_23_EEE_LPI_DURATION,x)
#define Rd_switch_PAGE_23_EEE_LPI_DURATION_PAGE_23_EEE_LPI_DURATION_COUNT(x) ReadReg(SWITCH_PAGE_23_EEE_LPI_DURATION)
#define SWITCH_PAGE_23_EEE_LPI_DURATION_PAGE_23_EEE_LPI_DURATION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_EEE_LPI_DURATION_PAGE_23_EEE_LPI_DURATION_COUNT_ALIGN 0
#define SWITCH_PAGE_23_EEE_LPI_DURATION_PAGE_23_EEE_LPI_DURATION_COUNT_BITS 32
#define SWITCH_PAGE_23_EEE_LPI_DURATION_PAGE_23_EEE_LPI_DURATION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_RxDiscard
 ***************************************************************************/
/* switch :: PAGE_23_RxDiscard :: PAGE_23_RxDiscard_COUNT [31:00] */
#define Wr_switch_PAGE_23_RxDiscard_PAGE_23_RxDiscard_COUNT(x) WriteReg(SWITCH_PAGE_23_RXDISCARD,x)
#define Rd_switch_PAGE_23_RxDiscard_PAGE_23_RxDiscard_COUNT(x) ReadReg(SWITCH_PAGE_23_RXDISCARD)
#define SWITCH_PAGE_23_RXDISCARD_PAGE_23_RXDISCARD_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_23_RXDISCARD_PAGE_23_RXDISCARD_COUNT_ALIGN     0
#define SWITCH_PAGE_23_RXDISCARD_PAGE_23_RXDISCARD_COUNT_BITS      32
#define SWITCH_PAGE_23_RXDISCARD_PAGE_23_RXDISCARD_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_23_TxQPKTQ6
 ***************************************************************************/
/* switch :: PAGE_23_TxQPKTQ6 :: PAGE_23_TxQPKTQ6_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxQPKTQ6_PAGE_23_TxQPKTQ6_COUNT(x) WriteReg(SWITCH_PAGE_23_TXQPKTQ6,x)
#define Rd_switch_PAGE_23_TxQPKTQ6_PAGE_23_TxQPKTQ6_COUNT(x) ReadReg(SWITCH_PAGE_23_TXQPKTQ6)
#define SWITCH_PAGE_23_TXQPKTQ6_PAGE_23_TXQPKTQ6_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_23_TXQPKTQ6_PAGE_23_TXQPKTQ6_COUNT_ALIGN       0
#define SWITCH_PAGE_23_TXQPKTQ6_PAGE_23_TXQPKTQ6_COUNT_BITS        32
#define SWITCH_PAGE_23_TXQPKTQ6_PAGE_23_TXQPKTQ6_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_TxQPKTQ7
 ***************************************************************************/
/* switch :: PAGE_23_TxQPKTQ7 :: PAGE_23_TxQPKTQ7_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxQPKTQ7_PAGE_23_TxQPKTQ7_COUNT(x) WriteReg(SWITCH_PAGE_23_TXQPKTQ7,x)
#define Rd_switch_PAGE_23_TxQPKTQ7_PAGE_23_TxQPKTQ7_COUNT(x) ReadReg(SWITCH_PAGE_23_TXQPKTQ7)
#define SWITCH_PAGE_23_TXQPKTQ7_PAGE_23_TXQPKTQ7_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_23_TXQPKTQ7_PAGE_23_TXQPKTQ7_COUNT_ALIGN       0
#define SWITCH_PAGE_23_TXQPKTQ7_PAGE_23_TXQPKTQ7_COUNT_BITS        32
#define SWITCH_PAGE_23_TXQPKTQ7_PAGE_23_TXQPKTQ7_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_23_TxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_23_TxPkts64Octets :: PAGE_23_TxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxPkts64Octets_PAGE_23_TxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_TXPKTS64OCTETS,x)
#define Rd_switch_PAGE_23_TxPkts64Octets_PAGE_23_TxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_TXPKTS64OCTETS)
#define SWITCH_PAGE_23_TXPKTS64OCTETS_PAGE_23_TXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXPKTS64OCTETS_PAGE_23_TXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXPKTS64OCTETS_PAGE_23_TXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXPKTS64OCTETS_PAGE_23_TXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_23_TxPkts65to127Octets :: PAGE_23_TxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxPkts65to127Octets_PAGE_23_TxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_TXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_23_TxPkts65to127Octets_PAGE_23_TxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_TXPKTS65TO127OCTETS)
#define SWITCH_PAGE_23_TXPKTS65TO127OCTETS_PAGE_23_TXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXPKTS65TO127OCTETS_PAGE_23_TXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXPKTS65TO127OCTETS_PAGE_23_TXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXPKTS65TO127OCTETS_PAGE_23_TXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_23_TxPkts128to255Octets :: PAGE_23_TxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxPkts128to255Octets_PAGE_23_TxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_TXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_23_TxPkts128to255Octets_PAGE_23_TxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_TXPKTS128TO255OCTETS)
#define SWITCH_PAGE_23_TXPKTS128TO255OCTETS_PAGE_23_TXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXPKTS128TO255OCTETS_PAGE_23_TXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXPKTS128TO255OCTETS_PAGE_23_TXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXPKTS128TO255OCTETS_PAGE_23_TXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_23_TxPkts256to511Octets :: PAGE_23_TxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxPkts256to511Octets_PAGE_23_TxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_TXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_23_TxPkts256to511Octets_PAGE_23_TxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_TXPKTS256TO511OCTETS)
#define SWITCH_PAGE_23_TXPKTS256TO511OCTETS_PAGE_23_TXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXPKTS256TO511OCTETS_PAGE_23_TXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXPKTS256TO511OCTETS_PAGE_23_TXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXPKTS256TO511OCTETS_PAGE_23_TXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_23_TxPkts512to1023Octets :: PAGE_23_TxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxPkts512to1023Octets_PAGE_23_TxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_23_TXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_23_TxPkts512to1023Octets_PAGE_23_TxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_23_TXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_23_TXPKTS512TO1023OCTETS_PAGE_23_TXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXPKTS512TO1023OCTETS_PAGE_23_TXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXPKTS512TO1023OCTETS_PAGE_23_TXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXPKTS512TO1023OCTETS_PAGE_23_TXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_23_TxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_23_TxPkts1024toMaxPktOctets :: PAGE_23_TxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_23_TxPkts1024toMaxPktOctets_PAGE_23_TxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_23_TXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_23_TxPkts1024toMaxPktOctets_PAGE_23_TxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_23_TXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_23_TXPKTS1024TOMAXPKTOCTETS_PAGE_23_TXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_23_TXPKTS1024TOMAXPKTOCTETS_PAGE_23_TXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_23_TXPKTS1024TOMAXPKTOCTETS_PAGE_23_TXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_23_TXPKTS1024TOMAXPKTOCTETS_PAGE_23_TXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxOctets
 ***************************************************************************/
/* switch :: PAGE_24_TxOctets :: PAGE_24_TxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_24_TxOctets_PAGE_24_TxOctets_COUNT(x) WriteReg(SWITCH_PAGE_24_TXOCTETS,x)
#define Rd_switch_PAGE_24_TxOctets_PAGE_24_TxOctets_COUNT(x) ReadReg(SWITCH_PAGE_24_TXOCTETS)
#define SWITCH_PAGE_24_TXOCTETS_PAGE_24_TXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_24_TXOCTETS_PAGE_24_TXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_24_TXOCTETS_PAGE_24_TXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_24_TXOCTETS_PAGE_24_TXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_TxDropPkts
 ***************************************************************************/
/* switch :: PAGE_24_TxDropPkts :: PAGE_24_TxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxDropPkts_PAGE_24_TxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_24_TXDROPPKTS,x)
#define Rd_switch_PAGE_24_TxDropPkts_PAGE_24_TxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_24_TXDROPPKTS)
#define SWITCH_PAGE_24_TXDROPPKTS_PAGE_24_TXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_24_TXDROPPKTS_PAGE_24_TXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_24_TXDROPPKTS_PAGE_24_TXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_24_TXDROPPKTS_PAGE_24_TXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_24_TxQPKTQ0
 ***************************************************************************/
/* switch :: PAGE_24_TxQPKTQ0 :: PAGE_24_TxQPKTQ0_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxQPKTQ0_PAGE_24_TxQPKTQ0_COUNT(x) WriteReg(SWITCH_PAGE_24_TXQPKTQ0,x)
#define Rd_switch_PAGE_24_TxQPKTQ0_PAGE_24_TxQPKTQ0_COUNT(x) ReadReg(SWITCH_PAGE_24_TXQPKTQ0)
#define SWITCH_PAGE_24_TXQPKTQ0_PAGE_24_TXQPKTQ0_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_24_TXQPKTQ0_PAGE_24_TXQPKTQ0_COUNT_ALIGN       0
#define SWITCH_PAGE_24_TXQPKTQ0_PAGE_24_TXQPKTQ0_COUNT_BITS        32
#define SWITCH_PAGE_24_TXQPKTQ0_PAGE_24_TXQPKTQ0_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_TxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_24_TxBroadcastPkts :: PAGE_24_TxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxBroadcastPkts_PAGE_24_TxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_24_TXBROADCASTPKTS,x)
#define Rd_switch_PAGE_24_TxBroadcastPkts_PAGE_24_TxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_24_TXBROADCASTPKTS)
#define SWITCH_PAGE_24_TXBROADCASTPKTS_PAGE_24_TXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXBROADCASTPKTS_PAGE_24_TXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXBROADCASTPKTS_PAGE_24_TXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXBROADCASTPKTS_PAGE_24_TXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_24_TxMulticastPkts :: PAGE_24_TxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxMulticastPkts_PAGE_24_TxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_24_TXMULTICASTPKTS,x)
#define Rd_switch_PAGE_24_TxMulticastPkts_PAGE_24_TxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_24_TXMULTICASTPKTS)
#define SWITCH_PAGE_24_TXMULTICASTPKTS_PAGE_24_TXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXMULTICASTPKTS_PAGE_24_TXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXMULTICASTPKTS_PAGE_24_TXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXMULTICASTPKTS_PAGE_24_TXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_24_TxUnicastPkts :: PAGE_24_TxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxUnicastPkts_PAGE_24_TxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_24_TXUNICASTPKTS,x)
#define Rd_switch_PAGE_24_TxUnicastPkts_PAGE_24_TxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_24_TXUNICASTPKTS)
#define SWITCH_PAGE_24_TXUNICASTPKTS_PAGE_24_TXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXUNICASTPKTS_PAGE_24_TXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXUNICASTPKTS_PAGE_24_TXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXUNICASTPKTS_PAGE_24_TXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxCollisions
 ***************************************************************************/
/* switch :: PAGE_24_TxCollisions :: PAGE_24_TxCollisions_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxCollisions_PAGE_24_TxCollisions_COUNT(x) WriteReg(SWITCH_PAGE_24_TXCOLLISIONS,x)
#define Rd_switch_PAGE_24_TxCollisions_PAGE_24_TxCollisions_COUNT(x) ReadReg(SWITCH_PAGE_24_TXCOLLISIONS)
#define SWITCH_PAGE_24_TXCOLLISIONS_PAGE_24_TXCOLLISIONS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXCOLLISIONS_PAGE_24_TXCOLLISIONS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXCOLLISIONS_PAGE_24_TXCOLLISIONS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXCOLLISIONS_PAGE_24_TXCOLLISIONS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxSingleCollision
 ***************************************************************************/
/* switch :: PAGE_24_TxSingleCollision :: PAGE_24_TxSingleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxSingleCollision_PAGE_24_TxSingleCollision_COUNT(x) WriteReg(SWITCH_PAGE_24_TXSINGLECOLLISION,x)
#define Rd_switch_PAGE_24_TxSingleCollision_PAGE_24_TxSingleCollision_COUNT(x) ReadReg(SWITCH_PAGE_24_TXSINGLECOLLISION)
#define SWITCH_PAGE_24_TXSINGLECOLLISION_PAGE_24_TXSINGLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXSINGLECOLLISION_PAGE_24_TXSINGLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXSINGLECOLLISION_PAGE_24_TXSINGLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_24_TXSINGLECOLLISION_PAGE_24_TXSINGLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxMultipleCollision
 ***************************************************************************/
/* switch :: PAGE_24_TxMultipleCollision :: PAGE_24_TxMultipleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxMultipleCollision_PAGE_24_TxMultipleCollision_COUNT(x) WriteReg(SWITCH_PAGE_24_TXMULTIPLECOLLISION,x)
#define Rd_switch_PAGE_24_TxMultipleCollision_PAGE_24_TxMultipleCollision_COUNT(x) ReadReg(SWITCH_PAGE_24_TXMULTIPLECOLLISION)
#define SWITCH_PAGE_24_TXMULTIPLECOLLISION_PAGE_24_TXMULTIPLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXMULTIPLECOLLISION_PAGE_24_TXMULTIPLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXMULTIPLECOLLISION_PAGE_24_TXMULTIPLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_24_TXMULTIPLECOLLISION_PAGE_24_TXMULTIPLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxDeferredTransmit
 ***************************************************************************/
/* switch :: PAGE_24_TxDeferredTransmit :: PAGE_24_TxDeferredTransmit_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxDeferredTransmit_PAGE_24_TxDeferredTransmit_COUNT(x) WriteReg(SWITCH_PAGE_24_TXDEFERREDTRANSMIT,x)
#define Rd_switch_PAGE_24_TxDeferredTransmit_PAGE_24_TxDeferredTransmit_COUNT(x) ReadReg(SWITCH_PAGE_24_TXDEFERREDTRANSMIT)
#define SWITCH_PAGE_24_TXDEFERREDTRANSMIT_PAGE_24_TXDEFERREDTRANSMIT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXDEFERREDTRANSMIT_PAGE_24_TXDEFERREDTRANSMIT_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXDEFERREDTRANSMIT_PAGE_24_TXDEFERREDTRANSMIT_COUNT_BITS 32
#define SWITCH_PAGE_24_TXDEFERREDTRANSMIT_PAGE_24_TXDEFERREDTRANSMIT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxLateCollision
 ***************************************************************************/
/* switch :: PAGE_24_TxLateCollision :: PAGE_24_TxLateCollision_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxLateCollision_PAGE_24_TxLateCollision_COUNT(x) WriteReg(SWITCH_PAGE_24_TXLATECOLLISION,x)
#define Rd_switch_PAGE_24_TxLateCollision_PAGE_24_TxLateCollision_COUNT(x) ReadReg(SWITCH_PAGE_24_TXLATECOLLISION)
#define SWITCH_PAGE_24_TXLATECOLLISION_PAGE_24_TXLATECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXLATECOLLISION_PAGE_24_TXLATECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXLATECOLLISION_PAGE_24_TXLATECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_24_TXLATECOLLISION_PAGE_24_TXLATECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxExcessiveCollision
 ***************************************************************************/
/* switch :: PAGE_24_TxExcessiveCollision :: PAGE_24_TxExcessiveCollision_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxExcessiveCollision_PAGE_24_TxExcessiveCollision_COUNT(x) WriteReg(SWITCH_PAGE_24_TXEXCESSIVECOLLISION,x)
#define Rd_switch_PAGE_24_TxExcessiveCollision_PAGE_24_TxExcessiveCollision_COUNT(x) ReadReg(SWITCH_PAGE_24_TXEXCESSIVECOLLISION)
#define SWITCH_PAGE_24_TXEXCESSIVECOLLISION_PAGE_24_TXEXCESSIVECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXEXCESSIVECOLLISION_PAGE_24_TXEXCESSIVECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXEXCESSIVECOLLISION_PAGE_24_TXEXCESSIVECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_24_TXEXCESSIVECOLLISION_PAGE_24_TXEXCESSIVECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxFrameInDisc
 ***************************************************************************/
/* switch :: PAGE_24_TxFrameInDisc :: PAGE_24_TxFrameInDisc_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxFrameInDisc_PAGE_24_TxFrameInDisc_COUNT(x) WriteReg(SWITCH_PAGE_24_TXFRAMEINDISC,x)
#define Rd_switch_PAGE_24_TxFrameInDisc_PAGE_24_TxFrameInDisc_COUNT(x) ReadReg(SWITCH_PAGE_24_TXFRAMEINDISC)
#define SWITCH_PAGE_24_TXFRAMEINDISC_PAGE_24_TXFRAMEINDISC_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXFRAMEINDISC_PAGE_24_TXFRAMEINDISC_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXFRAMEINDISC_PAGE_24_TXFRAMEINDISC_COUNT_BITS 32
#define SWITCH_PAGE_24_TXFRAMEINDISC_PAGE_24_TXFRAMEINDISC_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxPausePkts
 ***************************************************************************/
/* switch :: PAGE_24_TxPausePkts :: PAGE_24_TxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxPausePkts_PAGE_24_TxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_24_TXPAUSEPKTS,x)
#define Rd_switch_PAGE_24_TxPausePkts_PAGE_24_TxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_24_TXPAUSEPKTS)
#define SWITCH_PAGE_24_TXPAUSEPKTS_PAGE_24_TXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_24_TXPAUSEPKTS_PAGE_24_TXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXPAUSEPKTS_PAGE_24_TXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_24_TXPAUSEPKTS_PAGE_24_TXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxQPKTQ1
 ***************************************************************************/
/* switch :: PAGE_24_TxQPKTQ1 :: PAGE_24_TxQPKTQ1_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxQPKTQ1_PAGE_24_TxQPKTQ1_COUNT(x) WriteReg(SWITCH_PAGE_24_TXQPKTQ1,x)
#define Rd_switch_PAGE_24_TxQPKTQ1_PAGE_24_TxQPKTQ1_COUNT(x) ReadReg(SWITCH_PAGE_24_TXQPKTQ1)
#define SWITCH_PAGE_24_TXQPKTQ1_PAGE_24_TXQPKTQ1_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_24_TXQPKTQ1_PAGE_24_TXQPKTQ1_COUNT_ALIGN       0
#define SWITCH_PAGE_24_TXQPKTQ1_PAGE_24_TXQPKTQ1_COUNT_BITS        32
#define SWITCH_PAGE_24_TXQPKTQ1_PAGE_24_TXQPKTQ1_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_TxQPKTQ2
 ***************************************************************************/
/* switch :: PAGE_24_TxQPKTQ2 :: PAGE_24_TxQPKTQ2_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxQPKTQ2_PAGE_24_TxQPKTQ2_COUNT(x) WriteReg(SWITCH_PAGE_24_TXQPKTQ2,x)
#define Rd_switch_PAGE_24_TxQPKTQ2_PAGE_24_TxQPKTQ2_COUNT(x) ReadReg(SWITCH_PAGE_24_TXQPKTQ2)
#define SWITCH_PAGE_24_TXQPKTQ2_PAGE_24_TXQPKTQ2_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_24_TXQPKTQ2_PAGE_24_TXQPKTQ2_COUNT_ALIGN       0
#define SWITCH_PAGE_24_TXQPKTQ2_PAGE_24_TXQPKTQ2_COUNT_BITS        32
#define SWITCH_PAGE_24_TXQPKTQ2_PAGE_24_TXQPKTQ2_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_TxQPKTQ3
 ***************************************************************************/
/* switch :: PAGE_24_TxQPKTQ3 :: PAGE_24_TxQPKTQ3_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxQPKTQ3_PAGE_24_TxQPKTQ3_COUNT(x) WriteReg(SWITCH_PAGE_24_TXQPKTQ3,x)
#define Rd_switch_PAGE_24_TxQPKTQ3_PAGE_24_TxQPKTQ3_COUNT(x) ReadReg(SWITCH_PAGE_24_TXQPKTQ3)
#define SWITCH_PAGE_24_TXQPKTQ3_PAGE_24_TXQPKTQ3_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_24_TXQPKTQ3_PAGE_24_TXQPKTQ3_COUNT_ALIGN       0
#define SWITCH_PAGE_24_TXQPKTQ3_PAGE_24_TXQPKTQ3_COUNT_BITS        32
#define SWITCH_PAGE_24_TXQPKTQ3_PAGE_24_TXQPKTQ3_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_TxQPKTQ4
 ***************************************************************************/
/* switch :: PAGE_24_TxQPKTQ4 :: PAGE_24_TxQPKTQ4_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxQPKTQ4_PAGE_24_TxQPKTQ4_COUNT(x) WriteReg(SWITCH_PAGE_24_TXQPKTQ4,x)
#define Rd_switch_PAGE_24_TxQPKTQ4_PAGE_24_TxQPKTQ4_COUNT(x) ReadReg(SWITCH_PAGE_24_TXQPKTQ4)
#define SWITCH_PAGE_24_TXQPKTQ4_PAGE_24_TXQPKTQ4_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_24_TXQPKTQ4_PAGE_24_TXQPKTQ4_COUNT_ALIGN       0
#define SWITCH_PAGE_24_TXQPKTQ4_PAGE_24_TXQPKTQ4_COUNT_BITS        32
#define SWITCH_PAGE_24_TXQPKTQ4_PAGE_24_TXQPKTQ4_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_TxQPKTQ5
 ***************************************************************************/
/* switch :: PAGE_24_TxQPKTQ5 :: PAGE_24_TxQPKTQ5_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxQPKTQ5_PAGE_24_TxQPKTQ5_COUNT(x) WriteReg(SWITCH_PAGE_24_TXQPKTQ5,x)
#define Rd_switch_PAGE_24_TxQPKTQ5_PAGE_24_TxQPKTQ5_COUNT(x) ReadReg(SWITCH_PAGE_24_TXQPKTQ5)
#define SWITCH_PAGE_24_TXQPKTQ5_PAGE_24_TXQPKTQ5_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_24_TXQPKTQ5_PAGE_24_TXQPKTQ5_COUNT_ALIGN       0
#define SWITCH_PAGE_24_TXQPKTQ5_PAGE_24_TXQPKTQ5_COUNT_BITS        32
#define SWITCH_PAGE_24_TXQPKTQ5_PAGE_24_TXQPKTQ5_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_RxOctets
 ***************************************************************************/
/* switch :: PAGE_24_RxOctets :: PAGE_24_RxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_24_RxOctets_PAGE_24_RxOctets_COUNT(x) WriteReg(SWITCH_PAGE_24_RXOCTETS,x)
#define Rd_switch_PAGE_24_RxOctets_PAGE_24_RxOctets_COUNT(x) ReadReg(SWITCH_PAGE_24_RXOCTETS)
#define SWITCH_PAGE_24_RXOCTETS_PAGE_24_RXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_24_RXOCTETS_PAGE_24_RXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_24_RXOCTETS_PAGE_24_RXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_24_RXOCTETS_PAGE_24_RXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_RxUndersizePkts
 ***************************************************************************/
/* switch :: PAGE_24_RxUndersizePkts :: PAGE_24_RxUndersizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxUndersizePkts_PAGE_24_RxUndersizePkts_COUNT(x) WriteReg(SWITCH_PAGE_24_RXUNDERSIZEPKTS,x)
#define Rd_switch_PAGE_24_RxUndersizePkts_PAGE_24_RxUndersizePkts_COUNT(x) ReadReg(SWITCH_PAGE_24_RXUNDERSIZEPKTS)
#define SWITCH_PAGE_24_RXUNDERSIZEPKTS_PAGE_24_RXUNDERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXUNDERSIZEPKTS_PAGE_24_RXUNDERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXUNDERSIZEPKTS_PAGE_24_RXUNDERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXUNDERSIZEPKTS_PAGE_24_RXUNDERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxPausePkts
 ***************************************************************************/
/* switch :: PAGE_24_RxPausePkts :: PAGE_24_RxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxPausePkts_PAGE_24_RxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_24_RXPAUSEPKTS,x)
#define Rd_switch_PAGE_24_RxPausePkts_PAGE_24_RxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_24_RXPAUSEPKTS)
#define SWITCH_PAGE_24_RXPAUSEPKTS_PAGE_24_RXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_24_RXPAUSEPKTS_PAGE_24_RXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXPAUSEPKTS_PAGE_24_RXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_24_RXPAUSEPKTS_PAGE_24_RXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_24_RxPkts64Octets :: PAGE_24_RxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxPkts64Octets_PAGE_24_RxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_RXPKTS64OCTETS,x)
#define Rd_switch_PAGE_24_RxPkts64Octets_PAGE_24_RxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_RXPKTS64OCTETS)
#define SWITCH_PAGE_24_RXPKTS64OCTETS_PAGE_24_RXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXPKTS64OCTETS_PAGE_24_RXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXPKTS64OCTETS_PAGE_24_RXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXPKTS64OCTETS_PAGE_24_RXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_24_RxPkts65to127Octets :: PAGE_24_RxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxPkts65to127Octets_PAGE_24_RxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_RXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_24_RxPkts65to127Octets_PAGE_24_RxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_RXPKTS65TO127OCTETS)
#define SWITCH_PAGE_24_RXPKTS65TO127OCTETS_PAGE_24_RXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXPKTS65TO127OCTETS_PAGE_24_RXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXPKTS65TO127OCTETS_PAGE_24_RXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXPKTS65TO127OCTETS_PAGE_24_RXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_24_RxPkts128to255Octets :: PAGE_24_RxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxPkts128to255Octets_PAGE_24_RxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_RXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_24_RxPkts128to255Octets_PAGE_24_RxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_RXPKTS128TO255OCTETS)
#define SWITCH_PAGE_24_RXPKTS128TO255OCTETS_PAGE_24_RXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXPKTS128TO255OCTETS_PAGE_24_RXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXPKTS128TO255OCTETS_PAGE_24_RXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXPKTS128TO255OCTETS_PAGE_24_RXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_24_RxPkts256to511Octets :: PAGE_24_RxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxPkts256to511Octets_PAGE_24_RxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_RXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_24_RxPkts256to511Octets_PAGE_24_RxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_RXPKTS256TO511OCTETS)
#define SWITCH_PAGE_24_RXPKTS256TO511OCTETS_PAGE_24_RXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXPKTS256TO511OCTETS_PAGE_24_RXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXPKTS256TO511OCTETS_PAGE_24_RXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXPKTS256TO511OCTETS_PAGE_24_RXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_24_RxPkts512to1023Octets :: PAGE_24_RxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxPkts512to1023Octets_PAGE_24_RxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_RXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_24_RxPkts512to1023Octets_PAGE_24_RxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_RXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_24_RXPKTS512TO1023OCTETS_PAGE_24_RXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXPKTS512TO1023OCTETS_PAGE_24_RXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXPKTS512TO1023OCTETS_PAGE_24_RXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXPKTS512TO1023OCTETS_PAGE_24_RXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_24_RxPkts1024toMaxPktOctets :: PAGE_24_RxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxPkts1024toMaxPktOctets_PAGE_24_RxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_24_RXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_24_RxPkts1024toMaxPktOctets_PAGE_24_RxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_24_RXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_24_RXPKTS1024TOMAXPKTOCTETS_PAGE_24_RXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXPKTS1024TOMAXPKTOCTETS_PAGE_24_RXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXPKTS1024TOMAXPKTOCTETS_PAGE_24_RXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXPKTS1024TOMAXPKTOCTETS_PAGE_24_RXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxOversizePkts
 ***************************************************************************/
/* switch :: PAGE_24_RxOversizePkts :: PAGE_24_RxOversizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxOversizePkts_PAGE_24_RxOversizePkts_COUNT(x) WriteReg(SWITCH_PAGE_24_RXOVERSIZEPKTS,x)
#define Rd_switch_PAGE_24_RxOversizePkts_PAGE_24_RxOversizePkts_COUNT(x) ReadReg(SWITCH_PAGE_24_RXOVERSIZEPKTS)
#define SWITCH_PAGE_24_RXOVERSIZEPKTS_PAGE_24_RXOVERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXOVERSIZEPKTS_PAGE_24_RXOVERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXOVERSIZEPKTS_PAGE_24_RXOVERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXOVERSIZEPKTS_PAGE_24_RXOVERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxJabbers
 ***************************************************************************/
/* switch :: PAGE_24_RxJabbers :: PAGE_24_RxJabbers_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxJabbers_PAGE_24_RxJabbers_COUNT(x) WriteReg(SWITCH_PAGE_24_RXJABBERS,x)
#define Rd_switch_PAGE_24_RxJabbers_PAGE_24_RxJabbers_COUNT(x) ReadReg(SWITCH_PAGE_24_RXJABBERS)
#define SWITCH_PAGE_24_RXJABBERS_PAGE_24_RXJABBERS_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_24_RXJABBERS_PAGE_24_RXJABBERS_COUNT_ALIGN     0
#define SWITCH_PAGE_24_RXJABBERS_PAGE_24_RXJABBERS_COUNT_BITS      32
#define SWITCH_PAGE_24_RXJABBERS_PAGE_24_RXJABBERS_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_24_RxAlignmentErrors
 ***************************************************************************/
/* switch :: PAGE_24_RxAlignmentErrors :: PAGE_24_RxAlignmentErrors_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxAlignmentErrors_PAGE_24_RxAlignmentErrors_COUNT(x) WriteReg(SWITCH_PAGE_24_RXALIGNMENTERRORS,x)
#define Rd_switch_PAGE_24_RxAlignmentErrors_PAGE_24_RxAlignmentErrors_COUNT(x) ReadReg(SWITCH_PAGE_24_RXALIGNMENTERRORS)
#define SWITCH_PAGE_24_RXALIGNMENTERRORS_PAGE_24_RXALIGNMENTERRORS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXALIGNMENTERRORS_PAGE_24_RXALIGNMENTERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXALIGNMENTERRORS_PAGE_24_RXALIGNMENTERRORS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXALIGNMENTERRORS_PAGE_24_RXALIGNMENTERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxFCSErrors
 ***************************************************************************/
/* switch :: PAGE_24_RxFCSErrors :: PAGE_24_RxFCSErrors_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxFCSErrors_PAGE_24_RxFCSErrors_COUNT(x) WriteReg(SWITCH_PAGE_24_RXFCSERRORS,x)
#define Rd_switch_PAGE_24_RxFCSErrors_PAGE_24_RxFCSErrors_COUNT(x) ReadReg(SWITCH_PAGE_24_RXFCSERRORS)
#define SWITCH_PAGE_24_RXFCSERRORS_PAGE_24_RXFCSERRORS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_24_RXFCSERRORS_PAGE_24_RXFCSERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXFCSERRORS_PAGE_24_RXFCSERRORS_COUNT_BITS  32
#define SWITCH_PAGE_24_RXFCSERRORS_PAGE_24_RXFCSERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxGoodOctets
 ***************************************************************************/
/* switch :: PAGE_24_RxGoodOctets :: PAGE_24_RxGoodOctets_COUNT [63:00] */
#define Wr_switch_PAGE_24_RxGoodOctets_PAGE_24_RxGoodOctets_COUNT(x) WriteReg(SWITCH_PAGE_24_RXGOODOCTETS,x)
#define Rd_switch_PAGE_24_RxGoodOctets_PAGE_24_RxGoodOctets_COUNT(x) ReadReg(SWITCH_PAGE_24_RXGOODOCTETS)
#define SWITCH_PAGE_24_RXGOODOCTETS_PAGE_24_RXGOODOCTETS_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_24_RXGOODOCTETS_PAGE_24_RXGOODOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXGOODOCTETS_PAGE_24_RXGOODOCTETS_COUNT_BITS 64
#define SWITCH_PAGE_24_RXGOODOCTETS_PAGE_24_RXGOODOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxDropPkts
 ***************************************************************************/
/* switch :: PAGE_24_RxDropPkts :: PAGE_24_RxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxDropPkts_PAGE_24_RxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_24_RXDROPPKTS,x)
#define Rd_switch_PAGE_24_RxDropPkts_PAGE_24_RxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_24_RXDROPPKTS)
#define SWITCH_PAGE_24_RXDROPPKTS_PAGE_24_RXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_24_RXDROPPKTS_PAGE_24_RXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_24_RXDROPPKTS_PAGE_24_RXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_24_RXDROPPKTS_PAGE_24_RXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_24_RxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_24_RxUnicastPkts :: PAGE_24_RxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxUnicastPkts_PAGE_24_RxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_24_RXUNICASTPKTS,x)
#define Rd_switch_PAGE_24_RxUnicastPkts_PAGE_24_RxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_24_RXUNICASTPKTS)
#define SWITCH_PAGE_24_RXUNICASTPKTS_PAGE_24_RXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXUNICASTPKTS_PAGE_24_RXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXUNICASTPKTS_PAGE_24_RXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXUNICASTPKTS_PAGE_24_RXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_24_RxMulticastPkts :: PAGE_24_RxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxMulticastPkts_PAGE_24_RxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_24_RXMULTICASTPKTS,x)
#define Rd_switch_PAGE_24_RxMulticastPkts_PAGE_24_RxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_24_RXMULTICASTPKTS)
#define SWITCH_PAGE_24_RXMULTICASTPKTS_PAGE_24_RXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXMULTICASTPKTS_PAGE_24_RXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXMULTICASTPKTS_PAGE_24_RXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXMULTICASTPKTS_PAGE_24_RXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_24_RxBroadcastPkts :: PAGE_24_RxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxBroadcastPkts_PAGE_24_RxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_24_RXBROADCASTPKTS,x)
#define Rd_switch_PAGE_24_RxBroadcastPkts_PAGE_24_RxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_24_RXBROADCASTPKTS)
#define SWITCH_PAGE_24_RXBROADCASTPKTS_PAGE_24_RXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_RXBROADCASTPKTS_PAGE_24_RXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXBROADCASTPKTS_PAGE_24_RXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_24_RXBROADCASTPKTS_PAGE_24_RXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxSAChanges
 ***************************************************************************/
/* switch :: PAGE_24_RxSAChanges :: PAGE_24_RxSAChanges_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxSAChanges_PAGE_24_RxSAChanges_COUNT(x) WriteReg(SWITCH_PAGE_24_RXSACHANGES,x)
#define Rd_switch_PAGE_24_RxSAChanges_PAGE_24_RxSAChanges_COUNT(x) ReadReg(SWITCH_PAGE_24_RXSACHANGES)
#define SWITCH_PAGE_24_RXSACHANGES_PAGE_24_RXSACHANGES_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_24_RXSACHANGES_PAGE_24_RXSACHANGES_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXSACHANGES_PAGE_24_RXSACHANGES_COUNT_BITS  32
#define SWITCH_PAGE_24_RXSACHANGES_PAGE_24_RXSACHANGES_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxFragments
 ***************************************************************************/
/* switch :: PAGE_24_RxFragments :: PAGE_24_RxFragments_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxFragments_PAGE_24_RxFragments_COUNT(x) WriteReg(SWITCH_PAGE_24_RXFRAGMENTS,x)
#define Rd_switch_PAGE_24_RxFragments_PAGE_24_RxFragments_COUNT(x) ReadReg(SWITCH_PAGE_24_RXFRAGMENTS)
#define SWITCH_PAGE_24_RXFRAGMENTS_PAGE_24_RXFRAGMENTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_24_RXFRAGMENTS_PAGE_24_RXFRAGMENTS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_RXFRAGMENTS_PAGE_24_RXFRAGMENTS_COUNT_BITS  32
#define SWITCH_PAGE_24_RXFRAGMENTS_PAGE_24_RXFRAGMENTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxJumboPkt
 ***************************************************************************/
/* switch :: PAGE_24_RxJumboPkt :: PAGE_24_RxJumboPkt_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxJumboPkt_PAGE_24_RxJumboPkt_COUNT(x) WriteReg(SWITCH_PAGE_24_RXJUMBOPKT,x)
#define Rd_switch_PAGE_24_RxJumboPkt_PAGE_24_RxJumboPkt_COUNT(x) ReadReg(SWITCH_PAGE_24_RXJUMBOPKT)
#define SWITCH_PAGE_24_RXJUMBOPKT_PAGE_24_RXJUMBOPKT_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_24_RXJUMBOPKT_PAGE_24_RXJUMBOPKT_COUNT_ALIGN   0
#define SWITCH_PAGE_24_RXJUMBOPKT_PAGE_24_RXJUMBOPKT_COUNT_BITS    32
#define SWITCH_PAGE_24_RXJUMBOPKT_PAGE_24_RXJUMBOPKT_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_24_RxSymblErr
 ***************************************************************************/
/* switch :: PAGE_24_RxSymblErr :: PAGE_24_RxSymblErr_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxSymblErr_PAGE_24_RxSymblErr_COUNT(x) WriteReg(SWITCH_PAGE_24_RXSYMBLERR,x)
#define Rd_switch_PAGE_24_RxSymblErr_PAGE_24_RxSymblErr_COUNT(x) ReadReg(SWITCH_PAGE_24_RXSYMBLERR)
#define SWITCH_PAGE_24_RXSYMBLERR_PAGE_24_RXSYMBLERR_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_24_RXSYMBLERR_PAGE_24_RXSYMBLERR_COUNT_ALIGN   0
#define SWITCH_PAGE_24_RXSYMBLERR_PAGE_24_RXSYMBLERR_COUNT_BITS    32
#define SWITCH_PAGE_24_RXSYMBLERR_PAGE_24_RXSYMBLERR_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_24_InRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_24_InRangeErrCount :: PAGE_24_InRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_24_InRangeErrCount_PAGE_24_InRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_24_INRANGEERRCOUNT,x)
#define Rd_switch_PAGE_24_InRangeErrCount_PAGE_24_InRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_24_INRANGEERRCOUNT)
#define SWITCH_PAGE_24_INRANGEERRCOUNT_PAGE_24_INRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_INRANGEERRCOUNT_PAGE_24_INRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_24_INRANGEERRCOUNT_PAGE_24_INRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_24_INRANGEERRCOUNT_PAGE_24_INRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_OutRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_24_OutRangeErrCount :: PAGE_24_OutRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_24_OutRangeErrCount_PAGE_24_OutRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_24_OUTRANGEERRCOUNT,x)
#define Rd_switch_PAGE_24_OutRangeErrCount_PAGE_24_OutRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_24_OUTRANGEERRCOUNT)
#define SWITCH_PAGE_24_OUTRANGEERRCOUNT_PAGE_24_OUTRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_OUTRANGEERRCOUNT_PAGE_24_OUTRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_24_OUTRANGEERRCOUNT_PAGE_24_OUTRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_24_OUTRANGEERRCOUNT_PAGE_24_OUTRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_EEE_LPI_EVENT
 ***************************************************************************/
/* switch :: PAGE_24_EEE_LPI_EVENT :: PAGE_24_EEE_LPI_EVENT_COUNT [31:00] */
#define Wr_switch_PAGE_24_EEE_LPI_EVENT_PAGE_24_EEE_LPI_EVENT_COUNT(x) WriteReg(SWITCH_PAGE_24_EEE_LPI_EVENT,x)
#define Rd_switch_PAGE_24_EEE_LPI_EVENT_PAGE_24_EEE_LPI_EVENT_COUNT(x) ReadReg(SWITCH_PAGE_24_EEE_LPI_EVENT)
#define SWITCH_PAGE_24_EEE_LPI_EVENT_PAGE_24_EEE_LPI_EVENT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_EEE_LPI_EVENT_PAGE_24_EEE_LPI_EVENT_COUNT_ALIGN 0
#define SWITCH_PAGE_24_EEE_LPI_EVENT_PAGE_24_EEE_LPI_EVENT_COUNT_BITS 32
#define SWITCH_PAGE_24_EEE_LPI_EVENT_PAGE_24_EEE_LPI_EVENT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_EEE_LPI_DURATION
 ***************************************************************************/
/* switch :: PAGE_24_EEE_LPI_DURATION :: PAGE_24_EEE_LPI_DURATION_COUNT [31:00] */
#define Wr_switch_PAGE_24_EEE_LPI_DURATION_PAGE_24_EEE_LPI_DURATION_COUNT(x) WriteReg(SWITCH_PAGE_24_EEE_LPI_DURATION,x)
#define Rd_switch_PAGE_24_EEE_LPI_DURATION_PAGE_24_EEE_LPI_DURATION_COUNT(x) ReadReg(SWITCH_PAGE_24_EEE_LPI_DURATION)
#define SWITCH_PAGE_24_EEE_LPI_DURATION_PAGE_24_EEE_LPI_DURATION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_EEE_LPI_DURATION_PAGE_24_EEE_LPI_DURATION_COUNT_ALIGN 0
#define SWITCH_PAGE_24_EEE_LPI_DURATION_PAGE_24_EEE_LPI_DURATION_COUNT_BITS 32
#define SWITCH_PAGE_24_EEE_LPI_DURATION_PAGE_24_EEE_LPI_DURATION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_RxDiscard
 ***************************************************************************/
/* switch :: PAGE_24_RxDiscard :: PAGE_24_RxDiscard_COUNT [31:00] */
#define Wr_switch_PAGE_24_RxDiscard_PAGE_24_RxDiscard_COUNT(x) WriteReg(SWITCH_PAGE_24_RXDISCARD,x)
#define Rd_switch_PAGE_24_RxDiscard_PAGE_24_RxDiscard_COUNT(x) ReadReg(SWITCH_PAGE_24_RXDISCARD)
#define SWITCH_PAGE_24_RXDISCARD_PAGE_24_RXDISCARD_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_24_RXDISCARD_PAGE_24_RXDISCARD_COUNT_ALIGN     0
#define SWITCH_PAGE_24_RXDISCARD_PAGE_24_RXDISCARD_COUNT_BITS      32
#define SWITCH_PAGE_24_RXDISCARD_PAGE_24_RXDISCARD_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_24_TxQPKTQ6
 ***************************************************************************/
/* switch :: PAGE_24_TxQPKTQ6 :: PAGE_24_TxQPKTQ6_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxQPKTQ6_PAGE_24_TxQPKTQ6_COUNT(x) WriteReg(SWITCH_PAGE_24_TXQPKTQ6,x)
#define Rd_switch_PAGE_24_TxQPKTQ6_PAGE_24_TxQPKTQ6_COUNT(x) ReadReg(SWITCH_PAGE_24_TXQPKTQ6)
#define SWITCH_PAGE_24_TXQPKTQ6_PAGE_24_TXQPKTQ6_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_24_TXQPKTQ6_PAGE_24_TXQPKTQ6_COUNT_ALIGN       0
#define SWITCH_PAGE_24_TXQPKTQ6_PAGE_24_TXQPKTQ6_COUNT_BITS        32
#define SWITCH_PAGE_24_TXQPKTQ6_PAGE_24_TXQPKTQ6_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_TxQPKTQ7
 ***************************************************************************/
/* switch :: PAGE_24_TxQPKTQ7 :: PAGE_24_TxQPKTQ7_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxQPKTQ7_PAGE_24_TxQPKTQ7_COUNT(x) WriteReg(SWITCH_PAGE_24_TXQPKTQ7,x)
#define Rd_switch_PAGE_24_TxQPKTQ7_PAGE_24_TxQPKTQ7_COUNT(x) ReadReg(SWITCH_PAGE_24_TXQPKTQ7)
#define SWITCH_PAGE_24_TXQPKTQ7_PAGE_24_TXQPKTQ7_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_24_TXQPKTQ7_PAGE_24_TXQPKTQ7_COUNT_ALIGN       0
#define SWITCH_PAGE_24_TXQPKTQ7_PAGE_24_TXQPKTQ7_COUNT_BITS        32
#define SWITCH_PAGE_24_TXQPKTQ7_PAGE_24_TXQPKTQ7_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_24_TxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_24_TxPkts64Octets :: PAGE_24_TxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxPkts64Octets_PAGE_24_TxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_TXPKTS64OCTETS,x)
#define Rd_switch_PAGE_24_TxPkts64Octets_PAGE_24_TxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_TXPKTS64OCTETS)
#define SWITCH_PAGE_24_TXPKTS64OCTETS_PAGE_24_TXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXPKTS64OCTETS_PAGE_24_TXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXPKTS64OCTETS_PAGE_24_TXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXPKTS64OCTETS_PAGE_24_TXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_24_TxPkts65to127Octets :: PAGE_24_TxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxPkts65to127Octets_PAGE_24_TxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_TXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_24_TxPkts65to127Octets_PAGE_24_TxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_TXPKTS65TO127OCTETS)
#define SWITCH_PAGE_24_TXPKTS65TO127OCTETS_PAGE_24_TXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXPKTS65TO127OCTETS_PAGE_24_TXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXPKTS65TO127OCTETS_PAGE_24_TXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXPKTS65TO127OCTETS_PAGE_24_TXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_24_TxPkts128to255Octets :: PAGE_24_TxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxPkts128to255Octets_PAGE_24_TxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_TXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_24_TxPkts128to255Octets_PAGE_24_TxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_TXPKTS128TO255OCTETS)
#define SWITCH_PAGE_24_TXPKTS128TO255OCTETS_PAGE_24_TXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXPKTS128TO255OCTETS_PAGE_24_TXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXPKTS128TO255OCTETS_PAGE_24_TXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXPKTS128TO255OCTETS_PAGE_24_TXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_24_TxPkts256to511Octets :: PAGE_24_TxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxPkts256to511Octets_PAGE_24_TxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_TXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_24_TxPkts256to511Octets_PAGE_24_TxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_TXPKTS256TO511OCTETS)
#define SWITCH_PAGE_24_TXPKTS256TO511OCTETS_PAGE_24_TXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXPKTS256TO511OCTETS_PAGE_24_TXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXPKTS256TO511OCTETS_PAGE_24_TXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXPKTS256TO511OCTETS_PAGE_24_TXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_24_TxPkts512to1023Octets :: PAGE_24_TxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxPkts512to1023Octets_PAGE_24_TxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_24_TXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_24_TxPkts512to1023Octets_PAGE_24_TxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_24_TXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_24_TXPKTS512TO1023OCTETS_PAGE_24_TXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXPKTS512TO1023OCTETS_PAGE_24_TXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXPKTS512TO1023OCTETS_PAGE_24_TXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXPKTS512TO1023OCTETS_PAGE_24_TXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_24_TxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_24_TxPkts1024toMaxPktOctets :: PAGE_24_TxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_24_TxPkts1024toMaxPktOctets_PAGE_24_TxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_24_TXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_24_TxPkts1024toMaxPktOctets_PAGE_24_TxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_24_TXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_24_TXPKTS1024TOMAXPKTOCTETS_PAGE_24_TXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_24_TXPKTS1024TOMAXPKTOCTETS_PAGE_24_TXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_24_TXPKTS1024TOMAXPKTOCTETS_PAGE_24_TXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_24_TXPKTS1024TOMAXPKTOCTETS_PAGE_24_TXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxOctets
 ***************************************************************************/
/* switch :: PAGE_25_TxOctets :: PAGE_25_TxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_25_TxOctets_PAGE_25_TxOctets_COUNT(x) WriteReg(SWITCH_PAGE_25_TXOCTETS,x)
#define Rd_switch_PAGE_25_TxOctets_PAGE_25_TxOctets_COUNT(x) ReadReg(SWITCH_PAGE_25_TXOCTETS)
#define SWITCH_PAGE_25_TXOCTETS_PAGE_25_TXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_25_TXOCTETS_PAGE_25_TXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_25_TXOCTETS_PAGE_25_TXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_25_TXOCTETS_PAGE_25_TXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_TxDropPkts
 ***************************************************************************/
/* switch :: PAGE_25_TxDropPkts :: PAGE_25_TxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxDropPkts_PAGE_25_TxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_25_TXDROPPKTS,x)
#define Rd_switch_PAGE_25_TxDropPkts_PAGE_25_TxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_25_TXDROPPKTS)
#define SWITCH_PAGE_25_TXDROPPKTS_PAGE_25_TXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_25_TXDROPPKTS_PAGE_25_TXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_25_TXDROPPKTS_PAGE_25_TXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_25_TXDROPPKTS_PAGE_25_TXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_25_TxQPKTQ0
 ***************************************************************************/
/* switch :: PAGE_25_TxQPKTQ0 :: PAGE_25_TxQPKTQ0_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxQPKTQ0_PAGE_25_TxQPKTQ0_COUNT(x) WriteReg(SWITCH_PAGE_25_TXQPKTQ0,x)
#define Rd_switch_PAGE_25_TxQPKTQ0_PAGE_25_TxQPKTQ0_COUNT(x) ReadReg(SWITCH_PAGE_25_TXQPKTQ0)
#define SWITCH_PAGE_25_TXQPKTQ0_PAGE_25_TXQPKTQ0_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_25_TXQPKTQ0_PAGE_25_TXQPKTQ0_COUNT_ALIGN       0
#define SWITCH_PAGE_25_TXQPKTQ0_PAGE_25_TXQPKTQ0_COUNT_BITS        32
#define SWITCH_PAGE_25_TXQPKTQ0_PAGE_25_TXQPKTQ0_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_TxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_25_TxBroadcastPkts :: PAGE_25_TxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxBroadcastPkts_PAGE_25_TxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_25_TXBROADCASTPKTS,x)
#define Rd_switch_PAGE_25_TxBroadcastPkts_PAGE_25_TxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_25_TXBROADCASTPKTS)
#define SWITCH_PAGE_25_TXBROADCASTPKTS_PAGE_25_TXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXBROADCASTPKTS_PAGE_25_TXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXBROADCASTPKTS_PAGE_25_TXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXBROADCASTPKTS_PAGE_25_TXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_25_TxMulticastPkts :: PAGE_25_TxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxMulticastPkts_PAGE_25_TxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_25_TXMULTICASTPKTS,x)
#define Rd_switch_PAGE_25_TxMulticastPkts_PAGE_25_TxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_25_TXMULTICASTPKTS)
#define SWITCH_PAGE_25_TXMULTICASTPKTS_PAGE_25_TXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXMULTICASTPKTS_PAGE_25_TXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXMULTICASTPKTS_PAGE_25_TXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXMULTICASTPKTS_PAGE_25_TXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_25_TxUnicastPkts :: PAGE_25_TxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxUnicastPkts_PAGE_25_TxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_25_TXUNICASTPKTS,x)
#define Rd_switch_PAGE_25_TxUnicastPkts_PAGE_25_TxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_25_TXUNICASTPKTS)
#define SWITCH_PAGE_25_TXUNICASTPKTS_PAGE_25_TXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXUNICASTPKTS_PAGE_25_TXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXUNICASTPKTS_PAGE_25_TXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXUNICASTPKTS_PAGE_25_TXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxCollisions
 ***************************************************************************/
/* switch :: PAGE_25_TxCollisions :: PAGE_25_TxCollisions_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxCollisions_PAGE_25_TxCollisions_COUNT(x) WriteReg(SWITCH_PAGE_25_TXCOLLISIONS,x)
#define Rd_switch_PAGE_25_TxCollisions_PAGE_25_TxCollisions_COUNT(x) ReadReg(SWITCH_PAGE_25_TXCOLLISIONS)
#define SWITCH_PAGE_25_TXCOLLISIONS_PAGE_25_TXCOLLISIONS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXCOLLISIONS_PAGE_25_TXCOLLISIONS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXCOLLISIONS_PAGE_25_TXCOLLISIONS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXCOLLISIONS_PAGE_25_TXCOLLISIONS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxSingleCollision
 ***************************************************************************/
/* switch :: PAGE_25_TxSingleCollision :: PAGE_25_TxSingleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxSingleCollision_PAGE_25_TxSingleCollision_COUNT(x) WriteReg(SWITCH_PAGE_25_TXSINGLECOLLISION,x)
#define Rd_switch_PAGE_25_TxSingleCollision_PAGE_25_TxSingleCollision_COUNT(x) ReadReg(SWITCH_PAGE_25_TXSINGLECOLLISION)
#define SWITCH_PAGE_25_TXSINGLECOLLISION_PAGE_25_TXSINGLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXSINGLECOLLISION_PAGE_25_TXSINGLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXSINGLECOLLISION_PAGE_25_TXSINGLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_25_TXSINGLECOLLISION_PAGE_25_TXSINGLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxMultipleCollision
 ***************************************************************************/
/* switch :: PAGE_25_TxMultipleCollision :: PAGE_25_TxMultipleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxMultipleCollision_PAGE_25_TxMultipleCollision_COUNT(x) WriteReg(SWITCH_PAGE_25_TXMULTIPLECOLLISION,x)
#define Rd_switch_PAGE_25_TxMultipleCollision_PAGE_25_TxMultipleCollision_COUNT(x) ReadReg(SWITCH_PAGE_25_TXMULTIPLECOLLISION)
#define SWITCH_PAGE_25_TXMULTIPLECOLLISION_PAGE_25_TXMULTIPLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXMULTIPLECOLLISION_PAGE_25_TXMULTIPLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXMULTIPLECOLLISION_PAGE_25_TXMULTIPLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_25_TXMULTIPLECOLLISION_PAGE_25_TXMULTIPLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxDeferredTransmit
 ***************************************************************************/
/* switch :: PAGE_25_TxDeferredTransmit :: PAGE_25_TxDeferredTransmit_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxDeferredTransmit_PAGE_25_TxDeferredTransmit_COUNT(x) WriteReg(SWITCH_PAGE_25_TXDEFERREDTRANSMIT,x)
#define Rd_switch_PAGE_25_TxDeferredTransmit_PAGE_25_TxDeferredTransmit_COUNT(x) ReadReg(SWITCH_PAGE_25_TXDEFERREDTRANSMIT)
#define SWITCH_PAGE_25_TXDEFERREDTRANSMIT_PAGE_25_TXDEFERREDTRANSMIT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXDEFERREDTRANSMIT_PAGE_25_TXDEFERREDTRANSMIT_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXDEFERREDTRANSMIT_PAGE_25_TXDEFERREDTRANSMIT_COUNT_BITS 32
#define SWITCH_PAGE_25_TXDEFERREDTRANSMIT_PAGE_25_TXDEFERREDTRANSMIT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxLateCollision
 ***************************************************************************/
/* switch :: PAGE_25_TxLateCollision :: PAGE_25_TxLateCollision_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxLateCollision_PAGE_25_TxLateCollision_COUNT(x) WriteReg(SWITCH_PAGE_25_TXLATECOLLISION,x)
#define Rd_switch_PAGE_25_TxLateCollision_PAGE_25_TxLateCollision_COUNT(x) ReadReg(SWITCH_PAGE_25_TXLATECOLLISION)
#define SWITCH_PAGE_25_TXLATECOLLISION_PAGE_25_TXLATECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXLATECOLLISION_PAGE_25_TXLATECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXLATECOLLISION_PAGE_25_TXLATECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_25_TXLATECOLLISION_PAGE_25_TXLATECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxExcessiveCollision
 ***************************************************************************/
/* switch :: PAGE_25_TxExcessiveCollision :: PAGE_25_TxExcessiveCollision_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxExcessiveCollision_PAGE_25_TxExcessiveCollision_COUNT(x) WriteReg(SWITCH_PAGE_25_TXEXCESSIVECOLLISION,x)
#define Rd_switch_PAGE_25_TxExcessiveCollision_PAGE_25_TxExcessiveCollision_COUNT(x) ReadReg(SWITCH_PAGE_25_TXEXCESSIVECOLLISION)
#define SWITCH_PAGE_25_TXEXCESSIVECOLLISION_PAGE_25_TXEXCESSIVECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXEXCESSIVECOLLISION_PAGE_25_TXEXCESSIVECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXEXCESSIVECOLLISION_PAGE_25_TXEXCESSIVECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_25_TXEXCESSIVECOLLISION_PAGE_25_TXEXCESSIVECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxFrameInDisc
 ***************************************************************************/
/* switch :: PAGE_25_TxFrameInDisc :: PAGE_25_TxFrameInDisc_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxFrameInDisc_PAGE_25_TxFrameInDisc_COUNT(x) WriteReg(SWITCH_PAGE_25_TXFRAMEINDISC,x)
#define Rd_switch_PAGE_25_TxFrameInDisc_PAGE_25_TxFrameInDisc_COUNT(x) ReadReg(SWITCH_PAGE_25_TXFRAMEINDISC)
#define SWITCH_PAGE_25_TXFRAMEINDISC_PAGE_25_TXFRAMEINDISC_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXFRAMEINDISC_PAGE_25_TXFRAMEINDISC_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXFRAMEINDISC_PAGE_25_TXFRAMEINDISC_COUNT_BITS 32
#define SWITCH_PAGE_25_TXFRAMEINDISC_PAGE_25_TXFRAMEINDISC_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxPausePkts
 ***************************************************************************/
/* switch :: PAGE_25_TxPausePkts :: PAGE_25_TxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxPausePkts_PAGE_25_TxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_25_TXPAUSEPKTS,x)
#define Rd_switch_PAGE_25_TxPausePkts_PAGE_25_TxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_25_TXPAUSEPKTS)
#define SWITCH_PAGE_25_TXPAUSEPKTS_PAGE_25_TXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_25_TXPAUSEPKTS_PAGE_25_TXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXPAUSEPKTS_PAGE_25_TXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_25_TXPAUSEPKTS_PAGE_25_TXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxQPKTQ1
 ***************************************************************************/
/* switch :: PAGE_25_TxQPKTQ1 :: PAGE_25_TxQPKTQ1_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxQPKTQ1_PAGE_25_TxQPKTQ1_COUNT(x) WriteReg(SWITCH_PAGE_25_TXQPKTQ1,x)
#define Rd_switch_PAGE_25_TxQPKTQ1_PAGE_25_TxQPKTQ1_COUNT(x) ReadReg(SWITCH_PAGE_25_TXQPKTQ1)
#define SWITCH_PAGE_25_TXQPKTQ1_PAGE_25_TXQPKTQ1_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_25_TXQPKTQ1_PAGE_25_TXQPKTQ1_COUNT_ALIGN       0
#define SWITCH_PAGE_25_TXQPKTQ1_PAGE_25_TXQPKTQ1_COUNT_BITS        32
#define SWITCH_PAGE_25_TXQPKTQ1_PAGE_25_TXQPKTQ1_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_TxQPKTQ2
 ***************************************************************************/
/* switch :: PAGE_25_TxQPKTQ2 :: PAGE_25_TxQPKTQ2_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxQPKTQ2_PAGE_25_TxQPKTQ2_COUNT(x) WriteReg(SWITCH_PAGE_25_TXQPKTQ2,x)
#define Rd_switch_PAGE_25_TxQPKTQ2_PAGE_25_TxQPKTQ2_COUNT(x) ReadReg(SWITCH_PAGE_25_TXQPKTQ2)
#define SWITCH_PAGE_25_TXQPKTQ2_PAGE_25_TXQPKTQ2_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_25_TXQPKTQ2_PAGE_25_TXQPKTQ2_COUNT_ALIGN       0
#define SWITCH_PAGE_25_TXQPKTQ2_PAGE_25_TXQPKTQ2_COUNT_BITS        32
#define SWITCH_PAGE_25_TXQPKTQ2_PAGE_25_TXQPKTQ2_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_TxQPKTQ3
 ***************************************************************************/
/* switch :: PAGE_25_TxQPKTQ3 :: PAGE_25_TxQPKTQ3_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxQPKTQ3_PAGE_25_TxQPKTQ3_COUNT(x) WriteReg(SWITCH_PAGE_25_TXQPKTQ3,x)
#define Rd_switch_PAGE_25_TxQPKTQ3_PAGE_25_TxQPKTQ3_COUNT(x) ReadReg(SWITCH_PAGE_25_TXQPKTQ3)
#define SWITCH_PAGE_25_TXQPKTQ3_PAGE_25_TXQPKTQ3_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_25_TXQPKTQ3_PAGE_25_TXQPKTQ3_COUNT_ALIGN       0
#define SWITCH_PAGE_25_TXQPKTQ3_PAGE_25_TXQPKTQ3_COUNT_BITS        32
#define SWITCH_PAGE_25_TXQPKTQ3_PAGE_25_TXQPKTQ3_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_TxQPKTQ4
 ***************************************************************************/
/* switch :: PAGE_25_TxQPKTQ4 :: PAGE_25_TxQPKTQ4_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxQPKTQ4_PAGE_25_TxQPKTQ4_COUNT(x) WriteReg(SWITCH_PAGE_25_TXQPKTQ4,x)
#define Rd_switch_PAGE_25_TxQPKTQ4_PAGE_25_TxQPKTQ4_COUNT(x) ReadReg(SWITCH_PAGE_25_TXQPKTQ4)
#define SWITCH_PAGE_25_TXQPKTQ4_PAGE_25_TXQPKTQ4_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_25_TXQPKTQ4_PAGE_25_TXQPKTQ4_COUNT_ALIGN       0
#define SWITCH_PAGE_25_TXQPKTQ4_PAGE_25_TXQPKTQ4_COUNT_BITS        32
#define SWITCH_PAGE_25_TXQPKTQ4_PAGE_25_TXQPKTQ4_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_TxQPKTQ5
 ***************************************************************************/
/* switch :: PAGE_25_TxQPKTQ5 :: PAGE_25_TxQPKTQ5_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxQPKTQ5_PAGE_25_TxQPKTQ5_COUNT(x) WriteReg(SWITCH_PAGE_25_TXQPKTQ5,x)
#define Rd_switch_PAGE_25_TxQPKTQ5_PAGE_25_TxQPKTQ5_COUNT(x) ReadReg(SWITCH_PAGE_25_TXQPKTQ5)
#define SWITCH_PAGE_25_TXQPKTQ5_PAGE_25_TXQPKTQ5_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_25_TXQPKTQ5_PAGE_25_TXQPKTQ5_COUNT_ALIGN       0
#define SWITCH_PAGE_25_TXQPKTQ5_PAGE_25_TXQPKTQ5_COUNT_BITS        32
#define SWITCH_PAGE_25_TXQPKTQ5_PAGE_25_TXQPKTQ5_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_RxOctets
 ***************************************************************************/
/* switch :: PAGE_25_RxOctets :: PAGE_25_RxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_25_RxOctets_PAGE_25_RxOctets_COUNT(x) WriteReg(SWITCH_PAGE_25_RXOCTETS,x)
#define Rd_switch_PAGE_25_RxOctets_PAGE_25_RxOctets_COUNT(x) ReadReg(SWITCH_PAGE_25_RXOCTETS)
#define SWITCH_PAGE_25_RXOCTETS_PAGE_25_RXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_25_RXOCTETS_PAGE_25_RXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_25_RXOCTETS_PAGE_25_RXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_25_RXOCTETS_PAGE_25_RXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_RxUndersizePkts
 ***************************************************************************/
/* switch :: PAGE_25_RxUndersizePkts :: PAGE_25_RxUndersizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxUndersizePkts_PAGE_25_RxUndersizePkts_COUNT(x) WriteReg(SWITCH_PAGE_25_RXUNDERSIZEPKTS,x)
#define Rd_switch_PAGE_25_RxUndersizePkts_PAGE_25_RxUndersizePkts_COUNT(x) ReadReg(SWITCH_PAGE_25_RXUNDERSIZEPKTS)
#define SWITCH_PAGE_25_RXUNDERSIZEPKTS_PAGE_25_RXUNDERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXUNDERSIZEPKTS_PAGE_25_RXUNDERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXUNDERSIZEPKTS_PAGE_25_RXUNDERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXUNDERSIZEPKTS_PAGE_25_RXUNDERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxPausePkts
 ***************************************************************************/
/* switch :: PAGE_25_RxPausePkts :: PAGE_25_RxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxPausePkts_PAGE_25_RxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_25_RXPAUSEPKTS,x)
#define Rd_switch_PAGE_25_RxPausePkts_PAGE_25_RxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_25_RXPAUSEPKTS)
#define SWITCH_PAGE_25_RXPAUSEPKTS_PAGE_25_RXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_25_RXPAUSEPKTS_PAGE_25_RXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXPAUSEPKTS_PAGE_25_RXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_25_RXPAUSEPKTS_PAGE_25_RXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_25_RxPkts64Octets :: PAGE_25_RxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxPkts64Octets_PAGE_25_RxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_RXPKTS64OCTETS,x)
#define Rd_switch_PAGE_25_RxPkts64Octets_PAGE_25_RxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_RXPKTS64OCTETS)
#define SWITCH_PAGE_25_RXPKTS64OCTETS_PAGE_25_RXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXPKTS64OCTETS_PAGE_25_RXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXPKTS64OCTETS_PAGE_25_RXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXPKTS64OCTETS_PAGE_25_RXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_25_RxPkts65to127Octets :: PAGE_25_RxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxPkts65to127Octets_PAGE_25_RxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_RXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_25_RxPkts65to127Octets_PAGE_25_RxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_RXPKTS65TO127OCTETS)
#define SWITCH_PAGE_25_RXPKTS65TO127OCTETS_PAGE_25_RXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXPKTS65TO127OCTETS_PAGE_25_RXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXPKTS65TO127OCTETS_PAGE_25_RXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXPKTS65TO127OCTETS_PAGE_25_RXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_25_RxPkts128to255Octets :: PAGE_25_RxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxPkts128to255Octets_PAGE_25_RxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_RXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_25_RxPkts128to255Octets_PAGE_25_RxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_RXPKTS128TO255OCTETS)
#define SWITCH_PAGE_25_RXPKTS128TO255OCTETS_PAGE_25_RXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXPKTS128TO255OCTETS_PAGE_25_RXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXPKTS128TO255OCTETS_PAGE_25_RXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXPKTS128TO255OCTETS_PAGE_25_RXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_25_RxPkts256to511Octets :: PAGE_25_RxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxPkts256to511Octets_PAGE_25_RxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_RXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_25_RxPkts256to511Octets_PAGE_25_RxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_RXPKTS256TO511OCTETS)
#define SWITCH_PAGE_25_RXPKTS256TO511OCTETS_PAGE_25_RXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXPKTS256TO511OCTETS_PAGE_25_RXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXPKTS256TO511OCTETS_PAGE_25_RXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXPKTS256TO511OCTETS_PAGE_25_RXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_25_RxPkts512to1023Octets :: PAGE_25_RxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxPkts512to1023Octets_PAGE_25_RxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_RXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_25_RxPkts512to1023Octets_PAGE_25_RxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_RXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_25_RXPKTS512TO1023OCTETS_PAGE_25_RXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXPKTS512TO1023OCTETS_PAGE_25_RXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXPKTS512TO1023OCTETS_PAGE_25_RXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXPKTS512TO1023OCTETS_PAGE_25_RXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_25_RxPkts1024toMaxPktOctets :: PAGE_25_RxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxPkts1024toMaxPktOctets_PAGE_25_RxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_25_RXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_25_RxPkts1024toMaxPktOctets_PAGE_25_RxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_25_RXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_25_RXPKTS1024TOMAXPKTOCTETS_PAGE_25_RXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXPKTS1024TOMAXPKTOCTETS_PAGE_25_RXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXPKTS1024TOMAXPKTOCTETS_PAGE_25_RXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXPKTS1024TOMAXPKTOCTETS_PAGE_25_RXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxOversizePkts
 ***************************************************************************/
/* switch :: PAGE_25_RxOversizePkts :: PAGE_25_RxOversizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxOversizePkts_PAGE_25_RxOversizePkts_COUNT(x) WriteReg(SWITCH_PAGE_25_RXOVERSIZEPKTS,x)
#define Rd_switch_PAGE_25_RxOversizePkts_PAGE_25_RxOversizePkts_COUNT(x) ReadReg(SWITCH_PAGE_25_RXOVERSIZEPKTS)
#define SWITCH_PAGE_25_RXOVERSIZEPKTS_PAGE_25_RXOVERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXOVERSIZEPKTS_PAGE_25_RXOVERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXOVERSIZEPKTS_PAGE_25_RXOVERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXOVERSIZEPKTS_PAGE_25_RXOVERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxJabbers
 ***************************************************************************/
/* switch :: PAGE_25_RxJabbers :: PAGE_25_RxJabbers_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxJabbers_PAGE_25_RxJabbers_COUNT(x) WriteReg(SWITCH_PAGE_25_RXJABBERS,x)
#define Rd_switch_PAGE_25_RxJabbers_PAGE_25_RxJabbers_COUNT(x) ReadReg(SWITCH_PAGE_25_RXJABBERS)
#define SWITCH_PAGE_25_RXJABBERS_PAGE_25_RXJABBERS_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_25_RXJABBERS_PAGE_25_RXJABBERS_COUNT_ALIGN     0
#define SWITCH_PAGE_25_RXJABBERS_PAGE_25_RXJABBERS_COUNT_BITS      32
#define SWITCH_PAGE_25_RXJABBERS_PAGE_25_RXJABBERS_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_25_RxAlignmentErrors
 ***************************************************************************/
/* switch :: PAGE_25_RxAlignmentErrors :: PAGE_25_RxAlignmentErrors_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxAlignmentErrors_PAGE_25_RxAlignmentErrors_COUNT(x) WriteReg(SWITCH_PAGE_25_RXALIGNMENTERRORS,x)
#define Rd_switch_PAGE_25_RxAlignmentErrors_PAGE_25_RxAlignmentErrors_COUNT(x) ReadReg(SWITCH_PAGE_25_RXALIGNMENTERRORS)
#define SWITCH_PAGE_25_RXALIGNMENTERRORS_PAGE_25_RXALIGNMENTERRORS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXALIGNMENTERRORS_PAGE_25_RXALIGNMENTERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXALIGNMENTERRORS_PAGE_25_RXALIGNMENTERRORS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXALIGNMENTERRORS_PAGE_25_RXALIGNMENTERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxFCSErrors
 ***************************************************************************/
/* switch :: PAGE_25_RxFCSErrors :: PAGE_25_RxFCSErrors_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxFCSErrors_PAGE_25_RxFCSErrors_COUNT(x) WriteReg(SWITCH_PAGE_25_RXFCSERRORS,x)
#define Rd_switch_PAGE_25_RxFCSErrors_PAGE_25_RxFCSErrors_COUNT(x) ReadReg(SWITCH_PAGE_25_RXFCSERRORS)
#define SWITCH_PAGE_25_RXFCSERRORS_PAGE_25_RXFCSERRORS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_25_RXFCSERRORS_PAGE_25_RXFCSERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXFCSERRORS_PAGE_25_RXFCSERRORS_COUNT_BITS  32
#define SWITCH_PAGE_25_RXFCSERRORS_PAGE_25_RXFCSERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxGoodOctets
 ***************************************************************************/
/* switch :: PAGE_25_RxGoodOctets :: PAGE_25_RxGoodOctets_COUNT [63:00] */
#define Wr_switch_PAGE_25_RxGoodOctets_PAGE_25_RxGoodOctets_COUNT(x) WriteReg(SWITCH_PAGE_25_RXGOODOCTETS,x)
#define Rd_switch_PAGE_25_RxGoodOctets_PAGE_25_RxGoodOctets_COUNT(x) ReadReg(SWITCH_PAGE_25_RXGOODOCTETS)
#define SWITCH_PAGE_25_RXGOODOCTETS_PAGE_25_RXGOODOCTETS_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_25_RXGOODOCTETS_PAGE_25_RXGOODOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXGOODOCTETS_PAGE_25_RXGOODOCTETS_COUNT_BITS 64
#define SWITCH_PAGE_25_RXGOODOCTETS_PAGE_25_RXGOODOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxDropPkts
 ***************************************************************************/
/* switch :: PAGE_25_RxDropPkts :: PAGE_25_RxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxDropPkts_PAGE_25_RxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_25_RXDROPPKTS,x)
#define Rd_switch_PAGE_25_RxDropPkts_PAGE_25_RxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_25_RXDROPPKTS)
#define SWITCH_PAGE_25_RXDROPPKTS_PAGE_25_RXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_25_RXDROPPKTS_PAGE_25_RXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_25_RXDROPPKTS_PAGE_25_RXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_25_RXDROPPKTS_PAGE_25_RXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_25_RxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_25_RxUnicastPkts :: PAGE_25_RxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxUnicastPkts_PAGE_25_RxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_25_RXUNICASTPKTS,x)
#define Rd_switch_PAGE_25_RxUnicastPkts_PAGE_25_RxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_25_RXUNICASTPKTS)
#define SWITCH_PAGE_25_RXUNICASTPKTS_PAGE_25_RXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXUNICASTPKTS_PAGE_25_RXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXUNICASTPKTS_PAGE_25_RXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXUNICASTPKTS_PAGE_25_RXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_25_RxMulticastPkts :: PAGE_25_RxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxMulticastPkts_PAGE_25_RxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_25_RXMULTICASTPKTS,x)
#define Rd_switch_PAGE_25_RxMulticastPkts_PAGE_25_RxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_25_RXMULTICASTPKTS)
#define SWITCH_PAGE_25_RXMULTICASTPKTS_PAGE_25_RXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXMULTICASTPKTS_PAGE_25_RXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXMULTICASTPKTS_PAGE_25_RXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXMULTICASTPKTS_PAGE_25_RXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_25_RxBroadcastPkts :: PAGE_25_RxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxBroadcastPkts_PAGE_25_RxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_25_RXBROADCASTPKTS,x)
#define Rd_switch_PAGE_25_RxBroadcastPkts_PAGE_25_RxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_25_RXBROADCASTPKTS)
#define SWITCH_PAGE_25_RXBROADCASTPKTS_PAGE_25_RXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_RXBROADCASTPKTS_PAGE_25_RXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXBROADCASTPKTS_PAGE_25_RXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_25_RXBROADCASTPKTS_PAGE_25_RXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxSAChanges
 ***************************************************************************/
/* switch :: PAGE_25_RxSAChanges :: PAGE_25_RxSAChanges_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxSAChanges_PAGE_25_RxSAChanges_COUNT(x) WriteReg(SWITCH_PAGE_25_RXSACHANGES,x)
#define Rd_switch_PAGE_25_RxSAChanges_PAGE_25_RxSAChanges_COUNT(x) ReadReg(SWITCH_PAGE_25_RXSACHANGES)
#define SWITCH_PAGE_25_RXSACHANGES_PAGE_25_RXSACHANGES_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_25_RXSACHANGES_PAGE_25_RXSACHANGES_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXSACHANGES_PAGE_25_RXSACHANGES_COUNT_BITS  32
#define SWITCH_PAGE_25_RXSACHANGES_PAGE_25_RXSACHANGES_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxFragments
 ***************************************************************************/
/* switch :: PAGE_25_RxFragments :: PAGE_25_RxFragments_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxFragments_PAGE_25_RxFragments_COUNT(x) WriteReg(SWITCH_PAGE_25_RXFRAGMENTS,x)
#define Rd_switch_PAGE_25_RxFragments_PAGE_25_RxFragments_COUNT(x) ReadReg(SWITCH_PAGE_25_RXFRAGMENTS)
#define SWITCH_PAGE_25_RXFRAGMENTS_PAGE_25_RXFRAGMENTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_25_RXFRAGMENTS_PAGE_25_RXFRAGMENTS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_RXFRAGMENTS_PAGE_25_RXFRAGMENTS_COUNT_BITS  32
#define SWITCH_PAGE_25_RXFRAGMENTS_PAGE_25_RXFRAGMENTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxJumboPkt
 ***************************************************************************/
/* switch :: PAGE_25_RxJumboPkt :: PAGE_25_RxJumboPkt_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxJumboPkt_PAGE_25_RxJumboPkt_COUNT(x) WriteReg(SWITCH_PAGE_25_RXJUMBOPKT,x)
#define Rd_switch_PAGE_25_RxJumboPkt_PAGE_25_RxJumboPkt_COUNT(x) ReadReg(SWITCH_PAGE_25_RXJUMBOPKT)
#define SWITCH_PAGE_25_RXJUMBOPKT_PAGE_25_RXJUMBOPKT_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_25_RXJUMBOPKT_PAGE_25_RXJUMBOPKT_COUNT_ALIGN   0
#define SWITCH_PAGE_25_RXJUMBOPKT_PAGE_25_RXJUMBOPKT_COUNT_BITS    32
#define SWITCH_PAGE_25_RXJUMBOPKT_PAGE_25_RXJUMBOPKT_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_25_RxSymblErr
 ***************************************************************************/
/* switch :: PAGE_25_RxSymblErr :: PAGE_25_RxSymblErr_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxSymblErr_PAGE_25_RxSymblErr_COUNT(x) WriteReg(SWITCH_PAGE_25_RXSYMBLERR,x)
#define Rd_switch_PAGE_25_RxSymblErr_PAGE_25_RxSymblErr_COUNT(x) ReadReg(SWITCH_PAGE_25_RXSYMBLERR)
#define SWITCH_PAGE_25_RXSYMBLERR_PAGE_25_RXSYMBLERR_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_25_RXSYMBLERR_PAGE_25_RXSYMBLERR_COUNT_ALIGN   0
#define SWITCH_PAGE_25_RXSYMBLERR_PAGE_25_RXSYMBLERR_COUNT_BITS    32
#define SWITCH_PAGE_25_RXSYMBLERR_PAGE_25_RXSYMBLERR_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_25_InRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_25_InRangeErrCount :: PAGE_25_InRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_25_InRangeErrCount_PAGE_25_InRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_25_INRANGEERRCOUNT,x)
#define Rd_switch_PAGE_25_InRangeErrCount_PAGE_25_InRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_25_INRANGEERRCOUNT)
#define SWITCH_PAGE_25_INRANGEERRCOUNT_PAGE_25_INRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_INRANGEERRCOUNT_PAGE_25_INRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_25_INRANGEERRCOUNT_PAGE_25_INRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_25_INRANGEERRCOUNT_PAGE_25_INRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_OutRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_25_OutRangeErrCount :: PAGE_25_OutRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_25_OutRangeErrCount_PAGE_25_OutRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_25_OUTRANGEERRCOUNT,x)
#define Rd_switch_PAGE_25_OutRangeErrCount_PAGE_25_OutRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_25_OUTRANGEERRCOUNT)
#define SWITCH_PAGE_25_OUTRANGEERRCOUNT_PAGE_25_OUTRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_OUTRANGEERRCOUNT_PAGE_25_OUTRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_25_OUTRANGEERRCOUNT_PAGE_25_OUTRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_25_OUTRANGEERRCOUNT_PAGE_25_OUTRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_EEE_LPI_EVENT
 ***************************************************************************/
/* switch :: PAGE_25_EEE_LPI_EVENT :: PAGE_25_EEE_LPI_EVENT_COUNT [31:00] */
#define Wr_switch_PAGE_25_EEE_LPI_EVENT_PAGE_25_EEE_LPI_EVENT_COUNT(x) WriteReg(SWITCH_PAGE_25_EEE_LPI_EVENT,x)
#define Rd_switch_PAGE_25_EEE_LPI_EVENT_PAGE_25_EEE_LPI_EVENT_COUNT(x) ReadReg(SWITCH_PAGE_25_EEE_LPI_EVENT)
#define SWITCH_PAGE_25_EEE_LPI_EVENT_PAGE_25_EEE_LPI_EVENT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_EEE_LPI_EVENT_PAGE_25_EEE_LPI_EVENT_COUNT_ALIGN 0
#define SWITCH_PAGE_25_EEE_LPI_EVENT_PAGE_25_EEE_LPI_EVENT_COUNT_BITS 32
#define SWITCH_PAGE_25_EEE_LPI_EVENT_PAGE_25_EEE_LPI_EVENT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_EEE_LPI_DURATION
 ***************************************************************************/
/* switch :: PAGE_25_EEE_LPI_DURATION :: PAGE_25_EEE_LPI_DURATION_COUNT [31:00] */
#define Wr_switch_PAGE_25_EEE_LPI_DURATION_PAGE_25_EEE_LPI_DURATION_COUNT(x) WriteReg(SWITCH_PAGE_25_EEE_LPI_DURATION,x)
#define Rd_switch_PAGE_25_EEE_LPI_DURATION_PAGE_25_EEE_LPI_DURATION_COUNT(x) ReadReg(SWITCH_PAGE_25_EEE_LPI_DURATION)
#define SWITCH_PAGE_25_EEE_LPI_DURATION_PAGE_25_EEE_LPI_DURATION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_EEE_LPI_DURATION_PAGE_25_EEE_LPI_DURATION_COUNT_ALIGN 0
#define SWITCH_PAGE_25_EEE_LPI_DURATION_PAGE_25_EEE_LPI_DURATION_COUNT_BITS 32
#define SWITCH_PAGE_25_EEE_LPI_DURATION_PAGE_25_EEE_LPI_DURATION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_RxDiscard
 ***************************************************************************/
/* switch :: PAGE_25_RxDiscard :: PAGE_25_RxDiscard_COUNT [31:00] */
#define Wr_switch_PAGE_25_RxDiscard_PAGE_25_RxDiscard_COUNT(x) WriteReg(SWITCH_PAGE_25_RXDISCARD,x)
#define Rd_switch_PAGE_25_RxDiscard_PAGE_25_RxDiscard_COUNT(x) ReadReg(SWITCH_PAGE_25_RXDISCARD)
#define SWITCH_PAGE_25_RXDISCARD_PAGE_25_RXDISCARD_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_25_RXDISCARD_PAGE_25_RXDISCARD_COUNT_ALIGN     0
#define SWITCH_PAGE_25_RXDISCARD_PAGE_25_RXDISCARD_COUNT_BITS      32
#define SWITCH_PAGE_25_RXDISCARD_PAGE_25_RXDISCARD_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_25_TxQPKTQ6
 ***************************************************************************/
/* switch :: PAGE_25_TxQPKTQ6 :: PAGE_25_TxQPKTQ6_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxQPKTQ6_PAGE_25_TxQPKTQ6_COUNT(x) WriteReg(SWITCH_PAGE_25_TXQPKTQ6,x)
#define Rd_switch_PAGE_25_TxQPKTQ6_PAGE_25_TxQPKTQ6_COUNT(x) ReadReg(SWITCH_PAGE_25_TXQPKTQ6)
#define SWITCH_PAGE_25_TXQPKTQ6_PAGE_25_TXQPKTQ6_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_25_TXQPKTQ6_PAGE_25_TXQPKTQ6_COUNT_ALIGN       0
#define SWITCH_PAGE_25_TXQPKTQ6_PAGE_25_TXQPKTQ6_COUNT_BITS        32
#define SWITCH_PAGE_25_TXQPKTQ6_PAGE_25_TXQPKTQ6_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_TxQPKTQ7
 ***************************************************************************/
/* switch :: PAGE_25_TxQPKTQ7 :: PAGE_25_TxQPKTQ7_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxQPKTQ7_PAGE_25_TxQPKTQ7_COUNT(x) WriteReg(SWITCH_PAGE_25_TXQPKTQ7,x)
#define Rd_switch_PAGE_25_TxQPKTQ7_PAGE_25_TxQPKTQ7_COUNT(x) ReadReg(SWITCH_PAGE_25_TXQPKTQ7)
#define SWITCH_PAGE_25_TXQPKTQ7_PAGE_25_TXQPKTQ7_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_25_TXQPKTQ7_PAGE_25_TXQPKTQ7_COUNT_ALIGN       0
#define SWITCH_PAGE_25_TXQPKTQ7_PAGE_25_TXQPKTQ7_COUNT_BITS        32
#define SWITCH_PAGE_25_TXQPKTQ7_PAGE_25_TXQPKTQ7_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_25_TxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_25_TxPkts64Octets :: PAGE_25_TxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxPkts64Octets_PAGE_25_TxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_TXPKTS64OCTETS,x)
#define Rd_switch_PAGE_25_TxPkts64Octets_PAGE_25_TxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_TXPKTS64OCTETS)
#define SWITCH_PAGE_25_TXPKTS64OCTETS_PAGE_25_TXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXPKTS64OCTETS_PAGE_25_TXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXPKTS64OCTETS_PAGE_25_TXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXPKTS64OCTETS_PAGE_25_TXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_25_TxPkts65to127Octets :: PAGE_25_TxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxPkts65to127Octets_PAGE_25_TxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_TXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_25_TxPkts65to127Octets_PAGE_25_TxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_TXPKTS65TO127OCTETS)
#define SWITCH_PAGE_25_TXPKTS65TO127OCTETS_PAGE_25_TXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXPKTS65TO127OCTETS_PAGE_25_TXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXPKTS65TO127OCTETS_PAGE_25_TXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXPKTS65TO127OCTETS_PAGE_25_TXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_25_TxPkts128to255Octets :: PAGE_25_TxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxPkts128to255Octets_PAGE_25_TxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_TXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_25_TxPkts128to255Octets_PAGE_25_TxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_TXPKTS128TO255OCTETS)
#define SWITCH_PAGE_25_TXPKTS128TO255OCTETS_PAGE_25_TXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXPKTS128TO255OCTETS_PAGE_25_TXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXPKTS128TO255OCTETS_PAGE_25_TXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXPKTS128TO255OCTETS_PAGE_25_TXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_25_TxPkts256to511Octets :: PAGE_25_TxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxPkts256to511Octets_PAGE_25_TxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_TXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_25_TxPkts256to511Octets_PAGE_25_TxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_TXPKTS256TO511OCTETS)
#define SWITCH_PAGE_25_TXPKTS256TO511OCTETS_PAGE_25_TXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXPKTS256TO511OCTETS_PAGE_25_TXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXPKTS256TO511OCTETS_PAGE_25_TXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXPKTS256TO511OCTETS_PAGE_25_TXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_25_TxPkts512to1023Octets :: PAGE_25_TxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxPkts512to1023Octets_PAGE_25_TxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_25_TXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_25_TxPkts512to1023Octets_PAGE_25_TxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_25_TXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_25_TXPKTS512TO1023OCTETS_PAGE_25_TXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXPKTS512TO1023OCTETS_PAGE_25_TXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXPKTS512TO1023OCTETS_PAGE_25_TXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXPKTS512TO1023OCTETS_PAGE_25_TXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_25_TxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_25_TxPkts1024toMaxPktOctets :: PAGE_25_TxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_25_TxPkts1024toMaxPktOctets_PAGE_25_TxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_25_TXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_25_TxPkts1024toMaxPktOctets_PAGE_25_TxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_25_TXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_25_TXPKTS1024TOMAXPKTOCTETS_PAGE_25_TXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_25_TXPKTS1024TOMAXPKTOCTETS_PAGE_25_TXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_25_TXPKTS1024TOMAXPKTOCTETS_PAGE_25_TXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_25_TXPKTS1024TOMAXPKTOCTETS_PAGE_25_TXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxOctets
 ***************************************************************************/
/* switch :: PAGE_26_TxOctets :: PAGE_26_TxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_26_TxOctets_PAGE_26_TxOctets_COUNT(x) WriteReg(SWITCH_PAGE_26_TXOCTETS,x)
#define Rd_switch_PAGE_26_TxOctets_PAGE_26_TxOctets_COUNT(x) ReadReg(SWITCH_PAGE_26_TXOCTETS)
#define SWITCH_PAGE_26_TXOCTETS_PAGE_26_TXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_26_TXOCTETS_PAGE_26_TXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_26_TXOCTETS_PAGE_26_TXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_26_TXOCTETS_PAGE_26_TXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_TxDropPkts
 ***************************************************************************/
/* switch :: PAGE_26_TxDropPkts :: PAGE_26_TxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxDropPkts_PAGE_26_TxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_26_TXDROPPKTS,x)
#define Rd_switch_PAGE_26_TxDropPkts_PAGE_26_TxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_26_TXDROPPKTS)
#define SWITCH_PAGE_26_TXDROPPKTS_PAGE_26_TXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_26_TXDROPPKTS_PAGE_26_TXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_26_TXDROPPKTS_PAGE_26_TXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_26_TXDROPPKTS_PAGE_26_TXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_26_TxQPKTQ0
 ***************************************************************************/
/* switch :: PAGE_26_TxQPKTQ0 :: PAGE_26_TxQPKTQ0_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxQPKTQ0_PAGE_26_TxQPKTQ0_COUNT(x) WriteReg(SWITCH_PAGE_26_TXQPKTQ0,x)
#define Rd_switch_PAGE_26_TxQPKTQ0_PAGE_26_TxQPKTQ0_COUNT(x) ReadReg(SWITCH_PAGE_26_TXQPKTQ0)
#define SWITCH_PAGE_26_TXQPKTQ0_PAGE_26_TXQPKTQ0_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_26_TXQPKTQ0_PAGE_26_TXQPKTQ0_COUNT_ALIGN       0
#define SWITCH_PAGE_26_TXQPKTQ0_PAGE_26_TXQPKTQ0_COUNT_BITS        32
#define SWITCH_PAGE_26_TXQPKTQ0_PAGE_26_TXQPKTQ0_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_TxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_26_TxBroadcastPkts :: PAGE_26_TxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxBroadcastPkts_PAGE_26_TxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_26_TXBROADCASTPKTS,x)
#define Rd_switch_PAGE_26_TxBroadcastPkts_PAGE_26_TxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_26_TXBROADCASTPKTS)
#define SWITCH_PAGE_26_TXBROADCASTPKTS_PAGE_26_TXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXBROADCASTPKTS_PAGE_26_TXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXBROADCASTPKTS_PAGE_26_TXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXBROADCASTPKTS_PAGE_26_TXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_26_TxMulticastPkts :: PAGE_26_TxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxMulticastPkts_PAGE_26_TxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_26_TXMULTICASTPKTS,x)
#define Rd_switch_PAGE_26_TxMulticastPkts_PAGE_26_TxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_26_TXMULTICASTPKTS)
#define SWITCH_PAGE_26_TXMULTICASTPKTS_PAGE_26_TXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXMULTICASTPKTS_PAGE_26_TXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXMULTICASTPKTS_PAGE_26_TXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXMULTICASTPKTS_PAGE_26_TXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_26_TxUnicastPkts :: PAGE_26_TxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxUnicastPkts_PAGE_26_TxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_26_TXUNICASTPKTS,x)
#define Rd_switch_PAGE_26_TxUnicastPkts_PAGE_26_TxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_26_TXUNICASTPKTS)
#define SWITCH_PAGE_26_TXUNICASTPKTS_PAGE_26_TXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXUNICASTPKTS_PAGE_26_TXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXUNICASTPKTS_PAGE_26_TXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXUNICASTPKTS_PAGE_26_TXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxCollisions
 ***************************************************************************/
/* switch :: PAGE_26_TxCollisions :: PAGE_26_TxCollisions_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxCollisions_PAGE_26_TxCollisions_COUNT(x) WriteReg(SWITCH_PAGE_26_TXCOLLISIONS,x)
#define Rd_switch_PAGE_26_TxCollisions_PAGE_26_TxCollisions_COUNT(x) ReadReg(SWITCH_PAGE_26_TXCOLLISIONS)
#define SWITCH_PAGE_26_TXCOLLISIONS_PAGE_26_TXCOLLISIONS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXCOLLISIONS_PAGE_26_TXCOLLISIONS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXCOLLISIONS_PAGE_26_TXCOLLISIONS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXCOLLISIONS_PAGE_26_TXCOLLISIONS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxSingleCollision
 ***************************************************************************/
/* switch :: PAGE_26_TxSingleCollision :: PAGE_26_TxSingleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxSingleCollision_PAGE_26_TxSingleCollision_COUNT(x) WriteReg(SWITCH_PAGE_26_TXSINGLECOLLISION,x)
#define Rd_switch_PAGE_26_TxSingleCollision_PAGE_26_TxSingleCollision_COUNT(x) ReadReg(SWITCH_PAGE_26_TXSINGLECOLLISION)
#define SWITCH_PAGE_26_TXSINGLECOLLISION_PAGE_26_TXSINGLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXSINGLECOLLISION_PAGE_26_TXSINGLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXSINGLECOLLISION_PAGE_26_TXSINGLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_26_TXSINGLECOLLISION_PAGE_26_TXSINGLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxMultipleCollision
 ***************************************************************************/
/* switch :: PAGE_26_TxMultipleCollision :: PAGE_26_TxMultipleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxMultipleCollision_PAGE_26_TxMultipleCollision_COUNT(x) WriteReg(SWITCH_PAGE_26_TXMULTIPLECOLLISION,x)
#define Rd_switch_PAGE_26_TxMultipleCollision_PAGE_26_TxMultipleCollision_COUNT(x) ReadReg(SWITCH_PAGE_26_TXMULTIPLECOLLISION)
#define SWITCH_PAGE_26_TXMULTIPLECOLLISION_PAGE_26_TXMULTIPLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXMULTIPLECOLLISION_PAGE_26_TXMULTIPLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXMULTIPLECOLLISION_PAGE_26_TXMULTIPLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_26_TXMULTIPLECOLLISION_PAGE_26_TXMULTIPLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxDeferredTransmit
 ***************************************************************************/
/* switch :: PAGE_26_TxDeferredTransmit :: PAGE_26_TxDeferredTransmit_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxDeferredTransmit_PAGE_26_TxDeferredTransmit_COUNT(x) WriteReg(SWITCH_PAGE_26_TXDEFERREDTRANSMIT,x)
#define Rd_switch_PAGE_26_TxDeferredTransmit_PAGE_26_TxDeferredTransmit_COUNT(x) ReadReg(SWITCH_PAGE_26_TXDEFERREDTRANSMIT)
#define SWITCH_PAGE_26_TXDEFERREDTRANSMIT_PAGE_26_TXDEFERREDTRANSMIT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXDEFERREDTRANSMIT_PAGE_26_TXDEFERREDTRANSMIT_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXDEFERREDTRANSMIT_PAGE_26_TXDEFERREDTRANSMIT_COUNT_BITS 32
#define SWITCH_PAGE_26_TXDEFERREDTRANSMIT_PAGE_26_TXDEFERREDTRANSMIT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxLateCollision
 ***************************************************************************/
/* switch :: PAGE_26_TxLateCollision :: PAGE_26_TxLateCollision_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxLateCollision_PAGE_26_TxLateCollision_COUNT(x) WriteReg(SWITCH_PAGE_26_TXLATECOLLISION,x)
#define Rd_switch_PAGE_26_TxLateCollision_PAGE_26_TxLateCollision_COUNT(x) ReadReg(SWITCH_PAGE_26_TXLATECOLLISION)
#define SWITCH_PAGE_26_TXLATECOLLISION_PAGE_26_TXLATECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXLATECOLLISION_PAGE_26_TXLATECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXLATECOLLISION_PAGE_26_TXLATECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_26_TXLATECOLLISION_PAGE_26_TXLATECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxExcessiveCollision
 ***************************************************************************/
/* switch :: PAGE_26_TxExcessiveCollision :: PAGE_26_TxExcessiveCollision_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxExcessiveCollision_PAGE_26_TxExcessiveCollision_COUNT(x) WriteReg(SWITCH_PAGE_26_TXEXCESSIVECOLLISION,x)
#define Rd_switch_PAGE_26_TxExcessiveCollision_PAGE_26_TxExcessiveCollision_COUNT(x) ReadReg(SWITCH_PAGE_26_TXEXCESSIVECOLLISION)
#define SWITCH_PAGE_26_TXEXCESSIVECOLLISION_PAGE_26_TXEXCESSIVECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXEXCESSIVECOLLISION_PAGE_26_TXEXCESSIVECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXEXCESSIVECOLLISION_PAGE_26_TXEXCESSIVECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_26_TXEXCESSIVECOLLISION_PAGE_26_TXEXCESSIVECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxFrameInDisc
 ***************************************************************************/
/* switch :: PAGE_26_TxFrameInDisc :: PAGE_26_TxFrameInDisc_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxFrameInDisc_PAGE_26_TxFrameInDisc_COUNT(x) WriteReg(SWITCH_PAGE_26_TXFRAMEINDISC,x)
#define Rd_switch_PAGE_26_TxFrameInDisc_PAGE_26_TxFrameInDisc_COUNT(x) ReadReg(SWITCH_PAGE_26_TXFRAMEINDISC)
#define SWITCH_PAGE_26_TXFRAMEINDISC_PAGE_26_TXFRAMEINDISC_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXFRAMEINDISC_PAGE_26_TXFRAMEINDISC_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXFRAMEINDISC_PAGE_26_TXFRAMEINDISC_COUNT_BITS 32
#define SWITCH_PAGE_26_TXFRAMEINDISC_PAGE_26_TXFRAMEINDISC_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxPausePkts
 ***************************************************************************/
/* switch :: PAGE_26_TxPausePkts :: PAGE_26_TxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxPausePkts_PAGE_26_TxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_26_TXPAUSEPKTS,x)
#define Rd_switch_PAGE_26_TxPausePkts_PAGE_26_TxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_26_TXPAUSEPKTS)
#define SWITCH_PAGE_26_TXPAUSEPKTS_PAGE_26_TXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_26_TXPAUSEPKTS_PAGE_26_TXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXPAUSEPKTS_PAGE_26_TXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_26_TXPAUSEPKTS_PAGE_26_TXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxQPKTQ1
 ***************************************************************************/
/* switch :: PAGE_26_TxQPKTQ1 :: PAGE_26_TxQPKTQ1_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxQPKTQ1_PAGE_26_TxQPKTQ1_COUNT(x) WriteReg(SWITCH_PAGE_26_TXQPKTQ1,x)
#define Rd_switch_PAGE_26_TxQPKTQ1_PAGE_26_TxQPKTQ1_COUNT(x) ReadReg(SWITCH_PAGE_26_TXQPKTQ1)
#define SWITCH_PAGE_26_TXQPKTQ1_PAGE_26_TXQPKTQ1_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_26_TXQPKTQ1_PAGE_26_TXQPKTQ1_COUNT_ALIGN       0
#define SWITCH_PAGE_26_TXQPKTQ1_PAGE_26_TXQPKTQ1_COUNT_BITS        32
#define SWITCH_PAGE_26_TXQPKTQ1_PAGE_26_TXQPKTQ1_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_TxQPKTQ2
 ***************************************************************************/
/* switch :: PAGE_26_TxQPKTQ2 :: PAGE_26_TxQPKTQ2_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxQPKTQ2_PAGE_26_TxQPKTQ2_COUNT(x) WriteReg(SWITCH_PAGE_26_TXQPKTQ2,x)
#define Rd_switch_PAGE_26_TxQPKTQ2_PAGE_26_TxQPKTQ2_COUNT(x) ReadReg(SWITCH_PAGE_26_TXQPKTQ2)
#define SWITCH_PAGE_26_TXQPKTQ2_PAGE_26_TXQPKTQ2_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_26_TXQPKTQ2_PAGE_26_TXQPKTQ2_COUNT_ALIGN       0
#define SWITCH_PAGE_26_TXQPKTQ2_PAGE_26_TXQPKTQ2_COUNT_BITS        32
#define SWITCH_PAGE_26_TXQPKTQ2_PAGE_26_TXQPKTQ2_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_TxQPKTQ3
 ***************************************************************************/
/* switch :: PAGE_26_TxQPKTQ3 :: PAGE_26_TxQPKTQ3_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxQPKTQ3_PAGE_26_TxQPKTQ3_COUNT(x) WriteReg(SWITCH_PAGE_26_TXQPKTQ3,x)
#define Rd_switch_PAGE_26_TxQPKTQ3_PAGE_26_TxQPKTQ3_COUNT(x) ReadReg(SWITCH_PAGE_26_TXQPKTQ3)
#define SWITCH_PAGE_26_TXQPKTQ3_PAGE_26_TXQPKTQ3_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_26_TXQPKTQ3_PAGE_26_TXQPKTQ3_COUNT_ALIGN       0
#define SWITCH_PAGE_26_TXQPKTQ3_PAGE_26_TXQPKTQ3_COUNT_BITS        32
#define SWITCH_PAGE_26_TXQPKTQ3_PAGE_26_TXQPKTQ3_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_TxQPKTQ4
 ***************************************************************************/
/* switch :: PAGE_26_TxQPKTQ4 :: PAGE_26_TxQPKTQ4_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxQPKTQ4_PAGE_26_TxQPKTQ4_COUNT(x) WriteReg(SWITCH_PAGE_26_TXQPKTQ4,x)
#define Rd_switch_PAGE_26_TxQPKTQ4_PAGE_26_TxQPKTQ4_COUNT(x) ReadReg(SWITCH_PAGE_26_TXQPKTQ4)
#define SWITCH_PAGE_26_TXQPKTQ4_PAGE_26_TXQPKTQ4_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_26_TXQPKTQ4_PAGE_26_TXQPKTQ4_COUNT_ALIGN       0
#define SWITCH_PAGE_26_TXQPKTQ4_PAGE_26_TXQPKTQ4_COUNT_BITS        32
#define SWITCH_PAGE_26_TXQPKTQ4_PAGE_26_TXQPKTQ4_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_TxQPKTQ5
 ***************************************************************************/
/* switch :: PAGE_26_TxQPKTQ5 :: PAGE_26_TxQPKTQ5_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxQPKTQ5_PAGE_26_TxQPKTQ5_COUNT(x) WriteReg(SWITCH_PAGE_26_TXQPKTQ5,x)
#define Rd_switch_PAGE_26_TxQPKTQ5_PAGE_26_TxQPKTQ5_COUNT(x) ReadReg(SWITCH_PAGE_26_TXQPKTQ5)
#define SWITCH_PAGE_26_TXQPKTQ5_PAGE_26_TXQPKTQ5_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_26_TXQPKTQ5_PAGE_26_TXQPKTQ5_COUNT_ALIGN       0
#define SWITCH_PAGE_26_TXQPKTQ5_PAGE_26_TXQPKTQ5_COUNT_BITS        32
#define SWITCH_PAGE_26_TXQPKTQ5_PAGE_26_TXQPKTQ5_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_RxOctets
 ***************************************************************************/
/* switch :: PAGE_26_RxOctets :: PAGE_26_RxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_26_RxOctets_PAGE_26_RxOctets_COUNT(x) WriteReg(SWITCH_PAGE_26_RXOCTETS,x)
#define Rd_switch_PAGE_26_RxOctets_PAGE_26_RxOctets_COUNT(x) ReadReg(SWITCH_PAGE_26_RXOCTETS)
#define SWITCH_PAGE_26_RXOCTETS_PAGE_26_RXOCTETS_COUNT_MASK        0xffffffffffffffff
#define SWITCH_PAGE_26_RXOCTETS_PAGE_26_RXOCTETS_COUNT_ALIGN       0
#define SWITCH_PAGE_26_RXOCTETS_PAGE_26_RXOCTETS_COUNT_BITS        64
#define SWITCH_PAGE_26_RXOCTETS_PAGE_26_RXOCTETS_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_RxUndersizePkts
 ***************************************************************************/
/* switch :: PAGE_26_RxUndersizePkts :: PAGE_26_RxUndersizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxUndersizePkts_PAGE_26_RxUndersizePkts_COUNT(x) WriteReg(SWITCH_PAGE_26_RXUNDERSIZEPKTS,x)
#define Rd_switch_PAGE_26_RxUndersizePkts_PAGE_26_RxUndersizePkts_COUNT(x) ReadReg(SWITCH_PAGE_26_RXUNDERSIZEPKTS)
#define SWITCH_PAGE_26_RXUNDERSIZEPKTS_PAGE_26_RXUNDERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXUNDERSIZEPKTS_PAGE_26_RXUNDERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXUNDERSIZEPKTS_PAGE_26_RXUNDERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXUNDERSIZEPKTS_PAGE_26_RXUNDERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxPausePkts
 ***************************************************************************/
/* switch :: PAGE_26_RxPausePkts :: PAGE_26_RxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxPausePkts_PAGE_26_RxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_26_RXPAUSEPKTS,x)
#define Rd_switch_PAGE_26_RxPausePkts_PAGE_26_RxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_26_RXPAUSEPKTS)
#define SWITCH_PAGE_26_RXPAUSEPKTS_PAGE_26_RXPAUSEPKTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_26_RXPAUSEPKTS_PAGE_26_RXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXPAUSEPKTS_PAGE_26_RXPAUSEPKTS_COUNT_BITS  32
#define SWITCH_PAGE_26_RXPAUSEPKTS_PAGE_26_RXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_26_RxPkts64Octets :: PAGE_26_RxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxPkts64Octets_PAGE_26_RxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_RXPKTS64OCTETS,x)
#define Rd_switch_PAGE_26_RxPkts64Octets_PAGE_26_RxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_RXPKTS64OCTETS)
#define SWITCH_PAGE_26_RXPKTS64OCTETS_PAGE_26_RXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXPKTS64OCTETS_PAGE_26_RXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXPKTS64OCTETS_PAGE_26_RXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXPKTS64OCTETS_PAGE_26_RXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_26_RxPkts65to127Octets :: PAGE_26_RxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxPkts65to127Octets_PAGE_26_RxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_RXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_26_RxPkts65to127Octets_PAGE_26_RxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_RXPKTS65TO127OCTETS)
#define SWITCH_PAGE_26_RXPKTS65TO127OCTETS_PAGE_26_RXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXPKTS65TO127OCTETS_PAGE_26_RXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXPKTS65TO127OCTETS_PAGE_26_RXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXPKTS65TO127OCTETS_PAGE_26_RXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_26_RxPkts128to255Octets :: PAGE_26_RxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxPkts128to255Octets_PAGE_26_RxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_RXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_26_RxPkts128to255Octets_PAGE_26_RxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_RXPKTS128TO255OCTETS)
#define SWITCH_PAGE_26_RXPKTS128TO255OCTETS_PAGE_26_RXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXPKTS128TO255OCTETS_PAGE_26_RXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXPKTS128TO255OCTETS_PAGE_26_RXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXPKTS128TO255OCTETS_PAGE_26_RXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_26_RxPkts256to511Octets :: PAGE_26_RxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxPkts256to511Octets_PAGE_26_RxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_RXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_26_RxPkts256to511Octets_PAGE_26_RxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_RXPKTS256TO511OCTETS)
#define SWITCH_PAGE_26_RXPKTS256TO511OCTETS_PAGE_26_RXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXPKTS256TO511OCTETS_PAGE_26_RXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXPKTS256TO511OCTETS_PAGE_26_RXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXPKTS256TO511OCTETS_PAGE_26_RXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_26_RxPkts512to1023Octets :: PAGE_26_RxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxPkts512to1023Octets_PAGE_26_RxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_RXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_26_RxPkts512to1023Octets_PAGE_26_RxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_RXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_26_RXPKTS512TO1023OCTETS_PAGE_26_RXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXPKTS512TO1023OCTETS_PAGE_26_RXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXPKTS512TO1023OCTETS_PAGE_26_RXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXPKTS512TO1023OCTETS_PAGE_26_RXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_26_RxPkts1024toMaxPktOctets :: PAGE_26_RxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxPkts1024toMaxPktOctets_PAGE_26_RxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_26_RXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_26_RxPkts1024toMaxPktOctets_PAGE_26_RxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_26_RXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_26_RXPKTS1024TOMAXPKTOCTETS_PAGE_26_RXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXPKTS1024TOMAXPKTOCTETS_PAGE_26_RXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXPKTS1024TOMAXPKTOCTETS_PAGE_26_RXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXPKTS1024TOMAXPKTOCTETS_PAGE_26_RXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxOversizePkts
 ***************************************************************************/
/* switch :: PAGE_26_RxOversizePkts :: PAGE_26_RxOversizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxOversizePkts_PAGE_26_RxOversizePkts_COUNT(x) WriteReg(SWITCH_PAGE_26_RXOVERSIZEPKTS,x)
#define Rd_switch_PAGE_26_RxOversizePkts_PAGE_26_RxOversizePkts_COUNT(x) ReadReg(SWITCH_PAGE_26_RXOVERSIZEPKTS)
#define SWITCH_PAGE_26_RXOVERSIZEPKTS_PAGE_26_RXOVERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXOVERSIZEPKTS_PAGE_26_RXOVERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXOVERSIZEPKTS_PAGE_26_RXOVERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXOVERSIZEPKTS_PAGE_26_RXOVERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxJabbers
 ***************************************************************************/
/* switch :: PAGE_26_RxJabbers :: PAGE_26_RxJabbers_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxJabbers_PAGE_26_RxJabbers_COUNT(x) WriteReg(SWITCH_PAGE_26_RXJABBERS,x)
#define Rd_switch_PAGE_26_RxJabbers_PAGE_26_RxJabbers_COUNT(x) ReadReg(SWITCH_PAGE_26_RXJABBERS)
#define SWITCH_PAGE_26_RXJABBERS_PAGE_26_RXJABBERS_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_26_RXJABBERS_PAGE_26_RXJABBERS_COUNT_ALIGN     0
#define SWITCH_PAGE_26_RXJABBERS_PAGE_26_RXJABBERS_COUNT_BITS      32
#define SWITCH_PAGE_26_RXJABBERS_PAGE_26_RXJABBERS_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_26_RxAlignmentErrors
 ***************************************************************************/
/* switch :: PAGE_26_RxAlignmentErrors :: PAGE_26_RxAlignmentErrors_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxAlignmentErrors_PAGE_26_RxAlignmentErrors_COUNT(x) WriteReg(SWITCH_PAGE_26_RXALIGNMENTERRORS,x)
#define Rd_switch_PAGE_26_RxAlignmentErrors_PAGE_26_RxAlignmentErrors_COUNT(x) ReadReg(SWITCH_PAGE_26_RXALIGNMENTERRORS)
#define SWITCH_PAGE_26_RXALIGNMENTERRORS_PAGE_26_RXALIGNMENTERRORS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXALIGNMENTERRORS_PAGE_26_RXALIGNMENTERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXALIGNMENTERRORS_PAGE_26_RXALIGNMENTERRORS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXALIGNMENTERRORS_PAGE_26_RXALIGNMENTERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxFCSErrors
 ***************************************************************************/
/* switch :: PAGE_26_RxFCSErrors :: PAGE_26_RxFCSErrors_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxFCSErrors_PAGE_26_RxFCSErrors_COUNT(x) WriteReg(SWITCH_PAGE_26_RXFCSERRORS,x)
#define Rd_switch_PAGE_26_RxFCSErrors_PAGE_26_RxFCSErrors_COUNT(x) ReadReg(SWITCH_PAGE_26_RXFCSERRORS)
#define SWITCH_PAGE_26_RXFCSERRORS_PAGE_26_RXFCSERRORS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_26_RXFCSERRORS_PAGE_26_RXFCSERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXFCSERRORS_PAGE_26_RXFCSERRORS_COUNT_BITS  32
#define SWITCH_PAGE_26_RXFCSERRORS_PAGE_26_RXFCSERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxGoodOctets
 ***************************************************************************/
/* switch :: PAGE_26_RxGoodOctets :: PAGE_26_RxGoodOctets_COUNT [63:00] */
#define Wr_switch_PAGE_26_RxGoodOctets_PAGE_26_RxGoodOctets_COUNT(x) WriteReg(SWITCH_PAGE_26_RXGOODOCTETS,x)
#define Rd_switch_PAGE_26_RxGoodOctets_PAGE_26_RxGoodOctets_COUNT(x) ReadReg(SWITCH_PAGE_26_RXGOODOCTETS)
#define SWITCH_PAGE_26_RXGOODOCTETS_PAGE_26_RXGOODOCTETS_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_26_RXGOODOCTETS_PAGE_26_RXGOODOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXGOODOCTETS_PAGE_26_RXGOODOCTETS_COUNT_BITS 64
#define SWITCH_PAGE_26_RXGOODOCTETS_PAGE_26_RXGOODOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxDropPkts
 ***************************************************************************/
/* switch :: PAGE_26_RxDropPkts :: PAGE_26_RxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxDropPkts_PAGE_26_RxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_26_RXDROPPKTS,x)
#define Rd_switch_PAGE_26_RxDropPkts_PAGE_26_RxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_26_RXDROPPKTS)
#define SWITCH_PAGE_26_RXDROPPKTS_PAGE_26_RXDROPPKTS_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_26_RXDROPPKTS_PAGE_26_RXDROPPKTS_COUNT_ALIGN   0
#define SWITCH_PAGE_26_RXDROPPKTS_PAGE_26_RXDROPPKTS_COUNT_BITS    32
#define SWITCH_PAGE_26_RXDROPPKTS_PAGE_26_RXDROPPKTS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_26_RxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_26_RxUnicastPkts :: PAGE_26_RxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxUnicastPkts_PAGE_26_RxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_26_RXUNICASTPKTS,x)
#define Rd_switch_PAGE_26_RxUnicastPkts_PAGE_26_RxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_26_RXUNICASTPKTS)
#define SWITCH_PAGE_26_RXUNICASTPKTS_PAGE_26_RXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXUNICASTPKTS_PAGE_26_RXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXUNICASTPKTS_PAGE_26_RXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXUNICASTPKTS_PAGE_26_RXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_26_RxMulticastPkts :: PAGE_26_RxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxMulticastPkts_PAGE_26_RxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_26_RXMULTICASTPKTS,x)
#define Rd_switch_PAGE_26_RxMulticastPkts_PAGE_26_RxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_26_RXMULTICASTPKTS)
#define SWITCH_PAGE_26_RXMULTICASTPKTS_PAGE_26_RXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXMULTICASTPKTS_PAGE_26_RXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXMULTICASTPKTS_PAGE_26_RXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXMULTICASTPKTS_PAGE_26_RXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_26_RxBroadcastPkts :: PAGE_26_RxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxBroadcastPkts_PAGE_26_RxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_26_RXBROADCASTPKTS,x)
#define Rd_switch_PAGE_26_RxBroadcastPkts_PAGE_26_RxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_26_RXBROADCASTPKTS)
#define SWITCH_PAGE_26_RXBROADCASTPKTS_PAGE_26_RXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_RXBROADCASTPKTS_PAGE_26_RXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXBROADCASTPKTS_PAGE_26_RXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_26_RXBROADCASTPKTS_PAGE_26_RXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxSAChanges
 ***************************************************************************/
/* switch :: PAGE_26_RxSAChanges :: PAGE_26_RxSAChanges_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxSAChanges_PAGE_26_RxSAChanges_COUNT(x) WriteReg(SWITCH_PAGE_26_RXSACHANGES,x)
#define Rd_switch_PAGE_26_RxSAChanges_PAGE_26_RxSAChanges_COUNT(x) ReadReg(SWITCH_PAGE_26_RXSACHANGES)
#define SWITCH_PAGE_26_RXSACHANGES_PAGE_26_RXSACHANGES_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_26_RXSACHANGES_PAGE_26_RXSACHANGES_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXSACHANGES_PAGE_26_RXSACHANGES_COUNT_BITS  32
#define SWITCH_PAGE_26_RXSACHANGES_PAGE_26_RXSACHANGES_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxFragments
 ***************************************************************************/
/* switch :: PAGE_26_RxFragments :: PAGE_26_RxFragments_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxFragments_PAGE_26_RxFragments_COUNT(x) WriteReg(SWITCH_PAGE_26_RXFRAGMENTS,x)
#define Rd_switch_PAGE_26_RxFragments_PAGE_26_RxFragments_COUNT(x) ReadReg(SWITCH_PAGE_26_RXFRAGMENTS)
#define SWITCH_PAGE_26_RXFRAGMENTS_PAGE_26_RXFRAGMENTS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_26_RXFRAGMENTS_PAGE_26_RXFRAGMENTS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_RXFRAGMENTS_PAGE_26_RXFRAGMENTS_COUNT_BITS  32
#define SWITCH_PAGE_26_RXFRAGMENTS_PAGE_26_RXFRAGMENTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxJumboPkt
 ***************************************************************************/
/* switch :: PAGE_26_RxJumboPkt :: PAGE_26_RxJumboPkt_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxJumboPkt_PAGE_26_RxJumboPkt_COUNT(x) WriteReg(SWITCH_PAGE_26_RXJUMBOPKT,x)
#define Rd_switch_PAGE_26_RxJumboPkt_PAGE_26_RxJumboPkt_COUNT(x) ReadReg(SWITCH_PAGE_26_RXJUMBOPKT)
#define SWITCH_PAGE_26_RXJUMBOPKT_PAGE_26_RXJUMBOPKT_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_26_RXJUMBOPKT_PAGE_26_RXJUMBOPKT_COUNT_ALIGN   0
#define SWITCH_PAGE_26_RXJUMBOPKT_PAGE_26_RXJUMBOPKT_COUNT_BITS    32
#define SWITCH_PAGE_26_RXJUMBOPKT_PAGE_26_RXJUMBOPKT_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_26_RxSymblErr
 ***************************************************************************/
/* switch :: PAGE_26_RxSymblErr :: PAGE_26_RxSymblErr_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxSymblErr_PAGE_26_RxSymblErr_COUNT(x) WriteReg(SWITCH_PAGE_26_RXSYMBLERR,x)
#define Rd_switch_PAGE_26_RxSymblErr_PAGE_26_RxSymblErr_COUNT(x) ReadReg(SWITCH_PAGE_26_RXSYMBLERR)
#define SWITCH_PAGE_26_RXSYMBLERR_PAGE_26_RXSYMBLERR_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_26_RXSYMBLERR_PAGE_26_RXSYMBLERR_COUNT_ALIGN   0
#define SWITCH_PAGE_26_RXSYMBLERR_PAGE_26_RXSYMBLERR_COUNT_BITS    32
#define SWITCH_PAGE_26_RXSYMBLERR_PAGE_26_RXSYMBLERR_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_26_InRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_26_InRangeErrCount :: PAGE_26_InRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_26_InRangeErrCount_PAGE_26_InRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_26_INRANGEERRCOUNT,x)
#define Rd_switch_PAGE_26_InRangeErrCount_PAGE_26_InRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_26_INRANGEERRCOUNT)
#define SWITCH_PAGE_26_INRANGEERRCOUNT_PAGE_26_INRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_INRANGEERRCOUNT_PAGE_26_INRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_26_INRANGEERRCOUNT_PAGE_26_INRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_26_INRANGEERRCOUNT_PAGE_26_INRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_OutRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_26_OutRangeErrCount :: PAGE_26_OutRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_26_OutRangeErrCount_PAGE_26_OutRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_26_OUTRANGEERRCOUNT,x)
#define Rd_switch_PAGE_26_OutRangeErrCount_PAGE_26_OutRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_26_OUTRANGEERRCOUNT)
#define SWITCH_PAGE_26_OUTRANGEERRCOUNT_PAGE_26_OUTRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_OUTRANGEERRCOUNT_PAGE_26_OUTRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_26_OUTRANGEERRCOUNT_PAGE_26_OUTRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_26_OUTRANGEERRCOUNT_PAGE_26_OUTRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_EEE_LPI_EVENT
 ***************************************************************************/
/* switch :: PAGE_26_EEE_LPI_EVENT :: PAGE_26_EEE_LPI_EVENT_COUNT [31:00] */
#define Wr_switch_PAGE_26_EEE_LPI_EVENT_PAGE_26_EEE_LPI_EVENT_COUNT(x) WriteReg(SWITCH_PAGE_26_EEE_LPI_EVENT,x)
#define Rd_switch_PAGE_26_EEE_LPI_EVENT_PAGE_26_EEE_LPI_EVENT_COUNT(x) ReadReg(SWITCH_PAGE_26_EEE_LPI_EVENT)
#define SWITCH_PAGE_26_EEE_LPI_EVENT_PAGE_26_EEE_LPI_EVENT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_EEE_LPI_EVENT_PAGE_26_EEE_LPI_EVENT_COUNT_ALIGN 0
#define SWITCH_PAGE_26_EEE_LPI_EVENT_PAGE_26_EEE_LPI_EVENT_COUNT_BITS 32
#define SWITCH_PAGE_26_EEE_LPI_EVENT_PAGE_26_EEE_LPI_EVENT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_EEE_LPI_DURATION
 ***************************************************************************/
/* switch :: PAGE_26_EEE_LPI_DURATION :: PAGE_26_EEE_LPI_DURATION_COUNT [31:00] */
#define Wr_switch_PAGE_26_EEE_LPI_DURATION_PAGE_26_EEE_LPI_DURATION_COUNT(x) WriteReg(SWITCH_PAGE_26_EEE_LPI_DURATION,x)
#define Rd_switch_PAGE_26_EEE_LPI_DURATION_PAGE_26_EEE_LPI_DURATION_COUNT(x) ReadReg(SWITCH_PAGE_26_EEE_LPI_DURATION)
#define SWITCH_PAGE_26_EEE_LPI_DURATION_PAGE_26_EEE_LPI_DURATION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_EEE_LPI_DURATION_PAGE_26_EEE_LPI_DURATION_COUNT_ALIGN 0
#define SWITCH_PAGE_26_EEE_LPI_DURATION_PAGE_26_EEE_LPI_DURATION_COUNT_BITS 32
#define SWITCH_PAGE_26_EEE_LPI_DURATION_PAGE_26_EEE_LPI_DURATION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_RxDiscard
 ***************************************************************************/
/* switch :: PAGE_26_RxDiscard :: PAGE_26_RxDiscard_COUNT [31:00] */
#define Wr_switch_PAGE_26_RxDiscard_PAGE_26_RxDiscard_COUNT(x) WriteReg(SWITCH_PAGE_26_RXDISCARD,x)
#define Rd_switch_PAGE_26_RxDiscard_PAGE_26_RxDiscard_COUNT(x) ReadReg(SWITCH_PAGE_26_RXDISCARD)
#define SWITCH_PAGE_26_RXDISCARD_PAGE_26_RXDISCARD_COUNT_MASK      0xffffffff
#define SWITCH_PAGE_26_RXDISCARD_PAGE_26_RXDISCARD_COUNT_ALIGN     0
#define SWITCH_PAGE_26_RXDISCARD_PAGE_26_RXDISCARD_COUNT_BITS      32
#define SWITCH_PAGE_26_RXDISCARD_PAGE_26_RXDISCARD_COUNT_SHIFT     0


/****************************************************************************
 * switch :: PAGE_26_TxQPKTQ6
 ***************************************************************************/
/* switch :: PAGE_26_TxQPKTQ6 :: PAGE_26_TxQPKTQ6_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxQPKTQ6_PAGE_26_TxQPKTQ6_COUNT(x) WriteReg(SWITCH_PAGE_26_TXQPKTQ6,x)
#define Rd_switch_PAGE_26_TxQPKTQ6_PAGE_26_TxQPKTQ6_COUNT(x) ReadReg(SWITCH_PAGE_26_TXQPKTQ6)
#define SWITCH_PAGE_26_TXQPKTQ6_PAGE_26_TXQPKTQ6_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_26_TXQPKTQ6_PAGE_26_TXQPKTQ6_COUNT_ALIGN       0
#define SWITCH_PAGE_26_TXQPKTQ6_PAGE_26_TXQPKTQ6_COUNT_BITS        32
#define SWITCH_PAGE_26_TXQPKTQ6_PAGE_26_TXQPKTQ6_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_TxQPKTQ7
 ***************************************************************************/
/* switch :: PAGE_26_TxQPKTQ7 :: PAGE_26_TxQPKTQ7_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxQPKTQ7_PAGE_26_TxQPKTQ7_COUNT(x) WriteReg(SWITCH_PAGE_26_TXQPKTQ7,x)
#define Rd_switch_PAGE_26_TxQPKTQ7_PAGE_26_TxQPKTQ7_COUNT(x) ReadReg(SWITCH_PAGE_26_TXQPKTQ7)
#define SWITCH_PAGE_26_TXQPKTQ7_PAGE_26_TXQPKTQ7_COUNT_MASK        0xffffffff
#define SWITCH_PAGE_26_TXQPKTQ7_PAGE_26_TXQPKTQ7_COUNT_ALIGN       0
#define SWITCH_PAGE_26_TXQPKTQ7_PAGE_26_TXQPKTQ7_COUNT_BITS        32
#define SWITCH_PAGE_26_TXQPKTQ7_PAGE_26_TXQPKTQ7_COUNT_SHIFT       0


/****************************************************************************
 * switch :: PAGE_26_TxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_26_TxPkts64Octets :: PAGE_26_TxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxPkts64Octets_PAGE_26_TxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_TXPKTS64OCTETS,x)
#define Rd_switch_PAGE_26_TxPkts64Octets_PAGE_26_TxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_TXPKTS64OCTETS)
#define SWITCH_PAGE_26_TXPKTS64OCTETS_PAGE_26_TXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXPKTS64OCTETS_PAGE_26_TXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXPKTS64OCTETS_PAGE_26_TXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXPKTS64OCTETS_PAGE_26_TXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_26_TxPkts65to127Octets :: PAGE_26_TxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxPkts65to127Octets_PAGE_26_TxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_TXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_26_TxPkts65to127Octets_PAGE_26_TxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_TXPKTS65TO127OCTETS)
#define SWITCH_PAGE_26_TXPKTS65TO127OCTETS_PAGE_26_TXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXPKTS65TO127OCTETS_PAGE_26_TXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXPKTS65TO127OCTETS_PAGE_26_TXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXPKTS65TO127OCTETS_PAGE_26_TXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_26_TxPkts128to255Octets :: PAGE_26_TxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxPkts128to255Octets_PAGE_26_TxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_TXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_26_TxPkts128to255Octets_PAGE_26_TxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_TXPKTS128TO255OCTETS)
#define SWITCH_PAGE_26_TXPKTS128TO255OCTETS_PAGE_26_TXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXPKTS128TO255OCTETS_PAGE_26_TXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXPKTS128TO255OCTETS_PAGE_26_TXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXPKTS128TO255OCTETS_PAGE_26_TXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_26_TxPkts256to511Octets :: PAGE_26_TxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxPkts256to511Octets_PAGE_26_TxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_TXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_26_TxPkts256to511Octets_PAGE_26_TxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_TXPKTS256TO511OCTETS)
#define SWITCH_PAGE_26_TXPKTS256TO511OCTETS_PAGE_26_TXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXPKTS256TO511OCTETS_PAGE_26_TXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXPKTS256TO511OCTETS_PAGE_26_TXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXPKTS256TO511OCTETS_PAGE_26_TXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_26_TxPkts512to1023Octets :: PAGE_26_TxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxPkts512to1023Octets_PAGE_26_TxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_26_TXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_26_TxPkts512to1023Octets_PAGE_26_TxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_26_TXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_26_TXPKTS512TO1023OCTETS_PAGE_26_TXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXPKTS512TO1023OCTETS_PAGE_26_TXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXPKTS512TO1023OCTETS_PAGE_26_TXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXPKTS512TO1023OCTETS_PAGE_26_TXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_26_TxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_26_TxPkts1024toMaxPktOctets :: PAGE_26_TxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_26_TxPkts1024toMaxPktOctets_PAGE_26_TxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_26_TXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_26_TxPkts1024toMaxPktOctets_PAGE_26_TxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_26_TXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_26_TXPKTS1024TOMAXPKTOCTETS_PAGE_26_TXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_26_TXPKTS1024TOMAXPKTOCTETS_PAGE_26_TXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_26_TXPKTS1024TOMAXPKTOCTETS_PAGE_26_TXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_26_TXPKTS1024TOMAXPKTOCTETS_PAGE_26_TXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxOctets_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxOctets_P7 :: PAGE_27_TxOctets_P7_COUNT [63:00] */
#define Wr_switch_PAGE_27_TxOctets_P7_PAGE_27_TxOctets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXOCTETS_P7,x)
#define Rd_switch_PAGE_27_TxOctets_P7_PAGE_27_TxOctets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXOCTETS_P7)
#define SWITCH_PAGE_27_TXOCTETS_P7_PAGE_27_TXOCTETS_P7_COUNT_MASK  0xffffffffffffffff
#define SWITCH_PAGE_27_TXOCTETS_P7_PAGE_27_TXOCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXOCTETS_P7_PAGE_27_TXOCTETS_P7_COUNT_BITS  64
#define SWITCH_PAGE_27_TXOCTETS_P7_PAGE_27_TXOCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxDropPkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxDropPkts_P7 :: PAGE_27_TxDropPkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxDropPkts_P7_PAGE_27_TxDropPkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXDROPPKTS_P7,x)
#define Rd_switch_PAGE_27_TxDropPkts_P7_PAGE_27_TxDropPkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXDROPPKTS_P7)
#define SWITCH_PAGE_27_TXDROPPKTS_P7_PAGE_27_TXDROPPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXDROPPKTS_P7_PAGE_27_TXDROPPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXDROPPKTS_P7_PAGE_27_TXDROPPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXDROPPKTS_P7_PAGE_27_TXDROPPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxQPKTQ0_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxQPKTQ0_P7 :: PAGE_27_TxQPKTQ0_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxQPKTQ0_P7_PAGE_27_TxQPKTQ0_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXQPKTQ0_P7,x)
#define Rd_switch_PAGE_27_TxQPKTQ0_P7_PAGE_27_TxQPKTQ0_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXQPKTQ0_P7)
#define SWITCH_PAGE_27_TXQPKTQ0_P7_PAGE_27_TXQPKTQ0_P7_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_27_TXQPKTQ0_P7_PAGE_27_TXQPKTQ0_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXQPKTQ0_P7_PAGE_27_TXQPKTQ0_P7_COUNT_BITS  32
#define SWITCH_PAGE_27_TXQPKTQ0_P7_PAGE_27_TXQPKTQ0_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxBroadcastPkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxBroadcastPkts_P7 :: PAGE_27_TxBroadcastPkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxBroadcastPkts_P7_PAGE_27_TxBroadcastPkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXBROADCASTPKTS_P7,x)
#define Rd_switch_PAGE_27_TxBroadcastPkts_P7_PAGE_27_TxBroadcastPkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXBROADCASTPKTS_P7)
#define SWITCH_PAGE_27_TXBROADCASTPKTS_P7_PAGE_27_TXBROADCASTPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXBROADCASTPKTS_P7_PAGE_27_TXBROADCASTPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXBROADCASTPKTS_P7_PAGE_27_TXBROADCASTPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXBROADCASTPKTS_P7_PAGE_27_TXBROADCASTPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxMulticastPkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxMulticastPkts_P7 :: PAGE_27_TxMulticastPkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxMulticastPkts_P7_PAGE_27_TxMulticastPkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXMULTICASTPKTS_P7,x)
#define Rd_switch_PAGE_27_TxMulticastPkts_P7_PAGE_27_TxMulticastPkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXMULTICASTPKTS_P7)
#define SWITCH_PAGE_27_TXMULTICASTPKTS_P7_PAGE_27_TXMULTICASTPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXMULTICASTPKTS_P7_PAGE_27_TXMULTICASTPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXMULTICASTPKTS_P7_PAGE_27_TXMULTICASTPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXMULTICASTPKTS_P7_PAGE_27_TXMULTICASTPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxUnicastPkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxUnicastPkts_P7 :: PAGE_27_TxUnicastPkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxUnicastPkts_P7_PAGE_27_TxUnicastPkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXUNICASTPKTS_P7,x)
#define Rd_switch_PAGE_27_TxUnicastPkts_P7_PAGE_27_TxUnicastPkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXUNICASTPKTS_P7)
#define SWITCH_PAGE_27_TXUNICASTPKTS_P7_PAGE_27_TXUNICASTPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXUNICASTPKTS_P7_PAGE_27_TXUNICASTPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXUNICASTPKTS_P7_PAGE_27_TXUNICASTPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXUNICASTPKTS_P7_PAGE_27_TXUNICASTPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxCollisions_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxCollisions_P7 :: PAGE_27_TxCollisions_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxCollisions_P7_PAGE_27_TxCollisions_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXCOLLISIONS_P7,x)
#define Rd_switch_PAGE_27_TxCollisions_P7_PAGE_27_TxCollisions_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXCOLLISIONS_P7)
#define SWITCH_PAGE_27_TXCOLLISIONS_P7_PAGE_27_TXCOLLISIONS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXCOLLISIONS_P7_PAGE_27_TXCOLLISIONS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXCOLLISIONS_P7_PAGE_27_TXCOLLISIONS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXCOLLISIONS_P7_PAGE_27_TXCOLLISIONS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxSingleCollision_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxSingleCollision_P7 :: PAGE_27_TxSingleCollision_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxSingleCollision_P7_PAGE_27_TxSingleCollision_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXSINGLECOLLISION_P7,x)
#define Rd_switch_PAGE_27_TxSingleCollision_P7_PAGE_27_TxSingleCollision_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXSINGLECOLLISION_P7)
#define SWITCH_PAGE_27_TXSINGLECOLLISION_P7_PAGE_27_TXSINGLECOLLISION_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXSINGLECOLLISION_P7_PAGE_27_TXSINGLECOLLISION_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXSINGLECOLLISION_P7_PAGE_27_TXSINGLECOLLISION_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXSINGLECOLLISION_P7_PAGE_27_TXSINGLECOLLISION_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxMultipleCollision_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxMultipleCollision_P7 :: PAGE_27_TxMultipleCollision_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxMultipleCollision_P7_PAGE_27_TxMultipleCollision_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXMULTIPLECOLLISION_P7,x)
#define Rd_switch_PAGE_27_TxMultipleCollision_P7_PAGE_27_TxMultipleCollision_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXMULTIPLECOLLISION_P7)
#define SWITCH_PAGE_27_TXMULTIPLECOLLISION_P7_PAGE_27_TXMULTIPLECOLLISION_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXMULTIPLECOLLISION_P7_PAGE_27_TXMULTIPLECOLLISION_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXMULTIPLECOLLISION_P7_PAGE_27_TXMULTIPLECOLLISION_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXMULTIPLECOLLISION_P7_PAGE_27_TXMULTIPLECOLLISION_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxDeferredTransmit_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxDeferredTransmit_P7 :: PAGE_27_TxDeferredTransmit_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxDeferredTransmit_P7_PAGE_27_TxDeferredTransmit_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXDEFERREDTRANSMIT_P7,x)
#define Rd_switch_PAGE_27_TxDeferredTransmit_P7_PAGE_27_TxDeferredTransmit_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXDEFERREDTRANSMIT_P7)
#define SWITCH_PAGE_27_TXDEFERREDTRANSMIT_P7_PAGE_27_TXDEFERREDTRANSMIT_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXDEFERREDTRANSMIT_P7_PAGE_27_TXDEFERREDTRANSMIT_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXDEFERREDTRANSMIT_P7_PAGE_27_TXDEFERREDTRANSMIT_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXDEFERREDTRANSMIT_P7_PAGE_27_TXDEFERREDTRANSMIT_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxLateCollision_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxLateCollision_P7 :: PAGE_27_TxLateCollision_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxLateCollision_P7_PAGE_27_TxLateCollision_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXLATECOLLISION_P7,x)
#define Rd_switch_PAGE_27_TxLateCollision_P7_PAGE_27_TxLateCollision_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXLATECOLLISION_P7)
#define SWITCH_PAGE_27_TXLATECOLLISION_P7_PAGE_27_TXLATECOLLISION_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXLATECOLLISION_P7_PAGE_27_TXLATECOLLISION_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXLATECOLLISION_P7_PAGE_27_TXLATECOLLISION_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXLATECOLLISION_P7_PAGE_27_TXLATECOLLISION_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxExcessiveCollision_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxExcessiveCollision_P7 :: PAGE_27_TxExcessiveCollision_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxExcessiveCollision_P7_PAGE_27_TxExcessiveCollision_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXEXCESSIVECOLLISION_P7,x)
#define Rd_switch_PAGE_27_TxExcessiveCollision_P7_PAGE_27_TxExcessiveCollision_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXEXCESSIVECOLLISION_P7)
#define SWITCH_PAGE_27_TXEXCESSIVECOLLISION_P7_PAGE_27_TXEXCESSIVECOLLISION_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXEXCESSIVECOLLISION_P7_PAGE_27_TXEXCESSIVECOLLISION_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXEXCESSIVECOLLISION_P7_PAGE_27_TXEXCESSIVECOLLISION_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXEXCESSIVECOLLISION_P7_PAGE_27_TXEXCESSIVECOLLISION_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxFrameInDisc_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxFrameInDisc_P7 :: PAGE_27_TxFrameInDisc_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxFrameInDisc_P7_PAGE_27_TxFrameInDisc_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXFRAMEINDISC_P7,x)
#define Rd_switch_PAGE_27_TxFrameInDisc_P7_PAGE_27_TxFrameInDisc_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXFRAMEINDISC_P7)
#define SWITCH_PAGE_27_TXFRAMEINDISC_P7_PAGE_27_TXFRAMEINDISC_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXFRAMEINDISC_P7_PAGE_27_TXFRAMEINDISC_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXFRAMEINDISC_P7_PAGE_27_TXFRAMEINDISC_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXFRAMEINDISC_P7_PAGE_27_TXFRAMEINDISC_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxPausePkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxPausePkts_P7 :: PAGE_27_TxPausePkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxPausePkts_P7_PAGE_27_TxPausePkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXPAUSEPKTS_P7,x)
#define Rd_switch_PAGE_27_TxPausePkts_P7_PAGE_27_TxPausePkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXPAUSEPKTS_P7)
#define SWITCH_PAGE_27_TXPAUSEPKTS_P7_PAGE_27_TXPAUSEPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXPAUSEPKTS_P7_PAGE_27_TXPAUSEPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXPAUSEPKTS_P7_PAGE_27_TXPAUSEPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXPAUSEPKTS_P7_PAGE_27_TXPAUSEPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxQPKTQ1_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxQPKTQ1_P7 :: PAGE_27_TxQPKTQ1_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxQPKTQ1_P7_PAGE_27_TxQPKTQ1_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXQPKTQ1_P7,x)
#define Rd_switch_PAGE_27_TxQPKTQ1_P7_PAGE_27_TxQPKTQ1_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXQPKTQ1_P7)
#define SWITCH_PAGE_27_TXQPKTQ1_P7_PAGE_27_TXQPKTQ1_P7_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_27_TXQPKTQ1_P7_PAGE_27_TXQPKTQ1_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXQPKTQ1_P7_PAGE_27_TXQPKTQ1_P7_COUNT_BITS  32
#define SWITCH_PAGE_27_TXQPKTQ1_P7_PAGE_27_TXQPKTQ1_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxQPKTQ2_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxQPKTQ2_P7 :: PAGE_27_TxQPKTQ2_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxQPKTQ2_P7_PAGE_27_TxQPKTQ2_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXQPKTQ2_P7,x)
#define Rd_switch_PAGE_27_TxQPKTQ2_P7_PAGE_27_TxQPKTQ2_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXQPKTQ2_P7)
#define SWITCH_PAGE_27_TXQPKTQ2_P7_PAGE_27_TXQPKTQ2_P7_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_27_TXQPKTQ2_P7_PAGE_27_TXQPKTQ2_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXQPKTQ2_P7_PAGE_27_TXQPKTQ2_P7_COUNT_BITS  32
#define SWITCH_PAGE_27_TXQPKTQ2_P7_PAGE_27_TXQPKTQ2_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxQPKTQ3_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxQPKTQ3_P7 :: PAGE_27_TxQPKTQ3_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxQPKTQ3_P7_PAGE_27_TxQPKTQ3_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXQPKTQ3_P7,x)
#define Rd_switch_PAGE_27_TxQPKTQ3_P7_PAGE_27_TxQPKTQ3_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXQPKTQ3_P7)
#define SWITCH_PAGE_27_TXQPKTQ3_P7_PAGE_27_TXQPKTQ3_P7_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_27_TXQPKTQ3_P7_PAGE_27_TXQPKTQ3_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXQPKTQ3_P7_PAGE_27_TXQPKTQ3_P7_COUNT_BITS  32
#define SWITCH_PAGE_27_TXQPKTQ3_P7_PAGE_27_TXQPKTQ3_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxQPKTQ4_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxQPKTQ4_P7 :: PAGE_27_TxQPKTQ4_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxQPKTQ4_P7_PAGE_27_TxQPKTQ4_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXQPKTQ4_P7,x)
#define Rd_switch_PAGE_27_TxQPKTQ4_P7_PAGE_27_TxQPKTQ4_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXQPKTQ4_P7)
#define SWITCH_PAGE_27_TXQPKTQ4_P7_PAGE_27_TXQPKTQ4_P7_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_27_TXQPKTQ4_P7_PAGE_27_TXQPKTQ4_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXQPKTQ4_P7_PAGE_27_TXQPKTQ4_P7_COUNT_BITS  32
#define SWITCH_PAGE_27_TXQPKTQ4_P7_PAGE_27_TXQPKTQ4_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxQPKTQ5_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxQPKTQ5_P7 :: PAGE_27_TxQPKTQ5_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxQPKTQ5_P7_PAGE_27_TxQPKTQ5_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXQPKTQ5_P7,x)
#define Rd_switch_PAGE_27_TxQPKTQ5_P7_PAGE_27_TxQPKTQ5_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXQPKTQ5_P7)
#define SWITCH_PAGE_27_TXQPKTQ5_P7_PAGE_27_TXQPKTQ5_P7_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_27_TXQPKTQ5_P7_PAGE_27_TXQPKTQ5_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXQPKTQ5_P7_PAGE_27_TXQPKTQ5_P7_COUNT_BITS  32
#define SWITCH_PAGE_27_TXQPKTQ5_P7_PAGE_27_TXQPKTQ5_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxOctets_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxOctets_P7 :: PAGE_27_RxOctets_P7_COUNT [63:00] */
#define Wr_switch_PAGE_27_RxOctets_P7_PAGE_27_RxOctets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXOCTETS_P7,x)
#define Rd_switch_PAGE_27_RxOctets_P7_PAGE_27_RxOctets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXOCTETS_P7)
#define SWITCH_PAGE_27_RXOCTETS_P7_PAGE_27_RXOCTETS_P7_COUNT_MASK  0xffffffffffffffff
#define SWITCH_PAGE_27_RXOCTETS_P7_PAGE_27_RXOCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXOCTETS_P7_PAGE_27_RXOCTETS_P7_COUNT_BITS  64
#define SWITCH_PAGE_27_RXOCTETS_P7_PAGE_27_RXOCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxUndersizePkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxUndersizePkts_P7 :: PAGE_27_RxUndersizePkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxUndersizePkts_P7_PAGE_27_RxUndersizePkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXUNDERSIZEPKTS_P7,x)
#define Rd_switch_PAGE_27_RxUndersizePkts_P7_PAGE_27_RxUndersizePkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXUNDERSIZEPKTS_P7)
#define SWITCH_PAGE_27_RXUNDERSIZEPKTS_P7_PAGE_27_RXUNDERSIZEPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXUNDERSIZEPKTS_P7_PAGE_27_RXUNDERSIZEPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXUNDERSIZEPKTS_P7_PAGE_27_RXUNDERSIZEPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXUNDERSIZEPKTS_P7_PAGE_27_RXUNDERSIZEPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxPausePkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxPausePkts_P7 :: PAGE_27_RxPausePkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxPausePkts_P7_PAGE_27_RxPausePkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXPAUSEPKTS_P7,x)
#define Rd_switch_PAGE_27_RxPausePkts_P7_PAGE_27_RxPausePkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXPAUSEPKTS_P7)
#define SWITCH_PAGE_27_RXPAUSEPKTS_P7_PAGE_27_RXPAUSEPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXPAUSEPKTS_P7_PAGE_27_RXPAUSEPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXPAUSEPKTS_P7_PAGE_27_RXPAUSEPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXPAUSEPKTS_P7_PAGE_27_RXPAUSEPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxPkts64Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxPkts64Octets_P7 :: PAGE_27_RxPkts64Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxPkts64Octets_P7_PAGE_27_RxPkts64Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXPKTS64OCTETS_P7,x)
#define Rd_switch_PAGE_27_RxPkts64Octets_P7_PAGE_27_RxPkts64Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXPKTS64OCTETS_P7)
#define SWITCH_PAGE_27_RXPKTS64OCTETS_P7_PAGE_27_RXPKTS64OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXPKTS64OCTETS_P7_PAGE_27_RXPKTS64OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXPKTS64OCTETS_P7_PAGE_27_RXPKTS64OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXPKTS64OCTETS_P7_PAGE_27_RXPKTS64OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxPkts65to127Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxPkts65to127Octets_P7 :: PAGE_27_RxPkts65to127Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxPkts65to127Octets_P7_PAGE_27_RxPkts65to127Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXPKTS65TO127OCTETS_P7,x)
#define Rd_switch_PAGE_27_RxPkts65to127Octets_P7_PAGE_27_RxPkts65to127Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXPKTS65TO127OCTETS_P7)
#define SWITCH_PAGE_27_RXPKTS65TO127OCTETS_P7_PAGE_27_RXPKTS65TO127OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXPKTS65TO127OCTETS_P7_PAGE_27_RXPKTS65TO127OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXPKTS65TO127OCTETS_P7_PAGE_27_RXPKTS65TO127OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXPKTS65TO127OCTETS_P7_PAGE_27_RXPKTS65TO127OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxPkts128to255Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxPkts128to255Octets_P7 :: PAGE_27_RxPkts128to255Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxPkts128to255Octets_P7_PAGE_27_RxPkts128to255Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXPKTS128TO255OCTETS_P7,x)
#define Rd_switch_PAGE_27_RxPkts128to255Octets_P7_PAGE_27_RxPkts128to255Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXPKTS128TO255OCTETS_P7)
#define SWITCH_PAGE_27_RXPKTS128TO255OCTETS_P7_PAGE_27_RXPKTS128TO255OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXPKTS128TO255OCTETS_P7_PAGE_27_RXPKTS128TO255OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXPKTS128TO255OCTETS_P7_PAGE_27_RXPKTS128TO255OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXPKTS128TO255OCTETS_P7_PAGE_27_RXPKTS128TO255OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxPkts256to511Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxPkts256to511Octets_P7 :: PAGE_27_RxPkts256to511Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxPkts256to511Octets_P7_PAGE_27_RxPkts256to511Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXPKTS256TO511OCTETS_P7,x)
#define Rd_switch_PAGE_27_RxPkts256to511Octets_P7_PAGE_27_RxPkts256to511Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXPKTS256TO511OCTETS_P7)
#define SWITCH_PAGE_27_RXPKTS256TO511OCTETS_P7_PAGE_27_RXPKTS256TO511OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXPKTS256TO511OCTETS_P7_PAGE_27_RXPKTS256TO511OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXPKTS256TO511OCTETS_P7_PAGE_27_RXPKTS256TO511OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXPKTS256TO511OCTETS_P7_PAGE_27_RXPKTS256TO511OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxPkts512to1023Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxPkts512to1023Octets_P7 :: PAGE_27_RxPkts512to1023Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxPkts512to1023Octets_P7_PAGE_27_RxPkts512to1023Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXPKTS512TO1023OCTETS_P7,x)
#define Rd_switch_PAGE_27_RxPkts512to1023Octets_P7_PAGE_27_RxPkts512to1023Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXPKTS512TO1023OCTETS_P7)
#define SWITCH_PAGE_27_RXPKTS512TO1023OCTETS_P7_PAGE_27_RXPKTS512TO1023OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXPKTS512TO1023OCTETS_P7_PAGE_27_RXPKTS512TO1023OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXPKTS512TO1023OCTETS_P7_PAGE_27_RXPKTS512TO1023OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXPKTS512TO1023OCTETS_P7_PAGE_27_RXPKTS512TO1023OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxPkts1024toMaxPktOctets_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxPkts1024toMaxPktOctets_P7 :: PAGE_27_RxPkts1024toMaxPktOctets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxPkts1024toMaxPktOctets_P7_PAGE_27_RxPkts1024toMaxPktOctets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7,x)
#define Rd_switch_PAGE_27_RxPkts1024toMaxPktOctets_P7_PAGE_27_RxPkts1024toMaxPktOctets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7)
#define SWITCH_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7_PAGE_27_RXPKTS1024TOMAXPKTOCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxOversizePkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxOversizePkts_P7 :: PAGE_27_RxOversizePkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxOversizePkts_P7_PAGE_27_RxOversizePkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXOVERSIZEPKTS_P7,x)
#define Rd_switch_PAGE_27_RxOversizePkts_P7_PAGE_27_RxOversizePkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXOVERSIZEPKTS_P7)
#define SWITCH_PAGE_27_RXOVERSIZEPKTS_P7_PAGE_27_RXOVERSIZEPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXOVERSIZEPKTS_P7_PAGE_27_RXOVERSIZEPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXOVERSIZEPKTS_P7_PAGE_27_RXOVERSIZEPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXOVERSIZEPKTS_P7_PAGE_27_RXOVERSIZEPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxJabbers_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxJabbers_P7 :: PAGE_27_RxJabbers_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxJabbers_P7_PAGE_27_RxJabbers_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXJABBERS_P7,x)
#define Rd_switch_PAGE_27_RxJabbers_P7_PAGE_27_RxJabbers_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXJABBERS_P7)
#define SWITCH_PAGE_27_RXJABBERS_P7_PAGE_27_RXJABBERS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXJABBERS_P7_PAGE_27_RXJABBERS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXJABBERS_P7_PAGE_27_RXJABBERS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXJABBERS_P7_PAGE_27_RXJABBERS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxAlignmentErrors_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxAlignmentErrors_P7 :: PAGE_27_RxAlignmentErrors_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxAlignmentErrors_P7_PAGE_27_RxAlignmentErrors_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXALIGNMENTERRORS_P7,x)
#define Rd_switch_PAGE_27_RxAlignmentErrors_P7_PAGE_27_RxAlignmentErrors_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXALIGNMENTERRORS_P7)
#define SWITCH_PAGE_27_RXALIGNMENTERRORS_P7_PAGE_27_RXALIGNMENTERRORS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXALIGNMENTERRORS_P7_PAGE_27_RXALIGNMENTERRORS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXALIGNMENTERRORS_P7_PAGE_27_RXALIGNMENTERRORS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXALIGNMENTERRORS_P7_PAGE_27_RXALIGNMENTERRORS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxFCSErrors_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxFCSErrors_P7 :: PAGE_27_RxFCSErrors_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxFCSErrors_P7_PAGE_27_RxFCSErrors_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXFCSERRORS_P7,x)
#define Rd_switch_PAGE_27_RxFCSErrors_P7_PAGE_27_RxFCSErrors_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXFCSERRORS_P7)
#define SWITCH_PAGE_27_RXFCSERRORS_P7_PAGE_27_RXFCSERRORS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXFCSERRORS_P7_PAGE_27_RXFCSERRORS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXFCSERRORS_P7_PAGE_27_RXFCSERRORS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXFCSERRORS_P7_PAGE_27_RXFCSERRORS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxGoodOctets_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxGoodOctets_P7 :: PAGE_27_RxGoodOctets_P7_COUNT [63:00] */
#define Wr_switch_PAGE_27_RxGoodOctets_P7_PAGE_27_RxGoodOctets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXGOODOCTETS_P7,x)
#define Rd_switch_PAGE_27_RxGoodOctets_P7_PAGE_27_RxGoodOctets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXGOODOCTETS_P7)
#define SWITCH_PAGE_27_RXGOODOCTETS_P7_PAGE_27_RXGOODOCTETS_P7_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_27_RXGOODOCTETS_P7_PAGE_27_RXGOODOCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXGOODOCTETS_P7_PAGE_27_RXGOODOCTETS_P7_COUNT_BITS 64
#define SWITCH_PAGE_27_RXGOODOCTETS_P7_PAGE_27_RXGOODOCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxDropPkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxDropPkts_P7 :: PAGE_27_RxDropPkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxDropPkts_P7_PAGE_27_RxDropPkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXDROPPKTS_P7,x)
#define Rd_switch_PAGE_27_RxDropPkts_P7_PAGE_27_RxDropPkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXDROPPKTS_P7)
#define SWITCH_PAGE_27_RXDROPPKTS_P7_PAGE_27_RXDROPPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXDROPPKTS_P7_PAGE_27_RXDROPPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXDROPPKTS_P7_PAGE_27_RXDROPPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXDROPPKTS_P7_PAGE_27_RXDROPPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxUnicastPkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxUnicastPkts_P7 :: PAGE_27_RxUnicastPkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxUnicastPkts_P7_PAGE_27_RxUnicastPkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXUNICASTPKTS_P7,x)
#define Rd_switch_PAGE_27_RxUnicastPkts_P7_PAGE_27_RxUnicastPkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXUNICASTPKTS_P7)
#define SWITCH_PAGE_27_RXUNICASTPKTS_P7_PAGE_27_RXUNICASTPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXUNICASTPKTS_P7_PAGE_27_RXUNICASTPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXUNICASTPKTS_P7_PAGE_27_RXUNICASTPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXUNICASTPKTS_P7_PAGE_27_RXUNICASTPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxMulticastPkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxMulticastPkts_P7 :: PAGE_27_RxMulticastPkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxMulticastPkts_P7_PAGE_27_RxMulticastPkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXMULTICASTPKTS_P7,x)
#define Rd_switch_PAGE_27_RxMulticastPkts_P7_PAGE_27_RxMulticastPkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXMULTICASTPKTS_P7)
#define SWITCH_PAGE_27_RXMULTICASTPKTS_P7_PAGE_27_RXMULTICASTPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXMULTICASTPKTS_P7_PAGE_27_RXMULTICASTPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXMULTICASTPKTS_P7_PAGE_27_RXMULTICASTPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXMULTICASTPKTS_P7_PAGE_27_RXMULTICASTPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxBroadcastPkts_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxBroadcastPkts_P7 :: PAGE_27_RxBroadcastPkts_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxBroadcastPkts_P7_PAGE_27_RxBroadcastPkts_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXBROADCASTPKTS_P7,x)
#define Rd_switch_PAGE_27_RxBroadcastPkts_P7_PAGE_27_RxBroadcastPkts_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXBROADCASTPKTS_P7)
#define SWITCH_PAGE_27_RXBROADCASTPKTS_P7_PAGE_27_RXBROADCASTPKTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXBROADCASTPKTS_P7_PAGE_27_RXBROADCASTPKTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXBROADCASTPKTS_P7_PAGE_27_RXBROADCASTPKTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXBROADCASTPKTS_P7_PAGE_27_RXBROADCASTPKTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxSAChanges_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxSAChanges_P7 :: PAGE_27_RxSAChanges_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxSAChanges_P7_PAGE_27_RxSAChanges_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXSACHANGES_P7,x)
#define Rd_switch_PAGE_27_RxSAChanges_P7_PAGE_27_RxSAChanges_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXSACHANGES_P7)
#define SWITCH_PAGE_27_RXSACHANGES_P7_PAGE_27_RXSACHANGES_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXSACHANGES_P7_PAGE_27_RXSACHANGES_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXSACHANGES_P7_PAGE_27_RXSACHANGES_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXSACHANGES_P7_PAGE_27_RXSACHANGES_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxFragments_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxFragments_P7 :: PAGE_27_RxFragments_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxFragments_P7_PAGE_27_RxFragments_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXFRAGMENTS_P7,x)
#define Rd_switch_PAGE_27_RxFragments_P7_PAGE_27_RxFragments_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXFRAGMENTS_P7)
#define SWITCH_PAGE_27_RXFRAGMENTS_P7_PAGE_27_RXFRAGMENTS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXFRAGMENTS_P7_PAGE_27_RXFRAGMENTS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXFRAGMENTS_P7_PAGE_27_RXFRAGMENTS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXFRAGMENTS_P7_PAGE_27_RXFRAGMENTS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxJumboPkt_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxJumboPkt_P7 :: PAGE_27_RxJumboPkt_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxJumboPkt_P7_PAGE_27_RxJumboPkt_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXJUMBOPKT_P7,x)
#define Rd_switch_PAGE_27_RxJumboPkt_P7_PAGE_27_RxJumboPkt_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXJUMBOPKT_P7)
#define SWITCH_PAGE_27_RXJUMBOPKT_P7_PAGE_27_RXJUMBOPKT_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXJUMBOPKT_P7_PAGE_27_RXJUMBOPKT_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXJUMBOPKT_P7_PAGE_27_RXJUMBOPKT_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXJUMBOPKT_P7_PAGE_27_RXJUMBOPKT_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxSymblErr_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxSymblErr_P7 :: PAGE_27_RxSymblErr_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxSymblErr_P7_PAGE_27_RxSymblErr_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXSYMBLERR_P7,x)
#define Rd_switch_PAGE_27_RxSymblErr_P7_PAGE_27_RxSymblErr_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXSYMBLERR_P7)
#define SWITCH_PAGE_27_RXSYMBLERR_P7_PAGE_27_RXSYMBLERR_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXSYMBLERR_P7_PAGE_27_RXSYMBLERR_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXSYMBLERR_P7_PAGE_27_RXSYMBLERR_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXSYMBLERR_P7_PAGE_27_RXSYMBLERR_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_InRangeErrCount_P7
 ***************************************************************************/
/* switch :: PAGE_27_InRangeErrCount_P7 :: PAGE_27_InRangeErrCount_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_InRangeErrCount_P7_PAGE_27_InRangeErrCount_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_INRANGEERRCOUNT_P7,x)
#define Rd_switch_PAGE_27_InRangeErrCount_P7_PAGE_27_InRangeErrCount_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_INRANGEERRCOUNT_P7)
#define SWITCH_PAGE_27_INRANGEERRCOUNT_P7_PAGE_27_INRANGEERRCOUNT_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_INRANGEERRCOUNT_P7_PAGE_27_INRANGEERRCOUNT_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_INRANGEERRCOUNT_P7_PAGE_27_INRANGEERRCOUNT_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_INRANGEERRCOUNT_P7_PAGE_27_INRANGEERRCOUNT_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_OutRangeErrCount_P7
 ***************************************************************************/
/* switch :: PAGE_27_OutRangeErrCount_P7 :: PAGE_27_OutRangeErrCount_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_OutRangeErrCount_P7_PAGE_27_OutRangeErrCount_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_OUTRANGEERRCOUNT_P7,x)
#define Rd_switch_PAGE_27_OutRangeErrCount_P7_PAGE_27_OutRangeErrCount_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_OUTRANGEERRCOUNT_P7)
#define SWITCH_PAGE_27_OUTRANGEERRCOUNT_P7_PAGE_27_OUTRANGEERRCOUNT_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_OUTRANGEERRCOUNT_P7_PAGE_27_OUTRANGEERRCOUNT_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_OUTRANGEERRCOUNT_P7_PAGE_27_OUTRANGEERRCOUNT_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_OUTRANGEERRCOUNT_P7_PAGE_27_OUTRANGEERRCOUNT_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_EEE_LPI_EVENT_P7
 ***************************************************************************/
/* switch :: PAGE_27_EEE_LPI_EVENT_P7 :: PAGE_27_EEE_LPI_EVENT_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_EEE_LPI_EVENT_P7_PAGE_27_EEE_LPI_EVENT_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_EEE_LPI_EVENT_P7,x)
#define Rd_switch_PAGE_27_EEE_LPI_EVENT_P7_PAGE_27_EEE_LPI_EVENT_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_EEE_LPI_EVENT_P7)
#define SWITCH_PAGE_27_EEE_LPI_EVENT_P7_PAGE_27_EEE_LPI_EVENT_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_EEE_LPI_EVENT_P7_PAGE_27_EEE_LPI_EVENT_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_EEE_LPI_EVENT_P7_PAGE_27_EEE_LPI_EVENT_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_EEE_LPI_EVENT_P7_PAGE_27_EEE_LPI_EVENT_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_EEE_LPI_DURATION_P7
 ***************************************************************************/
/* switch :: PAGE_27_EEE_LPI_DURATION_P7 :: PAGE_27_EEE_LPI_DURATION_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_EEE_LPI_DURATION_P7_PAGE_27_EEE_LPI_DURATION_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_EEE_LPI_DURATION_P7,x)
#define Rd_switch_PAGE_27_EEE_LPI_DURATION_P7_PAGE_27_EEE_LPI_DURATION_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_EEE_LPI_DURATION_P7)
#define SWITCH_PAGE_27_EEE_LPI_DURATION_P7_PAGE_27_EEE_LPI_DURATION_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_EEE_LPI_DURATION_P7_PAGE_27_EEE_LPI_DURATION_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_EEE_LPI_DURATION_P7_PAGE_27_EEE_LPI_DURATION_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_EEE_LPI_DURATION_P7_PAGE_27_EEE_LPI_DURATION_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_RxDiscard_P7
 ***************************************************************************/
/* switch :: PAGE_27_RxDiscard_P7 :: PAGE_27_RxDiscard_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_RxDiscard_P7_PAGE_27_RxDiscard_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_RXDISCARD_P7,x)
#define Rd_switch_PAGE_27_RxDiscard_P7_PAGE_27_RxDiscard_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_RXDISCARD_P7)
#define SWITCH_PAGE_27_RXDISCARD_P7_PAGE_27_RXDISCARD_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_RXDISCARD_P7_PAGE_27_RXDISCARD_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_RXDISCARD_P7_PAGE_27_RXDISCARD_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_RXDISCARD_P7_PAGE_27_RXDISCARD_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxQPKTQ6_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxQPKTQ6_P7 :: PAGE_27_TxQPKTQ6_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxQPKTQ6_P7_PAGE_27_TxQPKTQ6_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXQPKTQ6_P7,x)
#define Rd_switch_PAGE_27_TxQPKTQ6_P7_PAGE_27_TxQPKTQ6_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXQPKTQ6_P7)
#define SWITCH_PAGE_27_TXQPKTQ6_P7_PAGE_27_TXQPKTQ6_P7_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_27_TXQPKTQ6_P7_PAGE_27_TXQPKTQ6_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXQPKTQ6_P7_PAGE_27_TXQPKTQ6_P7_COUNT_BITS  32
#define SWITCH_PAGE_27_TXQPKTQ6_P7_PAGE_27_TXQPKTQ6_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxQPKTQ7_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxQPKTQ7_P7 :: PAGE_27_TxQPKTQ7_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxQPKTQ7_P7_PAGE_27_TxQPKTQ7_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXQPKTQ7_P7,x)
#define Rd_switch_PAGE_27_TxQPKTQ7_P7_PAGE_27_TxQPKTQ7_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXQPKTQ7_P7)
#define SWITCH_PAGE_27_TXQPKTQ7_P7_PAGE_27_TXQPKTQ7_P7_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_27_TXQPKTQ7_P7_PAGE_27_TXQPKTQ7_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXQPKTQ7_P7_PAGE_27_TXQPKTQ7_P7_COUNT_BITS  32
#define SWITCH_PAGE_27_TXQPKTQ7_P7_PAGE_27_TXQPKTQ7_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxPkts64Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxPkts64Octets_P7 :: PAGE_27_TxPkts64Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxPkts64Octets_P7_PAGE_27_TxPkts64Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXPKTS64OCTETS_P7,x)
#define Rd_switch_PAGE_27_TxPkts64Octets_P7_PAGE_27_TxPkts64Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXPKTS64OCTETS_P7)
#define SWITCH_PAGE_27_TXPKTS64OCTETS_P7_PAGE_27_TXPKTS64OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXPKTS64OCTETS_P7_PAGE_27_TXPKTS64OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXPKTS64OCTETS_P7_PAGE_27_TXPKTS64OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXPKTS64OCTETS_P7_PAGE_27_TXPKTS64OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxPkts65to127Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxPkts65to127Octets_P7 :: PAGE_27_TxPkts65to127Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxPkts65to127Octets_P7_PAGE_27_TxPkts65to127Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXPKTS65TO127OCTETS_P7,x)
#define Rd_switch_PAGE_27_TxPkts65to127Octets_P7_PAGE_27_TxPkts65to127Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXPKTS65TO127OCTETS_P7)
#define SWITCH_PAGE_27_TXPKTS65TO127OCTETS_P7_PAGE_27_TXPKTS65TO127OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXPKTS65TO127OCTETS_P7_PAGE_27_TXPKTS65TO127OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXPKTS65TO127OCTETS_P7_PAGE_27_TXPKTS65TO127OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXPKTS65TO127OCTETS_P7_PAGE_27_TXPKTS65TO127OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxPkts128to255Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxPkts128to255Octets_P7 :: PAGE_27_TxPkts128to255Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxPkts128to255Octets_P7_PAGE_27_TxPkts128to255Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXPKTS128TO255OCTETS_P7,x)
#define Rd_switch_PAGE_27_TxPkts128to255Octets_P7_PAGE_27_TxPkts128to255Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXPKTS128TO255OCTETS_P7)
#define SWITCH_PAGE_27_TXPKTS128TO255OCTETS_P7_PAGE_27_TXPKTS128TO255OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXPKTS128TO255OCTETS_P7_PAGE_27_TXPKTS128TO255OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXPKTS128TO255OCTETS_P7_PAGE_27_TXPKTS128TO255OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXPKTS128TO255OCTETS_P7_PAGE_27_TXPKTS128TO255OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxPkts256to511Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxPkts256to511Octets_P7 :: PAGE_27_TxPkts256to511Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxPkts256to511Octets_P7_PAGE_27_TxPkts256to511Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXPKTS256TO511OCTETS_P7,x)
#define Rd_switch_PAGE_27_TxPkts256to511Octets_P7_PAGE_27_TxPkts256to511Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXPKTS256TO511OCTETS_P7)
#define SWITCH_PAGE_27_TXPKTS256TO511OCTETS_P7_PAGE_27_TXPKTS256TO511OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXPKTS256TO511OCTETS_P7_PAGE_27_TXPKTS256TO511OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXPKTS256TO511OCTETS_P7_PAGE_27_TXPKTS256TO511OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXPKTS256TO511OCTETS_P7_PAGE_27_TXPKTS256TO511OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxPkts512to1023Octets_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxPkts512to1023Octets_P7 :: PAGE_27_TxPkts512to1023Octets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxPkts512to1023Octets_P7_PAGE_27_TxPkts512to1023Octets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXPKTS512TO1023OCTETS_P7,x)
#define Rd_switch_PAGE_27_TxPkts512to1023Octets_P7_PAGE_27_TxPkts512to1023Octets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXPKTS512TO1023OCTETS_P7)
#define SWITCH_PAGE_27_TXPKTS512TO1023OCTETS_P7_PAGE_27_TXPKTS512TO1023OCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXPKTS512TO1023OCTETS_P7_PAGE_27_TXPKTS512TO1023OCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXPKTS512TO1023OCTETS_P7_PAGE_27_TXPKTS512TO1023OCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXPKTS512TO1023OCTETS_P7_PAGE_27_TXPKTS512TO1023OCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_27_TxPkts1024toMaxPktOctets_P7
 ***************************************************************************/
/* switch :: PAGE_27_TxPkts1024toMaxPktOctets_P7 :: PAGE_27_TxPkts1024toMaxPktOctets_P7_COUNT [31:00] */
#define Wr_switch_PAGE_27_TxPkts1024toMaxPktOctets_P7_PAGE_27_TxPkts1024toMaxPktOctets_P7_COUNT(x) WriteReg(SWITCH_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7,x)
#define Rd_switch_PAGE_27_TxPkts1024toMaxPktOctets_P7_PAGE_27_TxPkts1024toMaxPktOctets_P7_COUNT(x) ReadReg(SWITCH_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7)
#define SWITCH_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7_COUNT_ALIGN 0
#define SWITCH_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7_COUNT_BITS 32
#define SWITCH_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7_PAGE_27_TXPKTS1024TOMAXPKTOCTETS_P7_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxOctets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxOctets_IMP :: PAGE_28_TxOctets_IMP_COUNT [63:00] */
#define Wr_switch_PAGE_28_TxOctets_IMP_PAGE_28_TxOctets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXOCTETS_IMP,x)
#define Rd_switch_PAGE_28_TxOctets_IMP_PAGE_28_TxOctets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXOCTETS_IMP)
#define SWITCH_PAGE_28_TXOCTETS_IMP_PAGE_28_TXOCTETS_IMP_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_28_TXOCTETS_IMP_PAGE_28_TXOCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXOCTETS_IMP_PAGE_28_TXOCTETS_IMP_COUNT_BITS 64
#define SWITCH_PAGE_28_TXOCTETS_IMP_PAGE_28_TXOCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxDropPkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxDropPkts_IMP :: PAGE_28_TxDropPkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxDropPkts_IMP_PAGE_28_TxDropPkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXDROPPKTS_IMP,x)
#define Rd_switch_PAGE_28_TxDropPkts_IMP_PAGE_28_TxDropPkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXDROPPKTS_IMP)
#define SWITCH_PAGE_28_TXDROPPKTS_IMP_PAGE_28_TXDROPPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXDROPPKTS_IMP_PAGE_28_TXDROPPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXDROPPKTS_IMP_PAGE_28_TXDROPPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXDROPPKTS_IMP_PAGE_28_TXDROPPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxQPKTQ0_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxQPKTQ0_IMP :: PAGE_28_TxQPKTQ0_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxQPKTQ0_IMP_PAGE_28_TxQPKTQ0_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXQPKTQ0_IMP,x)
#define Rd_switch_PAGE_28_TxQPKTQ0_IMP_PAGE_28_TxQPKTQ0_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXQPKTQ0_IMP)
#define SWITCH_PAGE_28_TXQPKTQ0_IMP_PAGE_28_TXQPKTQ0_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXQPKTQ0_IMP_PAGE_28_TXQPKTQ0_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXQPKTQ0_IMP_PAGE_28_TXQPKTQ0_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXQPKTQ0_IMP_PAGE_28_TXQPKTQ0_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxBroadcastPkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxBroadcastPkts_IMP :: PAGE_28_TxBroadcastPkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxBroadcastPkts_IMP_PAGE_28_TxBroadcastPkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXBROADCASTPKTS_IMP,x)
#define Rd_switch_PAGE_28_TxBroadcastPkts_IMP_PAGE_28_TxBroadcastPkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXBROADCASTPKTS_IMP)
#define SWITCH_PAGE_28_TXBROADCASTPKTS_IMP_PAGE_28_TXBROADCASTPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXBROADCASTPKTS_IMP_PAGE_28_TXBROADCASTPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXBROADCASTPKTS_IMP_PAGE_28_TXBROADCASTPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXBROADCASTPKTS_IMP_PAGE_28_TXBROADCASTPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxMulticastPkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxMulticastPkts_IMP :: PAGE_28_TxMulticastPkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxMulticastPkts_IMP_PAGE_28_TxMulticastPkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXMULTICASTPKTS_IMP,x)
#define Rd_switch_PAGE_28_TxMulticastPkts_IMP_PAGE_28_TxMulticastPkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXMULTICASTPKTS_IMP)
#define SWITCH_PAGE_28_TXMULTICASTPKTS_IMP_PAGE_28_TXMULTICASTPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXMULTICASTPKTS_IMP_PAGE_28_TXMULTICASTPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXMULTICASTPKTS_IMP_PAGE_28_TXMULTICASTPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXMULTICASTPKTS_IMP_PAGE_28_TXMULTICASTPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxUnicastPkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxUnicastPkts_IMP :: PAGE_28_TxUnicastPkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxUnicastPkts_IMP_PAGE_28_TxUnicastPkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXUNICASTPKTS_IMP,x)
#define Rd_switch_PAGE_28_TxUnicastPkts_IMP_PAGE_28_TxUnicastPkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXUNICASTPKTS_IMP)
#define SWITCH_PAGE_28_TXUNICASTPKTS_IMP_PAGE_28_TXUNICASTPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXUNICASTPKTS_IMP_PAGE_28_TXUNICASTPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXUNICASTPKTS_IMP_PAGE_28_TXUNICASTPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXUNICASTPKTS_IMP_PAGE_28_TXUNICASTPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxCollisions_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxCollisions_IMP :: PAGE_28_TxCollisions_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxCollisions_IMP_PAGE_28_TxCollisions_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXCOLLISIONS_IMP,x)
#define Rd_switch_PAGE_28_TxCollisions_IMP_PAGE_28_TxCollisions_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXCOLLISIONS_IMP)
#define SWITCH_PAGE_28_TXCOLLISIONS_IMP_PAGE_28_TXCOLLISIONS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXCOLLISIONS_IMP_PAGE_28_TXCOLLISIONS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXCOLLISIONS_IMP_PAGE_28_TXCOLLISIONS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXCOLLISIONS_IMP_PAGE_28_TXCOLLISIONS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxSingleCollision_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxSingleCollision_IMP :: PAGE_28_TxSingleCollision_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxSingleCollision_IMP_PAGE_28_TxSingleCollision_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXSINGLECOLLISION_IMP,x)
#define Rd_switch_PAGE_28_TxSingleCollision_IMP_PAGE_28_TxSingleCollision_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXSINGLECOLLISION_IMP)
#define SWITCH_PAGE_28_TXSINGLECOLLISION_IMP_PAGE_28_TXSINGLECOLLISION_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXSINGLECOLLISION_IMP_PAGE_28_TXSINGLECOLLISION_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXSINGLECOLLISION_IMP_PAGE_28_TXSINGLECOLLISION_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXSINGLECOLLISION_IMP_PAGE_28_TXSINGLECOLLISION_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxMultipleCollision_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxMultipleCollision_IMP :: PAGE_28_TxMultipleCollision_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxMultipleCollision_IMP_PAGE_28_TxMultipleCollision_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXMULTIPLECOLLISION_IMP,x)
#define Rd_switch_PAGE_28_TxMultipleCollision_IMP_PAGE_28_TxMultipleCollision_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXMULTIPLECOLLISION_IMP)
#define SWITCH_PAGE_28_TXMULTIPLECOLLISION_IMP_PAGE_28_TXMULTIPLECOLLISION_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXMULTIPLECOLLISION_IMP_PAGE_28_TXMULTIPLECOLLISION_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXMULTIPLECOLLISION_IMP_PAGE_28_TXMULTIPLECOLLISION_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXMULTIPLECOLLISION_IMP_PAGE_28_TXMULTIPLECOLLISION_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxDeferredTransmit_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxDeferredTransmit_IMP :: PAGE_28_TxDeferredTransmit_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxDeferredTransmit_IMP_PAGE_28_TxDeferredTransmit_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXDEFERREDTRANSMIT_IMP,x)
#define Rd_switch_PAGE_28_TxDeferredTransmit_IMP_PAGE_28_TxDeferredTransmit_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXDEFERREDTRANSMIT_IMP)
#define SWITCH_PAGE_28_TXDEFERREDTRANSMIT_IMP_PAGE_28_TXDEFERREDTRANSMIT_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXDEFERREDTRANSMIT_IMP_PAGE_28_TXDEFERREDTRANSMIT_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXDEFERREDTRANSMIT_IMP_PAGE_28_TXDEFERREDTRANSMIT_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXDEFERREDTRANSMIT_IMP_PAGE_28_TXDEFERREDTRANSMIT_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxLateCollision_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxLateCollision_IMP :: PAGE_28_TxLateCollision_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxLateCollision_IMP_PAGE_28_TxLateCollision_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXLATECOLLISION_IMP,x)
#define Rd_switch_PAGE_28_TxLateCollision_IMP_PAGE_28_TxLateCollision_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXLATECOLLISION_IMP)
#define SWITCH_PAGE_28_TXLATECOLLISION_IMP_PAGE_28_TXLATECOLLISION_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXLATECOLLISION_IMP_PAGE_28_TXLATECOLLISION_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXLATECOLLISION_IMP_PAGE_28_TXLATECOLLISION_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXLATECOLLISION_IMP_PAGE_28_TXLATECOLLISION_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxExcessiveCollision_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxExcessiveCollision_IMP :: PAGE_28_TxExcessiveCollision_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxExcessiveCollision_IMP_PAGE_28_TxExcessiveCollision_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXEXCESSIVECOLLISION_IMP,x)
#define Rd_switch_PAGE_28_TxExcessiveCollision_IMP_PAGE_28_TxExcessiveCollision_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXEXCESSIVECOLLISION_IMP)
#define SWITCH_PAGE_28_TXEXCESSIVECOLLISION_IMP_PAGE_28_TXEXCESSIVECOLLISION_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXEXCESSIVECOLLISION_IMP_PAGE_28_TXEXCESSIVECOLLISION_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXEXCESSIVECOLLISION_IMP_PAGE_28_TXEXCESSIVECOLLISION_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXEXCESSIVECOLLISION_IMP_PAGE_28_TXEXCESSIVECOLLISION_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxFrameInDisc_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxFrameInDisc_IMP :: PAGE_28_TxFrameInDisc_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxFrameInDisc_IMP_PAGE_28_TxFrameInDisc_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXFRAMEINDISC_IMP,x)
#define Rd_switch_PAGE_28_TxFrameInDisc_IMP_PAGE_28_TxFrameInDisc_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXFRAMEINDISC_IMP)
#define SWITCH_PAGE_28_TXFRAMEINDISC_IMP_PAGE_28_TXFRAMEINDISC_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXFRAMEINDISC_IMP_PAGE_28_TXFRAMEINDISC_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXFRAMEINDISC_IMP_PAGE_28_TXFRAMEINDISC_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXFRAMEINDISC_IMP_PAGE_28_TXFRAMEINDISC_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxPausePkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxPausePkts_IMP :: PAGE_28_TxPausePkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxPausePkts_IMP_PAGE_28_TxPausePkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXPAUSEPKTS_IMP,x)
#define Rd_switch_PAGE_28_TxPausePkts_IMP_PAGE_28_TxPausePkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXPAUSEPKTS_IMP)
#define SWITCH_PAGE_28_TXPAUSEPKTS_IMP_PAGE_28_TXPAUSEPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXPAUSEPKTS_IMP_PAGE_28_TXPAUSEPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXPAUSEPKTS_IMP_PAGE_28_TXPAUSEPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXPAUSEPKTS_IMP_PAGE_28_TXPAUSEPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxQPKTQ1_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxQPKTQ1_IMP :: PAGE_28_TxQPKTQ1_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxQPKTQ1_IMP_PAGE_28_TxQPKTQ1_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXQPKTQ1_IMP,x)
#define Rd_switch_PAGE_28_TxQPKTQ1_IMP_PAGE_28_TxQPKTQ1_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXQPKTQ1_IMP)
#define SWITCH_PAGE_28_TXQPKTQ1_IMP_PAGE_28_TXQPKTQ1_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXQPKTQ1_IMP_PAGE_28_TXQPKTQ1_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXQPKTQ1_IMP_PAGE_28_TXQPKTQ1_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXQPKTQ1_IMP_PAGE_28_TXQPKTQ1_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxQPKTQ2_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxQPKTQ2_IMP :: PAGE_28_TxQPKTQ2_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxQPKTQ2_IMP_PAGE_28_TxQPKTQ2_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXQPKTQ2_IMP,x)
#define Rd_switch_PAGE_28_TxQPKTQ2_IMP_PAGE_28_TxQPKTQ2_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXQPKTQ2_IMP)
#define SWITCH_PAGE_28_TXQPKTQ2_IMP_PAGE_28_TXQPKTQ2_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXQPKTQ2_IMP_PAGE_28_TXQPKTQ2_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXQPKTQ2_IMP_PAGE_28_TXQPKTQ2_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXQPKTQ2_IMP_PAGE_28_TXQPKTQ2_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxQPKTQ3_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxQPKTQ3_IMP :: PAGE_28_TxQPKTQ3_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxQPKTQ3_IMP_PAGE_28_TxQPKTQ3_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXQPKTQ3_IMP,x)
#define Rd_switch_PAGE_28_TxQPKTQ3_IMP_PAGE_28_TxQPKTQ3_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXQPKTQ3_IMP)
#define SWITCH_PAGE_28_TXQPKTQ3_IMP_PAGE_28_TXQPKTQ3_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXQPKTQ3_IMP_PAGE_28_TXQPKTQ3_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXQPKTQ3_IMP_PAGE_28_TXQPKTQ3_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXQPKTQ3_IMP_PAGE_28_TXQPKTQ3_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxQPKTQ4_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxQPKTQ4_IMP :: PAGE_28_TxQPKTQ4_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxQPKTQ4_IMP_PAGE_28_TxQPKTQ4_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXQPKTQ4_IMP,x)
#define Rd_switch_PAGE_28_TxQPKTQ4_IMP_PAGE_28_TxQPKTQ4_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXQPKTQ4_IMP)
#define SWITCH_PAGE_28_TXQPKTQ4_IMP_PAGE_28_TXQPKTQ4_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXQPKTQ4_IMP_PAGE_28_TXQPKTQ4_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXQPKTQ4_IMP_PAGE_28_TXQPKTQ4_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXQPKTQ4_IMP_PAGE_28_TXQPKTQ4_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxQPKTQ5_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxQPKTQ5_IMP :: PAGE_28_TxQPKTQ5_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxQPKTQ5_IMP_PAGE_28_TxQPKTQ5_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXQPKTQ5_IMP,x)
#define Rd_switch_PAGE_28_TxQPKTQ5_IMP_PAGE_28_TxQPKTQ5_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXQPKTQ5_IMP)
#define SWITCH_PAGE_28_TXQPKTQ5_IMP_PAGE_28_TXQPKTQ5_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXQPKTQ5_IMP_PAGE_28_TXQPKTQ5_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXQPKTQ5_IMP_PAGE_28_TXQPKTQ5_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXQPKTQ5_IMP_PAGE_28_TXQPKTQ5_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxOctets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxOctets_IMP :: PAGE_28_RxOctets_IMP_COUNT [63:00] */
#define Wr_switch_PAGE_28_RxOctets_IMP_PAGE_28_RxOctets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXOCTETS_IMP,x)
#define Rd_switch_PAGE_28_RxOctets_IMP_PAGE_28_RxOctets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXOCTETS_IMP)
#define SWITCH_PAGE_28_RXOCTETS_IMP_PAGE_28_RXOCTETS_IMP_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_28_RXOCTETS_IMP_PAGE_28_RXOCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXOCTETS_IMP_PAGE_28_RXOCTETS_IMP_COUNT_BITS 64
#define SWITCH_PAGE_28_RXOCTETS_IMP_PAGE_28_RXOCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxUndersizePkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxUndersizePkts_IMP :: PAGE_28_RxUndersizePkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxUndersizePkts_IMP_PAGE_28_RxUndersizePkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXUNDERSIZEPKTS_IMP,x)
#define Rd_switch_PAGE_28_RxUndersizePkts_IMP_PAGE_28_RxUndersizePkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXUNDERSIZEPKTS_IMP)
#define SWITCH_PAGE_28_RXUNDERSIZEPKTS_IMP_PAGE_28_RXUNDERSIZEPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXUNDERSIZEPKTS_IMP_PAGE_28_RXUNDERSIZEPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXUNDERSIZEPKTS_IMP_PAGE_28_RXUNDERSIZEPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXUNDERSIZEPKTS_IMP_PAGE_28_RXUNDERSIZEPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxPausePkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxPausePkts_IMP :: PAGE_28_RxPausePkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxPausePkts_IMP_PAGE_28_RxPausePkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXPAUSEPKTS_IMP,x)
#define Rd_switch_PAGE_28_RxPausePkts_IMP_PAGE_28_RxPausePkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXPAUSEPKTS_IMP)
#define SWITCH_PAGE_28_RXPAUSEPKTS_IMP_PAGE_28_RXPAUSEPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXPAUSEPKTS_IMP_PAGE_28_RXPAUSEPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXPAUSEPKTS_IMP_PAGE_28_RXPAUSEPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXPAUSEPKTS_IMP_PAGE_28_RXPAUSEPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxPkts64Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxPkts64Octets_IMP :: PAGE_28_RxPkts64Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxPkts64Octets_IMP_PAGE_28_RxPkts64Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXPKTS64OCTETS_IMP,x)
#define Rd_switch_PAGE_28_RxPkts64Octets_IMP_PAGE_28_RxPkts64Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXPKTS64OCTETS_IMP)
#define SWITCH_PAGE_28_RXPKTS64OCTETS_IMP_PAGE_28_RXPKTS64OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXPKTS64OCTETS_IMP_PAGE_28_RXPKTS64OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXPKTS64OCTETS_IMP_PAGE_28_RXPKTS64OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXPKTS64OCTETS_IMP_PAGE_28_RXPKTS64OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxPkts65to127Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxPkts65to127Octets_IMP :: PAGE_28_RxPkts65to127Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxPkts65to127Octets_IMP_PAGE_28_RxPkts65to127Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXPKTS65TO127OCTETS_IMP,x)
#define Rd_switch_PAGE_28_RxPkts65to127Octets_IMP_PAGE_28_RxPkts65to127Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXPKTS65TO127OCTETS_IMP)
#define SWITCH_PAGE_28_RXPKTS65TO127OCTETS_IMP_PAGE_28_RXPKTS65TO127OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXPKTS65TO127OCTETS_IMP_PAGE_28_RXPKTS65TO127OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXPKTS65TO127OCTETS_IMP_PAGE_28_RXPKTS65TO127OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXPKTS65TO127OCTETS_IMP_PAGE_28_RXPKTS65TO127OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxPkts128to255Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxPkts128to255Octets_IMP :: PAGE_28_RxPkts128to255Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxPkts128to255Octets_IMP_PAGE_28_RxPkts128to255Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXPKTS128TO255OCTETS_IMP,x)
#define Rd_switch_PAGE_28_RxPkts128to255Octets_IMP_PAGE_28_RxPkts128to255Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXPKTS128TO255OCTETS_IMP)
#define SWITCH_PAGE_28_RXPKTS128TO255OCTETS_IMP_PAGE_28_RXPKTS128TO255OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXPKTS128TO255OCTETS_IMP_PAGE_28_RXPKTS128TO255OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXPKTS128TO255OCTETS_IMP_PAGE_28_RXPKTS128TO255OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXPKTS128TO255OCTETS_IMP_PAGE_28_RXPKTS128TO255OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxPkts256to511Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxPkts256to511Octets_IMP :: PAGE_28_RxPkts256to511Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxPkts256to511Octets_IMP_PAGE_28_RxPkts256to511Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXPKTS256TO511OCTETS_IMP,x)
#define Rd_switch_PAGE_28_RxPkts256to511Octets_IMP_PAGE_28_RxPkts256to511Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXPKTS256TO511OCTETS_IMP)
#define SWITCH_PAGE_28_RXPKTS256TO511OCTETS_IMP_PAGE_28_RXPKTS256TO511OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXPKTS256TO511OCTETS_IMP_PAGE_28_RXPKTS256TO511OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXPKTS256TO511OCTETS_IMP_PAGE_28_RXPKTS256TO511OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXPKTS256TO511OCTETS_IMP_PAGE_28_RXPKTS256TO511OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxPkts512to1023Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxPkts512to1023Octets_IMP :: PAGE_28_RxPkts512to1023Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxPkts512to1023Octets_IMP_PAGE_28_RxPkts512to1023Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXPKTS512TO1023OCTETS_IMP,x)
#define Rd_switch_PAGE_28_RxPkts512to1023Octets_IMP_PAGE_28_RxPkts512to1023Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXPKTS512TO1023OCTETS_IMP)
#define SWITCH_PAGE_28_RXPKTS512TO1023OCTETS_IMP_PAGE_28_RXPKTS512TO1023OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXPKTS512TO1023OCTETS_IMP_PAGE_28_RXPKTS512TO1023OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXPKTS512TO1023OCTETS_IMP_PAGE_28_RXPKTS512TO1023OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXPKTS512TO1023OCTETS_IMP_PAGE_28_RXPKTS512TO1023OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxPkts1024toMaxPktOctets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxPkts1024toMaxPktOctets_IMP :: PAGE_28_RxPkts1024toMaxPktOctets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxPkts1024toMaxPktOctets_IMP_PAGE_28_RxPkts1024toMaxPktOctets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP,x)
#define Rd_switch_PAGE_28_RxPkts1024toMaxPktOctets_IMP_PAGE_28_RxPkts1024toMaxPktOctets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP)
#define SWITCH_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP_PAGE_28_RXPKTS1024TOMAXPKTOCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxOversizePkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxOversizePkts_IMP :: PAGE_28_RxOversizePkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxOversizePkts_IMP_PAGE_28_RxOversizePkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXOVERSIZEPKTS_IMP,x)
#define Rd_switch_PAGE_28_RxOversizePkts_IMP_PAGE_28_RxOversizePkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXOVERSIZEPKTS_IMP)
#define SWITCH_PAGE_28_RXOVERSIZEPKTS_IMP_PAGE_28_RXOVERSIZEPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXOVERSIZEPKTS_IMP_PAGE_28_RXOVERSIZEPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXOVERSIZEPKTS_IMP_PAGE_28_RXOVERSIZEPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXOVERSIZEPKTS_IMP_PAGE_28_RXOVERSIZEPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxJabbers_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxJabbers_IMP :: PAGE_28_RxJabbers_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxJabbers_IMP_PAGE_28_RxJabbers_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXJABBERS_IMP,x)
#define Rd_switch_PAGE_28_RxJabbers_IMP_PAGE_28_RxJabbers_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXJABBERS_IMP)
#define SWITCH_PAGE_28_RXJABBERS_IMP_PAGE_28_RXJABBERS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXJABBERS_IMP_PAGE_28_RXJABBERS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXJABBERS_IMP_PAGE_28_RXJABBERS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXJABBERS_IMP_PAGE_28_RXJABBERS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxAlignmentErrors_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxAlignmentErrors_IMP :: PAGE_28_RxAlignmentErrors_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxAlignmentErrors_IMP_PAGE_28_RxAlignmentErrors_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXALIGNMENTERRORS_IMP,x)
#define Rd_switch_PAGE_28_RxAlignmentErrors_IMP_PAGE_28_RxAlignmentErrors_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXALIGNMENTERRORS_IMP)
#define SWITCH_PAGE_28_RXALIGNMENTERRORS_IMP_PAGE_28_RXALIGNMENTERRORS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXALIGNMENTERRORS_IMP_PAGE_28_RXALIGNMENTERRORS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXALIGNMENTERRORS_IMP_PAGE_28_RXALIGNMENTERRORS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXALIGNMENTERRORS_IMP_PAGE_28_RXALIGNMENTERRORS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxFCSErrors_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxFCSErrors_IMP :: PAGE_28_RxFCSErrors_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxFCSErrors_IMP_PAGE_28_RxFCSErrors_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXFCSERRORS_IMP,x)
#define Rd_switch_PAGE_28_RxFCSErrors_IMP_PAGE_28_RxFCSErrors_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXFCSERRORS_IMP)
#define SWITCH_PAGE_28_RXFCSERRORS_IMP_PAGE_28_RXFCSERRORS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXFCSERRORS_IMP_PAGE_28_RXFCSERRORS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXFCSERRORS_IMP_PAGE_28_RXFCSERRORS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXFCSERRORS_IMP_PAGE_28_RXFCSERRORS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxGoodOctets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxGoodOctets_IMP :: PAGE_28_RxGoodOctets_IMP_COUNT [63:00] */
#define Wr_switch_PAGE_28_RxGoodOctets_IMP_PAGE_28_RxGoodOctets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXGOODOCTETS_IMP,x)
#define Rd_switch_PAGE_28_RxGoodOctets_IMP_PAGE_28_RxGoodOctets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXGOODOCTETS_IMP)
#define SWITCH_PAGE_28_RXGOODOCTETS_IMP_PAGE_28_RXGOODOCTETS_IMP_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_28_RXGOODOCTETS_IMP_PAGE_28_RXGOODOCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXGOODOCTETS_IMP_PAGE_28_RXGOODOCTETS_IMP_COUNT_BITS 64
#define SWITCH_PAGE_28_RXGOODOCTETS_IMP_PAGE_28_RXGOODOCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxDropPkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxDropPkts_IMP :: PAGE_28_RxDropPkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxDropPkts_IMP_PAGE_28_RxDropPkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXDROPPKTS_IMP,x)
#define Rd_switch_PAGE_28_RxDropPkts_IMP_PAGE_28_RxDropPkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXDROPPKTS_IMP)
#define SWITCH_PAGE_28_RXDROPPKTS_IMP_PAGE_28_RXDROPPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXDROPPKTS_IMP_PAGE_28_RXDROPPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXDROPPKTS_IMP_PAGE_28_RXDROPPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXDROPPKTS_IMP_PAGE_28_RXDROPPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxUnicastPkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxUnicastPkts_IMP :: PAGE_28_RxUnicastPkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxUnicastPkts_IMP_PAGE_28_RxUnicastPkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXUNICASTPKTS_IMP,x)
#define Rd_switch_PAGE_28_RxUnicastPkts_IMP_PAGE_28_RxUnicastPkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXUNICASTPKTS_IMP)
#define SWITCH_PAGE_28_RXUNICASTPKTS_IMP_PAGE_28_RXUNICASTPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXUNICASTPKTS_IMP_PAGE_28_RXUNICASTPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXUNICASTPKTS_IMP_PAGE_28_RXUNICASTPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXUNICASTPKTS_IMP_PAGE_28_RXUNICASTPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxMulticastPkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxMulticastPkts_IMP :: PAGE_28_RxMulticastPkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxMulticastPkts_IMP_PAGE_28_RxMulticastPkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXMULTICASTPKTS_IMP,x)
#define Rd_switch_PAGE_28_RxMulticastPkts_IMP_PAGE_28_RxMulticastPkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXMULTICASTPKTS_IMP)
#define SWITCH_PAGE_28_RXMULTICASTPKTS_IMP_PAGE_28_RXMULTICASTPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXMULTICASTPKTS_IMP_PAGE_28_RXMULTICASTPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXMULTICASTPKTS_IMP_PAGE_28_RXMULTICASTPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXMULTICASTPKTS_IMP_PAGE_28_RXMULTICASTPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxBroadcastPkts_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxBroadcastPkts_IMP :: PAGE_28_RxBroadcastPkts_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxBroadcastPkts_IMP_PAGE_28_RxBroadcastPkts_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXBROADCASTPKTS_IMP,x)
#define Rd_switch_PAGE_28_RxBroadcastPkts_IMP_PAGE_28_RxBroadcastPkts_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXBROADCASTPKTS_IMP)
#define SWITCH_PAGE_28_RXBROADCASTPKTS_IMP_PAGE_28_RXBROADCASTPKTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXBROADCASTPKTS_IMP_PAGE_28_RXBROADCASTPKTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXBROADCASTPKTS_IMP_PAGE_28_RXBROADCASTPKTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXBROADCASTPKTS_IMP_PAGE_28_RXBROADCASTPKTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxSAChanges_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxSAChanges_IMP :: PAGE_28_RxSAChanges_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxSAChanges_IMP_PAGE_28_RxSAChanges_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXSACHANGES_IMP,x)
#define Rd_switch_PAGE_28_RxSAChanges_IMP_PAGE_28_RxSAChanges_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXSACHANGES_IMP)
#define SWITCH_PAGE_28_RXSACHANGES_IMP_PAGE_28_RXSACHANGES_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXSACHANGES_IMP_PAGE_28_RXSACHANGES_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXSACHANGES_IMP_PAGE_28_RXSACHANGES_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXSACHANGES_IMP_PAGE_28_RXSACHANGES_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxFragments_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxFragments_IMP :: PAGE_28_RxFragments_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxFragments_IMP_PAGE_28_RxFragments_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXFRAGMENTS_IMP,x)
#define Rd_switch_PAGE_28_RxFragments_IMP_PAGE_28_RxFragments_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXFRAGMENTS_IMP)
#define SWITCH_PAGE_28_RXFRAGMENTS_IMP_PAGE_28_RXFRAGMENTS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXFRAGMENTS_IMP_PAGE_28_RXFRAGMENTS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXFRAGMENTS_IMP_PAGE_28_RXFRAGMENTS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXFRAGMENTS_IMP_PAGE_28_RXFRAGMENTS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxJumboPkt_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxJumboPkt_IMP :: PAGE_28_RxJumboPkt_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxJumboPkt_IMP_PAGE_28_RxJumboPkt_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXJUMBOPKT_IMP,x)
#define Rd_switch_PAGE_28_RxJumboPkt_IMP_PAGE_28_RxJumboPkt_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXJUMBOPKT_IMP)
#define SWITCH_PAGE_28_RXJUMBOPKT_IMP_PAGE_28_RXJUMBOPKT_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXJUMBOPKT_IMP_PAGE_28_RXJUMBOPKT_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXJUMBOPKT_IMP_PAGE_28_RXJUMBOPKT_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXJUMBOPKT_IMP_PAGE_28_RXJUMBOPKT_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxSymblErr_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxSymblErr_IMP :: PAGE_28_RxSymblErr_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxSymblErr_IMP_PAGE_28_RxSymblErr_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXSYMBLERR_IMP,x)
#define Rd_switch_PAGE_28_RxSymblErr_IMP_PAGE_28_RxSymblErr_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXSYMBLERR_IMP)
#define SWITCH_PAGE_28_RXSYMBLERR_IMP_PAGE_28_RXSYMBLERR_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXSYMBLERR_IMP_PAGE_28_RXSYMBLERR_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXSYMBLERR_IMP_PAGE_28_RXSYMBLERR_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXSYMBLERR_IMP_PAGE_28_RXSYMBLERR_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_InRangeErrCount_IMP
 ***************************************************************************/
/* switch :: PAGE_28_InRangeErrCount_IMP :: PAGE_28_InRangeErrCount_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_InRangeErrCount_IMP_PAGE_28_InRangeErrCount_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_INRANGEERRCOUNT_IMP,x)
#define Rd_switch_PAGE_28_InRangeErrCount_IMP_PAGE_28_InRangeErrCount_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_INRANGEERRCOUNT_IMP)
#define SWITCH_PAGE_28_INRANGEERRCOUNT_IMP_PAGE_28_INRANGEERRCOUNT_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_INRANGEERRCOUNT_IMP_PAGE_28_INRANGEERRCOUNT_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_INRANGEERRCOUNT_IMP_PAGE_28_INRANGEERRCOUNT_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_INRANGEERRCOUNT_IMP_PAGE_28_INRANGEERRCOUNT_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_OutRangeErrCount_IMP
 ***************************************************************************/
/* switch :: PAGE_28_OutRangeErrCount_IMP :: PAGE_28_OutRangeErrCount_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_OutRangeErrCount_IMP_PAGE_28_OutRangeErrCount_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_OUTRANGEERRCOUNT_IMP,x)
#define Rd_switch_PAGE_28_OutRangeErrCount_IMP_PAGE_28_OutRangeErrCount_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_OUTRANGEERRCOUNT_IMP)
#define SWITCH_PAGE_28_OUTRANGEERRCOUNT_IMP_PAGE_28_OUTRANGEERRCOUNT_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_OUTRANGEERRCOUNT_IMP_PAGE_28_OUTRANGEERRCOUNT_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_OUTRANGEERRCOUNT_IMP_PAGE_28_OUTRANGEERRCOUNT_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_OUTRANGEERRCOUNT_IMP_PAGE_28_OUTRANGEERRCOUNT_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_EEE_LPI_EVENT_IMP
 ***************************************************************************/
/* switch :: PAGE_28_EEE_LPI_EVENT_IMP :: PAGE_28_EEE_LPI_EVENT_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_EEE_LPI_EVENT_IMP_PAGE_28_EEE_LPI_EVENT_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_EEE_LPI_EVENT_IMP,x)
#define Rd_switch_PAGE_28_EEE_LPI_EVENT_IMP_PAGE_28_EEE_LPI_EVENT_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_EEE_LPI_EVENT_IMP)
#define SWITCH_PAGE_28_EEE_LPI_EVENT_IMP_PAGE_28_EEE_LPI_EVENT_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_EEE_LPI_EVENT_IMP_PAGE_28_EEE_LPI_EVENT_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_EEE_LPI_EVENT_IMP_PAGE_28_EEE_LPI_EVENT_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_EEE_LPI_EVENT_IMP_PAGE_28_EEE_LPI_EVENT_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_EEE_LPI_DURATION_IMP
 ***************************************************************************/
/* switch :: PAGE_28_EEE_LPI_DURATION_IMP :: PAGE_28_EEE_LPI_DURATION_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_EEE_LPI_DURATION_IMP_PAGE_28_EEE_LPI_DURATION_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_EEE_LPI_DURATION_IMP,x)
#define Rd_switch_PAGE_28_EEE_LPI_DURATION_IMP_PAGE_28_EEE_LPI_DURATION_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_EEE_LPI_DURATION_IMP)
#define SWITCH_PAGE_28_EEE_LPI_DURATION_IMP_PAGE_28_EEE_LPI_DURATION_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_EEE_LPI_DURATION_IMP_PAGE_28_EEE_LPI_DURATION_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_EEE_LPI_DURATION_IMP_PAGE_28_EEE_LPI_DURATION_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_EEE_LPI_DURATION_IMP_PAGE_28_EEE_LPI_DURATION_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_RxDiscard_IMP
 ***************************************************************************/
/* switch :: PAGE_28_RxDiscard_IMP :: PAGE_28_RxDiscard_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_RxDiscard_IMP_PAGE_28_RxDiscard_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_RXDISCARD_IMP,x)
#define Rd_switch_PAGE_28_RxDiscard_IMP_PAGE_28_RxDiscard_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_RXDISCARD_IMP)
#define SWITCH_PAGE_28_RXDISCARD_IMP_PAGE_28_RXDISCARD_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_RXDISCARD_IMP_PAGE_28_RXDISCARD_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_RXDISCARD_IMP_PAGE_28_RXDISCARD_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_RXDISCARD_IMP_PAGE_28_RXDISCARD_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxQPKTQ6_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxQPKTQ6_IMP :: PAGE_28_TxQPKTQ6_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxQPKTQ6_IMP_PAGE_28_TxQPKTQ6_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXQPKTQ6_IMP,x)
#define Rd_switch_PAGE_28_TxQPKTQ6_IMP_PAGE_28_TxQPKTQ6_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXQPKTQ6_IMP)
#define SWITCH_PAGE_28_TXQPKTQ6_IMP_PAGE_28_TXQPKTQ6_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXQPKTQ6_IMP_PAGE_28_TXQPKTQ6_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXQPKTQ6_IMP_PAGE_28_TXQPKTQ6_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXQPKTQ6_IMP_PAGE_28_TXQPKTQ6_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxQPKTQ7_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxQPKTQ7_IMP :: PAGE_28_TxQPKTQ7_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxQPKTQ7_IMP_PAGE_28_TxQPKTQ7_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXQPKTQ7_IMP,x)
#define Rd_switch_PAGE_28_TxQPKTQ7_IMP_PAGE_28_TxQPKTQ7_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXQPKTQ7_IMP)
#define SWITCH_PAGE_28_TXQPKTQ7_IMP_PAGE_28_TXQPKTQ7_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXQPKTQ7_IMP_PAGE_28_TXQPKTQ7_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXQPKTQ7_IMP_PAGE_28_TXQPKTQ7_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXQPKTQ7_IMP_PAGE_28_TXQPKTQ7_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxPkts64Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxPkts64Octets_IMP :: PAGE_28_TxPkts64Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxPkts64Octets_IMP_PAGE_28_TxPkts64Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXPKTS64OCTETS_IMP,x)
#define Rd_switch_PAGE_28_TxPkts64Octets_IMP_PAGE_28_TxPkts64Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXPKTS64OCTETS_IMP)
#define SWITCH_PAGE_28_TXPKTS64OCTETS_IMP_PAGE_28_TXPKTS64OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXPKTS64OCTETS_IMP_PAGE_28_TXPKTS64OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXPKTS64OCTETS_IMP_PAGE_28_TXPKTS64OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXPKTS64OCTETS_IMP_PAGE_28_TXPKTS64OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxPkts65to127Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxPkts65to127Octets_IMP :: PAGE_28_TxPkts65to127Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxPkts65to127Octets_IMP_PAGE_28_TxPkts65to127Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXPKTS65TO127OCTETS_IMP,x)
#define Rd_switch_PAGE_28_TxPkts65to127Octets_IMP_PAGE_28_TxPkts65to127Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXPKTS65TO127OCTETS_IMP)
#define SWITCH_PAGE_28_TXPKTS65TO127OCTETS_IMP_PAGE_28_TXPKTS65TO127OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXPKTS65TO127OCTETS_IMP_PAGE_28_TXPKTS65TO127OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXPKTS65TO127OCTETS_IMP_PAGE_28_TXPKTS65TO127OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXPKTS65TO127OCTETS_IMP_PAGE_28_TXPKTS65TO127OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxPkts128to255Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxPkts128to255Octets_IMP :: PAGE_28_TxPkts128to255Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxPkts128to255Octets_IMP_PAGE_28_TxPkts128to255Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXPKTS128TO255OCTETS_IMP,x)
#define Rd_switch_PAGE_28_TxPkts128to255Octets_IMP_PAGE_28_TxPkts128to255Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXPKTS128TO255OCTETS_IMP)
#define SWITCH_PAGE_28_TXPKTS128TO255OCTETS_IMP_PAGE_28_TXPKTS128TO255OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXPKTS128TO255OCTETS_IMP_PAGE_28_TXPKTS128TO255OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXPKTS128TO255OCTETS_IMP_PAGE_28_TXPKTS128TO255OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXPKTS128TO255OCTETS_IMP_PAGE_28_TXPKTS128TO255OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxPkts256to511Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxPkts256to511Octets_IMP :: PAGE_28_TxPkts256to511Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxPkts256to511Octets_IMP_PAGE_28_TxPkts256to511Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXPKTS256TO511OCTETS_IMP,x)
#define Rd_switch_PAGE_28_TxPkts256to511Octets_IMP_PAGE_28_TxPkts256to511Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXPKTS256TO511OCTETS_IMP)
#define SWITCH_PAGE_28_TXPKTS256TO511OCTETS_IMP_PAGE_28_TXPKTS256TO511OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXPKTS256TO511OCTETS_IMP_PAGE_28_TXPKTS256TO511OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXPKTS256TO511OCTETS_IMP_PAGE_28_TXPKTS256TO511OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXPKTS256TO511OCTETS_IMP_PAGE_28_TXPKTS256TO511OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxPkts512to1023Octets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxPkts512to1023Octets_IMP :: PAGE_28_TxPkts512to1023Octets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxPkts512to1023Octets_IMP_PAGE_28_TxPkts512to1023Octets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXPKTS512TO1023OCTETS_IMP,x)
#define Rd_switch_PAGE_28_TxPkts512to1023Octets_IMP_PAGE_28_TxPkts512to1023Octets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXPKTS512TO1023OCTETS_IMP)
#define SWITCH_PAGE_28_TXPKTS512TO1023OCTETS_IMP_PAGE_28_TXPKTS512TO1023OCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXPKTS512TO1023OCTETS_IMP_PAGE_28_TXPKTS512TO1023OCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXPKTS512TO1023OCTETS_IMP_PAGE_28_TXPKTS512TO1023OCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXPKTS512TO1023OCTETS_IMP_PAGE_28_TXPKTS512TO1023OCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_28_TxPkts1024toMaxPktOctets_IMP
 ***************************************************************************/
/* switch :: PAGE_28_TxPkts1024toMaxPktOctets_IMP :: PAGE_28_TxPkts1024toMaxPktOctets_IMP_COUNT [31:00] */
#define Wr_switch_PAGE_28_TxPkts1024toMaxPktOctets_IMP_PAGE_28_TxPkts1024toMaxPktOctets_IMP_COUNT(x) WriteReg(SWITCH_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP,x)
#define Rd_switch_PAGE_28_TxPkts1024toMaxPktOctets_IMP_PAGE_28_TxPkts1024toMaxPktOctets_IMP_COUNT(x) ReadReg(SWITCH_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP)
#define SWITCH_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP_COUNT_ALIGN 0
#define SWITCH_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP_COUNT_BITS 32
#define SWITCH_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP_PAGE_28_TXPKTS1024TOMAXPKTOCTETS_IMP_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_QOS_GLOBAL_CTRL
 ***************************************************************************/
/* switch :: PAGE_30_QOS_GLOBAL_CTRL :: PAGE_30_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE [07:07] */
#define Wr_switch_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE(x) WriteRegBits(SWITCH_PAGE_30_QOS_GLOBAL_CTRL,0x80,7,x)
#define Rd_switch_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE(x) ReadRegBits(SWITCH_PAGE_30_QOS_GLOBAL_CTRL,0x80,7)
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_MASK 0x80
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_ALIGN 0
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_BITS 1
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P8_AGGREGATION_MODE_SHIFT 7

/* switch :: PAGE_30_QOS_GLOBAL_CTRL :: PAGE_30_QOS_GLOBAL_CTRL_RESERVED_1 [06:05] */
#define Wr_switch_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_30_QOS_GLOBAL_CTRL,0x60,5,x)
#define Rd_switch_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_30_QOS_GLOBAL_CTRL,0x60,5)
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_1_MASK 0x60
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_1_BITS 2
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_1_SHIFT 5

/* switch :: PAGE_30_QOS_GLOBAL_CTRL :: PAGE_30_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE [04:04] */
#define Wr_switch_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE(x) WriteRegBits(SWITCH_PAGE_30_QOS_GLOBAL_CTRL,0x10,4,x)
#define Rd_switch_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE(x) ReadRegBits(SWITCH_PAGE_30_QOS_GLOBAL_CTRL,0x10,4)
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_MASK 0x10
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_ALIGN 0
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_BITS 1
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_P5_AGGREGATION_MODE_SHIFT 4

/* switch :: PAGE_30_QOS_GLOBAL_CTRL :: PAGE_30_QOS_GLOBAL_CTRL_RESERVED_0 [03:00] */
#define Wr_switch_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_30_QOS_GLOBAL_CTRL,0xf,0,x)
#define Rd_switch_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_30_QOS_GLOBAL_CTRL,0xf,0)
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_0_MASK 0x0f
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_0_BITS 4
#define SWITCH_PAGE_30_QOS_GLOBAL_CTRL_PAGE_30_QOS_GLOBAL_CTRL_RESERVED_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_QOS_1P_EN
 ***************************************************************************/
/* switch :: PAGE_30_QOS_1P_EN :: PAGE_30_QOS_1P_EN_RESERVED [15:09] */
#define Wr_switch_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_30_QOS_1P_EN,0xfe00,9,x)
#define Rd_switch_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_30_QOS_1P_EN,0xfe00,9)
#define SWITCH_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_RESERVED_MASK   0xfe00
#define SWITCH_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_RESERVED_ALIGN  0
#define SWITCH_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_RESERVED_BITS   7
#define SWITCH_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_RESERVED_SHIFT  9

/* switch :: PAGE_30_QOS_1P_EN :: PAGE_30_QOS_1P_EN_QOS_1P_EN [08:00] */
#define Wr_switch_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_QOS_1P_EN(x) WriteRegBits16(SWITCH_PAGE_30_QOS_1P_EN,0x1ff,0,x)
#define Rd_switch_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_QOS_1P_EN(x) ReadRegBits16(SWITCH_PAGE_30_QOS_1P_EN,0x1ff,0)
#define SWITCH_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_QOS_1P_EN_MASK  0x01ff
#define SWITCH_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_QOS_1P_EN_ALIGN 0
#define SWITCH_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_QOS_1P_EN_BITS  9
#define SWITCH_PAGE_30_QOS_1P_EN_PAGE_30_QOS_1P_EN_QOS_1P_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_QOS_EN_DIFFSERV
 ***************************************************************************/
/* switch :: PAGE_30_QOS_EN_DIFFSERV :: PAGE_30_QOS_EN_DIFFSERV_RESERVED [15:09] */
#define Wr_switch_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_RESERVED(x) WriteRegBits16(SWITCH_PAGE_30_QOS_EN_DIFFSERV,0xfe00,9,x)
#define Rd_switch_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_RESERVED(x) ReadRegBits16(SWITCH_PAGE_30_QOS_EN_DIFFSERV,0xfe00,9)
#define SWITCH_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_RESERVED_ALIGN 0
#define SWITCH_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_RESERVED_BITS 7
#define SWITCH_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_RESERVED_SHIFT 9

/* switch :: PAGE_30_QOS_EN_DIFFSERV :: PAGE_30_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV [08:00] */
#define Wr_switch_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV(x) WriteRegBits16(SWITCH_PAGE_30_QOS_EN_DIFFSERV,0x1ff,0,x)
#define Rd_switch_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV(x) ReadRegBits16(SWITCH_PAGE_30_QOS_EN_DIFFSERV,0x1ff,0)
#define SWITCH_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_MASK 0x01ff
#define SWITCH_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_ALIGN 0
#define SWITCH_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_BITS 9
#define SWITCH_PAGE_30_QOS_EN_DIFFSERV_PAGE_30_QOS_EN_DIFFSERV_QOS_EN_DIFFSERV_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI0_port0
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI0_port0 :: PAGE_30_PN_PCP2TC_DEI0_RESERVED_0 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_RESERVED_0_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_RESERVED_0_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_RESERVED_0_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port0 :: PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_0 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_0_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_0_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port0 :: PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_0 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_0_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_0_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port0 :: PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_0 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_0_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_0_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port0 :: PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_0 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_0_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_0_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port0 :: PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_0 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_0_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_0_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port0 :: PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_0 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_0_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_0_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port0 :: PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_0 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_0_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_0_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port0 :: PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_0 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port0_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_0_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT0_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI0_port1
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI0_port1 :: PAGE_30_PN_PCP2TC_DEI0_RESERVED_1 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_RESERVED_1_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_RESERVED_1_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_RESERVED_1_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port1 :: PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_1 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_1_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_1_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port1 :: PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_1 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_1_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_1_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port1 :: PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_1 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_1_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_1_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port1 :: PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_1 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_1_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_1_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port1 :: PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_1 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_1_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_1_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port1 :: PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_1 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_1_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_1_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port1 :: PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_1 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_1_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_1_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port1 :: PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_1 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port1_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_1_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT1_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI0_port2
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI0_port2 :: PAGE_30_PN_PCP2TC_DEI0_RESERVED_2 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_RESERVED_2_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_RESERVED_2_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_RESERVED_2_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port2 :: PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_2 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_2_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_2_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port2 :: PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_2 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_2_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_2_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port2 :: PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_2 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_2_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_2_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port2 :: PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_2 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_2_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_2_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port2 :: PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_2 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_2_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_2_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port2 :: PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_2 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_2_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_2_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port2 :: PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_2 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_2_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_2_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port2 :: PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_2 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port2_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_2_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT2_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI0_port3
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI0_port3 :: PAGE_30_PN_PCP2TC_DEI0_RESERVED_3 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_RESERVED_3_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_RESERVED_3_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_RESERVED_3_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port3 :: PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_3 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_3_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_3_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port3 :: PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_3 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_3_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_3_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port3 :: PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_3 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_3_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_3_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port3 :: PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_3 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_3_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_3_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port3 :: PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_3 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_3_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_3_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port3 :: PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_3 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_3_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_3_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port3 :: PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_3 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_3_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_3_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port3 :: PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_3 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port3_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_3_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT3_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI0_port4
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI0_port4 :: PAGE_30_PN_PCP2TC_DEI0_RESERVED_4 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_RESERVED_4_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_RESERVED_4_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_RESERVED_4_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port4 :: PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_4 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_4_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_4_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port4 :: PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_4 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_4_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_4_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port4 :: PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_4 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_4_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_4_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port4 :: PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_4 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_4_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_4_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port4 :: PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_4 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_4_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_4_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port4 :: PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_4 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_4_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_4_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port4 :: PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_4 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_4_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_4_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port4 :: PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_4 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port4_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_4_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT4_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI0_port5
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI0_port5 :: PAGE_30_PN_PCP2TC_DEI0_RESERVED_5 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_RESERVED_5_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_RESERVED_5_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_RESERVED_5_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port5 :: PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_5 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_5_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_5_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port5 :: PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_5 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_5_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_5_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port5 :: PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_5 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_5_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_5_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port5 :: PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_5 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_5_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_5_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port5 :: PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_5 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_5_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_5_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port5 :: PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_5 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_5_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_5_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port5 :: PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_5 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_5_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_5_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port5 :: PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_5 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port5_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_5_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT5_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI0_port6
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI0_port6 :: PAGE_30_PN_PCP2TC_DEI0_RESERVED_6 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_RESERVED_6_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_RESERVED_6_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_RESERVED_6_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port6 :: PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_6 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_6_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG111_PRI_MAP_6_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port6 :: PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_6 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_6_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG110_PRI_MAP_6_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port6 :: PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_6 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_6_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG101_PRI_MAP_6_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port6 :: PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_6 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_6_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG100_PRI_MAP_6_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port6 :: PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_6 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_6_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG011_PRI_MAP_6_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port6 :: PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_6 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_6_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG010_PRI_MAP_6_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port6 :: PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_6 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_6_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG001_PRI_MAP_6_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI0_port6 :: PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_6 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI0_port6_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_6_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI0_PORT6_PAGE_30_PN_PCP2TC_DEI0_TAG000_PRI_MAP_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_P7_PCP2TC_DEI0
 ***************************************************************************/
/* switch :: PAGE_30_P7_PCP2TC_DEI0 :: PAGE_30_P7_PCP2TC_DEI0_RESERVED [31:24] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_RESERVED(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0xff000000,24,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_RESERVED(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0xff000000,24)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_RESERVED_MASK 0xff000000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_RESERVED_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_RESERVED_BITS 8
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_RESERVED_SHIFT 24

/* switch :: PAGE_30_P7_PCP2TC_DEI0 :: PAGE_30_P7_PCP2TC_DEI0_TAG111_PRI_MAP [23:21] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG111_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0xe00000,21,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG111_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0xe00000,21)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG111_PRI_MAP_MASK 0x00e00000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG111_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG111_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG111_PRI_MAP_SHIFT 21

/* switch :: PAGE_30_P7_PCP2TC_DEI0 :: PAGE_30_P7_PCP2TC_DEI0_TAG110_PRI_MAP [20:18] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG110_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x1c0000,18,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG110_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x1c0000,18)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG110_PRI_MAP_MASK 0x001c0000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG110_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG110_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG110_PRI_MAP_SHIFT 18

/* switch :: PAGE_30_P7_PCP2TC_DEI0 :: PAGE_30_P7_PCP2TC_DEI0_TAG101_PRI_MAP [17:15] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG101_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x38000,15,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG101_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x38000,15)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG101_PRI_MAP_MASK 0x00038000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG101_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG101_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG101_PRI_MAP_SHIFT 15

/* switch :: PAGE_30_P7_PCP2TC_DEI0 :: PAGE_30_P7_PCP2TC_DEI0_TAG100_PRI_MAP [14:12] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG100_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x7000,12,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG100_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x7000,12)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG100_PRI_MAP_MASK 0x00007000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG100_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG100_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG100_PRI_MAP_SHIFT 12

/* switch :: PAGE_30_P7_PCP2TC_DEI0 :: PAGE_30_P7_PCP2TC_DEI0_TAG011_PRI_MAP [11:09] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG011_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0xe00,9,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG011_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0xe00,9)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG011_PRI_MAP_MASK 0x00000e00
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG011_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG011_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG011_PRI_MAP_SHIFT 9

/* switch :: PAGE_30_P7_PCP2TC_DEI0 :: PAGE_30_P7_PCP2TC_DEI0_TAG010_PRI_MAP [08:06] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG010_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x1c0,6,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG010_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x1c0,6)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG010_PRI_MAP_MASK 0x000001c0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG010_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG010_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG010_PRI_MAP_SHIFT 6

/* switch :: PAGE_30_P7_PCP2TC_DEI0 :: PAGE_30_P7_PCP2TC_DEI0_TAG001_PRI_MAP [05:03] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG001_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x38,3,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG001_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x38,3)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG001_PRI_MAP_MASK 0x00000038
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG001_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG001_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG001_PRI_MAP_SHIFT 3

/* switch :: PAGE_30_P7_PCP2TC_DEI0 :: PAGE_30_P7_PCP2TC_DEI0_TAG000_PRI_MAP [02:00] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG000_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x7,0,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG000_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI0,0x7,0)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG000_PRI_MAP_MASK 0x00000007
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG000_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG000_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI0_PAGE_30_P7_PCP2TC_DEI0_TAG000_PRI_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_IMP_PCP2TC_DEI0
 ***************************************************************************/
/* switch :: PAGE_30_IMP_PCP2TC_DEI0 :: PAGE_30_IMP_PCP2TC_DEI0_RESERVED [31:24] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_RESERVED(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0xff000000,24,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_RESERVED(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0xff000000,24)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_RESERVED_MASK 0xff000000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_RESERVED_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_RESERVED_BITS 8
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_RESERVED_SHIFT 24

/* switch :: PAGE_30_IMP_PCP2TC_DEI0 :: PAGE_30_IMP_PCP2TC_DEI0_TAG111_PRI_MAP [23:21] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG111_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0xe00000,21,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG111_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0xe00000,21)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_MASK 0x00e00000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG111_PRI_MAP_SHIFT 21

/* switch :: PAGE_30_IMP_PCP2TC_DEI0 :: PAGE_30_IMP_PCP2TC_DEI0_TAG110_PRI_MAP [20:18] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG110_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x1c0000,18,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG110_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x1c0000,18)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_MASK 0x001c0000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG110_PRI_MAP_SHIFT 18

/* switch :: PAGE_30_IMP_PCP2TC_DEI0 :: PAGE_30_IMP_PCP2TC_DEI0_TAG101_PRI_MAP [17:15] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG101_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x38000,15,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG101_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x38000,15)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_MASK 0x00038000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG101_PRI_MAP_SHIFT 15

/* switch :: PAGE_30_IMP_PCP2TC_DEI0 :: PAGE_30_IMP_PCP2TC_DEI0_TAG100_PRI_MAP [14:12] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG100_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x7000,12,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG100_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x7000,12)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_MASK 0x00007000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG100_PRI_MAP_SHIFT 12

/* switch :: PAGE_30_IMP_PCP2TC_DEI0 :: PAGE_30_IMP_PCP2TC_DEI0_TAG011_PRI_MAP [11:09] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG011_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0xe00,9,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG011_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0xe00,9)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_MASK 0x00000e00
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG011_PRI_MAP_SHIFT 9

/* switch :: PAGE_30_IMP_PCP2TC_DEI0 :: PAGE_30_IMP_PCP2TC_DEI0_TAG010_PRI_MAP [08:06] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG010_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x1c0,6,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG010_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x1c0,6)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_MASK 0x000001c0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG010_PRI_MAP_SHIFT 6

/* switch :: PAGE_30_IMP_PCP2TC_DEI0 :: PAGE_30_IMP_PCP2TC_DEI0_TAG001_PRI_MAP [05:03] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG001_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x38,3,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG001_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x38,3)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_MASK 0x00000038
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG001_PRI_MAP_SHIFT 3

/* switch :: PAGE_30_IMP_PCP2TC_DEI0 :: PAGE_30_IMP_PCP2TC_DEI0_TAG000_PRI_MAP [02:00] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG000_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x7,0,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG000_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI0,0x7,0)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_MASK 0x00000007
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI0_PAGE_30_IMP_PCP2TC_DEI0_TAG000_PRI_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_QOS_DIFF_DSCP0
 ***************************************************************************/
/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: reserved0 [63:48] */
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_RESERVED0_MASK               0xffff000000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_RESERVED0_ALIGN              0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_RESERVED0_BITS               16
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_RESERVED0_SHIFT              48

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001111 [47:45] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001111(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0xe00000000000,45,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001111(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0xe00000000000,45)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001111_MASK 0x0000e00000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001111_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001111_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001111_SHIFT 45

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001110 [44:42] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001110(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x1c0000000000,42,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001110(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x1c0000000000,42)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001110_MASK 0x00001c0000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001110_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001110_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001110_SHIFT 42

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001101 [41:39] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001101(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x38000000000,39,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001101(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x38000000000,39)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001101_MASK 0x0000038000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001101_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001101_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001101_SHIFT 39

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001100 [38:36] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001100(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x7000000000,36,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001100(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x7000000000,36)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001100_MASK 0x0000007000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001100_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001100_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001100_SHIFT 36

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001011 [35:33] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001011(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0xe00000000,33,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001011(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0xe00000000,33)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001011_MASK 0x0000000e00000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001011_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001011_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001011_SHIFT 33

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001010 [32:30] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001010(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x1c0000000,30,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001010(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x1c0000000,30)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001010_MASK 0x00000001c0000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001010_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001010_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001010_SHIFT 30

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001001 [29:27] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001001(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x38000000,27,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001001(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x38000000,27)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001001_MASK 0x0000000038000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001001_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001001_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001001_SHIFT 27

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001000 [26:24] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001000(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x7000000,24,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001000(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x7000000,24)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001000_MASK 0x0000000007000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001000_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001000_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_001000_SHIFT 24

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000111 [23:21] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000111(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0xe00000,21,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000111(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0xe00000,21)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000111_MASK 0x0000000000e00000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000111_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000111_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000111_SHIFT 21

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000110 [20:18] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000110(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x1c0000,18,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000110(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x1c0000,18)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000110_MASK 0x00000000001c0000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000110_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000110_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000110_SHIFT 18

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000101 [17:15] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000101(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x38000,15,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000101(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x38000,15)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000101_MASK 0x0000000000038000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000101_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000101_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000101_SHIFT 15

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000100 [14:12] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000100(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x7000,12,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000100(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x7000,12)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000100_MASK 0x0000000000007000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000100_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000100_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000100_SHIFT 12

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000011 [11:09] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000011(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0xe00,9,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000011(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0xe00,9)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000011_MASK 0x0000000000000e00
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000011_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000011_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000011_SHIFT 9

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000010 [08:06] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000010(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x1c0,6,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000010(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x1c0,6)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000010_MASK 0x00000000000001c0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000010_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000010_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000010_SHIFT 6

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000001 [05:03] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000001(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x38,3,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000001(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x38,3)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000001_MASK 0x0000000000000038
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000001_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000001_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000001_SHIFT 3

/* switch :: PAGE_30_QOS_DIFF_DSCP0 :: PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000000 [02:00] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000000(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x7,0,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000000(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP0,0x7,0)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000000_MASK 0x0000000000000007
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000000_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000000_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP0_PAGE_30_QOS_DIFF_DSCP0_PRI_DSCP_000000_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_QOS_DIFF_DSCP1
 ***************************************************************************/
/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: reserved0 [63:48] */
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_RESERVED0_MASK               0xffff000000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_RESERVED0_ALIGN              0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_RESERVED0_BITS               16
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_RESERVED0_SHIFT              48

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011111 [47:45] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011111(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0xe00000000000,45,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011111(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0xe00000000000,45)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011111_MASK 0x0000e00000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011111_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011111_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011111_SHIFT 45

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011110 [44:42] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011110(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x1c0000000000,42,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011110(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x1c0000000000,42)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011110_MASK 0x00001c0000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011110_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011110_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011110_SHIFT 42

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011101 [41:39] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011101(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x38000000000,39,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011101(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x38000000000,39)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011101_MASK 0x0000038000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011101_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011101_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011101_SHIFT 39

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011100 [38:36] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011100(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x7000000000,36,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011100(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x7000000000,36)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011100_MASK 0x0000007000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011100_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011100_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011100_SHIFT 36

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011011 [35:33] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011011(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0xe00000000,33,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011011(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0xe00000000,33)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011011_MASK 0x0000000e00000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011011_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011011_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011011_SHIFT 33

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011010 [32:30] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011010(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x1c0000000,30,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011010(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x1c0000000,30)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011010_MASK 0x00000001c0000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011010_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011010_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011010_SHIFT 30

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011001 [29:27] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011001(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x38000000,27,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011001(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x38000000,27)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011001_MASK 0x0000000038000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011001_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011001_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011001_SHIFT 27

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011000 [26:24] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011000(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x7000000,24,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011000(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x7000000,24)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011000_MASK 0x0000000007000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011000_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011000_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_011000_SHIFT 24

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010111 [23:21] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010111(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0xe00000,21,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010111(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0xe00000,21)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010111_MASK 0x0000000000e00000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010111_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010111_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010111_SHIFT 21

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010110 [20:18] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010110(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x1c0000,18,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010110(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x1c0000,18)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010110_MASK 0x00000000001c0000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010110_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010110_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010110_SHIFT 18

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010101 [17:15] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010101(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x38000,15,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010101(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x38000,15)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010101_MASK 0x0000000000038000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010101_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010101_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010101_SHIFT 15

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010100 [14:12] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010100(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x7000,12,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010100(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x7000,12)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010100_MASK 0x0000000000007000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010100_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010100_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010100_SHIFT 12

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010011 [11:09] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010011(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0xe00,9,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010011(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0xe00,9)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010011_MASK 0x0000000000000e00
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010011_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010011_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010011_SHIFT 9

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010010 [08:06] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010010(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x1c0,6,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010010(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x1c0,6)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010010_MASK 0x00000000000001c0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010010_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010010_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010010_SHIFT 6

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010001 [05:03] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010001(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x38,3,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010001(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x38,3)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010001_MASK 0x0000000000000038
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010001_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010001_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010001_SHIFT 3

/* switch :: PAGE_30_QOS_DIFF_DSCP1 :: PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010000 [02:00] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010000(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x7,0,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010000(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP1,0x7,0)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010000_MASK 0x0000000000000007
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010000_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010000_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP1_PAGE_30_QOS_DIFF_DSCP1_PRI_DSCP_010000_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_QOS_DIFF_DSCP2
 ***************************************************************************/
/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: reserved0 [63:48] */
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_RESERVED0_MASK               0xffff000000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_RESERVED0_ALIGN              0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_RESERVED0_BITS               16
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_RESERVED0_SHIFT              48

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101111 [47:45] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101111(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0xe00000000000,45,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101111(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0xe00000000000,45)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101111_MASK 0x0000e00000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101111_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101111_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101111_SHIFT 45

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101110 [44:42] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101110(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x1c0000000000,42,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101110(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x1c0000000000,42)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101110_MASK 0x00001c0000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101110_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101110_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101110_SHIFT 42

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101101 [41:39] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101101(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x38000000000,39,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101101(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x38000000000,39)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101101_MASK 0x0000038000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101101_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101101_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101101_SHIFT 39

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101100 [38:36] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101100(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x7000000000,36,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101100(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x7000000000,36)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101100_MASK 0x0000007000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101100_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101100_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101100_SHIFT 36

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101011 [35:33] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101011(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0xe00000000,33,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101011(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0xe00000000,33)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101011_MASK 0x0000000e00000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101011_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101011_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101011_SHIFT 33

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101010 [32:30] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101010(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x1c0000000,30,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101010(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x1c0000000,30)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101010_MASK 0x00000001c0000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101010_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101010_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101010_SHIFT 30

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101001 [29:27] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101001(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x38000000,27,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101001(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x38000000,27)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101001_MASK 0x0000000038000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101001_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101001_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101001_SHIFT 27

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101000 [26:24] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101000(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x7000000,24,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101000(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x7000000,24)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101000_MASK 0x0000000007000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101000_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101000_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_101000_SHIFT 24

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100111 [23:21] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100111(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0xe00000,21,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100111(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0xe00000,21)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100111_MASK 0x0000000000e00000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100111_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100111_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100111_SHIFT 21

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100110 [20:18] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100110(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x1c0000,18,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100110(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x1c0000,18)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100110_MASK 0x00000000001c0000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100110_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100110_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100110_SHIFT 18

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100101 [17:15] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100101(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x38000,15,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100101(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x38000,15)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100101_MASK 0x0000000000038000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100101_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100101_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100101_SHIFT 15

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100100 [14:12] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100100(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x7000,12,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100100(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x7000,12)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100100_MASK 0x0000000000007000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100100_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100100_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100100_SHIFT 12

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100011 [11:09] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100011(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0xe00,9,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100011(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0xe00,9)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100011_MASK 0x0000000000000e00
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100011_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100011_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100011_SHIFT 9

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100010 [08:06] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100010(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x1c0,6,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100010(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x1c0,6)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100010_MASK 0x00000000000001c0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100010_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100010_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100010_SHIFT 6

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100001 [05:03] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100001(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x38,3,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100001(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x38,3)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100001_MASK 0x0000000000000038
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100001_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100001_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100001_SHIFT 3

/* switch :: PAGE_30_QOS_DIFF_DSCP2 :: PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100000 [02:00] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100000(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x7,0,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100000(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP2,0x7,0)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100000_MASK 0x0000000000000007
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100000_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100000_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP2_PAGE_30_QOS_DIFF_DSCP2_PRI_DSCP_100000_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_QOS_DIFF_DSCP3
 ***************************************************************************/
/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: reserved0 [63:48] */
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_RESERVED0_MASK               0xffff000000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_RESERVED0_ALIGN              0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_RESERVED0_BITS               16
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_RESERVED0_SHIFT              48

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111111 [47:45] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111111(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0xe00000000000,45,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111111(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0xe00000000000,45)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111111_MASK 0x0000e00000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111111_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111111_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111111_SHIFT 45

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111110 [44:42] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111110(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x1c0000000000,42,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111110(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x1c0000000000,42)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111110_MASK 0x00001c0000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111110_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111110_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111110_SHIFT 42

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111101 [41:39] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111101(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x38000000000,39,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111101(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x38000000000,39)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111101_MASK 0x0000038000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111101_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111101_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111101_SHIFT 39

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111100 [38:36] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111100(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x7000000000,36,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111100(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x7000000000,36)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111100_MASK 0x0000007000000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111100_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111100_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111100_SHIFT 36

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111011 [35:33] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111011(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0xe00000000,33,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111011(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0xe00000000,33)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111011_MASK 0x0000000e00000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111011_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111011_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111011_SHIFT 33

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111010 [32:30] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111010(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x1c0000000,30,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111010(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x1c0000000,30)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111010_MASK 0x00000001c0000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111010_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111010_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111010_SHIFT 30

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111001 [29:27] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111001(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x38000000,27,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111001(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x38000000,27)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111001_MASK 0x0000000038000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111001_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111001_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111001_SHIFT 27

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111000 [26:24] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111000(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x7000000,24,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111000(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x7000000,24)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111000_MASK 0x0000000007000000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111000_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111000_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_111000_SHIFT 24

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110111 [23:21] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110111(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0xe00000,21,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110111(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0xe00000,21)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110111_MASK 0x0000000000e00000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110111_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110111_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110111_SHIFT 21

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110110 [20:18] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110110(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x1c0000,18,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110110(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x1c0000,18)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110110_MASK 0x00000000001c0000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110110_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110110_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110110_SHIFT 18

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110101 [17:15] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110101(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x38000,15,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110101(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x38000,15)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110101_MASK 0x0000000000038000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110101_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110101_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110101_SHIFT 15

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110100 [14:12] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110100(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x7000,12,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110100(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x7000,12)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110100_MASK 0x0000000000007000
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110100_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110100_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110100_SHIFT 12

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110011 [11:09] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110011(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0xe00,9,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110011(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0xe00,9)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110011_MASK 0x0000000000000e00
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110011_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110011_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110011_SHIFT 9

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110010 [08:06] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110010(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x1c0,6,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110010(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x1c0,6)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110010_MASK 0x00000000000001c0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110010_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110010_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110010_SHIFT 6

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110001 [05:03] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110001(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x38,3,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110001(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x38,3)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110001_MASK 0x0000000000000038
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110001_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110001_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110001_SHIFT 3

/* switch :: PAGE_30_QOS_DIFF_DSCP3 :: PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110000 [02:00] */
#define Wr_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110000(x) WriteRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x7,0,x)
#define Rd_switch_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110000(x) ReadRegBits(SWITCH_PAGE_30_QOS_DIFF_DSCP3,0x7,0)
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110000_MASK 0x0000000000000007
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110000_ALIGN 0
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110000_BITS 3
#define SWITCH_PAGE_30_QOS_DIFF_DSCP3_PAGE_30_QOS_DIFF_DSCP3_PRI_DSCP_110000_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PID2TC
 ***************************************************************************/
/* switch :: PAGE_30_PID2TC :: PAGE_30_PID2TC_RESERVED [31:27] */
#define Wr_switch_PAGE_30_PID2TC_PAGE_30_PID2TC_RESERVED(x) WriteRegBits(SWITCH_PAGE_30_PID2TC,0xf8000000,27,x)
#define Rd_switch_PAGE_30_PID2TC_PAGE_30_PID2TC_RESERVED(x) ReadRegBits(SWITCH_PAGE_30_PID2TC,0xf8000000,27)
#define SWITCH_PAGE_30_PID2TC_PAGE_30_PID2TC_RESERVED_MASK         0xf8000000
#define SWITCH_PAGE_30_PID2TC_PAGE_30_PID2TC_RESERVED_ALIGN        0
#define SWITCH_PAGE_30_PID2TC_PAGE_30_PID2TC_RESERVED_BITS         5
#define SWITCH_PAGE_30_PID2TC_PAGE_30_PID2TC_RESERVED_SHIFT        27

/* switch :: PAGE_30_PID2TC :: PAGE_30_PID2TC_PID2TC [26:00] */
#define Wr_switch_PAGE_30_PID2TC_PAGE_30_PID2TC_PID2TC(x) WriteRegBits(SWITCH_PAGE_30_PID2TC,0x7ffffff,0,x)
#define Rd_switch_PAGE_30_PID2TC_PAGE_30_PID2TC_PID2TC(x) ReadRegBits(SWITCH_PAGE_30_PID2TC,0x7ffffff,0)
#define SWITCH_PAGE_30_PID2TC_PAGE_30_PID2TC_PID2TC_MASK           0x07ffffff
#define SWITCH_PAGE_30_PID2TC_PAGE_30_PID2TC_PID2TC_ALIGN          0
#define SWITCH_PAGE_30_PID2TC_PAGE_30_PID2TC_PID2TC_BITS           27
#define SWITCH_PAGE_30_PID2TC_PAGE_30_PID2TC_PID2TC_SHIFT          0


/****************************************************************************
 * switch :: PAGE_30_TC_SEL_TABLE_port0
 ***************************************************************************/
/* switch :: PAGE_30_TC_SEL_TABLE_port0 :: PAGE_30_TC_SEL_TABLE_TC_SEL_7_0 [15:14] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_7_0(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0xc000,14,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_7_0(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0xc000,14)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_7_0_MASK 0xc000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_7_0_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_7_0_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_7_0_SHIFT 14

/* switch :: PAGE_30_TC_SEL_TABLE_port0 :: PAGE_30_TC_SEL_TABLE_TC_SEL_6_0 [13:12] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_6_0(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0x3000,12,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_6_0(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0x3000,12)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_6_0_MASK 0x3000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_6_0_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_6_0_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_6_0_SHIFT 12

/* switch :: PAGE_30_TC_SEL_TABLE_port0 :: PAGE_30_TC_SEL_TABLE_TC_SEL_5_0 [11:10] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_5_0(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0xc00,10,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_5_0(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0xc00,10)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_5_0_MASK 0x0c00
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_5_0_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_5_0_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_5_0_SHIFT 10

/* switch :: PAGE_30_TC_SEL_TABLE_port0 :: PAGE_30_TC_SEL_TABLE_TC_SEL_4_0 [09:08] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_4_0(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0x300,8,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_4_0(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0x300,8)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_4_0_MASK 0x0300
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_4_0_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_4_0_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_4_0_SHIFT 8

/* switch :: PAGE_30_TC_SEL_TABLE_port0 :: PAGE_30_TC_SEL_TABLE_TC_SEL_3_0 [07:06] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_3_0(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0xc0,6,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_3_0(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0xc0,6)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_3_0_MASK 0x00c0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_3_0_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_3_0_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_3_0_SHIFT 6

/* switch :: PAGE_30_TC_SEL_TABLE_port0 :: PAGE_30_TC_SEL_TABLE_TC_SEL_2_0 [05:04] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_2_0(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0x30,4,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_2_0(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0x30,4)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_2_0_MASK 0x0030
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_2_0_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_2_0_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_2_0_SHIFT 4

/* switch :: PAGE_30_TC_SEL_TABLE_port0 :: PAGE_30_TC_SEL_TABLE_TC_SEL_1_0 [03:02] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_1_0(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0xc,2,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_1_0(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0xc,2)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_1_0_MASK 0x000c
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_1_0_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_1_0_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_1_0_SHIFT 2

/* switch :: PAGE_30_TC_SEL_TABLE_port0 :: PAGE_30_TC_SEL_TABLE_TC_SEL_0_0 [01:00] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_0_0(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0x3,0,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port0_PAGE_30_TC_SEL_TABLE_TC_SEL_0_0(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT0,0x3,0)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_0_0_MASK 0x0003
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_0_0_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_0_0_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT0_PAGE_30_TC_SEL_TABLE_TC_SEL_0_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_TC_SEL_TABLE_port1
 ***************************************************************************/
/* switch :: PAGE_30_TC_SEL_TABLE_port1 :: PAGE_30_TC_SEL_TABLE_TC_SEL_7_1 [15:14] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_7_1(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0xc000,14,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_7_1(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0xc000,14)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_7_1_MASK 0xc000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_7_1_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_7_1_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_7_1_SHIFT 14

/* switch :: PAGE_30_TC_SEL_TABLE_port1 :: PAGE_30_TC_SEL_TABLE_TC_SEL_6_1 [13:12] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_6_1(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0x3000,12,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_6_1(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0x3000,12)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_6_1_MASK 0x3000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_6_1_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_6_1_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_6_1_SHIFT 12

/* switch :: PAGE_30_TC_SEL_TABLE_port1 :: PAGE_30_TC_SEL_TABLE_TC_SEL_5_1 [11:10] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_5_1(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0xc00,10,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_5_1(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0xc00,10)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_5_1_MASK 0x0c00
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_5_1_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_5_1_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_5_1_SHIFT 10

/* switch :: PAGE_30_TC_SEL_TABLE_port1 :: PAGE_30_TC_SEL_TABLE_TC_SEL_4_1 [09:08] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_4_1(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0x300,8,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_4_1(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0x300,8)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_4_1_MASK 0x0300
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_4_1_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_4_1_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_4_1_SHIFT 8

/* switch :: PAGE_30_TC_SEL_TABLE_port1 :: PAGE_30_TC_SEL_TABLE_TC_SEL_3_1 [07:06] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_3_1(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0xc0,6,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_3_1(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0xc0,6)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_3_1_MASK 0x00c0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_3_1_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_3_1_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_3_1_SHIFT 6

/* switch :: PAGE_30_TC_SEL_TABLE_port1 :: PAGE_30_TC_SEL_TABLE_TC_SEL_2_1 [05:04] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_2_1(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0x30,4,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_2_1(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0x30,4)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_2_1_MASK 0x0030
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_2_1_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_2_1_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_2_1_SHIFT 4

/* switch :: PAGE_30_TC_SEL_TABLE_port1 :: PAGE_30_TC_SEL_TABLE_TC_SEL_1_1 [03:02] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_1_1(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0xc,2,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_1_1(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0xc,2)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_1_1_MASK 0x000c
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_1_1_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_1_1_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_1_1_SHIFT 2

/* switch :: PAGE_30_TC_SEL_TABLE_port1 :: PAGE_30_TC_SEL_TABLE_TC_SEL_0_1 [01:00] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_0_1(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0x3,0,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port1_PAGE_30_TC_SEL_TABLE_TC_SEL_0_1(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT1,0x3,0)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_0_1_MASK 0x0003
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_0_1_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_0_1_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT1_PAGE_30_TC_SEL_TABLE_TC_SEL_0_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_TC_SEL_TABLE_port2
 ***************************************************************************/
/* switch :: PAGE_30_TC_SEL_TABLE_port2 :: PAGE_30_TC_SEL_TABLE_TC_SEL_7_2 [15:14] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_7_2(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0xc000,14,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_7_2(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0xc000,14)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_7_2_MASK 0xc000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_7_2_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_7_2_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_7_2_SHIFT 14

/* switch :: PAGE_30_TC_SEL_TABLE_port2 :: PAGE_30_TC_SEL_TABLE_TC_SEL_6_2 [13:12] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_6_2(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0x3000,12,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_6_2(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0x3000,12)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_6_2_MASK 0x3000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_6_2_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_6_2_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_6_2_SHIFT 12

/* switch :: PAGE_30_TC_SEL_TABLE_port2 :: PAGE_30_TC_SEL_TABLE_TC_SEL_5_2 [11:10] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_5_2(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0xc00,10,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_5_2(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0xc00,10)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_5_2_MASK 0x0c00
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_5_2_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_5_2_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_5_2_SHIFT 10

/* switch :: PAGE_30_TC_SEL_TABLE_port2 :: PAGE_30_TC_SEL_TABLE_TC_SEL_4_2 [09:08] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_4_2(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0x300,8,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_4_2(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0x300,8)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_4_2_MASK 0x0300
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_4_2_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_4_2_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_4_2_SHIFT 8

/* switch :: PAGE_30_TC_SEL_TABLE_port2 :: PAGE_30_TC_SEL_TABLE_TC_SEL_3_2 [07:06] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_3_2(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0xc0,6,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_3_2(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0xc0,6)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_3_2_MASK 0x00c0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_3_2_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_3_2_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_3_2_SHIFT 6

/* switch :: PAGE_30_TC_SEL_TABLE_port2 :: PAGE_30_TC_SEL_TABLE_TC_SEL_2_2 [05:04] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_2_2(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0x30,4,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_2_2(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0x30,4)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_2_2_MASK 0x0030
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_2_2_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_2_2_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_2_2_SHIFT 4

/* switch :: PAGE_30_TC_SEL_TABLE_port2 :: PAGE_30_TC_SEL_TABLE_TC_SEL_1_2 [03:02] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_1_2(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0xc,2,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_1_2(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0xc,2)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_1_2_MASK 0x000c
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_1_2_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_1_2_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_1_2_SHIFT 2

/* switch :: PAGE_30_TC_SEL_TABLE_port2 :: PAGE_30_TC_SEL_TABLE_TC_SEL_0_2 [01:00] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_0_2(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0x3,0,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port2_PAGE_30_TC_SEL_TABLE_TC_SEL_0_2(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT2,0x3,0)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_0_2_MASK 0x0003
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_0_2_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_0_2_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT2_PAGE_30_TC_SEL_TABLE_TC_SEL_0_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_TC_SEL_TABLE_port3
 ***************************************************************************/
/* switch :: PAGE_30_TC_SEL_TABLE_port3 :: PAGE_30_TC_SEL_TABLE_TC_SEL_7_3 [15:14] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_7_3(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0xc000,14,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_7_3(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0xc000,14)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_7_3_MASK 0xc000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_7_3_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_7_3_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_7_3_SHIFT 14

/* switch :: PAGE_30_TC_SEL_TABLE_port3 :: PAGE_30_TC_SEL_TABLE_TC_SEL_6_3 [13:12] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_6_3(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0x3000,12,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_6_3(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0x3000,12)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_6_3_MASK 0x3000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_6_3_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_6_3_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_6_3_SHIFT 12

/* switch :: PAGE_30_TC_SEL_TABLE_port3 :: PAGE_30_TC_SEL_TABLE_TC_SEL_5_3 [11:10] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_5_3(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0xc00,10,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_5_3(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0xc00,10)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_5_3_MASK 0x0c00
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_5_3_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_5_3_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_5_3_SHIFT 10

/* switch :: PAGE_30_TC_SEL_TABLE_port3 :: PAGE_30_TC_SEL_TABLE_TC_SEL_4_3 [09:08] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_4_3(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0x300,8,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_4_3(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0x300,8)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_4_3_MASK 0x0300
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_4_3_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_4_3_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_4_3_SHIFT 8

/* switch :: PAGE_30_TC_SEL_TABLE_port3 :: PAGE_30_TC_SEL_TABLE_TC_SEL_3_3 [07:06] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_3_3(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0xc0,6,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_3_3(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0xc0,6)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_3_3_MASK 0x00c0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_3_3_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_3_3_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_3_3_SHIFT 6

/* switch :: PAGE_30_TC_SEL_TABLE_port3 :: PAGE_30_TC_SEL_TABLE_TC_SEL_2_3 [05:04] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_2_3(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0x30,4,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_2_3(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0x30,4)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_2_3_MASK 0x0030
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_2_3_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_2_3_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_2_3_SHIFT 4

/* switch :: PAGE_30_TC_SEL_TABLE_port3 :: PAGE_30_TC_SEL_TABLE_TC_SEL_1_3 [03:02] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_1_3(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0xc,2,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_1_3(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0xc,2)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_1_3_MASK 0x000c
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_1_3_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_1_3_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_1_3_SHIFT 2

/* switch :: PAGE_30_TC_SEL_TABLE_port3 :: PAGE_30_TC_SEL_TABLE_TC_SEL_0_3 [01:00] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_0_3(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0x3,0,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port3_PAGE_30_TC_SEL_TABLE_TC_SEL_0_3(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT3,0x3,0)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_0_3_MASK 0x0003
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_0_3_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_0_3_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT3_PAGE_30_TC_SEL_TABLE_TC_SEL_0_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_TC_SEL_TABLE_port4
 ***************************************************************************/
/* switch :: PAGE_30_TC_SEL_TABLE_port4 :: PAGE_30_TC_SEL_TABLE_TC_SEL_7_4 [15:14] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_7_4(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0xc000,14,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_7_4(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0xc000,14)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_7_4_MASK 0xc000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_7_4_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_7_4_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_7_4_SHIFT 14

/* switch :: PAGE_30_TC_SEL_TABLE_port4 :: PAGE_30_TC_SEL_TABLE_TC_SEL_6_4 [13:12] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_6_4(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0x3000,12,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_6_4(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0x3000,12)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_6_4_MASK 0x3000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_6_4_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_6_4_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_6_4_SHIFT 12

/* switch :: PAGE_30_TC_SEL_TABLE_port4 :: PAGE_30_TC_SEL_TABLE_TC_SEL_5_4 [11:10] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_5_4(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0xc00,10,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_5_4(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0xc00,10)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_5_4_MASK 0x0c00
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_5_4_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_5_4_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_5_4_SHIFT 10

/* switch :: PAGE_30_TC_SEL_TABLE_port4 :: PAGE_30_TC_SEL_TABLE_TC_SEL_4_4 [09:08] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_4_4(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0x300,8,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_4_4(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0x300,8)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_4_4_MASK 0x0300
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_4_4_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_4_4_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_4_4_SHIFT 8

/* switch :: PAGE_30_TC_SEL_TABLE_port4 :: PAGE_30_TC_SEL_TABLE_TC_SEL_3_4 [07:06] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_3_4(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0xc0,6,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_3_4(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0xc0,6)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_3_4_MASK 0x00c0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_3_4_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_3_4_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_3_4_SHIFT 6

/* switch :: PAGE_30_TC_SEL_TABLE_port4 :: PAGE_30_TC_SEL_TABLE_TC_SEL_2_4 [05:04] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_2_4(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0x30,4,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_2_4(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0x30,4)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_2_4_MASK 0x0030
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_2_4_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_2_4_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_2_4_SHIFT 4

/* switch :: PAGE_30_TC_SEL_TABLE_port4 :: PAGE_30_TC_SEL_TABLE_TC_SEL_1_4 [03:02] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_1_4(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0xc,2,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_1_4(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0xc,2)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_1_4_MASK 0x000c
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_1_4_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_1_4_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_1_4_SHIFT 2

/* switch :: PAGE_30_TC_SEL_TABLE_port4 :: PAGE_30_TC_SEL_TABLE_TC_SEL_0_4 [01:00] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_0_4(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0x3,0,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port4_PAGE_30_TC_SEL_TABLE_TC_SEL_0_4(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT4,0x3,0)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_0_4_MASK 0x0003
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_0_4_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_0_4_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT4_PAGE_30_TC_SEL_TABLE_TC_SEL_0_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_TC_SEL_TABLE_port5
 ***************************************************************************/
/* switch :: PAGE_30_TC_SEL_TABLE_port5 :: PAGE_30_TC_SEL_TABLE_TC_SEL_7_5 [15:14] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_7_5(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0xc000,14,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_7_5(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0xc000,14)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_7_5_MASK 0xc000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_7_5_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_7_5_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_7_5_SHIFT 14

/* switch :: PAGE_30_TC_SEL_TABLE_port5 :: PAGE_30_TC_SEL_TABLE_TC_SEL_6_5 [13:12] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_6_5(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0x3000,12,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_6_5(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0x3000,12)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_6_5_MASK 0x3000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_6_5_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_6_5_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_6_5_SHIFT 12

/* switch :: PAGE_30_TC_SEL_TABLE_port5 :: PAGE_30_TC_SEL_TABLE_TC_SEL_5_5 [11:10] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_5_5(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0xc00,10,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_5_5(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0xc00,10)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_5_5_MASK 0x0c00
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_5_5_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_5_5_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_5_5_SHIFT 10

/* switch :: PAGE_30_TC_SEL_TABLE_port5 :: PAGE_30_TC_SEL_TABLE_TC_SEL_4_5 [09:08] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_4_5(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0x300,8,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_4_5(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0x300,8)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_4_5_MASK 0x0300
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_4_5_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_4_5_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_4_5_SHIFT 8

/* switch :: PAGE_30_TC_SEL_TABLE_port5 :: PAGE_30_TC_SEL_TABLE_TC_SEL_3_5 [07:06] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_3_5(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0xc0,6,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_3_5(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0xc0,6)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_3_5_MASK 0x00c0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_3_5_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_3_5_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_3_5_SHIFT 6

/* switch :: PAGE_30_TC_SEL_TABLE_port5 :: PAGE_30_TC_SEL_TABLE_TC_SEL_2_5 [05:04] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_2_5(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0x30,4,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_2_5(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0x30,4)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_2_5_MASK 0x0030
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_2_5_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_2_5_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_2_5_SHIFT 4

/* switch :: PAGE_30_TC_SEL_TABLE_port5 :: PAGE_30_TC_SEL_TABLE_TC_SEL_1_5 [03:02] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_1_5(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0xc,2,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_1_5(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0xc,2)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_1_5_MASK 0x000c
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_1_5_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_1_5_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_1_5_SHIFT 2

/* switch :: PAGE_30_TC_SEL_TABLE_port5 :: PAGE_30_TC_SEL_TABLE_TC_SEL_0_5 [01:00] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_0_5(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0x3,0,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port5_PAGE_30_TC_SEL_TABLE_TC_SEL_0_5(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT5,0x3,0)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_0_5_MASK 0x0003
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_0_5_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_0_5_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT5_PAGE_30_TC_SEL_TABLE_TC_SEL_0_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_TC_SEL_TABLE_port6
 ***************************************************************************/
/* switch :: PAGE_30_TC_SEL_TABLE_port6 :: PAGE_30_TC_SEL_TABLE_TC_SEL_7_6 [15:14] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_7_6(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0xc000,14,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_7_6(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0xc000,14)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_7_6_MASK 0xc000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_7_6_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_7_6_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_7_6_SHIFT 14

/* switch :: PAGE_30_TC_SEL_TABLE_port6 :: PAGE_30_TC_SEL_TABLE_TC_SEL_6_6 [13:12] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_6_6(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0x3000,12,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_6_6(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0x3000,12)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_6_6_MASK 0x3000
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_6_6_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_6_6_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_6_6_SHIFT 12

/* switch :: PAGE_30_TC_SEL_TABLE_port6 :: PAGE_30_TC_SEL_TABLE_TC_SEL_5_6 [11:10] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_5_6(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0xc00,10,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_5_6(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0xc00,10)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_5_6_MASK 0x0c00
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_5_6_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_5_6_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_5_6_SHIFT 10

/* switch :: PAGE_30_TC_SEL_TABLE_port6 :: PAGE_30_TC_SEL_TABLE_TC_SEL_4_6 [09:08] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_4_6(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0x300,8,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_4_6(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0x300,8)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_4_6_MASK 0x0300
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_4_6_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_4_6_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_4_6_SHIFT 8

/* switch :: PAGE_30_TC_SEL_TABLE_port6 :: PAGE_30_TC_SEL_TABLE_TC_SEL_3_6 [07:06] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_3_6(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0xc0,6,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_3_6(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0xc0,6)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_3_6_MASK 0x00c0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_3_6_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_3_6_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_3_6_SHIFT 6

/* switch :: PAGE_30_TC_SEL_TABLE_port6 :: PAGE_30_TC_SEL_TABLE_TC_SEL_2_6 [05:04] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_2_6(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0x30,4,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_2_6(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0x30,4)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_2_6_MASK 0x0030
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_2_6_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_2_6_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_2_6_SHIFT 4

/* switch :: PAGE_30_TC_SEL_TABLE_port6 :: PAGE_30_TC_SEL_TABLE_TC_SEL_1_6 [03:02] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_1_6(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0xc,2,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_1_6(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0xc,2)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_1_6_MASK 0x000c
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_1_6_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_1_6_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_1_6_SHIFT 2

/* switch :: PAGE_30_TC_SEL_TABLE_port6 :: PAGE_30_TC_SEL_TABLE_TC_SEL_0_6 [01:00] */
#define Wr_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_0_6(x) WriteRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0x3,0,x)
#define Rd_switch_PAGE_30_TC_SEL_TABLE_port6_PAGE_30_TC_SEL_TABLE_TC_SEL_0_6(x) ReadRegBits16(SWITCH_PAGE_30_TC_SEL_TABLE_PORT6,0x3,0)
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_0_6_MASK 0x0003
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_0_6_ALIGN 0
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_0_6_BITS 2
#define SWITCH_PAGE_30_TC_SEL_TABLE_PORT6_PAGE_30_TC_SEL_TABLE_TC_SEL_0_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_P7_TC_SEL_TABLE
 ***************************************************************************/
/* switch :: PAGE_30_P7_TC_SEL_TABLE :: PAGE_30_P7_TC_SEL_TABLE_TC_SEL_7 [15:14] */
#define Wr_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_7(x) WriteRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0xc000,14,x)
#define Rd_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_7(x) ReadRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0xc000,14)
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_7_MASK 0xc000
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_7_ALIGN 0
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_7_BITS 2
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_7_SHIFT 14

/* switch :: PAGE_30_P7_TC_SEL_TABLE :: PAGE_30_P7_TC_SEL_TABLE_TC_SEL_6 [13:12] */
#define Wr_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_6(x) WriteRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0x3000,12,x)
#define Rd_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_6(x) ReadRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0x3000,12)
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_6_MASK 0x3000
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_6_ALIGN 0
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_6_BITS 2
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_6_SHIFT 12

/* switch :: PAGE_30_P7_TC_SEL_TABLE :: PAGE_30_P7_TC_SEL_TABLE_TC_SEL_5 [11:10] */
#define Wr_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_5(x) WriteRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0xc00,10,x)
#define Rd_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_5(x) ReadRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0xc00,10)
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_5_MASK 0x0c00
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_5_ALIGN 0
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_5_BITS 2
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_5_SHIFT 10

/* switch :: PAGE_30_P7_TC_SEL_TABLE :: PAGE_30_P7_TC_SEL_TABLE_TC_SEL_4 [09:08] */
#define Wr_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_4(x) WriteRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0x300,8,x)
#define Rd_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_4(x) ReadRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0x300,8)
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_4_MASK 0x0300
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_4_ALIGN 0
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_4_BITS 2
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_4_SHIFT 8

/* switch :: PAGE_30_P7_TC_SEL_TABLE :: PAGE_30_P7_TC_SEL_TABLE_TC_SEL_3 [07:06] */
#define Wr_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_3(x) WriteRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0xc0,6,x)
#define Rd_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_3(x) ReadRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0xc0,6)
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_3_MASK 0x00c0
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_3_ALIGN 0
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_3_BITS 2
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_3_SHIFT 6

/* switch :: PAGE_30_P7_TC_SEL_TABLE :: PAGE_30_P7_TC_SEL_TABLE_TC_SEL_2 [05:04] */
#define Wr_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_2(x) WriteRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0x30,4,x)
#define Rd_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_2(x) ReadRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0x30,4)
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_2_MASK 0x0030
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_2_ALIGN 0
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_2_BITS 2
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_2_SHIFT 4

/* switch :: PAGE_30_P7_TC_SEL_TABLE :: PAGE_30_P7_TC_SEL_TABLE_TC_SEL_1 [03:02] */
#define Wr_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_1(x) WriteRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0xc,2,x)
#define Rd_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_1(x) ReadRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0xc,2)
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_1_MASK 0x000c
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_1_ALIGN 0
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_1_BITS 2
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_1_SHIFT 2

/* switch :: PAGE_30_P7_TC_SEL_TABLE :: PAGE_30_P7_TC_SEL_TABLE_TC_SEL_0 [01:00] */
#define Wr_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_0(x) WriteRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0x3,0,x)
#define Rd_switch_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_0(x) ReadRegBits16(SWITCH_PAGE_30_P7_TC_SEL_TABLE,0x3,0)
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_0_MASK 0x0003
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_0_ALIGN 0
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_0_BITS 2
#define SWITCH_PAGE_30_P7_TC_SEL_TABLE_PAGE_30_P7_TC_SEL_TABLE_TC_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_IMP_TC_SEL_TABLE
 ***************************************************************************/
/* switch :: PAGE_30_IMP_TC_SEL_TABLE :: PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_7 [15:14] */
#define Wr_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_7(x) WriteRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0xc000,14,x)
#define Rd_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_7(x) ReadRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0xc000,14)
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_7_MASK 0xc000
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_7_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_7_BITS 2
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_7_SHIFT 14

/* switch :: PAGE_30_IMP_TC_SEL_TABLE :: PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_6 [13:12] */
#define Wr_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_6(x) WriteRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0x3000,12,x)
#define Rd_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_6(x) ReadRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0x3000,12)
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_6_MASK 0x3000
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_6_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_6_BITS 2
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_6_SHIFT 12

/* switch :: PAGE_30_IMP_TC_SEL_TABLE :: PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_5 [11:10] */
#define Wr_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_5(x) WriteRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0xc00,10,x)
#define Rd_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_5(x) ReadRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0xc00,10)
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_5_MASK 0x0c00
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_5_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_5_BITS 2
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_5_SHIFT 10

/* switch :: PAGE_30_IMP_TC_SEL_TABLE :: PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_4 [09:08] */
#define Wr_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_4(x) WriteRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0x300,8,x)
#define Rd_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_4(x) ReadRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0x300,8)
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_4_MASK 0x0300
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_4_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_4_BITS 2
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_4_SHIFT 8

/* switch :: PAGE_30_IMP_TC_SEL_TABLE :: PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_3 [07:06] */
#define Wr_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_3(x) WriteRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0xc0,6,x)
#define Rd_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_3(x) ReadRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0xc0,6)
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_3_MASK 0x00c0
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_3_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_3_BITS 2
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_3_SHIFT 6

/* switch :: PAGE_30_IMP_TC_SEL_TABLE :: PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_2 [05:04] */
#define Wr_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_2(x) WriteRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0x30,4,x)
#define Rd_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_2(x) ReadRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0x30,4)
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_2_MASK 0x0030
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_2_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_2_BITS 2
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_2_SHIFT 4

/* switch :: PAGE_30_IMP_TC_SEL_TABLE :: PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_1 [03:02] */
#define Wr_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_1(x) WriteRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0xc,2,x)
#define Rd_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_1(x) ReadRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0xc,2)
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_1_MASK 0x000c
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_1_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_1_BITS 2
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_1_SHIFT 2

/* switch :: PAGE_30_IMP_TC_SEL_TABLE :: PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_0 [01:00] */
#define Wr_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_0(x) WriteRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0x3,0,x)
#define Rd_switch_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_0(x) ReadRegBits16(SWITCH_PAGE_30_IMP_TC_SEL_TABLE,0x3,0)
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_0_MASK 0x0003
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_0_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_0_BITS 2
#define SWITCH_PAGE_30_IMP_TC_SEL_TABLE_PAGE_30_IMP_TC_SEL_TABLE_TC_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_CPU2COS_MAP
 ***************************************************************************/
/* switch :: PAGE_30_CPU2COS_MAP :: PAGE_30_CPU2COS_MAP_RESERVED [31:18] */
#define Wr_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_RESERVED(x) WriteRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0xfffc0000,18,x)
#define Rd_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_RESERVED(x) ReadRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0xfffc0000,18)
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_RESERVED_BITS 14
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_RESERVED_SHIFT 18

/* switch :: PAGE_30_CPU2COS_MAP :: PAGE_30_CPU2COS_MAP_EXCPT_PRCS [17:15] */
#define Wr_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_EXCPT_PRCS(x) WriteRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x38000,15,x)
#define Rd_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_EXCPT_PRCS(x) ReadRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x38000,15)
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_EXCPT_PRCS_MASK 0x00038000
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_EXCPT_PRCS_ALIGN 0
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_EXCPT_PRCS_BITS 3
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_EXCPT_PRCS_SHIFT 15

/* switch :: PAGE_30_CPU2COS_MAP :: PAGE_30_CPU2COS_MAP_PRTC_SNOOP [14:12] */
#define Wr_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_SNOOP(x) WriteRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x7000,12,x)
#define Rd_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_SNOOP(x) ReadRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x7000,12)
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_SNOOP_MASK 0x00007000
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_SNOOP_ALIGN 0
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_SNOOP_BITS 3
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_SNOOP_SHIFT 12

/* switch :: PAGE_30_CPU2COS_MAP :: PAGE_30_CPU2COS_MAP_PRTC_TRMNT [11:09] */
#define Wr_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_TRMNT(x) WriteRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0xe00,9,x)
#define Rd_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_TRMNT(x) ReadRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0xe00,9)
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_TRMNT_MASK 0x00000e00
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_TRMNT_ALIGN 0
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_TRMNT_BITS 3
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_PRTC_TRMNT_SHIFT 9

/* switch :: PAGE_30_CPU2COS_MAP :: PAGE_30_CPU2COS_MAP_SW_FLD [08:06] */
#define Wr_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SW_FLD(x) WriteRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x1c0,6,x)
#define Rd_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SW_FLD(x) ReadRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x1c0,6)
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SW_FLD_MASK 0x000001c0
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SW_FLD_ALIGN 0
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SW_FLD_BITS 3
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SW_FLD_SHIFT 6

/* switch :: PAGE_30_CPU2COS_MAP :: PAGE_30_CPU2COS_MAP_SA_LRN [05:03] */
#define Wr_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SA_LRN(x) WriteRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x38,3,x)
#define Rd_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SA_LRN(x) ReadRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x38,3)
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SA_LRN_MASK 0x00000038
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SA_LRN_ALIGN 0
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SA_LRN_BITS 3
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_SA_LRN_SHIFT 3

/* switch :: PAGE_30_CPU2COS_MAP :: PAGE_30_CPU2COS_MAP_MIRROR [02:00] */
#define Wr_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_MIRROR(x) WriteRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x7,0,x)
#define Rd_switch_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_MIRROR(x) ReadRegBits(SWITCH_PAGE_30_CPU2COS_MAP,0x7,0)
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_MIRROR_MASK 0x00000007
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_MIRROR_ALIGN 0
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_MIRROR_BITS 3
#define SWITCH_PAGE_30_CPU2COS_MAP_PAGE_30_CPU2COS_MAP_MIRROR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_TC2COS_MAP_port0
 ***************************************************************************/
/* switch :: PAGE_30_PN_TC2COS_MAP_port0 :: PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_0 [31:24] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_0(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_0(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0xff000000,24)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_0_MASK 0xff000000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_0_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_0_BITS 8
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_0_SHIFT 24

/* switch :: PAGE_30_PN_TC2COS_MAP_port0 :: PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_0 [23:21] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_0(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_0(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0xe00000,21)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_0_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_0_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_0_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_0_SHIFT 21

/* switch :: PAGE_30_PN_TC2COS_MAP_port0 :: PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_0 [20:18] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_0(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_0(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x1c0000,18)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_0_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_0_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_0_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_0_SHIFT 18

/* switch :: PAGE_30_PN_TC2COS_MAP_port0 :: PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_0 [17:15] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_0(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_0(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x38000,15)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_0_MASK 0x00038000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_0_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_0_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_0_SHIFT 15

/* switch :: PAGE_30_PN_TC2COS_MAP_port0 :: PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_0 [14:12] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_0(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_0(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x7000,12)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_0_MASK 0x00007000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_0_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_0_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_0_SHIFT 12

/* switch :: PAGE_30_PN_TC2COS_MAP_port0 :: PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_0 [11:09] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_0(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_0(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0xe00,9)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_0_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_0_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_0_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_0_SHIFT 9

/* switch :: PAGE_30_PN_TC2COS_MAP_port0 :: PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_0 [08:06] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_0(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_0(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x1c0,6)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_0_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_0_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_0_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_0_SHIFT 6

/* switch :: PAGE_30_PN_TC2COS_MAP_port0 :: PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_0 [05:03] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_0(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x38,3,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_0(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x38,3)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_0_MASK 0x00000038
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_0_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_0_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_0_SHIFT 3

/* switch :: PAGE_30_PN_TC2COS_MAP_port0 :: PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_0 [02:00] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_0(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x7,0,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port0_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_0(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0,0x7,0)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_0_MASK 0x00000007
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_0_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_0_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT0_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_TC2COS_MAP_port1
 ***************************************************************************/
/* switch :: PAGE_30_PN_TC2COS_MAP_port1 :: PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_1 [31:24] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_1(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_1(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0xff000000,24)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_1_MASK 0xff000000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_1_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_1_BITS 8
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_1_SHIFT 24

/* switch :: PAGE_30_PN_TC2COS_MAP_port1 :: PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_1 [23:21] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_1(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_1(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0xe00000,21)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_1_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_1_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_1_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_1_SHIFT 21

/* switch :: PAGE_30_PN_TC2COS_MAP_port1 :: PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_1 [20:18] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_1(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_1(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x1c0000,18)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_1_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_1_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_1_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_1_SHIFT 18

/* switch :: PAGE_30_PN_TC2COS_MAP_port1 :: PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_1 [17:15] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_1(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_1(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x38000,15)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_1_MASK 0x00038000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_1_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_1_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_1_SHIFT 15

/* switch :: PAGE_30_PN_TC2COS_MAP_port1 :: PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_1 [14:12] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_1(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_1(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x7000,12)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_1_MASK 0x00007000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_1_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_1_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_1_SHIFT 12

/* switch :: PAGE_30_PN_TC2COS_MAP_port1 :: PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_1 [11:09] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_1(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_1(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0xe00,9)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_1_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_1_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_1_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_1_SHIFT 9

/* switch :: PAGE_30_PN_TC2COS_MAP_port1 :: PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_1 [08:06] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_1(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_1(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x1c0,6)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_1_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_1_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_1_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_1_SHIFT 6

/* switch :: PAGE_30_PN_TC2COS_MAP_port1 :: PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_1 [05:03] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_1(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x38,3,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_1(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x38,3)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_1_MASK 0x00000038
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_1_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_1_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_1_SHIFT 3

/* switch :: PAGE_30_PN_TC2COS_MAP_port1 :: PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_1 [02:00] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_1(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x7,0,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port1_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_1(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1,0x7,0)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_1_MASK 0x00000007
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_1_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_1_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT1_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_TC2COS_MAP_port2
 ***************************************************************************/
/* switch :: PAGE_30_PN_TC2COS_MAP_port2 :: PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_2 [31:24] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_2(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_2(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0xff000000,24)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_2_MASK 0xff000000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_2_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_2_BITS 8
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_2_SHIFT 24

/* switch :: PAGE_30_PN_TC2COS_MAP_port2 :: PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_2 [23:21] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_2(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_2(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0xe00000,21)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_2_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_2_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_2_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_2_SHIFT 21

/* switch :: PAGE_30_PN_TC2COS_MAP_port2 :: PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_2 [20:18] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_2(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_2(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x1c0000,18)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_2_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_2_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_2_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_2_SHIFT 18

/* switch :: PAGE_30_PN_TC2COS_MAP_port2 :: PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_2 [17:15] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_2(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_2(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x38000,15)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_2_MASK 0x00038000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_2_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_2_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_2_SHIFT 15

/* switch :: PAGE_30_PN_TC2COS_MAP_port2 :: PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_2 [14:12] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_2(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_2(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x7000,12)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_2_MASK 0x00007000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_2_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_2_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_2_SHIFT 12

/* switch :: PAGE_30_PN_TC2COS_MAP_port2 :: PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_2 [11:09] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_2(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_2(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0xe00,9)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_2_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_2_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_2_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_2_SHIFT 9

/* switch :: PAGE_30_PN_TC2COS_MAP_port2 :: PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_2 [08:06] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_2(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_2(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x1c0,6)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_2_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_2_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_2_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_2_SHIFT 6

/* switch :: PAGE_30_PN_TC2COS_MAP_port2 :: PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_2 [05:03] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_2(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x38,3,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_2(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x38,3)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_2_MASK 0x00000038
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_2_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_2_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_2_SHIFT 3

/* switch :: PAGE_30_PN_TC2COS_MAP_port2 :: PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_2 [02:00] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_2(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x7,0,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port2_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_2(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2,0x7,0)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_2_MASK 0x00000007
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_2_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_2_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT2_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_TC2COS_MAP_port3
 ***************************************************************************/
/* switch :: PAGE_30_PN_TC2COS_MAP_port3 :: PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_3 [31:24] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_3(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_3(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0xff000000,24)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_3_MASK 0xff000000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_3_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_3_BITS 8
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_3_SHIFT 24

/* switch :: PAGE_30_PN_TC2COS_MAP_port3 :: PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_3 [23:21] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_3(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_3(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0xe00000,21)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_3_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_3_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_3_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_3_SHIFT 21

/* switch :: PAGE_30_PN_TC2COS_MAP_port3 :: PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_3 [20:18] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_3(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_3(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x1c0000,18)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_3_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_3_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_3_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_3_SHIFT 18

/* switch :: PAGE_30_PN_TC2COS_MAP_port3 :: PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_3 [17:15] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_3(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_3(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x38000,15)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_3_MASK 0x00038000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_3_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_3_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_3_SHIFT 15

/* switch :: PAGE_30_PN_TC2COS_MAP_port3 :: PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_3 [14:12] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_3(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_3(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x7000,12)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_3_MASK 0x00007000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_3_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_3_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_3_SHIFT 12

/* switch :: PAGE_30_PN_TC2COS_MAP_port3 :: PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_3 [11:09] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_3(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_3(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0xe00,9)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_3_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_3_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_3_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_3_SHIFT 9

/* switch :: PAGE_30_PN_TC2COS_MAP_port3 :: PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_3 [08:06] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_3(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_3(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x1c0,6)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_3_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_3_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_3_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_3_SHIFT 6

/* switch :: PAGE_30_PN_TC2COS_MAP_port3 :: PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_3 [05:03] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_3(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x38,3,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_3(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x38,3)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_3_MASK 0x00000038
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_3_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_3_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_3_SHIFT 3

/* switch :: PAGE_30_PN_TC2COS_MAP_port3 :: PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_3 [02:00] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_3(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x7,0,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port3_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_3(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3,0x7,0)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_3_MASK 0x00000007
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_3_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_3_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT3_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_TC2COS_MAP_port4
 ***************************************************************************/
/* switch :: PAGE_30_PN_TC2COS_MAP_port4 :: PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_4 [31:24] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_4(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_4(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0xff000000,24)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_4_MASK 0xff000000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_4_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_4_BITS 8
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_4_SHIFT 24

/* switch :: PAGE_30_PN_TC2COS_MAP_port4 :: PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_4 [23:21] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_4(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_4(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0xe00000,21)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_4_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_4_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_4_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_4_SHIFT 21

/* switch :: PAGE_30_PN_TC2COS_MAP_port4 :: PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_4 [20:18] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_4(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_4(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x1c0000,18)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_4_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_4_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_4_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_4_SHIFT 18

/* switch :: PAGE_30_PN_TC2COS_MAP_port4 :: PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_4 [17:15] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_4(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_4(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x38000,15)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_4_MASK 0x00038000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_4_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_4_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_4_SHIFT 15

/* switch :: PAGE_30_PN_TC2COS_MAP_port4 :: PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_4 [14:12] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_4(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_4(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x7000,12)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_4_MASK 0x00007000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_4_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_4_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_4_SHIFT 12

/* switch :: PAGE_30_PN_TC2COS_MAP_port4 :: PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_4 [11:09] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_4(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_4(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0xe00,9)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_4_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_4_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_4_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_4_SHIFT 9

/* switch :: PAGE_30_PN_TC2COS_MAP_port4 :: PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_4 [08:06] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_4(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_4(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x1c0,6)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_4_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_4_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_4_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_4_SHIFT 6

/* switch :: PAGE_30_PN_TC2COS_MAP_port4 :: PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_4 [05:03] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_4(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x38,3,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_4(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x38,3)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_4_MASK 0x00000038
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_4_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_4_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_4_SHIFT 3

/* switch :: PAGE_30_PN_TC2COS_MAP_port4 :: PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_4 [02:00] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_4(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x7,0,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port4_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_4(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4,0x7,0)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_4_MASK 0x00000007
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_4_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_4_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT4_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_TC2COS_MAP_port5
 ***************************************************************************/
/* switch :: PAGE_30_PN_TC2COS_MAP_port5 :: PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_5 [31:24] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_5(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_5(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0xff000000,24)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_5_MASK 0xff000000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_5_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_5_BITS 8
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_5_SHIFT 24

/* switch :: PAGE_30_PN_TC2COS_MAP_port5 :: PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_5 [23:21] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_5(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_5(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0xe00000,21)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_5_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_5_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_5_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_5_SHIFT 21

/* switch :: PAGE_30_PN_TC2COS_MAP_port5 :: PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_5 [20:18] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_5(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_5(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x1c0000,18)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_5_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_5_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_5_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_5_SHIFT 18

/* switch :: PAGE_30_PN_TC2COS_MAP_port5 :: PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_5 [17:15] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_5(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_5(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x38000,15)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_5_MASK 0x00038000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_5_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_5_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_5_SHIFT 15

/* switch :: PAGE_30_PN_TC2COS_MAP_port5 :: PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_5 [14:12] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_5(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_5(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x7000,12)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_5_MASK 0x00007000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_5_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_5_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_5_SHIFT 12

/* switch :: PAGE_30_PN_TC2COS_MAP_port5 :: PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_5 [11:09] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_5(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_5(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0xe00,9)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_5_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_5_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_5_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_5_SHIFT 9

/* switch :: PAGE_30_PN_TC2COS_MAP_port5 :: PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_5 [08:06] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_5(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_5(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x1c0,6)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_5_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_5_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_5_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_5_SHIFT 6

/* switch :: PAGE_30_PN_TC2COS_MAP_port5 :: PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_5 [05:03] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_5(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x38,3,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_5(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x38,3)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_5_MASK 0x00000038
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_5_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_5_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_5_SHIFT 3

/* switch :: PAGE_30_PN_TC2COS_MAP_port5 :: PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_5 [02:00] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_5(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x7,0,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port5_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_5(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5,0x7,0)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_5_MASK 0x00000007
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_5_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_5_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT5_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_TC2COS_MAP_port6
 ***************************************************************************/
/* switch :: PAGE_30_PN_TC2COS_MAP_port6 :: PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_6 [31:24] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_6(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_6(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0xff000000,24)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_6_MASK 0xff000000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_6_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_6_BITS 8
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_BCAST_DLF_DROP_TC_6_SHIFT 24

/* switch :: PAGE_30_PN_TC2COS_MAP_port6 :: PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_6 [23:21] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_6(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_6(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0xe00000,21)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_6_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_6_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_6_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT111_TO_QID_6_SHIFT 21

/* switch :: PAGE_30_PN_TC2COS_MAP_port6 :: PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_6 [20:18] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_6(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_6(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x1c0000,18)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_6_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_6_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_6_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT110_TO_QID_6_SHIFT 18

/* switch :: PAGE_30_PN_TC2COS_MAP_port6 :: PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_6 [17:15] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_6(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_6(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x38000,15)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_6_MASK 0x00038000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_6_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_6_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT101_TO_QID_6_SHIFT 15

/* switch :: PAGE_30_PN_TC2COS_MAP_port6 :: PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_6 [14:12] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_6(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_6(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x7000,12)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_6_MASK 0x00007000
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_6_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_6_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT100_TO_QID_6_SHIFT 12

/* switch :: PAGE_30_PN_TC2COS_MAP_port6 :: PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_6 [11:09] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_6(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_6(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0xe00,9)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_6_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_6_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_6_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT011_TO_QID_6_SHIFT 9

/* switch :: PAGE_30_PN_TC2COS_MAP_port6 :: PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_6 [08:06] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_6(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_6(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x1c0,6)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_6_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_6_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_6_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT010_TO_QID_6_SHIFT 6

/* switch :: PAGE_30_PN_TC2COS_MAP_port6 :: PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_6 [05:03] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_6(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x38,3,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_6(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x38,3)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_6_MASK 0x00000038
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_6_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_6_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT001_TO_QID_6_SHIFT 3

/* switch :: PAGE_30_PN_TC2COS_MAP_port6 :: PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_6 [02:00] */
#define Wr_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_6(x) WriteRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x7,0,x)
#define Rd_switch_PAGE_30_PN_TC2COS_MAP_port6_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_6(x) ReadRegBits(SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6,0x7,0)
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_6_MASK 0x00000007
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_6_ALIGN 0
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_6_BITS 3
#define SWITCH_PAGE_30_PN_TC2COS_MAP_PORT6_PAGE_30_PN_TC2COS_MAP_PRT000_TO_QID_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_P7_TC2COS_MAP
 ***************************************************************************/
/* switch :: PAGE_30_P7_TC2COS_MAP :: PAGE_30_P7_TC2COS_MAP_BCAST_DLF_DROP_TC [31:24] */
#define Wr_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_BCAST_DLF_DROP_TC(x) WriteRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0xff000000,24,x)
#define Rd_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_BCAST_DLF_DROP_TC(x) ReadRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0xff000000,24)
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_MASK 0xff000000
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_ALIGN 0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_BITS 8
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_BCAST_DLF_DROP_TC_SHIFT 24

/* switch :: PAGE_30_P7_TC2COS_MAP :: PAGE_30_P7_TC2COS_MAP_PRT111_TO_QID [23:21] */
#define Wr_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT111_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0xe00000,21,x)
#define Rd_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT111_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0xe00000,21)
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT111_TO_QID_MASK 0x00e00000
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT111_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT111_TO_QID_BITS 3
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT111_TO_QID_SHIFT 21

/* switch :: PAGE_30_P7_TC2COS_MAP :: PAGE_30_P7_TC2COS_MAP_PRT110_TO_QID [20:18] */
#define Wr_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT110_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x1c0000,18,x)
#define Rd_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT110_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x1c0000,18)
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT110_TO_QID_MASK 0x001c0000
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT110_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT110_TO_QID_BITS 3
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT110_TO_QID_SHIFT 18

/* switch :: PAGE_30_P7_TC2COS_MAP :: PAGE_30_P7_TC2COS_MAP_PRT101_TO_QID [17:15] */
#define Wr_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT101_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x38000,15,x)
#define Rd_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT101_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x38000,15)
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT101_TO_QID_MASK 0x00038000
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT101_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT101_TO_QID_BITS 3
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT101_TO_QID_SHIFT 15

/* switch :: PAGE_30_P7_TC2COS_MAP :: PAGE_30_P7_TC2COS_MAP_PRT100_TO_QID [14:12] */
#define Wr_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT100_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x7000,12,x)
#define Rd_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT100_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x7000,12)
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT100_TO_QID_MASK 0x00007000
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT100_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT100_TO_QID_BITS 3
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT100_TO_QID_SHIFT 12

/* switch :: PAGE_30_P7_TC2COS_MAP :: PAGE_30_P7_TC2COS_MAP_PRT011_TO_QID [11:09] */
#define Wr_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT011_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0xe00,9,x)
#define Rd_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT011_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0xe00,9)
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT011_TO_QID_MASK 0x00000e00
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT011_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT011_TO_QID_BITS 3
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT011_TO_QID_SHIFT 9

/* switch :: PAGE_30_P7_TC2COS_MAP :: PAGE_30_P7_TC2COS_MAP_PRT010_TO_QID [08:06] */
#define Wr_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT010_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x1c0,6,x)
#define Rd_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT010_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x1c0,6)
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT010_TO_QID_MASK 0x000001c0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT010_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT010_TO_QID_BITS 3
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT010_TO_QID_SHIFT 6

/* switch :: PAGE_30_P7_TC2COS_MAP :: PAGE_30_P7_TC2COS_MAP_PRT001_TO_QID [05:03] */
#define Wr_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT001_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x38,3,x)
#define Rd_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT001_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x38,3)
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT001_TO_QID_MASK 0x00000038
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT001_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT001_TO_QID_BITS 3
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT001_TO_QID_SHIFT 3

/* switch :: PAGE_30_P7_TC2COS_MAP :: PAGE_30_P7_TC2COS_MAP_PRT000_TO_QID [02:00] */
#define Wr_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT000_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x7,0,x)
#define Rd_switch_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT000_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_P7_TC2COS_MAP,0x7,0)
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT000_TO_QID_MASK 0x00000007
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT000_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT000_TO_QID_BITS 3
#define SWITCH_PAGE_30_P7_TC2COS_MAP_PAGE_30_P7_TC2COS_MAP_PRT000_TO_QID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_IMP_TC2COS_MAP
 ***************************************************************************/
/* switch :: PAGE_30_IMP_TC2COS_MAP :: PAGE_30_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC [31:24] */
#define Wr_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC(x) WriteRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0xff000000,24,x)
#define Rd_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC(x) ReadRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0xff000000,24)
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_MASK 0xff000000
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_BITS 8
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_BCAST_DLF_DROP_TC_SHIFT 24

/* switch :: PAGE_30_IMP_TC2COS_MAP :: PAGE_30_IMP_TC2COS_MAP_PRT111_TO_QID [23:21] */
#define Wr_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT111_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0xe00000,21,x)
#define Rd_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT111_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0xe00000,21)
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT111_TO_QID_MASK 0x00e00000
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT111_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT111_TO_QID_BITS 3
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT111_TO_QID_SHIFT 21

/* switch :: PAGE_30_IMP_TC2COS_MAP :: PAGE_30_IMP_TC2COS_MAP_PRT110_TO_QID [20:18] */
#define Wr_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT110_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x1c0000,18,x)
#define Rd_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT110_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x1c0000,18)
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT110_TO_QID_MASK 0x001c0000
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT110_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT110_TO_QID_BITS 3
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT110_TO_QID_SHIFT 18

/* switch :: PAGE_30_IMP_TC2COS_MAP :: PAGE_30_IMP_TC2COS_MAP_PRT101_TO_QID [17:15] */
#define Wr_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT101_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x38000,15,x)
#define Rd_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT101_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x38000,15)
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT101_TO_QID_MASK 0x00038000
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT101_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT101_TO_QID_BITS 3
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT101_TO_QID_SHIFT 15

/* switch :: PAGE_30_IMP_TC2COS_MAP :: PAGE_30_IMP_TC2COS_MAP_PRT100_TO_QID [14:12] */
#define Wr_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT100_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x7000,12,x)
#define Rd_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT100_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x7000,12)
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT100_TO_QID_MASK 0x00007000
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT100_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT100_TO_QID_BITS 3
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT100_TO_QID_SHIFT 12

/* switch :: PAGE_30_IMP_TC2COS_MAP :: PAGE_30_IMP_TC2COS_MAP_PRT011_TO_QID [11:09] */
#define Wr_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT011_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0xe00,9,x)
#define Rd_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT011_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0xe00,9)
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT011_TO_QID_MASK 0x00000e00
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT011_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT011_TO_QID_BITS 3
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT011_TO_QID_SHIFT 9

/* switch :: PAGE_30_IMP_TC2COS_MAP :: PAGE_30_IMP_TC2COS_MAP_PRT010_TO_QID [08:06] */
#define Wr_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT010_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x1c0,6,x)
#define Rd_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT010_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x1c0,6)
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT010_TO_QID_MASK 0x000001c0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT010_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT010_TO_QID_BITS 3
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT010_TO_QID_SHIFT 6

/* switch :: PAGE_30_IMP_TC2COS_MAP :: PAGE_30_IMP_TC2COS_MAP_PRT001_TO_QID [05:03] */
#define Wr_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT001_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x38,3,x)
#define Rd_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT001_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x38,3)
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT001_TO_QID_MASK 0x00000038
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT001_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT001_TO_QID_BITS 3
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT001_TO_QID_SHIFT 3

/* switch :: PAGE_30_IMP_TC2COS_MAP :: PAGE_30_IMP_TC2COS_MAP_PRT000_TO_QID [02:00] */
#define Wr_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT000_TO_QID(x) WriteRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x7,0,x)
#define Rd_switch_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT000_TO_QID(x) ReadRegBits(SWITCH_PAGE_30_IMP_TC2COS_MAP,0x7,0)
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT000_TO_QID_MASK 0x00000007
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT000_TO_QID_ALIGN 0
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT000_TO_QID_BITS 3
#define SWITCH_PAGE_30_IMP_TC2COS_MAP_PAGE_30_IMP_TC2COS_MAP_PRT000_TO_QID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_QOS_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_30_QOS_REG_SPARE0 :: PAGE_30_QOS_REG_SPARE0_QOS_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_30_QOS_REG_SPARE0_PAGE_30_QOS_REG_SPARE0_QOS_REG_SPARE0(x) WriteReg(SWITCH_PAGE_30_QOS_REG_SPARE0,x)
#define Rd_switch_PAGE_30_QOS_REG_SPARE0_PAGE_30_QOS_REG_SPARE0_QOS_REG_SPARE0(x) ReadReg(SWITCH_PAGE_30_QOS_REG_SPARE0)
#define SWITCH_PAGE_30_QOS_REG_SPARE0_PAGE_30_QOS_REG_SPARE0_QOS_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_30_QOS_REG_SPARE0_PAGE_30_QOS_REG_SPARE0_QOS_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_30_QOS_REG_SPARE0_PAGE_30_QOS_REG_SPARE0_QOS_REG_SPARE0_BITS 32
#define SWITCH_PAGE_30_QOS_REG_SPARE0_PAGE_30_QOS_REG_SPARE0_QOS_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_QOS_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_30_QOS_REG_SPARE1 :: PAGE_30_QOS_REG_SPARE1_QOS_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_30_QOS_REG_SPARE1_PAGE_30_QOS_REG_SPARE1_QOS_REG_SPARE1(x) WriteReg(SWITCH_PAGE_30_QOS_REG_SPARE1,x)
#define Rd_switch_PAGE_30_QOS_REG_SPARE1_PAGE_30_QOS_REG_SPARE1_QOS_REG_SPARE1(x) ReadReg(SWITCH_PAGE_30_QOS_REG_SPARE1)
#define SWITCH_PAGE_30_QOS_REG_SPARE1_PAGE_30_QOS_REG_SPARE1_QOS_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_30_QOS_REG_SPARE1_PAGE_30_QOS_REG_SPARE1_QOS_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_30_QOS_REG_SPARE1_PAGE_30_QOS_REG_SPARE1_QOS_REG_SPARE1_BITS 32
#define SWITCH_PAGE_30_QOS_REG_SPARE1_PAGE_30_QOS_REG_SPARE1_QOS_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI1_port0
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI1_port0 :: PAGE_30_PN_PCP2TC_DEI1_RESERVED_0 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_RESERVED_0_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_RESERVED_0_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_RESERVED_0_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port0 :: PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_0 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_0_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_0_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port0 :: PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_0 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_0_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_0_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port0 :: PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_0 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_0_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_0_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port0 :: PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_0 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_0_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_0_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port0 :: PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_0 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_0_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_0_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port0 :: PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_0 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_0_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_0_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port0 :: PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_0 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_0_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_0_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port0 :: PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_0 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_0(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port0_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_0(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_0_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_0_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_0_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT0_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI1_port1
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI1_port1 :: PAGE_30_PN_PCP2TC_DEI1_RESERVED_1 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_RESERVED_1_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_RESERVED_1_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_RESERVED_1_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port1 :: PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_1 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_1_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_1_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port1 :: PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_1 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_1_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_1_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port1 :: PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_1 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_1_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_1_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port1 :: PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_1 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_1_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_1_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port1 :: PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_1 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_1_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_1_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port1 :: PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_1 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_1_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_1_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port1 :: PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_1 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_1_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_1_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port1 :: PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_1 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_1(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port1_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_1(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_1_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_1_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_1_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT1_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI1_port2
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI1_port2 :: PAGE_30_PN_PCP2TC_DEI1_RESERVED_2 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_RESERVED_2_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_RESERVED_2_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_RESERVED_2_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port2 :: PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_2 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_2_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_2_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port2 :: PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_2 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_2_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_2_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port2 :: PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_2 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_2_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_2_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port2 :: PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_2 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_2_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_2_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port2 :: PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_2 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_2_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_2_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port2 :: PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_2 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_2_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_2_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port2 :: PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_2 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_2_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_2_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port2 :: PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_2 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_2(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port2_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_2(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_2_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_2_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_2_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT2_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI1_port3
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI1_port3 :: PAGE_30_PN_PCP2TC_DEI1_RESERVED_3 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_RESERVED_3_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_RESERVED_3_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_RESERVED_3_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port3 :: PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_3 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_3_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_3_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port3 :: PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_3 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_3_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_3_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port3 :: PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_3 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_3_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_3_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port3 :: PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_3 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_3_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_3_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port3 :: PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_3 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_3_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_3_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port3 :: PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_3 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_3_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_3_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port3 :: PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_3 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_3_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_3_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port3 :: PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_3 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_3(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port3_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_3(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_3_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_3_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_3_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT3_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI1_port4
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI1_port4 :: PAGE_30_PN_PCP2TC_DEI1_RESERVED_4 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_RESERVED_4_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_RESERVED_4_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_RESERVED_4_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port4 :: PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_4 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_4_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_4_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port4 :: PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_4 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_4_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_4_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port4 :: PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_4 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_4_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_4_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port4 :: PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_4 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_4_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_4_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port4 :: PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_4 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_4_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_4_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port4 :: PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_4 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_4_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_4_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port4 :: PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_4 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_4_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_4_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port4 :: PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_4 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_4(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port4_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_4(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_4_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_4_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_4_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT4_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI1_port5
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI1_port5 :: PAGE_30_PN_PCP2TC_DEI1_RESERVED_5 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_RESERVED_5_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_RESERVED_5_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_RESERVED_5_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port5 :: PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_5 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_5_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_5_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port5 :: PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_5 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_5_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_5_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port5 :: PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_5 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_5_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_5_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port5 :: PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_5 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_5_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_5_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port5 :: PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_5 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_5_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_5_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port5 :: PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_5 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_5_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_5_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port5 :: PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_5 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_5_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_5_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port5 :: PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_5 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_5(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port5_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_5(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_5_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_5_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_5_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT5_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_PN_PCP2TC_DEI1_port6
 ***************************************************************************/
/* switch :: PAGE_30_PN_PCP2TC_DEI1_port6 :: PAGE_30_PN_PCP2TC_DEI1_RESERVED_6 [31:24] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0xff000000,24,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0xff000000,24)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_RESERVED_6_MASK 0xff000000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_RESERVED_6_BITS 8
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_RESERVED_6_SHIFT 24

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port6 :: PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_6 [23:21] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0xe00000,21,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0xe00000,21)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_6_MASK 0x00e00000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG111_PRI_MAP_6_SHIFT 21

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port6 :: PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_6 [20:18] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x1c0000,18,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x1c0000,18)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_6_MASK 0x001c0000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG110_PRI_MAP_6_SHIFT 18

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port6 :: PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_6 [17:15] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x38000,15,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x38000,15)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_6_MASK 0x00038000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG101_PRI_MAP_6_SHIFT 15

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port6 :: PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_6 [14:12] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x7000,12,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x7000,12)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_6_MASK 0x00007000
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG100_PRI_MAP_6_SHIFT 12

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port6 :: PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_6 [11:09] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0xe00,9,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0xe00,9)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_6_MASK 0x00000e00
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG011_PRI_MAP_6_SHIFT 9

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port6 :: PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_6 [08:06] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x1c0,6,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x1c0,6)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_6_MASK 0x000001c0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG010_PRI_MAP_6_SHIFT 6

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port6 :: PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_6 [05:03] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x38,3,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x38,3)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_6_MASK 0x00000038
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG001_PRI_MAP_6_SHIFT 3

/* switch :: PAGE_30_PN_PCP2TC_DEI1_port6 :: PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_6 [02:00] */
#define Wr_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_6(x) WriteRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x7,0,x)
#define Rd_switch_PAGE_30_PN_PCP2TC_DEI1_port6_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_6(x) ReadRegBits(SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6,0x7,0)
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_6_MASK 0x00000007
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_6_ALIGN 0
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_6_BITS 3
#define SWITCH_PAGE_30_PN_PCP2TC_DEI1_PORT6_PAGE_30_PN_PCP2TC_DEI1_TAG000_PRI_MAP_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_P7_PCP2TC_DEI1
 ***************************************************************************/
/* switch :: PAGE_30_P7_PCP2TC_DEI1 :: PAGE_30_P7_PCP2TC_DEI1_RESERVED [31:24] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_RESERVED(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0xff000000,24,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_RESERVED(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0xff000000,24)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_RESERVED_MASK 0xff000000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_RESERVED_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_RESERVED_BITS 8
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_RESERVED_SHIFT 24

/* switch :: PAGE_30_P7_PCP2TC_DEI1 :: PAGE_30_P7_PCP2TC_DEI1_TAG111_PRI_MAP [23:21] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG111_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0xe00000,21,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG111_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0xe00000,21)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG111_PRI_MAP_MASK 0x00e00000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG111_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG111_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG111_PRI_MAP_SHIFT 21

/* switch :: PAGE_30_P7_PCP2TC_DEI1 :: PAGE_30_P7_PCP2TC_DEI1_TAG110_PRI_MAP [20:18] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG110_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x1c0000,18,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG110_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x1c0000,18)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG110_PRI_MAP_MASK 0x001c0000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG110_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG110_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG110_PRI_MAP_SHIFT 18

/* switch :: PAGE_30_P7_PCP2TC_DEI1 :: PAGE_30_P7_PCP2TC_DEI1_TAG101_PRI_MAP [17:15] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG101_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x38000,15,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG101_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x38000,15)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG101_PRI_MAP_MASK 0x00038000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG101_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG101_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG101_PRI_MAP_SHIFT 15

/* switch :: PAGE_30_P7_PCP2TC_DEI1 :: PAGE_30_P7_PCP2TC_DEI1_TAG100_PRI_MAP [14:12] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG100_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x7000,12,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG100_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x7000,12)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG100_PRI_MAP_MASK 0x00007000
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG100_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG100_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG100_PRI_MAP_SHIFT 12

/* switch :: PAGE_30_P7_PCP2TC_DEI1 :: PAGE_30_P7_PCP2TC_DEI1_TAG011_PRI_MAP [11:09] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG011_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0xe00,9,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG011_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0xe00,9)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG011_PRI_MAP_MASK 0x00000e00
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG011_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG011_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG011_PRI_MAP_SHIFT 9

/* switch :: PAGE_30_P7_PCP2TC_DEI1 :: PAGE_30_P7_PCP2TC_DEI1_TAG010_PRI_MAP [08:06] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG010_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x1c0,6,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG010_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x1c0,6)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG010_PRI_MAP_MASK 0x000001c0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG010_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG010_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG010_PRI_MAP_SHIFT 6

/* switch :: PAGE_30_P7_PCP2TC_DEI1 :: PAGE_30_P7_PCP2TC_DEI1_TAG001_PRI_MAP [05:03] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG001_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x38,3,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG001_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x38,3)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG001_PRI_MAP_MASK 0x00000038
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG001_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG001_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG001_PRI_MAP_SHIFT 3

/* switch :: PAGE_30_P7_PCP2TC_DEI1 :: PAGE_30_P7_PCP2TC_DEI1_TAG000_PRI_MAP [02:00] */
#define Wr_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG000_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x7,0,x)
#define Rd_switch_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG000_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_P7_PCP2TC_DEI1,0x7,0)
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG000_PRI_MAP_MASK 0x00000007
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG000_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG000_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_P7_PCP2TC_DEI1_PAGE_30_P7_PCP2TC_DEI1_TAG000_PRI_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_30_IMP_PCP2TC_DEI1
 ***************************************************************************/
/* switch :: PAGE_30_IMP_PCP2TC_DEI1 :: PAGE_30_IMP_PCP2TC_DEI1_RESERVED [31:24] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_RESERVED(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0xff000000,24,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_RESERVED(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0xff000000,24)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_RESERVED_MASK 0xff000000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_RESERVED_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_RESERVED_BITS 8
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_RESERVED_SHIFT 24

/* switch :: PAGE_30_IMP_PCP2TC_DEI1 :: PAGE_30_IMP_PCP2TC_DEI1_TAG111_PRI_MAP [23:21] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG111_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0xe00000,21,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG111_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0xe00000,21)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_MASK 0x00e00000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG111_PRI_MAP_SHIFT 21

/* switch :: PAGE_30_IMP_PCP2TC_DEI1 :: PAGE_30_IMP_PCP2TC_DEI1_TAG110_PRI_MAP [20:18] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG110_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x1c0000,18,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG110_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x1c0000,18)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_MASK 0x001c0000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG110_PRI_MAP_SHIFT 18

/* switch :: PAGE_30_IMP_PCP2TC_DEI1 :: PAGE_30_IMP_PCP2TC_DEI1_TAG101_PRI_MAP [17:15] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG101_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x38000,15,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG101_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x38000,15)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_MASK 0x00038000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG101_PRI_MAP_SHIFT 15

/* switch :: PAGE_30_IMP_PCP2TC_DEI1 :: PAGE_30_IMP_PCP2TC_DEI1_TAG100_PRI_MAP [14:12] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG100_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x7000,12,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG100_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x7000,12)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_MASK 0x00007000
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG100_PRI_MAP_SHIFT 12

/* switch :: PAGE_30_IMP_PCP2TC_DEI1 :: PAGE_30_IMP_PCP2TC_DEI1_TAG011_PRI_MAP [11:09] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG011_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0xe00,9,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG011_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0xe00,9)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_MASK 0x00000e00
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG011_PRI_MAP_SHIFT 9

/* switch :: PAGE_30_IMP_PCP2TC_DEI1 :: PAGE_30_IMP_PCP2TC_DEI1_TAG010_PRI_MAP [08:06] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG010_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x1c0,6,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG010_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x1c0,6)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_MASK 0x000001c0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG010_PRI_MAP_SHIFT 6

/* switch :: PAGE_30_IMP_PCP2TC_DEI1 :: PAGE_30_IMP_PCP2TC_DEI1_TAG001_PRI_MAP [05:03] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG001_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x38,3,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG001_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x38,3)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_MASK 0x00000038
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG001_PRI_MAP_SHIFT 3

/* switch :: PAGE_30_IMP_PCP2TC_DEI1 :: PAGE_30_IMP_PCP2TC_DEI1_TAG000_PRI_MAP [02:00] */
#define Wr_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG000_PRI_MAP(x) WriteRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x7,0,x)
#define Rd_switch_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG000_PRI_MAP(x) ReadRegBits(SWITCH_PAGE_30_IMP_PCP2TC_DEI1,0x7,0)
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_MASK 0x00000007
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_ALIGN 0
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_BITS 3
#define SWITCH_PAGE_30_IMP_PCP2TC_DEI1_PAGE_30_IMP_PCP2TC_DEI1_TAG000_PRI_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_PORT_VLAN_CTL_port0
 ***************************************************************************/
/* switch :: PAGE_31_PORT_VLAN_CTL_port0 :: PAGE_31_PORT_VLAN_CTL_RESERVED_0 [15:09] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port0_PAGE_31_PORT_VLAN_CTL_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0,0xfe00,9,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port0_PAGE_31_PORT_VLAN_CTL_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0,0xfe00,9)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0_PAGE_31_PORT_VLAN_CTL_RESERVED_0_MASK 0xfe00
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0_PAGE_31_PORT_VLAN_CTL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0_PAGE_31_PORT_VLAN_CTL_RESERVED_0_BITS 7
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0_PAGE_31_PORT_VLAN_CTL_RESERVED_0_SHIFT 9

/* switch :: PAGE_31_PORT_VLAN_CTL_port0 :: PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_0 [08:00] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port0_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_0(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0,0x1ff,0,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port0_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_0(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0,0x1ff,0)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_0_MASK 0x01ff
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_0_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_0_BITS 9
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT0_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_PORT_VLAN_CTL_port1
 ***************************************************************************/
/* switch :: PAGE_31_PORT_VLAN_CTL_port1 :: PAGE_31_PORT_VLAN_CTL_RESERVED_1 [15:09] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port1_PAGE_31_PORT_VLAN_CTL_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1,0xfe00,9,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port1_PAGE_31_PORT_VLAN_CTL_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1,0xfe00,9)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1_PAGE_31_PORT_VLAN_CTL_RESERVED_1_MASK 0xfe00
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1_PAGE_31_PORT_VLAN_CTL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1_PAGE_31_PORT_VLAN_CTL_RESERVED_1_BITS 7
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1_PAGE_31_PORT_VLAN_CTL_RESERVED_1_SHIFT 9

/* switch :: PAGE_31_PORT_VLAN_CTL_port1 :: PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_1 [08:00] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port1_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_1(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1,0x1ff,0,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port1_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_1(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1,0x1ff,0)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_1_MASK 0x01ff
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_1_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_1_BITS 9
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT1_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_PORT_VLAN_CTL_port2
 ***************************************************************************/
/* switch :: PAGE_31_PORT_VLAN_CTL_port2 :: PAGE_31_PORT_VLAN_CTL_RESERVED_2 [15:09] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port2_PAGE_31_PORT_VLAN_CTL_RESERVED_2(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2,0xfe00,9,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port2_PAGE_31_PORT_VLAN_CTL_RESERVED_2(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2,0xfe00,9)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2_PAGE_31_PORT_VLAN_CTL_RESERVED_2_MASK 0xfe00
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2_PAGE_31_PORT_VLAN_CTL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2_PAGE_31_PORT_VLAN_CTL_RESERVED_2_BITS 7
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2_PAGE_31_PORT_VLAN_CTL_RESERVED_2_SHIFT 9

/* switch :: PAGE_31_PORT_VLAN_CTL_port2 :: PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_2 [08:00] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port2_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_2(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2,0x1ff,0,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port2_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_2(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2,0x1ff,0)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_2_MASK 0x01ff
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_2_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_2_BITS 9
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT2_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_PORT_VLAN_CTL_port3
 ***************************************************************************/
/* switch :: PAGE_31_PORT_VLAN_CTL_port3 :: PAGE_31_PORT_VLAN_CTL_RESERVED_3 [15:09] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port3_PAGE_31_PORT_VLAN_CTL_RESERVED_3(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3,0xfe00,9,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port3_PAGE_31_PORT_VLAN_CTL_RESERVED_3(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3,0xfe00,9)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3_PAGE_31_PORT_VLAN_CTL_RESERVED_3_MASK 0xfe00
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3_PAGE_31_PORT_VLAN_CTL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3_PAGE_31_PORT_VLAN_CTL_RESERVED_3_BITS 7
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3_PAGE_31_PORT_VLAN_CTL_RESERVED_3_SHIFT 9

/* switch :: PAGE_31_PORT_VLAN_CTL_port3 :: PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_3 [08:00] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port3_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_3(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3,0x1ff,0,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port3_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_3(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3,0x1ff,0)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_3_MASK 0x01ff
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_3_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_3_BITS 9
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT3_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_PORT_VLAN_CTL_port4
 ***************************************************************************/
/* switch :: PAGE_31_PORT_VLAN_CTL_port4 :: PAGE_31_PORT_VLAN_CTL_RESERVED_4 [15:09] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port4_PAGE_31_PORT_VLAN_CTL_RESERVED_4(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4,0xfe00,9,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port4_PAGE_31_PORT_VLAN_CTL_RESERVED_4(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4,0xfe00,9)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4_PAGE_31_PORT_VLAN_CTL_RESERVED_4_MASK 0xfe00
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4_PAGE_31_PORT_VLAN_CTL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4_PAGE_31_PORT_VLAN_CTL_RESERVED_4_BITS 7
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4_PAGE_31_PORT_VLAN_CTL_RESERVED_4_SHIFT 9

/* switch :: PAGE_31_PORT_VLAN_CTL_port4 :: PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_4 [08:00] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port4_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_4(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4,0x1ff,0,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port4_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_4(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4,0x1ff,0)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_4_MASK 0x01ff
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_4_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_4_BITS 9
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT4_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_PORT_VLAN_CTL_port5
 ***************************************************************************/
/* switch :: PAGE_31_PORT_VLAN_CTL_port5 :: PAGE_31_PORT_VLAN_CTL_RESERVED_5 [15:09] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port5_PAGE_31_PORT_VLAN_CTL_RESERVED_5(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5,0xfe00,9,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port5_PAGE_31_PORT_VLAN_CTL_RESERVED_5(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5,0xfe00,9)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5_PAGE_31_PORT_VLAN_CTL_RESERVED_5_MASK 0xfe00
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5_PAGE_31_PORT_VLAN_CTL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5_PAGE_31_PORT_VLAN_CTL_RESERVED_5_BITS 7
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5_PAGE_31_PORT_VLAN_CTL_RESERVED_5_SHIFT 9

/* switch :: PAGE_31_PORT_VLAN_CTL_port5 :: PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_5 [08:00] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port5_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_5(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5,0x1ff,0,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port5_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_5(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5,0x1ff,0)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_5_MASK 0x01ff
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_5_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_5_BITS 9
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT5_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_PORT_VLAN_CTL_port6
 ***************************************************************************/
/* switch :: PAGE_31_PORT_VLAN_CTL_port6 :: PAGE_31_PORT_VLAN_CTL_RESERVED_6 [15:09] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port6_PAGE_31_PORT_VLAN_CTL_RESERVED_6(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6,0xfe00,9,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port6_PAGE_31_PORT_VLAN_CTL_RESERVED_6(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6,0xfe00,9)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6_PAGE_31_PORT_VLAN_CTL_RESERVED_6_MASK 0xfe00
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6_PAGE_31_PORT_VLAN_CTL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6_PAGE_31_PORT_VLAN_CTL_RESERVED_6_BITS 7
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6_PAGE_31_PORT_VLAN_CTL_RESERVED_6_SHIFT 9

/* switch :: PAGE_31_PORT_VLAN_CTL_port6 :: PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_6 [08:00] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_port6_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_6(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6,0x1ff,0,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_port6_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_6(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6,0x1ff,0)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_6_MASK 0x01ff
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_6_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_6_BITS 9
#define SWITCH_PAGE_31_PORT_VLAN_CTL_PORT6_PAGE_31_PORT_VLAN_CTL_PORT_EGRESS_EN_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_PORT_VLAN_CTL_P7
 ***************************************************************************/
/* switch :: PAGE_31_PORT_VLAN_CTL_P7 :: PAGE_31_PORT_VLAN_CTL_P7_RESERVED [15:09] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_P7,0xfe00,9,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_P7,0xfe00,9)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_RESERVED_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_RESERVED_BITS 7
#define SWITCH_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_RESERVED_SHIFT 9

/* switch :: PAGE_31_PORT_VLAN_CTL_P7 :: PAGE_31_PORT_VLAN_CTL_P7_PORT_EGRESS_EN [08:00] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_PORT_EGRESS_EN(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_P7,0x1ff,0,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_PORT_EGRESS_EN(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_P7,0x1ff,0)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_MASK 0x01ff
#define SWITCH_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_BITS 9
#define SWITCH_PAGE_31_PORT_VLAN_CTL_P7_PAGE_31_PORT_VLAN_CTL_P7_PORT_EGRESS_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_PORT_VLAN_CTL_IMP
 ***************************************************************************/
/* switch :: PAGE_31_PORT_VLAN_CTL_IMP :: PAGE_31_PORT_VLAN_CTL_IMP_RESERVED [15:09] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_IMP,0xfe00,9,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_IMP,0xfe00,9)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_RESERVED_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_RESERVED_BITS 7
#define SWITCH_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_RESERVED_SHIFT 9

/* switch :: PAGE_31_PORT_VLAN_CTL_IMP :: PAGE_31_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN [08:00] */
#define Wr_switch_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN(x) WriteRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_IMP,0x1ff,0,x)
#define Rd_switch_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN(x) ReadRegBits16(SWITCH_PAGE_31_PORT_VLAN_CTL_IMP,0x1ff,0)
#define SWITCH_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_MASK 0x01ff
#define SWITCH_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_ALIGN 0
#define SWITCH_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_BITS 9
#define SWITCH_PAGE_31_PORT_VLAN_CTL_IMP_PAGE_31_PORT_VLAN_CTL_IMP_PORT_EGRESS_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_VLAN_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_31_VLAN_REG_SPARE0 :: PAGE_31_VLAN_REG_SPARE0_VLAN_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_31_VLAN_REG_SPARE0_PAGE_31_VLAN_REG_SPARE0_VLAN_REG_SPARE0(x) WriteReg(SWITCH_PAGE_31_VLAN_REG_SPARE0,x)
#define Rd_switch_PAGE_31_VLAN_REG_SPARE0_PAGE_31_VLAN_REG_SPARE0_VLAN_REG_SPARE0(x) ReadReg(SWITCH_PAGE_31_VLAN_REG_SPARE0)
#define SWITCH_PAGE_31_VLAN_REG_SPARE0_PAGE_31_VLAN_REG_SPARE0_VLAN_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_31_VLAN_REG_SPARE0_PAGE_31_VLAN_REG_SPARE0_VLAN_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_31_VLAN_REG_SPARE0_PAGE_31_VLAN_REG_SPARE0_VLAN_REG_SPARE0_BITS 32
#define SWITCH_PAGE_31_VLAN_REG_SPARE0_PAGE_31_VLAN_REG_SPARE0_VLAN_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_31_VLAN_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_31_VLAN_REG_SPARE1 :: PAGE_31_VLAN_REG_SPARE1_VLAN_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_31_VLAN_REG_SPARE1_PAGE_31_VLAN_REG_SPARE1_VLAN_REG_SPARE1(x) WriteReg(SWITCH_PAGE_31_VLAN_REG_SPARE1,x)
#define Rd_switch_PAGE_31_VLAN_REG_SPARE1_PAGE_31_VLAN_REG_SPARE1_VLAN_REG_SPARE1(x) ReadReg(SWITCH_PAGE_31_VLAN_REG_SPARE1)
#define SWITCH_PAGE_31_VLAN_REG_SPARE1_PAGE_31_VLAN_REG_SPARE1_VLAN_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_31_VLAN_REG_SPARE1_PAGE_31_VLAN_REG_SPARE1_VLAN_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_31_VLAN_REG_SPARE1_PAGE_31_VLAN_REG_SPARE1_VLAN_REG_SPARE1_BITS 32
#define SWITCH_PAGE_31_VLAN_REG_SPARE1_PAGE_31_VLAN_REG_SPARE1_VLAN_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_32_MAC_TRUNK_CTL
 ***************************************************************************/
/* switch :: PAGE_32_MAC_TRUNK_CTL :: PAGE_32_MAC_TRUNK_CTL_SERVER_1 [07:04] */
#define Wr_switch_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_1(x) WriteRegBits(SWITCH_PAGE_32_MAC_TRUNK_CTL,0xf0,4,x)
#define Rd_switch_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_1(x) ReadRegBits(SWITCH_PAGE_32_MAC_TRUNK_CTL,0xf0,4)
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_1_MASK 0xf0
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_1_ALIGN 0
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_1_BITS 4
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_1_SHIFT 4

/* switch :: PAGE_32_MAC_TRUNK_CTL :: PAGE_32_MAC_TRUNK_CTL_EN_TRUNK_LOCAL [03:03] */
#define Wr_switch_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_EN_TRUNK_LOCAL(x) WriteRegBits(SWITCH_PAGE_32_MAC_TRUNK_CTL,0x8,3,x)
#define Rd_switch_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_EN_TRUNK_LOCAL(x) ReadRegBits(SWITCH_PAGE_32_MAC_TRUNK_CTL,0x8,3)
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_MASK 0x08
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_ALIGN 0
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_BITS 1
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_EN_TRUNK_LOCAL_SHIFT 3

/* switch :: PAGE_32_MAC_TRUNK_CTL :: PAGE_32_MAC_TRUNK_CTL_SERVER_0 [02:02] */
#define Wr_switch_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_0(x) WriteRegBits(SWITCH_PAGE_32_MAC_TRUNK_CTL,0x4,2,x)
#define Rd_switch_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_0(x) ReadRegBits(SWITCH_PAGE_32_MAC_TRUNK_CTL,0x4,2)
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_0_MASK 0x04
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_0_ALIGN 0
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_0_BITS 1
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_SERVER_0_SHIFT 2

/* switch :: PAGE_32_MAC_TRUNK_CTL :: PAGE_32_MAC_TRUNK_CTL_HASH_SEL [01:00] */
#define Wr_switch_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_HASH_SEL(x) WriteRegBits(SWITCH_PAGE_32_MAC_TRUNK_CTL,0x3,0,x)
#define Rd_switch_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_HASH_SEL(x) ReadRegBits(SWITCH_PAGE_32_MAC_TRUNK_CTL,0x3,0)
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_HASH_SEL_MASK 0x03
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_HASH_SEL_ALIGN 0
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_HASH_SEL_BITS 2
#define SWITCH_PAGE_32_MAC_TRUNK_CTL_PAGE_32_MAC_TRUNK_CTL_HASH_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_32_TRUNK_GRP_CTL0
 ***************************************************************************/
/* switch :: PAGE_32_TRUNK_GRP_CTL0 :: PAGE_32_TRUNK_GRP_CTL0_RESERVED [15:09] */
#define Wr_switch_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL0,0xfe00,9,x)
#define Rd_switch_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL0,0xfe00,9)
#define SWITCH_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_RESERVED_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_RESERVED_BITS 7
#define SWITCH_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_RESERVED_SHIFT 9

/* switch :: PAGE_32_TRUNK_GRP_CTL0 :: PAGE_32_TRUNK_GRP_CTL0_EN_TRUNK_GRP [08:00] */
#define Wr_switch_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_EN_TRUNK_GRP(x) WriteRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL0,0x1ff,0,x)
#define Rd_switch_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_EN_TRUNK_GRP(x) ReadRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL0,0x1ff,0)
#define SWITCH_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_EN_TRUNK_GRP_MASK 0x01ff
#define SWITCH_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_EN_TRUNK_GRP_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_EN_TRUNK_GRP_BITS 9
#define SWITCH_PAGE_32_TRUNK_GRP_CTL0_PAGE_32_TRUNK_GRP_CTL0_EN_TRUNK_GRP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_32_TRUNK_GRP_CTL1
 ***************************************************************************/
/* switch :: PAGE_32_TRUNK_GRP_CTL1 :: PAGE_32_TRUNK_GRP_CTL1_RESERVED [15:09] */
#define Wr_switch_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL1,0xfe00,9,x)
#define Rd_switch_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL1,0xfe00,9)
#define SWITCH_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_RESERVED_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_RESERVED_BITS 7
#define SWITCH_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_RESERVED_SHIFT 9

/* switch :: PAGE_32_TRUNK_GRP_CTL1 :: PAGE_32_TRUNK_GRP_CTL1_EN_TRUNK_GRP [08:00] */
#define Wr_switch_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_EN_TRUNK_GRP(x) WriteRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL1,0x1ff,0,x)
#define Rd_switch_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_EN_TRUNK_GRP(x) ReadRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL1,0x1ff,0)
#define SWITCH_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_EN_TRUNK_GRP_MASK 0x01ff
#define SWITCH_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_EN_TRUNK_GRP_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_EN_TRUNK_GRP_BITS 9
#define SWITCH_PAGE_32_TRUNK_GRP_CTL1_PAGE_32_TRUNK_GRP_CTL1_EN_TRUNK_GRP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_32_TRUNK_GRP_CTL2
 ***************************************************************************/
/* switch :: PAGE_32_TRUNK_GRP_CTL2 :: PAGE_32_TRUNK_GRP_CTL2_RESERVED [15:09] */
#define Wr_switch_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL2,0xfe00,9,x)
#define Rd_switch_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL2,0xfe00,9)
#define SWITCH_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_RESERVED_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_RESERVED_BITS 7
#define SWITCH_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_RESERVED_SHIFT 9

/* switch :: PAGE_32_TRUNK_GRP_CTL2 :: PAGE_32_TRUNK_GRP_CTL2_EN_TRUNK_GRP [08:00] */
#define Wr_switch_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_EN_TRUNK_GRP(x) WriteRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL2,0x1ff,0,x)
#define Rd_switch_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_EN_TRUNK_GRP(x) ReadRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL2,0x1ff,0)
#define SWITCH_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_EN_TRUNK_GRP_MASK 0x01ff
#define SWITCH_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_EN_TRUNK_GRP_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_EN_TRUNK_GRP_BITS 9
#define SWITCH_PAGE_32_TRUNK_GRP_CTL2_PAGE_32_TRUNK_GRP_CTL2_EN_TRUNK_GRP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_32_TRUNK_GRP_CTL3
 ***************************************************************************/
/* switch :: PAGE_32_TRUNK_GRP_CTL3 :: PAGE_32_TRUNK_GRP_CTL3_RESERVED [15:09] */
#define Wr_switch_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL3,0xfe00,9,x)
#define Rd_switch_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL3,0xfe00,9)
#define SWITCH_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_RESERVED_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_RESERVED_BITS 7
#define SWITCH_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_RESERVED_SHIFT 9

/* switch :: PAGE_32_TRUNK_GRP_CTL3 :: PAGE_32_TRUNK_GRP_CTL3_EN_TRUNK_GRP [08:00] */
#define Wr_switch_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_EN_TRUNK_GRP(x) WriteRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL3,0x1ff,0,x)
#define Rd_switch_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_EN_TRUNK_GRP(x) ReadRegBits16(SWITCH_PAGE_32_TRUNK_GRP_CTL3,0x1ff,0)
#define SWITCH_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_EN_TRUNK_GRP_MASK 0x01ff
#define SWITCH_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_EN_TRUNK_GRP_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_EN_TRUNK_GRP_BITS 9
#define SWITCH_PAGE_32_TRUNK_GRP_CTL3_PAGE_32_TRUNK_GRP_CTL3_EN_TRUNK_GRP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_32_TRUNK_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_32_TRUNK_REG_SPARE0 :: PAGE_32_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_32_TRUNK_REG_SPARE0_PAGE_32_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0(x) WriteReg(SWITCH_PAGE_32_TRUNK_REG_SPARE0,x)
#define Rd_switch_PAGE_32_TRUNK_REG_SPARE0_PAGE_32_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0(x) ReadReg(SWITCH_PAGE_32_TRUNK_REG_SPARE0)
#define SWITCH_PAGE_32_TRUNK_REG_SPARE0_PAGE_32_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_32_TRUNK_REG_SPARE0_PAGE_32_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_REG_SPARE0_PAGE_32_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_BITS 32
#define SWITCH_PAGE_32_TRUNK_REG_SPARE0_PAGE_32_TRUNK_REG_SPARE0_TRUNK_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_32_TRUNK_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_32_TRUNK_REG_SPARE1 :: PAGE_32_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_32_TRUNK_REG_SPARE1_PAGE_32_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1(x) WriteReg(SWITCH_PAGE_32_TRUNK_REG_SPARE1,x)
#define Rd_switch_PAGE_32_TRUNK_REG_SPARE1_PAGE_32_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1(x) ReadReg(SWITCH_PAGE_32_TRUNK_REG_SPARE1)
#define SWITCH_PAGE_32_TRUNK_REG_SPARE1_PAGE_32_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_32_TRUNK_REG_SPARE1_PAGE_32_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_32_TRUNK_REG_SPARE1_PAGE_32_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_BITS 32
#define SWITCH_PAGE_32_TRUNK_REG_SPARE1_PAGE_32_TRUNK_REG_SPARE1_TRUNK_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_VLAN_CTRL0
 ***************************************************************************/
/* switch :: PAGE_34_VLAN_CTRL0 :: PAGE_34_VLAN_CTRL0_VLAN_EN [07:07] */
#define Wr_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_EN(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x80,7,x)
#define Rd_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_EN(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x80,7)
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_EN_MASK  0x80
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_EN_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_EN_BITS  1
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_EN_SHIFT 7

/* switch :: PAGE_34_VLAN_CTRL0 :: PAGE_34_VLAN_CTRL0_VLAN_LEARN_MODE [06:05] */
#define Wr_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_LEARN_MODE(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x60,5,x)
#define Rd_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_LEARN_MODE(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x60,5)
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_LEARN_MODE_MASK 0x60
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_LEARN_MODE_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_LEARN_MODE_BITS 2
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_VLAN_LEARN_MODE_SHIFT 5

/* switch :: PAGE_34_VLAN_CTRL0 :: PAGE_34_VLAN_CTRL0_RESERVED_1 [04:04] */
#define Wr_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x10,4,x)
#define Rd_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x10,4)
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_1_MASK 0x10
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_1_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_1_SHIFT 4

/* switch :: PAGE_34_VLAN_CTRL0 :: PAGE_34_VLAN_CTRL0_CHANGE_1Q_VID [03:03] */
#define Wr_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1Q_VID(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x8,3,x)
#define Rd_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1Q_VID(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x8,3)
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1Q_VID_MASK 0x08
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1Q_VID_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1Q_VID_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1Q_VID_SHIFT 3

/* switch :: PAGE_34_VLAN_CTRL0 :: PAGE_34_VLAN_CTRL0_RESERVED_0 [02:02] */
#define Wr_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x4,2,x)
#define Rd_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x4,2)
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_0_MASK 0x04
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_0_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_RESERVED_0_SHIFT 2

/* switch :: PAGE_34_VLAN_CTRL0 :: PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_OUTER [01:01] */
#define Wr_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_OUTER(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x2,1,x)
#define Rd_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_OUTER(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x2,1)
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_OUTER_MASK 0x02
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_OUTER_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_OUTER_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_OUTER_SHIFT 1

/* switch :: PAGE_34_VLAN_CTRL0 :: PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_INNER [00:00] */
#define Wr_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_INNER(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x1,0,x)
#define Rd_switch_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_INNER(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL0,0x1,0)
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_INNER_MASK 0x01
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_INNER_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_INNER_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL0_PAGE_34_VLAN_CTRL0_CHANGE_1P_VID_INNER_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_VLAN_CTRL1
 ***************************************************************************/
/* switch :: PAGE_34_VLAN_CTRL1 :: PAGE_34_VLAN_CTRL1_RESERVED_3 [07:07] */
#define Wr_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x80,7,x)
#define Rd_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x80,7)
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_3_MASK 0x80
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_3_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_3_SHIFT 7

/* switch :: PAGE_34_VLAN_CTRL1 :: PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG [06:06] */
#define Wr_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x40,6,x)
#define Rd_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x40,6)
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_MASK 0x40
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_UNTAG_SHIFT 6

/* switch :: PAGE_34_VLAN_CTRL1 :: PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP [05:05] */
#define Wr_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x20,5,x)
#define Rd_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x20,5)
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_MASK 0x20
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_IPMC_BYPASS_FWDMAP_SHIFT 5

/* switch :: PAGE_34_VLAN_CTRL1 :: PAGE_34_VLAN_CTRL1_RESERVED_2 [04:04] */
#define Wr_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x10,4,x)
#define Rd_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x10,4)
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_2_MASK 0x10
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_2_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_2_SHIFT 4

/* switch :: PAGE_34_VLAN_CTRL1 :: PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_UNTAG [03:03] */
#define Wr_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_UNTAG(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x8,3,x)
#define Rd_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_UNTAG(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x8,3)
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_MASK 0x08
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_UNTAG_SHIFT 3

/* switch :: PAGE_34_VLAN_CTRL1 :: PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP [02:02] */
#define Wr_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x4,2,x)
#define Rd_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x4,2)
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_MASK 0x04
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_EN_RSV_MCAST_FWDMAP_SHIFT 2

/* switch :: PAGE_34_VLAN_CTRL1 :: PAGE_34_VLAN_CTRL1_RESERVED_1 [01:01] */
#define Wr_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x2,1,x)
#define Rd_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x2,1)
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_1_MASK 0x02
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_1_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_1_SHIFT 1

/* switch :: PAGE_34_VLAN_CTRL1 :: PAGE_34_VLAN_CTRL1_RESERVED_0 [00:00] */
#define Wr_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x1,0,x)
#define Rd_switch_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL1,0x1,0)
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_0_MASK 0x01
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_0_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL1_PAGE_34_VLAN_CTRL1_RESERVED_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_VLAN_CTRL2
 ***************************************************************************/
/* switch :: PAGE_34_VLAN_CTRL2 :: PAGE_34_VLAN_CTRL2_RESERVED [07:07] */
#define Wr_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x80,7,x)
#define Rd_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x80,7)
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_MASK 0x80
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_SHIFT 7

/* switch :: PAGE_34_VLAN_CTRL2 :: PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP [06:06] */
#define Wr_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x40,6,x)
#define Rd_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x40,6)
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_MASK 0x40
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_UNTAG_MAP_SHIFT 6

/* switch :: PAGE_34_VLAN_CTRL2 :: PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP [05:05] */
#define Wr_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x20,5,x)
#define Rd_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x20,5)
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_MASK 0x20
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_GMRP_GVRP_V_FWDMAP_SHIFT 5

/* switch :: PAGE_34_VLAN_CTRL2 :: PAGE_34_VLAN_CTRL2_RESERVED_2 [04:03] */
#define Wr_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x18,3,x)
#define Rd_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x18,3)
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_2_MASK 0x18
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_2_BITS 2
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_2_SHIFT 3

/* switch :: PAGE_34_VLAN_CTRL2 :: PAGE_34_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP [02:02] */
#define Wr_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x4,2,x)
#define Rd_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x4,2)
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_MASK 0x04
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_EN_MIIM_BYPASS_V_FWDMAP_SHIFT 2

/* switch :: PAGE_34_VLAN_CTRL2 :: PAGE_34_VLAN_CTRL2_RESERVED_0 [01:00] */
#define Wr_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x3,0,x)
#define Rd_switch_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL2,0x3,0)
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_0_MASK 0x03
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_0_BITS 2
#define SWITCH_PAGE_34_VLAN_CTRL2_PAGE_34_VLAN_CTRL2_RESERVED_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_VLAN_CTRL3
 ***************************************************************************/
/* switch :: PAGE_34_VLAN_CTRL3 :: PAGE_34_VLAN_CTRL3_RESERVED [15:09] */
#define Wr_switch_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_CTRL3,0xfe00,9,x)
#define Rd_switch_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_CTRL3,0xfe00,9)
#define SWITCH_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_RESERVED_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_RESERVED_BITS 7
#define SWITCH_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_RESERVED_SHIFT 9

/* switch :: PAGE_34_VLAN_CTRL3 :: PAGE_34_VLAN_CTRL3_EN_DROP_NON1Q [08:00] */
#define Wr_switch_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_EN_DROP_NON1Q(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_CTRL3,0x1ff,0,x)
#define Rd_switch_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_EN_DROP_NON1Q(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_CTRL3,0x1ff,0)
#define SWITCH_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_EN_DROP_NON1Q_MASK 0x01ff
#define SWITCH_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_EN_DROP_NON1Q_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_EN_DROP_NON1Q_BITS 9
#define SWITCH_PAGE_34_VLAN_CTRL3_PAGE_34_VLAN_CTRL3_EN_DROP_NON1Q_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_VLAN_CTRL4
 ***************************************************************************/
/* switch :: PAGE_34_VLAN_CTRL4 :: PAGE_34_VLAN_CTRL4_INGR_VID_CHK [07:06] */
#define Wr_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_INGR_VID_CHK(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0xc0,6,x)
#define Rd_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_INGR_VID_CHK(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0xc0,6)
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_INGR_VID_CHK_MASK 0xc0
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_INGR_VID_CHK_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_INGR_VID_CHK_BITS 2
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_INGR_VID_CHK_SHIFT 6

/* switch :: PAGE_34_VLAN_CTRL4 :: PAGE_34_VLAN_CTRL4_EN_MGE_REV_GVRP [05:05] */
#define Wr_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GVRP(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0x20,5,x)
#define Rd_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GVRP(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0x20,5)
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GVRP_MASK 0x20
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GVRP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GVRP_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GVRP_SHIFT 5

/* switch :: PAGE_34_VLAN_CTRL4 :: PAGE_34_VLAN_CTRL4_EN_MGE_REV_GMRP [04:04] */
#define Wr_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GMRP(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0x10,4,x)
#define Rd_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GMRP(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0x10,4)
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GMRP_MASK 0x10
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GMRP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GMRP_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_MGE_REV_GMRP_SHIFT 4

/* switch :: PAGE_34_VLAN_CTRL4 :: PAGE_34_VLAN_CTRL4_EN_DOUBLE_TAG [03:02] */
#define Wr_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_DOUBLE_TAG(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0xc,2,x)
#define Rd_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_DOUBLE_TAG(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0xc,2)
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_DOUBLE_TAG_MASK 0x0c
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_DOUBLE_TAG_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_DOUBLE_TAG_BITS 2
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_EN_DOUBLE_TAG_SHIFT 2

/* switch :: PAGE_34_VLAN_CTRL4 :: PAGE_34_VLAN_CTRL4_RESV_MCAST_FLOOD [01:01] */
#define Wr_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESV_MCAST_FLOOD(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0x2,1,x)
#define Rd_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESV_MCAST_FLOOD(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0x2,1)
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESV_MCAST_FLOOD_MASK 0x02
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESV_MCAST_FLOOD_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESV_MCAST_FLOOD_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESV_MCAST_FLOOD_SHIFT 1

/* switch :: PAGE_34_VLAN_CTRL4 :: PAGE_34_VLAN_CTRL4_RESERVED_1 [00:00] */
#define Wr_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0x1,0,x)
#define Rd_switch_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL4,0x1,0)
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESERVED_1_MASK 0x01
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESERVED_1_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL4_PAGE_34_VLAN_CTRL4_RESERVED_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_VLAN_CTRL5
 ***************************************************************************/
/* switch :: PAGE_34_VLAN_CTRL5 :: PAGE_34_VLAN_CTRL5_RESERVED_2 [07:07] */
#define Wr_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x80,7,x)
#define Rd_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x80,7)
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_2_MASK 0x80
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_2_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_2_SHIFT 7

/* switch :: PAGE_34_VLAN_CTRL5 :: PAGE_34_VLAN_CTRL5_PRESV_NON1Q [06:06] */
#define Wr_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_PRESV_NON1Q(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x40,6,x)
#define Rd_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_PRESV_NON1Q(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x40,6)
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_PRESV_NON1Q_MASK 0x40
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_PRESV_NON1Q_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_PRESV_NON1Q_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_PRESV_NON1Q_SHIFT 6

/* switch :: PAGE_34_VLAN_CTRL5 :: PAGE_34_VLAN_CTRL5_RESERVED_1 [05:05] */
#define Wr_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x20,5,x)
#define Rd_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x20,5)
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_1_MASK 0x20
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_1_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_1_SHIFT 5

/* switch :: PAGE_34_VLAN_CTRL5 :: PAGE_34_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN [04:04] */
#define Wr_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x10,4,x)
#define Rd_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x10,4)
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_MASK 0x10
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EGRESS_DIR_FRM_BYPASS_TRUNK_EN_SHIFT 4

/* switch :: PAGE_34_VLAN_CTRL5 :: PAGE_34_VLAN_CTRL5_DROP_VTABLE_MISS [03:03] */
#define Wr_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_DROP_VTABLE_MISS(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x8,3,x)
#define Rd_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_DROP_VTABLE_MISS(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x8,3)
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_DROP_VTABLE_MISS_MASK 0x08
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_DROP_VTABLE_MISS_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_DROP_VTABLE_MISS_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_DROP_VTABLE_MISS_SHIFT 3

/* switch :: PAGE_34_VLAN_CTRL5 :: PAGE_34_VLAN_CTRL5_EN_VID_FFF_FWD [02:02] */
#define Wr_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_VID_FFF_FWD(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x4,2,x)
#define Rd_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_VID_FFF_FWD(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x4,2)
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_VID_FFF_FWD_MASK 0x04
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_VID_FFF_FWD_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_VID_FFF_FWD_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_VID_FFF_FWD_SHIFT 2

/* switch :: PAGE_34_VLAN_CTRL5 :: PAGE_34_VLAN_CTRL5_RESERVED_0 [01:01] */
#define Wr_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x2,1,x)
#define Rd_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x2,1)
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_0_MASK 0x02
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_0_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_RESERVED_0_SHIFT 1

/* switch :: PAGE_34_VLAN_CTRL5 :: PAGE_34_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK [00:00] */
#define Wr_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x1,0,x)
#define Rd_switch_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL5,0x1,0)
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_MASK 0x01
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL5_PAGE_34_VLAN_CTRL5_EN_CPU_RX_BYP_INNER_CRCCHK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_VLAN_CTRL6
 ***************************************************************************/
/* switch :: PAGE_34_VLAN_CTRL6 :: PAGE_34_VLAN_CTRL6_RESERVED_1 [07:05] */
#define Wr_switch_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL6,0xe0,5,x)
#define Rd_switch_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL6,0xe0,5)
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_1_MASK 0xe0
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_1_BITS 3
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_1_SHIFT 5

/* switch :: PAGE_34_VLAN_CTRL6 :: PAGE_34_VLAN_CTRL6_DIS_ARL_BUST_LMT [04:04] */
#define Wr_switch_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_DIS_ARL_BUST_LMT(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL6,0x10,4,x)
#define Rd_switch_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_DIS_ARL_BUST_LMT(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL6,0x10,4)
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_DIS_ARL_BUST_LMT_MASK 0x10
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_DIS_ARL_BUST_LMT_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_DIS_ARL_BUST_LMT_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_DIS_ARL_BUST_LMT_SHIFT 4

/* switch :: PAGE_34_VLAN_CTRL6 :: PAGE_34_VLAN_CTRL6_RESERVED_0 [03:01] */
#define Wr_switch_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL6,0xe,1,x)
#define Rd_switch_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL6,0xe,1)
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_0_MASK 0x0e
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_0_BITS 3
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_RESERVED_0_SHIFT 1

/* switch :: PAGE_34_VLAN_CTRL6 :: PAGE_34_VLAN_CTRL6_STRICT_SFD_DETECT [00:00] */
#define Wr_switch_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_STRICT_SFD_DETECT(x) WriteRegBits(SWITCH_PAGE_34_VLAN_CTRL6,0x1,0,x)
#define Rd_switch_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_STRICT_SFD_DETECT(x) ReadRegBits(SWITCH_PAGE_34_VLAN_CTRL6,0x1,0)
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_STRICT_SFD_DETECT_MASK 0x01
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_STRICT_SFD_DETECT_ALIGN 0
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_STRICT_SFD_DETECT_BITS 1
#define SWITCH_PAGE_34_VLAN_CTRL6_PAGE_34_VLAN_CTRL6_STRICT_SFD_DETECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL
 ***************************************************************************/
/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_RESERVED [15:12] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0xf000,12,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0xf000,12)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_RESERVED_MASK 0xf000
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_RESERVED_BITS 4
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_RESERVED_SHIFT 12

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP [11:11] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x800,11,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x800,11)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_MASK 0x0800
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_UTG_MAP_SHIFT 11

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP [10:10] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x400,10,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x400,10)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_MASK 0x0400
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT5_V_FWD_MAP_SHIFT 10

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP [09:09] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x200,9,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x200,9)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_MASK 0x0200
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_UTG_MAP_SHIFT 9

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP [08:08] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x100,8,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x100,8)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_MASK 0x0100
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT4_V_FWD_MAP_SHIFT 8

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP [07:07] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x80,7,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x80,7)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_MASK 0x0080
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_UTG_MAP_SHIFT 7

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP [06:06] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x40,6,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x40,6)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_MASK 0x0040
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT3_V_FWD_MAP_SHIFT 6

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP [05:05] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x20,5,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x20,5)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_MASK 0x0020
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_UTG_MAP_SHIFT 5

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP [04:04] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x10,4,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x10,4)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_MASK 0x0010
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT2_V_FWD_MAP_SHIFT 4

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP [03:03] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x8,3,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x8,3)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_MASK 0x0008
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_UTG_MAP_SHIFT 3

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP [02:02] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x4,2,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x4,2)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_MASK 0x0004
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT1_V_FWD_MAP_SHIFT 2

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP [01:01] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x2,1,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x2,1)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_MASK 0x0002
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_UTG_MAP_SHIFT 1

/* switch :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL :: PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP [00:00] */
#define Wr_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP(x) WriteRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x1,0,x)
#define Rd_switch_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP(x) ReadRegBits16(SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL,0x1,0)
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_MASK 0x0001
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_ALIGN 0
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_BITS 1
#define SWITCH_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_PAGE_34_VLAN_MULTI_PORT_ADDR_CTL_EN_MPORT0_V_FWD_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DEFAULT_1Q_TAG_port0
 ***************************************************************************/
/* switch :: PAGE_34_DEFAULT_1Q_TAG_port0 :: PAGE_34_DEFAULT_1Q_TAG_PRI_0 [15:13] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port0_PAGE_34_DEFAULT_1Q_TAG_PRI_0(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0,0xe000,13,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port0_PAGE_34_DEFAULT_1Q_TAG_PRI_0(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0,0xe000,13)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_PRI_0_MASK 0xe000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_PRI_0_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_PRI_0_BITS 3
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_PRI_0_SHIFT 13

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port0 :: PAGE_34_DEFAULT_1Q_TAG_CFI_0 [12:12] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port0_PAGE_34_DEFAULT_1Q_TAG_CFI_0(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0,0x1000,12,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port0_PAGE_34_DEFAULT_1Q_TAG_CFI_0(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0,0x1000,12)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_CFI_0_MASK 0x1000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_CFI_0_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_CFI_0_BITS 1
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_CFI_0_SHIFT 12

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port0 :: PAGE_34_DEFAULT_1Q_TAG_VID_0 [11:00] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port0_PAGE_34_DEFAULT_1Q_TAG_VID_0(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0,0xfff,0,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port0_PAGE_34_DEFAULT_1Q_TAG_VID_0(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0,0xfff,0)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_VID_0_MASK 0x0fff
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_VID_0_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_VID_0_BITS 12
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT0_PAGE_34_DEFAULT_1Q_TAG_VID_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DEFAULT_1Q_TAG_port1
 ***************************************************************************/
/* switch :: PAGE_34_DEFAULT_1Q_TAG_port1 :: PAGE_34_DEFAULT_1Q_TAG_PRI_1 [15:13] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port1_PAGE_34_DEFAULT_1Q_TAG_PRI_1(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1,0xe000,13,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port1_PAGE_34_DEFAULT_1Q_TAG_PRI_1(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1,0xe000,13)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_PRI_1_MASK 0xe000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_PRI_1_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_PRI_1_BITS 3
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_PRI_1_SHIFT 13

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port1 :: PAGE_34_DEFAULT_1Q_TAG_CFI_1 [12:12] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port1_PAGE_34_DEFAULT_1Q_TAG_CFI_1(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1,0x1000,12,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port1_PAGE_34_DEFAULT_1Q_TAG_CFI_1(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1,0x1000,12)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_CFI_1_MASK 0x1000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_CFI_1_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_CFI_1_BITS 1
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_CFI_1_SHIFT 12

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port1 :: PAGE_34_DEFAULT_1Q_TAG_VID_1 [11:00] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port1_PAGE_34_DEFAULT_1Q_TAG_VID_1(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1,0xfff,0,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port1_PAGE_34_DEFAULT_1Q_TAG_VID_1(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1,0xfff,0)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_VID_1_MASK 0x0fff
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_VID_1_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_VID_1_BITS 12
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT1_PAGE_34_DEFAULT_1Q_TAG_VID_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DEFAULT_1Q_TAG_port2
 ***************************************************************************/
/* switch :: PAGE_34_DEFAULT_1Q_TAG_port2 :: PAGE_34_DEFAULT_1Q_TAG_PRI_2 [15:13] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port2_PAGE_34_DEFAULT_1Q_TAG_PRI_2(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2,0xe000,13,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port2_PAGE_34_DEFAULT_1Q_TAG_PRI_2(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2,0xe000,13)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_PRI_2_MASK 0xe000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_PRI_2_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_PRI_2_BITS 3
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_PRI_2_SHIFT 13

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port2 :: PAGE_34_DEFAULT_1Q_TAG_CFI_2 [12:12] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port2_PAGE_34_DEFAULT_1Q_TAG_CFI_2(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2,0x1000,12,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port2_PAGE_34_DEFAULT_1Q_TAG_CFI_2(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2,0x1000,12)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_CFI_2_MASK 0x1000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_CFI_2_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_CFI_2_BITS 1
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_CFI_2_SHIFT 12

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port2 :: PAGE_34_DEFAULT_1Q_TAG_VID_2 [11:00] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port2_PAGE_34_DEFAULT_1Q_TAG_VID_2(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2,0xfff,0,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port2_PAGE_34_DEFAULT_1Q_TAG_VID_2(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2,0xfff,0)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_VID_2_MASK 0x0fff
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_VID_2_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_VID_2_BITS 12
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT2_PAGE_34_DEFAULT_1Q_TAG_VID_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DEFAULT_1Q_TAG_port3
 ***************************************************************************/
/* switch :: PAGE_34_DEFAULT_1Q_TAG_port3 :: PAGE_34_DEFAULT_1Q_TAG_PRI_3 [15:13] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port3_PAGE_34_DEFAULT_1Q_TAG_PRI_3(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3,0xe000,13,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port3_PAGE_34_DEFAULT_1Q_TAG_PRI_3(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3,0xe000,13)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_PRI_3_MASK 0xe000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_PRI_3_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_PRI_3_BITS 3
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_PRI_3_SHIFT 13

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port3 :: PAGE_34_DEFAULT_1Q_TAG_CFI_3 [12:12] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port3_PAGE_34_DEFAULT_1Q_TAG_CFI_3(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3,0x1000,12,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port3_PAGE_34_DEFAULT_1Q_TAG_CFI_3(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3,0x1000,12)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_CFI_3_MASK 0x1000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_CFI_3_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_CFI_3_BITS 1
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_CFI_3_SHIFT 12

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port3 :: PAGE_34_DEFAULT_1Q_TAG_VID_3 [11:00] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port3_PAGE_34_DEFAULT_1Q_TAG_VID_3(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3,0xfff,0,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port3_PAGE_34_DEFAULT_1Q_TAG_VID_3(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3,0xfff,0)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_VID_3_MASK 0x0fff
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_VID_3_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_VID_3_BITS 12
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT3_PAGE_34_DEFAULT_1Q_TAG_VID_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DEFAULT_1Q_TAG_port4
 ***************************************************************************/
/* switch :: PAGE_34_DEFAULT_1Q_TAG_port4 :: PAGE_34_DEFAULT_1Q_TAG_PRI_4 [15:13] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port4_PAGE_34_DEFAULT_1Q_TAG_PRI_4(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4,0xe000,13,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port4_PAGE_34_DEFAULT_1Q_TAG_PRI_4(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4,0xe000,13)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_PRI_4_MASK 0xe000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_PRI_4_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_PRI_4_BITS 3
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_PRI_4_SHIFT 13

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port4 :: PAGE_34_DEFAULT_1Q_TAG_CFI_4 [12:12] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port4_PAGE_34_DEFAULT_1Q_TAG_CFI_4(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4,0x1000,12,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port4_PAGE_34_DEFAULT_1Q_TAG_CFI_4(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4,0x1000,12)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_CFI_4_MASK 0x1000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_CFI_4_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_CFI_4_BITS 1
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_CFI_4_SHIFT 12

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port4 :: PAGE_34_DEFAULT_1Q_TAG_VID_4 [11:00] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port4_PAGE_34_DEFAULT_1Q_TAG_VID_4(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4,0xfff,0,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port4_PAGE_34_DEFAULT_1Q_TAG_VID_4(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4,0xfff,0)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_VID_4_MASK 0x0fff
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_VID_4_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_VID_4_BITS 12
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT4_PAGE_34_DEFAULT_1Q_TAG_VID_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DEFAULT_1Q_TAG_port5
 ***************************************************************************/
/* switch :: PAGE_34_DEFAULT_1Q_TAG_port5 :: PAGE_34_DEFAULT_1Q_TAG_PRI_5 [15:13] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port5_PAGE_34_DEFAULT_1Q_TAG_PRI_5(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5,0xe000,13,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port5_PAGE_34_DEFAULT_1Q_TAG_PRI_5(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5,0xe000,13)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_PRI_5_MASK 0xe000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_PRI_5_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_PRI_5_BITS 3
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_PRI_5_SHIFT 13

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port5 :: PAGE_34_DEFAULT_1Q_TAG_CFI_5 [12:12] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port5_PAGE_34_DEFAULT_1Q_TAG_CFI_5(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5,0x1000,12,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port5_PAGE_34_DEFAULT_1Q_TAG_CFI_5(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5,0x1000,12)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_CFI_5_MASK 0x1000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_CFI_5_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_CFI_5_BITS 1
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_CFI_5_SHIFT 12

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port5 :: PAGE_34_DEFAULT_1Q_TAG_VID_5 [11:00] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port5_PAGE_34_DEFAULT_1Q_TAG_VID_5(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5,0xfff,0,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port5_PAGE_34_DEFAULT_1Q_TAG_VID_5(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5,0xfff,0)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_VID_5_MASK 0x0fff
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_VID_5_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_VID_5_BITS 12
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT5_PAGE_34_DEFAULT_1Q_TAG_VID_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DEFAULT_1Q_TAG_port6
 ***************************************************************************/
/* switch :: PAGE_34_DEFAULT_1Q_TAG_port6 :: PAGE_34_DEFAULT_1Q_TAG_PRI_6 [15:13] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port6_PAGE_34_DEFAULT_1Q_TAG_PRI_6(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6,0xe000,13,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port6_PAGE_34_DEFAULT_1Q_TAG_PRI_6(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6,0xe000,13)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_PRI_6_MASK 0xe000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_PRI_6_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_PRI_6_BITS 3
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_PRI_6_SHIFT 13

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port6 :: PAGE_34_DEFAULT_1Q_TAG_CFI_6 [12:12] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port6_PAGE_34_DEFAULT_1Q_TAG_CFI_6(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6,0x1000,12,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port6_PAGE_34_DEFAULT_1Q_TAG_CFI_6(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6,0x1000,12)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_CFI_6_MASK 0x1000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_CFI_6_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_CFI_6_BITS 1
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_CFI_6_SHIFT 12

/* switch :: PAGE_34_DEFAULT_1Q_TAG_port6 :: PAGE_34_DEFAULT_1Q_TAG_VID_6 [11:00] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_port6_PAGE_34_DEFAULT_1Q_TAG_VID_6(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6,0xfff,0,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_port6_PAGE_34_DEFAULT_1Q_TAG_VID_6(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6,0xfff,0)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_VID_6_MASK 0x0fff
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_VID_6_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_VID_6_BITS 12
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_PORT6_PAGE_34_DEFAULT_1Q_TAG_VID_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DEFAULT_1Q_TAG_P7
 ***************************************************************************/
/* switch :: PAGE_34_DEFAULT_1Q_TAG_P7 :: PAGE_34_DEFAULT_1Q_TAG_P7_PRI [15:13] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_PRI(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7,0xe000,13,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_PRI(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7,0xe000,13)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_PRI_MASK 0xe000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_PRI_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_PRI_BITS 3
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_PRI_SHIFT 13

/* switch :: PAGE_34_DEFAULT_1Q_TAG_P7 :: PAGE_34_DEFAULT_1Q_TAG_P7_CFI [12:12] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_CFI(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7,0x1000,12,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_CFI(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7,0x1000,12)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_CFI_MASK 0x1000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_CFI_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_CFI_BITS 1
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_CFI_SHIFT 12

/* switch :: PAGE_34_DEFAULT_1Q_TAG_P7 :: PAGE_34_DEFAULT_1Q_TAG_P7_VID [11:00] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_VID(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7,0xfff,0,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_VID(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7,0xfff,0)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_VID_MASK 0x0fff
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_VID_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_VID_BITS 12
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_P7_PAGE_34_DEFAULT_1Q_TAG_P7_VID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DEFAULT_1Q_TAG_IMP
 ***************************************************************************/
/* switch :: PAGE_34_DEFAULT_1Q_TAG_IMP :: PAGE_34_DEFAULT_1Q_TAG_IMP_PRI [15:13] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_PRI(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP,0xe000,13,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_PRI(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP,0xe000,13)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_PRI_MASK 0xe000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_PRI_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_PRI_BITS 3
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_PRI_SHIFT 13

/* switch :: PAGE_34_DEFAULT_1Q_TAG_IMP :: PAGE_34_DEFAULT_1Q_TAG_IMP_CFI [12:12] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_CFI(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP,0x1000,12,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_CFI(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP,0x1000,12)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_CFI_MASK 0x1000
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_CFI_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_CFI_BITS 1
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_CFI_SHIFT 12

/* switch :: PAGE_34_DEFAULT_1Q_TAG_IMP :: PAGE_34_DEFAULT_1Q_TAG_IMP_VID [11:00] */
#define Wr_switch_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_VID(x) WriteRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP,0xfff,0,x)
#define Rd_switch_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_VID(x) ReadRegBits16(SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP,0xfff,0)
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_VID_MASK 0x0fff
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_VID_ALIGN 0
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_VID_BITS 12
#define SWITCH_PAGE_34_DEFAULT_1Q_TAG_IMP_PAGE_34_DEFAULT_1Q_TAG_IMP_VID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_DTAG_TPID
 ***************************************************************************/
/* switch :: PAGE_34_DTAG_TPID :: PAGE_34_DTAG_TPID_ISP_TPID [15:00] */
#define Wr_switch_PAGE_34_DTAG_TPID_PAGE_34_DTAG_TPID_ISP_TPID(x) WriteReg16(SWITCH_PAGE_34_DTAG_TPID,x)
#define Rd_switch_PAGE_34_DTAG_TPID_PAGE_34_DTAG_TPID_ISP_TPID(x) ReadReg16(SWITCH_PAGE_34_DTAG_TPID)
#define SWITCH_PAGE_34_DTAG_TPID_PAGE_34_DTAG_TPID_ISP_TPID_MASK   0xffff
#define SWITCH_PAGE_34_DTAG_TPID_PAGE_34_DTAG_TPID_ISP_TPID_ALIGN  0
#define SWITCH_PAGE_34_DTAG_TPID_PAGE_34_DTAG_TPID_ISP_TPID_BITS   16
#define SWITCH_PAGE_34_DTAG_TPID_PAGE_34_DTAG_TPID_ISP_TPID_SHIFT  0


/****************************************************************************
 * switch :: PAGE_34_ISP_SEL_PORTMAP
 ***************************************************************************/
/* switch :: PAGE_34_ISP_SEL_PORTMAP :: PAGE_34_ISP_SEL_PORTMAP_RESERVED [15:09] */
#define Wr_switch_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_34_ISP_SEL_PORTMAP,0xfe00,9,x)
#define Rd_switch_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_34_ISP_SEL_PORTMAP,0xfe00,9)
#define SWITCH_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_RESERVED_BITS 7
#define SWITCH_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_RESERVED_SHIFT 9

/* switch :: PAGE_34_ISP_SEL_PORTMAP :: PAGE_34_ISP_SEL_PORTMAP_ISP_PORTMAP [08:00] */
#define Wr_switch_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_ISP_PORTMAP(x) WriteRegBits16(SWITCH_PAGE_34_ISP_SEL_PORTMAP,0x1ff,0,x)
#define Rd_switch_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_ISP_PORTMAP(x) ReadRegBits16(SWITCH_PAGE_34_ISP_SEL_PORTMAP,0x1ff,0)
#define SWITCH_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_ISP_PORTMAP_MASK 0x01ff
#define SWITCH_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_ISP_PORTMAP_ALIGN 0
#define SWITCH_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_ISP_PORTMAP_BITS 9
#define SWITCH_PAGE_34_ISP_SEL_PORTMAP_PAGE_34_ISP_SEL_PORTMAP_ISP_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_EGRESS_VID_RMK_TBL_ACS
 ***************************************************************************/
/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_ACS :: PAGE_34_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN [31:31] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x80000000,31,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x80000000,31)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_MASK 0x80000000
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_BITS 1
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_GLOBAL_WR_EN_SHIFT 31

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_ACS :: PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED1 [30:16] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED1(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x7fff0000,16,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED1(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x7fff0000,16)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED1_MASK 0x7fff0000
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED1_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED1_BITS 15
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED1_SHIFT 16

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_ACS :: PAGE_34_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR [15:08] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0xff00,8,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0xff00,8)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_MASK 0x0000ff00
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_BITS 8
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_TBL_ADDR_SHIFT 8

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_ACS :: PAGE_34_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT [07:04] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0xf0,4,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0xf0,4)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_MASK 0x000000f0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_BITS 4
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_EGRESS_PORT_SHIFT 4

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_ACS :: PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED2 [03:03] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED2(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x8,3,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED2(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x8,3)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED2_MASK 0x00000008
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED2_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED2_BITS 1
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESERVED2_SHIFT 3

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_ACS :: PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESET_EVT [02:02] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESET_EVT(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x4,2,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESET_EVT(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x4,2)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_MASK 0x00000004
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_BITS 1
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_RESET_EVT_SHIFT 2

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_ACS :: PAGE_34_EGRESS_VID_RMK_TBL_ACS_OP [01:01] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_OP(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x2,1,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_OP(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x2,1)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_OP_MASK 0x00000002
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_OP_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_OP_BITS 1
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_OP_SHIFT 1

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_ACS :: PAGE_34_EGRESS_VID_RMK_TBL_ACS_START_DONE [00:00] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_START_DONE(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x1,0,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_START_DONE(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS,0x1,0)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_START_DONE_MASK 0x00000001
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_START_DONE_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_START_DONE_BITS 1
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_ACS_PAGE_34_EGRESS_VID_RMK_TBL_ACS_START_DONE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_EGRESS_VID_RMK_TBL_DATA
 ***************************************************************************/
/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_DATA :: PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED1 [31:30] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED1(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0xc0000000,30,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED1(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0xc0000000,30)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED1_MASK 0xc0000000
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED1_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED1_BITS 2
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED1_SHIFT 30

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_DATA :: PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_OP [29:28] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_OP(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0x30000000,28,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_OP(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0x30000000,28)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_MASK 0x30000000
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_BITS 2
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_OP_SHIFT 28

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_DATA :: PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_VID [27:16] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_VID(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0xfff0000,16,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_VID(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0xfff0000,16)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_MASK 0x0fff0000
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_BITS 12
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_OUTER_VID_SHIFT 16

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_DATA :: PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED2 [15:14] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED2(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0xc000,14,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED2(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0xc000,14)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED2_MASK 0x0000c000
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED2_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED2_BITS 2
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_RESERVED2_SHIFT 14

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_DATA :: PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_OP [13:12] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_OP(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0x3000,12,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_OP(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0x3000,12)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_OP_MASK 0x00003000
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_OP_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_OP_BITS 2
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_OP_SHIFT 12

/* switch :: PAGE_34_EGRESS_VID_RMK_TBL_DATA :: PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_VID [11:00] */
#define Wr_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_VID(x) WriteRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0xfff,0,x)
#define Rd_switch_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_VID(x) ReadRegBits(SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA,0xfff,0)
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_VID_MASK 0x00000fff
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_VID_ALIGN 0
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_VID_BITS 12
#define SWITCH_PAGE_34_EGRESS_VID_RMK_TBL_DATA_PAGE_34_EGRESS_VID_RMK_TBL_DATA_INNER_VID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_JOIN_ALL_VLAN_EN
 ***************************************************************************/
/* switch :: PAGE_34_JOIN_ALL_VLAN_EN :: PAGE_34_JOIN_ALL_VLAN_EN_RESERVED [15:09] */
#define Wr_switch_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_34_JOIN_ALL_VLAN_EN,0xfe00,9,x)
#define Rd_switch_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_34_JOIN_ALL_VLAN_EN,0xfe00,9)
#define SWITCH_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_RESERVED_ALIGN 0
#define SWITCH_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_RESERVED_BITS 7
#define SWITCH_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_RESERVED_SHIFT 9

/* switch :: PAGE_34_JOIN_ALL_VLAN_EN :: PAGE_34_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN [08:00] */
#define Wr_switch_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN(x) WriteRegBits16(SWITCH_PAGE_34_JOIN_ALL_VLAN_EN,0x1ff,0,x)
#define Rd_switch_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN(x) ReadRegBits16(SWITCH_PAGE_34_JOIN_ALL_VLAN_EN,0x1ff,0)
#define SWITCH_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_MASK 0x01ff
#define SWITCH_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_ALIGN 0
#define SWITCH_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_BITS 9
#define SWITCH_PAGE_34_JOIN_ALL_VLAN_EN_PAGE_34_JOIN_ALL_VLAN_EN_JOIN_ALL_VLAN_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_PORT_IVL_SVL_CTRL
 ***************************************************************************/
/* switch :: PAGE_34_PORT_IVL_SVL_CTRL :: PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN [15:15] */
#define Wr_switch_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN(x) WriteRegBits16(SWITCH_PAGE_34_PORT_IVL_SVL_CTRL,0x8000,15,x)
#define Rd_switch_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN(x) ReadRegBits16(SWITCH_PAGE_34_PORT_IVL_SVL_CTRL,0x8000,15)
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_MASK 0x8000
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_ALIGN 0
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_BITS 1
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_EN_SHIFT 15

/* switch :: PAGE_34_PORT_IVL_SVL_CTRL :: PAGE_34_PORT_IVL_SVL_CTRL_RESERVED [14:09] */
#define Wr_switch_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_34_PORT_IVL_SVL_CTRL,0x7e00,9,x)
#define Rd_switch_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_34_PORT_IVL_SVL_CTRL,0x7e00,9)
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_RESERVED_MASK 0x7e00
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_RESERVED_BITS 6
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_RESERVED_SHIFT 9

/* switch :: PAGE_34_PORT_IVL_SVL_CTRL :: PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL [08:00] */
#define Wr_switch_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL(x) WriteRegBits16(SWITCH_PAGE_34_PORT_IVL_SVL_CTRL,0x1ff,0,x)
#define Rd_switch_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL(x) ReadRegBits16(SWITCH_PAGE_34_PORT_IVL_SVL_CTRL,0x1ff,0)
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_MASK 0x01ff
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_ALIGN 0
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_BITS 9
#define SWITCH_PAGE_34_PORT_IVL_SVL_CTRL_PAGE_34_PORT_IVL_SVL_CTRL_PORT_IVL_SVL_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_BCM8021Q_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_34_BCM8021Q_REG_SPARE0 :: PAGE_34_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_34_BCM8021Q_REG_SPARE0_PAGE_34_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0(x) WriteReg(SWITCH_PAGE_34_BCM8021Q_REG_SPARE0,x)
#define Rd_switch_PAGE_34_BCM8021Q_REG_SPARE0_PAGE_34_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0(x) ReadReg(SWITCH_PAGE_34_BCM8021Q_REG_SPARE0)
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE0_PAGE_34_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE0_PAGE_34_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE0_PAGE_34_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_BITS 32
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE0_PAGE_34_BCM8021Q_REG_SPARE0_BCM8021Q_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_34_BCM8021Q_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_34_BCM8021Q_REG_SPARE1 :: PAGE_34_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_34_BCM8021Q_REG_SPARE1_PAGE_34_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1(x) WriteReg(SWITCH_PAGE_34_BCM8021Q_REG_SPARE1,x)
#define Rd_switch_PAGE_34_BCM8021Q_REG_SPARE1_PAGE_34_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1(x) ReadReg(SWITCH_PAGE_34_BCM8021Q_REG_SPARE1)
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE1_PAGE_34_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE1_PAGE_34_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE1_PAGE_34_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_BITS 32
#define SWITCH_PAGE_34_BCM8021Q_REG_SPARE1_PAGE_34_BCM8021Q_REG_SPARE1_BCM8021Q_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_36_DOS_CTRL
 ***************************************************************************/
/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_RESERVED_1 [31:14] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0xffffc000,14,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0xffffc000,14)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_1_MASK   0xffffc000
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_1_ALIGN  0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_1_BITS   18
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_1_SHIFT  14

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN [13:13] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x2000,13,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x2000,13)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_MASK 0x00002000
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_LONG_PING_DROP_EN_SHIFT 13

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN [12:12] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x1000,12,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x1000,12)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_MASK 0x00001000
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_LONG_PING_DROP_EN_SHIFT 12

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN [11:11] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x800,11,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x800,11)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_MASK 0x00000800
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV6_FRAGMENT_DROP_EN_SHIFT 11

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN [10:10] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x400,10,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x400,10)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_MASK 0x00000400
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_ICMPV4_FRAGMENT_DROP_EN_SHIFT 10

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_TCP_FRAG_ERR_DROP_EN [09:09] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_FRAG_ERR_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x200,9,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_FRAG_ERR_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x200,9)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_MASK 0x00000200
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_FRAG_ERR_DROP_EN_SHIFT 9

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_TCP_SHORT_HDR_DROP_EN [08:08] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SHORT_HDR_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x100,8,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SHORT_HDR_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x100,8)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_MASK 0x00000100
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SHORT_HDR_DROP_EN_SHIFT 8

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_TCP_SYN_ERR_DROP_EN [07:07] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYN_ERR_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x80,7,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYN_ERR_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x80,7)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYN_ERR_DROP_EN_MASK 0x00000080
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYN_ERR_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYN_ERR_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYN_ERR_DROP_EN_SHIFT 7

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN [06:06] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x40,6,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x40,6)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_MASK 0x00000040
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_SYNFIN_SCAN_DROP_EN_SHIFT 6

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN [05:05] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x20,5,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x20,5)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_MASK 0x00000020
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_XMASS_SCAN_DROP_EN_SHIFT 5

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_TCP_NULL_SCAN_DROP_EN [04:04] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_NULL_SCAN_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x10,4,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_NULL_SCAN_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x10,4)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_MASK 0x00000010
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_NULL_SCAN_DROP_EN_SHIFT 4

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_UDP_BLAT_DROP_EN [03:03] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_UDP_BLAT_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x8,3,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_UDP_BLAT_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x8,3)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_UDP_BLAT_DROP_EN_MASK 0x00000008
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_UDP_BLAT_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_UDP_BLAT_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_UDP_BLAT_DROP_EN_SHIFT 3

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_TCP_BLAT_DROP_EN [02:02] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_BLAT_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x4,2,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_BLAT_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x4,2)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_BLAT_DROP_EN_MASK 0x00000004
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_BLAT_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_BLAT_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_TCP_BLAT_DROP_EN_SHIFT 2

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_IP_LAND_DROP_EN [01:01] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_IP_LAND_DROP_EN(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x2,1,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_IP_LAND_DROP_EN(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x2,1)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_IP_LAND_DROP_EN_MASK 0x00000002
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_IP_LAND_DROP_EN_ALIGN 0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_IP_LAND_DROP_EN_BITS 1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_IP_LAND_DROP_EN_SHIFT 1

/* switch :: PAGE_36_DOS_CTRL :: PAGE_36_DOS_CTRL_RESERVED_0 [00:00] */
#define Wr_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_36_DOS_CTRL,0x1,0,x)
#define Rd_switch_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_36_DOS_CTRL,0x1,0)
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_0_MASK   0x00000001
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_0_ALIGN  0
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_0_BITS   1
#define SWITCH_PAGE_36_DOS_CTRL_PAGE_36_DOS_CTRL_RESERVED_0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_36_MINIMUM_TCP_HDR_SZ
 ***************************************************************************/
/* switch :: PAGE_36_MINIMUM_TCP_HDR_SZ :: PAGE_36_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ [07:00] */
#define Wr_switch_PAGE_36_MINIMUM_TCP_HDR_SZ_PAGE_36_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ(x) WriteReg(SWITCH_PAGE_36_MINIMUM_TCP_HDR_SZ,x)
#define Rd_switch_PAGE_36_MINIMUM_TCP_HDR_SZ_PAGE_36_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ(x) ReadReg(SWITCH_PAGE_36_MINIMUM_TCP_HDR_SZ)
#define SWITCH_PAGE_36_MINIMUM_TCP_HDR_SZ_PAGE_36_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_MASK 0xff
#define SWITCH_PAGE_36_MINIMUM_TCP_HDR_SZ_PAGE_36_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_ALIGN 0
#define SWITCH_PAGE_36_MINIMUM_TCP_HDR_SZ_PAGE_36_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_BITS 8
#define SWITCH_PAGE_36_MINIMUM_TCP_HDR_SZ_PAGE_36_MINIMUM_TCP_HDR_SZ_MIN_TCP_HDR_SZ_SHIFT 0


/****************************************************************************
 * switch :: PAGE_36_MAX_ICMPV4_SIZE_REG
 ***************************************************************************/
/* switch :: PAGE_36_MAX_ICMPV4_SIZE_REG :: PAGE_36_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE [31:00] */
#define Wr_switch_PAGE_36_MAX_ICMPV4_SIZE_REG_PAGE_36_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE(x) WriteReg(SWITCH_PAGE_36_MAX_ICMPV4_SIZE_REG,x)
#define Rd_switch_PAGE_36_MAX_ICMPV4_SIZE_REG_PAGE_36_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE(x) ReadReg(SWITCH_PAGE_36_MAX_ICMPV4_SIZE_REG)
#define SWITCH_PAGE_36_MAX_ICMPV4_SIZE_REG_PAGE_36_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_MASK 0xffffffff
#define SWITCH_PAGE_36_MAX_ICMPV4_SIZE_REG_PAGE_36_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_ALIGN 0
#define SWITCH_PAGE_36_MAX_ICMPV4_SIZE_REG_PAGE_36_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_BITS 32
#define SWITCH_PAGE_36_MAX_ICMPV4_SIZE_REG_PAGE_36_MAX_ICMPV4_SIZE_REG_MAX_ICMPV4_SIZE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_36_MAX_ICMPV6_SIZE_REG
 ***************************************************************************/
/* switch :: PAGE_36_MAX_ICMPV6_SIZE_REG :: PAGE_36_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE [31:00] */
#define Wr_switch_PAGE_36_MAX_ICMPV6_SIZE_REG_PAGE_36_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE(x) WriteReg(SWITCH_PAGE_36_MAX_ICMPV6_SIZE_REG,x)
#define Rd_switch_PAGE_36_MAX_ICMPV6_SIZE_REG_PAGE_36_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE(x) ReadReg(SWITCH_PAGE_36_MAX_ICMPV6_SIZE_REG)
#define SWITCH_PAGE_36_MAX_ICMPV6_SIZE_REG_PAGE_36_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_MASK 0xffffffff
#define SWITCH_PAGE_36_MAX_ICMPV6_SIZE_REG_PAGE_36_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_ALIGN 0
#define SWITCH_PAGE_36_MAX_ICMPV6_SIZE_REG_PAGE_36_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_BITS 32
#define SWITCH_PAGE_36_MAX_ICMPV6_SIZE_REG_PAGE_36_MAX_ICMPV6_SIZE_REG_MAX_ICMPV6_SIZE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_36_DOS_DIS_LRN_REG
 ***************************************************************************/
/* switch :: PAGE_36_DOS_DIS_LRN_REG :: PAGE_36_DOS_DIS_LRN_REG_RESERVED [07:01] */
#define Wr_switch_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_RESERVED(x) WriteRegBits(SWITCH_PAGE_36_DOS_DIS_LRN_REG,0xfe,1,x)
#define Rd_switch_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_RESERVED(x) ReadRegBits(SWITCH_PAGE_36_DOS_DIS_LRN_REG,0xfe,1)
#define SWITCH_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_RESERVED_MASK 0xfe
#define SWITCH_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_RESERVED_ALIGN 0
#define SWITCH_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_RESERVED_BITS 7
#define SWITCH_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_RESERVED_SHIFT 1

/* switch :: PAGE_36_DOS_DIS_LRN_REG :: PAGE_36_DOS_DIS_LRN_REG_DOS_DIS_LRN [00:00] */
#define Wr_switch_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_DOS_DIS_LRN(x) WriteRegBits(SWITCH_PAGE_36_DOS_DIS_LRN_REG,0x1,0,x)
#define Rd_switch_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_DOS_DIS_LRN(x) ReadRegBits(SWITCH_PAGE_36_DOS_DIS_LRN_REG,0x1,0)
#define SWITCH_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_DOS_DIS_LRN_MASK 0x01
#define SWITCH_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_DOS_DIS_LRN_ALIGN 0
#define SWITCH_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_DOS_DIS_LRN_BITS 1
#define SWITCH_PAGE_36_DOS_DIS_LRN_REG_PAGE_36_DOS_DIS_LRN_REG_DOS_DIS_LRN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_36_DOS_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_36_DOS_REG_SPARE0 :: PAGE_36_DOS_REG_SPARE0_DOS_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_36_DOS_REG_SPARE0_PAGE_36_DOS_REG_SPARE0_DOS_REG_SPARE0(x) WriteReg(SWITCH_PAGE_36_DOS_REG_SPARE0,x)
#define Rd_switch_PAGE_36_DOS_REG_SPARE0_PAGE_36_DOS_REG_SPARE0_DOS_REG_SPARE0(x) ReadReg(SWITCH_PAGE_36_DOS_REG_SPARE0)
#define SWITCH_PAGE_36_DOS_REG_SPARE0_PAGE_36_DOS_REG_SPARE0_DOS_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_36_DOS_REG_SPARE0_PAGE_36_DOS_REG_SPARE0_DOS_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_36_DOS_REG_SPARE0_PAGE_36_DOS_REG_SPARE0_DOS_REG_SPARE0_BITS 32
#define SWITCH_PAGE_36_DOS_REG_SPARE0_PAGE_36_DOS_REG_SPARE0_DOS_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_36_DOS_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_36_DOS_REG_SPARE1 :: PAGE_36_DOS_REG_SPARE1_DOS_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_36_DOS_REG_SPARE1_PAGE_36_DOS_REG_SPARE1_DOS_REG_SPARE1(x) WriteReg(SWITCH_PAGE_36_DOS_REG_SPARE1,x)
#define Rd_switch_PAGE_36_DOS_REG_SPARE1_PAGE_36_DOS_REG_SPARE1_DOS_REG_SPARE1(x) ReadReg(SWITCH_PAGE_36_DOS_REG_SPARE1)
#define SWITCH_PAGE_36_DOS_REG_SPARE1_PAGE_36_DOS_REG_SPARE1_DOS_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_36_DOS_REG_SPARE1_PAGE_36_DOS_REG_SPARE1_DOS_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_36_DOS_REG_SPARE1_PAGE_36_DOS_REG_SPARE1_DOS_REG_SPARE1_BITS 32
#define SWITCH_PAGE_36_DOS_REG_SPARE1_PAGE_36_DOS_REG_SPARE1_DOS_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_40_JUMBO_PORT_MASK
 ***************************************************************************/
/* switch :: PAGE_40_JUMBO_PORT_MASK :: PAGE_40_JUMBO_PORT_MASK_RESERVED_1 [31:25] */
#define Wr_switch_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_40_JUMBO_PORT_MASK,0xfe000000,25,x)
#define Rd_switch_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_40_JUMBO_PORT_MASK,0xfe000000,25)
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_1_MASK 0xfe000000
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_1_BITS 7
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_1_SHIFT 25

/* switch :: PAGE_40_JUMBO_PORT_MASK :: PAGE_40_JUMBO_PORT_MASK_EN_10_100_JUMBO [24:24] */
#define Wr_switch_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_EN_10_100_JUMBO(x) WriteRegBits(SWITCH_PAGE_40_JUMBO_PORT_MASK,0x1000000,24,x)
#define Rd_switch_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_EN_10_100_JUMBO(x) ReadRegBits(SWITCH_PAGE_40_JUMBO_PORT_MASK,0x1000000,24)
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_EN_10_100_JUMBO_MASK 0x01000000
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_EN_10_100_JUMBO_ALIGN 0
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_EN_10_100_JUMBO_BITS 1
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_EN_10_100_JUMBO_SHIFT 24

/* switch :: PAGE_40_JUMBO_PORT_MASK :: PAGE_40_JUMBO_PORT_MASK_RESERVED_0 [23:09] */
#define Wr_switch_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_40_JUMBO_PORT_MASK,0xfffe00,9,x)
#define Rd_switch_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_40_JUMBO_PORT_MASK,0xfffe00,9)
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_0_MASK 0x00fffe00
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_0_BITS 15
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_RESERVED_0_SHIFT 9

/* switch :: PAGE_40_JUMBO_PORT_MASK :: PAGE_40_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK [08:00] */
#define Wr_switch_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK(x) WriteRegBits(SWITCH_PAGE_40_JUMBO_PORT_MASK,0x1ff,0,x)
#define Rd_switch_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK(x) ReadRegBits(SWITCH_PAGE_40_JUMBO_PORT_MASK,0x1ff,0)
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_MASK 0x000001ff
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_ALIGN 0
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_BITS 9
#define SWITCH_PAGE_40_JUMBO_PORT_MASK_PAGE_40_JUMBO_PORT_MASK_JUMBO_FM_PORT_MASK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_40_MIB_GD_FM_MAX_SIZE
 ***************************************************************************/
/* switch :: PAGE_40_MIB_GD_FM_MAX_SIZE :: PAGE_40_MIB_GD_FM_MAX_SIZE_RESERVED [15:14] */
#define Wr_switch_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE,0xc000,14,x)
#define Rd_switch_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE,0xc000,14)
#define SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_RESERVED_MASK 0xc000
#define SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_RESERVED_ALIGN 0
#define SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_RESERVED_BITS 2
#define SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_RESERVED_SHIFT 14

/* switch :: PAGE_40_MIB_GD_FM_MAX_SIZE :: PAGE_40_MIB_GD_FM_MAX_SIZE_MAX_SIZE [13:00] */
#define Wr_switch_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_MAX_SIZE(x) WriteRegBits16(SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE,0x3fff,0,x)
#define Rd_switch_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_MAX_SIZE(x) ReadRegBits16(SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE,0x3fff,0)
#define SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_MAX_SIZE_MASK 0x3fff
#define SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_MAX_SIZE_ALIGN 0
#define SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_MAX_SIZE_BITS 14
#define SWITCH_PAGE_40_MIB_GD_FM_MAX_SIZE_PAGE_40_MIB_GD_FM_MAX_SIZE_MAX_SIZE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_40_JUMBO_CTRL_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_40_JUMBO_CTRL_REG_SPARE0 :: PAGE_40_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_40_JUMBO_CTRL_REG_SPARE0_PAGE_40_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0(x) WriteReg(SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE0,x)
#define Rd_switch_PAGE_40_JUMBO_CTRL_REG_SPARE0_PAGE_40_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0(x) ReadReg(SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE0)
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE0_PAGE_40_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE0_PAGE_40_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE0_PAGE_40_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_BITS 32
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE0_PAGE_40_JUMBO_CTRL_REG_SPARE0_JUMBO_CTRL_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_40_JUMBO_CTRL_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_40_JUMBO_CTRL_REG_SPARE1 :: PAGE_40_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_40_JUMBO_CTRL_REG_SPARE1_PAGE_40_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1(x) WriteReg(SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE1,x)
#define Rd_switch_PAGE_40_JUMBO_CTRL_REG_SPARE1_PAGE_40_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1(x) ReadReg(SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE1)
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE1_PAGE_40_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE1_PAGE_40_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE1_PAGE_40_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_BITS 32
#define SWITCH_PAGE_40_JUMBO_CTRL_REG_SPARE1_PAGE_40_JUMBO_CTRL_REG_SPARE1_JUMBO_CTRL_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_COMM_IRC_CON
 ***************************************************************************/
/* switch :: PAGE_41_COMM_IRC_CON :: PAGE_41_COMM_IRC_CON_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0xfffc0000,18,x)
#define Rd_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0xfffc0000,18)
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_2_BITS 14
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_2_SHIFT 18

/* switch :: PAGE_41_COMM_IRC_CON :: PAGE_41_COMM_IRC_CON_RATE_TYPE1 [17:17] */
#define Wr_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE1(x) WriteRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0x20000,17,x)
#define Rd_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE1(x) ReadRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0x20000,17)
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE1_MASK 0x00020000
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE1_ALIGN 0
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE1_BITS 1
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE1_SHIFT 17

/* switch :: PAGE_41_COMM_IRC_CON :: PAGE_41_COMM_IRC_CON_RESERVED_1 [16:09] */
#define Wr_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0x1fe00,9,x)
#define Rd_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0x1fe00,9)
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_1_MASK 0x0001fe00
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_1_BITS 8
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_1_SHIFT 9

/* switch :: PAGE_41_COMM_IRC_CON :: PAGE_41_COMM_IRC_CON_RATE_TYPE0 [08:08] */
#define Wr_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE0(x) WriteRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0x100,8,x)
#define Rd_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE0(x) ReadRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0x100,8)
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE0_MASK 0x00000100
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE0_ALIGN 0
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE0_BITS 1
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RATE_TYPE0_SHIFT 8

/* switch :: PAGE_41_COMM_IRC_CON :: PAGE_41_COMM_IRC_CON_RESERVED_0 [07:00] */
#define Wr_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0xff,0,x)
#define Rd_switch_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_41_COMM_IRC_CON,0xff,0)
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_0_MASK 0x000000ff
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_0_BITS 8
#define SWITCH_PAGE_41_COMM_IRC_CON_PAGE_41_COMM_IRC_CON_RESERVED_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_IRC_VIRTUAL_ZERO_THD
 ***************************************************************************/
/* switch :: PAGE_41_IRC_VIRTUAL_ZERO_THD :: PAGE_41_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD [15:00] */
#define Wr_switch_PAGE_41_IRC_VIRTUAL_ZERO_THD_PAGE_41_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD(x) WriteReg16(SWITCH_PAGE_41_IRC_VIRTUAL_ZERO_THD,x)
#define Rd_switch_PAGE_41_IRC_VIRTUAL_ZERO_THD_PAGE_41_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD(x) ReadReg16(SWITCH_PAGE_41_IRC_VIRTUAL_ZERO_THD)
#define SWITCH_PAGE_41_IRC_VIRTUAL_ZERO_THD_PAGE_41_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_MASK 0xffff
#define SWITCH_PAGE_41_IRC_VIRTUAL_ZERO_THD_PAGE_41_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_ALIGN 0
#define SWITCH_PAGE_41_IRC_VIRTUAL_ZERO_THD_PAGE_41_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_BITS 16
#define SWITCH_PAGE_41_IRC_VIRTUAL_ZERO_THD_PAGE_41_IRC_VIRTUAL_ZERO_THD_IRC_VIRTUAL_ZERO_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_IRC_ALARM_THD
 ***************************************************************************/
/* switch :: PAGE_41_IRC_ALARM_THD :: PAGE_41_IRC_ALARM_THD_IRC_ALARM_THD [15:00] */
#define Wr_switch_PAGE_41_IRC_ALARM_THD_PAGE_41_IRC_ALARM_THD_IRC_ALARM_THD(x) WriteReg16(SWITCH_PAGE_41_IRC_ALARM_THD,x)
#define Rd_switch_PAGE_41_IRC_ALARM_THD_PAGE_41_IRC_ALARM_THD_IRC_ALARM_THD(x) ReadReg16(SWITCH_PAGE_41_IRC_ALARM_THD)
#define SWITCH_PAGE_41_IRC_ALARM_THD_PAGE_41_IRC_ALARM_THD_IRC_ALARM_THD_MASK 0xffff
#define SWITCH_PAGE_41_IRC_ALARM_THD_PAGE_41_IRC_ALARM_THD_IRC_ALARM_THD_ALIGN 0
#define SWITCH_PAGE_41_IRC_ALARM_THD_PAGE_41_IRC_ALARM_THD_IRC_ALARM_THD_BITS 16
#define SWITCH_PAGE_41_IRC_ALARM_THD_PAGE_41_IRC_ALARM_THD_IRC_ALARM_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_P_port0
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_0 [31:31] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x80000000,31)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_0_MASK 0x80000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_0_SHIFT 31

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_0 [30:30] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x40000000,30,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x40000000,30)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_0_MASK 0x40000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_0_SHIFT 30

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_0 [29:29] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x20000000,29,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x20000000,29)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_0_MASK 0x20000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_0_SHIFT 29

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_0 [28:24] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x1f000000,24,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x1f000000,24)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_0_MASK 0x1f000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_0_BITS 5
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_0_SHIFT 24

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_0 [23:23] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x800000,23,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x800000,23)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_0_MASK 0x00800000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_0_SHIFT 23

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_0 [22:22] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x400000,22,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x400000,22)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_0_MASK 0x00400000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_0_SHIFT 22

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_0 [21:19] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x380000,19,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x380000,19)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_0_MASK 0x00380000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_0_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_0_SHIFT 19

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_0 [18:11] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x7f800,11,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x7f800,11)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_0_MASK 0x0007f800
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_0_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_0_SHIFT 11

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_0 [10:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x700,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0x700,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_0_MASK 0x00000700
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_0_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_0_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port0 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_0 [07:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0xff,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0,0xff,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_0_MASK 0x000000ff
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_0_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT0_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_P_port1
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_1 [31:31] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x80000000,31)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_1_MASK 0x80000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_1_SHIFT 31

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_1 [30:30] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x40000000,30,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x40000000,30)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_1_MASK 0x40000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_1_SHIFT 30

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_1 [29:29] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x20000000,29,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x20000000,29)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_1_MASK 0x20000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_1_SHIFT 29

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_1 [28:24] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x1f000000,24,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x1f000000,24)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_1_MASK 0x1f000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_1_BITS 5
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_1_SHIFT 24

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_1 [23:23] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x800000,23,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x800000,23)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_1_MASK 0x00800000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_1_SHIFT 23

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_1 [22:22] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x400000,22,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x400000,22)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_1_MASK 0x00400000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_1_SHIFT 22

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_1 [21:19] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x380000,19,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x380000,19)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_1_MASK 0x00380000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_1_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_1_SHIFT 19

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_1 [18:11] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x7f800,11,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x7f800,11)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_1_MASK 0x0007f800
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_1_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_1_SHIFT 11

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_1 [10:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x700,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0x700,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_1_MASK 0x00000700
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_1_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_1_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port1 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_1 [07:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0xff,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1,0xff,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_1_MASK 0x000000ff
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_1_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT1_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_P_port2
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_2 [31:31] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x80000000,31)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_2_MASK 0x80000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_2_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_2_SHIFT 31

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_2 [30:30] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x40000000,30,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x40000000,30)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_2_MASK 0x40000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_2_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_2_SHIFT 30

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_2 [29:29] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x20000000,29,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x20000000,29)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_2_MASK 0x20000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_2_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_2_SHIFT 29

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_2 [28:24] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x1f000000,24,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x1f000000,24)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_2_MASK 0x1f000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_2_BITS 5
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_2_SHIFT 24

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_2 [23:23] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x800000,23,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x800000,23)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_2_MASK 0x00800000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_2_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_2_SHIFT 23

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_2 [22:22] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x400000,22,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x400000,22)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_2_MASK 0x00400000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_2_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_2_SHIFT 22

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_2 [21:19] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x380000,19,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x380000,19)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_2_MASK 0x00380000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_2_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_2_SHIFT 19

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_2 [18:11] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x7f800,11,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x7f800,11)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_2_MASK 0x0007f800
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_2_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_2_SHIFT 11

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_2 [10:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x700,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0x700,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_2_MASK 0x00000700
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_2_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_2_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port2 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_2 [07:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_2(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0xff,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_2(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2,0xff,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_2_MASK 0x000000ff
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_2_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT2_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_P_port3
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_3 [31:31] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x80000000,31)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_3_MASK 0x80000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_3_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_3_SHIFT 31

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_3 [30:30] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x40000000,30,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x40000000,30)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_3_MASK 0x40000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_3_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_3_SHIFT 30

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_3 [29:29] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x20000000,29,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x20000000,29)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_3_MASK 0x20000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_3_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_3_SHIFT 29

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_3 [28:24] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x1f000000,24,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x1f000000,24)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_3_MASK 0x1f000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_3_BITS 5
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_3_SHIFT 24

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_3 [23:23] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x800000,23,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x800000,23)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_3_MASK 0x00800000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_3_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_3_SHIFT 23

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_3 [22:22] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x400000,22,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x400000,22)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_3_MASK 0x00400000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_3_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_3_SHIFT 22

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_3 [21:19] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x380000,19,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x380000,19)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_3_MASK 0x00380000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_3_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_3_SHIFT 19

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_3 [18:11] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x7f800,11,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x7f800,11)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_3_MASK 0x0007f800
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_3_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_3_SHIFT 11

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_3 [10:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x700,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0x700,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_3_MASK 0x00000700
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_3_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_3_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port3 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_3 [07:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_3(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0xff,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_3(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3,0xff,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_3_MASK 0x000000ff
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_3_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT3_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_P_port4
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_4 [31:31] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x80000000,31)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_4_MASK 0x80000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_4_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_4_SHIFT 31

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_4 [30:30] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x40000000,30,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x40000000,30)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_4_MASK 0x40000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_4_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_4_SHIFT 30

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_4 [29:29] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x20000000,29,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x20000000,29)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_4_MASK 0x20000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_4_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_4_SHIFT 29

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_4 [28:24] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x1f000000,24,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x1f000000,24)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_4_MASK 0x1f000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_4_BITS 5
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_4_SHIFT 24

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_4 [23:23] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x800000,23,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x800000,23)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_4_MASK 0x00800000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_4_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_4_SHIFT 23

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_4 [22:22] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x400000,22,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x400000,22)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_4_MASK 0x00400000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_4_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_4_SHIFT 22

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_4 [21:19] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x380000,19,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x380000,19)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_4_MASK 0x00380000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_4_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_4_SHIFT 19

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_4 [18:11] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x7f800,11,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x7f800,11)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_4_MASK 0x0007f800
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_4_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_4_SHIFT 11

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_4 [10:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x700,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0x700,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_4_MASK 0x00000700
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_4_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_4_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port4 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_4 [07:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_4(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0xff,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_4(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4,0xff,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_4_MASK 0x000000ff
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_4_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT4_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_P_port5
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_5 [31:31] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x80000000,31)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_5_MASK 0x80000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_5_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_5_SHIFT 31

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_5 [30:30] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x40000000,30,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x40000000,30)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_5_MASK 0x40000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_5_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_5_SHIFT 30

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_5 [29:29] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x20000000,29,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x20000000,29)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_5_MASK 0x20000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_5_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_5_SHIFT 29

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_5 [28:24] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x1f000000,24,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x1f000000,24)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_5_MASK 0x1f000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_5_BITS 5
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_5_SHIFT 24

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_5 [23:23] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x800000,23,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x800000,23)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_5_MASK 0x00800000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_5_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_5_SHIFT 23

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_5 [22:22] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x400000,22,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x400000,22)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_5_MASK 0x00400000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_5_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_5_SHIFT 22

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_5 [21:19] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x380000,19,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x380000,19)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_5_MASK 0x00380000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_5_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_5_SHIFT 19

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_5 [18:11] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x7f800,11,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x7f800,11)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_5_MASK 0x0007f800
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_5_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_5_SHIFT 11

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_5 [10:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x700,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0x700,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_5_MASK 0x00000700
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_5_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_5_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port5 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_5 [07:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_5(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0xff,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_5(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5,0xff,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_5_MASK 0x000000ff
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_5_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT5_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_P_port6
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_6 [31:31] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x80000000,31)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_6_MASK 0x80000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_6_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_1_6_SHIFT 31

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_6 [30:30] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x40000000,30,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x40000000,30)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_6_MASK 0x40000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_6_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE1_6_SHIFT 30

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_6 [29:29] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x20000000,29,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x20000000,29)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_6_MASK 0x20000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_6_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET_MODE0_6_SHIFT 29

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_6 [28:24] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x1f000000,24,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x1f000000,24)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_6_MASK 0x1f000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_6_BITS 5
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_RESERVED_0_6_SHIFT 24

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_6 [23:23] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x800000,23,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x800000,23)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_6_MASK 0x00800000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_6_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET1_6_SHIFT 23

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_6 [22:22] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x400000,22,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x400000,22)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_6_MASK 0x00400000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_6_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_EN_BUCKET0_6_SHIFT 22

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_6 [21:19] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x380000,19,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x380000,19)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_6_MASK 0x00380000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_6_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_SIZE_6_SHIFT 19

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_6 [18:11] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x7f800,11,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x7f800,11)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_6_MASK 0x0007f800
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_6_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET1_REF_CNT_6_SHIFT 11

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_6 [10:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x700,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0x700,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_6_MASK 0x00000700
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_6_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_SIZE_6_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_P_port6 :: PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_6 [07:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_6(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0xff,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P_port6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_6(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6,0xff,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_6_MASK 0x000000ff
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_6_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P_PORT6_PAGE_41_BC_SUP_RATECTRL_P_BUCKET0_REF_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_P7
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_1 [31:31] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x80000000,31,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x80000000,31)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_1_MASK 0x80000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_1_SHIFT 31

/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE1 [30:30] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x40000000,30,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x40000000,30)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE1_MASK 0x40000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE1_SHIFT 30

/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE0 [29:29] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x20000000,29,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x20000000,29)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE0_MASK 0x20000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET_MODE0_SHIFT 29

/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_0 [28:24] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x1f000000,24,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x1f000000,24)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_0_MASK 0x1f000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_0_BITS 5
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_RESERVED_0_SHIFT 24

/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET1 [23:23] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x800000,23,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x800000,23)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET1_MASK 0x00800000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET1_SHIFT 23

/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET0 [22:22] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x400000,22,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x400000,22)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET0_MASK 0x00400000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_EN_BUCKET0_SHIFT 22

/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_SIZE [21:19] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_SIZE(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x380000,19,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_SIZE(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x380000,19)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_MASK 0x00380000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_SIZE_SHIFT 19

/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT [18:11] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x7f800,11,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x7f800,11)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_MASK 0x0007f800
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET1_REF_CNT_SHIFT 11

/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_SIZE [10:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_SIZE(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x700,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_SIZE(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0x700,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_MASK 0x00000700
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_SIZE_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_P7 :: PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT [07:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0xff,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_P7,0xff,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_MASK 0x000000ff
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_P7_PAGE_41_BC_SUP_RATECTRL_P7_BUCKET0_REF_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_IMP
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_1 [31:31] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x80000000,31,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x80000000,31)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_1_MASK 0x80000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_1_SHIFT 31

/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE1 [30:30] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x40000000,30,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x40000000,30)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_MASK 0x40000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE1_SHIFT 30

/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE0 [29:29] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x20000000,29,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x20000000,29)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_MASK 0x20000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET_MODE0_SHIFT 29

/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_0 [28:24] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x1f000000,24,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x1f000000,24)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_0_MASK 0x1f000000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_0_BITS 5
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_RESERVED_0_SHIFT 24

/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET1 [23:23] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET1(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x800000,23,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET1(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x800000,23)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET1_MASK 0x00800000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET1_SHIFT 23

/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET0 [22:22] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET0(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x400000,22,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET0(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x400000,22)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET0_MASK 0x00400000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_EN_BUCKET0_SHIFT 22

/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE [21:19] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x380000,19,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x380000,19)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_MASK 0x00380000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_SIZE_SHIFT 19

/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT [18:11] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x7f800,11,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x7f800,11)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_MASK 0x0007f800
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET1_REF_CNT_SHIFT 11

/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE [10:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x700,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0x700,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_MASK 0x00000700
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_BITS 3
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_SIZE_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_IMP :: PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT [07:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT(x) WriteRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0xff,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT(x) ReadRegBits(SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP,0xff,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_MASK 0x000000ff
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_BITS 8
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_IMP_PAGE_41_BC_SUP_RATECTRL_IMP_BUCKET0_REF_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port0
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port0 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_0 [15:15] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_0(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0,0x8000,15,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_0(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0,0x8000,15)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_0_MASK 0x8000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_0_SHIFT 15

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port0 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_0 [14:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_0(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0,0x7f00,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_0(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0,0x7f00,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_0_MASK 0x7f00
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_0_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_0_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port0 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_0 [07:07] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_0(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0,0x80,7,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_0(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0,0x80,7)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_0_MASK 0x0080
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_0_SHIFT 7

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port0 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_0 [06:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_0(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0,0x7f,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_0(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0,0x7f,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_0_MASK 0x007f
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_0_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT0_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port1
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port1 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_1 [15:15] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_1(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1,0x8000,15,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_1(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1,0x8000,15)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_1_MASK 0x8000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_1_SHIFT 15

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port1 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_1 [14:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_1(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1,0x7f00,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_1(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1,0x7f00,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_1_MASK 0x7f00
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_1_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_1_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port1 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_1 [07:07] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_1(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1,0x80,7,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_1(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1,0x80,7)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_1_MASK 0x0080
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_1_SHIFT 7

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port1 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_1 [06:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_1(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1,0x7f,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_1(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1,0x7f,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_1_MASK 0x007f
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_1_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT1_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port2
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port2 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_2 [15:15] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_2(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2,0x8000,15,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_2(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2,0x8000,15)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_2_MASK 0x8000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_2_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_2_SHIFT 15

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port2 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_2 [14:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_2(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2,0x7f00,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_2(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2,0x7f00,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_2_MASK 0x7f00
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_2_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_2_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port2 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_2 [07:07] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_2(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2,0x80,7,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_2(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2,0x80,7)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_2_MASK 0x0080
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_2_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_2_SHIFT 7

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port2 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_2 [06:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_2(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2,0x7f,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_2(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2,0x7f,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_2_MASK 0x007f
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_2_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT2_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port3
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port3 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_3 [15:15] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_3(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3,0x8000,15,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_3(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3,0x8000,15)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_3_MASK 0x8000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_3_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_3_SHIFT 15

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port3 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_3 [14:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_3(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3,0x7f00,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_3(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3,0x7f00,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_3_MASK 0x7f00
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_3_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_3_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port3 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_3 [07:07] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_3(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3,0x80,7,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_3(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3,0x80,7)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_3_MASK 0x0080
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_3_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_3_SHIFT 7

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port3 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_3 [06:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_3(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3,0x7f,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_3(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3,0x7f,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_3_MASK 0x007f
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_3_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT3_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port4
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port4 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_4 [15:15] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_4(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4,0x8000,15,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_4(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4,0x8000,15)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_4_MASK 0x8000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_4_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_4_SHIFT 15

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port4 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_4 [14:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_4(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4,0x7f00,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_4(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4,0x7f00,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_4_MASK 0x7f00
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_4_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_4_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port4 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_4 [07:07] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_4(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4,0x80,7,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_4(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4,0x80,7)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_4_MASK 0x0080
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_4_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_4_SHIFT 7

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port4 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_4 [06:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_4(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4,0x7f,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_4(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4,0x7f,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_4_MASK 0x007f
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_4_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT4_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port5
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port5 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_5 [15:15] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_5(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5,0x8000,15,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_5(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5,0x8000,15)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_5_MASK 0x8000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_5_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_5_SHIFT 15

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port5 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_5 [14:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_5(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5,0x7f00,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_5(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5,0x7f00,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_5_MASK 0x7f00
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_5_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_5_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port5 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_5 [07:07] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_5(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5,0x80,7,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_5(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5,0x80,7)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_5_MASK 0x0080
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_5_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_5_SHIFT 7

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port5 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_5 [06:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_5(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5,0x7f,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_5(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5,0x7f,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_5_MASK 0x007f
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_5_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT5_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port6
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port6 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_6 [15:15] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_6(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6,0x8000,15,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_6(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6,0x8000,15)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_6_MASK 0x8000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_6_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES1_6_SHIFT 15

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port6 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_6 [14:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_6(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6,0x7f00,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_6(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6,0x7f00,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_6_MASK 0x7f00
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_6_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK1_6_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port6 :: PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_6 [07:07] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_6(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6,0x80,7,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_6(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6,0x80,7)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_6_MASK 0x0080
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_6_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_IFG_BYTES0_6_SHIFT 7

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P_port6 :: PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_6 [06:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_6(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6,0x7f,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P_port6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_6(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6,0x7f,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_6_MASK 0x007f
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_6_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P_PORT6_PAGE_41_BC_SUP_RATECTRL_1_P_PKT_MSK0_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_1_P7
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P7 :: PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES1 [15:15] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES1(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7,0x8000,15,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES1(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7,0x8000,15)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_MASK 0x8000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES1_SHIFT 15

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P7 :: PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK1 [14:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK1(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7,0x7f00,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK1(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7,0x7f00,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK1_MASK 0x7f00
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK1_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK1_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P7 :: PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES0 [07:07] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES0(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7,0x80,7,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES0(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7,0x80,7)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_MASK 0x0080
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_IFG_BYTES0_SHIFT 7

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_P7 :: PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK0 [06:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK0(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7,0x7f,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK0(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7,0x7f,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK0_MASK 0x007f
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK0_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_P7_PAGE_41_BC_SUP_RATECTRL_1_P7_PKT_MSK0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_RATECTRL_1_IMP
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_RATECTRL_1_IMP :: PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1 [15:15] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP,0x8000,15,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP,0x8000,15)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_MASK 0x8000
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES1_SHIFT 15

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_IMP :: PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK1 [14:08] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK1(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP,0x7f00,8,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK1(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP,0x7f00,8)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_MASK 0x7f00
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK1_SHIFT 8

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_IMP :: PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0 [07:07] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP,0x80,7,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP,0x80,7)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_MASK 0x0080
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_BITS 1
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_IFG_BYTES0_SHIFT 7

/* switch :: PAGE_41_BC_SUP_RATECTRL_1_IMP :: PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK0 [06:00] */
#define Wr_switch_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK0(x) WriteRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP,0x7f,0,x)
#define Rd_switch_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK0(x) ReadRegBits16(SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP,0x7f,0)
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_MASK 0x007f
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_BITS 7
#define SWITCH_PAGE_41_BC_SUP_RATECTRL_1_IMP_PAGE_41_BC_SUP_RATECTRL_1_IMP_PKT_MSK0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port0
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port0 :: PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_0 [31:00] */
#define Wr_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port0_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_0(x) WriteReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT0,x)
#define Rd_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port0_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_0(x) ReadReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT0)
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT0_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_0_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT0_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT0_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_0_BITS 32
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT0_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port1
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port1 :: PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_1 [31:00] */
#define Wr_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port1_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_1(x) WriteReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT1,x)
#define Rd_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port1_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_1(x) ReadReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT1)
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT1_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_1_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT1_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT1_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_1_BITS 32
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT1_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port2
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port2 :: PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_2 [31:00] */
#define Wr_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port2_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_2(x) WriteReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT2,x)
#define Rd_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port2_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_2(x) ReadReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT2)
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT2_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_2_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT2_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_2_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT2_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_2_BITS 32
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT2_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port3
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port3 :: PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_3 [31:00] */
#define Wr_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port3_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_3(x) WriteReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT3,x)
#define Rd_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port3_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_3(x) ReadReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT3)
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT3_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_3_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT3_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_3_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT3_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_3_BITS 32
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT3_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port4
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port4 :: PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_4 [31:00] */
#define Wr_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port4_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_4(x) WriteReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT4,x)
#define Rd_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port4_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_4(x) ReadReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT4)
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT4_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_4_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT4_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_4_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT4_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_4_BITS 32
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT4_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port5
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port5 :: PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_5 [31:00] */
#define Wr_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port5_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_5(x) WriteReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT5,x)
#define Rd_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port5_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_5(x) ReadReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT5)
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT5_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_5_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT5_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_5_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT5_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_5_BITS 32
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT5_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port6
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P_port6 :: PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_6 [31:00] */
#define Wr_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port6_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_6(x) WriteReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT6,x)
#define Rd_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P_port6_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_6(x) ReadReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT6)
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT6_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_6_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT6_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_6_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT6_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_6_BITS 32
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P_PORT6_PAGE_41_BC_SUP_PKTDROP_CNT_P_PK_DROP_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P7
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_PKTDROP_CNT_P7 :: PAGE_41_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT [31:00] */
#define Wr_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT(x) WriteReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P7,x)
#define Rd_switch_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT(x) ReadReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P7)
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_BITS 32
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PAGE_41_BC_SUP_PKTDROP_CNT_P7_PK_DROP_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUP_PKTDROP_CNT_IMP
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUP_PKTDROP_CNT_IMP :: PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT [31:00] */
#define Wr_switch_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT(x) WriteReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_IMP,x)
#define Rd_switch_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT(x) ReadReg(SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_IMP)
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_ALIGN 0
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_BITS 32
#define SWITCH_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PAGE_41_BC_SUP_PKTDROP_CNT_IMP_PK_DROP_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUPPRESS_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUPPRESS_REG_SPARE0 :: PAGE_41_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_41_BC_SUPPRESS_REG_SPARE0_PAGE_41_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0(x) WriteReg(SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE0,x)
#define Rd_switch_PAGE_41_BC_SUPPRESS_REG_SPARE0_PAGE_41_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0(x) ReadReg(SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE0)
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE0_PAGE_41_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE0_PAGE_41_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE0_PAGE_41_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_BITS 32
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE0_PAGE_41_BC_SUPPRESS_REG_SPARE0_BC_SUPPRESS_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_41_BC_SUPPRESS_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_41_BC_SUPPRESS_REG_SPARE1 :: PAGE_41_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_41_BC_SUPPRESS_REG_SPARE1_PAGE_41_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1(x) WriteReg(SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE1,x)
#define Rd_switch_PAGE_41_BC_SUPPRESS_REG_SPARE1_PAGE_41_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1(x) ReadReg(SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE1)
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE1_PAGE_41_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE1_PAGE_41_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE1_PAGE_41_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_BITS 32
#define SWITCH_PAGE_41_BC_SUPPRESS_REG_SPARE1_PAGE_41_BC_SUPPRESS_REG_SPARE1_BC_SUPPRESS_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_EAP_GLO_CON
 ***************************************************************************/
/* switch :: PAGE_42_EAP_GLO_CON :: PAGE_42_EAP_GLO_CON_RESERVED_0 [07:07] */
#define Wr_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x80,7,x)
#define Rd_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x80,7)
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_0_MASK 0x80
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_0_BITS 1
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_0_SHIFT 7

/* switch :: PAGE_42_EAP_GLO_CON :: PAGE_42_EAP_GLO_CON_EN_RARP [06:06] */
#define Wr_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RARP(x) WriteRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x40,6,x)
#define Rd_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RARP(x) ReadRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x40,6)
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RARP_MASK 0x40
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RARP_ALIGN 0
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RARP_BITS 1
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RARP_SHIFT 6

/* switch :: PAGE_42_EAP_GLO_CON :: PAGE_42_EAP_GLO_CON_EN_BPDU [05:05] */
#define Wr_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_BPDU(x) WriteRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x20,5,x)
#define Rd_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_BPDU(x) ReadRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x20,5)
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_BPDU_MASK 0x20
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_BPDU_ALIGN 0
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_BPDU_BITS 1
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_BPDU_SHIFT 5

/* switch :: PAGE_42_EAP_GLO_CON :: PAGE_42_EAP_GLO_CON_EN_RMC [04:04] */
#define Wr_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RMC(x) WriteRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x10,4,x)
#define Rd_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RMC(x) ReadRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x10,4)
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RMC_MASK 0x10
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RMC_ALIGN 0
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RMC_BITS 1
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_RMC_SHIFT 4

/* switch :: PAGE_42_EAP_GLO_CON :: PAGE_42_EAP_GLO_CON_EN_DHCP [03:03] */
#define Wr_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_DHCP(x) WriteRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x8,3,x)
#define Rd_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_DHCP(x) ReadRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x8,3)
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_DHCP_MASK 0x08
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_DHCP_ALIGN 0
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_DHCP_BITS 1
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_DHCP_SHIFT 3

/* switch :: PAGE_42_EAP_GLO_CON :: PAGE_42_EAP_GLO_CON_EN_ARP [02:02] */
#define Wr_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_ARP(x) WriteRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x4,2,x)
#define Rd_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_ARP(x) ReadRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x4,2)
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_ARP_MASK 0x04
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_ARP_ALIGN 0
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_ARP_BITS 1
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_ARP_SHIFT 2

/* switch :: PAGE_42_EAP_GLO_CON :: PAGE_42_EAP_GLO_CON_EN_2_DIP [01:01] */
#define Wr_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_2_DIP(x) WriteRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x2,1,x)
#define Rd_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_2_DIP(x) ReadRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x2,1)
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_2_DIP_MASK 0x02
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_2_DIP_ALIGN 0
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_2_DIP_BITS 1
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_EN_2_DIP_SHIFT 1

/* switch :: PAGE_42_EAP_GLO_CON :: PAGE_42_EAP_GLO_CON_RESERVED [00:00] */
#define Wr_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x1,0,x)
#define Rd_switch_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_EAP_GLO_CON,0x1,0)
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_MASK 0x01
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_BITS 1
#define SWITCH_PAGE_42_EAP_GLO_CON_PAGE_42_EAP_GLO_CON_RESERVED_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_EAP_MULTI_ADDR_CTRL
 ***************************************************************************/
/* switch :: PAGE_42_EAP_MULTI_ADDR_CTRL :: PAGE_42_EAP_MULTI_ADDR_CTRL_RESERVED [07:06] */
#define Wr_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0xc0,6,x)
#define Rd_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0xc0,6)
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_RESERVED_MASK 0xc0
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_RESERVED_BITS 2
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_RESERVED_SHIFT 6

/* switch :: PAGE_42_EAP_MULTI_ADDR_CTRL :: PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT5 [05:05] */
#define Wr_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT5(x) WriteRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x20,5,x)
#define Rd_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT5(x) ReadRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x20,5)
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT5_MASK 0x20
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT5_ALIGN 0
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT5_BITS 1
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT5_SHIFT 5

/* switch :: PAGE_42_EAP_MULTI_ADDR_CTRL :: PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT4 [04:04] */
#define Wr_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT4(x) WriteRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x10,4,x)
#define Rd_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT4(x) ReadRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x10,4)
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT4_MASK 0x10
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT4_ALIGN 0
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT4_BITS 1
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT4_SHIFT 4

/* switch :: PAGE_42_EAP_MULTI_ADDR_CTRL :: PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT3 [03:03] */
#define Wr_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT3(x) WriteRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x8,3,x)
#define Rd_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT3(x) ReadRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x8,3)
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT3_MASK 0x08
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT3_ALIGN 0
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT3_BITS 1
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT3_SHIFT 3

/* switch :: PAGE_42_EAP_MULTI_ADDR_CTRL :: PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT2 [02:02] */
#define Wr_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT2(x) WriteRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x4,2,x)
#define Rd_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT2(x) ReadRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x4,2)
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT2_MASK 0x04
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT2_ALIGN 0
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT2_BITS 1
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT2_SHIFT 2

/* switch :: PAGE_42_EAP_MULTI_ADDR_CTRL :: PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT1 [01:01] */
#define Wr_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT1(x) WriteRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x2,1,x)
#define Rd_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT1(x) ReadRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x2,1)
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT1_MASK 0x02
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT1_ALIGN 0
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT1_BITS 1
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT1_SHIFT 1

/* switch :: PAGE_42_EAP_MULTI_ADDR_CTRL :: PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT0 [00:00] */
#define Wr_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT0(x) WriteRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x1,0,x)
#define Rd_switch_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT0(x) ReadRegBits(SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL,0x1,0)
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT0_MASK 0x01
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT0_ALIGN 0
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT0_BITS 1
#define SWITCH_PAGE_42_EAP_MULTI_ADDR_CTRL_PAGE_42_EAP_MULTI_ADDR_CTRL_EN_MPORT0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_EAP_DIP0
 ***************************************************************************/
/* switch :: PAGE_42_EAP_DIP0 :: PAGE_42_EAP_DIP0_DIP_SUB_REG [63:32] */
#define Wr_switch_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_SUB_REG(x) WriteRegBits(SWITCH_PAGE_42_EAP_DIP0,0xffffffff00000000,32,x)
#define Rd_switch_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_SUB_REG(x) ReadRegBits(SWITCH_PAGE_42_EAP_DIP0,0xffffffff00000000,32)
#define SWITCH_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_SUB_REG_MASK  0xffffffff00000000
#define SWITCH_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_SUB_REG_ALIGN 0
#define SWITCH_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_SUB_REG_BITS  32
#define SWITCH_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_SUB_REG_SHIFT 32

/* switch :: PAGE_42_EAP_DIP0 :: PAGE_42_EAP_DIP0_DIP_MASK_REG [31:00] */
#define Wr_switch_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_MASK_REG(x) WriteRegBits(SWITCH_PAGE_42_EAP_DIP0,0xffffffff,0,x)
#define Rd_switch_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_MASK_REG(x) ReadRegBits(SWITCH_PAGE_42_EAP_DIP0,0xffffffff,0)
#define SWITCH_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_MASK_REG_MASK 0x00000000ffffffff
#define SWITCH_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_MASK_REG_ALIGN 0
#define SWITCH_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_MASK_REG_BITS 32
#define SWITCH_PAGE_42_EAP_DIP0_PAGE_42_EAP_DIP0_DIP_MASK_REG_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_EAP_DIP1
 ***************************************************************************/
/* switch :: PAGE_42_EAP_DIP1 :: PAGE_42_EAP_DIP1_DIP_SUB_REG [63:32] */
#define Wr_switch_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_SUB_REG(x) WriteRegBits(SWITCH_PAGE_42_EAP_DIP1,0xffffffff00000000,32,x)
#define Rd_switch_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_SUB_REG(x) ReadRegBits(SWITCH_PAGE_42_EAP_DIP1,0xffffffff00000000,32)
#define SWITCH_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_SUB_REG_MASK  0xffffffff00000000
#define SWITCH_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_SUB_REG_ALIGN 0
#define SWITCH_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_SUB_REG_BITS  32
#define SWITCH_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_SUB_REG_SHIFT 32

/* switch :: PAGE_42_EAP_DIP1 :: PAGE_42_EAP_DIP1_DIP_MASK_REG [31:00] */
#define Wr_switch_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_MASK_REG(x) WriteRegBits(SWITCH_PAGE_42_EAP_DIP1,0xffffffff,0,x)
#define Rd_switch_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_MASK_REG(x) ReadRegBits(SWITCH_PAGE_42_EAP_DIP1,0xffffffff,0)
#define SWITCH_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_MASK_REG_MASK 0x00000000ffffffff
#define SWITCH_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_MASK_REG_ALIGN 0
#define SWITCH_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_MASK_REG_BITS 32
#define SWITCH_PAGE_42_EAP_DIP1_PAGE_42_EAP_DIP1_DIP_MASK_REG_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_PORT_EAP_CON_P0
 ***************************************************************************/
/* switch :: PAGE_42_PORT_EAP_CON_P0 :: PAGE_42_PORT_EAP_CON_P0_RESERVED [63:53] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0xffe0000000000000,53,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0xffe0000000000000,53)
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_RESERVED_MASK 0xffe0000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_RESERVED_BITS 11
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_RESERVED_SHIFT 53

/* switch :: PAGE_42_PORT_EAP_CON_P0 :: PAGE_42_PORT_EAP_CON_P0_EAP_MODE [52:51] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0x18000000000000,51,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0x18000000000000,51)
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_MODE_MASK 0x0018000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_MODE_SHIFT 51

/* switch :: PAGE_42_PORT_EAP_CON_P0 :: PAGE_42_PORT_EAP_CON_P0_EAP_BLK_MODE [50:49] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_BLK_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0x6000000000000,49,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_BLK_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0x6000000000000,49)
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_BLK_MODE_MASK 0x0006000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_BLK_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_BLK_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_BLK_MODE_SHIFT 49

/* switch :: PAGE_42_PORT_EAP_CON_P0 :: PAGE_42_PORT_EAP_CON_P0_EAP_EN_UNI_DA [48:48] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_EN_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0x1000000000000,48,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_EN_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0x1000000000000,48)
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_EN_UNI_DA_MASK 0x0001000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_EN_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_EN_UNI_DA_BITS 1
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_EN_UNI_DA_SHIFT 48

/* switch :: PAGE_42_PORT_EAP_CON_P0 :: PAGE_42_PORT_EAP_CON_P0_EAP_UNI_DA [47:00] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0xffffffffffff,0,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P0,0xffffffffffff,0)
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_UNI_DA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_UNI_DA_BITS 48
#define SWITCH_PAGE_42_PORT_EAP_CON_P0_PAGE_42_PORT_EAP_CON_P0_EAP_UNI_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_PORT_EAP_CON_P1
 ***************************************************************************/
/* switch :: PAGE_42_PORT_EAP_CON_P1 :: PAGE_42_PORT_EAP_CON_P1_RESERVED [63:53] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0xffe0000000000000,53,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0xffe0000000000000,53)
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_RESERVED_MASK 0xffe0000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_RESERVED_BITS 11
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_RESERVED_SHIFT 53

/* switch :: PAGE_42_PORT_EAP_CON_P1 :: PAGE_42_PORT_EAP_CON_P1_EAP_MODE [52:51] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0x18000000000000,51,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0x18000000000000,51)
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_MODE_MASK 0x0018000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_MODE_SHIFT 51

/* switch :: PAGE_42_PORT_EAP_CON_P1 :: PAGE_42_PORT_EAP_CON_P1_EAP_BLK_MODE [50:49] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_BLK_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0x6000000000000,49,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_BLK_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0x6000000000000,49)
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_BLK_MODE_MASK 0x0006000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_BLK_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_BLK_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_BLK_MODE_SHIFT 49

/* switch :: PAGE_42_PORT_EAP_CON_P1 :: PAGE_42_PORT_EAP_CON_P1_EAP_EN_UNI_DA [48:48] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_EN_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0x1000000000000,48,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_EN_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0x1000000000000,48)
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_EN_UNI_DA_MASK 0x0001000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_EN_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_EN_UNI_DA_BITS 1
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_EN_UNI_DA_SHIFT 48

/* switch :: PAGE_42_PORT_EAP_CON_P1 :: PAGE_42_PORT_EAP_CON_P1_EAP_UNI_DA [47:00] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0xffffffffffff,0,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P1,0xffffffffffff,0)
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_UNI_DA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_UNI_DA_BITS 48
#define SWITCH_PAGE_42_PORT_EAP_CON_P1_PAGE_42_PORT_EAP_CON_P1_EAP_UNI_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_PORT_EAP_CON_P2
 ***************************************************************************/
/* switch :: PAGE_42_PORT_EAP_CON_P2 :: PAGE_42_PORT_EAP_CON_P2_RESERVED [63:53] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0xffe0000000000000,53,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0xffe0000000000000,53)
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_RESERVED_MASK 0xffe0000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_RESERVED_BITS 11
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_RESERVED_SHIFT 53

/* switch :: PAGE_42_PORT_EAP_CON_P2 :: PAGE_42_PORT_EAP_CON_P2_EAP_MODE [52:51] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0x18000000000000,51,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0x18000000000000,51)
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_MODE_MASK 0x0018000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_MODE_SHIFT 51

/* switch :: PAGE_42_PORT_EAP_CON_P2 :: PAGE_42_PORT_EAP_CON_P2_EAP_BLK_MODE [50:49] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_BLK_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0x6000000000000,49,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_BLK_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0x6000000000000,49)
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_BLK_MODE_MASK 0x0006000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_BLK_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_BLK_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_BLK_MODE_SHIFT 49

/* switch :: PAGE_42_PORT_EAP_CON_P2 :: PAGE_42_PORT_EAP_CON_P2_EAP_EN_UNI_DA [48:48] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_EN_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0x1000000000000,48,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_EN_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0x1000000000000,48)
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_EN_UNI_DA_MASK 0x0001000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_EN_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_EN_UNI_DA_BITS 1
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_EN_UNI_DA_SHIFT 48

/* switch :: PAGE_42_PORT_EAP_CON_P2 :: PAGE_42_PORT_EAP_CON_P2_EAP_UNI_DA [47:00] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0xffffffffffff,0,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P2,0xffffffffffff,0)
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_UNI_DA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_UNI_DA_BITS 48
#define SWITCH_PAGE_42_PORT_EAP_CON_P2_PAGE_42_PORT_EAP_CON_P2_EAP_UNI_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_PORT_EAP_CON_P3
 ***************************************************************************/
/* switch :: PAGE_42_PORT_EAP_CON_P3 :: PAGE_42_PORT_EAP_CON_P3_RESERVED [63:53] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0xffe0000000000000,53,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0xffe0000000000000,53)
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_RESERVED_MASK 0xffe0000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_RESERVED_BITS 11
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_RESERVED_SHIFT 53

/* switch :: PAGE_42_PORT_EAP_CON_P3 :: PAGE_42_PORT_EAP_CON_P3_EAP_MODE [52:51] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0x18000000000000,51,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0x18000000000000,51)
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_MODE_MASK 0x0018000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_MODE_SHIFT 51

/* switch :: PAGE_42_PORT_EAP_CON_P3 :: PAGE_42_PORT_EAP_CON_P3_EAP_BLK_MODE [50:49] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_BLK_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0x6000000000000,49,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_BLK_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0x6000000000000,49)
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_BLK_MODE_MASK 0x0006000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_BLK_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_BLK_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_BLK_MODE_SHIFT 49

/* switch :: PAGE_42_PORT_EAP_CON_P3 :: PAGE_42_PORT_EAP_CON_P3_EAP_EN_UNI_DA [48:48] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_EN_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0x1000000000000,48,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_EN_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0x1000000000000,48)
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_EN_UNI_DA_MASK 0x0001000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_EN_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_EN_UNI_DA_BITS 1
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_EN_UNI_DA_SHIFT 48

/* switch :: PAGE_42_PORT_EAP_CON_P3 :: PAGE_42_PORT_EAP_CON_P3_EAP_UNI_DA [47:00] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0xffffffffffff,0,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P3,0xffffffffffff,0)
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_UNI_DA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_UNI_DA_BITS 48
#define SWITCH_PAGE_42_PORT_EAP_CON_P3_PAGE_42_PORT_EAP_CON_P3_EAP_UNI_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_PORT_EAP_CON_P4
 ***************************************************************************/
/* switch :: PAGE_42_PORT_EAP_CON_P4 :: PAGE_42_PORT_EAP_CON_P4_RESERVED [63:53] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0xffe0000000000000,53,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0xffe0000000000000,53)
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_RESERVED_MASK 0xffe0000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_RESERVED_BITS 11
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_RESERVED_SHIFT 53

/* switch :: PAGE_42_PORT_EAP_CON_P4 :: PAGE_42_PORT_EAP_CON_P4_EAP_MODE [52:51] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0x18000000000000,51,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0x18000000000000,51)
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_MODE_MASK 0x0018000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_MODE_SHIFT 51

/* switch :: PAGE_42_PORT_EAP_CON_P4 :: PAGE_42_PORT_EAP_CON_P4_EAP_BLK_MODE [50:49] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_BLK_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0x6000000000000,49,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_BLK_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0x6000000000000,49)
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_BLK_MODE_MASK 0x0006000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_BLK_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_BLK_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_BLK_MODE_SHIFT 49

/* switch :: PAGE_42_PORT_EAP_CON_P4 :: PAGE_42_PORT_EAP_CON_P4_EAP_EN_UNI_DA [48:48] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_EN_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0x1000000000000,48,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_EN_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0x1000000000000,48)
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_EN_UNI_DA_MASK 0x0001000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_EN_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_EN_UNI_DA_BITS 1
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_EN_UNI_DA_SHIFT 48

/* switch :: PAGE_42_PORT_EAP_CON_P4 :: PAGE_42_PORT_EAP_CON_P4_EAP_UNI_DA [47:00] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0xffffffffffff,0,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P4,0xffffffffffff,0)
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_UNI_DA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_UNI_DA_BITS 48
#define SWITCH_PAGE_42_PORT_EAP_CON_P4_PAGE_42_PORT_EAP_CON_P4_EAP_UNI_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_PORT_EAP_CON_P5
 ***************************************************************************/
/* switch :: PAGE_42_PORT_EAP_CON_P5 :: PAGE_42_PORT_EAP_CON_P5_RESERVED [63:53] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0xffe0000000000000,53,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0xffe0000000000000,53)
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_RESERVED_MASK 0xffe0000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_RESERVED_BITS 11
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_RESERVED_SHIFT 53

/* switch :: PAGE_42_PORT_EAP_CON_P5 :: PAGE_42_PORT_EAP_CON_P5_EAP_MODE [52:51] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0x18000000000000,51,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0x18000000000000,51)
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_MODE_MASK 0x0018000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_MODE_SHIFT 51

/* switch :: PAGE_42_PORT_EAP_CON_P5 :: PAGE_42_PORT_EAP_CON_P5_EAP_BLK_MODE [50:49] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_BLK_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0x6000000000000,49,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_BLK_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0x6000000000000,49)
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_BLK_MODE_MASK 0x0006000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_BLK_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_BLK_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_BLK_MODE_SHIFT 49

/* switch :: PAGE_42_PORT_EAP_CON_P5 :: PAGE_42_PORT_EAP_CON_P5_EAP_EN_UNI_DA [48:48] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_EN_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0x1000000000000,48,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_EN_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0x1000000000000,48)
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_EN_UNI_DA_MASK 0x0001000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_EN_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_EN_UNI_DA_BITS 1
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_EN_UNI_DA_SHIFT 48

/* switch :: PAGE_42_PORT_EAP_CON_P5 :: PAGE_42_PORT_EAP_CON_P5_EAP_UNI_DA [47:00] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0xffffffffffff,0,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P5,0xffffffffffff,0)
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_UNI_DA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_UNI_DA_BITS 48
#define SWITCH_PAGE_42_PORT_EAP_CON_P5_PAGE_42_PORT_EAP_CON_P5_EAP_UNI_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_PORT_EAP_CON_P6
 ***************************************************************************/
/* switch :: PAGE_42_PORT_EAP_CON_P6 :: PAGE_42_PORT_EAP_CON_P6_RESERVED [63:53] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0xffe0000000000000,53,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0xffe0000000000000,53)
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_RESERVED_MASK 0xffe0000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_RESERVED_BITS 11
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_RESERVED_SHIFT 53

/* switch :: PAGE_42_PORT_EAP_CON_P6 :: PAGE_42_PORT_EAP_CON_P6_EAP_MODE [52:51] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0x18000000000000,51,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0x18000000000000,51)
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_MODE_MASK 0x0018000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_MODE_SHIFT 51

/* switch :: PAGE_42_PORT_EAP_CON_P6 :: PAGE_42_PORT_EAP_CON_P6_EAP_BLK_MODE [50:49] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_BLK_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0x6000000000000,49,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_BLK_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0x6000000000000,49)
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_BLK_MODE_MASK 0x0006000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_BLK_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_BLK_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_BLK_MODE_SHIFT 49

/* switch :: PAGE_42_PORT_EAP_CON_P6 :: PAGE_42_PORT_EAP_CON_P6_EAP_EN_UNI_DA [48:48] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_EN_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0x1000000000000,48,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_EN_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0x1000000000000,48)
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_EN_UNI_DA_MASK 0x0001000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_EN_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_EN_UNI_DA_BITS 1
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_EN_UNI_DA_SHIFT 48

/* switch :: PAGE_42_PORT_EAP_CON_P6 :: PAGE_42_PORT_EAP_CON_P6_EAP_UNI_DA [47:00] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0xffffffffffff,0,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P6,0xffffffffffff,0)
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_UNI_DA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_UNI_DA_BITS 48
#define SWITCH_PAGE_42_PORT_EAP_CON_P6_PAGE_42_PORT_EAP_CON_P6_EAP_UNI_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_PORT_EAP_CON_P7
 ***************************************************************************/
/* switch :: PAGE_42_PORT_EAP_CON_P7 :: PAGE_42_PORT_EAP_CON_P7_RESERVED [63:53] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0xffe0000000000000,53,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0xffe0000000000000,53)
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_RESERVED_MASK 0xffe0000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_RESERVED_BITS 11
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_RESERVED_SHIFT 53

/* switch :: PAGE_42_PORT_EAP_CON_P7 :: PAGE_42_PORT_EAP_CON_P7_EAP_MODE [52:51] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0x18000000000000,51,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0x18000000000000,51)
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_MODE_MASK 0x0018000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_MODE_SHIFT 51

/* switch :: PAGE_42_PORT_EAP_CON_P7 :: PAGE_42_PORT_EAP_CON_P7_EAP_BLK_MODE [50:49] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_BLK_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0x6000000000000,49,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_BLK_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0x6000000000000,49)
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_BLK_MODE_MASK 0x0006000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_BLK_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_BLK_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_BLK_MODE_SHIFT 49

/* switch :: PAGE_42_PORT_EAP_CON_P7 :: PAGE_42_PORT_EAP_CON_P7_EAP_EN_UNI_DA [48:48] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_EN_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0x1000000000000,48,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_EN_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0x1000000000000,48)
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_EN_UNI_DA_MASK 0x0001000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_EN_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_EN_UNI_DA_BITS 1
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_EN_UNI_DA_SHIFT 48

/* switch :: PAGE_42_PORT_EAP_CON_P7 :: PAGE_42_PORT_EAP_CON_P7_EAP_UNI_DA [47:00] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0xffffffffffff,0,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_P7,0xffffffffffff,0)
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_UNI_DA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_UNI_DA_BITS 48
#define SWITCH_PAGE_42_PORT_EAP_CON_P7_PAGE_42_PORT_EAP_CON_P7_EAP_UNI_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_PORT_EAP_CON_IMP
 ***************************************************************************/
/* switch :: PAGE_42_PORT_EAP_CON_IMP :: PAGE_42_PORT_EAP_CON_IMP_RESERVED [63:53] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_RESERVED(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0xffe0000000000000,53,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_RESERVED(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0xffe0000000000000,53)
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_RESERVED_MASK 0xffe0000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_RESERVED_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_RESERVED_BITS 11
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_RESERVED_SHIFT 53

/* switch :: PAGE_42_PORT_EAP_CON_IMP :: PAGE_42_PORT_EAP_CON_IMP_EAP_MODE [52:51] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0x18000000000000,51,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0x18000000000000,51)
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_MODE_MASK 0x0018000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_MODE_SHIFT 51

/* switch :: PAGE_42_PORT_EAP_CON_IMP :: PAGE_42_PORT_EAP_CON_IMP_EAP_BLK_MODE [50:49] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_BLK_MODE(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0x6000000000000,49,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_BLK_MODE(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0x6000000000000,49)
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_BLK_MODE_MASK 0x0006000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_BLK_MODE_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_BLK_MODE_BITS 2
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_BLK_MODE_SHIFT 49

/* switch :: PAGE_42_PORT_EAP_CON_IMP :: PAGE_42_PORT_EAP_CON_IMP_EAP_EN_UNI_DA [48:48] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_EN_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0x1000000000000,48,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_EN_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0x1000000000000,48)
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_MASK 0x0001000000000000
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_BITS 1
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_EN_UNI_DA_SHIFT 48

/* switch :: PAGE_42_PORT_EAP_CON_IMP :: PAGE_42_PORT_EAP_CON_IMP_EAP_UNI_DA [47:00] */
#define Wr_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_UNI_DA(x) WriteRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0xffffffffffff,0,x)
#define Rd_switch_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_UNI_DA(x) ReadRegBits(SWITCH_PAGE_42_PORT_EAP_CON_IMP,0xffffffffffff,0)
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_UNI_DA_MASK 0x0000ffffffffffff
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_UNI_DA_ALIGN 0
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_UNI_DA_BITS 48
#define SWITCH_PAGE_42_PORT_EAP_CON_IMP_PAGE_42_PORT_EAP_CON_IMP_EAP_UNI_DA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_IEEE8021X_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_42_IEEE8021X_REG_SPARE0 :: PAGE_42_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_42_IEEE8021X_REG_SPARE0_PAGE_42_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0(x) WriteReg(SWITCH_PAGE_42_IEEE8021X_REG_SPARE0,x)
#define Rd_switch_PAGE_42_IEEE8021X_REG_SPARE0_PAGE_42_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0(x) ReadReg(SWITCH_PAGE_42_IEEE8021X_REG_SPARE0)
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE0_PAGE_42_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE0_PAGE_42_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE0_PAGE_42_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_BITS 32
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE0_PAGE_42_IEEE8021X_REG_SPARE0_IEEE8021X_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_42_IEEE8021X_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_42_IEEE8021X_REG_SPARE1 :: PAGE_42_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_42_IEEE8021X_REG_SPARE1_PAGE_42_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1(x) WriteReg(SWITCH_PAGE_42_IEEE8021X_REG_SPARE1,x)
#define Rd_switch_PAGE_42_IEEE8021X_REG_SPARE1_PAGE_42_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1(x) ReadReg(SWITCH_PAGE_42_IEEE8021X_REG_SPARE1)
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE1_PAGE_42_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE1_PAGE_42_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE1_PAGE_42_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_BITS 32
#define SWITCH_PAGE_42_IEEE8021X_REG_SPARE1_PAGE_42_IEEE8021X_REG_SPARE1_IEEE8021X_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_43_MST_CON
 ***************************************************************************/
/* switch :: PAGE_43_MST_CON :: PAGE_43_MST_CON_RESERVED [07:01] */
#define Wr_switch_PAGE_43_MST_CON_PAGE_43_MST_CON_RESERVED(x) WriteRegBits(SWITCH_PAGE_43_MST_CON,0xfe,1,x)
#define Rd_switch_PAGE_43_MST_CON_PAGE_43_MST_CON_RESERVED(x) ReadRegBits(SWITCH_PAGE_43_MST_CON,0xfe,1)
#define SWITCH_PAGE_43_MST_CON_PAGE_43_MST_CON_RESERVED_MASK       0xfe
#define SWITCH_PAGE_43_MST_CON_PAGE_43_MST_CON_RESERVED_ALIGN      0
#define SWITCH_PAGE_43_MST_CON_PAGE_43_MST_CON_RESERVED_BITS       7
#define SWITCH_PAGE_43_MST_CON_PAGE_43_MST_CON_RESERVED_SHIFT      1

/* switch :: PAGE_43_MST_CON :: PAGE_43_MST_CON_EN_802_1S [00:00] */
#define Wr_switch_PAGE_43_MST_CON_PAGE_43_MST_CON_EN_802_1S(x) WriteRegBits(SWITCH_PAGE_43_MST_CON,0x1,0,x)
#define Rd_switch_PAGE_43_MST_CON_PAGE_43_MST_CON_EN_802_1S(x) ReadRegBits(SWITCH_PAGE_43_MST_CON,0x1,0)
#define SWITCH_PAGE_43_MST_CON_PAGE_43_MST_CON_EN_802_1S_MASK      0x01
#define SWITCH_PAGE_43_MST_CON_PAGE_43_MST_CON_EN_802_1S_ALIGN     0
#define SWITCH_PAGE_43_MST_CON_PAGE_43_MST_CON_EN_802_1S_BITS      1
#define SWITCH_PAGE_43_MST_CON_PAGE_43_MST_CON_EN_802_1S_SHIFT     0


/****************************************************************************
 * switch :: PAGE_43_MST_AGE
 ***************************************************************************/
/* switch :: PAGE_43_MST_AGE :: PAGE_43_MST_AGE_RESERVED [31:08] */
#define Wr_switch_PAGE_43_MST_AGE_PAGE_43_MST_AGE_RESERVED(x) WriteRegBits(SWITCH_PAGE_43_MST_AGE,0xffffff00,8,x)
#define Rd_switch_PAGE_43_MST_AGE_PAGE_43_MST_AGE_RESERVED(x) ReadRegBits(SWITCH_PAGE_43_MST_AGE,0xffffff00,8)
#define SWITCH_PAGE_43_MST_AGE_PAGE_43_MST_AGE_RESERVED_MASK       0xffffff00
#define SWITCH_PAGE_43_MST_AGE_PAGE_43_MST_AGE_RESERVED_ALIGN      0
#define SWITCH_PAGE_43_MST_AGE_PAGE_43_MST_AGE_RESERVED_BITS       24
#define SWITCH_PAGE_43_MST_AGE_PAGE_43_MST_AGE_RESERVED_SHIFT      8

/* switch :: PAGE_43_MST_AGE :: PAGE_43_MST_AGE_AGE_EN_PRT [07:00] */
#define Wr_switch_PAGE_43_MST_AGE_PAGE_43_MST_AGE_AGE_EN_PRT(x) WriteRegBits(SWITCH_PAGE_43_MST_AGE,0xff,0,x)
#define Rd_switch_PAGE_43_MST_AGE_PAGE_43_MST_AGE_AGE_EN_PRT(x) ReadRegBits(SWITCH_PAGE_43_MST_AGE,0xff,0)
#define SWITCH_PAGE_43_MST_AGE_PAGE_43_MST_AGE_AGE_EN_PRT_MASK     0x000000ff
#define SWITCH_PAGE_43_MST_AGE_PAGE_43_MST_AGE_AGE_EN_PRT_ALIGN    0
#define SWITCH_PAGE_43_MST_AGE_PAGE_43_MST_AGE_AGE_EN_PRT_BITS     8
#define SWITCH_PAGE_43_MST_AGE_PAGE_43_MST_AGE_AGE_EN_PRT_SHIFT    0


/****************************************************************************
 * switch :: PAGE_43_MST_TAB_0
 ***************************************************************************/
/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_MST_TAB_RSRV [31:27] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_MST_TAB_RSRV(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0xf8000000,27,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_MST_TAB_RSRV(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0xf8000000,27)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_MST_TAB_RSRV_MASK 0xf8000000
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_MST_TAB_RSRV_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_MST_TAB_RSRV_BITS 5
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_MST_TAB_RSRV_SHIFT 27

/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_RESERVED_1 [26:24] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0x7000000,24,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0x7000000,24)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_RESERVED_1_MASK 0x07000000
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_RESERVED_1_BITS 3
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_RESERVED_1_SHIFT 24

/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_SPT_STA7 [23:21] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA7(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0xe00000,21,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA7(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0xe00000,21)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA7_MASK   0x00e00000
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA7_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA7_BITS   3
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA7_SHIFT  21

/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_SPT_STA6 [20:18] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA6(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0x1c0000,18,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA6(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0x1c0000,18)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA6_MASK   0x001c0000
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA6_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA6_BITS   3
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA6_SHIFT  18

/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_SPT_STA5 [17:15] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA5(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0x38000,15,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA5(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0x38000,15)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA5_MASK   0x00038000
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA5_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA5_BITS   3
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA5_SHIFT  15

/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_SPT_STA4 [14:12] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA4(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0x7000,12,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA4(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0x7000,12)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA4_MASK   0x00007000
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA4_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA4_BITS   3
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA4_SHIFT  12

/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_SPT_STA3 [11:09] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA3(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0xe00,9,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA3(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0xe00,9)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA3_MASK   0x00000e00
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA3_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA3_BITS   3
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA3_SHIFT  9

/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_SPT_STA2 [08:06] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA2(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0x1c0,6,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA2(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0x1c0,6)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA2_MASK   0x000001c0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA2_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA2_BITS   3
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA2_SHIFT  6

/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_SPT_STA1 [05:03] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0x38,3,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0x38,3)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA1_MASK   0x00000038
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA1_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA1_BITS   3
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA1_SHIFT  3

/* switch :: PAGE_43_MST_TAB_0 :: PAGE_43_MST_TAB_0_SPT_STA0 [02:00] */
#define Wr_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA0(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_0,0x7,0,x)
#define Rd_switch_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA0(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_0,0x7,0)
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA0_MASK   0x00000007
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA0_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA0_BITS   3
#define SWITCH_PAGE_43_MST_TAB_0_PAGE_43_MST_TAB_0_SPT_STA0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_43_MST_TAB_1
 ***************************************************************************/
/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_MST_TAB_RSRV [31:27] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_MST_TAB_RSRV(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0xf8000000,27,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_MST_TAB_RSRV(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0xf8000000,27)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_MST_TAB_RSRV_MASK 0xf8000000
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_MST_TAB_RSRV_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_MST_TAB_RSRV_BITS 5
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_MST_TAB_RSRV_SHIFT 27

/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_RESERVED_1 [26:24] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0x7000000,24,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0x7000000,24)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_RESERVED_1_MASK 0x07000000
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_RESERVED_1_BITS 3
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_RESERVED_1_SHIFT 24

/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_SPT_STA7 [23:21] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA7(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0xe00000,21,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA7(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0xe00000,21)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA7_MASK   0x00e00000
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA7_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA7_BITS   3
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA7_SHIFT  21

/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_SPT_STA6 [20:18] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA6(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0x1c0000,18,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA6(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0x1c0000,18)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA6_MASK   0x001c0000
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA6_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA6_BITS   3
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA6_SHIFT  18

/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_SPT_STA5 [17:15] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA5(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0x38000,15,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA5(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0x38000,15)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA5_MASK   0x00038000
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA5_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA5_BITS   3
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA5_SHIFT  15

/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_SPT_STA4 [14:12] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA4(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0x7000,12,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA4(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0x7000,12)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA4_MASK   0x00007000
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA4_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA4_BITS   3
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA4_SHIFT  12

/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_SPT_STA3 [11:09] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA3(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0xe00,9,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA3(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0xe00,9)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA3_MASK   0x00000e00
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA3_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA3_BITS   3
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA3_SHIFT  9

/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_SPT_STA2 [08:06] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA2(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0x1c0,6,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA2(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0x1c0,6)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA2_MASK   0x000001c0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA2_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA2_BITS   3
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA2_SHIFT  6

/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_SPT_STA1 [05:03] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0x38,3,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0x38,3)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA1_MASK   0x00000038
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA1_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA1_BITS   3
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA1_SHIFT  3

/* switch :: PAGE_43_MST_TAB_1 :: PAGE_43_MST_TAB_1_SPT_STA0 [02:00] */
#define Wr_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA0(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_1,0x7,0,x)
#define Rd_switch_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA0(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_1,0x7,0)
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA0_MASK   0x00000007
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA0_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA0_BITS   3
#define SWITCH_PAGE_43_MST_TAB_1_PAGE_43_MST_TAB_1_SPT_STA0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_43_MST_TAB_2
 ***************************************************************************/
/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_MST_TAB_RSRV [31:27] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_MST_TAB_RSRV(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0xf8000000,27,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_MST_TAB_RSRV(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0xf8000000,27)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_MST_TAB_RSRV_MASK 0xf8000000
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_MST_TAB_RSRV_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_MST_TAB_RSRV_BITS 5
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_MST_TAB_RSRV_SHIFT 27

/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_RESERVED_1 [26:24] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0x7000000,24,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0x7000000,24)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_RESERVED_1_MASK 0x07000000
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_RESERVED_1_BITS 3
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_RESERVED_1_SHIFT 24

/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_SPT_STA7 [23:21] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA7(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0xe00000,21,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA7(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0xe00000,21)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA7_MASK   0x00e00000
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA7_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA7_BITS   3
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA7_SHIFT  21

/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_SPT_STA6 [20:18] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA6(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0x1c0000,18,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA6(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0x1c0000,18)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA6_MASK   0x001c0000
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA6_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA6_BITS   3
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA6_SHIFT  18

/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_SPT_STA5 [17:15] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA5(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0x38000,15,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA5(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0x38000,15)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA5_MASK   0x00038000
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA5_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA5_BITS   3
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA5_SHIFT  15

/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_SPT_STA4 [14:12] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA4(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0x7000,12,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA4(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0x7000,12)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA4_MASK   0x00007000
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA4_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA4_BITS   3
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA4_SHIFT  12

/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_SPT_STA3 [11:09] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA3(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0xe00,9,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA3(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0xe00,9)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA3_MASK   0x00000e00
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA3_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA3_BITS   3
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA3_SHIFT  9

/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_SPT_STA2 [08:06] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA2(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0x1c0,6,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA2(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0x1c0,6)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA2_MASK   0x000001c0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA2_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA2_BITS   3
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA2_SHIFT  6

/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_SPT_STA1 [05:03] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0x38,3,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0x38,3)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA1_MASK   0x00000038
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA1_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA1_BITS   3
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA1_SHIFT  3

/* switch :: PAGE_43_MST_TAB_2 :: PAGE_43_MST_TAB_2_SPT_STA0 [02:00] */
#define Wr_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA0(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_2,0x7,0,x)
#define Rd_switch_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA0(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_2,0x7,0)
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA0_MASK   0x00000007
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA0_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA0_BITS   3
#define SWITCH_PAGE_43_MST_TAB_2_PAGE_43_MST_TAB_2_SPT_STA0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_43_MST_TAB_3
 ***************************************************************************/
/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_MST_TAB_RSRV [31:27] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_MST_TAB_RSRV(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0xf8000000,27,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_MST_TAB_RSRV(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0xf8000000,27)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_MST_TAB_RSRV_MASK 0xf8000000
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_MST_TAB_RSRV_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_MST_TAB_RSRV_BITS 5
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_MST_TAB_RSRV_SHIFT 27

/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_RESERVED_1 [26:24] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0x7000000,24,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0x7000000,24)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_RESERVED_1_MASK 0x07000000
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_RESERVED_1_BITS 3
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_RESERVED_1_SHIFT 24

/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_SPT_STA7 [23:21] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA7(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0xe00000,21,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA7(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0xe00000,21)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA7_MASK   0x00e00000
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA7_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA7_BITS   3
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA7_SHIFT  21

/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_SPT_STA6 [20:18] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA6(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0x1c0000,18,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA6(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0x1c0000,18)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA6_MASK   0x001c0000
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA6_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA6_BITS   3
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA6_SHIFT  18

/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_SPT_STA5 [17:15] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA5(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0x38000,15,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA5(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0x38000,15)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA5_MASK   0x00038000
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA5_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA5_BITS   3
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA5_SHIFT  15

/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_SPT_STA4 [14:12] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA4(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0x7000,12,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA4(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0x7000,12)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA4_MASK   0x00007000
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA4_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA4_BITS   3
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA4_SHIFT  12

/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_SPT_STA3 [11:09] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA3(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0xe00,9,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA3(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0xe00,9)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA3_MASK   0x00000e00
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA3_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA3_BITS   3
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA3_SHIFT  9

/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_SPT_STA2 [08:06] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA2(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0x1c0,6,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA2(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0x1c0,6)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA2_MASK   0x000001c0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA2_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA2_BITS   3
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA2_SHIFT  6

/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_SPT_STA1 [05:03] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0x38,3,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0x38,3)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA1_MASK   0x00000038
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA1_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA1_BITS   3
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA1_SHIFT  3

/* switch :: PAGE_43_MST_TAB_3 :: PAGE_43_MST_TAB_3_SPT_STA0 [02:00] */
#define Wr_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA0(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_3,0x7,0,x)
#define Rd_switch_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA0(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_3,0x7,0)
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA0_MASK   0x00000007
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA0_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA0_BITS   3
#define SWITCH_PAGE_43_MST_TAB_3_PAGE_43_MST_TAB_3_SPT_STA0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_43_MST_TAB_4
 ***************************************************************************/
/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_MST_TAB_RSRV [31:27] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_MST_TAB_RSRV(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0xf8000000,27,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_MST_TAB_RSRV(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0xf8000000,27)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_MST_TAB_RSRV_MASK 0xf8000000
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_MST_TAB_RSRV_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_MST_TAB_RSRV_BITS 5
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_MST_TAB_RSRV_SHIFT 27

/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_RESERVED_1 [26:24] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0x7000000,24,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0x7000000,24)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_RESERVED_1_MASK 0x07000000
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_RESERVED_1_BITS 3
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_RESERVED_1_SHIFT 24

/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_SPT_STA7 [23:21] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA7(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0xe00000,21,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA7(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0xe00000,21)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA7_MASK   0x00e00000
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA7_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA7_BITS   3
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA7_SHIFT  21

/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_SPT_STA6 [20:18] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA6(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0x1c0000,18,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA6(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0x1c0000,18)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA6_MASK   0x001c0000
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA6_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA6_BITS   3
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA6_SHIFT  18

/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_SPT_STA5 [17:15] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA5(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0x38000,15,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA5(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0x38000,15)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA5_MASK   0x00038000
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA5_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA5_BITS   3
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA5_SHIFT  15

/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_SPT_STA4 [14:12] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA4(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0x7000,12,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA4(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0x7000,12)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA4_MASK   0x00007000
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA4_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA4_BITS   3
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA4_SHIFT  12

/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_SPT_STA3 [11:09] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA3(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0xe00,9,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA3(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0xe00,9)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA3_MASK   0x00000e00
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA3_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA3_BITS   3
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA3_SHIFT  9

/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_SPT_STA2 [08:06] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA2(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0x1c0,6,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA2(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0x1c0,6)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA2_MASK   0x000001c0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA2_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA2_BITS   3
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA2_SHIFT  6

/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_SPT_STA1 [05:03] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0x38,3,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0x38,3)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA1_MASK   0x00000038
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA1_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA1_BITS   3
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA1_SHIFT  3

/* switch :: PAGE_43_MST_TAB_4 :: PAGE_43_MST_TAB_4_SPT_STA0 [02:00] */
#define Wr_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA0(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_4,0x7,0,x)
#define Rd_switch_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA0(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_4,0x7,0)
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA0_MASK   0x00000007
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA0_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA0_BITS   3
#define SWITCH_PAGE_43_MST_TAB_4_PAGE_43_MST_TAB_4_SPT_STA0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_43_MST_TAB_5
 ***************************************************************************/
/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_MST_TAB_RSRV [31:27] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_MST_TAB_RSRV(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0xf8000000,27,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_MST_TAB_RSRV(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0xf8000000,27)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_MST_TAB_RSRV_MASK 0xf8000000
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_MST_TAB_RSRV_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_MST_TAB_RSRV_BITS 5
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_MST_TAB_RSRV_SHIFT 27

/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_RESERVED_1 [26:24] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0x7000000,24,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0x7000000,24)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_RESERVED_1_MASK 0x07000000
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_RESERVED_1_BITS 3
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_RESERVED_1_SHIFT 24

/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_SPT_STA7 [23:21] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA7(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0xe00000,21,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA7(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0xe00000,21)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA7_MASK   0x00e00000
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA7_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA7_BITS   3
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA7_SHIFT  21

/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_SPT_STA6 [20:18] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA6(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0x1c0000,18,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA6(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0x1c0000,18)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA6_MASK   0x001c0000
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA6_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA6_BITS   3
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA6_SHIFT  18

/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_SPT_STA5 [17:15] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA5(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0x38000,15,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA5(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0x38000,15)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA5_MASK   0x00038000
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA5_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA5_BITS   3
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA5_SHIFT  15

/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_SPT_STA4 [14:12] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA4(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0x7000,12,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA4(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0x7000,12)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA4_MASK   0x00007000
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA4_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA4_BITS   3
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA4_SHIFT  12

/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_SPT_STA3 [11:09] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA3(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0xe00,9,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA3(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0xe00,9)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA3_MASK   0x00000e00
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA3_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA3_BITS   3
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA3_SHIFT  9

/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_SPT_STA2 [08:06] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA2(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0x1c0,6,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA2(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0x1c0,6)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA2_MASK   0x000001c0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA2_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA2_BITS   3
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA2_SHIFT  6

/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_SPT_STA1 [05:03] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0x38,3,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0x38,3)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA1_MASK   0x00000038
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA1_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA1_BITS   3
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA1_SHIFT  3

/* switch :: PAGE_43_MST_TAB_5 :: PAGE_43_MST_TAB_5_SPT_STA0 [02:00] */
#define Wr_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA0(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_5,0x7,0,x)
#define Rd_switch_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA0(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_5,0x7,0)
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA0_MASK   0x00000007
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA0_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA0_BITS   3
#define SWITCH_PAGE_43_MST_TAB_5_PAGE_43_MST_TAB_5_SPT_STA0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_43_MST_TAB_6
 ***************************************************************************/
/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_MST_TAB_RSRV [31:27] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_MST_TAB_RSRV(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0xf8000000,27,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_MST_TAB_RSRV(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0xf8000000,27)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_MST_TAB_RSRV_MASK 0xf8000000
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_MST_TAB_RSRV_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_MST_TAB_RSRV_BITS 5
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_MST_TAB_RSRV_SHIFT 27

/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_RESERVED_1 [26:24] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0x7000000,24,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0x7000000,24)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_RESERVED_1_MASK 0x07000000
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_RESERVED_1_BITS 3
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_RESERVED_1_SHIFT 24

/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_SPT_STA7 [23:21] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA7(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0xe00000,21,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA7(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0xe00000,21)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA7_MASK   0x00e00000
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA7_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA7_BITS   3
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA7_SHIFT  21

/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_SPT_STA6 [20:18] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA6(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0x1c0000,18,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA6(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0x1c0000,18)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA6_MASK   0x001c0000
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA6_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA6_BITS   3
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA6_SHIFT  18

/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_SPT_STA5 [17:15] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA5(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0x38000,15,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA5(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0x38000,15)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA5_MASK   0x00038000
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA5_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA5_BITS   3
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA5_SHIFT  15

/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_SPT_STA4 [14:12] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA4(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0x7000,12,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA4(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0x7000,12)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA4_MASK   0x00007000
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA4_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA4_BITS   3
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA4_SHIFT  12

/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_SPT_STA3 [11:09] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA3(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0xe00,9,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA3(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0xe00,9)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA3_MASK   0x00000e00
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA3_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA3_BITS   3
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA3_SHIFT  9

/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_SPT_STA2 [08:06] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA2(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0x1c0,6,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA2(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0x1c0,6)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA2_MASK   0x000001c0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA2_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA2_BITS   3
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA2_SHIFT  6

/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_SPT_STA1 [05:03] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0x38,3,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0x38,3)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA1_MASK   0x00000038
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA1_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA1_BITS   3
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA1_SHIFT  3

/* switch :: PAGE_43_MST_TAB_6 :: PAGE_43_MST_TAB_6_SPT_STA0 [02:00] */
#define Wr_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA0(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_6,0x7,0,x)
#define Rd_switch_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA0(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_6,0x7,0)
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA0_MASK   0x00000007
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA0_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA0_BITS   3
#define SWITCH_PAGE_43_MST_TAB_6_PAGE_43_MST_TAB_6_SPT_STA0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_43_MST_TAB_7
 ***************************************************************************/
/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_MST_TAB_RSRV [31:27] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_MST_TAB_RSRV(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0xf8000000,27,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_MST_TAB_RSRV(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0xf8000000,27)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_MST_TAB_RSRV_MASK 0xf8000000
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_MST_TAB_RSRV_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_MST_TAB_RSRV_BITS 5
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_MST_TAB_RSRV_SHIFT 27

/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_RESERVED_1 [26:24] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0x7000000,24,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0x7000000,24)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_RESERVED_1_MASK 0x07000000
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_RESERVED_1_BITS 3
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_RESERVED_1_SHIFT 24

/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_SPT_STA7 [23:21] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA7(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0xe00000,21,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA7(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0xe00000,21)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA7_MASK   0x00e00000
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA7_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA7_BITS   3
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA7_SHIFT  21

/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_SPT_STA6 [20:18] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA6(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0x1c0000,18,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA6(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0x1c0000,18)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA6_MASK   0x001c0000
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA6_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA6_BITS   3
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA6_SHIFT  18

/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_SPT_STA5 [17:15] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA5(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0x38000,15,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA5(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0x38000,15)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA5_MASK   0x00038000
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA5_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA5_BITS   3
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA5_SHIFT  15

/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_SPT_STA4 [14:12] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA4(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0x7000,12,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA4(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0x7000,12)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA4_MASK   0x00007000
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA4_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA4_BITS   3
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA4_SHIFT  12

/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_SPT_STA3 [11:09] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA3(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0xe00,9,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA3(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0xe00,9)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA3_MASK   0x00000e00
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA3_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA3_BITS   3
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA3_SHIFT  9

/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_SPT_STA2 [08:06] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA2(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0x1c0,6,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA2(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0x1c0,6)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA2_MASK   0x000001c0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA2_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA2_BITS   3
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA2_SHIFT  6

/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_SPT_STA1 [05:03] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA1(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0x38,3,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA1(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0x38,3)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA1_MASK   0x00000038
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA1_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA1_BITS   3
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA1_SHIFT  3

/* switch :: PAGE_43_MST_TAB_7 :: PAGE_43_MST_TAB_7_SPT_STA0 [02:00] */
#define Wr_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA0(x) WriteRegBits(SWITCH_PAGE_43_MST_TAB_7,0x7,0,x)
#define Rd_switch_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA0(x) ReadRegBits(SWITCH_PAGE_43_MST_TAB_7,0x7,0)
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA0_MASK   0x00000007
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA0_ALIGN  0
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA0_BITS   3
#define SWITCH_PAGE_43_MST_TAB_7_PAGE_43_MST_TAB_7_SPT_STA0_SHIFT  0


/****************************************************************************
 * switch :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL
 ***************************************************************************/
/* switch :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_RESERVED [15:06] */
#define Wr_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0xffc0,6,x)
#define Rd_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0xffc0,6)
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_RESERVED_MASK 0xffc0
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_RESERVED_BITS 10
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_RESERVED_SHIFT 6

/* switch :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT [05:05] */
#define Wr_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT(x) WriteRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x20,5,x)
#define Rd_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT(x) ReadRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x20,5)
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_MASK 0x0020
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_ALIGN 0
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_BITS 1
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT5_BYPASS_SPT_SHIFT 5

/* switch :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT [04:04] */
#define Wr_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT(x) WriteRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x10,4,x)
#define Rd_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT(x) ReadRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x10,4)
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_MASK 0x0010
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_ALIGN 0
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_BITS 1
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT4_BYPASS_SPT_SHIFT 4

/* switch :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT [03:03] */
#define Wr_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT(x) WriteRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x8,3,x)
#define Rd_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT(x) ReadRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x8,3)
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_MASK 0x0008
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_ALIGN 0
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_BITS 1
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT3_BYPASS_SPT_SHIFT 3

/* switch :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT [02:02] */
#define Wr_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT(x) WriteRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x4,2,x)
#define Rd_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT(x) ReadRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x4,2)
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_MASK 0x0004
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_ALIGN 0
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_BITS 1
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT2_BYPASS_SPT_SHIFT 2

/* switch :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT [01:01] */
#define Wr_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT(x) WriteRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x2,1,x)
#define Rd_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT(x) ReadRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x2,1)
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_MASK 0x0002
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_ALIGN 0
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_BITS 1
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT1_BYPASS_SPT_SHIFT 1

/* switch :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL :: PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT [00:00] */
#define Wr_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT(x) WriteRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x1,0,x)
#define Rd_switch_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT(x) ReadRegBits16(SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL,0x1,0)
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_MASK 0x0001
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_ALIGN 0
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_BITS 1
#define SWITCH_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_PAGE_43_SPT_MULTI_ADDR_BPS_CTRL_EN_MPORT0_BYPASS_SPT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_43_IEEE8021S_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_43_IEEE8021S_REG_SPARE0 :: PAGE_43_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_43_IEEE8021S_REG_SPARE0_PAGE_43_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0(x) WriteReg(SWITCH_PAGE_43_IEEE8021S_REG_SPARE0,x)
#define Rd_switch_PAGE_43_IEEE8021S_REG_SPARE0_PAGE_43_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0(x) ReadReg(SWITCH_PAGE_43_IEEE8021S_REG_SPARE0)
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE0_PAGE_43_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE0_PAGE_43_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE0_PAGE_43_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_BITS 32
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE0_PAGE_43_IEEE8021S_REG_SPARE0_IEEE8021S_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_43_IEEE8021S_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_43_IEEE8021S_REG_SPARE1 :: PAGE_43_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_43_IEEE8021S_REG_SPARE1_PAGE_43_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1(x) WriteReg(SWITCH_PAGE_43_IEEE8021S_REG_SPARE1,x)
#define Rd_switch_PAGE_43_IEEE8021S_REG_SPARE1_PAGE_43_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1(x) ReadReg(SWITCH_PAGE_43_IEEE8021S_REG_SPARE1)
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE1_PAGE_43_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE1_PAGE_43_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE1_PAGE_43_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_BITS 32
#define SWITCH_PAGE_43_IEEE8021S_REG_SPARE1_PAGE_43_IEEE8021S_REG_SPARE1_IEEE8021S_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_SA_LIMIT_ENABLE
 ***************************************************************************/
/* switch :: PAGE_45_SA_LIMIT_ENABLE :: PAGE_45_SA_LIMIT_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_SA_LIMIT_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_SA_LIMIT_ENABLE,0xfe00,9)
#define SWITCH_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_45_SA_LIMIT_ENABLE :: PAGE_45_SA_LIMIT_ENABLE_SA_LIMIT_EN [08:00] */
#define Wr_switch_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_SA_LIMIT_EN(x) WriteRegBits16(SWITCH_PAGE_45_SA_LIMIT_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_SA_LIMIT_EN(x) ReadRegBits16(SWITCH_PAGE_45_SA_LIMIT_ENABLE,0x1ff,0)
#define SWITCH_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_SA_LIMIT_EN_MASK 0x01ff
#define SWITCH_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_SA_LIMIT_EN_ALIGN 0
#define SWITCH_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_SA_LIMIT_EN_BITS 9
#define SWITCH_PAGE_45_SA_LIMIT_ENABLE_PAGE_45_SA_LIMIT_ENABLE_SA_LIMIT_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_SA_LRN_CNTR_RST
 ***************************************************************************/
/* switch :: PAGE_45_SA_LRN_CNTR_RST :: PAGE_45_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST [15:15] */
#define Wr_switch_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST(x) WriteRegBits16(SWITCH_PAGE_45_SA_LRN_CNTR_RST,0x8000,15,x)
#define Rd_switch_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST(x) ReadRegBits16(SWITCH_PAGE_45_SA_LRN_CNTR_RST,0x8000,15)
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_MASK 0x8000
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_ALIGN 0
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_BITS 1
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_TOTAL_SA_LRN_CNTR_RST_SHIFT 15

/* switch :: PAGE_45_SA_LRN_CNTR_RST :: PAGE_45_SA_LRN_CNTR_RST_RESERVED [14:09] */
#define Wr_switch_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_SA_LRN_CNTR_RST,0x7e00,9,x)
#define Rd_switch_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_SA_LRN_CNTR_RST,0x7e00,9)
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_RESERVED_MASK 0x7e00
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_RESERVED_BITS 6
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_RESERVED_SHIFT 9

/* switch :: PAGE_45_SA_LRN_CNTR_RST :: PAGE_45_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST [08:00] */
#define Wr_switch_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST(x) WriteRegBits16(SWITCH_PAGE_45_SA_LRN_CNTR_RST,0x1ff,0,x)
#define Rd_switch_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST(x) ReadRegBits16(SWITCH_PAGE_45_SA_LRN_CNTR_RST,0x1ff,0)
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_MASK 0x01ff
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_ALIGN 0
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_BITS 9
#define SWITCH_PAGE_45_SA_LRN_CNTR_RST_PAGE_45_SA_LRN_CNTR_RST_PORT_SA_LRN_CNTR_RST_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_SA_OVERLIMIT_CNTR_RST
 ***************************************************************************/
/* switch :: PAGE_45_SA_OVERLIMIT_CNTR_RST :: PAGE_45_SA_OVERLIMIT_CNTR_RST_RESERVED [15:09] */
#define Wr_switch_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST,0xfe00,9,x)
#define Rd_switch_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST,0xfe00,9)
#define SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_RESERVED_BITS 7
#define SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_RESERVED_SHIFT 9

/* switch :: PAGE_45_SA_OVERLIMIT_CNTR_RST :: PAGE_45_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST [08:00] */
#define Wr_switch_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST(x) WriteRegBits16(SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST,0x1ff,0,x)
#define Rd_switch_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST(x) ReadRegBits16(SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST,0x1ff,0)
#define SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_MASK 0x01ff
#define SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_ALIGN 0
#define SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_BITS 9
#define SWITCH_PAGE_45_SA_OVERLIMIT_CNTR_RST_PAGE_45_SA_OVERLIMIT_CNTR_RST_PORT_SA_OVER_LIMIT_CNTR_RST_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_TOTAL_SA_LIMIT_CTL
 ***************************************************************************/
/* switch :: PAGE_45_TOTAL_SA_LIMIT_CTL :: PAGE_45_TOTAL_SA_LIMIT_CTL_RESERVED [15:13] */
#define Wr_switch_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL,0xe000,13,x)
#define Rd_switch_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL,0xe000,13)
#define SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_RESERVED_MASK 0xe000
#define SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_RESERVED_BITS 3
#define SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_RESERVED_SHIFT 13

/* switch :: PAGE_45_TOTAL_SA_LIMIT_CTL :: PAGE_45_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM [12:00] */
#define Wr_switch_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM(x) WriteRegBits16(SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL,0x1fff,0,x)
#define Rd_switch_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM(x) ReadRegBits16(SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL,0x1fff,0)
#define SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_MASK 0x1fff
#define SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_ALIGN 0
#define SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_BITS 13
#define SWITCH_PAGE_45_TOTAL_SA_LIMIT_CTL_PAGE_45_TOTAL_SA_LIMIT_CTL_TOTAL_SA_LRN_CNT_LIM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port0
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port0 :: PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_0 [15:14] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port0_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_0(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0,0xc000,14,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port0_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_0(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0,0xc000,14)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_0_MASK 0xc000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_0_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_0_BITS 2
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_0_SHIFT 14

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port0 :: PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_0 [13:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port0_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0,0x2000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port0_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0,0x2000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_0_MASK 0x2000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_0_BITS 1
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_0_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port0 :: PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_0 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port0_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_0(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port0_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_0(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_0_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_0_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_0_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT0_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port1
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port1 :: PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_1 [15:14] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port1_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_1(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1,0xc000,14,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port1_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_1(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1,0xc000,14)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_1_MASK 0xc000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_1_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_1_BITS 2
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_1_SHIFT 14

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port1 :: PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_1 [13:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port1_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1,0x2000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port1_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1,0x2000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_1_MASK 0x2000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_1_BITS 1
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_1_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port1 :: PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_1 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port1_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_1(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port1_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_1(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_1_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_1_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_1_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT1_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port2
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port2 :: PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_2 [15:14] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port2_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_2(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2,0xc000,14,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port2_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_2(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2,0xc000,14)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_2_MASK 0xc000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_2_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_2_BITS 2
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_2_SHIFT 14

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port2 :: PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_2 [13:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port2_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_2(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2,0x2000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port2_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_2(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2,0x2000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_2_MASK 0x2000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_2_BITS 1
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_2_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port2 :: PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_2 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port2_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_2(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port2_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_2(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_2_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_2_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_2_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT2_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port3
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port3 :: PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_3 [15:14] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port3_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_3(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3,0xc000,14,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port3_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_3(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3,0xc000,14)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_3_MASK 0xc000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_3_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_3_BITS 2
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_3_SHIFT 14

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port3 :: PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_3 [13:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port3_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_3(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3,0x2000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port3_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_3(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3,0x2000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_3_MASK 0x2000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_3_BITS 1
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_3_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port3 :: PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_3 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port3_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_3(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port3_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_3(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_3_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_3_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_3_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT3_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port4
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port4 :: PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_4 [15:14] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port4_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_4(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4,0xc000,14,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port4_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_4(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4,0xc000,14)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_4_MASK 0xc000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_4_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_4_BITS 2
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_4_SHIFT 14

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port4 :: PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_4 [13:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port4_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_4(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4,0x2000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port4_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_4(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4,0x2000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_4_MASK 0x2000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_4_BITS 1
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_4_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port4 :: PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_4 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port4_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_4(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port4_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_4(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_4_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_4_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_4_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT4_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port5
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port5 :: PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_5 [15:14] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port5_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_5(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5,0xc000,14,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port5_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_5(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5,0xc000,14)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_5_MASK 0xc000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_5_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_5_BITS 2
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_5_SHIFT 14

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port5 :: PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_5 [13:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port5_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_5(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5,0x2000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port5_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_5(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5,0x2000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_5_MASK 0x2000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_5_BITS 1
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_5_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port5 :: PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_5 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port5_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_5(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port5_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_5(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_5_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_5_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_5_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT5_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port6
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port6 :: PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_6 [15:14] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port6_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_6(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6,0xc000,14,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port6_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_6(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6,0xc000,14)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_6_MASK 0xc000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_6_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_6_BITS 2
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_6_SHIFT 14

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port6 :: PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_6 [13:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port6_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_6(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6,0x2000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port6_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_6(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6,0x2000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_6_MASK 0x2000
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_6_BITS 1
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_RESERVED_6_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LIMIT_CTL_port6 :: PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_6 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port6_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_6(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LIMIT_CTL_port6_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_6(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_6_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_6_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_6_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LIMIT_CTL_PORT6_PAGE_45_PORT_N_SA_LIMIT_CTL_SA_LRN_CNT_LIM_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_7_SA_LIMIT_CTL
 ***************************************************************************/
/* switch :: PAGE_45_PORT_7_SA_LIMIT_CTL :: PAGE_45_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS [15:14] */
#define Wr_switch_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS(x) WriteRegBits16(SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL,0xc000,14,x)
#define Rd_switch_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS(x) ReadRegBits16(SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL,0xc000,14)
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_MASK 0xc000
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_ALIGN 0
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_BITS 2
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_SHIFT 14

/* switch :: PAGE_45_PORT_7_SA_LIMIT_CTL :: PAGE_45_PORT_7_SA_LIMIT_CTL_RESERVED [13:13] */
#define Wr_switch_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL,0x2000,13,x)
#define Rd_switch_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL,0x2000,13)
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_RESERVED_MASK 0x2000
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_RESERVED_BITS 1
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_RESERVED_SHIFT 13

/* switch :: PAGE_45_PORT_7_SA_LIMIT_CTL :: PAGE_45_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM [12:00] */
#define Wr_switch_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM(x) WriteRegBits16(SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM(x) ReadRegBits16(SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL,0x1fff,0)
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_ALIGN 0
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_BITS 13
#define SWITCH_PAGE_45_PORT_7_SA_LIMIT_CTL_PAGE_45_PORT_7_SA_LIMIT_CTL_SA_LRN_CNT_LIM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_8_SA_LIMIT_CTL
 ***************************************************************************/
/* switch :: PAGE_45_PORT_8_SA_LIMIT_CTL :: PAGE_45_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS [15:14] */
#define Wr_switch_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS(x) WriteRegBits16(SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL,0xc000,14,x)
#define Rd_switch_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS(x) ReadRegBits16(SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL,0xc000,14)
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_MASK 0xc000
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_ALIGN 0
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_BITS 2
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_OVER_LIMIT_ACTIONS_SHIFT 14

/* switch :: PAGE_45_PORT_8_SA_LIMIT_CTL :: PAGE_45_PORT_8_SA_LIMIT_CTL_RESERVED [13:13] */
#define Wr_switch_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL,0x2000,13,x)
#define Rd_switch_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL,0x2000,13)
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_RESERVED_MASK 0x2000
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_RESERVED_BITS 1
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_RESERVED_SHIFT 13

/* switch :: PAGE_45_PORT_8_SA_LIMIT_CTL :: PAGE_45_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM [12:00] */
#define Wr_switch_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM(x) WriteRegBits16(SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM(x) ReadRegBits16(SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL,0x1fff,0)
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_ALIGN 0
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_BITS 13
#define SWITCH_PAGE_45_PORT_8_SA_LIMIT_CTL_PAGE_45_PORT_8_SA_LIMIT_CTL_SA_LRN_CNT_LIM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_TOTAL_SA_LRN_CNTR
 ***************************************************************************/
/* switch :: PAGE_45_TOTAL_SA_LRN_CNTR :: PAGE_45_TOTAL_SA_LRN_CNTR_RESERVED [15:13] */
#define Wr_switch_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR,0xe000,13,x)
#define Rd_switch_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR,0xe000,13)
#define SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_RESERVED_MASK 0xe000
#define SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_RESERVED_BITS 3
#define SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_RESERVED_SHIFT 13

/* switch :: PAGE_45_TOTAL_SA_LRN_CNTR :: PAGE_45_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO [12:00] */
#define Wr_switch_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO(x) WriteRegBits16(SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR,0x1fff,0,x)
#define Rd_switch_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO(x) ReadRegBits16(SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR,0x1fff,0)
#define SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_MASK 0x1fff
#define SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_ALIGN 0
#define SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_BITS 13
#define SWITCH_PAGE_45_TOTAL_SA_LRN_CNTR_PAGE_45_TOTAL_SA_LRN_CNTR_TOTAL_SA_LRN_CNT_NO_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port0
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port0 :: PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_0 [15:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port0_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0,0xe000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port0_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0,0xe000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_0_MASK 0xe000
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_0_BITS 3
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_0_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port0 :: PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_0 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port0_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_0(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port0_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_0(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_0_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_0_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_0_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT0_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port1
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port1 :: PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_1 [15:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port1_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1,0xe000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port1_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1,0xe000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_1_MASK 0xe000
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_1_BITS 3
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_1_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port1 :: PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_1 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port1_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_1(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port1_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_1(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_1_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_1_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_1_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT1_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port2
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port2 :: PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_2 [15:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port2_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_2(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2,0xe000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port2_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_2(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2,0xe000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_2_MASK 0xe000
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_2_BITS 3
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_2_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port2 :: PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_2 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port2_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_2(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port2_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_2(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_2_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_2_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_2_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT2_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port3
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port3 :: PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_3 [15:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port3_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_3(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3,0xe000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port3_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_3(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3,0xe000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_3_MASK 0xe000
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_3_BITS 3
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_3_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port3 :: PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_3 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port3_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_3(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port3_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_3(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_3_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_3_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_3_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT3_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port4
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port4 :: PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_4 [15:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port4_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_4(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4,0xe000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port4_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_4(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4,0xe000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_4_MASK 0xe000
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_4_BITS 3
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_4_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port4 :: PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_4 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port4_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_4(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port4_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_4(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_4_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_4_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_4_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT4_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port5
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port5 :: PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_5 [15:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port5_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_5(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5,0xe000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port5_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_5(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5,0xe000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_5_MASK 0xe000
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_5_BITS 3
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_5_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port5 :: PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_5 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port5_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_5(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port5_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_5(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_5_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_5_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_5_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT5_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port6
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port6 :: PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_6 [15:13] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port6_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_6(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6,0xe000,13,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port6_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_6(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6,0xe000,13)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_6_MASK 0xe000
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_6_BITS 3
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6_PAGE_45_PORT_N_SA_LRN_CNTR_RESERVED_6_SHIFT 13

/* switch :: PAGE_45_PORT_N_SA_LRN_CNTR_port6 :: PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_6 [12:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port6_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_6(x) WriteRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_LRN_CNTR_port6_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_6(x) ReadRegBits16(SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6,0x1fff,0)
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_6_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_6_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_6_BITS 13
#define SWITCH_PAGE_45_PORT_N_SA_LRN_CNTR_PORT6_PAGE_45_PORT_N_SA_LRN_CNTR_SA_LRN_CNT_NO_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_7_SA_LRN_CNTR
 ***************************************************************************/
/* switch :: PAGE_45_PORT_7_SA_LRN_CNTR :: PAGE_45_PORT_7_SA_LRN_CNTR_RESERVED [15:13] */
#define Wr_switch_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR,0xe000,13,x)
#define Rd_switch_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR,0xe000,13)
#define SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_RESERVED_MASK 0xe000
#define SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_RESERVED_BITS 3
#define SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_RESERVED_SHIFT 13

/* switch :: PAGE_45_PORT_7_SA_LRN_CNTR :: PAGE_45_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO [12:00] */
#define Wr_switch_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO(x) WriteRegBits16(SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO(x) ReadRegBits16(SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR,0x1fff,0)
#define SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_ALIGN 0
#define SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_BITS 13
#define SWITCH_PAGE_45_PORT_7_SA_LRN_CNTR_PAGE_45_PORT_7_SA_LRN_CNTR_SA_LRN_CNT_NO_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_8_SA_LRN_CNTR
 ***************************************************************************/
/* switch :: PAGE_45_PORT_8_SA_LRN_CNTR :: PAGE_45_PORT_8_SA_LRN_CNTR_RESERVED [15:13] */
#define Wr_switch_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR,0xe000,13,x)
#define Rd_switch_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR,0xe000,13)
#define SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_RESERVED_MASK 0xe000
#define SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_RESERVED_BITS 3
#define SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_RESERVED_SHIFT 13

/* switch :: PAGE_45_PORT_8_SA_LRN_CNTR :: PAGE_45_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO [12:00] */
#define Wr_switch_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO(x) WriteRegBits16(SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR,0x1fff,0,x)
#define Rd_switch_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO(x) ReadRegBits16(SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR,0x1fff,0)
#define SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_MASK 0x1fff
#define SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_ALIGN 0
#define SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_BITS 13
#define SWITCH_PAGE_45_PORT_8_SA_LRN_CNTR_PAGE_45_PORT_8_SA_LRN_CNTR_SA_LRN_CNT_NO_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port0
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port0 :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_0 [31:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port0_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_0(x) WriteReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT0,x)
#define Rd_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port0_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_0(x) ReadReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT0)
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT0_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_0_MASK 0xffffffff
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT0_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_0_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT0_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_0_BITS 32
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT0_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port1
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port1 :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_1 [31:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port1_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_1(x) WriteReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT1,x)
#define Rd_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port1_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_1(x) ReadReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT1)
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT1_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_1_MASK 0xffffffff
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT1_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_1_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT1_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_1_BITS 32
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT1_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port2
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port2 :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_2 [31:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port2_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_2(x) WriteReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT2,x)
#define Rd_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port2_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_2(x) ReadReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT2)
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT2_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_2_MASK 0xffffffff
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT2_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_2_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT2_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_2_BITS 32
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT2_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port3
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port3 :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_3 [31:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port3_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_3(x) WriteReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT3,x)
#define Rd_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port3_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_3(x) ReadReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT3)
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT3_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_3_MASK 0xffffffff
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT3_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_3_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT3_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_3_BITS 32
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT3_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port4
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port4 :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_4 [31:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port4_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_4(x) WriteReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT4,x)
#define Rd_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port4_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_4(x) ReadReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT4)
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT4_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_4_MASK 0xffffffff
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT4_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_4_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT4_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_4_BITS 32
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT4_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port5
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port5 :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_5 [31:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port5_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_5(x) WriteReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT5,x)
#define Rd_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port5_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_5(x) ReadReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT5)
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT5_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_5_MASK 0xffffffff
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT5_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_5_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT5_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_5_BITS 32
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT5_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port6
 ***************************************************************************/
/* switch :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port6 :: PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_6 [31:00] */
#define Wr_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port6_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_6(x) WriteReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT6,x)
#define Rd_switch_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_port6_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_6(x) ReadReg(SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT6)
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT6_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_6_MASK 0xffffffff
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT6_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_6_ALIGN 0
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT6_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_6_BITS 32
#define SWITCH_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_PORT6_PAGE_45_PORT_N_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_7_SA_OVERLIMIT_CNTR
 ***************************************************************************/
/* switch :: PAGE_45_PORT_7_SA_OVERLIMIT_CNTR :: PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR [31:00] */
#define Wr_switch_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR(x) WriteReg(SWITCH_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR,x)
#define Rd_switch_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR(x) ReadReg(SWITCH_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR)
#define SWITCH_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
#define SWITCH_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_ALIGN 0
#define SWITCH_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_BITS 32
#define SWITCH_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_PAGE_45_PORT_7_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_PORT_8_SA_OVERLIMIT_CNTR
 ***************************************************************************/
/* switch :: PAGE_45_PORT_8_SA_OVERLIMIT_CNTR :: PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR [31:00] */
#define Wr_switch_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR(x) WriteReg(SWITCH_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR,x)
#define Rd_switch_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR(x) ReadReg(SWITCH_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR)
#define SWITCH_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_MASK 0xffffffff
#define SWITCH_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_ALIGN 0
#define SWITCH_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_BITS 32
#define SWITCH_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_PAGE_45_PORT_8_SA_OVERLIMIT_CNTR_SA_OVER_LIMIT_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT
 ***************************************************************************/
/* switch :: PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT :: PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_RESERVED [15:04] */
#define Wr_switch_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT,0xfff0,4,x)
#define Rd_switch_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT,0xfff0,4)
#define SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_RESERVED_MASK 0xfff0
#define SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_RESERVED_BITS 12
#define SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_RESERVED_SHIFT 4

/* switch :: PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT :: PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID [03:00] */
#define Wr_switch_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID(x) WriteRegBits16(SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT,0xf,0,x)
#define Rd_switch_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID(x) ReadRegBits16(SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT,0xf,0)
#define SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_MASK 0x000f
#define SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_ALIGN 0
#define SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_BITS 4
#define SWITCH_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_PAGE_45_SA_OVER_LIMIT_COPY_REDIRECT_COPY_REDIRECT_PORT_ID_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_MAC_LIMIT_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_45_MAC_LIMIT_REG_SPARE0 :: PAGE_45_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_45_MAC_LIMIT_REG_SPARE0_PAGE_45_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0(x) WriteReg(SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE0,x)
#define Rd_switch_PAGE_45_MAC_LIMIT_REG_SPARE0_PAGE_45_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0(x) ReadReg(SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE0)
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE0_PAGE_45_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE0_PAGE_45_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE0_PAGE_45_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_BITS 32
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE0_PAGE_45_MAC_LIMIT_REG_SPARE0_MAC_LIMIT_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_45_MAC_LIMIT_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_45_MAC_LIMIT_REG_SPARE1 :: PAGE_45_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_45_MAC_LIMIT_REG_SPARE1_PAGE_45_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1(x) WriteReg(SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE1,x)
#define Rd_switch_PAGE_45_MAC_LIMIT_REG_SPARE1_PAGE_45_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1(x) ReadReg(SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE1)
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE1_PAGE_45_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE1_PAGE_45_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE1_PAGE_45_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_BITS 32
#define SWITCH_PAGE_45_MAC_LIMIT_REG_SPARE1_PAGE_45_MAC_LIMIT_REG_SPARE1_MAC_LIMIT_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_PRI_CTL_port0
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_PRI_CTL_port0 :: PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_0 [07:07] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x80,7,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x80,7)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_0_MASK 0x80
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_0_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_0_SHIFT 7

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port0 :: PAGE_46_PN_QOS_PRI_CTL_RESERVED_0 [06:06] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x40,6,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x40,6)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_RESERVED_0_MASK 0x40
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_RESERVED_0_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_RESERVED_0_SHIFT 6

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port0 :: PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_0 [05:05] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x20,5,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x20,5)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_0_MASK 0x20
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_0_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_0_SHIFT 5

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port0 :: PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_0 [04:04] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x10,4,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x10,4)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_0_MASK 0x10
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_0_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_0_SHIFT 4

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port0 :: PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_0 [03:03] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x8,3,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x8,3)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_0_MASK 0x08
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_0_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_0_SHIFT 3

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port0 :: PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_0 [02:00] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x7,0,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port0_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0,0x7,0)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_0_MASK 0x07
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_0_BITS 3
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT0_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_PRI_CTL_port1
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_PRI_CTL_port1 :: PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_1 [07:07] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x80,7,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x80,7)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_1_MASK 0x80
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_1_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_1_SHIFT 7

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port1 :: PAGE_46_PN_QOS_PRI_CTL_RESERVED_1 [06:06] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x40,6,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x40,6)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_RESERVED_1_MASK 0x40
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_RESERVED_1_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_RESERVED_1_SHIFT 6

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port1 :: PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_1 [05:05] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x20,5,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x20,5)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_1_MASK 0x20
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_1_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_1_SHIFT 5

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port1 :: PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_1 [04:04] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x10,4,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x10,4)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_1_MASK 0x10
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_1_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_1_SHIFT 4

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port1 :: PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_1 [03:03] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x8,3,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x8,3)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_1_MASK 0x08
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_1_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_1_SHIFT 3

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port1 :: PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_1 [02:00] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x7,0,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port1_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1,0x7,0)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_1_MASK 0x07
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_1_BITS 3
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT1_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_PRI_CTL_port2
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_PRI_CTL_port2 :: PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_2 [07:07] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x80,7,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x80,7)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_2_MASK 0x80
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_2_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_2_SHIFT 7

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port2 :: PAGE_46_PN_QOS_PRI_CTL_RESERVED_2 [06:06] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x40,6,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x40,6)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_RESERVED_2_MASK 0x40
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_RESERVED_2_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_RESERVED_2_SHIFT 6

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port2 :: PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_2 [05:05] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x20,5,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x20,5)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_2_MASK 0x20
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_2_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_2_SHIFT 5

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port2 :: PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_2 [04:04] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x10,4,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x10,4)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_2_MASK 0x10
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_2_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_2_SHIFT 4

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port2 :: PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_2 [03:03] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x8,3,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x8,3)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_2_MASK 0x08
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_2_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_2_SHIFT 3

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port2 :: PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_2 [02:00] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x7,0,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port2_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2,0x7,0)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_2_MASK 0x07
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_2_BITS 3
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT2_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_PRI_CTL_port3
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_PRI_CTL_port3 :: PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_3 [07:07] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x80,7,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x80,7)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_3_MASK 0x80
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_3_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_3_SHIFT 7

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port3 :: PAGE_46_PN_QOS_PRI_CTL_RESERVED_3 [06:06] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x40,6,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x40,6)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_RESERVED_3_MASK 0x40
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_RESERVED_3_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_RESERVED_3_SHIFT 6

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port3 :: PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_3 [05:05] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x20,5,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x20,5)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_3_MASK 0x20
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_3_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_3_SHIFT 5

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port3 :: PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_3 [04:04] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x10,4,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x10,4)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_3_MASK 0x10
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_3_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_3_SHIFT 4

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port3 :: PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_3 [03:03] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x8,3,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x8,3)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_3_MASK 0x08
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_3_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_3_SHIFT 3

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port3 :: PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_3 [02:00] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x7,0,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port3_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3,0x7,0)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_3_MASK 0x07
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_3_BITS 3
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT3_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_PRI_CTL_port4
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_PRI_CTL_port4 :: PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_4 [07:07] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x80,7,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x80,7)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_4_MASK 0x80
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_4_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_4_SHIFT 7

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port4 :: PAGE_46_PN_QOS_PRI_CTL_RESERVED_4 [06:06] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x40,6,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x40,6)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_RESERVED_4_MASK 0x40
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_RESERVED_4_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_RESERVED_4_SHIFT 6

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port4 :: PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_4 [05:05] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x20,5,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x20,5)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_4_MASK 0x20
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_4_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_4_SHIFT 5

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port4 :: PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_4 [04:04] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x10,4,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x10,4)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_4_MASK 0x10
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_4_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_4_SHIFT 4

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port4 :: PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_4 [03:03] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x8,3,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x8,3)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_4_MASK 0x08
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_4_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_4_SHIFT 3

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port4 :: PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_4 [02:00] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x7,0,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port4_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4,0x7,0)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_4_MASK 0x07
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_4_BITS 3
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT4_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_PRI_CTL_port5
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_PRI_CTL_port5 :: PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_5 [07:07] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x80,7,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x80,7)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_5_MASK 0x80
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_5_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_5_SHIFT 7

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port5 :: PAGE_46_PN_QOS_PRI_CTL_RESERVED_5 [06:06] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x40,6,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x40,6)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_RESERVED_5_MASK 0x40
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_RESERVED_5_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_RESERVED_5_SHIFT 6

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port5 :: PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_5 [05:05] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x20,5,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x20,5)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_5_MASK 0x20
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_5_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_5_SHIFT 5

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port5 :: PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_5 [04:04] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x10,4,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x10,4)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_5_MASK 0x10
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_5_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_5_SHIFT 4

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port5 :: PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_5 [03:03] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x8,3,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x8,3)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_5_MASK 0x08
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_5_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_5_SHIFT 3

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port5 :: PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_5 [02:00] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x7,0,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port5_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5,0x7,0)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_5_MASK 0x07
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_5_BITS 3
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT5_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_PRI_CTL_port6
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_PRI_CTL_port6 :: PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_6 [07:07] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x80,7,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x80,7)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_6_MASK 0x80
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_6_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_6_SHIFT 7

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port6 :: PAGE_46_PN_QOS_PRI_CTL_RESERVED_6 [06:06] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x40,6,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x40,6)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_RESERVED_6_MASK 0x40
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_RESERVED_6_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_RESERVED_6_SHIFT 6

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port6 :: PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_6 [05:05] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x20,5,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x20,5)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_6_MASK 0x20
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_6_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_6_SHIFT 5

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port6 :: PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_6 [04:04] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x10,4,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x10,4)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_6_MASK 0x10
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_6_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_6_SHIFT 4

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port6 :: PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_6 [03:03] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x8,3,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x8,3)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_6_MASK 0x08
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_6_BITS 1
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_WDRR_GRANULARITY_6_SHIFT 3

/* switch :: PAGE_46_PN_QOS_PRI_CTL_port6 :: PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_6 [02:00] */
#define Wr_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x7,0,x)
#define Rd_switch_PAGE_46_PN_QOS_PRI_CTL_port6_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6,0x7,0)
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_6_MASK 0x07
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_6_BITS 3
#define SWITCH_PAGE_46_PN_QOS_PRI_CTL_PORT6_PAGE_46_PN_QOS_PRI_CTL_SCHEDULER_SELECT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_P7_QOS_PRI_CTL
 ***************************************************************************/
/* switch :: PAGE_46_P7_QOS_PRI_CTL :: PAGE_46_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT [07:07] */
#define Wr_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x80,7,x)
#define Rd_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x80,7)
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_MASK 0x80
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_BITS 1
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_SHIFT 7

/* switch :: PAGE_46_P7_QOS_PRI_CTL :: PAGE_46_P7_QOS_PRI_CTL_RESERVED [06:06] */
#define Wr_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_RESERVED(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x40,6,x)
#define Rd_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_RESERVED(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x40,6)
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_RESERVED_MASK 0x40
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_RESERVED_BITS 1
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_RESERVED_SHIFT 6

/* switch :: PAGE_46_P7_QOS_PRI_CTL :: PAGE_46_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
#define Wr_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x20,5,x)
#define Rd_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x20,5)
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x20
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_BITS 1
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5

/* switch :: PAGE_46_P7_QOS_PRI_CTL :: PAGE_46_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
#define Wr_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x10,4,x)
#define Rd_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x10,4)
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x10
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_BITS 1
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4

/* switch :: PAGE_46_P7_QOS_PRI_CTL :: PAGE_46_P7_QOS_PRI_CTL_WDRR_GRANULARITY [03:03] */
#define Wr_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_WDRR_GRANULARITY(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x8,3,x)
#define Rd_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_WDRR_GRANULARITY(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x8,3)
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_WDRR_GRANULARITY_MASK 0x08
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_WDRR_GRANULARITY_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_WDRR_GRANULARITY_BITS 1
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_WDRR_GRANULARITY_SHIFT 3

/* switch :: PAGE_46_P7_QOS_PRI_CTL :: PAGE_46_P7_QOS_PRI_CTL_SCHEDULER_SELECT [02:00] */
#define Wr_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_SCHEDULER_SELECT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x7,0,x)
#define Rd_switch_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_SCHEDULER_SELECT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_PRI_CTL,0x7,0)
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_SCHEDULER_SELECT_MASK 0x07
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_SCHEDULER_SELECT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_SCHEDULER_SELECT_BITS 3
#define SWITCH_PAGE_46_P7_QOS_PRI_CTL_PAGE_46_P7_QOS_PRI_CTL_SCHEDULER_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_IMP_QOS_PRI_CTL
 ***************************************************************************/
/* switch :: PAGE_46_IMP_QOS_PRI_CTL :: PAGE_46_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT [07:07] */
#define Wr_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x80,7,x)
#define Rd_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x80,7)
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_MASK 0x80
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_BITS 1
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_TXQ_EMPTY_STATUS_SELECT_SHIFT 7

/* switch :: PAGE_46_IMP_QOS_PRI_CTL :: PAGE_46_IMP_QOS_PRI_CTL_RESERVED [06:06] */
#define Wr_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_RESERVED(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x40,6,x)
#define Rd_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_RESERVED(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x40,6)
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_RESERVED_MASK 0x40
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_RESERVED_BITS 1
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_RESERVED_SHIFT 6

/* switch :: PAGE_46_IMP_QOS_PRI_CTL :: PAGE_46_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE [05:05] */
#define Wr_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x20,5,x)
#define Rd_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x20,5)
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_MASK 0x20
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_BITS 1
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_NEGATIVE_CREDIT_CLR_DISABLE_SHIFT 5

/* switch :: PAGE_46_IMP_QOS_PRI_CTL :: PAGE_46_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE [04:04] */
#define Wr_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x10,4,x)
#define Rd_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x10,4)
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_MASK 0x10
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_BITS 1
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_ROUNDROBIN_BURST_MODE_ENABLE_SHIFT 4

/* switch :: PAGE_46_IMP_QOS_PRI_CTL :: PAGE_46_IMP_QOS_PRI_CTL_WDRR_GRANULARITY [03:03] */
#define Wr_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_WDRR_GRANULARITY(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x8,3,x)
#define Rd_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_WDRR_GRANULARITY(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x8,3)
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_MASK 0x08
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_BITS 1
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_WDRR_GRANULARITY_SHIFT 3

/* switch :: PAGE_46_IMP_QOS_PRI_CTL :: PAGE_46_IMP_QOS_PRI_CTL_SCHEDULER_SELECT [02:00] */
#define Wr_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_SCHEDULER_SELECT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x7,0,x)
#define Rd_switch_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_SCHEDULER_SELECT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_PRI_CTL,0x7,0)
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_MASK 0x07
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_BITS 3
#define SWITCH_PAGE_46_IMP_QOS_PRI_CTL_PAGE_46_IMP_QOS_PRI_CTL_SCHEDULER_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_WEIGHT_port0
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_WEIGHT_port0 :: PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_0 [63:56] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff00000000000000,56,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff00000000000000,56)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_0_MASK 0xff00000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_0_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_0_SHIFT 56

/* switch :: PAGE_46_PN_QOS_WEIGHT_port0 :: PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_0 [55:48] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff000000000000,48,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff000000000000,48)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_0_MASK 0x00ff000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_0_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_0_SHIFT 48

/* switch :: PAGE_46_PN_QOS_WEIGHT_port0 :: PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_0 [47:40] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff0000000000,40,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff0000000000,40)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_0_MASK 0x0000ff0000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_0_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_0_SHIFT 40

/* switch :: PAGE_46_PN_QOS_WEIGHT_port0 :: PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_0 [39:32] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff00000000,32,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff00000000,32)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_0_MASK 0x000000ff00000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_0_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_0_SHIFT 32

/* switch :: PAGE_46_PN_QOS_WEIGHT_port0 :: PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_0 [31:24] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff000000,24,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff000000,24)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_0_MASK 0x00000000ff000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_0_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_0_SHIFT 24

/* switch :: PAGE_46_PN_QOS_WEIGHT_port0 :: PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_0 [23:16] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff0000,16,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff0000,16)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_0_MASK 0x0000000000ff0000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_0_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_0_SHIFT 16

/* switch :: PAGE_46_PN_QOS_WEIGHT_port0 :: PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_0 [15:08] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff00,8)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_0_MASK 0x000000000000ff00
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_0_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_0_SHIFT 8

/* switch :: PAGE_46_PN_QOS_WEIGHT_port0 :: PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_0 [07:00] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_0(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff,0,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port0_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_0(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0,0xff,0)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_0_MASK 0x00000000000000ff
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_0_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_0_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT0_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_WEIGHT_port1
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_WEIGHT_port1 :: PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_1 [63:56] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff00000000000000,56,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff00000000000000,56)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_1_MASK 0xff00000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_1_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_1_SHIFT 56

/* switch :: PAGE_46_PN_QOS_WEIGHT_port1 :: PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_1 [55:48] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff000000000000,48,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff000000000000,48)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_1_MASK 0x00ff000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_1_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_1_SHIFT 48

/* switch :: PAGE_46_PN_QOS_WEIGHT_port1 :: PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_1 [47:40] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff0000000000,40,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff0000000000,40)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_1_MASK 0x0000ff0000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_1_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_1_SHIFT 40

/* switch :: PAGE_46_PN_QOS_WEIGHT_port1 :: PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_1 [39:32] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff00000000,32,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff00000000,32)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_1_MASK 0x000000ff00000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_1_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_1_SHIFT 32

/* switch :: PAGE_46_PN_QOS_WEIGHT_port1 :: PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_1 [31:24] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff000000,24,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff000000,24)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_1_MASK 0x00000000ff000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_1_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_1_SHIFT 24

/* switch :: PAGE_46_PN_QOS_WEIGHT_port1 :: PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_1 [23:16] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff0000,16,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff0000,16)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_1_MASK 0x0000000000ff0000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_1_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_1_SHIFT 16

/* switch :: PAGE_46_PN_QOS_WEIGHT_port1 :: PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_1 [15:08] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff00,8)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_1_MASK 0x000000000000ff00
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_1_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_1_SHIFT 8

/* switch :: PAGE_46_PN_QOS_WEIGHT_port1 :: PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_1 [07:00] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_1(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff,0,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port1_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_1(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1,0xff,0)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_1_MASK 0x00000000000000ff
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_1_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_1_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT1_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_WEIGHT_port2
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_WEIGHT_port2 :: PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_2 [63:56] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff00000000000000,56,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff00000000000000,56)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_2_MASK 0xff00000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_2_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_2_SHIFT 56

/* switch :: PAGE_46_PN_QOS_WEIGHT_port2 :: PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_2 [55:48] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff000000000000,48,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff000000000000,48)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_2_MASK 0x00ff000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_2_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_2_SHIFT 48

/* switch :: PAGE_46_PN_QOS_WEIGHT_port2 :: PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_2 [47:40] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff0000000000,40,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff0000000000,40)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_2_MASK 0x0000ff0000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_2_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_2_SHIFT 40

/* switch :: PAGE_46_PN_QOS_WEIGHT_port2 :: PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_2 [39:32] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff00000000,32,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff00000000,32)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_2_MASK 0x000000ff00000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_2_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_2_SHIFT 32

/* switch :: PAGE_46_PN_QOS_WEIGHT_port2 :: PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_2 [31:24] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff000000,24,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff000000,24)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_2_MASK 0x00000000ff000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_2_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_2_SHIFT 24

/* switch :: PAGE_46_PN_QOS_WEIGHT_port2 :: PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_2 [23:16] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff0000,16,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff0000,16)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_2_MASK 0x0000000000ff0000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_2_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_2_SHIFT 16

/* switch :: PAGE_46_PN_QOS_WEIGHT_port2 :: PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_2 [15:08] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff00,8)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_2_MASK 0x000000000000ff00
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_2_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_2_SHIFT 8

/* switch :: PAGE_46_PN_QOS_WEIGHT_port2 :: PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_2 [07:00] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_2(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff,0,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port2_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_2(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2,0xff,0)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_2_MASK 0x00000000000000ff
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_2_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_2_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT2_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_WEIGHT_port3
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_WEIGHT_port3 :: PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_3 [63:56] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff00000000000000,56,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff00000000000000,56)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_3_MASK 0xff00000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_3_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_3_SHIFT 56

/* switch :: PAGE_46_PN_QOS_WEIGHT_port3 :: PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_3 [55:48] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff000000000000,48,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff000000000000,48)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_3_MASK 0x00ff000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_3_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_3_SHIFT 48

/* switch :: PAGE_46_PN_QOS_WEIGHT_port3 :: PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_3 [47:40] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff0000000000,40,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff0000000000,40)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_3_MASK 0x0000ff0000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_3_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_3_SHIFT 40

/* switch :: PAGE_46_PN_QOS_WEIGHT_port3 :: PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_3 [39:32] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff00000000,32,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff00000000,32)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_3_MASK 0x000000ff00000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_3_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_3_SHIFT 32

/* switch :: PAGE_46_PN_QOS_WEIGHT_port3 :: PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_3 [31:24] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff000000,24,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff000000,24)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_3_MASK 0x00000000ff000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_3_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_3_SHIFT 24

/* switch :: PAGE_46_PN_QOS_WEIGHT_port3 :: PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_3 [23:16] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff0000,16,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff0000,16)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_3_MASK 0x0000000000ff0000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_3_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_3_SHIFT 16

/* switch :: PAGE_46_PN_QOS_WEIGHT_port3 :: PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_3 [15:08] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff00,8)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_3_MASK 0x000000000000ff00
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_3_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_3_SHIFT 8

/* switch :: PAGE_46_PN_QOS_WEIGHT_port3 :: PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_3 [07:00] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_3(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff,0,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port3_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_3(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3,0xff,0)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_3_MASK 0x00000000000000ff
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_3_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_3_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT3_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_WEIGHT_port4
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_WEIGHT_port4 :: PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_4 [63:56] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff00000000000000,56,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff00000000000000,56)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_4_MASK 0xff00000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_4_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_4_SHIFT 56

/* switch :: PAGE_46_PN_QOS_WEIGHT_port4 :: PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_4 [55:48] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff000000000000,48,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff000000000000,48)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_4_MASK 0x00ff000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_4_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_4_SHIFT 48

/* switch :: PAGE_46_PN_QOS_WEIGHT_port4 :: PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_4 [47:40] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff0000000000,40,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff0000000000,40)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_4_MASK 0x0000ff0000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_4_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_4_SHIFT 40

/* switch :: PAGE_46_PN_QOS_WEIGHT_port4 :: PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_4 [39:32] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff00000000,32,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff00000000,32)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_4_MASK 0x000000ff00000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_4_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_4_SHIFT 32

/* switch :: PAGE_46_PN_QOS_WEIGHT_port4 :: PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_4 [31:24] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff000000,24,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff000000,24)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_4_MASK 0x00000000ff000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_4_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_4_SHIFT 24

/* switch :: PAGE_46_PN_QOS_WEIGHT_port4 :: PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_4 [23:16] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff0000,16,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff0000,16)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_4_MASK 0x0000000000ff0000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_4_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_4_SHIFT 16

/* switch :: PAGE_46_PN_QOS_WEIGHT_port4 :: PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_4 [15:08] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff00,8)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_4_MASK 0x000000000000ff00
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_4_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_4_SHIFT 8

/* switch :: PAGE_46_PN_QOS_WEIGHT_port4 :: PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_4 [07:00] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_4(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff,0,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port4_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_4(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4,0xff,0)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_4_MASK 0x00000000000000ff
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_4_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_4_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT4_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_WEIGHT_port5
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_WEIGHT_port5 :: PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_5 [63:56] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff00000000000000,56,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff00000000000000,56)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_5_MASK 0xff00000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_5_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_5_SHIFT 56

/* switch :: PAGE_46_PN_QOS_WEIGHT_port5 :: PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_5 [55:48] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff000000000000,48,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff000000000000,48)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_5_MASK 0x00ff000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_5_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_5_SHIFT 48

/* switch :: PAGE_46_PN_QOS_WEIGHT_port5 :: PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_5 [47:40] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff0000000000,40,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff0000000000,40)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_5_MASK 0x0000ff0000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_5_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_5_SHIFT 40

/* switch :: PAGE_46_PN_QOS_WEIGHT_port5 :: PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_5 [39:32] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff00000000,32,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff00000000,32)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_5_MASK 0x000000ff00000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_5_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_5_SHIFT 32

/* switch :: PAGE_46_PN_QOS_WEIGHT_port5 :: PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_5 [31:24] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff000000,24,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff000000,24)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_5_MASK 0x00000000ff000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_5_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_5_SHIFT 24

/* switch :: PAGE_46_PN_QOS_WEIGHT_port5 :: PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_5 [23:16] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff0000,16,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff0000,16)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_5_MASK 0x0000000000ff0000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_5_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_5_SHIFT 16

/* switch :: PAGE_46_PN_QOS_WEIGHT_port5 :: PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_5 [15:08] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff00,8)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_5_MASK 0x000000000000ff00
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_5_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_5_SHIFT 8

/* switch :: PAGE_46_PN_QOS_WEIGHT_port5 :: PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_5 [07:00] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_5(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff,0,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port5_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_5(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5,0xff,0)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_5_MASK 0x00000000000000ff
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_5_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_5_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT5_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_QOS_WEIGHT_port6
 ***************************************************************************/
/* switch :: PAGE_46_PN_QOS_WEIGHT_port6 :: PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_6 [63:56] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff00000000000000,56,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff00000000000000,56)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_6_MASK 0xff00000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_6_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q7_WEIGHT_6_SHIFT 56

/* switch :: PAGE_46_PN_QOS_WEIGHT_port6 :: PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_6 [55:48] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff000000000000,48,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff000000000000,48)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_6_MASK 0x00ff000000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_6_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q6_WEIGHT_6_SHIFT 48

/* switch :: PAGE_46_PN_QOS_WEIGHT_port6 :: PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_6 [47:40] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff0000000000,40,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff0000000000,40)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_6_MASK 0x0000ff0000000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_6_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q5_WEIGHT_6_SHIFT 40

/* switch :: PAGE_46_PN_QOS_WEIGHT_port6 :: PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_6 [39:32] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff00000000,32,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff00000000,32)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_6_MASK 0x000000ff00000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_6_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q4_WEIGHT_6_SHIFT 32

/* switch :: PAGE_46_PN_QOS_WEIGHT_port6 :: PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_6 [31:24] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff000000,24,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff000000,24)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_6_MASK 0x00000000ff000000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_6_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q3_WEIGHT_6_SHIFT 24

/* switch :: PAGE_46_PN_QOS_WEIGHT_port6 :: PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_6 [23:16] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff0000,16,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff0000,16)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_6_MASK 0x0000000000ff0000
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_6_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q2_WEIGHT_6_SHIFT 16

/* switch :: PAGE_46_PN_QOS_WEIGHT_port6 :: PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_6 [15:08] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff00,8)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_6_MASK 0x000000000000ff00
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_6_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q1_WEIGHT_6_SHIFT 8

/* switch :: PAGE_46_PN_QOS_WEIGHT_port6 :: PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_6 [07:00] */
#define Wr_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_6(x) WriteRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff,0,x)
#define Rd_switch_PAGE_46_PN_QOS_WEIGHT_port6_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_6(x) ReadRegBits(SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6,0xff,0)
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_6_MASK 0x00000000000000ff
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_6_ALIGN 0
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_6_BITS 8
#define SWITCH_PAGE_46_PN_QOS_WEIGHT_PORT6_PAGE_46_PN_QOS_WEIGHT_Q0_WEIGHT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_P7_QOS_WEIGHT
 ***************************************************************************/
/* switch :: PAGE_46_P7_QOS_WEIGHT :: PAGE_46_P7_QOS_WEIGHT_Q7_WEIGHT [63:56] */
#define Wr_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q7_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff00000000000000,56,x)
#define Rd_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q7_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff00000000000000,56)
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q7_WEIGHT_MASK 0xff00000000000000
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q7_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q7_WEIGHT_BITS 8
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q7_WEIGHT_SHIFT 56

/* switch :: PAGE_46_P7_QOS_WEIGHT :: PAGE_46_P7_QOS_WEIGHT_Q6_WEIGHT [55:48] */
#define Wr_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q6_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff000000000000,48,x)
#define Rd_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q6_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff000000000000,48)
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q6_WEIGHT_MASK 0x00ff000000000000
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q6_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q6_WEIGHT_BITS 8
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q6_WEIGHT_SHIFT 48

/* switch :: PAGE_46_P7_QOS_WEIGHT :: PAGE_46_P7_QOS_WEIGHT_Q5_WEIGHT [47:40] */
#define Wr_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q5_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff0000000000,40,x)
#define Rd_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q5_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff0000000000,40)
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q5_WEIGHT_MASK 0x0000ff0000000000
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q5_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q5_WEIGHT_BITS 8
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q5_WEIGHT_SHIFT 40

/* switch :: PAGE_46_P7_QOS_WEIGHT :: PAGE_46_P7_QOS_WEIGHT_Q4_WEIGHT [39:32] */
#define Wr_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q4_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff00000000,32,x)
#define Rd_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q4_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff00000000,32)
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q4_WEIGHT_MASK 0x000000ff00000000
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q4_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q4_WEIGHT_BITS 8
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q4_WEIGHT_SHIFT 32

/* switch :: PAGE_46_P7_QOS_WEIGHT :: PAGE_46_P7_QOS_WEIGHT_Q3_WEIGHT [31:24] */
#define Wr_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q3_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff000000,24,x)
#define Rd_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q3_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff000000,24)
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q3_WEIGHT_MASK 0x00000000ff000000
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q3_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q3_WEIGHT_BITS 8
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q3_WEIGHT_SHIFT 24

/* switch :: PAGE_46_P7_QOS_WEIGHT :: PAGE_46_P7_QOS_WEIGHT_Q2_WEIGHT [23:16] */
#define Wr_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q2_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff0000,16,x)
#define Rd_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q2_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff0000,16)
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q2_WEIGHT_MASK 0x0000000000ff0000
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q2_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q2_WEIGHT_BITS 8
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q2_WEIGHT_SHIFT 16

/* switch :: PAGE_46_P7_QOS_WEIGHT :: PAGE_46_P7_QOS_WEIGHT_Q1_WEIGHT [15:08] */
#define Wr_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q1_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff00,8,x)
#define Rd_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q1_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff00,8)
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q1_WEIGHT_MASK 0x000000000000ff00
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q1_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q1_WEIGHT_BITS 8
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q1_WEIGHT_SHIFT 8

/* switch :: PAGE_46_P7_QOS_WEIGHT :: PAGE_46_P7_QOS_WEIGHT_Q0_WEIGHT [07:00] */
#define Wr_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q0_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff,0,x)
#define Rd_switch_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q0_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_P7_QOS_WEIGHT,0xff,0)
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q0_WEIGHT_MASK 0x00000000000000ff
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q0_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q0_WEIGHT_BITS 8
#define SWITCH_PAGE_46_P7_QOS_WEIGHT_PAGE_46_P7_QOS_WEIGHT_Q0_WEIGHT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_IMP_QOS_WEIGHT
 ***************************************************************************/
/* switch :: PAGE_46_IMP_QOS_WEIGHT :: PAGE_46_IMP_QOS_WEIGHT_Q7_WEIGHT [63:56] */
#define Wr_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q7_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff00000000000000,56,x)
#define Rd_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q7_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff00000000000000,56)
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q7_WEIGHT_MASK 0xff00000000000000
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q7_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q7_WEIGHT_BITS 8
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q7_WEIGHT_SHIFT 56

/* switch :: PAGE_46_IMP_QOS_WEIGHT :: PAGE_46_IMP_QOS_WEIGHT_Q6_WEIGHT [55:48] */
#define Wr_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q6_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff000000000000,48,x)
#define Rd_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q6_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff000000000000,48)
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q6_WEIGHT_MASK 0x00ff000000000000
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q6_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q6_WEIGHT_BITS 8
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q6_WEIGHT_SHIFT 48

/* switch :: PAGE_46_IMP_QOS_WEIGHT :: PAGE_46_IMP_QOS_WEIGHT_Q5_WEIGHT [47:40] */
#define Wr_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q5_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff0000000000,40,x)
#define Rd_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q5_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff0000000000,40)
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q5_WEIGHT_MASK 0x0000ff0000000000
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q5_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q5_WEIGHT_BITS 8
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q5_WEIGHT_SHIFT 40

/* switch :: PAGE_46_IMP_QOS_WEIGHT :: PAGE_46_IMP_QOS_WEIGHT_Q4_WEIGHT [39:32] */
#define Wr_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q4_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff00000000,32,x)
#define Rd_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q4_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff00000000,32)
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q4_WEIGHT_MASK 0x000000ff00000000
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q4_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q4_WEIGHT_BITS 8
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q4_WEIGHT_SHIFT 32

/* switch :: PAGE_46_IMP_QOS_WEIGHT :: PAGE_46_IMP_QOS_WEIGHT_Q3_WEIGHT [31:24] */
#define Wr_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q3_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff000000,24,x)
#define Rd_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q3_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff000000,24)
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q3_WEIGHT_MASK 0x00000000ff000000
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q3_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q3_WEIGHT_BITS 8
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q3_WEIGHT_SHIFT 24

/* switch :: PAGE_46_IMP_QOS_WEIGHT :: PAGE_46_IMP_QOS_WEIGHT_Q2_WEIGHT [23:16] */
#define Wr_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q2_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff0000,16,x)
#define Rd_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q2_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff0000,16)
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q2_WEIGHT_MASK 0x0000000000ff0000
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q2_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q2_WEIGHT_BITS 8
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q2_WEIGHT_SHIFT 16

/* switch :: PAGE_46_IMP_QOS_WEIGHT :: PAGE_46_IMP_QOS_WEIGHT_Q1_WEIGHT [15:08] */
#define Wr_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q1_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff00,8,x)
#define Rd_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q1_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff00,8)
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q1_WEIGHT_MASK 0x000000000000ff00
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q1_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q1_WEIGHT_BITS 8
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q1_WEIGHT_SHIFT 8

/* switch :: PAGE_46_IMP_QOS_WEIGHT :: PAGE_46_IMP_QOS_WEIGHT_Q0_WEIGHT [07:00] */
#define Wr_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q0_WEIGHT(x) WriteRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff,0,x)
#define Rd_switch_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q0_WEIGHT(x) ReadRegBits(SWITCH_PAGE_46_IMP_QOS_WEIGHT,0xff,0)
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q0_WEIGHT_MASK 0x00000000000000ff
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q0_WEIGHT_ALIGN 0
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q0_WEIGHT_BITS 8
#define SWITCH_PAGE_46_IMP_QOS_WEIGHT_PAGE_46_IMP_QOS_WEIGHT_Q0_WEIGHT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_WDRR_PENALTY_port0
 ***************************************************************************/
/* switch :: PAGE_46_PN_WDRR_PENALTY_port0 :: PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_0 [15:08] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port0_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_0(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port0_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_0(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0,0xff00,8)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_0_MASK 0xff00
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_0_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_0_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_0_SHIFT 8

/* switch :: PAGE_46_PN_WDRR_PENALTY_port0 :: PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_0 [07:00] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port0_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_0(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0,0xff,0,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port0_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_0(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0,0xff,0)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_0_MASK 0x00ff
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_0_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_0_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT0_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_WDRR_PENALTY_port1
 ***************************************************************************/
/* switch :: PAGE_46_PN_WDRR_PENALTY_port1 :: PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_1 [15:08] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port1_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_1(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port1_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_1(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1,0xff00,8)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_1_MASK 0xff00
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_1_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_1_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_1_SHIFT 8

/* switch :: PAGE_46_PN_WDRR_PENALTY_port1 :: PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_1 [07:00] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port1_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_1(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1,0xff,0,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port1_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_1(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1,0xff,0)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_1_MASK 0x00ff
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_1_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_1_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT1_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_WDRR_PENALTY_port2
 ***************************************************************************/
/* switch :: PAGE_46_PN_WDRR_PENALTY_port2 :: PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_2 [15:08] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port2_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_2(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port2_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_2(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2,0xff00,8)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_2_MASK 0xff00
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_2_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_2_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_2_SHIFT 8

/* switch :: PAGE_46_PN_WDRR_PENALTY_port2 :: PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_2 [07:00] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port2_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_2(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2,0xff,0,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port2_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_2(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2,0xff,0)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_2_MASK 0x00ff
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_2_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_2_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT2_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_WDRR_PENALTY_port3
 ***************************************************************************/
/* switch :: PAGE_46_PN_WDRR_PENALTY_port3 :: PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_3 [15:08] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port3_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_3(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port3_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_3(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3,0xff00,8)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_3_MASK 0xff00
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_3_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_3_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_3_SHIFT 8

/* switch :: PAGE_46_PN_WDRR_PENALTY_port3 :: PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_3 [07:00] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port3_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_3(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3,0xff,0,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port3_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_3(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3,0xff,0)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_3_MASK 0x00ff
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_3_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_3_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT3_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_WDRR_PENALTY_port4
 ***************************************************************************/
/* switch :: PAGE_46_PN_WDRR_PENALTY_port4 :: PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_4 [15:08] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port4_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_4(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port4_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_4(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4,0xff00,8)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_4_MASK 0xff00
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_4_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_4_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_4_SHIFT 8

/* switch :: PAGE_46_PN_WDRR_PENALTY_port4 :: PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_4 [07:00] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port4_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_4(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4,0xff,0,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port4_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_4(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4,0xff,0)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_4_MASK 0x00ff
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_4_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_4_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT4_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_WDRR_PENALTY_port5
 ***************************************************************************/
/* switch :: PAGE_46_PN_WDRR_PENALTY_port5 :: PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_5 [15:08] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port5_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_5(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port5_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_5(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5,0xff00,8)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_5_MASK 0xff00
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_5_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_5_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_5_SHIFT 8

/* switch :: PAGE_46_PN_WDRR_PENALTY_port5 :: PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_5 [07:00] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port5_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_5(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5,0xff,0,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port5_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_5(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5,0xff,0)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_5_MASK 0x00ff
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_5_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_5_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT5_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_PN_WDRR_PENALTY_port6
 ***************************************************************************/
/* switch :: PAGE_46_PN_WDRR_PENALTY_port6 :: PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_6 [15:08] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port6_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_6(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6,0xff00,8,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port6_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_6(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6,0xff00,8)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_6_MASK 0xff00
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_6_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_6_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6_PAGE_46_PN_WDRR_PENALTY_PEAK_ITERATION_CYCLES_6_SHIFT 8

/* switch :: PAGE_46_PN_WDRR_PENALTY_port6 :: PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_6 [07:00] */
#define Wr_switch_PAGE_46_PN_WDRR_PENALTY_port6_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_6(x) WriteRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6,0xff,0,x)
#define Rd_switch_PAGE_46_PN_WDRR_PENALTY_port6_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_6(x) ReadRegBits16(SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6,0xff,0)
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_6_MASK 0x00ff
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_6_ALIGN 0
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_6_BITS 8
#define SWITCH_PAGE_46_PN_WDRR_PENALTY_PORT6_PAGE_46_PN_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_P7_WDRR_PENALTY
 ***************************************************************************/
/* switch :: PAGE_46_P7_WDRR_PENALTY :: PAGE_46_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES [15:08] */
#define Wr_switch_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES(x) WriteRegBits16(SWITCH_PAGE_46_P7_WDRR_PENALTY,0xff00,8,x)
#define Rd_switch_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES(x) ReadRegBits16(SWITCH_PAGE_46_P7_WDRR_PENALTY,0xff00,8)
#define SWITCH_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_MASK 0xff00
#define SWITCH_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_ALIGN 0
#define SWITCH_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_BITS 8
#define SWITCH_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_ITERATION_CYCLES_SHIFT 8

/* switch :: PAGE_46_P7_WDRR_PENALTY :: PAGE_46_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY [07:00] */
#define Wr_switch_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY(x) WriteRegBits16(SWITCH_PAGE_46_P7_WDRR_PENALTY,0xff,0,x)
#define Rd_switch_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY(x) ReadRegBits16(SWITCH_PAGE_46_P7_WDRR_PENALTY,0xff,0)
#define SWITCH_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_MASK 0x00ff
#define SWITCH_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_ALIGN 0
#define SWITCH_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_BITS 8
#define SWITCH_PAGE_46_P7_WDRR_PENALTY_PAGE_46_P7_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_P8_WDRR_PENALTY
 ***************************************************************************/
/* switch :: PAGE_46_P8_WDRR_PENALTY :: PAGE_46_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES [15:08] */
#define Wr_switch_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES(x) WriteRegBits16(SWITCH_PAGE_46_P8_WDRR_PENALTY,0xff00,8,x)
#define Rd_switch_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES(x) ReadRegBits16(SWITCH_PAGE_46_P8_WDRR_PENALTY,0xff00,8)
#define SWITCH_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_MASK 0xff00
#define SWITCH_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_ALIGN 0
#define SWITCH_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_BITS 8
#define SWITCH_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_ITERATION_CYCLES_SHIFT 8

/* switch :: PAGE_46_P8_WDRR_PENALTY :: PAGE_46_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY [07:00] */
#define Wr_switch_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY(x) WriteRegBits16(SWITCH_PAGE_46_P8_WDRR_PENALTY,0xff,0,x)
#define Rd_switch_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY(x) ReadRegBits16(SWITCH_PAGE_46_P8_WDRR_PENALTY,0xff,0)
#define SWITCH_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_MASK 0x00ff
#define SWITCH_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_ALIGN 0
#define SWITCH_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_BITS 8
#define SWITCH_PAGE_46_P8_WDRR_PENALTY_PAGE_46_P8_WDRR_PENALTY_PEAK_BACK2BACK_PENALTY_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_SCHEDULER_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_46_SCHEDULER_REG_SPARE0 :: PAGE_46_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_46_SCHEDULER_REG_SPARE0_PAGE_46_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0(x) WriteReg(SWITCH_PAGE_46_SCHEDULER_REG_SPARE0,x)
#define Rd_switch_PAGE_46_SCHEDULER_REG_SPARE0_PAGE_46_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0(x) ReadReg(SWITCH_PAGE_46_SCHEDULER_REG_SPARE0)
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE0_PAGE_46_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE0_PAGE_46_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE0_PAGE_46_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_BITS 32
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE0_PAGE_46_SCHEDULER_REG_SPARE0_SCHEDULER_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_46_SCHEDULER_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_46_SCHEDULER_REG_SPARE1 :: PAGE_46_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_46_SCHEDULER_REG_SPARE1_PAGE_46_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1(x) WriteReg(SWITCH_PAGE_46_SCHEDULER_REG_SPARE1,x)
#define Rd_switch_PAGE_46_SCHEDULER_REG_SPARE1_PAGE_46_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1(x) ReadReg(SWITCH_PAGE_46_SCHEDULER_REG_SPARE1)
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE1_PAGE_46_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE1_PAGE_46_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE1_PAGE_46_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_BITS 32
#define SWITCH_PAGE_46_SCHEDULER_REG_SPARE1_PAGE_46_SCHEDULER_REG_SPARE1_SCHEDULER_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port0 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port0 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port1 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port1 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port2 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port2 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port3 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port3 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port4 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port4 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port5 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port5 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port6 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port6 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_port6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port0 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port0 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port1 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port1 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port2 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port2 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port3 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port3 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port4 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port4 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port5 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port5 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port6 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port6 :: PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_port6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL :: PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_BYTE_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_STS_port0
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port0 :: PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_0 [31:31] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port0_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port0_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0,0x80000000,31)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_0_MASK 0x80000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_0_BITS 1
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_0_SHIFT 31

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port0 :: PAGE_47_PN_PORT_SHAPER_STS_RESERVED_0 [30:29] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port0_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0,0x60000000,29,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port0_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0,0x60000000,29)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_0_MASK 0x60000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_0_BITS 2
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_0_SHIFT 29

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port0 :: PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_0 [28:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port0_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0,0x1fffffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port0_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0,0x1fffffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_0_MASK 0x1fffffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_0_BITS 29
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT0_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_STS_port1
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port1 :: PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_1 [31:31] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port1_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port1_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1,0x80000000,31)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_1_MASK 0x80000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_1_BITS 1
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_1_SHIFT 31

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port1 :: PAGE_47_PN_PORT_SHAPER_STS_RESERVED_1 [30:29] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port1_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1,0x60000000,29,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port1_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1,0x60000000,29)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_1_MASK 0x60000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_1_BITS 2
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_1_SHIFT 29

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port1 :: PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_1 [28:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port1_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1,0x1fffffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port1_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1,0x1fffffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_1_MASK 0x1fffffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_1_BITS 29
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT1_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_STS_port2
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port2 :: PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_2 [31:31] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port2_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port2_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2,0x80000000,31)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_2_MASK 0x80000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_2_BITS 1
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_2_SHIFT 31

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port2 :: PAGE_47_PN_PORT_SHAPER_STS_RESERVED_2 [30:29] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port2_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2,0x60000000,29,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port2_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2,0x60000000,29)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_2_MASK 0x60000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_2_BITS 2
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_2_SHIFT 29

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port2 :: PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_2 [28:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port2_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2,0x1fffffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port2_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2,0x1fffffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_2_MASK 0x1fffffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_2_BITS 29
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT2_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_STS_port3
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port3 :: PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_3 [31:31] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port3_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port3_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3,0x80000000,31)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_3_MASK 0x80000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_3_BITS 1
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_3_SHIFT 31

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port3 :: PAGE_47_PN_PORT_SHAPER_STS_RESERVED_3 [30:29] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port3_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3,0x60000000,29,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port3_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3,0x60000000,29)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_3_MASK 0x60000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_3_BITS 2
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_3_SHIFT 29

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port3 :: PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_3 [28:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port3_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3,0x1fffffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port3_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3,0x1fffffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_3_MASK 0x1fffffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_3_BITS 29
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT3_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_STS_port4
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port4 :: PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_4 [31:31] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port4_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port4_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4,0x80000000,31)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_4_MASK 0x80000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_4_BITS 1
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_4_SHIFT 31

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port4 :: PAGE_47_PN_PORT_SHAPER_STS_RESERVED_4 [30:29] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port4_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4,0x60000000,29,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port4_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4,0x60000000,29)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_4_MASK 0x60000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_4_BITS 2
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_4_SHIFT 29

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port4 :: PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_4 [28:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port4_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4,0x1fffffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port4_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4,0x1fffffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_4_MASK 0x1fffffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_4_BITS 29
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT4_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_STS_port5
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port5 :: PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_5 [31:31] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port5_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port5_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5,0x80000000,31)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_5_MASK 0x80000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_5_BITS 1
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_5_SHIFT 31

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port5 :: PAGE_47_PN_PORT_SHAPER_STS_RESERVED_5 [30:29] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port5_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5,0x60000000,29,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port5_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5,0x60000000,29)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_5_MASK 0x60000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_5_BITS 2
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_5_SHIFT 29

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port5 :: PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_5 [28:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port5_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5,0x1fffffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port5_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5,0x1fffffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_5_MASK 0x1fffffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_5_BITS 29
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT5_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_STS_port6
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port6 :: PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_6 [31:31] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port6_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port6_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6,0x80000000,31)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_6_MASK 0x80000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_6_BITS 1
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_IN_PROFILE_FLAG_6_SHIFT 31

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port6 :: PAGE_47_PN_PORT_SHAPER_STS_RESERVED_6 [30:29] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port6_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6,0x60000000,29,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port6_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6,0x60000000,29)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_6_MASK 0x60000000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_6_BITS 2
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_RESERVED_6_SHIFT 29

/* switch :: PAGE_47_PN_PORT_SHAPER_STS_port6 :: PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_6 [28:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_STS_port6_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6,0x1fffffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_STS_port6_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6,0x1fffffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_6_MASK 0x1fffffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_6_BITS 29
#define SWITCH_PAGE_47_PN_PORT_SHAPER_STS_PORT6_PAGE_47_PN_PORT_SHAPER_STS_BUCKET_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_P7_PORT_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_47_P7_PORT_SHAPER_STS :: PAGE_47_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_47_P7_PORT_SHAPER_STS :: PAGE_47_P7_PORT_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_47_P7_PORT_SHAPER_STS :: PAGE_47_P7_PORT_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_47_P7_PORT_SHAPER_STS_PAGE_47_P7_PORT_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_IMP_PORT_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_47_IMP_PORT_SHAPER_STS :: PAGE_47_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_47_IMP_PORT_SHAPER_STS :: PAGE_47_IMP_PORT_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_47_IMP_PORT_SHAPER_STS :: PAGE_47_IMP_PORT_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_STS_PAGE_47_IMP_PORT_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port0 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port0 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port1 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port1 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port2 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port2 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port3 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port3 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port4 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port4 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port5 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port5 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port6 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port6 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_port6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0 :: PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0,x)
#define Rd_switch_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0)
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE0_EGRESS_SHAPER_CTLREG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1 :: PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1,x)
#define Rd_switch_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1)
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_PAGE_47_EGRESS_SHAPER_CTLREG_REG_SPARE1_EGRESS_SHAPER_CTLREG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port0 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port0 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT0_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port1 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port1 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT1_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port2 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port2 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT2_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port3 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port3 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT3_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port4 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port4 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT4_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port5 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port5 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT5_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port6 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port6 :: PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_port6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PORT6_PAGE_47_PN_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_P7_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL :: PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_PAGE_47_IMP_PORT_SHAPER_PACKET_BASED_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE
 ***************************************************************************/
/* switch :: PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE :: PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_RESERVED [15:09] */
#define Wr_switch_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE,0xfe00,9,x)
#define Rd_switch_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE,0xfe00,9)
#define SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_RESERVED_SHIFT 9

/* switch :: PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE :: PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE [08:00] */
#define Wr_switch_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE(x) WriteRegBits16(SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE,0x1ff,0,x)
#define Rd_switch_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE(x) ReadRegBits16(SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE,0x1ff,0)
#define SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_MASK 0x01ff
#define SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_ALIGN 0
#define SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_BITS 9
#define SWITCH_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PAGE_47_PORT_SHAPER_AVB_SHAPING_MODE_PORT_SHAPER_AVB_SHAPING_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PORT_SHAPER_ENABLE
 ***************************************************************************/
/* switch :: PAGE_47_PORT_SHAPER_ENABLE :: PAGE_47_PORT_SHAPER_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_47_PORT_SHAPER_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_47_PORT_SHAPER_ENABLE,0xfe00,9)
#define SWITCH_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_47_PORT_SHAPER_ENABLE :: PAGE_47_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE [08:00] */
#define Wr_switch_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE(x) WriteRegBits16(SWITCH_PAGE_47_PORT_SHAPER_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE(x) ReadRegBits16(SWITCH_PAGE_47_PORT_SHAPER_ENABLE,0x1ff,0)
#define SWITCH_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_MASK 0x01ff
#define SWITCH_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_ALIGN 0
#define SWITCH_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_BITS 9
#define SWITCH_PAGE_47_PORT_SHAPER_ENABLE_PAGE_47_PORT_SHAPER_ENABLE_PORT_SHAPER_ENABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT
 ***************************************************************************/
/* switch :: PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT :: PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_RESERVED [15:09] */
#define Wr_switch_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9,x)
#define Rd_switch_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9)
#define SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_RESERVED_BITS 7
#define SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_RESERVED_SHIFT 9

/* switch :: PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT :: PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT [08:00] */
#define Wr_switch_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT(x) WriteRegBits16(SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0,x)
#define Rd_switch_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT(x) ReadRegBits16(SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0)
#define SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_MASK 0x01ff
#define SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_ALIGN 0
#define SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_BITS 9
#define SWITCH_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PAGE_47_PORT_SHAPER_BUCKET_COUNT_SELECT_PORT_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_PORT_SHAPER_BLOCKING
 ***************************************************************************/
/* switch :: PAGE_47_PORT_SHAPER_BLOCKING :: PAGE_47_PORT_SHAPER_BLOCKING_RESERVED [15:09] */
#define Wr_switch_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_RESERVED(x) WriteRegBits16(SWITCH_PAGE_47_PORT_SHAPER_BLOCKING,0xfe00,9,x)
#define Rd_switch_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_RESERVED(x) ReadRegBits16(SWITCH_PAGE_47_PORT_SHAPER_BLOCKING,0xfe00,9)
#define SWITCH_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_RESERVED_ALIGN 0
#define SWITCH_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_RESERVED_BITS 7
#define SWITCH_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_RESERVED_SHIFT 9

/* switch :: PAGE_47_PORT_SHAPER_BLOCKING :: PAGE_47_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING [08:00] */
#define Wr_switch_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING(x) WriteRegBits16(SWITCH_PAGE_47_PORT_SHAPER_BLOCKING,0x1ff,0,x)
#define Rd_switch_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING(x) ReadRegBits16(SWITCH_PAGE_47_PORT_SHAPER_BLOCKING,0x1ff,0)
#define SWITCH_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_MASK 0x01ff
#define SWITCH_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_ALIGN 0
#define SWITCH_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_BITS 9
#define SWITCH_PAGE_47_PORT_SHAPER_BLOCKING_PAGE_47_PORT_SHAPER_BLOCKING_PORT_SHAPER_BLOCKING_SHIFT 0


/****************************************************************************
 * switch :: PAGE_47_IFG_BYTES
 ***************************************************************************/
/* switch :: PAGE_47_IFG_BYTES :: PAGE_47_IFG_BYTES_RESERVED [15:09] */
#define Wr_switch_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_RESERVED(x) WriteRegBits16(SWITCH_PAGE_47_IFG_BYTES,0xfe00,9,x)
#define Rd_switch_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_RESERVED(x) ReadRegBits16(SWITCH_PAGE_47_IFG_BYTES,0xfe00,9)
#define SWITCH_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_RESERVED_MASK   0xfe00
#define SWITCH_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_RESERVED_ALIGN  0
#define SWITCH_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_RESERVED_BITS   7
#define SWITCH_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_RESERVED_SHIFT  9

/* switch :: PAGE_47_IFG_BYTES :: PAGE_47_IFG_BYTES_IFG_BYTES [08:00] */
#define Wr_switch_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_IFG_BYTES(x) WriteRegBits16(SWITCH_PAGE_47_IFG_BYTES,0x1ff,0,x)
#define Rd_switch_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_IFG_BYTES(x) ReadRegBits16(SWITCH_PAGE_47_IFG_BYTES,0x1ff,0)
#define SWITCH_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_IFG_BYTES_MASK  0x01ff
#define SWITCH_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_IFG_BYTES_ALIGN 0
#define SWITCH_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_IFG_BYTES_BITS  9
#define SWITCH_PAGE_47_IFG_BYTES_PAGE_47_IFG_BYTES_IFG_BYTES_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port0 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port0_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port0_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port0 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port0_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port0_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port1 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port1_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port1_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port1 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port1_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port1_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port2 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port2_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port2_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port2 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port2_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port2_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port3 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port3_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port3_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port3 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port3_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port3_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port4 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port4_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port4_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port4 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port4_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port4_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port5 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port5_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port5_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port5 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port5_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port5_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port6 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port6_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port6_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_REFRESH_port6 :: PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port6_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_REFRESH_port6_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_P7_QUEUE0_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_48_P7_QUEUE0_MAX_REFRESH :: PAGE_48_P7_QUEUE0_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_48_P7_QUEUE0_MAX_REFRESH :: PAGE_48_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_REFRESH_PAGE_48_P7_QUEUE0_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_IMP_QUEUE0_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_48_IMP_QUEUE0_MAX_REFRESH :: PAGE_48_IMP_QUEUE0_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_48_IMP_QUEUE0_MAX_REFRESH :: PAGE_48_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_PAGE_48_IMP_QUEUE0_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port0 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port0 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port1 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port1 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port2 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port2 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port3 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port3 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port4 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port4 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port5 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port5 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port6 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_port6 :: PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_THD_SEL_port6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_P7_QUEUE0_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_48_P7_QUEUE0_MAX_THD_SEL :: PAGE_48_P7_QUEUE0_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_48_P7_QUEUE0_MAX_THD_SEL :: PAGE_48_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_THD_SEL_PAGE_48_P7_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_IMP_QUEUE0_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_48_IMP_QUEUE0_MAX_THD_SEL :: PAGE_48_IMP_QUEUE0_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_48_IMP_QUEUE0_MAX_THD_SEL :: PAGE_48_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port0
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port0 :: PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_0 [31:31] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port0_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port0_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0,0x80000000,31)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_0_MASK 0x80000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_0_BITS 1
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_0_SHIFT 31

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port0 :: PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_0 [30:29] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port0_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0,0x60000000,29,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port0_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0,0x60000000,29)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_0_MASK 0x60000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_0_BITS 2
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_0_SHIFT 29

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port0 :: PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_0 [28:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port0_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0,0x1fffffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port0_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0,0x1fffffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_0_MASK 0x1fffffff
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_0_BITS 29
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT0_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port1
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port1 :: PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_1 [31:31] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port1_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port1_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1,0x80000000,31)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_1_MASK 0x80000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_1_BITS 1
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_1_SHIFT 31

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port1 :: PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_1 [30:29] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port1_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1,0x60000000,29,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port1_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1,0x60000000,29)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_1_MASK 0x60000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_1_BITS 2
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_1_SHIFT 29

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port1 :: PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_1 [28:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port1_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1,0x1fffffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port1_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1,0x1fffffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_1_MASK 0x1fffffff
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_1_BITS 29
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT1_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port2
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port2 :: PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_2 [31:31] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port2_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port2_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2,0x80000000,31)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_2_MASK 0x80000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_2_BITS 1
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_2_SHIFT 31

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port2 :: PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_2 [30:29] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port2_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2,0x60000000,29,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port2_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2,0x60000000,29)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_2_MASK 0x60000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_2_BITS 2
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_2_SHIFT 29

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port2 :: PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_2 [28:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port2_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2,0x1fffffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port2_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2,0x1fffffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_2_MASK 0x1fffffff
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_2_BITS 29
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT2_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port3
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port3 :: PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_3 [31:31] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port3_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port3_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3,0x80000000,31)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_3_MASK 0x80000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_3_BITS 1
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_3_SHIFT 31

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port3 :: PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_3 [30:29] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port3_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3,0x60000000,29,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port3_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3,0x60000000,29)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_3_MASK 0x60000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_3_BITS 2
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_3_SHIFT 29

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port3 :: PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_3 [28:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port3_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3,0x1fffffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port3_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3,0x1fffffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_3_MASK 0x1fffffff
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_3_BITS 29
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT3_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port4
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port4 :: PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_4 [31:31] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port4_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port4_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4,0x80000000,31)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_4_MASK 0x80000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_4_BITS 1
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_4_SHIFT 31

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port4 :: PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_4 [30:29] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port4_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4,0x60000000,29,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port4_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4,0x60000000,29)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_4_MASK 0x60000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_4_BITS 2
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_4_SHIFT 29

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port4 :: PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_4 [28:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port4_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4,0x1fffffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port4_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4,0x1fffffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_4_MASK 0x1fffffff
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_4_BITS 29
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT4_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port5
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port5 :: PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_5 [31:31] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port5_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port5_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5,0x80000000,31)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_5_MASK 0x80000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_5_BITS 1
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_5_SHIFT 31

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port5 :: PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_5 [30:29] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port5_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5,0x60000000,29,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port5_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5,0x60000000,29)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_5_MASK 0x60000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_5_BITS 2
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_5_SHIFT 29

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port5 :: PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_5 [28:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port5_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5,0x1fffffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port5_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5,0x1fffffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_5_MASK 0x1fffffff
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_5_BITS 29
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT5_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port6
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port6 :: PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_6 [31:31] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port6_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port6_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6,0x80000000,31)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_6_MASK 0x80000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_6_BITS 1
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_6_SHIFT 31

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port6 :: PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_6 [30:29] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port6_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6,0x60000000,29,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port6_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6,0x60000000,29)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_6_MASK 0x60000000
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_6_BITS 2
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_RESERVED_6_SHIFT 29

/* switch :: PAGE_48_PN_QUEUE0_SHAPER_STS_port6 :: PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_6 [28:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port6_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6,0x1fffffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_SHAPER_STS_port6_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6,0x1fffffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_6_MASK 0x1fffffff
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_6_BITS 29
#define SWITCH_PAGE_48_PN_QUEUE0_SHAPER_STS_PORT6_PAGE_48_PN_QUEUE0_SHAPER_STS_BUCKET_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_P7_QUEUE0_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_48_P7_QUEUE0_SHAPER_STS :: PAGE_48_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_48_P7_QUEUE0_SHAPER_STS :: PAGE_48_P7_QUEUE0_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_48_P7_QUEUE0_SHAPER_STS :: PAGE_48_P7_QUEUE0_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_48_P7_QUEUE0_SHAPER_STS_PAGE_48_P7_QUEUE0_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_IMP_QUEUE0_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_48_IMP_QUEUE0_SHAPER_STS :: PAGE_48_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_48_IMP_QUEUE0_SHAPER_STS :: PAGE_48_IMP_QUEUE0_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_48_IMP_QUEUE0_SHAPER_STS :: PAGE_48_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_48_IMP_QUEUE0_SHAPER_STS_PAGE_48_IMP_QUEUE0_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port0 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port0 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port1 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port1 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port2 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port2 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port3 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port3 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port4 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port4 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port5 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port5 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port6 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port6 :: PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_port6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH :: PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH :: PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_P7_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH :: PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH :: PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_PAGE_48_IMP_QUEUE0_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 :: PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0,x)
#define Rd_switch_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0)
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 :: PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1,x)
#define Rd_switch_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1)
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_PAGE_48_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q0_CONFIG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port0 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port0 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT0_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port1 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port1 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT1_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port2 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port2 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT2_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port3 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port3 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT3_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port4 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port4 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT4_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port5 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port5 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT5_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port6 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port6 :: PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_port6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_PORT6_PAGE_48_PN_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL :: PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL :: PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_P7_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL :: PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL :: PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_PAGE_48_IMP_QUEUE0_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_QUEUE0_AVB_SHAPING_MODE
 ***************************************************************************/
/* switch :: PAGE_48_QUEUE0_AVB_SHAPING_MODE :: PAGE_48_QUEUE0_AVB_SHAPING_MODE_RESERVED [15:09] */
#define Wr_switch_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE,0xfe00,9,x)
#define Rd_switch_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE,0xfe00,9)
#define SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_RESERVED_SHIFT 9

/* switch :: PAGE_48_QUEUE0_AVB_SHAPING_MODE :: PAGE_48_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE [08:00] */
#define Wr_switch_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE(x) WriteRegBits16(SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE,0x1ff,0,x)
#define Rd_switch_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE(x) ReadRegBits16(SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE,0x1ff,0)
#define SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_MASK 0x01ff
#define SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_ALIGN 0
#define SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_BITS 9
#define SWITCH_PAGE_48_QUEUE0_AVB_SHAPING_MODE_PAGE_48_QUEUE0_AVB_SHAPING_MODE_QUEUE0_AVB_SHAPING_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_QUEUE0_SHAPER_ENABLE
 ***************************************************************************/
/* switch :: PAGE_48_QUEUE0_SHAPER_ENABLE :: PAGE_48_QUEUE0_SHAPER_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE,0xfe00,9)
#define SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_48_QUEUE0_SHAPER_ENABLE :: PAGE_48_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE [08:00] */
#define Wr_switch_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE(x) WriteRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE(x) ReadRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE,0x1ff,0)
#define SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_MASK 0x01ff
#define SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_ALIGN 0
#define SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_BITS 9
#define SWITCH_PAGE_48_QUEUE0_SHAPER_ENABLE_PAGE_48_QUEUE0_SHAPER_ENABLE_QUEUE0_SHAPER_ENABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT
 ***************************************************************************/
/* switch :: PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_RESERVED [15:09] */
#define Wr_switch_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9,x)
#define Rd_switch_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9)
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_RESERVED_BITS 7
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_RESERVED_SHIFT 9

/* switch :: PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT :: PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT [08:00] */
#define Wr_switch_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT(x) WriteRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0,x)
#define Rd_switch_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT(x) ReadRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0)
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_MASK 0x01ff
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_ALIGN 0
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_BITS 9
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_PAGE_48_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_QUEUE0_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_48_QUEUE0_SHAPER_BLOCKING
 ***************************************************************************/
/* switch :: PAGE_48_QUEUE0_SHAPER_BLOCKING :: PAGE_48_QUEUE0_SHAPER_BLOCKING_RESERVED [15:09] */
#define Wr_switch_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_RESERVED(x) WriteRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING,0xfe00,9,x)
#define Rd_switch_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_RESERVED(x) ReadRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING,0xfe00,9)
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_RESERVED_ALIGN 0
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_RESERVED_BITS 7
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_RESERVED_SHIFT 9

/* switch :: PAGE_48_QUEUE0_SHAPER_BLOCKING :: PAGE_48_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING [08:00] */
#define Wr_switch_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING(x) WriteRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING,0x1ff,0,x)
#define Rd_switch_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING(x) ReadRegBits16(SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING,0x1ff,0)
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_MASK 0x01ff
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_ALIGN 0
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_BITS 9
#define SWITCH_PAGE_48_QUEUE0_SHAPER_BLOCKING_PAGE_48_QUEUE0_SHAPER_BLOCKING_QUEUE0_SHAPER_BLOCKING_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port0 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port0_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port0_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port0 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port0_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port0_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port1 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port1_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port1_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port1 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port1_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port1_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port2 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port2_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port2_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port2 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port2_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port2_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port3 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port3_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port3_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port3 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port3_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port3_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port4 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port4_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port4_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port4 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port4_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port4_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port5 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port5_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port5_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port5 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port5_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port5_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port6 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port6_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port6_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_REFRESH_port6 :: PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port6_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_REFRESH_port6_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_P7_QUEUE1_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_49_P7_QUEUE1_MAX_REFRESH :: PAGE_49_P7_QUEUE1_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_49_P7_QUEUE1_MAX_REFRESH :: PAGE_49_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_REFRESH_PAGE_49_P7_QUEUE1_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_IMP_QUEUE1_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_49_IMP_QUEUE1_MAX_REFRESH :: PAGE_49_IMP_QUEUE1_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_49_IMP_QUEUE1_MAX_REFRESH :: PAGE_49_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_PAGE_49_IMP_QUEUE1_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port0 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port0 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port1 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port1 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port2 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port2 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port3 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port3 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port4 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port4 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port5 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port5 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port6 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_port6 :: PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_THD_SEL_port6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_P7_QUEUE1_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_49_P7_QUEUE1_MAX_THD_SEL :: PAGE_49_P7_QUEUE1_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_49_P7_QUEUE1_MAX_THD_SEL :: PAGE_49_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_THD_SEL_PAGE_49_P7_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_IMP_QUEUE1_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_49_IMP_QUEUE1_MAX_THD_SEL :: PAGE_49_IMP_QUEUE1_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_49_IMP_QUEUE1_MAX_THD_SEL :: PAGE_49_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port0
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port0 :: PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_0 [31:31] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port0_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port0_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0,0x80000000,31)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_0_MASK 0x80000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_0_BITS 1
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_0_SHIFT 31

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port0 :: PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_0 [30:29] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port0_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0,0x60000000,29,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port0_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0,0x60000000,29)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_0_MASK 0x60000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_0_BITS 2
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_0_SHIFT 29

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port0 :: PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_0 [28:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port0_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0,0x1fffffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port0_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0,0x1fffffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_0_MASK 0x1fffffff
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_0_BITS 29
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT0_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port1
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port1 :: PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_1 [31:31] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port1_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port1_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1,0x80000000,31)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_1_MASK 0x80000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_1_BITS 1
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_1_SHIFT 31

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port1 :: PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_1 [30:29] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port1_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1,0x60000000,29,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port1_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1,0x60000000,29)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_1_MASK 0x60000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_1_BITS 2
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_1_SHIFT 29

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port1 :: PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_1 [28:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port1_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1,0x1fffffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port1_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1,0x1fffffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_1_MASK 0x1fffffff
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_1_BITS 29
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT1_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port2
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port2 :: PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_2 [31:31] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port2_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port2_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2,0x80000000,31)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_2_MASK 0x80000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_2_BITS 1
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_2_SHIFT 31

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port2 :: PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_2 [30:29] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port2_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2,0x60000000,29,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port2_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2,0x60000000,29)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_2_MASK 0x60000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_2_BITS 2
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_2_SHIFT 29

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port2 :: PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_2 [28:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port2_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2,0x1fffffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port2_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2,0x1fffffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_2_MASK 0x1fffffff
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_2_BITS 29
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT2_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port3
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port3 :: PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_3 [31:31] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port3_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port3_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3,0x80000000,31)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_3_MASK 0x80000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_3_BITS 1
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_3_SHIFT 31

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port3 :: PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_3 [30:29] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port3_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3,0x60000000,29,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port3_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3,0x60000000,29)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_3_MASK 0x60000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_3_BITS 2
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_3_SHIFT 29

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port3 :: PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_3 [28:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port3_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3,0x1fffffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port3_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3,0x1fffffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_3_MASK 0x1fffffff
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_3_BITS 29
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT3_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port4
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port4 :: PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_4 [31:31] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port4_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port4_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4,0x80000000,31)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_4_MASK 0x80000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_4_BITS 1
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_4_SHIFT 31

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port4 :: PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_4 [30:29] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port4_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4,0x60000000,29,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port4_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4,0x60000000,29)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_4_MASK 0x60000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_4_BITS 2
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_4_SHIFT 29

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port4 :: PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_4 [28:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port4_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4,0x1fffffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port4_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4,0x1fffffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_4_MASK 0x1fffffff
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_4_BITS 29
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT4_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port5
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port5 :: PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_5 [31:31] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port5_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port5_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5,0x80000000,31)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_5_MASK 0x80000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_5_BITS 1
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_5_SHIFT 31

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port5 :: PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_5 [30:29] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port5_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5,0x60000000,29,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port5_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5,0x60000000,29)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_5_MASK 0x60000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_5_BITS 2
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_5_SHIFT 29

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port5 :: PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_5 [28:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port5_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5,0x1fffffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port5_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5,0x1fffffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_5_MASK 0x1fffffff
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_5_BITS 29
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT5_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port6
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port6 :: PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_6 [31:31] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port6_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port6_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6,0x80000000,31)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_6_MASK 0x80000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_6_BITS 1
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_6_SHIFT 31

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port6 :: PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_6 [30:29] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port6_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6,0x60000000,29,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port6_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6,0x60000000,29)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_6_MASK 0x60000000
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_6_BITS 2
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_RESERVED_6_SHIFT 29

/* switch :: PAGE_49_PN_QUEUE1_SHAPER_STS_port6 :: PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_6 [28:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port6_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6,0x1fffffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_SHAPER_STS_port6_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6,0x1fffffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_6_MASK 0x1fffffff
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_6_BITS 29
#define SWITCH_PAGE_49_PN_QUEUE1_SHAPER_STS_PORT6_PAGE_49_PN_QUEUE1_SHAPER_STS_BUCKET_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_P7_QUEUE1_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_49_P7_QUEUE1_SHAPER_STS :: PAGE_49_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_49_P7_QUEUE1_SHAPER_STS :: PAGE_49_P7_QUEUE1_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_49_P7_QUEUE1_SHAPER_STS :: PAGE_49_P7_QUEUE1_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_49_P7_QUEUE1_SHAPER_STS_PAGE_49_P7_QUEUE1_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_IMP_QUEUE1_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_49_IMP_QUEUE1_SHAPER_STS :: PAGE_49_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_49_IMP_QUEUE1_SHAPER_STS :: PAGE_49_IMP_QUEUE1_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_49_IMP_QUEUE1_SHAPER_STS :: PAGE_49_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_49_IMP_QUEUE1_SHAPER_STS_PAGE_49_IMP_QUEUE1_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port0 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port0 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port1 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port1 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port2 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port2 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port3 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port3 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port4 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port4 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port5 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port5 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port6 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port6 :: PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_port6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH :: PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH :: PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_P7_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH :: PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH :: PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_PAGE_49_IMP_QUEUE1_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 :: PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0,x)
#define Rd_switch_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0)
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 :: PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1,x)
#define Rd_switch_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1)
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_PAGE_49_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q1_CONFIG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port0 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port0 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT0_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port1 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port1 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT1_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port2 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port2 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT2_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port3 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port3 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT3_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port4 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port4 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT4_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port5 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port5 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT5_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port6 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port6 :: PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_port6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_PORT6_PAGE_49_PN_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL :: PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL :: PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_P7_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL :: PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL :: PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_PAGE_49_IMP_QUEUE1_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_QUEUE1_AVB_SHAPING_MODE
 ***************************************************************************/
/* switch :: PAGE_49_QUEUE1_AVB_SHAPING_MODE :: PAGE_49_QUEUE1_AVB_SHAPING_MODE_RESERVED [15:09] */
#define Wr_switch_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE,0xfe00,9,x)
#define Rd_switch_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE,0xfe00,9)
#define SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_RESERVED_SHIFT 9

/* switch :: PAGE_49_QUEUE1_AVB_SHAPING_MODE :: PAGE_49_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE [08:00] */
#define Wr_switch_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE(x) WriteRegBits16(SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE,0x1ff,0,x)
#define Rd_switch_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE(x) ReadRegBits16(SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE,0x1ff,0)
#define SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_MASK 0x01ff
#define SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_ALIGN 0
#define SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_BITS 9
#define SWITCH_PAGE_49_QUEUE1_AVB_SHAPING_MODE_PAGE_49_QUEUE1_AVB_SHAPING_MODE_QUEUE1_AVB_SHAPING_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_QUEUE1_SHAPER_ENABLE
 ***************************************************************************/
/* switch :: PAGE_49_QUEUE1_SHAPER_ENABLE :: PAGE_49_QUEUE1_SHAPER_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE,0xfe00,9)
#define SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_49_QUEUE1_SHAPER_ENABLE :: PAGE_49_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE [08:00] */
#define Wr_switch_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE(x) WriteRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE(x) ReadRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE,0x1ff,0)
#define SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_MASK 0x01ff
#define SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_ALIGN 0
#define SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_BITS 9
#define SWITCH_PAGE_49_QUEUE1_SHAPER_ENABLE_PAGE_49_QUEUE1_SHAPER_ENABLE_QUEUE1_SHAPER_ENABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT
 ***************************************************************************/
/* switch :: PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_RESERVED [15:09] */
#define Wr_switch_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9,x)
#define Rd_switch_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9)
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_RESERVED_BITS 7
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_RESERVED_SHIFT 9

/* switch :: PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT :: PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT [08:00] */
#define Wr_switch_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT(x) WriteRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0,x)
#define Rd_switch_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT(x) ReadRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0)
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_MASK 0x01ff
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_ALIGN 0
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_BITS 9
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_PAGE_49_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_QUEUE1_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_49_QUEUE1_SHAPER_BLOCKING
 ***************************************************************************/
/* switch :: PAGE_49_QUEUE1_SHAPER_BLOCKING :: PAGE_49_QUEUE1_SHAPER_BLOCKING_RESERVED [15:09] */
#define Wr_switch_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_RESERVED(x) WriteRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING,0xfe00,9,x)
#define Rd_switch_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_RESERVED(x) ReadRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING,0xfe00,9)
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_RESERVED_ALIGN 0
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_RESERVED_BITS 7
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_RESERVED_SHIFT 9

/* switch :: PAGE_49_QUEUE1_SHAPER_BLOCKING :: PAGE_49_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING [08:00] */
#define Wr_switch_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING(x) WriteRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING,0x1ff,0,x)
#define Rd_switch_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING(x) ReadRegBits16(SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING,0x1ff,0)
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_MASK 0x01ff
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_ALIGN 0
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_BITS 9
#define SWITCH_PAGE_49_QUEUE1_SHAPER_BLOCKING_PAGE_49_QUEUE1_SHAPER_BLOCKING_QUEUE1_SHAPER_BLOCKING_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port0 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port0 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port1 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port1 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port2 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port2 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port3 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port3 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port4 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port4 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port5 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port5 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port6 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_port6 :: PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_REFRESH_port6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_P7_QUEUE2_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4A_P7_QUEUE2_MAX_REFRESH :: PAGE_4A_P7_QUEUE2_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4A_P7_QUEUE2_MAX_REFRESH :: PAGE_4A_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_PAGE_4A_P7_QUEUE2_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_IMP_QUEUE2_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4A_IMP_QUEUE2_MAX_REFRESH :: PAGE_4A_IMP_QUEUE2_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4A_IMP_QUEUE2_MAX_REFRESH :: PAGE_4A_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port0 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port0 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port1 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port1 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port2 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port2 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port3 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port3 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port4 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port4 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port5 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port5 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port6 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port6 :: PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_port6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_P7_QUEUE2_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4A_P7_QUEUE2_MAX_THD_SEL :: PAGE_4A_P7_QUEUE2_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4A_P7_QUEUE2_MAX_THD_SEL :: PAGE_4A_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_IMP_QUEUE2_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4A_IMP_QUEUE2_MAX_THD_SEL :: PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4A_IMP_QUEUE2_MAX_THD_SEL :: PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port0
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port0 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_0 [31:31] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port0_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port0_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0,0x80000000,31)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_0_MASK 0x80000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_0_BITS 1
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_0_SHIFT 31

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port0 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_0 [30:29] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port0_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0,0x60000000,29,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port0_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0,0x60000000,29)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_0_MASK 0x60000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_0_BITS 2
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_0_SHIFT 29

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port0 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_0 [28:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port0_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0,0x1fffffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port0_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0,0x1fffffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_0_MASK 0x1fffffff
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_0_BITS 29
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT0_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port1
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port1 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_1 [31:31] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port1_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port1_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1,0x80000000,31)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_1_MASK 0x80000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_1_BITS 1
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_1_SHIFT 31

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port1 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_1 [30:29] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port1_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1,0x60000000,29,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port1_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1,0x60000000,29)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_1_MASK 0x60000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_1_BITS 2
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_1_SHIFT 29

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port1 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_1 [28:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port1_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1,0x1fffffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port1_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1,0x1fffffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_1_MASK 0x1fffffff
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_1_BITS 29
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT1_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port2
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port2 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_2 [31:31] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port2_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port2_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2,0x80000000,31)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_2_MASK 0x80000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_2_BITS 1
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_2_SHIFT 31

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port2 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_2 [30:29] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port2_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2,0x60000000,29,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port2_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2,0x60000000,29)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_2_MASK 0x60000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_2_BITS 2
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_2_SHIFT 29

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port2 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_2 [28:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port2_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2,0x1fffffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port2_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2,0x1fffffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_2_MASK 0x1fffffff
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_2_BITS 29
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT2_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port3
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port3 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_3 [31:31] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port3_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port3_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3,0x80000000,31)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_3_MASK 0x80000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_3_BITS 1
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_3_SHIFT 31

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port3 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_3 [30:29] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port3_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3,0x60000000,29,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port3_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3,0x60000000,29)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_3_MASK 0x60000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_3_BITS 2
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_3_SHIFT 29

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port3 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_3 [28:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port3_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3,0x1fffffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port3_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3,0x1fffffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_3_MASK 0x1fffffff
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_3_BITS 29
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT3_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port4
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port4 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_4 [31:31] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port4_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port4_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4,0x80000000,31)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_4_MASK 0x80000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_4_BITS 1
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_4_SHIFT 31

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port4 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_4 [30:29] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port4_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4,0x60000000,29,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port4_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4,0x60000000,29)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_4_MASK 0x60000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_4_BITS 2
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_4_SHIFT 29

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port4 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_4 [28:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port4_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4,0x1fffffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port4_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4,0x1fffffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_4_MASK 0x1fffffff
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_4_BITS 29
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT4_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port5
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port5 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_5 [31:31] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port5_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port5_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5,0x80000000,31)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_5_MASK 0x80000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_5_BITS 1
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_5_SHIFT 31

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port5 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_5 [30:29] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port5_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5,0x60000000,29,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port5_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5,0x60000000,29)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_5_MASK 0x60000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_5_BITS 2
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_5_SHIFT 29

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port5 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_5 [28:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port5_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5,0x1fffffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port5_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5,0x1fffffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_5_MASK 0x1fffffff
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_5_BITS 29
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT5_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port6
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port6 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_6 [31:31] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port6_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port6_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6,0x80000000,31)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_6_MASK 0x80000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_6_BITS 1
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_6_SHIFT 31

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port6 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_6 [30:29] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port6_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6,0x60000000,29,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port6_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6,0x60000000,29)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_6_MASK 0x60000000
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_6_BITS 2
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_RESERVED_6_SHIFT 29

/* switch :: PAGE_4A_PN_QUEUE2_SHAPER_STS_port6 :: PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_6 [28:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port6_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6,0x1fffffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_SHAPER_STS_port6_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6,0x1fffffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_6_MASK 0x1fffffff
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_6_BITS 29
#define SWITCH_PAGE_4A_PN_QUEUE2_SHAPER_STS_PORT6_PAGE_4A_PN_QUEUE2_SHAPER_STS_BUCKET_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_P7_QUEUE2_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4A_P7_QUEUE2_SHAPER_STS :: PAGE_4A_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4A_P7_QUEUE2_SHAPER_STS :: PAGE_4A_P7_QUEUE2_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4A_P7_QUEUE2_SHAPER_STS :: PAGE_4A_P7_QUEUE2_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4A_P7_QUEUE2_SHAPER_STS_PAGE_4A_P7_QUEUE2_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_IMP_QUEUE2_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4A_IMP_QUEUE2_SHAPER_STS :: PAGE_4A_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4A_IMP_QUEUE2_SHAPER_STS :: PAGE_4A_IMP_QUEUE2_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4A_IMP_QUEUE2_SHAPER_STS :: PAGE_4A_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4A_IMP_QUEUE2_SHAPER_STS_PAGE_4A_IMP_QUEUE2_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port0 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port0 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port1 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port1 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port2 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port2 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port3 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port3 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port4 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port4 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port5 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port5 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port6 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port6 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_port6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH :: PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH :: PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_P7_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 :: PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0,x)
#define Rd_switch_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0)
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 :: PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1,x)
#define Rd_switch_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1)
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_PAGE_4A_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q2_CONFIG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port0 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port0 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT0_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port1 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port1 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT1_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port2 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port2 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT2_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port3 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port3 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT3_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port4 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port4 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT4_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port5 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port5 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT5_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port6 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port6 :: PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_port6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_PORT6_PAGE_4A_PN_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL :: PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL :: PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_P7_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL :: PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_PAGE_4A_IMP_QUEUE2_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_QUEUE2_AVB_SHAPING_MODE
 ***************************************************************************/
/* switch :: PAGE_4A_QUEUE2_AVB_SHAPING_MODE :: PAGE_4A_QUEUE2_AVB_SHAPING_MODE_RESERVED [15:09] */
#define Wr_switch_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE,0xfe00,9,x)
#define Rd_switch_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE,0xfe00,9)
#define SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_RESERVED_SHIFT 9

/* switch :: PAGE_4A_QUEUE2_AVB_SHAPING_MODE :: PAGE_4A_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE [08:00] */
#define Wr_switch_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE(x) WriteRegBits16(SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE,0x1ff,0,x)
#define Rd_switch_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE(x) ReadRegBits16(SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE,0x1ff,0)
#define SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_MASK 0x01ff
#define SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_ALIGN 0
#define SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_BITS 9
#define SWITCH_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_PAGE_4A_QUEUE2_AVB_SHAPING_MODE_QUEUE2_AVB_SHAPING_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_QUEUE2_SHAPER_ENABLE
 ***************************************************************************/
/* switch :: PAGE_4A_QUEUE2_SHAPER_ENABLE :: PAGE_4A_QUEUE2_SHAPER_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE,0xfe00,9)
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_4A_QUEUE2_SHAPER_ENABLE :: PAGE_4A_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE [08:00] */
#define Wr_switch_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE(x) WriteRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE(x) ReadRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE,0x1ff,0)
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_MASK 0x01ff
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_ALIGN 0
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_BITS 9
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_ENABLE_PAGE_4A_QUEUE2_SHAPER_ENABLE_QUEUE2_SHAPER_ENABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT
 ***************************************************************************/
/* switch :: PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_RESERVED [15:09] */
#define Wr_switch_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9,x)
#define Rd_switch_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9)
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_RESERVED_BITS 7
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_RESERVED_SHIFT 9

/* switch :: PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT [08:00] */
#define Wr_switch_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT(x) WriteRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0,x)
#define Rd_switch_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT(x) ReadRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0)
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_MASK 0x01ff
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_ALIGN 0
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_BITS 9
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_PAGE_4A_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_QUEUE2_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4A_QUEUE2_SHAPER_BLOCKING
 ***************************************************************************/
/* switch :: PAGE_4A_QUEUE2_SHAPER_BLOCKING :: PAGE_4A_QUEUE2_SHAPER_BLOCKING_RESERVED [15:09] */
#define Wr_switch_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING,0xfe00,9,x)
#define Rd_switch_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING,0xfe00,9)
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_RESERVED_ALIGN 0
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_RESERVED_BITS 7
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_RESERVED_SHIFT 9

/* switch :: PAGE_4A_QUEUE2_SHAPER_BLOCKING :: PAGE_4A_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING [08:00] */
#define Wr_switch_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING(x) WriteRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING,0x1ff,0,x)
#define Rd_switch_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING(x) ReadRegBits16(SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING,0x1ff,0)
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_MASK 0x01ff
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_ALIGN 0
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_BITS 9
#define SWITCH_PAGE_4A_QUEUE2_SHAPER_BLOCKING_PAGE_4A_QUEUE2_SHAPER_BLOCKING_QUEUE2_SHAPER_BLOCKING_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port0 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port0 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port1 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port1 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port2 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port2 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port3 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port3 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port4 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port4 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port5 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port5 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port6 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_port6 :: PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_REFRESH_port6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_P7_QUEUE3_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4B_P7_QUEUE3_MAX_REFRESH :: PAGE_4B_P7_QUEUE3_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4B_P7_QUEUE3_MAX_REFRESH :: PAGE_4B_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_PAGE_4B_P7_QUEUE3_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_IMP_QUEUE3_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4B_IMP_QUEUE3_MAX_REFRESH :: PAGE_4B_IMP_QUEUE3_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4B_IMP_QUEUE3_MAX_REFRESH :: PAGE_4B_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port0 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port0 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port1 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port1 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port2 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port2 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port3 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port3 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port4 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port4 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port5 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port5 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port6 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port6 :: PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_port6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_P7_QUEUE3_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4B_P7_QUEUE3_MAX_THD_SEL :: PAGE_4B_P7_QUEUE3_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4B_P7_QUEUE3_MAX_THD_SEL :: PAGE_4B_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_IMP_QUEUE3_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4B_IMP_QUEUE3_MAX_THD_SEL :: PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4B_IMP_QUEUE3_MAX_THD_SEL :: PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port0
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port0 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_0 [31:31] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port0_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port0_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0,0x80000000,31)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_0_MASK 0x80000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_0_BITS 1
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_0_SHIFT 31

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port0 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_0 [30:29] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port0_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0,0x60000000,29,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port0_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0,0x60000000,29)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_0_MASK 0x60000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_0_BITS 2
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_0_SHIFT 29

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port0 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_0 [28:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port0_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0,0x1fffffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port0_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0,0x1fffffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_0_MASK 0x1fffffff
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_0_BITS 29
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT0_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port1
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port1 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_1 [31:31] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port1_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port1_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1,0x80000000,31)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_1_MASK 0x80000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_1_BITS 1
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_1_SHIFT 31

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port1 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_1 [30:29] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port1_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1,0x60000000,29,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port1_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1,0x60000000,29)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_1_MASK 0x60000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_1_BITS 2
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_1_SHIFT 29

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port1 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_1 [28:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port1_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1,0x1fffffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port1_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1,0x1fffffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_1_MASK 0x1fffffff
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_1_BITS 29
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT1_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port2
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port2 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_2 [31:31] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port2_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port2_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2,0x80000000,31)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_2_MASK 0x80000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_2_BITS 1
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_2_SHIFT 31

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port2 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_2 [30:29] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port2_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2,0x60000000,29,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port2_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2,0x60000000,29)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_2_MASK 0x60000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_2_BITS 2
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_2_SHIFT 29

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port2 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_2 [28:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port2_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2,0x1fffffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port2_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2,0x1fffffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_2_MASK 0x1fffffff
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_2_BITS 29
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT2_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port3
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port3 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_3 [31:31] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port3_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port3_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3,0x80000000,31)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_3_MASK 0x80000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_3_BITS 1
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_3_SHIFT 31

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port3 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_3 [30:29] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port3_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3,0x60000000,29,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port3_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3,0x60000000,29)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_3_MASK 0x60000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_3_BITS 2
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_3_SHIFT 29

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port3 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_3 [28:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port3_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3,0x1fffffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port3_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3,0x1fffffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_3_MASK 0x1fffffff
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_3_BITS 29
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT3_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port4
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port4 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_4 [31:31] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port4_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port4_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4,0x80000000,31)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_4_MASK 0x80000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_4_BITS 1
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_4_SHIFT 31

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port4 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_4 [30:29] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port4_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4,0x60000000,29,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port4_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4,0x60000000,29)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_4_MASK 0x60000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_4_BITS 2
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_4_SHIFT 29

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port4 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_4 [28:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port4_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4,0x1fffffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port4_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4,0x1fffffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_4_MASK 0x1fffffff
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_4_BITS 29
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT4_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port5
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port5 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_5 [31:31] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port5_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port5_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5,0x80000000,31)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_5_MASK 0x80000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_5_BITS 1
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_5_SHIFT 31

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port5 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_5 [30:29] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port5_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5,0x60000000,29,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port5_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5,0x60000000,29)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_5_MASK 0x60000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_5_BITS 2
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_5_SHIFT 29

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port5 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_5 [28:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port5_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5,0x1fffffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port5_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5,0x1fffffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_5_MASK 0x1fffffff
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_5_BITS 29
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT5_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port6
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port6 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_6 [31:31] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port6_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port6_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6,0x80000000,31)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_6_MASK 0x80000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_6_BITS 1
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_6_SHIFT 31

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port6 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_6 [30:29] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port6_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6,0x60000000,29,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port6_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6,0x60000000,29)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_6_MASK 0x60000000
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_6_BITS 2
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_RESERVED_6_SHIFT 29

/* switch :: PAGE_4B_PN_QUEUE3_SHAPER_STS_port6 :: PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_6 [28:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port6_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6,0x1fffffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_SHAPER_STS_port6_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6,0x1fffffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_6_MASK 0x1fffffff
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_6_BITS 29
#define SWITCH_PAGE_4B_PN_QUEUE3_SHAPER_STS_PORT6_PAGE_4B_PN_QUEUE3_SHAPER_STS_BUCKET_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_P7_QUEUE3_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4B_P7_QUEUE3_SHAPER_STS :: PAGE_4B_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4B_P7_QUEUE3_SHAPER_STS :: PAGE_4B_P7_QUEUE3_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4B_P7_QUEUE3_SHAPER_STS :: PAGE_4B_P7_QUEUE3_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4B_P7_QUEUE3_SHAPER_STS_PAGE_4B_P7_QUEUE3_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_IMP_QUEUE3_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4B_IMP_QUEUE3_SHAPER_STS :: PAGE_4B_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4B_IMP_QUEUE3_SHAPER_STS :: PAGE_4B_IMP_QUEUE3_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4B_IMP_QUEUE3_SHAPER_STS :: PAGE_4B_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4B_IMP_QUEUE3_SHAPER_STS_PAGE_4B_IMP_QUEUE3_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port0 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port0 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port1 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port1 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port2 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port2 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port3 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port3 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port4 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port4 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port5 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port5 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port6 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port6 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_port6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH :: PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH :: PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_P7_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 :: PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0,x)
#define Rd_switch_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0)
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 :: PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1,x)
#define Rd_switch_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1)
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_PAGE_4B_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q3_CONFIG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port0 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port0 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT0_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port1 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port1 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT1_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port2 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port2 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT2_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port3 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port3 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT3_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port4 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port4 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT4_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port5 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port5 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT5_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port6 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port6 :: PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_port6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_PORT6_PAGE_4B_PN_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL :: PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL :: PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_P7_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL :: PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_PAGE_4B_IMP_QUEUE3_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_QUEUE3_AVB_SHAPING_MODE
 ***************************************************************************/
/* switch :: PAGE_4B_QUEUE3_AVB_SHAPING_MODE :: PAGE_4B_QUEUE3_AVB_SHAPING_MODE_RESERVED [15:09] */
#define Wr_switch_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE,0xfe00,9,x)
#define Rd_switch_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE,0xfe00,9)
#define SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_RESERVED_SHIFT 9

/* switch :: PAGE_4B_QUEUE3_AVB_SHAPING_MODE :: PAGE_4B_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE [08:00] */
#define Wr_switch_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE(x) WriteRegBits16(SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE,0x1ff,0,x)
#define Rd_switch_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE(x) ReadRegBits16(SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE,0x1ff,0)
#define SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_MASK 0x01ff
#define SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_ALIGN 0
#define SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_BITS 9
#define SWITCH_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_PAGE_4B_QUEUE3_AVB_SHAPING_MODE_QUEUE3_AVB_SHAPING_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_QUEUE3_SHAPER_ENABLE
 ***************************************************************************/
/* switch :: PAGE_4B_QUEUE3_SHAPER_ENABLE :: PAGE_4B_QUEUE3_SHAPER_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE,0xfe00,9)
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_4B_QUEUE3_SHAPER_ENABLE :: PAGE_4B_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE [08:00] */
#define Wr_switch_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE(x) WriteRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE(x) ReadRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE,0x1ff,0)
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_MASK 0x01ff
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_ALIGN 0
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_BITS 9
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_ENABLE_PAGE_4B_QUEUE3_SHAPER_ENABLE_QUEUE3_SHAPER_ENABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT
 ***************************************************************************/
/* switch :: PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_RESERVED [15:09] */
#define Wr_switch_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9,x)
#define Rd_switch_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9)
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_RESERVED_BITS 7
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_RESERVED_SHIFT 9

/* switch :: PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT [08:00] */
#define Wr_switch_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT(x) WriteRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0,x)
#define Rd_switch_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT(x) ReadRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0)
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_MASK 0x01ff
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_ALIGN 0
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_BITS 9
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_PAGE_4B_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_QUEUE3_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4B_QUEUE3_SHAPER_BLOCKING
 ***************************************************************************/
/* switch :: PAGE_4B_QUEUE3_SHAPER_BLOCKING :: PAGE_4B_QUEUE3_SHAPER_BLOCKING_RESERVED [15:09] */
#define Wr_switch_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING,0xfe00,9,x)
#define Rd_switch_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING,0xfe00,9)
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_RESERVED_ALIGN 0
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_RESERVED_BITS 7
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_RESERVED_SHIFT 9

/* switch :: PAGE_4B_QUEUE3_SHAPER_BLOCKING :: PAGE_4B_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING [08:00] */
#define Wr_switch_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING(x) WriteRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING,0x1ff,0,x)
#define Rd_switch_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING(x) ReadRegBits16(SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING,0x1ff,0)
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_MASK 0x01ff
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_ALIGN 0
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_BITS 9
#define SWITCH_PAGE_4B_QUEUE3_SHAPER_BLOCKING_PAGE_4B_QUEUE3_SHAPER_BLOCKING_QUEUE3_SHAPER_BLOCKING_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port0 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port0 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port1 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port1 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port2 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port2 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port3 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port3 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port4 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port4 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port5 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port5 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port6 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_port6 :: PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_REFRESH_port6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_P7_QUEUE4_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4C_P7_QUEUE4_MAX_REFRESH :: PAGE_4C_P7_QUEUE4_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4C_P7_QUEUE4_MAX_REFRESH :: PAGE_4C_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_PAGE_4C_P7_QUEUE4_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_IMP_QUEUE4_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4C_IMP_QUEUE4_MAX_REFRESH :: PAGE_4C_IMP_QUEUE4_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4C_IMP_QUEUE4_MAX_REFRESH :: PAGE_4C_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port0 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port0 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port1 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port1 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port2 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port2 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port3 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port3 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port4 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port4 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port5 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port5 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port6 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port6 :: PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_port6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_P7_QUEUE4_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4C_P7_QUEUE4_MAX_THD_SEL :: PAGE_4C_P7_QUEUE4_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4C_P7_QUEUE4_MAX_THD_SEL :: PAGE_4C_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_IMP_QUEUE4_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4C_IMP_QUEUE4_MAX_THD_SEL :: PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4C_IMP_QUEUE4_MAX_THD_SEL :: PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port0
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port0 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_0 [31:31] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port0_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port0_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0,0x80000000,31)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_0_MASK 0x80000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_0_BITS 1
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_0_SHIFT 31

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port0 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_0 [30:29] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port0_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0,0x60000000,29,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port0_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0,0x60000000,29)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_0_MASK 0x60000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_0_BITS 2
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_0_SHIFT 29

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port0 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_0 [28:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port0_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0,0x1fffffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port0_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0,0x1fffffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_0_MASK 0x1fffffff
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_0_BITS 29
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT0_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port1
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port1 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_1 [31:31] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port1_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port1_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1,0x80000000,31)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_1_MASK 0x80000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_1_BITS 1
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_1_SHIFT 31

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port1 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_1 [30:29] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port1_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1,0x60000000,29,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port1_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1,0x60000000,29)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_1_MASK 0x60000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_1_BITS 2
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_1_SHIFT 29

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port1 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_1 [28:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port1_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1,0x1fffffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port1_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1,0x1fffffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_1_MASK 0x1fffffff
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_1_BITS 29
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT1_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port2
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port2 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_2 [31:31] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port2_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port2_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2,0x80000000,31)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_2_MASK 0x80000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_2_BITS 1
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_2_SHIFT 31

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port2 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_2 [30:29] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port2_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2,0x60000000,29,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port2_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2,0x60000000,29)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_2_MASK 0x60000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_2_BITS 2
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_2_SHIFT 29

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port2 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_2 [28:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port2_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2,0x1fffffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port2_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2,0x1fffffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_2_MASK 0x1fffffff
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_2_BITS 29
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT2_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port3
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port3 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_3 [31:31] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port3_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port3_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3,0x80000000,31)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_3_MASK 0x80000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_3_BITS 1
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_3_SHIFT 31

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port3 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_3 [30:29] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port3_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3,0x60000000,29,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port3_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3,0x60000000,29)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_3_MASK 0x60000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_3_BITS 2
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_3_SHIFT 29

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port3 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_3 [28:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port3_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3,0x1fffffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port3_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3,0x1fffffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_3_MASK 0x1fffffff
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_3_BITS 29
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT3_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port4
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port4 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_4 [31:31] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port4_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port4_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4,0x80000000,31)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_4_MASK 0x80000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_4_BITS 1
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_4_SHIFT 31

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port4 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_4 [30:29] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port4_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4,0x60000000,29,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port4_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4,0x60000000,29)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_4_MASK 0x60000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_4_BITS 2
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_4_SHIFT 29

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port4 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_4 [28:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port4_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4,0x1fffffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port4_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4,0x1fffffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_4_MASK 0x1fffffff
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_4_BITS 29
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT4_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port5
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port5 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_5 [31:31] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port5_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port5_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5,0x80000000,31)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_5_MASK 0x80000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_5_BITS 1
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_5_SHIFT 31

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port5 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_5 [30:29] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port5_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5,0x60000000,29,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port5_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5,0x60000000,29)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_5_MASK 0x60000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_5_BITS 2
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_5_SHIFT 29

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port5 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_5 [28:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port5_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5,0x1fffffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port5_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5,0x1fffffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_5_MASK 0x1fffffff
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_5_BITS 29
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT5_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port6
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port6 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_6 [31:31] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port6_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port6_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6,0x80000000,31)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_6_MASK 0x80000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_6_BITS 1
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_6_SHIFT 31

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port6 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_6 [30:29] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port6_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6,0x60000000,29,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port6_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6,0x60000000,29)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_6_MASK 0x60000000
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_6_BITS 2
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_RESERVED_6_SHIFT 29

/* switch :: PAGE_4C_PN_QUEUE4_SHAPER_STS_port6 :: PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_6 [28:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port6_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6,0x1fffffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_SHAPER_STS_port6_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6,0x1fffffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_6_MASK 0x1fffffff
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_6_BITS 29
#define SWITCH_PAGE_4C_PN_QUEUE4_SHAPER_STS_PORT6_PAGE_4C_PN_QUEUE4_SHAPER_STS_BUCKET_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_P7_QUEUE4_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4C_P7_QUEUE4_SHAPER_STS :: PAGE_4C_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4C_P7_QUEUE4_SHAPER_STS :: PAGE_4C_P7_QUEUE4_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4C_P7_QUEUE4_SHAPER_STS :: PAGE_4C_P7_QUEUE4_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4C_P7_QUEUE4_SHAPER_STS_PAGE_4C_P7_QUEUE4_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_IMP_QUEUE4_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4C_IMP_QUEUE4_SHAPER_STS :: PAGE_4C_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4C_IMP_QUEUE4_SHAPER_STS :: PAGE_4C_IMP_QUEUE4_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4C_IMP_QUEUE4_SHAPER_STS :: PAGE_4C_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4C_IMP_QUEUE4_SHAPER_STS_PAGE_4C_IMP_QUEUE4_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port0 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port0 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port1 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port1 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port2 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port2 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port3 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port3 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port4 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port4 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port5 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port5 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port6 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port6 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_port6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH :: PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH :: PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_P7_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 :: PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0,x)
#define Rd_switch_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0)
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 :: PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1,x)
#define Rd_switch_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1)
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_PAGE_4C_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q4_CONFIG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port0 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port0 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT0_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port1 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port1 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT1_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port2 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port2 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT2_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port3 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port3 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT3_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port4 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port4 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT4_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port5 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port5 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT5_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port6 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port6 :: PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_port6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_PORT6_PAGE_4C_PN_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL :: PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL :: PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_P7_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL :: PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_PAGE_4C_IMP_QUEUE4_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_QUEUE4_AVB_SHAPING_MODE
 ***************************************************************************/
/* switch :: PAGE_4C_QUEUE4_AVB_SHAPING_MODE :: PAGE_4C_QUEUE4_AVB_SHAPING_MODE_RESERVED [15:09] */
#define Wr_switch_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE,0xfe00,9,x)
#define Rd_switch_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE,0xfe00,9)
#define SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_RESERVED_SHIFT 9

/* switch :: PAGE_4C_QUEUE4_AVB_SHAPING_MODE :: PAGE_4C_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE [08:00] */
#define Wr_switch_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE(x) WriteRegBits16(SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE,0x1ff,0,x)
#define Rd_switch_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE(x) ReadRegBits16(SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE,0x1ff,0)
#define SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_MASK 0x01ff
#define SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_ALIGN 0
#define SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_BITS 9
#define SWITCH_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_PAGE_4C_QUEUE4_AVB_SHAPING_MODE_QUEUE4_AVB_SHAPING_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_QUEUE4_SHAPER_ENABLE
 ***************************************************************************/
/* switch :: PAGE_4C_QUEUE4_SHAPER_ENABLE :: PAGE_4C_QUEUE4_SHAPER_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE,0xfe00,9)
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_4C_QUEUE4_SHAPER_ENABLE :: PAGE_4C_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE [08:00] */
#define Wr_switch_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE(x) WriteRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE(x) ReadRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE,0x1ff,0)
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_MASK 0x01ff
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_ALIGN 0
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_BITS 9
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_ENABLE_PAGE_4C_QUEUE4_SHAPER_ENABLE_QUEUE4_SHAPER_ENABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT
 ***************************************************************************/
/* switch :: PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_RESERVED [15:09] */
#define Wr_switch_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9,x)
#define Rd_switch_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9)
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_RESERVED_BITS 7
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_RESERVED_SHIFT 9

/* switch :: PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT [08:00] */
#define Wr_switch_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT(x) WriteRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0,x)
#define Rd_switch_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT(x) ReadRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0)
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_MASK 0x01ff
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_ALIGN 0
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_BITS 9
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_PAGE_4C_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_QUEUE4_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4C_QUEUE4_SHAPER_BLOCKING
 ***************************************************************************/
/* switch :: PAGE_4C_QUEUE4_SHAPER_BLOCKING :: PAGE_4C_QUEUE4_SHAPER_BLOCKING_RESERVED [15:09] */
#define Wr_switch_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING,0xfe00,9,x)
#define Rd_switch_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING,0xfe00,9)
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_RESERVED_ALIGN 0
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_RESERVED_BITS 7
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_RESERVED_SHIFT 9

/* switch :: PAGE_4C_QUEUE4_SHAPER_BLOCKING :: PAGE_4C_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING [08:00] */
#define Wr_switch_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING(x) WriteRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING,0x1ff,0,x)
#define Rd_switch_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING(x) ReadRegBits16(SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING,0x1ff,0)
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_MASK 0x01ff
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_ALIGN 0
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_BITS 9
#define SWITCH_PAGE_4C_QUEUE4_SHAPER_BLOCKING_PAGE_4C_QUEUE4_SHAPER_BLOCKING_QUEUE4_SHAPER_BLOCKING_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port0 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port0 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port1 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port1 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port2 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port2 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port3 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port3 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port4 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port4 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port5 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port5 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port6 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_port6 :: PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_REFRESH_port6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_P7_QUEUE5_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4D_P7_QUEUE5_MAX_REFRESH :: PAGE_4D_P7_QUEUE5_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4D_P7_QUEUE5_MAX_REFRESH :: PAGE_4D_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_PAGE_4D_P7_QUEUE5_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_IMP_QUEUE5_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4D_IMP_QUEUE5_MAX_REFRESH :: PAGE_4D_IMP_QUEUE5_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4D_IMP_QUEUE5_MAX_REFRESH :: PAGE_4D_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port0 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port0 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port1 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port1 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port2 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port2 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port3 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port3 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port4 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port4 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port5 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port5 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port6 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port6 :: PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_port6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_P7_QUEUE5_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4D_P7_QUEUE5_MAX_THD_SEL :: PAGE_4D_P7_QUEUE5_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4D_P7_QUEUE5_MAX_THD_SEL :: PAGE_4D_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_IMP_QUEUE5_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4D_IMP_QUEUE5_MAX_THD_SEL :: PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4D_IMP_QUEUE5_MAX_THD_SEL :: PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port0
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port0 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_0 [31:31] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port0_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port0_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0,0x80000000,31)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_0_MASK 0x80000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_0_BITS 1
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_0_SHIFT 31

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port0 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_0 [30:29] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port0_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0,0x60000000,29,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port0_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0,0x60000000,29)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_0_MASK 0x60000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_0_BITS 2
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_0_SHIFT 29

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port0 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_0 [28:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port0_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0,0x1fffffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port0_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0,0x1fffffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_0_MASK 0x1fffffff
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_0_BITS 29
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT0_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port1
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port1 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_1 [31:31] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port1_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port1_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1,0x80000000,31)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_1_MASK 0x80000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_1_BITS 1
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_1_SHIFT 31

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port1 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_1 [30:29] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port1_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1,0x60000000,29,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port1_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1,0x60000000,29)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_1_MASK 0x60000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_1_BITS 2
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_1_SHIFT 29

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port1 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_1 [28:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port1_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1,0x1fffffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port1_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1,0x1fffffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_1_MASK 0x1fffffff
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_1_BITS 29
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT1_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port2
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port2 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_2 [31:31] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port2_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port2_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2,0x80000000,31)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_2_MASK 0x80000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_2_BITS 1
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_2_SHIFT 31

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port2 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_2 [30:29] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port2_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2,0x60000000,29,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port2_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2,0x60000000,29)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_2_MASK 0x60000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_2_BITS 2
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_2_SHIFT 29

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port2 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_2 [28:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port2_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2,0x1fffffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port2_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2,0x1fffffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_2_MASK 0x1fffffff
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_2_BITS 29
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT2_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port3
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port3 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_3 [31:31] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port3_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port3_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3,0x80000000,31)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_3_MASK 0x80000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_3_BITS 1
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_3_SHIFT 31

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port3 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_3 [30:29] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port3_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3,0x60000000,29,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port3_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3,0x60000000,29)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_3_MASK 0x60000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_3_BITS 2
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_3_SHIFT 29

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port3 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_3 [28:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port3_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3,0x1fffffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port3_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3,0x1fffffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_3_MASK 0x1fffffff
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_3_BITS 29
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT3_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port4
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port4 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_4 [31:31] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port4_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port4_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4,0x80000000,31)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_4_MASK 0x80000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_4_BITS 1
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_4_SHIFT 31

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port4 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_4 [30:29] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port4_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4,0x60000000,29,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port4_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4,0x60000000,29)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_4_MASK 0x60000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_4_BITS 2
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_4_SHIFT 29

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port4 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_4 [28:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port4_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4,0x1fffffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port4_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4,0x1fffffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_4_MASK 0x1fffffff
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_4_BITS 29
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT4_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port5
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port5 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_5 [31:31] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port5_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port5_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5,0x80000000,31)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_5_MASK 0x80000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_5_BITS 1
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_5_SHIFT 31

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port5 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_5 [30:29] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port5_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5,0x60000000,29,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port5_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5,0x60000000,29)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_5_MASK 0x60000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_5_BITS 2
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_5_SHIFT 29

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port5 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_5 [28:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port5_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5,0x1fffffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port5_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5,0x1fffffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_5_MASK 0x1fffffff
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_5_BITS 29
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT5_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port6
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port6 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_6 [31:31] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port6_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port6_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6,0x80000000,31)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_6_MASK 0x80000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_6_BITS 1
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_6_SHIFT 31

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port6 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_6 [30:29] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port6_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6,0x60000000,29,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port6_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6,0x60000000,29)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_6_MASK 0x60000000
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_6_BITS 2
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_RESERVED_6_SHIFT 29

/* switch :: PAGE_4D_PN_QUEUE5_SHAPER_STS_port6 :: PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_6 [28:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port6_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6,0x1fffffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_SHAPER_STS_port6_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6,0x1fffffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_6_MASK 0x1fffffff
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_6_BITS 29
#define SWITCH_PAGE_4D_PN_QUEUE5_SHAPER_STS_PORT6_PAGE_4D_PN_QUEUE5_SHAPER_STS_BUCKET_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_P7_QUEUE5_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4D_P7_QUEUE5_SHAPER_STS :: PAGE_4D_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4D_P7_QUEUE5_SHAPER_STS :: PAGE_4D_P7_QUEUE5_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4D_P7_QUEUE5_SHAPER_STS :: PAGE_4D_P7_QUEUE5_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4D_P7_QUEUE5_SHAPER_STS_PAGE_4D_P7_QUEUE5_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_IMP_QUEUE5_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4D_IMP_QUEUE5_SHAPER_STS :: PAGE_4D_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4D_IMP_QUEUE5_SHAPER_STS :: PAGE_4D_IMP_QUEUE5_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4D_IMP_QUEUE5_SHAPER_STS :: PAGE_4D_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4D_IMP_QUEUE5_SHAPER_STS_PAGE_4D_IMP_QUEUE5_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port0 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port0 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port1 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port1 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port2 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port2 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port3 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port3 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port4 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port4 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port5 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port5 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port6 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port6 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_port6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH :: PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH :: PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_P7_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 :: PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0,x)
#define Rd_switch_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0)
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 :: PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1,x)
#define Rd_switch_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1)
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_PAGE_4D_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q5_CONFIG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port0 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port0 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT0_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port1 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port1 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT1_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port2 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port2 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT2_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port3 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port3 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT3_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port4 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port4 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT4_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port5 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port5 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT5_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port6 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port6 :: PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_port6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_PORT6_PAGE_4D_PN_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL :: PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL :: PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_P7_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL :: PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_PAGE_4D_IMP_QUEUE5_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_QUEUE5_AVB_SHAPING_MODE
 ***************************************************************************/
/* switch :: PAGE_4D_QUEUE5_AVB_SHAPING_MODE :: PAGE_4D_QUEUE5_AVB_SHAPING_MODE_RESERVED [15:09] */
#define Wr_switch_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE,0xfe00,9,x)
#define Rd_switch_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE,0xfe00,9)
#define SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_RESERVED_SHIFT 9

/* switch :: PAGE_4D_QUEUE5_AVB_SHAPING_MODE :: PAGE_4D_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE [08:00] */
#define Wr_switch_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE(x) WriteRegBits16(SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE,0x1ff,0,x)
#define Rd_switch_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE(x) ReadRegBits16(SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE,0x1ff,0)
#define SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_MASK 0x01ff
#define SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_ALIGN 0
#define SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_BITS 9
#define SWITCH_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_PAGE_4D_QUEUE5_AVB_SHAPING_MODE_QUEUE5_AVB_SHAPING_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_QUEUE5_SHAPER_ENABLE
 ***************************************************************************/
/* switch :: PAGE_4D_QUEUE5_SHAPER_ENABLE :: PAGE_4D_QUEUE5_SHAPER_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE,0xfe00,9)
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_4D_QUEUE5_SHAPER_ENABLE :: PAGE_4D_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE [08:00] */
#define Wr_switch_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE(x) WriteRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE(x) ReadRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE,0x1ff,0)
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_MASK 0x01ff
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_ALIGN 0
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_BITS 9
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_ENABLE_PAGE_4D_QUEUE5_SHAPER_ENABLE_QUEUE5_SHAPER_ENABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT
 ***************************************************************************/
/* switch :: PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_RESERVED [15:09] */
#define Wr_switch_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9,x)
#define Rd_switch_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9)
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_RESERVED_BITS 7
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_RESERVED_SHIFT 9

/* switch :: PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT [08:00] */
#define Wr_switch_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT(x) WriteRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0,x)
#define Rd_switch_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT(x) ReadRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0)
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_MASK 0x01ff
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_ALIGN 0
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_BITS 9
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_PAGE_4D_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_QUEUE5_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4D_QUEUE5_SHAPER_BLOCKING
 ***************************************************************************/
/* switch :: PAGE_4D_QUEUE5_SHAPER_BLOCKING :: PAGE_4D_QUEUE5_SHAPER_BLOCKING_RESERVED [15:09] */
#define Wr_switch_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING,0xfe00,9,x)
#define Rd_switch_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING,0xfe00,9)
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_RESERVED_ALIGN 0
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_RESERVED_BITS 7
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_RESERVED_SHIFT 9

/* switch :: PAGE_4D_QUEUE5_SHAPER_BLOCKING :: PAGE_4D_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING [08:00] */
#define Wr_switch_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING(x) WriteRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING,0x1ff,0,x)
#define Rd_switch_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING(x) ReadRegBits16(SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING,0x1ff,0)
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_MASK 0x01ff
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_ALIGN 0
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_BITS 9
#define SWITCH_PAGE_4D_QUEUE5_SHAPER_BLOCKING_PAGE_4D_QUEUE5_SHAPER_BLOCKING_QUEUE5_SHAPER_BLOCKING_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port0 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port0 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port1 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port1 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port2 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port2 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port3 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port3 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port4 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port4 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port5 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port5 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port6 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_port6 :: PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_REFRESH_port6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_P7_QUEUE6_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4E_P7_QUEUE6_MAX_REFRESH :: PAGE_4E_P7_QUEUE6_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4E_P7_QUEUE6_MAX_REFRESH :: PAGE_4E_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_PAGE_4E_P7_QUEUE6_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_IMP_QUEUE6_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4E_IMP_QUEUE6_MAX_REFRESH :: PAGE_4E_IMP_QUEUE6_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4E_IMP_QUEUE6_MAX_REFRESH :: PAGE_4E_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port0 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port0 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port1 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port1 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port2 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port2 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port3 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port3 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port4 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port4 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port5 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port5 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port6 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port6 :: PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_port6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_P7_QUEUE6_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4E_P7_QUEUE6_MAX_THD_SEL :: PAGE_4E_P7_QUEUE6_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4E_P7_QUEUE6_MAX_THD_SEL :: PAGE_4E_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_IMP_QUEUE6_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4E_IMP_QUEUE6_MAX_THD_SEL :: PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4E_IMP_QUEUE6_MAX_THD_SEL :: PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port0
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port0 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_0 [31:31] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port0_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port0_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0,0x80000000,31)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_0_MASK 0x80000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_0_BITS 1
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_0_SHIFT 31

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port0 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_0 [30:29] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port0_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0,0x60000000,29,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port0_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0,0x60000000,29)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_0_MASK 0x60000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_0_BITS 2
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_0_SHIFT 29

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port0 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_0 [28:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port0_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0,0x1fffffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port0_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0,0x1fffffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_0_MASK 0x1fffffff
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_0_BITS 29
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT0_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port1
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port1 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_1 [31:31] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port1_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port1_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1,0x80000000,31)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_1_MASK 0x80000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_1_BITS 1
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_1_SHIFT 31

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port1 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_1 [30:29] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port1_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1,0x60000000,29,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port1_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1,0x60000000,29)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_1_MASK 0x60000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_1_BITS 2
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_1_SHIFT 29

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port1 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_1 [28:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port1_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1,0x1fffffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port1_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1,0x1fffffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_1_MASK 0x1fffffff
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_1_BITS 29
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT1_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port2
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port2 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_2 [31:31] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port2_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port2_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2,0x80000000,31)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_2_MASK 0x80000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_2_BITS 1
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_2_SHIFT 31

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port2 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_2 [30:29] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port2_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2,0x60000000,29,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port2_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2,0x60000000,29)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_2_MASK 0x60000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_2_BITS 2
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_2_SHIFT 29

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port2 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_2 [28:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port2_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2,0x1fffffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port2_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2,0x1fffffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_2_MASK 0x1fffffff
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_2_BITS 29
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT2_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port3
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port3 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_3 [31:31] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port3_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port3_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3,0x80000000,31)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_3_MASK 0x80000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_3_BITS 1
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_3_SHIFT 31

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port3 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_3 [30:29] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port3_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3,0x60000000,29,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port3_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3,0x60000000,29)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_3_MASK 0x60000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_3_BITS 2
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_3_SHIFT 29

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port3 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_3 [28:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port3_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3,0x1fffffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port3_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3,0x1fffffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_3_MASK 0x1fffffff
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_3_BITS 29
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT3_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port4
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port4 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_4 [31:31] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port4_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port4_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4,0x80000000,31)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_4_MASK 0x80000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_4_BITS 1
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_4_SHIFT 31

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port4 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_4 [30:29] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port4_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4,0x60000000,29,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port4_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4,0x60000000,29)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_4_MASK 0x60000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_4_BITS 2
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_4_SHIFT 29

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port4 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_4 [28:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port4_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4,0x1fffffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port4_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4,0x1fffffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_4_MASK 0x1fffffff
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_4_BITS 29
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT4_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port5
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port5 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_5 [31:31] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port5_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port5_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5,0x80000000,31)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_5_MASK 0x80000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_5_BITS 1
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_5_SHIFT 31

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port5 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_5 [30:29] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port5_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5,0x60000000,29,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port5_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5,0x60000000,29)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_5_MASK 0x60000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_5_BITS 2
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_5_SHIFT 29

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port5 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_5 [28:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port5_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5,0x1fffffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port5_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5,0x1fffffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_5_MASK 0x1fffffff
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_5_BITS 29
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT5_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port6
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port6 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_6 [31:31] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port6_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port6_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6,0x80000000,31)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_6_MASK 0x80000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_6_BITS 1
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_6_SHIFT 31

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port6 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_6 [30:29] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port6_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6,0x60000000,29,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port6_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6,0x60000000,29)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_6_MASK 0x60000000
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_6_BITS 2
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_RESERVED_6_SHIFT 29

/* switch :: PAGE_4E_PN_QUEUE6_SHAPER_STS_port6 :: PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_6 [28:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port6_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6,0x1fffffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_SHAPER_STS_port6_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6,0x1fffffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_6_MASK 0x1fffffff
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_6_BITS 29
#define SWITCH_PAGE_4E_PN_QUEUE6_SHAPER_STS_PORT6_PAGE_4E_PN_QUEUE6_SHAPER_STS_BUCKET_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_P7_QUEUE6_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4E_P7_QUEUE6_SHAPER_STS :: PAGE_4E_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4E_P7_QUEUE6_SHAPER_STS :: PAGE_4E_P7_QUEUE6_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4E_P7_QUEUE6_SHAPER_STS :: PAGE_4E_P7_QUEUE6_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4E_P7_QUEUE6_SHAPER_STS_PAGE_4E_P7_QUEUE6_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_IMP_QUEUE6_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4E_IMP_QUEUE6_SHAPER_STS :: PAGE_4E_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4E_IMP_QUEUE6_SHAPER_STS :: PAGE_4E_IMP_QUEUE6_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4E_IMP_QUEUE6_SHAPER_STS :: PAGE_4E_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4E_IMP_QUEUE6_SHAPER_STS_PAGE_4E_IMP_QUEUE6_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port0 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port0 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port1 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port1 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port2 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port2 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port3 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port3 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port4 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port4 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port5 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port5 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port6 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port6 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_port6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH :: PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH :: PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_P7_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 :: PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0,x)
#define Rd_switch_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0)
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 :: PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1,x)
#define Rd_switch_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1)
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_PAGE_4E_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q6_CONFIG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port0 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port0 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT0_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port1 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port1 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT1_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port2 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port2 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT2_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port3 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port3 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT3_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port4 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port4 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT4_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port5 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port5 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT5_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port6 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port6 :: PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_port6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_PORT6_PAGE_4E_PN_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL :: PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL :: PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_P7_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL :: PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_PAGE_4E_IMP_QUEUE6_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_QUEUE6_AVB_SHAPING_MODE
 ***************************************************************************/
/* switch :: PAGE_4E_QUEUE6_AVB_SHAPING_MODE :: PAGE_4E_QUEUE6_AVB_SHAPING_MODE_RESERVED [15:09] */
#define Wr_switch_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE,0xfe00,9,x)
#define Rd_switch_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE,0xfe00,9)
#define SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_RESERVED_SHIFT 9

/* switch :: PAGE_4E_QUEUE6_AVB_SHAPING_MODE :: PAGE_4E_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE [08:00] */
#define Wr_switch_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE(x) WriteRegBits16(SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE,0x1ff,0,x)
#define Rd_switch_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE(x) ReadRegBits16(SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE,0x1ff,0)
#define SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_MASK 0x01ff
#define SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_ALIGN 0
#define SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_BITS 9
#define SWITCH_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_PAGE_4E_QUEUE6_AVB_SHAPING_MODE_QUEUE6_AVB_SHAPING_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_QUEUE6_SHAPER_ENABLE
 ***************************************************************************/
/* switch :: PAGE_4E_QUEUE6_SHAPER_ENABLE :: PAGE_4E_QUEUE6_SHAPER_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE,0xfe00,9)
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_4E_QUEUE6_SHAPER_ENABLE :: PAGE_4E_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE [08:00] */
#define Wr_switch_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE(x) WriteRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE(x) ReadRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE,0x1ff,0)
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_MASK 0x01ff
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_ALIGN 0
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_BITS 9
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_ENABLE_PAGE_4E_QUEUE6_SHAPER_ENABLE_QUEUE6_SHAPER_ENABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT
 ***************************************************************************/
/* switch :: PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_RESERVED [15:09] */
#define Wr_switch_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9,x)
#define Rd_switch_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9)
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_RESERVED_BITS 7
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_RESERVED_SHIFT 9

/* switch :: PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT [08:00] */
#define Wr_switch_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT(x) WriteRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0,x)
#define Rd_switch_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT(x) ReadRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0)
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_MASK 0x01ff
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_ALIGN 0
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_BITS 9
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_PAGE_4E_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_QUEUE6_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4E_QUEUE6_SHAPER_BLOCKING
 ***************************************************************************/
/* switch :: PAGE_4E_QUEUE6_SHAPER_BLOCKING :: PAGE_4E_QUEUE6_SHAPER_BLOCKING_RESERVED [15:09] */
#define Wr_switch_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING,0xfe00,9,x)
#define Rd_switch_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING,0xfe00,9)
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_RESERVED_ALIGN 0
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_RESERVED_BITS 7
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_RESERVED_SHIFT 9

/* switch :: PAGE_4E_QUEUE6_SHAPER_BLOCKING :: PAGE_4E_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING [08:00] */
#define Wr_switch_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING(x) WriteRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING,0x1ff,0,x)
#define Rd_switch_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING(x) ReadRegBits16(SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING,0x1ff,0)
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_MASK 0x01ff
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_ALIGN 0
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_BITS 9
#define SWITCH_PAGE_4E_QUEUE6_SHAPER_BLOCKING_PAGE_4E_QUEUE6_SHAPER_BLOCKING_QUEUE6_SHAPER_BLOCKING_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port0 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port0 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port1 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port1 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port2 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port2 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port3 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port3 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port4 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port4 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port5 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port5 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port6 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_port6 :: PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_REFRESH_port6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_P7_QUEUE7_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4F_P7_QUEUE7_MAX_REFRESH :: PAGE_4F_P7_QUEUE7_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4F_P7_QUEUE7_MAX_REFRESH :: PAGE_4F_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_PAGE_4F_P7_QUEUE7_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_IMP_QUEUE7_MAX_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4F_IMP_QUEUE7_MAX_REFRESH :: PAGE_4F_IMP_QUEUE7_MAX_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4F_IMP_QUEUE7_MAX_REFRESH :: PAGE_4F_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port0 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port0 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port1 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port1 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port2 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port2 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port3 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port3 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port4 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port4 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port5 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port5 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port6 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port6 :: PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_port6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_P7_QUEUE7_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4F_P7_QUEUE7_MAX_THD_SEL :: PAGE_4F_P7_QUEUE7_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4F_P7_QUEUE7_MAX_THD_SEL :: PAGE_4F_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_IMP_QUEUE7_MAX_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4F_IMP_QUEUE7_MAX_THD_SEL :: PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4F_IMP_QUEUE7_MAX_THD_SEL :: PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port0
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port0 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_0 [31:31] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port0_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port0_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0,0x80000000,31)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_0_MASK 0x80000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_0_BITS 1
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_0_SHIFT 31

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port0 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_0 [30:29] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port0_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0,0x60000000,29,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port0_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0,0x60000000,29)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_0_MASK 0x60000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_0_BITS 2
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_0_SHIFT 29

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port0 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_0 [28:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port0_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0,0x1fffffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port0_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0,0x1fffffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_0_MASK 0x1fffffff
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_0_BITS 29
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT0_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port1
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port1 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_1 [31:31] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port1_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port1_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1,0x80000000,31)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_1_MASK 0x80000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_1_BITS 1
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_1_SHIFT 31

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port1 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_1 [30:29] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port1_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1,0x60000000,29,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port1_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1,0x60000000,29)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_1_MASK 0x60000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_1_BITS 2
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_1_SHIFT 29

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port1 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_1 [28:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port1_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1,0x1fffffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port1_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1,0x1fffffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_1_MASK 0x1fffffff
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_1_BITS 29
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT1_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port2
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port2 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_2 [31:31] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port2_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port2_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2,0x80000000,31)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_2_MASK 0x80000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_2_BITS 1
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_2_SHIFT 31

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port2 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_2 [30:29] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port2_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2,0x60000000,29,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port2_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2,0x60000000,29)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_2_MASK 0x60000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_2_BITS 2
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_2_SHIFT 29

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port2 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_2 [28:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port2_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2,0x1fffffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port2_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2,0x1fffffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_2_MASK 0x1fffffff
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_2_BITS 29
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT2_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port3
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port3 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_3 [31:31] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port3_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port3_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3,0x80000000,31)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_3_MASK 0x80000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_3_BITS 1
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_3_SHIFT 31

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port3 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_3 [30:29] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port3_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3,0x60000000,29,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port3_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3,0x60000000,29)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_3_MASK 0x60000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_3_BITS 2
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_3_SHIFT 29

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port3 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_3 [28:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port3_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3,0x1fffffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port3_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3,0x1fffffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_3_MASK 0x1fffffff
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_3_BITS 29
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT3_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port4
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port4 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_4 [31:31] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port4_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port4_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4,0x80000000,31)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_4_MASK 0x80000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_4_BITS 1
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_4_SHIFT 31

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port4 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_4 [30:29] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port4_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4,0x60000000,29,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port4_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4,0x60000000,29)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_4_MASK 0x60000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_4_BITS 2
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_4_SHIFT 29

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port4 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_4 [28:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port4_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4,0x1fffffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port4_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4,0x1fffffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_4_MASK 0x1fffffff
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_4_BITS 29
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT4_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port5
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port5 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_5 [31:31] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port5_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port5_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5,0x80000000,31)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_5_MASK 0x80000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_5_BITS 1
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_5_SHIFT 31

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port5 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_5 [30:29] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port5_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5,0x60000000,29,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port5_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5,0x60000000,29)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_5_MASK 0x60000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_5_BITS 2
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_5_SHIFT 29

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port5 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_5 [28:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port5_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5,0x1fffffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port5_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5,0x1fffffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_5_MASK 0x1fffffff
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_5_BITS 29
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT5_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port6
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port6 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_6 [31:31] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port6_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port6_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6,0x80000000,31)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_6_MASK 0x80000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_6_BITS 1
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_6_SHIFT 31

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port6 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_6 [30:29] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port6_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6,0x60000000,29,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port6_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6,0x60000000,29)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_6_MASK 0x60000000
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_6_BITS 2
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_RESERVED_6_SHIFT 29

/* switch :: PAGE_4F_PN_QUEUE7_SHAPER_STS_port6 :: PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_6 [28:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port6_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6,0x1fffffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_SHAPER_STS_port6_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6,0x1fffffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_6_MASK 0x1fffffff
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_6_BITS 29
#define SWITCH_PAGE_4F_PN_QUEUE7_SHAPER_STS_PORT6_PAGE_4F_PN_QUEUE7_SHAPER_STS_BUCKET_CNT_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_P7_QUEUE7_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4F_P7_QUEUE7_SHAPER_STS :: PAGE_4F_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4F_P7_QUEUE7_SHAPER_STS :: PAGE_4F_P7_QUEUE7_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4F_P7_QUEUE7_SHAPER_STS :: PAGE_4F_P7_QUEUE7_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4F_P7_QUEUE7_SHAPER_STS_PAGE_4F_P7_QUEUE7_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_IMP_QUEUE7_SHAPER_STS
 ***************************************************************************/
/* switch :: PAGE_4F_IMP_QUEUE7_SHAPER_STS :: PAGE_4F_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG [31:31] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS,0x80000000,31,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS,0x80000000,31)
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_MASK 0x80000000
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_BITS 1
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_IN_PROFILE_FLAG_SHIFT 31

/* switch :: PAGE_4F_IMP_QUEUE7_SHAPER_STS :: PAGE_4F_IMP_QUEUE7_SHAPER_STS_RESERVED [30:29] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS,0x60000000,29,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS,0x60000000,29)
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_RESERVED_MASK 0x60000000
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_RESERVED_BITS 2
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_RESERVED_SHIFT 29

/* switch :: PAGE_4F_IMP_QUEUE7_SHAPER_STS :: PAGE_4F_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT [28:00] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS,0x1fffffff,0,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS,0x1fffffff,0)
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_MASK 0x1fffffff
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_BITS 29
#define SWITCH_PAGE_4F_IMP_QUEUE7_SHAPER_STS_PAGE_4F_IMP_QUEUE7_SHAPER_STS_BUCKET_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port0
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port0 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_0_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_0_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port0 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_0 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_0_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_0_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port1
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port1 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_1_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_1_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port1 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_1 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_1_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_1_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port2
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port2 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_2_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_2_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port2 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_2 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_2_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_2_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port3
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port3 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_3_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_3_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port3 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_3 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_3_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_3_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port4
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port4 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_4_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_4_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port4 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_4 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_4_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_4_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port5
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port5 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_5_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_5_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port5 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_5 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_5_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_5_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port6
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port6 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_6_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_RESERVED_6_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port6 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_6 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_port6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_6_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_6_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH :: PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH :: PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_P7_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH
 ***************************************************************************/
/* switch :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_RESERVED [31:18] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH,0xfffc0000,18)
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_RESERVED_BITS 14
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_RESERVED_SHIFT 18

/* switch :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH [17:00] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH,0x3ffff,0)
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_MASK 0x0003ffff
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_BITS 18
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_REFRESH_MAX_REFRESH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 :: PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0,x)
#define Rd_switch_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0)
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 :: PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1,x)
#define Rd_switch_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1)
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_PAGE_4F_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_EGRESS_SHAPER_Q7_CONFIG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port0
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port0 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_0_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_0_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port0 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_0 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_0(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT0_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port1
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port1 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_1 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_1_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_1_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_1_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port1 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_1 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_1(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT1_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port2
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port2 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_2 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_2_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_2_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_2_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port2 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_2 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_2(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT2_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port3
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port3 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_3 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_3_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_3_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_3_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port3 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_3 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_3(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT3_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port4
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port4 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_4 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_4_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_4_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_4_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port4 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_4 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_4(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT4_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port5
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port5 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_5 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_5_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_5_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_5_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port5 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_5 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_5(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT5_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port6
 ***************************************************************************/
/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port6 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_6 [31:18] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6,0xfffc0000,18)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_6_MASK 0xfffc0000
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_6_BITS 14
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_6_SHIFT 18

/* switch :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port6 :: PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_6 [17:00] */
#define Wr_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) WriteRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_port6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_6(x) ReadRegBits(SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6,0x3ffff,0)
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_MASK 0x0003ffff
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_ALIGN 0
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_BITS 18
#define SWITCH_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_PORT6_PAGE_4F_PN_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL :: PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL :: PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_P7_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL
 ***************************************************************************/
/* switch :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_RESERVED [31:18] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_RESERVED(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL,0xfffc0000,18,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_RESERVED(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL,0xfffc0000,18)
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_MASK 0xfffc0000
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_BITS 14
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_RESERVED_SHIFT 18

/* switch :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL :: PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL [17:00] */
#define Wr_switch_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) WriteRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL,0x3ffff,0,x)
#define Rd_switch_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL(x) ReadRegBits(SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL,0x3ffff,0)
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_MASK 0x0003ffff
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_ALIGN 0
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_BITS 18
#define SWITCH_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_PAGE_4F_IMP_QUEUE7_MAX_PACKET_THD_SEL_MAX_THD_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_QUEUE7_AVB_SHAPING_MODE
 ***************************************************************************/
/* switch :: PAGE_4F_QUEUE7_AVB_SHAPING_MODE :: PAGE_4F_QUEUE7_AVB_SHAPING_MODE_RESERVED [15:09] */
#define Wr_switch_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE,0xfe00,9,x)
#define Rd_switch_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE,0xfe00,9)
#define SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_RESERVED_BITS 7
#define SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_RESERVED_SHIFT 9

/* switch :: PAGE_4F_QUEUE7_AVB_SHAPING_MODE :: PAGE_4F_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE [08:00] */
#define Wr_switch_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE(x) WriteRegBits16(SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE,0x1ff,0,x)
#define Rd_switch_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE(x) ReadRegBits16(SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE,0x1ff,0)
#define SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_MASK 0x01ff
#define SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_ALIGN 0
#define SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_BITS 9
#define SWITCH_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_PAGE_4F_QUEUE7_AVB_SHAPING_MODE_QUEUE7_AVB_SHAPING_MODE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_QUEUE7_SHAPER_ENABLE
 ***************************************************************************/
/* switch :: PAGE_4F_QUEUE7_SHAPER_ENABLE :: PAGE_4F_QUEUE7_SHAPER_ENABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE,0xfe00,9,x)
#define Rd_switch_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE,0xfe00,9)
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_RESERVED_BITS 7
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_RESERVED_SHIFT 9

/* switch :: PAGE_4F_QUEUE7_SHAPER_ENABLE :: PAGE_4F_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE [08:00] */
#define Wr_switch_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE(x) WriteRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE,0x1ff,0,x)
#define Rd_switch_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE(x) ReadRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE,0x1ff,0)
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_MASK 0x01ff
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_ALIGN 0
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_BITS 9
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_ENABLE_PAGE_4F_QUEUE7_SHAPER_ENABLE_QUEUE7_SHAPER_ENABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT
 ***************************************************************************/
/* switch :: PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_RESERVED [15:09] */
#define Wr_switch_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9,x)
#define Rd_switch_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT,0xfe00,9)
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_RESERVED_BITS 7
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_RESERVED_SHIFT 9

/* switch :: PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT :: PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT [08:00] */
#define Wr_switch_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT(x) WriteRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0,x)
#define Rd_switch_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT(x) ReadRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT,0x1ff,0)
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_MASK 0x01ff
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_ALIGN 0
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_BITS 9
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_PAGE_4F_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_QUEUE7_SHAPER_BUCKET_COUNT_SELECT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_4F_QUEUE7_SHAPER_BLOCKING
 ***************************************************************************/
/* switch :: PAGE_4F_QUEUE7_SHAPER_BLOCKING :: PAGE_4F_QUEUE7_SHAPER_BLOCKING_RESERVED [15:09] */
#define Wr_switch_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_RESERVED(x) WriteRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING,0xfe00,9,x)
#define Rd_switch_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_RESERVED(x) ReadRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING,0xfe00,9)
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_RESERVED_ALIGN 0
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_RESERVED_BITS 7
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_RESERVED_SHIFT 9

/* switch :: PAGE_4F_QUEUE7_SHAPER_BLOCKING :: PAGE_4F_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING [08:00] */
#define Wr_switch_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING(x) WriteRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING,0x1ff,0,x)
#define Rd_switch_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING(x) ReadRegBits16(SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING,0x1ff,0)
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_MASK 0x01ff
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_ALIGN 0
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_BITS 9
#define SWITCH_PAGE_4F_QUEUE7_SHAPER_BLOCKING_PAGE_4F_QUEUE7_SHAPER_BLOCKING_QUEUE7_SHAPER_BLOCKING_SHIFT 0


/****************************************************************************
 * switch :: PAGE_70_MIB_SNAPSHOT_CTL
 ***************************************************************************/
/* switch :: PAGE_70_MIB_SNAPSHOT_CTL :: PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE [07:07] */
#define Wr_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE(x) WriteRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0x80,7,x)
#define Rd_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE(x) ReadRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0x80,7)
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_MASK 0x80
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_ALIGN 0
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_BITS 1
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_STDONE_SHIFT 7

/* switch :: PAGE_70_MIB_SNAPSHOT_CTL :: PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR [06:06] */
#define Wr_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR(x) WriteRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0x40,6,x)
#define Rd_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR(x) ReadRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0x40,6)
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_MASK 0x40
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_ALIGN 0
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_BITS 1
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_MIRROR_SHIFT 6

/* switch :: PAGE_70_MIB_SNAPSHOT_CTL :: PAGE_70_MIB_SNAPSHOT_CTL_RESERVED [05:05] */
#define Wr_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RESERVED(x) WriteRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0x20,5,x)
#define Rd_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RESERVED(x) ReadRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0x20,5)
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RESERVED_MASK 0x20
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RESERVED_BITS 1
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RESERVED_SHIFT 5

/* switch :: PAGE_70_MIB_SNAPSHOT_CTL :: PAGE_70_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN [04:04] */
#define Wr_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN(x) WriteRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0x10,4,x)
#define Rd_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN(x) ReadRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0x10,4)
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_MASK 0x10
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_ALIGN 0
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_BITS 1
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_RST_MIB_SNAPSHOT_CNT_EN_SHIFT 4

/* switch :: PAGE_70_MIB_SNAPSHOT_CTL :: PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT [03:00] */
#define Wr_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT(x) WriteRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0xf,0,x)
#define Rd_switch_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT(x) ReadRegBits(SWITCH_PAGE_70_MIB_SNAPSHOT_CTL,0xf,0)
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_MASK 0x0f
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_ALIGN 0
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_BITS 4
#define SWITCH_PAGE_70_MIB_SNAPSHOT_CTL_PAGE_70_MIB_SNAPSHOT_CTL_SNAPSHOT_PORT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxOctets
 ***************************************************************************/
/* switch :: PAGE_71_S_TxOctets :: PAGE_71_S_TxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_71_S_TxOctets_PAGE_71_S_TxOctets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXOCTETS,x)
#define Rd_switch_PAGE_71_S_TxOctets_PAGE_71_S_TxOctets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXOCTETS)
#define SWITCH_PAGE_71_S_TXOCTETS_PAGE_71_S_TXOCTETS_COUNT_MASK    0xffffffffffffffff
#define SWITCH_PAGE_71_S_TXOCTETS_PAGE_71_S_TXOCTETS_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_TXOCTETS_PAGE_71_S_TXOCTETS_COUNT_BITS    64
#define SWITCH_PAGE_71_S_TXOCTETS_PAGE_71_S_TXOCTETS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_TxDropPkts
 ***************************************************************************/
/* switch :: PAGE_71_S_TxDropPkts :: PAGE_71_S_TxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxDropPkts_PAGE_71_S_TxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXDROPPKTS,x)
#define Rd_switch_PAGE_71_S_TxDropPkts_PAGE_71_S_TxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXDROPPKTS)
#define SWITCH_PAGE_71_S_TXDROPPKTS_PAGE_71_S_TXDROPPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXDROPPKTS_PAGE_71_S_TXDROPPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXDROPPKTS_PAGE_71_S_TXDROPPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXDROPPKTS_PAGE_71_S_TXDROPPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxQPKTQ0
 ***************************************************************************/
/* switch :: PAGE_71_S_TxQPKTQ0 :: PAGE_71_S_TxQPKTQ0_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxQPKTQ0_PAGE_71_S_TxQPKTQ0_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXQPKTQ0,x)
#define Rd_switch_PAGE_71_S_TxQPKTQ0_PAGE_71_S_TxQPKTQ0_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXQPKTQ0)
#define SWITCH_PAGE_71_S_TXQPKTQ0_PAGE_71_S_TXQPKTQ0_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_71_S_TXQPKTQ0_PAGE_71_S_TXQPKTQ0_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_TXQPKTQ0_PAGE_71_S_TXQPKTQ0_COUNT_BITS    32
#define SWITCH_PAGE_71_S_TXQPKTQ0_PAGE_71_S_TXQPKTQ0_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_TxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_71_S_TxBroadcastPkts :: PAGE_71_S_TxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxBroadcastPkts_PAGE_71_S_TxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXBROADCASTPKTS,x)
#define Rd_switch_PAGE_71_S_TxBroadcastPkts_PAGE_71_S_TxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXBROADCASTPKTS)
#define SWITCH_PAGE_71_S_TXBROADCASTPKTS_PAGE_71_S_TXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXBROADCASTPKTS_PAGE_71_S_TXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXBROADCASTPKTS_PAGE_71_S_TXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXBROADCASTPKTS_PAGE_71_S_TXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_71_S_TxMulticastPkts :: PAGE_71_S_TxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxMulticastPkts_PAGE_71_S_TxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXMULTICASTPKTS,x)
#define Rd_switch_PAGE_71_S_TxMulticastPkts_PAGE_71_S_TxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXMULTICASTPKTS)
#define SWITCH_PAGE_71_S_TXMULTICASTPKTS_PAGE_71_S_TXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXMULTICASTPKTS_PAGE_71_S_TXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXMULTICASTPKTS_PAGE_71_S_TXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXMULTICASTPKTS_PAGE_71_S_TXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_71_S_TxUnicastPkts :: PAGE_71_S_TxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxUnicastPkts_PAGE_71_S_TxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXUNICASTPKTS,x)
#define Rd_switch_PAGE_71_S_TxUnicastPkts_PAGE_71_S_TxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXUNICASTPKTS)
#define SWITCH_PAGE_71_S_TXUNICASTPKTS_PAGE_71_S_TXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXUNICASTPKTS_PAGE_71_S_TXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXUNICASTPKTS_PAGE_71_S_TXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXUNICASTPKTS_PAGE_71_S_TXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxCollisions
 ***************************************************************************/
/* switch :: PAGE_71_S_TxCollisions :: PAGE_71_S_TxCollisions_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxCollisions_PAGE_71_S_TxCollisions_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXCOLLISIONS,x)
#define Rd_switch_PAGE_71_S_TxCollisions_PAGE_71_S_TxCollisions_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXCOLLISIONS)
#define SWITCH_PAGE_71_S_TXCOLLISIONS_PAGE_71_S_TXCOLLISIONS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXCOLLISIONS_PAGE_71_S_TXCOLLISIONS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXCOLLISIONS_PAGE_71_S_TXCOLLISIONS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXCOLLISIONS_PAGE_71_S_TXCOLLISIONS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxSingleCollision
 ***************************************************************************/
/* switch :: PAGE_71_S_TxSingleCollision :: PAGE_71_S_TxSingleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxSingleCollision_PAGE_71_S_TxSingleCollision_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXSINGLECOLLISION,x)
#define Rd_switch_PAGE_71_S_TxSingleCollision_PAGE_71_S_TxSingleCollision_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXSINGLECOLLISION)
#define SWITCH_PAGE_71_S_TXSINGLECOLLISION_PAGE_71_S_TXSINGLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXSINGLECOLLISION_PAGE_71_S_TXSINGLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXSINGLECOLLISION_PAGE_71_S_TXSINGLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXSINGLECOLLISION_PAGE_71_S_TXSINGLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxMultipleCollision
 ***************************************************************************/
/* switch :: PAGE_71_S_TxMultipleCollision :: PAGE_71_S_TxMultipleCollision_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxMultipleCollision_PAGE_71_S_TxMultipleCollision_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXMULTIPLECOLLISION,x)
#define Rd_switch_PAGE_71_S_TxMultipleCollision_PAGE_71_S_TxMultipleCollision_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXMULTIPLECOLLISION)
#define SWITCH_PAGE_71_S_TXMULTIPLECOLLISION_PAGE_71_S_TXMULTIPLECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXMULTIPLECOLLISION_PAGE_71_S_TXMULTIPLECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXMULTIPLECOLLISION_PAGE_71_S_TXMULTIPLECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXMULTIPLECOLLISION_PAGE_71_S_TXMULTIPLECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxDeferredTransmit
 ***************************************************************************/
/* switch :: PAGE_71_S_TxDeferredTransmit :: PAGE_71_S_TxDeferredTransmit_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxDeferredTransmit_PAGE_71_S_TxDeferredTransmit_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXDEFERREDTRANSMIT,x)
#define Rd_switch_PAGE_71_S_TxDeferredTransmit_PAGE_71_S_TxDeferredTransmit_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXDEFERREDTRANSMIT)
#define SWITCH_PAGE_71_S_TXDEFERREDTRANSMIT_PAGE_71_S_TXDEFERREDTRANSMIT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXDEFERREDTRANSMIT_PAGE_71_S_TXDEFERREDTRANSMIT_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXDEFERREDTRANSMIT_PAGE_71_S_TXDEFERREDTRANSMIT_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXDEFERREDTRANSMIT_PAGE_71_S_TXDEFERREDTRANSMIT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxLateCollision
 ***************************************************************************/
/* switch :: PAGE_71_S_TxLateCollision :: PAGE_71_S_TxLateCollision_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxLateCollision_PAGE_71_S_TxLateCollision_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXLATECOLLISION,x)
#define Rd_switch_PAGE_71_S_TxLateCollision_PAGE_71_S_TxLateCollision_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXLATECOLLISION)
#define SWITCH_PAGE_71_S_TXLATECOLLISION_PAGE_71_S_TXLATECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXLATECOLLISION_PAGE_71_S_TXLATECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXLATECOLLISION_PAGE_71_S_TXLATECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXLATECOLLISION_PAGE_71_S_TXLATECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxExcessiveCollision
 ***************************************************************************/
/* switch :: PAGE_71_S_TxExcessiveCollision :: PAGE_71_S_TxExcessiveCollision_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxExcessiveCollision_PAGE_71_S_TxExcessiveCollision_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXEXCESSIVECOLLISION,x)
#define Rd_switch_PAGE_71_S_TxExcessiveCollision_PAGE_71_S_TxExcessiveCollision_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXEXCESSIVECOLLISION)
#define SWITCH_PAGE_71_S_TXEXCESSIVECOLLISION_PAGE_71_S_TXEXCESSIVECOLLISION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXEXCESSIVECOLLISION_PAGE_71_S_TXEXCESSIVECOLLISION_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXEXCESSIVECOLLISION_PAGE_71_S_TXEXCESSIVECOLLISION_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXEXCESSIVECOLLISION_PAGE_71_S_TXEXCESSIVECOLLISION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxFrameInDisc
 ***************************************************************************/
/* switch :: PAGE_71_S_TxFrameInDisc :: PAGE_71_S_TxFrameInDisc_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxFrameInDisc_PAGE_71_S_TxFrameInDisc_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXFRAMEINDISC,x)
#define Rd_switch_PAGE_71_S_TxFrameInDisc_PAGE_71_S_TxFrameInDisc_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXFRAMEINDISC)
#define SWITCH_PAGE_71_S_TXFRAMEINDISC_PAGE_71_S_TXFRAMEINDISC_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXFRAMEINDISC_PAGE_71_S_TXFRAMEINDISC_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXFRAMEINDISC_PAGE_71_S_TXFRAMEINDISC_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXFRAMEINDISC_PAGE_71_S_TXFRAMEINDISC_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxPausePkts
 ***************************************************************************/
/* switch :: PAGE_71_S_TxPausePkts :: PAGE_71_S_TxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxPausePkts_PAGE_71_S_TxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXPAUSEPKTS,x)
#define Rd_switch_PAGE_71_S_TxPausePkts_PAGE_71_S_TxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXPAUSEPKTS)
#define SWITCH_PAGE_71_S_TXPAUSEPKTS_PAGE_71_S_TXPAUSEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXPAUSEPKTS_PAGE_71_S_TXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXPAUSEPKTS_PAGE_71_S_TXPAUSEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXPAUSEPKTS_PAGE_71_S_TXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxQPKTQ1
 ***************************************************************************/
/* switch :: PAGE_71_S_TxQPKTQ1 :: PAGE_71_S_TxQPKTQ1_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxQPKTQ1_PAGE_71_S_TxQPKTQ1_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXQPKTQ1,x)
#define Rd_switch_PAGE_71_S_TxQPKTQ1_PAGE_71_S_TxQPKTQ1_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXQPKTQ1)
#define SWITCH_PAGE_71_S_TXQPKTQ1_PAGE_71_S_TXQPKTQ1_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_71_S_TXQPKTQ1_PAGE_71_S_TXQPKTQ1_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_TXQPKTQ1_PAGE_71_S_TXQPKTQ1_COUNT_BITS    32
#define SWITCH_PAGE_71_S_TXQPKTQ1_PAGE_71_S_TXQPKTQ1_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_TxQPKTQ2
 ***************************************************************************/
/* switch :: PAGE_71_S_TxQPKTQ2 :: PAGE_71_S_TxQPKTQ2_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxQPKTQ2_PAGE_71_S_TxQPKTQ2_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXQPKTQ2,x)
#define Rd_switch_PAGE_71_S_TxQPKTQ2_PAGE_71_S_TxQPKTQ2_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXQPKTQ2)
#define SWITCH_PAGE_71_S_TXQPKTQ2_PAGE_71_S_TXQPKTQ2_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_71_S_TXQPKTQ2_PAGE_71_S_TXQPKTQ2_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_TXQPKTQ2_PAGE_71_S_TXQPKTQ2_COUNT_BITS    32
#define SWITCH_PAGE_71_S_TXQPKTQ2_PAGE_71_S_TXQPKTQ2_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_TxQPKTQ3
 ***************************************************************************/
/* switch :: PAGE_71_S_TxQPKTQ3 :: PAGE_71_S_TxQPKTQ3_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxQPKTQ3_PAGE_71_S_TxQPKTQ3_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXQPKTQ3,x)
#define Rd_switch_PAGE_71_S_TxQPKTQ3_PAGE_71_S_TxQPKTQ3_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXQPKTQ3)
#define SWITCH_PAGE_71_S_TXQPKTQ3_PAGE_71_S_TXQPKTQ3_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_71_S_TXQPKTQ3_PAGE_71_S_TXQPKTQ3_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_TXQPKTQ3_PAGE_71_S_TXQPKTQ3_COUNT_BITS    32
#define SWITCH_PAGE_71_S_TXQPKTQ3_PAGE_71_S_TXQPKTQ3_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_TxQPKTQ4
 ***************************************************************************/
/* switch :: PAGE_71_S_TxQPKTQ4 :: PAGE_71_S_TxQPKTQ4_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxQPKTQ4_PAGE_71_S_TxQPKTQ4_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXQPKTQ4,x)
#define Rd_switch_PAGE_71_S_TxQPKTQ4_PAGE_71_S_TxQPKTQ4_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXQPKTQ4)
#define SWITCH_PAGE_71_S_TXQPKTQ4_PAGE_71_S_TXQPKTQ4_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_71_S_TXQPKTQ4_PAGE_71_S_TXQPKTQ4_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_TXQPKTQ4_PAGE_71_S_TXQPKTQ4_COUNT_BITS    32
#define SWITCH_PAGE_71_S_TXQPKTQ4_PAGE_71_S_TXQPKTQ4_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_TxQPKTQ5
 ***************************************************************************/
/* switch :: PAGE_71_S_TxQPKTQ5 :: PAGE_71_S_TxQPKTQ5_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxQPKTQ5_PAGE_71_S_TxQPKTQ5_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXQPKTQ5,x)
#define Rd_switch_PAGE_71_S_TxQPKTQ5_PAGE_71_S_TxQPKTQ5_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXQPKTQ5)
#define SWITCH_PAGE_71_S_TXQPKTQ5_PAGE_71_S_TXQPKTQ5_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_71_S_TXQPKTQ5_PAGE_71_S_TXQPKTQ5_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_TXQPKTQ5_PAGE_71_S_TXQPKTQ5_COUNT_BITS    32
#define SWITCH_PAGE_71_S_TXQPKTQ5_PAGE_71_S_TXQPKTQ5_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_RxOctets
 ***************************************************************************/
/* switch :: PAGE_71_S_RxOctets :: PAGE_71_S_RxOctets_COUNT [63:00] */
#define Wr_switch_PAGE_71_S_RxOctets_PAGE_71_S_RxOctets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXOCTETS,x)
#define Rd_switch_PAGE_71_S_RxOctets_PAGE_71_S_RxOctets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXOCTETS)
#define SWITCH_PAGE_71_S_RXOCTETS_PAGE_71_S_RXOCTETS_COUNT_MASK    0xffffffffffffffff
#define SWITCH_PAGE_71_S_RXOCTETS_PAGE_71_S_RXOCTETS_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_RXOCTETS_PAGE_71_S_RXOCTETS_COUNT_BITS    64
#define SWITCH_PAGE_71_S_RXOCTETS_PAGE_71_S_RXOCTETS_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_RxUndersizePkts
 ***************************************************************************/
/* switch :: PAGE_71_S_RxUndersizePkts :: PAGE_71_S_RxUndersizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxUndersizePkts_PAGE_71_S_RxUndersizePkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXUNDERSIZEPKTS,x)
#define Rd_switch_PAGE_71_S_RxUndersizePkts_PAGE_71_S_RxUndersizePkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXUNDERSIZEPKTS)
#define SWITCH_PAGE_71_S_RXUNDERSIZEPKTS_PAGE_71_S_RXUNDERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXUNDERSIZEPKTS_PAGE_71_S_RXUNDERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXUNDERSIZEPKTS_PAGE_71_S_RXUNDERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXUNDERSIZEPKTS_PAGE_71_S_RXUNDERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxPausePkts
 ***************************************************************************/
/* switch :: PAGE_71_S_RxPausePkts :: PAGE_71_S_RxPausePkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxPausePkts_PAGE_71_S_RxPausePkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXPAUSEPKTS,x)
#define Rd_switch_PAGE_71_S_RxPausePkts_PAGE_71_S_RxPausePkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXPAUSEPKTS)
#define SWITCH_PAGE_71_S_RXPAUSEPKTS_PAGE_71_S_RXPAUSEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXPAUSEPKTS_PAGE_71_S_RXPAUSEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXPAUSEPKTS_PAGE_71_S_RXPAUSEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXPAUSEPKTS_PAGE_71_S_RXPAUSEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_RxPkts64Octets :: PAGE_71_S_RxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxPkts64Octets_PAGE_71_S_RxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXPKTS64OCTETS,x)
#define Rd_switch_PAGE_71_S_RxPkts64Octets_PAGE_71_S_RxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXPKTS64OCTETS)
#define SWITCH_PAGE_71_S_RXPKTS64OCTETS_PAGE_71_S_RXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXPKTS64OCTETS_PAGE_71_S_RXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXPKTS64OCTETS_PAGE_71_S_RXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXPKTS64OCTETS_PAGE_71_S_RXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_RxPkts65to127Octets :: PAGE_71_S_RxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxPkts65to127Octets_PAGE_71_S_RxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_71_S_RxPkts65to127Octets_PAGE_71_S_RxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXPKTS65TO127OCTETS)
#define SWITCH_PAGE_71_S_RXPKTS65TO127OCTETS_PAGE_71_S_RXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXPKTS65TO127OCTETS_PAGE_71_S_RXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXPKTS65TO127OCTETS_PAGE_71_S_RXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXPKTS65TO127OCTETS_PAGE_71_S_RXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_RxPkts128to255Octets :: PAGE_71_S_RxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxPkts128to255Octets_PAGE_71_S_RxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_71_S_RxPkts128to255Octets_PAGE_71_S_RxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXPKTS128TO255OCTETS)
#define SWITCH_PAGE_71_S_RXPKTS128TO255OCTETS_PAGE_71_S_RXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXPKTS128TO255OCTETS_PAGE_71_S_RXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXPKTS128TO255OCTETS_PAGE_71_S_RXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXPKTS128TO255OCTETS_PAGE_71_S_RXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_RxPkts256to511Octets :: PAGE_71_S_RxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxPkts256to511Octets_PAGE_71_S_RxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_71_S_RxPkts256to511Octets_PAGE_71_S_RxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXPKTS256TO511OCTETS)
#define SWITCH_PAGE_71_S_RXPKTS256TO511OCTETS_PAGE_71_S_RXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXPKTS256TO511OCTETS_PAGE_71_S_RXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXPKTS256TO511OCTETS_PAGE_71_S_RXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXPKTS256TO511OCTETS_PAGE_71_S_RXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_RxPkts512to1023Octets :: PAGE_71_S_RxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxPkts512to1023Octets_PAGE_71_S_RxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_71_S_RxPkts512to1023Octets_PAGE_71_S_RxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_71_S_RXPKTS512TO1023OCTETS_PAGE_71_S_RXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXPKTS512TO1023OCTETS_PAGE_71_S_RXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXPKTS512TO1023OCTETS_PAGE_71_S_RXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXPKTS512TO1023OCTETS_PAGE_71_S_RXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_71_S_RxPkts1024toMaxPktOctets :: PAGE_71_S_RxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxPkts1024toMaxPktOctets_PAGE_71_S_RxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_71_S_RxPkts1024toMaxPktOctets_PAGE_71_S_RxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS_PAGE_71_S_RXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxOversizePkts
 ***************************************************************************/
/* switch :: PAGE_71_S_RxOversizePkts :: PAGE_71_S_RxOversizePkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxOversizePkts_PAGE_71_S_RxOversizePkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXOVERSIZEPKTS,x)
#define Rd_switch_PAGE_71_S_RxOversizePkts_PAGE_71_S_RxOversizePkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXOVERSIZEPKTS)
#define SWITCH_PAGE_71_S_RXOVERSIZEPKTS_PAGE_71_S_RXOVERSIZEPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXOVERSIZEPKTS_PAGE_71_S_RXOVERSIZEPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXOVERSIZEPKTS_PAGE_71_S_RXOVERSIZEPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXOVERSIZEPKTS_PAGE_71_S_RXOVERSIZEPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxJabbers
 ***************************************************************************/
/* switch :: PAGE_71_S_RxJabbers :: PAGE_71_S_RxJabbers_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxJabbers_PAGE_71_S_RxJabbers_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXJABBERS,x)
#define Rd_switch_PAGE_71_S_RxJabbers_PAGE_71_S_RxJabbers_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXJABBERS)
#define SWITCH_PAGE_71_S_RXJABBERS_PAGE_71_S_RXJABBERS_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_71_S_RXJABBERS_PAGE_71_S_RXJABBERS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXJABBERS_PAGE_71_S_RXJABBERS_COUNT_BITS  32
#define SWITCH_PAGE_71_S_RXJABBERS_PAGE_71_S_RXJABBERS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxAlignmentErrors
 ***************************************************************************/
/* switch :: PAGE_71_S_RxAlignmentErrors :: PAGE_71_S_RxAlignmentErrors_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxAlignmentErrors_PAGE_71_S_RxAlignmentErrors_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXALIGNMENTERRORS,x)
#define Rd_switch_PAGE_71_S_RxAlignmentErrors_PAGE_71_S_RxAlignmentErrors_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXALIGNMENTERRORS)
#define SWITCH_PAGE_71_S_RXALIGNMENTERRORS_PAGE_71_S_RXALIGNMENTERRORS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXALIGNMENTERRORS_PAGE_71_S_RXALIGNMENTERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXALIGNMENTERRORS_PAGE_71_S_RXALIGNMENTERRORS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXALIGNMENTERRORS_PAGE_71_S_RXALIGNMENTERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxFCSErrors
 ***************************************************************************/
/* switch :: PAGE_71_S_RxFCSErrors :: PAGE_71_S_RxFCSErrors_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxFCSErrors_PAGE_71_S_RxFCSErrors_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXFCSERRORS,x)
#define Rd_switch_PAGE_71_S_RxFCSErrors_PAGE_71_S_RxFCSErrors_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXFCSERRORS)
#define SWITCH_PAGE_71_S_RXFCSERRORS_PAGE_71_S_RXFCSERRORS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXFCSERRORS_PAGE_71_S_RXFCSERRORS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXFCSERRORS_PAGE_71_S_RXFCSERRORS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXFCSERRORS_PAGE_71_S_RXFCSERRORS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxGoodOctets
 ***************************************************************************/
/* switch :: PAGE_71_S_RxGoodOctets :: PAGE_71_S_RxGoodOctets_COUNT [63:00] */
#define Wr_switch_PAGE_71_S_RxGoodOctets_PAGE_71_S_RxGoodOctets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXGOODOCTETS,x)
#define Rd_switch_PAGE_71_S_RxGoodOctets_PAGE_71_S_RxGoodOctets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXGOODOCTETS)
#define SWITCH_PAGE_71_S_RXGOODOCTETS_PAGE_71_S_RXGOODOCTETS_COUNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_71_S_RXGOODOCTETS_PAGE_71_S_RXGOODOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXGOODOCTETS_PAGE_71_S_RXGOODOCTETS_COUNT_BITS 64
#define SWITCH_PAGE_71_S_RXGOODOCTETS_PAGE_71_S_RXGOODOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxDropPkts
 ***************************************************************************/
/* switch :: PAGE_71_S_RxDropPkts :: PAGE_71_S_RxDropPkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxDropPkts_PAGE_71_S_RxDropPkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXDROPPKTS,x)
#define Rd_switch_PAGE_71_S_RxDropPkts_PAGE_71_S_RxDropPkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXDROPPKTS)
#define SWITCH_PAGE_71_S_RXDROPPKTS_PAGE_71_S_RXDROPPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXDROPPKTS_PAGE_71_S_RXDROPPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXDROPPKTS_PAGE_71_S_RXDROPPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXDROPPKTS_PAGE_71_S_RXDROPPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxUnicastPkts
 ***************************************************************************/
/* switch :: PAGE_71_S_RxUnicastPkts :: PAGE_71_S_RxUnicastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxUnicastPkts_PAGE_71_S_RxUnicastPkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXUNICASTPKTS,x)
#define Rd_switch_PAGE_71_S_RxUnicastPkts_PAGE_71_S_RxUnicastPkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXUNICASTPKTS)
#define SWITCH_PAGE_71_S_RXUNICASTPKTS_PAGE_71_S_RXUNICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXUNICASTPKTS_PAGE_71_S_RXUNICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXUNICASTPKTS_PAGE_71_S_RXUNICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXUNICASTPKTS_PAGE_71_S_RXUNICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxMulticastPkts
 ***************************************************************************/
/* switch :: PAGE_71_S_RxMulticastPkts :: PAGE_71_S_RxMulticastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxMulticastPkts_PAGE_71_S_RxMulticastPkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXMULTICASTPKTS,x)
#define Rd_switch_PAGE_71_S_RxMulticastPkts_PAGE_71_S_RxMulticastPkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXMULTICASTPKTS)
#define SWITCH_PAGE_71_S_RXMULTICASTPKTS_PAGE_71_S_RXMULTICASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXMULTICASTPKTS_PAGE_71_S_RXMULTICASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXMULTICASTPKTS_PAGE_71_S_RXMULTICASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXMULTICASTPKTS_PAGE_71_S_RXMULTICASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxBroadcastPkts
 ***************************************************************************/
/* switch :: PAGE_71_S_RxBroadcastPkts :: PAGE_71_S_RxBroadcastPkts_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxBroadcastPkts_PAGE_71_S_RxBroadcastPkts_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXBROADCASTPKTS,x)
#define Rd_switch_PAGE_71_S_RxBroadcastPkts_PAGE_71_S_RxBroadcastPkts_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXBROADCASTPKTS)
#define SWITCH_PAGE_71_S_RXBROADCASTPKTS_PAGE_71_S_RXBROADCASTPKTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXBROADCASTPKTS_PAGE_71_S_RXBROADCASTPKTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXBROADCASTPKTS_PAGE_71_S_RXBROADCASTPKTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXBROADCASTPKTS_PAGE_71_S_RXBROADCASTPKTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxSAChanges
 ***************************************************************************/
/* switch :: PAGE_71_S_RxSAChanges :: PAGE_71_S_RxSAChanges_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxSAChanges_PAGE_71_S_RxSAChanges_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXSACHANGES,x)
#define Rd_switch_PAGE_71_S_RxSAChanges_PAGE_71_S_RxSAChanges_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXSACHANGES)
#define SWITCH_PAGE_71_S_RXSACHANGES_PAGE_71_S_RXSACHANGES_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXSACHANGES_PAGE_71_S_RXSACHANGES_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXSACHANGES_PAGE_71_S_RXSACHANGES_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXSACHANGES_PAGE_71_S_RXSACHANGES_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxFragments
 ***************************************************************************/
/* switch :: PAGE_71_S_RxFragments :: PAGE_71_S_RxFragments_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxFragments_PAGE_71_S_RxFragments_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXFRAGMENTS,x)
#define Rd_switch_PAGE_71_S_RxFragments_PAGE_71_S_RxFragments_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXFRAGMENTS)
#define SWITCH_PAGE_71_S_RXFRAGMENTS_PAGE_71_S_RXFRAGMENTS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXFRAGMENTS_PAGE_71_S_RXFRAGMENTS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXFRAGMENTS_PAGE_71_S_RXFRAGMENTS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXFRAGMENTS_PAGE_71_S_RXFRAGMENTS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxJumboPkt
 ***************************************************************************/
/* switch :: PAGE_71_S_RxJumboPkt :: PAGE_71_S_RxJumboPkt_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxJumboPkt_PAGE_71_S_RxJumboPkt_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXJUMBOPKT,x)
#define Rd_switch_PAGE_71_S_RxJumboPkt_PAGE_71_S_RxJumboPkt_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXJUMBOPKT)
#define SWITCH_PAGE_71_S_RXJUMBOPKT_PAGE_71_S_RXJUMBOPKT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXJUMBOPKT_PAGE_71_S_RXJUMBOPKT_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXJUMBOPKT_PAGE_71_S_RXJUMBOPKT_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXJUMBOPKT_PAGE_71_S_RXJUMBOPKT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxSymblErr
 ***************************************************************************/
/* switch :: PAGE_71_S_RxSymblErr :: PAGE_71_S_RxSymblErr_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxSymblErr_PAGE_71_S_RxSymblErr_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXSYMBLERR,x)
#define Rd_switch_PAGE_71_S_RxSymblErr_PAGE_71_S_RxSymblErr_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXSYMBLERR)
#define SWITCH_PAGE_71_S_RXSYMBLERR_PAGE_71_S_RXSYMBLERR_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_RXSYMBLERR_PAGE_71_S_RXSYMBLERR_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXSYMBLERR_PAGE_71_S_RXSYMBLERR_COUNT_BITS 32
#define SWITCH_PAGE_71_S_RXSYMBLERR_PAGE_71_S_RXSYMBLERR_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_InRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_71_S_InRangeErrCount :: PAGE_71_S_InRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_InRangeErrCount_PAGE_71_S_InRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_71_S_INRANGEERRCOUNT,x)
#define Rd_switch_PAGE_71_S_InRangeErrCount_PAGE_71_S_InRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_71_S_INRANGEERRCOUNT)
#define SWITCH_PAGE_71_S_INRANGEERRCOUNT_PAGE_71_S_INRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_INRANGEERRCOUNT_PAGE_71_S_INRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_INRANGEERRCOUNT_PAGE_71_S_INRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_71_S_INRANGEERRCOUNT_PAGE_71_S_INRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_OutRangeErrCount
 ***************************************************************************/
/* switch :: PAGE_71_S_OutRangeErrCount :: PAGE_71_S_OutRangeErrCount_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_OutRangeErrCount_PAGE_71_S_OutRangeErrCount_COUNT(x) WriteReg(SWITCH_PAGE_71_S_OUTRANGEERRCOUNT,x)
#define Rd_switch_PAGE_71_S_OutRangeErrCount_PAGE_71_S_OutRangeErrCount_COUNT(x) ReadReg(SWITCH_PAGE_71_S_OUTRANGEERRCOUNT)
#define SWITCH_PAGE_71_S_OUTRANGEERRCOUNT_PAGE_71_S_OUTRANGEERRCOUNT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_OUTRANGEERRCOUNT_PAGE_71_S_OUTRANGEERRCOUNT_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_OUTRANGEERRCOUNT_PAGE_71_S_OUTRANGEERRCOUNT_COUNT_BITS 32
#define SWITCH_PAGE_71_S_OUTRANGEERRCOUNT_PAGE_71_S_OUTRANGEERRCOUNT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_EEE_LPI_EVENT
 ***************************************************************************/
/* switch :: PAGE_71_S_EEE_LPI_EVENT :: PAGE_71_S_EEE_LPI_EVENT_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_EEE_LPI_EVENT_PAGE_71_S_EEE_LPI_EVENT_COUNT(x) WriteReg(SWITCH_PAGE_71_S_EEE_LPI_EVENT,x)
#define Rd_switch_PAGE_71_S_EEE_LPI_EVENT_PAGE_71_S_EEE_LPI_EVENT_COUNT(x) ReadReg(SWITCH_PAGE_71_S_EEE_LPI_EVENT)
#define SWITCH_PAGE_71_S_EEE_LPI_EVENT_PAGE_71_S_EEE_LPI_EVENT_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_EEE_LPI_EVENT_PAGE_71_S_EEE_LPI_EVENT_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_EEE_LPI_EVENT_PAGE_71_S_EEE_LPI_EVENT_COUNT_BITS 32
#define SWITCH_PAGE_71_S_EEE_LPI_EVENT_PAGE_71_S_EEE_LPI_EVENT_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_EEE_LPI_DURATION
 ***************************************************************************/
/* switch :: PAGE_71_S_EEE_LPI_DURATION :: PAGE_71_S_EEE_LPI_DURATION_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_EEE_LPI_DURATION_PAGE_71_S_EEE_LPI_DURATION_COUNT(x) WriteReg(SWITCH_PAGE_71_S_EEE_LPI_DURATION,x)
#define Rd_switch_PAGE_71_S_EEE_LPI_DURATION_PAGE_71_S_EEE_LPI_DURATION_COUNT(x) ReadReg(SWITCH_PAGE_71_S_EEE_LPI_DURATION)
#define SWITCH_PAGE_71_S_EEE_LPI_DURATION_PAGE_71_S_EEE_LPI_DURATION_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_EEE_LPI_DURATION_PAGE_71_S_EEE_LPI_DURATION_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_EEE_LPI_DURATION_PAGE_71_S_EEE_LPI_DURATION_COUNT_BITS 32
#define SWITCH_PAGE_71_S_EEE_LPI_DURATION_PAGE_71_S_EEE_LPI_DURATION_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_RxDiscard
 ***************************************************************************/
/* switch :: PAGE_71_S_RxDiscard :: PAGE_71_S_RxDiscard_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_RxDiscard_PAGE_71_S_RxDiscard_COUNT(x) WriteReg(SWITCH_PAGE_71_S_RXDISCARD,x)
#define Rd_switch_PAGE_71_S_RxDiscard_PAGE_71_S_RxDiscard_COUNT(x) ReadReg(SWITCH_PAGE_71_S_RXDISCARD)
#define SWITCH_PAGE_71_S_RXDISCARD_PAGE_71_S_RXDISCARD_COUNT_MASK  0xffffffff
#define SWITCH_PAGE_71_S_RXDISCARD_PAGE_71_S_RXDISCARD_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_RXDISCARD_PAGE_71_S_RXDISCARD_COUNT_BITS  32
#define SWITCH_PAGE_71_S_RXDISCARD_PAGE_71_S_RXDISCARD_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxQPKTQ6
 ***************************************************************************/
/* switch :: PAGE_71_S_TxQPKTQ6 :: PAGE_71_S_TxQPKTQ6_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxQPKTQ6_PAGE_71_S_TxQPKTQ6_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXQPKTQ6,x)
#define Rd_switch_PAGE_71_S_TxQPKTQ6_PAGE_71_S_TxQPKTQ6_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXQPKTQ6)
#define SWITCH_PAGE_71_S_TXQPKTQ6_PAGE_71_S_TXQPKTQ6_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_71_S_TXQPKTQ6_PAGE_71_S_TXQPKTQ6_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_TXQPKTQ6_PAGE_71_S_TXQPKTQ6_COUNT_BITS    32
#define SWITCH_PAGE_71_S_TXQPKTQ6_PAGE_71_S_TXQPKTQ6_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_TxQPKTQ7
 ***************************************************************************/
/* switch :: PAGE_71_S_TxQPKTQ7 :: PAGE_71_S_TxQPKTQ7_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxQPKTQ7_PAGE_71_S_TxQPKTQ7_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXQPKTQ7,x)
#define Rd_switch_PAGE_71_S_TxQPKTQ7_PAGE_71_S_TxQPKTQ7_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXQPKTQ7)
#define SWITCH_PAGE_71_S_TXQPKTQ7_PAGE_71_S_TXQPKTQ7_COUNT_MASK    0xffffffff
#define SWITCH_PAGE_71_S_TXQPKTQ7_PAGE_71_S_TXQPKTQ7_COUNT_ALIGN   0
#define SWITCH_PAGE_71_S_TXQPKTQ7_PAGE_71_S_TXQPKTQ7_COUNT_BITS    32
#define SWITCH_PAGE_71_S_TXQPKTQ7_PAGE_71_S_TXQPKTQ7_COUNT_SHIFT   0


/****************************************************************************
 * switch :: PAGE_71_S_TxPkts64Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_TxPkts64Octets :: PAGE_71_S_TxPkts64Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxPkts64Octets_PAGE_71_S_TxPkts64Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXPKTS64OCTETS,x)
#define Rd_switch_PAGE_71_S_TxPkts64Octets_PAGE_71_S_TxPkts64Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXPKTS64OCTETS)
#define SWITCH_PAGE_71_S_TXPKTS64OCTETS_PAGE_71_S_TXPKTS64OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXPKTS64OCTETS_PAGE_71_S_TXPKTS64OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXPKTS64OCTETS_PAGE_71_S_TXPKTS64OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXPKTS64OCTETS_PAGE_71_S_TXPKTS64OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxPkts65to127Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_TxPkts65to127Octets :: PAGE_71_S_TxPkts65to127Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxPkts65to127Octets_PAGE_71_S_TxPkts65to127Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXPKTS65TO127OCTETS,x)
#define Rd_switch_PAGE_71_S_TxPkts65to127Octets_PAGE_71_S_TxPkts65to127Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXPKTS65TO127OCTETS)
#define SWITCH_PAGE_71_S_TXPKTS65TO127OCTETS_PAGE_71_S_TXPKTS65TO127OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXPKTS65TO127OCTETS_PAGE_71_S_TXPKTS65TO127OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXPKTS65TO127OCTETS_PAGE_71_S_TXPKTS65TO127OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXPKTS65TO127OCTETS_PAGE_71_S_TXPKTS65TO127OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxPkts128to255Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_TxPkts128to255Octets :: PAGE_71_S_TxPkts128to255Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxPkts128to255Octets_PAGE_71_S_TxPkts128to255Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXPKTS128TO255OCTETS,x)
#define Rd_switch_PAGE_71_S_TxPkts128to255Octets_PAGE_71_S_TxPkts128to255Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXPKTS128TO255OCTETS)
#define SWITCH_PAGE_71_S_TXPKTS128TO255OCTETS_PAGE_71_S_TXPKTS128TO255OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXPKTS128TO255OCTETS_PAGE_71_S_TXPKTS128TO255OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXPKTS128TO255OCTETS_PAGE_71_S_TXPKTS128TO255OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXPKTS128TO255OCTETS_PAGE_71_S_TXPKTS128TO255OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxPkts256to511Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_TxPkts256to511Octets :: PAGE_71_S_TxPkts256to511Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxPkts256to511Octets_PAGE_71_S_TxPkts256to511Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXPKTS256TO511OCTETS,x)
#define Rd_switch_PAGE_71_S_TxPkts256to511Octets_PAGE_71_S_TxPkts256to511Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXPKTS256TO511OCTETS)
#define SWITCH_PAGE_71_S_TXPKTS256TO511OCTETS_PAGE_71_S_TXPKTS256TO511OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXPKTS256TO511OCTETS_PAGE_71_S_TXPKTS256TO511OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXPKTS256TO511OCTETS_PAGE_71_S_TXPKTS256TO511OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXPKTS256TO511OCTETS_PAGE_71_S_TXPKTS256TO511OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxPkts512to1023Octets
 ***************************************************************************/
/* switch :: PAGE_71_S_TxPkts512to1023Octets :: PAGE_71_S_TxPkts512to1023Octets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxPkts512to1023Octets_PAGE_71_S_TxPkts512to1023Octets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXPKTS512TO1023OCTETS,x)
#define Rd_switch_PAGE_71_S_TxPkts512to1023Octets_PAGE_71_S_TxPkts512to1023Octets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXPKTS512TO1023OCTETS)
#define SWITCH_PAGE_71_S_TXPKTS512TO1023OCTETS_PAGE_71_S_TXPKTS512TO1023OCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXPKTS512TO1023OCTETS_PAGE_71_S_TXPKTS512TO1023OCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXPKTS512TO1023OCTETS_PAGE_71_S_TXPKTS512TO1023OCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXPKTS512TO1023OCTETS_PAGE_71_S_TXPKTS512TO1023OCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_71_S_TxPkts1024toMaxPktOctets
 ***************************************************************************/
/* switch :: PAGE_71_S_TxPkts1024toMaxPktOctets :: PAGE_71_S_TxPkts1024toMaxPktOctets_COUNT [31:00] */
#define Wr_switch_PAGE_71_S_TxPkts1024toMaxPktOctets_PAGE_71_S_TxPkts1024toMaxPktOctets_COUNT(x) WriteReg(SWITCH_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS,x)
#define Rd_switch_PAGE_71_S_TxPkts1024toMaxPktOctets_PAGE_71_S_TxPkts1024toMaxPktOctets_COUNT(x) ReadReg(SWITCH_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS)
#define SWITCH_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS_COUNT_MASK 0xffffffff
#define SWITCH_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS_COUNT_ALIGN 0
#define SWITCH_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS_COUNT_BITS 32
#define SWITCH_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS_PAGE_71_S_TXPKTS1024TOMAXPKTOCTETS_COUNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_72_LPDET_CFG
 ***************************************************************************/
/* switch :: PAGE_72_LPDET_CFG :: PAGE_72_LPDET_CFG_RESERVED [15:15] */
#define Wr_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_RESERVED(x) WriteRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x8000,15,x)
#define Rd_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_RESERVED(x) ReadRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x8000,15)
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_RESERVED_MASK   0x8000
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_RESERVED_ALIGN  0
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_RESERVED_BITS   1
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_RESERVED_SHIFT  15

/* switch :: PAGE_72_LPDET_CFG :: PAGE_72_LPDET_CFG_DFQ_SEL2 [14:14] */
#define Wr_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL2(x) WriteRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x4000,14,x)
#define Rd_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL2(x) ReadRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x4000,14)
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL2_MASK   0x4000
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL2_ALIGN  0
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL2_BITS   1
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL2_SHIFT  14

/* switch :: PAGE_72_LPDET_CFG :: PAGE_72_LPDET_CFG_EN_TXPASS [13:13] */
#define Wr_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_TXPASS(x) WriteRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x2000,13,x)
#define Rd_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_TXPASS(x) ReadRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x2000,13)
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_TXPASS_MASK  0x2000
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_TXPASS_ALIGN 0
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_TXPASS_BITS  1
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_TXPASS_SHIFT 13

/* switch :: PAGE_72_LPDET_CFG :: PAGE_72_LPDET_CFG_EN_LPDET [12:12] */
#define Wr_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_LPDET(x) WriteRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x1000,12,x)
#define Rd_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_LPDET(x) ReadRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x1000,12)
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_LPDET_MASK   0x1000
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_LPDET_ALIGN  0
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_LPDET_BITS   1
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_EN_LPDET_SHIFT  12

/* switch :: PAGE_72_LPDET_CFG :: PAGE_72_LPDET_CFG_LOOP_IMP_SEL [11:11] */
#define Wr_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LOOP_IMP_SEL(x) WriteRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x800,11,x)
#define Rd_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LOOP_IMP_SEL(x) ReadRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x800,11)
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LOOP_IMP_SEL_MASK 0x0800
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LOOP_IMP_SEL_ALIGN 0
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LOOP_IMP_SEL_BITS 1
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LOOP_IMP_SEL_SHIFT 11

/* switch :: PAGE_72_LPDET_CFG :: PAGE_72_LPDET_CFG_LED_RST_CTL [10:03] */
#define Wr_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LED_RST_CTL(x) WriteRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x7f8,3,x)
#define Rd_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LED_RST_CTL(x) ReadRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x7f8,3)
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LED_RST_CTL_MASK 0x07f8
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LED_RST_CTL_ALIGN 0
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LED_RST_CTL_BITS 8
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_LED_RST_CTL_SHIFT 3

/* switch :: PAGE_72_LPDET_CFG :: PAGE_72_LPDET_CFG_OV_PAUSE_ON [02:02] */
#define Wr_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_OV_PAUSE_ON(x) WriteRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x4,2,x)
#define Rd_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_OV_PAUSE_ON(x) ReadRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x4,2)
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_OV_PAUSE_ON_MASK 0x0004
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_OV_PAUSE_ON_ALIGN 0
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_OV_PAUSE_ON_BITS 1
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_OV_PAUSE_ON_SHIFT 2

/* switch :: PAGE_72_LPDET_CFG :: PAGE_72_LPDET_CFG_DFQ_SEL [01:00] */
#define Wr_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL(x) WriteRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x3,0,x)
#define Rd_switch_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL(x) ReadRegBits16(SWITCH_PAGE_72_LPDET_CFG,0x3,0)
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL_MASK    0x0003
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL_ALIGN   0
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL_BITS    2
#define SWITCH_PAGE_72_LPDET_CFG_PAGE_72_LPDET_CFG_DFQ_SEL_SHIFT   0


/****************************************************************************
 * switch :: PAGE_72_DF_TIMER
 ***************************************************************************/
/* switch :: PAGE_72_DF_TIMER :: PAGE_72_DF_TIMER_RESERVED [07:04] */
#define Wr_switch_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_RESERVED(x) WriteRegBits(SWITCH_PAGE_72_DF_TIMER,0xf0,4,x)
#define Rd_switch_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_RESERVED(x) ReadRegBits(SWITCH_PAGE_72_DF_TIMER,0xf0,4)
#define SWITCH_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_RESERVED_MASK     0xf0
#define SWITCH_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_RESERVED_ALIGN    0
#define SWITCH_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_RESERVED_BITS     4
#define SWITCH_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_RESERVED_SHIFT    4

/* switch :: PAGE_72_DF_TIMER :: PAGE_72_DF_TIMER_DF_TIME [03:00] */
#define Wr_switch_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_DF_TIME(x) WriteRegBits(SWITCH_PAGE_72_DF_TIMER,0xf,0,x)
#define Rd_switch_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_DF_TIME(x) ReadRegBits(SWITCH_PAGE_72_DF_TIMER,0xf,0)
#define SWITCH_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_DF_TIME_MASK      0x0f
#define SWITCH_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_DF_TIME_ALIGN     0
#define SWITCH_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_DF_TIME_BITS      4
#define SWITCH_PAGE_72_DF_TIMER_PAGE_72_DF_TIMER_DF_TIME_SHIFT     0


/****************************************************************************
 * switch :: PAGE_72_LED_PORTMAP
 ***************************************************************************/
/* switch :: PAGE_72_LED_PORTMAP :: PAGE_72_LED_PORTMAP_RESERVED [15:09] */
#define Wr_switch_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_RESERVED(x) WriteRegBits16(SWITCH_PAGE_72_LED_PORTMAP,0xfe00,9,x)
#define Rd_switch_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_RESERVED(x) ReadRegBits16(SWITCH_PAGE_72_LED_PORTMAP,0xfe00,9)
#define SWITCH_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_RESERVED_ALIGN 0
#define SWITCH_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_RESERVED_BITS 7
#define SWITCH_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_RESERVED_SHIFT 9

/* switch :: PAGE_72_LED_PORTMAP :: PAGE_72_LED_PORTMAP_LED_WARNING_PORTMAP [08:00] */
#define Wr_switch_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_LED_WARNING_PORTMAP(x) WriteRegBits16(SWITCH_PAGE_72_LED_PORTMAP,0x1ff,0,x)
#define Rd_switch_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_LED_WARNING_PORTMAP(x) ReadRegBits16(SWITCH_PAGE_72_LED_PORTMAP,0x1ff,0)
#define SWITCH_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_LED_WARNING_PORTMAP_MASK 0x01ff
#define SWITCH_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_LED_WARNING_PORTMAP_ALIGN 0
#define SWITCH_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_LED_WARNING_PORTMAP_BITS 9
#define SWITCH_PAGE_72_LED_PORTMAP_PAGE_72_LED_PORTMAP_LED_WARNING_PORTMAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_72_MODULE_ID0
 ***************************************************************************/
/* switch :: PAGE_72_MODULE_ID0 :: reserved0 [63:48] */
#define SWITCH_PAGE_72_MODULE_ID0_RESERVED0_MASK                   0xffff000000000000
#define SWITCH_PAGE_72_MODULE_ID0_RESERVED0_ALIGN                  0
#define SWITCH_PAGE_72_MODULE_ID0_RESERVED0_BITS                   16
#define SWITCH_PAGE_72_MODULE_ID0_RESERVED0_SHIFT                  48

/* switch :: PAGE_72_MODULE_ID0 :: PAGE_72_MODULE_ID0_MID_SA [47:00] */
#define Wr_switch_PAGE_72_MODULE_ID0_PAGE_72_MODULE_ID0_MID_SA(x) WriteRegBits(SWITCH_PAGE_72_MODULE_ID0,0xffffffffffff,0,x)
#define Rd_switch_PAGE_72_MODULE_ID0_PAGE_72_MODULE_ID0_MID_SA(x) ReadRegBits(SWITCH_PAGE_72_MODULE_ID0,0xffffffffffff,0)
#define SWITCH_PAGE_72_MODULE_ID0_PAGE_72_MODULE_ID0_MID_SA_MASK   0x0000ffffffffffff
#define SWITCH_PAGE_72_MODULE_ID0_PAGE_72_MODULE_ID0_MID_SA_ALIGN  0
#define SWITCH_PAGE_72_MODULE_ID0_PAGE_72_MODULE_ID0_MID_SA_BITS   48
#define SWITCH_PAGE_72_MODULE_ID0_PAGE_72_MODULE_ID0_MID_SA_SHIFT  0


/****************************************************************************
 * switch :: PAGE_72_MODULE_ID1
 ***************************************************************************/
/* switch :: PAGE_72_MODULE_ID1 :: reserved0 [63:48] */
#define SWITCH_PAGE_72_MODULE_ID1_RESERVED0_MASK                   0xffff000000000000
#define SWITCH_PAGE_72_MODULE_ID1_RESERVED0_ALIGN                  0
#define SWITCH_PAGE_72_MODULE_ID1_RESERVED0_BITS                   16
#define SWITCH_PAGE_72_MODULE_ID1_RESERVED0_SHIFT                  48

/* switch :: PAGE_72_MODULE_ID1 :: PAGE_72_MODULE_ID1_MID_AVAIL [47:47] */
#define Wr_switch_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_AVAIL(x) WriteRegBits(SWITCH_PAGE_72_MODULE_ID1,0x800000000000,47,x)
#define Rd_switch_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_AVAIL(x) ReadRegBits(SWITCH_PAGE_72_MODULE_ID1,0x800000000000,47)
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_AVAIL_MASK 0x0000800000000000
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_AVAIL_ALIGN 0
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_AVAIL_BITS 1
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_AVAIL_SHIFT 47

/* switch :: PAGE_72_MODULE_ID1 :: PAGE_72_MODULE_ID1_RESERVED [46:40] */
#define Wr_switch_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_RESERVED(x) WriteRegBits(SWITCH_PAGE_72_MODULE_ID1,0x7f0000000000,40,x)
#define Rd_switch_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_RESERVED(x) ReadRegBits(SWITCH_PAGE_72_MODULE_ID1,0x7f0000000000,40)
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_RESERVED_MASK 0x00007f0000000000
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_RESERVED_ALIGN 0
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_RESERVED_BITS 7
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_RESERVED_SHIFT 40

/* switch :: PAGE_72_MODULE_ID1 :: PAGE_72_MODULE_ID1_MID_PORTNUM [39:32] */
#define Wr_switch_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_PORTNUM(x) WriteRegBits(SWITCH_PAGE_72_MODULE_ID1,0xff00000000,32,x)
#define Rd_switch_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_PORTNUM(x) ReadRegBits(SWITCH_PAGE_72_MODULE_ID1,0xff00000000,32)
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_PORTNUM_MASK 0x000000ff00000000
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_PORTNUM_ALIGN 0
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_PORTNUM_BITS 8
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_PORTNUM_SHIFT 32

/* switch :: PAGE_72_MODULE_ID1 :: PAGE_72_MODULE_ID1_MID_CRC [31:00] */
#define Wr_switch_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_CRC(x) WriteRegBits(SWITCH_PAGE_72_MODULE_ID1,0xffffffff,0,x)
#define Rd_switch_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_CRC(x) ReadRegBits(SWITCH_PAGE_72_MODULE_ID1,0xffffffff,0)
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_CRC_MASK  0x00000000ffffffff
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_CRC_ALIGN 0
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_CRC_BITS  32
#define SWITCH_PAGE_72_MODULE_ID1_PAGE_72_MODULE_ID1_MID_CRC_SHIFT 0


/****************************************************************************
 * switch :: PAGE_72_LPDET_SA
 ***************************************************************************/
/* switch :: PAGE_72_LPDET_SA :: reserved0 [63:48] */
#define SWITCH_PAGE_72_LPDET_SA_RESERVED0_MASK                     0xffff000000000000
#define SWITCH_PAGE_72_LPDET_SA_RESERVED0_ALIGN                    0
#define SWITCH_PAGE_72_LPDET_SA_RESERVED0_BITS                     16
#define SWITCH_PAGE_72_LPDET_SA_RESERVED0_SHIFT                    48

/* switch :: PAGE_72_LPDET_SA :: PAGE_72_LPDET_SA_LPDET_SA [47:00] */
#define Wr_switch_PAGE_72_LPDET_SA_PAGE_72_LPDET_SA_LPDET_SA(x) WriteRegBits(SWITCH_PAGE_72_LPDET_SA,0xffffffffffff,0,x)
#define Rd_switch_PAGE_72_LPDET_SA_PAGE_72_LPDET_SA_LPDET_SA(x) ReadRegBits(SWITCH_PAGE_72_LPDET_SA,0xffffffffffff,0)
#define SWITCH_PAGE_72_LPDET_SA_PAGE_72_LPDET_SA_LPDET_SA_MASK     0x0000ffffffffffff
#define SWITCH_PAGE_72_LPDET_SA_PAGE_72_LPDET_SA_LPDET_SA_ALIGN    0
#define SWITCH_PAGE_72_LPDET_SA_PAGE_72_LPDET_SA_LPDET_SA_BITS     48
#define SWITCH_PAGE_72_LPDET_SA_PAGE_72_LPDET_SA_LPDET_SA_SHIFT    0


/****************************************************************************
 * switch :: PAGE_72_LPDET_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_72_LPDET_REG_SPARE0 :: PAGE_72_LPDET_REG_SPARE0_LPDET_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_72_LPDET_REG_SPARE0_PAGE_72_LPDET_REG_SPARE0_LPDET_REG_SPARE0(x) WriteReg(SWITCH_PAGE_72_LPDET_REG_SPARE0,x)
#define Rd_switch_PAGE_72_LPDET_REG_SPARE0_PAGE_72_LPDET_REG_SPARE0_LPDET_REG_SPARE0(x) ReadReg(SWITCH_PAGE_72_LPDET_REG_SPARE0)
#define SWITCH_PAGE_72_LPDET_REG_SPARE0_PAGE_72_LPDET_REG_SPARE0_LPDET_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_72_LPDET_REG_SPARE0_PAGE_72_LPDET_REG_SPARE0_LPDET_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_72_LPDET_REG_SPARE0_PAGE_72_LPDET_REG_SPARE0_LPDET_REG_SPARE0_BITS 32
#define SWITCH_PAGE_72_LPDET_REG_SPARE0_PAGE_72_LPDET_REG_SPARE0_LPDET_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_72_LPDET_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_72_LPDET_REG_SPARE1 :: PAGE_72_LPDET_REG_SPARE1_LPDET_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_72_LPDET_REG_SPARE1_PAGE_72_LPDET_REG_SPARE1_LPDET_REG_SPARE1(x) WriteReg(SWITCH_PAGE_72_LPDET_REG_SPARE1,x)
#define Rd_switch_PAGE_72_LPDET_REG_SPARE1_PAGE_72_LPDET_REG_SPARE1_LPDET_REG_SPARE1(x) ReadReg(SWITCH_PAGE_72_LPDET_REG_SPARE1)
#define SWITCH_PAGE_72_LPDET_REG_SPARE1_PAGE_72_LPDET_REG_SPARE1_LPDET_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_72_LPDET_REG_SPARE1_PAGE_72_LPDET_REG_SPARE1_LPDET_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_72_LPDET_REG_SPARE1_PAGE_72_LPDET_REG_SPARE1_LPDET_REG_SPARE1_BITS 32
#define SWITCH_PAGE_72_LPDET_REG_SPARE1_PAGE_72_LPDET_REG_SPARE1_LPDET_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_BPM_CTRL
 ***************************************************************************/
/* switch :: PAGE_73_BPM_CTRL :: PAGE_73_BPM_CTRL_RESERVED [07:05] */
#define Wr_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_73_BPM_CTRL,0xe0,5,x)
#define Rd_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_73_BPM_CTRL,0xe0,5)
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RESERVED_MASK     0xe0
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RESERVED_ALIGN    0
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RESERVED_BITS     3
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RESERVED_SHIFT    5

/* switch :: PAGE_73_BPM_CTRL :: PAGE_73_BPM_CTRL_RX_PORT_KEEP2PAGE [04:04] */
#define Wr_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RX_PORT_KEEP2PAGE(x) WriteRegBits(SWITCH_PAGE_73_BPM_CTRL,0x10,4,x)
#define Rd_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RX_PORT_KEEP2PAGE(x) ReadRegBits(SWITCH_PAGE_73_BPM_CTRL,0x10,4)
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RX_PORT_KEEP2PAGE_MASK 0x10
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RX_PORT_KEEP2PAGE_ALIGN 0
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RX_PORT_KEEP2PAGE_BITS 1
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_RX_PORT_KEEP2PAGE_SHIFT 4

/* switch :: PAGE_73_BPM_CTRL :: PAGE_73_BPM_CTRL_PDA_CHG_OPT [03:03] */
#define Wr_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PDA_CHG_OPT(x) WriteRegBits(SWITCH_PAGE_73_BPM_CTRL,0x8,3,x)
#define Rd_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PDA_CHG_OPT(x) ReadRegBits(SWITCH_PAGE_73_BPM_CTRL,0x8,3)
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PDA_CHG_OPT_MASK  0x08
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PDA_CHG_OPT_ALIGN 0
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PDA_CHG_OPT_BITS  1
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PDA_CHG_OPT_SHIFT 3

/* switch :: PAGE_73_BPM_CTRL :: PAGE_73_BPM_CTRL_BFCFIFO_RECYCLE_EN [02:02] */
#define Wr_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_BFCFIFO_RECYCLE_EN(x) WriteRegBits(SWITCH_PAGE_73_BPM_CTRL,0x4,2,x)
#define Rd_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_BFCFIFO_RECYCLE_EN(x) ReadRegBits(SWITCH_PAGE_73_BPM_CTRL,0x4,2)
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_BFCFIFO_RECYCLE_EN_MASK 0x04
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_BFCFIFO_RECYCLE_EN_ALIGN 0
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_BFCFIFO_RECYCLE_EN_BITS 1
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_BFCFIFO_RECYCLE_EN_SHIFT 2

/* switch :: PAGE_73_BPM_CTRL :: PAGE_73_BPM_CTRL_PTR_RECYCLE_EN [01:01] */
#define Wr_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PTR_RECYCLE_EN(x) WriteRegBits(SWITCH_PAGE_73_BPM_CTRL,0x2,1,x)
#define Rd_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PTR_RECYCLE_EN(x) ReadRegBits(SWITCH_PAGE_73_BPM_CTRL,0x2,1)
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PTR_RECYCLE_EN_MASK 0x02
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PTR_RECYCLE_EN_ALIGN 0
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PTR_RECYCLE_EN_BITS 1
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PTR_RECYCLE_EN_SHIFT 1

/* switch :: PAGE_73_BPM_CTRL :: PAGE_73_BPM_CTRL_PSM_SW_EN [00:00] */
#define Wr_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PSM_SW_EN(x) WriteRegBits(SWITCH_PAGE_73_BPM_CTRL,0x1,0,x)
#define Rd_switch_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PSM_SW_EN(x) ReadRegBits(SWITCH_PAGE_73_BPM_CTRL,0x1,0)
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PSM_SW_EN_MASK    0x01
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PSM_SW_EN_ALIGN   0
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PSM_SW_EN_BITS    1
#define SWITCH_PAGE_73_BPM_CTRL_PAGE_73_BPM_CTRL_PSM_SW_EN_SHIFT   0


/****************************************************************************
 * switch :: PAGE_73_BPM_PSM_OVR_CTRL
 ***************************************************************************/
/* switch :: PAGE_73_BPM_PSM_OVR_CTRL :: PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN [07:07] */
#define Wr_switch_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN(x) WriteRegBits(SWITCH_PAGE_73_BPM_PSM_OVR_CTRL,0x80,7,x)
#define Rd_switch_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN(x) ReadRegBits(SWITCH_PAGE_73_BPM_PSM_OVR_CTRL,0x80,7)
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_MASK 0x80
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_ALIGN 0
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_BITS 1
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_EN_SHIFT 7

/* switch :: PAGE_73_BPM_PSM_OVR_CTRL :: PAGE_73_BPM_PSM_OVR_CTRL_RESERVED [06:03] */
#define Wr_switch_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_73_BPM_PSM_OVR_CTRL,0x78,3,x)
#define Rd_switch_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_73_BPM_PSM_OVR_CTRL,0x78,3)
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_RESERVED_MASK 0x78
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_RESERVED_BITS 4
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_RESERVED_SHIFT 3

/* switch :: PAGE_73_BPM_PSM_OVR_CTRL :: PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE [02:00] */
#define Wr_switch_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE(x) WriteRegBits(SWITCH_PAGE_73_BPM_PSM_OVR_CTRL,0x7,0,x)
#define Rd_switch_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE(x) ReadRegBits(SWITCH_PAGE_73_BPM_PSM_OVR_CTRL,0x7,0)
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_MASK 0x07
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_ALIGN 0
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_BITS 3
#define SWITCH_PAGE_73_BPM_PSM_OVR_CTRL_PAGE_73_BPM_PSM_OVR_CTRL_PSM_SW_OVERRIDE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_BPM_PSM_TIME_CFG
 ***************************************************************************/
/* switch :: PAGE_73_BPM_PSM_TIME_CFG :: PAGE_73_BPM_PSM_TIME_CFG_DPSM_CNT [15:08] */
#define Wr_switch_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_DPSM_CNT(x) WriteRegBits16(SWITCH_PAGE_73_BPM_PSM_TIME_CFG,0xff00,8,x)
#define Rd_switch_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_DPSM_CNT(x) ReadRegBits16(SWITCH_PAGE_73_BPM_PSM_TIME_CFG,0xff00,8)
#define SWITCH_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_DPSM_CNT_MASK 0xff00
#define SWITCH_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_DPSM_CNT_ALIGN 0
#define SWITCH_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_DPSM_CNT_BITS 8
#define SWITCH_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_DPSM_CNT_SHIFT 8

/* switch :: PAGE_73_BPM_PSM_TIME_CFG :: PAGE_73_BPM_PSM_TIME_CFG_MPSM_CNT [07:00] */
#define Wr_switch_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_MPSM_CNT(x) WriteRegBits16(SWITCH_PAGE_73_BPM_PSM_TIME_CFG,0xff,0,x)
#define Rd_switch_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_MPSM_CNT(x) ReadRegBits16(SWITCH_PAGE_73_BPM_PSM_TIME_CFG,0xff,0)
#define SWITCH_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_MPSM_CNT_MASK 0x00ff
#define SWITCH_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_MPSM_CNT_ALIGN 0
#define SWITCH_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_MPSM_CNT_BITS 8
#define SWITCH_PAGE_73_BPM_PSM_TIME_CFG_PAGE_73_BPM_PSM_TIME_CFG_MPSM_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_BPM_PSM_THD_CFG
 ***************************************************************************/
/* switch :: PAGE_73_BPM_PSM_THD_CFG :: PAGE_73_BPM_PSM_THD_CFG_RESERVED_1 [31:28] */
#define Wr_switch_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_73_BPM_PSM_THD_CFG,0xf0000000,28,x)
#define Rd_switch_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_73_BPM_PSM_THD_CFG,0xf0000000,28)
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_1_MASK 0xf0000000
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_1_BITS 4
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_1_SHIFT 28

/* switch :: PAGE_73_BPM_PSM_THD_CFG :: PAGE_73_BPM_PSM_THD_CFG_PSM_ON_THD [27:16] */
#define Wr_switch_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_ON_THD(x) WriteRegBits(SWITCH_PAGE_73_BPM_PSM_THD_CFG,0xfff0000,16,x)
#define Rd_switch_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_ON_THD(x) ReadRegBits(SWITCH_PAGE_73_BPM_PSM_THD_CFG,0xfff0000,16)
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_ON_THD_MASK 0x0fff0000
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_ON_THD_ALIGN 0
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_ON_THD_BITS 12
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_ON_THD_SHIFT 16

/* switch :: PAGE_73_BPM_PSM_THD_CFG :: PAGE_73_BPM_PSM_THD_CFG_RESERVED_0 [15:12] */
#define Wr_switch_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_73_BPM_PSM_THD_CFG,0xf000,12,x)
#define Rd_switch_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_73_BPM_PSM_THD_CFG,0xf000,12)
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_0_MASK 0x0000f000
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_0_BITS 4
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_RESERVED_0_SHIFT 12

/* switch :: PAGE_73_BPM_PSM_THD_CFG :: PAGE_73_BPM_PSM_THD_CFG_PSM_OFF_THD [11:00] */
#define Wr_switch_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_OFF_THD(x) WriteRegBits(SWITCH_PAGE_73_BPM_PSM_THD_CFG,0xfff,0,x)
#define Rd_switch_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_OFF_THD(x) ReadRegBits(SWITCH_PAGE_73_BPM_PSM_THD_CFG,0xfff,0)
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_OFF_THD_MASK 0x00000fff
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_OFF_THD_ALIGN 0
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_OFF_THD_BITS 12
#define SWITCH_PAGE_73_BPM_PSM_THD_CFG_PAGE_73_BPM_PSM_THD_CFG_PSM_OFF_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_ROW_VMASK_OVR_CTRL
 ***************************************************************************/
/* switch :: PAGE_73_ROW_VMASK_OVR_CTRL :: PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_EN [15:15] */
#define Wr_switch_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_EN(x) WriteRegBits16(SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL,0x8000,15,x)
#define Rd_switch_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_EN(x) ReadRegBits16(SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL,0x8000,15)
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_MASK 0x8000
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_ALIGN 0
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_BITS 1
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_EN_SHIFT 15

/* switch :: PAGE_73_ROW_VMASK_OVR_CTRL :: PAGE_73_ROW_VMASK_OVR_CTRL_RESERVED [14:12] */
#define Wr_switch_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL,0x7000,12,x)
#define Rd_switch_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL,0x7000,12)
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_RESERVED_MASK 0x7000
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_RESERVED_BITS 3
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_RESERVED_SHIFT 12

/* switch :: PAGE_73_ROW_VMASK_OVR_CTRL :: PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL [11:00] */
#define Wr_switch_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL(x) WriteRegBits16(SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL,0xfff,0,x)
#define Rd_switch_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL(x) ReadRegBits16(SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL,0xfff,0)
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_MASK 0x0fff
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_ALIGN 0
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_BITS 12
#define SWITCH_PAGE_73_ROW_VMASK_OVR_CTRL_PAGE_73_ROW_VMASK_OVR_CTRL_OVERRIDE_VAL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_BPM_STS
 ***************************************************************************/
/* switch :: PAGE_73_BPM_STS :: PAGE_73_BPM_STS_PBB_PWR_STS [31:29] */
#define Wr_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_PBB_PWR_STS(x) WriteRegBits(SWITCH_PAGE_73_BPM_STS,0xe0000000,29,x)
#define Rd_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_PBB_PWR_STS(x) ReadRegBits(SWITCH_PAGE_73_BPM_STS,0xe0000000,29)
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_PBB_PWR_STS_MASK    0xe0000000
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_PBB_PWR_STS_ALIGN   0
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_PBB_PWR_STS_BITS    3
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_PBB_PWR_STS_SHIFT   29

/* switch :: PAGE_73_BPM_STS :: PAGE_73_BPM_STS_RESERVED_1 [28:28] */
#define Wr_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_73_BPM_STS,0x10000000,28,x)
#define Rd_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_73_BPM_STS,0x10000000,28)
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_1_MASK     0x10000000
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_1_ALIGN    0
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_1_BITS     1
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_1_SHIFT    28

/* switch :: PAGE_73_BPM_STS :: PAGE_73_BPM_STS_ROW_USE_STS [27:16] */
#define Wr_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_USE_STS(x) WriteRegBits(SWITCH_PAGE_73_BPM_STS,0xfff0000,16,x)
#define Rd_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_USE_STS(x) ReadRegBits(SWITCH_PAGE_73_BPM_STS,0xfff0000,16)
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_USE_STS_MASK    0x0fff0000
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_USE_STS_ALIGN   0
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_USE_STS_BITS    12
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_USE_STS_SHIFT   16

/* switch :: PAGE_73_BPM_STS :: PAGE_73_BPM_STS_RESERVED_0 [15:14] */
#define Wr_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_73_BPM_STS,0xc000,14,x)
#define Rd_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_73_BPM_STS,0xc000,14)
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_0_MASK     0x0000c000
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_0_ALIGN    0
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_0_BITS     2
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_RESERVED_0_SHIFT    14

/* switch :: PAGE_73_BPM_STS :: PAGE_73_BPM_STS_CUR_PBB [13:12] */
#define Wr_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_CUR_PBB(x) WriteRegBits(SWITCH_PAGE_73_BPM_STS,0x3000,12,x)
#define Rd_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_CUR_PBB(x) ReadRegBits(SWITCH_PAGE_73_BPM_STS,0x3000,12)
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_CUR_PBB_MASK        0x00003000
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_CUR_PBB_ALIGN       0
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_CUR_PBB_BITS        2
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_CUR_PBB_SHIFT       12

/* switch :: PAGE_73_BPM_STS :: PAGE_73_BPM_STS_ROW_VMASK [11:00] */
#define Wr_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_VMASK(x) WriteRegBits(SWITCH_PAGE_73_BPM_STS,0xfff,0,x)
#define Rd_switch_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_VMASK(x) ReadRegBits(SWITCH_PAGE_73_BPM_STS,0xfff,0)
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_VMASK_MASK      0x00000fff
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_VMASK_ALIGN     0
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_VMASK_BITS      12
#define SWITCH_PAGE_73_BPM_STS_PAGE_73_BPM_STS_ROW_VMASK_SHIFT     0


/****************************************************************************
 * switch :: PAGE_73_BPM_PDA_OVR_CTRL
 ***************************************************************************/
/* switch :: PAGE_73_BPM_PDA_OVR_CTRL :: PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_EN [15:15] */
#define Wr_switch_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_EN(x) WriteRegBits16(SWITCH_PAGE_73_BPM_PDA_OVR_CTRL,0x8000,15,x)
#define Rd_switch_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_EN(x) ReadRegBits16(SWITCH_PAGE_73_BPM_PDA_OVR_CTRL,0x8000,15)
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_EN_MASK 0x8000
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_EN_ALIGN 0
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_EN_BITS 1
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_EN_SHIFT 15

/* switch :: PAGE_73_BPM_PDA_OVR_CTRL :: PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_DONE [14:14] */
#define Wr_switch_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_DONE(x) WriteRegBits16(SWITCH_PAGE_73_BPM_PDA_OVR_CTRL,0x4000,14,x)
#define Rd_switch_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_DONE(x) ReadRegBits16(SWITCH_PAGE_73_BPM_PDA_OVR_CTRL,0x4000,14)
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_MASK 0x4000
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_ALIGN 0
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_BITS 1
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_DONE_SHIFT 14

/* switch :: PAGE_73_BPM_PDA_OVR_CTRL :: PAGE_73_BPM_PDA_OVR_CTRL_RESERVED [13:12] */
#define Wr_switch_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_73_BPM_PDA_OVR_CTRL,0x3000,12,x)
#define Rd_switch_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_73_BPM_PDA_OVR_CTRL,0x3000,12)
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_RESERVED_MASK 0x3000
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_RESERVED_BITS 2
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_RESERVED_SHIFT 12

/* switch :: PAGE_73_BPM_PDA_OVR_CTRL :: PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_VAL [11:00] */
#define Wr_switch_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_VAL(x) WriteRegBits16(SWITCH_PAGE_73_BPM_PDA_OVR_CTRL,0xfff,0,x)
#define Rd_switch_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_VAL(x) ReadRegBits16(SWITCH_PAGE_73_BPM_PDA_OVR_CTRL,0xfff,0)
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_MASK 0x0fff
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_ALIGN 0
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_BITS 12
#define SWITCH_PAGE_73_BPM_PDA_OVR_CTRL_PAGE_73_BPM_PDA_OVR_CTRL_OVERRIDE_VAL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PDA_TIMEOUT_CFG
 ***************************************************************************/
/* switch :: PAGE_73_PDA_TIMEOUT_CFG :: PAGE_73_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT [15:00] */
#define Wr_switch_PAGE_73_PDA_TIMEOUT_CFG_PAGE_73_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT(x) WriteReg16(SWITCH_PAGE_73_PDA_TIMEOUT_CFG,x)
#define Rd_switch_PAGE_73_PDA_TIMEOUT_CFG_PAGE_73_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT(x) ReadReg16(SWITCH_PAGE_73_PDA_TIMEOUT_CFG)
#define SWITCH_PAGE_73_PDA_TIMEOUT_CFG_PAGE_73_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_MASK 0xffff
#define SWITCH_PAGE_73_PDA_TIMEOUT_CFG_PAGE_73_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_ALIGN 0
#define SWITCH_PAGE_73_PDA_TIMEOUT_CFG_PAGE_73_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_BITS 16
#define SWITCH_PAGE_73_PDA_TIMEOUT_CFG_PAGE_73_PDA_TIMEOUT_CFG_PDA_TIMEOUT_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PDA_SETUP_TIME_CFG
 ***************************************************************************/
/* switch :: PAGE_73_PDA_SETUP_TIME_CFG :: PAGE_73_PDA_SETUP_TIME_CFG_RESERVED [15:11] */
#define Wr_switch_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_RESERVED(x) WriteRegBits16(SWITCH_PAGE_73_PDA_SETUP_TIME_CFG,0xf800,11,x)
#define Rd_switch_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_RESERVED(x) ReadRegBits16(SWITCH_PAGE_73_PDA_SETUP_TIME_CFG,0xf800,11)
#define SWITCH_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_RESERVED_MASK 0xf800
#define SWITCH_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_RESERVED_ALIGN 0
#define SWITCH_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_RESERVED_BITS 5
#define SWITCH_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_RESERVED_SHIFT 11

/* switch :: PAGE_73_PDA_SETUP_TIME_CFG :: PAGE_73_PDA_SETUP_TIME_CFG_SETUP_TIME [10:00] */
#define Wr_switch_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_SETUP_TIME(x) WriteRegBits16(SWITCH_PAGE_73_PDA_SETUP_TIME_CFG,0x7ff,0,x)
#define Rd_switch_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_SETUP_TIME(x) ReadRegBits16(SWITCH_PAGE_73_PDA_SETUP_TIME_CFG,0x7ff,0)
#define SWITCH_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_SETUP_TIME_MASK 0x07ff
#define SWITCH_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_SETUP_TIME_ALIGN 0
#define SWITCH_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_SETUP_TIME_BITS 11
#define SWITCH_PAGE_73_PDA_SETUP_TIME_CFG_PAGE_73_PDA_SETUP_TIME_CFG_SETUP_TIME_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PDA_HOLD_TIME_CFG
 ***************************************************************************/
/* switch :: PAGE_73_PDA_HOLD_TIME_CFG :: PAGE_73_PDA_HOLD_TIME_CFG_RESERVED [15:11] */
#define Wr_switch_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_RESERVED(x) WriteRegBits16(SWITCH_PAGE_73_PDA_HOLD_TIME_CFG,0xf800,11,x)
#define Rd_switch_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_RESERVED(x) ReadRegBits16(SWITCH_PAGE_73_PDA_HOLD_TIME_CFG,0xf800,11)
#define SWITCH_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_RESERVED_MASK 0xf800
#define SWITCH_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_RESERVED_ALIGN 0
#define SWITCH_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_RESERVED_BITS 5
#define SWITCH_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_RESERVED_SHIFT 11

/* switch :: PAGE_73_PDA_HOLD_TIME_CFG :: PAGE_73_PDA_HOLD_TIME_CFG_HOLD_TIME [10:00] */
#define Wr_switch_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_HOLD_TIME(x) WriteRegBits16(SWITCH_PAGE_73_PDA_HOLD_TIME_CFG,0x7ff,0,x)
#define Rd_switch_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_HOLD_TIME(x) ReadRegBits16(SWITCH_PAGE_73_PDA_HOLD_TIME_CFG,0x7ff,0)
#define SWITCH_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_HOLD_TIME_MASK 0x07ff
#define SWITCH_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_HOLD_TIME_ALIGN 0
#define SWITCH_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_HOLD_TIME_BITS 11
#define SWITCH_PAGE_73_PDA_HOLD_TIME_CFG_PAGE_73_PDA_HOLD_TIME_CFG_HOLD_TIME_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PBB_VBUFCNT_0
 ***************************************************************************/
/* switch :: PAGE_73_PBB_VBUFCNT_0 :: PAGE_73_PBB_VBUFCNT_0_RESERVED [15:10] */
#define Wr_switch_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_0,0xfc00,10,x)
#define Rd_switch_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_0,0xfc00,10)
#define SWITCH_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_RESERVED_MASK 0xfc00
#define SWITCH_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_RESERVED_ALIGN 0
#define SWITCH_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_RESERVED_BITS 6
#define SWITCH_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_RESERVED_SHIFT 10

/* switch :: PAGE_73_PBB_VBUFCNT_0 :: PAGE_73_PBB_VBUFCNT_0_VALID_BUF_CNT [09:00] */
#define Wr_switch_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_VALID_BUF_CNT(x) WriteRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_0,0x3ff,0,x)
#define Rd_switch_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_VALID_BUF_CNT(x) ReadRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_0,0x3ff,0)
#define SWITCH_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_VALID_BUF_CNT_MASK 0x03ff
#define SWITCH_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_VALID_BUF_CNT_ALIGN 0
#define SWITCH_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_VALID_BUF_CNT_BITS 10
#define SWITCH_PAGE_73_PBB_VBUFCNT_0_PAGE_73_PBB_VBUFCNT_0_VALID_BUF_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PBB_VBUFCNT_1
 ***************************************************************************/
/* switch :: PAGE_73_PBB_VBUFCNT_1 :: PAGE_73_PBB_VBUFCNT_1_RESERVED [15:10] */
#define Wr_switch_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_1,0xfc00,10,x)
#define Rd_switch_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_1,0xfc00,10)
#define SWITCH_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_RESERVED_MASK 0xfc00
#define SWITCH_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_RESERVED_ALIGN 0
#define SWITCH_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_RESERVED_BITS 6
#define SWITCH_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_RESERVED_SHIFT 10

/* switch :: PAGE_73_PBB_VBUFCNT_1 :: PAGE_73_PBB_VBUFCNT_1_VALID_BUF_CNT [09:00] */
#define Wr_switch_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_VALID_BUF_CNT(x) WriteRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_1,0x3ff,0,x)
#define Rd_switch_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_VALID_BUF_CNT(x) ReadRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_1,0x3ff,0)
#define SWITCH_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_VALID_BUF_CNT_MASK 0x03ff
#define SWITCH_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_VALID_BUF_CNT_ALIGN 0
#define SWITCH_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_VALID_BUF_CNT_BITS 10
#define SWITCH_PAGE_73_PBB_VBUFCNT_1_PAGE_73_PBB_VBUFCNT_1_VALID_BUF_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PBB_VBUFCNT_2
 ***************************************************************************/
/* switch :: PAGE_73_PBB_VBUFCNT_2 :: PAGE_73_PBB_VBUFCNT_2_RESERVED [15:10] */
#define Wr_switch_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_2,0xfc00,10,x)
#define Rd_switch_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_2,0xfc00,10)
#define SWITCH_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_RESERVED_MASK 0xfc00
#define SWITCH_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_RESERVED_ALIGN 0
#define SWITCH_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_RESERVED_BITS 6
#define SWITCH_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_RESERVED_SHIFT 10

/* switch :: PAGE_73_PBB_VBUFCNT_2 :: PAGE_73_PBB_VBUFCNT_2_VALID_BUF_CNT [09:00] */
#define Wr_switch_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_VALID_BUF_CNT(x) WriteRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_2,0x3ff,0,x)
#define Rd_switch_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_VALID_BUF_CNT(x) ReadRegBits16(SWITCH_PAGE_73_PBB_VBUFCNT_2,0x3ff,0)
#define SWITCH_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_VALID_BUF_CNT_MASK 0x03ff
#define SWITCH_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_VALID_BUF_CNT_ALIGN 0
#define SWITCH_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_VALID_BUF_CNT_BITS 10
#define SWITCH_PAGE_73_PBB_VBUFCNT_2_PAGE_73_PBB_VBUFCNT_2_VALID_BUF_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_RCY_TIME_CFG
 ***************************************************************************/
/* switch :: PAGE_73_RCY_TIME_CFG :: PAGE_73_RCY_TIME_CFG_CHK_TIME [15:00] */
#define Wr_switch_PAGE_73_RCY_TIME_CFG_PAGE_73_RCY_TIME_CFG_CHK_TIME(x) WriteReg16(SWITCH_PAGE_73_RCY_TIME_CFG,x)
#define Rd_switch_PAGE_73_RCY_TIME_CFG_PAGE_73_RCY_TIME_CFG_CHK_TIME(x) ReadReg16(SWITCH_PAGE_73_RCY_TIME_CFG)
#define SWITCH_PAGE_73_RCY_TIME_CFG_PAGE_73_RCY_TIME_CFG_CHK_TIME_MASK 0xffff
#define SWITCH_PAGE_73_RCY_TIME_CFG_PAGE_73_RCY_TIME_CFG_CHK_TIME_ALIGN 0
#define SWITCH_PAGE_73_RCY_TIME_CFG_PAGE_73_RCY_TIME_CFG_CHK_TIME_BITS 16
#define SWITCH_PAGE_73_RCY_TIME_CFG_PAGE_73_RCY_TIME_CFG_CHK_TIME_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PBB_PWRDWN_MON_CTRL
 ***************************************************************************/
/* switch :: PAGE_73_PBB_PWRDWN_MON_CTRL :: PAGE_73_PBB_PWRDWN_MON_CTRL_MON_PERIOD [15:08] */
#define Wr_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_PERIOD(x) WriteRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0xff00,8,x)
#define Rd_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_PERIOD(x) ReadRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0xff00,8)
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_PERIOD_MASK 0xff00
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_PERIOD_ALIGN 0
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_PERIOD_BITS 8
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_PERIOD_SHIFT 8

/* switch :: PAGE_73_PBB_PWRDWN_MON_CTRL :: PAGE_73_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT [07:03] */
#define Wr_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT(x) WriteRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0xf8,3,x)
#define Rd_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT(x) ReadRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0xf8,3)
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_MASK 0x00f8
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_ALIGN 0
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_BITS 5
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_TIME_UNIT_SHIFT 3

/* switch :: PAGE_73_PBB_PWRDWN_MON_CTRL :: PAGE_73_PBB_PWRDWN_MON_CTRL_MON_DONE [02:02] */
#define Wr_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_DONE(x) WriteRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0x4,2,x)
#define Rd_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_DONE(x) ReadRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0x4,2)
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_DONE_MASK 0x0004
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_DONE_ALIGN 0
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_DONE_BITS 1
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_DONE_SHIFT 2

/* switch :: PAGE_73_PBB_PWRDWN_MON_CTRL :: PAGE_73_PBB_PWRDWN_MON_CTRL_MON_CLR [01:01] */
#define Wr_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_CLR(x) WriteRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0x2,1,x)
#define Rd_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_CLR(x) ReadRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0x2,1)
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_CLR_MASK 0x0002
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_CLR_ALIGN 0
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_CLR_BITS 1
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_CLR_SHIFT 1

/* switch :: PAGE_73_PBB_PWRDWN_MON_CTRL :: PAGE_73_PBB_PWRDWN_MON_CTRL_MON_EN [00:00] */
#define Wr_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_EN(x) WriteRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0x1,0,x)
#define Rd_switch_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_EN(x) ReadRegBits16(SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL,0x1,0)
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_EN_MASK 0x0001
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_EN_ALIGN 0
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_EN_BITS 1
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_CTRL_PAGE_73_PBB_PWRDWN_MON_CTRL_MON_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PBB_PWRDWN_MON_0
 ***************************************************************************/
/* switch :: PAGE_73_PBB_PWRDWN_MON_0 :: PAGE_73_PBB_PWRDWN_MON_0_PWRDWN_CNT [63:00] */
#define Wr_switch_PAGE_73_PBB_PWRDWN_MON_0_PAGE_73_PBB_PWRDWN_MON_0_PWRDWN_CNT(x) WriteReg(SWITCH_PAGE_73_PBB_PWRDWN_MON_0,x)
#define Rd_switch_PAGE_73_PBB_PWRDWN_MON_0_PAGE_73_PBB_PWRDWN_MON_0_PWRDWN_CNT(x) ReadReg(SWITCH_PAGE_73_PBB_PWRDWN_MON_0)
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_0_PAGE_73_PBB_PWRDWN_MON_0_PWRDWN_CNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_0_PAGE_73_PBB_PWRDWN_MON_0_PWRDWN_CNT_ALIGN 0
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_0_PAGE_73_PBB_PWRDWN_MON_0_PWRDWN_CNT_BITS 64
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_0_PAGE_73_PBB_PWRDWN_MON_0_PWRDWN_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PBB_PWRDWN_MON_1
 ***************************************************************************/
/* switch :: PAGE_73_PBB_PWRDWN_MON_1 :: PAGE_73_PBB_PWRDWN_MON_1_PWRDWN_CNT [63:00] */
#define Wr_switch_PAGE_73_PBB_PWRDWN_MON_1_PAGE_73_PBB_PWRDWN_MON_1_PWRDWN_CNT(x) WriteReg(SWITCH_PAGE_73_PBB_PWRDWN_MON_1,x)
#define Rd_switch_PAGE_73_PBB_PWRDWN_MON_1_PAGE_73_PBB_PWRDWN_MON_1_PWRDWN_CNT(x) ReadReg(SWITCH_PAGE_73_PBB_PWRDWN_MON_1)
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_1_PAGE_73_PBB_PWRDWN_MON_1_PWRDWN_CNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_1_PAGE_73_PBB_PWRDWN_MON_1_PWRDWN_CNT_ALIGN 0
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_1_PAGE_73_PBB_PWRDWN_MON_1_PWRDWN_CNT_BITS 64
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_1_PAGE_73_PBB_PWRDWN_MON_1_PWRDWN_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_PBB_PWRDWN_MON_2
 ***************************************************************************/
/* switch :: PAGE_73_PBB_PWRDWN_MON_2 :: PAGE_73_PBB_PWRDWN_MON_2_PWRDWN_CNT [63:00] */
#define Wr_switch_PAGE_73_PBB_PWRDWN_MON_2_PAGE_73_PBB_PWRDWN_MON_2_PWRDWN_CNT(x) WriteReg(SWITCH_PAGE_73_PBB_PWRDWN_MON_2,x)
#define Rd_switch_PAGE_73_PBB_PWRDWN_MON_2_PAGE_73_PBB_PWRDWN_MON_2_PWRDWN_CNT(x) ReadReg(SWITCH_PAGE_73_PBB_PWRDWN_MON_2)
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_2_PAGE_73_PBB_PWRDWN_MON_2_PWRDWN_CNT_MASK 0xffffffffffffffff
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_2_PAGE_73_PBB_PWRDWN_MON_2_PWRDWN_CNT_ALIGN 0
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_2_PAGE_73_PBB_PWRDWN_MON_2_PWRDWN_CNT_BITS 64
#define SWITCH_PAGE_73_PBB_PWRDWN_MON_2_PAGE_73_PBB_PWRDWN_MON_2_PWRDWN_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_BPM_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_73_BPM_REG_SPARE0 :: PAGE_73_BPM_REG_SPARE0_BPM_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_73_BPM_REG_SPARE0_PAGE_73_BPM_REG_SPARE0_BPM_REG_SPARE0(x) WriteReg(SWITCH_PAGE_73_BPM_REG_SPARE0,x)
#define Rd_switch_PAGE_73_BPM_REG_SPARE0_PAGE_73_BPM_REG_SPARE0_BPM_REG_SPARE0(x) ReadReg(SWITCH_PAGE_73_BPM_REG_SPARE0)
#define SWITCH_PAGE_73_BPM_REG_SPARE0_PAGE_73_BPM_REG_SPARE0_BPM_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_73_BPM_REG_SPARE0_PAGE_73_BPM_REG_SPARE0_BPM_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_73_BPM_REG_SPARE0_PAGE_73_BPM_REG_SPARE0_BPM_REG_SPARE0_BITS 32
#define SWITCH_PAGE_73_BPM_REG_SPARE0_PAGE_73_BPM_REG_SPARE0_BPM_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_73_BPM_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_73_BPM_REG_SPARE1 :: PAGE_73_BPM_REG_SPARE1_BPM_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_73_BPM_REG_SPARE1_PAGE_73_BPM_REG_SPARE1_BPM_REG_SPARE1(x) WriteReg(SWITCH_PAGE_73_BPM_REG_SPARE1,x)
#define Rd_switch_PAGE_73_BPM_REG_SPARE1_PAGE_73_BPM_REG_SPARE1_BPM_REG_SPARE1(x) ReadReg(SWITCH_PAGE_73_BPM_REG_SPARE1)
#define SWITCH_PAGE_73_BPM_REG_SPARE1_PAGE_73_BPM_REG_SPARE1_BPM_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_73_BPM_REG_SPARE1_PAGE_73_BPM_REG_SPARE1_BPM_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_73_BPM_REG_SPARE1_PAGE_73_BPM_REG_SPARE1_BPM_REG_SPARE1_BITS 32
#define SWITCH_PAGE_73_BPM_REG_SPARE1_PAGE_73_BPM_REG_SPARE1_BPM_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_TIME_STAMP_EN
 ***************************************************************************/
/* switch :: PAGE_90_AVB_TIME_STAMP_EN :: PAGE_90_AVB_TIME_STAMP_EN_RESERVED [15:06] */
#define Wr_switch_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_RESERVED(x) WriteRegBits16(SWITCH_PAGE_90_AVB_TIME_STAMP_EN,0xffc0,6,x)
#define Rd_switch_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_RESERVED(x) ReadRegBits16(SWITCH_PAGE_90_AVB_TIME_STAMP_EN,0xffc0,6)
#define SWITCH_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_RESERVED_MASK 0xffc0
#define SWITCH_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_RESERVED_ALIGN 0
#define SWITCH_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_RESERVED_BITS 10
#define SWITCH_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_RESERVED_SHIFT 6

/* switch :: PAGE_90_AVB_TIME_STAMP_EN :: PAGE_90_AVB_TIME_STAMP_EN_AVB_TIME_STAMP_EN [05:00] */
#define Wr_switch_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_AVB_TIME_STAMP_EN(x) WriteRegBits16(SWITCH_PAGE_90_AVB_TIME_STAMP_EN,0x3f,0,x)
#define Rd_switch_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_AVB_TIME_STAMP_EN(x) ReadRegBits16(SWITCH_PAGE_90_AVB_TIME_STAMP_EN,0x3f,0)
#define SWITCH_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_AVB_TIME_STAMP_EN_MASK 0x003f
#define SWITCH_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_AVB_TIME_STAMP_EN_ALIGN 0
#define SWITCH_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_AVB_TIME_STAMP_EN_BITS 6
#define SWITCH_PAGE_90_AVB_TIME_STAMP_EN_PAGE_90_AVB_TIME_STAMP_EN_AVB_TIME_STAMP_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_TM_STAMP_RPT_CTRL
 ***************************************************************************/
/* switch :: PAGE_90_TM_STAMP_RPT_CTRL :: PAGE_90_TM_STAMP_RPT_CTRL_RESERVED [07:01] */
#define Wr_switch_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_RESERVED(x) WriteRegBits(SWITCH_PAGE_90_TM_STAMP_RPT_CTRL,0xfe,1,x)
#define Rd_switch_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_RESERVED(x) ReadRegBits(SWITCH_PAGE_90_TM_STAMP_RPT_CTRL,0xfe,1)
#define SWITCH_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_RESERVED_MASK 0xfe
#define SWITCH_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_RESERVED_BITS 7
#define SWITCH_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_RESERVED_SHIFT 1

/* switch :: PAGE_90_TM_STAMP_RPT_CTRL :: PAGE_90_TM_STAMP_RPT_CTRL_TSRPT_PKT_EN [00:00] */
#define Wr_switch_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_TSRPT_PKT_EN(x) WriteRegBits(SWITCH_PAGE_90_TM_STAMP_RPT_CTRL,0x1,0,x)
#define Rd_switch_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_TSRPT_PKT_EN(x) ReadRegBits(SWITCH_PAGE_90_TM_STAMP_RPT_CTRL,0x1,0)
#define SWITCH_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_TSRPT_PKT_EN_MASK 0x01
#define SWITCH_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_TSRPT_PKT_EN_ALIGN 0
#define SWITCH_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_TSRPT_PKT_EN_BITS 1
#define SWITCH_PAGE_90_TM_STAMP_RPT_CTRL_PAGE_90_TM_STAMP_RPT_CTRL_TSRPT_PKT_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_TM_BASE
 ***************************************************************************/
/* switch :: PAGE_90_AVB_TM_BASE :: PAGE_90_AVB_TM_BASE_TM_BASE [31:00] */
#define Wr_switch_PAGE_90_AVB_TM_BASE_PAGE_90_AVB_TM_BASE_TM_BASE(x) WriteReg(SWITCH_PAGE_90_AVB_TM_BASE,x)
#define Rd_switch_PAGE_90_AVB_TM_BASE_PAGE_90_AVB_TM_BASE_TM_BASE(x) ReadReg(SWITCH_PAGE_90_AVB_TM_BASE)
#define SWITCH_PAGE_90_AVB_TM_BASE_PAGE_90_AVB_TM_BASE_TM_BASE_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_TM_BASE_PAGE_90_AVB_TM_BASE_TM_BASE_ALIGN 0
#define SWITCH_PAGE_90_AVB_TM_BASE_PAGE_90_AVB_TM_BASE_TM_BASE_BITS 32
#define SWITCH_PAGE_90_AVB_TM_BASE_PAGE_90_AVB_TM_BASE_TM_BASE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_TM_ADJ
 ***************************************************************************/
/* switch :: PAGE_90_AVB_TM_ADJ :: PAGE_90_AVB_TM_ADJ_RESERVED_0 [31:12] */
#define Wr_switch_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_90_AVB_TM_ADJ,0xfffff000,12,x)
#define Rd_switch_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_90_AVB_TM_ADJ,0xfffff000,12)
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_0_MASK 0xfffff000
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_0_BITS 20
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_0_SHIFT 12

/* switch :: PAGE_90_AVB_TM_ADJ :: PAGE_90_AVB_TM_ADJ_TM_ADJ_PRD [11:08] */
#define Wr_switch_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_ADJ_PRD(x) WriteRegBits(SWITCH_PAGE_90_AVB_TM_ADJ,0xf00,8,x)
#define Rd_switch_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_ADJ_PRD(x) ReadRegBits(SWITCH_PAGE_90_AVB_TM_ADJ,0xf00,8)
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_ADJ_PRD_MASK 0x00000f00
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_ADJ_PRD_ALIGN 0
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_ADJ_PRD_BITS 4
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_ADJ_PRD_SHIFT 8

/* switch :: PAGE_90_AVB_TM_ADJ :: PAGE_90_AVB_TM_ADJ_RESERVED_1 [07:06] */
#define Wr_switch_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_90_AVB_TM_ADJ,0xc0,6,x)
#define Rd_switch_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_90_AVB_TM_ADJ,0xc0,6)
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_1_MASK 0x000000c0
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_1_BITS 2
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_RESERVED_1_SHIFT 6

/* switch :: PAGE_90_AVB_TM_ADJ :: PAGE_90_AVB_TM_ADJ_TM_INC [05:00] */
#define Wr_switch_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_INC(x) WriteRegBits(SWITCH_PAGE_90_AVB_TM_ADJ,0x3f,0,x)
#define Rd_switch_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_INC(x) ReadRegBits(SWITCH_PAGE_90_AVB_TM_ADJ,0x3f,0)
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_INC_MASK   0x0000003f
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_INC_ALIGN  0
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_INC_BITS   6
#define SWITCH_PAGE_90_AVB_TM_ADJ_PAGE_90_AVB_TM_ADJ_TM_INC_SHIFT  0


/****************************************************************************
 * switch :: PAGE_90_AVB_SLOT_TICK
 ***************************************************************************/
/* switch :: PAGE_90_AVB_SLOT_TICK :: PAGE_90_AVB_SLOT_TICK_RESERVED_0 [31:28] */
#define Wr_switch_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_TICK,0xf0000000,28,x)
#define Rd_switch_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_TICK,0xf0000000,28)
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_0_MASK 0xf0000000
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_0_BITS 4
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_0_SHIFT 28

/* switch :: PAGE_90_AVB_SLOT_TICK :: PAGE_90_AVB_SLOT_TICK_TICK_CNTR [27:16] */
#define Wr_switch_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_TICK_CNTR(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_TICK,0xfff0000,16,x)
#define Rd_switch_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_TICK_CNTR(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_TICK,0xfff0000,16)
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_TICK_CNTR_MASK 0x0fff0000
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_TICK_CNTR_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_TICK_CNTR_BITS 12
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_TICK_CNTR_SHIFT 16

/* switch :: PAGE_90_AVB_SLOT_TICK :: PAGE_90_AVB_SLOT_TICK_RESERVED_1 [15:05] */
#define Wr_switch_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_TICK,0xffe0,5,x)
#define Rd_switch_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_TICK,0xffe0,5)
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_1_MASK 0x0000ffe0
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_1_BITS 11
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_RESERVED_1_SHIFT 5

/* switch :: PAGE_90_AVB_SLOT_TICK :: PAGE_90_AVB_SLOT_TICK_SLOT_NUM [04:00] */
#define Wr_switch_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_SLOT_NUM(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_TICK,0x1f,0,x)
#define Rd_switch_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_SLOT_NUM(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_TICK,0x1f,0)
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_SLOT_NUM_MASK 0x0000001f
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_SLOT_NUM_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_SLOT_NUM_BITS 5
#define SWITCH_PAGE_90_AVB_SLOT_TICK_PAGE_90_AVB_SLOT_TICK_SLOT_NUM_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_SLOT_ADJ
 ***************************************************************************/
/* switch :: PAGE_90_AVB_SLOT_ADJ :: PAGE_90_AVB_SLOT_ADJ_RESERVED_0 [31:18] */
#define Wr_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0xfffc0000,18,x)
#define Rd_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0xfffc0000,18)
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_0_MASK 0xfffc0000
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_0_BITS 14
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_0_SHIFT 18

/* switch :: PAGE_90_AVB_SLOT_ADJ :: PAGE_90_AVB_SLOT_ADJ_MCRO_SLOT_PRD [17:16] */
#define Wr_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_MCRO_SLOT_PRD(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0x30000,16,x)
#define Rd_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_MCRO_SLOT_PRD(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0x30000,16)
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_MCRO_SLOT_PRD_MASK 0x00030000
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_MCRO_SLOT_PRD_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_MCRO_SLOT_PRD_BITS 2
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_MCRO_SLOT_PRD_SHIFT 16

/* switch :: PAGE_90_AVB_SLOT_ADJ :: PAGE_90_AVB_SLOT_ADJ_RESERVED_1 [15:12] */
#define Wr_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0xf000,12,x)
#define Rd_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0xf000,12)
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_1_MASK 0x0000f000
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_1_BITS 4
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_1_SHIFT 12

/* switch :: PAGE_90_AVB_SLOT_ADJ :: PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_PRD [11:08] */
#define Wr_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_PRD(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0xf00,8,x)
#define Rd_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_PRD(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0xf00,8)
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_PRD_MASK 0x00000f00
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_PRD_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_PRD_BITS 4
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_PRD_SHIFT 8

/* switch :: PAGE_90_AVB_SLOT_ADJ :: PAGE_90_AVB_SLOT_ADJ_RESERVED_2 [07:02] */
#define Wr_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0xfc,2,x)
#define Rd_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0xfc,2)
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_2_MASK 0x000000fc
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_2_BITS 6
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_RESERVED_2_SHIFT 2

/* switch :: PAGE_90_AVB_SLOT_ADJ :: PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ [01:00] */
#define Wr_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ(x) WriteRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0x3,0,x)
#define Rd_switch_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ(x) ReadRegBits(SWITCH_PAGE_90_AVB_SLOT_ADJ,0x3,0)
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_MASK 0x00000003
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_ALIGN 0
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_BITS 2
#define SWITCH_PAGE_90_AVB_SLOT_ADJ_PAGE_90_AVB_SLOT_ADJ_SLOT_ADJ_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port0
 ***************************************************************************/
/* switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port0 :: PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_0 [31:00] */
#define Wr_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port0_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_0(x) WriteReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT0,x)
#define Rd_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port0_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_0(x) ReadReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT0)
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT0_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_0_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT0_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_0_ALIGN 0
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT0_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_0_BITS 32
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT0_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port1
 ***************************************************************************/
/* switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port1 :: PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_1 [31:00] */
#define Wr_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port1_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_1(x) WriteReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT1,x)
#define Rd_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port1_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_1(x) ReadReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT1)
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT1_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_1_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT1_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_1_ALIGN 0
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT1_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_1_BITS 32
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT1_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port2
 ***************************************************************************/
/* switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port2 :: PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_2 [31:00] */
#define Wr_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port2_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_2(x) WriteReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT2,x)
#define Rd_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port2_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_2(x) ReadReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT2)
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT2_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_2_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT2_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_2_ALIGN 0
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT2_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_2_BITS 32
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT2_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port3
 ***************************************************************************/
/* switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port3 :: PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_3 [31:00] */
#define Wr_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port3_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_3(x) WriteReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT3,x)
#define Rd_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port3_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_3(x) ReadReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT3)
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT3_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_3_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT3_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_3_ALIGN 0
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT3_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_3_BITS 32
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT3_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port4
 ***************************************************************************/
/* switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port4 :: PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_4 [31:00] */
#define Wr_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port4_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_4(x) WriteReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT4,x)
#define Rd_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port4_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_4(x) ReadReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT4)
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT4_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_4_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT4_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_4_ALIGN 0
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT4_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_4_BITS 32
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT4_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port5
 ***************************************************************************/
/* switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port5 :: PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_5 [31:00] */
#define Wr_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port5_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_5(x) WriteReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT5,x)
#define Rd_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port5_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_5(x) ReadReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT5)
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT5_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_5_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT5_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_5_ALIGN 0
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT5_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_5_BITS 32
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT5_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port6
 ***************************************************************************/
/* switch :: PAGE_90_AVB_EGRESS_TM_STAMP_port6 :: PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_6 [31:00] */
#define Wr_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port6_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_6(x) WriteReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT6,x)
#define Rd_switch_PAGE_90_AVB_EGRESS_TM_STAMP_port6_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_6(x) ReadReg(SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT6)
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT6_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_6_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT6_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_6_ALIGN 0
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT6_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_6_BITS 32
#define SWITCH_PAGE_90_AVB_EGRESS_TM_STAMP_PORT6_PAGE_90_AVB_EGRESS_TM_STAMP_EGRESS_TS_TM_STAMP_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_TM_STAMP_STATUS
 ***************************************************************************/
/* switch :: PAGE_90_TM_STAMP_STATUS :: PAGE_90_TM_STAMP_STATUS_VALID_STATUS [07:00] */
#define Wr_switch_PAGE_90_TM_STAMP_STATUS_PAGE_90_TM_STAMP_STATUS_VALID_STATUS(x) WriteReg(SWITCH_PAGE_90_TM_STAMP_STATUS,x)
#define Rd_switch_PAGE_90_TM_STAMP_STATUS_PAGE_90_TM_STAMP_STATUS_VALID_STATUS(x) ReadReg(SWITCH_PAGE_90_TM_STAMP_STATUS)
#define SWITCH_PAGE_90_TM_STAMP_STATUS_PAGE_90_TM_STAMP_STATUS_VALID_STATUS_MASK 0xff
#define SWITCH_PAGE_90_TM_STAMP_STATUS_PAGE_90_TM_STAMP_STATUS_VALID_STATUS_ALIGN 0
#define SWITCH_PAGE_90_TM_STAMP_STATUS_PAGE_90_TM_STAMP_STATUS_VALID_STATUS_BITS 8
#define SWITCH_PAGE_90_TM_STAMP_STATUS_PAGE_90_TM_STAMP_STATUS_VALID_STATUS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_EAV_LNK_STATUS
 ***************************************************************************/
/* switch :: PAGE_90_EAV_LNK_STATUS :: PAGE_90_EAV_LNK_STATUS_RESERVED [15:06] */
#define Wr_switch_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_90_EAV_LNK_STATUS,0xffc0,6,x)
#define Rd_switch_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_90_EAV_LNK_STATUS,0xffc0,6)
#define SWITCH_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_RESERVED_MASK 0xffc0
#define SWITCH_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_RESERVED_ALIGN 0
#define SWITCH_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_RESERVED_BITS 10
#define SWITCH_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_RESERVED_SHIFT 6

/* switch :: PAGE_90_EAV_LNK_STATUS :: PAGE_90_EAV_LNK_STATUS_PT_EAV_LNK_STATUS [05:00] */
#define Wr_switch_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_PT_EAV_LNK_STATUS(x) WriteRegBits16(SWITCH_PAGE_90_EAV_LNK_STATUS,0x3f,0,x)
#define Rd_switch_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_PT_EAV_LNK_STATUS(x) ReadRegBits16(SWITCH_PAGE_90_EAV_LNK_STATUS,0x3f,0)
#define SWITCH_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_PT_EAV_LNK_STATUS_MASK 0x003f
#define SWITCH_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_PT_EAV_LNK_STATUS_ALIGN 0
#define SWITCH_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_PT_EAV_LNK_STATUS_BITS 6
#define SWITCH_PAGE_90_EAV_LNK_STATUS_PAGE_90_EAV_LNK_STATUS_PT_EAV_LNK_STATUS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_P1588_CTRL
 ***************************************************************************/
/* switch :: PAGE_90_P1588_CTRL :: PAGE_90_P1588_CTRL_RESERVED [15:09] */
#define Wr_switch_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_90_P1588_CTRL,0xfe00,9,x)
#define Rd_switch_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_90_P1588_CTRL,0xfe00,9)
#define SWITCH_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_RESERVED_BITS 7
#define SWITCH_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_RESERVED_SHIFT 9

/* switch :: PAGE_90_P1588_CTRL :: PAGE_90_P1588_CTRL_SOP_SEL [08:00] */
#define Wr_switch_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_SOP_SEL(x) WriteRegBits16(SWITCH_PAGE_90_P1588_CTRL,0x1ff,0,x)
#define Rd_switch_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_SOP_SEL(x) ReadRegBits16(SWITCH_PAGE_90_P1588_CTRL,0x1ff,0)
#define SWITCH_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_SOP_SEL_MASK  0x01ff
#define SWITCH_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_SOP_SEL_ALIGN 0
#define SWITCH_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_SOP_SEL_BITS  9
#define SWITCH_PAGE_90_P1588_CTRL_PAGE_90_P1588_CTRL_SOP_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_TICK_CTRL
 ***************************************************************************/
/* switch :: PAGE_90_AVB_TICK_CTRL :: PAGE_90_AVB_TICK_CTRL_RESERVED [15:03] */
#define Wr_switch_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_90_AVB_TICK_CTRL,0xfff8,3,x)
#define Rd_switch_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_90_AVB_TICK_CTRL,0xfff8,3)
#define SWITCH_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_RESERVED_MASK 0xfff8
#define SWITCH_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_RESERVED_BITS 13
#define SWITCH_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_RESERVED_SHIFT 3

/* switch :: PAGE_90_AVB_TICK_CTRL :: PAGE_90_AVB_TICK_CTRL_TICK_SEL [02:00] */
#define Wr_switch_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_TICK_SEL(x) WriteRegBits16(SWITCH_PAGE_90_AVB_TICK_CTRL,0x7,0,x)
#define Rd_switch_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_TICK_SEL(x) ReadRegBits16(SWITCH_PAGE_90_AVB_TICK_CTRL,0x7,0)
#define SWITCH_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_TICK_SEL_MASK 0x0007
#define SWITCH_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_TICK_SEL_ALIGN 0
#define SWITCH_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_TICK_SEL_BITS 3
#define SWITCH_PAGE_90_AVB_TICK_CTRL_PAGE_90_AVB_TICK_CTRL_TICK_SEL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_90_AVB_REG_SPARE0 :: PAGE_90_AVB_REG_SPARE0_AVB_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_90_AVB_REG_SPARE0_PAGE_90_AVB_REG_SPARE0_AVB_REG_SPARE0(x) WriteReg(SWITCH_PAGE_90_AVB_REG_SPARE0,x)
#define Rd_switch_PAGE_90_AVB_REG_SPARE0_PAGE_90_AVB_REG_SPARE0_AVB_REG_SPARE0(x) ReadReg(SWITCH_PAGE_90_AVB_REG_SPARE0)
#define SWITCH_PAGE_90_AVB_REG_SPARE0_PAGE_90_AVB_REG_SPARE0_AVB_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_REG_SPARE0_PAGE_90_AVB_REG_SPARE0_AVB_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_90_AVB_REG_SPARE0_PAGE_90_AVB_REG_SPARE0_AVB_REG_SPARE0_BITS 32
#define SWITCH_PAGE_90_AVB_REG_SPARE0_PAGE_90_AVB_REG_SPARE0_AVB_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_90_AVB_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_90_AVB_REG_SPARE1 :: PAGE_90_AVB_REG_SPARE1_AVB_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_90_AVB_REG_SPARE1_PAGE_90_AVB_REG_SPARE1_AVB_REG_SPARE1(x) WriteReg(SWITCH_PAGE_90_AVB_REG_SPARE1,x)
#define Rd_switch_PAGE_90_AVB_REG_SPARE1_PAGE_90_AVB_REG_SPARE1_AVB_REG_SPARE1(x) ReadReg(SWITCH_PAGE_90_AVB_REG_SPARE1)
#define SWITCH_PAGE_90_AVB_REG_SPARE1_PAGE_90_AVB_REG_SPARE1_AVB_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_90_AVB_REG_SPARE1_PAGE_90_AVB_REG_SPARE1_AVB_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_90_AVB_REG_SPARE1_PAGE_90_AVB_REG_SPARE1_AVB_REG_SPARE1_BITS 32
#define SWITCH_PAGE_90_AVB_REG_SPARE1_PAGE_90_AVB_REG_SPARE1_AVB_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_TRREG_CTRL0
 ***************************************************************************/
/* switch :: PAGE_91_TRREG_CTRL0 :: PAGE_91_TRREG_CTRL0_RESERVED_1 [31:25] */
#define Wr_switch_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL0,0xfe000000,25,x)
#define Rd_switch_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL0,0xfe000000,25)
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_1_MASK 0xfe000000
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_1_BITS 7
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_1_SHIFT 25

/* switch :: PAGE_91_TRREG_CTRL0 :: PAGE_91_TRREG_CTRL0_PCP_RMK_EN [24:16] */
#define Wr_switch_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_PCP_RMK_EN(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL0,0x1ff0000,16,x)
#define Rd_switch_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_PCP_RMK_EN(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL0,0x1ff0000,16)
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_PCP_RMK_EN_MASK 0x01ff0000
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_PCP_RMK_EN_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_PCP_RMK_EN_BITS 9
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_PCP_RMK_EN_SHIFT 16

/* switch :: PAGE_91_TRREG_CTRL0 :: PAGE_91_TRREG_CTRL0_RESERVED_0 [15:09] */
#define Wr_switch_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL0,0xfe00,9,x)
#define Rd_switch_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL0,0xfe00,9)
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_0_MASK 0x0000fe00
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_0_BITS 7
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_RESERVED_0_SHIFT 9

/* switch :: PAGE_91_TRREG_CTRL0 :: PAGE_91_TRREG_CTRL0_CFI_RMK_EN [08:00] */
#define Wr_switch_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_CFI_RMK_EN(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL0,0x1ff,0,x)
#define Rd_switch_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_CFI_RMK_EN(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL0,0x1ff,0)
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_CFI_RMK_EN_MASK 0x000001ff
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_CFI_RMK_EN_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_CFI_RMK_EN_BITS 9
#define SWITCH_PAGE_91_TRREG_CTRL0_PAGE_91_TRREG_CTRL0_CFI_RMK_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_TRREG_CTRL1
 ***************************************************************************/
/* switch :: PAGE_91_TRREG_CTRL1 :: PAGE_91_TRREG_CTRL1_RESERVED_1 [31:25] */
#define Wr_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0xfe000000,25,x)
#define Rd_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0xfe000000,25)
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_1_MASK 0xfe000000
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_1_BITS 7
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_1_SHIFT 25

/* switch :: PAGE_91_TRREG_CTRL1 :: PAGE_91_TRREG_CTRL1_DEI_RMK_EN [24:16] */
#define Wr_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DEI_RMK_EN(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0x1ff0000,16,x)
#define Rd_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DEI_RMK_EN(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0x1ff0000,16)
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DEI_RMK_EN_MASK 0x01ff0000
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DEI_RMK_EN_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DEI_RMK_EN_BITS 9
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DEI_RMK_EN_SHIFT 16

/* switch :: PAGE_91_TRREG_CTRL1 :: PAGE_91_TRREG_CTRL1_PPPOE_DSCP_RMK_EN [15:15] */
#define Wr_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_PPPOE_DSCP_RMK_EN(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0x8000,15,x)
#define Rd_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_PPPOE_DSCP_RMK_EN(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0x8000,15)
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_MASK 0x00008000
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_BITS 1
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_PPPOE_DSCP_RMK_EN_SHIFT 15

/* switch :: PAGE_91_TRREG_CTRL1 :: PAGE_91_TRREG_CTRL1_RESERVED_0 [14:09] */
#define Wr_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0x7e00,9,x)
#define Rd_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0x7e00,9)
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_0_MASK 0x00007e00
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_0_BITS 6
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_RESERVED_0_SHIFT 9

/* switch :: PAGE_91_TRREG_CTRL1 :: PAGE_91_TRREG_CTRL1_DSCP_RMK_EN [08:00] */
#define Wr_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DSCP_RMK_EN(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0x1ff,0,x)
#define Rd_switch_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DSCP_RMK_EN(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL1,0x1ff,0)
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DSCP_RMK_EN_MASK 0x000001ff
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DSCP_RMK_EN_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DSCP_RMK_EN_BITS 9
#define SWITCH_PAGE_91_TRREG_CTRL1_PAGE_91_TRREG_CTRL1_DSCP_RMK_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_TRREG_CTRL2
 ***************************************************************************/
/* switch :: PAGE_91_TRREG_CTRL2 :: PAGE_91_TRREG_CTRL2_RESERVED_1 [31:25] */
#define Wr_switch_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL2,0xfe000000,25,x)
#define Rd_switch_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL2,0xfe000000,25)
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_1_MASK 0xfe000000
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_1_BITS 7
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_1_SHIFT 25

/* switch :: PAGE_91_TRREG_CTRL2 :: PAGE_91_TRREG_CTRL2_C_PCP_RMK_EN [24:16] */
#define Wr_switch_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_C_PCP_RMK_EN(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL2,0x1ff0000,16,x)
#define Rd_switch_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_C_PCP_RMK_EN(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL2,0x1ff0000,16)
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_C_PCP_RMK_EN_MASK 0x01ff0000
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_C_PCP_RMK_EN_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_C_PCP_RMK_EN_BITS 9
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_C_PCP_RMK_EN_SHIFT 16

/* switch :: PAGE_91_TRREG_CTRL2 :: PAGE_91_TRREG_CTRL2_RESERVED_0 [15:09] */
#define Wr_switch_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL2,0xfe00,9,x)
#define Rd_switch_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL2,0xfe00,9)
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_0_MASK 0x0000fe00
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_0_BITS 7
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_RESERVED_0_SHIFT 9

/* switch :: PAGE_91_TRREG_CTRL2 :: PAGE_91_TRREG_CTRL2_S_PCP_RMK_EN [08:00] */
#define Wr_switch_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_S_PCP_RMK_EN(x) WriteRegBits(SWITCH_PAGE_91_TRREG_CTRL2,0x1ff,0,x)
#define Rd_switch_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_S_PCP_RMK_EN(x) ReadRegBits(SWITCH_PAGE_91_TRREG_CTRL2,0x1ff,0)
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_S_PCP_RMK_EN_MASK 0x000001ff
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_S_PCP_RMK_EN_ALIGN 0
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_S_PCP_RMK_EN_BITS 9
#define SWITCH_PAGE_91_TRREG_CTRL2_PAGE_91_TRREG_CTRL2_S_PCP_RMK_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_0 [63:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_0_MASK 0xf000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_0_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_0 [59:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_0_MASK 0x0f00000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_0_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_0 [55:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_0_MASK 0x00f0000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_0_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_0 [51:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_0_MASK 0x000f000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_0_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_0 [47:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_0_MASK 0x0000f00000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_0_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_0 [43:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_0_MASK 0x00000f0000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_0_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_0 [39:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_0_MASK 0x000000f000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_0_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_0 [35:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_0_MASK 0x0000000f00000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_0_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_0 [31:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_0_MASK 0x00000000f0000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_0_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_0 [27:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_0_MASK 0x000000000f000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_0_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_0 [23:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_0_MASK 0x0000000000f00000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_0_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_0 [19:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_0_MASK 0x00000000000f0000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_0_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_0 [15:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_0_MASK 0x000000000000f000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_0_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_0 [11:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf00,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_0_MASK 0x0000000000000f00
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_0_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_0 [07:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf0,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_0_MASK 0x00000000000000f0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_0_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_0 [03:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0,0xf,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_0_MASK 0x000000000000000f
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_0_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_1 [63:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_1_MASK 0xf000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_1_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_1 [59:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_1_MASK 0x0f00000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_1_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_1 [55:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_1_MASK 0x00f0000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_1_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_1 [51:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_1_MASK 0x000f000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_1_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_1 [47:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_1_MASK 0x0000f00000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_1_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_1 [43:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_1_MASK 0x00000f0000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_1_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_1 [39:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_1_MASK 0x000000f000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_1_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_1 [35:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_1_MASK 0x0000000f00000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_1_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_1 [31:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_1_MASK 0x00000000f0000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_1_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_1 [27:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_1_MASK 0x000000000f000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_1_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_1 [23:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_1_MASK 0x0000000000f00000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_1_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_1 [19:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_1_MASK 0x00000000000f0000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_1_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_1 [15:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_1_MASK 0x000000000000f000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_1_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_1 [11:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf00,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_1_MASK 0x0000000000000f00
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_1_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_1 [07:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf0,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_1_MASK 0x00000000000000f0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_1_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_1 [03:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1,0xf,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_1_MASK 0x000000000000000f
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_1_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_2 [63:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_2_MASK 0xf000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_2_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_2 [59:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_2_MASK 0x0f00000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_2_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_2 [55:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_2_MASK 0x00f0000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_2_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_2 [51:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_2_MASK 0x000f000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_2_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_2 [47:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_2_MASK 0x0000f00000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_2_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_2 [43:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_2_MASK 0x00000f0000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_2_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_2 [39:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_2_MASK 0x000000f000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_2_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_2 [35:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_2_MASK 0x0000000f00000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_2_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_2 [31:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_2_MASK 0x00000000f0000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_2_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_2 [27:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_2_MASK 0x000000000f000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_2_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_2 [23:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_2_MASK 0x0000000000f00000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_2_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_2 [19:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_2_MASK 0x00000000000f0000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_2_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_2 [15:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_2_MASK 0x000000000000f000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_2_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_2 [11:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf00,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_2_MASK 0x0000000000000f00
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_2_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_2 [07:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf0,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_2_MASK 0x00000000000000f0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_2_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_2 [03:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2,0xf,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_2_MASK 0x000000000000000f
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_2_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_3 [63:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_3_MASK 0xf000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_3_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_3 [59:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_3_MASK 0x0f00000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_3_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_3 [55:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_3_MASK 0x00f0000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_3_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_3 [51:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_3_MASK 0x000f000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_3_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_3 [47:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_3_MASK 0x0000f00000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_3_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_3 [43:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_3_MASK 0x00000f0000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_3_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_3 [39:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_3_MASK 0x000000f000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_3_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_3 [35:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_3_MASK 0x0000000f00000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_3_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_3 [31:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_3_MASK 0x00000000f0000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_3_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_3 [27:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_3_MASK 0x000000000f000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_3_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_3 [23:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_3_MASK 0x0000000000f00000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_3_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_3 [19:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_3_MASK 0x00000000000f0000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_3_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_3 [15:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_3_MASK 0x000000000000f000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_3_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_3 [11:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf00,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_3_MASK 0x0000000000000f00
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_3_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_3 [07:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf0,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_3_MASK 0x00000000000000f0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_3_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_3 [03:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3,0xf,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_3_MASK 0x000000000000000f
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_3_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_4 [63:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_4_MASK 0xf000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_4_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_4 [59:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_4_MASK 0x0f00000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_4_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_4 [55:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_4_MASK 0x00f0000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_4_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_4 [51:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_4_MASK 0x000f000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_4_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_4 [47:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_4_MASK 0x0000f00000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_4_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_4 [43:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_4_MASK 0x00000f0000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_4_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_4 [39:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_4_MASK 0x000000f000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_4_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_4 [35:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_4_MASK 0x0000000f00000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_4_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_4 [31:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_4_MASK 0x00000000f0000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_4_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_4 [27:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_4_MASK 0x000000000f000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_4_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_4 [23:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_4_MASK 0x0000000000f00000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_4_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_4 [19:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_4_MASK 0x00000000000f0000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_4_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_4 [15:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_4_MASK 0x000000000000f000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_4_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_4 [11:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf00,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_4_MASK 0x0000000000000f00
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_4_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_4 [07:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf0,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_4_MASK 0x00000000000000f0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_4_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_4 [03:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4,0xf,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_4_MASK 0x000000000000000f
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_4_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_5 [63:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_5_MASK 0xf000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_5_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_5 [59:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_5_MASK 0x0f00000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_5_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_5 [55:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_5_MASK 0x00f0000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_5_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_5 [51:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_5_MASK 0x000f000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_5_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_5 [47:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_5_MASK 0x0000f00000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_5_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_5 [43:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_5_MASK 0x00000f0000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_5_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_5 [39:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_5_MASK 0x000000f000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_5_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_5 [35:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_5_MASK 0x0000000f00000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_5_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_5 [31:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_5_MASK 0x00000000f0000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_5_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_5 [27:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_5_MASK 0x000000000f000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_5_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_5 [23:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_5_MASK 0x0000000000f00000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_5_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_5 [19:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_5_MASK 0x00000000000f0000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_5_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_5 [15:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_5_MASK 0x000000000000f000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_5_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_5 [11:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf00,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_5_MASK 0x0000000000000f00
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_5_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_5 [07:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf0,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_5_MASK 0x00000000000000f0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_5_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_5 [03:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5,0xf,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_5_MASK 0x000000000000000f
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_5_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_6 [63:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_6_MASK 0xf000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_6_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_6 [59:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_6_MASK 0x0f00000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_6_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_6 [55:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_6_MASK 0x00f0000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_6_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_6 [51:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_6_MASK 0x000f000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_6_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_6 [47:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_6_MASK 0x0000f00000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_6_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_6 [43:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_6_MASK 0x00000f0000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_6_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_6 [39:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_6_MASK 0x000000f000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_6_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_6 [35:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_6_MASK 0x0000000f00000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_6_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_6 [31:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_6_MASK 0x00000000f0000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_6_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_6 [27:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_6_MASK 0x000000000f000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_6_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_6 [23:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_6_MASK 0x0000000000f00000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_6_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_6 [19:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_6_MASK 0x00000000000f0000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_6_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_6 [15:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_6_MASK 0x000000000000f000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_6_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_6 [11:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf00,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_6_MASK 0x0000000000000f00
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_6_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_6 [07:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf0,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_6_MASK 0x00000000000000f0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_6_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_6 [03:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6,0xf,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_6_MASK 0x000000000000000f
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_6_BITS 4
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP
 ***************************************************************************/
/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7 [63:60] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000000000000000,60,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000000000000000,60)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_SHIFT 60

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6 [59:56] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00000000000000,56,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00000000000000,56)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_SHIFT 56

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5 [55:52] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0000000000000,52,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0000000000000,52)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_SHIFT 52

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4 [51:48] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000000000000,48,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000000000000,48)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_SHIFT 48

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3 [47:44] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00000000000,44,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00000000000,44)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_SHIFT 44

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2 [43:40] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0000000000,40,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0000000000,40)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_SHIFT 40

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1 [39:36] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000000000,36,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000000000,36)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_SHIFT 36

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0 [35:32] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00000000,32,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00000000,32)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_SHIFT 32

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7 [31:28] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0000000,28,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0000000,28)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_SHIFT 28

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6 [27:24] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000000,24,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000000,24)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_SHIFT 24

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5 [23:20] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00000,20,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00000,20)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_SHIFT 20

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4 [19:16] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0000,16,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0000,16)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_SHIFT 16

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3 [15:12] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000,12,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf000,12)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_SHIFT 12

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2 [11:08] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00,8,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf00,8)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_SHIFT 8

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1 [07:04] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0,4,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf0,4)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_SHIFT 4

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0 [03:00] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf,0,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP,0xf,0)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_BITS 4
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP
 ***************************************************************************/
/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7 [63:60] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000000000000000,60,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000000000000000,60)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_MASK 0xf000000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC7_SHIFT 60

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6 [59:56] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00000000000000,56,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00000000000000,56)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_MASK 0x0f00000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC6_SHIFT 56

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5 [55:52] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0000000000000,52,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0000000000000,52)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_MASK 0x00f0000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC5_SHIFT 52

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4 [51:48] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000000000000,48,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000000000000,48)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_MASK 0x000f000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC4_SHIFT 48

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3 [47:44] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00000000000,44,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00000000000,44)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_MASK 0x0000f00000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC3_SHIFT 44

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2 [43:40] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0000000000,40,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0000000000,40)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_MASK 0x00000f0000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC2_SHIFT 40

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1 [39:36] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000000000,36,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000000000,36)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_MASK 0x000000f000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC1_SHIFT 36

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0 [35:32] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00000000,32,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00000000,32)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_MASK 0x0000000f00000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV1_TC0_SHIFT 32

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7 [31:28] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0000000,28,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0000000,28)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_MASK 0x00000000f0000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC7_SHIFT 28

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6 [27:24] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000000,24,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000000,24)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_MASK 0x000000000f000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC6_SHIFT 24

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5 [23:20] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00000,20,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00000,20)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_MASK 0x0000000000f00000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC5_SHIFT 20

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4 [19:16] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0000,16,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0000,16)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_MASK 0x00000000000f0000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC4_SHIFT 16

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3 [15:12] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000,12,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf000,12)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_MASK 0x000000000000f000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC3_SHIFT 12

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2 [11:08] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00,8,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf00,8)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_MASK 0x0000000000000f00
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC2_SHIFT 8

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1 [07:04] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0,4,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf0,4)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_MASK 0x00000000000000f0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC1_SHIFT 4

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0 [03:00] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf,0,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP,0xf,0)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_MASK 0x000000000000000f
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_BITS 4
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2PCP_MAP_PCP_FOR_RV0_TC0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_0 [63:63] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000000000000000,63,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000000000000000,63)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_0_MASK 0x8000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_0_SHIFT 63

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_0 [62:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_0_MASK 0x7000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_0_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_0 [59:59] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800000000000000,59,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800000000000000,59)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_0_MASK 0x0800000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_0_SHIFT 59

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_0 [58:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_0_MASK 0x0700000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_0_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_0 [55:55] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80000000000000,55,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80000000000000,55)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_0_MASK 0x0080000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_0_SHIFT 55

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_0 [54:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_0_MASK 0x0070000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_0_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_0 [51:51] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000000000000,51,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000000000000,51)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_0_MASK 0x0008000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_0_SHIFT 51

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_0 [50:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_0_MASK 0x0007000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_0_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_0 [47:47] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800000000000,47,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800000000000,47)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_0_MASK 0x0000800000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_0_SHIFT 47

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_0 [46:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_0_MASK 0x0000700000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_0_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_0 [43:43] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80000000000,43,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80000000000,43)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_0_MASK 0x0000080000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_0_SHIFT 43

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_0 [42:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_0_MASK 0x0000070000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_0_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_0 [39:39] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000000000,39,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000000000,39)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_0_MASK 0x0000008000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_0_SHIFT 39

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_0 [38:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_0_MASK 0x0000007000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_0_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_0 [35:35] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800000000,35,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800000000,35)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_0_MASK 0x0000000800000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_0_SHIFT 35

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_0 [34:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_0_MASK 0x0000000700000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_0_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_0 [31:31] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80000000,31,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80000000,31)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_0_MASK 0x0000000080000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_0_SHIFT 31

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_0 [30:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_0_MASK 0x0000000070000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_0_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_0 [27:27] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000000,27,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000000,27)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_0_MASK 0x0000000008000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_0_SHIFT 27

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_0 [26:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_0_MASK 0x0000000007000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_0_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_0 [23:23] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800000,23,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800000,23)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_0_MASK 0x0000000000800000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_0_SHIFT 23

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_0 [22:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_0_MASK 0x0000000000700000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_0_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_0 [19:19] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80000,19,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80000,19)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_0_MASK 0x0000000000080000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_0_SHIFT 19

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_0 [18:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_0_MASK 0x0000000000070000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_0_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_0 [15:15] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000,15,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8000,15)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_0_MASK 0x0000000000008000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_0_SHIFT 15

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_0 [14:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_0_MASK 0x0000000000007000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_0_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_0 [11:11] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800,11,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x800,11)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_0_MASK 0x0000000000000800
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_0_SHIFT 11

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_0 [10:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x700,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_0_MASK 0x0000000000000700
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_0_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_0 [07:07] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80,7,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x80,7)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_0_MASK 0x0000000000000080
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_0_SHIFT 7

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_0 [06:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x70,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_0_MASK 0x0000000000000070
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_0_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_0 [03:03] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8,3,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x8,3)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_0_MASK 0x0000000000000008
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_0_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_0_SHIFT 3

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_0 [02:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_0(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_0(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0,0x7,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_0_MASK 0x0000000000000007
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_0_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_0_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT0_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_1 [63:63] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000000000000000,63,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000000000000000,63)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_1_MASK 0x8000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_1_SHIFT 63

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_1 [62:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_1_MASK 0x7000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_1_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_1 [59:59] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800000000000000,59,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800000000000000,59)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_1_MASK 0x0800000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_1_SHIFT 59

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_1 [58:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_1_MASK 0x0700000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_1_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_1 [55:55] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80000000000000,55,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80000000000000,55)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_1_MASK 0x0080000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_1_SHIFT 55

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_1 [54:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_1_MASK 0x0070000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_1_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_1 [51:51] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000000000000,51,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000000000000,51)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_1_MASK 0x0008000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_1_SHIFT 51

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_1 [50:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_1_MASK 0x0007000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_1_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_1 [47:47] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800000000000,47,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800000000000,47)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_1_MASK 0x0000800000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_1_SHIFT 47

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_1 [46:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_1_MASK 0x0000700000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_1_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_1 [43:43] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80000000000,43,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80000000000,43)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_1_MASK 0x0000080000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_1_SHIFT 43

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_1 [42:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_1_MASK 0x0000070000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_1_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_1 [39:39] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000000000,39,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000000000,39)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_1_MASK 0x0000008000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_1_SHIFT 39

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_1 [38:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_1_MASK 0x0000007000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_1_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_1 [35:35] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800000000,35,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800000000,35)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_1_MASK 0x0000000800000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_1_SHIFT 35

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_1 [34:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_1_MASK 0x0000000700000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_1_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_1 [31:31] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80000000,31,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80000000,31)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_1_MASK 0x0000000080000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_1_SHIFT 31

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_1 [30:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_1_MASK 0x0000000070000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_1_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_1 [27:27] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000000,27,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000000,27)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_1_MASK 0x0000000008000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_1_SHIFT 27

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_1 [26:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_1_MASK 0x0000000007000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_1_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_1 [23:23] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800000,23,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800000,23)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_1_MASK 0x0000000000800000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_1_SHIFT 23

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_1 [22:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_1_MASK 0x0000000000700000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_1_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_1 [19:19] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80000,19,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80000,19)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_1_MASK 0x0000000000080000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_1_SHIFT 19

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_1 [18:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_1_MASK 0x0000000000070000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_1_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_1 [15:15] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000,15,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8000,15)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_1_MASK 0x0000000000008000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_1_SHIFT 15

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_1 [14:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_1_MASK 0x0000000000007000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_1_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_1 [11:11] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800,11,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x800,11)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_1_MASK 0x0000000000000800
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_1_SHIFT 11

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_1 [10:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x700,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_1_MASK 0x0000000000000700
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_1_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_1 [07:07] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80,7,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x80,7)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_1_MASK 0x0000000000000080
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_1_SHIFT 7

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_1 [06:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x70,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_1_MASK 0x0000000000000070
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_1_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_1 [03:03] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8,3,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x8,3)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_1_MASK 0x0000000000000008
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_1_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_1_SHIFT 3

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_1 [02:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_1(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_1(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1,0x7,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_1_MASK 0x0000000000000007
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_1_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_1_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT1_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_2 [63:63] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000000000000000,63,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000000000000000,63)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_2_MASK 0x8000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_2_SHIFT 63

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_2 [62:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_2_MASK 0x7000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_2_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_2 [59:59] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800000000000000,59,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800000000000000,59)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_2_MASK 0x0800000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_2_SHIFT 59

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_2 [58:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_2_MASK 0x0700000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_2_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_2 [55:55] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80000000000000,55,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80000000000000,55)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_2_MASK 0x0080000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_2_SHIFT 55

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_2 [54:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_2_MASK 0x0070000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_2_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_2 [51:51] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000000000000,51,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000000000000,51)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_2_MASK 0x0008000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_2_SHIFT 51

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_2 [50:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_2_MASK 0x0007000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_2_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_2 [47:47] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800000000000,47,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800000000000,47)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_2_MASK 0x0000800000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_2_SHIFT 47

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_2 [46:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_2_MASK 0x0000700000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_2_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_2 [43:43] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80000000000,43,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80000000000,43)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_2_MASK 0x0000080000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_2_SHIFT 43

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_2 [42:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_2_MASK 0x0000070000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_2_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_2 [39:39] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000000000,39,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000000000,39)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_2_MASK 0x0000008000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_2_SHIFT 39

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_2 [38:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_2_MASK 0x0000007000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_2_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_2 [35:35] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800000000,35,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800000000,35)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_2_MASK 0x0000000800000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_2_SHIFT 35

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_2 [34:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_2_MASK 0x0000000700000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_2_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_2 [31:31] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80000000,31,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80000000,31)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_2_MASK 0x0000000080000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_2_SHIFT 31

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_2 [30:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_2_MASK 0x0000000070000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_2_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_2 [27:27] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000000,27,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000000,27)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_2_MASK 0x0000000008000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_2_SHIFT 27

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_2 [26:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_2_MASK 0x0000000007000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_2_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_2 [23:23] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800000,23,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800000,23)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_2_MASK 0x0000000000800000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_2_SHIFT 23

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_2 [22:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_2_MASK 0x0000000000700000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_2_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_2 [19:19] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80000,19,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80000,19)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_2_MASK 0x0000000000080000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_2_SHIFT 19

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_2 [18:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_2_MASK 0x0000000000070000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_2_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_2 [15:15] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000,15,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8000,15)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_2_MASK 0x0000000000008000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_2_SHIFT 15

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_2 [14:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_2_MASK 0x0000000000007000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_2_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_2 [11:11] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800,11,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x800,11)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_2_MASK 0x0000000000000800
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_2_SHIFT 11

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_2 [10:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x700,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_2_MASK 0x0000000000000700
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_2_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_2 [07:07] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80,7,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x80,7)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_2_MASK 0x0000000000000080
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_2_SHIFT 7

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_2 [06:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x70,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_2_MASK 0x0000000000000070
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_2_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_2 [03:03] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8,3,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x8,3)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_2_MASK 0x0000000000000008
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_2_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_2_SHIFT 3

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_2 [02:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_2(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_2(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2,0x7,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_2_MASK 0x0000000000000007
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_2_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_2_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT2_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_3 [63:63] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000000000000000,63,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000000000000000,63)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_3_MASK 0x8000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_3_SHIFT 63

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_3 [62:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_3_MASK 0x7000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_3_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_3 [59:59] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800000000000000,59,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800000000000000,59)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_3_MASK 0x0800000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_3_SHIFT 59

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_3 [58:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_3_MASK 0x0700000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_3_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_3 [55:55] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80000000000000,55,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80000000000000,55)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_3_MASK 0x0080000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_3_SHIFT 55

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_3 [54:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_3_MASK 0x0070000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_3_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_3 [51:51] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000000000000,51,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000000000000,51)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_3_MASK 0x0008000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_3_SHIFT 51

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_3 [50:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_3_MASK 0x0007000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_3_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_3 [47:47] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800000000000,47,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800000000000,47)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_3_MASK 0x0000800000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_3_SHIFT 47

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_3 [46:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_3_MASK 0x0000700000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_3_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_3 [43:43] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80000000000,43,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80000000000,43)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_3_MASK 0x0000080000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_3_SHIFT 43

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_3 [42:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_3_MASK 0x0000070000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_3_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_3 [39:39] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000000000,39,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000000000,39)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_3_MASK 0x0000008000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_3_SHIFT 39

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_3 [38:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_3_MASK 0x0000007000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_3_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_3 [35:35] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800000000,35,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800000000,35)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_3_MASK 0x0000000800000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_3_SHIFT 35

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_3 [34:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_3_MASK 0x0000000700000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_3_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_3 [31:31] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80000000,31,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80000000,31)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_3_MASK 0x0000000080000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_3_SHIFT 31

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_3 [30:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_3_MASK 0x0000000070000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_3_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_3 [27:27] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000000,27,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000000,27)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_3_MASK 0x0000000008000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_3_SHIFT 27

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_3 [26:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_3_MASK 0x0000000007000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_3_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_3 [23:23] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800000,23,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800000,23)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_3_MASK 0x0000000000800000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_3_SHIFT 23

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_3 [22:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_3_MASK 0x0000000000700000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_3_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_3 [19:19] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80000,19,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80000,19)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_3_MASK 0x0000000000080000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_3_SHIFT 19

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_3 [18:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_3_MASK 0x0000000000070000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_3_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_3 [15:15] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000,15,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8000,15)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_3_MASK 0x0000000000008000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_3_SHIFT 15

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_3 [14:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_3_MASK 0x0000000000007000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_3_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_3 [11:11] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800,11,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x800,11)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_3_MASK 0x0000000000000800
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_3_SHIFT 11

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_3 [10:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x700,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_3_MASK 0x0000000000000700
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_3_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_3 [07:07] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80,7,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x80,7)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_3_MASK 0x0000000000000080
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_3_SHIFT 7

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_3 [06:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x70,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_3_MASK 0x0000000000000070
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_3_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_3 [03:03] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8,3,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x8,3)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_3_MASK 0x0000000000000008
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_3_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_3_SHIFT 3

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_3 [02:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_3(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_3(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3,0x7,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_3_MASK 0x0000000000000007
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_3_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_3_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT3_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_4 [63:63] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000000000000000,63,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000000000000000,63)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_4_MASK 0x8000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_4_SHIFT 63

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_4 [62:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_4_MASK 0x7000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_4_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_4 [59:59] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800000000000000,59,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800000000000000,59)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_4_MASK 0x0800000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_4_SHIFT 59

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_4 [58:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_4_MASK 0x0700000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_4_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_4 [55:55] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80000000000000,55,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80000000000000,55)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_4_MASK 0x0080000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_4_SHIFT 55

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_4 [54:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_4_MASK 0x0070000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_4_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_4 [51:51] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000000000000,51,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000000000000,51)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_4_MASK 0x0008000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_4_SHIFT 51

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_4 [50:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_4_MASK 0x0007000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_4_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_4 [47:47] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800000000000,47,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800000000000,47)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_4_MASK 0x0000800000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_4_SHIFT 47

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_4 [46:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_4_MASK 0x0000700000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_4_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_4 [43:43] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80000000000,43,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80000000000,43)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_4_MASK 0x0000080000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_4_SHIFT 43

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_4 [42:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_4_MASK 0x0000070000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_4_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_4 [39:39] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000000000,39,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000000000,39)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_4_MASK 0x0000008000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_4_SHIFT 39

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_4 [38:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_4_MASK 0x0000007000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_4_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_4 [35:35] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800000000,35,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800000000,35)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_4_MASK 0x0000000800000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_4_SHIFT 35

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_4 [34:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_4_MASK 0x0000000700000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_4_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_4 [31:31] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80000000,31,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80000000,31)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_4_MASK 0x0000000080000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_4_SHIFT 31

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_4 [30:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_4_MASK 0x0000000070000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_4_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_4 [27:27] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000000,27,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000000,27)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_4_MASK 0x0000000008000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_4_SHIFT 27

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_4 [26:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_4_MASK 0x0000000007000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_4_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_4 [23:23] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800000,23,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800000,23)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_4_MASK 0x0000000000800000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_4_SHIFT 23

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_4 [22:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_4_MASK 0x0000000000700000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_4_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_4 [19:19] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80000,19,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80000,19)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_4_MASK 0x0000000000080000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_4_SHIFT 19

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_4 [18:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_4_MASK 0x0000000000070000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_4_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_4 [15:15] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000,15,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8000,15)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_4_MASK 0x0000000000008000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_4_SHIFT 15

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_4 [14:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_4_MASK 0x0000000000007000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_4_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_4 [11:11] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800,11,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x800,11)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_4_MASK 0x0000000000000800
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_4_SHIFT 11

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_4 [10:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x700,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_4_MASK 0x0000000000000700
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_4_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_4 [07:07] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80,7,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x80,7)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_4_MASK 0x0000000000000080
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_4_SHIFT 7

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_4 [06:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x70,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_4_MASK 0x0000000000000070
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_4_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_4 [03:03] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8,3,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x8,3)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_4_MASK 0x0000000000000008
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_4_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_4_SHIFT 3

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_4 [02:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_4(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_4(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4,0x7,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_4_MASK 0x0000000000000007
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_4_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_4_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT4_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_5 [63:63] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000000000000000,63,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000000000000000,63)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_5_MASK 0x8000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_5_SHIFT 63

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_5 [62:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_5_MASK 0x7000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_5_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_5 [59:59] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800000000000000,59,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800000000000000,59)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_5_MASK 0x0800000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_5_SHIFT 59

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_5 [58:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_5_MASK 0x0700000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_5_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_5 [55:55] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80000000000000,55,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80000000000000,55)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_5_MASK 0x0080000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_5_SHIFT 55

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_5 [54:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_5_MASK 0x0070000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_5_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_5 [51:51] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000000000000,51,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000000000000,51)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_5_MASK 0x0008000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_5_SHIFT 51

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_5 [50:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_5_MASK 0x0007000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_5_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_5 [47:47] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800000000000,47,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800000000000,47)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_5_MASK 0x0000800000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_5_SHIFT 47

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_5 [46:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_5_MASK 0x0000700000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_5_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_5 [43:43] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80000000000,43,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80000000000,43)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_5_MASK 0x0000080000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_5_SHIFT 43

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_5 [42:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_5_MASK 0x0000070000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_5_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_5 [39:39] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000000000,39,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000000000,39)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_5_MASK 0x0000008000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_5_SHIFT 39

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_5 [38:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_5_MASK 0x0000007000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_5_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_5 [35:35] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800000000,35,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800000000,35)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_5_MASK 0x0000000800000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_5_SHIFT 35

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_5 [34:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_5_MASK 0x0000000700000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_5_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_5 [31:31] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80000000,31,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80000000,31)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_5_MASK 0x0000000080000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_5_SHIFT 31

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_5 [30:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_5_MASK 0x0000000070000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_5_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_5 [27:27] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000000,27,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000000,27)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_5_MASK 0x0000000008000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_5_SHIFT 27

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_5 [26:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_5_MASK 0x0000000007000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_5_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_5 [23:23] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800000,23,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800000,23)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_5_MASK 0x0000000000800000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_5_SHIFT 23

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_5 [22:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_5_MASK 0x0000000000700000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_5_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_5 [19:19] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80000,19,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80000,19)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_5_MASK 0x0000000000080000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_5_SHIFT 19

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_5 [18:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_5_MASK 0x0000000000070000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_5_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_5 [15:15] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000,15,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8000,15)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_5_MASK 0x0000000000008000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_5_SHIFT 15

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_5 [14:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_5_MASK 0x0000000000007000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_5_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_5 [11:11] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800,11,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x800,11)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_5_MASK 0x0000000000000800
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_5_SHIFT 11

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_5 [10:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x700,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_5_MASK 0x0000000000000700
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_5_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_5 [07:07] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80,7,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x80,7)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_5_MASK 0x0000000000000080
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_5_SHIFT 7

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_5 [06:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x70,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_5_MASK 0x0000000000000070
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_5_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_5 [03:03] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8,3,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x8,3)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_5_MASK 0x0000000000000008
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_5_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_5_SHIFT 3

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_5 [02:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_5(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_5(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5,0x7,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_5_MASK 0x0000000000000007
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_5_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_5_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT5_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6
 ***************************************************************************/
/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_6 [63:63] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000000000000000,63,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000000000000000,63)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_6_MASK 0x8000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_6_SHIFT 63

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_6 [62:60] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000000000000000,60,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000000000000000,60)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_6_MASK 0x7000000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_6_SHIFT 60

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_6 [59:59] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800000000000000,59,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800000000000000,59)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_6_MASK 0x0800000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_6_SHIFT 59

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_6 [58:56] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700000000000000,56,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700000000000000,56)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_6_MASK 0x0700000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_6_SHIFT 56

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_6 [55:55] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80000000000000,55,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80000000000000,55)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_6_MASK 0x0080000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_6_SHIFT 55

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_6 [54:52] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70000000000000,52,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70000000000000,52)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_6_MASK 0x0070000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_6_SHIFT 52

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_6 [51:51] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000000000000,51,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000000000000,51)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_6_MASK 0x0008000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_6_SHIFT 51

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_6 [50:48] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000000000000,48,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000000000000,48)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_6_MASK 0x0007000000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_6_SHIFT 48

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_6 [47:47] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800000000000,47,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800000000000,47)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_6_MASK 0x0000800000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_6_SHIFT 47

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_6 [46:44] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700000000000,44,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700000000000,44)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_6_MASK 0x0000700000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_6_SHIFT 44

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_6 [43:43] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80000000000,43,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80000000000,43)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_6_MASK 0x0000080000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_6_SHIFT 43

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_6 [42:40] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70000000000,40,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70000000000,40)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_6_MASK 0x0000070000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_6_SHIFT 40

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_6 [39:39] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000000000,39,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000000000,39)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_6_MASK 0x0000008000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_6_SHIFT 39

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_6 [38:36] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000000000,36,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000000000,36)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_6_MASK 0x0000007000000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_6_SHIFT 36

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_6 [35:35] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800000000,35,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800000000,35)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_6_MASK 0x0000000800000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_6_SHIFT 35

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_6 [34:32] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700000000,32,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700000000,32)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_6_MASK 0x0000000700000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_6_SHIFT 32

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_6 [31:31] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80000000,31,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80000000,31)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_6_MASK 0x0000000080000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_6_SHIFT 31

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_6 [30:28] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70000000,28,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70000000,28)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_6_MASK 0x0000000070000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_6_SHIFT 28

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_6 [27:27] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000000,27,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000000,27)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_6_MASK 0x0000000008000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_6_SHIFT 27

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_6 [26:24] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000000,24,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000000,24)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_6_MASK 0x0000000007000000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_6_SHIFT 24

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_6 [23:23] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800000,23,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800000,23)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_6_MASK 0x0000000000800000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_6_SHIFT 23

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_6 [22:20] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700000,20,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700000,20)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_6_MASK 0x0000000000700000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_6_SHIFT 20

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_6 [19:19] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80000,19,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80000,19)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_6_MASK 0x0000000000080000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_6_SHIFT 19

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_6 [18:16] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70000,16,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70000,16)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_6_MASK 0x0000000000070000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_6_SHIFT 16

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_6 [15:15] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000,15,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8000,15)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_6_MASK 0x0000000000008000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_6_SHIFT 15

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_6 [14:12] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000,12,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7000,12)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_6_MASK 0x0000000000007000
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_6_SHIFT 12

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_6 [11:11] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800,11,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x800,11)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_6_MASK 0x0000000000000800
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_6_SHIFT 11

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_6 [10:08] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700,8,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x700,8)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_6_MASK 0x0000000000000700
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_6_SHIFT 8

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_6 [07:07] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80,7,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x80,7)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_6_MASK 0x0000000000000080
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_6_SHIFT 7

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_6 [06:04] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70,4,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x70,4)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_6_MASK 0x0000000000000070
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_6_SHIFT 4

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_6 [03:03] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8,3,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x8,3)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_6_MASK 0x0000000000000008
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_6_BITS 1
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_6_SHIFT 3

/* switch :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6 :: PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_6 [02:00] */
#define Wr_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_6(x) WriteRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7,0,x)
#define Rd_switch_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_port6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_6(x) ReadRegBits(SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6,0x7,0)
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_6_MASK 0x0000000000000007
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_6_ALIGN 0
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_6_BITS 3
#define SWITCH_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_PORT6_PAGE_91_PN_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP
 ***************************************************************************/
/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15 [63:63] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000000000000000,63,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000000000000000,63)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_MASK 0x8000000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_SHIFT 63

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7 [62:60] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000000000000000,60,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000000000000000,60)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_SHIFT 60

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14 [59:59] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800000000000000,59,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800000000000000,59)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_MASK 0x0800000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_SHIFT 59

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6 [58:56] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700000000000000,56,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700000000000000,56)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_SHIFT 56

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13 [55:55] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80000000000000,55,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80000000000000,55)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_MASK 0x0080000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_SHIFT 55

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5 [54:52] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70000000000000,52,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70000000000000,52)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_SHIFT 52

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12 [51:51] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000000000000,51,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000000000000,51)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_MASK 0x0008000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_SHIFT 51

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4 [50:48] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000000000000,48,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000000000000,48)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_SHIFT 48

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11 [47:47] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800000000000,47,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800000000000,47)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_MASK 0x0000800000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_SHIFT 47

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3 [46:44] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700000000000,44,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700000000000,44)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_SHIFT 44

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10 [43:43] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80000000000,43,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80000000000,43)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_MASK 0x0000080000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_SHIFT 43

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2 [42:40] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70000000000,40,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70000000000,40)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_SHIFT 40

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9 [39:39] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000000000,39,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000000000,39)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_MASK 0x0000008000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_SHIFT 39

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1 [38:36] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000000000,36,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000000000,36)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_SHIFT 36

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8 [35:35] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800000000,35,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800000000,35)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_MASK 0x0000000800000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_SHIFT 35

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0 [34:32] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700000000,32,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700000000,32)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_SHIFT 32

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7 [31:31] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80000000,31,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80000000,31)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_MASK 0x0000000080000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_SHIFT 31

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7 [30:28] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70000000,28,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70000000,28)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_SHIFT 28

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6 [27:27] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000000,27,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000000,27)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_MASK 0x0000000008000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_SHIFT 27

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6 [26:24] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000000,24,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000000,24)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_SHIFT 24

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5 [23:23] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800000,23,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800000,23)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_MASK 0x0000000000800000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_SHIFT 23

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5 [22:20] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700000,20,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700000,20)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_SHIFT 20

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4 [19:19] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80000,19,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80000,19)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_MASK 0x0000000000080000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_SHIFT 19

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4 [18:16] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70000,16,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70000,16)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_SHIFT 16

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3 [15:15] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000,15,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8000,15)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_MASK 0x0000000000008000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_SHIFT 15

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3 [14:12] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000,12,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7000,12)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_SHIFT 12

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2 [11:11] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800,11,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x800,11)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_MASK 0x0000000000000800
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_SHIFT 11

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2 [10:08] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700,8,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x700,8)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_SHIFT 8

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1 [07:07] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80,7,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x80,7)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_MASK 0x0000000000000080
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_SHIFT 7

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1 [06:04] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70,4,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x70,4)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_SHIFT 4

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0 [03:03] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8,3,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x8,3)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_MASK 0x0000000000000008
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_BITS 1
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_SHIFT 3

/* switch :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0 [02:00] */
#define Wr_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0(x) WriteRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7,0,x)
#define Rd_switch_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0(x) ReadRegBits(SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP,0x7,0)
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_ALIGN 0
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_BITS 3
#define SWITCH_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_P7_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP
 ***************************************************************************/
/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15 [63:63] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000000000000000,63,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000000000000000,63)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_MASK 0x8000000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_15_SHIFT 63

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7 [62:60] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000000000000000,60,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000000000000000,60)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_MASK 0x7000000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC7_SHIFT 60

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14 [59:59] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800000000000000,59,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800000000000000,59)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_MASK 0x0800000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_14_SHIFT 59

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6 [58:56] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700000000000000,56,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700000000000000,56)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_MASK 0x0700000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC6_SHIFT 56

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13 [55:55] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80000000000000,55,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80000000000000,55)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_MASK 0x0080000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_13_SHIFT 55

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5 [54:52] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70000000000000,52,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70000000000000,52)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_MASK 0x0070000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC5_SHIFT 52

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12 [51:51] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000000000000,51,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000000000000,51)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_MASK 0x0008000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_12_SHIFT 51

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4 [50:48] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000000000000,48,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000000000000,48)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_MASK 0x0007000000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC4_SHIFT 48

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11 [47:47] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800000000000,47,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800000000000,47)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_MASK 0x0000800000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_11_SHIFT 47

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3 [46:44] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700000000000,44,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700000000000,44)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_MASK 0x0000700000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC3_SHIFT 44

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10 [43:43] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80000000000,43,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80000000000,43)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_MASK 0x0000080000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_10_SHIFT 43

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2 [42:40] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70000000000,40,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70000000000,40)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_MASK 0x0000070000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC2_SHIFT 40

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9 [39:39] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000000000,39,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000000000,39)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_MASK 0x0000008000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_9_SHIFT 39

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1 [38:36] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000000000,36,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000000000,36)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_MASK 0x0000007000000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC1_SHIFT 36

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8 [35:35] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800000000,35,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800000000,35)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_MASK 0x0000000800000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_8_SHIFT 35

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0 [34:32] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700000000,32,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700000000,32)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_MASK 0x0000000700000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV1_TC0_SHIFT 32

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7 [31:31] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80000000,31,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80000000,31)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_MASK 0x0000000080000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_7_SHIFT 31

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7 [30:28] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70000000,28,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70000000,28)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_MASK 0x0000000070000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC7_SHIFT 28

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6 [27:27] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000000,27,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000000,27)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_MASK 0x0000000008000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_6_SHIFT 27

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6 [26:24] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000000,24,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000000,24)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_MASK 0x0000000007000000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC6_SHIFT 24

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5 [23:23] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800000,23,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800000,23)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_MASK 0x0000000000800000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_5_SHIFT 23

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5 [22:20] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700000,20,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700000,20)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_MASK 0x0000000000700000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC5_SHIFT 20

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4 [19:19] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80000,19,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80000,19)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_MASK 0x0000000000080000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_4_SHIFT 19

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4 [18:16] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70000,16,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70000,16)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_MASK 0x0000000000070000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC4_SHIFT 16

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3 [15:15] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000,15,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8000,15)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_MASK 0x0000000000008000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_3_SHIFT 15

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3 [14:12] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000,12,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7000,12)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_MASK 0x0000000000007000
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC3_SHIFT 12

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2 [11:11] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800,11,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x800,11)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_MASK 0x0000000000000800
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_2_SHIFT 11

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2 [10:08] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700,8,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x700,8)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_MASK 0x0000000000000700
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC2_SHIFT 8

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1 [07:07] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80,7,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x80,7)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_MASK 0x0000000000000080
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_1_SHIFT 7

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1 [06:04] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70,4,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x70,4)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_MASK 0x0000000000000070
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC1_SHIFT 4

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0 [03:03] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8,3,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x8,3)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_MASK 0x0000000000000008
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_BITS 1
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_RESERVED_0_SHIFT 3

/* switch :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP :: PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0 [02:00] */
#define Wr_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0(x) WriteRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7,0,x)
#define Rd_switch_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0(x) ReadRegBits(SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP,0x7,0)
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_MASK 0x0000000000000007
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_ALIGN 0
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_BITS 3
#define SWITCH_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_PAGE_91_IMP_EGRESS_PKT_TC2CPCP_MAP_CPCP_FOR_RV0_TC0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_TRREG_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_91_TRREG_REG_SPARE0 :: PAGE_91_TRREG_REG_SPARE0_TRREG_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_91_TRREG_REG_SPARE0_PAGE_91_TRREG_REG_SPARE0_TRREG_REG_SPARE0(x) WriteReg(SWITCH_PAGE_91_TRREG_REG_SPARE0,x)
#define Rd_switch_PAGE_91_TRREG_REG_SPARE0_PAGE_91_TRREG_REG_SPARE0_TRREG_REG_SPARE0(x) ReadReg(SWITCH_PAGE_91_TRREG_REG_SPARE0)
#define SWITCH_PAGE_91_TRREG_REG_SPARE0_PAGE_91_TRREG_REG_SPARE0_TRREG_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_91_TRREG_REG_SPARE0_PAGE_91_TRREG_REG_SPARE0_TRREG_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_91_TRREG_REG_SPARE0_PAGE_91_TRREG_REG_SPARE0_TRREG_REG_SPARE0_BITS 32
#define SWITCH_PAGE_91_TRREG_REG_SPARE0_PAGE_91_TRREG_REG_SPARE0_TRREG_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_91_TRREG_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_91_TRREG_REG_SPARE1 :: PAGE_91_TRREG_REG_SPARE1_TRREG_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_91_TRREG_REG_SPARE1_PAGE_91_TRREG_REG_SPARE1_TRREG_REG_SPARE1(x) WriteReg(SWITCH_PAGE_91_TRREG_REG_SPARE1,x)
#define Rd_switch_PAGE_91_TRREG_REG_SPARE1_PAGE_91_TRREG_REG_SPARE1_TRREG_REG_SPARE1(x) ReadReg(SWITCH_PAGE_91_TRREG_REG_SPARE1)
#define SWITCH_PAGE_91_TRREG_REG_SPARE1_PAGE_91_TRREG_REG_SPARE1_TRREG_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_91_TRREG_REG_SPARE1_PAGE_91_TRREG_REG_SPARE1_TRREG_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_91_TRREG_REG_SPARE1_PAGE_91_TRREG_REG_SPARE1_TRREG_REG_SPARE1_BITS 32
#define SWITCH_PAGE_91_TRREG_REG_SPARE1_PAGE_91_TRREG_REG_SPARE1_TRREG_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_EN_CTRL
 ***************************************************************************/
/* switch :: PAGE_92_EEE_EN_CTRL :: PAGE_92_EEE_EN_CTRL_RESERVED [15:09] */
#define Wr_switch_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_EN_CTRL,0xfe00,9,x)
#define Rd_switch_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_EN_CTRL,0xfe00,9)
#define SWITCH_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_RESERVED_BITS 7
#define SWITCH_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_RESERVED_SHIFT 9

/* switch :: PAGE_92_EEE_EN_CTRL :: PAGE_92_EEE_EN_CTRL_EN_EEE [08:00] */
#define Wr_switch_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_EN_EEE(x) WriteRegBits16(SWITCH_PAGE_92_EEE_EN_CTRL,0x1ff,0,x)
#define Rd_switch_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_EN_EEE(x) ReadRegBits16(SWITCH_PAGE_92_EEE_EN_CTRL,0x1ff,0)
#define SWITCH_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_EN_EEE_MASK 0x01ff
#define SWITCH_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_EN_EEE_ALIGN 0
#define SWITCH_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_EN_EEE_BITS 9
#define SWITCH_PAGE_92_EEE_EN_CTRL_PAGE_92_EEE_EN_CTRL_EN_EEE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_LPI_ASSERT
 ***************************************************************************/
/* switch :: PAGE_92_EEE_LPI_ASSERT :: PAGE_92_EEE_LPI_ASSERT_RESERVED [15:09] */
#define Wr_switch_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_LPI_ASSERT,0xfe00,9,x)
#define Rd_switch_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_LPI_ASSERT,0xfe00,9)
#define SWITCH_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_RESERVED_BITS 7
#define SWITCH_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_RESERVED_SHIFT 9

/* switch :: PAGE_92_EEE_LPI_ASSERT :: PAGE_92_EEE_LPI_ASSERT_LPI_ASSERT [08:00] */
#define Wr_switch_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_LPI_ASSERT(x) WriteRegBits16(SWITCH_PAGE_92_EEE_LPI_ASSERT,0x1ff,0,x)
#define Rd_switch_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_LPI_ASSERT(x) ReadRegBits16(SWITCH_PAGE_92_EEE_LPI_ASSERT,0x1ff,0)
#define SWITCH_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_LPI_ASSERT_MASK 0x01ff
#define SWITCH_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_LPI_ASSERT_ALIGN 0
#define SWITCH_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_LPI_ASSERT_BITS 9
#define SWITCH_PAGE_92_EEE_LPI_ASSERT_PAGE_92_EEE_LPI_ASSERT_LPI_ASSERT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_LPI_INDICATE
 ***************************************************************************/
/* switch :: PAGE_92_EEE_LPI_INDICATE :: PAGE_92_EEE_LPI_INDICATE_RESERVED [15:09] */
#define Wr_switch_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_LPI_INDICATE,0xfe00,9,x)
#define Rd_switch_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_LPI_INDICATE,0xfe00,9)
#define SWITCH_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_RESERVED_BITS 7
#define SWITCH_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_RESERVED_SHIFT 9

/* switch :: PAGE_92_EEE_LPI_INDICATE :: PAGE_92_EEE_LPI_INDICATE_LPI_INDICATE [08:00] */
#define Wr_switch_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_LPI_INDICATE(x) WriteRegBits16(SWITCH_PAGE_92_EEE_LPI_INDICATE,0x1ff,0,x)
#define Rd_switch_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_LPI_INDICATE(x) ReadRegBits16(SWITCH_PAGE_92_EEE_LPI_INDICATE,0x1ff,0)
#define SWITCH_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_LPI_INDICATE_MASK 0x01ff
#define SWITCH_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_LPI_INDICATE_ALIGN 0
#define SWITCH_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_LPI_INDICATE_BITS 9
#define SWITCH_PAGE_92_EEE_LPI_INDICATE_PAGE_92_EEE_LPI_INDICATE_LPI_INDICATE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_RX_IDLE_SYMBOL
 ***************************************************************************/
/* switch :: PAGE_92_EEE_RX_IDLE_SYMBOL :: PAGE_92_EEE_RX_IDLE_SYMBOL_RESERVED [15:09] */
#define Wr_switch_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL,0xfe00,9,x)
#define Rd_switch_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL,0xfe00,9)
#define SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RESERVED_BITS 7
#define SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RESERVED_SHIFT 9

/* switch :: PAGE_92_EEE_RX_IDLE_SYMBOL :: PAGE_92_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL [08:00] */
#define Wr_switch_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL(x) WriteRegBits16(SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL,0x1ff,0,x)
#define Rd_switch_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL(x) ReadRegBits16(SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL,0x1ff,0)
#define SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_MASK 0x01ff
#define SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_ALIGN 0
#define SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_BITS 9
#define SWITCH_PAGE_92_EEE_RX_IDLE_SYMBOL_PAGE_92_EEE_RX_IDLE_SYMBOL_RX_IDLE_SYMBOL_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE
 ***************************************************************************/
/* switch :: PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE :: PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_RESERVED [15:09] */
#define Wr_switch_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE,0xfe00,9,x)
#define Rd_switch_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE,0xfe00,9)
#define SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_RESERVED_BITS 7
#define SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_RESERVED_SHIFT 9

/* switch :: PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE :: PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE [08:00] */
#define Wr_switch_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE(x) WriteRegBits16(SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE,0x1ff,0,x)
#define Rd_switch_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE(x) ReadRegBits16(SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE,0x1ff,0)
#define SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_MASK 0x01ff
#define SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_ALIGN 0
#define SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_BITS 9
#define SWITCH_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_PAGE_92_EEE_LPI_SYMBOL_TX_DISABLE_EEE_LPI_SYMBOL_TX_DISABLE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_PIPELINE_TIMER
 ***************************************************************************/
/* switch :: PAGE_92_EEE_PIPELINE_TIMER :: PAGE_92_EEE_PIPELINE_TIMER_PIPELINE_TIMER [31:00] */
#define Wr_switch_PAGE_92_EEE_PIPELINE_TIMER_PAGE_92_EEE_PIPELINE_TIMER_PIPELINE_TIMER(x) WriteReg(SWITCH_PAGE_92_EEE_PIPELINE_TIMER,x)
#define Rd_switch_PAGE_92_EEE_PIPELINE_TIMER_PAGE_92_EEE_PIPELINE_TIMER_PIPELINE_TIMER(x) ReadReg(SWITCH_PAGE_92_EEE_PIPELINE_TIMER)
#define SWITCH_PAGE_92_EEE_PIPELINE_TIMER_PAGE_92_EEE_PIPELINE_TIMER_PIPELINE_TIMER_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_PIPELINE_TIMER_PAGE_92_EEE_PIPELINE_TIMER_PIPELINE_TIMER_ALIGN 0
#define SWITCH_PAGE_92_EEE_PIPELINE_TIMER_PAGE_92_EEE_PIPELINE_TIMER_PIPELINE_TIMER_BITS 32
#define SWITCH_PAGE_92_EEE_PIPELINE_TIMER_PAGE_92_EEE_PIPELINE_TIMER_PIPELINE_TIMER_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_G_port0
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_G_port0 :: PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_0 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_G_port0_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_0(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT0,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_G_port0_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_0(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT0)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT0_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_0_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT0_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_0_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT0_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_0_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT0_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_G_port1
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_G_port1 :: PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_1 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_G_port1_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_1(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT1,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_G_port1_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_1(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT1)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT1_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_1_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT1_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_1_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT1_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_1_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT1_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_G_port2
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_G_port2 :: PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_2 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_G_port2_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_2(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT2,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_G_port2_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_2(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT2)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT2_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_2_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT2_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_2_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT2_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_2_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT2_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_G_port3
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_G_port3 :: PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_3 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_G_port3_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_3(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT3,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_G_port3_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_3(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT3)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT3_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_3_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT3_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_3_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT3_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_3_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT3_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_G_port4
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_G_port4 :: PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_4 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_G_port4_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_4(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT4,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_G_port4_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_4(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT4)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT4_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_4_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT4_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_4_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT4_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_4_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT4_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_G_port5
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_G_port5 :: PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_5 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_G_port5_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_5(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT5,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_G_port5_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_5(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT5)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT5_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_5_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT5_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_5_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT5_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_5_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT5_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_G_port6
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_G_port6 :: PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_6 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_G_port6_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_6(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT6,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_G_port6_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_6(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT6)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT6_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_6_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT6_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_6_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT6_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_6_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_PORT6_PAGE_92_EEE_SLEEP_TIMER_G_SLEEP_TIMER_G_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_G_P7
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_G_P7 :: PAGE_92_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_G_P7_PAGE_92_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_P7,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_G_P7_PAGE_92_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_P7)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_P7_PAGE_92_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_P7_PAGE_92_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_P7_PAGE_92_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_P7_PAGE_92_EEE_SLEEP_TIMER_G_P7_SLEEP_TIMER_G_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_G_IMP
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_G_IMP :: PAGE_92_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_G_IMP_PAGE_92_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_IMP,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_G_IMP_PAGE_92_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_IMP)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_IMP_PAGE_92_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_IMP_PAGE_92_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_IMP_PAGE_92_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_G_IMP_PAGE_92_EEE_SLEEP_TIMER_G_IMP_SLEEP_TIMER_G_IMP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_H_port0
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_H_port0 :: PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_0 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_H_port0_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_0(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT0,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_H_port0_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_0(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT0)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT0_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_0_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT0_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_0_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT0_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_0_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT0_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_H_port1
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_H_port1 :: PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_1 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_H_port1_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_1(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT1,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_H_port1_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_1(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT1)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT1_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_1_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT1_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_1_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT1_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_1_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT1_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_H_port2
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_H_port2 :: PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_2 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_H_port2_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_2(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT2,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_H_port2_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_2(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT2)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT2_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_2_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT2_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_2_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT2_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_2_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT2_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_H_port3
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_H_port3 :: PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_3 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_H_port3_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_3(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT3,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_H_port3_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_3(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT3)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT3_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_3_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT3_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_3_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT3_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_3_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT3_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_H_port4
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_H_port4 :: PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_4 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_H_port4_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_4(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT4,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_H_port4_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_4(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT4)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT4_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_4_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT4_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_4_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT4_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_4_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT4_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_H_port5
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_H_port5 :: PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_5 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_H_port5_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_5(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT5,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_H_port5_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_5(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT5)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT5_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_5_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT5_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_5_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT5_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_5_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT5_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_H_port6
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_H_port6 :: PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_6 [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_H_port6_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_6(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT6,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_H_port6_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_6(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT6)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT6_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_6_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT6_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_6_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT6_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_6_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_PORT6_PAGE_92_EEE_SLEEP_TIMER_H_SLEEP_TIMER_H_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_H_P7
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_H_P7 :: PAGE_92_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_H_P7_PAGE_92_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_P7,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_H_P7_PAGE_92_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_P7)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_P7_PAGE_92_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_P7_PAGE_92_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_P7_PAGE_92_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_P7_PAGE_92_EEE_SLEEP_TIMER_H_P7_SLEEP_TIMER_H_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_SLEEP_TIMER_H_IMP
 ***************************************************************************/
/* switch :: PAGE_92_EEE_SLEEP_TIMER_H_IMP :: PAGE_92_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP [31:00] */
#define Wr_switch_PAGE_92_EEE_SLEEP_TIMER_H_IMP_PAGE_92_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP(x) WriteReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_IMP,x)
#define Rd_switch_PAGE_92_EEE_SLEEP_TIMER_H_IMP_PAGE_92_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP(x) ReadReg(SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_IMP)
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_IMP_PAGE_92_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_IMP_PAGE_92_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_ALIGN 0
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_IMP_PAGE_92_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_BITS 32
#define SWITCH_PAGE_92_EEE_SLEEP_TIMER_H_IMP_PAGE_92_EEE_SLEEP_TIMER_H_IMP_SLEEP_TIMER_H_IMP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port0
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port0 :: PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_0 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port0_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_0(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT0,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port0_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_0(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT0)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT0_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_0_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT0_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_0_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT0_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_0_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT0_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port1
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port1 :: PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_1 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port1_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_1(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT1,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port1_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_1(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT1)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT1_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_1_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT1_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_1_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT1_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_1_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT1_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port2
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port2 :: PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_2 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port2_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_2(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT2,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port2_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_2(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT2)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT2_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_2_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT2_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_2_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT2_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_2_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT2_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port3
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port3 :: PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_3 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port3_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_3(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT3,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port3_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_3(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT3)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT3_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_3_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT3_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_3_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT3_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_3_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT3_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port4
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port4 :: PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_4 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port4_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_4(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT4,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port4_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_4(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT4)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT4_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_4_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT4_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_4_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT4_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_4_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT4_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port5
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port5 :: PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_5 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port5_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_5(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT5,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port5_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_5(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT5)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT5_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_5_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT5_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_5_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT5_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_5_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT5_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port6
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_G_port6 :: PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_6 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port6_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_6(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT6,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_G_port6_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_6(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT6)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT6_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_6_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT6_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_6_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT6_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_6_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_PORT6_PAGE_92_EEE_MIN_LP_TIMER_G_MIN_LP_TIMER_G_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_G_P7
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_G_P7 :: PAGE_92_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_G_P7_PAGE_92_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_P7,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_G_P7_PAGE_92_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_P7)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_P7_PAGE_92_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_P7_PAGE_92_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_P7_PAGE_92_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_P7_PAGE_92_EEE_MIN_LP_TIMER_G_P7_MIN_LP_TIMER_G_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_G_IMP
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_G_IMP :: PAGE_92_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_IMP,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_IMP)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_PAGE_92_EEE_MIN_LP_TIMER_G_IMP_MIN_LP_TIMER_G_IMP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port0
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port0 :: PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_0 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port0_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_0(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT0,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port0_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_0(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT0)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT0_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_0_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT0_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_0_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT0_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_0_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT0_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port1
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port1 :: PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_1 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port1_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_1(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT1,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port1_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_1(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT1)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT1_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_1_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT1_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_1_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT1_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_1_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT1_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port2
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port2 :: PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_2 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port2_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_2(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT2,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port2_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_2(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT2)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT2_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_2_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT2_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_2_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT2_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_2_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT2_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port3
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port3 :: PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_3 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port3_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_3(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT3,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port3_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_3(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT3)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT3_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_3_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT3_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_3_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT3_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_3_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT3_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port4
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port4 :: PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_4 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port4_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_4(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT4,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port4_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_4(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT4)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT4_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_4_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT4_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_4_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT4_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_4_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT4_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port5
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port5 :: PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_5 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port5_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_5(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT5,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port5_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_5(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT5)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT5_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_5_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT5_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_5_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT5_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_5_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT5_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port6
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_H_port6 :: PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_6 [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port6_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_6(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT6,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_H_port6_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_6(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT6)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT6_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_6_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT6_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_6_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT6_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_6_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_PORT6_PAGE_92_EEE_MIN_LP_TIMER_H_MIN_LP_TIMER_H_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_H_P7
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_H_P7 :: PAGE_92_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_H_P7_PAGE_92_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_P7,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_H_P7_PAGE_92_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_P7)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_P7_PAGE_92_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_P7_PAGE_92_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_P7_PAGE_92_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_P7_PAGE_92_EEE_MIN_LP_TIMER_H_P7_MIN_LP_TIMER_H_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_MIN_LP_TIMER_H_IMP
 ***************************************************************************/
/* switch :: PAGE_92_EEE_MIN_LP_TIMER_H_IMP :: PAGE_92_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP [31:00] */
#define Wr_switch_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP(x) WriteReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_IMP,x)
#define Rd_switch_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP(x) ReadReg(SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_IMP)
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_ALIGN 0
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_BITS 32
#define SWITCH_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_PAGE_92_EEE_MIN_LP_TIMER_H_IMP_MIN_LP_TIMER_H_IMP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_G_port0
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_G_port0 :: PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_0 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_G_port0_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_0(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT0,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_G_port0_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_0(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT0)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT0_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_0_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT0_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_0_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT0_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_0_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT0_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_G_port1
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_G_port1 :: PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_1 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_G_port1_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_1(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT1,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_G_port1_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_1(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT1)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT1_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_1_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT1_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_1_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT1_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_1_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT1_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_G_port2
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_G_port2 :: PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_2 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_G_port2_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_2(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT2,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_G_port2_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_2(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT2)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT2_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_2_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT2_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_2_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT2_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_2_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT2_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_G_port3
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_G_port3 :: PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_3 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_G_port3_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_3(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT3,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_G_port3_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_3(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT3)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT3_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_3_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT3_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_3_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT3_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_3_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT3_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_G_port4
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_G_port4 :: PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_4 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_G_port4_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_4(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT4,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_G_port4_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_4(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT4)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT4_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_4_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT4_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_4_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT4_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_4_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT4_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_G_port5
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_G_port5 :: PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_5 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_G_port5_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_5(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT5,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_G_port5_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_5(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT5)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT5_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_5_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT5_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_5_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT5_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_5_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT5_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_G_port6
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_G_port6 :: PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_6 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_G_port6_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_6(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT6,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_G_port6_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_6(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT6)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT6_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_6_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT6_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_6_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT6_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_6_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_PORT6_PAGE_92_EEE_WAKE_TIMER_G_WAKE_TIMER_G_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_G_P7
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_G_P7 :: PAGE_92_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_G_P7_PAGE_92_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_P7,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_G_P7_PAGE_92_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_P7)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_P7_PAGE_92_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_P7_PAGE_92_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_P7_PAGE_92_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_P7_PAGE_92_EEE_WAKE_TIMER_G_P7_WAKE_TIMER_G_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_G_IMP
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_G_IMP :: PAGE_92_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_G_IMP_PAGE_92_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_IMP,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_G_IMP_PAGE_92_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_G_IMP)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_IMP_PAGE_92_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_IMP_PAGE_92_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_IMP_PAGE_92_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_G_IMP_PAGE_92_EEE_WAKE_TIMER_G_IMP_WAKE_TIMER_G_IMP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_H_port0
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_H_port0 :: PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_0 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_H_port0_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_0(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT0,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_H_port0_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_0(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT0)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT0_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_0_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT0_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_0_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT0_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_0_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT0_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_H_port1
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_H_port1 :: PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_1 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_H_port1_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_1(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT1,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_H_port1_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_1(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT1)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT1_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_1_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT1_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_1_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT1_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_1_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT1_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_H_port2
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_H_port2 :: PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_2 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_H_port2_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_2(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT2,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_H_port2_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_2(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT2)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT2_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_2_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT2_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_2_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT2_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_2_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT2_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_H_port3
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_H_port3 :: PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_3 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_H_port3_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_3(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT3,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_H_port3_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_3(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT3)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT3_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_3_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT3_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_3_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT3_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_3_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT3_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_H_port4
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_H_port4 :: PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_4 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_H_port4_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_4(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT4,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_H_port4_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_4(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT4)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT4_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_4_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT4_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_4_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT4_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_4_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT4_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_H_port5
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_H_port5 :: PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_5 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_H_port5_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_5(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT5,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_H_port5_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_5(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT5)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT5_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_5_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT5_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_5_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT5_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_5_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT5_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_H_port6
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_H_port6 :: PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_6 [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_H_port6_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_6(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT6,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_H_port6_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_6(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT6)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT6_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_6_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT6_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_6_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT6_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_6_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_PORT6_PAGE_92_EEE_WAKE_TIMER_H_WAKE_TIMER_H_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_H_P7
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_H_P7 :: PAGE_92_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_H_P7_PAGE_92_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_P7,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_H_P7_PAGE_92_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_P7)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_P7_PAGE_92_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_P7_PAGE_92_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_P7_PAGE_92_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_P7_PAGE_92_EEE_WAKE_TIMER_H_P7_WAKE_TIMER_H_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_WAKE_TIMER_H_IMP
 ***************************************************************************/
/* switch :: PAGE_92_EEE_WAKE_TIMER_H_IMP :: PAGE_92_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP [15:00] */
#define Wr_switch_PAGE_92_EEE_WAKE_TIMER_H_IMP_PAGE_92_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP(x) WriteReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_IMP,x)
#define Rd_switch_PAGE_92_EEE_WAKE_TIMER_H_IMP_PAGE_92_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP(x) ReadReg16(SWITCH_PAGE_92_EEE_WAKE_TIMER_H_IMP)
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_IMP_PAGE_92_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_MASK 0xffff
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_IMP_PAGE_92_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_ALIGN 0
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_IMP_PAGE_92_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_BITS 16
#define SWITCH_PAGE_92_EEE_WAKE_TIMER_H_IMP_PAGE_92_EEE_WAKE_TIMER_H_IMP_WAKE_TIMER_H_IMP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_GLB_CONG_TH
 ***************************************************************************/
/* switch :: PAGE_92_EEE_GLB_CONG_TH :: PAGE_92_EEE_GLB_CONG_TH_RESERVED [15:11] */
#define Wr_switch_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_GLB_CONG_TH,0xf800,11,x)
#define Rd_switch_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_GLB_CONG_TH,0xf800,11)
#define SWITCH_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_RESERVED_MASK 0xf800
#define SWITCH_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_RESERVED_BITS 5
#define SWITCH_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_RESERVED_SHIFT 11

/* switch :: PAGE_92_EEE_GLB_CONG_TH :: PAGE_92_EEE_GLB_CONG_TH_GLB_CONG_TH [10:00] */
#define Wr_switch_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_GLB_CONG_TH(x) WriteRegBits16(SWITCH_PAGE_92_EEE_GLB_CONG_TH,0x7ff,0,x)
#define Rd_switch_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_GLB_CONG_TH(x) ReadRegBits16(SWITCH_PAGE_92_EEE_GLB_CONG_TH,0x7ff,0)
#define SWITCH_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_GLB_CONG_TH_MASK 0x07ff
#define SWITCH_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_GLB_CONG_TH_ALIGN 0
#define SWITCH_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_GLB_CONG_TH_BITS 11
#define SWITCH_PAGE_92_EEE_GLB_CONG_TH_PAGE_92_EEE_GLB_CONG_TH_GLB_CONG_TH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_TXQ_CONG_TH0
 ***************************************************************************/
/* switch :: PAGE_92_EEE_TXQ_CONG_TH0 :: PAGE_92_EEE_TXQ_CONG_TH0_RESERVED [15:11] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH0,0xf800,11,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH0,0xf800,11)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_RESERVED_MASK 0xf800
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_RESERVED_BITS 5
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_RESERVED_SHIFT 11

/* switch :: PAGE_92_EEE_TXQ_CONG_TH0 :: PAGE_92_EEE_TXQ_CONG_TH0_TXQ_CONG_TH [10:00] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_TXQ_CONG_TH(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH0,0x7ff,0,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_TXQ_CONG_TH(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH0,0x7ff,0)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_TXQ_CONG_TH_MASK 0x07ff
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_TXQ_CONG_TH_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_TXQ_CONG_TH_BITS 11
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH0_PAGE_92_EEE_TXQ_CONG_TH0_TXQ_CONG_TH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_TXQ_CONG_TH1
 ***************************************************************************/
/* switch :: PAGE_92_EEE_TXQ_CONG_TH1 :: PAGE_92_EEE_TXQ_CONG_TH1_RESERVED [15:11] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH1,0xf800,11,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH1,0xf800,11)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_RESERVED_MASK 0xf800
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_RESERVED_BITS 5
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_RESERVED_SHIFT 11

/* switch :: PAGE_92_EEE_TXQ_CONG_TH1 :: PAGE_92_EEE_TXQ_CONG_TH1_TXQ_CONG_TH [10:00] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_TXQ_CONG_TH(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH1,0x7ff,0,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_TXQ_CONG_TH(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH1,0x7ff,0)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_TXQ_CONG_TH_MASK 0x07ff
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_TXQ_CONG_TH_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_TXQ_CONG_TH_BITS 11
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH1_PAGE_92_EEE_TXQ_CONG_TH1_TXQ_CONG_TH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_TXQ_CONG_TH2
 ***************************************************************************/
/* switch :: PAGE_92_EEE_TXQ_CONG_TH2 :: PAGE_92_EEE_TXQ_CONG_TH2_RESERVED [15:11] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH2,0xf800,11,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH2,0xf800,11)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_RESERVED_MASK 0xf800
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_RESERVED_BITS 5
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_RESERVED_SHIFT 11

/* switch :: PAGE_92_EEE_TXQ_CONG_TH2 :: PAGE_92_EEE_TXQ_CONG_TH2_TXQ_CONG_TH [10:00] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_TXQ_CONG_TH(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH2,0x7ff,0,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_TXQ_CONG_TH(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH2,0x7ff,0)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_TXQ_CONG_TH_MASK 0x07ff
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_TXQ_CONG_TH_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_TXQ_CONG_TH_BITS 11
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH2_PAGE_92_EEE_TXQ_CONG_TH2_TXQ_CONG_TH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_TXQ_CONG_TH3
 ***************************************************************************/
/* switch :: PAGE_92_EEE_TXQ_CONG_TH3 :: PAGE_92_EEE_TXQ_CONG_TH3_RESERVED [15:11] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH3,0xf800,11,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH3,0xf800,11)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_RESERVED_MASK 0xf800
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_RESERVED_BITS 5
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_RESERVED_SHIFT 11

/* switch :: PAGE_92_EEE_TXQ_CONG_TH3 :: PAGE_92_EEE_TXQ_CONG_TH3_TXQ_CONG_TH [10:00] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_TXQ_CONG_TH(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH3,0x7ff,0,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_TXQ_CONG_TH(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH3,0x7ff,0)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_TXQ_CONG_TH_MASK 0x07ff
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_TXQ_CONG_TH_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_TXQ_CONG_TH_BITS 11
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH3_PAGE_92_EEE_TXQ_CONG_TH3_TXQ_CONG_TH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_TXQ_CONG_TH4
 ***************************************************************************/
/* switch :: PAGE_92_EEE_TXQ_CONG_TH4 :: PAGE_92_EEE_TXQ_CONG_TH4_RESERVED [15:11] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH4,0xf800,11,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH4,0xf800,11)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_RESERVED_MASK 0xf800
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_RESERVED_BITS 5
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_RESERVED_SHIFT 11

/* switch :: PAGE_92_EEE_TXQ_CONG_TH4 :: PAGE_92_EEE_TXQ_CONG_TH4_TXQ_CONG_TH [10:00] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_TXQ_CONG_TH(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH4,0x7ff,0,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_TXQ_CONG_TH(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH4,0x7ff,0)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_TXQ_CONG_TH_MASK 0x07ff
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_TXQ_CONG_TH_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_TXQ_CONG_TH_BITS 11
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH4_PAGE_92_EEE_TXQ_CONG_TH4_TXQ_CONG_TH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_TXQ_CONG_TH5
 ***************************************************************************/
/* switch :: PAGE_92_EEE_TXQ_CONG_TH5 :: PAGE_92_EEE_TXQ_CONG_TH5_RESERVED [15:11] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH5,0xf800,11,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH5,0xf800,11)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_RESERVED_MASK 0xf800
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_RESERVED_BITS 5
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_RESERVED_SHIFT 11

/* switch :: PAGE_92_EEE_TXQ_CONG_TH5 :: PAGE_92_EEE_TXQ_CONG_TH5_TXQ_CONG_TH [10:00] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_TXQ_CONG_TH(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH5,0x7ff,0,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_TXQ_CONG_TH(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH5,0x7ff,0)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_TXQ_CONG_TH_MASK 0x07ff
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_TXQ_CONG_TH_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_TXQ_CONG_TH_BITS 11
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH5_PAGE_92_EEE_TXQ_CONG_TH5_TXQ_CONG_TH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_TXQ_CONG_TH6
 ***************************************************************************/
/* switch :: PAGE_92_EEE_TXQ_CONG_TH6 :: PAGE_92_EEE_TXQ_CONG_TH6_RESERVED [15:11] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH6,0xf800,11,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH6,0xf800,11)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_RESERVED_MASK 0xf800
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_RESERVED_BITS 5
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_RESERVED_SHIFT 11

/* switch :: PAGE_92_EEE_TXQ_CONG_TH6 :: PAGE_92_EEE_TXQ_CONG_TH6_TXQ_CONG_TH [10:00] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_TXQ_CONG_TH(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH6,0x7ff,0,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_TXQ_CONG_TH(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH6,0x7ff,0)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_MASK 0x07ff
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_BITS 11
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH6_PAGE_92_EEE_TXQ_CONG_TH6_TXQ_CONG_TH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_TXQ_CONG_TH7
 ***************************************************************************/
/* switch :: PAGE_92_EEE_TXQ_CONG_TH7 :: PAGE_92_EEE_TXQ_CONG_TH7_RESERVED [15:11] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_RESERVED(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH7,0xf800,11,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_RESERVED(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH7,0xf800,11)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_RESERVED_MASK 0xf800
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_RESERVED_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_RESERVED_BITS 5
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_RESERVED_SHIFT 11

/* switch :: PAGE_92_EEE_TXQ_CONG_TH7 :: PAGE_92_EEE_TXQ_CONG_TH7_TXQ_CONG_TH [10:00] */
#define Wr_switch_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_TXQ_CONG_TH(x) WriteRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH7,0x7ff,0,x)
#define Rd_switch_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_TXQ_CONG_TH(x) ReadRegBits16(SWITCH_PAGE_92_EEE_TXQ_CONG_TH7,0x7ff,0)
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_MASK 0x07ff
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_ALIGN 0
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_BITS 11
#define SWITCH_PAGE_92_EEE_TXQ_CONG_TH7_PAGE_92_EEE_TXQ_CONG_TH7_TXQ_CONG_TH_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_CTL_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_92_EEE_CTL_REG_SPARE0 :: PAGE_92_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_92_EEE_CTL_REG_SPARE0_PAGE_92_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0(x) WriteReg(SWITCH_PAGE_92_EEE_CTL_REG_SPARE0,x)
#define Rd_switch_PAGE_92_EEE_CTL_REG_SPARE0_PAGE_92_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0(x) ReadReg(SWITCH_PAGE_92_EEE_CTL_REG_SPARE0)
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE0_PAGE_92_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE0_PAGE_92_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE0_PAGE_92_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_BITS 32
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE0_PAGE_92_EEE_CTL_REG_SPARE0_EEE_CTL_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_CTL_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_92_EEE_CTL_REG_SPARE1 :: PAGE_92_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_92_EEE_CTL_REG_SPARE1_PAGE_92_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1(x) WriteReg(SWITCH_PAGE_92_EEE_CTL_REG_SPARE1,x)
#define Rd_switch_PAGE_92_EEE_CTL_REG_SPARE1_PAGE_92_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1(x) ReadReg(SWITCH_PAGE_92_EEE_CTL_REG_SPARE1)
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE1_PAGE_92_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE1_PAGE_92_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE1_PAGE_92_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_BITS 32
#define SWITCH_PAGE_92_EEE_CTL_REG_SPARE1_PAGE_92_EEE_CTL_REG_SPARE1_EEE_CTL_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_DEBUG
 ***************************************************************************/
/* switch :: PAGE_92_EEE_DEBUG :: PAGE_92_EEE_DEBUG_RESERVED [07:02] */
#define Wr_switch_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_RESERVED(x) WriteRegBits(SWITCH_PAGE_92_EEE_DEBUG,0xfc,2,x)
#define Rd_switch_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_RESERVED(x) ReadRegBits(SWITCH_PAGE_92_EEE_DEBUG,0xfc,2)
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_RESERVED_MASK   0xfc
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_RESERVED_ALIGN  0
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_RESERVED_BITS   6
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_RESERVED_SHIFT  2

/* switch :: PAGE_92_EEE_DEBUG :: PAGE_92_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX [01:01] */
#define Wr_switch_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX(x) WriteRegBits(SWITCH_PAGE_92_EEE_DEBUG,0x2,1,x)
#define Rd_switch_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX(x) ReadRegBits(SWITCH_PAGE_92_EEE_DEBUG,0x2,1)
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_MASK 0x02
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_ALIGN 0
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_BITS 1
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EXIT_LPI_FLOW_CON_TX_SHIFT 1

/* switch :: PAGE_92_EEE_DEBUG :: PAGE_92_EEE_DEBUG_DIS_EMPTY_FLOW_CON [00:00] */
#define Wr_switch_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EMPTY_FLOW_CON(x) WriteRegBits(SWITCH_PAGE_92_EEE_DEBUG,0x1,0,x)
#define Rd_switch_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EMPTY_FLOW_CON(x) ReadRegBits(SWITCH_PAGE_92_EEE_DEBUG,0x1,0)
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EMPTY_FLOW_CON_MASK 0x01
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EMPTY_FLOW_CON_ALIGN 0
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EMPTY_FLOW_CON_BITS 1
#define SWITCH_PAGE_92_EEE_DEBUG_PAGE_92_EEE_DEBUG_DIS_EMPTY_FLOW_CON_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_LINK_DLY_TIMER
 ***************************************************************************/
/* switch :: PAGE_92_EEE_LINK_DLY_TIMER :: PAGE_92_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER [31:00] */
#define Wr_switch_PAGE_92_EEE_LINK_DLY_TIMER_PAGE_92_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER(x) WriteReg(SWITCH_PAGE_92_EEE_LINK_DLY_TIMER,x)
#define Rd_switch_PAGE_92_EEE_LINK_DLY_TIMER_PAGE_92_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER(x) ReadReg(SWITCH_PAGE_92_EEE_LINK_DLY_TIMER)
#define SWITCH_PAGE_92_EEE_LINK_DLY_TIMER_PAGE_92_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_MASK 0xffffffff
#define SWITCH_PAGE_92_EEE_LINK_DLY_TIMER_PAGE_92_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_ALIGN 0
#define SWITCH_PAGE_92_EEE_LINK_DLY_TIMER_PAGE_92_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_BITS 32
#define SWITCH_PAGE_92_EEE_LINK_DLY_TIMER_PAGE_92_EEE_LINK_DLY_TIMER_LINK_DLY_TIMER_SHIFT 0


/****************************************************************************
 * switch :: PAGE_92_EEE_STATE
 ***************************************************************************/
/* switch :: PAGE_92_EEE_STATE :: PAGE_92_EEE_STATE_RESERVED [31:27] */
#define Wr_switch_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_RESERVED(x) WriteRegBits(SWITCH_PAGE_92_EEE_STATE,0xf8000000,27,x)
#define Rd_switch_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_RESERVED(x) ReadRegBits(SWITCH_PAGE_92_EEE_STATE,0xf8000000,27)
#define SWITCH_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_RESERVED_MASK   0xf8000000
#define SWITCH_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_RESERVED_ALIGN  0
#define SWITCH_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_RESERVED_BITS   5
#define SWITCH_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_RESERVED_SHIFT  27

/* switch :: PAGE_92_EEE_STATE :: PAGE_92_EEE_STATE_EEE_STATE [26:00] */
#define Wr_switch_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_EEE_STATE(x) WriteRegBits(SWITCH_PAGE_92_EEE_STATE,0x7ffffff,0,x)
#define Rd_switch_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_EEE_STATE(x) ReadRegBits(SWITCH_PAGE_92_EEE_STATE,0x7ffffff,0)
#define SWITCH_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_EEE_STATE_MASK  0x07ffffff
#define SWITCH_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_EEE_STATE_ALIGN 0
#define SWITCH_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_EEE_STATE_BITS  27
#define SWITCH_PAGE_92_EEE_STATE_PAGE_92_EEE_STATE_EEE_STATE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_CONTROL
 ***************************************************************************/
/* switch :: PAGE_95_RED_CONTROL :: PAGE_95_RED_CONTROL_RESERVED [15:09] */
#define Wr_switch_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_95_RED_CONTROL,0xfe00,9,x)
#define Rd_switch_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_95_RED_CONTROL,0xfe00,9)
#define SWITCH_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RESERVED_BITS 7
#define SWITCH_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RESERVED_SHIFT 9

/* switch :: PAGE_95_RED_CONTROL :: PAGE_95_RED_CONTROL_RED_EN [08:00] */
#define Wr_switch_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RED_EN(x) WriteRegBits16(SWITCH_PAGE_95_RED_CONTROL,0x1ff,0,x)
#define Rd_switch_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RED_EN(x) ReadRegBits16(SWITCH_PAGE_95_RED_CONTROL,0x1ff,0)
#define SWITCH_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RED_EN_MASK 0x01ff
#define SWITCH_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RED_EN_ALIGN 0
#define SWITCH_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RED_EN_BITS 9
#define SWITCH_PAGE_95_RED_CONTROL_PAGE_95_RED_CONTROL_RED_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_TC2RED_PROFILE_TABLE
 ***************************************************************************/
/* switch :: PAGE_95_TC2RED_PROFILE_TABLE :: PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD [15:15] */
#define Wr_switch_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD(x) WriteRegBits16(SWITCH_PAGE_95_TC2RED_PROFILE_TABLE,0x8000,15,x)
#define Rd_switch_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD(x) ReadRegBits16(SWITCH_PAGE_95_TC2RED_PROFILE_TABLE,0x8000,15)
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_MASK 0x8000
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_ALIGN 0
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_BITS 1
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_WR_RD_SHIFT 15

/* switch :: PAGE_95_TC2RED_PROFILE_TABLE :: PAGE_95_TC2RED_PROFILE_TABLE_RESERVED [14:13] */
#define Wr_switch_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_RESERVED(x) WriteRegBits16(SWITCH_PAGE_95_TC2RED_PROFILE_TABLE,0x6000,13,x)
#define Rd_switch_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_RESERVED(x) ReadRegBits16(SWITCH_PAGE_95_TC2RED_PROFILE_TABLE,0x6000,13)
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_RESERVED_MASK 0x6000
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_RESERVED_BITS 2
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_RESERVED_SHIFT 13

/* switch :: PAGE_95_TC2RED_PROFILE_TABLE :: PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR [12:04] */
#define Wr_switch_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR(x) WriteRegBits16(SWITCH_PAGE_95_TC2RED_PROFILE_TABLE,0x1ff0,4,x)
#define Rd_switch_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR(x) ReadRegBits16(SWITCH_PAGE_95_TC2RED_PROFILE_TABLE,0x1ff0,4)
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_MASK 0x1ff0
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_ALIGN 0
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_BITS 9
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_ADDR_SHIFT 4

/* switch :: PAGE_95_TC2RED_PROFILE_TABLE :: PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA [03:00] */
#define Wr_switch_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA(x) WriteRegBits16(SWITCH_PAGE_95_TC2RED_PROFILE_TABLE,0xf,0,x)
#define Rd_switch_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA(x) ReadRegBits16(SWITCH_PAGE_95_TC2RED_PROFILE_TABLE,0xf,0)
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_MASK 0x000f
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_ALIGN 0
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_BITS 4
#define SWITCH_PAGE_95_TC2RED_PROFILE_TABLE_PAGE_95_TC2RED_PROFILE_TABLE_TC2RED_TABLE_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_EGRESS_BYPASS
 ***************************************************************************/
/* switch :: PAGE_95_RED_EGRESS_BYPASS :: PAGE_95_RED_EGRESS_BYPASS_RESERVED [15:09] */
#define Wr_switch_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RESERVED(x) WriteRegBits16(SWITCH_PAGE_95_RED_EGRESS_BYPASS,0xfe00,9,x)
#define Rd_switch_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RESERVED(x) ReadRegBits16(SWITCH_PAGE_95_RED_EGRESS_BYPASS,0xfe00,9)
#define SWITCH_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RESERVED_BITS 7
#define SWITCH_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RESERVED_SHIFT 9

/* switch :: PAGE_95_RED_EGRESS_BYPASS :: PAGE_95_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS [08:00] */
#define Wr_switch_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS(x) WriteRegBits16(SWITCH_PAGE_95_RED_EGRESS_BYPASS,0x1ff,0,x)
#define Rd_switch_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS(x) ReadRegBits16(SWITCH_PAGE_95_RED_EGRESS_BYPASS,0x1ff,0)
#define SWITCH_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_MASK 0x01ff
#define SWITCH_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_ALIGN 0
#define SWITCH_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_BITS 9
#define SWITCH_PAGE_95_RED_EGRESS_BYPASS_PAGE_95_RED_EGRESS_BYPASS_RED_EGRESS_BYPASS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_AQD_CONTROL
 ***************************************************************************/
/* switch :: PAGE_95_RED_AQD_CONTROL :: PAGE_95_RED_AQD_CONTROL_RESERVED_2 [15:12] */
#define Wr_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_2(x) WriteRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0xf000,12,x)
#define Rd_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_2(x) ReadRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0xf000,12)
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_2_MASK 0xf000
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_2_ALIGN 0
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_2_BITS 4
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_2_SHIFT 12

/* switch :: PAGE_95_RED_AQD_CONTROL :: PAGE_95_RED_AQD_CONTROL_AQD_PERIOD [11:08] */
#define Wr_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_PERIOD(x) WriteRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0xf00,8,x)
#define Rd_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_PERIOD(x) ReadRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0xf00,8)
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_PERIOD_MASK 0x0f00
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_PERIOD_ALIGN 0
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_PERIOD_BITS 4
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_PERIOD_SHIFT 8

/* switch :: PAGE_95_RED_AQD_CONTROL :: PAGE_95_RED_AQD_CONTROL_RESERVED_1 [07:06] */
#define Wr_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_1(x) WriteRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0xc0,6,x)
#define Rd_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_1(x) ReadRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0xc0,6)
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_1_MASK 0x00c0
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_1_BITS 2
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_1_SHIFT 6

/* switch :: PAGE_95_RED_AQD_CONTROL :: PAGE_95_RED_AQD_CONTROL_AQD_RST [05:05] */
#define Wr_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_RST(x) WriteRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0x20,5,x)
#define Rd_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_RST(x) ReadRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0x20,5)
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_RST_MASK 0x0020
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_RST_ALIGN 0
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_RST_BITS 1
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_AQD_RST_SHIFT 5

/* switch :: PAGE_95_RED_AQD_CONTROL :: PAGE_95_RED_AQD_CONTROL_RED_FAST_CORR [04:04] */
#define Wr_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RED_FAST_CORR(x) WriteRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0x10,4,x)
#define Rd_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RED_FAST_CORR(x) ReadRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0x10,4)
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RED_FAST_CORR_MASK 0x0010
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RED_FAST_CORR_ALIGN 0
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RED_FAST_CORR_BITS 1
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RED_FAST_CORR_SHIFT 4

/* switch :: PAGE_95_RED_AQD_CONTROL :: PAGE_95_RED_AQD_CONTROL_RESERVED_0 [03:00] */
#define Wr_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_0(x) WriteRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0xf,0,x)
#define Rd_switch_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_0(x) ReadRegBits16(SWITCH_PAGE_95_RED_AQD_CONTROL,0xf,0)
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_0_MASK 0x000f
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_0_BITS 4
#define SWITCH_PAGE_95_RED_AQD_CONTROL_PAGE_95_RED_AQD_CONTROL_RESERVED_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_EXPONENT
 ***************************************************************************/
/* switch :: PAGE_95_RED_EXPONENT :: PAGE_95_RED_EXPONENT_RESERVED [15:08] */
#define Wr_switch_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RESERVED(x) WriteRegBits16(SWITCH_PAGE_95_RED_EXPONENT,0xff00,8,x)
#define Rd_switch_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RESERVED(x) ReadRegBits16(SWITCH_PAGE_95_RED_EXPONENT,0xff00,8)
#define SWITCH_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RESERVED_MASK 0xff00
#define SWITCH_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RESERVED_BITS 8
#define SWITCH_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RESERVED_SHIFT 8

/* switch :: PAGE_95_RED_EXPONENT :: PAGE_95_RED_EXPONENT_RED_EXPONENT [07:00] */
#define Wr_switch_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RED_EXPONENT(x) WriteRegBits16(SWITCH_PAGE_95_RED_EXPONENT,0xff,0,x)
#define Rd_switch_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RED_EXPONENT(x) ReadRegBits16(SWITCH_PAGE_95_RED_EXPONENT,0xff,0)
#define SWITCH_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RED_EXPONENT_MASK 0x00ff
#define SWITCH_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RED_EXPONENT_ALIGN 0
#define SWITCH_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RED_EXPONENT_BITS 8
#define SWITCH_PAGE_95_RED_EXPONENT_PAGE_95_RED_EXPONENT_RED_EXPONENT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_DROP_ADD_TO_MIB
 ***************************************************************************/
/* switch :: PAGE_95_RED_DROP_ADD_TO_MIB :: PAGE_95_RED_DROP_ADD_TO_MIB_RESERVED [15:09] */
#define Wr_switch_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RESERVED(x) WriteRegBits16(SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB,0xfe00,9,x)
#define Rd_switch_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RESERVED(x) ReadRegBits16(SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB,0xfe00,9)
#define SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RESERVED_BITS 7
#define SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RESERVED_SHIFT 9

/* switch :: PAGE_95_RED_DROP_ADD_TO_MIB :: PAGE_95_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB [08:00] */
#define Wr_switch_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB(x) WriteRegBits16(SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB,0x1ff,0,x)
#define Rd_switch_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB(x) ReadRegBits16(SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB,0x1ff,0)
#define SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_MASK 0x01ff
#define SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_ALIGN 0
#define SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_BITS 9
#define SWITCH_PAGE_95_RED_DROP_ADD_TO_MIB_PAGE_95_RED_DROP_ADD_TO_MIB_RED_DROP_ADD_TO_MIB_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_DEFAULT
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_DEFAULT :: PAGE_95_RED_PROFILE_DEFAULT_RESERVED [31:04] */
#define Wr_switch_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_DEFAULT,0xfffffff0,4,x)
#define Rd_switch_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_DEFAULT,0xfffffff0,4)
#define SWITCH_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RESERVED_MASK 0xfffffff0
#define SWITCH_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RESERVED_BITS 28
#define SWITCH_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RESERVED_SHIFT 4

/* switch :: PAGE_95_RED_PROFILE_DEFAULT :: PAGE_95_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT [03:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_DEFAULT,0xf,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_DEFAULT,0xf,0)
#define SWITCH_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_MASK 0x0000000f
#define SWITCH_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_DEFAULT_PAGE_95_RED_PROFILE_DEFAULT_RED_PROFILE_DEFAULT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_WRED_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_95_WRED_REG_SPARE0 :: PAGE_95_WRED_REG_SPARE0_WRED_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_95_WRED_REG_SPARE0_PAGE_95_WRED_REG_SPARE0_WRED_REG_SPARE0(x) WriteReg(SWITCH_PAGE_95_WRED_REG_SPARE0,x)
#define Rd_switch_PAGE_95_WRED_REG_SPARE0_PAGE_95_WRED_REG_SPARE0_WRED_REG_SPARE0(x) ReadReg(SWITCH_PAGE_95_WRED_REG_SPARE0)
#define SWITCH_PAGE_95_WRED_REG_SPARE0_PAGE_95_WRED_REG_SPARE0_WRED_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_95_WRED_REG_SPARE0_PAGE_95_WRED_REG_SPARE0_WRED_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_95_WRED_REG_SPARE0_PAGE_95_WRED_REG_SPARE0_WRED_REG_SPARE0_BITS 32
#define SWITCH_PAGE_95_WRED_REG_SPARE0_PAGE_95_WRED_REG_SPARE0_WRED_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_WRED_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_95_WRED_REG_SPARE1 :: PAGE_95_WRED_REG_SPARE1_WRED_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_95_WRED_REG_SPARE1_PAGE_95_WRED_REG_SPARE1_WRED_REG_SPARE1(x) WriteReg(SWITCH_PAGE_95_WRED_REG_SPARE1,x)
#define Rd_switch_PAGE_95_WRED_REG_SPARE1_PAGE_95_WRED_REG_SPARE1_WRED_REG_SPARE1(x) ReadReg(SWITCH_PAGE_95_WRED_REG_SPARE1)
#define SWITCH_PAGE_95_WRED_REG_SPARE1_PAGE_95_WRED_REG_SPARE1_WRED_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_95_WRED_REG_SPARE1_PAGE_95_WRED_REG_SPARE1_WRED_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_95_WRED_REG_SPARE1_PAGE_95_WRED_REG_SPARE1_WRED_REG_SPARE1_BITS 32
#define SWITCH_PAGE_95_WRED_REG_SPARE1_PAGE_95_WRED_REG_SPARE1_WRED_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_0
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_0 :: PAGE_95_RED_PROFILE_0_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_0,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_0,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_0 :: PAGE_95_RED_PROFILE_0_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_0,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_0,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_0 :: PAGE_95_RED_PROFILE_0_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_0,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_0,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_0 :: PAGE_95_RED_PROFILE_0_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_0,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_0,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_0_PAGE_95_RED_PROFILE_0_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_1
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_1 :: PAGE_95_RED_PROFILE_1_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_1,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_1,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_1 :: PAGE_95_RED_PROFILE_1_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_1,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_1,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_1 :: PAGE_95_RED_PROFILE_1_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_1,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_1,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_1 :: PAGE_95_RED_PROFILE_1_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_1,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_1,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_1_PAGE_95_RED_PROFILE_1_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_2
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_2 :: PAGE_95_RED_PROFILE_2_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_2,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_2,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_2 :: PAGE_95_RED_PROFILE_2_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_2,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_2,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_2 :: PAGE_95_RED_PROFILE_2_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_2,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_2,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_2 :: PAGE_95_RED_PROFILE_2_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_2,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_2,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_2_PAGE_95_RED_PROFILE_2_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_3
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_3 :: PAGE_95_RED_PROFILE_3_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_3,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_3,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_3 :: PAGE_95_RED_PROFILE_3_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_3,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_3,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_3 :: PAGE_95_RED_PROFILE_3_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_3,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_3,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_3 :: PAGE_95_RED_PROFILE_3_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_3,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_3,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_3_PAGE_95_RED_PROFILE_3_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_4
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_4 :: PAGE_95_RED_PROFILE_4_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_4,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_4,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_4 :: PAGE_95_RED_PROFILE_4_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_4,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_4,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_4 :: PAGE_95_RED_PROFILE_4_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_4,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_4,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_4 :: PAGE_95_RED_PROFILE_4_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_4,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_4,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_4_PAGE_95_RED_PROFILE_4_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_5
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_5 :: PAGE_95_RED_PROFILE_5_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_5,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_5,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_5 :: PAGE_95_RED_PROFILE_5_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_5,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_5,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_5 :: PAGE_95_RED_PROFILE_5_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_5,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_5,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_5 :: PAGE_95_RED_PROFILE_5_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_5,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_5,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_5_PAGE_95_RED_PROFILE_5_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_6
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_6 :: PAGE_95_RED_PROFILE_6_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_6,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_6,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_6 :: PAGE_95_RED_PROFILE_6_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_6,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_6,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_6 :: PAGE_95_RED_PROFILE_6_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_6,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_6,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_6 :: PAGE_95_RED_PROFILE_6_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_6,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_6,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_6_PAGE_95_RED_PROFILE_6_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_7
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_7 :: PAGE_95_RED_PROFILE_7_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_7,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_7,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_7 :: PAGE_95_RED_PROFILE_7_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_7,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_7,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_7 :: PAGE_95_RED_PROFILE_7_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_7,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_7,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_7 :: PAGE_95_RED_PROFILE_7_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_7,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_7,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_7_PAGE_95_RED_PROFILE_7_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_8
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_8 :: PAGE_95_RED_PROFILE_8_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_8,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_8,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_8 :: PAGE_95_RED_PROFILE_8_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_8,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_8,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_8 :: PAGE_95_RED_PROFILE_8_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_8,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_8,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_8 :: PAGE_95_RED_PROFILE_8_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_8,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_8,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_8_PAGE_95_RED_PROFILE_8_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_9
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_9 :: PAGE_95_RED_PROFILE_9_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_9,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_9,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_9 :: PAGE_95_RED_PROFILE_9_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_9,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_9,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_9 :: PAGE_95_RED_PROFILE_9_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_9,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_9,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_9 :: PAGE_95_RED_PROFILE_9_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_9,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_9,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_9_PAGE_95_RED_PROFILE_9_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_10
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_10 :: PAGE_95_RED_PROFILE_10_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_10,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_10,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_10 :: PAGE_95_RED_PROFILE_10_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_10,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_10,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_10 :: PAGE_95_RED_PROFILE_10_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_10,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_10,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_10 :: PAGE_95_RED_PROFILE_10_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_10,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_10,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_10_PAGE_95_RED_PROFILE_10_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_11
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_11 :: PAGE_95_RED_PROFILE_11_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_11,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_11,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_11 :: PAGE_95_RED_PROFILE_11_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_11,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_11,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_11 :: PAGE_95_RED_PROFILE_11_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_11,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_11,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_11 :: PAGE_95_RED_PROFILE_11_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_11,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_11,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_11_PAGE_95_RED_PROFILE_11_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_12
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_12 :: PAGE_95_RED_PROFILE_12_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_12,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_12,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_12 :: PAGE_95_RED_PROFILE_12_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_12,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_12,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_12 :: PAGE_95_RED_PROFILE_12_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_12,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_12,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_12 :: PAGE_95_RED_PROFILE_12_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_12,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_12,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_12_PAGE_95_RED_PROFILE_12_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_13
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_13 :: PAGE_95_RED_PROFILE_13_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_13,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_13,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_13 :: PAGE_95_RED_PROFILE_13_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_13,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_13,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_13 :: PAGE_95_RED_PROFILE_13_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_13,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_13,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_13 :: PAGE_95_RED_PROFILE_13_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_13,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_13,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_13_PAGE_95_RED_PROFILE_13_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_14
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_14 :: PAGE_95_RED_PROFILE_14_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_14,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_14,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_14 :: PAGE_95_RED_PROFILE_14_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_14,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_14,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_14 :: PAGE_95_RED_PROFILE_14_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_14,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_14,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_14 :: PAGE_95_RED_PROFILE_14_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_14,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_14,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_14_PAGE_95_RED_PROFILE_14_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_PROFILE_15
 ***************************************************************************/
/* switch :: PAGE_95_RED_PROFILE_15 :: PAGE_95_RED_PROFILE_15_RESERVED [31:26] */
#define Wr_switch_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RESERVED(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_15,0xfc000000,26,x)
#define Rd_switch_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RESERVED(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_15,0xfc000000,26)
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RESERVED_MASK 0xfc000000
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RESERVED_BITS 6
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RESERVED_SHIFT 26

/* switch :: PAGE_95_RED_PROFILE_15 :: PAGE_95_RED_PROFILE_15_RED_DROP_PROB [25:22] */
#define Wr_switch_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_DROP_PROB(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_15,0x3c00000,22,x)
#define Rd_switch_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_DROP_PROB(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_15,0x3c00000,22)
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_DROP_PROB_MASK 0x03c00000
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_DROP_PROB_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_DROP_PROB_BITS 4
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_DROP_PROB_SHIFT 22

/* switch :: PAGE_95_RED_PROFILE_15 :: PAGE_95_RED_PROFILE_15_RED_MAX_THD [21:11] */
#define Wr_switch_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MAX_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_15,0x3ff800,11,x)
#define Rd_switch_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MAX_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_15,0x3ff800,11)
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MAX_THD_MASK 0x003ff800
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MAX_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MAX_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MAX_THD_SHIFT 11

/* switch :: PAGE_95_RED_PROFILE_15 :: PAGE_95_RED_PROFILE_15_RED_MIN_THD [10:00] */
#define Wr_switch_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MIN_THD(x) WriteRegBits(SWITCH_PAGE_95_RED_PROFILE_15,0x7ff,0,x)
#define Rd_switch_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MIN_THD(x) ReadRegBits(SWITCH_PAGE_95_RED_PROFILE_15,0x7ff,0)
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MIN_THD_MASK 0x000007ff
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MIN_THD_ALIGN 0
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MIN_THD_BITS 11
#define SWITCH_PAGE_95_RED_PROFILE_15_PAGE_95_RED_PROFILE_15_RED_MIN_THD_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_RED_DROP_CNTR_RST
 ***************************************************************************/
/* switch :: PAGE_95_RED_DROP_CNTR_RST :: PAGE_95_RED_DROP_CNTR_RST_RESERVED [15:09] */
#define Wr_switch_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RESERVED(x) WriteRegBits16(SWITCH_PAGE_95_RED_DROP_CNTR_RST,0xfe00,9,x)
#define Rd_switch_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RESERVED(x) ReadRegBits16(SWITCH_PAGE_95_RED_DROP_CNTR_RST,0xfe00,9)
#define SWITCH_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RESERVED_ALIGN 0
#define SWITCH_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RESERVED_BITS 7
#define SWITCH_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RESERVED_SHIFT 9

/* switch :: PAGE_95_RED_DROP_CNTR_RST :: PAGE_95_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST [08:00] */
#define Wr_switch_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST(x) WriteRegBits16(SWITCH_PAGE_95_RED_DROP_CNTR_RST,0x1ff,0,x)
#define Rd_switch_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST(x) ReadRegBits16(SWITCH_PAGE_95_RED_DROP_CNTR_RST,0x1ff,0)
#define SWITCH_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_MASK 0x01ff
#define SWITCH_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_ALIGN 0
#define SWITCH_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_BITS 9
#define SWITCH_PAGE_95_RED_DROP_CNTR_RST_PAGE_95_RED_DROP_CNTR_RST_RED_DROP_CNTR_RST_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port0
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port0 :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_0 [31:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port0_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_0(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT0,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port0_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_0(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT0)
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT0_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_0_MASK 0xffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT0_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_0_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT0_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_0_BITS 32
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT0_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port1
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port1 :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_1 [31:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port1_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_1(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT1,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port1_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_1(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT1)
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT1_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_1_MASK 0xffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT1_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_1_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT1_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_1_BITS 32
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT1_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port2
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port2 :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_2 [31:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port2_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_2(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT2,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port2_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_2(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT2)
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT2_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_2_MASK 0xffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT2_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_2_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT2_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_2_BITS 32
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT2_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port3
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port3 :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_3 [31:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port3_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_3(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT3,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port3_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_3(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT3)
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT3_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_3_MASK 0xffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT3_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_3_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT3_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_3_BITS 32
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT3_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port4
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port4 :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_4 [31:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port4_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_4(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT4,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port4_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_4(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT4)
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT4_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_4_MASK 0xffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT4_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_4_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT4_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_4_BITS 32
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT4_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port5
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port5 :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_5 [31:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port5_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_5(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT5,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port5_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_5(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT5)
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT5_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_5_MASK 0xffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT5_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_5_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT5_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_5_BITS 32
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT5_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port6
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port6 :: PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_6 [31:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port6_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_6(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT6,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_port6_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_6(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT6)
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT6_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_6_MASK 0xffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT6_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_6_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT6_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_6_BITS 32
#define SWITCH_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_PORT6_PAGE_95_PN_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_P7_PORT_RED_PKT_DROP_CNTR
 ***************************************************************************/
/* switch :: PAGE_95_P7_PORT_RED_PKT_DROP_CNTR :: PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR [31:00] */
#define Wr_switch_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR(x) WriteReg(SWITCH_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR,x)
#define Rd_switch_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR(x) ReadReg(SWITCH_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR)
#define SWITCH_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_MASK 0xffffffff
#define SWITCH_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_ALIGN 0
#define SWITCH_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_BITS 32
#define SWITCH_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_PAGE_95_P7_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR
 ***************************************************************************/
/* switch :: PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR :: PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR [31:00] */
#define Wr_switch_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR(x) WriteReg(SWITCH_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR,x)
#define Rd_switch_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR(x) ReadReg(SWITCH_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR)
#define SWITCH_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_MASK 0xffffffff
#define SWITCH_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_ALIGN 0
#define SWITCH_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_BITS 32
#define SWITCH_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_PAGE_95_IMP_PORT_RED_PKT_DROP_CNTR_RED_PKT_DROP_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port0
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port0 :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_0 [63:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port0_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_0(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT0,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port0_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_0(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT0)
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT0_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_0_MASK 0xffffffffffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT0_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_0_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT0_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_0_BITS 64
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT0_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port1
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port1 :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_1 [63:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port1_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_1(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT1,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port1_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_1(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT1)
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT1_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_1_MASK 0xffffffffffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT1_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_1_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT1_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_1_BITS 64
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT1_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port2
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port2 :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_2 [63:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port2_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_2(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT2,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port2_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_2(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT2)
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT2_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_2_MASK 0xffffffffffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT2_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_2_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT2_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_2_BITS 64
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT2_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port3
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port3 :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_3 [63:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port3_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_3(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT3,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port3_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_3(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT3)
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT3_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_3_MASK 0xffffffffffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT3_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_3_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT3_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_3_BITS 64
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT3_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port4
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port4 :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_4 [63:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port4_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_4(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT4,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port4_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_4(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT4)
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT4_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_4_MASK 0xffffffffffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT4_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_4_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT4_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_4_BITS 64
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT4_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port5
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port5 :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_5 [63:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port5_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_5(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT5,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port5_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_5(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT5)
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT5_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_5_MASK 0xffffffffffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT5_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_5_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT5_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_5_BITS 64
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT5_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port6
 ***************************************************************************/
/* switch :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port6 :: PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_6 [63:00] */
#define Wr_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port6_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_6(x) WriteReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT6,x)
#define Rd_switch_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_port6_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_6(x) ReadReg(SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT6)
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT6_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_6_MASK 0xffffffffffffffff
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT6_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_6_ALIGN 0
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT6_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_6_BITS 64
#define SWITCH_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_PORT6_PAGE_95_PN_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR
 ***************************************************************************/
/* switch :: PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR :: PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR [63:00] */
#define Wr_switch_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR(x) WriteReg(SWITCH_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR,x)
#define Rd_switch_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR(x) ReadReg(SWITCH_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR)
#define SWITCH_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_MASK 0xffffffffffffffff
#define SWITCH_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_ALIGN 0
#define SWITCH_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_BITS 64
#define SWITCH_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_PAGE_95_P7_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR
 ***************************************************************************/
/* switch :: PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR :: PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR [63:00] */
#define Wr_switch_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR(x) WriteReg(SWITCH_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR,x)
#define Rd_switch_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR(x) ReadReg(SWITCH_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR)
#define SWITCH_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_MASK 0xffffffffffffffff
#define SWITCH_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_ALIGN 0
#define SWITCH_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_BITS 64
#define SWITCH_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_PAGE_95_IMP_PORT_RED_BYTE_DROP_CNTR_RED_BYTE_DROP_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_ACC
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_RD_STS [31:28] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RD_STS(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0xf0000000,28,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RD_STS(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0xf0000000,28)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RD_STS_MASK         0xf0000000
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RD_STS_ALIGN        0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RD_STS_BITS         4
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RD_STS_SHIFT        28

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_SERCH_STS [27:27] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_SERCH_STS(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0x8000000,27,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_SERCH_STS(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0x8000000,27)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_SERCH_STS_MASK      0x08000000
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_SERCH_STS_ALIGN     0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_SERCH_STS_BITS      1
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_SERCH_STS_SHIFT     27

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_RESERVED_1 [26:24] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0x7000000,24,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0x7000000,24)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_1_MASK     0x07000000
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_1_ALIGN    0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_1_BITS     3
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_1_SHIFT    24

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_XCESS_ADDR [23:16] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_XCESS_ADDR(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0xff0000,16,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_XCESS_ADDR(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0xff0000,16)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_XCESS_ADDR_MASK     0x00ff0000
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_XCESS_ADDR_ALIGN    0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_XCESS_ADDR_BITS     8
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_XCESS_ADDR_SHIFT    16

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_TCAM_RST [15:15] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_TCAM_RST(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0x8000,15,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_TCAM_RST(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0x8000,15)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_TCAM_RST_MASK       0x00008000
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_TCAM_RST_ALIGN      0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_TCAM_RST_BITS       1
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_TCAM_RST_SHIFT      15

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_RAM_SEL [14:10] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RAM_SEL(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0x7c00,10,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RAM_SEL(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0x7c00,10)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RAM_SEL_MASK        0x00007c00
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RAM_SEL_ALIGN       0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RAM_SEL_BITS        5
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RAM_SEL_SHIFT       10

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_RESERVED_0 [09:06] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0x3c0,6,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0x3c0,6)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_0_MASK     0x000003c0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_0_ALIGN    0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_0_BITS     4
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_RESERVED_0_SHIFT    6

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_KEY_0_1_RAW_ENC [05:05] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_KEY_0_1_RAW_ENC(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0x20,5,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_KEY_0_1_RAW_ENC(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0x20,5)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_KEY_0_1_RAW_ENC_MASK 0x00000020
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_KEY_0_1_RAW_ENC_ALIGN 0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_KEY_0_1_RAW_ENC_BITS 1
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_KEY_0_1_RAW_ENC_SHIFT 5

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_CFP_RAM_CLEAR [04:04] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_CFP_RAM_CLEAR(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0x10,4,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_CFP_RAM_CLEAR(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0x10,4)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_CFP_RAM_CLEAR_MASK  0x00000010
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_CFP_RAM_CLEAR_ALIGN 0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_CFP_RAM_CLEAR_BITS  1
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_CFP_RAM_CLEAR_SHIFT 4

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_OP_SEL [03:01] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_SEL(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0xe,1,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_SEL(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0xe,1)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_SEL_MASK         0x0000000e
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_SEL_ALIGN        0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_SEL_BITS         3
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_SEL_SHIFT        1

/* switch :: PAGE_A0_CFP_ACC :: PAGE_A0_CFP_ACC_OP_STR_DONE [00:00] */
#define Wr_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_STR_DONE(x) WriteRegBits(SWITCH_PAGE_A0_CFP_ACC,0x1,0,x)
#define Rd_switch_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_STR_DONE(x) ReadRegBits(SWITCH_PAGE_A0_CFP_ACC,0x1,0)
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_STR_DONE_MASK    0x00000001
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_STR_DONE_ALIGN   0
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_STR_DONE_BITS    1
#define SWITCH_PAGE_A0_CFP_ACC_PAGE_A0_CFP_ACC_OP_STR_DONE_SHIFT   0


/****************************************************************************
 * switch :: PAGE_A0_RATE_METER_GLOBAL_CTL
 ***************************************************************************/
/* switch :: PAGE_A0_RATE_METER_GLOBAL_CTL :: PAGE_A0_RATE_METER_GLOBAL_CTL_RESERVED [15:03] */
#define Wr_switch_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RESERVED(x) WriteRegBits16(SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL,0xfff8,3,x)
#define Rd_switch_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RESERVED(x) ReadRegBits16(SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL,0xfff8,3)
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RESERVED_MASK 0xfff8
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RESERVED_BITS 13
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RESERVED_SHIFT 3

/* switch :: PAGE_A0_RATE_METER_GLOBAL_CTL :: PAGE_A0_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN [02:02] */
#define Wr_switch_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN(x) WriteRegBits16(SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL,0x4,2,x)
#define Rd_switch_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN(x) ReadRegBits16(SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL,0x4,2)
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_MASK 0x0004
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_BITS 1
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_RATE_REFRESH_EN_SHIFT 2

/* switch :: PAGE_A0_RATE_METER_GLOBAL_CTL :: PAGE_A0_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR [01:00] */
#define Wr_switch_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR(x) WriteRegBits16(SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL,0x3,0,x)
#define Rd_switch_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR(x) ReadRegBits16(SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL,0x3,0)
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_MASK 0x0003
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_BITS 2
#define SWITCH_PAGE_A0_RATE_METER_GLOBAL_CTL_PAGE_A0_RATE_METER_GLOBAL_CTL_PKT_LEN_CORR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_DATA0
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_DATA0 :: PAGE_A0_CFP_DATA0_TCAM_DATA [31:00] */
#define Wr_switch_PAGE_A0_CFP_DATA0_PAGE_A0_CFP_DATA0_TCAM_DATA(x) WriteReg(SWITCH_PAGE_A0_CFP_DATA0,x)
#define Rd_switch_PAGE_A0_CFP_DATA0_PAGE_A0_CFP_DATA0_TCAM_DATA(x) ReadReg(SWITCH_PAGE_A0_CFP_DATA0)
#define SWITCH_PAGE_A0_CFP_DATA0_PAGE_A0_CFP_DATA0_TCAM_DATA_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_DATA0_PAGE_A0_CFP_DATA0_TCAM_DATA_ALIGN 0
#define SWITCH_PAGE_A0_CFP_DATA0_PAGE_A0_CFP_DATA0_TCAM_DATA_BITS  32
#define SWITCH_PAGE_A0_CFP_DATA0_PAGE_A0_CFP_DATA0_TCAM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_DATA1
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_DATA1 :: PAGE_A0_CFP_DATA1_TCAM_DATA [31:00] */
#define Wr_switch_PAGE_A0_CFP_DATA1_PAGE_A0_CFP_DATA1_TCAM_DATA(x) WriteReg(SWITCH_PAGE_A0_CFP_DATA1,x)
#define Rd_switch_PAGE_A0_CFP_DATA1_PAGE_A0_CFP_DATA1_TCAM_DATA(x) ReadReg(SWITCH_PAGE_A0_CFP_DATA1)
#define SWITCH_PAGE_A0_CFP_DATA1_PAGE_A0_CFP_DATA1_TCAM_DATA_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_DATA1_PAGE_A0_CFP_DATA1_TCAM_DATA_ALIGN 0
#define SWITCH_PAGE_A0_CFP_DATA1_PAGE_A0_CFP_DATA1_TCAM_DATA_BITS  32
#define SWITCH_PAGE_A0_CFP_DATA1_PAGE_A0_CFP_DATA1_TCAM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_DATA2
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_DATA2 :: PAGE_A0_CFP_DATA2_TCAM_DATA [31:00] */
#define Wr_switch_PAGE_A0_CFP_DATA2_PAGE_A0_CFP_DATA2_TCAM_DATA(x) WriteReg(SWITCH_PAGE_A0_CFP_DATA2,x)
#define Rd_switch_PAGE_A0_CFP_DATA2_PAGE_A0_CFP_DATA2_TCAM_DATA(x) ReadReg(SWITCH_PAGE_A0_CFP_DATA2)
#define SWITCH_PAGE_A0_CFP_DATA2_PAGE_A0_CFP_DATA2_TCAM_DATA_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_DATA2_PAGE_A0_CFP_DATA2_TCAM_DATA_ALIGN 0
#define SWITCH_PAGE_A0_CFP_DATA2_PAGE_A0_CFP_DATA2_TCAM_DATA_BITS  32
#define SWITCH_PAGE_A0_CFP_DATA2_PAGE_A0_CFP_DATA2_TCAM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_DATA3
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_DATA3 :: PAGE_A0_CFP_DATA3_TCAM_DATA [31:00] */
#define Wr_switch_PAGE_A0_CFP_DATA3_PAGE_A0_CFP_DATA3_TCAM_DATA(x) WriteReg(SWITCH_PAGE_A0_CFP_DATA3,x)
#define Rd_switch_PAGE_A0_CFP_DATA3_PAGE_A0_CFP_DATA3_TCAM_DATA(x) ReadReg(SWITCH_PAGE_A0_CFP_DATA3)
#define SWITCH_PAGE_A0_CFP_DATA3_PAGE_A0_CFP_DATA3_TCAM_DATA_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_DATA3_PAGE_A0_CFP_DATA3_TCAM_DATA_ALIGN 0
#define SWITCH_PAGE_A0_CFP_DATA3_PAGE_A0_CFP_DATA3_TCAM_DATA_BITS  32
#define SWITCH_PAGE_A0_CFP_DATA3_PAGE_A0_CFP_DATA3_TCAM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_DATA4
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_DATA4 :: PAGE_A0_CFP_DATA4_TCAM_DATA [31:00] */
#define Wr_switch_PAGE_A0_CFP_DATA4_PAGE_A0_CFP_DATA4_TCAM_DATA(x) WriteReg(SWITCH_PAGE_A0_CFP_DATA4,x)
#define Rd_switch_PAGE_A0_CFP_DATA4_PAGE_A0_CFP_DATA4_TCAM_DATA(x) ReadReg(SWITCH_PAGE_A0_CFP_DATA4)
#define SWITCH_PAGE_A0_CFP_DATA4_PAGE_A0_CFP_DATA4_TCAM_DATA_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_DATA4_PAGE_A0_CFP_DATA4_TCAM_DATA_ALIGN 0
#define SWITCH_PAGE_A0_CFP_DATA4_PAGE_A0_CFP_DATA4_TCAM_DATA_BITS  32
#define SWITCH_PAGE_A0_CFP_DATA4_PAGE_A0_CFP_DATA4_TCAM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_DATA5
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_DATA5 :: PAGE_A0_CFP_DATA5_TCAM_DATA [31:00] */
#define Wr_switch_PAGE_A0_CFP_DATA5_PAGE_A0_CFP_DATA5_TCAM_DATA(x) WriteReg(SWITCH_PAGE_A0_CFP_DATA5,x)
#define Rd_switch_PAGE_A0_CFP_DATA5_PAGE_A0_CFP_DATA5_TCAM_DATA(x) ReadReg(SWITCH_PAGE_A0_CFP_DATA5)
#define SWITCH_PAGE_A0_CFP_DATA5_PAGE_A0_CFP_DATA5_TCAM_DATA_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_DATA5_PAGE_A0_CFP_DATA5_TCAM_DATA_ALIGN 0
#define SWITCH_PAGE_A0_CFP_DATA5_PAGE_A0_CFP_DATA5_TCAM_DATA_BITS  32
#define SWITCH_PAGE_A0_CFP_DATA5_PAGE_A0_CFP_DATA5_TCAM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_DATA6
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_DATA6 :: PAGE_A0_CFP_DATA6_TCAM_DATA [31:00] */
#define Wr_switch_PAGE_A0_CFP_DATA6_PAGE_A0_CFP_DATA6_TCAM_DATA(x) WriteReg(SWITCH_PAGE_A0_CFP_DATA6,x)
#define Rd_switch_PAGE_A0_CFP_DATA6_PAGE_A0_CFP_DATA6_TCAM_DATA(x) ReadReg(SWITCH_PAGE_A0_CFP_DATA6)
#define SWITCH_PAGE_A0_CFP_DATA6_PAGE_A0_CFP_DATA6_TCAM_DATA_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_DATA6_PAGE_A0_CFP_DATA6_TCAM_DATA_ALIGN 0
#define SWITCH_PAGE_A0_CFP_DATA6_PAGE_A0_CFP_DATA6_TCAM_DATA_BITS  32
#define SWITCH_PAGE_A0_CFP_DATA6_PAGE_A0_CFP_DATA6_TCAM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_DATA7
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_DATA7 :: reserved0 [31:08] */
#define SWITCH_PAGE_A0_CFP_DATA7_RESERVED0_MASK                    0xffffff00
#define SWITCH_PAGE_A0_CFP_DATA7_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_A0_CFP_DATA7_RESERVED0_BITS                    24
#define SWITCH_PAGE_A0_CFP_DATA7_RESERVED0_SHIFT                   8

/* switch :: PAGE_A0_CFP_DATA7 :: PAGE_A0_CFP_DATA7_TCAM_DATA [07:00] */
#define Wr_switch_PAGE_A0_CFP_DATA7_PAGE_A0_CFP_DATA7_TCAM_DATA(x) WriteRegBits(SWITCH_PAGE_A0_CFP_DATA7,0xff,0,x)
#define Rd_switch_PAGE_A0_CFP_DATA7_PAGE_A0_CFP_DATA7_TCAM_DATA(x) ReadRegBits(SWITCH_PAGE_A0_CFP_DATA7,0xff,0)
#define SWITCH_PAGE_A0_CFP_DATA7_PAGE_A0_CFP_DATA7_TCAM_DATA_MASK  0x000000ff
#define SWITCH_PAGE_A0_CFP_DATA7_PAGE_A0_CFP_DATA7_TCAM_DATA_ALIGN 0
#define SWITCH_PAGE_A0_CFP_DATA7_PAGE_A0_CFP_DATA7_TCAM_DATA_BITS  8
#define SWITCH_PAGE_A0_CFP_DATA7_PAGE_A0_CFP_DATA7_TCAM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_MASK0
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_MASK0 :: PAGE_A0_CFP_MASK0_TCAM_MASK [31:00] */
#define Wr_switch_PAGE_A0_CFP_MASK0_PAGE_A0_CFP_MASK0_TCAM_MASK(x) WriteReg(SWITCH_PAGE_A0_CFP_MASK0,x)
#define Rd_switch_PAGE_A0_CFP_MASK0_PAGE_A0_CFP_MASK0_TCAM_MASK(x) ReadReg(SWITCH_PAGE_A0_CFP_MASK0)
#define SWITCH_PAGE_A0_CFP_MASK0_PAGE_A0_CFP_MASK0_TCAM_MASK_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_MASK0_PAGE_A0_CFP_MASK0_TCAM_MASK_ALIGN 0
#define SWITCH_PAGE_A0_CFP_MASK0_PAGE_A0_CFP_MASK0_TCAM_MASK_BITS  32
#define SWITCH_PAGE_A0_CFP_MASK0_PAGE_A0_CFP_MASK0_TCAM_MASK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_MASK1
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_MASK1 :: PAGE_A0_CFP_MASK1_TCAM_MASK [31:00] */
#define Wr_switch_PAGE_A0_CFP_MASK1_PAGE_A0_CFP_MASK1_TCAM_MASK(x) WriteReg(SWITCH_PAGE_A0_CFP_MASK1,x)
#define Rd_switch_PAGE_A0_CFP_MASK1_PAGE_A0_CFP_MASK1_TCAM_MASK(x) ReadReg(SWITCH_PAGE_A0_CFP_MASK1)
#define SWITCH_PAGE_A0_CFP_MASK1_PAGE_A0_CFP_MASK1_TCAM_MASK_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_MASK1_PAGE_A0_CFP_MASK1_TCAM_MASK_ALIGN 0
#define SWITCH_PAGE_A0_CFP_MASK1_PAGE_A0_CFP_MASK1_TCAM_MASK_BITS  32
#define SWITCH_PAGE_A0_CFP_MASK1_PAGE_A0_CFP_MASK1_TCAM_MASK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_MASK2
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_MASK2 :: PAGE_A0_CFP_MASK2_TCAM_MASK [31:00] */
#define Wr_switch_PAGE_A0_CFP_MASK2_PAGE_A0_CFP_MASK2_TCAM_MASK(x) WriteReg(SWITCH_PAGE_A0_CFP_MASK2,x)
#define Rd_switch_PAGE_A0_CFP_MASK2_PAGE_A0_CFP_MASK2_TCAM_MASK(x) ReadReg(SWITCH_PAGE_A0_CFP_MASK2)
#define SWITCH_PAGE_A0_CFP_MASK2_PAGE_A0_CFP_MASK2_TCAM_MASK_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_MASK2_PAGE_A0_CFP_MASK2_TCAM_MASK_ALIGN 0
#define SWITCH_PAGE_A0_CFP_MASK2_PAGE_A0_CFP_MASK2_TCAM_MASK_BITS  32
#define SWITCH_PAGE_A0_CFP_MASK2_PAGE_A0_CFP_MASK2_TCAM_MASK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_MASK3
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_MASK3 :: PAGE_A0_CFP_MASK3_TCAM_MASK [31:00] */
#define Wr_switch_PAGE_A0_CFP_MASK3_PAGE_A0_CFP_MASK3_TCAM_MASK(x) WriteReg(SWITCH_PAGE_A0_CFP_MASK3,x)
#define Rd_switch_PAGE_A0_CFP_MASK3_PAGE_A0_CFP_MASK3_TCAM_MASK(x) ReadReg(SWITCH_PAGE_A0_CFP_MASK3)
#define SWITCH_PAGE_A0_CFP_MASK3_PAGE_A0_CFP_MASK3_TCAM_MASK_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_MASK3_PAGE_A0_CFP_MASK3_TCAM_MASK_ALIGN 0
#define SWITCH_PAGE_A0_CFP_MASK3_PAGE_A0_CFP_MASK3_TCAM_MASK_BITS  32
#define SWITCH_PAGE_A0_CFP_MASK3_PAGE_A0_CFP_MASK3_TCAM_MASK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_MASK4
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_MASK4 :: PAGE_A0_CFP_MASK4_TCAM_MASK [31:00] */
#define Wr_switch_PAGE_A0_CFP_MASK4_PAGE_A0_CFP_MASK4_TCAM_MASK(x) WriteReg(SWITCH_PAGE_A0_CFP_MASK4,x)
#define Rd_switch_PAGE_A0_CFP_MASK4_PAGE_A0_CFP_MASK4_TCAM_MASK(x) ReadReg(SWITCH_PAGE_A0_CFP_MASK4)
#define SWITCH_PAGE_A0_CFP_MASK4_PAGE_A0_CFP_MASK4_TCAM_MASK_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_MASK4_PAGE_A0_CFP_MASK4_TCAM_MASK_ALIGN 0
#define SWITCH_PAGE_A0_CFP_MASK4_PAGE_A0_CFP_MASK4_TCAM_MASK_BITS  32
#define SWITCH_PAGE_A0_CFP_MASK4_PAGE_A0_CFP_MASK4_TCAM_MASK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_MASK5
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_MASK5 :: PAGE_A0_CFP_MASK5_TCAM_MASK [31:00] */
#define Wr_switch_PAGE_A0_CFP_MASK5_PAGE_A0_CFP_MASK5_TCAM_MASK(x) WriteReg(SWITCH_PAGE_A0_CFP_MASK5,x)
#define Rd_switch_PAGE_A0_CFP_MASK5_PAGE_A0_CFP_MASK5_TCAM_MASK(x) ReadReg(SWITCH_PAGE_A0_CFP_MASK5)
#define SWITCH_PAGE_A0_CFP_MASK5_PAGE_A0_CFP_MASK5_TCAM_MASK_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_MASK5_PAGE_A0_CFP_MASK5_TCAM_MASK_ALIGN 0
#define SWITCH_PAGE_A0_CFP_MASK5_PAGE_A0_CFP_MASK5_TCAM_MASK_BITS  32
#define SWITCH_PAGE_A0_CFP_MASK5_PAGE_A0_CFP_MASK5_TCAM_MASK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_MASK6
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_MASK6 :: PAGE_A0_CFP_MASK6_TCAM_MASK [31:00] */
#define Wr_switch_PAGE_A0_CFP_MASK6_PAGE_A0_CFP_MASK6_TCAM_MASK(x) WriteReg(SWITCH_PAGE_A0_CFP_MASK6,x)
#define Rd_switch_PAGE_A0_CFP_MASK6_PAGE_A0_CFP_MASK6_TCAM_MASK(x) ReadReg(SWITCH_PAGE_A0_CFP_MASK6)
#define SWITCH_PAGE_A0_CFP_MASK6_PAGE_A0_CFP_MASK6_TCAM_MASK_MASK  0xffffffff
#define SWITCH_PAGE_A0_CFP_MASK6_PAGE_A0_CFP_MASK6_TCAM_MASK_ALIGN 0
#define SWITCH_PAGE_A0_CFP_MASK6_PAGE_A0_CFP_MASK6_TCAM_MASK_BITS  32
#define SWITCH_PAGE_A0_CFP_MASK6_PAGE_A0_CFP_MASK6_TCAM_MASK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_MASK7
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_MASK7 :: reserved0 [31:08] */
#define SWITCH_PAGE_A0_CFP_MASK7_RESERVED0_MASK                    0xffffff00
#define SWITCH_PAGE_A0_CFP_MASK7_RESERVED0_ALIGN                   0
#define SWITCH_PAGE_A0_CFP_MASK7_RESERVED0_BITS                    24
#define SWITCH_PAGE_A0_CFP_MASK7_RESERVED0_SHIFT                   8

/* switch :: PAGE_A0_CFP_MASK7 :: PAGE_A0_CFP_MASK7_TCAM_MASK [07:00] */
#define Wr_switch_PAGE_A0_CFP_MASK7_PAGE_A0_CFP_MASK7_TCAM_MASK(x) WriteRegBits(SWITCH_PAGE_A0_CFP_MASK7,0xff,0,x)
#define Rd_switch_PAGE_A0_CFP_MASK7_PAGE_A0_CFP_MASK7_TCAM_MASK(x) ReadRegBits(SWITCH_PAGE_A0_CFP_MASK7,0xff,0)
#define SWITCH_PAGE_A0_CFP_MASK7_PAGE_A0_CFP_MASK7_TCAM_MASK_MASK  0x000000ff
#define SWITCH_PAGE_A0_CFP_MASK7_PAGE_A0_CFP_MASK7_TCAM_MASK_ALIGN 0
#define SWITCH_PAGE_A0_CFP_MASK7_PAGE_A0_CFP_MASK7_TCAM_MASK_BITS  8
#define SWITCH_PAGE_A0_CFP_MASK7_PAGE_A0_CFP_MASK7_TCAM_MASK_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_ACT_POL_DATA0
 ***************************************************************************/
/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_NEW_DSCP_IB [31:26] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_DSCP_IB(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0xfc000000,26,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_DSCP_IB(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0xfc000000,26)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_DSCP_IB_MASK 0xfc000000
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_DSCP_IB_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_DSCP_IB_BITS 6
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_DSCP_IB_SHIFT 26

/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB [25:24] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x3000000,24,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x3000000,24)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_MASK 0x03000000
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_BITS 2
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_FWRD_MAP_IB_SHIFT 24

/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_DST_MAP_IB [23:14] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_DST_MAP_IB(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0xffc000,14,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_DST_MAP_IB(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0xffc000,14)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_DST_MAP_IB_MASK 0x00ffc000
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_DST_MAP_IB_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_DST_MAP_IB_BITS 10
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_DST_MAP_IB_SHIFT 14

/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_CHANGE_TC [13:13] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_TC(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x2000,13,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_TC(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x2000,13)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_TC_MASK 0x00002000
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_TC_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_TC_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_CHANGE_TC_SHIFT 13

/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_NEW_TC [12:10] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_TC(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x1c00,10,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_TC(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x1c00,10)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_TC_MASK 0x00001c00
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_TC_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_TC_BITS 3
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_NEW_TC_SHIFT 10

/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_LOOP_BK_EN [09:09] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_LOOP_BK_EN(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x200,9,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_LOOP_BK_EN(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x200,9)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_LOOP_BK_EN_MASK 0x00000200
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_LOOP_BK_EN_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_LOOP_BK_EN_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_LOOP_BK_EN_SHIFT 9

/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_REASON_CODE [08:03] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_REASON_CODE(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x1f8,3,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_REASON_CODE(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x1f8,3)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_REASON_CODE_MASK 0x000001f8
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_REASON_CODE_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_REASON_CODE_BITS 6
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_REASON_CODE_SHIFT 3

/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_STP_BYP [02:02] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_STP_BYP(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x4,2,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_STP_BYP(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x4,2)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_STP_BYP_MASK 0x00000004
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_STP_BYP_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_STP_BYP_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_STP_BYP_SHIFT 2

/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_EAP_BYP [01:01] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_EAP_BYP(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x2,1,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_EAP_BYP(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x2,1)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_EAP_BYP_MASK 0x00000002
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_EAP_BYP_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_EAP_BYP_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_EAP_BYP_SHIFT 1

/* switch :: PAGE_A0_ACT_POL_DATA0 :: PAGE_A0_ACT_POL_DATA0_VLAN_BYP [00:00] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_VLAN_BYP(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x1,0,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_VLAN_BYP(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA0,0x1,0)
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_VLAN_BYP_MASK 0x00000001
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_VLAN_BYP_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_VLAN_BYP_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA0_PAGE_A0_ACT_POL_DATA0_VLAN_BYP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_ACT_POL_DATA1
 ***************************************************************************/
/* switch :: PAGE_A0_ACT_POL_DATA1 :: PAGE_A0_ACT_POL_DATA1_RED_DEFAULT [31:31] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_RED_DEFAULT(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x80000000,31,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_RED_DEFAULT(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x80000000,31)
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_RED_DEFAULT_MASK 0x80000000
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_RED_DEFAULT_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_RED_DEFAULT_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_RED_DEFAULT_SHIFT 31

/* switch :: PAGE_A0_ACT_POL_DATA1 :: PAGE_A0_ACT_POL_DATA1_NEW_COLOR [30:29] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_COLOR(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x60000000,29,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_COLOR(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x60000000,29)
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_COLOR_MASK 0x60000000
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_COLOR_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_COLOR_BITS 2
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_COLOR_SHIFT 29

/* switch :: PAGE_A0_ACT_POL_DATA1 :: PAGE_A0_ACT_POL_DATA1_CHANGE_COLOR [28:28] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_COLOR(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x10000000,28,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_COLOR(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x10000000,28)
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_COLOR_MASK 0x10000000
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_COLOR_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_COLOR_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_COLOR_SHIFT 28

/* switch :: PAGE_A0_ACT_POL_DATA1 :: PAGE_A0_ACT_POL_DATA1_CHAIN_ID [27:20] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHAIN_ID(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0xff00000,20,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHAIN_ID(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0xff00000,20)
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHAIN_ID_MASK 0x0ff00000
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHAIN_ID_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHAIN_ID_BITS 8
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHAIN_ID_SHIFT 20

/* switch :: PAGE_A0_ACT_POL_DATA1 :: PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_OB [19:19] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_OB(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x80000,19,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_OB(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x80000,19)
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_OB_MASK 0x00080000
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_OB_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_OB_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_OB_SHIFT 19

/* switch :: PAGE_A0_ACT_POL_DATA1 :: PAGE_A0_ACT_POL_DATA1_NEW_DSCP_OB [18:13] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_DSCP_OB(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x7e000,13,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_DSCP_OB(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x7e000,13)
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_DSCP_OB_MASK 0x0007e000
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_DSCP_OB_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_DSCP_OB_BITS 6
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_NEW_DSCP_OB_SHIFT 13

/* switch :: PAGE_A0_ACT_POL_DATA1 :: PAGE_A0_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB [12:11] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x1800,11,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x1800,11)
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_MASK 0x00001800
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_BITS 2
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_FWRD_MAP_OB_SHIFT 11

/* switch :: PAGE_A0_ACT_POL_DATA1 :: PAGE_A0_ACT_POL_DATA1_DST_MAP_OB [10:01] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_DST_MAP_OB(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x7fe,1,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_DST_MAP_OB(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x7fe,1)
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_DST_MAP_OB_MASK 0x000007fe
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_DST_MAP_OB_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_DST_MAP_OB_BITS 10
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_DST_MAP_OB_SHIFT 1

/* switch :: PAGE_A0_ACT_POL_DATA1 :: PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_IB [00:00] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_IB(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x1,0,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_IB(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA1,0x1,0)
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_IB_MASK 0x00000001
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_IB_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_IB_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA1_PAGE_A0_ACT_POL_DATA1_CHANGE_DSCP_IB_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_ACT_POL_DATA2
 ***************************************************************************/
/* switch :: PAGE_A0_ACT_POL_DATA2 :: PAGE_A0_ACT_POL_DATA2_RESERVED [31:08] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_RESERVED(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0xffffff00,8,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_RESERVED(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0xffffff00,8)
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_RESERVED_MASK 0xffffff00
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_RESERVED_BITS 24
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_RESERVED_SHIFT 8

/* switch :: PAGE_A0_ACT_POL_DATA2 :: PAGE_A0_ACT_POL_DATA2_DEI_RMK_DISABLE [07:07] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_DEI_RMK_DISABLE(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x80,7,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_DEI_RMK_DISABLE(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x80,7)
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_DEI_RMK_DISABLE_MASK 0x00000080
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_DEI_RMK_DISABLE_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_DEI_RMK_DISABLE_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_DEI_RMK_DISABLE_SHIFT 7

/* switch :: PAGE_A0_ACT_POL_DATA2 :: PAGE_A0_ACT_POL_DATA2_CPCP_RMK_DISABLE [06:06] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CPCP_RMK_DISABLE(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x40,6,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CPCP_RMK_DISABLE(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x40,6)
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CPCP_RMK_DISABLE_MASK 0x00000040
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CPCP_RMK_DISABLE_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CPCP_RMK_DISABLE_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CPCP_RMK_DISABLE_SHIFT 6

/* switch :: PAGE_A0_ACT_POL_DATA2 :: PAGE_A0_ACT_POL_DATA2_SPCP_RMK_DISABLE [05:05] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_SPCP_RMK_DISABLE(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x20,5,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_SPCP_RMK_DISABLE(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x20,5)
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_SPCP_RMK_DISABLE_MASK 0x00000020
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_SPCP_RMK_DISABLE_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_SPCP_RMK_DISABLE_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_SPCP_RMK_DISABLE_SHIFT 5

/* switch :: PAGE_A0_ACT_POL_DATA2 :: PAGE_A0_ACT_POL_DATA2_NEW_TC_O [04:02] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_NEW_TC_O(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x1c,2,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_NEW_TC_O(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x1c,2)
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_NEW_TC_O_MASK 0x0000001c
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_NEW_TC_O_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_NEW_TC_O_BITS 3
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_NEW_TC_O_SHIFT 2

/* switch :: PAGE_A0_ACT_POL_DATA2 :: PAGE_A0_ACT_POL_DATA2_CHANGE_TC_O [01:01] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CHANGE_TC_O(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x2,1,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CHANGE_TC_O(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x2,1)
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CHANGE_TC_O_MASK 0x00000002
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CHANGE_TC_O_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CHANGE_TC_O_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_CHANGE_TC_O_SHIFT 1

/* switch :: PAGE_A0_ACT_POL_DATA2 :: PAGE_A0_ACT_POL_DATA2_MAC_LIMIT_BYPASS [00:00] */
#define Wr_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_MAC_LIMIT_BYPASS(x) WriteRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x1,0,x)
#define Rd_switch_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_MAC_LIMIT_BYPASS(x) ReadRegBits(SWITCH_PAGE_A0_ACT_POL_DATA2,0x1,0)
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_MAC_LIMIT_BYPASS_MASK 0x00000001
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_MAC_LIMIT_BYPASS_ALIGN 0
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_MAC_LIMIT_BYPASS_BITS 1
#define SWITCH_PAGE_A0_ACT_POL_DATA2_PAGE_A0_ACT_POL_DATA2_MAC_LIMIT_BYPASS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_RATE_METER0
 ***************************************************************************/
/* switch :: PAGE_A0_RATE_METER0 :: PAGE_A0_RATE_METER0_RESERVED [31:05] */
#define Wr_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_RESERVED(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER0,0xffffffe0,5,x)
#define Rd_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_RESERVED(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER0,0xffffffe0,5)
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_RESERVED_MASK 0xffffffe0
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_RESERVED_BITS 27
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_RESERVED_SHIFT 5

/* switch :: PAGE_A0_RATE_METER0 :: PAGE_A0_RATE_METER0_POLICER_MODE [04:03] */
#define Wr_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_MODE(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER0,0x18,3,x)
#define Rd_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_MODE(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER0,0x18,3)
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_MODE_MASK 0x00000018
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_MODE_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_MODE_BITS 2
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_MODE_SHIFT 3

/* switch :: PAGE_A0_RATE_METER0 :: PAGE_A0_RATE_METER0_CF [02:02] */
#define Wr_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CF(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER0,0x4,2,x)
#define Rd_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CF(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER0,0x4,2)
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CF_MASK     0x00000004
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CF_ALIGN    0
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CF_BITS     1
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CF_SHIFT    2

/* switch :: PAGE_A0_RATE_METER0 :: PAGE_A0_RATE_METER0_POLICER_ACTION [01:01] */
#define Wr_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_ACTION(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER0,0x2,1,x)
#define Rd_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_ACTION(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER0,0x2,1)
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_ACTION_MASK 0x00000002
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_ACTION_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_ACTION_BITS 1
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_POLICER_ACTION_SHIFT 1

/* switch :: PAGE_A0_RATE_METER0 :: PAGE_A0_RATE_METER0_CM [00:00] */
#define Wr_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CM(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER0,0x1,0,x)
#define Rd_switch_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CM(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER0,0x1,0)
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CM_MASK     0x00000001
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CM_ALIGN    0
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CM_BITS     1
#define SWITCH_PAGE_A0_RATE_METER0_PAGE_A0_RATE_METER0_CM_SHIFT    0


/****************************************************************************
 * switch :: PAGE_A0_RATE_METER1
 ***************************************************************************/
/* switch :: PAGE_A0_RATE_METER1 :: PAGE_A0_RATE_METER1_RESERVED [31:23] */
#define Wr_switch_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_RESERVED(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER1,0xff800000,23,x)
#define Rd_switch_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_RESERVED(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER1,0xff800000,23)
#define SWITCH_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_RESERVED_MASK 0xff800000
#define SWITCH_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_RESERVED_BITS 9
#define SWITCH_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_RESERVED_SHIFT 23

/* switch :: PAGE_A0_RATE_METER1 :: PAGE_A0_RATE_METER1_EIR_TK_BKT [22:00] */
#define Wr_switch_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_EIR_TK_BKT(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER1,0x7fffff,0,x)
#define Rd_switch_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_EIR_TK_BKT(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER1,0x7fffff,0)
#define SWITCH_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_EIR_TK_BKT_MASK 0x007fffff
#define SWITCH_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_EIR_TK_BKT_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_EIR_TK_BKT_BITS 23
#define SWITCH_PAGE_A0_RATE_METER1_PAGE_A0_RATE_METER1_EIR_TK_BKT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_RATE_METER2
 ***************************************************************************/
/* switch :: PAGE_A0_RATE_METER2 :: PAGE_A0_RATE_METER2_RESERVED [31:20] */
#define Wr_switch_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_RESERVED(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER2,0xfff00000,20,x)
#define Rd_switch_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_RESERVED(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER2,0xfff00000,20)
#define SWITCH_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_RESERVED_MASK 0xfff00000
#define SWITCH_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_RESERVED_BITS 12
#define SWITCH_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_RESERVED_SHIFT 20

/* switch :: PAGE_A0_RATE_METER2 :: PAGE_A0_RATE_METER2_EIR_BKT_SIZE [19:00] */
#define Wr_switch_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_EIR_BKT_SIZE(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER2,0xfffff,0,x)
#define Rd_switch_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_EIR_BKT_SIZE(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER2,0xfffff,0)
#define SWITCH_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_EIR_BKT_SIZE_MASK 0x000fffff
#define SWITCH_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_EIR_BKT_SIZE_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_EIR_BKT_SIZE_BITS 20
#define SWITCH_PAGE_A0_RATE_METER2_PAGE_A0_RATE_METER2_EIR_BKT_SIZE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_RATE_METER3
 ***************************************************************************/
/* switch :: PAGE_A0_RATE_METER3 :: PAGE_A0_RATE_METER3_RESERVED [31:19] */
#define Wr_switch_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_RESERVED(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER3,0xfff80000,19,x)
#define Rd_switch_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_RESERVED(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER3,0xfff80000,19)
#define SWITCH_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_RESERVED_MASK 0xfff80000
#define SWITCH_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_RESERVED_BITS 13
#define SWITCH_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_RESERVED_SHIFT 19

/* switch :: PAGE_A0_RATE_METER3 :: PAGE_A0_RATE_METER3_EIR_REF_CNT [18:00] */
#define Wr_switch_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_EIR_REF_CNT(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER3,0x7ffff,0,x)
#define Rd_switch_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_EIR_REF_CNT(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER3,0x7ffff,0)
#define SWITCH_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_EIR_REF_CNT_MASK 0x0007ffff
#define SWITCH_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_EIR_REF_CNT_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_EIR_REF_CNT_BITS 19
#define SWITCH_PAGE_A0_RATE_METER3_PAGE_A0_RATE_METER3_EIR_REF_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_RATE_METER4
 ***************************************************************************/
/* switch :: PAGE_A0_RATE_METER4 :: PAGE_A0_RATE_METER4_RESERVED [31:23] */
#define Wr_switch_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_RESERVED(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER4,0xff800000,23,x)
#define Rd_switch_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_RESERVED(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER4,0xff800000,23)
#define SWITCH_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_RESERVED_MASK 0xff800000
#define SWITCH_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_RESERVED_BITS 9
#define SWITCH_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_RESERVED_SHIFT 23

/* switch :: PAGE_A0_RATE_METER4 :: PAGE_A0_RATE_METER4_CIR_TK_BKT [22:00] */
#define Wr_switch_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_CIR_TK_BKT(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER4,0x7fffff,0,x)
#define Rd_switch_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_CIR_TK_BKT(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER4,0x7fffff,0)
#define SWITCH_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_CIR_TK_BKT_MASK 0x007fffff
#define SWITCH_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_CIR_TK_BKT_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_CIR_TK_BKT_BITS 23
#define SWITCH_PAGE_A0_RATE_METER4_PAGE_A0_RATE_METER4_CIR_TK_BKT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_RATE_METER5
 ***************************************************************************/
/* switch :: PAGE_A0_RATE_METER5 :: PAGE_A0_RATE_METER5_RESERVED [31:20] */
#define Wr_switch_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_RESERVED(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER5,0xfff00000,20,x)
#define Rd_switch_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_RESERVED(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER5,0xfff00000,20)
#define SWITCH_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_RESERVED_MASK 0xfff00000
#define SWITCH_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_RESERVED_BITS 12
#define SWITCH_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_RESERVED_SHIFT 20

/* switch :: PAGE_A0_RATE_METER5 :: PAGE_A0_RATE_METER5_CIR_BKT_SIZE [19:00] */
#define Wr_switch_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_CIR_BKT_SIZE(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER5,0xfffff,0,x)
#define Rd_switch_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_CIR_BKT_SIZE(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER5,0xfffff,0)
#define SWITCH_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_CIR_BKT_SIZE_MASK 0x000fffff
#define SWITCH_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_CIR_BKT_SIZE_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_CIR_BKT_SIZE_BITS 20
#define SWITCH_PAGE_A0_RATE_METER5_PAGE_A0_RATE_METER5_CIR_BKT_SIZE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_RATE_METER6
 ***************************************************************************/
/* switch :: PAGE_A0_RATE_METER6 :: PAGE_A0_RATE_METER6_RESERVED [31:19] */
#define Wr_switch_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_RESERVED(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER6,0xfff80000,19,x)
#define Rd_switch_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_RESERVED(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER6,0xfff80000,19)
#define SWITCH_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_RESERVED_MASK 0xfff80000
#define SWITCH_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_RESERVED_BITS 13
#define SWITCH_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_RESERVED_SHIFT 19

/* switch :: PAGE_A0_RATE_METER6 :: PAGE_A0_RATE_METER6_CIR_REF_CNT [18:00] */
#define Wr_switch_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_CIR_REF_CNT(x) WriteRegBits(SWITCH_PAGE_A0_RATE_METER6,0x7ffff,0,x)
#define Rd_switch_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_CIR_REF_CNT(x) ReadRegBits(SWITCH_PAGE_A0_RATE_METER6,0x7ffff,0)
#define SWITCH_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_CIR_REF_CNT_MASK 0x0007ffff
#define SWITCH_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_CIR_REF_CNT_ALIGN 0
#define SWITCH_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_CIR_REF_CNT_BITS 19
#define SWITCH_PAGE_A0_RATE_METER6_PAGE_A0_RATE_METER6_CIR_REF_CNT_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_TC2COLOR
 ***************************************************************************/
/* switch :: PAGE_A0_TC2COLOR :: PAGE_A0_TC2COLOR_RESERVED [15:11] */
#define Wr_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_RESERVED(x) WriteRegBits16(SWITCH_PAGE_A0_TC2COLOR,0xf800,11,x)
#define Rd_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_RESERVED(x) ReadRegBits16(SWITCH_PAGE_A0_TC2COLOR,0xf800,11)
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_RESERVED_MASK     0xf800
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_RESERVED_ALIGN    0
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_RESERVED_BITS     5
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_RESERVED_SHIFT    11

/* switch :: PAGE_A0_TC2COLOR :: PAGE_A0_TC2COLOR_TC2COLOR_MAP_COLOR [10:09] */
#define Wr_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_COLOR(x) WriteRegBits16(SWITCH_PAGE_A0_TC2COLOR,0x600,9,x)
#define Rd_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_COLOR(x) ReadRegBits16(SWITCH_PAGE_A0_TC2COLOR,0x600,9)
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_COLOR_MASK 0x0600
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_COLOR_ALIGN 0
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_COLOR_BITS 2
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_COLOR_SHIFT 9

/* switch :: PAGE_A0_TC2COLOR :: PAGE_A0_TC2COLOR_TC2COLOR_MAP_DEI [08:08] */
#define Wr_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_DEI(x) WriteRegBits16(SWITCH_PAGE_A0_TC2COLOR,0x100,8,x)
#define Rd_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_DEI(x) ReadRegBits16(SWITCH_PAGE_A0_TC2COLOR,0x100,8)
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_DEI_MASK 0x0100
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_DEI_ALIGN 0
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_DEI_BITS 1
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_DEI_SHIFT 8

/* switch :: PAGE_A0_TC2COLOR :: PAGE_A0_TC2COLOR_TC2COLOR_MAP_TC [07:05] */
#define Wr_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_TC(x) WriteRegBits16(SWITCH_PAGE_A0_TC2COLOR,0xe0,5,x)
#define Rd_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_TC(x) ReadRegBits16(SWITCH_PAGE_A0_TC2COLOR,0xe0,5)
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_TC_MASK 0x00e0
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_TC_ALIGN 0
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_TC_BITS 3
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_TC_SHIFT 5

/* switch :: PAGE_A0_TC2COLOR :: PAGE_A0_TC2COLOR_TC2COLOR_MAP_ING_PORT [04:01] */
#define Wr_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_ING_PORT(x) WriteRegBits16(SWITCH_PAGE_A0_TC2COLOR,0x1e,1,x)
#define Rd_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_ING_PORT(x) ReadRegBits16(SWITCH_PAGE_A0_TC2COLOR,0x1e,1)
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_ING_PORT_MASK 0x001e
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_ING_PORT_ALIGN 0
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_ING_PORT_BITS 4
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_ING_PORT_SHIFT 1

/* switch :: PAGE_A0_TC2COLOR :: PAGE_A0_TC2COLOR_TC2COLOR_MAP_RW [00:00] */
#define Wr_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_RW(x) WriteRegBits16(SWITCH_PAGE_A0_TC2COLOR,0x1,0,x)
#define Rd_switch_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_RW(x) ReadRegBits16(SWITCH_PAGE_A0_TC2COLOR,0x1,0)
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_RW_MASK 0x0001
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_RW_ALIGN 0
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_RW_BITS 1
#define SWITCH_PAGE_A0_TC2COLOR_PAGE_A0_TC2COLOR_TC2COLOR_MAP_RW_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_STAT_GREEN_CNTR
 ***************************************************************************/
/* switch :: PAGE_A0_STAT_GREEN_CNTR :: PAGE_A0_STAT_GREEN_CNTR_GREEN_CNTR [31:00] */
#define Wr_switch_PAGE_A0_STAT_GREEN_CNTR_PAGE_A0_STAT_GREEN_CNTR_GREEN_CNTR(x) WriteReg(SWITCH_PAGE_A0_STAT_GREEN_CNTR,x)
#define Rd_switch_PAGE_A0_STAT_GREEN_CNTR_PAGE_A0_STAT_GREEN_CNTR_GREEN_CNTR(x) ReadReg(SWITCH_PAGE_A0_STAT_GREEN_CNTR)
#define SWITCH_PAGE_A0_STAT_GREEN_CNTR_PAGE_A0_STAT_GREEN_CNTR_GREEN_CNTR_MASK 0xffffffff
#define SWITCH_PAGE_A0_STAT_GREEN_CNTR_PAGE_A0_STAT_GREEN_CNTR_GREEN_CNTR_ALIGN 0
#define SWITCH_PAGE_A0_STAT_GREEN_CNTR_PAGE_A0_STAT_GREEN_CNTR_GREEN_CNTR_BITS 32
#define SWITCH_PAGE_A0_STAT_GREEN_CNTR_PAGE_A0_STAT_GREEN_CNTR_GREEN_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_STAT_YELLOW_CNTR
 ***************************************************************************/
/* switch :: PAGE_A0_STAT_YELLOW_CNTR :: PAGE_A0_STAT_YELLOW_CNTR_YELLOW_CNTR [31:00] */
#define Wr_switch_PAGE_A0_STAT_YELLOW_CNTR_PAGE_A0_STAT_YELLOW_CNTR_YELLOW_CNTR(x) WriteReg(SWITCH_PAGE_A0_STAT_YELLOW_CNTR,x)
#define Rd_switch_PAGE_A0_STAT_YELLOW_CNTR_PAGE_A0_STAT_YELLOW_CNTR_YELLOW_CNTR(x) ReadReg(SWITCH_PAGE_A0_STAT_YELLOW_CNTR)
#define SWITCH_PAGE_A0_STAT_YELLOW_CNTR_PAGE_A0_STAT_YELLOW_CNTR_YELLOW_CNTR_MASK 0xffffffff
#define SWITCH_PAGE_A0_STAT_YELLOW_CNTR_PAGE_A0_STAT_YELLOW_CNTR_YELLOW_CNTR_ALIGN 0
#define SWITCH_PAGE_A0_STAT_YELLOW_CNTR_PAGE_A0_STAT_YELLOW_CNTR_YELLOW_CNTR_BITS 32
#define SWITCH_PAGE_A0_STAT_YELLOW_CNTR_PAGE_A0_STAT_YELLOW_CNTR_YELLOW_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_STAT_RED_CNTR
 ***************************************************************************/
/* switch :: PAGE_A0_STAT_RED_CNTR :: PAGE_A0_STAT_RED_CNTR_RED_CNTR [31:00] */
#define Wr_switch_PAGE_A0_STAT_RED_CNTR_PAGE_A0_STAT_RED_CNTR_RED_CNTR(x) WriteReg(SWITCH_PAGE_A0_STAT_RED_CNTR,x)
#define Rd_switch_PAGE_A0_STAT_RED_CNTR_PAGE_A0_STAT_RED_CNTR_RED_CNTR(x) ReadReg(SWITCH_PAGE_A0_STAT_RED_CNTR)
#define SWITCH_PAGE_A0_STAT_RED_CNTR_PAGE_A0_STAT_RED_CNTR_RED_CNTR_MASK 0xffffffff
#define SWITCH_PAGE_A0_STAT_RED_CNTR_PAGE_A0_STAT_RED_CNTR_RED_CNTR_ALIGN 0
#define SWITCH_PAGE_A0_STAT_RED_CNTR_PAGE_A0_STAT_RED_CNTR_RED_CNTR_BITS 32
#define SWITCH_PAGE_A0_STAT_RED_CNTR_PAGE_A0_STAT_RED_CNTR_RED_CNTR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_TCAM_BIST_CONTROL
 ***************************************************************************/
/* switch :: PAGE_A0_TCAM_BIST_CONTROL :: PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_DONE [31:31] */
#define Wr_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_DONE(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x80000000,31,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_DONE(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x80000000,31)
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_DONE_MASK 0x80000000
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_DONE_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_DONE_BITS 1
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_DONE_SHIFT 31

/* switch :: PAGE_A0_TCAM_BIST_CONTROL :: PAGE_A0_TCAM_BIST_CONTROL_RESERVED_1 [30:17] */
#define Wr_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x7ffe0000,17,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x7ffe0000,17)
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_1_MASK 0x7ffe0000
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_1_BITS 14
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_1_SHIFT 17

/* switch :: PAGE_A0_TCAM_BIST_CONTROL :: PAGE_A0_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE [16:16] */
#define Wr_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x10000,16,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x10000,16)
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_MASK 0x00010000
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_BITS 1
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_TEST_COMPARE_SHIFT 16

/* switch :: PAGE_A0_TCAM_BIST_CONTROL :: PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT [15:08] */
#define Wr_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0xff00,8,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0xff00,8)
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_MASK 0x0000ff00
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_BITS 8
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_SKIP_ERR_CNT_SHIFT 8

/* switch :: PAGE_A0_TCAM_BIST_CONTROL :: PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL [07:04] */
#define Wr_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0xf0,4,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0xf0,4)
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_MASK 0x000000f0
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_BITS 4
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_STATUS_SEL_SHIFT 4

/* switch :: PAGE_A0_TCAM_BIST_CONTROL :: PAGE_A0_TCAM_BIST_CONTROL_RESERVED_0 [03:02] */
#define Wr_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0xc,2,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0xc,2)
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_0_MASK 0x0000000c
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_0_BITS 2
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_RESERVED_0_SHIFT 2

/* switch :: PAGE_A0_TCAM_BIST_CONTROL :: PAGE_A0_TCAM_BIST_CONTROL_TCAM_SEL [01:01] */
#define Wr_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_SEL(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x2,1,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_SEL(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x2,1)
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_SEL_MASK 0x00000002
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_SEL_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_SEL_BITS 1
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_SEL_SHIFT 1

/* switch :: PAGE_A0_TCAM_BIST_CONTROL :: PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_EN [00:00] */
#define Wr_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_EN(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x1,0,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_EN(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_CONTROL,0x1,0)
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_EN_MASK 0x00000001
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_EN_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_EN_BITS 1
#define SWITCH_PAGE_A0_TCAM_BIST_CONTROL_PAGE_A0_TCAM_BIST_CONTROL_TCAM_BIST_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_TCAM_BIST_STATUS
 ***************************************************************************/
/* switch :: PAGE_A0_TCAM_BIST_STATUS :: PAGE_A0_TCAM_BIST_STATUS_RESERVED [31:16] */
#define Wr_switch_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_RESERVED(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_STATUS,0xffff0000,16,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_RESERVED(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_STATUS,0xffff0000,16)
#define SWITCH_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_RESERVED_MASK 0xffff0000
#define SWITCH_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_RESERVED_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_RESERVED_BITS 16
#define SWITCH_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_RESERVED_SHIFT 16

/* switch :: PAGE_A0_TCAM_BIST_STATUS :: PAGE_A0_TCAM_BIST_STATUS_TCAM_BIST_STATUS [15:00] */
#define Wr_switch_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_TCAM_BIST_STATUS(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_BIST_STATUS,0xffff,0,x)
#define Rd_switch_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_TCAM_BIST_STATUS(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_BIST_STATUS,0xffff,0)
#define SWITCH_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_TCAM_BIST_STATUS_MASK 0x0000ffff
#define SWITCH_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_TCAM_BIST_STATUS_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_TCAM_BIST_STATUS_BITS 16
#define SWITCH_PAGE_A0_TCAM_BIST_STATUS_PAGE_A0_TCAM_BIST_STATUS_TCAM_BIST_STATUS_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_TCAM_TEST_COMPARE_STATUS
 ***************************************************************************/
/* switch :: PAGE_A0_TCAM_TEST_COMPARE_STATUS :: PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_1 [31:16] */
#define Wr_switch_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS,0xffff0000,16,x)
#define Rd_switch_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS,0xffff0000,16)
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_1_MASK 0xffff0000
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_1_BITS 16
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_1_SHIFT 16

/* switch :: PAGE_A0_TCAM_TEST_COMPARE_STATUS :: PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT [15:15] */
#define Wr_switch_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS,0x8000,15,x)
#define Rd_switch_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS,0x8000,15)
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_MASK 0x00008000
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_BITS 1
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_SHIFT 15

/* switch :: PAGE_A0_TCAM_TEST_COMPARE_STATUS :: PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_0 [14:07] */
#define Wr_switch_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS,0x7f80,7,x)
#define Rd_switch_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS,0x7f80,7)
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_0_MASK 0x00007f80
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_0_BITS 8
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_RESERVED_0_SHIFT 7

/* switch :: PAGE_A0_TCAM_TEST_COMPARE_STATUS :: PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR [06:00] */
#define Wr_switch_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR(x) WriteRegBits(SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS,0x7f,0,x)
#define Rd_switch_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR(x) ReadRegBits(SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS,0x7f,0)
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_MASK 0x0000007f
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_ALIGN 0
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_BITS 7
#define SWITCH_PAGE_A0_TCAM_TEST_COMPARE_STATUS_PAGE_A0_TCAM_TEST_COMPARE_STATUS_TCAM_HIT_ADDR_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_REG_SPARE0
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_REG_SPARE0 :: PAGE_A0_CFP_REG_SPARE0_CFP_REG_SPARE0 [31:00] */
#define Wr_switch_PAGE_A0_CFP_REG_SPARE0_PAGE_A0_CFP_REG_SPARE0_CFP_REG_SPARE0(x) WriteReg(SWITCH_PAGE_A0_CFP_REG_SPARE0,x)
#define Rd_switch_PAGE_A0_CFP_REG_SPARE0_PAGE_A0_CFP_REG_SPARE0_CFP_REG_SPARE0(x) ReadReg(SWITCH_PAGE_A0_CFP_REG_SPARE0)
#define SWITCH_PAGE_A0_CFP_REG_SPARE0_PAGE_A0_CFP_REG_SPARE0_CFP_REG_SPARE0_MASK 0xffffffff
#define SWITCH_PAGE_A0_CFP_REG_SPARE0_PAGE_A0_CFP_REG_SPARE0_CFP_REG_SPARE0_ALIGN 0
#define SWITCH_PAGE_A0_CFP_REG_SPARE0_PAGE_A0_CFP_REG_SPARE0_CFP_REG_SPARE0_BITS 32
#define SWITCH_PAGE_A0_CFP_REG_SPARE0_PAGE_A0_CFP_REG_SPARE0_CFP_REG_SPARE0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A0_CFP_REG_SPARE1
 ***************************************************************************/
/* switch :: PAGE_A0_CFP_REG_SPARE1 :: PAGE_A0_CFP_REG_SPARE1_CFP_REG_SPARE1 [31:00] */
#define Wr_switch_PAGE_A0_CFP_REG_SPARE1_PAGE_A0_CFP_REG_SPARE1_CFP_REG_SPARE1(x) WriteReg(SWITCH_PAGE_A0_CFP_REG_SPARE1,x)
#define Rd_switch_PAGE_A0_CFP_REG_SPARE1_PAGE_A0_CFP_REG_SPARE1_CFP_REG_SPARE1(x) ReadReg(SWITCH_PAGE_A0_CFP_REG_SPARE1)
#define SWITCH_PAGE_A0_CFP_REG_SPARE1_PAGE_A0_CFP_REG_SPARE1_CFP_REG_SPARE1_MASK 0xffffffff
#define SWITCH_PAGE_A0_CFP_REG_SPARE1_PAGE_A0_CFP_REG_SPARE1_CFP_REG_SPARE1_ALIGN 0
#define SWITCH_PAGE_A0_CFP_REG_SPARE1_PAGE_A0_CFP_REG_SPARE1_CFP_REG_SPARE1_BITS 32
#define SWITCH_PAGE_A0_CFP_REG_SPARE1_PAGE_A0_CFP_REG_SPARE1_CFP_REG_SPARE1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_CFP_CTL_REG
 ***************************************************************************/
/* switch :: PAGE_A1_CFP_CTL_REG :: PAGE_A1_CFP_CTL_REG_RESERVED [15:09] */
#define Wr_switch_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_RESERVED(x) WriteRegBits16(SWITCH_PAGE_A1_CFP_CTL_REG,0xfe00,9,x)
#define Rd_switch_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_RESERVED(x) ReadRegBits16(SWITCH_PAGE_A1_CFP_CTL_REG,0xfe00,9)
#define SWITCH_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_RESERVED_MASK 0xfe00
#define SWITCH_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_RESERVED_ALIGN 0
#define SWITCH_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_RESERVED_BITS 7
#define SWITCH_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_RESERVED_SHIFT 9

/* switch :: PAGE_A1_CFP_CTL_REG :: PAGE_A1_CFP_CTL_REG_CFP_EN_MAP [08:00] */
#define Wr_switch_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_CFP_EN_MAP(x) WriteRegBits16(SWITCH_PAGE_A1_CFP_CTL_REG,0x1ff,0,x)
#define Rd_switch_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_CFP_EN_MAP(x) ReadRegBits16(SWITCH_PAGE_A1_CFP_CTL_REG,0x1ff,0)
#define SWITCH_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_CFP_EN_MAP_MASK 0x01ff
#define SWITCH_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_CFP_EN_MAP_ALIGN 0
#define SWITCH_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_CFP_EN_MAP_BITS 9
#define SWITCH_PAGE_A1_CFP_CTL_REG_PAGE_A1_CFP_CTL_REG_CFP_EN_MAP_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_A_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_A_0 :: PAGE_A1_UDF_0_A_0_CFG_UDF_0_A_0 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_A_0_PAGE_A1_UDF_0_A_0_CFG_UDF_0_A_0(x) WriteReg(SWITCH_PAGE_A1_UDF_0_A_0,x)
#define Rd_switch_PAGE_A1_UDF_0_A_0_PAGE_A1_UDF_0_A_0_CFG_UDF_0_A_0(x) ReadReg(SWITCH_PAGE_A1_UDF_0_A_0)
#define SWITCH_PAGE_A1_UDF_0_A_0_PAGE_A1_UDF_0_A_0_CFG_UDF_0_A_0_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_A_0_PAGE_A1_UDF_0_A_0_CFG_UDF_0_A_0_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_A_0_PAGE_A1_UDF_0_A_0_CFG_UDF_0_A_0_BITS 8
#define SWITCH_PAGE_A1_UDF_0_A_0_PAGE_A1_UDF_0_A_0_CFG_UDF_0_A_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_A_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_A_1 :: PAGE_A1_UDF_0_A_1_CFG_UDF_0_A_1 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_A_1_PAGE_A1_UDF_0_A_1_CFG_UDF_0_A_1(x) WriteReg(SWITCH_PAGE_A1_UDF_0_A_1,x)
#define Rd_switch_PAGE_A1_UDF_0_A_1_PAGE_A1_UDF_0_A_1_CFG_UDF_0_A_1(x) ReadReg(SWITCH_PAGE_A1_UDF_0_A_1)
#define SWITCH_PAGE_A1_UDF_0_A_1_PAGE_A1_UDF_0_A_1_CFG_UDF_0_A_1_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_A_1_PAGE_A1_UDF_0_A_1_CFG_UDF_0_A_1_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_A_1_PAGE_A1_UDF_0_A_1_CFG_UDF_0_A_1_BITS 8
#define SWITCH_PAGE_A1_UDF_0_A_1_PAGE_A1_UDF_0_A_1_CFG_UDF_0_A_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_A_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_A_2 :: PAGE_A1_UDF_0_A_2_CFG_UDF_0_A_2 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_A_2_PAGE_A1_UDF_0_A_2_CFG_UDF_0_A_2(x) WriteReg(SWITCH_PAGE_A1_UDF_0_A_2,x)
#define Rd_switch_PAGE_A1_UDF_0_A_2_PAGE_A1_UDF_0_A_2_CFG_UDF_0_A_2(x) ReadReg(SWITCH_PAGE_A1_UDF_0_A_2)
#define SWITCH_PAGE_A1_UDF_0_A_2_PAGE_A1_UDF_0_A_2_CFG_UDF_0_A_2_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_A_2_PAGE_A1_UDF_0_A_2_CFG_UDF_0_A_2_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_A_2_PAGE_A1_UDF_0_A_2_CFG_UDF_0_A_2_BITS 8
#define SWITCH_PAGE_A1_UDF_0_A_2_PAGE_A1_UDF_0_A_2_CFG_UDF_0_A_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_A_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_A_3 :: PAGE_A1_UDF_0_A_3_CFG_UDF_0_A_3 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_A_3_PAGE_A1_UDF_0_A_3_CFG_UDF_0_A_3(x) WriteReg(SWITCH_PAGE_A1_UDF_0_A_3,x)
#define Rd_switch_PAGE_A1_UDF_0_A_3_PAGE_A1_UDF_0_A_3_CFG_UDF_0_A_3(x) ReadReg(SWITCH_PAGE_A1_UDF_0_A_3)
#define SWITCH_PAGE_A1_UDF_0_A_3_PAGE_A1_UDF_0_A_3_CFG_UDF_0_A_3_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_A_3_PAGE_A1_UDF_0_A_3_CFG_UDF_0_A_3_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_A_3_PAGE_A1_UDF_0_A_3_CFG_UDF_0_A_3_BITS 8
#define SWITCH_PAGE_A1_UDF_0_A_3_PAGE_A1_UDF_0_A_3_CFG_UDF_0_A_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_A_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_A_4 :: PAGE_A1_UDF_0_A_4_CFG_UDF_0_A_4 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_A_4_PAGE_A1_UDF_0_A_4_CFG_UDF_0_A_4(x) WriteReg(SWITCH_PAGE_A1_UDF_0_A_4,x)
#define Rd_switch_PAGE_A1_UDF_0_A_4_PAGE_A1_UDF_0_A_4_CFG_UDF_0_A_4(x) ReadReg(SWITCH_PAGE_A1_UDF_0_A_4)
#define SWITCH_PAGE_A1_UDF_0_A_4_PAGE_A1_UDF_0_A_4_CFG_UDF_0_A_4_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_A_4_PAGE_A1_UDF_0_A_4_CFG_UDF_0_A_4_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_A_4_PAGE_A1_UDF_0_A_4_CFG_UDF_0_A_4_BITS 8
#define SWITCH_PAGE_A1_UDF_0_A_4_PAGE_A1_UDF_0_A_4_CFG_UDF_0_A_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_A_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_A_5 :: PAGE_A1_UDF_0_A_5_CFG_UDF_0_A_5 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_A_5_PAGE_A1_UDF_0_A_5_CFG_UDF_0_A_5(x) WriteReg(SWITCH_PAGE_A1_UDF_0_A_5,x)
#define Rd_switch_PAGE_A1_UDF_0_A_5_PAGE_A1_UDF_0_A_5_CFG_UDF_0_A_5(x) ReadReg(SWITCH_PAGE_A1_UDF_0_A_5)
#define SWITCH_PAGE_A1_UDF_0_A_5_PAGE_A1_UDF_0_A_5_CFG_UDF_0_A_5_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_A_5_PAGE_A1_UDF_0_A_5_CFG_UDF_0_A_5_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_A_5_PAGE_A1_UDF_0_A_5_CFG_UDF_0_A_5_BITS 8
#define SWITCH_PAGE_A1_UDF_0_A_5_PAGE_A1_UDF_0_A_5_CFG_UDF_0_A_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_A_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_A_6 :: PAGE_A1_UDF_0_A_6_CFG_UDF_0_A_6 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_A_6_PAGE_A1_UDF_0_A_6_CFG_UDF_0_A_6(x) WriteReg(SWITCH_PAGE_A1_UDF_0_A_6,x)
#define Rd_switch_PAGE_A1_UDF_0_A_6_PAGE_A1_UDF_0_A_6_CFG_UDF_0_A_6(x) ReadReg(SWITCH_PAGE_A1_UDF_0_A_6)
#define SWITCH_PAGE_A1_UDF_0_A_6_PAGE_A1_UDF_0_A_6_CFG_UDF_0_A_6_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_A_6_PAGE_A1_UDF_0_A_6_CFG_UDF_0_A_6_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_A_6_PAGE_A1_UDF_0_A_6_CFG_UDF_0_A_6_BITS 8
#define SWITCH_PAGE_A1_UDF_0_A_6_PAGE_A1_UDF_0_A_6_CFG_UDF_0_A_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_A_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_A_7 :: PAGE_A1_UDF_0_A_7_CFG_UDF_0_A_7 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_A_7_PAGE_A1_UDF_0_A_7_CFG_UDF_0_A_7(x) WriteReg(SWITCH_PAGE_A1_UDF_0_A_7,x)
#define Rd_switch_PAGE_A1_UDF_0_A_7_PAGE_A1_UDF_0_A_7_CFG_UDF_0_A_7(x) ReadReg(SWITCH_PAGE_A1_UDF_0_A_7)
#define SWITCH_PAGE_A1_UDF_0_A_7_PAGE_A1_UDF_0_A_7_CFG_UDF_0_A_7_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_A_7_PAGE_A1_UDF_0_A_7_CFG_UDF_0_A_7_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_A_7_PAGE_A1_UDF_0_A_7_CFG_UDF_0_A_7_BITS 8
#define SWITCH_PAGE_A1_UDF_0_A_7_PAGE_A1_UDF_0_A_7_CFG_UDF_0_A_7_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_A_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_A_8 :: PAGE_A1_UDF_0_A_8_CFG_UDF_0_A_8 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_A_8_PAGE_A1_UDF_0_A_8_CFG_UDF_0_A_8(x) WriteReg(SWITCH_PAGE_A1_UDF_0_A_8,x)
#define Rd_switch_PAGE_A1_UDF_0_A_8_PAGE_A1_UDF_0_A_8_CFG_UDF_0_A_8(x) ReadReg(SWITCH_PAGE_A1_UDF_0_A_8)
#define SWITCH_PAGE_A1_UDF_0_A_8_PAGE_A1_UDF_0_A_8_CFG_UDF_0_A_8_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_A_8_PAGE_A1_UDF_0_A_8_CFG_UDF_0_A_8_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_A_8_PAGE_A1_UDF_0_A_8_CFG_UDF_0_A_8_BITS 8
#define SWITCH_PAGE_A1_UDF_0_A_8_PAGE_A1_UDF_0_A_8_CFG_UDF_0_A_8_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_A_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_A_0 :: PAGE_A1_UDF_1_A_0_CFG_UDF_1_A_0 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_A_0_PAGE_A1_UDF_1_A_0_CFG_UDF_1_A_0(x) WriteReg(SWITCH_PAGE_A1_UDF_1_A_0,x)
#define Rd_switch_PAGE_A1_UDF_1_A_0_PAGE_A1_UDF_1_A_0_CFG_UDF_1_A_0(x) ReadReg(SWITCH_PAGE_A1_UDF_1_A_0)
#define SWITCH_PAGE_A1_UDF_1_A_0_PAGE_A1_UDF_1_A_0_CFG_UDF_1_A_0_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_A_0_PAGE_A1_UDF_1_A_0_CFG_UDF_1_A_0_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_A_0_PAGE_A1_UDF_1_A_0_CFG_UDF_1_A_0_BITS 8
#define SWITCH_PAGE_A1_UDF_1_A_0_PAGE_A1_UDF_1_A_0_CFG_UDF_1_A_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_A_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_A_1 :: PAGE_A1_UDF_1_A_1_CFG_UDF_1_A_1 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_A_1_PAGE_A1_UDF_1_A_1_CFG_UDF_1_A_1(x) WriteReg(SWITCH_PAGE_A1_UDF_1_A_1,x)
#define Rd_switch_PAGE_A1_UDF_1_A_1_PAGE_A1_UDF_1_A_1_CFG_UDF_1_A_1(x) ReadReg(SWITCH_PAGE_A1_UDF_1_A_1)
#define SWITCH_PAGE_A1_UDF_1_A_1_PAGE_A1_UDF_1_A_1_CFG_UDF_1_A_1_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_A_1_PAGE_A1_UDF_1_A_1_CFG_UDF_1_A_1_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_A_1_PAGE_A1_UDF_1_A_1_CFG_UDF_1_A_1_BITS 8
#define SWITCH_PAGE_A1_UDF_1_A_1_PAGE_A1_UDF_1_A_1_CFG_UDF_1_A_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_A_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_A_2 :: PAGE_A1_UDF_1_A_2_CFG_UDF_1_A_2 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_A_2_PAGE_A1_UDF_1_A_2_CFG_UDF_1_A_2(x) WriteReg(SWITCH_PAGE_A1_UDF_1_A_2,x)
#define Rd_switch_PAGE_A1_UDF_1_A_2_PAGE_A1_UDF_1_A_2_CFG_UDF_1_A_2(x) ReadReg(SWITCH_PAGE_A1_UDF_1_A_2)
#define SWITCH_PAGE_A1_UDF_1_A_2_PAGE_A1_UDF_1_A_2_CFG_UDF_1_A_2_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_A_2_PAGE_A1_UDF_1_A_2_CFG_UDF_1_A_2_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_A_2_PAGE_A1_UDF_1_A_2_CFG_UDF_1_A_2_BITS 8
#define SWITCH_PAGE_A1_UDF_1_A_2_PAGE_A1_UDF_1_A_2_CFG_UDF_1_A_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_A_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_A_3 :: PAGE_A1_UDF_1_A_3_CFG_UDF_1_A_3 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_A_3_PAGE_A1_UDF_1_A_3_CFG_UDF_1_A_3(x) WriteReg(SWITCH_PAGE_A1_UDF_1_A_3,x)
#define Rd_switch_PAGE_A1_UDF_1_A_3_PAGE_A1_UDF_1_A_3_CFG_UDF_1_A_3(x) ReadReg(SWITCH_PAGE_A1_UDF_1_A_3)
#define SWITCH_PAGE_A1_UDF_1_A_3_PAGE_A1_UDF_1_A_3_CFG_UDF_1_A_3_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_A_3_PAGE_A1_UDF_1_A_3_CFG_UDF_1_A_3_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_A_3_PAGE_A1_UDF_1_A_3_CFG_UDF_1_A_3_BITS 8
#define SWITCH_PAGE_A1_UDF_1_A_3_PAGE_A1_UDF_1_A_3_CFG_UDF_1_A_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_A_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_A_4 :: PAGE_A1_UDF_1_A_4_CFG_UDF_1_A_4 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_A_4_PAGE_A1_UDF_1_A_4_CFG_UDF_1_A_4(x) WriteReg(SWITCH_PAGE_A1_UDF_1_A_4,x)
#define Rd_switch_PAGE_A1_UDF_1_A_4_PAGE_A1_UDF_1_A_4_CFG_UDF_1_A_4(x) ReadReg(SWITCH_PAGE_A1_UDF_1_A_4)
#define SWITCH_PAGE_A1_UDF_1_A_4_PAGE_A1_UDF_1_A_4_CFG_UDF_1_A_4_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_A_4_PAGE_A1_UDF_1_A_4_CFG_UDF_1_A_4_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_A_4_PAGE_A1_UDF_1_A_4_CFG_UDF_1_A_4_BITS 8
#define SWITCH_PAGE_A1_UDF_1_A_4_PAGE_A1_UDF_1_A_4_CFG_UDF_1_A_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_A_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_A_5 :: PAGE_A1_UDF_1_A_5_CFG_UDF_1_A_5 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_A_5_PAGE_A1_UDF_1_A_5_CFG_UDF_1_A_5(x) WriteReg(SWITCH_PAGE_A1_UDF_1_A_5,x)
#define Rd_switch_PAGE_A1_UDF_1_A_5_PAGE_A1_UDF_1_A_5_CFG_UDF_1_A_5(x) ReadReg(SWITCH_PAGE_A1_UDF_1_A_5)
#define SWITCH_PAGE_A1_UDF_1_A_5_PAGE_A1_UDF_1_A_5_CFG_UDF_1_A_5_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_A_5_PAGE_A1_UDF_1_A_5_CFG_UDF_1_A_5_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_A_5_PAGE_A1_UDF_1_A_5_CFG_UDF_1_A_5_BITS 8
#define SWITCH_PAGE_A1_UDF_1_A_5_PAGE_A1_UDF_1_A_5_CFG_UDF_1_A_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_A_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_A_6 :: PAGE_A1_UDF_1_A_6_CFG_UDF_1_A_6 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_A_6_PAGE_A1_UDF_1_A_6_CFG_UDF_1_A_6(x) WriteReg(SWITCH_PAGE_A1_UDF_1_A_6,x)
#define Rd_switch_PAGE_A1_UDF_1_A_6_PAGE_A1_UDF_1_A_6_CFG_UDF_1_A_6(x) ReadReg(SWITCH_PAGE_A1_UDF_1_A_6)
#define SWITCH_PAGE_A1_UDF_1_A_6_PAGE_A1_UDF_1_A_6_CFG_UDF_1_A_6_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_A_6_PAGE_A1_UDF_1_A_6_CFG_UDF_1_A_6_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_A_6_PAGE_A1_UDF_1_A_6_CFG_UDF_1_A_6_BITS 8
#define SWITCH_PAGE_A1_UDF_1_A_6_PAGE_A1_UDF_1_A_6_CFG_UDF_1_A_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_A_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_A_7 :: PAGE_A1_UDF_1_A_7_CFG_UDF_1_A_7 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_A_7_PAGE_A1_UDF_1_A_7_CFG_UDF_1_A_7(x) WriteReg(SWITCH_PAGE_A1_UDF_1_A_7,x)
#define Rd_switch_PAGE_A1_UDF_1_A_7_PAGE_A1_UDF_1_A_7_CFG_UDF_1_A_7(x) ReadReg(SWITCH_PAGE_A1_UDF_1_A_7)
#define SWITCH_PAGE_A1_UDF_1_A_7_PAGE_A1_UDF_1_A_7_CFG_UDF_1_A_7_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_A_7_PAGE_A1_UDF_1_A_7_CFG_UDF_1_A_7_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_A_7_PAGE_A1_UDF_1_A_7_CFG_UDF_1_A_7_BITS 8
#define SWITCH_PAGE_A1_UDF_1_A_7_PAGE_A1_UDF_1_A_7_CFG_UDF_1_A_7_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_A_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_A_8 :: PAGE_A1_UDF_1_A_8_CFG_UDF_1_A_8 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_A_8_PAGE_A1_UDF_1_A_8_CFG_UDF_1_A_8(x) WriteReg(SWITCH_PAGE_A1_UDF_1_A_8,x)
#define Rd_switch_PAGE_A1_UDF_1_A_8_PAGE_A1_UDF_1_A_8_CFG_UDF_1_A_8(x) ReadReg(SWITCH_PAGE_A1_UDF_1_A_8)
#define SWITCH_PAGE_A1_UDF_1_A_8_PAGE_A1_UDF_1_A_8_CFG_UDF_1_A_8_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_A_8_PAGE_A1_UDF_1_A_8_CFG_UDF_1_A_8_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_A_8_PAGE_A1_UDF_1_A_8_CFG_UDF_1_A_8_BITS 8
#define SWITCH_PAGE_A1_UDF_1_A_8_PAGE_A1_UDF_1_A_8_CFG_UDF_1_A_8_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_A_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_A_0 :: PAGE_A1_UDF_2_A_0_CFG_UDF_2_A_0 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_A_0_PAGE_A1_UDF_2_A_0_CFG_UDF_2_A_0(x) WriteReg(SWITCH_PAGE_A1_UDF_2_A_0,x)
#define Rd_switch_PAGE_A1_UDF_2_A_0_PAGE_A1_UDF_2_A_0_CFG_UDF_2_A_0(x) ReadReg(SWITCH_PAGE_A1_UDF_2_A_0)
#define SWITCH_PAGE_A1_UDF_2_A_0_PAGE_A1_UDF_2_A_0_CFG_UDF_2_A_0_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_A_0_PAGE_A1_UDF_2_A_0_CFG_UDF_2_A_0_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_A_0_PAGE_A1_UDF_2_A_0_CFG_UDF_2_A_0_BITS 8
#define SWITCH_PAGE_A1_UDF_2_A_0_PAGE_A1_UDF_2_A_0_CFG_UDF_2_A_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_A_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_A_1 :: PAGE_A1_UDF_2_A_1_CFG_UDF_2_A_1 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_A_1_PAGE_A1_UDF_2_A_1_CFG_UDF_2_A_1(x) WriteReg(SWITCH_PAGE_A1_UDF_2_A_1,x)
#define Rd_switch_PAGE_A1_UDF_2_A_1_PAGE_A1_UDF_2_A_1_CFG_UDF_2_A_1(x) ReadReg(SWITCH_PAGE_A1_UDF_2_A_1)
#define SWITCH_PAGE_A1_UDF_2_A_1_PAGE_A1_UDF_2_A_1_CFG_UDF_2_A_1_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_A_1_PAGE_A1_UDF_2_A_1_CFG_UDF_2_A_1_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_A_1_PAGE_A1_UDF_2_A_1_CFG_UDF_2_A_1_BITS 8
#define SWITCH_PAGE_A1_UDF_2_A_1_PAGE_A1_UDF_2_A_1_CFG_UDF_2_A_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_A_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_A_2 :: PAGE_A1_UDF_2_A_2_CFG_UDF_2_A_2 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_A_2_PAGE_A1_UDF_2_A_2_CFG_UDF_2_A_2(x) WriteReg(SWITCH_PAGE_A1_UDF_2_A_2,x)
#define Rd_switch_PAGE_A1_UDF_2_A_2_PAGE_A1_UDF_2_A_2_CFG_UDF_2_A_2(x) ReadReg(SWITCH_PAGE_A1_UDF_2_A_2)
#define SWITCH_PAGE_A1_UDF_2_A_2_PAGE_A1_UDF_2_A_2_CFG_UDF_2_A_2_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_A_2_PAGE_A1_UDF_2_A_2_CFG_UDF_2_A_2_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_A_2_PAGE_A1_UDF_2_A_2_CFG_UDF_2_A_2_BITS 8
#define SWITCH_PAGE_A1_UDF_2_A_2_PAGE_A1_UDF_2_A_2_CFG_UDF_2_A_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_A_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_A_3 :: PAGE_A1_UDF_2_A_3_CFG_UDF_2_A_3 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_A_3_PAGE_A1_UDF_2_A_3_CFG_UDF_2_A_3(x) WriteReg(SWITCH_PAGE_A1_UDF_2_A_3,x)
#define Rd_switch_PAGE_A1_UDF_2_A_3_PAGE_A1_UDF_2_A_3_CFG_UDF_2_A_3(x) ReadReg(SWITCH_PAGE_A1_UDF_2_A_3)
#define SWITCH_PAGE_A1_UDF_2_A_3_PAGE_A1_UDF_2_A_3_CFG_UDF_2_A_3_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_A_3_PAGE_A1_UDF_2_A_3_CFG_UDF_2_A_3_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_A_3_PAGE_A1_UDF_2_A_3_CFG_UDF_2_A_3_BITS 8
#define SWITCH_PAGE_A1_UDF_2_A_3_PAGE_A1_UDF_2_A_3_CFG_UDF_2_A_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_A_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_A_4 :: PAGE_A1_UDF_2_A_4_CFG_UDF_2_A_4 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_A_4_PAGE_A1_UDF_2_A_4_CFG_UDF_2_A_4(x) WriteReg(SWITCH_PAGE_A1_UDF_2_A_4,x)
#define Rd_switch_PAGE_A1_UDF_2_A_4_PAGE_A1_UDF_2_A_4_CFG_UDF_2_A_4(x) ReadReg(SWITCH_PAGE_A1_UDF_2_A_4)
#define SWITCH_PAGE_A1_UDF_2_A_4_PAGE_A1_UDF_2_A_4_CFG_UDF_2_A_4_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_A_4_PAGE_A1_UDF_2_A_4_CFG_UDF_2_A_4_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_A_4_PAGE_A1_UDF_2_A_4_CFG_UDF_2_A_4_BITS 8
#define SWITCH_PAGE_A1_UDF_2_A_4_PAGE_A1_UDF_2_A_4_CFG_UDF_2_A_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_A_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_A_5 :: PAGE_A1_UDF_2_A_5_CFG_UDF_2_A_5 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_A_5_PAGE_A1_UDF_2_A_5_CFG_UDF_2_A_5(x) WriteReg(SWITCH_PAGE_A1_UDF_2_A_5,x)
#define Rd_switch_PAGE_A1_UDF_2_A_5_PAGE_A1_UDF_2_A_5_CFG_UDF_2_A_5(x) ReadReg(SWITCH_PAGE_A1_UDF_2_A_5)
#define SWITCH_PAGE_A1_UDF_2_A_5_PAGE_A1_UDF_2_A_5_CFG_UDF_2_A_5_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_A_5_PAGE_A1_UDF_2_A_5_CFG_UDF_2_A_5_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_A_5_PAGE_A1_UDF_2_A_5_CFG_UDF_2_A_5_BITS 8
#define SWITCH_PAGE_A1_UDF_2_A_5_PAGE_A1_UDF_2_A_5_CFG_UDF_2_A_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_A_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_A_6 :: PAGE_A1_UDF_2_A_6_CFG_UDF_2_A_6 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_A_6_PAGE_A1_UDF_2_A_6_CFG_UDF_2_A_6(x) WriteReg(SWITCH_PAGE_A1_UDF_2_A_6,x)
#define Rd_switch_PAGE_A1_UDF_2_A_6_PAGE_A1_UDF_2_A_6_CFG_UDF_2_A_6(x) ReadReg(SWITCH_PAGE_A1_UDF_2_A_6)
#define SWITCH_PAGE_A1_UDF_2_A_6_PAGE_A1_UDF_2_A_6_CFG_UDF_2_A_6_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_A_6_PAGE_A1_UDF_2_A_6_CFG_UDF_2_A_6_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_A_6_PAGE_A1_UDF_2_A_6_CFG_UDF_2_A_6_BITS 8
#define SWITCH_PAGE_A1_UDF_2_A_6_PAGE_A1_UDF_2_A_6_CFG_UDF_2_A_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_A_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_A_7 :: PAGE_A1_UDF_2_A_7_CFG_UDF_2_A_7 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_A_7_PAGE_A1_UDF_2_A_7_CFG_UDF_2_A_7(x) WriteReg(SWITCH_PAGE_A1_UDF_2_A_7,x)
#define Rd_switch_PAGE_A1_UDF_2_A_7_PAGE_A1_UDF_2_A_7_CFG_UDF_2_A_7(x) ReadReg(SWITCH_PAGE_A1_UDF_2_A_7)
#define SWITCH_PAGE_A1_UDF_2_A_7_PAGE_A1_UDF_2_A_7_CFG_UDF_2_A_7_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_A_7_PAGE_A1_UDF_2_A_7_CFG_UDF_2_A_7_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_A_7_PAGE_A1_UDF_2_A_7_CFG_UDF_2_A_7_BITS 8
#define SWITCH_PAGE_A1_UDF_2_A_7_PAGE_A1_UDF_2_A_7_CFG_UDF_2_A_7_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_A_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_A_8 :: PAGE_A1_UDF_2_A_8_CFG_UDF_2_A_8 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_A_8_PAGE_A1_UDF_2_A_8_CFG_UDF_2_A_8(x) WriteReg(SWITCH_PAGE_A1_UDF_2_A_8,x)
#define Rd_switch_PAGE_A1_UDF_2_A_8_PAGE_A1_UDF_2_A_8_CFG_UDF_2_A_8(x) ReadReg(SWITCH_PAGE_A1_UDF_2_A_8)
#define SWITCH_PAGE_A1_UDF_2_A_8_PAGE_A1_UDF_2_A_8_CFG_UDF_2_A_8_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_A_8_PAGE_A1_UDF_2_A_8_CFG_UDF_2_A_8_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_A_8_PAGE_A1_UDF_2_A_8_CFG_UDF_2_A_8_BITS 8
#define SWITCH_PAGE_A1_UDF_2_A_8_PAGE_A1_UDF_2_A_8_CFG_UDF_2_A_8_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_B_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_B_0 :: PAGE_A1_UDF_0_B_0_CFG_UDF_0_B_0 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_B_0_PAGE_A1_UDF_0_B_0_CFG_UDF_0_B_0(x) WriteReg(SWITCH_PAGE_A1_UDF_0_B_0,x)
#define Rd_switch_PAGE_A1_UDF_0_B_0_PAGE_A1_UDF_0_B_0_CFG_UDF_0_B_0(x) ReadReg(SWITCH_PAGE_A1_UDF_0_B_0)
#define SWITCH_PAGE_A1_UDF_0_B_0_PAGE_A1_UDF_0_B_0_CFG_UDF_0_B_0_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_B_0_PAGE_A1_UDF_0_B_0_CFG_UDF_0_B_0_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_B_0_PAGE_A1_UDF_0_B_0_CFG_UDF_0_B_0_BITS 8
#define SWITCH_PAGE_A1_UDF_0_B_0_PAGE_A1_UDF_0_B_0_CFG_UDF_0_B_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_B_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_B_1 :: PAGE_A1_UDF_0_B_1_CFG_UDF_0_B_1 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_B_1_PAGE_A1_UDF_0_B_1_CFG_UDF_0_B_1(x) WriteReg(SWITCH_PAGE_A1_UDF_0_B_1,x)
#define Rd_switch_PAGE_A1_UDF_0_B_1_PAGE_A1_UDF_0_B_1_CFG_UDF_0_B_1(x) ReadReg(SWITCH_PAGE_A1_UDF_0_B_1)
#define SWITCH_PAGE_A1_UDF_0_B_1_PAGE_A1_UDF_0_B_1_CFG_UDF_0_B_1_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_B_1_PAGE_A1_UDF_0_B_1_CFG_UDF_0_B_1_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_B_1_PAGE_A1_UDF_0_B_1_CFG_UDF_0_B_1_BITS 8
#define SWITCH_PAGE_A1_UDF_0_B_1_PAGE_A1_UDF_0_B_1_CFG_UDF_0_B_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_B_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_B_2 :: PAGE_A1_UDF_0_B_2_CFG_UDF_0_B_2 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_B_2_PAGE_A1_UDF_0_B_2_CFG_UDF_0_B_2(x) WriteReg(SWITCH_PAGE_A1_UDF_0_B_2,x)
#define Rd_switch_PAGE_A1_UDF_0_B_2_PAGE_A1_UDF_0_B_2_CFG_UDF_0_B_2(x) ReadReg(SWITCH_PAGE_A1_UDF_0_B_2)
#define SWITCH_PAGE_A1_UDF_0_B_2_PAGE_A1_UDF_0_B_2_CFG_UDF_0_B_2_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_B_2_PAGE_A1_UDF_0_B_2_CFG_UDF_0_B_2_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_B_2_PAGE_A1_UDF_0_B_2_CFG_UDF_0_B_2_BITS 8
#define SWITCH_PAGE_A1_UDF_0_B_2_PAGE_A1_UDF_0_B_2_CFG_UDF_0_B_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_B_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_B_3 :: PAGE_A1_UDF_0_B_3_CFG_UDF_0_B_3 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_B_3_PAGE_A1_UDF_0_B_3_CFG_UDF_0_B_3(x) WriteReg(SWITCH_PAGE_A1_UDF_0_B_3,x)
#define Rd_switch_PAGE_A1_UDF_0_B_3_PAGE_A1_UDF_0_B_3_CFG_UDF_0_B_3(x) ReadReg(SWITCH_PAGE_A1_UDF_0_B_3)
#define SWITCH_PAGE_A1_UDF_0_B_3_PAGE_A1_UDF_0_B_3_CFG_UDF_0_B_3_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_B_3_PAGE_A1_UDF_0_B_3_CFG_UDF_0_B_3_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_B_3_PAGE_A1_UDF_0_B_3_CFG_UDF_0_B_3_BITS 8
#define SWITCH_PAGE_A1_UDF_0_B_3_PAGE_A1_UDF_0_B_3_CFG_UDF_0_B_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_B_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_B_4 :: PAGE_A1_UDF_0_B_4_CFG_UDF_0_B_4 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_B_4_PAGE_A1_UDF_0_B_4_CFG_UDF_0_B_4(x) WriteReg(SWITCH_PAGE_A1_UDF_0_B_4,x)
#define Rd_switch_PAGE_A1_UDF_0_B_4_PAGE_A1_UDF_0_B_4_CFG_UDF_0_B_4(x) ReadReg(SWITCH_PAGE_A1_UDF_0_B_4)
#define SWITCH_PAGE_A1_UDF_0_B_4_PAGE_A1_UDF_0_B_4_CFG_UDF_0_B_4_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_B_4_PAGE_A1_UDF_0_B_4_CFG_UDF_0_B_4_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_B_4_PAGE_A1_UDF_0_B_4_CFG_UDF_0_B_4_BITS 8
#define SWITCH_PAGE_A1_UDF_0_B_4_PAGE_A1_UDF_0_B_4_CFG_UDF_0_B_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_B_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_B_5 :: PAGE_A1_UDF_0_B_5_CFG_UDF_0_B_5 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_B_5_PAGE_A1_UDF_0_B_5_CFG_UDF_0_B_5(x) WriteReg(SWITCH_PAGE_A1_UDF_0_B_5,x)
#define Rd_switch_PAGE_A1_UDF_0_B_5_PAGE_A1_UDF_0_B_5_CFG_UDF_0_B_5(x) ReadReg(SWITCH_PAGE_A1_UDF_0_B_5)
#define SWITCH_PAGE_A1_UDF_0_B_5_PAGE_A1_UDF_0_B_5_CFG_UDF_0_B_5_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_B_5_PAGE_A1_UDF_0_B_5_CFG_UDF_0_B_5_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_B_5_PAGE_A1_UDF_0_B_5_CFG_UDF_0_B_5_BITS 8
#define SWITCH_PAGE_A1_UDF_0_B_5_PAGE_A1_UDF_0_B_5_CFG_UDF_0_B_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_B_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_B_6 :: PAGE_A1_UDF_0_B_6_CFG_UDF_0_B_6 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_B_6_PAGE_A1_UDF_0_B_6_CFG_UDF_0_B_6(x) WriteReg(SWITCH_PAGE_A1_UDF_0_B_6,x)
#define Rd_switch_PAGE_A1_UDF_0_B_6_PAGE_A1_UDF_0_B_6_CFG_UDF_0_B_6(x) ReadReg(SWITCH_PAGE_A1_UDF_0_B_6)
#define SWITCH_PAGE_A1_UDF_0_B_6_PAGE_A1_UDF_0_B_6_CFG_UDF_0_B_6_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_B_6_PAGE_A1_UDF_0_B_6_CFG_UDF_0_B_6_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_B_6_PAGE_A1_UDF_0_B_6_CFG_UDF_0_B_6_BITS 8
#define SWITCH_PAGE_A1_UDF_0_B_6_PAGE_A1_UDF_0_B_6_CFG_UDF_0_B_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_B_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_B_7 :: PAGE_A1_UDF_0_B_7_CFG_UDF_0_B_7 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_B_7_PAGE_A1_UDF_0_B_7_CFG_UDF_0_B_7(x) WriteReg(SWITCH_PAGE_A1_UDF_0_B_7,x)
#define Rd_switch_PAGE_A1_UDF_0_B_7_PAGE_A1_UDF_0_B_7_CFG_UDF_0_B_7(x) ReadReg(SWITCH_PAGE_A1_UDF_0_B_7)
#define SWITCH_PAGE_A1_UDF_0_B_7_PAGE_A1_UDF_0_B_7_CFG_UDF_0_B_7_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_B_7_PAGE_A1_UDF_0_B_7_CFG_UDF_0_B_7_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_B_7_PAGE_A1_UDF_0_B_7_CFG_UDF_0_B_7_BITS 8
#define SWITCH_PAGE_A1_UDF_0_B_7_PAGE_A1_UDF_0_B_7_CFG_UDF_0_B_7_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_B_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_B_8 :: PAGE_A1_UDF_0_B_8_CFG_UDF_0_B_8 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_B_8_PAGE_A1_UDF_0_B_8_CFG_UDF_0_B_8(x) WriteReg(SWITCH_PAGE_A1_UDF_0_B_8,x)
#define Rd_switch_PAGE_A1_UDF_0_B_8_PAGE_A1_UDF_0_B_8_CFG_UDF_0_B_8(x) ReadReg(SWITCH_PAGE_A1_UDF_0_B_8)
#define SWITCH_PAGE_A1_UDF_0_B_8_PAGE_A1_UDF_0_B_8_CFG_UDF_0_B_8_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_B_8_PAGE_A1_UDF_0_B_8_CFG_UDF_0_B_8_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_B_8_PAGE_A1_UDF_0_B_8_CFG_UDF_0_B_8_BITS 8
#define SWITCH_PAGE_A1_UDF_0_B_8_PAGE_A1_UDF_0_B_8_CFG_UDF_0_B_8_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_B_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_B_0 :: PAGE_A1_UDF_1_B_0_CFG_UDF_1_B_0 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_B_0_PAGE_A1_UDF_1_B_0_CFG_UDF_1_B_0(x) WriteReg(SWITCH_PAGE_A1_UDF_1_B_0,x)
#define Rd_switch_PAGE_A1_UDF_1_B_0_PAGE_A1_UDF_1_B_0_CFG_UDF_1_B_0(x) ReadReg(SWITCH_PAGE_A1_UDF_1_B_0)
#define SWITCH_PAGE_A1_UDF_1_B_0_PAGE_A1_UDF_1_B_0_CFG_UDF_1_B_0_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_B_0_PAGE_A1_UDF_1_B_0_CFG_UDF_1_B_0_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_B_0_PAGE_A1_UDF_1_B_0_CFG_UDF_1_B_0_BITS 8
#define SWITCH_PAGE_A1_UDF_1_B_0_PAGE_A1_UDF_1_B_0_CFG_UDF_1_B_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_B_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_B_1 :: PAGE_A1_UDF_1_B_1_CFG_UDF_1_B_1 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_B_1_PAGE_A1_UDF_1_B_1_CFG_UDF_1_B_1(x) WriteReg(SWITCH_PAGE_A1_UDF_1_B_1,x)
#define Rd_switch_PAGE_A1_UDF_1_B_1_PAGE_A1_UDF_1_B_1_CFG_UDF_1_B_1(x) ReadReg(SWITCH_PAGE_A1_UDF_1_B_1)
#define SWITCH_PAGE_A1_UDF_1_B_1_PAGE_A1_UDF_1_B_1_CFG_UDF_1_B_1_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_B_1_PAGE_A1_UDF_1_B_1_CFG_UDF_1_B_1_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_B_1_PAGE_A1_UDF_1_B_1_CFG_UDF_1_B_1_BITS 8
#define SWITCH_PAGE_A1_UDF_1_B_1_PAGE_A1_UDF_1_B_1_CFG_UDF_1_B_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_B_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_B_2 :: PAGE_A1_UDF_1_B_2_CFG_UDF_1_B_2 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_B_2_PAGE_A1_UDF_1_B_2_CFG_UDF_1_B_2(x) WriteReg(SWITCH_PAGE_A1_UDF_1_B_2,x)
#define Rd_switch_PAGE_A1_UDF_1_B_2_PAGE_A1_UDF_1_B_2_CFG_UDF_1_B_2(x) ReadReg(SWITCH_PAGE_A1_UDF_1_B_2)
#define SWITCH_PAGE_A1_UDF_1_B_2_PAGE_A1_UDF_1_B_2_CFG_UDF_1_B_2_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_B_2_PAGE_A1_UDF_1_B_2_CFG_UDF_1_B_2_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_B_2_PAGE_A1_UDF_1_B_2_CFG_UDF_1_B_2_BITS 8
#define SWITCH_PAGE_A1_UDF_1_B_2_PAGE_A1_UDF_1_B_2_CFG_UDF_1_B_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_B_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_B_3 :: PAGE_A1_UDF_1_B_3_CFG_UDF_1_B_3 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_B_3_PAGE_A1_UDF_1_B_3_CFG_UDF_1_B_3(x) WriteReg(SWITCH_PAGE_A1_UDF_1_B_3,x)
#define Rd_switch_PAGE_A1_UDF_1_B_3_PAGE_A1_UDF_1_B_3_CFG_UDF_1_B_3(x) ReadReg(SWITCH_PAGE_A1_UDF_1_B_3)
#define SWITCH_PAGE_A1_UDF_1_B_3_PAGE_A1_UDF_1_B_3_CFG_UDF_1_B_3_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_B_3_PAGE_A1_UDF_1_B_3_CFG_UDF_1_B_3_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_B_3_PAGE_A1_UDF_1_B_3_CFG_UDF_1_B_3_BITS 8
#define SWITCH_PAGE_A1_UDF_1_B_3_PAGE_A1_UDF_1_B_3_CFG_UDF_1_B_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_B_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_B_4 :: PAGE_A1_UDF_1_B_4_CFG_UDF_1_B_4 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_B_4_PAGE_A1_UDF_1_B_4_CFG_UDF_1_B_4(x) WriteReg(SWITCH_PAGE_A1_UDF_1_B_4,x)
#define Rd_switch_PAGE_A1_UDF_1_B_4_PAGE_A1_UDF_1_B_4_CFG_UDF_1_B_4(x) ReadReg(SWITCH_PAGE_A1_UDF_1_B_4)
#define SWITCH_PAGE_A1_UDF_1_B_4_PAGE_A1_UDF_1_B_4_CFG_UDF_1_B_4_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_B_4_PAGE_A1_UDF_1_B_4_CFG_UDF_1_B_4_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_B_4_PAGE_A1_UDF_1_B_4_CFG_UDF_1_B_4_BITS 8
#define SWITCH_PAGE_A1_UDF_1_B_4_PAGE_A1_UDF_1_B_4_CFG_UDF_1_B_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_B_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_B_5 :: PAGE_A1_UDF_1_B_5_CFG_UDF_1_B_5 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_B_5_PAGE_A1_UDF_1_B_5_CFG_UDF_1_B_5(x) WriteReg(SWITCH_PAGE_A1_UDF_1_B_5,x)
#define Rd_switch_PAGE_A1_UDF_1_B_5_PAGE_A1_UDF_1_B_5_CFG_UDF_1_B_5(x) ReadReg(SWITCH_PAGE_A1_UDF_1_B_5)
#define SWITCH_PAGE_A1_UDF_1_B_5_PAGE_A1_UDF_1_B_5_CFG_UDF_1_B_5_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_B_5_PAGE_A1_UDF_1_B_5_CFG_UDF_1_B_5_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_B_5_PAGE_A1_UDF_1_B_5_CFG_UDF_1_B_5_BITS 8
#define SWITCH_PAGE_A1_UDF_1_B_5_PAGE_A1_UDF_1_B_5_CFG_UDF_1_B_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_B_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_B_6 :: PAGE_A1_UDF_1_B_6_CFG_UDF_1_B_6 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_B_6_PAGE_A1_UDF_1_B_6_CFG_UDF_1_B_6(x) WriteReg(SWITCH_PAGE_A1_UDF_1_B_6,x)
#define Rd_switch_PAGE_A1_UDF_1_B_6_PAGE_A1_UDF_1_B_6_CFG_UDF_1_B_6(x) ReadReg(SWITCH_PAGE_A1_UDF_1_B_6)
#define SWITCH_PAGE_A1_UDF_1_B_6_PAGE_A1_UDF_1_B_6_CFG_UDF_1_B_6_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_B_6_PAGE_A1_UDF_1_B_6_CFG_UDF_1_B_6_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_B_6_PAGE_A1_UDF_1_B_6_CFG_UDF_1_B_6_BITS 8
#define SWITCH_PAGE_A1_UDF_1_B_6_PAGE_A1_UDF_1_B_6_CFG_UDF_1_B_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_B_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_B_7 :: PAGE_A1_UDF_1_B_7_CFG_UDF_1_B_7 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_B_7_PAGE_A1_UDF_1_B_7_CFG_UDF_1_B_7(x) WriteReg(SWITCH_PAGE_A1_UDF_1_B_7,x)
#define Rd_switch_PAGE_A1_UDF_1_B_7_PAGE_A1_UDF_1_B_7_CFG_UDF_1_B_7(x) ReadReg(SWITCH_PAGE_A1_UDF_1_B_7)
#define SWITCH_PAGE_A1_UDF_1_B_7_PAGE_A1_UDF_1_B_7_CFG_UDF_1_B_7_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_B_7_PAGE_A1_UDF_1_B_7_CFG_UDF_1_B_7_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_B_7_PAGE_A1_UDF_1_B_7_CFG_UDF_1_B_7_BITS 8
#define SWITCH_PAGE_A1_UDF_1_B_7_PAGE_A1_UDF_1_B_7_CFG_UDF_1_B_7_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_B_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_B_8 :: PAGE_A1_UDF_1_B_8_CFG_UDF_1_B_8 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_B_8_PAGE_A1_UDF_1_B_8_CFG_UDF_1_B_8(x) WriteReg(SWITCH_PAGE_A1_UDF_1_B_8,x)
#define Rd_switch_PAGE_A1_UDF_1_B_8_PAGE_A1_UDF_1_B_8_CFG_UDF_1_B_8(x) ReadReg(SWITCH_PAGE_A1_UDF_1_B_8)
#define SWITCH_PAGE_A1_UDF_1_B_8_PAGE_A1_UDF_1_B_8_CFG_UDF_1_B_8_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_B_8_PAGE_A1_UDF_1_B_8_CFG_UDF_1_B_8_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_B_8_PAGE_A1_UDF_1_B_8_CFG_UDF_1_B_8_BITS 8
#define SWITCH_PAGE_A1_UDF_1_B_8_PAGE_A1_UDF_1_B_8_CFG_UDF_1_B_8_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_B_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_B_0 :: PAGE_A1_UDF_2_B_0_CFG_UDF_2_B_0 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_B_0_PAGE_A1_UDF_2_B_0_CFG_UDF_2_B_0(x) WriteReg(SWITCH_PAGE_A1_UDF_2_B_0,x)
#define Rd_switch_PAGE_A1_UDF_2_B_0_PAGE_A1_UDF_2_B_0_CFG_UDF_2_B_0(x) ReadReg(SWITCH_PAGE_A1_UDF_2_B_0)
#define SWITCH_PAGE_A1_UDF_2_B_0_PAGE_A1_UDF_2_B_0_CFG_UDF_2_B_0_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_B_0_PAGE_A1_UDF_2_B_0_CFG_UDF_2_B_0_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_B_0_PAGE_A1_UDF_2_B_0_CFG_UDF_2_B_0_BITS 8
#define SWITCH_PAGE_A1_UDF_2_B_0_PAGE_A1_UDF_2_B_0_CFG_UDF_2_B_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_B_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_B_1 :: PAGE_A1_UDF_2_B_1_CFG_UDF_2_B_1 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_B_1_PAGE_A1_UDF_2_B_1_CFG_UDF_2_B_1(x) WriteReg(SWITCH_PAGE_A1_UDF_2_B_1,x)
#define Rd_switch_PAGE_A1_UDF_2_B_1_PAGE_A1_UDF_2_B_1_CFG_UDF_2_B_1(x) ReadReg(SWITCH_PAGE_A1_UDF_2_B_1)
#define SWITCH_PAGE_A1_UDF_2_B_1_PAGE_A1_UDF_2_B_1_CFG_UDF_2_B_1_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_B_1_PAGE_A1_UDF_2_B_1_CFG_UDF_2_B_1_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_B_1_PAGE_A1_UDF_2_B_1_CFG_UDF_2_B_1_BITS 8
#define SWITCH_PAGE_A1_UDF_2_B_1_PAGE_A1_UDF_2_B_1_CFG_UDF_2_B_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_B_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_B_2 :: PAGE_A1_UDF_2_B_2_CFG_UDF_2_B_2 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_B_2_PAGE_A1_UDF_2_B_2_CFG_UDF_2_B_2(x) WriteReg(SWITCH_PAGE_A1_UDF_2_B_2,x)
#define Rd_switch_PAGE_A1_UDF_2_B_2_PAGE_A1_UDF_2_B_2_CFG_UDF_2_B_2(x) ReadReg(SWITCH_PAGE_A1_UDF_2_B_2)
#define SWITCH_PAGE_A1_UDF_2_B_2_PAGE_A1_UDF_2_B_2_CFG_UDF_2_B_2_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_B_2_PAGE_A1_UDF_2_B_2_CFG_UDF_2_B_2_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_B_2_PAGE_A1_UDF_2_B_2_CFG_UDF_2_B_2_BITS 8
#define SWITCH_PAGE_A1_UDF_2_B_2_PAGE_A1_UDF_2_B_2_CFG_UDF_2_B_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_B_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_B_3 :: PAGE_A1_UDF_2_B_3_CFG_UDF_2_B_3 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_B_3_PAGE_A1_UDF_2_B_3_CFG_UDF_2_B_3(x) WriteReg(SWITCH_PAGE_A1_UDF_2_B_3,x)
#define Rd_switch_PAGE_A1_UDF_2_B_3_PAGE_A1_UDF_2_B_3_CFG_UDF_2_B_3(x) ReadReg(SWITCH_PAGE_A1_UDF_2_B_3)
#define SWITCH_PAGE_A1_UDF_2_B_3_PAGE_A1_UDF_2_B_3_CFG_UDF_2_B_3_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_B_3_PAGE_A1_UDF_2_B_3_CFG_UDF_2_B_3_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_B_3_PAGE_A1_UDF_2_B_3_CFG_UDF_2_B_3_BITS 8
#define SWITCH_PAGE_A1_UDF_2_B_3_PAGE_A1_UDF_2_B_3_CFG_UDF_2_B_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_B_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_B_4 :: PAGE_A1_UDF_2_B_4_CFG_UDF_2_B_4 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_B_4_PAGE_A1_UDF_2_B_4_CFG_UDF_2_B_4(x) WriteReg(SWITCH_PAGE_A1_UDF_2_B_4,x)
#define Rd_switch_PAGE_A1_UDF_2_B_4_PAGE_A1_UDF_2_B_4_CFG_UDF_2_B_4(x) ReadReg(SWITCH_PAGE_A1_UDF_2_B_4)
#define SWITCH_PAGE_A1_UDF_2_B_4_PAGE_A1_UDF_2_B_4_CFG_UDF_2_B_4_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_B_4_PAGE_A1_UDF_2_B_4_CFG_UDF_2_B_4_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_B_4_PAGE_A1_UDF_2_B_4_CFG_UDF_2_B_4_BITS 8
#define SWITCH_PAGE_A1_UDF_2_B_4_PAGE_A1_UDF_2_B_4_CFG_UDF_2_B_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_B_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_B_5 :: PAGE_A1_UDF_2_B_5_CFG_UDF_2_B_5 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_B_5_PAGE_A1_UDF_2_B_5_CFG_UDF_2_B_5(x) WriteReg(SWITCH_PAGE_A1_UDF_2_B_5,x)
#define Rd_switch_PAGE_A1_UDF_2_B_5_PAGE_A1_UDF_2_B_5_CFG_UDF_2_B_5(x) ReadReg(SWITCH_PAGE_A1_UDF_2_B_5)
#define SWITCH_PAGE_A1_UDF_2_B_5_PAGE_A1_UDF_2_B_5_CFG_UDF_2_B_5_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_B_5_PAGE_A1_UDF_2_B_5_CFG_UDF_2_B_5_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_B_5_PAGE_A1_UDF_2_B_5_CFG_UDF_2_B_5_BITS 8
#define SWITCH_PAGE_A1_UDF_2_B_5_PAGE_A1_UDF_2_B_5_CFG_UDF_2_B_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_B_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_B_6 :: PAGE_A1_UDF_2_B_6_CFG_UDF_2_B_6 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_B_6_PAGE_A1_UDF_2_B_6_CFG_UDF_2_B_6(x) WriteReg(SWITCH_PAGE_A1_UDF_2_B_6,x)
#define Rd_switch_PAGE_A1_UDF_2_B_6_PAGE_A1_UDF_2_B_6_CFG_UDF_2_B_6(x) ReadReg(SWITCH_PAGE_A1_UDF_2_B_6)
#define SWITCH_PAGE_A1_UDF_2_B_6_PAGE_A1_UDF_2_B_6_CFG_UDF_2_B_6_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_B_6_PAGE_A1_UDF_2_B_6_CFG_UDF_2_B_6_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_B_6_PAGE_A1_UDF_2_B_6_CFG_UDF_2_B_6_BITS 8
#define SWITCH_PAGE_A1_UDF_2_B_6_PAGE_A1_UDF_2_B_6_CFG_UDF_2_B_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_B_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_B_7 :: PAGE_A1_UDF_2_B_7_CFG_UDF_2_B_7 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_B_7_PAGE_A1_UDF_2_B_7_CFG_UDF_2_B_7(x) WriteReg(SWITCH_PAGE_A1_UDF_2_B_7,x)
#define Rd_switch_PAGE_A1_UDF_2_B_7_PAGE_A1_UDF_2_B_7_CFG_UDF_2_B_7(x) ReadReg(SWITCH_PAGE_A1_UDF_2_B_7)
#define SWITCH_PAGE_A1_UDF_2_B_7_PAGE_A1_UDF_2_B_7_CFG_UDF_2_B_7_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_B_7_PAGE_A1_UDF_2_B_7_CFG_UDF_2_B_7_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_B_7_PAGE_A1_UDF_2_B_7_CFG_UDF_2_B_7_BITS 8
#define SWITCH_PAGE_A1_UDF_2_B_7_PAGE_A1_UDF_2_B_7_CFG_UDF_2_B_7_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_B_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_B_8 :: PAGE_A1_UDF_2_B_8_CFG_UDF_2_B_8 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_B_8_PAGE_A1_UDF_2_B_8_CFG_UDF_2_B_8(x) WriteReg(SWITCH_PAGE_A1_UDF_2_B_8,x)
#define Rd_switch_PAGE_A1_UDF_2_B_8_PAGE_A1_UDF_2_B_8_CFG_UDF_2_B_8(x) ReadReg(SWITCH_PAGE_A1_UDF_2_B_8)
#define SWITCH_PAGE_A1_UDF_2_B_8_PAGE_A1_UDF_2_B_8_CFG_UDF_2_B_8_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_B_8_PAGE_A1_UDF_2_B_8_CFG_UDF_2_B_8_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_B_8_PAGE_A1_UDF_2_B_8_CFG_UDF_2_B_8_BITS 8
#define SWITCH_PAGE_A1_UDF_2_B_8_PAGE_A1_UDF_2_B_8_CFG_UDF_2_B_8_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_C_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_C_0 :: PAGE_A1_UDF_0_C_0_CFG_UDF_0_C_0 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_C_0_PAGE_A1_UDF_0_C_0_CFG_UDF_0_C_0(x) WriteReg(SWITCH_PAGE_A1_UDF_0_C_0,x)
#define Rd_switch_PAGE_A1_UDF_0_C_0_PAGE_A1_UDF_0_C_0_CFG_UDF_0_C_0(x) ReadReg(SWITCH_PAGE_A1_UDF_0_C_0)
#define SWITCH_PAGE_A1_UDF_0_C_0_PAGE_A1_UDF_0_C_0_CFG_UDF_0_C_0_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_C_0_PAGE_A1_UDF_0_C_0_CFG_UDF_0_C_0_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_C_0_PAGE_A1_UDF_0_C_0_CFG_UDF_0_C_0_BITS 8
#define SWITCH_PAGE_A1_UDF_0_C_0_PAGE_A1_UDF_0_C_0_CFG_UDF_0_C_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_C_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_C_1 :: PAGE_A1_UDF_0_C_1_CFG_UDF_0_C_1 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_C_1_PAGE_A1_UDF_0_C_1_CFG_UDF_0_C_1(x) WriteReg(SWITCH_PAGE_A1_UDF_0_C_1,x)
#define Rd_switch_PAGE_A1_UDF_0_C_1_PAGE_A1_UDF_0_C_1_CFG_UDF_0_C_1(x) ReadReg(SWITCH_PAGE_A1_UDF_0_C_1)
#define SWITCH_PAGE_A1_UDF_0_C_1_PAGE_A1_UDF_0_C_1_CFG_UDF_0_C_1_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_C_1_PAGE_A1_UDF_0_C_1_CFG_UDF_0_C_1_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_C_1_PAGE_A1_UDF_0_C_1_CFG_UDF_0_C_1_BITS 8
#define SWITCH_PAGE_A1_UDF_0_C_1_PAGE_A1_UDF_0_C_1_CFG_UDF_0_C_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_C_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_C_2 :: PAGE_A1_UDF_0_C_2_CFG_UDF_0_C_2 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_C_2_PAGE_A1_UDF_0_C_2_CFG_UDF_0_C_2(x) WriteReg(SWITCH_PAGE_A1_UDF_0_C_2,x)
#define Rd_switch_PAGE_A1_UDF_0_C_2_PAGE_A1_UDF_0_C_2_CFG_UDF_0_C_2(x) ReadReg(SWITCH_PAGE_A1_UDF_0_C_2)
#define SWITCH_PAGE_A1_UDF_0_C_2_PAGE_A1_UDF_0_C_2_CFG_UDF_0_C_2_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_C_2_PAGE_A1_UDF_0_C_2_CFG_UDF_0_C_2_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_C_2_PAGE_A1_UDF_0_C_2_CFG_UDF_0_C_2_BITS 8
#define SWITCH_PAGE_A1_UDF_0_C_2_PAGE_A1_UDF_0_C_2_CFG_UDF_0_C_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_C_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_C_3 :: PAGE_A1_UDF_0_C_3_CFG_UDF_0_C_3 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_C_3_PAGE_A1_UDF_0_C_3_CFG_UDF_0_C_3(x) WriteReg(SWITCH_PAGE_A1_UDF_0_C_3,x)
#define Rd_switch_PAGE_A1_UDF_0_C_3_PAGE_A1_UDF_0_C_3_CFG_UDF_0_C_3(x) ReadReg(SWITCH_PAGE_A1_UDF_0_C_3)
#define SWITCH_PAGE_A1_UDF_0_C_3_PAGE_A1_UDF_0_C_3_CFG_UDF_0_C_3_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_C_3_PAGE_A1_UDF_0_C_3_CFG_UDF_0_C_3_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_C_3_PAGE_A1_UDF_0_C_3_CFG_UDF_0_C_3_BITS 8
#define SWITCH_PAGE_A1_UDF_0_C_3_PAGE_A1_UDF_0_C_3_CFG_UDF_0_C_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_C_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_C_4 :: PAGE_A1_UDF_0_C_4_CFG_UDF_0_C_4 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_C_4_PAGE_A1_UDF_0_C_4_CFG_UDF_0_C_4(x) WriteReg(SWITCH_PAGE_A1_UDF_0_C_4,x)
#define Rd_switch_PAGE_A1_UDF_0_C_4_PAGE_A1_UDF_0_C_4_CFG_UDF_0_C_4(x) ReadReg(SWITCH_PAGE_A1_UDF_0_C_4)
#define SWITCH_PAGE_A1_UDF_0_C_4_PAGE_A1_UDF_0_C_4_CFG_UDF_0_C_4_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_C_4_PAGE_A1_UDF_0_C_4_CFG_UDF_0_C_4_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_C_4_PAGE_A1_UDF_0_C_4_CFG_UDF_0_C_4_BITS 8
#define SWITCH_PAGE_A1_UDF_0_C_4_PAGE_A1_UDF_0_C_4_CFG_UDF_0_C_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_C_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_C_5 :: PAGE_A1_UDF_0_C_5_CFG_UDF_0_C_5 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_C_5_PAGE_A1_UDF_0_C_5_CFG_UDF_0_C_5(x) WriteReg(SWITCH_PAGE_A1_UDF_0_C_5,x)
#define Rd_switch_PAGE_A1_UDF_0_C_5_PAGE_A1_UDF_0_C_5_CFG_UDF_0_C_5(x) ReadReg(SWITCH_PAGE_A1_UDF_0_C_5)
#define SWITCH_PAGE_A1_UDF_0_C_5_PAGE_A1_UDF_0_C_5_CFG_UDF_0_C_5_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_C_5_PAGE_A1_UDF_0_C_5_CFG_UDF_0_C_5_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_C_5_PAGE_A1_UDF_0_C_5_CFG_UDF_0_C_5_BITS 8
#define SWITCH_PAGE_A1_UDF_0_C_5_PAGE_A1_UDF_0_C_5_CFG_UDF_0_C_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_C_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_C_6 :: PAGE_A1_UDF_0_C_6_CFG_UDF_0_C_6 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_C_6_PAGE_A1_UDF_0_C_6_CFG_UDF_0_C_6(x) WriteReg(SWITCH_PAGE_A1_UDF_0_C_6,x)
#define Rd_switch_PAGE_A1_UDF_0_C_6_PAGE_A1_UDF_0_C_6_CFG_UDF_0_C_6(x) ReadReg(SWITCH_PAGE_A1_UDF_0_C_6)
#define SWITCH_PAGE_A1_UDF_0_C_6_PAGE_A1_UDF_0_C_6_CFG_UDF_0_C_6_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_C_6_PAGE_A1_UDF_0_C_6_CFG_UDF_0_C_6_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_C_6_PAGE_A1_UDF_0_C_6_CFG_UDF_0_C_6_BITS 8
#define SWITCH_PAGE_A1_UDF_0_C_6_PAGE_A1_UDF_0_C_6_CFG_UDF_0_C_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_C_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_C_7 :: PAGE_A1_UDF_0_C_7_CFG_UDF_0_C_7 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_C_7_PAGE_A1_UDF_0_C_7_CFG_UDF_0_C_7(x) WriteReg(SWITCH_PAGE_A1_UDF_0_C_7,x)
#define Rd_switch_PAGE_A1_UDF_0_C_7_PAGE_A1_UDF_0_C_7_CFG_UDF_0_C_7(x) ReadReg(SWITCH_PAGE_A1_UDF_0_C_7)
#define SWITCH_PAGE_A1_UDF_0_C_7_PAGE_A1_UDF_0_C_7_CFG_UDF_0_C_7_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_C_7_PAGE_A1_UDF_0_C_7_CFG_UDF_0_C_7_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_C_7_PAGE_A1_UDF_0_C_7_CFG_UDF_0_C_7_BITS 8
#define SWITCH_PAGE_A1_UDF_0_C_7_PAGE_A1_UDF_0_C_7_CFG_UDF_0_C_7_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_C_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_C_8 :: PAGE_A1_UDF_0_C_8_CFG_UDF_0_C_8 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_C_8_PAGE_A1_UDF_0_C_8_CFG_UDF_0_C_8(x) WriteReg(SWITCH_PAGE_A1_UDF_0_C_8,x)
#define Rd_switch_PAGE_A1_UDF_0_C_8_PAGE_A1_UDF_0_C_8_CFG_UDF_0_C_8(x) ReadReg(SWITCH_PAGE_A1_UDF_0_C_8)
#define SWITCH_PAGE_A1_UDF_0_C_8_PAGE_A1_UDF_0_C_8_CFG_UDF_0_C_8_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_C_8_PAGE_A1_UDF_0_C_8_CFG_UDF_0_C_8_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_C_8_PAGE_A1_UDF_0_C_8_CFG_UDF_0_C_8_BITS 8
#define SWITCH_PAGE_A1_UDF_0_C_8_PAGE_A1_UDF_0_C_8_CFG_UDF_0_C_8_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_C_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_C_0 :: PAGE_A1_UDF_1_C_0_CFG_UDF_1_C_0 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_C_0_PAGE_A1_UDF_1_C_0_CFG_UDF_1_C_0(x) WriteReg(SWITCH_PAGE_A1_UDF_1_C_0,x)
#define Rd_switch_PAGE_A1_UDF_1_C_0_PAGE_A1_UDF_1_C_0_CFG_UDF_1_C_0(x) ReadReg(SWITCH_PAGE_A1_UDF_1_C_0)
#define SWITCH_PAGE_A1_UDF_1_C_0_PAGE_A1_UDF_1_C_0_CFG_UDF_1_C_0_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_C_0_PAGE_A1_UDF_1_C_0_CFG_UDF_1_C_0_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_C_0_PAGE_A1_UDF_1_C_0_CFG_UDF_1_C_0_BITS 8
#define SWITCH_PAGE_A1_UDF_1_C_0_PAGE_A1_UDF_1_C_0_CFG_UDF_1_C_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_C_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_C_1 :: PAGE_A1_UDF_1_C_1_CFG_UDF_1_C_1 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_C_1_PAGE_A1_UDF_1_C_1_CFG_UDF_1_C_1(x) WriteReg(SWITCH_PAGE_A1_UDF_1_C_1,x)
#define Rd_switch_PAGE_A1_UDF_1_C_1_PAGE_A1_UDF_1_C_1_CFG_UDF_1_C_1(x) ReadReg(SWITCH_PAGE_A1_UDF_1_C_1)
#define SWITCH_PAGE_A1_UDF_1_C_1_PAGE_A1_UDF_1_C_1_CFG_UDF_1_C_1_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_C_1_PAGE_A1_UDF_1_C_1_CFG_UDF_1_C_1_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_C_1_PAGE_A1_UDF_1_C_1_CFG_UDF_1_C_1_BITS 8
#define SWITCH_PAGE_A1_UDF_1_C_1_PAGE_A1_UDF_1_C_1_CFG_UDF_1_C_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_C_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_C_2 :: PAGE_A1_UDF_1_C_2_CFG_UDF_1_C_2 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_C_2_PAGE_A1_UDF_1_C_2_CFG_UDF_1_C_2(x) WriteReg(SWITCH_PAGE_A1_UDF_1_C_2,x)
#define Rd_switch_PAGE_A1_UDF_1_C_2_PAGE_A1_UDF_1_C_2_CFG_UDF_1_C_2(x) ReadReg(SWITCH_PAGE_A1_UDF_1_C_2)
#define SWITCH_PAGE_A1_UDF_1_C_2_PAGE_A1_UDF_1_C_2_CFG_UDF_1_C_2_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_C_2_PAGE_A1_UDF_1_C_2_CFG_UDF_1_C_2_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_C_2_PAGE_A1_UDF_1_C_2_CFG_UDF_1_C_2_BITS 8
#define SWITCH_PAGE_A1_UDF_1_C_2_PAGE_A1_UDF_1_C_2_CFG_UDF_1_C_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_C_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_C_3 :: PAGE_A1_UDF_1_C_3_CFG_UDF_1_C_3 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_C_3_PAGE_A1_UDF_1_C_3_CFG_UDF_1_C_3(x) WriteReg(SWITCH_PAGE_A1_UDF_1_C_3,x)
#define Rd_switch_PAGE_A1_UDF_1_C_3_PAGE_A1_UDF_1_C_3_CFG_UDF_1_C_3(x) ReadReg(SWITCH_PAGE_A1_UDF_1_C_3)
#define SWITCH_PAGE_A1_UDF_1_C_3_PAGE_A1_UDF_1_C_3_CFG_UDF_1_C_3_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_C_3_PAGE_A1_UDF_1_C_3_CFG_UDF_1_C_3_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_C_3_PAGE_A1_UDF_1_C_3_CFG_UDF_1_C_3_BITS 8
#define SWITCH_PAGE_A1_UDF_1_C_3_PAGE_A1_UDF_1_C_3_CFG_UDF_1_C_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_C_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_C_4 :: PAGE_A1_UDF_1_C_4_CFG_UDF_1_C_4 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_C_4_PAGE_A1_UDF_1_C_4_CFG_UDF_1_C_4(x) WriteReg(SWITCH_PAGE_A1_UDF_1_C_4,x)
#define Rd_switch_PAGE_A1_UDF_1_C_4_PAGE_A1_UDF_1_C_4_CFG_UDF_1_C_4(x) ReadReg(SWITCH_PAGE_A1_UDF_1_C_4)
#define SWITCH_PAGE_A1_UDF_1_C_4_PAGE_A1_UDF_1_C_4_CFG_UDF_1_C_4_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_C_4_PAGE_A1_UDF_1_C_4_CFG_UDF_1_C_4_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_C_4_PAGE_A1_UDF_1_C_4_CFG_UDF_1_C_4_BITS 8
#define SWITCH_PAGE_A1_UDF_1_C_4_PAGE_A1_UDF_1_C_4_CFG_UDF_1_C_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_C_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_C_5 :: PAGE_A1_UDF_1_C_5_CFG_UDF_1_C_5 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_C_5_PAGE_A1_UDF_1_C_5_CFG_UDF_1_C_5(x) WriteReg(SWITCH_PAGE_A1_UDF_1_C_5,x)
#define Rd_switch_PAGE_A1_UDF_1_C_5_PAGE_A1_UDF_1_C_5_CFG_UDF_1_C_5(x) ReadReg(SWITCH_PAGE_A1_UDF_1_C_5)
#define SWITCH_PAGE_A1_UDF_1_C_5_PAGE_A1_UDF_1_C_5_CFG_UDF_1_C_5_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_C_5_PAGE_A1_UDF_1_C_5_CFG_UDF_1_C_5_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_C_5_PAGE_A1_UDF_1_C_5_CFG_UDF_1_C_5_BITS 8
#define SWITCH_PAGE_A1_UDF_1_C_5_PAGE_A1_UDF_1_C_5_CFG_UDF_1_C_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_C_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_C_6 :: PAGE_A1_UDF_1_C_6_CFG_UDF_1_C_6 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_C_6_PAGE_A1_UDF_1_C_6_CFG_UDF_1_C_6(x) WriteReg(SWITCH_PAGE_A1_UDF_1_C_6,x)
#define Rd_switch_PAGE_A1_UDF_1_C_6_PAGE_A1_UDF_1_C_6_CFG_UDF_1_C_6(x) ReadReg(SWITCH_PAGE_A1_UDF_1_C_6)
#define SWITCH_PAGE_A1_UDF_1_C_6_PAGE_A1_UDF_1_C_6_CFG_UDF_1_C_6_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_C_6_PAGE_A1_UDF_1_C_6_CFG_UDF_1_C_6_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_C_6_PAGE_A1_UDF_1_C_6_CFG_UDF_1_C_6_BITS 8
#define SWITCH_PAGE_A1_UDF_1_C_6_PAGE_A1_UDF_1_C_6_CFG_UDF_1_C_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_C_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_C_7 :: PAGE_A1_UDF_1_C_7_CFG_UDF_1_C_7 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_C_7_PAGE_A1_UDF_1_C_7_CFG_UDF_1_C_7(x) WriteReg(SWITCH_PAGE_A1_UDF_1_C_7,x)
#define Rd_switch_PAGE_A1_UDF_1_C_7_PAGE_A1_UDF_1_C_7_CFG_UDF_1_C_7(x) ReadReg(SWITCH_PAGE_A1_UDF_1_C_7)
#define SWITCH_PAGE_A1_UDF_1_C_7_PAGE_A1_UDF_1_C_7_CFG_UDF_1_C_7_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_C_7_PAGE_A1_UDF_1_C_7_CFG_UDF_1_C_7_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_C_7_PAGE_A1_UDF_1_C_7_CFG_UDF_1_C_7_BITS 8
#define SWITCH_PAGE_A1_UDF_1_C_7_PAGE_A1_UDF_1_C_7_CFG_UDF_1_C_7_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_1_C_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_1_C_8 :: PAGE_A1_UDF_1_C_8_CFG_UDF_1_C_8 [07:00] */
#define Wr_switch_PAGE_A1_UDF_1_C_8_PAGE_A1_UDF_1_C_8_CFG_UDF_1_C_8(x) WriteReg(SWITCH_PAGE_A1_UDF_1_C_8,x)
#define Rd_switch_PAGE_A1_UDF_1_C_8_PAGE_A1_UDF_1_C_8_CFG_UDF_1_C_8(x) ReadReg(SWITCH_PAGE_A1_UDF_1_C_8)
#define SWITCH_PAGE_A1_UDF_1_C_8_PAGE_A1_UDF_1_C_8_CFG_UDF_1_C_8_MASK 0xff
#define SWITCH_PAGE_A1_UDF_1_C_8_PAGE_A1_UDF_1_C_8_CFG_UDF_1_C_8_ALIGN 0
#define SWITCH_PAGE_A1_UDF_1_C_8_PAGE_A1_UDF_1_C_8_CFG_UDF_1_C_8_BITS 8
#define SWITCH_PAGE_A1_UDF_1_C_8_PAGE_A1_UDF_1_C_8_CFG_UDF_1_C_8_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_C_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_C_0 :: PAGE_A1_UDF_2_C_0_CFG_UDF_2_C_0 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_C_0_PAGE_A1_UDF_2_C_0_CFG_UDF_2_C_0(x) WriteReg(SWITCH_PAGE_A1_UDF_2_C_0,x)
#define Rd_switch_PAGE_A1_UDF_2_C_0_PAGE_A1_UDF_2_C_0_CFG_UDF_2_C_0(x) ReadReg(SWITCH_PAGE_A1_UDF_2_C_0)
#define SWITCH_PAGE_A1_UDF_2_C_0_PAGE_A1_UDF_2_C_0_CFG_UDF_2_C_0_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_C_0_PAGE_A1_UDF_2_C_0_CFG_UDF_2_C_0_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_C_0_PAGE_A1_UDF_2_C_0_CFG_UDF_2_C_0_BITS 8
#define SWITCH_PAGE_A1_UDF_2_C_0_PAGE_A1_UDF_2_C_0_CFG_UDF_2_C_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_C_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_C_1 :: PAGE_A1_UDF_2_C_1_CFG_UDF_2_C_1 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_C_1_PAGE_A1_UDF_2_C_1_CFG_UDF_2_C_1(x) WriteReg(SWITCH_PAGE_A1_UDF_2_C_1,x)
#define Rd_switch_PAGE_A1_UDF_2_C_1_PAGE_A1_UDF_2_C_1_CFG_UDF_2_C_1(x) ReadReg(SWITCH_PAGE_A1_UDF_2_C_1)
#define SWITCH_PAGE_A1_UDF_2_C_1_PAGE_A1_UDF_2_C_1_CFG_UDF_2_C_1_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_C_1_PAGE_A1_UDF_2_C_1_CFG_UDF_2_C_1_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_C_1_PAGE_A1_UDF_2_C_1_CFG_UDF_2_C_1_BITS 8
#define SWITCH_PAGE_A1_UDF_2_C_1_PAGE_A1_UDF_2_C_1_CFG_UDF_2_C_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_C_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_C_2 :: PAGE_A1_UDF_2_C_2_CFG_UDF_2_C_2 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_C_2_PAGE_A1_UDF_2_C_2_CFG_UDF_2_C_2(x) WriteReg(SWITCH_PAGE_A1_UDF_2_C_2,x)
#define Rd_switch_PAGE_A1_UDF_2_C_2_PAGE_A1_UDF_2_C_2_CFG_UDF_2_C_2(x) ReadReg(SWITCH_PAGE_A1_UDF_2_C_2)
#define SWITCH_PAGE_A1_UDF_2_C_2_PAGE_A1_UDF_2_C_2_CFG_UDF_2_C_2_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_C_2_PAGE_A1_UDF_2_C_2_CFG_UDF_2_C_2_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_C_2_PAGE_A1_UDF_2_C_2_CFG_UDF_2_C_2_BITS 8
#define SWITCH_PAGE_A1_UDF_2_C_2_PAGE_A1_UDF_2_C_2_CFG_UDF_2_C_2_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_C_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_C_3 :: PAGE_A1_UDF_2_C_3_CFG_UDF_2_C_3 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_C_3_PAGE_A1_UDF_2_C_3_CFG_UDF_2_C_3(x) WriteReg(SWITCH_PAGE_A1_UDF_2_C_3,x)
#define Rd_switch_PAGE_A1_UDF_2_C_3_PAGE_A1_UDF_2_C_3_CFG_UDF_2_C_3(x) ReadReg(SWITCH_PAGE_A1_UDF_2_C_3)
#define SWITCH_PAGE_A1_UDF_2_C_3_PAGE_A1_UDF_2_C_3_CFG_UDF_2_C_3_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_C_3_PAGE_A1_UDF_2_C_3_CFG_UDF_2_C_3_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_C_3_PAGE_A1_UDF_2_C_3_CFG_UDF_2_C_3_BITS 8
#define SWITCH_PAGE_A1_UDF_2_C_3_PAGE_A1_UDF_2_C_3_CFG_UDF_2_C_3_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_C_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_C_4 :: PAGE_A1_UDF_2_C_4_CFG_UDF_2_C_4 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_C_4_PAGE_A1_UDF_2_C_4_CFG_UDF_2_C_4(x) WriteReg(SWITCH_PAGE_A1_UDF_2_C_4,x)
#define Rd_switch_PAGE_A1_UDF_2_C_4_PAGE_A1_UDF_2_C_4_CFG_UDF_2_C_4(x) ReadReg(SWITCH_PAGE_A1_UDF_2_C_4)
#define SWITCH_PAGE_A1_UDF_2_C_4_PAGE_A1_UDF_2_C_4_CFG_UDF_2_C_4_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_C_4_PAGE_A1_UDF_2_C_4_CFG_UDF_2_C_4_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_C_4_PAGE_A1_UDF_2_C_4_CFG_UDF_2_C_4_BITS 8
#define SWITCH_PAGE_A1_UDF_2_C_4_PAGE_A1_UDF_2_C_4_CFG_UDF_2_C_4_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_C_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_C_5 :: PAGE_A1_UDF_2_C_5_CFG_UDF_2_C_5 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_C_5_PAGE_A1_UDF_2_C_5_CFG_UDF_2_C_5(x) WriteReg(SWITCH_PAGE_A1_UDF_2_C_5,x)
#define Rd_switch_PAGE_A1_UDF_2_C_5_PAGE_A1_UDF_2_C_5_CFG_UDF_2_C_5(x) ReadReg(SWITCH_PAGE_A1_UDF_2_C_5)
#define SWITCH_PAGE_A1_UDF_2_C_5_PAGE_A1_UDF_2_C_5_CFG_UDF_2_C_5_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_C_5_PAGE_A1_UDF_2_C_5_CFG_UDF_2_C_5_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_C_5_PAGE_A1_UDF_2_C_5_CFG_UDF_2_C_5_BITS 8
#define SWITCH_PAGE_A1_UDF_2_C_5_PAGE_A1_UDF_2_C_5_CFG_UDF_2_C_5_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_C_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_C_6 :: PAGE_A1_UDF_2_C_6_CFG_UDF_2_C_6 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_C_6_PAGE_A1_UDF_2_C_6_CFG_UDF_2_C_6(x) WriteReg(SWITCH_PAGE_A1_UDF_2_C_6,x)
#define Rd_switch_PAGE_A1_UDF_2_C_6_PAGE_A1_UDF_2_C_6_CFG_UDF_2_C_6(x) ReadReg(SWITCH_PAGE_A1_UDF_2_C_6)
#define SWITCH_PAGE_A1_UDF_2_C_6_PAGE_A1_UDF_2_C_6_CFG_UDF_2_C_6_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_C_6_PAGE_A1_UDF_2_C_6_CFG_UDF_2_C_6_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_C_6_PAGE_A1_UDF_2_C_6_CFG_UDF_2_C_6_BITS 8
#define SWITCH_PAGE_A1_UDF_2_C_6_PAGE_A1_UDF_2_C_6_CFG_UDF_2_C_6_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_C_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_C_7 :: PAGE_A1_UDF_2_C_7_CFG_UDF_2_C_7 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_C_7_PAGE_A1_UDF_2_C_7_CFG_UDF_2_C_7(x) WriteReg(SWITCH_PAGE_A1_UDF_2_C_7,x)
#define Rd_switch_PAGE_A1_UDF_2_C_7_PAGE_A1_UDF_2_C_7_CFG_UDF_2_C_7(x) ReadReg(SWITCH_PAGE_A1_UDF_2_C_7)
#define SWITCH_PAGE_A1_UDF_2_C_7_PAGE_A1_UDF_2_C_7_CFG_UDF_2_C_7_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_C_7_PAGE_A1_UDF_2_C_7_CFG_UDF_2_C_7_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_C_7_PAGE_A1_UDF_2_C_7_CFG_UDF_2_C_7_BITS 8
#define SWITCH_PAGE_A1_UDF_2_C_7_PAGE_A1_UDF_2_C_7_CFG_UDF_2_C_7_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_2_C_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_2_C_8 :: PAGE_A1_UDF_2_C_8_CFG_UDF_2_C_8 [07:00] */
#define Wr_switch_PAGE_A1_UDF_2_C_8_PAGE_A1_UDF_2_C_8_CFG_UDF_2_C_8(x) WriteReg(SWITCH_PAGE_A1_UDF_2_C_8,x)
#define Rd_switch_PAGE_A1_UDF_2_C_8_PAGE_A1_UDF_2_C_8_CFG_UDF_2_C_8(x) ReadReg(SWITCH_PAGE_A1_UDF_2_C_8)
#define SWITCH_PAGE_A1_UDF_2_C_8_PAGE_A1_UDF_2_C_8_CFG_UDF_2_C_8_MASK 0xff
#define SWITCH_PAGE_A1_UDF_2_C_8_PAGE_A1_UDF_2_C_8_CFG_UDF_2_C_8_ALIGN 0
#define SWITCH_PAGE_A1_UDF_2_C_8_PAGE_A1_UDF_2_C_8_CFG_UDF_2_C_8_BITS 8
#define SWITCH_PAGE_A1_UDF_2_C_8_PAGE_A1_UDF_2_C_8_CFG_UDF_2_C_8_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_0
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_0 :: PAGE_A1_UDF_0_D_0_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_0_PAGE_A1_UDF_0_D_0_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_0,x)
#define Rd_switch_PAGE_A1_UDF_0_D_0_PAGE_A1_UDF_0_D_0_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_0)
#define SWITCH_PAGE_A1_UDF_0_D_0_PAGE_A1_UDF_0_D_0_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_0_PAGE_A1_UDF_0_D_0_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_0_PAGE_A1_UDF_0_D_0_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_0_PAGE_A1_UDF_0_D_0_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_1
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_1 :: PAGE_A1_UDF_0_D_1_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_1_PAGE_A1_UDF_0_D_1_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_1,x)
#define Rd_switch_PAGE_A1_UDF_0_D_1_PAGE_A1_UDF_0_D_1_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_1)
#define SWITCH_PAGE_A1_UDF_0_D_1_PAGE_A1_UDF_0_D_1_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_1_PAGE_A1_UDF_0_D_1_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_1_PAGE_A1_UDF_0_D_1_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_1_PAGE_A1_UDF_0_D_1_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_2
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_2 :: PAGE_A1_UDF_0_D_2_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_2_PAGE_A1_UDF_0_D_2_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_2,x)
#define Rd_switch_PAGE_A1_UDF_0_D_2_PAGE_A1_UDF_0_D_2_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_2)
#define SWITCH_PAGE_A1_UDF_0_D_2_PAGE_A1_UDF_0_D_2_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_2_PAGE_A1_UDF_0_D_2_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_2_PAGE_A1_UDF_0_D_2_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_2_PAGE_A1_UDF_0_D_2_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_3
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_3 :: PAGE_A1_UDF_0_D_3_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_3_PAGE_A1_UDF_0_D_3_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_3,x)
#define Rd_switch_PAGE_A1_UDF_0_D_3_PAGE_A1_UDF_0_D_3_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_3)
#define SWITCH_PAGE_A1_UDF_0_D_3_PAGE_A1_UDF_0_D_3_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_3_PAGE_A1_UDF_0_D_3_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_3_PAGE_A1_UDF_0_D_3_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_3_PAGE_A1_UDF_0_D_3_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_4
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_4 :: PAGE_A1_UDF_0_D_4_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_4_PAGE_A1_UDF_0_D_4_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_4,x)
#define Rd_switch_PAGE_A1_UDF_0_D_4_PAGE_A1_UDF_0_D_4_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_4)
#define SWITCH_PAGE_A1_UDF_0_D_4_PAGE_A1_UDF_0_D_4_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_4_PAGE_A1_UDF_0_D_4_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_4_PAGE_A1_UDF_0_D_4_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_4_PAGE_A1_UDF_0_D_4_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_5
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_5 :: PAGE_A1_UDF_0_D_5_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_5_PAGE_A1_UDF_0_D_5_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_5,x)
#define Rd_switch_PAGE_A1_UDF_0_D_5_PAGE_A1_UDF_0_D_5_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_5)
#define SWITCH_PAGE_A1_UDF_0_D_5_PAGE_A1_UDF_0_D_5_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_5_PAGE_A1_UDF_0_D_5_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_5_PAGE_A1_UDF_0_D_5_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_5_PAGE_A1_UDF_0_D_5_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_6
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_6 :: PAGE_A1_UDF_0_D_6_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_6_PAGE_A1_UDF_0_D_6_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_6,x)
#define Rd_switch_PAGE_A1_UDF_0_D_6_PAGE_A1_UDF_0_D_6_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_6)
#define SWITCH_PAGE_A1_UDF_0_D_6_PAGE_A1_UDF_0_D_6_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_6_PAGE_A1_UDF_0_D_6_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_6_PAGE_A1_UDF_0_D_6_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_6_PAGE_A1_UDF_0_D_6_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_7
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_7 :: PAGE_A1_UDF_0_D_7_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_7_PAGE_A1_UDF_0_D_7_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_7,x)
#define Rd_switch_PAGE_A1_UDF_0_D_7_PAGE_A1_UDF_0_D_7_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_7)
#define SWITCH_PAGE_A1_UDF_0_D_7_PAGE_A1_UDF_0_D_7_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_7_PAGE_A1_UDF_0_D_7_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_7_PAGE_A1_UDF_0_D_7_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_7_PAGE_A1_UDF_0_D_7_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_8
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_8 :: PAGE_A1_UDF_0_D_8_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_8_PAGE_A1_UDF_0_D_8_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_8,x)
#define Rd_switch_PAGE_A1_UDF_0_D_8_PAGE_A1_UDF_0_D_8_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_8)
#define SWITCH_PAGE_A1_UDF_0_D_8_PAGE_A1_UDF_0_D_8_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_8_PAGE_A1_UDF_0_D_8_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_8_PAGE_A1_UDF_0_D_8_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_8_PAGE_A1_UDF_0_D_8_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_9
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_9 :: PAGE_A1_UDF_0_D_9_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_9_PAGE_A1_UDF_0_D_9_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_9,x)
#define Rd_switch_PAGE_A1_UDF_0_D_9_PAGE_A1_UDF_0_D_9_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_9)
#define SWITCH_PAGE_A1_UDF_0_D_9_PAGE_A1_UDF_0_D_9_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_9_PAGE_A1_UDF_0_D_9_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_9_PAGE_A1_UDF_0_D_9_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_9_PAGE_A1_UDF_0_D_9_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_A
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_A :: PAGE_A1_UDF_0_D_A_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_A_PAGE_A1_UDF_0_D_A_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_A,x)
#define Rd_switch_PAGE_A1_UDF_0_D_A_PAGE_A1_UDF_0_D_A_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_A)
#define SWITCH_PAGE_A1_UDF_0_D_A_PAGE_A1_UDF_0_D_A_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_A_PAGE_A1_UDF_0_D_A_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_A_PAGE_A1_UDF_0_D_A_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_A_PAGE_A1_UDF_0_D_A_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_A1_UDF_0_D_B
 ***************************************************************************/
/* switch :: PAGE_A1_UDF_0_D_B :: PAGE_A1_UDF_0_D_B_CFG_UDF_0_D_0_11 [07:00] */
#define Wr_switch_PAGE_A1_UDF_0_D_B_PAGE_A1_UDF_0_D_B_CFG_UDF_0_D_0_11(x) WriteReg(SWITCH_PAGE_A1_UDF_0_D_B,x)
#define Rd_switch_PAGE_A1_UDF_0_D_B_PAGE_A1_UDF_0_D_B_CFG_UDF_0_D_0_11(x) ReadReg(SWITCH_PAGE_A1_UDF_0_D_B)
#define SWITCH_PAGE_A1_UDF_0_D_B_PAGE_A1_UDF_0_D_B_CFG_UDF_0_D_0_11_MASK 0xff
#define SWITCH_PAGE_A1_UDF_0_D_B_PAGE_A1_UDF_0_D_B_CFG_UDF_0_D_0_11_ALIGN 0
#define SWITCH_PAGE_A1_UDF_0_D_B_PAGE_A1_UDF_0_D_B_CFG_UDF_0_D_0_11_BITS 8
#define SWITCH_PAGE_A1_UDF_0_D_B_PAGE_A1_UDF_0_D_B_CFG_UDF_0_D_0_11_SHIFT 0


/****************************************************************************
 * switch :: PAGE_B0_ARL_TCAM_ACC
 ***************************************************************************/
/* switch :: PAGE_B0_ARL_TCAM_ACC :: PAGE_B0_ARL_TCAM_ACC_TCAM_RD_STS [31:31] */
#define Wr_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RD_STS(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x80000000,31,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RD_STS(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x80000000,31)
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RD_STS_MASK 0x80000000
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RD_STS_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RD_STS_BITS 1
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RD_STS_SHIFT 31

/* switch :: PAGE_B0_ARL_TCAM_ACC :: PAGE_B0_ARL_TCAM_ACC_SMEM_RD_STS [30:30] */
#define Wr_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_SMEM_RD_STS(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x40000000,30,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_SMEM_RD_STS(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x40000000,30)
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_SMEM_RD_STS_MASK 0x40000000
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_SMEM_RD_STS_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_SMEM_RD_STS_BITS 1
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_SMEM_RD_STS_SHIFT 30

/* switch :: PAGE_B0_ARL_TCAM_ACC :: PAGE_B0_ARL_TCAM_ACC_RESERVED [29:24] */
#define Wr_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x3f000000,24,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x3f000000,24)
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_MASK 0x3f000000
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_BITS 6
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_SHIFT 24

/* switch :: PAGE_B0_ARL_TCAM_ACC :: PAGE_B0_ARL_TCAM_ACC_XCESS_ADDR [23:16] */
#define Wr_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_XCESS_ADDR(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0xff0000,16,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_XCESS_ADDR(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0xff0000,16)
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_XCESS_ADDR_MASK 0x00ff0000
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_XCESS_ADDR_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_XCESS_ADDR_BITS 8
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_XCESS_ADDR_SHIFT 16

/* switch :: PAGE_B0_ARL_TCAM_ACC :: PAGE_B0_ARL_TCAM_ACC_RESERVED_1 [15:04] */
#define Wr_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0xfff0,4,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0xfff0,4)
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_1_MASK 0x0000fff0
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_1_BITS 12
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_RESERVED_1_SHIFT 4

/* switch :: PAGE_B0_ARL_TCAM_ACC :: PAGE_B0_ARL_TCAM_ACC_TCAM_RST [03:03] */
#define Wr_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RST(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x8,3,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RST(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x8,3)
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RST_MASK 0x00000008
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RST_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RST_BITS 1
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_TCAM_RST_SHIFT 3

/* switch :: PAGE_B0_ARL_TCAM_ACC :: PAGE_B0_ARL_TCAM_ACC_OP_SEL [02:01] */
#define Wr_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_SEL(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x6,1,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_SEL(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x6,1)
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_SEL_MASK 0x00000006
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_SEL_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_SEL_BITS 2
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_SEL_SHIFT 1

/* switch :: PAGE_B0_ARL_TCAM_ACC :: PAGE_B0_ARL_TCAM_ACC_OP_STR_DONE [00:00] */
#define Wr_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_STR_DONE(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x1,0,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_STR_DONE(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_ACC,0x1,0)
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_STR_DONE_MASK 0x00000001
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_STR_DONE_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_STR_DONE_BITS 1
#define SWITCH_PAGE_B0_ARL_TCAM_ACC_PAGE_B0_ARL_TCAM_ACC_OP_STR_DONE_SHIFT 0


/****************************************************************************
 * switch :: PAGE_B0_ARL_TCAM_DATA_0
 ***************************************************************************/
/* switch :: PAGE_B0_ARL_TCAM_DATA_0 :: PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_0 [31:00] */
#define Wr_switch_PAGE_B0_ARL_TCAM_DATA_0_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_0(x) WriteReg(SWITCH_PAGE_B0_ARL_TCAM_DATA_0,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_DATA_0_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_0(x) ReadReg(SWITCH_PAGE_B0_ARL_TCAM_DATA_0)
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_0_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_0_MASK 0xffffffff
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_0_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_0_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_0_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_0_BITS 32
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_0_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_0_SHIFT 0


/****************************************************************************
 * switch :: PAGE_B0_ARL_TCAM_DATA_1
 ***************************************************************************/
/* switch :: PAGE_B0_ARL_TCAM_DATA_1 :: PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_1 [31:00] */
#define Wr_switch_PAGE_B0_ARL_TCAM_DATA_1_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_1(x) WriteReg(SWITCH_PAGE_B0_ARL_TCAM_DATA_1,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_DATA_1_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_1(x) ReadReg(SWITCH_PAGE_B0_ARL_TCAM_DATA_1)
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_1_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_1_MASK 0xffffffff
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_1_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_1_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_1_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_1_BITS 32
#define SWITCH_PAGE_B0_ARL_TCAM_DATA_1_PAGE_B0_ARL_TCAM_DATA_TCAM_DATA_1_SHIFT 0


/****************************************************************************
 * switch :: PAGE_B0_ARL_SMEM_DATA
 ***************************************************************************/
/* switch :: PAGE_B0_ARL_SMEM_DATA :: PAGE_B0_ARL_SMEM_DATA_RESERVED [31:12] */
#define Wr_switch_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_RESERVED(x) WriteRegBits(SWITCH_PAGE_B0_ARL_SMEM_DATA,0xfffff000,12,x)
#define Rd_switch_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_RESERVED(x) ReadRegBits(SWITCH_PAGE_B0_ARL_SMEM_DATA,0xfffff000,12)
#define SWITCH_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_RESERVED_MASK 0xfffff000
#define SWITCH_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_RESERVED_ALIGN 0
#define SWITCH_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_RESERVED_BITS 20
#define SWITCH_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_RESERVED_SHIFT 12

/* switch :: PAGE_B0_ARL_SMEM_DATA :: PAGE_B0_ARL_SMEM_DATA_SMEM_DATA [11:00] */
#define Wr_switch_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_SMEM_DATA(x) WriteRegBits(SWITCH_PAGE_B0_ARL_SMEM_DATA,0xfff,0,x)
#define Rd_switch_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_SMEM_DATA(x) ReadRegBits(SWITCH_PAGE_B0_ARL_SMEM_DATA,0xfff,0)
#define SWITCH_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_SMEM_DATA_MASK 0x00000fff
#define SWITCH_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_SMEM_DATA_ALIGN 0
#define SWITCH_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_SMEM_DATA_BITS 12
#define SWITCH_PAGE_B0_ARL_SMEM_DATA_PAGE_B0_ARL_SMEM_DATA_SMEM_DATA_SHIFT 0


/****************************************************************************
 * switch :: PAGE_B0_ARL_TCAM_BIST_CTRL
 ***************************************************************************/
/* switch :: PAGE_B0_ARL_TCAM_BIST_CTRL :: PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_DONE [31:31] */
#define Wr_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_DONE(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0x80000000,31,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_DONE(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0x80000000,31)
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_DONE_MASK 0x80000000
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_DONE_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_DONE_BITS 1
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_DONE_SHIFT 31

/* switch :: PAGE_B0_ARL_TCAM_BIST_CTRL :: PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_1 [30:16] */
#define Wr_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_1(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0x7fff0000,16,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_1(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0x7fff0000,16)
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_1_MASK 0x7fff0000
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_1_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_1_BITS 15
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_1_SHIFT 16

/* switch :: PAGE_B0_ARL_TCAM_BIST_CTRL :: PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_SKIP_ERR_CNT [15:08] */
#define Wr_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_SKIP_ERR_CNT(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0xff00,8,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_SKIP_ERR_CNT(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0xff00,8)
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_SKIP_ERR_CNT_MASK 0x0000ff00
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_SKIP_ERR_CNT_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_SKIP_ERR_CNT_BITS 8
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_SKIP_ERR_CNT_SHIFT 8

/* switch :: PAGE_B0_ARL_TCAM_BIST_CTRL :: PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_STATUS_SEL [07:04] */
#define Wr_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_STATUS_SEL(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0xf0,4,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_STATUS_SEL(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0xf0,4)
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_STATUS_SEL_MASK 0x000000f0
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_STATUS_SEL_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_STATUS_SEL_BITS 4
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_STATUS_SEL_SHIFT 4

/* switch :: PAGE_B0_ARL_TCAM_BIST_CTRL :: PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_0 [03:01] */
#define Wr_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_0(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0xe,1,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_0(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0xe,1)
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_0_MASK 0x0000000e
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_0_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_0_BITS 3
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_RESERVED_0_SHIFT 1

/* switch :: PAGE_B0_ARL_TCAM_BIST_CTRL :: PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_EN [00:00] */
#define Wr_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_EN(x) WriteRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0x1,0,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_EN(x) ReadRegBits(SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL,0x1,0)
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_EN_MASK 0x00000001
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_EN_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_EN_BITS 1
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_CTRL_PAGE_B0_ARL_TCAM_BIST_CTRL_TCAM_BIST_EN_SHIFT 0


/****************************************************************************
 * switch :: PAGE_B0_ARL_TCAM_BIST_STS
 ***************************************************************************/
/* switch :: PAGE_B0_ARL_TCAM_BIST_STS :: PAGE_B0_ARL_TCAM_BIST_STS_TCAM_BIST_STATUS [31:00] */
#define Wr_switch_PAGE_B0_ARL_TCAM_BIST_STS_PAGE_B0_ARL_TCAM_BIST_STS_TCAM_BIST_STATUS(x) WriteReg(SWITCH_PAGE_B0_ARL_TCAM_BIST_STS,x)
#define Rd_switch_PAGE_B0_ARL_TCAM_BIST_STS_PAGE_B0_ARL_TCAM_BIST_STS_TCAM_BIST_STATUS(x) ReadReg(SWITCH_PAGE_B0_ARL_TCAM_BIST_STS)
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_STS_PAGE_B0_ARL_TCAM_BIST_STS_TCAM_BIST_STATUS_MASK 0xffffffff
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_STS_PAGE_B0_ARL_TCAM_BIST_STS_TCAM_BIST_STATUS_ALIGN 0
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_STS_PAGE_B0_ARL_TCAM_BIST_STS_TCAM_BIST_STATUS_BITS 32
#define SWITCH_PAGE_B0_ARL_TCAM_BIST_STS_PAGE_B0_ARL_TCAM_BIST_STS_TCAM_BIST_STATUS_SHIFT 0


/****************************************************************************
 * Datatype Definitions.
 ***************************************************************************/
#endif /* #ifndef BCM89530_H__ */

/* End of File */

